diff options
| author | Ian Rogers <irogers@google.com> | 2024-06-20 20:17:51 +0200 |
|---|---|---|
| committer | Namhyung Kim <namhyung@kernel.org> | 2024-06-21 01:56:57 +0200 |
| commit | 788c5160526a6385fc70bc1ad32cf686e4ec3a61 (patch) | |
| tree | 8d0825ef0549391220a9be740cf77b2ee90b8596 /tools/perf/pmu-events | |
| parent | perf vendor events: Add westmereep-sp counter information (diff) | |
| download | linux-788c5160526a6385fc70bc1ad32cf686e4ec3a61.tar.xz linux-788c5160526a6385fc70bc1ad32cf686e4ec3a61.zip | |
perf vendor events: Add westmereex counter information
Add counter information necessary for optimizing event grouping the
perf tool.
The most recent RFC patch set using this information:
https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/
The information was added in:
https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4765e1
and later patches.
Co-authored-by: Weilin Wang <weilin.wang@intel.com>
Co-authored-by: Caleb Biggers <caleb.biggers@intel.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Link: https://lore.kernel.org/r/20240620181752.3945845-38-irogers@google.com
Diffstat (limited to 'tools/perf/pmu-events')
8 files changed, 586 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/x86/westmereex/cache.json b/tools/perf/pmu-events/arch/x86/westmereex/cache.json index 18d61d43e4c9..9f922370ee8b 100644 --- a/tools/perf/pmu-events/arch/x86/westmereex/cache.json +++ b/tools/perf/pmu-events/arch/x86/westmereex/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles L1D locked", + "Counter": "0,1", "EventCode": "0x63", "EventName": "CACHE_LOCK_CYCLES.L1D", "SampleAfterValue": "2000000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Cycles L1D and L2 locked", + "Counter": "0,1", "EventCode": "0x63", "EventName": "CACHE_LOCK_CYCLES.L1D_L2", "SampleAfterValue": "2000000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "L1D cache lines replaced in M state", + "Counter": "0,1", "EventCode": "0x51", "EventName": "L1D.M_EVICT", "SampleAfterValue": "2000000", @@ -22,6 +25,7 @@ }, { "BriefDescription": "L1D cache lines allocated in the M state", + "Counter": "0,1", "EventCode": "0x51", "EventName": "L1D.M_REPL", "SampleAfterValue": "2000000", @@ -29,6 +33,7 @@ }, { "BriefDescription": "L1D snoop eviction of cache lines in M state", + "Counter": "0,1", "EventCode": "0x51", "EventName": "L1D.M_SNOOP_EVICT", "SampleAfterValue": "2000000", @@ -36,6 +41,7 @@ }, { "BriefDescription": "L1 data cache lines allocated", + "Counter": "0,1", "EventCode": "0x51", "EventName": "L1D.REPL", "SampleAfterValue": "2000000", @@ -43,6 +49,7 @@ }, { "BriefDescription": "L1D prefetch load lock accepted in fill buffer", + "Counter": "0,1", "EventCode": "0x52", "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", "SampleAfterValue": "2000000", @@ -50,6 +57,7 @@ }, { "BriefDescription": "L1D hardware prefetch misses", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "L1D_PREFETCH.MISS", "SampleAfterValue": "200000", @@ -57,6 +65,7 @@ }, { "BriefDescription": "L1D hardware prefetch requests", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "L1D_PREFETCH.REQUESTS", "SampleAfterValue": "200000", @@ -64,6 +73,7 @@ }, { "BriefDescription": "L1D hardware prefetch requests triggered", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "L1D_PREFETCH.TRIGGERS", "SampleAfterValue": "200000", @@ -71,6 +81,7 @@ }, { "BriefDescription": "L1 writebacks to L2 in E state", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.E_STATE", "SampleAfterValue": "100000", @@ -78,6 +89,7 @@ }, { "BriefDescription": "L1 writebacks to L2 in I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.I_STATE", "SampleAfterValue": "100000", @@ -85,6 +97,7 @@ }, { "BriefDescription": "All L1 writebacks to L2", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.MESI", "SampleAfterValue": "100000", @@ -92,6 +105,7 @@ }, { "BriefDescription": "L1 writebacks to L2 in M state", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.M_STATE", "SampleAfterValue": "100000", @@ -99,6 +113,7 @@ }, { "BriefDescription": "L1 writebacks to L2 in S state", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.S_STATE", "SampleAfterValue": "100000", @@ -106,6 +121,7 @@ }, { "BriefDescription": "All L2 data requests", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.ANY", "SampleAfterValue": "200000", @@ -113,6 +129,7 @@ }, { "BriefDescription": "L2 data demand loads in E state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", "SampleAfterValue": "200000", @@ -120,6 +137,7 @@ }, { "BriefDescription": "L2 data demand loads in I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", "SampleAfterValue": "200000", @@ -127,6 +145,7 @@ }, { "BriefDescription": "L2 data demand requests", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.MESI", "SampleAfterValue": "200000", @@ -134,6 +153,7 @@ }, { "BriefDescription": "L2 data demand loads in M state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", "SampleAfterValue": "200000", @@ -141,6 +161,7 @@ }, { "BriefDescription": "L2 data demand loads in S state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", "SampleAfterValue": "200000", @@ -148,6 +169,7 @@ }, { "BriefDescription": "L2 data prefetches in E state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", "SampleAfterValue": "200000", @@ -155,6 +177,7 @@ }, { "BriefDescription": "L2 data prefetches in the I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", "SampleAfterValue": "200000", @@ -162,6 +185,7 @@ }, { "BriefDescription": "All L2 data prefetches", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", "SampleAfterValue": "200000", @@ -169,6 +193,7 @@ }, { "BriefDescription": "L2 data prefetches in M state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", "SampleAfterValue": "200000", @@ -176,6 +201,7 @@ }, { "BriefDescription": "L2 data prefetches in the S state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", "SampleAfterValue": "200000", @@ -183,6 +209,7 @@ }, { "BriefDescription": "L2 lines allocated", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.ANY", "SampleAfterValue": "100000", @@ -190,6 +217,7 @@ }, { "BriefDescription": "L2 lines allocated in the E state", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.E_STATE", "SampleAfterValue": "100000", @@ -197,6 +225,7 @@ }, { "BriefDescription": "L2 lines allocated in the S state", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.S_STATE", "SampleAfterValue": "100000", @@ -204,6 +233,7 @@ }, { "BriefDescription": "L2 lines evicted", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.ANY", "SampleAfterValue": "100000", @@ -211,6 +241,7 @@ }, { "BriefDescription": "L2 lines evicted by a demand request", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_CLEAN", "SampleAfterValue": "100000", @@ -218,6 +249,7 @@ }, { "BriefDescription": "L2 modified lines evicted by a demand request", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_DIRTY", "SampleAfterValue": "100000", @@ -225,6 +257,7 @@ }, { "BriefDescription": "L2 lines evicted by a prefetch request", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", "SampleAfterValue": "100000", @@ -232,6 +265,7 @@ }, { "BriefDescription": "L2 modified lines evicted by a prefetch request", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", "SampleAfterValue": "100000", @@ -239,6 +273,7 @@ }, { "BriefDescription": "L2 instruction fetches", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.IFETCHES", "SampleAfterValue": "200000", @@ -246,6 +281,7 @@ }, { "BriefDescription": "L2 instruction fetch hits", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.IFETCH_HIT", "SampleAfterValue": "200000", @@ -253,6 +289,7 @@ }, { "BriefDescription": "L2 instruction fetch misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.IFETCH_MISS", "SampleAfterValue": "200000", @@ -260,6 +297,7 @@ }, { "BriefDescription": "L2 load hits", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.LD_HIT", "SampleAfterValue": "200000", @@ -267,6 +305,7 @@ }, { "BriefDescription": "L2 load misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.LD_MISS", "SampleAfterValue": "200000", @@ -274,6 +313,7 @@ }, { "BriefDescription": "L2 requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.LOADS", "SampleAfterValue": "200000", @@ -281,6 +321,7 @@ }, { "BriefDescription": "All L2 misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", "SampleAfterValue": "200000", @@ -288,6 +329,7 @@ }, { "BriefDescription": "All L2 prefetches", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PREFETCHES", "SampleAfterValue": "200000", @@ -295,6 +337,7 @@ }, { "BriefDescription": "L2 prefetch hits", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PREFETCH_HIT", "SampleAfterValue": "200000", @@ -302,6 +345,7 @@ }, { "BriefDescription": "L2 prefetch misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PREFETCH_MISS", "SampleAfterValue": "200000", @@ -309,6 +353,7 @@ }, { "BriefDescription": "All L2 requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.REFERENCES", "SampleAfterValue": "200000", @@ -316,6 +361,7 @@ }, { "BriefDescription": "L2 RFO requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFOS", "SampleAfterValue": "200000", @@ -323,6 +369,7 @@ }, { "BriefDescription": "L2 RFO hits", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "SampleAfterValue": "200000", @@ -330,6 +377,7 @@ }, { "BriefDescription": "L2 RFO misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "SampleAfterValue": "200000", @@ -337,6 +385,7 @@ }, { "BriefDescription": "All L2 transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.ANY", "SampleAfterValue": "200000", @@ -344,6 +393,7 @@ }, { "BriefDescription": "L2 fill transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.FILL", "SampleAfterValue": "200000", @@ -351,6 +401,7 @@ }, { "BriefDescription": "L2 instruction fetch transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.IFETCH", "SampleAfterValue": "200000", @@ -358,6 +409,7 @@ }, { "BriefDescription": "L1D writeback to L2 transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.L1D_WB", "SampleAfterValue": "200000", @@ -365,6 +417,7 @@ }, { "BriefDescription": "L2 Load transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.LOAD", "SampleAfterValue": "200000", @@ -372,6 +425,7 @@ }, { "BriefDescription": "L2 prefetch transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.PREFETCH", "SampleAfterValue": "200000", @@ -379,6 +433,7 @@ }, { "BriefDescription": "L2 RFO transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.RFO", "SampleAfterValue": "200000", @@ -386,6 +441,7 @@ }, { "BriefDescription": "L2 writeback to LLC transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.WB", "SampleAfterValue": "200000", @@ -393,6 +449,7 @@ }, { "BriefDescription": "L2 demand lock RFOs in E state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.E_STATE", "SampleAfterValue": "100000", @@ -400,6 +457,7 @@ }, { "BriefDescription": "All demand L2 lock RFOs that hit the cache", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.HIT", "SampleAfterValue": "100000", @@ -407,6 +465,7 @@ }, { "BriefDescription": "L2 demand lock RFOs in I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.I_STATE", "SampleAfterValue": "100000", @@ -414,6 +473,7 @@ }, { "BriefDescription": "All demand L2 lock RFOs", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.MESI", "SampleAfterValue": "100000", @@ -421,6 +481,7 @@ }, { "BriefDescription": "L2 demand lock RFOs in M state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.M_STATE", "SampleAfterValue": "100000", @@ -428,6 +489,7 @@ }, { "BriefDescription": "L2 demand lock RFOs in S state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.S_STATE", "SampleAfterValue": "100000", @@ -435,6 +497,7 @@ }, { "BriefDescription": "All L2 demand store RFOs that hit the cache", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.HIT", "SampleAfterValue": "100000", @@ -442,6 +505,7 @@ }, { "BriefDescription": "L2 demand store RFOs in I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.I_STATE", "SampleAfterValue": "100000", @@ -449,6 +513,7 @@ }, { "BriefDescription": "All L2 demand store RFOs", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.MESI", "SampleAfterValue": "100000", @@ -456,6 +521,7 @@ }, { "BriefDescription": "L2 demand store RFOs in M state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.M_STATE", "SampleAfterValue": "100000", @@ -463,6 +529,7 @@ }, { "BriefDescription": "L2 demand store RFOs in S state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.S_STATE", "SampleAfterValue": "100000", @@ -470,6 +537,7 @@ }, { "BriefDescription": "Longest latency cache miss", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", "SampleAfterValue": "100000", @@ -477,6 +545,7 @@ }, { "BriefDescription": "Longest latency cache reference", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "SampleAfterValue": "200000", @@ -484,6 +553,7 @@ }, { "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", "MSRIndex": "0x3F6", @@ -493,6 +563,7 @@ }, { "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", "MSRIndex": "0x3F6", @@ -503,6 +574,7 @@ }, { "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", "MSRIndex": "0x3F6", @@ -513,6 +585,7 @@ }, { "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", "MSRIndex": "0x3F6", @@ -523,6 +596,7 @@ }, { "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", "MSRIndex": "0x3F6", @@ -533,6 +607,7 @@ }, { "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", "MSRIndex": "0x3F6", @@ -543,6 +618,7 @@ }, { "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", "MSRIndex": "0x3F6", @@ -553,6 +629,7 @@ }, { "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", "MSRIndex": "0x3F6", @@ -563,6 +640,7 @@ }, { "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", "MSRIndex": "0x3F6", @@ -573,6 +651,7 @@ }, { "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", "MSRIndex": "0x3F6", @@ -583,6 +662,7 @@ }, { "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", "MSRIndex": "0x3F6", @@ -593,6 +673,7 @@ }, { "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", "MSRIndex": "0x3F6", @@ -603,6 +684,7 @@ }, { "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", "MSRIndex": "0x3F6", @@ -613,6 +695,7 @@ }, { "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", "MSRIndex": "0x3F6", @@ -623,6 +706,7 @@ }, { "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", "MSRIndex": "0x3F6", @@ -633,6 +717,7 @@ }, { "BriefDescription": "Instructions retired which contains a load (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LOADS", "PEBS": "1", @@ -641,6 +726,7 @@ }, { "BriefDescription": "Instructions retired which contains a store (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.STORES", "PEBS": "1", @@ -649,6 +735,7 @@ }, { "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.HIT_LFB", "PEBS": "1", @@ -657,6 +744,7 @@ }, { "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.L1D_HIT", "PEBS": "1", @@ -665,6 +753,7 @@ }, { "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.L2_HIT", "PEBS": "1", @@ -673,6 +762,7 @@ }, { "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.LLC_MISS", "PEBS": "1", @@ -681,6 +771,7 @@ }, { "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", "PEBS": "1", @@ -689,6 +780,7 @@ }, { "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", "PEBS": "1", @@ -697,6 +789,7 @@ }, { "BriefDescription": "Load instructions retired local dram and remote cache HIT data sources (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "PEBS": "1", @@ -705,6 +798,7 @@ }, { "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "MEM_UNCORE_RETIRED.LOCAL_HITM", "PEBS": "1", @@ -713,6 +807,7 @@ }, { "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM", "PEBS": "1", @@ -721,6 +816,7 @@ }, { "BriefDescription": "Retired loads that hit remote socket in modified state (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "MEM_UNCORE_RETIRED.REMOTE_HITM", "PEBS": "1", @@ -729,6 +825,7 @@ }, { "BriefDescription": "Load instructions retired IO (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE", "PEBS": "1", @@ -737,6 +834,7 @@ }, { "BriefDescription": "All offcore requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ANY", "SampleAfterValue": "100000", @@ -744,6 +842,7 @@ }, { "BriefDescription": "Offcore read requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ANY.READ", "SampleAfterValue": "100000", @@ -751,6 +850,7 @@ }, { "BriefDescription": "Offcore RFO requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ANY.RFO", "SampleAfterValue": "100000", @@ -758,6 +858,7 @@ }, { "BriefDescription": "Offcore demand code read requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE", "SampleAfterValue": "100000", @@ -765,6 +866,7 @@ }, { "BriefDescription": "Offcore demand data read requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA", "SampleAfterValue": "100000", @@ -772,6 +874,7 @@ }, { "BriefDescription": "Offcore demand RFO requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND.RFO", "SampleAfterValue": "100000", @@ -779,6 +882,7 @@ }, { "BriefDescription": "Offcore L1 data cache writebacks", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", "SampleAfterValue": "100000", @@ -786,6 +890,7 @@ }, { "BriefDescription": "Outstanding offcore reads", + "Counter": "0", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", "SampleAfterValue": "2000000", @@ -793,6 +898,7 @@ }, { "BriefDescription": "Cycles offcore reads busy", + "Counter": "0", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY", @@ -801,6 +907,7 @@ }, { "BriefDescription": "Outstanding offcore demand code reads", + "Counter": "0", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", "SampleAfterValue": "2000000", @@ -808,6 +915,7 @@ }, { "BriefDescription": "Cycles offcore demand code read busy", + "Counter": "0", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY", @@ -816,6 +924,7 @@ }, { "BriefDescription": "Outstanding offcore demand data reads", + "Counter": "0", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", "SampleAfterValue": "2000000", @@ -823,6 +932,7 @@ }, { "BriefDescription": "Cycles offcore demand data read busy", + "Counter": "0", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY", @@ -831,6 +941,7 @@ }, { "BriefDescription": "Outstanding offcore demand RFOs", + "Counter": "0", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", "SampleAfterValue": "2000000", @@ -838,6 +949,7 @@ }, { "BriefDescription": "Cycles offcore demand RFOs busy", + "Counter": "0", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY", @@ -846,6 +958,7 @@ }, { "BriefDescription": "Offcore requests blocked due to Super Queue full", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "OFFCORE_REQUESTS_SQ_FULL", "SampleAfterValue": "100000", @@ -853,6 +966,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by any cache or DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -862,6 +976,7 @@ }, { "BriefDescription": "All offcore data reads", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -871,6 +986,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -880,6 +996,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -889,6 +1006,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -898,6 +1016,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -907,6 +1026,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -916,6 +1036,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -925,6 +1046,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -934,6 +1056,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -943,6 +1066,7 @@ }, { "BriefDescription": "Offcore data reads that HIT in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -952,6 +1076,7 @@ }, { "BriefDescription": "Offcore data reads that HITM in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -961,6 +1086,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by any cache or DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -970,6 +1096,7 @@ }, { "BriefDescription": "All offcore code reads", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -979,6 +1106,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -988,6 +1116,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -997,6 +1126,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -1006,6 +1136,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -1015,6 +1146,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1024,6 +1156,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1033,6 +1166,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1042,6 +1176,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1051,6 +1186,7 @@ }, { "BriefDescription": "Offcore code reads that HIT in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1060,6 +1196,7 @@ }, { "BriefDescription": "Offcore code reads that HITM in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1069,6 +1206,7 @@ }, { "BriefDescription": "Offcore requests satisfied by any cache or DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1078,6 +1216,7 @@ }, { "BriefDescription": "All offcore requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1087,6 +1226,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1096,6 +1236,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -1105,6 +1246,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -1114,6 +1256,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -1123,6 +1266,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1132,6 +1276,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1141,6 +1286,7 @@ }, { "BriefDescription": "Offcore requests satisfied by a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1150,6 +1296,7 @@ }, { "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1159,6 +1306,7 @@ }, { "BriefDescription": "Offcore requests that HIT in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1168,6 +1316,7 @@ }, { "BriefDescription": "Offcore requests that HITM in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1177,6 +1326,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1186,6 +1336,7 @@ }, { "BriefDescription": "All offcore RFO requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1195,6 +1346,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1204,6 +1356,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -1213,6 +1366,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -1222,6 +1376,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -1231,6 +1386,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1240,6 +1396,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1249,6 +1406,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1258,6 +1416,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1267,6 +1426,7 @@ }, { "BriefDescription": "Offcore RFO requests that HIT in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1276,6 +1436,7 @@ }, { "BriefDescription": "Offcore RFO requests that HITM in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1285,6 +1446,7 @@ }, { "BriefDescription": "Offcore writebacks to any cache or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1294,6 +1456,7 @@ }, { "BriefDescription": "All offcore writebacks", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1303,6 +1466,7 @@ }, { "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1312,6 +1476,7 @@ }, { "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -1321,6 +1486,7 @@ }, { "BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -1330,6 +1496,7 @@ }, { "BriefDescription": "Offcore writebacks to the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1339,6 +1506,7 @@ }, { "BriefDescription": "Offcore writebacks to the LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1348,6 +1516,7 @@ }, { "BriefDescription": "Offcore writebacks to a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1357,6 +1526,7 @@ }, { "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1366,6 +1536,7 @@ }, { "BriefDescription": "Offcore writebacks that HIT in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1375,6 +1546,7 @@ }, { "BriefDescription": "Offcore writebacks that HITM in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1384,6 +1556,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1393,6 +1566,7 @@ }, { "BriefDescription": "All offcore code or data read requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1402,6 +1576,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1411,6 +1586,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -1420,6 +1596,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -1429,6 +1606,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -1438,6 +1616,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied by the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1447,6 +1626,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1456,6 +1636,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied by a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1465,6 +1646,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1474,6 +1656,7 @@ }, { "BriefDescription": "Offcore code or data read requests that HIT in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1483,6 +1666,7 @@ }, { "BriefDescription": "Offcore code or data read requests that HITM in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1492,6 +1676,7 @@ }, { "BriefDescription": "Offcore request = all data, response = any cache_dram", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1501,6 +1686,7 @@ }, { "BriefDescription": "Offcore request = all data, response = any location", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1510,6 +1696,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1519,6 +1706,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -1528,6 +1716,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -1537,6 +1726,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -1546,6 +1736,7 @@ }, { "BriefDescription": "Offcore request = all data, response = local cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1555,6 +1746,7 @@ }, { "BriefDescription": "Offcore request = all data, response = local cache or dram", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1564,6 +1756,7 @@ }, { "BriefDescription": "Offcore request = all data, response = remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1573,6 +1766,7 @@ }, { "BriefDescription": "Offcore request = all data, response = remote cache or dram", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1582,6 +1776,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches that HIT in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1591,6 +1786,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches that HITM in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1600,6 +1796,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1609,6 +1806,7 @@ }, { "BriefDescription": "All offcore demand data requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1618,6 +1816,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1627,6 +1826,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -1636,6 +1836,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -1645,6 +1846,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -1654,6 +1856,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1663,6 +1866,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1672,6 +1876,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1681,6 +1886,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1690,6 +1896,7 @@ }, { "BriefDescription": "Offcore demand data requests that HIT in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1699,6 +1906,7 @@ }, { "BriefDescription": "Offcore demand data requests that HITM in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1708,6 +1916,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1717,6 +1926,7 @@ }, { "BriefDescription": "All offcore demand data reads", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1726,6 +1936,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1735,6 +1946,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -1744,6 +1956,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -1753,6 +1966,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -1762,6 +1976,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1771,6 +1986,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1780,6 +1996,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1789,6 +2006,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1798,6 +2016,7 @@ }, { "BriefDescription": "Offcore demand data reads that HIT in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1807,6 +2026,7 @@ }, { "BriefDescription": "Offcore demand data reads that HITM in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1816,6 +2036,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1825,6 +2046,7 @@ }, { "BriefDescription": "All offcore demand code reads", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1834,6 +2056,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1843,6 +2066,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -1852,6 +2076,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -1861,6 +2086,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -1870,6 +2096,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1879,6 +2106,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1888,6 +2116,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1897,6 +2126,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1906,6 +2136,7 @@ }, { "BriefDescription": "Offcore demand code reads that HIT in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1915,6 +2146,7 @@ }, { "BriefDescription": "Offcore demand code reads that HITM in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1924,6 +2156,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1933,6 +2166,7 @@ }, { "BriefDescription": "All offcore demand RFO requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1942,6 +2176,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1951,6 +2186,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -1960,6 +2196,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -1969,6 +2206,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -1978,6 +2216,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1987,6 +2226,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1996,6 +2236,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -2005,6 +2246,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2014,6 +2256,7 @@ }, { "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -2023,6 +2266,7 @@ }, { "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -2032,6 +2276,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2041,6 +2286,7 @@ }, { "BriefDescription": "All offcore other requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -2050,6 +2296,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -2059,6 +2306,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -2068,6 +2316,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -2077,6 +2326,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -2086,6 +2336,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -2095,6 +2346,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2104,6 +2356,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -2113,6 +2366,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2122,6 +2376,7 @@ }, { "BriefDescription": "Offcore other requests that HIT in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -2131,6 +2386,7 @@ }, { "BriefDescription": "Offcore other requests that HITM in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -2140,6 +2396,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2149,6 +2406,7 @@ }, { "BriefDescription": "All offcore prefetch data requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -2158,6 +2416,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -2167,6 +2426,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -2176,6 +2436,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -2185,6 +2446,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -2194,6 +2456,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -2203,6 +2466,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2212,6 +2476,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -2221,6 +2486,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2230,6 +2496,7 @@ }, { "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -2239,6 +2506,7 @@ }, { "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -2248,6 +2516,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2257,6 +2526,7 @@ }, { "BriefDescription": "All offcore prefetch data reads", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -2266,6 +2536,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -2275,6 +2546,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -2284,6 +2556,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -2293,6 +2566,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -2302,6 +2576,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -2311,6 +2586,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2320,6 +2596,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -2329,6 +2606,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2338,6 +2616,7 @@ }, { "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -2347,6 +2626,7 @@ }, { "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -2356,6 +2636,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2365,6 +2646,7 @@ }, { "BriefDescription": "All offcore prefetch code reads", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -2374,6 +2656,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -2383,6 +2666,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -2392,6 +2676,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -2401,6 +2686,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -2410,6 +2696,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -2419,6 +2706,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2428,6 +2716,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -2437,6 +2726,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2446,6 +2736,7 @@ }, { "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -2455,6 +2746,7 @@ }, { "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -2464,6 +2756,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2473,6 +2766,7 @@ }, { "BriefDescription": "All offcore prefetch RFO requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -2482,6 +2776,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -2491,6 +2786,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -2500,6 +2796,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -2509,6 +2806,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -2518,6 +2816,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -2527,6 +2826,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2536,6 +2836,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -2545,6 +2846,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2554,6 +2856,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -2563,6 +2866,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -2572,6 +2876,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2581,6 +2886,7 @@ }, { "BriefDescription": "All offcore prefetch requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -2590,6 +2896,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -2599,6 +2906,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -2608,6 +2916,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -2617,6 +2926,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -2626,6 +2936,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -2635,6 +2946,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2644,6 +2956,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -2653,6 +2966,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2662,6 +2976,7 @@ }, { "BriefDescription": "Offcore prefetch requests that HIT in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -2671,6 +2986,7 @@ }, { "BriefDescription": "Offcore prefetch requests that HITM in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -2680,6 +2996,7 @@ }, { "BriefDescription": "Super Queue LRU hints sent to LLC", + "Counter": "0,1,2,3", "EventCode": "0xF4", "EventName": "SQ_MISC.LRU_HINTS", "SampleAfterValue": "2000000", @@ -2687,6 +3004,7 @@ }, { "BriefDescription": "Super Queue lock splits across a cache line", + "Counter": "0,1,2,3", "EventCode": "0xF4", "EventName": "SQ_MISC.SPLIT_LOCK", "SampleAfterValue": "2000000", @@ -2694,6 +3012,7 @@ }, { "BriefDescription": "Loads delayed with at-Retirement block code", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "STORE_BLOCKS.AT_RET", "SampleAfterValue": "200000", @@ -2701,6 +3020,7 @@ }, { "BriefDescription": "Cacheable loads delayed with L1D block code", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "STORE_BLOCKS.L1D_BLOCK", "SampleAfterValue": "200000", diff --git a/tools/perf/pmu-events/arch/x86/westmereex/counter.json b/tools/perf/pmu-events/arch/x86/westmereex/counter.json new file mode 100644 index 000000000000..ecf0795dceab --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/westmereex/counter.json @@ -0,0 +1,7 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "4", + "CountersNumGeneric": "4" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereex/floating-point.json b/tools/perf/pmu-events/arch/x86/westmereex/floating-point.json index 196ae1d9b157..9bac9313b65c 100644 --- a/tools/perf/pmu-events/arch/x86/westmereex/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/westmereex/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "X87 Floating point assists (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF7", "EventName": "FP_ASSIST.ALL", "PEBS": "1", @@ -9,6 +10,7 @@ }, { "BriefDescription": "X87 Floating point assists for invalid input value (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF7", "EventName": "FP_ASSIST.INPUT", "PEBS": "1", @@ -17,6 +19,7 @@ }, { "BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF7", "EventName": "FP_ASSIST.OUTPUT", "PEBS": "1", @@ -25,6 +28,7 @@ }, { "BriefDescription": "MMX Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.MMX", "SampleAfterValue": "2000000", @@ -32,6 +36,7 @@ }, { "BriefDescription": "SSE2 integer Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER", "SampleAfterValue": "2000000", @@ -39,6 +44,7 @@ }, { "BriefDescription": "SSE* FP double precision Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", "SampleAfterValue": "2000000", @@ -46,6 +52,7 @@ }, { "BriefDescription": "SSE and SSE2 FP Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP", "SampleAfterValue": "2000000", @@ -53,6 +60,7 @@ }, { "BriefDescription": "SSE FP packed Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED", "SampleAfterValue": "2000000", @@ -60,6 +68,7 @@ }, { "BriefDescription": "SSE FP scalar Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR", "SampleAfterValue": "2000000", @@ -67,6 +76,7 @@ }, { "BriefDescription": "SSE* FP single precision Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", "SampleAfterValue": "2000000", @@ -74,6 +84,7 @@ }, { "BriefDescription": "Computational floating-point operations executed", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.X87", "SampleAfterValue": "2000000", @@ -81,6 +92,7 @@ }, { "BriefDescription": "All Floating Point to and from MMX transitions", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.ANY", "SampleAfterValue": "2000000", @@ -88,6 +100,7 @@ }, { "BriefDescription": "Transitions from MMX to Floating Point instructions", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.TO_FP", "SampleAfterValue": "2000000", @@ -95,6 +108,7 @@ }, { "BriefDescription": "Transitions from Floating Point to MMX instructions", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.TO_MMX", "SampleAfterValue": "2000000", @@ -102,6 +116,7 @@ }, { "BriefDescription": "128 bit SIMD integer pack operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.PACK", "SampleAfterValue": "200000", @@ -109,6 +124,7 @@ }, { "BriefDescription": "128 bit SIMD integer arithmetic operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_ARITH", "SampleAfterValue": "200000", @@ -116,6 +132,7 @@ }, { "BriefDescription": "128 bit SIMD integer logical operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_LOGICAL", "SampleAfterValue": "200000", @@ -123,6 +140,7 @@ }, { "BriefDescription": "128 bit SIMD integer multiply operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_MPY", "SampleAfterValue": "200000", @@ -130,6 +148,7 @@ }, { "BriefDescription": "128 bit SIMD integer shift operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_SHIFT", "SampleAfterValue": "200000", @@ -137,6 +156,7 @@ }, { "BriefDescription": "128 bit SIMD integer shuffle/move operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.SHUFFLE_MOVE", "SampleAfterValue": "200000", @@ -144,6 +164,7 @@ }, { "BriefDescription": "128 bit SIMD integer unpack operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.UNPACK", "SampleAfterValue": "200000", @@ -151,6 +172,7 @@ }, { "BriefDescription": "SIMD integer 64 bit pack operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACK", "SampleAfterValue": "200000", @@ -158,6 +180,7 @@ }, { "BriefDescription": "SIMD integer 64 bit arithmetic operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_ARITH", "SampleAfterValue": "200000", @@ -165,6 +188,7 @@ }, { "BriefDescription": "SIMD integer 64 bit logical operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_LOGICAL", "SampleAfterValue": "200000", @@ -172,6 +196,7 @@ }, { "BriefDescription": "SIMD integer 64 bit packed multiply operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_MPY", "SampleAfterValue": "200000", @@ -179,6 +204,7 @@ }, { "BriefDescription": "SIMD integer 64 bit shift operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_SHIFT", "SampleAfterValue": "200000", @@ -186,6 +212,7 @@ }, { "BriefDescription": "SIMD integer 64 bit shuffle/move operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.SHUFFLE_MOVE", "SampleAfterValue": "200000", @@ -193,6 +220,7 @@ }, { "BriefDescription": "SIMD integer 64 bit unpack operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.UNPACK", "SampleAfterValue": "200000", diff --git a/tools/perf/pmu-events/arch/x86/westmereex/frontend.json b/tools/perf/pmu-events/arch/x86/westmereex/frontend.json index f7f28510e3ae..c561ac24d91d 100644 --- a/tools/perf/pmu-events/arch/x86/westmereex/frontend.json +++ b/tools/perf/pmu-events/arch/x86/westmereex/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MACRO_INSTS.DECODED", "SampleAfterValue": "2000000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Macro-fused instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "MACRO_INSTS.FUSIONS_DECODED", "SampleAfterValue": "2000000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "Two Uop instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "TWO_UOP_INSTS_DECODED", "SampleAfterValue": "2000000", diff --git a/tools/perf/pmu-events/arch/x86/westmereex/memory.json b/tools/perf/pmu-events/arch/x86/westmereex/memory.json index f3c0d2d4bc6a..aaa7c43a7fec 100644 --- a/tools/perf/pmu-events/arch/x86/westmereex/memory.json +++ b/tools/perf/pmu-events/arch/x86/westmereex/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Misaligned store references", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "MISALIGN_MEM_REF.STORE", "SampleAfterValue": "200000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM", "MSRIndex": "0x1A6", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Offcore data reads that missed the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -35,6 +39,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by a remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -44,6 +49,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", @@ -53,6 +59,7 @@ }, { "BriefDescription": "Offcore code reads that missed the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -62,6 +69,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -71,6 +79,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by a remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -80,6 +89,7 @@ }, { "BriefDescription": "Offcore requests satisfied by any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM", "MSRIndex": "0x1A6", @@ -89,6 +99,7 @@ }, { "BriefDescription": "Offcore requests that missed the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -98,6 +109,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -107,6 +119,7 @@ }, { "BriefDescription": "Offcore requests satisfied by a remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -116,6 +129,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM", "MSRIndex": "0x1A6", @@ -125,6 +139,7 @@ }, { "BriefDescription": "Offcore RFO requests that missed the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -134,6 +149,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -143,6 +159,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by a remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -152,6 +169,7 @@ }, { "BriefDescription": "Offcore writebacks to any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM", "MSRIndex": "0x1A6", @@ -161,6 +179,7 @@ }, { "BriefDescription": "Offcore writebacks that missed the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -170,6 +189,7 @@ }, { "BriefDescription": "Offcore writebacks to the local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -179,6 +199,7 @@ }, { "BriefDescription": "Offcore writebacks to a remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -188,6 +209,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied by any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", @@ -197,6 +219,7 @@ }, { "BriefDescription": "Offcore code or data read requests that missed the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -206,6 +229,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied by the local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -215,6 +239,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied by a remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -224,6 +249,7 @@ }, { "BriefDescription": "Offcore request = all data, response = any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM", "MSRIndex": "0x1A6", @@ -233,6 +259,7 @@ }, { "BriefDescription": "Offcore request = all data, response = any LLC miss", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -242,6 +269,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the local DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -251,6 +279,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -260,6 +289,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM", "MSRIndex": "0x1A6", @@ -269,6 +299,7 @@ }, { "BriefDescription": "Offcore demand data requests that missed the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -278,6 +309,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -287,6 +319,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by a remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -296,6 +329,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM", "MSRIndex": "0x1A6", @@ -305,6 +339,7 @@ }, { "BriefDescription": "Offcore demand data reads that missed the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -314,6 +349,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -323,6 +359,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by a remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -332,6 +369,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", @@ -341,6 +379,7 @@ }, { "BriefDescription": "Offcore demand code reads that missed the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -350,6 +389,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -359,6 +399,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by a remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -368,6 +409,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM", "MSRIndex": "0x1A6", @@ -377,6 +419,7 @@ }, { "BriefDescription": "Offcore demand RFO requests that missed the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -386,6 +429,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -395,6 +439,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by a remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -404,6 +449,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM", "MSRIndex": "0x1A6", @@ -413,6 +459,7 @@ }, { "BriefDescription": "Offcore other requests that missed the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -422,6 +469,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by a remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -431,6 +479,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM", "MSRIndex": "0x1A6", @@ -440,6 +489,7 @@ }, { "BriefDescription": "Offcore prefetch data requests that missed the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -449,6 +499,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by the local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -458,6 +509,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by a remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -467,6 +519,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM", "MSRIndex": "0x1A6", @@ -476,6 +529,7 @@ }, { "BriefDescription": "Offcore prefetch data reads that missed the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -485,6 +539,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -494,6 +549,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by a remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -503,6 +559,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", @@ -512,6 +569,7 @@ }, { "BriefDescription": "Offcore prefetch code reads that missed the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -521,6 +579,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -530,6 +589,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by a remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -539,6 +599,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM", "MSRIndex": "0x1A6", @@ -548,6 +609,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests that missed the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -557,6 +619,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by the local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -566,6 +629,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -575,6 +639,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM", "MSRIndex": "0x1A6", @@ -584,6 +649,7 @@ }, { "BriefDescription": "Offcore prefetch requests that missed the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -593,6 +659,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -602,6 +669,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by a remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", diff --git a/tools/perf/pmu-events/arch/x86/westmereex/other.json b/tools/perf/pmu-events/arch/x86/westmereex/other.json index 488274980564..bcf5bcf637c0 100644 --- a/tools/perf/pmu-events/arch/x86/westmereex/other.json +++ b/tools/perf/pmu-events/arch/x86/westmereex/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "ES segment renames", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "ES_REG_RENAMES", "SampleAfterValue": "2000000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "I/O transactions", + "Counter": "0,1,2,3", "EventCode": "0x6C", "EventName": "IO_TRANSACTIONS", "SampleAfterValue": "2000000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "L1I instruction fetch stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "L1I.CYCLES_STALLED", "SampleAfterValue": "2000000", @@ -22,6 +25,7 @@ }, { "BriefDescription": "L1I instruction fetch hits", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "L1I.HITS", "SampleAfterValue": "2000000", @@ -29,6 +33,7 @@ }, { "BriefDescription": "L1I instruction fetch misses", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "L1I.MISSES", "SampleAfterValue": "2000000", @@ -36,6 +41,7 @@ }, { "BriefDescription": "L1I Instruction fetches", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "L1I.READS", "SampleAfterValue": "2000000", @@ -43,6 +49,7 @@ }, { "BriefDescription": "Large ITLB hit", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "LARGE_ITLB.HIT", "SampleAfterValue": "200000", @@ -50,6 +57,7 @@ }, { "BriefDescription": "Loads that partially overlap an earlier store", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "LOAD_BLOCK.OVERLAP_STORE", "SampleAfterValue": "200000", @@ -57,6 +65,7 @@ }, { "BriefDescription": "All loads dispatched", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "LOAD_DISPATCH.ANY", "SampleAfterValue": "2000000", @@ -64,6 +73,7 @@ }, { "BriefDescription": "Loads dispatched from the MOB", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "LOAD_DISPATCH.MOB", "SampleAfterValue": "2000000", @@ -71,6 +81,7 @@ }, { "BriefDescription": "Loads dispatched that bypass the MOB", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "LOAD_DISPATCH.RS", "SampleAfterValue": "2000000", @@ -78,6 +89,7 @@ }, { "BriefDescription": "Loads dispatched from stage 305", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "LOAD_DISPATCH.RS_DELAYED", "SampleAfterValue": "2000000", @@ -85,6 +97,7 @@ }, { "BriefDescription": "False dependencies due to partial address aliasing", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "PARTIAL_ADDRESS_ALIAS", "SampleAfterValue": "200000", @@ -92,6 +105,7 @@ }, { "BriefDescription": "All Store buffer stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "SB_DRAIN.ANY", "SampleAfterValue": "200000", @@ -99,6 +113,7 @@ }, { "BriefDescription": "Segment rename stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "SEG_RENAME_STALLS", "SampleAfterValue": "2000000", @@ -106,6 +121,7 @@ }, { "BriefDescription": "Snoop code requests", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "SNOOPQ_REQUESTS.CODE", "SampleAfterValue": "100000", @@ -113,6 +129,7 @@ }, { "BriefDescription": "Snoop data requests", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "SNOOPQ_REQUESTS.DATA", "SampleAfterValue": "100000", @@ -120,6 +137,7 @@ }, { "BriefDescription": "Snoop invalidate requests", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "SNOOPQ_REQUESTS.INVALIDATE", "SampleAfterValue": "100000", @@ -127,6 +145,7 @@ }, { "BriefDescription": "Outstanding snoop code requests", + "Counter": "0", "EventCode": "0xB3", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE", "SampleAfterValue": "2000000", @@ -134,6 +153,7 @@ }, { "BriefDescription": "Cycles snoop code requests queued", + "Counter": "0", "CounterMask": "1", "EventCode": "0xB3", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY", @@ -142,6 +162,7 @@ }, { "BriefDescription": "Outstanding snoop data requests", + "Counter": "0", "EventCode": "0xB3", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA", "SampleAfterValue": "2000000", @@ -149,6 +170,7 @@ }, { "BriefDescription": "Cycles snoop data requests queued", + "Counter": "0", "CounterMask": "1", "EventCode": "0xB3", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY", @@ -157,6 +179,7 @@ }, { "BriefDescription": "Outstanding snoop invalidate requests", + "Counter": "0", "EventCode": "0xB3", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE", "SampleAfterValue": "2000000", @@ -164,6 +187,7 @@ }, { "BriefDescription": "Cycles snoop invalidate requests queued", + "Counter": "0", "CounterMask": "1", "EventCode": "0xB3", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY", @@ -172,6 +196,7 @@ }, { "BriefDescription": "Thread responded HIT to snoop", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "SNOOP_RESPONSE.HIT", "SampleAfterValue": "100000", @@ -179,6 +204,7 @@ }, { "BriefDescription": "Thread responded HITE to snoop", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "SNOOP_RESPONSE.HITE", "SampleAfterValue": "100000", @@ -186,6 +212,7 @@ }, { "BriefDescription": "Thread responded HITM to snoop", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "SNOOP_RESPONSE.HITM", "SampleAfterValue": "100000", @@ -193,6 +220,7 @@ }, { "BriefDescription": "Super Queue full stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xF6", "EventName": "SQ_FULL_STALL_CYCLES", "SampleAfterValue": "2000000", diff --git a/tools/perf/pmu-events/arch/x86/westmereex/pipeline.json b/tools/perf/pmu-events/arch/x86/westmereex/pipeline.json index 026236558d05..e8cac8622b30 100644 --- a/tools/perf/pmu-events/arch/x86/westmereex/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/westmereex/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles the divider is busy", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "ARITH.CYCLES_DIV_BUSY", "SampleAfterValue": "2000000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Divide Operations executed", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x14", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Multiply operations executed", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "ARITH.MUL", "SampleAfterValue": "2000000", @@ -25,6 +28,7 @@ }, { "BriefDescription": "BACLEAR asserted with bad target address", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "BACLEAR.BAD_TARGET", "SampleAfterValue": "2000000", @@ -32,6 +36,7 @@ }, { "BriefDescription": "BACLEAR asserted, regardless of cause", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "BACLEAR.CLEAR", "SampleAfterValue": "2000000", @@ -39,6 +44,7 @@ }, { "BriefDescription": "Instruction queue forced BACLEAR", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "BACLEAR_FORCE_IQ", "SampleAfterValue": "2000000", @@ -46,6 +52,7 @@ }, { "BriefDescription": "Early Branch Prediction Unit clears", + "Counter": "0,1,2,3", "EventCode": "0xE8", "EventName": "BPU_CLEARS.EARLY", "SampleAfterValue": "2000000", @@ -53,6 +60,7 @@ }, { "BriefDescription": "Late Branch Prediction Unit clears", + "Counter": "0,1,2,3", "EventCode": "0xE8", "EventName": "BPU_CLEARS.LATE", "SampleAfterValue": "2000000", @@ -60,6 +68,7 @@ }, { "BriefDescription": "Branch prediction unit missed call or return", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "BPU_MISSED_CALL_RET", "SampleAfterValue": "2000000", @@ -67,6 +76,7 @@ }, { "BriefDescription": "Branch instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "BR_INST_DECODED", "SampleAfterValue": "2000000", @@ -74,6 +84,7 @@ }, { "BriefDescription": "Branch instructions executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ANY", "SampleAfterValue": "200000", @@ -81,6 +92,7 @@ }, { "BriefDescription": "Conditional branch instructions executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.COND", "SampleAfterValue": "200000", @@ -88,6 +100,7 @@ }, { "BriefDescription": "Unconditional branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.DIRECT", "SampleAfterValue": "200000", @@ -95,6 +108,7 @@ }, { "BriefDescription": "Unconditional call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL", "SampleAfterValue": "20000", @@ -102,6 +116,7 @@ }, { "BriefDescription": "Indirect call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL", "SampleAfterValue": "20000", @@ -109,6 +124,7 @@ }, { "BriefDescription": "Indirect non call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL", "SampleAfterValue": "20000", @@ -116,6 +132,7 @@ }, { "BriefDescription": "Call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.NEAR_CALLS", "SampleAfterValue": "20000", @@ -123,6 +140,7 @@ }, { "BriefDescription": "All non call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.NON_CALLS", "SampleAfterValue": "200000", @@ -130,6 +148,7 @@ }, { "BriefDescription": "Indirect return branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.RETURN_NEAR", "SampleAfterValue": "20000", @@ -137,6 +156,7 @@ }, { "BriefDescription": "Taken branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN", "SampleAfterValue": "200000", @@ -144,6 +164,7 @@ }, { "BriefDescription": "Retired branch instructions (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -152,6 +173,7 @@ }, { "BriefDescription": "Retired conditional branch instructions (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CONDITIONAL", "PEBS": "1", @@ -160,6 +182,7 @@ }, { "BriefDescription": "Retired near call instructions (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL", "PEBS": "1", @@ -168,6 +191,7 @@ }, { "BriefDescription": "Mispredicted branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ANY", "SampleAfterValue": "20000", @@ -175,6 +199,7 @@ }, { "BriefDescription": "Mispredicted conditional branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.COND", "SampleAfterValue": "20000", @@ -182,6 +207,7 @@ }, { "BriefDescription": "Mispredicted unconditional branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.DIRECT", "SampleAfterValue": "20000", @@ -189,6 +215,7 @@ }, { "BriefDescription": "Mispredicted non call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL", "SampleAfterValue": "2000", @@ -196,6 +223,7 @@ }, { "BriefDescription": "Mispredicted indirect call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL", "SampleAfterValue": "2000", @@ -203,6 +231,7 @@ }, { "BriefDescription": "Mispredicted indirect non call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL", "SampleAfterValue": "2000", @@ -210,6 +239,7 @@ }, { "BriefDescription": "Mispredicted call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NEAR_CALLS", "SampleAfterValue": "2000", @@ -217,6 +247,7 @@ }, { "BriefDescription": "Mispredicted non call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NON_CALLS", "SampleAfterValue": "20000", @@ -224,6 +255,7 @@ }, { "BriefDescription": "Mispredicted return branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.RETURN_NEAR", "SampleAfterValue": "2000", @@ -231,6 +263,7 @@ }, { "BriefDescription": "Mispredicted taken branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN", "SampleAfterValue": "20000", @@ -238,6 +271,7 @@ }, { "BriefDescription": "Mispredicted retired branch instructions (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -246,6 +280,7 @@ }, { "BriefDescription": "Mispredicted conditional retired branches (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.CONDITIONAL", "PEBS": "1", @@ -254,6 +289,7 @@ }, { "BriefDescription": "Mispredicted near retired calls (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_CALL", "PEBS": "1", @@ -262,11 +298,13 @@ }, { "BriefDescription": "Reference cycles when thread is not halted (fixed counter)", + "Counter": "Fixed counter 3", "EventName": "CPU_CLK_UNHALTED.REF", "SampleAfterValue": "2000000" }, { "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_P", "SampleAfterValue": "100000", @@ -274,17 +312,20 @@ }, { "BriefDescription": "Cycles when thread is not halted (fixed counter)", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.THREAD", "SampleAfterValue": "2000000" }, { "BriefDescription": "Cycles when thread is not halted (programmable counter)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "SampleAfterValue": "2000000" }, { "BriefDescription": "Total CPU cycles", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES", @@ -293,6 +334,7 @@ }, { "BriefDescription": "Any Instruction Length Decoder stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.ANY", "SampleAfterValue": "2000000", @@ -300,6 +342,7 @@ }, { "BriefDescription": "Instruction Queue full stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.IQ_FULL", "SampleAfterValue": "2000000", @@ -307,6 +350,7 @@ }, { "BriefDescription": "Length Change Prefix stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.LCP", "SampleAfterValue": "2000000", @@ -314,6 +358,7 @@ }, { "BriefDescription": "Stall cycles due to BPU MRU bypass", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.MRU", "SampleAfterValue": "2000000", @@ -321,6 +366,7 @@ }, { "BriefDescription": "Regen stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.REGEN", "SampleAfterValue": "2000000", @@ -328,6 +374,7 @@ }, { "BriefDescription": "Instructions that must be decoded by decoder 0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "INST_DECODED.DEC0", "SampleAfterValue": "2000000", @@ -335,6 +382,7 @@ }, { "BriefDescription": "Instructions written to instruction queue.", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "INST_QUEUE_WRITES", "SampleAfterValue": "2000000", @@ -342,6 +390,7 @@ }, { "BriefDescription": "Cycles instructions are written to the instruction queue", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "INST_QUEUE_WRITE_CYCLES", "SampleAfterValue": "2000000", @@ -349,11 +398,13 @@ }, { "BriefDescription": "Instructions retired (fixed counter)", + "Counter": "Fixed counter 1", "EventName": "INST_RETIRED.ANY", "SampleAfterValue": "2000000" }, { "BriefDescription": "Instructions retired (Programmable counter and Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", "PEBS": "1", @@ -362,6 +413,7 @@ }, { "BriefDescription": "Retired MMX instructions (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "INST_RETIRED.MMX", "PEBS": "1", @@ -370,6 +422,7 @@ }, { "BriefDescription": "Total cycles (Precise Event)", + "Counter": "0,1,2,3", "CounterMask": "16", "EventCode": "0xC0", "EventName": "INST_RETIRED.TOTAL_CYCLES", @@ -380,6 +433,7 @@ }, { "BriefDescription": "Total cycles (Precise Event)", + "Counter": "0,1,2,3", "CounterMask": "16", "EventCode": "0xC0", "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", @@ -390,6 +444,7 @@ }, { "BriefDescription": "Retired floating-point operations (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "INST_RETIRED.X87", "PEBS": "1", @@ -398,6 +453,7 @@ }, { "BriefDescription": "Load operations conflicting with software prefetches", + "Counter": "0,1", "EventCode": "0x4C", "EventName": "LOAD_HIT_PRE", "SampleAfterValue": "200000", @@ -405,6 +461,7 @@ }, { "BriefDescription": "Cycles when uops were delivered by the LSD", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA8", "EventName": "LSD.ACTIVE", @@ -413,6 +470,7 @@ }, { "BriefDescription": "Cycles no uops were delivered by the LSD", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA8", "EventName": "LSD.INACTIVE", @@ -422,6 +480,7 @@ }, { "BriefDescription": "Loops that can't stream from the instruction queue", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "LSD_OVERFLOW", "SampleAfterValue": "2000000", @@ -429,6 +488,7 @@ }, { "BriefDescription": "Cycles machine clear asserted", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.CYCLES", "SampleAfterValue": "20000", @@ -436,6 +496,7 @@ }, { "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEM_ORDER", "SampleAfterValue": "20000", @@ -443,6 +504,7 @@ }, { "BriefDescription": "Self-Modifying Code detected", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "SampleAfterValue": "20000", @@ -450,6 +512,7 @@ }, { "BriefDescription": "All RAT stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "RAT_STALLS.ANY", "SampleAfterValue": "2000000", @@ -457,6 +520,7 @@ }, { "BriefDescription": "Flag stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "RAT_STALLS.FLAGS", "SampleAfterValue": "2000000", @@ -464,6 +528,7 @@ }, { "BriefDescription": "Partial register stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "RAT_STALLS.REGISTERS", "SampleAfterValue": "2000000", @@ -471,6 +536,7 @@ }, { "BriefDescription": "ROB read port stalls cycles", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "RAT_STALLS.ROB_READ_PORT", "SampleAfterValue": "2000000", @@ -478,6 +544,7 @@ }, { "BriefDescription": "Scoreboard stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "RAT_STALLS.SCOREBOARD", "SampleAfterValue": "2000000", @@ -485,6 +552,7 @@ }, { "BriefDescription": "Resource related stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ANY", "SampleAfterValue": "2000000", @@ -492,6 +560,7 @@ }, { "BriefDescription": "FPU control word write stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.FPCW", "SampleAfterValue": "2000000", @@ -499,6 +568,7 @@ }, { "BriefDescription": "Load buffer stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.LOAD", "SampleAfterValue": "2000000", @@ -506,6 +576,7 @@ }, { "BriefDescription": "MXCSR rename stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.MXCSR", "SampleAfterValue": "2000000", @@ -513,6 +584,7 @@ }, { "BriefDescription": "Other Resource related stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.OTHER", "SampleAfterValue": "2000000", @@ -520,6 +592,7 @@ }, { "BriefDescription": "ROB full stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ROB_FULL", "SampleAfterValue": "2000000", @@ -527,6 +600,7 @@ }, { "BriefDescription": "Reservation Station full stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.RS_FULL", "SampleAfterValue": "2000000", @@ -534,6 +608,7 @@ }, { "BriefDescription": "Store buffer stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.STORE", "SampleAfterValue": "2000000", @@ -541,6 +616,7 @@ }, { "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE", "PEBS": "1", @@ -549,6 +625,7 @@ }, { "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE", "PEBS": "1", @@ -557,6 +634,7 @@ }, { "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE", "PEBS": "1", @@ -565,6 +643,7 @@ }, { "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE", "PEBS": "1", @@ -573,6 +652,7 @@ }, { "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER", "PEBS": "1", @@ -581,6 +661,7 @@ }, { "BriefDescription": "Stack pointer instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UOPS_DECODED.ESP_FOLDING", "SampleAfterValue": "2000000", @@ -588,6 +669,7 @@ }, { "BriefDescription": "Stack pointer sync operations", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UOPS_DECODED.ESP_SYNC", "SampleAfterValue": "2000000", @@ -595,6 +677,7 @@ }, { "BriefDescription": "Uops decoded by Microcode Sequencer", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xD1", "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE", @@ -603,6 +686,7 @@ }, { "BriefDescription": "Cycles no Uops are decoded", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xD1", "EventName": "UOPS_DECODED.STALL_CYCLES", @@ -613,6 +697,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles Uops executed on any port (core count)", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES", @@ -622,6 +707,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5", @@ -630,6 +716,7 @@ }, { "BriefDescription": "Uops executed on any port (core count)", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xB1", @@ -640,6 +727,7 @@ }, { "BriefDescription": "Uops executed on ports 0-4 (core count)", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xB1", @@ -651,6 +739,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles no Uops issued on any port (core count)", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES", @@ -661,6 +750,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5", @@ -670,6 +760,7 @@ }, { "BriefDescription": "Uops executed on port 0", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT0", "SampleAfterValue": "2000000", @@ -677,6 +768,7 @@ }, { "BriefDescription": "Uops issued on ports 0, 1 or 5", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT015", "SampleAfterValue": "2000000", @@ -684,6 +776,7 @@ }, { "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES", @@ -693,6 +786,7 @@ }, { "BriefDescription": "Uops executed on port 1", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT1", "SampleAfterValue": "2000000", @@ -701,6 +795,7 @@ { "AnyThread": "1", "BriefDescription": "Uops issued on ports 2, 3 or 4", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT234_CORE", "SampleAfterValue": "2000000", @@ -709,6 +804,7 @@ { "AnyThread": "1", "BriefDescription": "Uops executed on port 2 (core count)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT2_CORE", "SampleAfterValue": "2000000", @@ -717,6 +813,7 @@ { "AnyThread": "1", "BriefDescription": "Uops executed on port 3 (core count)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT3_CORE", "SampleAfterValue": "2000000", @@ -725,6 +822,7 @@ { "AnyThread": "1", "BriefDescription": "Uops executed on port 4 (core count)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT4_CORE", "SampleAfterValue": "2000000", @@ -732,6 +830,7 @@ }, { "BriefDescription": "Uops executed on port 5", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT5", "SampleAfterValue": "2000000", @@ -739,6 +838,7 @@ }, { "BriefDescription": "Uops issued", + "Counter": "0,1,2,3", "EventCode": "0xE", "EventName": "UOPS_ISSUED.ANY", "SampleAfterValue": "2000000", @@ -747,6 +847,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles no Uops were issued on any thread", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xE", "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", @@ -757,6 +858,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles Uops were issued on either thread", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xE", "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS", @@ -765,6 +867,7 @@ }, { "BriefDescription": "Fused Uops issued", + "Counter": "0,1,2,3", "EventCode": "0xE", "EventName": "UOPS_ISSUED.FUSED", "SampleAfterValue": "2000000", @@ -772,6 +875,7 @@ }, { "BriefDescription": "Cycles no Uops were issued", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xE", "EventName": "UOPS_ISSUED.STALL_CYCLES", @@ -781,6 +885,7 @@ }, { "BriefDescription": "Cycles Uops are being retired", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ACTIVE_CYCLES", @@ -790,6 +895,7 @@ }, { "BriefDescription": "Uops retired (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ANY", "PEBS": "1", @@ -798,6 +904,7 @@ }, { "BriefDescription": "Macro-fused Uops retired (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.MACRO_FUSED", "PEBS": "1", @@ -806,6 +913,7 @@ }, { "BriefDescription": "Retirement slots used (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.RETIRE_SLOTS", "PEBS": "1", @@ -814,6 +922,7 @@ }, { "BriefDescription": "Cycles Uops are not retiring (Precise Event)", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.STALL_CYCLES", @@ -824,6 +933,7 @@ }, { "BriefDescription": "Total cycles using precise uop retired event (Precise Event)", + "Counter": "0,1,2,3", "CounterMask": "16", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", @@ -834,6 +944,7 @@ }, { "BriefDescription": "Uop unfusions due to FP exceptions", + "Counter": "0,1,2,3", "EventCode": "0xDB", "EventName": "UOP_UNFUSION", "SampleAfterValue": "2000000", diff --git a/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json b/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json index 6c92b2be2d06..0c3501e6e5a3 100644 --- a/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "DTLB load misses", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.ANY", "SampleAfterValue": "200000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "DTLB load miss large page walks", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "DTLB load miss caused by low part of address", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.PDE_MISS", "SampleAfterValue": "200000", @@ -22,6 +25,7 @@ }, { "BriefDescription": "DTLB second level hit", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "2000000", @@ -29,6 +33,7 @@ }, { "BriefDescription": "DTLB load miss page walks complete", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", @@ -36,6 +41,7 @@ }, { "BriefDescription": "DTLB load miss page walk cycles", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES", "SampleAfterValue": "200000", @@ -43,6 +49,7 @@ }, { "BriefDescription": "DTLB misses", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.ANY", "SampleAfterValue": "200000", @@ -50,6 +57,7 @@ }, { "BriefDescription": "DTLB miss large page walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", @@ -57,6 +65,7 @@ }, { "BriefDescription": "DTLB misses caused by low part of address. Count also includes 2M page references because 2M pages do not use the PDE.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.PDE_MISS", "SampleAfterValue": "200000", @@ -64,6 +73,7 @@ }, { "BriefDescription": "DTLB first level misses but second level hit", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.STLB_HIT", "SampleAfterValue": "200000", @@ -71,6 +81,7 @@ }, { "BriefDescription": "DTLB miss page walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", @@ -78,6 +89,7 @@ }, { "BriefDescription": "DTLB miss page walk cycles", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.WALK_CYCLES", "SampleAfterValue": "2000000", @@ -85,6 +97,7 @@ }, { "BriefDescription": "Extended Page Table walk cycles", + "Counter": "0,1,2,3", "EventCode": "0x4F", "EventName": "EPT.WALK_CYCLES", "SampleAfterValue": "2000000", @@ -92,6 +105,7 @@ }, { "BriefDescription": "ITLB flushes", + "Counter": "0,1,2,3", "EventCode": "0xAE", "EventName": "ITLB_FLUSH", "SampleAfterValue": "2000000", @@ -99,6 +113,7 @@ }, { "BriefDescription": "ITLB miss", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.ANY", "SampleAfterValue": "200000", @@ -106,6 +121,7 @@ }, { "BriefDescription": "ITLB miss large page walks", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", @@ -113,6 +129,7 @@ }, { "BriefDescription": "ITLB miss page walks", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", @@ -120,6 +137,7 @@ }, { "BriefDescription": "ITLB miss page walk cycles", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_CYCLES", "SampleAfterValue": "2000000", @@ -127,6 +145,7 @@ }, { "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC8", "EventName": "ITLB_MISS_RETIRED", "PEBS": "1", @@ -135,6 +154,7 @@ }, { "BriefDescription": "Retired loads that miss the DTLB (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", "PEBS": "1", @@ -143,6 +163,7 @@ }, { "BriefDescription": "Retired stores that miss the DTLB (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC", "EventName": "MEM_STORE_RETIRED.DTLB_MISS", "PEBS": "1", |