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| author | Dan Williams <dan.j.williams@intel.com> | 2022-05-19 01:34:48 +0200 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-05-19 17:50:41 +0200 |
| commit | 14d78874077442d1d0f08129f5a0ea5070984b4b (patch) | |
| tree | 4c80ac1f7f8fb934b3a430fdcdacee9d40e47f05 /tools/testing/cxl/Kbuild | |
| parent | cxl/pci: Move cxl_await_media_ready() to the core (diff) | |
| download | linux-14d78874077442d1d0f08129f5a0ea5070984b4b.tar.xz linux-14d78874077442d1d0f08129f5a0ea5070984b4b.zip | |
cxl/mem: Consolidate CXL DVSEC Range enumeration in the core
In preparation for fixing the setting of the 'mem_enabled' bit in CXL
DVSEC Control register, move all CXL DVSEC range enumeration into the
same source file.
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/165291688886.1426646.15046138604010482084.stgit@dwillia2-xfh
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'tools/testing/cxl/Kbuild')
| -rw-r--r-- | tools/testing/cxl/Kbuild | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild index 6007fe770122..2ea6fcb8baa5 100644 --- a/tools/testing/cxl/Kbuild +++ b/tools/testing/cxl/Kbuild @@ -9,6 +9,7 @@ ldflags-y += --wrap=devm_cxl_setup_hdm ldflags-y += --wrap=devm_cxl_add_passthrough_decoder ldflags-y += --wrap=devm_cxl_enumerate_decoders ldflags-y += --wrap=cxl_await_media_ready +ldflags-y += --wrap=cxl_dvsec_ranges DRIVERS := ../../../drivers CXL_SRC := $(DRIVERS)/cxl |