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* cxl/pci: Rename cxl_setup_parent_dport() and cxl_dport_map_regs()Li Ming2024-09-041-1/+1
* cxl/test: Skip cxl_setup_parent_dport() for emulated dportsLi Ming2024-08-101-0/+1
* cxl/test: Add support for qos_class checkingDave Jiang2024-02-171-0/+1
* tools/testing/cxl: Disable "missing prototypes / declarations" warningsDan Williams2024-01-221-0/+2
* cxl: Add callback to parse the DSMAS subtables from CDATDave Jiang2023-12-221-0/+1
* cxl: Add cxl_num_decoders_committed() usage to cxl_testDave Jiang2023-12-051-0/+1
* Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams2023-06-261-1/+2
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| * cxl/acpi: Probe RCRB later during RCH downstream port creationRobert Richter2023-06-251-1/+2
* | Merge branch 'for-6.5/cxl-perf' into for-6.5/cxlDan Williams2023-06-261-0/+1
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| * | cxl/pci: Find and register CXL PMU devicesJonathan Cameron2023-05-301-0/+1
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* / Revert "cxl/port: Enable the HDM decoder capability for switch ports"Dan Williams2023-06-251-1/+0
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* cxl/port: Enable the HDM decoder capability for switch portsDan Williams2023-05-181-0/+1
* Merge branch 'for-6.3/cxl-rr-emu' into cxl/nextDan Williams2023-02-151-0/+1
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| * cxl/port: Export cxl_dvsec_rr_decode() to cxl_portDave Jiang2023-02-151-0/+1
* | tools/testing/cxl: Prevent cxl_test from confusing production modulesDan Williams2023-01-061-0/+6
* | cxl/pci: Move tracepoint definitions to drivers/cxl/core/Dan Williams2023-01-051-0/+2
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* Merge branch 'for-6.2/cxl-security' into for-6.2/cxlDan Williams2022-12-051-0/+1
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| * cxl/pmem: Introduce nvdimm_security_ops with ->get_flags() operationDave Jiang2022-12-011-0/+1
* | cxl/acpi: Extract component registers of restricted hosts from RCRBRobert Richter2022-12-031-0/+1
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* cxl/region: Add region creation supportBen Widawsky2022-07-221-0/+1
* cxl/mem: Merge cxl_dvsec_ranges() and cxl_hdm_decode_init()Dan Williams2022-05-191-2/+1
* cxl/mem: Consolidate CXL DVSEC Range enumeration in the coreDan Williams2022-05-191-0/+1
* cxl/pci: Move cxl_await_media_ready() to the coreDan Williams2022-05-191-0/+1
* cxl/mem: Add the cxl_mem driverBen Widawsky2022-02-091-0/+6
* cxl/port: Add a driver for 'struct cxl_port' objectsBen Widawsky2022-02-091-0/+5
* cxl/core/hdm: Add CXL standard decoder enumeration to the coreDan Williams2022-02-091-0/+4
* cxl/core: Generalize dport enumeration in the coreDan Williams2022-02-091-1/+2
* cxl/pmem: Introduce a find_cxl_root() helperDan Williams2022-02-091-2/+0
* cxl/core/port: Rename bus.c to port.cDan Williams2022-02-091-1/+1
* cxl/test: Mock acpi_table_parse_cedt()Dan Williams2021-11-151-2/+1
* tools/testing/cxl: Introduce a mock memory device + driverDan Williams2021-09-211-0/+2
* tools/testing/cxl: Introduce a mocked-up CXL port hierarchyDan Williams2021-09-211-0/+36