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Author
Age
Files
Lines
*
cxl/pci: Rename cxl_setup_parent_dport() and cxl_dport_map_regs()
Li Ming
2024-09-04
1
-1
/
+1
*
cxl/test: Skip cxl_setup_parent_dport() for emulated dports
Li Ming
2024-08-10
1
-0
/
+1
*
cxl/test: Add support for qos_class checking
Dave Jiang
2024-02-17
1
-0
/
+1
*
tools/testing/cxl: Disable "missing prototypes / declarations" warnings
Dan Williams
2024-01-22
1
-0
/
+2
*
cxl: Add callback to parse the DSMAS subtables from CDAT
Dave Jiang
2023-12-22
1
-0
/
+1
*
cxl: Add cxl_num_decoders_committed() usage to cxl_test
Dave Jiang
2023-12-05
1
-0
/
+1
*
Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxl
Dan Williams
2023-06-26
1
-1
/
+2
|
\
|
*
cxl/acpi: Probe RCRB later during RCH downstream port creation
Robert Richter
2023-06-25
1
-1
/
+2
*
|
Merge branch 'for-6.5/cxl-perf' into for-6.5/cxl
Dan Williams
2023-06-26
1
-0
/
+1
|
\
\
|
*
|
cxl/pci: Find and register CXL PMU devices
Jonathan Cameron
2023-05-30
1
-0
/
+1
|
|
/
*
/
Revert "cxl/port: Enable the HDM decoder capability for switch ports"
Dan Williams
2023-06-25
1
-1
/
+0
|
/
*
cxl/port: Enable the HDM decoder capability for switch ports
Dan Williams
2023-05-18
1
-0
/
+1
*
Merge branch 'for-6.3/cxl-rr-emu' into cxl/next
Dan Williams
2023-02-15
1
-0
/
+1
|
\
|
*
cxl/port: Export cxl_dvsec_rr_decode() to cxl_port
Dave Jiang
2023-02-15
1
-0
/
+1
*
|
tools/testing/cxl: Prevent cxl_test from confusing production modules
Dan Williams
2023-01-06
1
-0
/
+6
*
|
cxl/pci: Move tracepoint definitions to drivers/cxl/core/
Dan Williams
2023-01-05
1
-0
/
+2
|
/
*
Merge branch 'for-6.2/cxl-security' into for-6.2/cxl
Dan Williams
2022-12-05
1
-0
/
+1
|
\
|
*
cxl/pmem: Introduce nvdimm_security_ops with ->get_flags() operation
Dave Jiang
2022-12-01
1
-0
/
+1
*
|
cxl/acpi: Extract component registers of restricted hosts from RCRB
Robert Richter
2022-12-03
1
-0
/
+1
|
/
*
cxl/region: Add region creation support
Ben Widawsky
2022-07-22
1
-0
/
+1
*
cxl/mem: Merge cxl_dvsec_ranges() and cxl_hdm_decode_init()
Dan Williams
2022-05-19
1
-2
/
+1
*
cxl/mem: Consolidate CXL DVSEC Range enumeration in the core
Dan Williams
2022-05-19
1
-0
/
+1
*
cxl/pci: Move cxl_await_media_ready() to the core
Dan Williams
2022-05-19
1
-0
/
+1
*
cxl/mem: Add the cxl_mem driver
Ben Widawsky
2022-02-09
1
-0
/
+6
*
cxl/port: Add a driver for 'struct cxl_port' objects
Ben Widawsky
2022-02-09
1
-0
/
+5
*
cxl/core/hdm: Add CXL standard decoder enumeration to the core
Dan Williams
2022-02-09
1
-0
/
+4
*
cxl/core: Generalize dport enumeration in the core
Dan Williams
2022-02-09
1
-1
/
+2
*
cxl/pmem: Introduce a find_cxl_root() helper
Dan Williams
2022-02-09
1
-2
/
+0
*
cxl/core/port: Rename bus.c to port.c
Dan Williams
2022-02-09
1
-1
/
+1
*
cxl/test: Mock acpi_table_parse_cedt()
Dan Williams
2021-11-15
1
-2
/
+1
*
tools/testing/cxl: Introduce a mock memory device + driver
Dan Williams
2021-09-21
1
-0
/
+2
*
tools/testing/cxl: Introduce a mocked-up CXL port hierarchy
Dan Williams
2021-09-21
1
-0
/
+36