diff options
38 files changed, 7022 insertions, 3115 deletions
diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index e04c213a0dee..d2e887415d5d 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -248,6 +248,13 @@ properties: - const: friendlyarm,nanopc-t6 - const: rockchip,rk3588 + - description: FriendlyElec CM3588-based boards + items: + - enum: + - friendlyarm,cm3588-nas + - const: friendlyarm,cm3588 + - const: rockchip,rk3588 + - description: GameForce Chi items: - const: gameforce,chi @@ -627,6 +634,11 @@ properties: - const: mqmaker,miqi - const: rockchip,rk3288 + - description: Neardi LBA3368 + items: + - const: neardi,lba3368 + - const: rockchip,rk3368 + - description: Netxeon R89 board items: - const: netxeon,r89 @@ -814,6 +826,18 @@ properties: - const: radxa,rock-5b - const: rockchip,rk3588 + - description: Radxa ROCK S0 + items: + - const: radxa,rock-s0 + - const: rockchip,rk3308 + + - description: Radxa ZERO 3W/3E + items: + - enum: + - radxa,zero-3e + - radxa,zero-3w + - const: rockchip,rk3566 + - description: Rikomagic MK808 v1 items: - const: rikomagic,mk808 diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index eabc353b8512..80f209fc0bac 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -997,6 +997,8 @@ patternProperties: description: MYIR Tech Limited "^national,.*": description: National Semiconductor + "^neardi,.*": + description: Shanghai Neardi Technology Co., Ltd. "^nec,.*": description: NEC LCD Technologies, Ltd. "^neonode,.*": diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index f42fa62b4064..adfb168759dd 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-ringneck-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-rock-pi-s.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-rock-s0.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a95x-z2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-anbernic-rg351m.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-anbernic-rg351v.dtb @@ -27,6 +28,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lba3368.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lion-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb @@ -90,6 +92,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-powkiddy-x55.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-cm3-io.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-zero-3e.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-zero-3w.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rock-3c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-blade.dtb @@ -118,12 +122,15 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-wifi.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-friendlyelec-cm3588-nas.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-jaguar.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ok3588-c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-plus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-quartzpro64.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtbo +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-turing-rk1.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts index b47fe02c33fb..0b973c1a5ef9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts @@ -15,6 +15,7 @@ ethernet0 = &gmac; mmc0 = &emmc; mmc1 = &sdmmc; + mmc2 = &sdio; }; chosen { @@ -136,11 +137,25 @@ &gmac { clock_in_out = "output"; + phy-handle = <&rtl8201f>; phy-supply = <&vcc_io>; - snps,reset-gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 50000 50000>; status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + rtl8201f: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&mac_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + }; + }; }; &gpio0 { @@ -209,10 +224,40 @@ status = "okay"; }; +&io_domains { + vccio0-supply = <&vcc_io>; + vccio1-supply = <&vcc_io>; + vccio2-supply = <&vcc_io>; + vccio3-supply = <&vcc_io>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_io>; + status = "okay"; +}; + &pinctrl { pinctrl-names = "default"; pinctrl-0 = <&rtc_32k>; + bluetooth { + bt_reg_on: bt-reg-on { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host: bt-wake-host { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + host_wake_bt: host-wake-bt { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gmac { + mac_rst: mac-rst { + rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + leds { green_led_gio: green-led-gpio { rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; @@ -256,15 +301,31 @@ cap-sd-highspeed; cap-sdio-irq; keep-power-in-suspend; - max-frequency = <1000000>; + max-frequency = <100000000>; mmc-pwrseq = <&sdio_pwrseq>; + no-mmc; + no-sd; non-removable; - sd-uhs-sdr104; + sd-uhs-sdr50; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc_1v8>; status = "okay"; + + rtl8723ds: wifi@1 { + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake>; + }; }; &sdmmc { + cap-mmc-highspeed; cap-sd-highspeed; + disable-wp; + vmmc-supply = <&vcc_io>; status = "okay"; }; @@ -283,16 +344,22 @@ }; &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; status = "okay"; }; &uart4 { + uart-has-rtscts; status = "okay"; bluetooth { - compatible = "realtek,rtl8723bs-bt"; - device-wake-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + compatible = "realtek,rtl8723ds-bt"; + device-wake-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; host-wake-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reg_on &bt_wake_host &host_wake_bt>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts b/arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts new file mode 100644 index 000000000000..bd6419a5c20a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-s0.dts @@ -0,0 +1,293 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/leds/common.h> +#include "rk3308.dtsi" + +/ { + model = "Radxa ROCK S0"; + compatible = "radxa,rock-s0", "rockchip,rk3308"; + + aliases { + ethernet0 = &gmac; + mmc0 = &emmc; + mmc1 = &sdmmc; + mmc2 = &sdio; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_led>; + + led-green { + color = <LED_COLOR_ID_GREEN>; + default-state = "on"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + vdd_log: regulator-1v04-vdd-log { + compatible = "regulator-fixed"; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1040000>; + regulator-max-microvolt = <1040000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_ddr: regulator-1v5-vcc-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v8: regulator-1v8-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_io>; + }; + + vcc_io: regulator-3v3-vcc-io { + compatible = "regulator-fixed"; + regulator-name = "vcc_io"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: regulator-5v0-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vdd_core: regulator-vdd-core { + compatible = "pwm-regulator"; + pwms = <&pwm0 0 5000 1>; + pwm-supply = <&vcc5v0_sys>; + regulator-name = "vdd_core"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <827000>; + regulator-max-microvolt = <1340000>; + regulator-settling-time-up-us = <250>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on>; + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_core>; +}; + +&emmc { + cap-mmc-highspeed; + no-sd; + no-sdio; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_pwren>; + vmmc-supply = <&vcc_io>; + status = "okay"; +}; + +&gmac { + clock_in_out = "output"; + phy-handle = <&rtl8201f>; + phy-supply = <&vcc_io>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + rtl8201f: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&mac_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&io_domains { + vccio0-supply = <&vcc_io>; + vccio1-supply = <&vcc_io>; + vccio2-supply = <&vcc_io>; + vccio3-supply = <&vcc_io>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_io>; + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&rtc_32k>; + + bluetooth { + bt_reg_on: bt-reg-on { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host: bt-wake-host { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + host_wake_bt: host-wake-bt { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gmac { + mac_rst: mac-rst { + rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + pwr_led: pwr-led { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_reg_on: wifi-reg-on { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_wake_host: wifi-wake-host { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin_pull_down>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdio { + #address-cells = <1>; + #size-cells = <0>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + max-frequency = <50000000>; + mmc-pwrseq = <&sdio_pwrseq>; + no-mmc; + no-sd; + non-removable; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm43430a1-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_wake_host>; + }; +}; + +&sdmmc { + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + vmmc-supply = <&vcc_io>; + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; + status = "okay"; +}; + +&uart4 { + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43430a1-bt"; + clocks = <&cru SCLK_RTC32K>; + clock-names = "lpo"; + interrupt-parent = <&gpio4>; + interrupts = <RK_PB4 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wakeup"; + device-wakeup-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reg_on &bt_wake_host &host_wake_bt>; + vbat-supply = <&vcc_io>; + vddio-supply = <&vcc_1v8>; + }; +}; + +&usb_host_ehci { + status = "okay"; +}; + +&usb_host_ohci { + status = "okay"; +}; + +&usb20_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi index 962ea893999b..9996e022fef8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi @@ -173,6 +173,11 @@ compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; reg = <0x0 0xff000000 0x0 0x08000>; + io_domains: io-domains { + compatible = "rockchip,rk3308-io-voltage-domain"; + status = "disabled"; + }; + reboot-mode { compatible = "syscon-reboot-mode"; offset = <0x500>; @@ -556,6 +561,30 @@ status = "disabled"; }; + otp: efuse@ff210000 { + compatible = "rockchip,rk3308-otp"; + reg = <0x0 0xff210000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, + <&cru PCLK_OTP_PHY>; + clock-names = "otp", "apb_pclk", "phy"; + resets = <&cru SRST_OTP_PHY>; + reset-names = "phy"; + + cpu_id: id@7 { + reg = <0x07 0x10>; + }; + + cpu_leakage: cpu-leakage@17 { + reg = <0x17 0x1>; + }; + + logic_leakage: logic-leakage@18 { + reg = <0x18 0x1>; + }; + }; + dmac0: dma-controller@ff2c0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xff2c0000 0x0 0x4000>; diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index 07dcc949b899..b01efd6d042c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -850,8 +850,8 @@ <0>, <24000000>, <24000000>, <24000000>, <15000000>, <15000000>, - <100000000>, <100000000>, - <100000000>, <100000000>, + <300000000>, <100000000>, + <400000000>, <100000000>, <50000000>, <100000000>, <100000000>, <100000000>, <50000000>, <50000000>, diff --git a/arch/arm64/boot/dts/rockchip/rk3368-lba3368.dts b/arch/arm64/boot/dts/rockchip/rk3368-lba3368.dts new file mode 100644 index 000000000000..e0cc4da7f392 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3368-lba3368.dts @@ -0,0 +1,659 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/clock/rockchip,rk808.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/sound/rt5640.h> +#include "rk3368.dtsi" + +/ { + model = "Neardi LBA3368"; + compatible = "neardi,lba3368", "rockchip,rk3368"; + + aliases { + ethernet0 = &gmac; + mmc0 = &emmc; + mmc1 = &sdmmc; + mmc2 = &sdio0; + rtc0 = &hym8563; + rtc1 = &rk808; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; + + adc-key { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + button-recovery { + label = "Recovery"; + linux,code = <KEY_VENDOR>; + press-threshold-microvolt = <0>; + }; + }; + + analog-sound { + compatible = "audio-graph-card"; + dais = <&i2s_8ch_p0>; + hp-det-gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + label = "alc5640"; + routing = "Mic Jack", "MICBIAS1", + "IN1P", "Mic Jack", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR", + "Speakers", "SPORP", + "Speakers", "SPORN", + "Speakers", "SPOLP", + "Speakers", "SPOLN"; + widgets = "Microphone", "Mic Jack", + "Headphone", "Headphone Jack", + "Speaker", "Speakers"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + }; + + dc_12v: dc-12v-regulator { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + ext_gmac: gmac-clk { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + clock-output-names = "ext_gmac"; + #clock-cells = <0>; + }; + + hub_avdd: hub-avdd-regulator { + compatible = "regulator-fixed"; + regulator-name = "hub_avdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + regulator-always-on; + }; + + leds { + compatible = "gpio-leds"; + + power-led { + gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_GREEN>; + default-state = "on"; + pinctrl-names = "default"; + pinctrl-0 = <&power_led>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 RK808_CLKOUT1>; + clock-names = "ext_clock"; + reset-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on>; + }; + + vcc_host: vcc-host-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + enable-active-high; + regulator-always-on; + }; + + vcc_lan: vcc-lan-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_lan"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + regulator-always-on; + }; + + vcc_otg: vcc-otg-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + enable-active-high; + regulator-always-on; + }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + regulator-always-on; + regulator-boot-on; + }; + + vdd10_usb: vdd10-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vdd10_usb"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + vin-supply = <&vdd_10>; + regulator-always-on; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu>; +}; + +&emmc { + bus-width = <8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc_18>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + cap-mmc-highspeed; + non-removable; + no-sd; + no-sdio; + mmc-hs200-1_8v; + status = "okay"; +}; + +&gmac { + clock_in_out = "input"; + phy-handle = <&phy>; + phy-mode = "rmii"; + phy-supply = <&vcc_lan>; + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + pinctrl-names = "default"; + pinctrl-0 = <&rmii_pins>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + max-speed = <100>; + reset-assert-us = <10000>; + reset-deassert-us = <1000000>; + reset-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&phy_rst>; + }; + }; +}; + +&io_domains { + audio-supply = <&vcca1v8_codec>; + dvp-supply = <&vcc_18>; + flash0-supply = <&vcc_18>; + gpio1830-supply = <&vcc_io>; + gpio30-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vdd1v8_wl>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupts-extended = <&gpio0 RK_PA5 IRQ_TYPE_LEVEL_LOW>; + clock-output-names = "rk808-clkout1", "xin32k_wifi_bt"; + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_io>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc_io>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int &pmic_sleep>; + system-power-controller; + wakeup-source; + #clock-cells = <1>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log: DCDC_REG2 { + regulator-name = "vdd_log"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-suspend-microvolt = <1000000>; + regulator-on-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-suspend-microvolt = <3300000>; + regulator-on-in-suspend; + }; + }; + + vcca1v8_codec: LDO_REG1 { + regulator-name = "vcca1v8_codec"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca3v0_codec: LDO_REG2 { + regulator-name = "vcca3v0_codec"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-suspend-microvolt = <1000000>; + regulator-on-in-suspend; + }; + }; + + vdd1v8_wl: LDO_REG4 { + regulator-name = "vdd1v8_wl"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd10_lcd: LDO_REG6 { + regulator-name = "vdd10_lcd"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_18: LDO_REG7 { + regulator-name = "vcc_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-suspend-microvolt = <1800000>; + regulator-on-in-suspend; + }; + }; + + vcc18_lcd: LDO_REG8 { + regulator-name = "vcc18_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_tp: SWITCH_REG1 { + regulator-name = "vcc_tp"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_sd: SWITCH_REG2 { + regulator-name = "vcc_sd"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + + codec@1c { + compatible = "realtek,rt5640"; + reg = <0x1c>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + realtek,dmic1-data-pin = <RT5640_DMIC1_DATA_PIN_IN1P>; + realtek,dmic2-data-pin = <RT5640_DMIC2_DATA_PIN_IN1N>; + realtek,in1-differential; + #sound-dai-cells = <0>; + + port { + rt5640_p0_0: endpoint { + remote-endpoint = <&i2s_8ch_p0_0>; + }; + }; + }; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + }; +}; + +&i2s_8ch { + status = "okay"; + + i2s_8ch_p0: port { + i2s_8ch_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&rt5640_p0_0>; + }; + }; +}; + +&pinctrl { + bluetooth { + bt_host_wake: bt-host-wake { + rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reg_on: bt-reg-on { + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + bt_wake: bt-wake { + rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + power_led: power-led { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + phy { + phy_rst: phy-rst { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pmic_sleep: pmic-sleep { + rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_reg_on: wifi-reg-on { + rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sound { + hp_det: hp-det { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_host_wake: wifi-host-wake { + rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmu-supply = <&vcc_io>; + vop-supply = <&vcc_io>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_18>; + status = "okay"; +}; + +&sdio0 { + bus-width = <4>; + mmc-pwrseq = <&sdio_pwrseq>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vdd1v8_wl>; + assigned-clocks = <&cru SCLK_SDIO0>; + assigned-clock-parents = <&cru PLL_CPLL>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + cap-sd-highspeed; + cap-sdio-irq; + no-sd; + no-mmc; + non-removable; + sd-uhs-sdr104; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm43455-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + interrupts-extended = <&gpio3 RK_PA6 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake>; + }; +}; + +&sdmmc { + bus-width = <4>; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4 &sdmmc_cd>; + cap-sd-highspeed; + disable-wp; + no-mmc; + no-sdio; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4345c5"; + interrupts-extended = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + interrupt-names = "host-wakeup"; + clocks = <&rk808 RK808_CLKOUT1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + max-speed = <15000000>; + vbat-supply = <&vcc_io>; + vddio-supply = <&vdd1v8_wl>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake &bt_wake &bt_reg_on>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_xfer>; + status = "okay"; +}; + +&usb_host0_ehci { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + hub@1 { + compatible = "usb5e3,610"; + reg = <1>; + vdd-supply = <&hub_avdd>; + }; +}; + +&usb_otg { + vbus-supply = <&vcc_otg>; + vusb_a-supply = <&vcc_io>; + vusb_d-supply = <&vdd10_usb>; + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts index e5709c7ee06a..ef754ea30a94 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts @@ -12,6 +12,7 @@ /dts-v1/; #include <dt-bindings/input/gpio-keys.h> #include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/leds/common.h> #include "rk3399.dtsi" #include "rk3399-opp.dtsi" @@ -69,6 +70,34 @@ }; }; + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&red_led_pin &green_led_pin &blue_led_pin>; + + led_red: led-0 { + color = <LED_COLOR_ID_RED>; + gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + }; + + led_green: led-1 { + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>; + }; + + led_blue: led-2 { + color = <LED_COLOR_ID_BLUE>; + gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>; + }; + }; + + multi-led { + compatible = "leds-group-multicolor"; + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_INDICATOR; + leds = <&led_red>, <&led_green>, <&led_blue>; + }; + vcc_sys: vcc-sys-regulator { compatible = "regulator-fixed"; regulator-name = "vcc_sys"; @@ -152,6 +181,12 @@ gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; }; + + vibrator { + compatible = "gpio-vibrator"; + enable-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; + vcc-supply = <&vcc3v3_sys>; + }; }; &cpu_alert0 { @@ -407,6 +442,21 @@ }; }; +&i2c4 { + i2c-scl-rising-time-ns = <600>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + + /* Accelerometer/gyroscope */ + mpu6500@68 { + compatible = "invensense,mpu6500"; + reg = <0x68>; + interrupt-parent = <&gpio1>; + interrupts = <RK_PC6 IRQ_TYPE_LEVEL_LOW>; + vddio-supply = <&vcc_1v8>; + }; +}; + &cluster0_opp { opp04 { status = "disabled"; @@ -481,6 +531,20 @@ }; }; + leds { + red_led_pin: red-led-pin { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + green_led_pin: green-led-pin { + rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + blue_led_pin: blue-led-pin { + rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { pmic_int_l: pmic-int-l { rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; @@ -565,6 +629,16 @@ status = "okay"; }; +&spi1 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + }; +}; + &tsadc { rockchip,hw-tshut-mode = <1>; rockchip,hw-tshut-polarity = <1>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi deleted file mode 100644 index bb5ebf6608b9..000000000000 --- a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. - -#include "rk3399.dtsi" - -/ { - compatible = "rockchip,rk3399pro"; -}; - -/* Default to enabled since AP talk to NPU part over pcie */ -&pcie_phy { - status = "okay"; -}; - -/* Default to enabled since AP talk to NPU part over pcie */ -&pcie0 { - ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_clkreqn_cpm>; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi new file mode 100644 index 000000000000..9cc7aa3298d0 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi @@ -0,0 +1,531 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include "rk3566.dtsi" + +/ { + chosen { + stdout-path = "serial2:1500000n8"; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "d"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&user_led2>; + + led-green { + color = <LED_COLOR_ID_GREEN>; + default-state = "on"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + vcc_1v8: regulator-1v8-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_p>; + }; + + vcca_1v8: regulator-1v8-vcca { + compatible = "regulator-fixed"; + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_p>; + }; + + vcca1v8_image: regulator-1v8-vcca-image { + compatible = "regulator-fixed"; + regulator-name = "vcca1v8_image"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_p>; + }; + + vcc_3v3: regulator-3v3-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc_sys: regulator-5v0-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&combphy1 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gpio0 { + gpio-line-names = + /* GPIO0_A0 - A7 */ + "", "", "", "", "", "", "", "", + /* GPIO0_B0 - B7 */ + "", "", "", "", "", "", "", "", + /* GPIO0_C0 - C7 */ + "", "", "", "", "", "", "", "", + /* GPIO0_D0 - D7 */ + "pin-10 [GPIO0_D0]", "pin-08 [GPIO0_D1]", "", + "", "", "", "", ""; +}; + +&gpio1 { + gpio-line-names = + /* GPIO1_A0 - A7 */ + "pin-03 [GPIO1_A0]", "pin-05 [GPIO1_A1]", "", + "", "pin-37 [GPIO1_A4]", "", + "", "", + /* GPIO1_B0 - B7 */ + "", "", "", "", "", "", "", "", + /* GPIO1_C0 - C7 */ + "", "", "", "", "", "", "", "", + /* GPIO1_D0 - D7 */ + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + /* GPIO2_A0 - A7 */ + "", "", "", "", "", "", "", "", + /* GPIO2_B0 - B7 */ + "", "", "", "", "", "", "", "", + /* GPIO2_C0 - C7 */ + "", "", "", "", "", "", "", "", + /* GPIO2_D0 - D7 */ + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + /* GPIO3_A0 - A7 */ + "", "pin-11 [GPIO3_A1]", "pin-13 [GPIO3_A2]", + "pin-12 [GPIO3_A3]", "pin-35 [GPIO3_A4]", "pin-40 [GPIO3_A5]", + "pin-38 [GPIO3_A6]", "pin-36 [GPIO3_A7]", + /* GPIO3_B0 - B7 */ + "pin-15 [GPIO3_B0]", "pin-16 [GPIO3_B1]", "pin-18 [GPIO3_B2]", + "pin-29 [GPIO3_B3]", "pin-31 [GPIO3_B4]", "", + "", "", + /* GPIO3_C0 - C7 */ + "", "pin-22 [GPIO3_C1]", "pin-32 [GPIO3_C2]", + "pin-33 [GPIO3_C3]", "pin-07 [GPIO3_C4]", "", + "", "", + /* GPIO3_D0 - D7 */ + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + /* GPIO4_A0 - A7 */ + "", "", "", "", "", "", "", "", + /* GPIO4_B0 - B7 */ + "", "", "pin-27 [GPIO4_B2]", + "pin-28 [GPIO4_B3]", "", "", "", "", + /* GPIO4_C0 - C7 */ + "", "", "pin-23 [GPIO4_C2]", + "pin-19 [GPIO4_C3]", "", "pin-21 [GPIO4_C5]", + "pin-24 [GPIO4_C6]", "", + /* GPIO4_D0 - D7 */ + "", "", "", "", "", "", "", ""; +}; + +&gpu { + mali-supply = <&vdd_gpu_npu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda_0v9>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + #clock-cells = <1>; + clock-output-names = "rk817-clkout1", "rk817-clkout2"; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&vcc5v_midu>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_gpu_npu: DCDC_REG2 { + regulator-name = "vdd_gpu_npu"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_sys: DCDC_REG4 { + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca1v8_pmu: LDO_REG1 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v8_p: LDO_REG7 { + regulator-name = "vcc_1v8_p"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-name = "vcc1v8_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG9 { + regulator-name = "vcc2v8_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc5v_midu: BOOST { + regulator-name = "vcc5v_midu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vbus: OTG_SWITCH { + regulator-name = "vbus"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu: regulator@40 { + compatible = "rockchip,rk8600"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&pinctrl { + leds { + user_led2: user-led2 { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcca1v8_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + status = "okay"; +}; + +&usb2phy0_otg { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts new file mode 100644 index 000000000000..4a830eb09f0b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-radxa-zero-3.dtsi" + +/ { + model = "Radxa ZERO 3E"; + compatible = "radxa,zero-3e", "rockchip,rk3566"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdmmc0; + }; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + clock_in_out = "input"; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus + &gmac1m1_clkinout>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_rstn>; + reset-assert-us = <20000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + gmac1 { + gmac1_rstn: gmac1-rstn { + rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts new file mode 100644 index 000000000000..f92475c59deb --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-radxa-zero-3.dtsi" + +/ { + model = "Radxa ZERO 3W"; + compatible = "radxa,zero-3w", "rockchip,rk3566"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc0; + mmc2 = &sdmmc1; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h>; + post-power-on-delay-ms = <100>; + power-off-delay-us = <5000000>; + reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + bluetooth { + bt_reg_on_h: bt-reg-on-h { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host_h: bt-wake-host-h { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + host_wake_bt_h: host-wake-bt-h { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_reg_on_h: wifi-reg-on-h { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_wake_host_h: wifi-wake-host-h { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <200000000>; + mmc-hs200-1_8v; + no-sd; + no-sdio; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + no-mmc; + no-sd; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + uart-has-rtscts; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts index 63eea27293fe..67e7801bd489 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts @@ -269,7 +269,7 @@ vcc9-supply = <&vcc3v3_sys>; codec { - mic-in-differential; + rockchip,mic-in-differential; }; regulators { diff --git a/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts b/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts index b242409d378c..f2cc086e5001 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts @@ -633,7 +633,7 @@ flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; - spi-max-frequency = <120000000>; + spi-max-frequency = <104000000>; spi-rx-bus-width = <4>; spi-tx-bus-width = <1>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts index 19f8fc369b13..8c3ab07d3807 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts @@ -475,7 +475,7 @@ }; codec { - mic-in-differential; + rockchip,mic-in-differential; }; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts index ebdedea15ad1..59f1403b4fa5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts @@ -531,10 +531,6 @@ }; }; }; - - codec { - mic-in-differential; - }; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts index 98c622b27647..c667704ba985 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts @@ -673,6 +673,10 @@ }; }; +&tsadc { + status = "okay"; +}; + &u2phy0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi index 30db12c4fc82..30db12c4fc82 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi new file mode 100644 index 000000000000..b6e4df180f0b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -0,0 +1,2799 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include <dt-bindings/clock/rockchip,rk3588-cru.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/power/rk3588-power.h> +#include <dt-bindings/reset/rockchip,rk3588-cru.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/ata/ahci.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + compatible = "rockchip,rk3588"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; + serial7 = &uart7; + serial8 = &uart8; + serial9 = &uart9; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + spi4 = &spi4; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu_l0>; + }; + core1 { + cpu = <&cpu_l1>; + }; + core2 { + cpu = <&cpu_l2>; + }; + core3 { + cpu = <&cpu_l3>; + }; + }; + cluster1 { + core0 { + cpu = <&cpu_b0>; + }; + core1 { + cpu = <&cpu_b1>; + }; + }; + cluster2 { + core0 { + cpu = <&cpu_b2>; + }; + core1 { + cpu = <&cpu_b3>; + }; + }; + }; + + cpu_l0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <530>; + clocks = <&scmi_clk SCMI_CLK_CPUL>; + assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; + assigned-clock-rates = <816000000>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l0>; + dynamic-power-coefficient = <228>; + #cooling-cells = <2>; + }; + + cpu_l1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <530>; + clocks = <&scmi_clk SCMI_CLK_CPUL>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l1>; + dynamic-power-coefficient = <228>; + #cooling-cells = <2>; + }; + + cpu_l2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + capacity-dmips-mhz = <530>; + clocks = <&scmi_clk SCMI_CLK_CPUL>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l2>; + dynamic-power-coefficient = <228>; + #cooling-cells = <2>; + }; + + cpu_l3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + capacity-dmips-mhz = <530>; + clocks = <&scmi_clk SCMI_CLK_CPUL>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l3>; + dynamic-power-coefficient = <228>; + #cooling-cells = <2>; + }; + + cpu_b0: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x400>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + clocks = <&scmi_clk SCMI_CLK_CPUB01>; + assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; + assigned-clock-rates = <816000000>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_b0>; + dynamic-power-coefficient = <416>; + #cooling-cells = <2>; + }; + + cpu_b1: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x500>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + clocks = <&scmi_clk SCMI_CLK_CPUB01>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_b1>; + dynamic-power-coefficient = <416>; + #cooling-cells = <2>; + }; + + cpu_b2: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x600>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + clocks = <&scmi_clk SCMI_CLK_CPUB23>; + assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; + assigned-clock-rates = <816000000>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_b2>; + dynamic-power-coefficient = <416>; + #cooling-cells = <2>; + }; + + cpu_b3: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x700>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + clocks = <&scmi_clk SCMI_CLK_CPUB23>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_b3>; + dynamic-power-coefficient = <416>; + #cooling-cells = <2>; + }; + + idle-states { + entry-method = "psci"; + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <100>; + exit-latency-us = <120>; + min-residency-us = <1000>; + }; + }; + + l2_cache_l0: l2-cache-l0 { + compatible = "cache"; + cache-size = <131072>; + cache-line-size = <64>; + cache-sets = <512>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l1: l2-cache-l1 { + compatible = "cache"; + cache-size = <131072>; + cache-line-size = <64>; + cache-sets = <512>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l2: l2-cache-l2 { + compatible = "cache"; + cache-size = <131072>; + cache-line-size = <64>; + cache-sets = <512>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l3: l2-cache-l3 { + compatible = "cache"; + cache-size = <131072>; + cache-line-size = <64>; + cache-sets = <512>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_b0: l2-cache-b0 { + compatible = "cache"; + cache-size = <524288>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_b1: l2-cache-b1 { + compatible = "cache"; + cache-size = <524288>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_b2: l2-cache-b2 { + compatible = "cache"; + cache-size = <524288>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_b3: l2-cache-b3 { + compatible = "cache"; + cache-size = <524288>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l3_cache: l3-cache { + compatible = "cache"; + cache-size = <3145728>; + cache-line-size = <64>; + cache-sets = <4096>; + cache-level = <3>; + cache-unified; + }; + }; + + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + }; + + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + scmi: scmi { + compatible = "arm,scmi-smc"; + arm,smc-id = <0x82000010>; + shmem = <&scmi_shmem>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + }; + + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>; + }; + + pmu-a76 { + compatible = "arm,cortex-a76-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + spll: clock-0 { + compatible = "fixed-clock"; + clock-frequency = <702000000>; + clock-output-names = "spll"; + #clock-cells = <0>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; + }; + + xin24m: clock-1 { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + xin32k: clock-2 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + }; + + pmu_sram: sram@10f000 { + compatible = "mmio-sram"; + reg = <0x0 0x0010f000 0x0 0x100>; + ranges = <0 0x0 0x0010f000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + + scmi_shmem: sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x100>; + }; + }; + + gpu: gpu@fb000000 { + compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; + reg = <0x0 0xfb000000 0x0 0x200000>; + #cooling-cells = <2>; + assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; + assigned-clock-rates = <200000000>; + clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, + <&cru CLK_GPU_STACKS>; + clock-names = "core", "coregroup", "stacks"; + dynamic-power-coefficient = <2982>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "job", "mmu", "gpu"; + power-domains = <&power RK3588_PD_GPU>; + status = "disabled"; + }; + + usb_host0_xhci: usb@fc000000 { + compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; + reg = <0x0 0xfc000000 0x0 0x400000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, + <&cru ACLK_USB3OTG0>; + clock-names = "ref_clk", "suspend_clk", "bus_clk"; + dr_mode = "otg"; + phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + power-domains = <&power RK3588_PD_USB>; + resets = <&cru SRST_A_USB3OTG0>; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + status = "disabled"; + }; + + usb_host0_ehci: usb@fc800000 { + compatible = "rockchip,rk3588-ehci", "generic-ehci"; + reg = <0x0 0xfc800000 0x0 0x40000>; + interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; + phys = <&u2phy2_host>; + phy-names = "usb"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host0_ohci: usb@fc840000 { + compatible = "rockchip,rk3588-ohci", "generic-ohci"; + reg = <0x0 0xfc840000 0x0 0x40000>; + interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; + phys = <&u2phy2_host>; + phy-names = "usb"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host1_ehci: usb@fc880000 { + compatible = "rockchip,rk3588-ehci", "generic-ehci"; + reg = <0x0 0xfc880000 0x0 0x40000>; + interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; + phys = <&u2phy3_host>; + phy-names = "usb"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host1_ohci: usb@fc8c0000 { + compatible = "rockchip,rk3588-ohci", "generic-ohci"; + reg = <0x0 0xfc8c0000 0x0 0x40000>; + interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; + phys = <&u2phy3_host>; + phy-names = "usb"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host2_xhci: usb@fcd00000 { + compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; + reg = <0x0 0xfcd00000 0x0 0x400000>; + interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, + <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, + <&cru CLK_PIPEPHY2_PIPE_U3_G>; + clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe"; + dr_mode = "host"; + phys = <&combphy2_psu PHY_TYPE_USB3>; + phy-names = "usb3-phy"; + phy_type = "utmi_wide"; + resets = <&cru SRST_A_USB3OTG2>; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis_rxdet_inp3_quirk; + status = "disabled"; + }; + + mmu600_pcie: iommu@fc900000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0xfc900000 0x0 0x200000>; + interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; + #iommu-cells = <1>; + status = "disabled"; + }; + + mmu600_php: iommu@fcb00000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0xfcb00000 0x0 0x200000>; + interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; + #iommu-cells = <1>; + status = "disabled"; + }; + + pmu1grf: syscon@fd58a000 { + compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; + reg = <0x0 0xfd58a000 0x0 0x10000>; + }; + + sys_grf: syscon@fd58c000 { + compatible = "rockchip,rk3588-sys-grf", "syscon"; + reg = <0x0 0xfd58c000 0x0 0x1000>; + }; + + vop_grf: syscon@fd5a4000 { + compatible = "rockchip,rk3588-vop-grf", "syscon"; + reg = <0x0 0xfd5a4000 0x0 0x2000>; + }; + + vo0_grf: syscon@fd5a6000 { + compatible = "rockchip,rk3588-vo-grf", "syscon"; + reg = <0x0 0xfd5a6000 0x0 0x2000>; + clocks = <&cru PCLK_VO0GRF>; + }; + + vo1_grf: syscon@fd5a8000 { + compatible = "rockchip,rk3588-vo-grf", "syscon"; + reg = <0x0 0xfd5a8000 0x0 0x100>; + clocks = <&cru PCLK_VO1GRF>; + }; + + usb_grf: syscon@fd5ac000 { + compatible = "rockchip,rk3588-usb-grf", "syscon"; + reg = <0x0 0xfd5ac000 0x0 0x4000>; + }; + + php_grf: syscon@fd5b0000 { + compatible = "rockchip,rk3588-php-grf", "syscon"; + reg = <0x0 0xfd5b0000 0x0 0x1000>; + }; + + pipe_phy0_grf: syscon@fd5bc000 { + compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5bc000 0x0 0x100>; + }; + + pipe_phy2_grf: syscon@fd5c4000 { + compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5c4000 0x0 0x100>; + }; + + usbdpphy0_grf: syscon@fd5c8000 { + compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; + reg = <0x0 0xfd5c8000 0x0 0x4000>; + }; + + usb2phy0_grf: syscon@fd5d0000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd5d0000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy0: usb2phy@0 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x0 0x10>; + #clock-cells = <0>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy0"; + interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>; + resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; + reset-names = "phy", "apb"; + status = "disabled"; + + u2phy0_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + usb2phy2_grf: syscon@fd5d8000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd5d8000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy2: usb2phy@8000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x8000 0x10>; + #clock-cells = <0>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy2"; + interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>; + resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; + reset-names = "phy", "apb"; + status = "disabled"; + + u2phy2_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + usb2phy3_grf: syscon@fd5dc000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd5dc000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy3: usb2phy@c000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0xc000 0x10>; + #clock-cells = <0>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy3"; + interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>; + resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; + reset-names = "phy", "apb"; + status = "disabled"; + + u2phy3_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + hdptxphy0_grf: syscon@fd5e0000 { + compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; + reg = <0x0 0xfd5e0000 0x0 0x100>; + }; + + ioc: syscon@fd5f0000 { + compatible = "rockchip,rk3588-ioc", "syscon"; + reg = <0x0 0xfd5f0000 0x0 0x10000>; + }; + + system_sram1: sram@fd600000 { + compatible = "mmio-sram"; + reg = <0x0 0xfd600000 0x0 0x100000>; + ranges = <0x0 0x0 0xfd600000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + cru: clock-controller@fd7c0000 { + compatible = "rockchip,rk3588-cru"; + reg = <0x0 0xfd7c0000 0x0 0x5c000>; + assigned-clocks = + <&cru PLL_PPLL>, <&cru PLL_AUPLL>, + <&cru PLL_NPLL>, <&cru PLL_GPLL>, + <&cru ACLK_CENTER_ROOT>, + <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, + <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, + <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, + <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>, + <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, + <&cru CLK_GPU>; + assigned-clock-rates = + <1100000000>, <786432000>, + <850000000>, <1188000000>, + <702000000>, + <400000000>, <500000000>, + <800000000>, <100000000>, + <400000000>, <100000000>, + <200000000>, <500000000>, + <375000000>, <150000000>, + <200000000>; + rockchip,grf = <&php_grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + i2c0: i2c@fd880000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfd880000 0x0 0x1000>; + interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c0m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart0: serial@fd890000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfd890000 0x0 0x100>; + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 6>, <&dmac0 7>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart0m1_xfer>; + pinctrl-names = "default"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + pwm0: pwm@fd8b0000 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfd8b0000 0x0 0x10>; + clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm0m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1: pwm@fd8b0010 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfd8b0010 0x0 0x10>; + clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm1m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm2: pwm@fd8b0020 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfd8b0020 0x0 0x10>; + clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm2m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3: pwm@fd8b0030 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfd8b0030 0x0 0x10>; + clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm3m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pmu: power-management@fd8d8000 { + compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; + reg = <0x0 0xfd8d8000 0x0 0x400>; + + power: power-controller { + compatible = "rockchip,rk3588-power-controller"; + #address-cells = <1>; + #power-domain-cells = <1>; + #size-cells = <0>; + status = "okay"; + + /* These power domains are grouped by VD_NPU */ + power-domain@RK3588_PD_NPU { + reg = <RK3588_PD_NPU>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3588_PD_NPUTOP { + reg = <RK3588_PD_NPUTOP>; + clocks = <&cru HCLK_NPU_ROOT>, + <&cru PCLK_NPU_ROOT>, + <&cru CLK_NPU_DSU0>, + <&cru HCLK_NPU_CM0_ROOT>; + pm_qos = <&qos_npu0_mwr>, + <&qos_npu0_mro>, + <&qos_mcu_npu>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3588_PD_NPU1 { + reg = <RK3588_PD_NPU1>; + clocks = <&cru HCLK_NPU_ROOT>, + <&cru PCLK_NPU_ROOT>, + <&cru CLK_NPU_DSU0>; + pm_qos = <&qos_npu1>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_NPU2 { + reg = <RK3588_PD_NPU2>; + clocks = <&cru HCLK_NPU_ROOT>, + <&cru PCLK_NPU_ROOT>, + <&cru CLK_NPU_DSU0>; + pm_qos = <&qos_npu2>; + #power-domain-cells = <0>; + }; + }; + }; + /* These power domains are grouped by VD_GPU */ + power-domain@RK3588_PD_GPU { + reg = <RK3588_PD_GPU>; + clocks = <&cru CLK_GPU>, + <&cru CLK_GPU_COREGROUP>, + <&cru CLK_GPU_STACKS>; + pm_qos = <&qos_gpu_m0>, + <&qos_gpu_m1>, + <&qos_gpu_m2>, + <&qos_gpu_m3>; + #power-domain-cells = <0>; + }; + /* These power domains are grouped by VD_VCODEC */ + power-domain@RK3588_PD_VCODEC { + reg = <RK3588_PD_VCODEC>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + power-domain@RK3588_PD_RKVDEC0 { + reg = <RK3588_PD_RKVDEC0>; + clocks = <&cru HCLK_RKVDEC0>, + <&cru HCLK_VDPU_ROOT>, + <&cru ACLK_VDPU_ROOT>, + <&cru ACLK_RKVDEC0>, + <&cru ACLK_RKVDEC_CCU>; + pm_qos = <&qos_rkvdec0>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_RKVDEC1 { + reg = <RK3588_PD_RKVDEC1>; + clocks = <&cru HCLK_RKVDEC1>, + <&cru HCLK_VDPU_ROOT>, + <&cru ACLK_VDPU_ROOT>, + <&cru ACLK_RKVDEC1>; + pm_qos = <&qos_rkvdec1>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_VENC0 { + reg = <RK3588_PD_VENC0>; + clocks = <&cru HCLK_RKVENC0>, + <&cru ACLK_RKVENC0>; + pm_qos = <&qos_rkvenc0_m0ro>, + <&qos_rkvenc0_m1ro>, + <&qos_rkvenc0_m2wo>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + power-domain@RK3588_PD_VENC1 { + reg = <RK3588_PD_VENC1>; + clocks = <&cru HCLK_RKVENC1>, + <&cru HCLK_RKVENC0>, + <&cru ACLK_RKVENC0>, + <&cru ACLK_RKVENC1>; + pm_qos = <&qos_rkvenc1_m0ro>, + <&qos_rkvenc1_m1ro>, + <&qos_rkvenc1_m2wo>; + #power-domain-cells = <0>; + }; + }; + }; + /* These power domains are grouped by VD_LOGIC */ + power-domain@RK3588_PD_VDPU { + reg = <RK3588_PD_VDPU>; + clocks = <&cru HCLK_VDPU_ROOT>, + <&cru ACLK_VDPU_LOW_ROOT>, + <&cru ACLK_VDPU_ROOT>, + <&cru ACLK_JPEG_DECODER_ROOT>, + <&cru ACLK_IEP2P0>, + <&cru HCLK_IEP2P0>, + <&cru ACLK_JPEG_ENCODER0>, + <&cru HCLK_JPEG_ENCODER0>, + <&cru ACLK_JPEG_ENCODER1>, + <&cru HCLK_JPEG_ENCODER1>, + <&cru ACLK_JPEG_ENCODER2>, + <&cru HCLK_JPEG_ENCODER2>, + <&cru ACLK_JPEG_ENCODER3>, + <&cru HCLK_JPEG_ENCODER3>, + <&cru ACLK_JPEG_DECODER>, + <&cru HCLK_JPEG_DECODER>, + <&cru ACLK_RGA2>, + <&cru HCLK_RGA2>; + pm_qos = <&qos_iep>, + <&qos_jpeg_dec>, + <&qos_jpeg_enc0>, + <&qos_jpeg_enc1>, + <&qos_jpeg_enc2>, + <&qos_jpeg_enc3>, + <&qos_rga2_mro>, + <&qos_rga2_mwo>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + + power-domain@RK3588_PD_AV1 { + reg = <RK3588_PD_AV1>; + clocks = <&cru PCLK_AV1>, + <&cru ACLK_AV1>, + <&cru HCLK_VDPU_ROOT>; + pm_qos = <&qos_av1>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_RKVDEC0 { + reg = <RK3588_PD_RKVDEC0>; + clocks = <&cru HCLK_RKVDEC0>, + <&cru HCLK_VDPU_ROOT>, + <&cru ACLK_VDPU_ROOT>, + <&cru ACLK_RKVDEC0>; + pm_qos = <&qos_rkvdec0>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_RKVDEC1 { + reg = <RK3588_PD_RKVDEC1>; + clocks = <&cru HCLK_RKVDEC1>, + <&cru HCLK_VDPU_ROOT>, + <&cru ACLK_VDPU_ROOT>; + pm_qos = <&qos_rkvdec1>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_RGA30 { + reg = <RK3588_PD_RGA30>; + clocks = <&cru ACLK_RGA3_0>, + <&cru HCLK_RGA3_0>; + pm_qos = <&qos_rga3_0>; + #power-domain-cells = <0>; + }; + }; + power-domain@RK3588_PD_VOP { + reg = <RK3588_PD_VOP>; + clocks = <&cru PCLK_VOP_ROOT>, + <&cru HCLK_VOP_ROOT>, + <&cru ACLK_VOP>; + pm_qos = <&qos_vop_m0>, + <&qos_vop_m1>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + power-domain@RK3588_PD_VO0 { + reg = <RK3588_PD_VO0>; + clocks = <&cru PCLK_VO0_ROOT>, + <&cru PCLK_VO0_S_ROOT>, + <&cru HCLK_VO0_S_ROOT>, + <&cru ACLK_VO0_ROOT>, + <&cru HCLK_HDCP0>, + <&cru ACLK_HDCP0>, + <&cru HCLK_VOP_ROOT>; + pm_qos = <&qos_hdcp0>; + #power-domain-cells = <0>; + }; + }; + power-domain@RK3588_PD_VO1 { + reg = <RK3588_PD_VO1>; + clocks = <&cru PCLK_VO1_ROOT>, + <&cru PCLK_VO1_S_ROOT>, + <&cru HCLK_VO1_S_ROOT>, + <&cru HCLK_HDCP1>, + <&cru ACLK_HDCP1>, + <&cru ACLK_HDMIRX_ROOT>, + <&cru HCLK_VO1USB_TOP_ROOT>; + pm_qos = <&qos_hdcp1>, + <&qos_hdmirx>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_VI { + reg = <RK3588_PD_VI>; + clocks = <&cru HCLK_VI_ROOT>, + <&cru PCLK_VI_ROOT>, + <&cru HCLK_ISP0>, + <&cru ACLK_ISP0>, + <&cru HCLK_VICAP>, + <&cru ACLK_VICAP>; + pm_qos = <&qos_isp0_mro>, + <&qos_isp0_mwo>, + <&qos_vicap_m0>, + <&qos_vicap_m1>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + power-domain@RK3588_PD_ISP1 { + reg = <RK3588_PD_ISP1>; + clocks = <&cru HCLK_ISP1>, + <&cru ACLK_ISP1>, + <&cru HCLK_VI_ROOT>, + <&cru PCLK_VI_ROOT>; + pm_qos = <&qos_isp1_mwo>, + <&qos_isp1_mro>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_FEC { + reg = <RK3588_PD_FEC>; + clocks = <&cru HCLK_FISHEYE0>, + <&cru ACLK_FISHEYE0>, + <&cru HCLK_FISHEYE1>, + <&cru ACLK_FISHEYE1>, + <&cru PCLK_VI_ROOT>; + pm_qos = <&qos_fisheye0>, + <&qos_fisheye1>; + #power-domain-cells = <0>; + }; + }; + power-domain@RK3588_PD_RGA31 { + reg = <RK3588_PD_RGA31>; + clocks = <&cru HCLK_RGA3_1>, + <&cru ACLK_RGA3_1>; + pm_qos = <&qos_rga3_1>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_USB { + reg = <RK3588_PD_USB>; + clocks = <&cru PCLK_PHP_ROOT>, + <&cru ACLK_USB_ROOT>, + <&cru ACLK_USB>, + <&cru HCLK_USB_ROOT>, + <&cru HCLK_HOST0>, + <&cru HCLK_HOST_ARB0>, + <&cru HCLK_HOST1>, + <&cru HCLK_HOST_ARB1>; + pm_qos = <&qos_usb3_0>, + <&qos_usb3_1>, + <&qos_usb2host_0>, + <&qos_usb2host_1>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_GMAC { + reg = <RK3588_PD_GMAC>; + clocks = <&cru PCLK_PHP_ROOT>, + <&cru ACLK_PCIE_ROOT>, + <&cru ACLK_PHP_ROOT>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_PCIE { + reg = <RK3588_PD_PCIE>; + clocks = <&cru PCLK_PHP_ROOT>, + <&cru ACLK_PCIE_ROOT>, + <&cru ACLK_PHP_ROOT>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_SDIO { + reg = <RK3588_PD_SDIO>; + clocks = <&cru HCLK_SDIO>, + <&cru HCLK_NVM_ROOT>; + pm_qos = <&qos_sdio>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_AUDIO { + reg = <RK3588_PD_AUDIO>; + clocks = <&cru HCLK_AUDIO_ROOT>, + <&cru PCLK_AUDIO_ROOT>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_SDMMC { + reg = <RK3588_PD_SDMMC>; + pm_qos = <&qos_sdmmc>; + #power-domain-cells = <0>; + }; + }; + }; + + av1d: video-codec@fdc70000 { + compatible = "rockchip,rk3588-av1-vpu"; + reg = <0x0 0xfdc70000 0x0 0x800>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "vdpu"; + assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; + assigned-clock-rates = <400000000>, <400000000>; + clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; + clock-names = "aclk", "hclk"; + power-domains = <&power RK3588_PD_AV1>; + resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; + }; + + vop: vop@fdd90000 { + compatible = "rockchip,rk3588-vop"; + reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; + reg-names = "vop", "gamma-lut"; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_VOP>, + <&cru HCLK_VOP>, + <&cru DCLK_VOP0>, + <&cru DCLK_VOP1>, + <&cru DCLK_VOP2>, + <&cru DCLK_VOP3>, + <&cru PCLK_VOP_ROOT>; + clock-names = "aclk", + "hclk", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2", + "dclk_vp3", + "pclk_vop"; + iommus = <&vop_mmu>; + power-domains = <&power RK3588_PD_VOP>; + rockchip,grf = <&sys_grf>; + rockchip,vop-grf = <&vop_grf>; + rockchip,vo1-grf = <&vo1_grf>; + rockchip,pmu = <&pmu>; + status = "disabled"; + + vop_out: ports { + #address-cells = <1>; + #size-cells = <0>; + + vp0: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + vp1: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + vp2: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + vp3: port@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + }; + + vop_mmu: iommu@fdd97e00 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_VOP>; + status = "disabled"; + }; + + i2s4_8ch: i2s@fddc0000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddc0000 0x0 0x1000>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 0>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO0>; + resets = <&cru SRST_M_I2S4_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s5_8ch: i2s@fddf0000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf0000 0x0 0x1000>; + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 2>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S5_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s9_8ch: i2s@fddfc000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddfc000 0x0 0x1000>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 23>; + dma-names = "rx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S9_8CH_RX>; + reset-names = "rx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + qos_gpu_m0: qos@fdf35000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf35000 0x0 0x20>; + }; + + qos_gpu_m1: qos@fdf35200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf35200 0x0 0x20>; + }; + + qos_gpu_m2: qos@fdf35400 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf35400 0x0 0x20>; + }; + + qos_gpu_m3: qos@fdf35600 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf35600 0x0 0x20>; + }; + + qos_rga3_1: qos@fdf36000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf36000 0x0 0x20>; + }; + + qos_sdio: qos@fdf39000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf39000 0x0 0x20>; + }; + + qos_sdmmc: qos@fdf3d800 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf3d800 0x0 0x20>; + }; + + qos_usb3_1: qos@fdf3e000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf3e000 0x0 0x20>; + }; + + qos_usb3_0: qos@fdf3e200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf3e200 0x0 0x20>; + }; + + qos_usb2host_0: qos@fdf3e400 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf3e400 0x0 0x20>; + }; + + qos_usb2host_1: qos@fdf3e600 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf3e600 0x0 0x20>; + }; + + qos_fisheye0: qos@fdf40000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf40000 0x0 0x20>; + }; + + qos_fisheye1: qos@fdf40200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf40200 0x0 0x20>; + }; + + qos_isp0_mro: qos@fdf40400 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf40400 0x0 0x20>; + }; + + qos_isp0_mwo: qos@fdf40500 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf40500 0x0 0x20>; + }; + + qos_vicap_m0: qos@fdf40600 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf40600 0x0 0x20>; + }; + + qos_vicap_m1: qos@fdf40800 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf40800 0x0 0x20>; + }; + + qos_isp1_mwo: qos@fdf41000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf41000 0x0 0x20>; + }; + + qos_isp1_mro: qos@fdf41100 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf41100 0x0 0x20>; + }; + + qos_rkvenc0_m0ro: qos@fdf60000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf60000 0x0 0x20>; + }; + + qos_rkvenc0_m1ro: qos@fdf60200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf60200 0x0 0x20>; + }; + + qos_rkvenc0_m2wo: qos@fdf60400 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf60400 0x0 0x20>; + }; + + qos_rkvenc1_m0ro: qos@fdf61000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf61000 0x0 0x20>; + }; + + qos_rkvenc1_m1ro: qos@fdf61200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf61200 0x0 0x20>; + }; + + qos_rkvenc1_m2wo: qos@fdf61400 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf61400 0x0 0x20>; + }; + + qos_rkvdec0: qos@fdf62000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf62000 0x0 0x20>; + }; + + qos_rkvdec1: qos@fdf63000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf63000 0x0 0x20>; + }; + + qos_av1: qos@fdf64000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf64000 0x0 0x20>; + }; + + qos_iep: qos@fdf66000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf66000 0x0 0x20>; + }; + + qos_jpeg_dec: qos@fdf66200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf66200 0x0 0x20>; + }; + + qos_jpeg_enc0: qos@fdf66400 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf66400 0x0 0x20>; + }; + + qos_jpeg_enc1: qos@fdf66600 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf66600 0x0 0x20>; + }; + + qos_jpeg_enc2: qos@fdf66800 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf66800 0x0 0x20>; + }; + + qos_jpeg_enc3: qos@fdf66a00 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf66a00 0x0 0x20>; + }; + + qos_rga2_mro: qos@fdf66c00 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf66c00 0x0 0x20>; + }; + + qos_rga2_mwo: qos@fdf66e00 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf66e00 0x0 0x20>; + }; + + qos_rga3_0: qos@fdf67000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf67000 0x0 0x20>; + }; + + qos_vdpu: qos@fdf67200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf67200 0x0 0x20>; + }; + + qos_npu1: qos@fdf70000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf70000 0x0 0x20>; + }; + + qos_npu2: qos@fdf71000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf71000 0x0 0x20>; + }; + + qos_npu0_mwr: qos@fdf72000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf72000 0x0 0x20>; + }; + + qos_npu0_mro: qos@fdf72200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf72200 0x0 0x20>; + }; + + qos_mcu_npu: qos@fdf72400 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf72400 0x0 0x20>; + }; + + qos_hdcp0: qos@fdf80000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf80000 0x0 0x20>; + }; + + qos_hdcp1: qos@fdf81000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf81000 0x0 0x20>; + }; + + qos_hdmirx: qos@fdf81200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf81200 0x0 0x20>; + }; + + qos_vop_m0: qos@fdf82000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf82000 0x0 0x20>; + }; + + qos_vop_m1: qos@fdf82200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf82200 0x0 0x20>; + }; + + dfi: dfi@fe060000 { + reg = <0x00 0xfe060000 0x00 0x10000>; + compatible = "rockchip,rk3588-dfi"; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; + rockchip,pmu = <&pmu1grf>; + }; + + pcie2x1l1: pcie@fe180000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + bus-range = <0x30 0x3f>; + clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, + <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, + <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, + <0 0 0 2 &pcie2x1l1_intc 1>, + <0 0 0 3 &pcie2x1l1_intc 2>, + <0 0 0 4 &pcie2x1l1_intc 3>; + linux,pci-domain = <3>; + max-link-speed = <2>; + msi-map = <0x3000 &its0 0x3000 0x1000>; + num-lanes = <1>; + phys = <&combphy2_psu PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, + <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>; + reg = <0xa 0x40c00000 0x0 0x00400000>, + <0x0 0xfe180000 0x0 0x00010000>, + <0x0 0xf3000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; + reset-names = "pwr", "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie2x1l1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + + pcie2x1l2: pcie@fe190000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + bus-range = <0x40 0x4f>; + clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, + <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, + <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, + <0 0 0 2 &pcie2x1l2_intc 1>, + <0 0 0 3 &pcie2x1l2_intc 2>, + <0 0 0 4 &pcie2x1l2_intc 3>; + linux,pci-domain = <4>; + max-link-speed = <2>; + msi-map = <0x4000 &its0 0x4000 0x1000>; + num-lanes = <1>; + phys = <&combphy0_ps PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, + <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; + reg = <0xa 0x41000000 0x0 0x00400000>, + <0x0 0xfe190000 0x0 0x00010000>, + <0x0 0xf4000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; + reset-names = "pwr", "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie2x1l2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + + gmac1: ethernet@fe1c0000 { + compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xfe1c0000 0x0 0x10000>; + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "macirq", "eth_wake_irq"; + clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, + <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, + <&cru CLK_GMAC1_PTP_REF>; + clock-names = "stmmaceth", "clk_mac_ref", + "pclk_mac", "aclk_mac", + "ptp_ref"; + power-domains = <&power RK3588_PD_GMAC>; + resets = <&cru SRST_A_GMAC1>; + reset-names = "stmmaceth"; + rockchip,grf = <&sys_grf>; + rockchip,php-grf = <&php_grf>; + snps,axi-config = <&gmac1_stmmac_axi_setup>; + snps,mixed-burst; + snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; + snps,tso; + status = "disabled"; + + mdio1: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + gmac1_stmmac_axi_setup: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + }; + + gmac1_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <2>; + queue0 {}; + queue1 {}; + }; + + gmac1_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <2>; + queue0 {}; + queue1 {}; + }; + }; + + sata0: sata@fe210000 { + compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfe210000 0 0x1000>; + interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, + <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, + <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; + ports-implemented = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata-port@0 { + reg = <0>; + hba-port-cap = <HBA_PORT_FBSCP>; + phys = <&combphy0_ps PHY_TYPE_SATA>; + phy-names = "sata-phy"; + snps,rx-ts-max = <32>; + snps,tx-ts-max = <32>; + }; + }; + + sata2: sata@fe230000 { + compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfe230000 0 0x1000>; + interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, + <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, + <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; + ports-implemented = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata-port@0 { + reg = <0>; + hba-port-cap = <HBA_PORT_FBSCP>; + phys = <&combphy2_psu PHY_TYPE_SATA>; + phy-names = "sata-phy"; + snps,rx-ts-max = <32>; + snps,tx-ts-max = <32>; + }; + }; + + sfc: spi@fe2b0000 { + compatible = "rockchip,sfc"; + reg = <0x0 0xfe2b0000 0x0 0x4000>; + interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sdmmc: mmc@fe2c0000 { + compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe2c0000 0x0 0x4000>; + interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; + power-domains = <&power RK3588_PD_SDMMC>; + status = "disabled"; + }; + + sdio: mmc@fe2d0000 { + compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x00 0xfe2d0000 0x00 0x4000>; + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom1_pins>; + power-domains = <&power RK3588_PD_SDIO>; + status = "disabled"; + }; + + sdhci: mmc@fe2e0000 { + compatible = "rockchip,rk3588-dwcmshc"; + reg = <0x0 0xfe2e0000 0x0 0x10000>; + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; + assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>; + assigned-clock-rates = <200000000>, <24000000>, <200000000>; + clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, + <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, + <&cru TMCLK_EMMC>; + clock-names = "core", "bus", "axi", "block", "timer"; + max-frequency = <200000000>; + pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, + <&emmc_cmd>, <&emmc_data_strobe>; + pinctrl-names = "default"; + resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, + <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, + <&cru SRST_T_EMMC>; + reset-names = "core", "bus", "axi", "block", "timer"; + status = "disabled"; + }; + + i2s0_8ch: i2s@fe470000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfe470000 0x0 0x1000>; + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; + dmas = <&dmac0 0>, <&dmac0 1>; + dma-names = "tx", "rx"; + power-domains = <&power RK3588_PD_AUDIO>; + resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; + reset-names = "tx-m", "rx-m"; + rockchip,trcm-sync-tx-only; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdi1 + &i2s0_sdi2 + &i2s0_sdi3 + &i2s0_sdo0 + &i2s0_sdo1 + &i2s0_sdo2 + &i2s0_sdo3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s1_8ch: i2s@fe480000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfe480000 0x0 0x1000>; + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + dmas = <&dmac0 2>, <&dmac0 3>; + dma-names = "tx", "rx"; + resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; + reset-names = "tx-m", "rx-m"; + rockchip,trcm-sync-tx-only; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_lrck + &i2s1m0_sclk + &i2s1m0_sdi0 + &i2s1m0_sdi1 + &i2s1m0_sdi2 + &i2s1m0_sdi3 + &i2s1m0_sdo0 + &i2s1m0_sdo1 + &i2s1m0_sdo2 + &i2s1m0_sdo3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s2_2ch: i2s@fe490000 { + compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xfe490000 0x0 0x1000>; + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; + clock-names = "i2s_clk", "i2s_hclk"; + assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac1 0>, <&dmac1 1>; + dma-names = "tx", "rx"; + power-domains = <&power RK3588_PD_AUDIO>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2m1_lrck + &i2s2m1_sclk + &i2s2m1_sdi + &i2s2m1_sdo>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s3_2ch: i2s@fe4a0000 { + compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xfe4a0000 0x0 0x1000>; + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; + clock-names = "i2s_clk", "i2s_hclk"; + assigned-clocks = <&cru CLK_I2S3_2CH_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac1 2>, <&dmac1 3>; + dma-names = "tx", "rx"; + power-domains = <&power RK3588_PD_AUDIO>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s3_lrck + &i2s3_sclk + &i2s3_sdi + &i2s3_sdo>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + gic: interrupt-controller@fe600000 { + compatible = "arm,gic-v3"; + reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ + <0x0 0xfe680000 0 0x100000>; /* GICR */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-controller; + mbi-alias = <0x0 0xfe610000>; + mbi-ranges = <424 56>; + msi-controller; + ranges; + #address-cells = <2>; + #interrupt-cells = <4>; + #size-cells = <2>; + + its0: msi-controller@fe640000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0xfe640000 0x0 0x20000>; + msi-controller; + #msi-cells = <1>; + }; + + its1: msi-controller@fe660000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0xfe660000 0x0 0x20000>; + msi-controller; + #msi-cells = <1>; + }; + + ppi-partitions { + ppi_partition0: interrupt-partition-0 { + affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; + }; + + ppi_partition1: interrupt-partition-1 { + affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>; + }; + }; + }; + + dmac0: dma-controller@fea10000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfea10000 0x0 0x4000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + dmac1: dma-controller@fea30000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfea30000 0x0 0x4000>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + i2c1: i2c@fea90000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfea90000 0x0 0x1000>; + clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&i2c1m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@feaa0000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfeaa0000 0x0 0x1000>; + clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&i2c2m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@feab0000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfeab0000 0x0 0x1000>; + clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&i2c3m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@feac0000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfeac0000 0x0 0x1000>; + clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&i2c4m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@fead0000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfead0000 0x0 0x1000>; + clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&i2c5m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + timer0: timer@feae0000 { + compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; + reg = <0x0 0xfeae0000 0x0 0x20>; + interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; + clock-names = "pclk", "timer"; + }; + + wdt: watchdog@feaf0000 { + compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; + reg = <0x0 0xfeaf0000 0x0 0x100>; + clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; + clock-names = "tclk", "pclk"; + interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>; + }; + + spi0: spi@feb00000 { + compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfeb00000 0x0 0x1000>; + interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 14>, <&dmac0 15>; + dma-names = "tx", "rx"; + num-cs = <2>; + pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@feb10000 { + compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfeb10000 0x0 0x1000>; + interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 16>, <&dmac0 17>; + dma-names = "tx", "rx"; + num-cs = <2>; + pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@feb20000 { + compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfeb20000 0x0 0x1000>; + interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac1 15>, <&dmac1 16>; + dma-names = "tx", "rx"; + num-cs = <2>; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@feb30000 { + compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfeb30000 0x0 0x1000>; + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac1 17>, <&dmac1 18>; + dma-names = "tx", "rx"; + num-cs = <2>; + pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart1: serial@feb40000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb40000 0x0 0x100>; + interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 8>, <&dmac0 9>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart1m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart2: serial@feb50000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb50000 0x0 0x100>; + interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 10>, <&dmac0 11>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart2m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart3: serial@feb60000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb60000 0x0 0x100>; + interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 12>, <&dmac0 13>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart3m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart4: serial@feb70000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb70000 0x0 0x100>; + interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac1 9>, <&dmac1 10>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart4m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart5: serial@feb80000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb80000 0x0 0x100>; + interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac1 11>, <&dmac1 12>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart5m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart6: serial@feb90000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb90000 0x0 0x100>; + interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac1 13>, <&dmac1 14>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart6m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart7: serial@feba0000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeba0000 0x0 0x100>; + interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac2 7>, <&dmac2 8>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart7m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart8: serial@febb0000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfebb0000 0x0 0x100>; + interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac2 9>, <&dmac2 10>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart8m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart9: serial@febc0000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfebc0000 0x0 0x100>; + interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac2 11>, <&dmac2 12>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart9m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + pwm4: pwm@febd0000 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebd0000 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm4m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm5: pwm@febd0010 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebd0010 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm5m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm6: pwm@febd0020 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebd0020 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm6m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm7: pwm@febd0030 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebd0030 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm7m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm8: pwm@febe0000 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebe0000 0x0 0x10>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm8m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm9: pwm@febe0010 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebe0010 0x0 0x10>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm9m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm10: pwm@febe0020 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebe0020 0x0 0x10>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm10m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm11: pwm@febe0030 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebe0030 0x0 0x10>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm11m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm12: pwm@febf0000 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebf0000 0x0 0x10>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm12m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm13: pwm@febf0010 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebf0010 0x0 0x10>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm13m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm14: pwm@febf0020 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebf0020 0x0 0x10>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm14m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm15: pwm@febf0030 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebf0030 0x0 0x10>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm15m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + thermal_zones: thermal-zones { + /* sensor near the center of the SoC */ + package_thermal: package-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 0>; + + trips { + package_crit: package-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + /* sensor between A76 cores 0 and 1 */ + bigcore0_thermal: bigcore0-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&tsadc 1>; + + trips { + bigcore0_alert: bigcore0-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + bigcore0_crit: bigcore0-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&bigcore0_alert>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + /* sensor between A76 cores 2 and 3 */ + bigcore2_thermal: bigcore2-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&tsadc 2>; + + trips { + bigcore2_alert: bigcore2-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + bigcore2_crit: bigcore2-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&bigcore2_alert>; + cooling-device = + <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + /* sensor between the four A55 cores */ + little_core_thermal: littlecore-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&tsadc 3>; + + trips { + littlecore_alert: littlecore-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + littlecore_crit: littlecore-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&littlecore_alert>; + cooling-device = + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + /* sensor near the PD_CENTER power domain */ + center_thermal: center-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 4>; + + trips { + center_crit: center-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&tsadc 5>; + + trips { + gpu_alert: gpu-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu_crit: gpu-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_alert>; + cooling-device = + <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + npu_thermal: npu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 6>; + + trips { + npu_crit: npu-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; + + tsadc: tsadc@fec00000 { + compatible = "rockchip,rk3588-tsadc"; + reg = <0x0 0xfec00000 0x0 0x400>; + interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + assigned-clocks = <&cru CLK_TSADC>; + assigned-clock-rates = <2000000>; + resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; + reset-names = "tsadc-apb", "tsadc"; + rockchip,hw-tshut-temp = <120000>; + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + pinctrl-0 = <&tsadc_gpio_func>; + pinctrl-1 = <&tsadc_shut>; + pinctrl-names = "gpio", "otpout"; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + + saradc: adc@fec10000 { + compatible = "rockchip,rk3588-saradc"; + reg = <0x0 0xfec10000 0x0 0x10000>; + interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>; + #io-channel-cells = <1>; + clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_P_SARADC>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + i2c6: i2c@fec80000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfec80000 0x0 0x1000>; + clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&i2c6m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@fec90000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfec90000 0x0 0x1000>; + clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&i2c7m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@feca0000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfeca0000 0x0 0x1000>; + clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&i2c8m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@fecb0000 { + compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfecb0000 0x0 0x1000>; + interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac2 13>, <&dmac2 14>; + dma-names = "tx", "rx"; + num-cs = <2>; + pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + otp: efuse@fecc0000 { + compatible = "rockchip,rk3588-otp"; + reg = <0x0 0xfecc0000 0x0 0x400>; + clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, + <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>; + clock-names = "otp", "apb_pclk", "phy", "arb"; + resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, + <&cru SRST_OTPC_ARB>; + reset-names = "otp", "apb", "arb"; + #address-cells = <1>; + #size-cells = <1>; + + cpu_code: cpu-code@2 { + reg = <0x02 0x2>; + }; + + otp_id: id@7 { + reg = <0x07 0x10>; + }; + + cpub0_leakage: cpu-leakage@17 { + reg = <0x17 0x1>; + }; + + cpub1_leakage: cpu-leakage@18 { + reg = <0x18 0x1>; + }; + + cpul_leakage: cpu-leakage@19 { + reg = <0x19 0x1>; + }; + + log_leakage: log-leakage@1a { + reg = <0x1a 0x1>; + }; + + gpu_leakage: gpu-leakage@1b { + reg = <0x1b 0x1>; + }; + + otp_cpu_version: cpu-version@1c { + reg = <0x1c 0x1>; + bits = <3 3>; + }; + + npu_leakage: npu-leakage@28 { + reg = <0x28 0x1>; + }; + + codec_leakage: codec-leakage@29 { + reg = <0x29 0x1>; + }; + }; + + dmac2: dma-controller@fed10000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfed10000 0x0 0x4000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC2>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + hdptxphy_hdmi0: phy@fed60000 { + compatible = "rockchip,rk3588-hdptx-phy"; + reg = <0x0 0xfed60000 0x0 0x2000>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; + clock-names = "ref", "apb"; + #phy-cells = <0>; + resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, + <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, + <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, + <&cru SRST_HDPTX0_LCPLL>; + reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", + "lcpll"; + rockchip,grf = <&hdptxphy0_grf>; + status = "disabled"; + }; + + usbdp_phy0: phy@fed80000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x0 0xfed80000 0x0 0x10000>; + #phy-cells = <1>; + clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, + <&cru CLK_USBDP_PHY0_IMMORTAL>, + <&cru PCLK_USBDPPHY0>, + <&u2phy0>; + clock-names = "refclk", "immortal", "pclk", "utmi"; + resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, + <&cru SRST_USBDP_COMBO_PHY0_CMN>, + <&cru SRST_USBDP_COMBO_PHY0_LANE>, + <&cru SRST_USBDP_COMBO_PHY0_PCS>, + <&cru SRST_P_USBDPPHY0>; + reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; + rockchip,u2phy-grf = <&usb2phy0_grf>; + rockchip,usb-grf = <&usb_grf>; + rockchip,usbdpphy-grf = <&usbdpphy0_grf>; + rockchip,vo-grf = <&vo0_grf>; + status = "disabled"; + }; + + combphy0_ps: phy@fee00000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee00000 0x0 0x100>; + clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, + <&cru PCLK_PHP_ROOT>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; + assigned-clock-rates = <100000000>; + #phy-cells = <1>; + resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>; + reset-names = "phy", "apb"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy0_grf>; + status = "disabled"; + }; + + combphy2_psu: phy@fee20000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee20000 0x0 0x100>; + clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, + <&cru PCLK_PHP_ROOT>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; + assigned-clock-rates = <100000000>; + #phy-cells = <1>; + resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>; + reset-names = "phy", "apb"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy2_grf>; + status = "disabled"; + }; + + system_sram2: sram@ff001000 { + compatible = "mmio-sram"; + reg = <0x0 0xff001000 0x0 0xef000>; + ranges = <0x0 0x0 0xff001000 0xef000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3588-pinctrl"; + ranges; + rockchip,grf = <&ioc>; + #address-cells = <2>; + #size-cells = <2>; + + gpio0: gpio@fd8a0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfd8a0000 0x0 0x100>; + interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 32>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio1: gpio@fec20000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec20000 0x0 0x100>; + interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + gpio-controller; + gpio-ranges = <&pinctrl 0 32 32>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio2: gpio@fec30000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec30000 0x0 0x100>; + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + gpio-controller; + gpio-ranges = <&pinctrl 0 64 32>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio3: gpio@fec40000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec40000 0x0 0x100>; + interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + gpio-controller; + gpio-ranges = <&pinctrl 0 96 32>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio4: gpio@fec50000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec50000 0x0 0x100>; + interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + gpio-controller; + gpio-ranges = <&pinctrl 0 128 32>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + }; +}; + +#include "rk3588-base-pinctrl.dtsi" diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi index 709d348cf06b..03fd193be253 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi @@ -466,3 +466,7 @@ }; }; }; + +&tsadc { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts index 7be2190244ba..00f660d50127 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts @@ -878,6 +878,8 @@ vdd_cpu_big1_s0: dcdc-reg1 { regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_big1_mem_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <550000>; regulator-max-microvolt = <1050000>; regulator-ramp-delay = <12500>; @@ -890,6 +892,8 @@ vdd_cpu_big0_s0: dcdc-reg2 { regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_big0_mem_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <550000>; regulator-max-microvolt = <1050000>; regulator-ramp-delay = <12500>; @@ -902,6 +906,8 @@ vdd_cpu_lit_s0: dcdc-reg3 { regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_lit_mem_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <550000>; regulator-max-microvolt = <950000>; regulator-ramp-delay = <12500>; @@ -926,6 +932,8 @@ vdd_cpu_big1_mem_s0: dcdc-reg5 { regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_big1_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <675000>; regulator-max-microvolt = <1050000>; regulator-ramp-delay = <12500>; @@ -939,6 +947,8 @@ vdd_cpu_big0_mem_s0: dcdc-reg6 { regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_big0_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <675000>; regulator-max-microvolt = <1050000>; regulator-ramp-delay = <12500>; @@ -963,6 +973,8 @@ vdd_cpu_lit_mem_s0: dcdc-reg8 { regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_lit_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <675000>; regulator-max-microvolt = <950000>; regulator-ramp-delay = <12500>; @@ -1131,6 +1143,10 @@ status = "okay"; }; +&tsadc { + status = "okay"; +}; + &u2phy0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra-pinctrl.dtsi index 244c66faa161..244c66faa161 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-extra-pinctrl.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi new file mode 100644 index 000000000000..0ce0934ec6b7 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi @@ -0,0 +1,448 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include "rk3588-base.dtsi" +#include "rk3588-extra-pinctrl.dtsi" + +/ { + usb_host1_xhci: usb@fc400000 { + compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; + reg = <0x0 0xfc400000 0x0 0x400000>; + interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, + <&cru ACLK_USB3OTG1>; + clock-names = "ref_clk", "suspend_clk", "bus_clk"; + dr_mode = "otg"; + phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + power-domains = <&power RK3588_PD_USB>; + resets = <&cru SRST_A_USB3OTG1>; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + status = "disabled"; + }; + + pcie30_phy_grf: syscon@fd5b8000 { + compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; + reg = <0x0 0xfd5b8000 0x0 0x10000>; + }; + + pipe_phy1_grf: syscon@fd5c0000 { + compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5c0000 0x0 0x100>; + }; + + usbdpphy1_grf: syscon@fd5cc000 { + compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; + reg = <0x0 0xfd5cc000 0x0 0x4000>; + }; + + usb2phy1_grf: syscon@fd5d4000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd5d4000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy1: usb2phy@4000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x4000 0x10>; + #clock-cells = <0>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy1"; + interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>; + resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; + reset-names = "phy", "apb"; + status = "disabled"; + + u2phy1_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + i2s8_8ch: i2s@fddc8000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddc8000 0x0 0x1000>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 22>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO0>; + resets = <&cru SRST_M_I2S8_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s6_8ch: i2s@fddf4000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf4000 0x0 0x1000>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 4>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S6_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s7_8ch: i2s@fddf8000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf8000 0x0 0x1000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 21>; + dma-names = "rx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S7_8CH_RX>; + reset-names = "rx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s10_8ch: i2s@fde00000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfde00000 0x0 0x1000>; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 24>; + dma-names = "rx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S10_8CH_RX>; + reset-names = "rx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + pcie3x4: pcie@fe150000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0x0f>; + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, + <0 0 0 2 &pcie3x4_intc 1>, + <0 0 0 3 &pcie3x4_intc 2>, + <0 0 0 4 &pcie3x4_intc 3>; + linux,pci-domain = <0>; + max-link-speed = <3>; + msi-map = <0x0000 &its1 0x0000 0x1000>; + num-lanes = <4>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, + <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>; + reg = <0xa 0x40000000 0x0 0x00400000>, + <0x0 0xfe150000 0x0 0x00010000>, + <0x0 0xf0000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; + reset-names = "pwr", "pipe"; + status = "disabled"; + + pcie3x4_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + + pcie3x4_ep: pcie-ep@fe150000 { + compatible = "rockchip,rk3588-pcie-ep"; + reg = <0xa 0x40000000 0x0 0x00100000>, + <0xa 0x40100000 0x0 0x00100000>, + <0x0 0xfe150000 0x0 0x00010000>, + <0x9 0x00000000 0x0 0x40000000>, + <0xa 0x40300000 0x0 0x00100000>; + reg-names = "dbi", "dbi2", "apb", "addr_space", "atu"; + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err", + "dma0", "dma1", "dma2", "dma3"; + max-link-speed = <3>; + num-lanes = <4>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; + reset-names = "pwr", "pipe"; + status = "disabled"; + }; + + pcie3x2: pcie@fe160000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x10 0x1f>; + clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, + <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, + <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, + <0 0 0 2 &pcie3x2_intc 1>, + <0 0 0 3 &pcie3x2_intc 2>, + <0 0 0 4 &pcie3x2_intc 3>; + linux,pci-domain = <1>; + max-link-speed = <3>; + msi-map = <0x1000 &its1 0x1000 0x1000>; + num-lanes = <2>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>, + <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>; + reg = <0xa 0x40400000 0x0 0x00400000>, + <0x0 0xfe160000 0x0 0x00010000>, + <0x0 0xf1000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; + reset-names = "pwr", "pipe"; + status = "disabled"; + + pcie3x2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + + pcie2x1l0: pcie@fe170000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + bus-range = <0x20 0x2f>; + clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>, + <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>, + <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>, + <0 0 0 2 &pcie2x1l0_intc 1>, + <0 0 0 3 &pcie2x1l0_intc 2>, + <0 0 0 4 &pcie2x1l0_intc 3>; + linux,pci-domain = <2>; + max-link-speed = <2>; + msi-map = <0x2000 &its0 0x2000 0x1000>; + num-lanes = <1>; + phys = <&combphy1_ps PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, + <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>; + reg = <0xa 0x40800000 0x0 0x00400000>, + <0x0 0xfe170000 0x0 0x00010000>, + <0x0 0xf2000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>; + reset-names = "pwr", "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie2x1l0_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + + gmac0: ethernet@fe1b0000 { + compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xfe1b0000 0x0 0x10000>; + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "macirq", "eth_wake_irq"; + clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, + <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, + <&cru CLK_GMAC0_PTP_REF>; + clock-names = "stmmaceth", "clk_mac_ref", + "pclk_mac", "aclk_mac", + "ptp_ref"; + power-domains = <&power RK3588_PD_GMAC>; + resets = <&cru SRST_A_GMAC0>; + reset-names = "stmmaceth"; + rockchip,grf = <&sys_grf>; + rockchip,php-grf = <&php_grf>; + snps,axi-config = <&gmac0_stmmac_axi_setup>; + snps,mixed-burst; + snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; + snps,tso; + status = "disabled"; + + mdio0: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + gmac0_stmmac_axi_setup: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + }; + + gmac0_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <2>; + queue0 {}; + queue1 {}; + }; + + gmac0_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <2>; + queue0 {}; + queue1 {}; + }; + }; + + sata1: sata@fe220000 { + compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfe220000 0 0x1000>; + interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, + <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>, + <&cru CLK_PIPEPHY1_PIPE_ASIC_G>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; + ports-implemented = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata-port@0 { + reg = <0>; + hba-port-cap = <HBA_PORT_FBSCP>; + phys = <&combphy1_ps PHY_TYPE_SATA>; + phy-names = "sata-phy"; + snps,rx-ts-max = <32>; + snps,tx-ts-max = <32>; + }; + }; + + usbdp_phy1: phy@fed90000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x0 0xfed90000 0x0 0x10000>; + #phy-cells = <1>; + clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, + <&cru CLK_USBDP_PHY1_IMMORTAL>, + <&cru PCLK_USBDPPHY1>, + <&u2phy1>; + clock-names = "refclk", "immortal", "pclk", "utmi"; + resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>, + <&cru SRST_USBDP_COMBO_PHY1_CMN>, + <&cru SRST_USBDP_COMBO_PHY1_LANE>, + <&cru SRST_USBDP_COMBO_PHY1_PCS>, + <&cru SRST_P_USBDPPHY1>; + reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; + rockchip,u2phy-grf = <&usb2phy1_grf>; + rockchip,usb-grf = <&usb_grf>; + rockchip,usbdpphy-grf = <&usbdpphy1_grf>; + rockchip,vo-grf = <&vo0_grf>; + status = "disabled"; + }; + + combphy1_ps: phy@fee10000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee10000 0x0 0x100>; + clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>, + <&cru PCLK_PHP_ROOT>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY1>; + assigned-clock-rates = <100000000>; + #phy-cells = <1>; + resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>; + reset-names = "phy", "apb"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy1_grf>; + status = "disabled"; + }; + + pcie30phy: phy@fee80000 { + compatible = "rockchip,rk3588-pcie3-phy"; + reg = <0x0 0xfee80000 0x0 0x20000>; + #phy-cells = <0>; + clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>; + clock-names = "pclk"; + resets = <&cru SRST_PCIE30_PHY>; + reset-names = "phy"; + rockchip,pipe-grf = <&php_grf>; + rockchip,phy-grf = <&pcie30_phy_grf>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts new file mode 100644 index 000000000000..83103e4c7216 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts @@ -0,0 +1,778 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2023 Thomas McKahan + * Copyright (c) 2024 Sebastian Kropatsch + * + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/usb/pd.h> +#include "rk3588-friendlyelec-cm3588.dtsi" + +/ { + model = "FriendlyElec CM3588 NAS"; + compatible = "friendlyarm,cm3588-nas", "friendlyarm,cm3588", "rockchip,rk3588"; + + adc_key_recovery: adc-key-recovery { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-recovery { + label = "Recovery"; + linux,code = <KEY_VENDOR>; + press-threshold-microvolt = <17000>; + }; + }; + + analog-sound { + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&headphone_detect>; + + simple-audio-card,format = "i2s"; + simple-audio-card,hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "realtek,rt5616-codec"; + + simple-audio-card,routing = + "Headphones", "HPOL", + "Headphones", "HPOR", + "MIC1", "Microphone Jack", + "Microphone Jack", "micbias1"; + simple-audio-card,widgets = + "Headphone", "Headphones", + "Microphone", "Microphone Jack"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + + simple-audio-card,codec { + sound-dai = <&rt5616>; + }; + }; + + buzzer: pwm-beeper { + compatible = "pwm-beeper"; + amp-supply = <&vcc_5v0_sys>; + beeper-hz = <500>; + pwms = <&pwm8 0 500000 0>; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-levels = <0 50 80 120 160 220>; + fan-supply = <&vcc_5v0_sys>; + pwms = <&pwm1 0 50000 0>; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key1_pin>; + + button-user { + debounce-interval = <50>; + gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_LOW>; + label = "User Button"; + linux,code = <BTN_1>; + wakeup-source; + }; + }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>; + }; + + vcc_12v_dcin: regulator-vcc-12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc_12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc_3v3_m2_a: regulator-vcc-3v3-m2-a { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_m2_a"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_12v_dcin>; + }; + + vcc_3v3_m2_b: regulator-vcc-3v3-m2-b { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_m2_b"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_12v_dcin>; + }; + + vcc_3v3_m2_c: regulator-vcc-3v3-m2-c { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_m2_c"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_12v_dcin>; + }; + + vcc_3v3_m2_d: regulator-vcc-3v3-m2-d { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_m2_d"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_12v_dcin>; + }; + + /* vcc_5v0_sys powers the peripherals */ + vcc_5v0_sys: regulator-vcc-5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_12v_dcin>; + }; + + /* SY6280AAC power switch (U14 in schematics) */ + vcc_5v0_host_20: regulator-vcc-5v0-host-20 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_5v0_host20_en>; + regulator-name = "vcc_5v0_host_20"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v0_sys>; + }; + + /* SY6280AAC power switch (U8 in schematics) */ + vcc_5v0_host_30_p1: regulator-vcc-5v0-host-30-p1 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_5v0_host30p1_en>; + regulator-name = "vcc_5v0_host_30_p1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v0_sys>; + }; + + /* SY6280AAC power switch (U9 in schematics) */ + vcc_5v0_host_30_p2: regulator-vcc-5v0-host-30-p2 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_5v0_host30p2_en>; + regulator-name = "vcc_5v0_host_30_p2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v0_sys>; + }; + + /* SY6280AAC power switch (U10 in schematics) */ + vbus_5v0_typec: regulator-vbus-5v0-typec { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&typec_5v_pwr_en>; + regulator-name = "vbus_5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v0_sys>; + }; +}; + +/* vcc_4v0_sys powers the RK806 and RK860's */ +&vcc_4v0_sys { + vin-supply = <&vcc_12v_dcin>; +}; + +/* Combo PHY 1 is configured to act as as PCIe 2.0 PHY */ +/* Used by PCIe controller 2 (pcie2x1l0) */ +&combphy1_ps { + status = "okay"; +}; + +/* Combo PHY 2 is configured to act as USB3 PHY */ +/* Used by USB 3.0 OTG 2 controller (USB 3.0 Type-A port 2) */ +/* CM3588 USB Controller Config Table: USB30 HOST2 */ +&combphy2_psu { + status = "okay"; +}; + +/* GPIO names are in the format "Human-readable-name [SIGNAL_LABEL]" */ +/* Signal labels match the official CM3588 NAS SDK schematic revision 2309 */ +&gpio0 { + gpio-line-names = + /* GPIO0 A0-A7 */ + "", "", "", "", + "MicroSD detect [SDMMC_DET_L]", "", "", "", + /* GPIO0 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO0 C0-C7 */ + "", "", "", "", + "Pin 10 [UART0_RX_M0]", "Pin 08 [UART0_TX_M0/PWM4_M0]", "Pin 32 [PWM5_M1]", "", + /* GPIO0 D0-D7 */ + "", "", "", "USB3 Type-C [CC_INT_L]", + "IR receiver [PWM3_IR_M0]", "User Button", "", ""; +}; + +&gpio1 { + gpio-line-names = + /* GPIO1 A0-A7 */ + "Pin 27 [UART6_RX_M1]", "Pin 28 [UART6_TX_M1]", "", "", + "USB2 Type-A [USB2_PWREN]", "", "", "Pin 15", + /* GPIO1 B0-B7 */ + "Pin 26", "Pin 21 [SPI0_MISO_M2]", "Pin 19 [SPI0_MOSI_M2/UART4_RX_M2]", "Pin 23 [SPI0_CLK_M2/UART4_TX_M2]", + "Pin 24 [SPI0_CS0_M2/UART7_RX_M2]", "Pin 22 [SPI0_CS1_M0/UART7_TX_M2]", "", "CSI-Pin 14 [MIPI_CAM2_CLKOUT]", + /* GPIO1 C0-C7 */ + "", "", "", "", + "Headphone detect [HP_DET_L]", "", "", "", + /* GPIO1 D0-D7 */ + "", "", "USB3 Type-C [TYPEC5V_PWREN_H]", "5V Fan [PWM1_M1]", + "", "HDMI-in detect [HDMIIRX_DET_L]", "Pin 05 [I2C8_SCL_M2]", "Pin 03 [I2C8_SDA_M2]"; +}; + +&gpio2 { + gpio-line-names = + /* GPIO2 A0-A7 */ + "", "", "", "", + "", "", "SPI NOR Flash [FSPI_D0_M1]", "SPI NOR Flash [FSPI_D1_M1]", + /* GPIO2 B0-B7 */ + "SPI NOR Flash [FSPI_D2_M1]", "SPI NOR Flash [FSPI_D3_M1]", "", "SPI NOR Flash [FSPI_CLK_M1]", + "SPI NOR Flash [FSPI_CSN0_M1]", "", "", "", + /* GPIO2 C0-C7 */ + "", "CSI-Pin 11 [MIPI_CAM2_RESET_L]", "CSI-Pin 12 [MIPI_CAM2_PDN_L]", "", + "", "", "", "", + /* GPIO2 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + /* GPIO3 A0-A7 */ + "Pin 35 [SPI4_MISO_M1/PWM10_M0]", "Pin 38 [SPI4_MOSI_M1]", "Pin 40 [SPI4_CLK_M1/UART8_TX_M1]", "Pin 36 [SPI4_CS0_M1/UART8_RX_M1]", + "Pin 37 [SPI4_CS1_M1]", "USB3-A #2 [USB3_2_PWREN]", "DSI-Pin 12 [LCD_RST]", "Buzzer [PWM8_M0]", + /* GPIO3 B0-B7 */ + "Pin 33 [PWM9_M0]", "DSI-Pin 10 [PWM2_M1/LCD_BL]", "Pin 07", "Pin 16", + "Pin 18", "Pin 29 [UART3_TX_M1/PWM12_M0]", "Pin 31 [UART3_RX_M1/PWM13_M0]", "Pin 12", + /* GPIO3 C0-C7 */ + "DSI-Pin 08 [TP_INT_L]", "DSI-Pin 14 [TP_RST_L]", "Pin 11 [PWM14_M0]", "Pin 13 [PWM15_IR_M0]", + "", "", "", "DSI-Pin 06 [I2C5_SCL_M0_TP]", + /* GPIO3 D0-D7 */ + "DSI-Pin 05 [I2C5_SDA_M0_TP]", "", "", "", + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + /* GPIO4 A0-A7 */ + "", "", "M.2 M-Key Slot4 [M2_D_PERST_L]", "", + "", "", "", "", + /* GPIO4 B0-B7 */ + "USB3-A #1 [USB3_TYPEC1_PWREN]", "", "", "M.2 M-Key Slot3 [M2_C_PERST_L]", + "M.2 M-Key Slot2 [M2_B_PERST_L]", "M.2 M-Key Slot1 [M2_A_CLKREQ_L]", "M.2 M-Key Slot1 [M2_A_PERST_L]", "", + /* GPIO4 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO4 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +/* Connected to MIPI-DSI0 */ +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m0_xfer>; + status = "disabled"; +}; + +&i2c6 { + fusb302: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus_5v0_typec>; + + usb_con: connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + power-role = "source"; + source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>; + try-power-role = "source"; + vbus-supply = <&vbus_5v0_typec>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + + usbc0_role_sw: endpoint { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + + port@2 { + reg = <2>; + + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +/* Connected to MIPI-CSI1 */ +/* &i2c7 */ + +/* GPIO Connector, connected to 40-pin GPIO header */ +&i2c8 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m2_xfer>; + status = "okay"; +}; + +&pcie2x1l0 { + /* 2. M.2 socket, CON14: pcie30phy port0 lane1, @fe170000 */ + max-link-speed = <3>; + num-lanes = <1>; + phys = <&pcie30phy>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_0_rst>; + reset-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_m2_b>; + status = "okay"; +}; + +&pcie2x1l1 { + /* 4. M.2 socket, CON16: pcie30phy port1 lane1, @fe180000 */ + max-link-speed = <3>; + num-lanes = <1>; + phys = <&pcie30phy>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_1_rst>; + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_m2_d>; + status = "okay"; +}; + +&pcie30phy { + /* + * Data lane mapping <1 3 2 4> = x1x1 x1x1 (bifurcation of both ports) + * port 0 lane 0 - always mapped to controller 0 (4L) + * port 0 lane 1 - map to controller 2 (1L0) + * port 1 lane 0 - map to controller 1 (2L) + * port 1 lane 1 - map to controller 3 (1L1) + */ + data-lanes = <1 3 2 4>; + status = "okay"; +}; + +&pcie3x4 { + /* 1. M.2 socket, CON13: pcie30phy port0 lane0, @fe150000 */ + max-link-speed = <3>; + num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie3x4_rst>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_m2_a>; + status = "okay"; +}; + +&pcie3x2 { + /* 3. M.2 socket, CON15: pcie30phy port1 lane0, @fe160000 */ + max-link-speed = <3>; + num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie3x2_rst>; + reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_m2_c>; + status = "okay"; +}; + +&pinctrl { + audio { + headphone_detect: headphone-detect { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gpio-key { + key1_pin: key1-pin { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pcie { + pcie2_0_rst: pcie2-0-rst { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie2_1_rst: pcie2-1-rst { + rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie3x2_rst: pcie3x2-rst { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie3x4_rst: pcie3x4-rst { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc_5v0_host20_en: vcc-5v0-host20-en { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc_5v0_host30p1_en: vcc-5v0-host30p1-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc_5v0_host30p2_en: vcc-5v0-host30p2-en { + rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec_5v_pwr_en: typec-5v-pwr-en { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +/* Connected to 5V Fan */ +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm1m1_pins>; + status = "okay"; +}; + +/* Connected to MIPI-DSI0 */ +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2m1_pins>; +}; + +/* Connected to IR Receiver */ +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m0_pins>; + status = "okay"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Shared with UART0 */ +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm4m1_pins>; + status = "disabled"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +&pwm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm5m1_pins>; + status = "okay"; +}; + +/* Connected to Buzzer */ +&pwm8 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm8m0_pins>; + status = "okay"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +&pwm9 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm9m0_pins>; + status = "okay"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Shared with SPI4 */ +&pwm10 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm10m0_pins>; + status = "disabled"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Shared with UART3 */ +&pwm12 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm12m0_pins>; + status = "disabled"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Shared with UART3 */ +&pwm13 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm13m0_pins>; + status = "disabled"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +&pwm14 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm14m0_pins>; + status = "okay"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Optimized for infrared applications */ +&pwm15 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm15m0_pins>; + status = "disabled"; +}; + +/* microSD card */ +&sdmmc { + status = "okay"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Shared with UART4, UART7 and PWM10 */ +&spi0 { + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0m2_cs0 &spi0m2_pins>; + status = "disabled"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Shared with UART8 */ +&spi4 { + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi4m1_cs0 &spi4m1_pins>; + status = "disabled"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Shared with PWM4 */ +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; + status = "disabled"; +}; + +/* Debug UART */ +&uart2 { + status = "okay"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Shared with PWM12 and PWM13 */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3m1_xfer>; + status = "disabled"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Shared with SPI0 */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4m2_xfer>; + status = "disabled"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&uart6m1_xfer>; + status = "okay"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Shared with SPI0 */ +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7m2_xfer>; + status = "disabled"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Shared with SPI4 */ +&uart8 { + pinctrl-names = "default"; + pinctrl-0 = <&uart8m1_xfer>; + status = "disabled"; +}; + +/* USB2 PHY for USB Type-C port */ +/* CM3588 USB Controller Config Table: USB20 OTG0 */ +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + phy-supply = <&vbus_5v0_typec>; + status = "okay"; +}; + +/* USB2 PHY for USB 3.0 Type-A port 1 */ +/* CM3588 USB Controller Config Table: USB20 OTG1 */ +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc_5v0_host_30_p1>; + status = "okay"; +}; + +/* USB2 PHY for USB 2.0 Type-A */ +/* CM3588 USB Controller Config Table: USB20 HOST0 */ +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc_5v0_host_20>; + status = "okay"; +}; + +/* USB2 PHY for USB 3.0 Type-A port 2 */ +/* CM3588 USB Controller Config Table: USB20 HOST1 */ +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc_5v0_host_30_p2>; + status = "okay"; +}; + +/* USB 2.0 Type-A */ +/* PHY: <&u2phy2_host> */ +&usb_host0_ehci { + status = "okay"; +}; + +/* USB 2.0 Type-A */ +/* PHY: <&u2phy2_host> */ +&usb_host0_ohci { + status = "okay"; +}; + +/* USB Type-C */ +/* PHYs: <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3> */ +&usb_host0_xhci { + usb-role-switch; + status = "okay"; + + port { + dwc3_0_role_switch: endpoint { + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +/* Lower USB 3.0 Type-A (port 2) */ +/* PHY: <&u2phy3_host> */ +&usb_host1_ehci { + status = "okay"; +}; + +/* Lower USB 3.0 Type-A (port 2) */ +/* PHY: <&u2phy3_host> */ +&usb_host1_ohci { + status = "okay"; +}; + +/* Upper USB 3.0 Type-A (port 1) */ +/* PHYs: <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3> */ +&usb_host1_xhci { + dr_mode = "host"; + status = "okay"; +}; + +/* Lower USB 3.0 Type-A (port 2) */ +/* PHYs: <&combphy2_psu PHY_TYPE_USB3> */ +&usb_host2_xhci { + status = "okay"; +}; + +/* USB3 PHY for USB Type-C port */ +/* CM3588 USB Controller Config Table: USB30 OTG0 */ +&usbdp_phy0 { + mode-switch; + orientation-switch; + sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +/* USB3 PHY for USB 3.0 Type-A port 1 */ +/* CM3588 USB Controller Config Table: USB30 OTG1 */ +&usbdp_phy1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi new file mode 100644 index 000000000000..e3a9598b99fc --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi @@ -0,0 +1,653 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2023 Thomas McKahan + * Copyright (c) 2024 Sebastian Kropatsch + * + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3588.dtsi" + +/ { + model = "FriendlyElec CM3588"; + compatible = "friendlyarm,cm3588", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + leds { + compatible = "gpio-leds"; + + led_sys: led-0 { + color = <LED_COLOR_ID_AMBER>; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&led_sys_pin>; + }; + + led_usr: led-1 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&led_usr_pin>; + }; + }; + + /* vcc_4v0_sys powers the RK806 and RK860's */ + vcc_4v0_sys: regulator-vcc-4v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_4v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <4000000>; + }; + + vcc_3v3_pcie20: regulator-vcc-3v3-pcie20 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_pcie20"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_3v3_sd_s0: regulator-vcc-3v3-sd-s0 { + compatible = "regulator-fixed"; + gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sd_s0_pwr>; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc_3v3_sd_s0"; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc-1v1-nldo-s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc_4v0_sys>; + }; +}; + +/* Combo PHY 0 is configured to act as as PCIe 2.0 PHY */ +/* Used by PCIe controller 4 (pcie2x1l2) */ +&combphy0_ps { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + sram-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc_4v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc_4v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc_4v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + clock-frequency = <200000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +&i2c7 { + clock-frequency = <200000>; + status = "okay"; + + rt5616: audio-codec@1b { + compatible = "realtek,rt5616"; + reg = <0x1b>; + #sound-dai-cells = <0>; + }; +}; + +&i2s0_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&i2s7_8ch { + status = "okay"; +}; + +&pcie2x1l2 { + /* r8125 ethernet, @fe190000 */ + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_2_rst>; + reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_pcie20>; + status = "okay"; +}; + +&pinctrl { + gpio-leds { + led_sys_pin: led-sys-pin { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + led_usr_pin: led-usr-pin { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: rtc-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pcie { + pcie2_2_rst: pcie2-2-rst { + rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + sd_s0_pwr: sd-s0-pwr { + rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +}; + +/* eMMC */ +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sd; + no-sdio; + non-removable; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vcc_1v8_s3>; + status = "okay"; +}; + +/* microSD card */ +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + no-mmc; + no-sdio; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_sd_s0>; + vqmmc-supply = <&vccio_sd_s0>; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + rk806_single: pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + spi-max-frequency = <1000000>; + system-power-controller; + + vcc1-supply = <&vcc_4v0_sys>; + vcc2-supply = <&vcc_4v0_sys>; + vcc3-supply = <&vcc_4v0_sys>; + vcc4-supply = <&vcc_4v0_sys>; + vcc5-supply = <&vcc_4v0_sys>; + vcc6-supply = <&vcc_4v0_sys>; + vcc7-supply = <&vcc_4v0_sys>; + vcc8-supply = <&vcc_4v0_sys>; + vcc9-supply = <&vcc_4v0_sys>; + vcc10-supply = <&vcc_4v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc_4v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc_4v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + status = "okay"; +}; + +/* Debug UART */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts b/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts index 009566d881f3..230e630820b4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts @@ -376,6 +376,10 @@ status = "okay"; }; +&tsadc { + status = "okay"; +}; + &u2phy2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi new file mode 100644 index 000000000000..0f1a77697351 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/ { + cluster0_opp_table: opp-table-cluster0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <675000 675000 950000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <712500 712500 950000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <762500 762500 950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <850000 850000 950000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <950000 950000 950000>; + clock-latency-ns = <40000>; + }; + }; + + cluster1_opp_table: opp-table-cluster1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <725000 725000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <762500 762500 1000000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <850000 850000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <925000 925000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-microvolt = <987500 987500 1000000>; + clock-latency-ns = <40000>; + }; + opp-2400000000 { + opp-hz = /bits/ 64 <2400000000>; + opp-microvolt = <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + }; + + cluster2_opp_table: opp-table-cluster2 { + compatible = "operating-points-v2"; + opp-shared; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <725000 725000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <762500 762500 1000000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <850000 850000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <925000 925000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-microvolt = <987500 987500 1000000>; + clock-latency-ns = <40000>; + }; + opp-2400000000 { + opp-hz = /bits/ 64 <2400000000>; + opp-microvolt = <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <700000 700000 850000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <750000 750000 850000>; + }; + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <800000 800000 850000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <850000 850000 850000>; + }; + }; +}; + +&cpu_b0 { + operating-points-v2 = <&cluster1_opp_table>; +}; + +&cpu_b1 { + operating-points-v2 = <&cluster1_opp_table>; +}; + +&cpu_b2 { + operating-points-v2 = <&cluster2_opp_table>; +}; + +&cpu_b3 { + operating-points-v2 = <&cluster2_opp_table>; +}; + +&cpu_l0 { + operating-points-v2 = <&cluster0_opp_table>; +}; + +&cpu_l1 { + operating-points-v2 = <&cluster0_opp_table>; +}; + +&cpu_l2 { + operating-points-v2 = <&cluster0_opp_table>; +}; + +&cpu_l3 { + operating-points-v2 = <&cluster0_opp_table>; +}; + +&gpu { + operating-points-v2 = <&gpu_opp_table>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts b/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts index b4f22d95ac0e..baeb08d665c7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts @@ -832,6 +832,8 @@ regulator-name = "vdd_cpu_big1_s0"; regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_big1_mem_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <550000>; regulator-max-microvolt = <1050000>; regulator-ramp-delay = <12500>; @@ -845,6 +847,8 @@ regulator-name = "vdd_cpu_big0_s0"; regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_big0_mem_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <550000>; regulator-max-microvolt = <1050000>; regulator-ramp-delay = <12500>; @@ -858,6 +862,8 @@ regulator-name = "vdd_cpu_lit_s0"; regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_lit_mem_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <550000>; regulator-max-microvolt = <950000>; regulator-ramp-delay = <12500>; @@ -884,6 +890,8 @@ regulator-name = "vdd_cpu_big1_mem_s0"; regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_big1_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <675000>; regulator-max-microvolt = <1050000>; regulator-ramp-delay = <12500>; @@ -898,6 +906,8 @@ regulator-name = "vdd_cpu_big0_mem_s0"; regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_big0_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <675000>; regulator-max-microvolt = <1050000>; regulator-ramp-delay = <12500>; @@ -924,6 +934,8 @@ regulator-name = "vdd_cpu_lit_mem_s0"; regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&vdd_cpu_lit_s0>; + regulator-coupled-max-spread = <10000>; regulator-min-microvolt = <675000>; regulator-max-microvolt = <950000>; regulator-ramp-delay = <12500>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso new file mode 100644 index 000000000000..672d748fcc67 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * DT-overlay to run the PCIe3_4L Dual Mode controller in Endpoint mode + * in the SRNS (Separate Reference Clock No Spread) configuration. + * + * NOTE: If using a setup with two ROCK 5B:s, with one board running in + * RC mode and the other board running in EP mode, see also the device + * tree overlay: rk3588-rock-5b-pcie-srns.dtso. + */ + +/dts-v1/; +/plugin/; + +&pcie30phy { + rockchip,rx-common-refclk-mode = <0 0 0 0>; +}; + +&pcie3x4 { + status = "disabled"; +}; + +&pcie3x4_ep { + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso new file mode 100644 index 000000000000..1a0f1af65c43 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * DT-overlay to run the PCIe3_4L Dual Mode controller in Root Complex + * mode in the SRNS (Separate Reference Clock No Spread) configuration. + * + * This device tree overlay is only needed (on the RC side) when running + * a setup with two ROCK 5B:s, with one board running in RC mode and the + * other board running in EP mode. + */ + +/dts-v1/; +/plugin/; + +&pcie30phy { + rockchip,rx-common-refclk-mode = <0 0 0 0>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index b8e15b76a8a6..d0ba3bf16fc6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -52,7 +52,7 @@ fan: pwm-fan { compatible = "pwm-fan"; - cooling-levels = <0 95 145 195 255>; + cooling-levels = <0 120 150 180 210 240 255>; fan-supply = <&vcc5v0_sys>; pwms = <&pwm1 0 50000 0>; #cooling-cells = <2>; @@ -65,6 +65,13 @@ shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; }; + rfkill-bt { + compatible = "rfkill-gpio"; + label = "rfkill-m2-bt"; + radio-type = "bluetooth"; + shutdown-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + }; + vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -279,6 +286,36 @@ }; }; +&package_thermal { + polling-delay = <1000>; + + trips { + package_fan0: package-fan0 { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + + package_fan1: package-fan1 { + temperature = <65000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map1 { + trip = <&package_fan0>; + cooling-device = <&fan THERMAL_NO_LIMIT 1>; + }; + + map2 { + trip = <&package_fan1>; + cooling-device = <&fan 2 THERMAL_NO_LIMIT>; + }; + }; +}; + &pcie2x1l0 { pinctrl-names = "default"; pinctrl-0 = <&pcie2_0_rst>; @@ -411,6 +448,20 @@ status = "okay"; }; +&sfc { + pinctrl-names = "default"; + pinctrl-0 = <&fspim2_pins>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + &uart6 { pinctrl-names = "default"; pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>; @@ -742,6 +793,10 @@ }; }; +&tsadc { + status = "okay"; +}; + &uart2 { pinctrl-0 = <&uart2m0_xfer>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts index 9090c5c99f2a..d0021524e7f9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts @@ -648,6 +648,10 @@ }; }; +&tsadc { + status = "okay"; +}; + &u2phy2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi index 6b9206ce4a03..77bcf0f6b028 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi @@ -601,6 +601,10 @@ }; }; +&tsadc { + status = "okay"; +}; + &uart2 { pinctrl-0 = <&uart2m0_xfer>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi index 5984016b5f96..7462cc1e1007 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -1,413 +1,8 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * */ -#include "rk3588s.dtsi" -#include "rk3588-pinctrl.dtsi" - -/ { - usb_host1_xhci: usb@fc400000 { - compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; - reg = <0x0 0xfc400000 0x0 0x400000>; - interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, - <&cru ACLK_USB3OTG1>; - clock-names = "ref_clk", "suspend_clk", "bus_clk"; - dr_mode = "otg"; - phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>; - phy-names = "usb2-phy", "usb3-phy"; - phy_type = "utmi_wide"; - power-domains = <&power RK3588_PD_USB>; - resets = <&cru SRST_A_USB3OTG1>; - snps,dis_enblslpm_quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; - status = "disabled"; - }; - - pcie30_phy_grf: syscon@fd5b8000 { - compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; - reg = <0x0 0xfd5b8000 0x0 0x10000>; - }; - - pipe_phy1_grf: syscon@fd5c0000 { - compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; - reg = <0x0 0xfd5c0000 0x0 0x100>; - }; - - usbdpphy1_grf: syscon@fd5cc000 { - compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; - reg = <0x0 0xfd5cc000 0x0 0x4000>; - }; - - usb2phy1_grf: syscon@fd5d4000 { - compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; - reg = <0x0 0xfd5d4000 0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy1: usb2phy@4000 { - compatible = "rockchip,rk3588-usb2phy"; - reg = <0x4000 0x10>; - #clock-cells = <0>; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy1"; - interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>; - resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; - reset-names = "phy", "apb"; - status = "disabled"; - - u2phy1_otg: otg-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - i2s8_8ch: i2s@fddc8000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfddc8000 0x0 0x1000>; - interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac2 22>; - dma-names = "tx"; - power-domains = <&power RK3588_PD_VO0>; - resets = <&cru SRST_M_I2S8_8CH_TX>; - reset-names = "tx-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s6_8ch: i2s@fddf4000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfddf4000 0x0 0x1000>; - interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac2 4>; - dma-names = "tx"; - power-domains = <&power RK3588_PD_VO1>; - resets = <&cru SRST_M_I2S6_8CH_TX>; - reset-names = "tx-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s7_8ch: i2s@fddf8000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfddf8000 0x0 0x1000>; - interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac2 21>; - dma-names = "rx"; - power-domains = <&power RK3588_PD_VO1>; - resets = <&cru SRST_M_I2S7_8CH_RX>; - reset-names = "rx-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s10_8ch: i2s@fde00000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfde00000 0x0 0x1000>; - interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac2 24>; - dma-names = "rx"; - power-domains = <&power RK3588_PD_VO1>; - resets = <&cru SRST_M_I2S10_8CH_RX>; - reset-names = "rx-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - pcie3x4: pcie@fe150000 { - compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0x0f>; - clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, - <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, - <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", - "aux", "pipe"; - device_type = "pci"; - interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "sys", "pmc", "msg", "legacy", "err"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, - <0 0 0 2 &pcie3x4_intc 1>, - <0 0 0 3 &pcie3x4_intc 2>, - <0 0 0 4 &pcie3x4_intc 3>; - linux,pci-domain = <0>; - max-link-speed = <3>; - msi-map = <0x0000 &its1 0x0000 0x1000>; - num-lanes = <4>; - phys = <&pcie30phy>; - phy-names = "pcie-phy"; - power-domains = <&power RK3588_PD_PCIE>; - ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, - <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>; - reg = <0xa 0x40000000 0x0 0x00400000>, - <0x0 0xfe150000 0x0 0x00010000>, - <0x0 0xf0000000 0x0 0x00100000>; - reg-names = "dbi", "apb", "config"; - resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; - reset-names = "pwr", "pipe"; - status = "disabled"; - - pcie3x4_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>; - }; - }; - - pcie3x2: pcie@fe160000 { - compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x10 0x1f>; - clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, - <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, - <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", - "aux", "pipe"; - device_type = "pci"; - interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "sys", "pmc", "msg", "legacy", "err"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, - <0 0 0 2 &pcie3x2_intc 1>, - <0 0 0 3 &pcie3x2_intc 2>, - <0 0 0 4 &pcie3x2_intc 3>; - linux,pci-domain = <1>; - max-link-speed = <3>; - msi-map = <0x1000 &its1 0x1000 0x1000>; - num-lanes = <2>; - phys = <&pcie30phy>; - phy-names = "pcie-phy"; - power-domains = <&power RK3588_PD_PCIE>; - ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>, - <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>; - reg = <0xa 0x40400000 0x0 0x00400000>, - <0x0 0xfe160000 0x0 0x00010000>, - <0x0 0xf1000000 0x0 0x00100000>; - reg-names = "dbi", "apb", "config"; - resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; - reset-names = "pwr", "pipe"; - status = "disabled"; - - pcie3x2_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>; - }; - }; - - pcie2x1l0: pcie@fe170000 { - compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; - bus-range = <0x20 0x2f>; - clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>, - <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>, - <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", - "aux", "pipe"; - device_type = "pci"; - interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "sys", "pmc", "msg", "legacy", "err"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>, - <0 0 0 2 &pcie2x1l0_intc 1>, - <0 0 0 3 &pcie2x1l0_intc 2>, - <0 0 0 4 &pcie2x1l0_intc 3>; - linux,pci-domain = <2>; - max-link-speed = <2>; - msi-map = <0x2000 &its0 0x2000 0x1000>; - num-lanes = <1>; - phys = <&combphy1_ps PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - power-domains = <&power RK3588_PD_PCIE>; - ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, - <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>; - reg = <0xa 0x40800000 0x0 0x00400000>, - <0x0 0xfe170000 0x0 0x00010000>, - <0x0 0xf2000000 0x0 0x00100000>; - reg-names = "dbi", "apb", "config"; - resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>; - reset-names = "pwr", "pipe"; - #address-cells = <3>; - #size-cells = <2>; - status = "disabled"; - - pcie2x1l0_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>; - }; - }; - - gmac0: ethernet@fe1b0000 { - compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; - reg = <0x0 0xfe1b0000 0x0 0x10000>; - interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "macirq", "eth_wake_irq"; - clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, - <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, - <&cru CLK_GMAC0_PTP_REF>; - clock-names = "stmmaceth", "clk_mac_ref", - "pclk_mac", "aclk_mac", - "ptp_ref"; - power-domains = <&power RK3588_PD_GMAC>; - resets = <&cru SRST_A_GMAC0>; - reset-names = "stmmaceth"; - rockchip,grf = <&sys_grf>; - rockchip,php-grf = <&php_grf>; - snps,axi-config = <&gmac0_stmmac_axi_setup>; - snps,mixed-burst; - snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; - snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; - snps,tso; - status = "disabled"; - - mdio0: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <0x1>; - #size-cells = <0x0>; - }; - - gmac0_stmmac_axi_setup: stmmac-axi-config { - snps,blen = <0 0 0 0 16 8 4>; - snps,wr_osr_lmt = <4>; - snps,rd_osr_lmt = <8>; - }; - - gmac0_mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <2>; - queue0 {}; - queue1 {}; - }; - - gmac0_mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <2>; - queue0 {}; - queue1 {}; - }; - }; - - sata1: sata@fe220000 { - compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; - reg = <0 0xfe220000 0 0x1000>; - interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, - <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>, - <&cru CLK_PIPEPHY1_PIPE_ASIC_G>; - clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; - ports-implemented = <0x1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata-port@0 { - reg = <0>; - hba-port-cap = <HBA_PORT_FBSCP>; - phys = <&combphy1_ps PHY_TYPE_SATA>; - phy-names = "sata-phy"; - snps,rx-ts-max = <32>; - snps,tx-ts-max = <32>; - }; - }; - - usbdp_phy1: phy@fed90000 { - compatible = "rockchip,rk3588-usbdp-phy"; - reg = <0x0 0xfed90000 0x0 0x10000>; - #phy-cells = <1>; - clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, - <&cru CLK_USBDP_PHY1_IMMORTAL>, - <&cru PCLK_USBDPPHY1>, - <&u2phy1>; - clock-names = "refclk", "immortal", "pclk", "utmi"; - resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>, - <&cru SRST_USBDP_COMBO_PHY1_CMN>, - <&cru SRST_USBDP_COMBO_PHY1_LANE>, - <&cru SRST_USBDP_COMBO_PHY1_PCS>, - <&cru SRST_P_USBDPPHY1>; - reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; - rockchip,u2phy-grf = <&usb2phy1_grf>; - rockchip,usb-grf = <&usb_grf>; - rockchip,usbdpphy-grf = <&usbdpphy1_grf>; - rockchip,vo-grf = <&vo0_grf>; - status = "disabled"; - }; - - combphy1_ps: phy@fee10000 { - compatible = "rockchip,rk3588-naneng-combphy"; - reg = <0x0 0xfee10000 0x0 0x100>; - clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>, - <&cru PCLK_PHP_ROOT>; - clock-names = "ref", "apb", "pipe"; - assigned-clocks = <&cru CLK_REF_PIPE_PHY1>; - assigned-clock-rates = <100000000>; - #phy-cells = <1>; - resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>; - reset-names = "phy", "apb"; - rockchip,pipe-grf = <&php_grf>; - rockchip,pipe-phy-grf = <&pipe_phy1_grf>; - status = "disabled"; - }; - - pcie30phy: phy@fee80000 { - compatible = "rockchip,rk3588-pcie3-phy"; - reg = <0x0 0xfee80000 0x0 0x20000>; - #phy-cells = <0>; - clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>; - clock-names = "pclk"; - resets = <&cru SRST_PCIE30_PHY>; - reset-names = "phy"; - rockchip,pipe-grf = <&php_grf>; - rockchip,phy-grf = <&pcie30_phy_grf>; - status = "disabled"; - }; -}; +#include "rk3588-extra.dtsi" +#include "rk3588-opp.dtsi" diff --git a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi index 38b9dbf38a21..bce72bac4503 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi @@ -4,4 +4,145 @@ * */ -#include "rk3588.dtsi" +#include "rk3588-extra.dtsi" + +/ { + cluster0_opp_table: opp-table-cluster0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <887500 887500 950000>; + clock-latency-ns = <40000>; + }; + opp-1704000000 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <937500 937500 950000>; + clock-latency-ns = <40000>; + }; + }; + + cluster1_opp_table: opp-table-cluster1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <787500 787500 950000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <875000 875000 950000>; + clock-latency-ns = <40000>; + }; + opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <950000 950000 950000>; + clock-latency-ns = <40000>; + }; + }; + + cluster2_opp_table: opp-table-cluster2 { + compatible = "operating-points-v2"; + opp-shared; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <787500 787500 950000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <875000 875000 950000>; + clock-latency-ns = <40000>; + }; + opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <950000 950000 950000>; + clock-latency-ns = <40000>; + }; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <750000 750000 850000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <750000 750000 850000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <750000 750000 850000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <750000 750000 850000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <750000 750000 850000>; + }; + opp-850000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <787500 787500 850000>; + }; + }; +}; + +&cpu_b0 { + operating-points-v2 = <&cluster1_opp_table>; +}; + +&cpu_b1 { + operating-points-v2 = <&cluster1_opp_table>; +}; + +&cpu_b2 { + operating-points-v2 = <&cluster2_opp_table>; +}; + +&cpu_b3 { + operating-points-v2 = <&cluster2_opp_table>; +}; + +&cpu_l0 { + operating-points-v2 = <&cluster0_opp_table>; +}; + +&cpu_l1 { + operating-points-v2 = <&cluster0_opp_table>; +}; + +&cpu_l2 { + operating-points-v2 = <&cluster0_opp_table>; +}; + +&cpu_l3 { + operating-points-v2 = <&cluster0_opp_table>; +}; + +&gpu { + operating-points-v2 = <&gpu_opp_table>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts index 8e2a07612d17..4cc1790ebd08 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts @@ -376,6 +376,19 @@ status = "okay"; }; +&sfc { + pinctrl-names = "default"; + pinctrl-0 = <&fspim0_pins>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + &spi2 { status = "okay"; assigned-clocks = <&cru CLK_SPI2>; @@ -697,6 +710,10 @@ }; }; +&tsadc { + status = "okay"; +}; + &u2phy0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 6ac5ac8b48ab..c7fecf8fe7ec 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -1,2670 +1,8 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * */ -#include <dt-bindings/clock/rockchip,rk3588-cru.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/power/rk3588-power.h> -#include <dt-bindings/reset/rockchip,rk3588-cru.h> -#include <dt-bindings/phy/phy.h> -#include <dt-bindings/ata/ahci.h> - -/ { - compatible = "rockchip,rk3588"; - - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - serial6 = &uart6; - serial7 = &uart7; - serial8 = &uart8; - serial9 = &uart9; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - spi3 = &spi3; - spi4 = &spi4; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu_l0>; - }; - core1 { - cpu = <&cpu_l1>; - }; - core2 { - cpu = <&cpu_l2>; - }; - core3 { - cpu = <&cpu_l3>; - }; - }; - cluster1 { - core0 { - cpu = <&cpu_b0>; - }; - core1 { - cpu = <&cpu_b1>; - }; - }; - cluster2 { - core0 { - cpu = <&cpu_b2>; - }; - core1 { - cpu = <&cpu_b3>; - }; - }; - }; - - cpu_l0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0>; - enable-method = "psci"; - capacity-dmips-mhz = <530>; - clocks = <&scmi_clk SCMI_CLK_CPUL>; - assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; - assigned-clock-rates = <816000000>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <32768>; - i-cache-line-size = <64>; - i-cache-sets = <128>; - d-cache-size = <32768>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&l2_cache_l0>; - dynamic-power-coefficient = <228>; - #cooling-cells = <2>; - }; - - cpu_l1: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x100>; - enable-method = "psci"; - capacity-dmips-mhz = <530>; - clocks = <&scmi_clk SCMI_CLK_CPUL>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <32768>; - i-cache-line-size = <64>; - i-cache-sets = <128>; - d-cache-size = <32768>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&l2_cache_l1>; - dynamic-power-coefficient = <228>; - #cooling-cells = <2>; - }; - - cpu_l2: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x200>; - enable-method = "psci"; - capacity-dmips-mhz = <530>; - clocks = <&scmi_clk SCMI_CLK_CPUL>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <32768>; - i-cache-line-size = <64>; - i-cache-sets = <128>; - d-cache-size = <32768>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&l2_cache_l2>; - dynamic-power-coefficient = <228>; - #cooling-cells = <2>; - }; - - cpu_l3: cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x300>; - enable-method = "psci"; - capacity-dmips-mhz = <530>; - clocks = <&scmi_clk SCMI_CLK_CPUL>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <32768>; - i-cache-line-size = <64>; - i-cache-sets = <128>; - d-cache-size = <32768>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&l2_cache_l3>; - dynamic-power-coefficient = <228>; - #cooling-cells = <2>; - }; - - cpu_b0: cpu@400 { - device_type = "cpu"; - compatible = "arm,cortex-a76"; - reg = <0x400>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk SCMI_CLK_CPUB01>; - assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; - assigned-clock-rates = <816000000>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <65536>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_cache_b0>; - dynamic-power-coefficient = <416>; - #cooling-cells = <2>; - }; - - cpu_b1: cpu@500 { - device_type = "cpu"; - compatible = "arm,cortex-a76"; - reg = <0x500>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk SCMI_CLK_CPUB01>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <65536>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_cache_b1>; - dynamic-power-coefficient = <416>; - #cooling-cells = <2>; - }; - - cpu_b2: cpu@600 { - device_type = "cpu"; - compatible = "arm,cortex-a76"; - reg = <0x600>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk SCMI_CLK_CPUB23>; - assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; - assigned-clock-rates = <816000000>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <65536>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_cache_b2>; - dynamic-power-coefficient = <416>; - #cooling-cells = <2>; - }; - - cpu_b3: cpu@700 { - device_type = "cpu"; - compatible = "arm,cortex-a76"; - reg = <0x700>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk SCMI_CLK_CPUB23>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <65536>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_cache_b3>; - dynamic-power-coefficient = <416>; - #cooling-cells = <2>; - }; - - idle-states { - entry-method = "psci"; - CPU_SLEEP: cpu-sleep { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <100>; - exit-latency-us = <120>; - min-residency-us = <1000>; - }; - }; - - l2_cache_l0: l2-cache-l0 { - compatible = "cache"; - cache-size = <131072>; - cache-line-size = <64>; - cache-sets = <512>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_l1: l2-cache-l1 { - compatible = "cache"; - cache-size = <131072>; - cache-line-size = <64>; - cache-sets = <512>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_l2: l2-cache-l2 { - compatible = "cache"; - cache-size = <131072>; - cache-line-size = <64>; - cache-sets = <512>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_l3: l2-cache-l3 { - compatible = "cache"; - cache-size = <131072>; - cache-line-size = <64>; - cache-sets = <512>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_b0: l2-cache-b0 { - compatible = "cache"; - cache-size = <524288>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_b1: l2-cache-b1 { - compatible = "cache"; - cache-size = <524288>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_b2: l2-cache-b2 { - compatible = "cache"; - cache-size = <524288>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_b3: l2-cache-b3 { - compatible = "cache"; - cache-size = <524288>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l3_cache: l3-cache { - compatible = "cache"; - cache-size = <3145728>; - cache-line-size = <64>; - cache-sets = <4096>; - cache-level = <3>; - cache-unified; - }; - }; - - display_subsystem: display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop_out>; - }; - - firmware { - optee: optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - - scmi: scmi { - compatible = "arm,scmi-smc"; - arm,smc-id = <0x82000010>; - shmem = <&scmi_shmem>; - #address-cells = <1>; - #size-cells = <0>; - - scmi_clk: protocol@14 { - reg = <0x14>; - #clock-cells = <1>; - }; - - scmi_reset: protocol@16 { - reg = <0x16>; - #reset-cells = <1>; - }; - }; - }; - - pmu-a55 { - compatible = "arm,cortex-a55-pmu"; - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>; - }; - - pmu-a76 { - compatible = "arm,cortex-a76-pmu"; - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - spll: clock-0 { - compatible = "fixed-clock"; - clock-frequency = <702000000>; - clock-output-names = "spll"; - #clock-cells = <0>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; - }; - - xin24m: clock-1 { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - xin32k: clock-2 { - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - #clock-cells = <0>; - }; - - pmu_sram: sram@10f000 { - compatible = "mmio-sram"; - reg = <0x0 0x0010f000 0x0 0x100>; - ranges = <0 0x0 0x0010f000 0x100>; - #address-cells = <1>; - #size-cells = <1>; - - scmi_shmem: sram@0 { - compatible = "arm,scmi-shmem"; - reg = <0x0 0x100>; - }; - }; - - gpu: gpu@fb000000 { - compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; - reg = <0x0 0xfb000000 0x0 0x200000>; - #cooling-cells = <2>; - assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; - assigned-clock-rates = <200000000>; - clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, - <&cru CLK_GPU_STACKS>; - clock-names = "core", "coregroup", "stacks"; - dynamic-power-coefficient = <2982>; - interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "job", "mmu", "gpu"; - operating-points-v2 = <&gpu_opp_table>; - power-domains = <&power RK3588_PD_GPU>; - status = "disabled"; - - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <700000 700000 850000>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <750000 750000 850000>; - }; - opp-900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <800000 800000 850000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <850000 850000 850000>; - }; - }; - }; - - usb_host0_xhci: usb@fc000000 { - compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; - reg = <0x0 0xfc000000 0x0 0x400000>; - interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, - <&cru ACLK_USB3OTG0>; - clock-names = "ref_clk", "suspend_clk", "bus_clk"; - dr_mode = "otg"; - phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>; - phy-names = "usb2-phy", "usb3-phy"; - phy_type = "utmi_wide"; - power-domains = <&power RK3588_PD_USB>; - resets = <&cru SRST_A_USB3OTG0>; - snps,dis_enblslpm_quirk; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; - status = "disabled"; - }; - - usb_host0_ehci: usb@fc800000 { - compatible = "rockchip,rk3588-ehci", "generic-ehci"; - reg = <0x0 0xfc800000 0x0 0x40000>; - interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; - phys = <&u2phy2_host>; - phy-names = "usb"; - power-domains = <&power RK3588_PD_USB>; - status = "disabled"; - }; - - usb_host0_ohci: usb@fc840000 { - compatible = "rockchip,rk3588-ohci", "generic-ohci"; - reg = <0x0 0xfc840000 0x0 0x40000>; - interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; - phys = <&u2phy2_host>; - phy-names = "usb"; - power-domains = <&power RK3588_PD_USB>; - status = "disabled"; - }; - - usb_host1_ehci: usb@fc880000 { - compatible = "rockchip,rk3588-ehci", "generic-ehci"; - reg = <0x0 0xfc880000 0x0 0x40000>; - interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; - phys = <&u2phy3_host>; - phy-names = "usb"; - power-domains = <&power RK3588_PD_USB>; - status = "disabled"; - }; - - usb_host1_ohci: usb@fc8c0000 { - compatible = "rockchip,rk3588-ohci", "generic-ohci"; - reg = <0x0 0xfc8c0000 0x0 0x40000>; - interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; - phys = <&u2phy3_host>; - phy-names = "usb"; - power-domains = <&power RK3588_PD_USB>; - status = "disabled"; - }; - - usb_host2_xhci: usb@fcd00000 { - compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; - reg = <0x0 0xfcd00000 0x0 0x400000>; - interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, - <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, - <&cru CLK_PIPEPHY2_PIPE_U3_G>; - clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe"; - dr_mode = "host"; - phys = <&combphy2_psu PHY_TYPE_USB3>; - phy-names = "usb3-phy"; - phy_type = "utmi_wide"; - resets = <&cru SRST_A_USB3OTG2>; - snps,dis_enblslpm_quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; - snps,dis_rxdet_inp3_quirk; - status = "disabled"; - }; - - mmu600_pcie: iommu@fc900000 { - compatible = "arm,smmu-v3"; - reg = <0x0 0xfc900000 0x0 0x200000>; - interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; - #iommu-cells = <1>; - status = "disabled"; - }; - - mmu600_php: iommu@fcb00000 { - compatible = "arm,smmu-v3"; - reg = <0x0 0xfcb00000 0x0 0x200000>; - interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; - #iommu-cells = <1>; - status = "disabled"; - }; - - pmu1grf: syscon@fd58a000 { - compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; - reg = <0x0 0xfd58a000 0x0 0x10000>; - }; - - sys_grf: syscon@fd58c000 { - compatible = "rockchip,rk3588-sys-grf", "syscon"; - reg = <0x0 0xfd58c000 0x0 0x1000>; - }; - - vop_grf: syscon@fd5a4000 { - compatible = "rockchip,rk3588-vop-grf", "syscon"; - reg = <0x0 0xfd5a4000 0x0 0x2000>; - }; - - vo0_grf: syscon@fd5a6000 { - compatible = "rockchip,rk3588-vo-grf", "syscon"; - reg = <0x0 0xfd5a6000 0x0 0x2000>; - clocks = <&cru PCLK_VO0GRF>; - }; - - vo1_grf: syscon@fd5a8000 { - compatible = "rockchip,rk3588-vo-grf", "syscon"; - reg = <0x0 0xfd5a8000 0x0 0x100>; - clocks = <&cru PCLK_VO1GRF>; - }; - - usb_grf: syscon@fd5ac000 { - compatible = "rockchip,rk3588-usb-grf", "syscon"; - reg = <0x0 0xfd5ac000 0x0 0x4000>; - }; - - php_grf: syscon@fd5b0000 { - compatible = "rockchip,rk3588-php-grf", "syscon"; - reg = <0x0 0xfd5b0000 0x0 0x1000>; - }; - - pipe_phy0_grf: syscon@fd5bc000 { - compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; - reg = <0x0 0xfd5bc000 0x0 0x100>; - }; - - pipe_phy2_grf: syscon@fd5c4000 { - compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; - reg = <0x0 0xfd5c4000 0x0 0x100>; - }; - - usbdpphy0_grf: syscon@fd5c8000 { - compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; - reg = <0x0 0xfd5c8000 0x0 0x4000>; - }; - - usb2phy0_grf: syscon@fd5d0000 { - compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; - reg = <0x0 0xfd5d0000 0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy0: usb2phy@0 { - compatible = "rockchip,rk3588-usb2phy"; - reg = <0x0 0x10>; - #clock-cells = <0>; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy0"; - interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>; - resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; - reset-names = "phy", "apb"; - status = "disabled"; - - u2phy0_otg: otg-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - usb2phy2_grf: syscon@fd5d8000 { - compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; - reg = <0x0 0xfd5d8000 0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy2: usb2phy@8000 { - compatible = "rockchip,rk3588-usb2phy"; - reg = <0x8000 0x10>; - #clock-cells = <0>; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy2"; - interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>; - resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; - reset-names = "phy", "apb"; - status = "disabled"; - - u2phy2_host: host-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - usb2phy3_grf: syscon@fd5dc000 { - compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; - reg = <0x0 0xfd5dc000 0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy3: usb2phy@c000 { - compatible = "rockchip,rk3588-usb2phy"; - reg = <0xc000 0x10>; - #clock-cells = <0>; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy3"; - interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>; - resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; - reset-names = "phy", "apb"; - status = "disabled"; - - u2phy3_host: host-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - hdptxphy0_grf: syscon@fd5e0000 { - compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; - reg = <0x0 0xfd5e0000 0x0 0x100>; - }; - - ioc: syscon@fd5f0000 { - compatible = "rockchip,rk3588-ioc", "syscon"; - reg = <0x0 0xfd5f0000 0x0 0x10000>; - }; - - system_sram1: sram@fd600000 { - compatible = "mmio-sram"; - reg = <0x0 0xfd600000 0x0 0x100000>; - ranges = <0x0 0x0 0xfd600000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - cru: clock-controller@fd7c0000 { - compatible = "rockchip,rk3588-cru"; - reg = <0x0 0xfd7c0000 0x0 0x5c000>; - assigned-clocks = - <&cru PLL_PPLL>, <&cru PLL_AUPLL>, - <&cru PLL_NPLL>, <&cru PLL_GPLL>, - <&cru ACLK_CENTER_ROOT>, - <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, - <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, - <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, - <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>, - <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, - <&cru CLK_GPU>; - assigned-clock-rates = - <1100000000>, <786432000>, - <850000000>, <1188000000>, - <702000000>, - <400000000>, <500000000>, - <800000000>, <100000000>, - <400000000>, <100000000>, - <200000000>, <500000000>, - <375000000>, <150000000>, - <200000000>; - rockchip,grf = <&php_grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - i2c0: i2c@fd880000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfd880000 0x0 0x1000>; - interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; - clock-names = "i2c", "pclk"; - pinctrl-0 = <&i2c0m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart0: serial@fd890000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfd890000 0x0 0x100>; - interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 6>, <&dmac0 7>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart0m1_xfer>; - pinctrl-names = "default"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - pwm0: pwm@fd8b0000 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfd8b0000 0x0 0x10>; - clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm0m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm1: pwm@fd8b0010 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfd8b0010 0x0 0x10>; - clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm1m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm2: pwm@fd8b0020 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfd8b0020 0x0 0x10>; - clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm2m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm3: pwm@fd8b0030 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfd8b0030 0x0 0x10>; - clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm3m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pmu: power-management@fd8d8000 { - compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; - reg = <0x0 0xfd8d8000 0x0 0x400>; - - power: power-controller { - compatible = "rockchip,rk3588-power-controller"; - #address-cells = <1>; - #power-domain-cells = <1>; - #size-cells = <0>; - status = "okay"; - - /* These power domains are grouped by VD_NPU */ - power-domain@RK3588_PD_NPU { - reg = <RK3588_PD_NPU>; - #power-domain-cells = <0>; - #address-cells = <1>; - #size-cells = <0>; - - power-domain@RK3588_PD_NPUTOP { - reg = <RK3588_PD_NPUTOP>; - clocks = <&cru HCLK_NPU_ROOT>, - <&cru PCLK_NPU_ROOT>, - <&cru CLK_NPU_DSU0>, - <&cru HCLK_NPU_CM0_ROOT>; - pm_qos = <&qos_npu0_mwr>, - <&qos_npu0_mro>, - <&qos_mcu_npu>; - #power-domain-cells = <0>; - #address-cells = <1>; - #size-cells = <0>; - - power-domain@RK3588_PD_NPU1 { - reg = <RK3588_PD_NPU1>; - clocks = <&cru HCLK_NPU_ROOT>, - <&cru PCLK_NPU_ROOT>, - <&cru CLK_NPU_DSU0>; - pm_qos = <&qos_npu1>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_NPU2 { - reg = <RK3588_PD_NPU2>; - clocks = <&cru HCLK_NPU_ROOT>, - <&cru PCLK_NPU_ROOT>, - <&cru CLK_NPU_DSU0>; - pm_qos = <&qos_npu2>; - #power-domain-cells = <0>; - }; - }; - }; - /* These power domains are grouped by VD_GPU */ - power-domain@RK3588_PD_GPU { - reg = <RK3588_PD_GPU>; - clocks = <&cru CLK_GPU>, - <&cru CLK_GPU_COREGROUP>, - <&cru CLK_GPU_STACKS>; - pm_qos = <&qos_gpu_m0>, - <&qos_gpu_m1>, - <&qos_gpu_m2>, - <&qos_gpu_m3>; - #power-domain-cells = <0>; - }; - /* These power domains are grouped by VD_VCODEC */ - power-domain@RK3588_PD_VCODEC { - reg = <RK3588_PD_VCODEC>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - power-domain@RK3588_PD_RKVDEC0 { - reg = <RK3588_PD_RKVDEC0>; - clocks = <&cru HCLK_RKVDEC0>, - <&cru HCLK_VDPU_ROOT>, - <&cru ACLK_VDPU_ROOT>, - <&cru ACLK_RKVDEC0>, - <&cru ACLK_RKVDEC_CCU>; - pm_qos = <&qos_rkvdec0>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_RKVDEC1 { - reg = <RK3588_PD_RKVDEC1>; - clocks = <&cru HCLK_RKVDEC1>, - <&cru HCLK_VDPU_ROOT>, - <&cru ACLK_VDPU_ROOT>, - <&cru ACLK_RKVDEC1>; - pm_qos = <&qos_rkvdec1>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_VENC0 { - reg = <RK3588_PD_VENC0>; - clocks = <&cru HCLK_RKVENC0>, - <&cru ACLK_RKVENC0>; - pm_qos = <&qos_rkvenc0_m0ro>, - <&qos_rkvenc0_m1ro>, - <&qos_rkvenc0_m2wo>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - power-domain@RK3588_PD_VENC1 { - reg = <RK3588_PD_VENC1>; - clocks = <&cru HCLK_RKVENC1>, - <&cru HCLK_RKVENC0>, - <&cru ACLK_RKVENC0>, - <&cru ACLK_RKVENC1>; - pm_qos = <&qos_rkvenc1_m0ro>, - <&qos_rkvenc1_m1ro>, - <&qos_rkvenc1_m2wo>; - #power-domain-cells = <0>; - }; - }; - }; - /* These power domains are grouped by VD_LOGIC */ - power-domain@RK3588_PD_VDPU { - reg = <RK3588_PD_VDPU>; - clocks = <&cru HCLK_VDPU_ROOT>, - <&cru ACLK_VDPU_LOW_ROOT>, - <&cru ACLK_VDPU_ROOT>, - <&cru ACLK_JPEG_DECODER_ROOT>, - <&cru ACLK_IEP2P0>, - <&cru HCLK_IEP2P0>, - <&cru ACLK_JPEG_ENCODER0>, - <&cru HCLK_JPEG_ENCODER0>, - <&cru ACLK_JPEG_ENCODER1>, - <&cru HCLK_JPEG_ENCODER1>, - <&cru ACLK_JPEG_ENCODER2>, - <&cru HCLK_JPEG_ENCODER2>, - <&cru ACLK_JPEG_ENCODER3>, - <&cru HCLK_JPEG_ENCODER3>, - <&cru ACLK_JPEG_DECODER>, - <&cru HCLK_JPEG_DECODER>, - <&cru ACLK_RGA2>, - <&cru HCLK_RGA2>; - pm_qos = <&qos_iep>, - <&qos_jpeg_dec>, - <&qos_jpeg_enc0>, - <&qos_jpeg_enc1>, - <&qos_jpeg_enc2>, - <&qos_jpeg_enc3>, - <&qos_rga2_mro>, - <&qos_rga2_mwo>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - - power-domain@RK3588_PD_AV1 { - reg = <RK3588_PD_AV1>; - clocks = <&cru PCLK_AV1>, - <&cru ACLK_AV1>, - <&cru HCLK_VDPU_ROOT>; - pm_qos = <&qos_av1>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_RKVDEC0 { - reg = <RK3588_PD_RKVDEC0>; - clocks = <&cru HCLK_RKVDEC0>, - <&cru HCLK_VDPU_ROOT>, - <&cru ACLK_VDPU_ROOT>, - <&cru ACLK_RKVDEC0>; - pm_qos = <&qos_rkvdec0>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_RKVDEC1 { - reg = <RK3588_PD_RKVDEC1>; - clocks = <&cru HCLK_RKVDEC1>, - <&cru HCLK_VDPU_ROOT>, - <&cru ACLK_VDPU_ROOT>; - pm_qos = <&qos_rkvdec1>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_RGA30 { - reg = <RK3588_PD_RGA30>; - clocks = <&cru ACLK_RGA3_0>, - <&cru HCLK_RGA3_0>; - pm_qos = <&qos_rga3_0>; - #power-domain-cells = <0>; - }; - }; - power-domain@RK3588_PD_VOP { - reg = <RK3588_PD_VOP>; - clocks = <&cru PCLK_VOP_ROOT>, - <&cru HCLK_VOP_ROOT>, - <&cru ACLK_VOP>; - pm_qos = <&qos_vop_m0>, - <&qos_vop_m1>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - power-domain@RK3588_PD_VO0 { - reg = <RK3588_PD_VO0>; - clocks = <&cru PCLK_VO0_ROOT>, - <&cru PCLK_VO0_S_ROOT>, - <&cru HCLK_VO0_S_ROOT>, - <&cru ACLK_VO0_ROOT>, - <&cru HCLK_HDCP0>, - <&cru ACLK_HDCP0>, - <&cru HCLK_VOP_ROOT>; - pm_qos = <&qos_hdcp0>; - #power-domain-cells = <0>; - }; - }; - power-domain@RK3588_PD_VO1 { - reg = <RK3588_PD_VO1>; - clocks = <&cru PCLK_VO1_ROOT>, - <&cru PCLK_VO1_S_ROOT>, - <&cru HCLK_VO1_S_ROOT>, - <&cru HCLK_HDCP1>, - <&cru ACLK_HDCP1>, - <&cru ACLK_HDMIRX_ROOT>, - <&cru HCLK_VO1USB_TOP_ROOT>; - pm_qos = <&qos_hdcp1>, - <&qos_hdmirx>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_VI { - reg = <RK3588_PD_VI>; - clocks = <&cru HCLK_VI_ROOT>, - <&cru PCLK_VI_ROOT>, - <&cru HCLK_ISP0>, - <&cru ACLK_ISP0>, - <&cru HCLK_VICAP>, - <&cru ACLK_VICAP>; - pm_qos = <&qos_isp0_mro>, - <&qos_isp0_mwo>, - <&qos_vicap_m0>, - <&qos_vicap_m1>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - power-domain@RK3588_PD_ISP1 { - reg = <RK3588_PD_ISP1>; - clocks = <&cru HCLK_ISP1>, - <&cru ACLK_ISP1>, - <&cru HCLK_VI_ROOT>, - <&cru PCLK_VI_ROOT>; - pm_qos = <&qos_isp1_mwo>, - <&qos_isp1_mro>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_FEC { - reg = <RK3588_PD_FEC>; - clocks = <&cru HCLK_FISHEYE0>, - <&cru ACLK_FISHEYE0>, - <&cru HCLK_FISHEYE1>, - <&cru ACLK_FISHEYE1>, - <&cru PCLK_VI_ROOT>; - pm_qos = <&qos_fisheye0>, - <&qos_fisheye1>; - #power-domain-cells = <0>; - }; - }; - power-domain@RK3588_PD_RGA31 { - reg = <RK3588_PD_RGA31>; - clocks = <&cru HCLK_RGA3_1>, - <&cru ACLK_RGA3_1>; - pm_qos = <&qos_rga3_1>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_USB { - reg = <RK3588_PD_USB>; - clocks = <&cru PCLK_PHP_ROOT>, - <&cru ACLK_USB_ROOT>, - <&cru ACLK_USB>, - <&cru HCLK_USB_ROOT>, - <&cru HCLK_HOST0>, - <&cru HCLK_HOST_ARB0>, - <&cru HCLK_HOST1>, - <&cru HCLK_HOST_ARB1>; - pm_qos = <&qos_usb3_0>, - <&qos_usb3_1>, - <&qos_usb2host_0>, - <&qos_usb2host_1>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_GMAC { - reg = <RK3588_PD_GMAC>; - clocks = <&cru PCLK_PHP_ROOT>, - <&cru ACLK_PCIE_ROOT>, - <&cru ACLK_PHP_ROOT>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_PCIE { - reg = <RK3588_PD_PCIE>; - clocks = <&cru PCLK_PHP_ROOT>, - <&cru ACLK_PCIE_ROOT>, - <&cru ACLK_PHP_ROOT>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_SDIO { - reg = <RK3588_PD_SDIO>; - clocks = <&cru HCLK_SDIO>, - <&cru HCLK_NVM_ROOT>; - pm_qos = <&qos_sdio>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_AUDIO { - reg = <RK3588_PD_AUDIO>; - clocks = <&cru HCLK_AUDIO_ROOT>, - <&cru PCLK_AUDIO_ROOT>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_SDMMC { - reg = <RK3588_PD_SDMMC>; - pm_qos = <&qos_sdmmc>; - #power-domain-cells = <0>; - }; - }; - }; - - av1d: video-codec@fdc70000 { - compatible = "rockchip,rk3588-av1-vpu"; - reg = <0x0 0xfdc70000 0x0 0x800>; - interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "vdpu"; - assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; - assigned-clock-rates = <400000000>, <400000000>; - clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; - clock-names = "aclk", "hclk"; - power-domains = <&power RK3588_PD_AV1>; - resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; - }; - - vop: vop@fdd90000 { - compatible = "rockchip,rk3588-vop"; - reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; - reg-names = "vop", "gamma-lut"; - interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru ACLK_VOP>, - <&cru HCLK_VOP>, - <&cru DCLK_VOP0>, - <&cru DCLK_VOP1>, - <&cru DCLK_VOP2>, - <&cru DCLK_VOP3>, - <&cru PCLK_VOP_ROOT>; - clock-names = "aclk", - "hclk", - "dclk_vp0", - "dclk_vp1", - "dclk_vp2", - "dclk_vp3", - "pclk_vop"; - iommus = <&vop_mmu>; - power-domains = <&power RK3588_PD_VOP>; - rockchip,grf = <&sys_grf>; - rockchip,vop-grf = <&vop_grf>; - rockchip,vo1-grf = <&vo1_grf>; - rockchip,pmu = <&pmu>; - status = "disabled"; - - vop_out: ports { - #address-cells = <1>; - #size-cells = <0>; - - vp0: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - vp1: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - vp2: port@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - vp3: port@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; - }; - - vop_mmu: iommu@fdd97e00 { - compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; - reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; - interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - power-domains = <&power RK3588_PD_VOP>; - status = "disabled"; - }; - - i2s4_8ch: i2s@fddc0000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfddc0000 0x0 0x1000>; - interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac2 0>; - dma-names = "tx"; - power-domains = <&power RK3588_PD_VO0>; - resets = <&cru SRST_M_I2S4_8CH_TX>; - reset-names = "tx-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s5_8ch: i2s@fddf0000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfddf0000 0x0 0x1000>; - interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac2 2>; - dma-names = "tx"; - power-domains = <&power RK3588_PD_VO1>; - resets = <&cru SRST_M_I2S5_8CH_TX>; - reset-names = "tx-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s9_8ch: i2s@fddfc000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfddfc000 0x0 0x1000>; - interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac2 23>; - dma-names = "rx"; - power-domains = <&power RK3588_PD_VO1>; - resets = <&cru SRST_M_I2S9_8CH_RX>; - reset-names = "rx-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - qos_gpu_m0: qos@fdf35000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf35000 0x0 0x20>; - }; - - qos_gpu_m1: qos@fdf35200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf35200 0x0 0x20>; - }; - - qos_gpu_m2: qos@fdf35400 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf35400 0x0 0x20>; - }; - - qos_gpu_m3: qos@fdf35600 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf35600 0x0 0x20>; - }; - - qos_rga3_1: qos@fdf36000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf36000 0x0 0x20>; - }; - - qos_sdio: qos@fdf39000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf39000 0x0 0x20>; - }; - - qos_sdmmc: qos@fdf3d800 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf3d800 0x0 0x20>; - }; - - qos_usb3_1: qos@fdf3e000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf3e000 0x0 0x20>; - }; - - qos_usb3_0: qos@fdf3e200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf3e200 0x0 0x20>; - }; - - qos_usb2host_0: qos@fdf3e400 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf3e400 0x0 0x20>; - }; - - qos_usb2host_1: qos@fdf3e600 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf3e600 0x0 0x20>; - }; - - qos_fisheye0: qos@fdf40000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf40000 0x0 0x20>; - }; - - qos_fisheye1: qos@fdf40200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf40200 0x0 0x20>; - }; - - qos_isp0_mro: qos@fdf40400 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf40400 0x0 0x20>; - }; - - qos_isp0_mwo: qos@fdf40500 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf40500 0x0 0x20>; - }; - - qos_vicap_m0: qos@fdf40600 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf40600 0x0 0x20>; - }; - - qos_vicap_m1: qos@fdf40800 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf40800 0x0 0x20>; - }; - - qos_isp1_mwo: qos@fdf41000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf41000 0x0 0x20>; - }; - - qos_isp1_mro: qos@fdf41100 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf41100 0x0 0x20>; - }; - - qos_rkvenc0_m0ro: qos@fdf60000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf60000 0x0 0x20>; - }; - - qos_rkvenc0_m1ro: qos@fdf60200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf60200 0x0 0x20>; - }; - - qos_rkvenc0_m2wo: qos@fdf60400 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf60400 0x0 0x20>; - }; - - qos_rkvenc1_m0ro: qos@fdf61000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf61000 0x0 0x20>; - }; - - qos_rkvenc1_m1ro: qos@fdf61200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf61200 0x0 0x20>; - }; - - qos_rkvenc1_m2wo: qos@fdf61400 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf61400 0x0 0x20>; - }; - - qos_rkvdec0: qos@fdf62000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf62000 0x0 0x20>; - }; - - qos_rkvdec1: qos@fdf63000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf63000 0x0 0x20>; - }; - - qos_av1: qos@fdf64000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf64000 0x0 0x20>; - }; - - qos_iep: qos@fdf66000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66000 0x0 0x20>; - }; - - qos_jpeg_dec: qos@fdf66200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66200 0x0 0x20>; - }; - - qos_jpeg_enc0: qos@fdf66400 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66400 0x0 0x20>; - }; - - qos_jpeg_enc1: qos@fdf66600 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66600 0x0 0x20>; - }; - - qos_jpeg_enc2: qos@fdf66800 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66800 0x0 0x20>; - }; - - qos_jpeg_enc3: qos@fdf66a00 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66a00 0x0 0x20>; - }; - - qos_rga2_mro: qos@fdf66c00 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66c00 0x0 0x20>; - }; - - qos_rga2_mwo: qos@fdf66e00 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66e00 0x0 0x20>; - }; - - qos_rga3_0: qos@fdf67000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf67000 0x0 0x20>; - }; - - qos_vdpu: qos@fdf67200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf67200 0x0 0x20>; - }; - - qos_npu1: qos@fdf70000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf70000 0x0 0x20>; - }; - - qos_npu2: qos@fdf71000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf71000 0x0 0x20>; - }; - - qos_npu0_mwr: qos@fdf72000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf72000 0x0 0x20>; - }; - - qos_npu0_mro: qos@fdf72200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf72200 0x0 0x20>; - }; - - qos_mcu_npu: qos@fdf72400 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf72400 0x0 0x20>; - }; - - qos_hdcp0: qos@fdf80000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf80000 0x0 0x20>; - }; - - qos_hdcp1: qos@fdf81000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf81000 0x0 0x20>; - }; - - qos_hdmirx: qos@fdf81200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf81200 0x0 0x20>; - }; - - qos_vop_m0: qos@fdf82000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf82000 0x0 0x20>; - }; - - qos_vop_m1: qos@fdf82200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf82200 0x0 0x20>; - }; - - dfi: dfi@fe060000 { - reg = <0x00 0xfe060000 0x00 0x10000>; - compatible = "rockchip,rk3588-dfi"; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; - rockchip,pmu = <&pmu1grf>; - }; - - pcie2x1l1: pcie@fe180000 { - compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; - bus-range = <0x30 0x3f>; - clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, - <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, - <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", - "aux", "pipe"; - device_type = "pci"; - interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "sys", "pmc", "msg", "legacy", "err"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, - <0 0 0 2 &pcie2x1l1_intc 1>, - <0 0 0 3 &pcie2x1l1_intc 2>, - <0 0 0 4 &pcie2x1l1_intc 3>; - linux,pci-domain = <3>; - max-link-speed = <2>; - msi-map = <0x3000 &its0 0x3000 0x1000>; - num-lanes = <1>; - phys = <&combphy2_psu PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - power-domains = <&power RK3588_PD_PCIE>; - ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, - <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>; - reg = <0xa 0x40c00000 0x0 0x00400000>, - <0x0 0xfe180000 0x0 0x00010000>, - <0x0 0xf3000000 0x0 0x00100000>; - reg-names = "dbi", "apb", "config"; - resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; - reset-names = "pwr", "pipe"; - #address-cells = <3>; - #size-cells = <2>; - status = "disabled"; - - pcie2x1l1_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>; - }; - }; - - pcie2x1l2: pcie@fe190000 { - compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; - bus-range = <0x40 0x4f>; - clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, - <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, - <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", - "aux", "pipe"; - device_type = "pci"; - interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "sys", "pmc", "msg", "legacy", "err"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, - <0 0 0 2 &pcie2x1l2_intc 1>, - <0 0 0 3 &pcie2x1l2_intc 2>, - <0 0 0 4 &pcie2x1l2_intc 3>; - linux,pci-domain = <4>; - max-link-speed = <2>; - msi-map = <0x4000 &its0 0x4000 0x1000>; - num-lanes = <1>; - phys = <&combphy0_ps PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - power-domains = <&power RK3588_PD_PCIE>; - ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, - <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; - reg = <0xa 0x41000000 0x0 0x00400000>, - <0x0 0xfe190000 0x0 0x00010000>, - <0x0 0xf4000000 0x0 0x00100000>; - reg-names = "dbi", "apb", "config"; - resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; - reset-names = "pwr", "pipe"; - #address-cells = <3>; - #size-cells = <2>; - status = "disabled"; - - pcie2x1l2_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>; - }; - }; - - gmac1: ethernet@fe1c0000 { - compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; - reg = <0x0 0xfe1c0000 0x0 0x10000>; - interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "macirq", "eth_wake_irq"; - clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, - <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, - <&cru CLK_GMAC1_PTP_REF>; - clock-names = "stmmaceth", "clk_mac_ref", - "pclk_mac", "aclk_mac", - "ptp_ref"; - power-domains = <&power RK3588_PD_GMAC>; - resets = <&cru SRST_A_GMAC1>; - reset-names = "stmmaceth"; - rockchip,grf = <&sys_grf>; - rockchip,php-grf = <&php_grf>; - snps,axi-config = <&gmac1_stmmac_axi_setup>; - snps,mixed-burst; - snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; - snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; - snps,tso; - status = "disabled"; - - mdio1: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <0x1>; - #size-cells = <0x0>; - }; - - gmac1_stmmac_axi_setup: stmmac-axi-config { - snps,blen = <0 0 0 0 16 8 4>; - snps,wr_osr_lmt = <4>; - snps,rd_osr_lmt = <8>; - }; - - gmac1_mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <2>; - queue0 {}; - queue1 {}; - }; - - gmac1_mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <2>; - queue0 {}; - queue1 {}; - }; - }; - - sata0: sata@fe210000 { - compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; - reg = <0 0xfe210000 0 0x1000>; - interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, - <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, - <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; - clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; - ports-implemented = <0x1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata-port@0 { - reg = <0>; - hba-port-cap = <HBA_PORT_FBSCP>; - phys = <&combphy0_ps PHY_TYPE_SATA>; - phy-names = "sata-phy"; - snps,rx-ts-max = <32>; - snps,tx-ts-max = <32>; - }; - }; - - sata2: sata@fe230000 { - compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; - reg = <0 0xfe230000 0 0x1000>; - interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, - <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, - <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; - clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; - ports-implemented = <0x1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata-port@0 { - reg = <0>; - hba-port-cap = <HBA_PORT_FBSCP>; - phys = <&combphy2_psu PHY_TYPE_SATA>; - phy-names = "sata-phy"; - snps,rx-ts-max = <32>; - snps,tx-ts-max = <32>; - }; - }; - - sfc: spi@fe2b0000 { - compatible = "rockchip,sfc"; - reg = <0x0 0xfe2b0000 0x0 0x4000>; - interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; - clock-names = "clk_sfc", "hclk_sfc"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sdmmc: mmc@fe2c0000 { - compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe2c0000 0x0 0x4000>; - interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; - power-domains = <&power RK3588_PD_SDMMC>; - status = "disabled"; - }; - - sdio: mmc@fe2d0000 { - compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x00 0xfe2d0000 0x00 0x4000>; - interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdiom1_pins>; - power-domains = <&power RK3588_PD_SDIO>; - status = "disabled"; - }; - - sdhci: mmc@fe2e0000 { - compatible = "rockchip,rk3588-dwcmshc"; - reg = <0x0 0xfe2e0000 0x0 0x10000>; - interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; - assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>; - assigned-clock-rates = <200000000>, <24000000>, <200000000>; - clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, - <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, - <&cru TMCLK_EMMC>; - clock-names = "core", "bus", "axi", "block", "timer"; - max-frequency = <200000000>; - pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, - <&emmc_cmd>, <&emmc_data_strobe>; - pinctrl-names = "default"; - resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, - <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, - <&cru SRST_T_EMMC>; - reset-names = "core", "bus", "axi", "block", "timer"; - status = "disabled"; - }; - - i2s0_8ch: i2s@fe470000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfe470000 0x0 0x1000>; - interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; - dmas = <&dmac0 0>, <&dmac0 1>; - dma-names = "tx", "rx"; - power-domains = <&power RK3588_PD_AUDIO>; - resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; - reset-names = "tx-m", "rx-m"; - rockchip,trcm-sync-tx-only; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_lrck - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdi1 - &i2s0_sdi2 - &i2s0_sdi3 - &i2s0_sdo0 - &i2s0_sdo1 - &i2s0_sdo2 - &i2s0_sdo3>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s1_8ch: i2s@fe480000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfe480000 0x0 0x1000>; - interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - dmas = <&dmac0 2>, <&dmac0 3>; - dma-names = "tx", "rx"; - resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; - reset-names = "tx-m", "rx-m"; - rockchip,trcm-sync-tx-only; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1m0_lrck - &i2s1m0_sclk - &i2s1m0_sdi0 - &i2s1m0_sdi1 - &i2s1m0_sdi2 - &i2s1m0_sdi3 - &i2s1m0_sdo0 - &i2s1m0_sdo1 - &i2s1m0_sdo2 - &i2s1m0_sdo3>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s2_2ch: i2s@fe490000 { - compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xfe490000 0x0 0x1000>; - interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; - clock-names = "i2s_clk", "i2s_hclk"; - assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac1 0>, <&dmac1 1>; - dma-names = "tx", "rx"; - power-domains = <&power RK3588_PD_AUDIO>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s2m1_lrck - &i2s2m1_sclk - &i2s2m1_sdi - &i2s2m1_sdo>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s3_2ch: i2s@fe4a0000 { - compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xfe4a0000 0x0 0x1000>; - interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; - clock-names = "i2s_clk", "i2s_hclk"; - assigned-clocks = <&cru CLK_I2S3_2CH_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac1 2>, <&dmac1 3>; - dma-names = "tx", "rx"; - power-domains = <&power RK3588_PD_AUDIO>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s3_lrck - &i2s3_sclk - &i2s3_sdi - &i2s3_sdo>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@fe600000 { - compatible = "arm,gic-v3"; - reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ - <0x0 0xfe680000 0 0x100000>; /* GICR */ - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-controller; - mbi-alias = <0x0 0xfe610000>; - mbi-ranges = <424 56>; - msi-controller; - ranges; - #address-cells = <2>; - #interrupt-cells = <4>; - #size-cells = <2>; - - its0: msi-controller@fe640000 { - compatible = "arm,gic-v3-its"; - reg = <0x0 0xfe640000 0x0 0x20000>; - msi-controller; - #msi-cells = <1>; - }; - - its1: msi-controller@fe660000 { - compatible = "arm,gic-v3-its"; - reg = <0x0 0xfe660000 0x0 0x20000>; - msi-controller; - #msi-cells = <1>; - }; - - ppi-partitions { - ppi_partition0: interrupt-partition-0 { - affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; - }; - - ppi_partition1: interrupt-partition-1 { - affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>; - }; - }; - }; - - dmac0: dma-controller@fea10000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xfea10000 0x0 0x4000>; - interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - dmac1: dma-controller@fea30000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xfea30000 0x0 0x4000>; - interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - i2c1: i2c@fea90000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfea90000 0x0 0x1000>; - clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; - clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-0 = <&i2c1m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@feaa0000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfeaa0000 0x0 0x1000>; - clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; - clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-0 = <&i2c2m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@feab0000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfeab0000 0x0 0x1000>; - clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; - clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-0 = <&i2c3m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@feac0000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfeac0000 0x0 0x1000>; - clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; - clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-0 = <&i2c4m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@fead0000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfead0000 0x0 0x1000>; - clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; - clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-0 = <&i2c5m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - timer0: timer@feae0000 { - compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; - reg = <0x0 0xfeae0000 0x0 0x20>; - interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; - clock-names = "pclk", "timer"; - }; - - wdt: watchdog@feaf0000 { - compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; - reg = <0x0 0xfeaf0000 0x0 0x100>; - clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; - clock-names = "tclk", "pclk"; - interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>; - }; - - spi0: spi@feb00000 { - compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfeb00000 0x0 0x1000>; - interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac0 14>, <&dmac0 15>; - dma-names = "tx", "rx"; - num-cs = <2>; - pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@feb10000 { - compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfeb10000 0x0 0x1000>; - interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac0 16>, <&dmac0 17>; - dma-names = "tx", "rx"; - num-cs = <2>; - pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@feb20000 { - compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfeb20000 0x0 0x1000>; - interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac1 15>, <&dmac1 16>; - dma-names = "tx", "rx"; - num-cs = <2>; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi3: spi@feb30000 { - compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfeb30000 0x0 0x1000>; - interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac1 17>, <&dmac1 18>; - dma-names = "tx", "rx"; - num-cs = <2>; - pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart1: serial@feb40000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfeb40000 0x0 0x100>; - interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 8>, <&dmac0 9>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart1m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart2: serial@feb50000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfeb50000 0x0 0x100>; - interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 10>, <&dmac0 11>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart2m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart3: serial@feb60000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfeb60000 0x0 0x100>; - interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 12>, <&dmac0 13>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart3m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart4: serial@feb70000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfeb70000 0x0 0x100>; - interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac1 9>, <&dmac1 10>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart4m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart5: serial@feb80000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfeb80000 0x0 0x100>; - interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac1 11>, <&dmac1 12>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart5m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart6: serial@feb90000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfeb90000 0x0 0x100>; - interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac1 13>, <&dmac1 14>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart6m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart7: serial@feba0000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfeba0000 0x0 0x100>; - interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac2 7>, <&dmac2 8>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart7m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart8: serial@febb0000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfebb0000 0x0 0x100>; - interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac2 9>, <&dmac2 10>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart8m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart9: serial@febc0000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfebc0000 0x0 0x100>; - interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac2 11>, <&dmac2 12>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart9m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - pwm4: pwm@febd0000 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebd0000 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm4m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm5: pwm@febd0010 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebd0010 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm5m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm6: pwm@febd0020 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebd0020 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm6m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm7: pwm@febd0030 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebd0030 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm7m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm8: pwm@febe0000 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebe0000 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm8m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm9: pwm@febe0010 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebe0010 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm9m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm10: pwm@febe0020 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebe0020 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm10m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm11: pwm@febe0030 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebe0030 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm11m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm12: pwm@febf0000 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebf0000 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm12m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm13: pwm@febf0010 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebf0010 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm13m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm14: pwm@febf0020 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebf0020 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm14m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm15: pwm@febf0030 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebf0030 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm15m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - tsadc: tsadc@fec00000 { - compatible = "rockchip,rk3588-tsadc"; - reg = <0x0 0xfec00000 0x0 0x400>; - interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - assigned-clocks = <&cru CLK_TSADC>; - assigned-clock-rates = <2000000>; - resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; - reset-names = "tsadc-apb", "tsadc"; - rockchip,hw-tshut-temp = <120000>; - rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ - pinctrl-0 = <&tsadc_gpio_func>; - pinctrl-1 = <&tsadc_shut>; - pinctrl-names = "gpio", "otpout"; - #thermal-sensor-cells = <1>; - status = "disabled"; - }; - - saradc: adc@fec10000 { - compatible = "rockchip,rk3588-saradc"; - reg = <0x0 0xfec10000 0x0 0x10000>; - interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>; - #io-channel-cells = <1>; - clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_P_SARADC>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - i2c6: i2c@fec80000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfec80000 0x0 0x1000>; - clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; - clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-0 = <&i2c6m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c7: i2c@fec90000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfec90000 0x0 0x1000>; - clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; - clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-0 = <&i2c7m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c8: i2c@feca0000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfeca0000 0x0 0x1000>; - clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; - clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-0 = <&i2c8m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi4: spi@fecb0000 { - compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfecb0000 0x0 0x1000>; - interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac2 13>, <&dmac2 14>; - dma-names = "tx", "rx"; - num-cs = <2>; - pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - otp: efuse@fecc0000 { - compatible = "rockchip,rk3588-otp"; - reg = <0x0 0xfecc0000 0x0 0x400>; - clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, - <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>; - clock-names = "otp", "apb_pclk", "phy", "arb"; - resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, - <&cru SRST_OTPC_ARB>; - reset-names = "otp", "apb", "arb"; - #address-cells = <1>; - #size-cells = <1>; - - cpu_code: cpu-code@2 { - reg = <0x02 0x2>; - }; - - otp_id: id@7 { - reg = <0x07 0x10>; - }; - - cpub0_leakage: cpu-leakage@17 { - reg = <0x17 0x1>; - }; - - cpub1_leakage: cpu-leakage@18 { - reg = <0x18 0x1>; - }; - - cpul_leakage: cpu-leakage@19 { - reg = <0x19 0x1>; - }; - - log_leakage: log-leakage@1a { - reg = <0x1a 0x1>; - }; - - gpu_leakage: gpu-leakage@1b { - reg = <0x1b 0x1>; - }; - - otp_cpu_version: cpu-version@1c { - reg = <0x1c 0x1>; - bits = <3 3>; - }; - - npu_leakage: npu-leakage@28 { - reg = <0x28 0x1>; - }; - - codec_leakage: codec-leakage@29 { - reg = <0x29 0x1>; - }; - }; - - dmac2: dma-controller@fed10000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xfed10000 0x0 0x4000>; - interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC2>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - hdptxphy_hdmi0: phy@fed60000 { - compatible = "rockchip,rk3588-hdptx-phy"; - reg = <0x0 0xfed60000 0x0 0x2000>; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; - clock-names = "ref", "apb"; - #phy-cells = <0>; - resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, - <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, - <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, - <&cru SRST_HDPTX0_LCPLL>; - reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", - "lcpll"; - rockchip,grf = <&hdptxphy0_grf>; - status = "disabled"; - }; - - usbdp_phy0: phy@fed80000 { - compatible = "rockchip,rk3588-usbdp-phy"; - reg = <0x0 0xfed80000 0x0 0x10000>; - #phy-cells = <1>; - clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, - <&cru CLK_USBDP_PHY0_IMMORTAL>, - <&cru PCLK_USBDPPHY0>, - <&u2phy0>; - clock-names = "refclk", "immortal", "pclk", "utmi"; - resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, - <&cru SRST_USBDP_COMBO_PHY0_CMN>, - <&cru SRST_USBDP_COMBO_PHY0_LANE>, - <&cru SRST_USBDP_COMBO_PHY0_PCS>, - <&cru SRST_P_USBDPPHY0>; - reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; - rockchip,u2phy-grf = <&usb2phy0_grf>; - rockchip,usb-grf = <&usb_grf>; - rockchip,usbdpphy-grf = <&usbdpphy0_grf>; - rockchip,vo-grf = <&vo0_grf>; - status = "disabled"; - }; - - combphy0_ps: phy@fee00000 { - compatible = "rockchip,rk3588-naneng-combphy"; - reg = <0x0 0xfee00000 0x0 0x100>; - clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, - <&cru PCLK_PHP_ROOT>; - clock-names = "ref", "apb", "pipe"; - assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; - assigned-clock-rates = <100000000>; - #phy-cells = <1>; - resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>; - reset-names = "phy", "apb"; - rockchip,pipe-grf = <&php_grf>; - rockchip,pipe-phy-grf = <&pipe_phy0_grf>; - status = "disabled"; - }; - - combphy2_psu: phy@fee20000 { - compatible = "rockchip,rk3588-naneng-combphy"; - reg = <0x0 0xfee20000 0x0 0x100>; - clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, - <&cru PCLK_PHP_ROOT>; - clock-names = "ref", "apb", "pipe"; - assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; - assigned-clock-rates = <100000000>; - #phy-cells = <1>; - resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>; - reset-names = "phy", "apb"; - rockchip,pipe-grf = <&php_grf>; - rockchip,pipe-phy-grf = <&pipe_phy2_grf>; - status = "disabled"; - }; - - system_sram2: sram@ff001000 { - compatible = "mmio-sram"; - reg = <0x0 0xff001000 0x0 0xef000>; - ranges = <0x0 0x0 0xff001000 0xef000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3588-pinctrl"; - ranges; - rockchip,grf = <&ioc>; - #address-cells = <2>; - #size-cells = <2>; - - gpio0: gpio@fd8a0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfd8a0000 0x0 0x100>; - interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; - gpio-controller; - gpio-ranges = <&pinctrl 0 0 32>; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio1: gpio@fec20000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfec20000 0x0 0x100>; - interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; - gpio-controller; - gpio-ranges = <&pinctrl 0 32 32>; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio2: gpio@fec30000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfec30000 0x0 0x100>; - interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; - gpio-controller; - gpio-ranges = <&pinctrl 0 64 32>; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio3: gpio@fec40000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfec40000 0x0 0x100>; - interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; - gpio-controller; - gpio-ranges = <&pinctrl 0 96 32>; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio4: gpio@fec50000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfec50000 0x0 0x100>; - interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; - gpio-controller; - gpio-ranges = <&pinctrl 0 128 32>; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - }; -}; - -#include "rk3588s-pinctrl.dtsi" +#include "rk3588-base.dtsi" +#include "rk3588-opp.dtsi" |