diff options
| -rw-r--r-- | drivers/clk/mediatek/clk-mt8183.c | 30 | ||||
| -rw-r--r-- | include/dt-bindings/clock/mt8183-clk.h | 4 |
2 files changed, 34 insertions, 0 deletions
diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index 94bbadc0d259..7e7452e56694 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -1002,6 +1002,20 @@ static const struct mtk_gate infra_clks[] = { "msdc50_0_sel", 24), }; +static const struct mtk_gate_regs peri_cg_regs = { + .set_ofs = 0x20c, + .clr_ofs = 0x20c, + .sta_ofs = 0x20c, +}; + +#define GATE_PERI(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift, \ + &mtk_clk_gate_ops_no_setclr_inv) + +static const struct mtk_gate peri_clks[] = { + GATE_PERI(CLK_PERI_AXI, "peri_axi", "axi_sel", 31), +}; + static const struct mtk_gate_regs apmixed_cg_regs = { .set_ofs = 0x20, .clr_ofs = 0x20, @@ -1208,6 +1222,19 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev) return r; } +static int clk_mt8183_peri_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + + clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); + + mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), + clk_data); + + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); +} + static int clk_mt8183_mcu_probe(struct platform_device *pdev) { struct clk_onecell_data *clk_data; @@ -1238,6 +1265,9 @@ static const struct of_device_id of_match_clk_mt8183[] = { .compatible = "mediatek,mt8183-infracfg", .data = clk_mt8183_infra_probe, }, { + .compatible = "mediatek,mt8183-pericfg", + .data = clk_mt8183_peri_probe, + }, { .compatible = "mediatek,mt8183-mcucfg", .data = clk_mt8183_mcu_probe, }, { diff --git a/include/dt-bindings/clock/mt8183-clk.h b/include/dt-bindings/clock/mt8183-clk.h index 0046506eb24c..a7b470b0ec8a 100644 --- a/include/dt-bindings/clock/mt8183-clk.h +++ b/include/dt-bindings/clock/mt8183-clk.h @@ -284,6 +284,10 @@ #define CLK_INFRA_FBIST2FPC 100 #define CLK_INFRA_NR_CLK 101 +/* PERICFG */ +#define CLK_PERI_AXI 0 +#define CLK_PERI_NR_CLK 1 + /* MFGCFG */ #define CLK_MFG_BG3D 0 #define CLK_MFG_NR_CLK 1 |