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Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8ulp.dtsi')
-rw-r--r--arch/arm64/boot/dts/freescale/imx8ulp.dtsi73
1 files changed, 72 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
index 57627bdaa851..8a6596d5a581 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/imx8ulp-power.h>
+#include <dt-bindings/thermal/thermal.h>
#include "imx8ulp-pinfunc.h"
@@ -39,6 +40,7 @@
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
+ cpu-idle-states = <&cpu_sleep>;
};
A35_1: cpu@1 {
@@ -47,6 +49,7 @@
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
+ cpu-idle-states = <&cpu_sleep>;
};
A35_L2: l2-cache0 {
@@ -54,6 +57,19 @@
cache-level = <2>;
cache-unified;
};
+
+ idle-states {
+ entry-method = "psci";
+
+ cpu_sleep: cpu-sleep {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0>;
+ local-timer-stop;
+ entry-latency-us = <1000>;
+ exit-latency-us = <700>;
+ min-residency-us = <2700>;
+ };
+ };
};
gic: interrupt-controller@2d400000 {
@@ -78,6 +94,28 @@
method = "smc";
};
+ thermal-zones {
+ cpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&scmi_sensor 0>;
+
+ trips {
+ cpu_alert0: trip0 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit0: trip1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
@@ -148,11 +186,17 @@
};
};
+ cm33: remoteproc-cm33 {
+ compatible = "fsl,imx8ulp-cm33";
+ status = "disabled";
+ };
+
soc: soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0x0 0x0 0x0 0x40000000>;
+ ranges = <0x0 0x0 0x0 0x40000000>,
+ <0x60000000 0x0 0x60000000 0x1000000>;
s4muap: mailbox@27020000 {
compatible = "fsl,imx8ulp-mu-s4";
@@ -307,6 +351,21 @@
#reset-cells = <1>;
};
+ flexspi2: spi@29810000 {
+ compatible = "nxp,imx8mm-fspi";
+ reg = <0x29810000 0x10000>, <0x60000000 0x10000000>;
+ reg-names = "fspi_base", "fspi_mmap";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pcc4 IMX8ULP_CLK_FLEXSPI2>,
+ <&pcc4 IMX8ULP_CLK_FLEXSPI2>;
+ clock-names = "fspi", "fspi_en";
+ assigned-clocks = <&pcc4 IMX8ULP_CLK_FLEXSPI2>;
+ assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>;
+ status = "disabled";
+ };
+
lpi2c6: i2c@29840000 {
compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x29840000 0x10000>;
@@ -365,6 +424,10 @@
<&pcc4 IMX8ULP_CLK_USDHC0>;
clock-names = "ipg", "ahb", "per";
power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>;
+ assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1>,
+ <&pcc4 IMX8ULP_CLK_USDHC0>;
+ assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1>;
+ assigned-clock-rates = <389283840>, <389283840>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step = <2>;
bus-width = <4>;
@@ -380,6 +443,10 @@
<&pcc4 IMX8ULP_CLK_USDHC1>;
clock-names = "ipg", "ahb", "per";
power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>;
+ assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>,
+ <&pcc4 IMX8ULP_CLK_USDHC1>;
+ assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>;
+ assigned-clock-rates = <194641920>, <194641920>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step = <2>;
bus-width = <4>;
@@ -395,6 +462,10 @@
<&pcc4 IMX8ULP_CLK_USDHC2>;
clock-names = "ipg", "ahb", "per";
power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>;
+ assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>,
+ <&pcc4 IMX8ULP_CLK_USDHC2>;
+ assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>;
+ assigned-clock-rates = <194641920>, <194641920>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step = <2>;
bus-width = <4>;