diff options
Diffstat (limited to 'arch/mips/sgi-ip22/ip22-nvram.c')
| -rw-r--r-- | arch/mips/sgi-ip22/ip22-nvram.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/mips/sgi-ip22/ip22-nvram.c b/arch/mips/sgi-ip22/ip22-nvram.c index 0177566475d4..e077036a676a 100644 --- a/arch/mips/sgi-ip22/ip22-nvram.c +++ b/arch/mips/sgi-ip22/ip22-nvram.c @@ -14,11 +14,11 @@ #define EEPROM_WRITE 0xa000 /* serial memory write */ #define EEPROM_WRALL 0x8800 /* write all registers */ #define EEPROM_WDS 0x8000 /* disable all programming */ -#define EEPROM_PRREAD 0xc000 /* read protect register */ -#define EEPROM_PREN 0x9800 /* enable protect register mode */ -#define EEPROM_PRCLEAR 0xffff /* clear protect register */ -#define EEPROM_PRWRITE 0xa000 /* write protect register */ -#define EEPROM_PRDS 0x8000 /* disable protect register, forever */ +#define EEPROM_PRREAD 0xc000 /* read protect register */ +#define EEPROM_PREN 0x9800 /* enable protect register mode */ +#define EEPROM_PRCLEAR 0xffff /* clear protect register */ +#define EEPROM_PRWRITE 0xa000 /* write protect register */ +#define EEPROM_PRDS 0x8000 /* disable protect register, forever */ #define EEPROM_EPROT 0x01 /* Protect register enable */ #define EEPROM_CSEL 0x02 /* Chip select */ @@ -27,7 +27,7 @@ #define EEPROM_DATI 0x10 /* Data in */ /* We need to use these functions early... */ -#define delay() ({ \ +#define delay() ({ \ int x; \ for (x=0; x<100000; x++) __asm__ __volatile__(""); }) @@ -35,7 +35,7 @@ __raw_writel(__raw_readl(ptr) & ~EEPROM_DATO, ptr); \ __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \ __raw_writel(__raw_readl(ptr) & ~EEPROM_EPROT, ptr); \ - delay(); \ + delay(); \ __raw_writel(__raw_readl(ptr) | EEPROM_CSEL, ptr); \ __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); }) @@ -46,7 +46,7 @@ __raw_writel(__raw_readl(ptr) | EEPROM_EPROT, ptr); \ __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); }) -#define BITS_IN_COMMAND 11 +#define BITS_IN_COMMAND 11 /* * clock in the nvram command and the register number. For the * national semiconductor nv ram chip the op code is 3 bits and |