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-rw-r--r--drivers/gpu/drm/amd/include/aldebaran_ip_offset.h1738
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h2
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h6
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h9
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_1_sh_mask.h16
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_offset.h7683
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h32949
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_7_offset.h5125
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_7_sh_mask.h32178
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_2_offset.h361
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_2_sh_mask.h531
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_0_offset.h5224
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_0_sh_mask.h13922
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_13_0_2_offset.h516
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_13_0_2_sh_mask.h1163
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/thm/thm_13_0_2_offset.h346
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/thm/thm_13_0_2_sh_mask.h1297
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_7_0_offset.h2620
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_7_0_sh_mask.h10796
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_offset.h1462
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h4535
-rw-r--r--drivers/gpu/drm/amd/include/atombios.h4
-rw-r--r--drivers/gpu/drm/amd/include/atomfirmware.h208
-rw-r--r--drivers/gpu/drm/amd/include/ivsrcid/dcn/irqsrcs_dcn_1_0.h4
-rw-r--r--drivers/gpu/drm/amd/include/kgd_pp_interface.h141
-rw-r--r--drivers/gpu/drm/amd/include/soc15_ih_clientid.h9
-rw-r--r--drivers/gpu/drm/amd/include/vi_structs.h32
27 files changed, 122852 insertions, 25 deletions
diff --git a/drivers/gpu/drm/amd/include/aldebaran_ip_offset.h b/drivers/gpu/drm/amd/include/aldebaran_ip_offset.h
new file mode 100644
index 000000000000..644ffec2b0ce
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/aldebaran_ip_offset.h
@@ -0,0 +1,1738 @@
+/*
+ * Copyright (C) 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _aldebaran_ip_offset_HEADER
+#define _aldebaran_ip_offset_HEADER
+
+#define MAX_INSTANCE 7
+#define MAX_SEGMENT 6
+
+struct IP_BASE_INSTANCE {
+ unsigned int segment[MAX_SEGMENT];
+};
+
+struct IP_BASE {
+ struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
+};
+
+static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C20, 0x02408C00, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } },
+ { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } },
+ { { 0x00017000, 0x02402000, 0, 0, 0, 0 } },
+ { { 0x00017200, 0x02402400, 0, 0, 0, 0 } },
+ { { 0x0001B000, 0x0242D800, 0, 0, 0, 0 } },
+ { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0 } },
+ { { 0x00017E00, 0x0240BC00, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DBGU_IO0_BASE = { { { { 0x000001E0, 0x0240B400, 0, 0, 0, 0 } },
+ { { 0x00000260, 0x02413C00, 0, 0, 0, 0 } },
+ { { 0x00000280, 0x02416000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0x07C00000, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE GC_BASE = { { { { 0x00002000, 0x0000A000, 0x02402C00, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE IOAGR0_BASE = { { { { 0x02419000, 0x056C0000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE IOAPIC0_BASE = { { { { 0x00A00000, 0x0241F000, 0x050C0000, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE IOHC0_BASE = { { { { 0x00010000, 0x02406000, 0x04EC0000, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE L1IMUIOAGR0_BASE = { { { { 0x0240CC00, 0x05200000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE L1IMUPCIE0_BASE = { { { { 0x0240C800, 0x051C0000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE L2IMU0_BASE = { { { { 0x00007DC0, 0x00900000, 0x02407000, 0x04FC0000, 0x055C0000, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0x02408800, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE PCIE0_BASE = { { { { 0x02411800, 0x04440000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0x00012540, 0x0040A800, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE SDMA1_BASE = { { { { 0x00001860, 0x00012560, 0x0040AC00, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE SDMA2_BASE = { { { { 0x00013760, 0x0001E000, 0x0042EC00, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE SDMA3_BASE = { { { { 0x00013780, 0x0001E400, 0x0042F000, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE SDMA4_BASE = { { { { 0x000137A0, 0x0001E800, 0x0042F400, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x02401000, 0x03440000, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x00054000, 0x02425800, 0, 0, 0 } },
+ { { 0x00094000, 0x000D4000, 0x02425C00, 0, 0, 0 } },
+ { { 0x00114000, 0x00154000, 0x02426000, 0, 0, 0 } },
+ { { 0x00194000, 0x001D4000, 0x02426400, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0, 0 } },
+ { { 0x00007A00, 0x00009000, 0x02445000, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE WAFL0_BASE = { { { { 0x02438000, 0x04880000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE WAFL1_BASE = { { { { 0, 0x01300000, 0x02410800, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE XGMI0_BASE = { { { { 0x02438C00, 0x04680000, 0x04940000, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE XGMI1_BASE = { { { { 0x02439000, 0x046C0000, 0x04980000, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE XGMI2_BASE = { { { { 0x04700000, 0x049C0000, 0, 0, 0, 0 } },
+ { { 0x04740000, 0x04A00000, 0, 0, 0, 0 } },
+ { { 0x04780000, 0x04A40000, 0, 0, 0, 0 } },
+ { { 0x047C0000, 0x04A80000, 0, 0, 0, 0 } },
+ { { 0x04800000, 0x04AC0000, 0, 0, 0, 0 } },
+ { { 0x04840000, 0x04B00000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0 } } } };
+
+
+#define ATHUB_BASE__INST0_SEG0 0x00000C20
+#define ATHUB_BASE__INST0_SEG1 0x02408C00
+#define ATHUB_BASE__INST0_SEG2 0
+#define ATHUB_BASE__INST0_SEG3 0
+#define ATHUB_BASE__INST0_SEG4 0
+#define ATHUB_BASE__INST0_SEG5 0
+
+#define ATHUB_BASE__INST1_SEG0 0
+#define ATHUB_BASE__INST1_SEG1 0
+#define ATHUB_BASE__INST1_SEG2 0
+#define ATHUB_BASE__INST1_SEG3 0
+#define ATHUB_BASE__INST1_SEG4 0
+#define ATHUB_BASE__INST1_SEG5 0
+
+#define ATHUB_BASE__INST2_SEG0 0
+#define ATHUB_BASE__INST2_SEG1 0
+#define ATHUB_BASE__INST2_SEG2 0
+#define ATHUB_BASE__INST2_SEG3 0
+#define ATHUB_BASE__INST2_SEG4 0
+#define ATHUB_BASE__INST2_SEG5 0
+
+#define ATHUB_BASE__INST3_SEG0 0
+#define ATHUB_BASE__INST3_SEG1 0
+#define ATHUB_BASE__INST3_SEG2 0
+#define ATHUB_BASE__INST3_SEG3 0
+#define ATHUB_BASE__INST3_SEG4 0
+#define ATHUB_BASE__INST3_SEG5 0
+
+#define ATHUB_BASE__INST4_SEG0 0
+#define ATHUB_BASE__INST4_SEG1 0
+#define ATHUB_BASE__INST4_SEG2 0
+#define ATHUB_BASE__INST4_SEG3 0
+#define ATHUB_BASE__INST4_SEG4 0
+#define ATHUB_BASE__INST4_SEG5 0
+
+#define ATHUB_BASE__INST5_SEG0 0
+#define ATHUB_BASE__INST5_SEG1 0
+#define ATHUB_BASE__INST5_SEG2 0
+#define ATHUB_BASE__INST5_SEG3 0
+#define ATHUB_BASE__INST5_SEG4 0
+#define ATHUB_BASE__INST5_SEG5 0
+
+#define ATHUB_BASE__INST6_SEG0 0
+#define ATHUB_BASE__INST6_SEG1 0
+#define ATHUB_BASE__INST6_SEG2 0
+#define ATHUB_BASE__INST6_SEG3 0
+#define ATHUB_BASE__INST6_SEG4 0
+#define ATHUB_BASE__INST6_SEG5 0
+
+#define CLK_BASE__INST0_SEG0 0x00016C00
+#define CLK_BASE__INST0_SEG1 0x02401800
+#define CLK_BASE__INST0_SEG2 0
+#define CLK_BASE__INST0_SEG3 0
+#define CLK_BASE__INST0_SEG4 0
+#define CLK_BASE__INST0_SEG5 0
+
+#define CLK_BASE__INST1_SEG0 0x00016E00
+#define CLK_BASE__INST1_SEG1 0x02401C00
+#define CLK_BASE__INST1_SEG2 0
+#define CLK_BASE__INST1_SEG3 0
+#define CLK_BASE__INST1_SEG4 0
+#define CLK_BASE__INST1_SEG5 0
+
+#define CLK_BASE__INST2_SEG0 0x00017000
+#define CLK_BASE__INST2_SEG1 0x02402000
+#define CLK_BASE__INST2_SEG2 0
+#define CLK_BASE__INST2_SEG3 0
+#define CLK_BASE__INST2_SEG4 0
+#define CLK_BASE__INST2_SEG5 0
+
+#define CLK_BASE__INST3_SEG0 0x00017200
+#define CLK_BASE__INST3_SEG1 0x02402400
+#define CLK_BASE__INST3_SEG2 0
+#define CLK_BASE__INST3_SEG3 0
+#define CLK_BASE__INST3_SEG4 0
+#define CLK_BASE__INST3_SEG5 0
+
+#define CLK_BASE__INST4_SEG0 0x0001B000
+#define CLK_BASE__INST4_SEG1 0x0242D800
+#define CLK_BASE__INST4_SEG2 0
+#define CLK_BASE__INST4_SEG3 0
+#define CLK_BASE__INST4_SEG4 0
+#define CLK_BASE__INST4_SEG5 0
+
+#define CLK_BASE__INST5_SEG0 0x0001B200
+#define CLK_BASE__INST5_SEG1 0x0242DC00
+#define CLK_BASE__INST5_SEG2 0
+#define CLK_BASE__INST5_SEG3 0
+#define CLK_BASE__INST5_SEG4 0
+#define CLK_BASE__INST5_SEG5 0
+
+#define CLK_BASE__INST6_SEG0 0x00017E00
+#define CLK_BASE__INST6_SEG1 0x0240BC00
+#define CLK_BASE__INST6_SEG2 0
+#define CLK_BASE__INST6_SEG3 0
+#define CLK_BASE__INST6_SEG4 0
+#define CLK_BASE__INST6_SEG5 0
+
+#define DBGU_IO0_BASE__INST0_SEG0 0x000001E0
+#define DBGU_IO0_BASE__INST0_SEG1 0x0240B400
+#define DBGU_IO0_BASE__INST0_SEG2 0
+#define DBGU_IO0_BASE__INST0_SEG3 0
+#define DBGU_IO0_BASE__INST0_SEG4 0
+#define DBGU_IO0_BASE__INST0_SEG5 0
+
+#define DBGU_IO0_BASE__INST1_SEG0 0x00000260
+#define DBGU_IO0_BASE__INST1_SEG1 0x02413C00
+#define DBGU_IO0_BASE__INST1_SEG2 0
+#define DBGU_IO0_BASE__INST1_SEG3 0
+#define DBGU_IO0_BASE__INST1_SEG4 0
+#define DBGU_IO0_BASE__INST1_SEG5 0
+
+#define DBGU_IO0_BASE__INST2_SEG0 0x00000280
+#define DBGU_IO0_BASE__INST2_SEG1 0x02416000
+#define DBGU_IO0_BASE__INST2_SEG2 0
+#define DBGU_IO0_BASE__INST2_SEG3 0
+#define DBGU_IO0_BASE__INST2_SEG4 0
+#define DBGU_IO0_BASE__INST2_SEG5 0
+
+#define DBGU_IO0_BASE__INST3_SEG0 0
+#define DBGU_IO0_BASE__INST3_SEG1 0
+#define DBGU_IO0_BASE__INST3_SEG2 0
+#define DBGU_IO0_BASE__INST3_SEG3 0
+#define DBGU_IO0_BASE__INST3_SEG4 0
+#define DBGU_IO0_BASE__INST3_SEG5 0
+
+#define DBGU_IO0_BASE__INST4_SEG0 0
+#define DBGU_IO0_BASE__INST4_SEG1 0
+#define DBGU_IO0_BASE__INST4_SEG2 0
+#define DBGU_IO0_BASE__INST4_SEG3 0
+#define DBGU_IO0_BASE__INST4_SEG4 0
+#define DBGU_IO0_BASE__INST4_SEG5 0
+
+#define DBGU_IO0_BASE__INST5_SEG0 0
+#define DBGU_IO0_BASE__INST5_SEG1 0
+#define DBGU_IO0_BASE__INST5_SEG2 0
+#define DBGU_IO0_BASE__INST5_SEG3 0
+#define DBGU_IO0_BASE__INST5_SEG4 0
+#define DBGU_IO0_BASE__INST5_SEG5 0
+
+#define DBGU_IO0_BASE__INST6_SEG0 0
+#define DBGU_IO0_BASE__INST6_SEG1 0
+#define DBGU_IO0_BASE__INST6_SEG2 0
+#define DBGU_IO0_BASE__INST6_SEG3 0
+#define DBGU_IO0_BASE__INST6_SEG4 0
+#define DBGU_IO0_BASE__INST6_SEG5 0
+
+#define DF_BASE__INST0_SEG0 0x00007000
+#define DF_BASE__INST0_SEG1 0x0240B800
+#define DF_BASE__INST0_SEG2 0x07C00000
+#define DF_BASE__INST0_SEG3 0
+#define DF_BASE__INST0_SEG4 0
+#define DF_BASE__INST0_SEG5 0
+
+#define DF_BASE__INST1_SEG0 0
+#define DF_BASE__INST1_SEG1 0
+#define DF_BASE__INST1_SEG2 0
+#define DF_BASE__INST1_SEG3 0
+#define DF_BASE__INST1_SEG4 0
+#define DF_BASE__INST1_SEG5 0
+
+#define DF_BASE__INST2_SEG0 0
+#define DF_BASE__INST2_SEG1 0
+#define DF_BASE__INST2_SEG2 0
+#define DF_BASE__INST2_SEG3 0
+#define DF_BASE__INST2_SEG4 0
+#define DF_BASE__INST2_SEG5 0
+
+#define DF_BASE__INST3_SEG0 0
+#define DF_BASE__INST3_SEG1 0
+#define DF_BASE__INST3_SEG2 0
+#define DF_BASE__INST3_SEG3 0
+#define DF_BASE__INST3_SEG4 0
+#define DF_BASE__INST3_SEG5 0
+
+#define DF_BASE__INST4_SEG0 0
+#define DF_BASE__INST4_SEG1 0
+#define DF_BASE__INST4_SEG2 0
+#define DF_BASE__INST4_SEG3 0
+#define DF_BASE__INST4_SEG4 0
+#define DF_BASE__INST4_SEG5 0
+
+#define DF_BASE__INST5_SEG0 0
+#define DF_BASE__INST5_SEG1 0
+#define DF_BASE__INST5_SEG2 0
+#define DF_BASE__INST5_SEG3 0
+#define DF_BASE__INST5_SEG4 0
+#define DF_BASE__INST5_SEG5 0
+
+#define DF_BASE__INST6_SEG0 0
+#define DF_BASE__INST6_SEG1 0
+#define DF_BASE__INST6_SEG2 0
+#define DF_BASE__INST6_SEG3 0
+#define DF_BASE__INST6_SEG4 0
+#define DF_BASE__INST6_SEG5 0
+
+#define FUSE_BASE__INST0_SEG0 0x00017400
+#define FUSE_BASE__INST0_SEG1 0x02401400
+#define FUSE_BASE__INST0_SEG2 0
+#define FUSE_BASE__INST0_SEG3 0
+#define FUSE_BASE__INST0_SEG4 0
+#define FUSE_BASE__INST0_SEG5 0
+
+#define FUSE_BASE__INST1_SEG0 0
+#define FUSE_BASE__INST1_SEG1 0
+#define FUSE_BASE__INST1_SEG2 0
+#define FUSE_BASE__INST1_SEG3 0
+#define FUSE_BASE__INST1_SEG4 0
+#define FUSE_BASE__INST1_SEG5 0
+
+#define FUSE_BASE__INST2_SEG0 0
+#define FUSE_BASE__INST2_SEG1 0
+#define FUSE_BASE__INST2_SEG2 0
+#define FUSE_BASE__INST2_SEG3 0
+#define FUSE_BASE__INST2_SEG4 0
+#define FUSE_BASE__INST2_SEG5 0
+
+#define FUSE_BASE__INST3_SEG0 0
+#define FUSE_BASE__INST3_SEG1 0
+#define FUSE_BASE__INST3_SEG2 0
+#define FUSE_BASE__INST3_SEG3 0
+#define FUSE_BASE__INST3_SEG4 0
+#define FUSE_BASE__INST3_SEG5 0
+
+#define FUSE_BASE__INST4_SEG0 0
+#define FUSE_BASE__INST4_SEG1 0
+#define FUSE_BASE__INST4_SEG2 0
+#define FUSE_BASE__INST4_SEG3 0
+#define FUSE_BASE__INST4_SEG4 0
+#define FUSE_BASE__INST4_SEG5 0
+
+#define FUSE_BASE__INST5_SEG0 0
+#define FUSE_BASE__INST5_SEG1 0
+#define FUSE_BASE__INST5_SEG2 0
+#define FUSE_BASE__INST5_SEG3 0
+#define FUSE_BASE__INST5_SEG4 0
+#define FUSE_BASE__INST5_SEG5 0
+
+#define FUSE_BASE__INST6_SEG0 0
+#define FUSE_BASE__INST6_SEG1 0
+#define FUSE_BASE__INST6_SEG2 0
+#define FUSE_BASE__INST6_SEG3 0
+#define FUSE_BASE__INST6_SEG4 0
+#define FUSE_BASE__INST6_SEG5 0
+
+#define GC_BASE__INST0_SEG0 0x00002000
+#define GC_BASE__INST0_SEG1 0x0000A000
+#define GC_BASE__INST0_SEG2 0x02402C00
+#define GC_BASE__INST0_SEG3 0
+#define GC_BASE__INST0_SEG4 0
+#define GC_BASE__INST0_SEG5 0
+
+#define GC_BASE__INST1_SEG0 0
+#define GC_BASE__INST1_SEG1 0
+#define GC_BASE__INST1_SEG2 0
+#define GC_BASE__INST1_SEG3 0
+#define GC_BASE__INST1_SEG4 0
+#define GC_BASE__INST1_SEG5 0
+
+#define GC_BASE__INST2_SEG0 0
+#define GC_BASE__INST2_SEG1 0
+#define GC_BASE__INST2_SEG2 0
+#define GC_BASE__INST2_SEG3 0
+#define GC_BASE__INST2_SEG4 0
+#define GC_BASE__INST2_SEG5 0
+
+#define GC_BASE__INST3_SEG0 0
+#define GC_BASE__INST3_SEG1 0
+#define GC_BASE__INST3_SEG2 0
+#define GC_BASE__INST3_SEG3 0
+#define GC_BASE__INST3_SEG4 0
+#define GC_BASE__INST3_SEG5 0
+
+#define GC_BASE__INST4_SEG0 0
+#define GC_BASE__INST4_SEG1 0
+#define GC_BASE__INST4_SEG2 0
+#define GC_BASE__INST4_SEG3 0
+#define GC_BASE__INST4_SEG4 0
+#define GC_BASE__INST4_SEG5 0
+
+#define GC_BASE__INST5_SEG0 0
+#define GC_BASE__INST5_SEG1 0
+#define GC_BASE__INST5_SEG2 0
+#define GC_BASE__INST5_SEG3 0
+#define GC_BASE__INST5_SEG4 0
+#define GC_BASE__INST5_SEG5 0
+
+#define GC_BASE__INST6_SEG0 0
+#define GC_BASE__INST6_SEG1 0
+#define GC_BASE__INST6_SEG2 0
+#define GC_BASE__INST6_SEG3 0
+#define GC_BASE__INST6_SEG4 0
+#define GC_BASE__INST6_SEG5 0
+
+#define HDP_BASE__INST0_SEG0 0x00000F20
+#define HDP_BASE__INST0_SEG1 0x0240A400
+#define HDP_BASE__INST0_SEG2 0
+#define HDP_BASE__INST0_SEG3 0
+#define HDP_BASE__INST0_SEG4 0
+#define HDP_BASE__INST0_SEG5 0
+
+#define HDP_BASE__INST1_SEG0 0
+#define HDP_BASE__INST1_SEG1 0
+#define HDP_BASE__INST1_SEG2 0
+#define HDP_BASE__INST1_SEG3 0
+#define HDP_BASE__INST1_SEG4 0
+#define HDP_BASE__INST1_SEG5 0
+
+#define HDP_BASE__INST2_SEG0 0
+#define HDP_BASE__INST2_SEG1 0
+#define HDP_BASE__INST2_SEG2 0
+#define HDP_BASE__INST2_SEG3 0
+#define HDP_BASE__INST2_SEG4 0
+#define HDP_BASE__INST2_SEG5 0
+
+#define HDP_BASE__INST3_SEG0 0
+#define HDP_BASE__INST3_SEG1 0
+#define HDP_BASE__INST3_SEG2 0
+#define HDP_BASE__INST3_SEG3 0
+#define HDP_BASE__INST3_SEG4 0
+#define HDP_BASE__INST3_SEG5 0
+
+#define HDP_BASE__INST4_SEG0 0
+#define HDP_BASE__INST4_SEG1 0
+#define HDP_BASE__INST4_SEG2 0
+#define HDP_BASE__INST4_SEG3 0
+#define HDP_BASE__INST4_SEG4 0
+#define HDP_BASE__INST4_SEG5 0
+
+#define HDP_BASE__INST5_SEG0 0
+#define HDP_BASE__INST5_SEG1 0
+#define HDP_BASE__INST5_SEG2 0
+#define HDP_BASE__INST5_SEG3 0
+#define HDP_BASE__INST5_SEG4 0
+#define HDP_BASE__INST5_SEG5 0
+
+#define HDP_BASE__INST6_SEG0 0
+#define HDP_BASE__INST6_SEG1 0
+#define HDP_BASE__INST6_SEG2 0
+#define HDP_BASE__INST6_SEG3 0
+#define HDP_BASE__INST6_SEG4 0
+#define HDP_BASE__INST6_SEG5 0
+
+#define IOAGR0_BASE__INST0_SEG0 0x02419000
+#define IOAGR0_BASE__INST0_SEG1 0x056C0000
+#define IOAGR0_BASE__INST0_SEG2 0
+#define IOAGR0_BASE__INST0_SEG3 0
+#define IOAGR0_BASE__INST0_SEG4 0
+#define IOAGR0_BASE__INST0_SEG5 0
+
+#define IOAGR0_BASE__INST1_SEG0 0
+#define IOAGR0_BASE__INST1_SEG1 0
+#define IOAGR0_BASE__INST1_SEG2 0
+#define IOAGR0_BASE__INST1_SEG3 0
+#define IOAGR0_BASE__INST1_SEG4 0
+#define IOAGR0_BASE__INST1_SEG5 0
+
+#define IOAGR0_BASE__INST2_SEG0 0
+#define IOAGR0_BASE__INST2_SEG1 0
+#define IOAGR0_BASE__INST2_SEG2 0
+#define IOAGR0_BASE__INST2_SEG3 0
+#define IOAGR0_BASE__INST2_SEG4 0
+#define IOAGR0_BASE__INST2_SEG5 0
+
+#define IOAGR0_BASE__INST3_SEG0 0
+#define IOAGR0_BASE__INST3_SEG1 0
+#define IOAGR0_BASE__INST3_SEG2 0
+#define IOAGR0_BASE__INST3_SEG3 0
+#define IOAGR0_BASE__INST3_SEG4 0
+#define IOAGR0_BASE__INST3_SEG5 0
+
+#define IOAGR0_BASE__INST4_SEG0 0
+#define IOAGR0_BASE__INST4_SEG1 0
+#define IOAGR0_BASE__INST4_SEG2 0
+#define IOAGR0_BASE__INST4_SEG3 0
+#define IOAGR0_BASE__INST4_SEG4 0
+#define IOAGR0_BASE__INST4_SEG5 0
+
+#define IOAGR0_BASE__INST5_SEG0 0
+#define IOAGR0_BASE__INST5_SEG1 0
+#define IOAGR0_BASE__INST5_SEG2 0
+#define IOAGR0_BASE__INST5_SEG3 0
+#define IOAGR0_BASE__INST5_SEG4 0
+#define IOAGR0_BASE__INST5_SEG5 0
+
+#define IOAGR0_BASE__INST6_SEG0 0
+#define IOAGR0_BASE__INST6_SEG1 0
+#define IOAGR0_BASE__INST6_SEG2 0
+#define IOAGR0_BASE__INST6_SEG3 0
+#define IOAGR0_BASE__INST6_SEG4 0
+#define IOAGR0_BASE__INST6_SEG5 0
+
+#define IOAPIC0_BASE__INST0_SEG0 0x00A00000
+#define IOAPIC0_BASE__INST0_SEG1 0x0241F000
+#define IOAPIC0_BASE__INST0_SEG2 0x050C0000
+#define IOAPIC0_BASE__INST0_SEG3 0
+#define IOAPIC0_BASE__INST0_SEG4 0
+#define IOAPIC0_BASE__INST0_SEG5 0
+
+#define IOAPIC0_BASE__INST1_SEG0 0
+#define IOAPIC0_BASE__INST1_SEG1 0
+#define IOAPIC0_BASE__INST1_SEG2 0
+#define IOAPIC0_BASE__INST1_SEG3 0
+#define IOAPIC0_BASE__INST1_SEG4 0
+#define IOAPIC0_BASE__INST1_SEG5 0
+
+#define IOAPIC0_BASE__INST2_SEG0 0
+#define IOAPIC0_BASE__INST2_SEG1 0
+#define IOAPIC0_BASE__INST2_SEG2 0
+#define IOAPIC0_BASE__INST2_SEG3 0
+#define IOAPIC0_BASE__INST2_SEG4 0
+#define IOAPIC0_BASE__INST2_SEG5 0
+
+#define IOAPIC0_BASE__INST3_SEG0 0
+#define IOAPIC0_BASE__INST3_SEG1 0
+#define IOAPIC0_BASE__INST3_SEG2 0
+#define IOAPIC0_BASE__INST3_SEG3 0
+#define IOAPIC0_BASE__INST3_SEG4 0
+#define IOAPIC0_BASE__INST3_SEG5 0
+
+#define IOAPIC0_BASE__INST4_SEG0 0
+#define IOAPIC0_BASE__INST4_SEG1 0
+#define IOAPIC0_BASE__INST4_SEG2 0
+#define IOAPIC0_BASE__INST4_SEG3 0
+#define IOAPIC0_BASE__INST4_SEG4 0
+#define IOAPIC0_BASE__INST4_SEG5 0
+
+#define IOAPIC0_BASE__INST5_SEG0 0
+#define IOAPIC0_BASE__INST5_SEG1 0
+#define IOAPIC0_BASE__INST5_SEG2 0
+#define IOAPIC0_BASE__INST5_SEG3 0
+#define IOAPIC0_BASE__INST5_SEG4 0
+#define IOAPIC0_BASE__INST5_SEG5 0
+
+#define IOAPIC0_BASE__INST6_SEG0 0
+#define IOAPIC0_BASE__INST6_SEG1 0
+#define IOAPIC0_BASE__INST6_SEG2 0
+#define IOAPIC0_BASE__INST6_SEG3 0
+#define IOAPIC0_BASE__INST6_SEG4 0
+#define IOAPIC0_BASE__INST6_SEG5 0
+
+#define IOHC0_BASE__INST0_SEG0 0x00010000
+#define IOHC0_BASE__INST0_SEG1 0x02406000
+#define IOHC0_BASE__INST0_SEG2 0x04EC0000
+#define IOHC0_BASE__INST0_SEG3 0
+#define IOHC0_BASE__INST0_SEG4 0
+#define IOHC0_BASE__INST0_SEG5 0
+
+#define IOHC0_BASE__INST1_SEG0 0
+#define IOHC0_BASE__INST1_SEG1 0
+#define IOHC0_BASE__INST1_SEG2 0
+#define IOHC0_BASE__INST1_SEG3 0
+#define IOHC0_BASE__INST1_SEG4 0
+#define IOHC0_BASE__INST1_SEG5 0
+
+#define IOHC0_BASE__INST2_SEG0 0
+#define IOHC0_BASE__INST2_SEG1 0
+#define IOHC0_BASE__INST2_SEG2 0
+#define IOHC0_BASE__INST2_SEG3 0
+#define IOHC0_BASE__INST2_SEG4 0
+#define IOHC0_BASE__INST2_SEG5 0
+
+#define IOHC0_BASE__INST3_SEG0 0
+#define IOHC0_BASE__INST3_SEG1 0
+#define IOHC0_BASE__INST3_SEG2 0
+#define IOHC0_BASE__INST3_SEG3 0
+#define IOHC0_BASE__INST3_SEG4 0
+#define IOHC0_BASE__INST3_SEG5 0
+
+#define IOHC0_BASE__INST4_SEG0 0
+#define IOHC0_BASE__INST4_SEG1 0
+#define IOHC0_BASE__INST4_SEG2 0
+#define IOHC0_BASE__INST4_SEG3 0
+#define IOHC0_BASE__INST4_SEG4 0
+#define IOHC0_BASE__INST4_SEG5 0
+
+#define IOHC0_BASE__INST5_SEG0 0
+#define IOHC0_BASE__INST5_SEG1 0
+#define IOHC0_BASE__INST5_SEG2 0
+#define IOHC0_BASE__INST5_SEG3 0
+#define IOHC0_BASE__INST5_SEG4 0
+#define IOHC0_BASE__INST5_SEG5 0
+
+#define IOHC0_BASE__INST6_SEG0 0
+#define IOHC0_BASE__INST6_SEG1 0
+#define IOHC0_BASE__INST6_SEG2 0
+#define IOHC0_BASE__INST6_SEG3 0
+#define IOHC0_BASE__INST6_SEG4 0
+#define IOHC0_BASE__INST6_SEG5 0
+
+#define L1IMUIOAGR0_BASE__INST0_SEG0 0x0240CC00
+#define L1IMUIOAGR0_BASE__INST0_SEG1 0x05200000
+#define L1IMUIOAGR0_BASE__INST0_SEG2 0
+#define L1IMUIOAGR0_BASE__INST0_SEG3 0
+#define L1IMUIOAGR0_BASE__INST0_SEG4 0
+#define L1IMUIOAGR0_BASE__INST0_SEG5 0
+
+#define L1IMUIOAGR0_BASE__INST1_SEG0 0
+#define L1IMUIOAGR0_BASE__INST1_SEG1 0
+#define L1IMUIOAGR0_BASE__INST1_SEG2 0
+#define L1IMUIOAGR0_BASE__INST1_SEG3 0
+#define L1IMUIOAGR0_BASE__INST1_SEG4 0
+#define L1IMUIOAGR0_BASE__INST1_SEG5 0
+
+#define L1IMUIOAGR0_BASE__INST2_SEG0 0
+#define L1IMUIOAGR0_BASE__INST2_SEG1 0
+#define L1IMUIOAGR0_BASE__INST2_SEG2 0
+#define L1IMUIOAGR0_BASE__INST2_SEG3 0
+#define L1IMUIOAGR0_BASE__INST2_SEG4 0
+#define L1IMUIOAGR0_BASE__INST2_SEG5 0
+
+#define L1IMUIOAGR0_BASE__INST3_SEG0 0
+#define L1IMUIOAGR0_BASE__INST3_SEG1 0
+#define L1IMUIOAGR0_BASE__INST3_SEG2 0
+#define L1IMUIOAGR0_BASE__INST3_SEG3 0
+#define L1IMUIOAGR0_BASE__INST3_SEG4 0
+#define L1IMUIOAGR0_BASE__INST3_SEG5 0
+
+#define L1IMUIOAGR0_BASE__INST4_SEG0 0
+#define L1IMUIOAGR0_BASE__INST4_SEG1 0
+#define L1IMUIOAGR0_BASE__INST4_SEG2 0
+#define L1IMUIOAGR0_BASE__INST4_SEG3 0
+#define L1IMUIOAGR0_BASE__INST4_SEG4 0
+#define L1IMUIOAGR0_BASE__INST4_SEG5 0
+
+#define L1IMUIOAGR0_BASE__INST5_SEG0 0
+#define L1IMUIOAGR0_BASE__INST5_SEG1 0
+#define L1IMUIOAGR0_BASE__INST5_SEG2 0
+#define L1IMUIOAGR0_BASE__INST5_SEG3 0
+#define L1IMUIOAGR0_BASE__INST5_SEG4 0
+#define L1IMUIOAGR0_BASE__INST5_SEG5 0
+
+#define L1IMUIOAGR0_BASE__INST6_SEG0 0
+#define L1IMUIOAGR0_BASE__INST6_SEG1 0
+#define L1IMUIOAGR0_BASE__INST6_SEG2 0
+#define L1IMUIOAGR0_BASE__INST6_SEG3 0
+#define L1IMUIOAGR0_BASE__INST6_SEG4 0
+#define L1IMUIOAGR0_BASE__INST6_SEG5 0
+
+#define L1IMUPCIE0_BASE__INST0_SEG0 0x0240C800
+#define L1IMUPCIE0_BASE__INST0_SEG1 0x051C0000
+#define L1IMUPCIE0_BASE__INST0_SEG2 0
+#define L1IMUPCIE0_BASE__INST0_SEG3 0
+#define L1IMUPCIE0_BASE__INST0_SEG4 0
+#define L1IMUPCIE0_BASE__INST0_SEG5 0
+
+#define L1IMUPCIE0_BASE__INST1_SEG0 0
+#define L1IMUPCIE0_BASE__INST1_SEG1 0
+#define L1IMUPCIE0_BASE__INST1_SEG2 0
+#define L1IMUPCIE0_BASE__INST1_SEG3 0
+#define L1IMUPCIE0_BASE__INST1_SEG4 0
+#define L1IMUPCIE0_BASE__INST1_SEG5 0
+
+#define L1IMUPCIE0_BASE__INST2_SEG0 0
+#define L1IMUPCIE0_BASE__INST2_SEG1 0
+#define L1IMUPCIE0_BASE__INST2_SEG2 0
+#define L1IMUPCIE0_BASE__INST2_SEG3 0
+#define L1IMUPCIE0_BASE__INST2_SEG4 0
+#define L1IMUPCIE0_BASE__INST2_SEG5 0
+
+#define L1IMUPCIE0_BASE__INST3_SEG0 0
+#define L1IMUPCIE0_BASE__INST3_SEG1 0
+#define L1IMUPCIE0_BASE__INST3_SEG2 0
+#define L1IMUPCIE0_BASE__INST3_SEG3 0
+#define L1IMUPCIE0_BASE__INST3_SEG4 0
+#define L1IMUPCIE0_BASE__INST3_SEG5 0
+
+#define L1IMUPCIE0_BASE__INST4_SEG0 0
+#define L1IMUPCIE0_BASE__INST4_SEG1 0
+#define L1IMUPCIE0_BASE__INST4_SEG2 0
+#define L1IMUPCIE0_BASE__INST4_SEG3 0
+#define L1IMUPCIE0_BASE__INST4_SEG4 0
+#define L1IMUPCIE0_BASE__INST4_SEG5 0
+
+#define L1IMUPCIE0_BASE__INST5_SEG0 0
+#define L1IMUPCIE0_BASE__INST5_SEG1 0
+#define L1IMUPCIE0_BASE__INST5_SEG2 0
+#define L1IMUPCIE0_BASE__INST5_SEG3 0
+#define L1IMUPCIE0_BASE__INST5_SEG4 0
+#define L1IMUPCIE0_BASE__INST5_SEG5 0
+
+#define L1IMUPCIE0_BASE__INST6_SEG0 0
+#define L1IMUPCIE0_BASE__INST6_SEG1 0
+#define L1IMUPCIE0_BASE__INST6_SEG2 0
+#define L1IMUPCIE0_BASE__INST6_SEG3 0
+#define L1IMUPCIE0_BASE__INST6_SEG4 0
+#define L1IMUPCIE0_BASE__INST6_SEG5 0
+
+#define L2IMU0_BASE__INST0_SEG0 0x00007DC0
+#define L2IMU0_BASE__INST0_SEG1 0x00900000
+#define L2IMU0_BASE__INST0_SEG2 0x02407000
+#define L2IMU0_BASE__INST0_SEG3 0x04FC0000
+#define L2IMU0_BASE__INST0_SEG4 0x055C0000
+#define L2IMU0_BASE__INST0_SEG5 0
+
+#define L2IMU0_BASE__INST1_SEG0 0
+#define L2IMU0_BASE__INST1_SEG1 0
+#define L2IMU0_BASE__INST1_SEG2 0
+#define L2IMU0_BASE__INST1_SEG3 0
+#define L2IMU0_BASE__INST1_SEG4 0
+#define L2IMU0_BASE__INST1_SEG5 0
+
+#define L2IMU0_BASE__INST2_SEG0 0
+#define L2IMU0_BASE__INST2_SEG1 0
+#define L2IMU0_BASE__INST2_SEG2 0
+#define L2IMU0_BASE__INST2_SEG3 0
+#define L2IMU0_BASE__INST2_SEG4 0
+#define L2IMU0_BASE__INST2_SEG5 0
+
+#define L2IMU0_BASE__INST3_SEG0 0
+#define L2IMU0_BASE__INST3_SEG1 0
+#define L2IMU0_BASE__INST3_SEG2 0
+#define L2IMU0_BASE__INST3_SEG3 0
+#define L2IMU0_BASE__INST3_SEG4 0
+#define L2IMU0_BASE__INST3_SEG5 0
+
+#define L2IMU0_BASE__INST4_SEG0 0
+#define L2IMU0_BASE__INST4_SEG1 0
+#define L2IMU0_BASE__INST4_SEG2 0
+#define L2IMU0_BASE__INST4_SEG3 0
+#define L2IMU0_BASE__INST4_SEG4 0
+#define L2IMU0_BASE__INST4_SEG5 0
+
+#define L2IMU0_BASE__INST5_SEG0 0
+#define L2IMU0_BASE__INST5_SEG1 0
+#define L2IMU0_BASE__INST5_SEG2 0
+#define L2IMU0_BASE__INST5_SEG3 0
+#define L2IMU0_BASE__INST5_SEG4 0
+#define L2IMU0_BASE__INST5_SEG5 0
+
+#define L2IMU0_BASE__INST6_SEG0 0
+#define L2IMU0_BASE__INST6_SEG1 0
+#define L2IMU0_BASE__INST6_SEG2 0
+#define L2IMU0_BASE__INST6_SEG3 0
+#define L2IMU0_BASE__INST6_SEG4 0
+#define L2IMU0_BASE__INST6_SEG5 0
+
+#define MMHUB_BASE__INST0_SEG0 0x0001A000
+#define MMHUB_BASE__INST0_SEG1 0x02408800
+#define MMHUB_BASE__INST0_SEG2 0
+#define MMHUB_BASE__INST0_SEG3 0
+#define MMHUB_BASE__INST0_SEG4 0
+#define MMHUB_BASE__INST0_SEG5 0
+
+#define MMHUB_BASE__INST1_SEG0 0
+#define MMHUB_BASE__INST1_SEG1 0
+#define MMHUB_BASE__INST1_SEG2 0
+#define MMHUB_BASE__INST1_SEG3 0
+#define MMHUB_BASE__INST1_SEG4 0
+#define MMHUB_BASE__INST1_SEG5 0
+
+#define MMHUB_BASE__INST2_SEG0 0
+#define MMHUB_BASE__INST2_SEG1 0
+#define MMHUB_BASE__INST2_SEG2 0
+#define MMHUB_BASE__INST2_SEG3 0
+#define MMHUB_BASE__INST2_SEG4 0
+#define MMHUB_BASE__INST2_SEG5 0
+
+#define MMHUB_BASE__INST3_SEG0 0
+#define MMHUB_BASE__INST3_SEG1 0
+#define MMHUB_BASE__INST3_SEG2 0
+#define MMHUB_BASE__INST3_SEG3 0
+#define MMHUB_BASE__INST3_SEG4 0
+#define MMHUB_BASE__INST3_SEG5 0
+
+#define MMHUB_BASE__INST4_SEG0 0
+#define MMHUB_BASE__INST4_SEG1 0
+#define MMHUB_BASE__INST4_SEG2 0
+#define MMHUB_BASE__INST4_SEG3 0
+#define MMHUB_BASE__INST4_SEG4 0
+#define MMHUB_BASE__INST4_SEG5 0
+
+#define MMHUB_BASE__INST5_SEG0 0
+#define MMHUB_BASE__INST5_SEG1 0
+#define MMHUB_BASE__INST5_SEG2 0
+#define MMHUB_BASE__INST5_SEG3 0
+#define MMHUB_BASE__INST5_SEG4 0
+#define MMHUB_BASE__INST5_SEG5 0
+
+#define MMHUB_BASE__INST6_SEG0 0
+#define MMHUB_BASE__INST6_SEG1 0
+#define MMHUB_BASE__INST6_SEG2 0
+#define MMHUB_BASE__INST6_SEG3 0
+#define MMHUB_BASE__INST6_SEG4 0
+#define MMHUB_BASE__INST6_SEG5 0
+
+#define MP0_BASE__INST0_SEG0 0x00016000
+#define MP0_BASE__INST0_SEG1 0x00DC0000
+#define MP0_BASE__INST0_SEG2 0x00E00000
+#define MP0_BASE__INST0_SEG3 0x00E40000
+#define MP0_BASE__INST0_SEG4 0x0243FC00
+#define MP0_BASE__INST0_SEG5 0
+
+#define MP0_BASE__INST1_SEG0 0
+#define MP0_BASE__INST1_SEG1 0
+#define MP0_BASE__INST1_SEG2 0
+#define MP0_BASE__INST1_SEG3 0
+#define MP0_BASE__INST1_SEG4 0
+#define MP0_BASE__INST1_SEG5 0
+
+#define MP0_BASE__INST2_SEG0 0
+#define MP0_BASE__INST2_SEG1 0
+#define MP0_BASE__INST2_SEG2 0
+#define MP0_BASE__INST2_SEG3 0
+#define MP0_BASE__INST2_SEG4 0
+#define MP0_BASE__INST2_SEG5 0
+
+#define MP0_BASE__INST3_SEG0 0
+#define MP0_BASE__INST3_SEG1 0
+#define MP0_BASE__INST3_SEG2 0
+#define MP0_BASE__INST3_SEG3 0
+#define MP0_BASE__INST3_SEG4 0
+#define MP0_BASE__INST3_SEG5 0
+
+#define MP0_BASE__INST4_SEG0 0
+#define MP0_BASE__INST4_SEG1 0
+#define MP0_BASE__INST4_SEG2 0
+#define MP0_BASE__INST4_SEG3 0
+#define MP0_BASE__INST4_SEG4 0
+#define MP0_BASE__INST4_SEG5 0
+
+#define MP0_BASE__INST5_SEG0 0
+#define MP0_BASE__INST5_SEG1 0
+#define MP0_BASE__INST5_SEG2 0
+#define MP0_BASE__INST5_SEG3 0
+#define MP0_BASE__INST5_SEG4 0
+#define MP0_BASE__INST5_SEG5 0
+
+#define MP0_BASE__INST6_SEG0 0
+#define MP0_BASE__INST6_SEG1 0
+#define MP0_BASE__INST6_SEG2 0
+#define MP0_BASE__INST6_SEG3 0
+#define MP0_BASE__INST6_SEG4 0
+#define MP0_BASE__INST6_SEG5 0
+
+#define MP1_BASE__INST0_SEG0 0x00016000
+#define MP1_BASE__INST0_SEG1 0x00DC0000
+#define MP1_BASE__INST0_SEG2 0x00E00000
+#define MP1_BASE__INST0_SEG3 0x00E40000
+#define MP1_BASE__INST0_SEG4 0x0243FC00
+#define MP1_BASE__INST0_SEG5 0
+
+#define MP1_BASE__INST1_SEG0 0
+#define MP1_BASE__INST1_SEG1 0
+#define MP1_BASE__INST1_SEG2 0
+#define MP1_BASE__INST1_SEG3 0
+#define MP1_BASE__INST1_SEG4 0
+#define MP1_BASE__INST1_SEG5 0
+
+#define MP1_BASE__INST2_SEG0 0
+#define MP1_BASE__INST2_SEG1 0
+#define MP1_BASE__INST2_SEG2 0
+#define MP1_BASE__INST2_SEG3 0
+#define MP1_BASE__INST2_SEG4 0
+#define MP1_BASE__INST2_SEG5 0
+
+#define MP1_BASE__INST3_SEG0 0
+#define MP1_BASE__INST3_SEG1 0
+#define MP1_BASE__INST3_SEG2 0
+#define MP1_BASE__INST3_SEG3 0
+#define MP1_BASE__INST3_SEG4 0
+#define MP1_BASE__INST3_SEG5 0
+
+#define MP1_BASE__INST4_SEG0 0
+#define MP1_BASE__INST4_SEG1 0
+#define MP1_BASE__INST4_SEG2 0
+#define MP1_BASE__INST4_SEG3 0
+#define MP1_BASE__INST4_SEG4 0
+#define MP1_BASE__INST4_SEG5 0
+
+#define MP1_BASE__INST5_SEG0 0
+#define MP1_BASE__INST5_SEG1 0
+#define MP1_BASE__INST5_SEG2 0
+#define MP1_BASE__INST5_SEG3 0
+#define MP1_BASE__INST5_SEG4 0
+#define MP1_BASE__INST5_SEG5 0
+
+#define MP1_BASE__INST6_SEG0 0
+#define MP1_BASE__INST6_SEG1 0
+#define MP1_BASE__INST6_SEG2 0
+#define MP1_BASE__INST6_SEG3 0
+#define MP1_BASE__INST6_SEG4 0
+#define MP1_BASE__INST6_SEG5 0
+
+#define NBIO_BASE__INST0_SEG0 0x00000000
+#define NBIO_BASE__INST0_SEG1 0x00000014
+#define NBIO_BASE__INST0_SEG2 0x00000D20
+#define NBIO_BASE__INST0_SEG3 0x00010400
+#define NBIO_BASE__INST0_SEG4 0x0241B000
+#define NBIO_BASE__INST0_SEG5 0x04040000
+
+#define NBIO_BASE__INST1_SEG0 0
+#define NBIO_BASE__INST1_SEG1 0
+#define NBIO_BASE__INST1_SEG2 0
+#define NBIO_BASE__INST1_SEG3 0
+#define NBIO_BASE__INST1_SEG4 0
+#define NBIO_BASE__INST1_SEG5 0
+
+#define NBIO_BASE__INST2_SEG0 0
+#define NBIO_BASE__INST2_SEG1 0
+#define NBIO_BASE__INST2_SEG2 0
+#define NBIO_BASE__INST2_SEG3 0
+#define NBIO_BASE__INST2_SEG4 0
+#define NBIO_BASE__INST2_SEG5 0
+
+#define NBIO_BASE__INST3_SEG0 0
+#define NBIO_BASE__INST3_SEG1 0
+#define NBIO_BASE__INST3_SEG2 0
+#define NBIO_BASE__INST3_SEG3 0
+#define NBIO_BASE__INST3_SEG4 0
+#define NBIO_BASE__INST3_SEG5 0
+
+#define NBIO_BASE__INST4_SEG0 0
+#define NBIO_BASE__INST4_SEG1 0
+#define NBIO_BASE__INST4_SEG2 0
+#define NBIO_BASE__INST4_SEG3 0
+#define NBIO_BASE__INST4_SEG4 0
+#define NBIO_BASE__INST4_SEG5 0
+
+#define NBIO_BASE__INST5_SEG0 0
+#define NBIO_BASE__INST5_SEG1 0
+#define NBIO_BASE__INST5_SEG2 0
+#define NBIO_BASE__INST5_SEG3 0
+#define NBIO_BASE__INST5_SEG4 0
+#define NBIO_BASE__INST5_SEG5 0
+
+#define NBIO_BASE__INST6_SEG0 0
+#define NBIO_BASE__INST6_SEG1 0
+#define NBIO_BASE__INST6_SEG2 0
+#define NBIO_BASE__INST6_SEG3 0
+#define NBIO_BASE__INST6_SEG4 0
+#define NBIO_BASE__INST6_SEG5 0
+
+#define OSSSYS_BASE__INST0_SEG0 0x000010A0
+#define OSSSYS_BASE__INST0_SEG1 0x0240A000
+#define OSSSYS_BASE__INST0_SEG2 0
+#define OSSSYS_BASE__INST0_SEG3 0
+#define OSSSYS_BASE__INST0_SEG4 0
+#define OSSSYS_BASE__INST0_SEG5 0
+
+#define OSSSYS_BASE__INST1_SEG0 0
+#define OSSSYS_BASE__INST1_SEG1 0
+#define OSSSYS_BASE__INST1_SEG2 0
+#define OSSSYS_BASE__INST1_SEG3 0
+#define OSSSYS_BASE__INST1_SEG4 0
+#define OSSSYS_BASE__INST1_SEG5 0
+
+#define OSSSYS_BASE__INST2_SEG0 0
+#define OSSSYS_BASE__INST2_SEG1 0
+#define OSSSYS_BASE__INST2_SEG2 0
+#define OSSSYS_BASE__INST2_SEG3 0
+#define OSSSYS_BASE__INST2_SEG4 0
+#define OSSSYS_BASE__INST2_SEG5 0
+
+#define OSSSYS_BASE__INST3_SEG0 0
+#define OSSSYS_BASE__INST3_SEG1 0
+#define OSSSYS_BASE__INST3_SEG2 0
+#define OSSSYS_BASE__INST3_SEG3 0
+#define OSSSYS_BASE__INST3_SEG4 0
+#define OSSSYS_BASE__INST3_SEG5 0
+
+#define OSSSYS_BASE__INST4_SEG0 0
+#define OSSSYS_BASE__INST4_SEG1 0
+#define OSSSYS_BASE__INST4_SEG2 0
+#define OSSSYS_BASE__INST4_SEG3 0
+#define OSSSYS_BASE__INST4_SEG4 0
+#define OSSSYS_BASE__INST4_SEG5 0
+
+#define OSSSYS_BASE__INST5_SEG0 0
+#define OSSSYS_BASE__INST5_SEG1 0
+#define OSSSYS_BASE__INST5_SEG2 0
+#define OSSSYS_BASE__INST5_SEG3 0
+#define OSSSYS_BASE__INST5_SEG4 0
+#define OSSSYS_BASE__INST5_SEG5 0
+
+#define OSSSYS_BASE__INST6_SEG0 0
+#define OSSSYS_BASE__INST6_SEG1 0
+#define OSSSYS_BASE__INST6_SEG2 0
+#define OSSSYS_BASE__INST6_SEG3 0
+#define OSSSYS_BASE__INST6_SEG4 0
+#define OSSSYS_BASE__INST6_SEG5 0
+
+#define PCIE0_BASE__INST0_SEG0 0x02411800
+#define PCIE0_BASE__INST0_SEG1 0x04440000
+#define PCIE0_BASE__INST0_SEG2 0
+#define PCIE0_BASE__INST0_SEG3 0
+#define PCIE0_BASE__INST0_SEG4 0
+#define PCIE0_BASE__INST0_SEG5 0
+
+#define PCIE0_BASE__INST1_SEG0 0
+#define PCIE0_BASE__INST1_SEG1 0
+#define PCIE0_BASE__INST1_SEG2 0
+#define PCIE0_BASE__INST1_SEG3 0
+#define PCIE0_BASE__INST1_SEG4 0
+#define PCIE0_BASE__INST1_SEG5 0
+
+#define PCIE0_BASE__INST2_SEG0 0
+#define PCIE0_BASE__INST2_SEG1 0
+#define PCIE0_BASE__INST2_SEG2 0
+#define PCIE0_BASE__INST2_SEG3 0
+#define PCIE0_BASE__INST2_SEG4 0
+#define PCIE0_BASE__INST2_SEG5 0
+
+#define PCIE0_BASE__INST3_SEG0 0
+#define PCIE0_BASE__INST3_SEG1 0
+#define PCIE0_BASE__INST3_SEG2 0
+#define PCIE0_BASE__INST3_SEG3 0
+#define PCIE0_BASE__INST3_SEG4 0
+#define PCIE0_BASE__INST3_SEG5 0
+
+#define PCIE0_BASE__INST4_SEG0 0
+#define PCIE0_BASE__INST4_SEG1 0
+#define PCIE0_BASE__INST4_SEG2 0
+#define PCIE0_BASE__INST4_SEG3 0
+#define PCIE0_BASE__INST4_SEG4 0
+#define PCIE0_BASE__INST4_SEG5 0
+
+#define PCIE0_BASE__INST5_SEG0 0
+#define PCIE0_BASE__INST5_SEG1 0
+#define PCIE0_BASE__INST5_SEG2 0
+#define PCIE0_BASE__INST5_SEG3 0
+#define PCIE0_BASE__INST5_SEG4 0
+#define PCIE0_BASE__INST5_SEG5 0
+
+#define PCIE0_BASE__INST6_SEG0 0
+#define PCIE0_BASE__INST6_SEG1 0
+#define PCIE0_BASE__INST6_SEG2 0
+#define PCIE0_BASE__INST6_SEG3 0
+#define PCIE0_BASE__INST6_SEG4 0
+#define PCIE0_BASE__INST6_SEG5 0
+
+#define SDMA0_BASE__INST0_SEG0 0x00001260
+#define SDMA0_BASE__INST0_SEG1 0x02445400
+#define SDMA0_BASE__INST0_SEG2 0
+#define SDMA0_BASE__INST0_SEG3 0
+#define SDMA0_BASE__INST0_SEG4 0
+#define SDMA0_BASE__INST0_SEG5 0
+
+#define SDMA0_BASE__INST1_SEG0 0
+#define SDMA0_BASE__INST1_SEG1 0
+#define SDMA0_BASE__INST1_SEG2 0
+#define SDMA0_BASE__INST1_SEG3 0
+#define SDMA0_BASE__INST1_SEG4 0
+#define SDMA0_BASE__INST1_SEG5 0
+
+#define SDMA0_BASE__INST2_SEG0 0
+#define SDMA0_BASE__INST2_SEG1 0
+#define SDMA0_BASE__INST2_SEG2 0
+#define SDMA0_BASE__INST2_SEG3 0
+#define SDMA0_BASE__INST2_SEG4 0
+#define SDMA0_BASE__INST2_SEG5 0
+
+#define SDMA0_BASE__INST3_SEG0 0
+#define SDMA0_BASE__INST3_SEG1 0
+#define SDMA0_BASE__INST3_SEG2 0
+#define SDMA0_BASE__INST3_SEG3 0
+#define SDMA0_BASE__INST3_SEG4 0
+#define SDMA0_BASE__INST3_SEG5 0
+
+#define SDMA0_BASE__INST4_SEG0 0
+#define SDMA0_BASE__INST4_SEG1 0
+#define SDMA0_BASE__INST4_SEG2 0
+#define SDMA0_BASE__INST4_SEG3 0
+#define SDMA0_BASE__INST4_SEG4 0
+#define SDMA0_BASE__INST4_SEG5 0
+
+#define SDMA0_BASE__INST5_SEG0 0
+#define SDMA0_BASE__INST5_SEG1 0
+#define SDMA0_BASE__INST5_SEG2 0
+#define SDMA0_BASE__INST5_SEG3 0
+#define SDMA0_BASE__INST5_SEG4 0
+#define SDMA0_BASE__INST5_SEG5 0
+
+#define SDMA0_BASE__INST6_SEG0 0
+#define SDMA0_BASE__INST6_SEG1 0
+#define SDMA0_BASE__INST6_SEG2 0
+#define SDMA0_BASE__INST6_SEG3 0
+#define SDMA0_BASE__INST6_SEG4 0
+#define SDMA0_BASE__INST6_SEG5 0
+
+#define SDMA1_BASE__INST0_SEG0 0x00001860
+#define SDMA1_BASE__INST0_SEG1 0x02445800
+#define SDMA1_BASE__INST0_SEG2 0
+#define SDMA1_BASE__INST0_SEG3 0
+#define SDMA1_BASE__INST0_SEG4 0
+#define SDMA1_BASE__INST0_SEG5 0
+
+#define SDMA1_BASE__INST1_SEG0 0x0001E000
+#define SDMA1_BASE__INST1_SEG1 0x02446400
+#define SDMA1_BASE__INST1_SEG2 0
+#define SDMA1_BASE__INST1_SEG3 0
+#define SDMA1_BASE__INST1_SEG4 0
+#define SDMA1_BASE__INST1_SEG5 0
+
+#define SDMA1_BASE__INST2_SEG0 0x0001E400
+#define SDMA1_BASE__INST2_SEG1 0x02446800
+#define SDMA1_BASE__INST2_SEG2 0
+#define SDMA1_BASE__INST2_SEG3 0
+#define SDMA1_BASE__INST2_SEG4 0
+#define SDMA1_BASE__INST2_SEG5 0
+
+#define SDMA1_BASE__INST3_SEG0 0x0001E800
+#define SDMA1_BASE__INST3_SEG1 0x02446C00
+#define SDMA1_BASE__INST3_SEG2 0
+#define SDMA1_BASE__INST3_SEG3 0
+#define SDMA1_BASE__INST3_SEG4 0
+#define SDMA1_BASE__INST3_SEG5 0
+
+#define SDMA1_BASE__INST4_SEG0 0
+#define SDMA1_BASE__INST4_SEG1 0
+#define SDMA1_BASE__INST4_SEG2 0
+#define SDMA1_BASE__INST4_SEG3 0
+#define SDMA1_BASE__INST4_SEG4 0
+#define SDMA1_BASE__INST4_SEG5 0
+
+#define SDMA1_BASE__INST5_SEG0 0
+#define SDMA1_BASE__INST5_SEG1 0
+#define SDMA1_BASE__INST5_SEG2 0
+#define SDMA1_BASE__INST5_SEG3 0
+#define SDMA1_BASE__INST5_SEG4 0
+#define SDMA1_BASE__INST5_SEG5 0
+
+#define SDMA1_BASE__INST6_SEG0 0
+#define SDMA1_BASE__INST6_SEG1 0
+#define SDMA1_BASE__INST6_SEG2 0
+#define SDMA1_BASE__INST6_SEG3 0
+#define SDMA1_BASE__INST6_SEG4 0
+#define SDMA1_BASE__INST6_SEG5 0
+
+#define SMUIO_BASE__INST0_SEG0 0x00016800
+#define SMUIO_BASE__INST0_SEG1 0x00016A00
+#define SMUIO_BASE__INST0_SEG2 0x02401000
+#define SMUIO_BASE__INST0_SEG3 0x03440000
+#define SMUIO_BASE__INST0_SEG4 0
+#define SMUIO_BASE__INST0_SEG5 0
+
+#define SMUIO_BASE__INST1_SEG0 0
+#define SMUIO_BASE__INST1_SEG1 0
+#define SMUIO_BASE__INST1_SEG2 0
+#define SMUIO_BASE__INST1_SEG3 0
+#define SMUIO_BASE__INST1_SEG4 0
+#define SMUIO_BASE__INST1_SEG5 0
+
+#define SMUIO_BASE__INST2_SEG0 0
+#define SMUIO_BASE__INST2_SEG1 0
+#define SMUIO_BASE__INST2_SEG2 0
+#define SMUIO_BASE__INST2_SEG3 0
+#define SMUIO_BASE__INST2_SEG4 0
+#define SMUIO_BASE__INST2_SEG5 0
+
+#define SMUIO_BASE__INST3_SEG0 0
+#define SMUIO_BASE__INST3_SEG1 0
+#define SMUIO_BASE__INST3_SEG2 0
+#define SMUIO_BASE__INST3_SEG3 0
+#define SMUIO_BASE__INST3_SEG4 0
+#define SMUIO_BASE__INST3_SEG5 0
+
+#define SMUIO_BASE__INST4_SEG0 0
+#define SMUIO_BASE__INST4_SEG1 0
+#define SMUIO_BASE__INST4_SEG2 0
+#define SMUIO_BASE__INST4_SEG3 0
+#define SMUIO_BASE__INST4_SEG4 0
+#define SMUIO_BASE__INST4_SEG5 0
+
+#define SMUIO_BASE__INST5_SEG0 0
+#define SMUIO_BASE__INST5_SEG1 0
+#define SMUIO_BASE__INST5_SEG2 0
+#define SMUIO_BASE__INST5_SEG3 0
+#define SMUIO_BASE__INST5_SEG4 0
+#define SMUIO_BASE__INST5_SEG5 0
+
+#define SMUIO_BASE__INST6_SEG0 0
+#define SMUIO_BASE__INST6_SEG1 0
+#define SMUIO_BASE__INST6_SEG2 0
+#define SMUIO_BASE__INST6_SEG3 0
+#define SMUIO_BASE__INST6_SEG4 0
+#define SMUIO_BASE__INST6_SEG5 0
+
+#define THM_BASE__INST0_SEG0 0x00016600
+#define THM_BASE__INST0_SEG1 0x02400C00
+#define THM_BASE__INST0_SEG2 0
+#define THM_BASE__INST0_SEG3 0
+#define THM_BASE__INST0_SEG4 0
+#define THM_BASE__INST0_SEG5 0
+
+#define THM_BASE__INST1_SEG0 0
+#define THM_BASE__INST1_SEG1 0
+#define THM_BASE__INST1_SEG2 0
+#define THM_BASE__INST1_SEG3 0
+#define THM_BASE__INST1_SEG4 0
+#define THM_BASE__INST1_SEG5 0
+
+#define THM_BASE__INST2_SEG0 0
+#define THM_BASE__INST2_SEG1 0
+#define THM_BASE__INST2_SEG2 0
+#define THM_BASE__INST2_SEG3 0
+#define THM_BASE__INST2_SEG4 0
+#define THM_BASE__INST2_SEG5 0
+
+#define THM_BASE__INST3_SEG0 0
+#define THM_BASE__INST3_SEG1 0
+#define THM_BASE__INST3_SEG2 0
+#define THM_BASE__INST3_SEG3 0
+#define THM_BASE__INST3_SEG4 0
+#define THM_BASE__INST3_SEG5 0
+
+#define THM_BASE__INST4_SEG0 0
+#define THM_BASE__INST4_SEG1 0
+#define THM_BASE__INST4_SEG2 0
+#define THM_BASE__INST4_SEG3 0
+#define THM_BASE__INST4_SEG4 0
+#define THM_BASE__INST4_SEG5 0
+
+#define THM_BASE__INST5_SEG0 0
+#define THM_BASE__INST5_SEG1 0
+#define THM_BASE__INST5_SEG2 0
+#define THM_BASE__INST5_SEG3 0
+#define THM_BASE__INST5_SEG4 0
+#define THM_BASE__INST5_SEG5 0
+
+#define THM_BASE__INST6_SEG0 0
+#define THM_BASE__INST6_SEG1 0
+#define THM_BASE__INST6_SEG2 0
+#define THM_BASE__INST6_SEG3 0
+#define THM_BASE__INST6_SEG4 0
+#define THM_BASE__INST6_SEG5 0
+
+#define UMC_BASE__INST0_SEG0 0x00014000
+#define UMC_BASE__INST0_SEG1 0x00054000
+#define UMC_BASE__INST0_SEG2 0x02425800
+#define UMC_BASE__INST0_SEG3 0
+#define UMC_BASE__INST0_SEG4 0
+#define UMC_BASE__INST0_SEG5 0
+
+#define UMC_BASE__INST1_SEG0 0x00094000
+#define UMC_BASE__INST1_SEG1 0x000D4000
+#define UMC_BASE__INST1_SEG2 0x02425C00
+#define UMC_BASE__INST1_SEG3 0
+#define UMC_BASE__INST1_SEG4 0
+#define UMC_BASE__INST1_SEG5 0
+
+#define UMC_BASE__INST2_SEG0 0x00114000
+#define UMC_BASE__INST2_SEG1 0x00154000
+#define UMC_BASE__INST2_SEG2 0x02426000
+#define UMC_BASE__INST2_SEG3 0
+#define UMC_BASE__INST2_SEG4 0
+#define UMC_BASE__INST2_SEG5 0
+
+#define UMC_BASE__INST3_SEG0 0x00194000
+#define UMC_BASE__INST3_SEG1 0x001D4000
+#define UMC_BASE__INST3_SEG2 0x02426400
+#define UMC_BASE__INST3_SEG3 0
+#define UMC_BASE__INST3_SEG4 0
+#define UMC_BASE__INST3_SEG5 0
+
+#define UMC_BASE__INST4_SEG0 0
+#define UMC_BASE__INST4_SEG1 0
+#define UMC_BASE__INST4_SEG2 0
+#define UMC_BASE__INST4_SEG3 0
+#define UMC_BASE__INST4_SEG4 0
+#define UMC_BASE__INST4_SEG5 0
+
+#define UMC_BASE__INST5_SEG0 0
+#define UMC_BASE__INST5_SEG1 0
+#define UMC_BASE__INST5_SEG2 0
+#define UMC_BASE__INST5_SEG3 0
+#define UMC_BASE__INST5_SEG4 0
+#define UMC_BASE__INST5_SEG5 0
+
+#define UMC_BASE__INST6_SEG0 0
+#define UMC_BASE__INST6_SEG1 0
+#define UMC_BASE__INST6_SEG2 0
+#define UMC_BASE__INST6_SEG3 0
+#define UMC_BASE__INST6_SEG4 0
+#define UMC_BASE__INST6_SEG5 0
+
+#define VCN_BASE__INST0_SEG0 0x00007800
+#define VCN_BASE__INST0_SEG1 0x00007E00
+#define VCN_BASE__INST0_SEG2 0x02403000
+#define VCN_BASE__INST0_SEG3 0
+#define VCN_BASE__INST0_SEG4 0
+#define VCN_BASE__INST0_SEG5 0
+
+#define VCN_BASE__INST1_SEG0 0x00007A00
+#define VCN_BASE__INST1_SEG1 0x00009000
+#define VCN_BASE__INST1_SEG2 0x02445000
+#define VCN_BASE__INST1_SEG3 0
+#define VCN_BASE__INST1_SEG4 0
+#define VCN_BASE__INST1_SEG5 0
+
+#define VCN_BASE__INST2_SEG0 0
+#define VCN_BASE__INST2_SEG1 0
+#define VCN_BASE__INST2_SEG2 0
+#define VCN_BASE__INST2_SEG3 0
+#define VCN_BASE__INST2_SEG4 0
+#define VCN_BASE__INST2_SEG5 0
+
+#define VCN_BASE__INST3_SEG0 0
+#define VCN_BASE__INST3_SEG1 0
+#define VCN_BASE__INST3_SEG2 0
+#define VCN_BASE__INST3_SEG3 0
+#define VCN_BASE__INST3_SEG4 0
+#define VCN_BASE__INST3_SEG5 0
+
+#define VCN_BASE__INST4_SEG0 0
+#define VCN_BASE__INST4_SEG1 0
+#define VCN_BASE__INST4_SEG2 0
+#define VCN_BASE__INST4_SEG3 0
+#define VCN_BASE__INST4_SEG4 0
+#define VCN_BASE__INST4_SEG5 0
+
+#define VCN_BASE__INST5_SEG0 0
+#define VCN_BASE__INST5_SEG1 0
+#define VCN_BASE__INST5_SEG2 0
+#define VCN_BASE__INST5_SEG3 0
+#define VCN_BASE__INST5_SEG4 0
+#define VCN_BASE__INST5_SEG5 0
+
+#define VCN_BASE__INST6_SEG0 0
+#define VCN_BASE__INST6_SEG1 0
+#define VCN_BASE__INST6_SEG2 0
+#define VCN_BASE__INST6_SEG3 0
+#define VCN_BASE__INST6_SEG4 0
+#define VCN_BASE__INST6_SEG5 0
+
+#define WAFL0_BASE__INST0_SEG0 0x02438000
+#define WAFL0_BASE__INST0_SEG1 0x04880000
+#define WAFL0_BASE__INST0_SEG2 0
+#define WAFL0_BASE__INST0_SEG3 0
+#define WAFL0_BASE__INST0_SEG4 0
+#define WAFL0_BASE__INST0_SEG5 0
+
+#define WAFL0_BASE__INST1_SEG0 0
+#define WAFL0_BASE__INST1_SEG1 0
+#define WAFL0_BASE__INST1_SEG2 0
+#define WAFL0_BASE__INST1_SEG3 0
+#define WAFL0_BASE__INST1_SEG4 0
+#define WAFL0_BASE__INST1_SEG5 0
+
+#define WAFL0_BASE__INST2_SEG0 0
+#define WAFL0_BASE__INST2_SEG1 0
+#define WAFL0_BASE__INST2_SEG2 0
+#define WAFL0_BASE__INST2_SEG3 0
+#define WAFL0_BASE__INST2_SEG4 0
+#define WAFL0_BASE__INST2_SEG5 0
+
+#define WAFL0_BASE__INST3_SEG0 0
+#define WAFL0_BASE__INST3_SEG1 0
+#define WAFL0_BASE__INST3_SEG2 0
+#define WAFL0_BASE__INST3_SEG3 0
+#define WAFL0_BASE__INST3_SEG4 0
+#define WAFL0_BASE__INST3_SEG5 0
+
+#define WAFL0_BASE__INST4_SEG0 0
+#define WAFL0_BASE__INST4_SEG1 0
+#define WAFL0_BASE__INST4_SEG2 0
+#define WAFL0_BASE__INST4_SEG3 0
+#define WAFL0_BASE__INST4_SEG4 0
+#define WAFL0_BASE__INST4_SEG5 0
+
+#define WAFL0_BASE__INST5_SEG0 0
+#define WAFL0_BASE__INST5_SEG1 0
+#define WAFL0_BASE__INST5_SEG2 0
+#define WAFL0_BASE__INST5_SEG3 0
+#define WAFL0_BASE__INST5_SEG4 0
+#define WAFL0_BASE__INST5_SEG5 0
+
+#define WAFL0_BASE__INST6_SEG0 0
+#define WAFL0_BASE__INST6_SEG1 0
+#define WAFL0_BASE__INST6_SEG2 0
+#define WAFL0_BASE__INST6_SEG3 0
+#define WAFL0_BASE__INST6_SEG4 0
+#define WAFL0_BASE__INST6_SEG5 0
+
+#define WAFL1_BASE__INST0_SEG0 0
+#define WAFL1_BASE__INST0_SEG1 0x01300000
+#define WAFL1_BASE__INST0_SEG2 0x02410800
+#define WAFL1_BASE__INST0_SEG3 0
+#define WAFL1_BASE__INST0_SEG4 0
+#define WAFL1_BASE__INST0_SEG5 0
+
+#define WAFL1_BASE__INST1_SEG0 0
+#define WAFL1_BASE__INST1_SEG1 0
+#define WAFL1_BASE__INST1_SEG2 0
+#define WAFL1_BASE__INST1_SEG3 0
+#define WAFL1_BASE__INST1_SEG4 0
+#define WAFL1_BASE__INST1_SEG5 0
+
+#define WAFL1_BASE__INST2_SEG0 0
+#define WAFL1_BASE__INST2_SEG1 0
+#define WAFL1_BASE__INST2_SEG2 0
+#define WAFL1_BASE__INST2_SEG3 0
+#define WAFL1_BASE__INST2_SEG4 0
+#define WAFL1_BASE__INST2_SEG5 0
+
+#define WAFL1_BASE__INST3_SEG0 0
+#define WAFL1_BASE__INST3_SEG1 0
+#define WAFL1_BASE__INST3_SEG2 0
+#define WAFL1_BASE__INST3_SEG3 0
+#define WAFL1_BASE__INST3_SEG4 0
+#define WAFL1_BASE__INST3_SEG5 0
+
+#define WAFL1_BASE__INST4_SEG0 0
+#define WAFL1_BASE__INST4_SEG1 0
+#define WAFL1_BASE__INST4_SEG2 0
+#define WAFL1_BASE__INST4_SEG3 0
+#define WAFL1_BASE__INST4_SEG4 0
+#define WAFL1_BASE__INST4_SEG5 0
+
+#define WAFL1_BASE__INST5_SEG0 0
+#define WAFL1_BASE__INST5_SEG1 0
+#define WAFL1_BASE__INST5_SEG2 0
+#define WAFL1_BASE__INST5_SEG3 0
+#define WAFL1_BASE__INST5_SEG4 0
+#define WAFL1_BASE__INST5_SEG5 0
+
+#define WAFL1_BASE__INST6_SEG0 0
+#define WAFL1_BASE__INST6_SEG1 0
+#define WAFL1_BASE__INST6_SEG2 0
+#define WAFL1_BASE__INST6_SEG3 0
+#define WAFL1_BASE__INST6_SEG4 0
+#define WAFL1_BASE__INST6_SEG5 0
+
+#define XGMI0_BASE__INST0_SEG0 0x02438C00
+#define XGMI0_BASE__INST0_SEG1 0x04680000
+#define XGMI0_BASE__INST0_SEG2 0x04940000
+#define XGMI0_BASE__INST0_SEG3 0
+#define XGMI0_BASE__INST0_SEG4 0
+#define XGMI0_BASE__INST0_SEG5 0
+
+#define XGMI0_BASE__INST1_SEG0 0
+#define XGMI0_BASE__INST1_SEG1 0
+#define XGMI0_BASE__INST1_SEG2 0
+#define XGMI0_BASE__INST1_SEG3 0
+#define XGMI0_BASE__INST1_SEG4 0
+#define XGMI0_BASE__INST1_SEG5 0
+
+#define XGMI0_BASE__INST2_SEG0 0
+#define XGMI0_BASE__INST2_SEG1 0
+#define XGMI0_BASE__INST2_SEG2 0
+#define XGMI0_BASE__INST2_SEG3 0
+#define XGMI0_BASE__INST2_SEG4 0
+#define XGMI0_BASE__INST2_SEG5 0
+
+#define XGMI0_BASE__INST3_SEG0 0
+#define XGMI0_BASE__INST3_SEG1 0
+#define XGMI0_BASE__INST3_SEG2 0
+#define XGMI0_BASE__INST3_SEG3 0
+#define XGMI0_BASE__INST3_SEG4 0
+#define XGMI0_BASE__INST3_SEG5 0
+
+#define XGMI0_BASE__INST4_SEG0 0
+#define XGMI0_BASE__INST4_SEG1 0
+#define XGMI0_BASE__INST4_SEG2 0
+#define XGMI0_BASE__INST4_SEG3 0
+#define XGMI0_BASE__INST4_SEG4 0
+#define XGMI0_BASE__INST4_SEG5 0
+
+#define XGMI0_BASE__INST5_SEG0 0
+#define XGMI0_BASE__INST5_SEG1 0
+#define XGMI0_BASE__INST5_SEG2 0
+#define XGMI0_BASE__INST5_SEG3 0
+#define XGMI0_BASE__INST5_SEG4 0
+#define XGMI0_BASE__INST5_SEG5 0
+
+#define XGMI0_BASE__INST6_SEG0 0
+#define XGMI0_BASE__INST6_SEG1 0
+#define XGMI0_BASE__INST6_SEG2 0
+#define XGMI0_BASE__INST6_SEG3 0
+#define XGMI0_BASE__INST6_SEG4 0
+#define XGMI0_BASE__INST6_SEG5 0
+
+#define XGMI1_BASE__INST0_SEG0 0x02439000
+#define XGMI1_BASE__INST0_SEG1 0x046C0000
+#define XGMI1_BASE__INST0_SEG2 0x04980000
+#define XGMI1_BASE__INST0_SEG3 0
+#define XGMI1_BASE__INST0_SEG4 0
+#define XGMI1_BASE__INST0_SEG5 0
+
+#define XGMI1_BASE__INST1_SEG0 0
+#define XGMI1_BASE__INST1_SEG1 0
+#define XGMI1_BASE__INST1_SEG2 0
+#define XGMI1_BASE__INST1_SEG3 0
+#define XGMI1_BASE__INST1_SEG4 0
+#define XGMI1_BASE__INST1_SEG5 0
+
+#define XGMI1_BASE__INST2_SEG0 0
+#define XGMI1_BASE__INST2_SEG1 0
+#define XGMI1_BASE__INST2_SEG2 0
+#define XGMI1_BASE__INST2_SEG3 0
+#define XGMI1_BASE__INST2_SEG4 0
+#define XGMI1_BASE__INST2_SEG5 0
+
+#define XGMI1_BASE__INST3_SEG0 0
+#define XGMI1_BASE__INST3_SEG1 0
+#define XGMI1_BASE__INST3_SEG2 0
+#define XGMI1_BASE__INST3_SEG3 0
+#define XGMI1_BASE__INST3_SEG4 0
+#define XGMI1_BASE__INST3_SEG5 0
+
+#define XGMI1_BASE__INST4_SEG0 0
+#define XGMI1_BASE__INST4_SEG1 0
+#define XGMI1_BASE__INST4_SEG2 0
+#define XGMI1_BASE__INST4_SEG3 0
+#define XGMI1_BASE__INST4_SEG4 0
+#define XGMI1_BASE__INST4_SEG5 0
+
+#define XGMI1_BASE__INST5_SEG0 0
+#define XGMI1_BASE__INST5_SEG1 0
+#define XGMI1_BASE__INST5_SEG2 0
+#define XGMI1_BASE__INST5_SEG3 0
+#define XGMI1_BASE__INST5_SEG4 0
+#define XGMI1_BASE__INST5_SEG5 0
+
+#define XGMI1_BASE__INST6_SEG0 0
+#define XGMI1_BASE__INST6_SEG1 0
+#define XGMI1_BASE__INST6_SEG2 0
+#define XGMI1_BASE__INST6_SEG3 0
+#define XGMI1_BASE__INST6_SEG4 0
+#define XGMI1_BASE__INST6_SEG5 0
+
+#define XGMI2_BASE__INST0_SEG0 0x04700000
+#define XGMI2_BASE__INST0_SEG1 0x049C0000
+#define XGMI2_BASE__INST0_SEG2 0
+#define XGMI2_BASE__INST0_SEG3 0
+#define XGMI2_BASE__INST0_SEG4 0
+#define XGMI2_BASE__INST0_SEG5 0
+
+#define XGMI2_BASE__INST1_SEG0 0x04740000
+#define XGMI2_BASE__INST1_SEG1 0x04A00000
+#define XGMI2_BASE__INST1_SEG2 0
+#define XGMI2_BASE__INST1_SEG3 0
+#define XGMI2_BASE__INST1_SEG4 0
+#define XGMI2_BASE__INST1_SEG5 0
+
+#define XGMI2_BASE__INST2_SEG0 0x04780000
+#define XGMI2_BASE__INST2_SEG1 0x04A40000
+#define XGMI2_BASE__INST2_SEG2 0
+#define XGMI2_BASE__INST2_SEG3 0
+#define XGMI2_BASE__INST2_SEG4 0
+#define XGMI2_BASE__INST2_SEG5 0
+
+#define XGMI2_BASE__INST3_SEG0 0x047C0000
+#define XGMI2_BASE__INST3_SEG1 0x04A80000
+#define XGMI2_BASE__INST3_SEG2 0
+#define XGMI2_BASE__INST3_SEG3 0
+#define XGMI2_BASE__INST3_SEG4 0
+#define XGMI2_BASE__INST3_SEG5 0
+
+#define XGMI2_BASE__INST4_SEG0 0x04800000
+#define XGMI2_BASE__INST4_SEG1 0x04AC0000
+#define XGMI2_BASE__INST4_SEG2 0
+#define XGMI2_BASE__INST4_SEG3 0
+#define XGMI2_BASE__INST4_SEG4 0
+#define XGMI2_BASE__INST4_SEG5 0
+
+#define XGMI2_BASE__INST5_SEG0 0x04840000
+#define XGMI2_BASE__INST5_SEG1 0x04B00000
+#define XGMI2_BASE__INST5_SEG2 0
+#define XGMI2_BASE__INST5_SEG3 0
+#define XGMI2_BASE__INST5_SEG4 0
+#define XGMI2_BASE__INST5_SEG5 0
+
+#define XGMI2_BASE__INST6_SEG0 0
+#define XGMI2_BASE__INST6_SEG1 0
+#define XGMI2_BASE__INST6_SEG2 0
+#define XGMI2_BASE__INST6_SEG3 0
+#define XGMI2_BASE__INST6_SEG4 0
+#define XGMI2_BASE__INST6_SEG5 0
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h
index cf166b591bc5..483769fb1736 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h
@@ -8922,7 +8922,7 @@
#define mmOTG1_OTG_CONTROL 0x1bc1
#define mmOTG1_OTG_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_BLANK_CONTROL 0x1bc2
-#define mmOTG1_OTG_BLANK_CONTROL_BASE_IDX
+#define mmOTG1_OTG_BLANK_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_INTERLACE_CONTROL 0x1bc4
#define mmOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_INTERLACE_STATUS 0x1bc5
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
index 0102487a2c5f..f21554a1c86c 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
@@ -6955,6 +6955,12 @@
#define mmCP_CE_IB2_BASE_HI_BASE_IDX 1
#define mmCP_CE_IB2_BUFSZ 0x20cb
#define mmCP_CE_IB2_BUFSZ_BASE_IDX 1
+#define mmCP_IB1_BASE_LO 0x20cc
+#define mmCP_IB1_BASE_LO_BASE_IDX 1
+#define mmCP_IB1_BASE_HI 0x20cd
+#define mmCP_IB1_BASE_HI_BASE_IDX 1
+#define mmCP_IB1_BUFSZ 0x20ce
+#define mmCP_IB1_BUFSZ_BASE_IDX 1
#define mmCP_IB2_BASE_LO 0x20cf
#define mmCP_IB2_BASE_LO_BASE_IDX 1
#define mmCP_IB2_BASE_HI 0x20d0
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h
index 4d2a1432c121..a827b0ff8905 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h
@@ -25818,6 +25818,15 @@
//CP_CE_IB2_BUFSZ
#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL
+//CP_IB1_BASE_LO
+#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
+#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL
+//CP_IB1_BASE_HI
+#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
+#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL
+//CP_IB1_BUFSZ
+#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
+#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL
//CP_IB2_BASE_LO
#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_1_sh_mask.h
index 4089cfa081f5..849450caca15 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_1_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_1_sh_mask.h
@@ -617,6 +617,22 @@
#define GCEA_EDC_CNT3__MAM_A3MEM_SEC_COUNT_MASK 0x30000000L
#define GCEA_EDC_CNT3__MAM_A3MEM_DED_COUNT_MASK 0xC0000000L
+//GCEA_ERR_STATUS
+#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0
+#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4
+#define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8
+#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa
+#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb
+#define GCEA_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc
+#define GCEA_ERR_STATUS__FUE_FLAG__SHIFT 0xd
+#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL
+#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L
+#define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L
+#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L
+#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L
+#define GCEA_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L
+#define GCEA_ERR_STATUS__FUE_FLAG_MASK 0x00002000L
+
// addressBlock: gc_gfxudec
//GRBM_GFX_INDEX
#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_offset.h
new file mode 100644
index 000000000000..a9ad00e017a5
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_offset.h
@@ -0,0 +1,7683 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef _gc_9_4_2_OFFSET_HEADER
+#define _gc_9_4_2_OFFSET_HEADER
+
+
+
+// addressBlock: didtind
+// base address: 0x0
+#define ixDIDT_SQ_CTRL0 0x0000
+#define ixDIDT_SQ_CTRL2 0x0002
+#define ixDIDT_SQ_STALL_CTRL 0x0004
+#define ixDIDT_SQ_TUNING_CTRL 0x0005
+#define ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL 0x0006
+#define ixDIDT_SQ_CTRL3 0x0007
+#define ixDIDT_SQ_STALL_PATTERN_1_2 0x0008
+#define ixDIDT_SQ_STALL_PATTERN_3_4 0x0009
+#define ixDIDT_SQ_STALL_PATTERN_5_6 0x000a
+#define ixDIDT_SQ_STALL_PATTERN_7 0x000b
+#define ixDIDT_SQ_MPD_SCALE_FACTOR 0x000c
+#define ixDIDT_SQ_THROTTLE_CNTL0 0x000d
+#define ixDIDT_SQ_THROTTLE_CNTL1 0x000e
+#define ixDIDT_SQ_THROTTLE_CNTL_STATUS 0x000f
+#define ixDIDT_SQ_WEIGHT0_3 0x0010
+#define ixDIDT_SQ_WEIGHT4_7 0x0011
+#define ixDIDT_SQ_WEIGHT8_11 0x0012
+#define ixDIDT_SQ_EDC_CTRL 0x0013
+#define ixDIDT_SQ_THROTTLE_CTRL 0x0014
+#define ixDIDT_SQ_EDC_STALL_PATTERN_1_2 0x0015
+#define ixDIDT_SQ_EDC_STALL_PATTERN_3_4 0x0016
+#define ixDIDT_SQ_EDC_STALL_PATTERN_5_6 0x0017
+#define ixDIDT_SQ_EDC_STALL_PATTERN_7 0x0018
+#define ixDIDT_SQ_EDC_STATUS 0x0019
+#define ixDIDT_SQ_EDC_STALL_DELAY_1 0x001a
+#define ixDIDT_SQ_EDC_STALL_DELAY_2 0x001b
+#define ixDIDT_SQ_EDC_STALL_DELAY_3 0x001c
+#define ixDIDT_SQ_EDC_STALL_DELAY_4 0x001d
+#define ixDIDT_SQ_EDC_OVERFLOW 0x001e
+#define ixDIDT_SQ_EDC_ROLLING_POWER_DELTA 0x001f
+#define ixDIDT_DB_CTRL0 0x0020
+#define ixDIDT_DB_CTRL2 0x0022
+#define ixDIDT_DB_STALL_CTRL 0x0024
+#define ixDIDT_DB_TUNING_CTRL 0x0025
+#define ixDIDT_DB_STALL_AUTO_RELEASE_CTRL 0x0026
+#define ixDIDT_DB_CTRL3 0x0027
+#define ixDIDT_DB_STALL_PATTERN_1_2 0x0028
+#define ixDIDT_DB_STALL_PATTERN_3_4 0x0029
+#define ixDIDT_DB_STALL_PATTERN_5_6 0x002a
+#define ixDIDT_DB_STALL_PATTERN_7 0x002b
+#define ixDIDT_DB_MPD_SCALE_FACTOR 0x002c
+#define ixDIDT_DB_THROTTLE_CNTL0 0x002d
+#define ixDIDT_DB_THROTTLE_CNTL1 0x002e
+#define ixDIDT_DB_THROTTLE_CNTL_STATUS 0x002f
+#define ixDIDT_DB_WEIGHT0_3 0x0030
+#define ixDIDT_DB_WEIGHT4_7 0x0031
+#define ixDIDT_DB_WEIGHT8_11 0x0032
+#define ixDIDT_DB_EDC_CTRL 0x0033
+#define ixDIDT_DB_THROTTLE_CTRL 0x0034
+#define ixDIDT_DB_EDC_STALL_PATTERN_1_2 0x0035
+#define ixDIDT_DB_EDC_STALL_PATTERN_3_4 0x0036
+#define ixDIDT_DB_EDC_STALL_PATTERN_5_6 0x0037
+#define ixDIDT_DB_EDC_STALL_PATTERN_7 0x0038
+#define ixDIDT_DB_EDC_STATUS 0x0039
+#define ixDIDT_DB_EDC_STALL_DELAY_1 0x003a
+#define ixDIDT_DB_EDC_OVERFLOW 0x003e
+#define ixDIDT_DB_EDC_ROLLING_POWER_DELTA 0x003f
+#define ixDIDT_TD_CTRL0 0x0040
+#define ixDIDT_TD_CTRL2 0x0042
+#define ixDIDT_TD_STALL_CTRL 0x0044
+#define ixDIDT_TD_TUNING_CTRL 0x0045
+#define ixDIDT_TD_STALL_AUTO_RELEASE_CTRL 0x0046
+#define ixDIDT_TD_CTRL3 0x0047
+#define ixDIDT_TD_STALL_PATTERN_1_2 0x0048
+#define ixDIDT_TD_STALL_PATTERN_3_4 0x0049
+#define ixDIDT_TD_STALL_PATTERN_5_6 0x004a
+#define ixDIDT_TD_STALL_PATTERN_7 0x004b
+#define ixDIDT_TD_MPD_SCALE_FACTOR 0x004c
+#define ixDIDT_TD_THROTTLE_CNTL0 0x004d
+#define ixDIDT_TD_THROTTLE_CNTL1 0x004e
+#define ixDIDT_TD_THROTTLE_CNTL_STATUS 0x004f
+#define ixDIDT_TD_WEIGHT0_3 0x0050
+#define ixDIDT_TD_WEIGHT4_7 0x0051
+#define ixDIDT_TD_WEIGHT8_11 0x0052
+#define ixDIDT_TD_EDC_CTRL 0x0053
+#define ixDIDT_TD_THROTTLE_CTRL 0x0054
+#define ixDIDT_TD_EDC_STALL_PATTERN_1_2 0x0055
+#define ixDIDT_TD_EDC_STALL_PATTERN_3_4 0x0056
+#define ixDIDT_TD_EDC_STALL_PATTERN_5_6 0x0057
+#define ixDIDT_TD_EDC_STALL_PATTERN_7 0x0058
+#define ixDIDT_TD_EDC_STATUS 0x0059
+#define ixDIDT_TD_EDC_STALL_DELAY_1 0x005a
+#define ixDIDT_TD_EDC_STALL_DELAY_2 0x005b
+#define ixDIDT_TD_EDC_STALL_DELAY_3 0x005c
+#define ixDIDT_TD_EDC_STALL_DELAY_4 0x005d
+#define ixDIDT_TD_EDC_OVERFLOW 0x005e
+#define ixDIDT_TD_EDC_ROLLING_POWER_DELTA 0x005f
+#define ixDIDT_TCP_CTRL0 0x0060
+#define ixDIDT_TCP_CTRL2 0x0062
+#define ixDIDT_TCP_STALL_CTRL 0x0064
+#define ixDIDT_TCP_TUNING_CTRL 0x0065
+#define ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL 0x0066
+#define ixDIDT_TCP_CTRL3 0x0067
+#define ixDIDT_TCP_STALL_PATTERN_1_2 0x0068
+#define ixDIDT_TCP_STALL_PATTERN_3_4 0x0069
+#define ixDIDT_TCP_STALL_PATTERN_5_6 0x006a
+#define ixDIDT_TCP_STALL_PATTERN_7 0x006b
+#define ixDIDT_TCP_MPD_SCALE_FACTOR 0x006c
+#define ixDIDT_TCP_THROTTLE_CNTL0 0x006d
+#define ixDIDT_TCP_THROTTLE_CNTL1 0x006e
+#define ixDIDT_TCP_THROTTLE_CNTL_STATUS 0x006f
+#define ixDIDT_TCP_WEIGHT0_3 0x0070
+#define ixDIDT_TCP_WEIGHT4_7 0x0071
+#define ixDIDT_TCP_WEIGHT8_11 0x0072
+#define ixDIDT_TCP_EDC_CTRL 0x0073
+#define ixDIDT_TCP_THROTTLE_CTRL 0x0074
+#define ixDIDT_TCP_EDC_STALL_PATTERN_1_2 0x0075
+#define ixDIDT_TCP_EDC_STALL_PATTERN_3_4 0x0076
+#define ixDIDT_TCP_EDC_STALL_PATTERN_5_6 0x0077
+#define ixDIDT_TCP_EDC_STALL_PATTERN_7 0x0078
+#define ixDIDT_TCP_EDC_STATUS 0x0079
+#define ixDIDT_TCP_EDC_STALL_DELAY_1 0x007a
+#define ixDIDT_TCP_EDC_STALL_DELAY_2 0x007b
+#define ixDIDT_TCP_EDC_STALL_DELAY_3 0x007c
+#define ixDIDT_TCP_EDC_STALL_DELAY_4 0x007d
+#define ixDIDT_TCP_EDC_OVERFLOW 0x007e
+#define ixDIDT_TCP_EDC_ROLLING_POWER_DELTA 0x007f
+#define ixDIDT_SQ_STALL_EVENT_COUNTER 0x00a0
+#define ixDIDT_DB_STALL_EVENT_COUNTER 0x00a1
+#define ixDIDT_TD_STALL_EVENT_COUNTER 0x00a2
+#define ixDIDT_TCP_STALL_EVENT_COUNTER 0x00a3
+#define ixDIDT_DBR_STALL_EVENT_COUNTER 0x00a4
+#define ixDIDT_SQ_EDC_PCC_PERF_COUNTER 0x00a5
+#define ixDIDT_TD_EDC_PCC_PERF_COUNTER 0x00a6
+#define ixDIDT_TCP_EDC_PCC_PERF_COUNTER 0x00a7
+#define ixDIDT_DB_EDC_PCC_PERF_COUNTER 0x00a8
+#define ixDIDT_DBR_EDC_PCC_PERF_COUNTER 0x00a9
+#define ixDIDT_SQ_CTRL1 0x00b0
+#define ixDIDT_SQ_EDC_THRESHOLD 0x00b1
+#define ixDIDT_DB_CTRL1 0x00b2
+#define ixDIDT_DB_EDC_THRESHOLD 0x00b3
+#define ixDIDT_TD_CTRL1 0x00b4
+#define ixDIDT_TD_EDC_THRESHOLD 0x00b5
+#define ixDIDT_TCP_CTRL1 0x00b6
+#define ixDIDT_TCP_EDC_THRESHOLD 0x00b7
+
+
+// addressBlock: gc_cpdec
+// base address: 0x8200
+#define regCP_CPC_STATUS 0x0084
+#define regCP_CPC_STATUS_BASE_IDX 0
+#define regCP_CPC_BUSY_STAT 0x0085
+#define regCP_CPC_BUSY_STAT_BASE_IDX 0
+#define regCP_CPC_STALLED_STAT1 0x0086
+#define regCP_CPC_STALLED_STAT1_BASE_IDX 0
+#define regCP_CPF_STATUS 0x0087
+#define regCP_CPF_STATUS_BASE_IDX 0
+#define regCP_CPF_BUSY_STAT 0x0088
+#define regCP_CPF_BUSY_STAT_BASE_IDX 0
+#define regCP_CPF_STALLED_STAT1 0x0089
+#define regCP_CPF_STALLED_STAT1_BASE_IDX 0
+#define regCP_CPC_GRBM_FREE_COUNT 0x008b
+#define regCP_CPC_GRBM_FREE_COUNT_BASE_IDX 0
+#define regCP_CPC_PRIV_VIOLATION_ADDR 0x008c
+#define regCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX 0
+#define regCP_MEC_CNTL 0x008d
+#define regCP_MEC_CNTL_BASE_IDX 0
+#define regCP_MEC_ME1_HEADER_DUMP 0x008e
+#define regCP_MEC_ME1_HEADER_DUMP_BASE_IDX 0
+#define regCP_MEC_ME2_HEADER_DUMP 0x008f
+#define regCP_MEC_ME2_HEADER_DUMP_BASE_IDX 0
+#define regCP_CPC_SCRATCH_INDEX 0x0090
+#define regCP_CPC_SCRATCH_INDEX_BASE_IDX 0
+#define regCP_CPC_SCRATCH_DATA 0x0091
+#define regCP_CPC_SCRATCH_DATA_BASE_IDX 0
+#define regCP_CPF_GRBM_FREE_COUNT 0x0092
+#define regCP_CPF_GRBM_FREE_COUNT_BASE_IDX 0
+#define regCP_CPC_HALT_HYST_COUNT 0x00a7
+#define regCP_CPC_HALT_HYST_COUNT_BASE_IDX 0
+#define regCP_CE_COMPARE_COUNT 0x00c0
+#define regCP_CE_COMPARE_COUNT_BASE_IDX 0
+#define regCP_CE_DE_COUNT 0x00c1
+#define regCP_CE_DE_COUNT_BASE_IDX 0
+#define regCP_DE_CE_COUNT 0x00c2
+#define regCP_DE_CE_COUNT_BASE_IDX 0
+#define regCP_DE_LAST_INVAL_COUNT 0x00c3
+#define regCP_DE_LAST_INVAL_COUNT_BASE_IDX 0
+#define regCP_DE_DE_COUNT 0x00c4
+#define regCP_DE_DE_COUNT_BASE_IDX 0
+#define regCP_STALLED_STAT3 0x019c
+#define regCP_STALLED_STAT3_BASE_IDX 0
+#define regCP_STALLED_STAT1 0x019d
+#define regCP_STALLED_STAT1_BASE_IDX 0
+#define regCP_STALLED_STAT2 0x019e
+#define regCP_STALLED_STAT2_BASE_IDX 0
+#define regCP_BUSY_STAT 0x019f
+#define regCP_BUSY_STAT_BASE_IDX 0
+#define regCP_STAT 0x01a0
+#define regCP_STAT_BASE_IDX 0
+#define regCP_ME_HEADER_DUMP 0x01a1
+#define regCP_ME_HEADER_DUMP_BASE_IDX 0
+#define regCP_PFP_HEADER_DUMP 0x01a2
+#define regCP_PFP_HEADER_DUMP_BASE_IDX 0
+#define regCP_GRBM_FREE_COUNT 0x01a3
+#define regCP_GRBM_FREE_COUNT_BASE_IDX 0
+#define regCP_CE_HEADER_DUMP 0x01a4
+#define regCP_CE_HEADER_DUMP_BASE_IDX 0
+#define regCP_PFP_INSTR_PNTR 0x01a5
+#define regCP_PFP_INSTR_PNTR_BASE_IDX 0
+#define regCP_ME_INSTR_PNTR 0x01a6
+#define regCP_ME_INSTR_PNTR_BASE_IDX 0
+#define regCP_CE_INSTR_PNTR 0x01a7
+#define regCP_CE_INSTR_PNTR_BASE_IDX 0
+#define regCP_MEC1_INSTR_PNTR 0x01a8
+#define regCP_MEC1_INSTR_PNTR_BASE_IDX 0
+#define regCP_MEC2_INSTR_PNTR 0x01a9
+#define regCP_MEC2_INSTR_PNTR_BASE_IDX 0
+#define regCP_CSF_STAT 0x01b4
+#define regCP_CSF_STAT_BASE_IDX 0
+#define regCP_ME_CNTL 0x01b6
+#define regCP_ME_CNTL_BASE_IDX 0
+#define regCP_CNTX_STAT 0x01b8
+#define regCP_CNTX_STAT_BASE_IDX 0
+#define regCP_ME_PREEMPTION 0x01b9
+#define regCP_ME_PREEMPTION_BASE_IDX 0
+#define regCP_ROQ_THRESHOLDS 0x01bc
+#define regCP_ROQ_THRESHOLDS_BASE_IDX 0
+#define regCP_MEQ_STQ_THRESHOLD 0x01bd
+#define regCP_MEQ_STQ_THRESHOLD_BASE_IDX 0
+#define regCP_RB2_RPTR 0x01be
+#define regCP_RB2_RPTR_BASE_IDX 0
+#define regCP_RB1_RPTR 0x01bf
+#define regCP_RB1_RPTR_BASE_IDX 0
+#define regCP_RB0_RPTR 0x01c0
+#define regCP_RB0_RPTR_BASE_IDX 0
+#define regCP_RB_RPTR 0x01c0
+#define regCP_RB_RPTR_BASE_IDX 0
+#define regCP_RB_WPTR_DELAY 0x01c1
+#define regCP_RB_WPTR_DELAY_BASE_IDX 0
+#define regCP_RB_WPTR_POLL_CNTL 0x01c2
+#define regCP_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regCP_ROQ1_THRESHOLDS 0x01d5
+#define regCP_ROQ1_THRESHOLDS_BASE_IDX 0
+#define regCP_ROQ2_THRESHOLDS 0x01d6
+#define regCP_ROQ2_THRESHOLDS_BASE_IDX 0
+#define regCP_STQ_THRESHOLDS 0x01d7
+#define regCP_STQ_THRESHOLDS_BASE_IDX 0
+#define regCP_QUEUE_THRESHOLDS 0x01d8
+#define regCP_QUEUE_THRESHOLDS_BASE_IDX 0
+#define regCP_MEQ_THRESHOLDS 0x01d9
+#define regCP_MEQ_THRESHOLDS_BASE_IDX 0
+#define regCP_ROQ_AVAIL 0x01da
+#define regCP_ROQ_AVAIL_BASE_IDX 0
+#define regCP_STQ_AVAIL 0x01db
+#define regCP_STQ_AVAIL_BASE_IDX 0
+#define regCP_ROQ2_AVAIL 0x01dc
+#define regCP_ROQ2_AVAIL_BASE_IDX 0
+#define regCP_MEQ_AVAIL 0x01dd
+#define regCP_MEQ_AVAIL_BASE_IDX 0
+#define regCP_CMD_INDEX 0x01de
+#define regCP_CMD_INDEX_BASE_IDX 0
+#define regCP_CMD_DATA 0x01df
+#define regCP_CMD_DATA_BASE_IDX 0
+#define regCP_ROQ_RB_STAT 0x01e0
+#define regCP_ROQ_RB_STAT_BASE_IDX 0
+#define regCP_ROQ_IB1_STAT 0x01e1
+#define regCP_ROQ_IB1_STAT_BASE_IDX 0
+#define regCP_ROQ_IB2_STAT 0x01e2
+#define regCP_ROQ_IB2_STAT_BASE_IDX 0
+#define regCP_STQ_STAT 0x01e3
+#define regCP_STQ_STAT_BASE_IDX 0
+#define regCP_STQ_WR_STAT 0x01e4
+#define regCP_STQ_WR_STAT_BASE_IDX 0
+#define regCP_MEQ_STAT 0x01e5
+#define regCP_MEQ_STAT_BASE_IDX 0
+#define regCP_CEQ1_AVAIL 0x01e6
+#define regCP_CEQ1_AVAIL_BASE_IDX 0
+#define regCP_CEQ2_AVAIL 0x01e7
+#define regCP_CEQ2_AVAIL_BASE_IDX 0
+#define regCP_CE_ROQ_RB_STAT 0x01e8
+#define regCP_CE_ROQ_RB_STAT_BASE_IDX 0
+#define regCP_CE_ROQ_IB1_STAT 0x01e9
+#define regCP_CE_ROQ_IB1_STAT_BASE_IDX 0
+#define regCP_CE_ROQ_IB2_STAT 0x01ea
+#define regCP_CE_ROQ_IB2_STAT_BASE_IDX 0
+#define regCP_PRIV_VIOLATION_ADDR 0x01fa
+#define regCP_PRIV_VIOLATION_ADDR_BASE_IDX 0
+
+
+// addressBlock: gc_cppdec
+// base address: 0xc080
+#define regCP_EOPQ_WAIT_TIME 0x1035
+#define regCP_EOPQ_WAIT_TIME_BASE_IDX 0
+#define regCP_CPC_MGCG_SYNC_CNTL 0x1036
+#define regCP_CPC_MGCG_SYNC_CNTL_BASE_IDX 0
+#define regCPC_INT_INFO 0x1037
+#define regCPC_INT_INFO_BASE_IDX 0
+#define regCP_VIRT_STATUS 0x1038
+#define regCP_VIRT_STATUS_BASE_IDX 0
+#define regCPC_INT_ADDR 0x1039
+#define regCPC_INT_ADDR_BASE_IDX 0
+#define regCPC_INT_PASID 0x103a
+#define regCPC_INT_PASID_BASE_IDX 0
+#define regCP_GFX_ERROR 0x103b
+#define regCP_GFX_ERROR_BASE_IDX 0
+#define regCPG_UTCL1_CNTL 0x103c
+#define regCPG_UTCL1_CNTL_BASE_IDX 0
+#define regCPC_UTCL1_CNTL 0x103d
+#define regCPC_UTCL1_CNTL_BASE_IDX 0
+#define regCPF_UTCL1_CNTL 0x103e
+#define regCPF_UTCL1_CNTL_BASE_IDX 0
+#define regCP_AQL_SMM_STATUS 0x103f
+#define regCP_AQL_SMM_STATUS_BASE_IDX 0
+#define regCP_RB0_BASE 0x1040
+#define regCP_RB0_BASE_BASE_IDX 0
+#define regCP_RB_BASE 0x1040
+#define regCP_RB_BASE_BASE_IDX 0
+#define regCP_RB0_CNTL 0x1041
+#define regCP_RB0_CNTL_BASE_IDX 0
+#define regCP_RB_CNTL 0x1041
+#define regCP_RB_CNTL_BASE_IDX 0
+#define regCP_RB_RPTR_WR 0x1042
+#define regCP_RB_RPTR_WR_BASE_IDX 0
+#define regCP_RB0_RPTR_ADDR 0x1043
+#define regCP_RB0_RPTR_ADDR_BASE_IDX 0
+#define regCP_RB_RPTR_ADDR 0x1043
+#define regCP_RB_RPTR_ADDR_BASE_IDX 0
+#define regCP_RB0_RPTR_ADDR_HI 0x1044
+#define regCP_RB0_RPTR_ADDR_HI_BASE_IDX 0
+#define regCP_RB_RPTR_ADDR_HI 0x1044
+#define regCP_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regCP_RB0_BUFSZ_MASK 0x1045
+#define regCP_RB0_BUFSZ_MASK_BASE_IDX 0
+#define regCP_RB_BUFSZ_MASK 0x1045
+#define regCP_RB_BUFSZ_MASK_BASE_IDX 0
+#define regCP_RB_WPTR_POLL_ADDR_LO 0x1046
+#define regCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regCP_RB_WPTR_POLL_ADDR_HI 0x1047
+#define regCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regCP_INT_CNTL 0x1049
+#define regCP_INT_CNTL_BASE_IDX 0
+#define regCP_INT_STATUS 0x104a
+#define regCP_INT_STATUS_BASE_IDX 0
+#define regCP_DEVICE_ID 0x104b
+#define regCP_DEVICE_ID_BASE_IDX 0
+#define regCP_ME0_PIPE_PRIORITY_CNTS 0x104c
+#define regCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX 0
+#define regCP_RING_PRIORITY_CNTS 0x104c
+#define regCP_RING_PRIORITY_CNTS_BASE_IDX 0
+#define regCP_ME0_PIPE0_PRIORITY 0x104d
+#define regCP_ME0_PIPE0_PRIORITY_BASE_IDX 0
+#define regCP_RING0_PRIORITY 0x104d
+#define regCP_RING0_PRIORITY_BASE_IDX 0
+#define regCP_ME0_PIPE1_PRIORITY 0x104e
+#define regCP_ME0_PIPE1_PRIORITY_BASE_IDX 0
+#define regCP_RING1_PRIORITY 0x104e
+#define regCP_RING1_PRIORITY_BASE_IDX 0
+#define regCP_ME0_PIPE2_PRIORITY 0x104f
+#define regCP_ME0_PIPE2_PRIORITY_BASE_IDX 0
+#define regCP_RING2_PRIORITY 0x104f
+#define regCP_RING2_PRIORITY_BASE_IDX 0
+#define regCP_FATAL_ERROR 0x1050
+#define regCP_FATAL_ERROR_BASE_IDX 0
+#define regCP_RB_VMID 0x1051
+#define regCP_RB_VMID_BASE_IDX 0
+#define regCP_ME0_PIPE0_VMID 0x1052
+#define regCP_ME0_PIPE0_VMID_BASE_IDX 0
+#define regCP_ME0_PIPE1_VMID 0x1053
+#define regCP_ME0_PIPE1_VMID_BASE_IDX 0
+#define regCP_RB0_WPTR 0x1054
+#define regCP_RB0_WPTR_BASE_IDX 0
+#define regCP_RB_WPTR 0x1054
+#define regCP_RB_WPTR_BASE_IDX 0
+#define regCP_RB0_WPTR_HI 0x1055
+#define regCP_RB0_WPTR_HI_BASE_IDX 0
+#define regCP_RB_WPTR_HI 0x1055
+#define regCP_RB_WPTR_HI_BASE_IDX 0
+#define regCP_RB1_WPTR 0x1056
+#define regCP_RB1_WPTR_BASE_IDX 0
+#define regCP_RB1_WPTR_HI 0x1057
+#define regCP_RB1_WPTR_HI_BASE_IDX 0
+#define regCP_RB2_WPTR 0x1058
+#define regCP_RB2_WPTR_BASE_IDX 0
+#define regCP_RB_DOORBELL_CONTROL 0x1059
+#define regCP_RB_DOORBELL_CONTROL_BASE_IDX 0
+#define regCP_RB_DOORBELL_RANGE_LOWER 0x105a
+#define regCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX 0
+#define regCP_RB_DOORBELL_RANGE_UPPER 0x105b
+#define regCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX 0
+#define regCP_MEC_DOORBELL_RANGE_LOWER 0x105c
+#define regCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX 0
+#define regCP_MEC_DOORBELL_RANGE_UPPER 0x105d
+#define regCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX 0
+#define regCPG_UTCL1_ERROR 0x105e
+#define regCPG_UTCL1_ERROR_BASE_IDX 0
+#define regCPC_UTCL1_ERROR 0x105f
+#define regCPC_UTCL1_ERROR_BASE_IDX 0
+#define regCP_RB1_BASE 0x1060
+#define regCP_RB1_BASE_BASE_IDX 0
+#define regCP_RB1_CNTL 0x1061
+#define regCP_RB1_CNTL_BASE_IDX 0
+#define regCP_RB1_RPTR_ADDR 0x1062
+#define regCP_RB1_RPTR_ADDR_BASE_IDX 0
+#define regCP_RB1_RPTR_ADDR_HI 0x1063
+#define regCP_RB1_RPTR_ADDR_HI_BASE_IDX 0
+#define regCP_RB2_BASE 0x1065
+#define regCP_RB2_BASE_BASE_IDX 0
+#define regCP_RB2_CNTL 0x1066
+#define regCP_RB2_CNTL_BASE_IDX 0
+#define regCP_RB2_RPTR_ADDR 0x1067
+#define regCP_RB2_RPTR_ADDR_BASE_IDX 0
+#define regCP_RB2_RPTR_ADDR_HI 0x1068
+#define regCP_RB2_RPTR_ADDR_HI_BASE_IDX 0
+#define regCP_RB0_ACTIVE 0x1069
+#define regCP_RB0_ACTIVE_BASE_IDX 0
+#define regCP_RB_ACTIVE 0x1069
+#define regCP_RB_ACTIVE_BASE_IDX 0
+#define regCP_INT_CNTL_RING0 0x106a
+#define regCP_INT_CNTL_RING0_BASE_IDX 0
+#define regCP_INT_CNTL_RING1 0x106b
+#define regCP_INT_CNTL_RING1_BASE_IDX 0
+#define regCP_INT_CNTL_RING2 0x106c
+#define regCP_INT_CNTL_RING2_BASE_IDX 0
+#define regCP_INT_STATUS_RING0 0x106d
+#define regCP_INT_STATUS_RING0_BASE_IDX 0
+#define regCP_INT_STATUS_RING1 0x106e
+#define regCP_INT_STATUS_RING1_BASE_IDX 0
+#define regCP_INT_STATUS_RING2 0x106f
+#define regCP_INT_STATUS_RING2_BASE_IDX 0
+#define regCP_ME_F32_INTERRUPT 0x1073
+#define regCP_ME_F32_INTERRUPT_BASE_IDX 0
+#define regCP_PFP_F32_INTERRUPT 0x1074
+#define regCP_PFP_F32_INTERRUPT_BASE_IDX 0
+#define regCP_CE_F32_INTERRUPT 0x1075
+#define regCP_CE_F32_INTERRUPT_BASE_IDX 0
+#define regCP_MEC1_F32_INTERRUPT 0x1076
+#define regCP_MEC1_F32_INTERRUPT_BASE_IDX 0
+#define regCP_MEC2_F32_INTERRUPT 0x1077
+#define regCP_MEC2_F32_INTERRUPT_BASE_IDX 0
+#define regCP_PWR_CNTL 0x1078
+#define regCP_PWR_CNTL_BASE_IDX 0
+#define regCP_MEM_SLP_CNTL 0x1079
+#define regCP_MEM_SLP_CNTL_BASE_IDX 0
+#define regCP_ECC_DMA_FIRST_OCCURRENCE 0x107a
+#define regCP_ECC_DMA_FIRST_OCCURRENCE_BASE_IDX 0
+#define regCP_ECC_FIRSTOCCURRENCE 0x107a
+#define regCP_ECC_FIRSTOCCURRENCE_BASE_IDX 0
+#define regCP_ECC_FIRSTOCCURRENCE_RING0 0x107b
+#define regCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX 0
+#define regCP_ECC_FIRSTOCCURRENCE_RING1 0x107c
+#define regCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX 0
+#define regCP_ECC_FIRSTOCCURRENCE_RING2 0x107d
+#define regCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX 0
+#define regGB_EDC_MODE 0x107e
+#define regGB_EDC_MODE_BASE_IDX 0
+#define regCP_PQ_WPTR_POLL_CNTL 0x1083
+#define regCP_PQ_WPTR_POLL_CNTL_BASE_IDX 0
+#define regCP_PQ_WPTR_POLL_CNTL1 0x1084
+#define regCP_PQ_WPTR_POLL_CNTL1_BASE_IDX 0
+#define regCP_ME1_PIPE0_INT_CNTL 0x1085
+#define regCP_ME1_PIPE0_INT_CNTL_BASE_IDX 0
+#define regCP_ME1_PIPE1_INT_CNTL 0x1086
+#define regCP_ME1_PIPE1_INT_CNTL_BASE_IDX 0
+#define regCP_ME1_PIPE2_INT_CNTL 0x1087
+#define regCP_ME1_PIPE2_INT_CNTL_BASE_IDX 0
+#define regCP_ME1_PIPE3_INT_CNTL 0x1088
+#define regCP_ME1_PIPE3_INT_CNTL_BASE_IDX 0
+#define regCP_ME2_PIPE0_INT_CNTL 0x1089
+#define regCP_ME2_PIPE0_INT_CNTL_BASE_IDX 0
+#define regCP_ME2_PIPE1_INT_CNTL 0x108a
+#define regCP_ME2_PIPE1_INT_CNTL_BASE_IDX 0
+#define regCP_ME2_PIPE2_INT_CNTL 0x108b
+#define regCP_ME2_PIPE2_INT_CNTL_BASE_IDX 0
+#define regCP_ME2_PIPE3_INT_CNTL 0x108c
+#define regCP_ME2_PIPE3_INT_CNTL_BASE_IDX 0
+#define regCP_ME1_PIPE0_INT_STATUS 0x108d
+#define regCP_ME1_PIPE0_INT_STATUS_BASE_IDX 0
+#define regCP_ME1_PIPE1_INT_STATUS 0x108e
+#define regCP_ME1_PIPE1_INT_STATUS_BASE_IDX 0
+#define regCP_ME1_PIPE2_INT_STATUS 0x108f
+#define regCP_ME1_PIPE2_INT_STATUS_BASE_IDX 0
+#define regCP_ME1_PIPE3_INT_STATUS 0x1090
+#define regCP_ME1_PIPE3_INT_STATUS_BASE_IDX 0
+#define regCP_ME2_PIPE0_INT_STATUS 0x1091
+#define regCP_ME2_PIPE0_INT_STATUS_BASE_IDX 0
+#define regCP_ME2_PIPE1_INT_STATUS 0x1092
+#define regCP_ME2_PIPE1_INT_STATUS_BASE_IDX 0
+#define regCP_ME2_PIPE2_INT_STATUS 0x1093
+#define regCP_ME2_PIPE2_INT_STATUS_BASE_IDX 0
+#define regCP_ME2_PIPE3_INT_STATUS 0x1094
+#define regCP_ME2_PIPE3_INT_STATUS_BASE_IDX 0
+#define regCC_GC_EDC_CONFIG 0x1098
+#define regCC_GC_EDC_CONFIG_BASE_IDX 0
+#define regCP_ME1_PIPE_PRIORITY_CNTS 0x1099
+#define regCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX 0
+#define regCP_ME1_PIPE0_PRIORITY 0x109a
+#define regCP_ME1_PIPE0_PRIORITY_BASE_IDX 0
+#define regCP_ME1_PIPE1_PRIORITY 0x109b
+#define regCP_ME1_PIPE1_PRIORITY_BASE_IDX 0
+#define regCP_ME1_PIPE2_PRIORITY 0x109c
+#define regCP_ME1_PIPE2_PRIORITY_BASE_IDX 0
+#define regCP_ME1_PIPE3_PRIORITY 0x109d
+#define regCP_ME1_PIPE3_PRIORITY_BASE_IDX 0
+#define regCP_ME2_PIPE_PRIORITY_CNTS 0x109e
+#define regCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX 0
+#define regCP_ME2_PIPE0_PRIORITY 0x109f
+#define regCP_ME2_PIPE0_PRIORITY_BASE_IDX 0
+#define regCP_ME2_PIPE1_PRIORITY 0x10a0
+#define regCP_ME2_PIPE1_PRIORITY_BASE_IDX 0
+#define regCP_ME2_PIPE2_PRIORITY 0x10a1
+#define regCP_ME2_PIPE2_PRIORITY_BASE_IDX 0
+#define regCP_ME2_PIPE3_PRIORITY 0x10a2
+#define regCP_ME2_PIPE3_PRIORITY_BASE_IDX 0
+#define regCP_CE_PRGRM_CNTR_START 0x10a3
+#define regCP_CE_PRGRM_CNTR_START_BASE_IDX 0
+#define regCP_PFP_PRGRM_CNTR_START 0x10a4
+#define regCP_PFP_PRGRM_CNTR_START_BASE_IDX 0
+#define regCP_ME_PRGRM_CNTR_START 0x10a5
+#define regCP_ME_PRGRM_CNTR_START_BASE_IDX 0
+#define regCP_MEC1_PRGRM_CNTR_START 0x10a6
+#define regCP_MEC1_PRGRM_CNTR_START_BASE_IDX 0
+#define regCP_MEC2_PRGRM_CNTR_START 0x10a7
+#define regCP_MEC2_PRGRM_CNTR_START_BASE_IDX 0
+#define regCP_CE_INTR_ROUTINE_START 0x10a8
+#define regCP_CE_INTR_ROUTINE_START_BASE_IDX 0
+#define regCP_PFP_INTR_ROUTINE_START 0x10a9
+#define regCP_PFP_INTR_ROUTINE_START_BASE_IDX 0
+#define regCP_ME_INTR_ROUTINE_START 0x10aa
+#define regCP_ME_INTR_ROUTINE_START_BASE_IDX 0
+#define regCP_MEC1_INTR_ROUTINE_START 0x10ab
+#define regCP_MEC1_INTR_ROUTINE_START_BASE_IDX 0
+#define regCP_MEC2_INTR_ROUTINE_START 0x10ac
+#define regCP_MEC2_INTR_ROUTINE_START_BASE_IDX 0
+#define regCP_CONTEXT_CNTL 0x10ad
+#define regCP_CONTEXT_CNTL_BASE_IDX 0
+#define regCP_MAX_CONTEXT 0x10ae
+#define regCP_MAX_CONTEXT_BASE_IDX 0
+#define regCP_IQ_WAIT_TIME1 0x10af
+#define regCP_IQ_WAIT_TIME1_BASE_IDX 0
+#define regCP_IQ_WAIT_TIME2 0x10b0
+#define regCP_IQ_WAIT_TIME2_BASE_IDX 0
+#define regCP_RB0_BASE_HI 0x10b1
+#define regCP_RB0_BASE_HI_BASE_IDX 0
+#define regCP_RB1_BASE_HI 0x10b2
+#define regCP_RB1_BASE_HI_BASE_IDX 0
+#define regCP_VMID_RESET 0x10b3
+#define regCP_VMID_RESET_BASE_IDX 0
+#define regCPC_INT_CNTL 0x10b4
+#define regCPC_INT_CNTL_BASE_IDX 0
+#define regCPC_INT_STATUS 0x10b5
+#define regCPC_INT_STATUS_BASE_IDX 0
+#define regCP_VMID_PREEMPT 0x10b6
+#define regCP_VMID_PREEMPT_BASE_IDX 0
+#define regCPC_INT_CNTX_ID 0x10b7
+#define regCPC_INT_CNTX_ID_BASE_IDX 0
+#define regCP_PQ_STATUS 0x10b8
+#define regCP_PQ_STATUS_BASE_IDX 0
+#define regCP_CPC_IC_BASE_LO 0x10b9
+#define regCP_CPC_IC_BASE_LO_BASE_IDX 0
+#define regCP_CPC_IC_BASE_HI 0x10ba
+#define regCP_CPC_IC_BASE_HI_BASE_IDX 0
+#define regCP_CPC_IC_BASE_CNTL 0x10bb
+#define regCP_CPC_IC_BASE_CNTL_BASE_IDX 0
+#define regCP_CPC_IC_OP_CNTL 0x10bc
+#define regCP_CPC_IC_OP_CNTL_BASE_IDX 0
+#define regCP_MEC1_F32_INT_DIS 0x10bd
+#define regCP_MEC1_F32_INT_DIS_BASE_IDX 0
+#define regCP_MEC2_F32_INT_DIS 0x10be
+#define regCP_MEC2_F32_INT_DIS_BASE_IDX 0
+#define regCP_VMID_STATUS 0x10bf
+#define regCP_VMID_STATUS_BASE_IDX 0
+
+
+// addressBlock: gc_cppdec2
+// base address: 0xc600
+#define regCP_RB_DOORBELL_CONTROL_SCH_0 0x1180
+#define regCP_RB_DOORBELL_CONTROL_SCH_0_BASE_IDX 0
+#define regCP_RB_DOORBELL_CONTROL_SCH_1 0x1181
+#define regCP_RB_DOORBELL_CONTROL_SCH_1_BASE_IDX 0
+#define regCP_RB_DOORBELL_CONTROL_SCH_2 0x1182
+#define regCP_RB_DOORBELL_CONTROL_SCH_2_BASE_IDX 0
+#define regCP_RB_DOORBELL_CONTROL_SCH_3 0x1183
+#define regCP_RB_DOORBELL_CONTROL_SCH_3_BASE_IDX 0
+#define regCP_RB_DOORBELL_CONTROL_SCH_4 0x1184
+#define regCP_RB_DOORBELL_CONTROL_SCH_4_BASE_IDX 0
+#define regCP_RB_DOORBELL_CONTROL_SCH_5 0x1185
+#define regCP_RB_DOORBELL_CONTROL_SCH_5_BASE_IDX 0
+#define regCP_RB_DOORBELL_CONTROL_SCH_6 0x1186
+#define regCP_RB_DOORBELL_CONTROL_SCH_6_BASE_IDX 0
+#define regCP_RB_DOORBELL_CONTROL_SCH_7 0x1187
+#define regCP_RB_DOORBELL_CONTROL_SCH_7_BASE_IDX 0
+#define regCP_RB_DOORBELL_CLEAR 0x1188
+#define regCP_RB_DOORBELL_CLEAR_BASE_IDX 0
+#define regCPF_EDC_TAG_CNT 0x1189
+#define regCPF_EDC_TAG_CNT_BASE_IDX 0
+#define regCPF_EDC_ROQ_CNT 0x118a
+#define regCPF_EDC_ROQ_CNT_BASE_IDX 0
+#define regCPG_EDC_TAG_CNT 0x118b
+#define regCPG_EDC_TAG_CNT_BASE_IDX 0
+#define regCPG_EDC_DMA_CNT 0x118d
+#define regCPG_EDC_DMA_CNT_BASE_IDX 0
+#define regCPC_EDC_SCRATCH_CNT 0x118e
+#define regCPC_EDC_SCRATCH_CNT_BASE_IDX 0
+#define regCPC_EDC_UCODE_CNT 0x118f
+#define regCPC_EDC_UCODE_CNT_BASE_IDX 0
+#define regDC_EDC_STATE_CNT 0x1191
+#define regDC_EDC_STATE_CNT_BASE_IDX 0
+#define regDC_EDC_CSINVOC_CNT 0x1192
+#define regDC_EDC_CSINVOC_CNT_BASE_IDX 0
+#define regDC_EDC_RESTORE_CNT 0x1193
+#define regDC_EDC_RESTORE_CNT_BASE_IDX 0
+#define regCP_CPF_DSM_CNTL 0x1194
+#define regCP_CPF_DSM_CNTL_BASE_IDX 0
+#define regCP_CPG_DSM_CNTL 0x1195
+#define regCP_CPG_DSM_CNTL_BASE_IDX 0
+#define regCP_CPC_DSM_CNTL 0x1196
+#define regCP_CPC_DSM_CNTL_BASE_IDX 0
+#define regCP_CPF_DSM_CNTL2 0x1197
+#define regCP_CPF_DSM_CNTL2_BASE_IDX 0
+#define regCP_CPG_DSM_CNTL2 0x1198
+#define regCP_CPG_DSM_CNTL2_BASE_IDX 0
+#define regCP_CPC_DSM_CNTL2 0x1199
+#define regCP_CPC_DSM_CNTL2_BASE_IDX 0
+#define regCP_CPF_DSM_CNTL2A 0x119a
+#define regCP_CPF_DSM_CNTL2A_BASE_IDX 0
+#define regCP_CPG_DSM_CNTL2A 0x119b
+#define regCP_CPG_DSM_CNTL2A_BASE_IDX 0
+#define regCP_CPC_DSM_CNTL2A 0x119c
+#define regCP_CPC_DSM_CNTL2A_BASE_IDX 0
+#define regCP_EDC_FUE_CNTL 0x119d
+#define regCP_EDC_FUE_CNTL_BASE_IDX 0
+#define regCP_GFX_MQD_CONTROL 0x11a0
+#define regCP_GFX_MQD_CONTROL_BASE_IDX 0
+#define regCP_GFX_MQD_BASE_ADDR 0x11a1
+#define regCP_GFX_MQD_BASE_ADDR_BASE_IDX 0
+#define regCP_GFX_MQD_BASE_ADDR_HI 0x11a2
+#define regCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX 0
+#define regCP_RB_STATUS 0x11a3
+#define regCP_RB_STATUS_BASE_IDX 0
+#define regCPG_UTCL1_STATUS 0x11b4
+#define regCPG_UTCL1_STATUS_BASE_IDX 0
+#define regCPC_UTCL1_STATUS 0x11b5
+#define regCPC_UTCL1_STATUS_BASE_IDX 0
+#define regCPF_UTCL1_STATUS 0x11b6
+#define regCPF_UTCL1_STATUS_BASE_IDX 0
+#define regCP_SD_CNTL 0x11b7
+#define regCP_SD_CNTL_BASE_IDX 0
+#define regCP_SOFT_RESET_CNTL 0x11b9
+#define regCP_SOFT_RESET_CNTL_BASE_IDX 0
+#define regCP_CPC_GFX_CNTL 0x11ba
+#define regCP_CPC_GFX_CNTL_BASE_IDX 0
+
+
+// addressBlock: gc_cpphqddec
+// base address: 0xc800
+#define regCP_HQD_GFX_CONTROL 0x123e
+#define regCP_HQD_GFX_CONTROL_BASE_IDX 0
+#define regCP_HQD_GFX_STATUS 0x123f
+#define regCP_HQD_GFX_STATUS_BASE_IDX 0
+#define regCP_HPD_ROQ_OFFSETS 0x1240
+#define regCP_HPD_ROQ_OFFSETS_BASE_IDX 0
+#define regCP_HPD_STATUS0 0x1241
+#define regCP_HPD_STATUS0_BASE_IDX 0
+#define regCP_HPD_UTCL1_CNTL 0x1242
+#define regCP_HPD_UTCL1_CNTL_BASE_IDX 0
+#define regCP_HPD_UTCL1_ERROR 0x1243
+#define regCP_HPD_UTCL1_ERROR_BASE_IDX 0
+#define regCP_HPD_UTCL1_ERROR_ADDR 0x1244
+#define regCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX 0
+#define regCP_MQD_BASE_ADDR 0x1245
+#define regCP_MQD_BASE_ADDR_BASE_IDX 0
+#define regCP_MQD_BASE_ADDR_HI 0x1246
+#define regCP_MQD_BASE_ADDR_HI_BASE_IDX 0
+#define regCP_HQD_ACTIVE 0x1247
+#define regCP_HQD_ACTIVE_BASE_IDX 0
+#define regCP_HQD_VMID 0x1248
+#define regCP_HQD_VMID_BASE_IDX 0
+#define regCP_HQD_PERSISTENT_STATE 0x1249
+#define regCP_HQD_PERSISTENT_STATE_BASE_IDX 0
+#define regCP_HQD_PIPE_PRIORITY 0x124a
+#define regCP_HQD_PIPE_PRIORITY_BASE_IDX 0
+#define regCP_HQD_QUEUE_PRIORITY 0x124b
+#define regCP_HQD_QUEUE_PRIORITY_BASE_IDX 0
+#define regCP_HQD_QUANTUM 0x124c
+#define regCP_HQD_QUANTUM_BASE_IDX 0
+#define regCP_HQD_PQ_BASE 0x124d
+#define regCP_HQD_PQ_BASE_BASE_IDX 0
+#define regCP_HQD_PQ_BASE_HI 0x124e
+#define regCP_HQD_PQ_BASE_HI_BASE_IDX 0
+#define regCP_HQD_PQ_RPTR 0x124f
+#define regCP_HQD_PQ_RPTR_BASE_IDX 0
+#define regCP_HQD_PQ_RPTR_REPORT_ADDR 0x1250
+#define regCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX 0
+#define regCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1251
+#define regCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX 0
+#define regCP_HQD_PQ_WPTR_POLL_ADDR 0x1252
+#define regCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX 0
+#define regCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x1253
+#define regCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regCP_HQD_PQ_DOORBELL_CONTROL 0x1254
+#define regCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX 0
+#define regCP_HQD_PQ_CONTROL 0x1256
+#define regCP_HQD_PQ_CONTROL_BASE_IDX 0
+#define regCP_HQD_IB_BASE_ADDR 0x1257
+#define regCP_HQD_IB_BASE_ADDR_BASE_IDX 0
+#define regCP_HQD_IB_BASE_ADDR_HI 0x1258
+#define regCP_HQD_IB_BASE_ADDR_HI_BASE_IDX 0
+#define regCP_HQD_IB_RPTR 0x1259
+#define regCP_HQD_IB_RPTR_BASE_IDX 0
+#define regCP_HQD_IB_CONTROL 0x125a
+#define regCP_HQD_IB_CONTROL_BASE_IDX 0
+#define regCP_HQD_IQ_TIMER 0x125b
+#define regCP_HQD_IQ_TIMER_BASE_IDX 0
+#define regCP_HQD_IQ_RPTR 0x125c
+#define regCP_HQD_IQ_RPTR_BASE_IDX 0
+#define regCP_HQD_DEQUEUE_REQUEST 0x125d
+#define regCP_HQD_DEQUEUE_REQUEST_BASE_IDX 0
+#define regCP_HQD_DMA_OFFLOAD 0x125e
+#define regCP_HQD_DMA_OFFLOAD_BASE_IDX 0
+#define regCP_HQD_OFFLOAD 0x125e
+#define regCP_HQD_OFFLOAD_BASE_IDX 0
+#define regCP_HQD_SEMA_CMD 0x125f
+#define regCP_HQD_SEMA_CMD_BASE_IDX 0
+#define regCP_HQD_MSG_TYPE 0x1260
+#define regCP_HQD_MSG_TYPE_BASE_IDX 0
+#define regCP_HQD_ATOMIC0_PREOP_LO 0x1261
+#define regCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX 0
+#define regCP_HQD_ATOMIC0_PREOP_HI 0x1262
+#define regCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX 0
+#define regCP_HQD_ATOMIC1_PREOP_LO 0x1263
+#define regCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX 0
+#define regCP_HQD_ATOMIC1_PREOP_HI 0x1264
+#define regCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX 0
+#define regCP_HQD_HQ_SCHEDULER0 0x1265
+#define regCP_HQD_HQ_SCHEDULER0_BASE_IDX 0
+#define regCP_HQD_HQ_STATUS0 0x1265
+#define regCP_HQD_HQ_STATUS0_BASE_IDX 0
+#define regCP_HQD_HQ_CONTROL0 0x1266
+#define regCP_HQD_HQ_CONTROL0_BASE_IDX 0
+#define regCP_HQD_HQ_SCHEDULER1 0x1266
+#define regCP_HQD_HQ_SCHEDULER1_BASE_IDX 0
+#define regCP_MQD_CONTROL 0x1267
+#define regCP_MQD_CONTROL_BASE_IDX 0
+#define regCP_HQD_HQ_STATUS1 0x1268
+#define regCP_HQD_HQ_STATUS1_BASE_IDX 0
+#define regCP_HQD_HQ_CONTROL1 0x1269
+#define regCP_HQD_HQ_CONTROL1_BASE_IDX 0
+#define regCP_HQD_EOP_BASE_ADDR 0x126a
+#define regCP_HQD_EOP_BASE_ADDR_BASE_IDX 0
+#define regCP_HQD_EOP_BASE_ADDR_HI 0x126b
+#define regCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX 0
+#define regCP_HQD_EOP_CONTROL 0x126c
+#define regCP_HQD_EOP_CONTROL_BASE_IDX 0
+#define regCP_HQD_EOP_RPTR 0x126d
+#define regCP_HQD_EOP_RPTR_BASE_IDX 0
+#define regCP_HQD_EOP_WPTR 0x126e
+#define regCP_HQD_EOP_WPTR_BASE_IDX 0
+#define regCP_HQD_EOP_EVENTS 0x126f
+#define regCP_HQD_EOP_EVENTS_BASE_IDX 0
+#define regCP_HQD_CTX_SAVE_BASE_ADDR_LO 0x1270
+#define regCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX 0
+#define regCP_HQD_CTX_SAVE_BASE_ADDR_HI 0x1271
+#define regCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX 0
+#define regCP_HQD_CTX_SAVE_CONTROL 0x1272
+#define regCP_HQD_CTX_SAVE_CONTROL_BASE_IDX 0
+#define regCP_HQD_CNTL_STACK_OFFSET 0x1273
+#define regCP_HQD_CNTL_STACK_OFFSET_BASE_IDX 0
+#define regCP_HQD_CNTL_STACK_SIZE 0x1274
+#define regCP_HQD_CNTL_STACK_SIZE_BASE_IDX 0
+#define regCP_HQD_WG_STATE_OFFSET 0x1275
+#define regCP_HQD_WG_STATE_OFFSET_BASE_IDX 0
+#define regCP_HQD_CTX_SAVE_SIZE 0x1276
+#define regCP_HQD_CTX_SAVE_SIZE_BASE_IDX 0
+#define regCP_HQD_GDS_RESOURCE_STATE 0x1277
+#define regCP_HQD_GDS_RESOURCE_STATE_BASE_IDX 0
+#define regCP_HQD_ERROR 0x1278
+#define regCP_HQD_ERROR_BASE_IDX 0
+#define regCP_HQD_EOP_WPTR_MEM 0x1279
+#define regCP_HQD_EOP_WPTR_MEM_BASE_IDX 0
+#define regCP_HQD_AQL_CONTROL 0x127a
+#define regCP_HQD_AQL_CONTROL_BASE_IDX 0
+#define regCP_HQD_PQ_WPTR_LO 0x127b
+#define regCP_HQD_PQ_WPTR_LO_BASE_IDX 0
+#define regCP_HQD_PQ_WPTR_HI 0x127c
+#define regCP_HQD_PQ_WPTR_HI_BASE_IDX 0
+
+
+// addressBlock: gc_didtdec
+// base address: 0xca00
+#define regDIDT_IND_INDEX 0x1280
+#define regDIDT_IND_INDEX_BASE_IDX 0
+#define regDIDT_IND_DATA 0x1281
+#define regDIDT_IND_DATA_BASE_IDX 0
+#define regDIDT_INDEX_AUTO_INCR_EN 0x1282
+#define regDIDT_INDEX_AUTO_INCR_EN_BASE_IDX 0
+
+
+// addressBlock: gc_ea_gceadec
+// base address: 0xa800
+#define regGCEA_DRAM_RD_CLI2GRP_MAP0 0x0a00
+#define regGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0
+#define regGCEA_DRAM_RD_CLI2GRP_MAP1 0x0a01
+#define regGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0
+#define regGCEA_DRAM_WR_CLI2GRP_MAP0 0x0a02
+#define regGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0
+#define regGCEA_DRAM_WR_CLI2GRP_MAP1 0x0a03
+#define regGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0
+#define regGCEA_DRAM_RD_GRP2VC_MAP 0x0a04
+#define regGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX 0
+#define regGCEA_DRAM_WR_GRP2VC_MAP 0x0a05
+#define regGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX 0
+#define regGCEA_DRAM_RD_LAZY 0x0a06
+#define regGCEA_DRAM_RD_LAZY_BASE_IDX 0
+#define regGCEA_DRAM_WR_LAZY 0x0a07
+#define regGCEA_DRAM_WR_LAZY_BASE_IDX 0
+#define regGCEA_DRAM_RD_CAM_CNTL 0x0a08
+#define regGCEA_DRAM_RD_CAM_CNTL_BASE_IDX 0
+#define regGCEA_DRAM_WR_CAM_CNTL 0x0a09
+#define regGCEA_DRAM_WR_CAM_CNTL_BASE_IDX 0
+#define regGCEA_DRAM_PAGE_BURST 0x0a0a
+#define regGCEA_DRAM_PAGE_BURST_BASE_IDX 0
+#define regGCEA_DRAM_RD_PRI_AGE 0x0a0b
+#define regGCEA_DRAM_RD_PRI_AGE_BASE_IDX 0
+#define regGCEA_DRAM_WR_PRI_AGE 0x0a0c
+#define regGCEA_DRAM_WR_PRI_AGE_BASE_IDX 0
+#define regGCEA_DRAM_RD_PRI_QUEUING 0x0a0d
+#define regGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX 0
+#define regGCEA_DRAM_WR_PRI_QUEUING 0x0a0e
+#define regGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX 0
+#define regGCEA_DRAM_RD_PRI_FIXED 0x0a0f
+#define regGCEA_DRAM_RD_PRI_FIXED_BASE_IDX 0
+#define regGCEA_DRAM_WR_PRI_FIXED 0x0a10
+#define regGCEA_DRAM_WR_PRI_FIXED_BASE_IDX 0
+#define regGCEA_DRAM_RD_PRI_URGENCY 0x0a11
+#define regGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX 0
+#define regGCEA_DRAM_WR_PRI_URGENCY 0x0a12
+#define regGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX 0
+#define regGCEA_DRAM_RD_PRI_QUANT_PRI1 0x0a13
+#define regGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0
+#define regGCEA_DRAM_RD_PRI_QUANT_PRI2 0x0a14
+#define regGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0
+#define regGCEA_DRAM_RD_PRI_QUANT_PRI3 0x0a15
+#define regGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0
+#define regGCEA_DRAM_WR_PRI_QUANT_PRI1 0x0a16
+#define regGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0
+#define regGCEA_DRAM_WR_PRI_QUANT_PRI2 0x0a17
+#define regGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0
+#define regGCEA_DRAM_WR_PRI_QUANT_PRI3 0x0a18
+#define regGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0
+#define regGCEA_ADDRNORM_BASE_ADDR0 0x0a34
+#define regGCEA_ADDRNORM_BASE_ADDR0_BASE_IDX 0
+#define regGCEA_ADDRNORM_LIMIT_ADDR0 0x0a35
+#define regGCEA_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0
+#define regGCEA_ADDRNORM_BASE_ADDR1 0x0a36
+#define regGCEA_ADDRNORM_BASE_ADDR1_BASE_IDX 0
+#define regGCEA_ADDRNORM_LIMIT_ADDR1 0x0a37
+#define regGCEA_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0
+#define regGCEA_ADDRNORM_OFFSET_ADDR1 0x0a38
+#define regGCEA_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0
+#define regGCEA_ADDRNORM_BASE_ADDR2 0x0a39
+#define regGCEA_ADDRNORM_BASE_ADDR2_BASE_IDX 0
+#define regGCEA_ADDRNORM_LIMIT_ADDR2 0x0a3a
+#define regGCEA_ADDRNORM_LIMIT_ADDR2_BASE_IDX 0
+#define regGCEA_ADDRNORM_BASE_ADDR3 0x0a3b
+#define regGCEA_ADDRNORM_BASE_ADDR3_BASE_IDX 0
+#define regGCEA_ADDRNORM_LIMIT_ADDR3 0x0a3c
+#define regGCEA_ADDRNORM_LIMIT_ADDR3_BASE_IDX 0
+#define regGCEA_ADDRNORM_OFFSET_ADDR3 0x0a3d
+#define regGCEA_ADDRNORM_OFFSET_ADDR3_BASE_IDX 0
+#define regGCEA_ADDRNORM_MEGABASE_ADDR0 0x0a3e
+#define regGCEA_ADDRNORM_MEGABASE_ADDR0_BASE_IDX 0
+#define regGCEA_ADDRNORM_MEGALIMIT_ADDR0 0x0a3f
+#define regGCEA_ADDRNORM_MEGALIMIT_ADDR0_BASE_IDX 0
+#define regGCEA_ADDRNORM_MEGABASE_ADDR1 0x0a40
+#define regGCEA_ADDRNORM_MEGABASE_ADDR1_BASE_IDX 0
+#define regGCEA_ADDRNORM_MEGALIMIT_ADDR1 0x0a41
+#define regGCEA_ADDRNORM_MEGALIMIT_ADDR1_BASE_IDX 0
+#define regGCEA_ADDRNORMDRAM_HOLE_CNTL 0x0a43
+#define regGCEA_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0
+#define regGCEA_ADDRNORMGMI_HOLE_CNTL 0x0a44
+#define regGCEA_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 0
+#define regGCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0a45
+#define regGCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 0
+#define regGCEA_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0a46
+#define regGCEA_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 0
+#define regGCEA_ADDRDEC_BANK_CFG 0x0a47
+#define regGCEA_ADDRDEC_BANK_CFG_BASE_IDX 0
+#define regGCEA_ADDRDEC_MISC_CFG 0x0a48
+#define regGCEA_ADDRDEC_MISC_CFG_BASE_IDX 0
+#define regGCEA_ADDRDECDRAM_HARVEST_ENABLE 0x0a53
+#define regGCEA_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0
+#define regGCEA_ADDRDECGMI_HARVEST_ENABLE 0x0a5e
+#define regGCEA_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 0
+#define regGCEA_ADDRDEC0_BASE_ADDR_CS0 0x0a5f
+#define regGCEA_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0
+#define regGCEA_ADDRDEC0_BASE_ADDR_CS1 0x0a60
+#define regGCEA_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0
+#define regGCEA_ADDRDEC0_BASE_ADDR_CS2 0x0a61
+#define regGCEA_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0
+#define regGCEA_ADDRDEC0_BASE_ADDR_CS3 0x0a62
+#define regGCEA_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0
+#define regGCEA_ADDRDEC0_BASE_ADDR_SECCS0 0x0a63
+#define regGCEA_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0
+#define regGCEA_ADDRDEC0_BASE_ADDR_SECCS1 0x0a64
+#define regGCEA_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0
+#define regGCEA_ADDRDEC0_BASE_ADDR_SECCS2 0x0a65
+#define regGCEA_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0
+#define regGCEA_ADDRDEC0_BASE_ADDR_SECCS3 0x0a66
+#define regGCEA_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0
+#define regGCEA_ADDRDEC0_ADDR_MASK_CS01 0x0a67
+#define regGCEA_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0
+#define regGCEA_ADDRDEC0_ADDR_MASK_CS23 0x0a68
+#define regGCEA_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0
+#define regGCEA_ADDRDEC0_ADDR_MASK_SECCS01 0x0a69
+#define regGCEA_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0
+#define regGCEA_ADDRDEC0_ADDR_MASK_SECCS23 0x0a6a
+#define regGCEA_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0
+#define regGCEA_ADDRDEC0_ADDR_CFG_CS01 0x0a6b
+#define regGCEA_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0
+#define regGCEA_ADDRDEC0_ADDR_CFG_CS23 0x0a6c
+#define regGCEA_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0
+#define regGCEA_ADDRDEC0_ADDR_SEL_CS01 0x0a6d
+#define regGCEA_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0
+#define regGCEA_ADDRDEC0_ADDR_SEL_CS23 0x0a6e
+#define regGCEA_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0
+#define regGCEA_ADDRDEC0_ADDR_SEL2_CS01 0x0a6f
+#define regGCEA_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 0
+#define regGCEA_ADDRDEC0_ADDR_SEL2_CS23 0x0a70
+#define regGCEA_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 0
+#define regGCEA_ADDRDEC0_COL_SEL_LO_CS01 0x0a71
+#define regGCEA_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0
+#define regGCEA_ADDRDEC0_COL_SEL_LO_CS23 0x0a72
+#define regGCEA_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0
+#define regGCEA_ADDRDEC0_COL_SEL_HI_CS01 0x0a73
+#define regGCEA_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0
+#define regGCEA_ADDRDEC0_COL_SEL_HI_CS23 0x0a74
+#define regGCEA_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0
+#define regGCEA_ADDRDEC0_RM_SEL_CS01 0x0a75
+#define regGCEA_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0
+#define regGCEA_ADDRDEC0_RM_SEL_CS23 0x0a76
+#define regGCEA_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0
+#define regGCEA_ADDRDEC0_RM_SEL_SECCS01 0x0a77
+#define regGCEA_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0
+#define regGCEA_ADDRDEC0_RM_SEL_SECCS23 0x0a78
+#define regGCEA_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0
+#define regGCEA_ADDRDEC1_BASE_ADDR_CS0 0x0a79
+#define regGCEA_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0
+#define regGCEA_ADDRDEC1_BASE_ADDR_CS1 0x0a7a
+#define regGCEA_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0
+#define regGCEA_ADDRDEC1_BASE_ADDR_CS2 0x0a7b
+#define regGCEA_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0
+#define regGCEA_ADDRDEC1_BASE_ADDR_CS3 0x0a7c
+#define regGCEA_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0
+#define regGCEA_ADDRDEC1_BASE_ADDR_SECCS0 0x0a7d
+#define regGCEA_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0
+#define regGCEA_ADDRDEC1_BASE_ADDR_SECCS1 0x0a7e
+#define regGCEA_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0
+#define regGCEA_ADDRDEC1_BASE_ADDR_SECCS2 0x0a7f
+#define regGCEA_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0
+#define regGCEA_ADDRDEC1_BASE_ADDR_SECCS3 0x0a80
+#define regGCEA_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0
+#define regGCEA_ADDRDEC1_ADDR_MASK_CS01 0x0a81
+#define regGCEA_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0
+#define regGCEA_ADDRDEC1_ADDR_MASK_CS23 0x0a82
+#define regGCEA_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0
+#define regGCEA_ADDRDEC1_ADDR_MASK_SECCS01 0x0a83
+#define regGCEA_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0
+#define regGCEA_ADDRDEC1_ADDR_MASK_SECCS23 0x0a84
+#define regGCEA_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0
+#define regGCEA_ADDRDEC1_ADDR_CFG_CS01 0x0a85
+#define regGCEA_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0
+#define regGCEA_ADDRDEC1_ADDR_CFG_CS23 0x0a86
+#define regGCEA_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0
+#define regGCEA_ADDRDEC1_ADDR_SEL_CS01 0x0a87
+#define regGCEA_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0
+#define regGCEA_ADDRDEC1_ADDR_SEL_CS23 0x0a88
+#define regGCEA_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0
+#define regGCEA_ADDRDEC1_ADDR_SEL2_CS01 0x0a89
+#define regGCEA_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 0
+#define regGCEA_ADDRDEC1_ADDR_SEL2_CS23 0x0a8a
+#define regGCEA_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 0
+#define regGCEA_ADDRDEC1_COL_SEL_LO_CS01 0x0a8b
+#define regGCEA_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0
+#define regGCEA_ADDRDEC1_COL_SEL_LO_CS23 0x0a8c
+#define regGCEA_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0
+#define regGCEA_ADDRDEC1_COL_SEL_HI_CS01 0x0a8d
+#define regGCEA_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0
+#define regGCEA_ADDRDEC1_COL_SEL_HI_CS23 0x0a8e
+#define regGCEA_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0
+#define regGCEA_ADDRDEC1_RM_SEL_CS01 0x0a8f
+#define regGCEA_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0
+#define regGCEA_ADDRDEC1_RM_SEL_CS23 0x0a90
+#define regGCEA_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0
+#define regGCEA_ADDRDEC1_RM_SEL_SECCS01 0x0a91
+#define regGCEA_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0
+#define regGCEA_ADDRDEC1_RM_SEL_SECCS23 0x0a92
+#define regGCEA_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0
+#define regGCEA_ADDRDEC2_BASE_ADDR_CS0 0x0a93
+#define regGCEA_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 0
+#define regGCEA_ADDRDEC2_BASE_ADDR_CS1 0x0a94
+#define regGCEA_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 0
+#define regGCEA_ADDRDEC2_BASE_ADDR_CS2 0x0a95
+#define regGCEA_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 0
+#define regGCEA_ADDRDEC2_BASE_ADDR_CS3 0x0a96
+#define regGCEA_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 0
+#define regGCEA_ADDRDEC2_BASE_ADDR_SECCS0 0x0a97
+#define regGCEA_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 0
+#define regGCEA_ADDRDEC2_BASE_ADDR_SECCS1 0x0a98
+#define regGCEA_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 0
+#define regGCEA_ADDRDEC2_BASE_ADDR_SECCS2 0x0a99
+#define regGCEA_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 0
+#define regGCEA_ADDRDEC2_BASE_ADDR_SECCS3 0x0a9a
+#define regGCEA_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 0
+#define regGCEA_ADDRDEC2_ADDR_MASK_CS01 0x0a9b
+#define regGCEA_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 0
+#define regGCEA_ADDRDEC2_ADDR_MASK_CS23 0x0a9c
+#define regGCEA_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 0
+#define regGCEA_ADDRDEC2_ADDR_MASK_SECCS01 0x0a9d
+#define regGCEA_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 0
+#define regGCEA_ADDRDEC2_ADDR_MASK_SECCS23 0x0a9e
+#define regGCEA_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 0
+#define regGCEA_ADDRDEC2_ADDR_CFG_CS01 0x0a9f
+#define regGCEA_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 0
+#define regGCEA_ADDRDEC2_ADDR_CFG_CS23 0x0aa0
+#define regGCEA_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 0
+#define regGCEA_ADDRDEC2_ADDR_SEL_CS01 0x0aa1
+#define regGCEA_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 0
+#define regGCEA_ADDRDEC2_ADDR_SEL_CS23 0x0aa2
+#define regGCEA_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 0
+#define regGCEA_ADDRDEC2_ADDR_SEL2_CS01 0x0aa3
+#define regGCEA_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 0
+#define regGCEA_ADDRDEC2_ADDR_SEL2_CS23 0x0aa4
+#define regGCEA_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 0
+#define regGCEA_ADDRDEC2_COL_SEL_LO_CS01 0x0aa5
+#define regGCEA_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 0
+#define regGCEA_ADDRDEC2_COL_SEL_LO_CS23 0x0aa6
+#define regGCEA_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 0
+#define regGCEA_ADDRDEC2_COL_SEL_HI_CS01 0x0aa7
+#define regGCEA_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 0
+#define regGCEA_ADDRDEC2_COL_SEL_HI_CS23 0x0aa8
+#define regGCEA_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 0
+#define regGCEA_ADDRDEC2_RM_SEL_CS01 0x0aa9
+#define regGCEA_ADDRDEC2_RM_SEL_CS01_BASE_IDX 0
+#define regGCEA_ADDRDEC2_RM_SEL_CS23 0x0aaa
+#define regGCEA_ADDRDEC2_RM_SEL_CS23_BASE_IDX 0
+#define regGCEA_ADDRDEC2_RM_SEL_SECCS01 0x0aab
+#define regGCEA_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 0
+#define regGCEA_ADDRDEC2_RM_SEL_SECCS23 0x0aac
+#define regGCEA_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 0
+#define regGCEA_ADDRNORMDRAM_GLOBAL_CNTL 0x0aad
+#define regGCEA_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 0
+#define regGCEA_ADDRNORMGMI_GLOBAL_CNTL 0x0aae
+#define regGCEA_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 0
+#define regGCEA_ADDRNORM_MEGACONTROL_ADDR0 0x0ad1
+#define regGCEA_ADDRNORM_MEGACONTROL_ADDR0_BASE_IDX 0
+#define regGCEA_ADDRNORM_MEGACONTROL_ADDR1 0x0ad2
+#define regGCEA_ADDRNORM_MEGACONTROL_ADDR1_BASE_IDX 0
+#define regGCEA_ADDRNORMDRAM_MASKING 0x0ad3
+#define regGCEA_ADDRNORMDRAM_MASKING_BASE_IDX 0
+#define regGCEA_ADDRNORMGMI_MASKING 0x0ad4
+#define regGCEA_ADDRNORMGMI_MASKING_BASE_IDX 0
+#define regGCEA_IO_RD_CLI2GRP_MAP0 0x0ad5
+#define regGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX 0
+#define regGCEA_IO_RD_CLI2GRP_MAP1 0x0ad6
+#define regGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX 0
+#define regGCEA_IO_WR_CLI2GRP_MAP0 0x0ad7
+#define regGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX 0
+#define regGCEA_IO_WR_CLI2GRP_MAP1 0x0ad8
+#define regGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX 0
+#define regGCEA_IO_RD_COMBINE_FLUSH 0x0ad9
+#define regGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX 0
+#define regGCEA_IO_WR_COMBINE_FLUSH 0x0ada
+#define regGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX 0
+#define regGCEA_IO_GROUP_BURST 0x0adb
+#define regGCEA_IO_GROUP_BURST_BASE_IDX 0
+#define regGCEA_IO_RD_PRI_AGE 0x0adc
+#define regGCEA_IO_RD_PRI_AGE_BASE_IDX 0
+#define regGCEA_IO_WR_PRI_AGE 0x0add
+#define regGCEA_IO_WR_PRI_AGE_BASE_IDX 0
+#define regGCEA_IO_RD_PRI_QUEUING 0x0ade
+#define regGCEA_IO_RD_PRI_QUEUING_BASE_IDX 0
+#define regGCEA_IO_WR_PRI_QUEUING 0x0adf
+#define regGCEA_IO_WR_PRI_QUEUING_BASE_IDX 0
+#define regGCEA_IO_RD_PRI_FIXED 0x0ae0
+#define regGCEA_IO_RD_PRI_FIXED_BASE_IDX 0
+#define regGCEA_IO_WR_PRI_FIXED 0x0ae1
+#define regGCEA_IO_WR_PRI_FIXED_BASE_IDX 0
+#define regGCEA_IO_RD_PRI_URGENCY 0x0ae2
+#define regGCEA_IO_RD_PRI_URGENCY_BASE_IDX 0
+#define regGCEA_IO_WR_PRI_URGENCY 0x0ae3
+#define regGCEA_IO_WR_PRI_URGENCY_BASE_IDX 0
+#define regGCEA_IO_RD_PRI_URGENCY_MASKING 0x0ae4
+#define regGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0
+#define regGCEA_IO_WR_PRI_URGENCY_MASKING 0x0ae5
+#define regGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0
+#define regGCEA_IO_RD_PRI_QUANT_PRI1 0x0ae6
+#define regGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0
+#define regGCEA_IO_RD_PRI_QUANT_PRI2 0x0ae7
+#define regGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0
+#define regGCEA_IO_RD_PRI_QUANT_PRI3 0x0ae8
+#define regGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0
+#define regGCEA_IO_WR_PRI_QUANT_PRI1 0x0ae9
+#define regGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0
+#define regGCEA_IO_WR_PRI_QUANT_PRI2 0x0aea
+#define regGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0
+#define regGCEA_IO_WR_PRI_QUANT_PRI3 0x0aeb
+#define regGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0
+#define regGCEA_MISC 0x0afa
+#define regGCEA_MISC_BASE_IDX 0
+#define regGCEA_LATENCY_SAMPLING 0x0afb
+#define regGCEA_LATENCY_SAMPLING_BASE_IDX 0
+#define regGCEA_PERFCOUNTER_LO 0x0afc
+#define regGCEA_PERFCOUNTER_LO_BASE_IDX 0
+#define regGCEA_PERFCOUNTER_HI 0x0afd
+#define regGCEA_PERFCOUNTER_HI_BASE_IDX 0
+#define regGCEA_PERFCOUNTER0_CFG 0x0afe
+#define regGCEA_PERFCOUNTER0_CFG_BASE_IDX 0
+#define regGCEA_PERFCOUNTER1_CFG 0x0aff
+#define regGCEA_PERFCOUNTER1_CFG_BASE_IDX 0
+
+
+// addressBlock: gc_ea_gceadec2
+// base address: 0x9c00
+#define regGCEA_PERFCOUNTER_RSLT_CNTL 0x0700
+#define regGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+#define regGCEA_EDC_CNT 0x0706
+#define regGCEA_EDC_CNT_BASE_IDX 0
+#define regGCEA_EDC_CNT2 0x0707
+#define regGCEA_EDC_CNT2_BASE_IDX 0
+#define regGCEA_DSM_CNTL 0x0708
+#define regGCEA_DSM_CNTL_BASE_IDX 0
+#define regGCEA_DSM_CNTLA 0x0709
+#define regGCEA_DSM_CNTLA_BASE_IDX 0
+#define regGCEA_DSM_CNTLB 0x070a
+#define regGCEA_DSM_CNTLB_BASE_IDX 0
+#define regGCEA_DSM_CNTL2 0x070b
+#define regGCEA_DSM_CNTL2_BASE_IDX 0
+#define regGCEA_DSM_CNTL2A 0x070c
+#define regGCEA_DSM_CNTL2A_BASE_IDX 0
+#define regGCEA_DSM_CNTL2B 0x070d
+#define regGCEA_DSM_CNTL2B_BASE_IDX 0
+#define regGCEA_TCC_XBR_CREDITS 0x070e
+#define regGCEA_TCC_XBR_CREDITS_BASE_IDX 0
+#define regGCEA_TCC_XBR_MAXBURST 0x070f
+#define regGCEA_TCC_XBR_MAXBURST_BASE_IDX 0
+#define regGCEA_PROBE_CNTL 0x0710
+#define regGCEA_PROBE_CNTL_BASE_IDX 0
+#define regGCEA_PROBE_MAP 0x0711
+#define regGCEA_PROBE_MAP_BASE_IDX 0
+#define regGCEA_ERR_STATUS 0x0712
+#define regGCEA_ERR_STATUS_BASE_IDX 0
+#define regGCEA_MISC2 0x0713
+#define regGCEA_MISC2_BASE_IDX 0
+#define regGCEA_DRAM_BANK_ARB 0x0714
+#define regGCEA_DRAM_BANK_ARB_BASE_IDX 0
+#define regGCEA_ADDRDEC_SELECT 0x071a
+#define regGCEA_ADDRDEC_SELECT_BASE_IDX 0
+#define regGCEA_EDC_CNT3 0x071b
+#define regGCEA_EDC_CNT3_BASE_IDX 0
+
+// addressBlock: gc_ea_pwrdec
+// base address: 0x3c000
+#define regGCEA_CGTT_CLK_CTRL 0x50c4
+#define regGCEA_CGTT_CLK_CTRL_BASE_IDX 1
+
+
+// addressBlock: gc_gccacdec
+// base address: 0xca10
+#define regGC_CAC_CTRL_1 0x1284
+#define regGC_CAC_CTRL_1_BASE_IDX 0
+#define regGC_CAC_CTRL_2 0x1285
+#define regGC_CAC_CTRL_2_BASE_IDX 0
+#define regGC_CAC_INDEX_AUTO_INCR_EN 0x1286
+#define regGC_CAC_INDEX_AUTO_INCR_EN_BASE_IDX 0
+#define regGC_CAC_AGGR_LOWER 0x1287
+#define regGC_CAC_AGGR_LOWER_BASE_IDX 0
+#define regGC_CAC_AGGR_UPPER 0x1288
+#define regGC_CAC_AGGR_UPPER_BASE_IDX 0
+#define regGC_EDC_PERF_COUNTER 0x1289
+#define regGC_EDC_PERF_COUNTER_BASE_IDX 0
+#define regPCC_PERF_COUNTER 0x128a
+#define regPCC_PERF_COUNTER_BASE_IDX 0
+#define regGC_CAC_SOFT_CTRL 0x128d
+#define regGC_CAC_SOFT_CTRL_BASE_IDX 0
+#define regGC_DIDT_CTRL0 0x128e
+#define regGC_DIDT_CTRL0_BASE_IDX 0
+#define regGC_DIDT_CTRL1 0x128f
+#define regGC_DIDT_CTRL1_BASE_IDX 0
+#define regGC_DIDT_CTRL2 0x1290
+#define regGC_DIDT_CTRL2_BASE_IDX 0
+#define regGC_DIDT_WEIGHT 0x1291
+#define regGC_DIDT_WEIGHT_BASE_IDX 0
+#define regGC_THROTTLE_CTRL1 0x1292
+#define regGC_THROTTLE_CTRL1_BASE_IDX 0
+#define regGC_EDC_CTRL 0x1293
+#define regGC_EDC_CTRL_BASE_IDX 0
+#define regGC_EDC_THRESHOLD 0x1294
+#define regGC_EDC_THRESHOLD_BASE_IDX 0
+#define regGC_EDC_STATUS 0x1295
+#define regGC_EDC_STATUS_BASE_IDX 0
+#define regGC_EDC_OVERFLOW 0x1296
+#define regGC_EDC_OVERFLOW_BASE_IDX 0
+#define regGC_EDC_ROLLING_POWER_DELTA 0x1297
+#define regGC_EDC_ROLLING_POWER_DELTA_BASE_IDX 0
+#define regGC_EDC_CTRL1 0x1298
+#define regGC_EDC_CTRL1_BASE_IDX 0
+#define regGC_THROTTLE_CTRL2 0x1299
+#define regGC_THROTTLE_CTRL2_BASE_IDX 0
+#define regPWRBRK_PERF_COUNTER 0x129a
+#define regPWRBRK_PERF_COUNTER_BASE_IDX 0
+#define regGC_THROTTLE_CTRL 0x129b
+#define regGC_THROTTLE_CTRL_BASE_IDX 0
+#define regGC_CAC_IND_INDEX 0x129c
+#define regGC_CAC_IND_INDEX_BASE_IDX 0
+#define regGC_CAC_IND_DATA 0x129d
+#define regGC_CAC_IND_DATA_BASE_IDX 0
+#define regSE_CAC_IND_INDEX 0x129e
+#define regSE_CAC_IND_INDEX_BASE_IDX 0
+#define regSE_CAC_IND_DATA 0x129f
+#define regSE_CAC_IND_DATA_BASE_IDX 0
+
+
+// addressBlock: gc_gdsdec
+// base address: 0x9700
+#define regGDS_CONFIG 0x05c0
+#define regGDS_CONFIG_BASE_IDX 0
+#define regGDS_CNTL_STATUS 0x05c1
+#define regGDS_CNTL_STATUS_BASE_IDX 0
+#define regGDS_ENHANCE2 0x05c2
+#define regGDS_ENHANCE2_BASE_IDX 0
+#define regGDS_PROTECTION_FAULT 0x05c3
+#define regGDS_PROTECTION_FAULT_BASE_IDX 0
+#define regGDS_VM_PROTECTION_FAULT 0x05c4
+#define regGDS_VM_PROTECTION_FAULT_BASE_IDX 0
+#define regGDS_EDC_CNT 0x05c5
+#define regGDS_EDC_CNT_BASE_IDX 0
+#define regGDS_EDC_GRBM_CNT 0x05c6
+#define regGDS_EDC_GRBM_CNT_BASE_IDX 0
+#define regGDS_EDC_OA_DED 0x05c7
+#define regGDS_EDC_OA_DED_BASE_IDX 0
+#define regGDS_DSM_CNTL 0x05ca
+#define regGDS_DSM_CNTL_BASE_IDX 0
+#define regGDS_EDC_OA_PHY_CNT 0x05cb
+#define regGDS_EDC_OA_PHY_CNT_BASE_IDX 0
+#define regGDS_EDC_OA_PIPE_CNT 0x05cc
+#define regGDS_EDC_OA_PIPE_CNT_BASE_IDX 0
+#define regGDS_DSM_CNTL2 0x05cd
+#define regGDS_DSM_CNTL2_BASE_IDX 0
+#define regGDS_WD_GDS_CSB 0x05ce
+#define regGDS_WD_GDS_CSB_BASE_IDX 0
+
+
+// addressBlock: gc_gdspdec
+// base address: 0xcc00
+#define regGDS_VMID0_BASE 0x1300
+#define regGDS_VMID0_BASE_BASE_IDX 0
+#define regGDS_VMID0_SIZE 0x1301
+#define regGDS_VMID0_SIZE_BASE_IDX 0
+#define regGDS_VMID1_BASE 0x1302
+#define regGDS_VMID1_BASE_BASE_IDX 0
+#define regGDS_VMID1_SIZE 0x1303
+#define regGDS_VMID1_SIZE_BASE_IDX 0
+#define regGDS_VMID2_BASE 0x1304
+#define regGDS_VMID2_BASE_BASE_IDX 0
+#define regGDS_VMID2_SIZE 0x1305
+#define regGDS_VMID2_SIZE_BASE_IDX 0
+#define regGDS_VMID3_BASE 0x1306
+#define regGDS_VMID3_BASE_BASE_IDX 0
+#define regGDS_VMID3_SIZE 0x1307
+#define regGDS_VMID3_SIZE_BASE_IDX 0
+#define regGDS_VMID4_BASE 0x1308
+#define regGDS_VMID4_BASE_BASE_IDX 0
+#define regGDS_VMID4_SIZE 0x1309
+#define regGDS_VMID4_SIZE_BASE_IDX 0
+#define regGDS_VMID5_BASE 0x130a
+#define regGDS_VMID5_BASE_BASE_IDX 0
+#define regGDS_VMID5_SIZE 0x130b
+#define regGDS_VMID5_SIZE_BASE_IDX 0
+#define regGDS_VMID6_BASE 0x130c
+#define regGDS_VMID6_BASE_BASE_IDX 0
+#define regGDS_VMID6_SIZE 0x130d
+#define regGDS_VMID6_SIZE_BASE_IDX 0
+#define regGDS_VMID7_BASE 0x130e
+#define regGDS_VMID7_BASE_BASE_IDX 0
+#define regGDS_VMID7_SIZE 0x130f
+#define regGDS_VMID7_SIZE_BASE_IDX 0
+#define regGDS_VMID8_BASE 0x1310
+#define regGDS_VMID8_BASE_BASE_IDX 0
+#define regGDS_VMID8_SIZE 0x1311
+#define regGDS_VMID8_SIZE_BASE_IDX 0
+#define regGDS_VMID9_BASE 0x1312
+#define regGDS_VMID9_BASE_BASE_IDX 0
+#define regGDS_VMID9_SIZE 0x1313
+#define regGDS_VMID9_SIZE_BASE_IDX 0
+#define regGDS_VMID10_BASE 0x1314
+#define regGDS_VMID10_BASE_BASE_IDX 0
+#define regGDS_VMID10_SIZE 0x1315
+#define regGDS_VMID10_SIZE_BASE_IDX 0
+#define regGDS_VMID11_BASE 0x1316
+#define regGDS_VMID11_BASE_BASE_IDX 0
+#define regGDS_VMID11_SIZE 0x1317
+#define regGDS_VMID11_SIZE_BASE_IDX 0
+#define regGDS_VMID12_BASE 0x1318
+#define regGDS_VMID12_BASE_BASE_IDX 0
+#define regGDS_VMID12_SIZE 0x1319
+#define regGDS_VMID12_SIZE_BASE_IDX 0
+#define regGDS_VMID13_BASE 0x131a
+#define regGDS_VMID13_BASE_BASE_IDX 0
+#define regGDS_VMID13_SIZE 0x131b
+#define regGDS_VMID13_SIZE_BASE_IDX 0
+#define regGDS_VMID14_BASE 0x131c
+#define regGDS_VMID14_BASE_BASE_IDX 0
+#define regGDS_VMID14_SIZE 0x131d
+#define regGDS_VMID14_SIZE_BASE_IDX 0
+#define regGDS_VMID15_BASE 0x131e
+#define regGDS_VMID15_BASE_BASE_IDX 0
+#define regGDS_VMID15_SIZE 0x131f
+#define regGDS_VMID15_SIZE_BASE_IDX 0
+#define regGDS_GWS_VMID0 0x1320
+#define regGDS_GWS_VMID0_BASE_IDX 0
+#define regGDS_GWS_VMID1 0x1321
+#define regGDS_GWS_VMID1_BASE_IDX 0
+#define regGDS_GWS_VMID2 0x1322
+#define regGDS_GWS_VMID2_BASE_IDX 0
+#define regGDS_GWS_VMID3 0x1323
+#define regGDS_GWS_VMID3_BASE_IDX 0
+#define regGDS_GWS_VMID4 0x1324
+#define regGDS_GWS_VMID4_BASE_IDX 0
+#define regGDS_GWS_VMID5 0x1325
+#define regGDS_GWS_VMID5_BASE_IDX 0
+#define regGDS_GWS_VMID6 0x1326
+#define regGDS_GWS_VMID6_BASE_IDX 0
+#define regGDS_GWS_VMID7 0x1327
+#define regGDS_GWS_VMID7_BASE_IDX 0
+#define regGDS_GWS_VMID8 0x1328
+#define regGDS_GWS_VMID8_BASE_IDX 0
+#define regGDS_GWS_VMID9 0x1329
+#define regGDS_GWS_VMID9_BASE_IDX 0
+#define regGDS_GWS_VMID10 0x132a
+#define regGDS_GWS_VMID10_BASE_IDX 0
+#define regGDS_GWS_VMID11 0x132b
+#define regGDS_GWS_VMID11_BASE_IDX 0
+#define regGDS_GWS_VMID12 0x132c
+#define regGDS_GWS_VMID12_BASE_IDX 0
+#define regGDS_GWS_VMID13 0x132d
+#define regGDS_GWS_VMID13_BASE_IDX 0
+#define regGDS_GWS_VMID14 0x132e
+#define regGDS_GWS_VMID14_BASE_IDX 0
+#define regGDS_GWS_VMID15 0x132f
+#define regGDS_GWS_VMID15_BASE_IDX 0
+#define regGDS_OA_VMID0 0x1330
+#define regGDS_OA_VMID0_BASE_IDX 0
+#define regGDS_OA_VMID1 0x1331
+#define regGDS_OA_VMID1_BASE_IDX 0
+#define regGDS_OA_VMID2 0x1332
+#define regGDS_OA_VMID2_BASE_IDX 0
+#define regGDS_OA_VMID3 0x1333
+#define regGDS_OA_VMID3_BASE_IDX 0
+#define regGDS_OA_VMID4 0x1334
+#define regGDS_OA_VMID4_BASE_IDX 0
+#define regGDS_OA_VMID5 0x1335
+#define regGDS_OA_VMID5_BASE_IDX 0
+#define regGDS_OA_VMID6 0x1336
+#define regGDS_OA_VMID6_BASE_IDX 0
+#define regGDS_OA_VMID7 0x1337
+#define regGDS_OA_VMID7_BASE_IDX 0
+#define regGDS_OA_VMID8 0x1338
+#define regGDS_OA_VMID8_BASE_IDX 0
+#define regGDS_OA_VMID9 0x1339
+#define regGDS_OA_VMID9_BASE_IDX 0
+#define regGDS_OA_VMID10 0x133a
+#define regGDS_OA_VMID10_BASE_IDX 0
+#define regGDS_OA_VMID11 0x133b
+#define regGDS_OA_VMID11_BASE_IDX 0
+#define regGDS_OA_VMID12 0x133c
+#define regGDS_OA_VMID12_BASE_IDX 0
+#define regGDS_OA_VMID13 0x133d
+#define regGDS_OA_VMID13_BASE_IDX 0
+#define regGDS_OA_VMID14 0x133e
+#define regGDS_OA_VMID14_BASE_IDX 0
+#define regGDS_OA_VMID15 0x133f
+#define regGDS_OA_VMID15_BASE_IDX 0
+#define regGDS_GWS_RESET0 0x1344
+#define regGDS_GWS_RESET0_BASE_IDX 0
+#define regGDS_GWS_RESET1 0x1345
+#define regGDS_GWS_RESET1_BASE_IDX 0
+#define regGDS_GWS_RESOURCE_RESET 0x1346
+#define regGDS_GWS_RESOURCE_RESET_BASE_IDX 0
+#define regGDS_COMPUTE_MAX_WAVE_ID 0x1348
+#define regGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX 0
+#define regGDS_OA_RESET_MASK 0x1349
+#define regGDS_OA_RESET_MASK_BASE_IDX 0
+#define regGDS_OA_RESET 0x134a
+#define regGDS_OA_RESET_BASE_IDX 0
+#define regGDS_ENHANCE 0x134b
+#define regGDS_ENHANCE_BASE_IDX 0
+#define regGDS_OA_CGPG_RESTORE 0x134c
+#define regGDS_OA_CGPG_RESTORE_BASE_IDX 0
+#define regGDS_CS_CTXSW_STATUS 0x134d
+#define regGDS_CS_CTXSW_STATUS_BASE_IDX 0
+#define regGDS_CS_CTXSW_CNT0 0x134e
+#define regGDS_CS_CTXSW_CNT0_BASE_IDX 0
+#define regGDS_CS_CTXSW_CNT1 0x134f
+#define regGDS_CS_CTXSW_CNT1_BASE_IDX 0
+#define regGDS_CS_CTXSW_CNT2 0x1350
+#define regGDS_CS_CTXSW_CNT2_BASE_IDX 0
+#define regGDS_CS_CTXSW_CNT3 0x1351
+#define regGDS_CS_CTXSW_CNT3_BASE_IDX 0
+#define regGDS_GFX_CTXSW_STATUS 0x1352
+#define regGDS_GFX_CTXSW_STATUS_BASE_IDX 0
+#define regGDS_VS_CTXSW_CNT0 0x1353
+#define regGDS_VS_CTXSW_CNT0_BASE_IDX 0
+#define regGDS_VS_CTXSW_CNT1 0x1354
+#define regGDS_VS_CTXSW_CNT1_BASE_IDX 0
+#define regGDS_VS_CTXSW_CNT2 0x1355
+#define regGDS_VS_CTXSW_CNT2_BASE_IDX 0
+#define regGDS_VS_CTXSW_CNT3 0x1356
+#define regGDS_VS_CTXSW_CNT3_BASE_IDX 0
+#define regGDS_PS0_CTXSW_CNT0 0x1357
+#define regGDS_PS0_CTXSW_CNT0_BASE_IDX 0
+#define regGDS_PS0_CTXSW_CNT1 0x1358
+#define regGDS_PS0_CTXSW_CNT1_BASE_IDX 0
+#define regGDS_PS0_CTXSW_CNT2 0x1359
+#define regGDS_PS0_CTXSW_CNT2_BASE_IDX 0
+#define regGDS_PS0_CTXSW_CNT3 0x135a
+#define regGDS_PS0_CTXSW_CNT3_BASE_IDX 0
+#define regGDS_PS1_CTXSW_CNT0 0x135b
+#define regGDS_PS1_CTXSW_CNT0_BASE_IDX 0
+#define regGDS_PS1_CTXSW_CNT1 0x135c
+#define regGDS_PS1_CTXSW_CNT1_BASE_IDX 0
+#define regGDS_PS1_CTXSW_CNT2 0x135d
+#define regGDS_PS1_CTXSW_CNT2_BASE_IDX 0
+#define regGDS_PS1_CTXSW_CNT3 0x135e
+#define regGDS_PS1_CTXSW_CNT3_BASE_IDX 0
+#define regGDS_PS2_CTXSW_CNT0 0x135f
+#define regGDS_PS2_CTXSW_CNT0_BASE_IDX 0
+#define regGDS_PS2_CTXSW_CNT1 0x1360
+#define regGDS_PS2_CTXSW_CNT1_BASE_IDX 0
+#define regGDS_PS2_CTXSW_CNT2 0x1361
+#define regGDS_PS2_CTXSW_CNT2_BASE_IDX 0
+#define regGDS_PS2_CTXSW_CNT3 0x1362
+#define regGDS_PS2_CTXSW_CNT3_BASE_IDX 0
+#define regGDS_PS3_CTXSW_CNT0 0x1363
+#define regGDS_PS3_CTXSW_CNT0_BASE_IDX 0
+#define regGDS_PS3_CTXSW_CNT1 0x1364
+#define regGDS_PS3_CTXSW_CNT1_BASE_IDX 0
+#define regGDS_PS3_CTXSW_CNT2 0x1365
+#define regGDS_PS3_CTXSW_CNT2_BASE_IDX 0
+#define regGDS_PS3_CTXSW_CNT3 0x1366
+#define regGDS_PS3_CTXSW_CNT3_BASE_IDX 0
+#define regGDS_PS4_CTXSW_CNT0 0x1367
+#define regGDS_PS4_CTXSW_CNT0_BASE_IDX 0
+#define regGDS_PS4_CTXSW_CNT1 0x1368
+#define regGDS_PS4_CTXSW_CNT1_BASE_IDX 0
+#define regGDS_PS4_CTXSW_CNT2 0x1369
+#define regGDS_PS4_CTXSW_CNT2_BASE_IDX 0
+#define regGDS_PS4_CTXSW_CNT3 0x136a
+#define regGDS_PS4_CTXSW_CNT3_BASE_IDX 0
+#define regGDS_PS5_CTXSW_CNT0 0x136b
+#define regGDS_PS5_CTXSW_CNT0_BASE_IDX 0
+#define regGDS_PS5_CTXSW_CNT1 0x136c
+#define regGDS_PS5_CTXSW_CNT1_BASE_IDX 0
+#define regGDS_PS5_CTXSW_CNT2 0x136d
+#define regGDS_PS5_CTXSW_CNT2_BASE_IDX 0
+#define regGDS_PS5_CTXSW_CNT3 0x136e
+#define regGDS_PS5_CTXSW_CNT3_BASE_IDX 0
+#define regGDS_PS6_CTXSW_CNT0 0x136f
+#define regGDS_PS6_CTXSW_CNT0_BASE_IDX 0
+#define regGDS_PS6_CTXSW_CNT1 0x1370
+#define regGDS_PS6_CTXSW_CNT1_BASE_IDX 0
+#define regGDS_PS6_CTXSW_CNT2 0x1371
+#define regGDS_PS6_CTXSW_CNT2_BASE_IDX 0
+#define regGDS_PS6_CTXSW_CNT3 0x1372
+#define regGDS_PS6_CTXSW_CNT3_BASE_IDX 0
+#define regGDS_PS7_CTXSW_CNT0 0x1373
+#define regGDS_PS7_CTXSW_CNT0_BASE_IDX 0
+#define regGDS_PS7_CTXSW_CNT1 0x1374
+#define regGDS_PS7_CTXSW_CNT1_BASE_IDX 0
+#define regGDS_PS7_CTXSW_CNT2 0x1375
+#define regGDS_PS7_CTXSW_CNT2_BASE_IDX 0
+#define regGDS_PS7_CTXSW_CNT3 0x1376
+#define regGDS_PS7_CTXSW_CNT3_BASE_IDX 0
+#define regGDS_GS_CTXSW_CNT0 0x1377
+#define regGDS_GS_CTXSW_CNT0_BASE_IDX 0
+#define regGDS_GS_CTXSW_CNT1 0x1378
+#define regGDS_GS_CTXSW_CNT1_BASE_IDX 0
+#define regGDS_GS_CTXSW_CNT2 0x1379
+#define regGDS_GS_CTXSW_CNT2_BASE_IDX 0
+#define regGDS_GS_CTXSW_CNT3 0x137a
+#define regGDS_GS_CTXSW_CNT3_BASE_IDX 0
+
+
+// addressBlock: gc_gfxdec0
+// base address: 0x28000
+#define regDB_RENDER_CONTROL 0x0000
+#define regDB_RENDER_CONTROL_BASE_IDX 1
+#define regDB_COUNT_CONTROL 0x0001
+#define regDB_COUNT_CONTROL_BASE_IDX 1
+#define regDB_DEPTH_VIEW 0x0002
+#define regDB_DEPTH_VIEW_BASE_IDX 1
+#define regDB_RENDER_OVERRIDE 0x0003
+#define regDB_RENDER_OVERRIDE_BASE_IDX 1
+#define regDB_RENDER_OVERRIDE2 0x0004
+#define regDB_RENDER_OVERRIDE2_BASE_IDX 1
+#define regDB_HTILE_DATA_BASE 0x0005
+#define regDB_HTILE_DATA_BASE_BASE_IDX 1
+#define regDB_HTILE_DATA_BASE_HI 0x0006
+#define regDB_HTILE_DATA_BASE_HI_BASE_IDX 1
+#define regDB_DEPTH_SIZE 0x0007
+#define regDB_DEPTH_SIZE_BASE_IDX 1
+#define regDB_DEPTH_BOUNDS_MIN 0x0008
+#define regDB_DEPTH_BOUNDS_MIN_BASE_IDX 1
+#define regDB_DEPTH_BOUNDS_MAX 0x0009
+#define regDB_DEPTH_BOUNDS_MAX_BASE_IDX 1
+#define regDB_STENCIL_CLEAR 0x000a
+#define regDB_STENCIL_CLEAR_BASE_IDX 1
+#define regDB_DEPTH_CLEAR 0x000b
+#define regDB_DEPTH_CLEAR_BASE_IDX 1
+#define regPA_SC_SCREEN_SCISSOR_TL 0x000c
+#define regPA_SC_SCREEN_SCISSOR_TL_BASE_IDX 1
+#define regPA_SC_SCREEN_SCISSOR_BR 0x000d
+#define regPA_SC_SCREEN_SCISSOR_BR_BASE_IDX 1
+#define regDB_Z_INFO 0x000e
+#define regDB_Z_INFO_BASE_IDX 1
+#define regDB_STENCIL_INFO 0x000f
+#define regDB_STENCIL_INFO_BASE_IDX 1
+#define regDB_Z_READ_BASE 0x0010
+#define regDB_Z_READ_BASE_BASE_IDX 1
+#define regDB_Z_READ_BASE_HI 0x0011
+#define regDB_Z_READ_BASE_HI_BASE_IDX 1
+#define regDB_STENCIL_READ_BASE 0x0012
+#define regDB_STENCIL_READ_BASE_BASE_IDX 1
+#define regDB_STENCIL_READ_BASE_HI 0x0013
+#define regDB_STENCIL_READ_BASE_HI_BASE_IDX 1
+#define regDB_Z_WRITE_BASE 0x0014
+#define regDB_Z_WRITE_BASE_BASE_IDX 1
+#define regDB_Z_WRITE_BASE_HI 0x0015
+#define regDB_Z_WRITE_BASE_HI_BASE_IDX 1
+#define regDB_STENCIL_WRITE_BASE 0x0016
+#define regDB_STENCIL_WRITE_BASE_BASE_IDX 1
+#define regDB_STENCIL_WRITE_BASE_HI 0x0017
+#define regDB_STENCIL_WRITE_BASE_HI_BASE_IDX 1
+#define regDB_DFSM_CONTROL 0x0018
+#define regDB_DFSM_CONTROL_BASE_IDX 1
+#define regDB_Z_INFO2 0x001a
+#define regDB_Z_INFO2_BASE_IDX 1
+#define regDB_STENCIL_INFO2 0x001b
+#define regDB_STENCIL_INFO2_BASE_IDX 1
+#define regCOHER_DEST_BASE_HI_0 0x007a
+#define regCOHER_DEST_BASE_HI_0_BASE_IDX 1
+#define regCOHER_DEST_BASE_HI_1 0x007b
+#define regCOHER_DEST_BASE_HI_1_BASE_IDX 1
+#define regCOHER_DEST_BASE_HI_2 0x007c
+#define regCOHER_DEST_BASE_HI_2_BASE_IDX 1
+#define regCOHER_DEST_BASE_HI_3 0x007d
+#define regCOHER_DEST_BASE_HI_3_BASE_IDX 1
+#define regCOHER_DEST_BASE_2 0x007e
+#define regCOHER_DEST_BASE_2_BASE_IDX 1
+#define regCOHER_DEST_BASE_3 0x007f
+#define regCOHER_DEST_BASE_3_BASE_IDX 1
+#define regPA_SC_WINDOW_OFFSET 0x0080
+#define regPA_SC_WINDOW_OFFSET_BASE_IDX 1
+#define regPA_SC_WINDOW_SCISSOR_TL 0x0081
+#define regPA_SC_WINDOW_SCISSOR_TL_BASE_IDX 1
+#define regPA_SC_WINDOW_SCISSOR_BR 0x0082
+#define regPA_SC_WINDOW_SCISSOR_BR_BASE_IDX 1
+#define regPA_SC_CLIPRECT_RULE 0x0083
+#define regPA_SC_CLIPRECT_RULE_BASE_IDX 1
+#define regPA_SC_CLIPRECT_0_TL 0x0084
+#define regPA_SC_CLIPRECT_0_TL_BASE_IDX 1
+#define regPA_SC_CLIPRECT_0_BR 0x0085
+#define regPA_SC_CLIPRECT_0_BR_BASE_IDX 1
+#define regPA_SC_CLIPRECT_1_TL 0x0086
+#define regPA_SC_CLIPRECT_1_TL_BASE_IDX 1
+#define regPA_SC_CLIPRECT_1_BR 0x0087
+#define regPA_SC_CLIPRECT_1_BR_BASE_IDX 1
+#define regPA_SC_CLIPRECT_2_TL 0x0088
+#define regPA_SC_CLIPRECT_2_TL_BASE_IDX 1
+#define regPA_SC_CLIPRECT_2_BR 0x0089
+#define regPA_SC_CLIPRECT_2_BR_BASE_IDX 1
+#define regPA_SC_CLIPRECT_3_TL 0x008a
+#define regPA_SC_CLIPRECT_3_TL_BASE_IDX 1
+#define regPA_SC_CLIPRECT_3_BR 0x008b
+#define regPA_SC_CLIPRECT_3_BR_BASE_IDX 1
+#define regPA_SC_EDGERULE 0x008c
+#define regPA_SC_EDGERULE_BASE_IDX 1
+#define regPA_SU_HARDWARE_SCREEN_OFFSET 0x008d
+#define regPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX 1
+#define regCB_TARGET_MASK 0x008e
+#define regCB_TARGET_MASK_BASE_IDX 1
+#define regCB_SHADER_MASK 0x008f
+#define regCB_SHADER_MASK_BASE_IDX 1
+#define regPA_SC_GENERIC_SCISSOR_TL 0x0090
+#define regPA_SC_GENERIC_SCISSOR_TL_BASE_IDX 1
+#define regPA_SC_GENERIC_SCISSOR_BR 0x0091
+#define regPA_SC_GENERIC_SCISSOR_BR_BASE_IDX 1
+#define regCOHER_DEST_BASE_0 0x0092
+#define regCOHER_DEST_BASE_0_BASE_IDX 1
+#define regCOHER_DEST_BASE_1 0x0093
+#define regCOHER_DEST_BASE_1_BASE_IDX 1
+#define regPA_SC_VPORT_SCISSOR_0_TL 0x0094
+#define regPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX 1
+#define regPA_SC_VPORT_SCISSOR_0_BR 0x0095
+#define regPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX 1
+#define regPA_SC_VPORT_SCISSOR_1_TL 0x0096
+#define regPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX 1
+#define regPA_SC_VPORT_SCISSOR_1_BR 0x0097
+#define regPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX 1
+#define regPA_SC_VPORT_SCISSOR_2_TL 0x0098
+#define regPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX 1
+#define regPA_SC_VPORT_SCISSOR_2_BR 0x0099
+#define regPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX 1
+#define regPA_SC_VPORT_SCISSOR_3_TL 0x009a
+#define regPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX 1
+#define regPA_SC_VPORT_SCISSOR_3_BR 0x009b
+#define regPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX 1
+#define regPA_SC_VPORT_SCISSOR_4_TL 0x009c
+#define regPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX 1
+#define regPA_SC_VPORT_SCISSOR_4_BR 0x009d
+#define regPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX 1
+#define regPA_SC_VPORT_SCISSOR_5_TL 0x009e
+#define regPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX 1
+#define regPA_SC_VPORT_SCISSOR_5_BR 0x009f
+#define regPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX 1
+#define regPA_SC_VPORT_SCISSOR_6_TL 0x00a0
+#define regPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX 1
+#define regPA_SC_VPORT_SCISSOR_6_BR 0x00a1
+#define regPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX 1
+#define regPA_SC_VPORT_SCISSOR_7_TL 0x00a2
+#define regPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX 1
+#define regPA_SC_VPORT_SCISSOR_7_BR 0x00a3
+#define regPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX 1
+#define regPA_SC_VPORT_SCISSOR_8_TL 0x00a4
+#define regPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX 1
+#define regPA_SC_VPORT_SCISSOR_8_BR 0x00a5
+#define regPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX 1
+#define regPA_SC_VPORT_SCISSOR_9_TL 0x00a6
+#define regPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX 1
+#define regPA_SC_VPORT_SCISSOR_9_BR 0x00a7
+#define regPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX 1
+#define regPA_SC_VPORT_SCISSOR_10_TL 0x00a8
+#define regPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX 1
+#define regPA_SC_VPORT_SCISSOR_10_BR 0x00a9
+#define regPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX 1
+#define regPA_SC_VPORT_SCISSOR_11_TL 0x00aa
+#define regPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX 1
+#define regPA_SC_VPORT_SCISSOR_11_BR 0x00ab
+#define regPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX 1
+#define regPA_SC_VPORT_SCISSOR_12_TL 0x00ac
+#define regPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX 1
+#define regPA_SC_VPORT_SCISSOR_12_BR 0x00ad
+#define regPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX 1
+#define regPA_SC_VPORT_SCISSOR_13_TL 0x00ae
+#define regPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX 1
+#define regPA_SC_VPORT_SCISSOR_13_BR 0x00af
+#define regPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX 1
+#define regPA_SC_VPORT_SCISSOR_14_TL 0x00b0
+#define regPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX 1
+#define regPA_SC_VPORT_SCISSOR_14_BR 0x00b1
+#define regPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX 1
+#define regPA_SC_VPORT_SCISSOR_15_TL 0x00b2
+#define regPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX 1
+#define regPA_SC_VPORT_SCISSOR_15_BR 0x00b3
+#define regPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX 1
+#define regPA_SC_VPORT_ZMIN_0 0x00b4
+#define regPA_SC_VPORT_ZMIN_0_BASE_IDX 1
+#define regPA_SC_VPORT_ZMAX_0 0x00b5
+#define regPA_SC_VPORT_ZMAX_0_BASE_IDX 1
+#define regPA_SC_VPORT_ZMIN_1 0x00b6
+#define regPA_SC_VPORT_ZMIN_1_BASE_IDX 1
+#define regPA_SC_VPORT_ZMAX_1 0x00b7
+#define regPA_SC_VPORT_ZMAX_1_BASE_IDX 1
+#define regPA_SC_VPORT_ZMIN_2 0x00b8
+#define regPA_SC_VPORT_ZMIN_2_BASE_IDX 1
+#define regPA_SC_VPORT_ZMAX_2 0x00b9
+#define regPA_SC_VPORT_ZMAX_2_BASE_IDX 1
+#define regPA_SC_VPORT_ZMIN_3 0x00ba
+#define regPA_SC_VPORT_ZMIN_3_BASE_IDX 1
+#define regPA_SC_VPORT_ZMAX_3 0x00bb
+#define regPA_SC_VPORT_ZMAX_3_BASE_IDX 1
+#define regPA_SC_VPORT_ZMIN_4 0x00bc
+#define regPA_SC_VPORT_ZMIN_4_BASE_IDX 1
+#define regPA_SC_VPORT_ZMAX_4 0x00bd
+#define regPA_SC_VPORT_ZMAX_4_BASE_IDX 1
+#define regPA_SC_VPORT_ZMIN_5 0x00be
+#define regPA_SC_VPORT_ZMIN_5_BASE_IDX 1
+#define regPA_SC_VPORT_ZMAX_5 0x00bf
+#define regPA_SC_VPORT_ZMAX_5_BASE_IDX 1
+#define regPA_SC_VPORT_ZMIN_6 0x00c0
+#define regPA_SC_VPORT_ZMIN_6_BASE_IDX 1
+#define regPA_SC_VPORT_ZMAX_6 0x00c1
+#define regPA_SC_VPORT_ZMAX_6_BASE_IDX 1
+#define regPA_SC_VPORT_ZMIN_7 0x00c2
+#define regPA_SC_VPORT_ZMIN_7_BASE_IDX 1
+#define regPA_SC_VPORT_ZMAX_7 0x00c3
+#define regPA_SC_VPORT_ZMAX_7_BASE_IDX 1
+#define regPA_SC_VPORT_ZMIN_8 0x00c4
+#define regPA_SC_VPORT_ZMIN_8_BASE_IDX 1
+#define regPA_SC_VPORT_ZMAX_8 0x00c5
+#define regPA_SC_VPORT_ZMAX_8_BASE_IDX 1
+#define regPA_SC_VPORT_ZMIN_9 0x00c6
+#define regPA_SC_VPORT_ZMIN_9_BASE_IDX 1
+#define regPA_SC_VPORT_ZMAX_9 0x00c7
+#define regPA_SC_VPORT_ZMAX_9_BASE_IDX 1
+#define regPA_SC_VPORT_ZMIN_10 0x00c8
+#define regPA_SC_VPORT_ZMIN_10_BASE_IDX 1
+#define regPA_SC_VPORT_ZMAX_10 0x00c9
+#define regPA_SC_VPORT_ZMAX_10_BASE_IDX 1
+#define regPA_SC_VPORT_ZMIN_11 0x00ca
+#define regPA_SC_VPORT_ZMIN_11_BASE_IDX 1
+#define regPA_SC_VPORT_ZMAX_11 0x00cb
+#define regPA_SC_VPORT_ZMAX_11_BASE_IDX 1
+#define regPA_SC_VPORT_ZMIN_12 0x00cc
+#define regPA_SC_VPORT_ZMIN_12_BASE_IDX 1
+#define regPA_SC_VPORT_ZMAX_12 0x00cd
+#define regPA_SC_VPORT_ZMAX_12_BASE_IDX 1
+#define regPA_SC_VPORT_ZMIN_13 0x00ce
+#define regPA_SC_VPORT_ZMIN_13_BASE_IDX 1
+#define regPA_SC_VPORT_ZMAX_13 0x00cf
+#define regPA_SC_VPORT_ZMAX_13_BASE_IDX 1
+#define regPA_SC_VPORT_ZMIN_14 0x00d0
+#define regPA_SC_VPORT_ZMIN_14_BASE_IDX 1
+#define regPA_SC_VPORT_ZMAX_14 0x00d1
+#define regPA_SC_VPORT_ZMAX_14_BASE_IDX 1
+#define regPA_SC_VPORT_ZMIN_15 0x00d2
+#define regPA_SC_VPORT_ZMIN_15_BASE_IDX 1
+#define regPA_SC_VPORT_ZMAX_15 0x00d3
+#define regPA_SC_VPORT_ZMAX_15_BASE_IDX 1
+#define regPA_SC_RASTER_CONFIG 0x00d4
+#define regPA_SC_RASTER_CONFIG_BASE_IDX 1
+#define regPA_SC_RASTER_CONFIG_1 0x00d5
+#define regPA_SC_RASTER_CONFIG_1_BASE_IDX 1
+#define regPA_SC_SCREEN_EXTENT_CONTROL 0x00d6
+#define regPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX 1
+#define regPA_SC_TILE_STEERING_OVERRIDE 0x00d7
+#define regPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX 1
+#define regCP_PERFMON_CNTX_CNTL 0x00d8
+#define regCP_PERFMON_CNTX_CNTL_BASE_IDX 1
+#define regCP_PIPEID 0x00d9
+#define regCP_PIPEID_BASE_IDX 1
+#define regCP_RINGID 0x00d9
+#define regCP_RINGID_BASE_IDX 1
+#define regCP_VMID 0x00da
+#define regCP_VMID_BASE_IDX 1
+#define regPA_SC_RIGHT_VERT_GRID 0x00e8
+#define regPA_SC_RIGHT_VERT_GRID_BASE_IDX 1
+#define regPA_SC_LEFT_VERT_GRID 0x00e9
+#define regPA_SC_LEFT_VERT_GRID_BASE_IDX 1
+#define regPA_SC_HORIZ_GRID 0x00ea
+#define regPA_SC_HORIZ_GRID_BASE_IDX 1
+#define regVGT_MULTI_PRIM_IB_RESET_INDX 0x0103
+#define regVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX 1
+#define regCB_BLEND_RED 0x0105
+#define regCB_BLEND_RED_BASE_IDX 1
+#define regCB_BLEND_GREEN 0x0106
+#define regCB_BLEND_GREEN_BASE_IDX 1
+#define regCB_BLEND_BLUE 0x0107
+#define regCB_BLEND_BLUE_BASE_IDX 1
+#define regCB_BLEND_ALPHA 0x0108
+#define regCB_BLEND_ALPHA_BASE_IDX 1
+#define regCB_DCC_CONTROL 0x0109
+#define regCB_DCC_CONTROL_BASE_IDX 1
+#define regDB_STENCIL_CONTROL 0x010b
+#define regDB_STENCIL_CONTROL_BASE_IDX 1
+#define regDB_STENCILREFMASK 0x010c
+#define regDB_STENCILREFMASK_BASE_IDX 1
+#define regDB_STENCILREFMASK_BF 0x010d
+#define regDB_STENCILREFMASK_BF_BASE_IDX 1
+#define regPA_CL_VPORT_XSCALE 0x010f
+#define regPA_CL_VPORT_XSCALE_BASE_IDX 1
+#define regPA_CL_VPORT_XOFFSET 0x0110
+#define regPA_CL_VPORT_XOFFSET_BASE_IDX 1
+#define regPA_CL_VPORT_YSCALE 0x0111
+#define regPA_CL_VPORT_YSCALE_BASE_IDX 1
+#define regPA_CL_VPORT_YOFFSET 0x0112
+#define regPA_CL_VPORT_YOFFSET_BASE_IDX 1
+#define regPA_CL_VPORT_ZSCALE 0x0113
+#define regPA_CL_VPORT_ZSCALE_BASE_IDX 1
+#define regPA_CL_VPORT_ZOFFSET 0x0114
+#define regPA_CL_VPORT_ZOFFSET_BASE_IDX 1
+#define regPA_CL_VPORT_XSCALE_1 0x0115
+#define regPA_CL_VPORT_XSCALE_1_BASE_IDX 1
+#define regPA_CL_VPORT_XOFFSET_1 0x0116
+#define regPA_CL_VPORT_XOFFSET_1_BASE_IDX 1
+#define regPA_CL_VPORT_YSCALE_1 0x0117
+#define regPA_CL_VPORT_YSCALE_1_BASE_IDX 1
+#define regPA_CL_VPORT_YOFFSET_1 0x0118
+#define regPA_CL_VPORT_YOFFSET_1_BASE_IDX 1
+#define regPA_CL_VPORT_ZSCALE_1 0x0119
+#define regPA_CL_VPORT_ZSCALE_1_BASE_IDX 1
+#define regPA_CL_VPORT_ZOFFSET_1 0x011a
+#define regPA_CL_VPORT_ZOFFSET_1_BASE_IDX 1
+#define regPA_CL_VPORT_XSCALE_2 0x011b
+#define regPA_CL_VPORT_XSCALE_2_BASE_IDX 1
+#define regPA_CL_VPORT_XOFFSET_2 0x011c
+#define regPA_CL_VPORT_XOFFSET_2_BASE_IDX 1
+#define regPA_CL_VPORT_YSCALE_2 0x011d
+#define regPA_CL_VPORT_YSCALE_2_BASE_IDX 1
+#define regPA_CL_VPORT_YOFFSET_2 0x011e
+#define regPA_CL_VPORT_YOFFSET_2_BASE_IDX 1
+#define regPA_CL_VPORT_ZSCALE_2 0x011f
+#define regPA_CL_VPORT_ZSCALE_2_BASE_IDX 1
+#define regPA_CL_VPORT_ZOFFSET_2 0x0120
+#define regPA_CL_VPORT_ZOFFSET_2_BASE_IDX 1
+#define regPA_CL_VPORT_XSCALE_3 0x0121
+#define regPA_CL_VPORT_XSCALE_3_BASE_IDX 1
+#define regPA_CL_VPORT_XOFFSET_3 0x0122
+#define regPA_CL_VPORT_XOFFSET_3_BASE_IDX 1
+#define regPA_CL_VPORT_YSCALE_3 0x0123
+#define regPA_CL_VPORT_YSCALE_3_BASE_IDX 1
+#define regPA_CL_VPORT_YOFFSET_3 0x0124
+#define regPA_CL_VPORT_YOFFSET_3_BASE_IDX 1
+#define regPA_CL_VPORT_ZSCALE_3 0x0125
+#define regPA_CL_VPORT_ZSCALE_3_BASE_IDX 1
+#define regPA_CL_VPORT_ZOFFSET_3 0x0126
+#define regPA_CL_VPORT_ZOFFSET_3_BASE_IDX 1
+#define regPA_CL_VPORT_XSCALE_4 0x0127
+#define regPA_CL_VPORT_XSCALE_4_BASE_IDX 1
+#define regPA_CL_VPORT_XOFFSET_4 0x0128
+#define regPA_CL_VPORT_XOFFSET_4_BASE_IDX 1
+#define regPA_CL_VPORT_YSCALE_4 0x0129
+#define regPA_CL_VPORT_YSCALE_4_BASE_IDX 1
+#define regPA_CL_VPORT_YOFFSET_4 0x012a
+#define regPA_CL_VPORT_YOFFSET_4_BASE_IDX 1
+#define regPA_CL_VPORT_ZSCALE_4 0x012b
+#define regPA_CL_VPORT_ZSCALE_4_BASE_IDX 1
+#define regPA_CL_VPORT_ZOFFSET_4 0x012c
+#define regPA_CL_VPORT_ZOFFSET_4_BASE_IDX 1
+#define regPA_CL_VPORT_XSCALE_5 0x012d
+#define regPA_CL_VPORT_XSCALE_5_BASE_IDX 1
+#define regPA_CL_VPORT_XOFFSET_5 0x012e
+#define regPA_CL_VPORT_XOFFSET_5_BASE_IDX 1
+#define regPA_CL_VPORT_YSCALE_5 0x012f
+#define regPA_CL_VPORT_YSCALE_5_BASE_IDX 1
+#define regPA_CL_VPORT_YOFFSET_5 0x0130
+#define regPA_CL_VPORT_YOFFSET_5_BASE_IDX 1
+#define regPA_CL_VPORT_ZSCALE_5 0x0131
+#define regPA_CL_VPORT_ZSCALE_5_BASE_IDX 1
+#define regPA_CL_VPORT_ZOFFSET_5 0x0132
+#define regPA_CL_VPORT_ZOFFSET_5_BASE_IDX 1
+#define regPA_CL_VPORT_XSCALE_6 0x0133
+#define regPA_CL_VPORT_XSCALE_6_BASE_IDX 1
+#define regPA_CL_VPORT_XOFFSET_6 0x0134
+#define regPA_CL_VPORT_XOFFSET_6_BASE_IDX 1
+#define regPA_CL_VPORT_YSCALE_6 0x0135
+#define regPA_CL_VPORT_YSCALE_6_BASE_IDX 1
+#define regPA_CL_VPORT_YOFFSET_6 0x0136
+#define regPA_CL_VPORT_YOFFSET_6_BASE_IDX 1
+#define regPA_CL_VPORT_ZSCALE_6 0x0137
+#define regPA_CL_VPORT_ZSCALE_6_BASE_IDX 1
+#define regPA_CL_VPORT_ZOFFSET_6 0x0138
+#define regPA_CL_VPORT_ZOFFSET_6_BASE_IDX 1
+#define regPA_CL_VPORT_XSCALE_7 0x0139
+#define regPA_CL_VPORT_XSCALE_7_BASE_IDX 1
+#define regPA_CL_VPORT_XOFFSET_7 0x013a
+#define regPA_CL_VPORT_XOFFSET_7_BASE_IDX 1
+#define regPA_CL_VPORT_YSCALE_7 0x013b
+#define regPA_CL_VPORT_YSCALE_7_BASE_IDX 1
+#define regPA_CL_VPORT_YOFFSET_7 0x013c
+#define regPA_CL_VPORT_YOFFSET_7_BASE_IDX 1
+#define regPA_CL_VPORT_ZSCALE_7 0x013d
+#define regPA_CL_VPORT_ZSCALE_7_BASE_IDX 1
+#define regPA_CL_VPORT_ZOFFSET_7 0x013e
+#define regPA_CL_VPORT_ZOFFSET_7_BASE_IDX 1
+#define regPA_CL_VPORT_XSCALE_8 0x013f
+#define regPA_CL_VPORT_XSCALE_8_BASE_IDX 1
+#define regPA_CL_VPORT_XOFFSET_8 0x0140
+#define regPA_CL_VPORT_XOFFSET_8_BASE_IDX 1
+#define regPA_CL_VPORT_YSCALE_8 0x0141
+#define regPA_CL_VPORT_YSCALE_8_BASE_IDX 1
+#define regPA_CL_VPORT_YOFFSET_8 0x0142
+#define regPA_CL_VPORT_YOFFSET_8_BASE_IDX 1
+#define regPA_CL_VPORT_ZSCALE_8 0x0143
+#define regPA_CL_VPORT_ZSCALE_8_BASE_IDX 1
+#define regPA_CL_VPORT_ZOFFSET_8 0x0144
+#define regPA_CL_VPORT_ZOFFSET_8_BASE_IDX 1
+#define regPA_CL_VPORT_XSCALE_9 0x0145
+#define regPA_CL_VPORT_XSCALE_9_BASE_IDX 1
+#define regPA_CL_VPORT_XOFFSET_9 0x0146
+#define regPA_CL_VPORT_XOFFSET_9_BASE_IDX 1
+#define regPA_CL_VPORT_YSCALE_9 0x0147
+#define regPA_CL_VPORT_YSCALE_9_BASE_IDX 1
+#define regPA_CL_VPORT_YOFFSET_9 0x0148
+#define regPA_CL_VPORT_YOFFSET_9_BASE_IDX 1
+#define regPA_CL_VPORT_ZSCALE_9 0x0149
+#define regPA_CL_VPORT_ZSCALE_9_BASE_IDX 1
+#define regPA_CL_VPORT_ZOFFSET_9 0x014a
+#define regPA_CL_VPORT_ZOFFSET_9_BASE_IDX 1
+#define regPA_CL_VPORT_XSCALE_10 0x014b
+#define regPA_CL_VPORT_XSCALE_10_BASE_IDX 1
+#define regPA_CL_VPORT_XOFFSET_10 0x014c
+#define regPA_CL_VPORT_XOFFSET_10_BASE_IDX 1
+#define regPA_CL_VPORT_YSCALE_10 0x014d
+#define regPA_CL_VPORT_YSCALE_10_BASE_IDX 1
+#define regPA_CL_VPORT_YOFFSET_10 0x014e
+#define regPA_CL_VPORT_YOFFSET_10_BASE_IDX 1
+#define regPA_CL_VPORT_ZSCALE_10 0x014f
+#define regPA_CL_VPORT_ZSCALE_10_BASE_IDX 1
+#define regPA_CL_VPORT_ZOFFSET_10 0x0150
+#define regPA_CL_VPORT_ZOFFSET_10_BASE_IDX 1
+#define regPA_CL_VPORT_XSCALE_11 0x0151
+#define regPA_CL_VPORT_XSCALE_11_BASE_IDX 1
+#define regPA_CL_VPORT_XOFFSET_11 0x0152
+#define regPA_CL_VPORT_XOFFSET_11_BASE_IDX 1
+#define regPA_CL_VPORT_YSCALE_11 0x0153
+#define regPA_CL_VPORT_YSCALE_11_BASE_IDX 1
+#define regPA_CL_VPORT_YOFFSET_11 0x0154
+#define regPA_CL_VPORT_YOFFSET_11_BASE_IDX 1
+#define regPA_CL_VPORT_ZSCALE_11 0x0155
+#define regPA_CL_VPORT_ZSCALE_11_BASE_IDX 1
+#define regPA_CL_VPORT_ZOFFSET_11 0x0156
+#define regPA_CL_VPORT_ZOFFSET_11_BASE_IDX 1
+#define regPA_CL_VPORT_XSCALE_12 0x0157
+#define regPA_CL_VPORT_XSCALE_12_BASE_IDX 1
+#define regPA_CL_VPORT_XOFFSET_12 0x0158
+#define regPA_CL_VPORT_XOFFSET_12_BASE_IDX 1
+#define regPA_CL_VPORT_YSCALE_12 0x0159
+#define regPA_CL_VPORT_YSCALE_12_BASE_IDX 1
+#define regPA_CL_VPORT_YOFFSET_12 0x015a
+#define regPA_CL_VPORT_YOFFSET_12_BASE_IDX 1
+#define regPA_CL_VPORT_ZSCALE_12 0x015b
+#define regPA_CL_VPORT_ZSCALE_12_BASE_IDX 1
+#define regPA_CL_VPORT_ZOFFSET_12 0x015c
+#define regPA_CL_VPORT_ZOFFSET_12_BASE_IDX 1
+#define regPA_CL_VPORT_XSCALE_13 0x015d
+#define regPA_CL_VPORT_XSCALE_13_BASE_IDX 1
+#define regPA_CL_VPORT_XOFFSET_13 0x015e
+#define regPA_CL_VPORT_XOFFSET_13_BASE_IDX 1
+#define regPA_CL_VPORT_YSCALE_13 0x015f
+#define regPA_CL_VPORT_YSCALE_13_BASE_IDX 1
+#define regPA_CL_VPORT_YOFFSET_13 0x0160
+#define regPA_CL_VPORT_YOFFSET_13_BASE_IDX 1
+#define regPA_CL_VPORT_ZSCALE_13 0x0161
+#define regPA_CL_VPORT_ZSCALE_13_BASE_IDX 1
+#define regPA_CL_VPORT_ZOFFSET_13 0x0162
+#define regPA_CL_VPORT_ZOFFSET_13_BASE_IDX 1
+#define regPA_CL_VPORT_XSCALE_14 0x0163
+#define regPA_CL_VPORT_XSCALE_14_BASE_IDX 1
+#define regPA_CL_VPORT_XOFFSET_14 0x0164
+#define regPA_CL_VPORT_XOFFSET_14_BASE_IDX 1
+#define regPA_CL_VPORT_YSCALE_14 0x0165
+#define regPA_CL_VPORT_YSCALE_14_BASE_IDX 1
+#define regPA_CL_VPORT_YOFFSET_14 0x0166
+#define regPA_CL_VPORT_YOFFSET_14_BASE_IDX 1
+#define regPA_CL_VPORT_ZSCALE_14 0x0167
+#define regPA_CL_VPORT_ZSCALE_14_BASE_IDX 1
+#define regPA_CL_VPORT_ZOFFSET_14 0x0168
+#define regPA_CL_VPORT_ZOFFSET_14_BASE_IDX 1
+#define regPA_CL_VPORT_XSCALE_15 0x0169
+#define regPA_CL_VPORT_XSCALE_15_BASE_IDX 1
+#define regPA_CL_VPORT_XOFFSET_15 0x016a
+#define regPA_CL_VPORT_XOFFSET_15_BASE_IDX 1
+#define regPA_CL_VPORT_YSCALE_15 0x016b
+#define regPA_CL_VPORT_YSCALE_15_BASE_IDX 1
+#define regPA_CL_VPORT_YOFFSET_15 0x016c
+#define regPA_CL_VPORT_YOFFSET_15_BASE_IDX 1
+#define regPA_CL_VPORT_ZSCALE_15 0x016d
+#define regPA_CL_VPORT_ZSCALE_15_BASE_IDX 1
+#define regPA_CL_VPORT_ZOFFSET_15 0x016e
+#define regPA_CL_VPORT_ZOFFSET_15_BASE_IDX 1
+#define regPA_CL_UCP_0_X 0x016f
+#define regPA_CL_UCP_0_X_BASE_IDX 1
+#define regPA_CL_UCP_0_Y 0x0170
+#define regPA_CL_UCP_0_Y_BASE_IDX 1
+#define regPA_CL_UCP_0_Z 0x0171
+#define regPA_CL_UCP_0_Z_BASE_IDX 1
+#define regPA_CL_UCP_0_W 0x0172
+#define regPA_CL_UCP_0_W_BASE_IDX 1
+#define regPA_CL_UCP_1_X 0x0173
+#define regPA_CL_UCP_1_X_BASE_IDX 1
+#define regPA_CL_UCP_1_Y 0x0174
+#define regPA_CL_UCP_1_Y_BASE_IDX 1
+#define regPA_CL_UCP_1_Z 0x0175
+#define regPA_CL_UCP_1_Z_BASE_IDX 1
+#define regPA_CL_UCP_1_W 0x0176
+#define regPA_CL_UCP_1_W_BASE_IDX 1
+#define regPA_CL_UCP_2_X 0x0177
+#define regPA_CL_UCP_2_X_BASE_IDX 1
+#define regPA_CL_UCP_2_Y 0x0178
+#define regPA_CL_UCP_2_Y_BASE_IDX 1
+#define regPA_CL_UCP_2_Z 0x0179
+#define regPA_CL_UCP_2_Z_BASE_IDX 1
+#define regPA_CL_UCP_2_W 0x017a
+#define regPA_CL_UCP_2_W_BASE_IDX 1
+#define regPA_CL_UCP_3_X 0x017b
+#define regPA_CL_UCP_3_X_BASE_IDX 1
+#define regPA_CL_UCP_3_Y 0x017c
+#define regPA_CL_UCP_3_Y_BASE_IDX 1
+#define regPA_CL_UCP_3_Z 0x017d
+#define regPA_CL_UCP_3_Z_BASE_IDX 1
+#define regPA_CL_UCP_3_W 0x017e
+#define regPA_CL_UCP_3_W_BASE_IDX 1
+#define regPA_CL_UCP_4_X 0x017f
+#define regPA_CL_UCP_4_X_BASE_IDX 1
+#define regPA_CL_UCP_4_Y 0x0180
+#define regPA_CL_UCP_4_Y_BASE_IDX 1
+#define regPA_CL_UCP_4_Z 0x0181
+#define regPA_CL_UCP_4_Z_BASE_IDX 1
+#define regPA_CL_UCP_4_W 0x0182
+#define regPA_CL_UCP_4_W_BASE_IDX 1
+#define regPA_CL_UCP_5_X 0x0183
+#define regPA_CL_UCP_5_X_BASE_IDX 1
+#define regPA_CL_UCP_5_Y 0x0184
+#define regPA_CL_UCP_5_Y_BASE_IDX 1
+#define regPA_CL_UCP_5_Z 0x0185
+#define regPA_CL_UCP_5_Z_BASE_IDX 1
+#define regPA_CL_UCP_5_W 0x0186
+#define regPA_CL_UCP_5_W_BASE_IDX 1
+#define regPA_CL_PROG_NEAR_CLIP_Z 0x0187
+#define regPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX 1
+#define regSPI_PS_INPUT_CNTL_0 0x0191
+#define regSPI_PS_INPUT_CNTL_0_BASE_IDX 1
+#define regSPI_PS_INPUT_CNTL_1 0x0192
+#define regSPI_PS_INPUT_CNTL_1_BASE_IDX 1
+#define regSPI_PS_INPUT_CNTL_2 0x0193
+#define regSPI_PS_INPUT_CNTL_2_BASE_IDX 1
+#define regSPI_PS_INPUT_CNTL_3 0x0194
+#define regSPI_PS_INPUT_CNTL_3_BASE_IDX 1
+#define regSPI_PS_INPUT_CNTL_4 0x0195
+#define regSPI_PS_INPUT_CNTL_4_BASE_IDX 1
+#define regSPI_PS_INPUT_CNTL_5 0x0196
+#define regSPI_PS_INPUT_CNTL_5_BASE_IDX 1
+#define regSPI_PS_INPUT_CNTL_6 0x0197
+#define regSPI_PS_INPUT_CNTL_6_BASE_IDX 1
+#define regSPI_PS_INPUT_CNTL_7 0x0198
+#define regSPI_PS_INPUT_CNTL_7_BASE_IDX 1
+#define regSPI_PS_INPUT_CNTL_8 0x0199
+#define regSPI_PS_INPUT_CNTL_8_BASE_IDX 1
+#define regSPI_PS_INPUT_CNTL_9 0x019a
+#define regSPI_PS_INPUT_CNTL_9_BASE_IDX 1
+#define regSPI_PS_INPUT_CNTL_10 0x019b
+#define regSPI_PS_INPUT_CNTL_10_BASE_IDX 1
+#define regSPI_PS_INPUT_CNTL_11 0x019c
+#define regSPI_PS_INPUT_CNTL_11_BASE_IDX 1
+#define regSPI_PS_INPUT_CNTL_12 0x019d
+#define regSPI_PS_INPUT_CNTL_12_BASE_IDX 1
+#define regSPI_PS_INPUT_CNTL_13 0x019e
+#define regSPI_PS_INPUT_CNTL_13_BASE_IDX 1
+#define regSPI_PS_INPUT_CNTL_14 0x019f
+#define regSPI_PS_INPUT_CNTL_14_BASE_IDX 1
+#define regSPI_PS_INPUT_CNTL_15 0x01a0
+#define regSPI_PS_INPUT_CNTL_15_BASE_IDX 1
+#define regSPI_PS_INPUT_CNTL_16 0x01a1
+#define regSPI_PS_INPUT_CNTL_16_BASE_IDX 1
+#define regSPI_PS_INPUT_CNTL_17 0x01a2
+#define regSPI_PS_INPUT_CNTL_17_BASE_IDX 1
+#define regSPI_PS_INPUT_CNTL_18 0x01a3
+#define regSPI_PS_INPUT_CNTL_18_BASE_IDX 1
+#define regSPI_PS_INPUT_CNTL_19 0x01a4
+#define regSPI_PS_INPUT_CNTL_19_BASE_IDX 1
+#define regSPI_PS_INPUT_CNTL_20 0x01a5
+#define regSPI_PS_INPUT_CNTL_20_BASE_IDX 1
+#define regSPI_PS_INPUT_CNTL_21 0x01a6
+#define regSPI_PS_INPUT_CNTL_21_BASE_IDX 1
+#define regSPI_PS_INPUT_CNTL_22 0x01a7
+#define regSPI_PS_INPUT_CNTL_22_BASE_IDX 1
+#define regSPI_PS_INPUT_CNTL_23 0x01a8
+#define regSPI_PS_INPUT_CNTL_23_BASE_IDX 1
+#define regSPI_PS_INPUT_CNTL_24 0x01a9
+#define regSPI_PS_INPUT_CNTL_24_BASE_IDX 1
+#define regSPI_PS_INPUT_CNTL_25 0x01aa
+#define regSPI_PS_INPUT_CNTL_25_BASE_IDX 1
+#define regSPI_PS_INPUT_CNTL_26 0x01ab
+#define regSPI_PS_INPUT_CNTL_26_BASE_IDX 1
+#define regSPI_PS_INPUT_CNTL_27 0x01ac
+#define regSPI_PS_INPUT_CNTL_27_BASE_IDX 1
+#define regSPI_PS_INPUT_CNTL_28 0x01ad
+#define regSPI_PS_INPUT_CNTL_28_BASE_IDX 1
+#define regSPI_PS_INPUT_CNTL_29 0x01ae
+#define regSPI_PS_INPUT_CNTL_29_BASE_IDX 1
+#define regSPI_PS_INPUT_CNTL_30 0x01af
+#define regSPI_PS_INPUT_CNTL_30_BASE_IDX 1
+#define regSPI_PS_INPUT_CNTL_31 0x01b0
+#define regSPI_PS_INPUT_CNTL_31_BASE_IDX 1
+#define regSPI_VS_OUT_CONFIG 0x01b1
+#define regSPI_VS_OUT_CONFIG_BASE_IDX 1
+#define regSPI_PS_INPUT_ENA 0x01b3
+#define regSPI_PS_INPUT_ENA_BASE_IDX 1
+#define regSPI_PS_INPUT_ADDR 0x01b4
+#define regSPI_PS_INPUT_ADDR_BASE_IDX 1
+#define regSPI_INTERP_CONTROL_0 0x01b5
+#define regSPI_INTERP_CONTROL_0_BASE_IDX 1
+#define regSPI_PS_IN_CONTROL 0x01b6
+#define regSPI_PS_IN_CONTROL_BASE_IDX 1
+#define regSPI_BARYC_CNTL 0x01b8
+#define regSPI_BARYC_CNTL_BASE_IDX 1
+#define regSPI_TMPRING_SIZE 0x01ba
+#define regSPI_TMPRING_SIZE_BASE_IDX 1
+#define regSPI_SHADER_POS_FORMAT 0x01c3
+#define regSPI_SHADER_POS_FORMAT_BASE_IDX 1
+#define regSPI_SHADER_Z_FORMAT 0x01c4
+#define regSPI_SHADER_Z_FORMAT_BASE_IDX 1
+#define regSPI_SHADER_COL_FORMAT 0x01c5
+#define regSPI_SHADER_COL_FORMAT_BASE_IDX 1
+#define regSX_PS_DOWNCONVERT 0x01d5
+#define regSX_PS_DOWNCONVERT_BASE_IDX 1
+#define regSX_BLEND_OPT_EPSILON 0x01d6
+#define regSX_BLEND_OPT_EPSILON_BASE_IDX 1
+#define regSX_BLEND_OPT_CONTROL 0x01d7
+#define regSX_BLEND_OPT_CONTROL_BASE_IDX 1
+#define regSX_MRT0_BLEND_OPT 0x01d8
+#define regSX_MRT0_BLEND_OPT_BASE_IDX 1
+#define regSX_MRT1_BLEND_OPT 0x01d9
+#define regSX_MRT1_BLEND_OPT_BASE_IDX 1
+#define regSX_MRT2_BLEND_OPT 0x01da
+#define regSX_MRT2_BLEND_OPT_BASE_IDX 1
+#define regSX_MRT3_BLEND_OPT 0x01db
+#define regSX_MRT3_BLEND_OPT_BASE_IDX 1
+#define regSX_MRT4_BLEND_OPT 0x01dc
+#define regSX_MRT4_BLEND_OPT_BASE_IDX 1
+#define regSX_MRT5_BLEND_OPT 0x01dd
+#define regSX_MRT5_BLEND_OPT_BASE_IDX 1
+#define regSX_MRT6_BLEND_OPT 0x01de
+#define regSX_MRT6_BLEND_OPT_BASE_IDX 1
+#define regSX_MRT7_BLEND_OPT 0x01df
+#define regSX_MRT7_BLEND_OPT_BASE_IDX 1
+#define regCB_BLEND0_CONTROL 0x01e0
+#define regCB_BLEND0_CONTROL_BASE_IDX 1
+#define regCB_BLEND1_CONTROL 0x01e1
+#define regCB_BLEND1_CONTROL_BASE_IDX 1
+#define regCB_BLEND2_CONTROL 0x01e2
+#define regCB_BLEND2_CONTROL_BASE_IDX 1
+#define regCB_BLEND3_CONTROL 0x01e3
+#define regCB_BLEND3_CONTROL_BASE_IDX 1
+#define regCB_BLEND4_CONTROL 0x01e4
+#define regCB_BLEND4_CONTROL_BASE_IDX 1
+#define regCB_BLEND5_CONTROL 0x01e5
+#define regCB_BLEND5_CONTROL_BASE_IDX 1
+#define regCB_BLEND6_CONTROL 0x01e6
+#define regCB_BLEND6_CONTROL_BASE_IDX 1
+#define regCB_BLEND7_CONTROL 0x01e7
+#define regCB_BLEND7_CONTROL_BASE_IDX 1
+#define regCB_MRT0_EPITCH 0x01e8
+#define regCB_MRT0_EPITCH_BASE_IDX 1
+#define regCB_MRT1_EPITCH 0x01e9
+#define regCB_MRT1_EPITCH_BASE_IDX 1
+#define regCB_MRT2_EPITCH 0x01ea
+#define regCB_MRT2_EPITCH_BASE_IDX 1
+#define regCB_MRT3_EPITCH 0x01eb
+#define regCB_MRT3_EPITCH_BASE_IDX 1
+#define regCB_MRT4_EPITCH 0x01ec
+#define regCB_MRT4_EPITCH_BASE_IDX 1
+#define regCB_MRT5_EPITCH 0x01ed
+#define regCB_MRT5_EPITCH_BASE_IDX 1
+#define regCB_MRT6_EPITCH 0x01ee
+#define regCB_MRT6_EPITCH_BASE_IDX 1
+#define regCB_MRT7_EPITCH 0x01ef
+#define regCB_MRT7_EPITCH_BASE_IDX 1
+#define regCS_COPY_STATE 0x01f3
+#define regCS_COPY_STATE_BASE_IDX 1
+#define regGFX_COPY_STATE 0x01f4
+#define regGFX_COPY_STATE_BASE_IDX 1
+#define regPA_CL_POINT_X_RAD 0x01f5
+#define regPA_CL_POINT_X_RAD_BASE_IDX 1
+#define regPA_CL_POINT_Y_RAD 0x01f6
+#define regPA_CL_POINT_Y_RAD_BASE_IDX 1
+#define regPA_CL_POINT_SIZE 0x01f7
+#define regPA_CL_POINT_SIZE_BASE_IDX 1
+#define regPA_CL_POINT_CULL_RAD 0x01f8
+#define regPA_CL_POINT_CULL_RAD_BASE_IDX 1
+#define regVGT_DMA_BASE_HI 0x01f9
+#define regVGT_DMA_BASE_HI_BASE_IDX 1
+#define regVGT_DMA_BASE 0x01fa
+#define regVGT_DMA_BASE_BASE_IDX 1
+#define regVGT_DRAW_INITIATOR 0x01fc
+#define regVGT_DRAW_INITIATOR_BASE_IDX 1
+#define regVGT_IMMED_DATA 0x01fd
+#define regVGT_IMMED_DATA_BASE_IDX 1
+#define regVGT_EVENT_ADDRESS_REG 0x01fe
+#define regVGT_EVENT_ADDRESS_REG_BASE_IDX 1
+#define regDB_DEPTH_CONTROL 0x0200
+#define regDB_DEPTH_CONTROL_BASE_IDX 1
+#define regDB_EQAA 0x0201
+#define regDB_EQAA_BASE_IDX 1
+#define regCB_COLOR_CONTROL 0x0202
+#define regCB_COLOR_CONTROL_BASE_IDX 1
+#define regDB_SHADER_CONTROL 0x0203
+#define regDB_SHADER_CONTROL_BASE_IDX 1
+#define regPA_CL_CLIP_CNTL 0x0204
+#define regPA_CL_CLIP_CNTL_BASE_IDX 1
+#define regPA_SU_SC_MODE_CNTL 0x0205
+#define regPA_SU_SC_MODE_CNTL_BASE_IDX 1
+#define regPA_CL_VTE_CNTL 0x0206
+#define regPA_CL_VTE_CNTL_BASE_IDX 1
+#define regPA_CL_VS_OUT_CNTL 0x0207
+#define regPA_CL_VS_OUT_CNTL_BASE_IDX 1
+#define regPA_CL_NANINF_CNTL 0x0208
+#define regPA_CL_NANINF_CNTL_BASE_IDX 1
+#define regPA_SU_LINE_STIPPLE_CNTL 0x0209
+#define regPA_SU_LINE_STIPPLE_CNTL_BASE_IDX 1
+#define regPA_SU_LINE_STIPPLE_SCALE 0x020a
+#define regPA_SU_LINE_STIPPLE_SCALE_BASE_IDX 1
+#define regPA_SU_PRIM_FILTER_CNTL 0x020b
+#define regPA_SU_PRIM_FILTER_CNTL_BASE_IDX 1
+#define regPA_SU_SMALL_PRIM_FILTER_CNTL 0x020c
+#define regPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX 1
+#define regPA_CL_OBJPRIM_ID_CNTL 0x020d
+#define regPA_CL_OBJPRIM_ID_CNTL_BASE_IDX 1
+#define regPA_CL_NGG_CNTL 0x020e
+#define regPA_CL_NGG_CNTL_BASE_IDX 1
+#define regPA_SU_OVER_RASTERIZATION_CNTL 0x020f
+#define regPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX 1
+#define regPA_STEREO_CNTL 0x0210
+#define regPA_STEREO_CNTL_BASE_IDX 1
+#define regPA_SU_POINT_SIZE 0x0280
+#define regPA_SU_POINT_SIZE_BASE_IDX 1
+#define regPA_SU_POINT_MINMAX 0x0281
+#define regPA_SU_POINT_MINMAX_BASE_IDX 1
+#define regPA_SU_LINE_CNTL 0x0282
+#define regPA_SU_LINE_CNTL_BASE_IDX 1
+#define regPA_SC_LINE_STIPPLE 0x0283
+#define regPA_SC_LINE_STIPPLE_BASE_IDX 1
+#define regVGT_OUTPUT_PATH_CNTL 0x0284
+#define regVGT_OUTPUT_PATH_CNTL_BASE_IDX 1
+#define regVGT_HOS_CNTL 0x0285
+#define regVGT_HOS_CNTL_BASE_IDX 1
+#define regVGT_HOS_MAX_TESS_LEVEL 0x0286
+#define regVGT_HOS_MAX_TESS_LEVEL_BASE_IDX 1
+#define regVGT_HOS_MIN_TESS_LEVEL 0x0287
+#define regVGT_HOS_MIN_TESS_LEVEL_BASE_IDX 1
+#define regVGT_HOS_REUSE_DEPTH 0x0288
+#define regVGT_HOS_REUSE_DEPTH_BASE_IDX 1
+#define regVGT_GROUP_PRIM_TYPE 0x0289
+#define regVGT_GROUP_PRIM_TYPE_BASE_IDX 1
+#define regVGT_GROUP_FIRST_DECR 0x028a
+#define regVGT_GROUP_FIRST_DECR_BASE_IDX 1
+#define regVGT_GROUP_DECR 0x028b
+#define regVGT_GROUP_DECR_BASE_IDX 1
+#define regVGT_GROUP_VECT_0_CNTL 0x028c
+#define regVGT_GROUP_VECT_0_CNTL_BASE_IDX 1
+#define regVGT_GROUP_VECT_1_CNTL 0x028d
+#define regVGT_GROUP_VECT_1_CNTL_BASE_IDX 1
+#define regVGT_GROUP_VECT_0_FMT_CNTL 0x028e
+#define regVGT_GROUP_VECT_0_FMT_CNTL_BASE_IDX 1
+#define regVGT_GROUP_VECT_1_FMT_CNTL 0x028f
+#define regVGT_GROUP_VECT_1_FMT_CNTL_BASE_IDX 1
+#define regVGT_GS_MODE 0x0290
+#define regVGT_GS_MODE_BASE_IDX 1
+#define regVGT_GS_ONCHIP_CNTL 0x0291
+#define regVGT_GS_ONCHIP_CNTL_BASE_IDX 1
+#define regPA_SC_MODE_CNTL_0 0x0292
+#define regPA_SC_MODE_CNTL_0_BASE_IDX 1
+#define regPA_SC_MODE_CNTL_1 0x0293
+#define regPA_SC_MODE_CNTL_1_BASE_IDX 1
+#define regVGT_ENHANCE 0x0294
+#define regVGT_ENHANCE_BASE_IDX 1
+#define regVGT_GS_PER_ES 0x0295
+#define regVGT_GS_PER_ES_BASE_IDX 1
+#define regVGT_ES_PER_GS 0x0296
+#define regVGT_ES_PER_GS_BASE_IDX 1
+#define regVGT_GS_PER_VS 0x0297
+#define regVGT_GS_PER_VS_BASE_IDX 1
+#define regVGT_GSVS_RING_OFFSET_1 0x0298
+#define regVGT_GSVS_RING_OFFSET_1_BASE_IDX 1
+#define regVGT_GSVS_RING_OFFSET_2 0x0299
+#define regVGT_GSVS_RING_OFFSET_2_BASE_IDX 1
+#define regVGT_GSVS_RING_OFFSET_3 0x029a
+#define regVGT_GSVS_RING_OFFSET_3_BASE_IDX 1
+#define regVGT_GS_OUT_PRIM_TYPE 0x029b
+#define regVGT_GS_OUT_PRIM_TYPE_BASE_IDX 1
+#define regIA_ENHANCE 0x029c
+#define regIA_ENHANCE_BASE_IDX 1
+#define regVGT_DMA_SIZE 0x029d
+#define regVGT_DMA_SIZE_BASE_IDX 1
+#define regVGT_DMA_MAX_SIZE 0x029e
+#define regVGT_DMA_MAX_SIZE_BASE_IDX 1
+#define regVGT_DMA_INDEX_TYPE 0x029f
+#define regVGT_DMA_INDEX_TYPE_BASE_IDX 1
+#define regWD_ENHANCE 0x02a0
+#define regWD_ENHANCE_BASE_IDX 1
+#define regVGT_PRIMITIVEID_EN 0x02a1
+#define regVGT_PRIMITIVEID_EN_BASE_IDX 1
+#define regVGT_DMA_NUM_INSTANCES 0x02a2
+#define regVGT_DMA_NUM_INSTANCES_BASE_IDX 1
+#define regVGT_PRIMITIVEID_RESET 0x02a3
+#define regVGT_PRIMITIVEID_RESET_BASE_IDX 1
+#define regVGT_EVENT_INITIATOR 0x02a4
+#define regVGT_EVENT_INITIATOR_BASE_IDX 1
+#define regVGT_GS_MAX_PRIMS_PER_SUBGROUP 0x02a5
+#define regVGT_GS_MAX_PRIMS_PER_SUBGROUP_BASE_IDX 1
+#define regVGT_DRAW_PAYLOAD_CNTL 0x02a6
+#define regVGT_DRAW_PAYLOAD_CNTL_BASE_IDX 1
+#define regVGT_INSTANCE_STEP_RATE_0 0x02a8
+#define regVGT_INSTANCE_STEP_RATE_0_BASE_IDX 1
+#define regVGT_INSTANCE_STEP_RATE_1 0x02a9
+#define regVGT_INSTANCE_STEP_RATE_1_BASE_IDX 1
+#define regIA_MULTI_VGT_PARAM_BC 0x02aa
+#define regIA_MULTI_VGT_PARAM_BC_BASE_IDX 1
+#define regVGT_ESGS_RING_ITEMSIZE 0x02ab
+#define regVGT_ESGS_RING_ITEMSIZE_BASE_IDX 1
+#define regVGT_GSVS_RING_ITEMSIZE 0x02ac
+#define regVGT_GSVS_RING_ITEMSIZE_BASE_IDX 1
+#define regVGT_REUSE_OFF 0x02ad
+#define regVGT_REUSE_OFF_BASE_IDX 1
+#define regVGT_VTX_CNT_EN 0x02ae
+#define regVGT_VTX_CNT_EN_BASE_IDX 1
+#define regDB_HTILE_SURFACE 0x02af
+#define regDB_HTILE_SURFACE_BASE_IDX 1
+#define regDB_SRESULTS_COMPARE_STATE0 0x02b0
+#define regDB_SRESULTS_COMPARE_STATE0_BASE_IDX 1
+#define regDB_SRESULTS_COMPARE_STATE1 0x02b1
+#define regDB_SRESULTS_COMPARE_STATE1_BASE_IDX 1
+#define regDB_PRELOAD_CONTROL 0x02b2
+#define regDB_PRELOAD_CONTROL_BASE_IDX 1
+#define regVGT_STRMOUT_BUFFER_SIZE_0 0x02b4
+#define regVGT_STRMOUT_BUFFER_SIZE_0_BASE_IDX 1
+#define regVGT_STRMOUT_VTX_STRIDE_0 0x02b5
+#define regVGT_STRMOUT_VTX_STRIDE_0_BASE_IDX 1
+#define regVGT_STRMOUT_BUFFER_OFFSET_0 0x02b7
+#define regVGT_STRMOUT_BUFFER_OFFSET_0_BASE_IDX 1
+#define regVGT_STRMOUT_BUFFER_SIZE_1 0x02b8
+#define regVGT_STRMOUT_BUFFER_SIZE_1_BASE_IDX 1
+#define regVGT_STRMOUT_VTX_STRIDE_1 0x02b9
+#define regVGT_STRMOUT_VTX_STRIDE_1_BASE_IDX 1
+#define regVGT_STRMOUT_BUFFER_OFFSET_1 0x02bb
+#define regVGT_STRMOUT_BUFFER_OFFSET_1_BASE_IDX 1
+#define regVGT_STRMOUT_BUFFER_SIZE_2 0x02bc
+#define regVGT_STRMOUT_BUFFER_SIZE_2_BASE_IDX 1
+#define regVGT_STRMOUT_VTX_STRIDE_2 0x02bd
+#define regVGT_STRMOUT_VTX_STRIDE_2_BASE_IDX 1
+#define regVGT_STRMOUT_BUFFER_OFFSET_2 0x02bf
+#define regVGT_STRMOUT_BUFFER_OFFSET_2_BASE_IDX 1
+#define regVGT_STRMOUT_BUFFER_SIZE_3 0x02c0
+#define regVGT_STRMOUT_BUFFER_SIZE_3_BASE_IDX 1
+#define regVGT_STRMOUT_VTX_STRIDE_3 0x02c1
+#define regVGT_STRMOUT_VTX_STRIDE_3_BASE_IDX 1
+#define regVGT_STRMOUT_BUFFER_OFFSET_3 0x02c3
+#define regVGT_STRMOUT_BUFFER_OFFSET_3_BASE_IDX 1
+#define regVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0x02ca
+#define regVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX 1
+#define regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0x02cb
+#define regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX 1
+#define regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0x02cc
+#define regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX 1
+#define regVGT_GS_MAX_VERT_OUT 0x02ce
+#define regVGT_GS_MAX_VERT_OUT_BASE_IDX 1
+#define regVGT_TESS_DISTRIBUTION 0x02d4
+#define regVGT_TESS_DISTRIBUTION_BASE_IDX 1
+#define regVGT_SHADER_STAGES_EN 0x02d5
+#define regVGT_SHADER_STAGES_EN_BASE_IDX 1
+#define regVGT_LS_HS_CONFIG 0x02d6
+#define regVGT_LS_HS_CONFIG_BASE_IDX 1
+#define regVGT_GS_VERT_ITEMSIZE 0x02d7
+#define regVGT_GS_VERT_ITEMSIZE_BASE_IDX 1
+#define regVGT_GS_VERT_ITEMSIZE_1 0x02d8
+#define regVGT_GS_VERT_ITEMSIZE_1_BASE_IDX 1
+#define regVGT_GS_VERT_ITEMSIZE_2 0x02d9
+#define regVGT_GS_VERT_ITEMSIZE_2_BASE_IDX 1
+#define regVGT_GS_VERT_ITEMSIZE_3 0x02da
+#define regVGT_GS_VERT_ITEMSIZE_3_BASE_IDX 1
+#define regVGT_TF_PARAM 0x02db
+#define regVGT_TF_PARAM_BASE_IDX 1
+#define regDB_ALPHA_TO_MASK 0x02dc
+#define regDB_ALPHA_TO_MASK_BASE_IDX 1
+#define regVGT_DISPATCH_DRAW_INDEX 0x02dd
+#define regVGT_DISPATCH_DRAW_INDEX_BASE_IDX 1
+#define regPA_SU_POLY_OFFSET_DB_FMT_CNTL 0x02de
+#define regPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX 1
+#define regPA_SU_POLY_OFFSET_CLAMP 0x02df
+#define regPA_SU_POLY_OFFSET_CLAMP_BASE_IDX 1
+#define regPA_SU_POLY_OFFSET_FRONT_SCALE 0x02e0
+#define regPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX 1
+#define regPA_SU_POLY_OFFSET_FRONT_OFFSET 0x02e1
+#define regPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX 1
+#define regPA_SU_POLY_OFFSET_BACK_SCALE 0x02e2
+#define regPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX 1
+#define regPA_SU_POLY_OFFSET_BACK_OFFSET 0x02e3
+#define regPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX 1
+#define regVGT_GS_INSTANCE_CNT 0x02e4
+#define regVGT_GS_INSTANCE_CNT_BASE_IDX 1
+#define regVGT_STRMOUT_CONFIG 0x02e5
+#define regVGT_STRMOUT_CONFIG_BASE_IDX 1
+#define regVGT_STRMOUT_BUFFER_CONFIG 0x02e6
+#define regVGT_STRMOUT_BUFFER_CONFIG_BASE_IDX 1
+#define regVGT_DMA_EVENT_INITIATOR 0x02e7
+#define regVGT_DMA_EVENT_INITIATOR_BASE_IDX 1
+#define regPA_SC_CENTROID_PRIORITY_0 0x02f5
+#define regPA_SC_CENTROID_PRIORITY_0_BASE_IDX 1
+#define regPA_SC_CENTROID_PRIORITY_1 0x02f6
+#define regPA_SC_CENTROID_PRIORITY_1_BASE_IDX 1
+#define regPA_SC_LINE_CNTL 0x02f7
+#define regPA_SC_LINE_CNTL_BASE_IDX 1
+#define regPA_SC_AA_CONFIG 0x02f8
+#define regPA_SC_AA_CONFIG_BASE_IDX 1
+#define regPA_SU_VTX_CNTL 0x02f9
+#define regPA_SU_VTX_CNTL_BASE_IDX 1
+#define regPA_CL_GB_VERT_CLIP_ADJ 0x02fa
+#define regPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX 1
+#define regPA_CL_GB_VERT_DISC_ADJ 0x02fb
+#define regPA_CL_GB_VERT_DISC_ADJ_BASE_IDX 1
+#define regPA_CL_GB_HORZ_CLIP_ADJ 0x02fc
+#define regPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX 1
+#define regPA_CL_GB_HORZ_DISC_ADJ 0x02fd
+#define regPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX 1
+#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0x02fe
+#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX 1
+#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0x02ff
+#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX 1
+#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0x0300
+#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX 1
+#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0x0301
+#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX 1
+#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x0302
+#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX 1
+#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0x0303
+#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX 1
+#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0x0304
+#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX 1
+#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0x0305
+#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX 1
+#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x0306
+#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX 1
+#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0x0307
+#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX 1
+#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0x0308
+#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX 1
+#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0x0309
+#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX 1
+#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x030a
+#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX 1
+#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0x030b
+#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX 1
+#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0x030c
+#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX 1
+#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0x030d
+#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX 1
+#define regPA_SC_AA_MASK_X0Y0_X1Y0 0x030e
+#define regPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX 1
+#define regPA_SC_AA_MASK_X0Y1_X1Y1 0x030f
+#define regPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX 1
+#define regPA_SC_SHADER_CONTROL 0x0310
+#define regPA_SC_SHADER_CONTROL_BASE_IDX 1
+#define regPA_SC_BINNER_CNTL_0 0x0311
+#define regPA_SC_BINNER_CNTL_0_BASE_IDX 1
+#define regPA_SC_BINNER_CNTL_1 0x0312
+#define regPA_SC_BINNER_CNTL_1_BASE_IDX 1
+#define regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL 0x0313
+#define regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX 1
+#define regPA_SC_NGG_MODE_CNTL 0x0314
+#define regPA_SC_NGG_MODE_CNTL_BASE_IDX 1
+#define regVGT_VERTEX_REUSE_BLOCK_CNTL 0x0316
+#define regVGT_VERTEX_REUSE_BLOCK_CNTL_BASE_IDX 1
+#define regVGT_OUT_DEALLOC_CNTL 0x0317
+#define regVGT_OUT_DEALLOC_CNTL_BASE_IDX 1
+#define regCB_COLOR0_BASE 0x0318
+#define regCB_COLOR0_BASE_BASE_IDX 1
+#define regCB_COLOR0_BASE_EXT 0x0319
+#define regCB_COLOR0_BASE_EXT_BASE_IDX 1
+#define regCB_COLOR0_ATTRIB2 0x031a
+#define regCB_COLOR0_ATTRIB2_BASE_IDX 1
+#define regCB_COLOR0_VIEW 0x031b
+#define regCB_COLOR0_VIEW_BASE_IDX 1
+#define regCB_COLOR0_INFO 0x031c
+#define regCB_COLOR0_INFO_BASE_IDX 1
+#define regCB_COLOR0_ATTRIB 0x031d
+#define regCB_COLOR0_ATTRIB_BASE_IDX 1
+#define regCB_COLOR0_DCC_CONTROL 0x031e
+#define regCB_COLOR0_DCC_CONTROL_BASE_IDX 1
+#define regCB_COLOR0_CMASK 0x031f
+#define regCB_COLOR0_CMASK_BASE_IDX 1
+#define regCB_COLOR0_CMASK_BASE_EXT 0x0320
+#define regCB_COLOR0_CMASK_BASE_EXT_BASE_IDX 1
+#define regCB_COLOR0_FMASK 0x0321
+#define regCB_COLOR0_FMASK_BASE_IDX 1
+#define regCB_COLOR0_FMASK_BASE_EXT 0x0322
+#define regCB_COLOR0_FMASK_BASE_EXT_BASE_IDX 1
+#define regCB_COLOR0_CLEAR_WORD0 0x0323
+#define regCB_COLOR0_CLEAR_WORD0_BASE_IDX 1
+#define regCB_COLOR0_CLEAR_WORD1 0x0324
+#define regCB_COLOR0_CLEAR_WORD1_BASE_IDX 1
+#define regCB_COLOR0_DCC_BASE 0x0325
+#define regCB_COLOR0_DCC_BASE_BASE_IDX 1
+#define regCB_COLOR0_DCC_BASE_EXT 0x0326
+#define regCB_COLOR0_DCC_BASE_EXT_BASE_IDX 1
+#define regCB_COLOR1_BASE 0x0327
+#define regCB_COLOR1_BASE_BASE_IDX 1
+#define regCB_COLOR1_BASE_EXT 0x0328
+#define regCB_COLOR1_BASE_EXT_BASE_IDX 1
+#define regCB_COLOR1_ATTRIB2 0x0329
+#define regCB_COLOR1_ATTRIB2_BASE_IDX 1
+#define regCB_COLOR1_VIEW 0x032a
+#define regCB_COLOR1_VIEW_BASE_IDX 1
+#define regCB_COLOR1_INFO 0x032b
+#define regCB_COLOR1_INFO_BASE_IDX 1
+#define regCB_COLOR1_ATTRIB 0x032c
+#define regCB_COLOR1_ATTRIB_BASE_IDX 1
+#define regCB_COLOR1_DCC_CONTROL 0x032d
+#define regCB_COLOR1_DCC_CONTROL_BASE_IDX 1
+#define regCB_COLOR1_CMASK 0x032e
+#define regCB_COLOR1_CMASK_BASE_IDX 1
+#define regCB_COLOR1_CMASK_BASE_EXT 0x032f
+#define regCB_COLOR1_CMASK_BASE_EXT_BASE_IDX 1
+#define regCB_COLOR1_FMASK 0x0330
+#define regCB_COLOR1_FMASK_BASE_IDX 1
+#define regCB_COLOR1_FMASK_BASE_EXT 0x0331
+#define regCB_COLOR1_FMASK_BASE_EXT_BASE_IDX 1
+#define regCB_COLOR1_CLEAR_WORD0 0x0332
+#define regCB_COLOR1_CLEAR_WORD0_BASE_IDX 1
+#define regCB_COLOR1_CLEAR_WORD1 0x0333
+#define regCB_COLOR1_CLEAR_WORD1_BASE_IDX 1
+#define regCB_COLOR1_DCC_BASE 0x0334
+#define regCB_COLOR1_DCC_BASE_BASE_IDX 1
+#define regCB_COLOR1_DCC_BASE_EXT 0x0335
+#define regCB_COLOR1_DCC_BASE_EXT_BASE_IDX 1
+#define regCB_COLOR2_BASE 0x0336
+#define regCB_COLOR2_BASE_BASE_IDX 1
+#define regCB_COLOR2_BASE_EXT 0x0337
+#define regCB_COLOR2_BASE_EXT_BASE_IDX 1
+#define regCB_COLOR2_ATTRIB2 0x0338
+#define regCB_COLOR2_ATTRIB2_BASE_IDX 1
+#define regCB_COLOR2_VIEW 0x0339
+#define regCB_COLOR2_VIEW_BASE_IDX 1
+#define regCB_COLOR2_INFO 0x033a
+#define regCB_COLOR2_INFO_BASE_IDX 1
+#define regCB_COLOR2_ATTRIB 0x033b
+#define regCB_COLOR2_ATTRIB_BASE_IDX 1
+#define regCB_COLOR2_DCC_CONTROL 0x033c
+#define regCB_COLOR2_DCC_CONTROL_BASE_IDX 1
+#define regCB_COLOR2_CMASK 0x033d
+#define regCB_COLOR2_CMASK_BASE_IDX 1
+#define regCB_COLOR2_CMASK_BASE_EXT 0x033e
+#define regCB_COLOR2_CMASK_BASE_EXT_BASE_IDX 1
+#define regCB_COLOR2_FMASK 0x033f
+#define regCB_COLOR2_FMASK_BASE_IDX 1
+#define regCB_COLOR2_FMASK_BASE_EXT 0x0340
+#define regCB_COLOR2_FMASK_BASE_EXT_BASE_IDX 1
+#define regCB_COLOR2_CLEAR_WORD0 0x0341
+#define regCB_COLOR2_CLEAR_WORD0_BASE_IDX 1
+#define regCB_COLOR2_CLEAR_WORD1 0x0342
+#define regCB_COLOR2_CLEAR_WORD1_BASE_IDX 1
+#define regCB_COLOR2_DCC_BASE 0x0343
+#define regCB_COLOR2_DCC_BASE_BASE_IDX 1
+#define regCB_COLOR2_DCC_BASE_EXT 0x0344
+#define regCB_COLOR2_DCC_BASE_EXT_BASE_IDX 1
+#define regCB_COLOR3_BASE 0x0345
+#define regCB_COLOR3_BASE_BASE_IDX 1
+#define regCB_COLOR3_BASE_EXT 0x0346
+#define regCB_COLOR3_BASE_EXT_BASE_IDX 1
+#define regCB_COLOR3_ATTRIB2 0x0347
+#define regCB_COLOR3_ATTRIB2_BASE_IDX 1
+#define regCB_COLOR3_VIEW 0x0348
+#define regCB_COLOR3_VIEW_BASE_IDX 1
+#define regCB_COLOR3_INFO 0x0349
+#define regCB_COLOR3_INFO_BASE_IDX 1
+#define regCB_COLOR3_ATTRIB 0x034a
+#define regCB_COLOR3_ATTRIB_BASE_IDX 1
+#define regCB_COLOR3_DCC_CONTROL 0x034b
+#define regCB_COLOR3_DCC_CONTROL_BASE_IDX 1
+#define regCB_COLOR3_CMASK 0x034c
+#define regCB_COLOR3_CMASK_BASE_IDX 1
+#define regCB_COLOR3_CMASK_BASE_EXT 0x034d
+#define regCB_COLOR3_CMASK_BASE_EXT_BASE_IDX 1
+#define regCB_COLOR3_FMASK 0x034e
+#define regCB_COLOR3_FMASK_BASE_IDX 1
+#define regCB_COLOR3_FMASK_BASE_EXT 0x034f
+#define regCB_COLOR3_FMASK_BASE_EXT_BASE_IDX 1
+#define regCB_COLOR3_CLEAR_WORD0 0x0350
+#define regCB_COLOR3_CLEAR_WORD0_BASE_IDX 1
+#define regCB_COLOR3_CLEAR_WORD1 0x0351
+#define regCB_COLOR3_CLEAR_WORD1_BASE_IDX 1
+#define regCB_COLOR3_DCC_BASE 0x0352
+#define regCB_COLOR3_DCC_BASE_BASE_IDX 1
+#define regCB_COLOR3_DCC_BASE_EXT 0x0353
+#define regCB_COLOR3_DCC_BASE_EXT_BASE_IDX 1
+#define regCB_COLOR4_BASE 0x0354
+#define regCB_COLOR4_BASE_BASE_IDX 1
+#define regCB_COLOR4_BASE_EXT 0x0355
+#define regCB_COLOR4_BASE_EXT_BASE_IDX 1
+#define regCB_COLOR4_ATTRIB2 0x0356
+#define regCB_COLOR4_ATTRIB2_BASE_IDX 1
+#define regCB_COLOR4_VIEW 0x0357
+#define regCB_COLOR4_VIEW_BASE_IDX 1
+#define regCB_COLOR4_INFO 0x0358
+#define regCB_COLOR4_INFO_BASE_IDX 1
+#define regCB_COLOR4_ATTRIB 0x0359
+#define regCB_COLOR4_ATTRIB_BASE_IDX 1
+#define regCB_COLOR4_DCC_CONTROL 0x035a
+#define regCB_COLOR4_DCC_CONTROL_BASE_IDX 1
+#define regCB_COLOR4_CMASK 0x035b
+#define regCB_COLOR4_CMASK_BASE_IDX 1
+#define regCB_COLOR4_CMASK_BASE_EXT 0x035c
+#define regCB_COLOR4_CMASK_BASE_EXT_BASE_IDX 1
+#define regCB_COLOR4_FMASK 0x035d
+#define regCB_COLOR4_FMASK_BASE_IDX 1
+#define regCB_COLOR4_FMASK_BASE_EXT 0x035e
+#define regCB_COLOR4_FMASK_BASE_EXT_BASE_IDX 1
+#define regCB_COLOR4_CLEAR_WORD0 0x035f
+#define regCB_COLOR4_CLEAR_WORD0_BASE_IDX 1
+#define regCB_COLOR4_CLEAR_WORD1 0x0360
+#define regCB_COLOR4_CLEAR_WORD1_BASE_IDX 1
+#define regCB_COLOR4_DCC_BASE 0x0361
+#define regCB_COLOR4_DCC_BASE_BASE_IDX 1
+#define regCB_COLOR4_DCC_BASE_EXT 0x0362
+#define regCB_COLOR4_DCC_BASE_EXT_BASE_IDX 1
+#define regCB_COLOR5_BASE 0x0363
+#define regCB_COLOR5_BASE_BASE_IDX 1
+#define regCB_COLOR5_BASE_EXT 0x0364
+#define regCB_COLOR5_BASE_EXT_BASE_IDX 1
+#define regCB_COLOR5_ATTRIB2 0x0365
+#define regCB_COLOR5_ATTRIB2_BASE_IDX 1
+#define regCB_COLOR5_VIEW 0x0366
+#define regCB_COLOR5_VIEW_BASE_IDX 1
+#define regCB_COLOR5_INFO 0x0367
+#define regCB_COLOR5_INFO_BASE_IDX 1
+#define regCB_COLOR5_ATTRIB 0x0368
+#define regCB_COLOR5_ATTRIB_BASE_IDX 1
+#define regCB_COLOR5_DCC_CONTROL 0x0369
+#define regCB_COLOR5_DCC_CONTROL_BASE_IDX 1
+#define regCB_COLOR5_CMASK 0x036a
+#define regCB_COLOR5_CMASK_BASE_IDX 1
+#define regCB_COLOR5_CMASK_BASE_EXT 0x036b
+#define regCB_COLOR5_CMASK_BASE_EXT_BASE_IDX 1
+#define regCB_COLOR5_FMASK 0x036c
+#define regCB_COLOR5_FMASK_BASE_IDX 1
+#define regCB_COLOR5_FMASK_BASE_EXT 0x036d
+#define regCB_COLOR5_FMASK_BASE_EXT_BASE_IDX 1
+#define regCB_COLOR5_CLEAR_WORD0 0x036e
+#define regCB_COLOR5_CLEAR_WORD0_BASE_IDX 1
+#define regCB_COLOR5_CLEAR_WORD1 0x036f
+#define regCB_COLOR5_CLEAR_WORD1_BASE_IDX 1
+#define regCB_COLOR5_DCC_BASE 0x0370
+#define regCB_COLOR5_DCC_BASE_BASE_IDX 1
+#define regCB_COLOR5_DCC_BASE_EXT 0x0371
+#define regCB_COLOR5_DCC_BASE_EXT_BASE_IDX 1
+#define regCB_COLOR6_BASE 0x0372
+#define regCB_COLOR6_BASE_BASE_IDX 1
+#define regCB_COLOR6_BASE_EXT 0x0373
+#define regCB_COLOR6_BASE_EXT_BASE_IDX 1
+#define regCB_COLOR6_ATTRIB2 0x0374
+#define regCB_COLOR6_ATTRIB2_BASE_IDX 1
+#define regCB_COLOR6_VIEW 0x0375
+#define regCB_COLOR6_VIEW_BASE_IDX 1
+#define regCB_COLOR6_INFO 0x0376
+#define regCB_COLOR6_INFO_BASE_IDX 1
+#define regCB_COLOR6_ATTRIB 0x0377
+#define regCB_COLOR6_ATTRIB_BASE_IDX 1
+#define regCB_COLOR6_DCC_CONTROL 0x0378
+#define regCB_COLOR6_DCC_CONTROL_BASE_IDX 1
+#define regCB_COLOR6_CMASK 0x0379
+#define regCB_COLOR6_CMASK_BASE_IDX 1
+#define regCB_COLOR6_CMASK_BASE_EXT 0x037a
+#define regCB_COLOR6_CMASK_BASE_EXT_BASE_IDX 1
+#define regCB_COLOR6_FMASK 0x037b
+#define regCB_COLOR6_FMASK_BASE_IDX 1
+#define regCB_COLOR6_FMASK_BASE_EXT 0x037c
+#define regCB_COLOR6_FMASK_BASE_EXT_BASE_IDX 1
+#define regCB_COLOR6_CLEAR_WORD0 0x037d
+#define regCB_COLOR6_CLEAR_WORD0_BASE_IDX 1
+#define regCB_COLOR6_CLEAR_WORD1 0x037e
+#define regCB_COLOR6_CLEAR_WORD1_BASE_IDX 1
+#define regCB_COLOR6_DCC_BASE 0x037f
+#define regCB_COLOR6_DCC_BASE_BASE_IDX 1
+#define regCB_COLOR6_DCC_BASE_EXT 0x0380
+#define regCB_COLOR6_DCC_BASE_EXT_BASE_IDX 1
+#define regCB_COLOR7_BASE 0x0381
+#define regCB_COLOR7_BASE_BASE_IDX 1
+#define regCB_COLOR7_BASE_EXT 0x0382
+#define regCB_COLOR7_BASE_EXT_BASE_IDX 1
+#define regCB_COLOR7_ATTRIB2 0x0383
+#define regCB_COLOR7_ATTRIB2_BASE_IDX 1
+#define regCB_COLOR7_VIEW 0x0384
+#define regCB_COLOR7_VIEW_BASE_IDX 1
+#define regCB_COLOR7_INFO 0x0385
+#define regCB_COLOR7_INFO_BASE_IDX 1
+#define regCB_COLOR7_ATTRIB 0x0386
+#define regCB_COLOR7_ATTRIB_BASE_IDX 1
+#define regCB_COLOR7_DCC_CONTROL 0x0387
+#define regCB_COLOR7_DCC_CONTROL_BASE_IDX 1
+#define regCB_COLOR7_CMASK 0x0388
+#define regCB_COLOR7_CMASK_BASE_IDX 1
+#define regCB_COLOR7_CMASK_BASE_EXT 0x0389
+#define regCB_COLOR7_CMASK_BASE_EXT_BASE_IDX 1
+#define regCB_COLOR7_FMASK 0x038a
+#define regCB_COLOR7_FMASK_BASE_IDX 1
+#define regCB_COLOR7_FMASK_BASE_EXT 0x038b
+#define regCB_COLOR7_FMASK_BASE_EXT_BASE_IDX 1
+#define regCB_COLOR7_CLEAR_WORD0 0x038c
+#define regCB_COLOR7_CLEAR_WORD0_BASE_IDX 1
+#define regCB_COLOR7_CLEAR_WORD1 0x038d
+#define regCB_COLOR7_CLEAR_WORD1_BASE_IDX 1
+#define regCB_COLOR7_DCC_BASE 0x038e
+#define regCB_COLOR7_DCC_BASE_BASE_IDX 1
+#define regCB_COLOR7_DCC_BASE_EXT 0x038f
+#define regCB_COLOR7_DCC_BASE_EXT_BASE_IDX 1
+
+
+// addressBlock: gc_gfxudec
+// base address: 0x30000
+#define regCP_EOP_DONE_ADDR_LO 0x2000
+#define regCP_EOP_DONE_ADDR_LO_BASE_IDX 1
+#define regCP_EOP_DONE_ADDR_HI 0x2001
+#define regCP_EOP_DONE_ADDR_HI_BASE_IDX 1
+#define regCP_EOP_DONE_DATA_LO 0x2002
+#define regCP_EOP_DONE_DATA_LO_BASE_IDX 1
+#define regCP_EOP_DONE_DATA_HI 0x2003
+#define regCP_EOP_DONE_DATA_HI_BASE_IDX 1
+#define regCP_EOP_LAST_FENCE_LO 0x2004
+#define regCP_EOP_LAST_FENCE_LO_BASE_IDX 1
+#define regCP_EOP_LAST_FENCE_HI 0x2005
+#define regCP_EOP_LAST_FENCE_HI_BASE_IDX 1
+#define regCP_STREAM_OUT_ADDR_LO 0x2006
+#define regCP_STREAM_OUT_ADDR_LO_BASE_IDX 1
+#define regCP_STREAM_OUT_ADDR_HI 0x2007
+#define regCP_STREAM_OUT_ADDR_HI_BASE_IDX 1
+#define regCP_NUM_PRIM_WRITTEN_COUNT0_LO 0x2008
+#define regCP_NUM_PRIM_WRITTEN_COUNT0_LO_BASE_IDX 1
+#define regCP_NUM_PRIM_WRITTEN_COUNT0_HI 0x2009
+#define regCP_NUM_PRIM_WRITTEN_COUNT0_HI_BASE_IDX 1
+#define regCP_NUM_PRIM_NEEDED_COUNT0_LO 0x200a
+#define regCP_NUM_PRIM_NEEDED_COUNT0_LO_BASE_IDX 1
+#define regCP_NUM_PRIM_NEEDED_COUNT0_HI 0x200b
+#define regCP_NUM_PRIM_NEEDED_COUNT0_HI_BASE_IDX 1
+#define regCP_NUM_PRIM_WRITTEN_COUNT1_LO 0x200c
+#define regCP_NUM_PRIM_WRITTEN_COUNT1_LO_BASE_IDX 1
+#define regCP_NUM_PRIM_WRITTEN_COUNT1_HI 0x200d
+#define regCP_NUM_PRIM_WRITTEN_COUNT1_HI_BASE_IDX 1
+#define regCP_NUM_PRIM_NEEDED_COUNT1_LO 0x200e
+#define regCP_NUM_PRIM_NEEDED_COUNT1_LO_BASE_IDX 1
+#define regCP_NUM_PRIM_NEEDED_COUNT1_HI 0x200f
+#define regCP_NUM_PRIM_NEEDED_COUNT1_HI_BASE_IDX 1
+#define regCP_NUM_PRIM_WRITTEN_COUNT2_LO 0x2010
+#define regCP_NUM_PRIM_WRITTEN_COUNT2_LO_BASE_IDX 1
+#define regCP_NUM_PRIM_WRITTEN_COUNT2_HI 0x2011
+#define regCP_NUM_PRIM_WRITTEN_COUNT2_HI_BASE_IDX 1
+#define regCP_NUM_PRIM_NEEDED_COUNT2_LO 0x2012
+#define regCP_NUM_PRIM_NEEDED_COUNT2_LO_BASE_IDX 1
+#define regCP_NUM_PRIM_NEEDED_COUNT2_HI 0x2013
+#define regCP_NUM_PRIM_NEEDED_COUNT2_HI_BASE_IDX 1
+#define regCP_NUM_PRIM_WRITTEN_COUNT3_LO 0x2014
+#define regCP_NUM_PRIM_WRITTEN_COUNT3_LO_BASE_IDX 1
+#define regCP_NUM_PRIM_WRITTEN_COUNT3_HI 0x2015
+#define regCP_NUM_PRIM_WRITTEN_COUNT3_HI_BASE_IDX 1
+#define regCP_NUM_PRIM_NEEDED_COUNT3_LO 0x2016
+#define regCP_NUM_PRIM_NEEDED_COUNT3_LO_BASE_IDX 1
+#define regCP_NUM_PRIM_NEEDED_COUNT3_HI 0x2017
+#define regCP_NUM_PRIM_NEEDED_COUNT3_HI_BASE_IDX 1
+#define regCP_PIPE_STATS_ADDR_LO 0x2018
+#define regCP_PIPE_STATS_ADDR_LO_BASE_IDX 1
+#define regCP_PIPE_STATS_ADDR_HI 0x2019
+#define regCP_PIPE_STATS_ADDR_HI_BASE_IDX 1
+#define regCP_VGT_IAVERT_COUNT_LO 0x201a
+#define regCP_VGT_IAVERT_COUNT_LO_BASE_IDX 1
+#define regCP_VGT_IAVERT_COUNT_HI 0x201b
+#define regCP_VGT_IAVERT_COUNT_HI_BASE_IDX 1
+#define regCP_VGT_IAPRIM_COUNT_LO 0x201c
+#define regCP_VGT_IAPRIM_COUNT_LO_BASE_IDX 1
+#define regCP_VGT_IAPRIM_COUNT_HI 0x201d
+#define regCP_VGT_IAPRIM_COUNT_HI_BASE_IDX 1
+#define regCP_VGT_GSPRIM_COUNT_LO 0x201e
+#define regCP_VGT_GSPRIM_COUNT_LO_BASE_IDX 1
+#define regCP_VGT_GSPRIM_COUNT_HI 0x201f
+#define regCP_VGT_GSPRIM_COUNT_HI_BASE_IDX 1
+#define regCP_VGT_VSINVOC_COUNT_LO 0x2020
+#define regCP_VGT_VSINVOC_COUNT_LO_BASE_IDX 1
+#define regCP_VGT_VSINVOC_COUNT_HI 0x2021
+#define regCP_VGT_VSINVOC_COUNT_HI_BASE_IDX 1
+#define regCP_VGT_GSINVOC_COUNT_LO 0x2022
+#define regCP_VGT_GSINVOC_COUNT_LO_BASE_IDX 1
+#define regCP_VGT_GSINVOC_COUNT_HI 0x2023
+#define regCP_VGT_GSINVOC_COUNT_HI_BASE_IDX 1
+#define regCP_VGT_HSINVOC_COUNT_LO 0x2024
+#define regCP_VGT_HSINVOC_COUNT_LO_BASE_IDX 1
+#define regCP_VGT_HSINVOC_COUNT_HI 0x2025
+#define regCP_VGT_HSINVOC_COUNT_HI_BASE_IDX 1
+#define regCP_VGT_DSINVOC_COUNT_LO 0x2026
+#define regCP_VGT_DSINVOC_COUNT_LO_BASE_IDX 1
+#define regCP_VGT_DSINVOC_COUNT_HI 0x2027
+#define regCP_VGT_DSINVOC_COUNT_HI_BASE_IDX 1
+#define regCP_PA_CINVOC_COUNT_LO 0x2028
+#define regCP_PA_CINVOC_COUNT_LO_BASE_IDX 1
+#define regCP_PA_CINVOC_COUNT_HI 0x2029
+#define regCP_PA_CINVOC_COUNT_HI_BASE_IDX 1
+#define regCP_PA_CPRIM_COUNT_LO 0x202a
+#define regCP_PA_CPRIM_COUNT_LO_BASE_IDX 1
+#define regCP_PA_CPRIM_COUNT_HI 0x202b
+#define regCP_PA_CPRIM_COUNT_HI_BASE_IDX 1
+#define regCP_SC_PSINVOC_COUNT0_LO 0x202c
+#define regCP_SC_PSINVOC_COUNT0_LO_BASE_IDX 1
+#define regCP_SC_PSINVOC_COUNT0_HI 0x202d
+#define regCP_SC_PSINVOC_COUNT0_HI_BASE_IDX 1
+#define regCP_SC_PSINVOC_COUNT1_LO 0x202e
+#define regCP_SC_PSINVOC_COUNT1_LO_BASE_IDX 1
+#define regCP_SC_PSINVOC_COUNT1_HI 0x202f
+#define regCP_SC_PSINVOC_COUNT1_HI_BASE_IDX 1
+#define regCP_VGT_CSINVOC_COUNT_LO 0x2030
+#define regCP_VGT_CSINVOC_COUNT_LO_BASE_IDX 1
+#define regCP_VGT_CSINVOC_COUNT_HI 0x2031
+#define regCP_VGT_CSINVOC_COUNT_HI_BASE_IDX 1
+#define regCP_PIPE_STATS_CONTROL 0x203d
+#define regCP_PIPE_STATS_CONTROL_BASE_IDX 1
+#define regCP_STREAM_OUT_CONTROL 0x203e
+#define regCP_STREAM_OUT_CONTROL_BASE_IDX 1
+#define regCP_STRMOUT_CNTL 0x203f
+#define regCP_STRMOUT_CNTL_BASE_IDX 1
+#define regSCRATCH_REG0 0x2040
+#define regSCRATCH_REG0_BASE_IDX 1
+#define regSCRATCH_REG1 0x2041
+#define regSCRATCH_REG1_BASE_IDX 1
+#define regSCRATCH_REG2 0x2042
+#define regSCRATCH_REG2_BASE_IDX 1
+#define regSCRATCH_REG3 0x2043
+#define regSCRATCH_REG3_BASE_IDX 1
+#define regSCRATCH_REG4 0x2044
+#define regSCRATCH_REG4_BASE_IDX 1
+#define regSCRATCH_REG5 0x2045
+#define regSCRATCH_REG5_BASE_IDX 1
+#define regSCRATCH_REG6 0x2046
+#define regSCRATCH_REG6_BASE_IDX 1
+#define regSCRATCH_REG7 0x2047
+#define regSCRATCH_REG7_BASE_IDX 1
+#define regCP_APPEND_DATA_HI 0x204c
+#define regCP_APPEND_DATA_HI_BASE_IDX 1
+#define regCP_APPEND_LAST_CS_FENCE_HI 0x204d
+#define regCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX 1
+#define regCP_APPEND_LAST_PS_FENCE_HI 0x204e
+#define regCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX 1
+#define regSCRATCH_UMSK 0x2050
+#define regSCRATCH_UMSK_BASE_IDX 1
+#define regSCRATCH_ADDR 0x2051
+#define regSCRATCH_ADDR_BASE_IDX 1
+#define regCP_PFP_ATOMIC_PREOP_LO 0x2052
+#define regCP_PFP_ATOMIC_PREOP_LO_BASE_IDX 1
+#define regCP_PFP_ATOMIC_PREOP_HI 0x2053
+#define regCP_PFP_ATOMIC_PREOP_HI_BASE_IDX 1
+#define regCP_PFP_GDS_ATOMIC0_PREOP_LO 0x2054
+#define regCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1
+#define regCP_PFP_GDS_ATOMIC0_PREOP_HI 0x2055
+#define regCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1
+#define regCP_PFP_GDS_ATOMIC1_PREOP_LO 0x2056
+#define regCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1
+#define regCP_PFP_GDS_ATOMIC1_PREOP_HI 0x2057
+#define regCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1
+#define regCP_APPEND_ADDR_LO 0x2058
+#define regCP_APPEND_ADDR_LO_BASE_IDX 1
+#define regCP_APPEND_ADDR_HI 0x2059
+#define regCP_APPEND_ADDR_HI_BASE_IDX 1
+#define regCP_APPEND_DATA_LO 0x205a
+#define regCP_APPEND_DATA_LO_BASE_IDX 1
+#define regCP_APPEND_LAST_CS_FENCE_LO 0x205b
+#define regCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX 1
+#define regCP_APPEND_LAST_PS_FENCE_LO 0x205c
+#define regCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX 1
+#define regCP_ATOMIC_PREOP_LO 0x205d
+#define regCP_ATOMIC_PREOP_LO_BASE_IDX 1
+#define regCP_ME_ATOMIC_PREOP_LO 0x205d
+#define regCP_ME_ATOMIC_PREOP_LO_BASE_IDX 1
+#define regCP_ATOMIC_PREOP_HI 0x205e
+#define regCP_ATOMIC_PREOP_HI_BASE_IDX 1
+#define regCP_ME_ATOMIC_PREOP_HI 0x205e
+#define regCP_ME_ATOMIC_PREOP_HI_BASE_IDX 1
+#define regCP_GDS_ATOMIC0_PREOP_LO 0x205f
+#define regCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1
+#define regCP_ME_GDS_ATOMIC0_PREOP_LO 0x205f
+#define regCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1
+#define regCP_GDS_ATOMIC0_PREOP_HI 0x2060
+#define regCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1
+#define regCP_ME_GDS_ATOMIC0_PREOP_HI 0x2060
+#define regCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1
+#define regCP_GDS_ATOMIC1_PREOP_LO 0x2061
+#define regCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1
+#define regCP_ME_GDS_ATOMIC1_PREOP_LO 0x2061
+#define regCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1
+#define regCP_GDS_ATOMIC1_PREOP_HI 0x2062
+#define regCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1
+#define regCP_ME_GDS_ATOMIC1_PREOP_HI 0x2062
+#define regCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1
+#define regCP_ME_MC_WADDR_LO 0x2069
+#define regCP_ME_MC_WADDR_LO_BASE_IDX 1
+#define regCP_ME_MC_WADDR_HI 0x206a
+#define regCP_ME_MC_WADDR_HI_BASE_IDX 1
+#define regCP_ME_MC_WDATA_LO 0x206b
+#define regCP_ME_MC_WDATA_LO_BASE_IDX 1
+#define regCP_ME_MC_WDATA_HI 0x206c
+#define regCP_ME_MC_WDATA_HI_BASE_IDX 1
+#define regCP_ME_MC_RADDR_LO 0x206d
+#define regCP_ME_MC_RADDR_LO_BASE_IDX 1
+#define regCP_ME_MC_RADDR_HI 0x206e
+#define regCP_ME_MC_RADDR_HI_BASE_IDX 1
+#define regCP_SEM_WAIT_TIMER 0x206f
+#define regCP_SEM_WAIT_TIMER_BASE_IDX 1
+#define regCP_SIG_SEM_ADDR_LO 0x2070
+#define regCP_SIG_SEM_ADDR_LO_BASE_IDX 1
+#define regCP_SIG_SEM_ADDR_HI 0x2071
+#define regCP_SIG_SEM_ADDR_HI_BASE_IDX 1
+#define regCP_WAIT_REG_MEM_TIMEOUT 0x2074
+#define regCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX 1
+#define regCP_WAIT_SEM_ADDR_LO 0x2075
+#define regCP_WAIT_SEM_ADDR_LO_BASE_IDX 1
+#define regCP_WAIT_SEM_ADDR_HI 0x2076
+#define regCP_WAIT_SEM_ADDR_HI_BASE_IDX 1
+#define regCP_DMA_PFP_CONTROL 0x2077
+#define regCP_DMA_PFP_CONTROL_BASE_IDX 1
+#define regCP_DMA_ME_CONTROL 0x2078
+#define regCP_DMA_ME_CONTROL_BASE_IDX 1
+#define regCP_COHER_BASE_HI 0x2079
+#define regCP_COHER_BASE_HI_BASE_IDX 1
+#define regCP_COHER_START_DELAY 0x207b
+#define regCP_COHER_START_DELAY_BASE_IDX 1
+#define regCP_COHER_CNTL 0x207c
+#define regCP_COHER_CNTL_BASE_IDX 1
+#define regCP_COHER_SIZE 0x207d
+#define regCP_COHER_SIZE_BASE_IDX 1
+#define regCP_COHER_BASE 0x207e
+#define regCP_COHER_BASE_BASE_IDX 1
+#define regCP_COHER_STATUS 0x207f
+#define regCP_COHER_STATUS_BASE_IDX 1
+#define regCP_DMA_ME_SRC_ADDR 0x2080
+#define regCP_DMA_ME_SRC_ADDR_BASE_IDX 1
+#define regCP_DMA_ME_SRC_ADDR_HI 0x2081
+#define regCP_DMA_ME_SRC_ADDR_HI_BASE_IDX 1
+#define regCP_DMA_ME_DST_ADDR 0x2082
+#define regCP_DMA_ME_DST_ADDR_BASE_IDX 1
+#define regCP_DMA_ME_DST_ADDR_HI 0x2083
+#define regCP_DMA_ME_DST_ADDR_HI_BASE_IDX 1
+#define regCP_DMA_ME_COMMAND 0x2084
+#define regCP_DMA_ME_COMMAND_BASE_IDX 1
+#define regCP_DMA_PFP_SRC_ADDR 0x2085
+#define regCP_DMA_PFP_SRC_ADDR_BASE_IDX 1
+#define regCP_DMA_PFP_SRC_ADDR_HI 0x2086
+#define regCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX 1
+#define regCP_DMA_PFP_DST_ADDR 0x2087
+#define regCP_DMA_PFP_DST_ADDR_BASE_IDX 1
+#define regCP_DMA_PFP_DST_ADDR_HI 0x2088
+#define regCP_DMA_PFP_DST_ADDR_HI_BASE_IDX 1
+#define regCP_DMA_PFP_COMMAND 0x2089
+#define regCP_DMA_PFP_COMMAND_BASE_IDX 1
+#define regCP_DMA_CNTL 0x208a
+#define regCP_DMA_CNTL_BASE_IDX 1
+#define regCP_DMA_READ_TAGS 0x208b
+#define regCP_DMA_READ_TAGS_BASE_IDX 1
+#define regCP_COHER_SIZE_HI 0x208c
+#define regCP_COHER_SIZE_HI_BASE_IDX 1
+#define regCP_PFP_IB_CONTROL 0x208d
+#define regCP_PFP_IB_CONTROL_BASE_IDX 1
+#define regCP_PFP_LOAD_CONTROL 0x208e
+#define regCP_PFP_LOAD_CONTROL_BASE_IDX 1
+#define regCP_SCRATCH_INDEX 0x208f
+#define regCP_SCRATCH_INDEX_BASE_IDX 1
+#define regCP_SCRATCH_DATA 0x2090
+#define regCP_SCRATCH_DATA_BASE_IDX 1
+#define regCP_RB_OFFSET 0x2091
+#define regCP_RB_OFFSET_BASE_IDX 1
+#define regCP_IB2_OFFSET 0x2093
+#define regCP_IB2_OFFSET_BASE_IDX 1
+#define regCP_IB2_PREAMBLE_BEGIN 0x2096
+#define regCP_IB2_PREAMBLE_BEGIN_BASE_IDX 1
+#define regCP_IB2_PREAMBLE_END 0x2097
+#define regCP_IB2_PREAMBLE_END_BASE_IDX 1
+#define regCP_CE_IB1_OFFSET 0x2098
+#define regCP_CE_IB1_OFFSET_BASE_IDX 1
+#define regCP_CE_IB2_OFFSET 0x2099
+#define regCP_CE_IB2_OFFSET_BASE_IDX 1
+#define regCP_CE_COUNTER 0x209a
+#define regCP_CE_COUNTER_BASE_IDX 1
+#define regCP_CE_RB_OFFSET 0x209b
+#define regCP_CE_RB_OFFSET_BASE_IDX 1
+#define regCP_CE_INIT_CMD_BUFSZ 0x20bd
+#define regCP_CE_INIT_CMD_BUFSZ_BASE_IDX 1
+#define regCP_CE_IB1_CMD_BUFSZ 0x20be
+#define regCP_CE_IB1_CMD_BUFSZ_BASE_IDX 1
+#define regCP_CE_IB2_CMD_BUFSZ 0x20bf
+#define regCP_CE_IB2_CMD_BUFSZ_BASE_IDX 1
+#define regCP_IB2_CMD_BUFSZ 0x20c1
+#define regCP_IB2_CMD_BUFSZ_BASE_IDX 1
+#define regCP_ST_CMD_BUFSZ 0x20c2
+#define regCP_ST_CMD_BUFSZ_BASE_IDX 1
+#define regCP_CE_INIT_BASE_LO 0x20c3
+#define regCP_CE_INIT_BASE_LO_BASE_IDX 1
+#define regCP_CE_INIT_BASE_HI 0x20c4
+#define regCP_CE_INIT_BASE_HI_BASE_IDX 1
+#define regCP_CE_INIT_BUFSZ 0x20c5
+#define regCP_CE_INIT_BUFSZ_BASE_IDX 1
+#define regCP_CE_IB1_BASE_LO 0x20c6
+#define regCP_CE_IB1_BASE_LO_BASE_IDX 1
+#define regCP_CE_IB1_BASE_HI 0x20c7
+#define regCP_CE_IB1_BASE_HI_BASE_IDX 1
+#define regCP_CE_IB1_BUFSZ 0x20c8
+#define regCP_CE_IB1_BUFSZ_BASE_IDX 1
+#define regCP_CE_IB2_BASE_LO 0x20c9
+#define regCP_CE_IB2_BASE_LO_BASE_IDX 1
+#define regCP_CE_IB2_BASE_HI 0x20ca
+#define regCP_CE_IB2_BASE_HI_BASE_IDX 1
+#define regCP_CE_IB2_BUFSZ 0x20cb
+#define regCP_CE_IB2_BUFSZ_BASE_IDX 1
+#define regCP_IB2_BASE_LO 0x20cf
+#define regCP_IB2_BASE_LO_BASE_IDX 1
+#define regCP_IB2_BASE_HI 0x20d0
+#define regCP_IB2_BASE_HI_BASE_IDX 1
+#define regCP_IB2_BUFSZ 0x20d1
+#define regCP_IB2_BUFSZ_BASE_IDX 1
+#define regCP_ST_BASE_LO 0x20d2
+#define regCP_ST_BASE_LO_BASE_IDX 1
+#define regCP_ST_BASE_HI 0x20d3
+#define regCP_ST_BASE_HI_BASE_IDX 1
+#define regCP_ST_BUFSZ 0x20d4
+#define regCP_ST_BUFSZ_BASE_IDX 1
+#define regCP_EOP_DONE_EVENT_CNTL 0x20d5
+#define regCP_EOP_DONE_EVENT_CNTL_BASE_IDX 1
+#define regCP_EOP_DONE_DATA_CNTL 0x20d6
+#define regCP_EOP_DONE_DATA_CNTL_BASE_IDX 1
+#define regCP_EOP_DONE_CNTX_ID 0x20d7
+#define regCP_EOP_DONE_CNTX_ID_BASE_IDX 1
+#define regCP_PFP_COMPLETION_STATUS 0x20ec
+#define regCP_PFP_COMPLETION_STATUS_BASE_IDX 1
+#define regCP_CE_COMPLETION_STATUS 0x20ed
+#define regCP_CE_COMPLETION_STATUS_BASE_IDX 1
+#define regCP_PRED_NOT_VISIBLE 0x20ee
+#define regCP_PRED_NOT_VISIBLE_BASE_IDX 1
+#define regCP_PFP_METADATA_BASE_ADDR 0x20f0
+#define regCP_PFP_METADATA_BASE_ADDR_BASE_IDX 1
+#define regCP_PFP_METADATA_BASE_ADDR_HI 0x20f1
+#define regCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX 1
+#define regCP_CE_METADATA_BASE_ADDR 0x20f2
+#define regCP_CE_METADATA_BASE_ADDR_BASE_IDX 1
+#define regCP_CE_METADATA_BASE_ADDR_HI 0x20f3
+#define regCP_CE_METADATA_BASE_ADDR_HI_BASE_IDX 1
+#define regCP_DRAW_INDX_INDR_ADDR 0x20f4
+#define regCP_DRAW_INDX_INDR_ADDR_BASE_IDX 1
+#define regCP_DRAW_INDX_INDR_ADDR_HI 0x20f5
+#define regCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX 1
+#define regCP_DISPATCH_INDR_ADDR 0x20f6
+#define regCP_DISPATCH_INDR_ADDR_BASE_IDX 1
+#define regCP_DISPATCH_INDR_ADDR_HI 0x20f7
+#define regCP_DISPATCH_INDR_ADDR_HI_BASE_IDX 1
+#define regCP_INDEX_BASE_ADDR 0x20f8
+#define regCP_INDEX_BASE_ADDR_BASE_IDX 1
+#define regCP_INDEX_BASE_ADDR_HI 0x20f9
+#define regCP_INDEX_BASE_ADDR_HI_BASE_IDX 1
+#define regCP_INDEX_TYPE 0x20fa
+#define regCP_INDEX_TYPE_BASE_IDX 1
+#define regCP_GDS_BKUP_ADDR 0x20fb
+#define regCP_GDS_BKUP_ADDR_BASE_IDX 1
+#define regCP_GDS_BKUP_ADDR_HI 0x20fc
+#define regCP_GDS_BKUP_ADDR_HI_BASE_IDX 1
+#define regCP_SAMPLE_STATUS 0x20fd
+#define regCP_SAMPLE_STATUS_BASE_IDX 1
+#define regCP_ME_COHER_CNTL 0x20fe
+#define regCP_ME_COHER_CNTL_BASE_IDX 1
+#define regCP_ME_COHER_SIZE 0x20ff
+#define regCP_ME_COHER_SIZE_BASE_IDX 1
+#define regCP_ME_COHER_SIZE_HI 0x2100
+#define regCP_ME_COHER_SIZE_HI_BASE_IDX 1
+#define regCP_ME_COHER_BASE 0x2101
+#define regCP_ME_COHER_BASE_BASE_IDX 1
+#define regCP_ME_COHER_BASE_HI 0x2102
+#define regCP_ME_COHER_BASE_HI_BASE_IDX 1
+#define regCP_ME_COHER_STATUS 0x2103
+#define regCP_ME_COHER_STATUS_BASE_IDX 1
+#define regRLC_GPM_PERF_COUNT_0 0x2140
+#define regRLC_GPM_PERF_COUNT_0_BASE_IDX 1
+#define regRLC_GPM_PERF_COUNT_1 0x2141
+#define regRLC_GPM_PERF_COUNT_1_BASE_IDX 1
+#define regGRBM_GFX_INDEX 0x2200
+#define regGRBM_GFX_INDEX_BASE_IDX 1
+#define regVGT_GSVS_RING_SIZE 0x2241
+#define regVGT_GSVS_RING_SIZE_BASE_IDX 1
+#define regVGT_PRIMITIVE_TYPE 0x2242
+#define regVGT_PRIMITIVE_TYPE_BASE_IDX 1
+#define regVGT_INDEX_TYPE 0x2243
+#define regVGT_INDEX_TYPE_BASE_IDX 1
+#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0x2244
+#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_0_BASE_IDX 1
+#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0x2245
+#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_1_BASE_IDX 1
+#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0x2246
+#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_2_BASE_IDX 1
+#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0x2247
+#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_3_BASE_IDX 1
+#define regVGT_MAX_VTX_INDX 0x2248
+#define regVGT_MAX_VTX_INDX_BASE_IDX 1
+#define regVGT_MIN_VTX_INDX 0x2249
+#define regVGT_MIN_VTX_INDX_BASE_IDX 1
+#define regVGT_INDX_OFFSET 0x224a
+#define regVGT_INDX_OFFSET_BASE_IDX 1
+#define regVGT_MULTI_PRIM_IB_RESET_EN 0x224b
+#define regVGT_MULTI_PRIM_IB_RESET_EN_BASE_IDX 1
+#define regVGT_NUM_INDICES 0x224c
+#define regVGT_NUM_INDICES_BASE_IDX 1
+#define regVGT_NUM_INSTANCES 0x224d
+#define regVGT_NUM_INSTANCES_BASE_IDX 1
+#define regVGT_TF_RING_SIZE 0x224e
+#define regVGT_TF_RING_SIZE_BASE_IDX 1
+#define regVGT_HS_OFFCHIP_PARAM 0x224f
+#define regVGT_HS_OFFCHIP_PARAM_BASE_IDX 1
+#define regVGT_TF_MEMORY_BASE 0x2250
+#define regVGT_TF_MEMORY_BASE_BASE_IDX 1
+#define regVGT_TF_MEMORY_BASE_HI 0x2251
+#define regVGT_TF_MEMORY_BASE_HI_BASE_IDX 1
+#define regWD_POS_BUF_BASE 0x2252
+#define regWD_POS_BUF_BASE_BASE_IDX 1
+#define regWD_POS_BUF_BASE_HI 0x2253
+#define regWD_POS_BUF_BASE_HI_BASE_IDX 1
+#define regWD_CNTL_SB_BUF_BASE 0x2254
+#define regWD_CNTL_SB_BUF_BASE_BASE_IDX 1
+#define regWD_CNTL_SB_BUF_BASE_HI 0x2255
+#define regWD_CNTL_SB_BUF_BASE_HI_BASE_IDX 1
+#define regWD_INDEX_BUF_BASE 0x2256
+#define regWD_INDEX_BUF_BASE_BASE_IDX 1
+#define regWD_INDEX_BUF_BASE_HI 0x2257
+#define regWD_INDEX_BUF_BASE_HI_BASE_IDX 1
+#define regIA_MULTI_VGT_PARAM 0x2258
+#define regIA_MULTI_VGT_PARAM_BASE_IDX 1
+#define regVGT_INSTANCE_BASE_ID 0x225a
+#define regVGT_INSTANCE_BASE_ID_BASE_IDX 1
+#define regPA_SU_LINE_STIPPLE_VALUE 0x2280
+#define regPA_SU_LINE_STIPPLE_VALUE_BASE_IDX 1
+#define regPA_SC_LINE_STIPPLE_STATE 0x2281
+#define regPA_SC_LINE_STIPPLE_STATE_BASE_IDX 1
+#define regPA_SC_SCREEN_EXTENT_MIN_0 0x2284
+#define regPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX 1
+#define regPA_SC_SCREEN_EXTENT_MAX_0 0x2285
+#define regPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX 1
+#define regPA_SC_SCREEN_EXTENT_MIN_1 0x2286
+#define regPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX 1
+#define regPA_SC_SCREEN_EXTENT_MAX_1 0x228b
+#define regPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX 1
+#define regPA_SC_P3D_TRAP_SCREEN_HV_EN 0x22a0
+#define regPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX 1
+#define regPA_SC_P3D_TRAP_SCREEN_H 0x22a1
+#define regPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX 1
+#define regPA_SC_P3D_TRAP_SCREEN_V 0x22a2
+#define regPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX 1
+#define regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0x22a3
+#define regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1
+#define regPA_SC_P3D_TRAP_SCREEN_COUNT 0x22a4
+#define regPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX 1
+#define regPA_SC_HP3D_TRAP_SCREEN_HV_EN 0x22a8
+#define regPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX 1
+#define regPA_SC_HP3D_TRAP_SCREEN_H 0x22a9
+#define regPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX 1
+#define regPA_SC_HP3D_TRAP_SCREEN_V 0x22aa
+#define regPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX 1
+#define regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0x22ab
+#define regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1
+#define regPA_SC_HP3D_TRAP_SCREEN_COUNT 0x22ac
+#define regPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX 1
+#define regPA_SC_TRAP_SCREEN_HV_EN 0x22b0
+#define regPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX 1
+#define regPA_SC_TRAP_SCREEN_H 0x22b1
+#define regPA_SC_TRAP_SCREEN_H_BASE_IDX 1
+#define regPA_SC_TRAP_SCREEN_V 0x22b2
+#define regPA_SC_TRAP_SCREEN_V_BASE_IDX 1
+#define regPA_SC_TRAP_SCREEN_OCCURRENCE 0x22b3
+#define regPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1
+#define regPA_SC_TRAP_SCREEN_COUNT 0x22b4
+#define regPA_SC_TRAP_SCREEN_COUNT_BASE_IDX 1
+#define regPA_STATE_STEREO_X 0x22b5
+#define regPA_STATE_STEREO_X_BASE_IDX 1
+#define regSQ_THREAD_TRACE_BASE 0x2330
+#define regSQ_THREAD_TRACE_BASE_BASE_IDX 1
+#define regSQ_THREAD_TRACE_SIZE 0x2331
+#define regSQ_THREAD_TRACE_SIZE_BASE_IDX 1
+#define regSQ_THREAD_TRACE_MASK 0x2332
+#define regSQ_THREAD_TRACE_MASK_BASE_IDX 1
+#define regSQ_THREAD_TRACE_TOKEN_MASK 0x2333
+#define regSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX 1
+#define regSQ_THREAD_TRACE_PERF_MASK 0x2334
+#define regSQ_THREAD_TRACE_PERF_MASK_BASE_IDX 1
+#define regSQ_THREAD_TRACE_CTRL 0x2335
+#define regSQ_THREAD_TRACE_CTRL_BASE_IDX 1
+#define regSQ_THREAD_TRACE_MODE 0x2336
+#define regSQ_THREAD_TRACE_MODE_BASE_IDX 1
+#define regSQ_THREAD_TRACE_BASE2 0x2337
+#define regSQ_THREAD_TRACE_BASE2_BASE_IDX 1
+#define regSQ_THREAD_TRACE_TOKEN_MASK2 0x2338
+#define regSQ_THREAD_TRACE_TOKEN_MASK2_BASE_IDX 1
+#define regSQ_THREAD_TRACE_WPTR 0x2339
+#define regSQ_THREAD_TRACE_WPTR_BASE_IDX 1
+#define regSQ_THREAD_TRACE_STATUS 0x233a
+#define regSQ_THREAD_TRACE_STATUS_BASE_IDX 1
+#define regSQ_THREAD_TRACE_HIWATER 0x233b
+#define regSQ_THREAD_TRACE_HIWATER_BASE_IDX 1
+#define regSQ_THREAD_TRACE_CNTR 0x233c
+#define regSQ_THREAD_TRACE_CNTR_BASE_IDX 1
+#define regSQ_THREAD_TRACE_USERDATA_0 0x2340
+#define regSQ_THREAD_TRACE_USERDATA_0_BASE_IDX 1
+#define regSQ_THREAD_TRACE_USERDATA_1 0x2341
+#define regSQ_THREAD_TRACE_USERDATA_1_BASE_IDX 1
+#define regSQ_THREAD_TRACE_USERDATA_2 0x2342
+#define regSQ_THREAD_TRACE_USERDATA_2_BASE_IDX 1
+#define regSQ_THREAD_TRACE_USERDATA_3 0x2343
+#define regSQ_THREAD_TRACE_USERDATA_3_BASE_IDX 1
+#define regSQC_CACHES 0x2348
+#define regSQC_CACHES_BASE_IDX 1
+#define regSQC_WRITEBACK 0x2349
+#define regSQC_WRITEBACK_BASE_IDX 1
+#define regDB_OCCLUSION_COUNT0_LOW 0x23c0
+#define regDB_OCCLUSION_COUNT0_LOW_BASE_IDX 1
+#define regDB_OCCLUSION_COUNT0_HI 0x23c1
+#define regDB_OCCLUSION_COUNT0_HI_BASE_IDX 1
+#define regDB_OCCLUSION_COUNT1_LOW 0x23c2
+#define regDB_OCCLUSION_COUNT1_LOW_BASE_IDX 1
+#define regDB_OCCLUSION_COUNT1_HI 0x23c3
+#define regDB_OCCLUSION_COUNT1_HI_BASE_IDX 1
+#define regDB_OCCLUSION_COUNT2_LOW 0x23c4
+#define regDB_OCCLUSION_COUNT2_LOW_BASE_IDX 1
+#define regDB_OCCLUSION_COUNT2_HI 0x23c5
+#define regDB_OCCLUSION_COUNT2_HI_BASE_IDX 1
+#define regDB_OCCLUSION_COUNT3_LOW 0x23c6
+#define regDB_OCCLUSION_COUNT3_LOW_BASE_IDX 1
+#define regDB_OCCLUSION_COUNT3_HI 0x23c7
+#define regDB_OCCLUSION_COUNT3_HI_BASE_IDX 1
+#define regDB_ZPASS_COUNT_LOW 0x23fe
+#define regDB_ZPASS_COUNT_LOW_BASE_IDX 1
+#define regDB_ZPASS_COUNT_HI 0x23ff
+#define regDB_ZPASS_COUNT_HI_BASE_IDX 1
+#define regGDS_RD_ADDR 0x2400
+#define regGDS_RD_ADDR_BASE_IDX 1
+#define regGDS_RD_DATA 0x2401
+#define regGDS_RD_DATA_BASE_IDX 1
+#define regGDS_RD_BURST_ADDR 0x2402
+#define regGDS_RD_BURST_ADDR_BASE_IDX 1
+#define regGDS_RD_BURST_COUNT 0x2403
+#define regGDS_RD_BURST_COUNT_BASE_IDX 1
+#define regGDS_RD_BURST_DATA 0x2404
+#define regGDS_RD_BURST_DATA_BASE_IDX 1
+#define regGDS_WR_ADDR 0x2405
+#define regGDS_WR_ADDR_BASE_IDX 1
+#define regGDS_WR_DATA 0x2406
+#define regGDS_WR_DATA_BASE_IDX 1
+#define regGDS_WR_BURST_ADDR 0x2407
+#define regGDS_WR_BURST_ADDR_BASE_IDX 1
+#define regGDS_WR_BURST_DATA 0x2408
+#define regGDS_WR_BURST_DATA_BASE_IDX 1
+#define regGDS_WRITE_COMPLETE 0x2409
+#define regGDS_WRITE_COMPLETE_BASE_IDX 1
+#define regGDS_ATOM_CNTL 0x240a
+#define regGDS_ATOM_CNTL_BASE_IDX 1
+#define regGDS_ATOM_COMPLETE 0x240b
+#define regGDS_ATOM_COMPLETE_BASE_IDX 1
+#define regGDS_ATOM_BASE 0x240c
+#define regGDS_ATOM_BASE_BASE_IDX 1
+#define regGDS_ATOM_SIZE 0x240d
+#define regGDS_ATOM_SIZE_BASE_IDX 1
+#define regGDS_ATOM_OFFSET0 0x240e
+#define regGDS_ATOM_OFFSET0_BASE_IDX 1
+#define regGDS_ATOM_OFFSET1 0x240f
+#define regGDS_ATOM_OFFSET1_BASE_IDX 1
+#define regGDS_ATOM_DST 0x2410
+#define regGDS_ATOM_DST_BASE_IDX 1
+#define regGDS_ATOM_OP 0x2411
+#define regGDS_ATOM_OP_BASE_IDX 1
+#define regGDS_ATOM_SRC0 0x2412
+#define regGDS_ATOM_SRC0_BASE_IDX 1
+#define regGDS_ATOM_SRC0_U 0x2413
+#define regGDS_ATOM_SRC0_U_BASE_IDX 1
+#define regGDS_ATOM_SRC1 0x2414
+#define regGDS_ATOM_SRC1_BASE_IDX 1
+#define regGDS_ATOM_SRC1_U 0x2415
+#define regGDS_ATOM_SRC1_U_BASE_IDX 1
+#define regGDS_ATOM_READ0 0x2416
+#define regGDS_ATOM_READ0_BASE_IDX 1
+#define regGDS_ATOM_READ0_U 0x2417
+#define regGDS_ATOM_READ0_U_BASE_IDX 1
+#define regGDS_ATOM_READ1 0x2418
+#define regGDS_ATOM_READ1_BASE_IDX 1
+#define regGDS_ATOM_READ1_U 0x2419
+#define regGDS_ATOM_READ1_U_BASE_IDX 1
+#define regGDS_GWS_RESOURCE_CNTL 0x241a
+#define regGDS_GWS_RESOURCE_CNTL_BASE_IDX 1
+#define regGDS_GWS_RESOURCE 0x241b
+#define regGDS_GWS_RESOURCE_BASE_IDX 1
+#define regGDS_GWS_RESOURCE_CNT 0x241c
+#define regGDS_GWS_RESOURCE_CNT_BASE_IDX 1
+#define regGDS_OA_CNTL 0x241d
+#define regGDS_OA_CNTL_BASE_IDX 1
+#define regGDS_OA_COUNTER 0x241e
+#define regGDS_OA_COUNTER_BASE_IDX 1
+#define regGDS_OA_ADDRESS 0x241f
+#define regGDS_OA_ADDRESS_BASE_IDX 1
+#define regGDS_OA_INCDEC 0x2420
+#define regGDS_OA_INCDEC_BASE_IDX 1
+#define regGDS_OA_RING_SIZE 0x2421
+#define regGDS_OA_RING_SIZE_BASE_IDX 1
+#define regSPI_CONFIG_CNTL 0x2440
+#define regSPI_CONFIG_CNTL_BASE_IDX 1
+#define regSPI_CONFIG_CNTL_1 0x2441
+#define regSPI_CONFIG_CNTL_1_BASE_IDX 1
+#define regSPI_CONFIG_CNTL_2 0x2442
+#define regSPI_CONFIG_CNTL_2_BASE_IDX 1
+#define regSPI_WAVE_LIMIT_CNTL 0x2443
+#define regSPI_WAVE_LIMIT_CNTL_BASE_IDX 1
+
+
+// addressBlock: gc_grbmdec
+// base address: 0x8000
+#define regGRBM_CNTL 0x0000
+#define regGRBM_CNTL_BASE_IDX 0
+#define regGRBM_SKEW_CNTL 0x0001
+#define regGRBM_SKEW_CNTL_BASE_IDX 0
+#define regGRBM_STATUS2 0x0002
+#define regGRBM_STATUS2_BASE_IDX 0
+#define regGRBM_PWR_CNTL 0x0003
+#define regGRBM_PWR_CNTL_BASE_IDX 0
+#define regGRBM_STATUS 0x0004
+#define regGRBM_STATUS_BASE_IDX 0
+#define regGRBM_STATUS_SE0 0x0005
+#define regGRBM_STATUS_SE0_BASE_IDX 0
+#define regGRBM_STATUS_SE1 0x0006
+#define regGRBM_STATUS_SE1_BASE_IDX 0
+#define regGRBM_SOFT_RESET 0x0008
+#define regGRBM_SOFT_RESET_BASE_IDX 0
+#define regGRBM_GFX_CLKEN_CNTL 0x000c
+#define regGRBM_GFX_CLKEN_CNTL_BASE_IDX 0
+#define regGRBM_WAIT_IDLE_CLOCKS 0x000d
+#define regGRBM_WAIT_IDLE_CLOCKS_BASE_IDX 0
+#define regGRBM_STATUS_SE2 0x000e
+#define regGRBM_STATUS_SE2_BASE_IDX 0
+#define regGRBM_STATUS_SE3 0x000f
+#define regGRBM_STATUS_SE3_BASE_IDX 0
+#define regGRBM_READ_ERROR 0x0016
+#define regGRBM_READ_ERROR_BASE_IDX 0
+#define regGRBM_READ_ERROR2 0x0017
+#define regGRBM_READ_ERROR2_BASE_IDX 0
+#define regGRBM_INT_CNTL 0x0018
+#define regGRBM_INT_CNTL_BASE_IDX 0
+#define regGRBM_TRAP_OP 0x0019
+#define regGRBM_TRAP_OP_BASE_IDX 0
+#define regGRBM_TRAP_ADDR 0x001a
+#define regGRBM_TRAP_ADDR_BASE_IDX 0
+#define regGRBM_TRAP_ADDR_MSK 0x001b
+#define regGRBM_TRAP_ADDR_MSK_BASE_IDX 0
+#define regGRBM_TRAP_WD 0x001c
+#define regGRBM_TRAP_WD_BASE_IDX 0
+#define regGRBM_TRAP_WD_MSK 0x001d
+#define regGRBM_TRAP_WD_MSK_BASE_IDX 0
+#define regGRBM_WRITE_ERROR 0x001f
+#define regGRBM_WRITE_ERROR_BASE_IDX 0
+#define regGRBM_CHIP_REVISION 0x0021
+#define regGRBM_CHIP_REVISION_BASE_IDX 0
+#define regGRBM_GFX_CNTL 0x0022
+#define regGRBM_GFX_CNTL_BASE_IDX 0
+#define regGRBM_IH_CREDIT 0x0024
+#define regGRBM_IH_CREDIT_BASE_IDX 0
+#define regGRBM_PWR_CNTL2 0x0025
+#define regGRBM_PWR_CNTL2_BASE_IDX 0
+#define regGRBM_UTCL2_INVAL_RANGE_START 0x0026
+#define regGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX 0
+#define regGRBM_UTCL2_INVAL_RANGE_END 0x0027
+#define regGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX 0
+#define regGRBM_CHICKEN_BITS 0x0029
+#define regGRBM_CHICKEN_BITS_BASE_IDX 0
+#define regGRBM_FENCE_RANGE0 0x002a
+#define regGRBM_FENCE_RANGE0_BASE_IDX 0
+#define regGRBM_FENCE_RANGE1 0x002b
+#define regGRBM_FENCE_RANGE1_BASE_IDX 0
+#define regGRBM_NOWHERE 0x003f
+#define regGRBM_NOWHERE_BASE_IDX 0
+#define regGRBM_SCRATCH_REG0 0x0040
+#define regGRBM_SCRATCH_REG0_BASE_IDX 0
+#define regGRBM_SCRATCH_REG1 0x0041
+#define regGRBM_SCRATCH_REG1_BASE_IDX 0
+#define regGRBM_SCRATCH_REG2 0x0042
+#define regGRBM_SCRATCH_REG2_BASE_IDX 0
+#define regGRBM_SCRATCH_REG3 0x0043
+#define regGRBM_SCRATCH_REG3_BASE_IDX 0
+#define regGRBM_SCRATCH_REG4 0x0044
+#define regGRBM_SCRATCH_REG4_BASE_IDX 0
+#define regGRBM_SCRATCH_REG5 0x0045
+#define regGRBM_SCRATCH_REG5_BASE_IDX 0
+#define regGRBM_SCRATCH_REG6 0x0046
+#define regGRBM_SCRATCH_REG6_BASE_IDX 0
+#define regGRBM_SCRATCH_REG7 0x0047
+#define regGRBM_SCRATCH_REG7_BASE_IDX 0
+#define regVIOLATION_DATA_ASYNC_VF_PROG 0x0048
+#define regVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX 0
+
+
+// addressBlock: gc_hypdec
+// base address: 0x3e000
+#define regCP_HYP_PFP_UCODE_ADDR 0x5814
+#define regCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1
+#define regCP_PFP_UCODE_ADDR 0x5814
+#define regCP_PFP_UCODE_ADDR_BASE_IDX 1
+#define regCP_HYP_PFP_UCODE_DATA 0x5815
+#define regCP_HYP_PFP_UCODE_DATA_BASE_IDX 1
+#define regCP_PFP_UCODE_DATA 0x5815
+#define regCP_PFP_UCODE_DATA_BASE_IDX 1
+#define regCP_HYP_ME_UCODE_ADDR 0x5816
+#define regCP_HYP_ME_UCODE_ADDR_BASE_IDX 1
+#define regCP_ME_RAM_RADDR 0x5816
+#define regCP_ME_RAM_RADDR_BASE_IDX 1
+#define regCP_ME_RAM_WADDR 0x5816
+#define regCP_ME_RAM_WADDR_BASE_IDX 1
+#define regCP_HYP_ME_UCODE_DATA 0x5817
+#define regCP_HYP_ME_UCODE_DATA_BASE_IDX 1
+#define regCP_ME_RAM_DATA 0x5817
+#define regCP_ME_RAM_DATA_BASE_IDX 1
+#define regCP_CE_UCODE_ADDR 0x5818
+#define regCP_CE_UCODE_ADDR_BASE_IDX 1
+#define regCP_HYP_CE_UCODE_ADDR 0x5818
+#define regCP_HYP_CE_UCODE_ADDR_BASE_IDX 1
+#define regCP_CE_UCODE_DATA 0x5819
+#define regCP_CE_UCODE_DATA_BASE_IDX 1
+#define regCP_HYP_CE_UCODE_DATA 0x5819
+#define regCP_HYP_CE_UCODE_DATA_BASE_IDX 1
+#define regCP_HYP_MEC1_UCODE_ADDR 0x581a
+#define regCP_HYP_MEC1_UCODE_ADDR_BASE_IDX 1
+#define regCP_MEC_ME1_UCODE_ADDR 0x581a
+#define regCP_MEC_ME1_UCODE_ADDR_BASE_IDX 1
+#define regCP_HYP_MEC1_UCODE_DATA 0x581b
+#define regCP_HYP_MEC1_UCODE_DATA_BASE_IDX 1
+#define regCP_MEC_ME1_UCODE_DATA 0x581b
+#define regCP_MEC_ME1_UCODE_DATA_BASE_IDX 1
+#define regCP_HYP_MEC2_UCODE_ADDR 0x581c
+#define regCP_HYP_MEC2_UCODE_ADDR_BASE_IDX 1
+#define regCP_MEC_ME2_UCODE_ADDR 0x581c
+#define regCP_MEC_ME2_UCODE_ADDR_BASE_IDX 1
+#define regCP_HYP_MEC2_UCODE_DATA 0x581d
+#define regCP_HYP_MEC2_UCODE_DATA_BASE_IDX 1
+#define regCP_MEC_ME2_UCODE_DATA 0x581d
+#define regCP_MEC_ME2_UCODE_DATA_BASE_IDX 1
+#define regRLC_GPM_UCODE_ADDR 0x583c
+#define regRLC_GPM_UCODE_ADDR_BASE_IDX 1
+#define regRLC_GPM_UCODE_DATA 0x583d
+#define regRLC_GPM_UCODE_DATA_BASE_IDX 1
+#define regGRBM_GFX_INDEX_SR_SELECT 0x5a00
+#define regGRBM_GFX_INDEX_SR_SELECT_BASE_IDX 1
+#define regGRBM_GFX_INDEX_SR_DATA 0x5a01
+#define regGRBM_GFX_INDEX_SR_DATA_BASE_IDX 1
+#define regGRBM_GFX_CNTL_SR_SELECT 0x5a02
+#define regGRBM_GFX_CNTL_SR_SELECT_BASE_IDX 1
+#define regGRBM_GFX_CNTL_SR_DATA 0x5a03
+#define regGRBM_GFX_CNTL_SR_DATA_BASE_IDX 1
+#define regGRBM_CAM_INDEX 0x5a04
+#define regGRBM_CAM_INDEX_BASE_IDX 1
+#define regGRBM_HYP_CAM_INDEX 0x5a04
+#define regGRBM_HYP_CAM_INDEX_BASE_IDX 1
+#define regGRBM_CAM_DATA 0x5a05
+#define regGRBM_CAM_DATA_BASE_IDX 1
+#define regGRBM_HYP_CAM_DATA 0x5a05
+#define regGRBM_HYP_CAM_DATA_BASE_IDX 1
+#define regRLC_GPU_IOV_VF_ENABLE 0x5b00
+#define regRLC_GPU_IOV_VF_ENABLE_BASE_IDX 1
+#define regRLC_GPU_IOV_CFG_REG6 0x5b06
+#define regRLC_GPU_IOV_CFG_REG6_BASE_IDX 1
+#define regRLC_GPU_IOV_CFG_REG8 0x5b20
+#define regRLC_GPU_IOV_CFG_REG8_BASE_IDX 1
+#define regRLC_RLCV_TIMER_INT_0 0x5b25
+#define regRLC_RLCV_TIMER_INT_0_BASE_IDX 1
+#define regRLC_RLCV_TIMER_CTRL 0x5b26
+#define regRLC_RLCV_TIMER_CTRL_BASE_IDX 1
+#define regRLC_RLCV_TIMER_STAT 0x5b27
+#define regRLC_RLCV_TIMER_STAT_BASE_IDX 1
+#define regRLC_GPU_IOV_VF_DOORBELL_STATUS 0x5b2a
+#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX 1
+#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET 0x5b2b
+#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX 1
+#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR 0x5b2c
+#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX 1
+#define regRLC_GPU_IOV_VF_MASK 0x5b2d
+#define regRLC_GPU_IOV_VF_MASK_BASE_IDX 1
+#define regRLC_HYP_SEMAPHORE_0 0x5b2e
+#define regRLC_HYP_SEMAPHORE_0_BASE_IDX 1
+#define regRLC_HYP_SEMAPHORE_1 0x5b2f
+#define regRLC_HYP_SEMAPHORE_1_BASE_IDX 1
+#define regRLC_CLK_CNTL 0x5b31
+#define regRLC_CLK_CNTL_BASE_IDX 1
+#define regRLC_GPU_IOV_SCH_BLOCK 0x5b34
+#define regRLC_GPU_IOV_SCH_BLOCK_BASE_IDX 1
+#define regRLC_GPU_IOV_CFG_REG1 0x5b35
+#define regRLC_GPU_IOV_CFG_REG1_BASE_IDX 1
+#define regRLC_GPU_IOV_CFG_REG2 0x5b36
+#define regRLC_GPU_IOV_CFG_REG2_BASE_IDX 1
+#define regRLC_GPU_IOV_VM_BUSY_STATUS 0x5b37
+#define regRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX 1
+#define regRLC_GPU_IOV_SCH_0 0x5b38
+#define regRLC_GPU_IOV_SCH_0_BASE_IDX 1
+#define regRLC_GPU_IOV_ACTIVE_FCN_ID 0x5b39
+#define regRLC_GPU_IOV_ACTIVE_FCN_ID_BASE_IDX 1
+#define regRLC_GPU_IOV_SCH_3 0x5b3a
+#define regRLC_GPU_IOV_SCH_3_BASE_IDX 1
+#define regRLC_GPU_IOV_SCH_1 0x5b3b
+#define regRLC_GPU_IOV_SCH_1_BASE_IDX 1
+#define regRLC_GPU_IOV_SCH_2 0x5b3c
+#define regRLC_GPU_IOV_SCH_2_BASE_IDX 1
+#define regRLC_GPU_IOV_INT_STAT 0x5b3f
+#define regRLC_GPU_IOV_INT_STAT_BASE_IDX 1
+#define regRLC_RLCV_TIMER_INT_1 0x5b40
+#define regRLC_RLCV_TIMER_INT_1_BASE_IDX 1
+#define regRLC_GPU_IOV_UCODE_ADDR 0x5b42
+#define regRLC_GPU_IOV_UCODE_ADDR_BASE_IDX 1
+#define regRLC_GPU_IOV_UCODE_DATA 0x5b43
+#define regRLC_GPU_IOV_UCODE_DATA_BASE_IDX 1
+#define regRLC_GPU_IOV_SCRATCH_ADDR 0x5b44
+#define regRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX 1
+#define regRLC_GPU_IOV_SCRATCH_DATA 0x5b45
+#define regRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX 1
+#define regRLC_GPU_IOV_F32_CNTL 0x5b46
+#define regRLC_GPU_IOV_F32_CNTL_BASE_IDX 1
+#define regRLC_GPU_IOV_F32_RESET 0x5b47
+#define regRLC_GPU_IOV_F32_RESET_BASE_IDX 1
+#define regRLC_GPU_IOV_SDMA0_STATUS 0x5b48
+#define regRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX 1
+#define regRLC_GPU_IOV_SDMA1_STATUS 0x5b49
+#define regRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX 1
+#define regRLC_GPU_IOV_VIRT_RESET_REQ 0x5b4c
+#define regRLC_GPU_IOV_VIRT_RESET_REQ_BASE_IDX 1
+#define regRLC_GPU_IOV_RLC_RESPONSE 0x5b4d
+#define regRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX 1
+#define regRLC_GPU_IOV_INT_DISABLE 0x5b4e
+#define regRLC_GPU_IOV_INT_DISABLE_BASE_IDX 1
+#define regRLC_GPU_IOV_INT_FORCE 0x5b4f
+#define regRLC_GPU_IOV_INT_FORCE_BASE_IDX 1
+#define regRLC_GPU_IOV_SDMA0_BUSY_STATUS 0x5b50
+#define regRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX 1
+#define regRLC_GPU_IOV_SDMA1_BUSY_STATUS 0x5b51
+#define regRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX 1
+#define regRLC_HYP_SEMAPHORE_2 0x5b52
+#define regRLC_HYP_SEMAPHORE_2_BASE_IDX 1
+#define regRLC_HYP_SEMAPHORE_3 0x5b53
+#define regRLC_HYP_SEMAPHORE_3_BASE_IDX 1
+#define regRLC_GPU_IOV_SDMA2_STATUS 0x5b54
+#define regRLC_GPU_IOV_SDMA2_STATUS_BASE_IDX 1
+#define regRLC_GPU_IOV_SDMA3_STATUS 0x5b55
+#define regRLC_GPU_IOV_SDMA3_STATUS_BASE_IDX 1
+#define regRLC_GPU_IOV_SDMA4_STATUS 0x5b56
+#define regRLC_GPU_IOV_SDMA4_STATUS_BASE_IDX 1
+#define regRLC_GPU_IOV_SDMA5_STATUS 0x5b57
+#define regRLC_GPU_IOV_SDMA5_STATUS_BASE_IDX 1
+#define regRLC_GPU_IOV_SDMA6_STATUS 0x5b58
+#define regRLC_GPU_IOV_SDMA6_STATUS_BASE_IDX 1
+#define regRLC_GPU_IOV_SDMA7_STATUS 0x5b59
+#define regRLC_GPU_IOV_SDMA7_STATUS_BASE_IDX 1
+#define regRLC_GPU_IOV_SDMA2_BUSY_STATUS 0x5b5a
+#define regRLC_GPU_IOV_SDMA2_BUSY_STATUS_BASE_IDX 1
+#define regRLC_GPU_IOV_SDMA3_BUSY_STATUS 0x5b5b
+#define regRLC_GPU_IOV_SDMA3_BUSY_STATUS_BASE_IDX 1
+#define regRLC_GPU_IOV_SDMA4_BUSY_STATUS 0x5b5c
+#define regRLC_GPU_IOV_SDMA4_BUSY_STATUS_BASE_IDX 1
+#define regRLC_GPU_IOV_SDMA5_BUSY_STATUS 0x5b5d
+#define regRLC_GPU_IOV_SDMA5_BUSY_STATUS_BASE_IDX 1
+#define regRLC_GPU_IOV_SDMA6_BUSY_STATUS 0x5b5e
+#define regRLC_GPU_IOV_SDMA6_BUSY_STATUS_BASE_IDX 1
+#define regRLC_GPU_IOV_SDMA7_BUSY_STATUS 0x5b5f
+#define regRLC_GPU_IOV_SDMA7_BUSY_STATUS_BASE_IDX 1
+
+
+// addressBlock: gc_padec
+// base address: 0x8800
+#define regVGT_VTX_VECT_EJECT_REG 0x022c
+#define regVGT_VTX_VECT_EJECT_REG_BASE_IDX 0
+#define regVGT_DMA_DATA_FIFO_DEPTH 0x022d
+#define regVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX 0
+#define regVGT_DMA_REQ_FIFO_DEPTH 0x022e
+#define regVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX 0
+#define regVGT_DRAW_INIT_FIFO_DEPTH 0x022f
+#define regVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX 0
+#define regVGT_LAST_COPY_STATE 0x0230
+#define regVGT_LAST_COPY_STATE_BASE_IDX 0
+#define regVGT_CACHE_INVALIDATION 0x0231
+#define regVGT_CACHE_INVALIDATION_BASE_IDX 0
+#define regVGT_STRMOUT_DELAY 0x0233
+#define regVGT_STRMOUT_DELAY_BASE_IDX 0
+#define regVGT_FIFO_DEPTHS 0x0234
+#define regVGT_FIFO_DEPTHS_BASE_IDX 0
+#define regVGT_GS_VERTEX_REUSE 0x0235
+#define regVGT_GS_VERTEX_REUSE_BASE_IDX 0
+#define regVGT_MC_LAT_CNTL 0x0236
+#define regVGT_MC_LAT_CNTL_BASE_IDX 0
+#define regIA_CNTL_STATUS 0x0237
+#define regIA_CNTL_STATUS_BASE_IDX 0
+#define regVGT_CNTL_STATUS 0x023c
+#define regVGT_CNTL_STATUS_BASE_IDX 0
+#define regWD_CNTL_STATUS 0x023f
+#define regWD_CNTL_STATUS_BASE_IDX 0
+#define regCC_GC_PRIM_CONFIG 0x0240
+#define regCC_GC_PRIM_CONFIG_BASE_IDX 0
+#define regGC_USER_PRIM_CONFIG 0x0241
+#define regGC_USER_PRIM_CONFIG_BASE_IDX 0
+#define regWD_QOS 0x0242
+#define regWD_QOS_BASE_IDX 0
+#define regWD_UTCL1_CNTL 0x0243
+#define regWD_UTCL1_CNTL_BASE_IDX 0
+#define regWD_UTCL1_STATUS 0x0244
+#define regWD_UTCL1_STATUS_BASE_IDX 0
+#define regIA_UTCL1_CNTL 0x0246
+#define regIA_UTCL1_CNTL_BASE_IDX 0
+#define regIA_UTCL1_STATUS 0x0247
+#define regIA_UTCL1_STATUS_BASE_IDX 0
+#define regVGT_SYS_CONFIG 0x0263
+#define regVGT_SYS_CONFIG_BASE_IDX 0
+#define regVGT_VS_MAX_WAVE_ID 0x0268
+#define regVGT_VS_MAX_WAVE_ID_BASE_IDX 0
+#define regVGT_GS_MAX_WAVE_ID 0x0269
+#define regVGT_GS_MAX_WAVE_ID_BASE_IDX 0
+#define regGFX_PIPE_CONTROL 0x026d
+#define regGFX_PIPE_CONTROL_BASE_IDX 0
+#define regCC_GC_SHADER_ARRAY_CONFIG 0x026f
+#define regCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX 0
+#define regGC_USER_SHADER_ARRAY_CONFIG 0x0270
+#define regGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX 0
+#define regVGT_DMA_PRIMITIVE_TYPE 0x0271
+#define regVGT_DMA_PRIMITIVE_TYPE_BASE_IDX 0
+#define regVGT_DMA_CONTROL 0x0272
+#define regVGT_DMA_CONTROL_BASE_IDX 0
+#define regVGT_DMA_LS_HS_CONFIG 0x0273
+#define regVGT_DMA_LS_HS_CONFIG_BASE_IDX 0
+#define regWD_BUF_RESOURCE_1 0x0276
+#define regWD_BUF_RESOURCE_1_BASE_IDX 0
+#define regWD_BUF_RESOURCE_2 0x0277
+#define regWD_BUF_RESOURCE_2_BASE_IDX 0
+#define regPA_CL_CNTL_STATUS 0x0284
+#define regPA_CL_CNTL_STATUS_BASE_IDX 0
+#define regPA_CL_ENHANCE 0x0285
+#define regPA_CL_ENHANCE_BASE_IDX 0
+#define regPA_SU_CNTL_STATUS 0x0294
+#define regPA_SU_CNTL_STATUS_BASE_IDX 0
+#define regPA_SC_FIFO_DEPTH_CNTL 0x0295
+#define regPA_SC_FIFO_DEPTH_CNTL_BASE_IDX 0
+#define regPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x02c0
+#define regPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0
+#define regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x02c1
+#define regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0
+#define regPA_SC_TRAP_SCREEN_HV_LOCK 0x02c2
+#define regPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX 0
+#define regPA_SC_FORCE_EOV_MAX_CNTS 0x02c9
+#define regPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX 0
+#define regPA_SC_BINNER_EVENT_CNTL_0 0x02cc
+#define regPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX 0
+#define regPA_SC_BINNER_EVENT_CNTL_1 0x02cd
+#define regPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX 0
+#define regPA_SC_BINNER_EVENT_CNTL_2 0x02ce
+#define regPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX 0
+#define regPA_SC_BINNER_EVENT_CNTL_3 0x02cf
+#define regPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX 0
+#define regPA_SC_BINNER_TIMEOUT_COUNTER 0x02d0
+#define regPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX 0
+#define regPA_SC_BINNER_PERF_CNTL_0 0x02d1
+#define regPA_SC_BINNER_PERF_CNTL_0_BASE_IDX 0
+#define regPA_SC_BINNER_PERF_CNTL_1 0x02d2
+#define regPA_SC_BINNER_PERF_CNTL_1_BASE_IDX 0
+#define regPA_SC_BINNER_PERF_CNTL_2 0x02d3
+#define regPA_SC_BINNER_PERF_CNTL_2_BASE_IDX 0
+#define regPA_SC_BINNER_PERF_CNTL_3 0x02d4
+#define regPA_SC_BINNER_PERF_CNTL_3_BASE_IDX 0
+#define regPA_SC_ENHANCE_2 0x02dc
+#define regPA_SC_ENHANCE_2_BASE_IDX 0
+#define regPA_SC_FIFO_SIZE 0x02f3
+#define regPA_SC_FIFO_SIZE_BASE_IDX 0
+#define regPA_SC_IF_FIFO_SIZE 0x02f5
+#define regPA_SC_IF_FIFO_SIZE_BASE_IDX 0
+#define regPA_SC_PKR_WAVE_TABLE_CNTL 0x02f8
+#define regPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX 0
+#define regPA_UTCL1_CNTL1 0x02f9
+#define regPA_UTCL1_CNTL1_BASE_IDX 0
+#define regPA_UTCL1_CNTL2 0x02fa
+#define regPA_UTCL1_CNTL2_BASE_IDX 0
+#define regPA_SIDEBAND_REQUEST_DELAYS 0x02fb
+#define regPA_SIDEBAND_REQUEST_DELAYS_BASE_IDX 0
+#define regPA_SC_ENHANCE 0x02fc
+#define regPA_SC_ENHANCE_BASE_IDX 0
+#define regPA_SC_ENHANCE_1 0x02fd
+#define regPA_SC_ENHANCE_1_BASE_IDX 0
+#define regPA_SC_DSM_CNTL 0x02fe
+#define regPA_SC_DSM_CNTL_BASE_IDX 0
+#define regPA_SC_TILE_STEERING_CREST_OVERRIDE 0x02ff
+#define regPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX 0
+
+
+// addressBlock: gc_perfddec
+// base address: 0x34000
+#define regCPG_PERFCOUNTER1_LO 0x3000
+#define regCPG_PERFCOUNTER1_LO_BASE_IDX 1
+#define regCPG_PERFCOUNTER1_HI 0x3001
+#define regCPG_PERFCOUNTER1_HI_BASE_IDX 1
+#define regCPG_PERFCOUNTER0_LO 0x3002
+#define regCPG_PERFCOUNTER0_LO_BASE_IDX 1
+#define regCPG_PERFCOUNTER0_HI 0x3003
+#define regCPG_PERFCOUNTER0_HI_BASE_IDX 1
+#define regCPC_PERFCOUNTER1_LO 0x3004
+#define regCPC_PERFCOUNTER1_LO_BASE_IDX 1
+#define regCPC_PERFCOUNTER1_HI 0x3005
+#define regCPC_PERFCOUNTER1_HI_BASE_IDX 1
+#define regCPC_PERFCOUNTER0_LO 0x3006
+#define regCPC_PERFCOUNTER0_LO_BASE_IDX 1
+#define regCPC_PERFCOUNTER0_HI 0x3007
+#define regCPC_PERFCOUNTER0_HI_BASE_IDX 1
+#define regCPF_PERFCOUNTER1_LO 0x3008
+#define regCPF_PERFCOUNTER1_LO_BASE_IDX 1
+#define regCPF_PERFCOUNTER1_HI 0x3009
+#define regCPF_PERFCOUNTER1_HI_BASE_IDX 1
+#define regCPF_PERFCOUNTER0_LO 0x300a
+#define regCPF_PERFCOUNTER0_LO_BASE_IDX 1
+#define regCPF_PERFCOUNTER0_HI 0x300b
+#define regCPF_PERFCOUNTER0_HI_BASE_IDX 1
+#define regCPF_LATENCY_STATS_DATA 0x300c
+#define regCPF_LATENCY_STATS_DATA_BASE_IDX 1
+#define regCPG_LATENCY_STATS_DATA 0x300d
+#define regCPG_LATENCY_STATS_DATA_BASE_IDX 1
+#define regCPC_LATENCY_STATS_DATA 0x300e
+#define regCPC_LATENCY_STATS_DATA_BASE_IDX 1
+#define regGRBM_PERFCOUNTER0_LO 0x3040
+#define regGRBM_PERFCOUNTER0_LO_BASE_IDX 1
+#define regGRBM_PERFCOUNTER0_HI 0x3041
+#define regGRBM_PERFCOUNTER0_HI_BASE_IDX 1
+#define regGRBM_PERFCOUNTER1_LO 0x3043
+#define regGRBM_PERFCOUNTER1_LO_BASE_IDX 1
+#define regGRBM_PERFCOUNTER1_HI 0x3044
+#define regGRBM_PERFCOUNTER1_HI_BASE_IDX 1
+#define regGRBM_SE0_PERFCOUNTER_LO 0x3045
+#define regGRBM_SE0_PERFCOUNTER_LO_BASE_IDX 1
+#define regGRBM_SE0_PERFCOUNTER_HI 0x3046
+#define regGRBM_SE0_PERFCOUNTER_HI_BASE_IDX 1
+#define regGRBM_SE1_PERFCOUNTER_LO 0x3047
+#define regGRBM_SE1_PERFCOUNTER_LO_BASE_IDX 1
+#define regGRBM_SE1_PERFCOUNTER_HI 0x3048
+#define regGRBM_SE1_PERFCOUNTER_HI_BASE_IDX 1
+#define regGRBM_SE2_PERFCOUNTER_LO 0x3049
+#define regGRBM_SE2_PERFCOUNTER_LO_BASE_IDX 1
+#define regGRBM_SE2_PERFCOUNTER_HI 0x304a
+#define regGRBM_SE2_PERFCOUNTER_HI_BASE_IDX 1
+#define regGRBM_SE3_PERFCOUNTER_LO 0x304b
+#define regGRBM_SE3_PERFCOUNTER_LO_BASE_IDX 1
+#define regGRBM_SE3_PERFCOUNTER_HI 0x304c
+#define regGRBM_SE3_PERFCOUNTER_HI_BASE_IDX 1
+#define regWD_PERFCOUNTER0_LO 0x3080
+#define regWD_PERFCOUNTER0_LO_BASE_IDX 1
+#define regWD_PERFCOUNTER0_HI 0x3081
+#define regWD_PERFCOUNTER0_HI_BASE_IDX 1
+#define regWD_PERFCOUNTER1_LO 0x3082
+#define regWD_PERFCOUNTER1_LO_BASE_IDX 1
+#define regWD_PERFCOUNTER1_HI 0x3083
+#define regWD_PERFCOUNTER1_HI_BASE_IDX 1
+#define regWD_PERFCOUNTER2_LO 0x3084
+#define regWD_PERFCOUNTER2_LO_BASE_IDX 1
+#define regWD_PERFCOUNTER2_HI 0x3085
+#define regWD_PERFCOUNTER2_HI_BASE_IDX 1
+#define regWD_PERFCOUNTER3_LO 0x3086
+#define regWD_PERFCOUNTER3_LO_BASE_IDX 1
+#define regWD_PERFCOUNTER3_HI 0x3087
+#define regWD_PERFCOUNTER3_HI_BASE_IDX 1
+#define regIA_PERFCOUNTER0_LO 0x3088
+#define regIA_PERFCOUNTER0_LO_BASE_IDX 1
+#define regIA_PERFCOUNTER0_HI 0x3089
+#define regIA_PERFCOUNTER0_HI_BASE_IDX 1
+#define regIA_PERFCOUNTER1_LO 0x308a
+#define regIA_PERFCOUNTER1_LO_BASE_IDX 1
+#define regIA_PERFCOUNTER1_HI 0x308b
+#define regIA_PERFCOUNTER1_HI_BASE_IDX 1
+#define regIA_PERFCOUNTER2_LO 0x308c
+#define regIA_PERFCOUNTER2_LO_BASE_IDX 1
+#define regIA_PERFCOUNTER2_HI 0x308d
+#define regIA_PERFCOUNTER2_HI_BASE_IDX 1
+#define regIA_PERFCOUNTER3_LO 0x308e
+#define regIA_PERFCOUNTER3_LO_BASE_IDX 1
+#define regIA_PERFCOUNTER3_HI 0x308f
+#define regIA_PERFCOUNTER3_HI_BASE_IDX 1
+#define regVGT_PERFCOUNTER0_LO 0x3090
+#define regVGT_PERFCOUNTER0_LO_BASE_IDX 1
+#define regVGT_PERFCOUNTER0_HI 0x3091
+#define regVGT_PERFCOUNTER0_HI_BASE_IDX 1
+#define regVGT_PERFCOUNTER1_LO 0x3092
+#define regVGT_PERFCOUNTER1_LO_BASE_IDX 1
+#define regVGT_PERFCOUNTER1_HI 0x3093
+#define regVGT_PERFCOUNTER1_HI_BASE_IDX 1
+#define regVGT_PERFCOUNTER2_LO 0x3094
+#define regVGT_PERFCOUNTER2_LO_BASE_IDX 1
+#define regVGT_PERFCOUNTER2_HI 0x3095
+#define regVGT_PERFCOUNTER2_HI_BASE_IDX 1
+#define regVGT_PERFCOUNTER3_LO 0x3096
+#define regVGT_PERFCOUNTER3_LO_BASE_IDX 1
+#define regVGT_PERFCOUNTER3_HI 0x3097
+#define regVGT_PERFCOUNTER3_HI_BASE_IDX 1
+#define regPA_SU_PERFCOUNTER0_LO 0x3100
+#define regPA_SU_PERFCOUNTER0_LO_BASE_IDX 1
+#define regPA_SU_PERFCOUNTER0_HI 0x3101
+#define regPA_SU_PERFCOUNTER0_HI_BASE_IDX 1
+#define regPA_SU_PERFCOUNTER1_LO 0x3102
+#define regPA_SU_PERFCOUNTER1_LO_BASE_IDX 1
+#define regPA_SU_PERFCOUNTER1_HI 0x3103
+#define regPA_SU_PERFCOUNTER1_HI_BASE_IDX 1
+#define regPA_SU_PERFCOUNTER2_LO 0x3104
+#define regPA_SU_PERFCOUNTER2_LO_BASE_IDX 1
+#define regPA_SU_PERFCOUNTER2_HI 0x3105
+#define regPA_SU_PERFCOUNTER2_HI_BASE_IDX 1
+#define regPA_SU_PERFCOUNTER3_LO 0x3106
+#define regPA_SU_PERFCOUNTER3_LO_BASE_IDX 1
+#define regPA_SU_PERFCOUNTER3_HI 0x3107
+#define regPA_SU_PERFCOUNTER3_HI_BASE_IDX 1
+#define regPA_SC_PERFCOUNTER0_LO 0x3140
+#define regPA_SC_PERFCOUNTER0_LO_BASE_IDX 1
+#define regPA_SC_PERFCOUNTER0_HI 0x3141
+#define regPA_SC_PERFCOUNTER0_HI_BASE_IDX 1
+#define regPA_SC_PERFCOUNTER1_LO 0x3142
+#define regPA_SC_PERFCOUNTER1_LO_BASE_IDX 1
+#define regPA_SC_PERFCOUNTER1_HI 0x3143
+#define regPA_SC_PERFCOUNTER1_HI_BASE_IDX 1
+#define regPA_SC_PERFCOUNTER2_LO 0x3144
+#define regPA_SC_PERFCOUNTER2_LO_BASE_IDX 1
+#define regPA_SC_PERFCOUNTER2_HI 0x3145
+#define regPA_SC_PERFCOUNTER2_HI_BASE_IDX 1
+#define regPA_SC_PERFCOUNTER3_LO 0x3146
+#define regPA_SC_PERFCOUNTER3_LO_BASE_IDX 1
+#define regPA_SC_PERFCOUNTER3_HI 0x3147
+#define regPA_SC_PERFCOUNTER3_HI_BASE_IDX 1
+#define regPA_SC_PERFCOUNTER4_LO 0x3148
+#define regPA_SC_PERFCOUNTER4_LO_BASE_IDX 1
+#define regPA_SC_PERFCOUNTER4_HI 0x3149
+#define regPA_SC_PERFCOUNTER4_HI_BASE_IDX 1
+#define regPA_SC_PERFCOUNTER5_LO 0x314a
+#define regPA_SC_PERFCOUNTER5_LO_BASE_IDX 1
+#define regPA_SC_PERFCOUNTER5_HI 0x314b
+#define regPA_SC_PERFCOUNTER5_HI_BASE_IDX 1
+#define regPA_SC_PERFCOUNTER6_LO 0x314c
+#define regPA_SC_PERFCOUNTER6_LO_BASE_IDX 1
+#define regPA_SC_PERFCOUNTER6_HI 0x314d
+#define regPA_SC_PERFCOUNTER6_HI_BASE_IDX 1
+#define regPA_SC_PERFCOUNTER7_LO 0x314e
+#define regPA_SC_PERFCOUNTER7_LO_BASE_IDX 1
+#define regPA_SC_PERFCOUNTER7_HI 0x314f
+#define regPA_SC_PERFCOUNTER7_HI_BASE_IDX 1
+#define regSPI_PERFCOUNTER0_HI 0x3180
+#define regSPI_PERFCOUNTER0_HI_BASE_IDX 1
+#define regSPI_PERFCOUNTER0_LO 0x3181
+#define regSPI_PERFCOUNTER0_LO_BASE_IDX 1
+#define regSPI_PERFCOUNTER1_HI 0x3182
+#define regSPI_PERFCOUNTER1_HI_BASE_IDX 1
+#define regSPI_PERFCOUNTER1_LO 0x3183
+#define regSPI_PERFCOUNTER1_LO_BASE_IDX 1
+#define regSPI_PERFCOUNTER2_HI 0x3184
+#define regSPI_PERFCOUNTER2_HI_BASE_IDX 1
+#define regSPI_PERFCOUNTER2_LO 0x3185
+#define regSPI_PERFCOUNTER2_LO_BASE_IDX 1
+#define regSPI_PERFCOUNTER3_HI 0x3186
+#define regSPI_PERFCOUNTER3_HI_BASE_IDX 1
+#define regSPI_PERFCOUNTER3_LO 0x3187
+#define regSPI_PERFCOUNTER3_LO_BASE_IDX 1
+#define regSPI_PERFCOUNTER4_HI 0x3188
+#define regSPI_PERFCOUNTER4_HI_BASE_IDX 1
+#define regSPI_PERFCOUNTER4_LO 0x3189
+#define regSPI_PERFCOUNTER4_LO_BASE_IDX 1
+#define regSPI_PERFCOUNTER5_HI 0x318a
+#define regSPI_PERFCOUNTER5_HI_BASE_IDX 1
+#define regSPI_PERFCOUNTER5_LO 0x318b
+#define regSPI_PERFCOUNTER5_LO_BASE_IDX 1
+#define regSQ_PERFCOUNTER0_LO 0x31c0
+#define regSQ_PERFCOUNTER0_LO_BASE_IDX 1
+#define regSQ_PERFCOUNTER0_HI 0x31c1
+#define regSQ_PERFCOUNTER0_HI_BASE_IDX 1
+#define regSQ_PERFCOUNTER1_LO 0x31c2
+#define regSQ_PERFCOUNTER1_LO_BASE_IDX 1
+#define regSQ_PERFCOUNTER1_HI 0x31c3
+#define regSQ_PERFCOUNTER1_HI_BASE_IDX 1
+#define regSQ_PERFCOUNTER2_LO 0x31c4
+#define regSQ_PERFCOUNTER2_LO_BASE_IDX 1
+#define regSQ_PERFCOUNTER2_HI 0x31c5
+#define regSQ_PERFCOUNTER2_HI_BASE_IDX 1
+#define regSQ_PERFCOUNTER3_LO 0x31c6
+#define regSQ_PERFCOUNTER3_LO_BASE_IDX 1
+#define regSQ_PERFCOUNTER3_HI 0x31c7
+#define regSQ_PERFCOUNTER3_HI_BASE_IDX 1
+#define regSQ_PERFCOUNTER4_LO 0x31c8
+#define regSQ_PERFCOUNTER4_LO_BASE_IDX 1
+#define regSQ_PERFCOUNTER4_HI 0x31c9
+#define regSQ_PERFCOUNTER4_HI_BASE_IDX 1
+#define regSQ_PERFCOUNTER5_LO 0x31ca
+#define regSQ_PERFCOUNTER5_LO_BASE_IDX 1
+#define regSQ_PERFCOUNTER5_HI 0x31cb
+#define regSQ_PERFCOUNTER5_HI_BASE_IDX 1
+#define regSQ_PERFCOUNTER6_LO 0x31cc
+#define regSQ_PERFCOUNTER6_LO_BASE_IDX 1
+#define regSQ_PERFCOUNTER6_HI 0x31cd
+#define regSQ_PERFCOUNTER6_HI_BASE_IDX 1
+#define regSQ_PERFCOUNTER7_LO 0x31ce
+#define regSQ_PERFCOUNTER7_LO_BASE_IDX 1
+#define regSQ_PERFCOUNTER7_HI 0x31cf
+#define regSQ_PERFCOUNTER7_HI_BASE_IDX 1
+#define regSQ_PERFCOUNTER8_LO 0x31d0
+#define regSQ_PERFCOUNTER8_LO_BASE_IDX 1
+#define regSQ_PERFCOUNTER8_HI 0x31d1
+#define regSQ_PERFCOUNTER8_HI_BASE_IDX 1
+#define regSQ_PERFCOUNTER9_LO 0x31d2
+#define regSQ_PERFCOUNTER9_LO_BASE_IDX 1
+#define regSQ_PERFCOUNTER9_HI 0x31d3
+#define regSQ_PERFCOUNTER9_HI_BASE_IDX 1
+#define regSQ_PERFCOUNTER10_LO 0x31d4
+#define regSQ_PERFCOUNTER10_LO_BASE_IDX 1
+#define regSQ_PERFCOUNTER10_HI 0x31d5
+#define regSQ_PERFCOUNTER10_HI_BASE_IDX 1
+#define regSQ_PERFCOUNTER11_LO 0x31d6
+#define regSQ_PERFCOUNTER11_LO_BASE_IDX 1
+#define regSQ_PERFCOUNTER11_HI 0x31d7
+#define regSQ_PERFCOUNTER11_HI_BASE_IDX 1
+#define regSQ_PERFCOUNTER12_LO 0x31d8
+#define regSQ_PERFCOUNTER12_LO_BASE_IDX 1
+#define regSQ_PERFCOUNTER12_HI 0x31d9
+#define regSQ_PERFCOUNTER12_HI_BASE_IDX 1
+#define regSQ_PERFCOUNTER13_LO 0x31da
+#define regSQ_PERFCOUNTER13_LO_BASE_IDX 1
+#define regSQ_PERFCOUNTER13_HI 0x31db
+#define regSQ_PERFCOUNTER13_HI_BASE_IDX 1
+#define regSQ_PERFCOUNTER14_LO 0x31dc
+#define regSQ_PERFCOUNTER14_LO_BASE_IDX 1
+#define regSQ_PERFCOUNTER14_HI 0x31dd
+#define regSQ_PERFCOUNTER14_HI_BASE_IDX 1
+#define regSQ_PERFCOUNTER15_LO 0x31de
+#define regSQ_PERFCOUNTER15_LO_BASE_IDX 1
+#define regSQ_PERFCOUNTER15_HI 0x31df
+#define regSQ_PERFCOUNTER15_HI_BASE_IDX 1
+#define regSX_PERFCOUNTER0_LO 0x3240
+#define regSX_PERFCOUNTER0_LO_BASE_IDX 1
+#define regSX_PERFCOUNTER0_HI 0x3241
+#define regSX_PERFCOUNTER0_HI_BASE_IDX 1
+#define regSX_PERFCOUNTER1_LO 0x3242
+#define regSX_PERFCOUNTER1_LO_BASE_IDX 1
+#define regSX_PERFCOUNTER1_HI 0x3243
+#define regSX_PERFCOUNTER1_HI_BASE_IDX 1
+#define regSX_PERFCOUNTER2_LO 0x3244
+#define regSX_PERFCOUNTER2_LO_BASE_IDX 1
+#define regSX_PERFCOUNTER2_HI 0x3245
+#define regSX_PERFCOUNTER2_HI_BASE_IDX 1
+#define regSX_PERFCOUNTER3_LO 0x3246
+#define regSX_PERFCOUNTER3_LO_BASE_IDX 1
+#define regSX_PERFCOUNTER3_HI 0x3247
+#define regSX_PERFCOUNTER3_HI_BASE_IDX 1
+#define regGDS_PERFCOUNTER0_LO 0x3280
+#define regGDS_PERFCOUNTER0_LO_BASE_IDX 1
+#define regGDS_PERFCOUNTER0_HI 0x3281
+#define regGDS_PERFCOUNTER0_HI_BASE_IDX 1
+#define regGDS_PERFCOUNTER1_LO 0x3282
+#define regGDS_PERFCOUNTER1_LO_BASE_IDX 1
+#define regGDS_PERFCOUNTER1_HI 0x3283
+#define regGDS_PERFCOUNTER1_HI_BASE_IDX 1
+#define regGDS_PERFCOUNTER2_LO 0x3284
+#define regGDS_PERFCOUNTER2_LO_BASE_IDX 1
+#define regGDS_PERFCOUNTER2_HI 0x3285
+#define regGDS_PERFCOUNTER2_HI_BASE_IDX 1
+#define regGDS_PERFCOUNTER3_LO 0x3286
+#define regGDS_PERFCOUNTER3_LO_BASE_IDX 1
+#define regGDS_PERFCOUNTER3_HI 0x3287
+#define regGDS_PERFCOUNTER3_HI_BASE_IDX 1
+#define regTA_PERFCOUNTER0_LO 0x32c0
+#define regTA_PERFCOUNTER0_LO_BASE_IDX 1
+#define regTA_PERFCOUNTER0_HI 0x32c1
+#define regTA_PERFCOUNTER0_HI_BASE_IDX 1
+#define regTA_PERFCOUNTER1_LO 0x32c2
+#define regTA_PERFCOUNTER1_LO_BASE_IDX 1
+#define regTA_PERFCOUNTER1_HI 0x32c3
+#define regTA_PERFCOUNTER1_HI_BASE_IDX 1
+#define regTD_PERFCOUNTER0_LO 0x3300
+#define regTD_PERFCOUNTER0_LO_BASE_IDX 1
+#define regTD_PERFCOUNTER0_HI 0x3301
+#define regTD_PERFCOUNTER0_HI_BASE_IDX 1
+#define regTD_PERFCOUNTER1_LO 0x3302
+#define regTD_PERFCOUNTER1_LO_BASE_IDX 1
+#define regTD_PERFCOUNTER1_HI 0x3303
+#define regTD_PERFCOUNTER1_HI_BASE_IDX 1
+#define regTCP_PERFCOUNTER0_LO 0x3340
+#define regTCP_PERFCOUNTER0_LO_BASE_IDX 1
+#define regTCP_PERFCOUNTER0_HI 0x3341
+#define regTCP_PERFCOUNTER0_HI_BASE_IDX 1
+#define regTCP_PERFCOUNTER1_LO 0x3342
+#define regTCP_PERFCOUNTER1_LO_BASE_IDX 1
+#define regTCP_PERFCOUNTER1_HI 0x3343
+#define regTCP_PERFCOUNTER1_HI_BASE_IDX 1
+#define regTCP_PERFCOUNTER2_LO 0x3344
+#define regTCP_PERFCOUNTER2_LO_BASE_IDX 1
+#define regTCP_PERFCOUNTER2_HI 0x3345
+#define regTCP_PERFCOUNTER2_HI_BASE_IDX 1
+#define regTCP_PERFCOUNTER3_LO 0x3346
+#define regTCP_PERFCOUNTER3_LO_BASE_IDX 1
+#define regTCP_PERFCOUNTER3_HI 0x3347
+#define regTCP_PERFCOUNTER3_HI_BASE_IDX 1
+#define regTCC_PERFCOUNTER0_LO 0x3380
+#define regTCC_PERFCOUNTER0_LO_BASE_IDX 1
+#define regTCC_PERFCOUNTER0_HI 0x3381
+#define regTCC_PERFCOUNTER0_HI_BASE_IDX 1
+#define regTCC_PERFCOUNTER1_LO 0x3382
+#define regTCC_PERFCOUNTER1_LO_BASE_IDX 1
+#define regTCC_PERFCOUNTER1_HI 0x3383
+#define regTCC_PERFCOUNTER1_HI_BASE_IDX 1
+#define regTCC_PERFCOUNTER2_LO 0x3384
+#define regTCC_PERFCOUNTER2_LO_BASE_IDX 1
+#define regTCC_PERFCOUNTER2_HI 0x3385
+#define regTCC_PERFCOUNTER2_HI_BASE_IDX 1
+#define regTCC_PERFCOUNTER3_LO 0x3386
+#define regTCC_PERFCOUNTER3_LO_BASE_IDX 1
+#define regTCC_PERFCOUNTER3_HI 0x3387
+#define regTCC_PERFCOUNTER3_HI_BASE_IDX 1
+#define regTCA_PERFCOUNTER0_LO 0x3390
+#define regTCA_PERFCOUNTER0_LO_BASE_IDX 1
+#define regTCA_PERFCOUNTER0_HI 0x3391
+#define regTCA_PERFCOUNTER0_HI_BASE_IDX 1
+#define regTCA_PERFCOUNTER1_LO 0x3392
+#define regTCA_PERFCOUNTER1_LO_BASE_IDX 1
+#define regTCA_PERFCOUNTER1_HI 0x3393
+#define regTCA_PERFCOUNTER1_HI_BASE_IDX 1
+#define regTCA_PERFCOUNTER2_LO 0x3394
+#define regTCA_PERFCOUNTER2_LO_BASE_IDX 1
+#define regTCA_PERFCOUNTER2_HI 0x3395
+#define regTCA_PERFCOUNTER2_HI_BASE_IDX 1
+#define regTCA_PERFCOUNTER3_LO 0x3396
+#define regTCA_PERFCOUNTER3_LO_BASE_IDX 1
+#define regTCA_PERFCOUNTER3_HI 0x3397
+#define regTCA_PERFCOUNTER3_HI_BASE_IDX 1
+#define regCB_PERFCOUNTER0_LO 0x3406
+#define regCB_PERFCOUNTER0_LO_BASE_IDX 1
+#define regCB_PERFCOUNTER0_HI 0x3407
+#define regCB_PERFCOUNTER0_HI_BASE_IDX 1
+#define regCB_PERFCOUNTER1_LO 0x3408
+#define regCB_PERFCOUNTER1_LO_BASE_IDX 1
+#define regCB_PERFCOUNTER1_HI 0x3409
+#define regCB_PERFCOUNTER1_HI_BASE_IDX 1
+#define regCB_PERFCOUNTER2_LO 0x340a
+#define regCB_PERFCOUNTER2_LO_BASE_IDX 1
+#define regCB_PERFCOUNTER2_HI 0x340b
+#define regCB_PERFCOUNTER2_HI_BASE_IDX 1
+#define regCB_PERFCOUNTER3_LO 0x340c
+#define regCB_PERFCOUNTER3_LO_BASE_IDX 1
+#define regCB_PERFCOUNTER3_HI 0x340d
+#define regCB_PERFCOUNTER3_HI_BASE_IDX 1
+#define regDB_PERFCOUNTER0_LO 0x3440
+#define regDB_PERFCOUNTER0_LO_BASE_IDX 1
+#define regDB_PERFCOUNTER0_HI 0x3441
+#define regDB_PERFCOUNTER0_HI_BASE_IDX 1
+#define regDB_PERFCOUNTER1_LO 0x3442
+#define regDB_PERFCOUNTER1_LO_BASE_IDX 1
+#define regDB_PERFCOUNTER1_HI 0x3443
+#define regDB_PERFCOUNTER1_HI_BASE_IDX 1
+#define regDB_PERFCOUNTER2_LO 0x3444
+#define regDB_PERFCOUNTER2_LO_BASE_IDX 1
+#define regDB_PERFCOUNTER2_HI 0x3445
+#define regDB_PERFCOUNTER2_HI_BASE_IDX 1
+#define regDB_PERFCOUNTER3_LO 0x3446
+#define regDB_PERFCOUNTER3_LO_BASE_IDX 1
+#define regDB_PERFCOUNTER3_HI 0x3447
+#define regDB_PERFCOUNTER3_HI_BASE_IDX 1
+#define regRLC_PERFCOUNTER0_LO 0x3480
+#define regRLC_PERFCOUNTER0_LO_BASE_IDX 1
+#define regRLC_PERFCOUNTER0_HI 0x3481
+#define regRLC_PERFCOUNTER0_HI_BASE_IDX 1
+#define regRLC_PERFCOUNTER1_LO 0x3482
+#define regRLC_PERFCOUNTER1_LO_BASE_IDX 1
+#define regRLC_PERFCOUNTER1_HI 0x3483
+#define regRLC_PERFCOUNTER1_HI_BASE_IDX 1
+#define regRMI_PERFCOUNTER0_LO 0x34c0
+#define regRMI_PERFCOUNTER0_LO_BASE_IDX 1
+#define regRMI_PERFCOUNTER0_HI 0x34c1
+#define regRMI_PERFCOUNTER0_HI_BASE_IDX 1
+#define regRMI_PERFCOUNTER1_LO 0x34c2
+#define regRMI_PERFCOUNTER1_LO_BASE_IDX 1
+#define regRMI_PERFCOUNTER1_HI 0x34c3
+#define regRMI_PERFCOUNTER1_HI_BASE_IDX 1
+#define regRMI_PERFCOUNTER2_LO 0x34c4
+#define regRMI_PERFCOUNTER2_LO_BASE_IDX 1
+#define regRMI_PERFCOUNTER2_HI 0x34c5
+#define regRMI_PERFCOUNTER2_HI_BASE_IDX 1
+#define regRMI_PERFCOUNTER3_LO 0x34c6
+#define regRMI_PERFCOUNTER3_LO_BASE_IDX 1
+#define regRMI_PERFCOUNTER3_HI 0x34c7
+#define regRMI_PERFCOUNTER3_HI_BASE_IDX 1
+
+
+// addressBlock: gc_perfsdec
+// base address: 0x36000
+#define regCPG_PERFCOUNTER1_SELECT 0x3800
+#define regCPG_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define regCPG_PERFCOUNTER0_SELECT1 0x3801
+#define regCPG_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define regCPG_PERFCOUNTER0_SELECT 0x3802
+#define regCPG_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define regCPC_PERFCOUNTER1_SELECT 0x3803
+#define regCPC_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define regCPC_PERFCOUNTER0_SELECT1 0x3804
+#define regCPC_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define regCPF_PERFCOUNTER1_SELECT 0x3805
+#define regCPF_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define regCPF_PERFCOUNTER0_SELECT1 0x3806
+#define regCPF_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define regCPF_PERFCOUNTER0_SELECT 0x3807
+#define regCPF_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define regCP_PERFMON_CNTL 0x3808
+#define regCP_PERFMON_CNTL_BASE_IDX 1
+#define regCPC_PERFCOUNTER0_SELECT 0x3809
+#define regCPC_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define regCPF_TC_PERF_COUNTER_WINDOW_SELECT 0x380a
+#define regCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1
+#define regCPG_TC_PERF_COUNTER_WINDOW_SELECT 0x380b
+#define regCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1
+#define regCPF_LATENCY_STATS_SELECT 0x380c
+#define regCPF_LATENCY_STATS_SELECT_BASE_IDX 1
+#define regCPG_LATENCY_STATS_SELECT 0x380d
+#define regCPG_LATENCY_STATS_SELECT_BASE_IDX 1
+#define regCPC_LATENCY_STATS_SELECT 0x380e
+#define regCPC_LATENCY_STATS_SELECT_BASE_IDX 1
+#define regCP_DRAW_OBJECT 0x3810
+#define regCP_DRAW_OBJECT_BASE_IDX 1
+#define regCP_DRAW_OBJECT_COUNTER 0x3811
+#define regCP_DRAW_OBJECT_COUNTER_BASE_IDX 1
+#define regCP_DRAW_WINDOW_MASK_HI 0x3812
+#define regCP_DRAW_WINDOW_MASK_HI_BASE_IDX 1
+#define regCP_DRAW_WINDOW_HI 0x3813
+#define regCP_DRAW_WINDOW_HI_BASE_IDX 1
+#define regCP_DRAW_WINDOW_LO 0x3814
+#define regCP_DRAW_WINDOW_LO_BASE_IDX 1
+#define regCP_DRAW_WINDOW_CNTL 0x3815
+#define regCP_DRAW_WINDOW_CNTL_BASE_IDX 1
+#define regGRBM_PERFCOUNTER0_SELECT 0x3840
+#define regGRBM_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define regGRBM_PERFCOUNTER1_SELECT 0x3841
+#define regGRBM_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define regGRBM_SE0_PERFCOUNTER_SELECT 0x3842
+#define regGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX 1
+#define regGRBM_SE1_PERFCOUNTER_SELECT 0x3843
+#define regGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX 1
+#define regGRBM_SE2_PERFCOUNTER_SELECT 0x3844
+#define regGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX 1
+#define regGRBM_SE3_PERFCOUNTER_SELECT 0x3845
+#define regGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX 1
+#define regWD_PERFCOUNTER0_SELECT 0x3880
+#define regWD_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define regWD_PERFCOUNTER1_SELECT 0x3881
+#define regWD_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define regWD_PERFCOUNTER2_SELECT 0x3882
+#define regWD_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define regWD_PERFCOUNTER3_SELECT 0x3883
+#define regWD_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define regIA_PERFCOUNTER0_SELECT 0x3884
+#define regIA_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define regIA_PERFCOUNTER1_SELECT 0x3885
+#define regIA_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define regIA_PERFCOUNTER2_SELECT 0x3886
+#define regIA_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define regIA_PERFCOUNTER3_SELECT 0x3887
+#define regIA_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define regIA_PERFCOUNTER0_SELECT1 0x3888
+#define regIA_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define regVGT_PERFCOUNTER0_SELECT 0x388c
+#define regVGT_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define regVGT_PERFCOUNTER1_SELECT 0x388d
+#define regVGT_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define regVGT_PERFCOUNTER2_SELECT 0x388e
+#define regVGT_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define regVGT_PERFCOUNTER3_SELECT 0x388f
+#define regVGT_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define regVGT_PERFCOUNTER0_SELECT1 0x3890
+#define regVGT_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define regVGT_PERFCOUNTER1_SELECT1 0x3891
+#define regVGT_PERFCOUNTER1_SELECT1_BASE_IDX 1
+#define regVGT_PERFCOUNTER_SEID_MASK 0x3894
+#define regVGT_PERFCOUNTER_SEID_MASK_BASE_IDX 1
+#define regPA_SU_PERFCOUNTER0_SELECT 0x3900
+#define regPA_SU_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define regPA_SU_PERFCOUNTER0_SELECT1 0x3901
+#define regPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define regPA_SU_PERFCOUNTER1_SELECT 0x3902
+#define regPA_SU_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define regPA_SU_PERFCOUNTER1_SELECT1 0x3903
+#define regPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX 1
+#define regPA_SU_PERFCOUNTER2_SELECT 0x3904
+#define regPA_SU_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define regPA_SU_PERFCOUNTER3_SELECT 0x3905
+#define regPA_SU_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define regPA_SC_PERFCOUNTER0_SELECT 0x3940
+#define regPA_SC_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define regPA_SC_PERFCOUNTER0_SELECT1 0x3941
+#define regPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define regPA_SC_PERFCOUNTER1_SELECT 0x3942
+#define regPA_SC_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define regPA_SC_PERFCOUNTER2_SELECT 0x3943
+#define regPA_SC_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define regPA_SC_PERFCOUNTER3_SELECT 0x3944
+#define regPA_SC_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define regPA_SC_PERFCOUNTER4_SELECT 0x3945
+#define regPA_SC_PERFCOUNTER4_SELECT_BASE_IDX 1
+#define regPA_SC_PERFCOUNTER5_SELECT 0x3946
+#define regPA_SC_PERFCOUNTER5_SELECT_BASE_IDX 1
+#define regPA_SC_PERFCOUNTER6_SELECT 0x3947
+#define regPA_SC_PERFCOUNTER6_SELECT_BASE_IDX 1
+#define regPA_SC_PERFCOUNTER7_SELECT 0x3948
+#define regPA_SC_PERFCOUNTER7_SELECT_BASE_IDX 1
+#define regSPI_PERFCOUNTER0_SELECT 0x3980
+#define regSPI_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define regSPI_PERFCOUNTER1_SELECT 0x3981
+#define regSPI_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define regSPI_PERFCOUNTER2_SELECT 0x3982
+#define regSPI_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define regSPI_PERFCOUNTER3_SELECT 0x3983
+#define regSPI_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define regSPI_PERFCOUNTER0_SELECT1 0x3984
+#define regSPI_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define regSPI_PERFCOUNTER1_SELECT1 0x3985
+#define regSPI_PERFCOUNTER1_SELECT1_BASE_IDX 1
+#define regSPI_PERFCOUNTER2_SELECT1 0x3986
+#define regSPI_PERFCOUNTER2_SELECT1_BASE_IDX 1
+#define regSPI_PERFCOUNTER3_SELECT1 0x3987
+#define regSPI_PERFCOUNTER3_SELECT1_BASE_IDX 1
+#define regSPI_PERFCOUNTER4_SELECT 0x3988
+#define regSPI_PERFCOUNTER4_SELECT_BASE_IDX 1
+#define regSPI_PERFCOUNTER5_SELECT 0x3989
+#define regSPI_PERFCOUNTER5_SELECT_BASE_IDX 1
+#define regSPI_PERFCOUNTER_BINS 0x398a
+#define regSPI_PERFCOUNTER_BINS_BASE_IDX 1
+#define regSQ_PERFCOUNTER0_SELECT 0x39c0
+#define regSQ_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define regSQ_PERFCOUNTER1_SELECT 0x39c1
+#define regSQ_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define regSQ_PERFCOUNTER2_SELECT 0x39c2
+#define regSQ_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define regSQ_PERFCOUNTER3_SELECT 0x39c3
+#define regSQ_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define regSQ_PERFCOUNTER4_SELECT 0x39c4
+#define regSQ_PERFCOUNTER4_SELECT_BASE_IDX 1
+#define regSQ_PERFCOUNTER5_SELECT 0x39c5
+#define regSQ_PERFCOUNTER5_SELECT_BASE_IDX 1
+#define regSQ_PERFCOUNTER6_SELECT 0x39c6
+#define regSQ_PERFCOUNTER6_SELECT_BASE_IDX 1
+#define regSQ_PERFCOUNTER7_SELECT 0x39c7
+#define regSQ_PERFCOUNTER7_SELECT_BASE_IDX 1
+#define regSQ_PERFCOUNTER8_SELECT 0x39c8
+#define regSQ_PERFCOUNTER8_SELECT_BASE_IDX 1
+#define regSQ_PERFCOUNTER9_SELECT 0x39c9
+#define regSQ_PERFCOUNTER9_SELECT_BASE_IDX 1
+#define regSQ_PERFCOUNTER10_SELECT 0x39ca
+#define regSQ_PERFCOUNTER10_SELECT_BASE_IDX 1
+#define regSQ_PERFCOUNTER11_SELECT 0x39cb
+#define regSQ_PERFCOUNTER11_SELECT_BASE_IDX 1
+#define regSQ_PERFCOUNTER12_SELECT 0x39cc
+#define regSQ_PERFCOUNTER12_SELECT_BASE_IDX 1
+#define regSQ_PERFCOUNTER13_SELECT 0x39cd
+#define regSQ_PERFCOUNTER13_SELECT_BASE_IDX 1
+#define regSQ_PERFCOUNTER14_SELECT 0x39ce
+#define regSQ_PERFCOUNTER14_SELECT_BASE_IDX 1
+#define regSQ_PERFCOUNTER15_SELECT 0x39cf
+#define regSQ_PERFCOUNTER15_SELECT_BASE_IDX 1
+#define regSQ_PERFCOUNTER_CTRL 0x39e0
+#define regSQ_PERFCOUNTER_CTRL_BASE_IDX 1
+#define regSQ_PERFCOUNTER_MASK 0x39e1
+#define regSQ_PERFCOUNTER_MASK_BASE_IDX 1
+#define regSQ_PERFCOUNTER_CTRL2 0x39e2
+#define regSQ_PERFCOUNTER_CTRL2_BASE_IDX 1
+#define regSX_PERFCOUNTER0_SELECT 0x3a40
+#define regSX_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define regSX_PERFCOUNTER1_SELECT 0x3a41
+#define regSX_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define regSX_PERFCOUNTER2_SELECT 0x3a42
+#define regSX_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define regSX_PERFCOUNTER3_SELECT 0x3a43
+#define regSX_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define regSX_PERFCOUNTER0_SELECT1 0x3a44
+#define regSX_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define regSX_PERFCOUNTER1_SELECT1 0x3a45
+#define regSX_PERFCOUNTER1_SELECT1_BASE_IDX 1
+#define regGDS_PERFCOUNTER0_SELECT 0x3a80
+#define regGDS_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define regGDS_PERFCOUNTER1_SELECT 0x3a81
+#define regGDS_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define regGDS_PERFCOUNTER2_SELECT 0x3a82
+#define regGDS_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define regGDS_PERFCOUNTER3_SELECT 0x3a83
+#define regGDS_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define regGDS_PERFCOUNTER0_SELECT1 0x3a84
+#define regGDS_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define regTA_PERFCOUNTER0_SELECT 0x3ac0
+#define regTA_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define regTA_PERFCOUNTER0_SELECT1 0x3ac1
+#define regTA_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define regTA_PERFCOUNTER1_SELECT 0x3ac2
+#define regTA_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define regTD_PERFCOUNTER0_SELECT 0x3b00
+#define regTD_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define regTD_PERFCOUNTER0_SELECT1 0x3b01
+#define regTD_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define regTD_PERFCOUNTER1_SELECT 0x3b02
+#define regTD_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define regTCP_PERFCOUNTER0_SELECT 0x3b40
+#define regTCP_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define regTCP_PERFCOUNTER0_SELECT1 0x3b41
+#define regTCP_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define regTCP_PERFCOUNTER1_SELECT 0x3b42
+#define regTCP_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define regTCP_PERFCOUNTER1_SELECT1 0x3b43
+#define regTCP_PERFCOUNTER1_SELECT1_BASE_IDX 1
+#define regTCP_PERFCOUNTER2_SELECT 0x3b44
+#define regTCP_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define regTCP_PERFCOUNTER3_SELECT 0x3b45
+#define regTCP_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define regTCC_PERFCOUNTER0_SELECT 0x3b80
+#define regTCC_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define regTCC_PERFCOUNTER0_SELECT1 0x3b81
+#define regTCC_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define regTCC_PERFCOUNTER1_SELECT 0x3b82
+#define regTCC_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define regTCC_PERFCOUNTER1_SELECT1 0x3b83
+#define regTCC_PERFCOUNTER1_SELECT1_BASE_IDX 1
+#define regTCC_PERFCOUNTER2_SELECT 0x3b84
+#define regTCC_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define regTCC_PERFCOUNTER3_SELECT 0x3b85
+#define regTCC_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define regTCA_PERFCOUNTER0_SELECT 0x3b90
+#define regTCA_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define regTCA_PERFCOUNTER0_SELECT1 0x3b91
+#define regTCA_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define regTCA_PERFCOUNTER1_SELECT 0x3b92
+#define regTCA_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define regTCA_PERFCOUNTER1_SELECT1 0x3b93
+#define regTCA_PERFCOUNTER1_SELECT1_BASE_IDX 1
+#define regTCA_PERFCOUNTER2_SELECT 0x3b94
+#define regTCA_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define regTCA_PERFCOUNTER3_SELECT 0x3b95
+#define regTCA_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define regCB_PERFCOUNTER_FILTER 0x3c00
+#define regCB_PERFCOUNTER_FILTER_BASE_IDX 1
+#define regCB_PERFCOUNTER0_SELECT 0x3c01
+#define regCB_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define regCB_PERFCOUNTER0_SELECT1 0x3c02
+#define regCB_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define regCB_PERFCOUNTER1_SELECT 0x3c03
+#define regCB_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define regCB_PERFCOUNTER2_SELECT 0x3c04
+#define regCB_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define regCB_PERFCOUNTER3_SELECT 0x3c05
+#define regCB_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define regDB_PERFCOUNTER0_SELECT 0x3c40
+#define regDB_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define regDB_PERFCOUNTER0_SELECT1 0x3c41
+#define regDB_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define regDB_PERFCOUNTER1_SELECT 0x3c42
+#define regDB_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define regDB_PERFCOUNTER1_SELECT1 0x3c43
+#define regDB_PERFCOUNTER1_SELECT1_BASE_IDX 1
+#define regDB_PERFCOUNTER2_SELECT 0x3c44
+#define regDB_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define regDB_PERFCOUNTER3_SELECT 0x3c46
+#define regDB_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define regRLC_SPM_PERFMON_CNTL 0x3c80
+#define regRLC_SPM_PERFMON_CNTL_BASE_IDX 1
+#define regRLC_SPM_PERFMON_RING_BASE_LO 0x3c81
+#define regRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX 1
+#define regRLC_SPM_PERFMON_RING_BASE_HI 0x3c82
+#define regRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX 1
+#define regRLC_SPM_PERFMON_RING_SIZE 0x3c83
+#define regRLC_SPM_PERFMON_RING_SIZE_BASE_IDX 1
+#define regRLC_SPM_PERFMON_SEGMENT_SIZE 0x3c84
+#define regRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX 1
+#define regRLC_SPM_SE_MUXSEL_ADDR 0x3c85
+#define regRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX 1
+#define regRLC_SPM_SE_MUXSEL_DATA 0x3c86
+#define regRLC_SPM_SE_MUXSEL_DATA_BASE_IDX 1
+#define regRLC_SPM_CPG_PERFMON_SAMPLE_DELAY 0x3c87
+#define regRLC_SPM_CPG_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define regRLC_SPM_CPC_PERFMON_SAMPLE_DELAY 0x3c88
+#define regRLC_SPM_CPC_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define regRLC_SPM_CPF_PERFMON_SAMPLE_DELAY 0x3c89
+#define regRLC_SPM_CPF_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define regRLC_SPM_CB_PERFMON_SAMPLE_DELAY 0x3c8a
+#define regRLC_SPM_CB_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define regRLC_SPM_DB_PERFMON_SAMPLE_DELAY 0x3c8b
+#define regRLC_SPM_DB_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define regRLC_SPM_PA_PERFMON_SAMPLE_DELAY 0x3c8c
+#define regRLC_SPM_PA_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define regRLC_SPM_GDS_PERFMON_SAMPLE_DELAY 0x3c8d
+#define regRLC_SPM_GDS_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define regRLC_SPM_IA_PERFMON_SAMPLE_DELAY 0x3c8e
+#define regRLC_SPM_IA_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define regRLC_SPM_SC_PERFMON_SAMPLE_DELAY 0x3c90
+#define regRLC_SPM_SC_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define regRLC_SPM_TCC_PERFMON_SAMPLE_DELAY 0x3c91
+#define regRLC_SPM_TCC_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define regRLC_SPM_TCA_PERFMON_SAMPLE_DELAY 0x3c92
+#define regRLC_SPM_TCA_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define regRLC_SPM_TCP_PERFMON_SAMPLE_DELAY 0x3c93
+#define regRLC_SPM_TCP_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define regRLC_SPM_TA_PERFMON_SAMPLE_DELAY 0x3c94
+#define regRLC_SPM_TA_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define regRLC_SPM_TD_PERFMON_SAMPLE_DELAY 0x3c95
+#define regRLC_SPM_TD_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define regRLC_SPM_VGT_PERFMON_SAMPLE_DELAY 0x3c96
+#define regRLC_SPM_VGT_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define regRLC_SPM_SPI_PERFMON_SAMPLE_DELAY 0x3c97
+#define regRLC_SPM_SPI_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define regRLC_SPM_SQG_PERFMON_SAMPLE_DELAY 0x3c98
+#define regRLC_SPM_SQG_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define regRLC_SPM_SX_PERFMON_SAMPLE_DELAY 0x3c9a
+#define regRLC_SPM_SX_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define regRLC_SPM_GLOBAL_MUXSEL_ADDR 0x3c9b
+#define regRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX 1
+#define regRLC_SPM_GLOBAL_MUXSEL_DATA 0x3c9c
+#define regRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX 1
+#define regRLC_SPM_RING_RDPTR 0x3c9d
+#define regRLC_SPM_RING_RDPTR_BASE_IDX 1
+#define regRLC_SPM_SEGMENT_THRESHOLD 0x3c9e
+#define regRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX 1
+#define regRLC_SPM_RMI_PERFMON_SAMPLE_DELAY 0x3ca3
+#define regRLC_SPM_RMI_PERFMON_SAMPLE_DELAY_BASE_IDX 1
+#define regRLC_SPM_PERFMON_SAMPLE_DELAY_MAX 0x3ca4
+#define regRLC_SPM_PERFMON_SAMPLE_DELAY_MAX_BASE_IDX 1
+#define regRLC_SPM_PERFMON_SEGMENT_SIZE_CORE1 0x3caf
+#define regRLC_SPM_PERFMON_SEGMENT_SIZE_CORE1_BASE_IDX 1
+#define regRLC_PERFMON_CLK_CNTL_UCODE 0x3cbe
+#define regRLC_PERFMON_CLK_CNTL_UCODE_BASE_IDX 1
+#define regRLC_PERFMON_CLK_CNTL 0x3cbf
+#define regRLC_PERFMON_CLK_CNTL_BASE_IDX 1
+#define regRLC_PERFMON_CNTL 0x3cc0
+#define regRLC_PERFMON_CNTL_BASE_IDX 1
+#define regRLC_PERFCOUNTER0_SELECT 0x3cc1
+#define regRLC_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define regRLC_PERFCOUNTER1_SELECT 0x3cc2
+#define regRLC_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define regRLC_GPU_IOV_PERF_CNT_CNTL 0x3cc3
+#define regRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX 1
+#define regRLC_GPU_IOV_PERF_CNT_WR_ADDR 0x3cc4
+#define regRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX 1
+#define regRLC_GPU_IOV_PERF_CNT_WR_DATA 0x3cc5
+#define regRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX 1
+#define regRLC_GPU_IOV_PERF_CNT_RD_ADDR 0x3cc6
+#define regRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX 1
+#define regRLC_GPU_IOV_PERF_CNT_RD_DATA 0x3cc7
+#define regRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX 1
+#define regRMI_PERFCOUNTER0_SELECT 0x3d00
+#define regRMI_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define regRMI_PERFCOUNTER0_SELECT1 0x3d01
+#define regRMI_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define regRMI_PERFCOUNTER1_SELECT 0x3d02
+#define regRMI_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define regRMI_PERFCOUNTER2_SELECT 0x3d03
+#define regRMI_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define regRMI_PERFCOUNTER2_SELECT1 0x3d04
+#define regRMI_PERFCOUNTER2_SELECT1_BASE_IDX 1
+#define regRMI_PERFCOUNTER3_SELECT 0x3d05
+#define regRMI_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define regRMI_PERF_COUNTER_CNTL 0x3d06
+#define regRMI_PERF_COUNTER_CNTL_BASE_IDX 1
+
+
+// addressBlock: gc_pwrdec
+// base address: 0x3c000
+#define regCGTS_SM_CTRL_REG 0x5000
+#define regCGTS_SM_CTRL_REG_BASE_IDX 1
+#define regCGTS_RD_CTRL_REG 0x5001
+#define regCGTS_RD_CTRL_REG_BASE_IDX 1
+#define regCGTS_RD_REG 0x5002
+#define regCGTS_RD_REG_BASE_IDX 1
+#define regCGTS_TCC_DISABLE 0x5003
+#define regCGTS_TCC_DISABLE_BASE_IDX 1
+#define regCGTS_USER_TCC_DISABLE 0x5004
+#define regCGTS_USER_TCC_DISABLE_BASE_IDX 1
+#define regCGTS_TCC_DISABLE2 0x5005
+#define regCGTS_TCC_DISABLE2_BASE_IDX 1
+#define regCGTS_USER_TCC_DISABLE2 0x5006
+#define regCGTS_USER_TCC_DISABLE2_BASE_IDX 1
+#define regCGTS_CU0_SP0_CTRL_REG 0x5008
+#define regCGTS_CU0_SP0_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU0_LDS_SQ_CTRL_REG 0x5009
+#define regCGTS_CU0_LDS_SQ_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU0_TA_SQC_CTRL_REG 0x500a
+#define regCGTS_CU0_TA_SQC_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU0_SP1_CTRL_REG 0x500b
+#define regCGTS_CU0_SP1_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU1_SP0_CTRL_REG 0x500d
+#define regCGTS_CU1_SP0_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU1_LDS_SQ_CTRL_REG 0x500e
+#define regCGTS_CU1_LDS_SQ_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU1_TA_SQC_CTRL_REG 0x500f
+#define regCGTS_CU1_TA_SQC_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU1_SP1_CTRL_REG 0x5010
+#define regCGTS_CU1_SP1_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU2_SP0_CTRL_REG 0x5012
+#define regCGTS_CU2_SP0_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU2_LDS_SQ_CTRL_REG 0x5013
+#define regCGTS_CU2_LDS_SQ_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU2_TA_SQC_CTRL_REG 0x5014
+#define regCGTS_CU2_TA_SQC_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU2_SP1_CTRL_REG 0x5015
+#define regCGTS_CU2_SP1_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU3_SP0_CTRL_REG 0x5017
+#define regCGTS_CU3_SP0_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU3_LDS_SQ_CTRL_REG 0x5018
+#define regCGTS_CU3_LDS_SQ_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU3_TA_SQC_CTRL_REG 0x5019
+#define regCGTS_CU3_TA_SQC_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU3_SP1_CTRL_REG 0x501a
+#define regCGTS_CU3_SP1_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU4_SP0_CTRL_REG 0x501c
+#define regCGTS_CU4_SP0_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU4_LDS_SQ_CTRL_REG 0x501d
+#define regCGTS_CU4_LDS_SQ_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU4_TA_SQC_CTRL_REG 0x501e
+#define regCGTS_CU4_TA_SQC_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU4_SP1_CTRL_REG 0x501f
+#define regCGTS_CU4_SP1_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU5_SP0_CTRL_REG 0x5021
+#define regCGTS_CU5_SP0_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU5_LDS_SQ_CTRL_REG 0x5022
+#define regCGTS_CU5_LDS_SQ_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU5_TA_SQC_CTRL_REG 0x5023
+#define regCGTS_CU5_TA_SQC_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU5_SP1_CTRL_REG 0x5024
+#define regCGTS_CU5_SP1_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU6_SP0_CTRL_REG 0x5026
+#define regCGTS_CU6_SP0_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU6_LDS_SQ_CTRL_REG 0x5027
+#define regCGTS_CU6_LDS_SQ_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU6_TA_SQC_CTRL_REG 0x5028
+#define regCGTS_CU6_TA_SQC_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU6_SP1_CTRL_REG 0x5029
+#define regCGTS_CU6_SP1_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU7_SP0_CTRL_REG 0x502b
+#define regCGTS_CU7_SP0_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU7_LDS_SQ_CTRL_REG 0x502c
+#define regCGTS_CU7_LDS_SQ_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU7_TA_SQC_CTRL_REG 0x502d
+#define regCGTS_CU7_TA_SQC_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU7_SP1_CTRL_REG 0x502e
+#define regCGTS_CU7_SP1_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU8_SP0_CTRL_REG 0x5030
+#define regCGTS_CU8_SP0_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU8_LDS_SQ_CTRL_REG 0x5031
+#define regCGTS_CU8_LDS_SQ_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU8_TA_SQC_CTRL_REG 0x5032
+#define regCGTS_CU8_TA_SQC_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU8_SP1_CTRL_REG 0x5033
+#define regCGTS_CU8_SP1_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU9_SP0_CTRL_REG 0x5035
+#define regCGTS_CU9_SP0_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU9_LDS_SQ_CTRL_REG 0x5036
+#define regCGTS_CU9_LDS_SQ_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU9_TA_SQC_CTRL_REG 0x5037
+#define regCGTS_CU9_TA_SQC_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU9_SP1_CTRL_REG 0x5038
+#define regCGTS_CU9_SP1_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU10_SP0_CTRL_REG 0x503a
+#define regCGTS_CU10_SP0_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU10_LDS_SQ_CTRL_REG 0x503b
+#define regCGTS_CU10_LDS_SQ_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU10_TA_SQC_CTRL_REG 0x503c
+#define regCGTS_CU10_TA_SQC_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU10_SP1_CTRL_REG 0x503d
+#define regCGTS_CU10_SP1_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU11_SP0_CTRL_REG 0x503f
+#define regCGTS_CU11_SP0_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU11_LDS_SQ_CTRL_REG 0x5040
+#define regCGTS_CU11_LDS_SQ_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU11_TA_SQC_CTRL_REG 0x5041
+#define regCGTS_CU11_TA_SQC_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU11_SP1_CTRL_REG 0x5042
+#define regCGTS_CU11_SP1_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU12_SP0_CTRL_REG 0x5044
+#define regCGTS_CU12_SP0_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU12_LDS_SQ_CTRL_REG 0x5045
+#define regCGTS_CU12_LDS_SQ_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU12_TA_SQC_CTRL_REG 0x5046
+#define regCGTS_CU12_TA_SQC_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU12_SP1_CTRL_REG 0x5047
+#define regCGTS_CU12_SP1_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU13_SP0_CTRL_REG 0x5049
+#define regCGTS_CU13_SP0_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU13_LDS_SQ_CTRL_REG 0x504a
+#define regCGTS_CU13_LDS_SQ_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU13_TA_SQC_CTRL_REG 0x504b
+#define regCGTS_CU13_TA_SQC_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU13_SP1_CTRL_REG 0x504c
+#define regCGTS_CU13_SP1_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU14_SP0_CTRL_REG 0x504e
+#define regCGTS_CU14_SP0_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU14_LDS_SQ_CTRL_REG 0x504f
+#define regCGTS_CU14_LDS_SQ_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU14_TA_SQC_CTRL_REG 0x5050
+#define regCGTS_CU14_TA_SQC_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU14_SP1_CTRL_REG 0x5051
+#define regCGTS_CU14_SP1_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU15_SP0_CTRL_REG 0x5053
+#define regCGTS_CU15_SP0_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU15_LDS_SQ_CTRL_REG 0x5054
+#define regCGTS_CU15_LDS_SQ_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU15_TA_SQC_CTRL_REG 0x5055
+#define regCGTS_CU15_TA_SQC_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU15_SP1_CTRL_REG 0x5056
+#define regCGTS_CU15_SP1_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU0_TCPI_CTRL_REG 0x5058
+#define regCGTS_CU0_TCPI_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU1_TCPI_CTRL_REG 0x5059
+#define regCGTS_CU1_TCPI_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU2_TCPI_CTRL_REG 0x505a
+#define regCGTS_CU2_TCPI_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU3_TCPI_CTRL_REG 0x505b
+#define regCGTS_CU3_TCPI_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU4_TCPI_CTRL_REG 0x505c
+#define regCGTS_CU4_TCPI_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU5_TCPI_CTRL_REG 0x505d
+#define regCGTS_CU5_TCPI_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU6_TCPI_CTRL_REG 0x505e
+#define regCGTS_CU6_TCPI_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU7_TCPI_CTRL_REG 0x505f
+#define regCGTS_CU7_TCPI_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU8_TCPI_CTRL_REG 0x5060
+#define regCGTS_CU8_TCPI_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU9_TCPI_CTRL_REG 0x5061
+#define regCGTS_CU9_TCPI_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU10_TCPI_CTRL_REG 0x5062
+#define regCGTS_CU10_TCPI_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU11_TCPI_CTRL_REG 0x5063
+#define regCGTS_CU11_TCPI_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU12_TCPI_CTRL_REG 0x5064
+#define regCGTS_CU12_TCPI_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU13_TCPI_CTRL_REG 0x5065
+#define regCGTS_CU13_TCPI_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU14_TCPI_CTRL_REG 0x5066
+#define regCGTS_CU14_TCPI_CTRL_REG_BASE_IDX 1
+#define regCGTS_CU15_TCPI_CTRL_REG 0x5067
+#define regCGTS_CU15_TCPI_CTRL_REG_BASE_IDX 1
+#define regCGTT_SPI_PS_CLK_CTRL 0x507d
+#define regCGTT_SPI_PS_CLK_CTRL_BASE_IDX 1
+#define regCGTT_SPIS_CLK_CTRL 0x507e
+#define regCGTT_SPIS_CLK_CTRL_BASE_IDX 1
+#define regCGTT_SPI_CLK_CTRL 0x5080
+#define regCGTT_SPI_CLK_CTRL_BASE_IDX 1
+#define regCGTT_PC_CLK_CTRL 0x5081
+#define regCGTT_PC_CLK_CTRL_BASE_IDX 1
+#define regCGTT_BCI_CLK_CTRL 0x5082
+#define regCGTT_BCI_CLK_CTRL_BASE_IDX 1
+#define regCGTT_PA_CLK_CTRL 0x5088
+#define regCGTT_PA_CLK_CTRL_BASE_IDX 1
+#define regCGTT_SC_CLK_CTRL0 0x5089
+#define regCGTT_SC_CLK_CTRL0_BASE_IDX 1
+#define regCGTT_SC_CLK_CTRL1 0x508a
+#define regCGTT_SC_CLK_CTRL1_BASE_IDX 1
+#define regCGTT_SC_CLK_CTRL2 0x508b
+#define regCGTT_SC_CLK_CTRL2_BASE_IDX 1
+#define regCGTT_SQG_CLK_CTRL 0x508d
+#define regCGTT_SQG_CLK_CTRL_BASE_IDX 1
+#define regSQ_ALU_CLK_CTRL 0x508e
+#define regSQ_ALU_CLK_CTRL_BASE_IDX 1
+#define regSQ_TEX_CLK_CTRL 0x508f
+#define regSQ_TEX_CLK_CTRL_BASE_IDX 1
+#define regSQ_LDS_CLK_CTRL 0x5090
+#define regSQ_LDS_CLK_CTRL_BASE_IDX 1
+#define regSQ_POWER_THROTTLE 0x5091
+#define regSQ_POWER_THROTTLE_BASE_IDX 1
+#define regSQ_POWER_THROTTLE2 0x5092
+#define regSQ_POWER_THROTTLE2_BASE_IDX 1
+#define regCGTT_SX_CLK_CTRL0 0x5094
+#define regCGTT_SX_CLK_CTRL0_BASE_IDX 1
+#define regCGTT_SX_CLK_CTRL1 0x5095
+#define regCGTT_SX_CLK_CTRL1_BASE_IDX 1
+#define regCGTT_SX_CLK_CTRL2 0x5096
+#define regCGTT_SX_CLK_CTRL2_BASE_IDX 1
+#define regCGTT_SX_CLK_CTRL3 0x5097
+#define regCGTT_SX_CLK_CTRL3_BASE_IDX 1
+#define regCGTT_SX_CLK_CTRL4 0x5098
+#define regCGTT_SX_CLK_CTRL4_BASE_IDX 1
+#define regTD_CGTT_CTRL 0x509c
+#define regTD_CGTT_CTRL_BASE_IDX 1
+#define regTA_CGTT_CTRL 0x509d
+#define regTA_CGTT_CTRL_BASE_IDX 1
+#define regCGTT_TCI_CLK_CTRL 0x509f
+#define regCGTT_TCI_CLK_CTRL_BASE_IDX 1
+#define regCGTT_GDS_CLK_CTRL 0x50a0
+#define regCGTT_GDS_CLK_CTRL_BASE_IDX 1
+#define regCGTT_TCP_TCR_CLK_CTRL 0x50a1
+#define regCGTT_TCP_TCR_CLK_CTRL_BASE_IDX 1
+#define regCGTT_TCI_TCR_CLK_CTRL 0x50a2
+#define regCGTT_TCI_TCR_CLK_CTRL_BASE_IDX 1
+#define regTCX_CGTT_SCLK_CTRL 0x50a3
+#define regTCX_CGTT_SCLK_CTRL_BASE_IDX 1
+#define regDB_CGTT_CLK_CTRL_0 0x50a4
+#define regDB_CGTT_CLK_CTRL_0_BASE_IDX 1
+#define regCB_CGTT_SCLK_CTRL 0x50a8
+#define regCB_CGTT_SCLK_CTRL_BASE_IDX 1
+#define regTCC_CGTT_SCLK_CTRL 0x50ac
+#define regTCC_CGTT_SCLK_CTRL_BASE_IDX 1
+#define regTCC_CGTT_SCLK_CTRL2 0x50ad
+#define regTCC_CGTT_SCLK_CTRL2_BASE_IDX 1
+#define regTCC_CGTT_SCLK_CTRL3 0x50ae
+#define regTCC_CGTT_SCLK_CTRL3_BASE_IDX 1
+#define regTCA_CGTT_SCLK_CTRL 0x50af
+#define regTCA_CGTT_SCLK_CTRL_BASE_IDX 1
+#define regCGTT_CP_CLK_CTRL 0x50b0
+#define regCGTT_CP_CLK_CTRL_BASE_IDX 1
+#define regCGTT_CPF_CLK_CTRL 0x50b1
+#define regCGTT_CPF_CLK_CTRL_BASE_IDX 1
+#define regCGTT_CPC_CLK_CTRL 0x50b2
+#define regCGTT_CPC_CLK_CTRL_BASE_IDX 1
+#define regCGTT_RLC_CLK_CTRL 0x50b5
+#define regCGTT_RLC_CLK_CTRL_BASE_IDX 1
+#define regRLC_GFX_RM_CNTL 0x50b6
+#define regRLC_GFX_RM_CNTL_BASE_IDX 1
+#define regRMI_CGTT_SCLK_CTRL 0x50c0
+#define regRMI_CGTT_SCLK_CTRL_BASE_IDX 1
+#define regSE_CAC_CGTT_CLK_CTRL 0x50d0
+#define regSE_CAC_CGTT_CLK_CTRL_BASE_IDX 1
+#define regGC_CAC_CGTT_CLK_CTRL 0x50d8
+#define regGC_CAC_CGTT_CLK_CTRL_BASE_IDX 1
+#define regGRBM_CGTT_CLK_CNTL 0x50e0
+#define regGRBM_CGTT_CLK_CNTL_BASE_IDX 1
+
+
+// addressBlock: gc_rbdec
+// base address: 0x9800
+#define regDB_DEBUG 0x060c
+#define regDB_DEBUG_BASE_IDX 0
+#define regDB_DEBUG2 0x060d
+#define regDB_DEBUG2_BASE_IDX 0
+#define regDB_DEBUG3 0x060e
+#define regDB_DEBUG3_BASE_IDX 0
+#define regDB_DEBUG4 0x060f
+#define regDB_DEBUG4_BASE_IDX 0
+#define regDB_CREDIT_LIMIT 0x0614
+#define regDB_CREDIT_LIMIT_BASE_IDX 0
+#define regDB_WATERMARKS 0x0615
+#define regDB_WATERMARKS_BASE_IDX 0
+#define regDB_SUBTILE_CONTROL 0x0616
+#define regDB_SUBTILE_CONTROL_BASE_IDX 0
+#define regDB_FREE_CACHELINES 0x0617
+#define regDB_FREE_CACHELINES_BASE_IDX 0
+#define regDB_FIFO_DEPTH1 0x0618
+#define regDB_FIFO_DEPTH1_BASE_IDX 0
+#define regDB_FIFO_DEPTH2 0x0619
+#define regDB_FIFO_DEPTH2_BASE_IDX 0
+#define regDB_EXCEPTION_CONTROL 0x061a
+#define regDB_EXCEPTION_CONTROL_BASE_IDX 0
+#define regDB_RING_CONTROL 0x061b
+#define regDB_RING_CONTROL_BASE_IDX 0
+#define regDB_MEM_ARB_WATERMARKS 0x061c
+#define regDB_MEM_ARB_WATERMARKS_BASE_IDX 0
+#define regDB_RMI_CACHE_POLICY 0x061e
+#define regDB_RMI_CACHE_POLICY_BASE_IDX 0
+#define regDB_DFSM_CONFIG 0x0630
+#define regDB_DFSM_CONFIG_BASE_IDX 0
+#define regDB_DFSM_WATERMARK 0x0631
+#define regDB_DFSM_WATERMARK_BASE_IDX 0
+#define regDB_DFSM_TILES_IN_FLIGHT 0x0632
+#define regDB_DFSM_TILES_IN_FLIGHT_BASE_IDX 0
+#define regDB_DFSM_PRIMS_IN_FLIGHT 0x0633
+#define regDB_DFSM_PRIMS_IN_FLIGHT_BASE_IDX 0
+#define regDB_DFSM_WATCHDOG 0x0634
+#define regDB_DFSM_WATCHDOG_BASE_IDX 0
+#define regDB_DFSM_FLUSH_ENABLE 0x0635
+#define regDB_DFSM_FLUSH_ENABLE_BASE_IDX 0
+#define regDB_DFSM_FLUSH_AUX_EVENT 0x0636
+#define regDB_DFSM_FLUSH_AUX_EVENT_BASE_IDX 0
+#define regCC_RB_REDUNDANCY 0x063c
+#define regCC_RB_REDUNDANCY_BASE_IDX 0
+#define regCC_RB_BACKEND_DISABLE 0x063d
+#define regCC_RB_BACKEND_DISABLE_BASE_IDX 0
+#define regGB_ADDR_CONFIG 0x063e
+#define regGB_ADDR_CONFIG_BASE_IDX 0
+#define regGB_BACKEND_MAP 0x063f
+#define regGB_BACKEND_MAP_BASE_IDX 0
+#define regGB_GPU_ID 0x0640
+#define regGB_GPU_ID_BASE_IDX 0
+#define regCC_RB_DAISY_CHAIN 0x0641
+#define regCC_RB_DAISY_CHAIN_BASE_IDX 0
+#define regGB_ADDR_CONFIG_READ 0x0642
+#define regGB_ADDR_CONFIG_READ_BASE_IDX 0
+#define regGB_TILE_MODE0 0x0644
+#define regGB_TILE_MODE0_BASE_IDX 0
+#define regGB_TILE_MODE1 0x0645
+#define regGB_TILE_MODE1_BASE_IDX 0
+#define regGB_TILE_MODE2 0x0646
+#define regGB_TILE_MODE2_BASE_IDX 0
+#define regGB_TILE_MODE3 0x0647
+#define regGB_TILE_MODE3_BASE_IDX 0
+#define regGB_TILE_MODE4 0x0648
+#define regGB_TILE_MODE4_BASE_IDX 0
+#define regGB_TILE_MODE5 0x0649
+#define regGB_TILE_MODE5_BASE_IDX 0
+#define regGB_TILE_MODE6 0x064a
+#define regGB_TILE_MODE6_BASE_IDX 0
+#define regGB_TILE_MODE7 0x064b
+#define regGB_TILE_MODE7_BASE_IDX 0
+#define regGB_TILE_MODE8 0x064c
+#define regGB_TILE_MODE8_BASE_IDX 0
+#define regGB_TILE_MODE9 0x064d
+#define regGB_TILE_MODE9_BASE_IDX 0
+#define regGB_TILE_MODE10 0x064e
+#define regGB_TILE_MODE10_BASE_IDX 0
+#define regGB_TILE_MODE11 0x064f
+#define regGB_TILE_MODE11_BASE_IDX 0
+#define regGB_TILE_MODE12 0x0650
+#define regGB_TILE_MODE12_BASE_IDX 0
+#define regGB_TILE_MODE13 0x0651
+#define regGB_TILE_MODE13_BASE_IDX 0
+#define regGB_TILE_MODE14 0x0652
+#define regGB_TILE_MODE14_BASE_IDX 0
+#define regGB_TILE_MODE15 0x0653
+#define regGB_TILE_MODE15_BASE_IDX 0
+#define regGB_TILE_MODE16 0x0654
+#define regGB_TILE_MODE16_BASE_IDX 0
+#define regGB_TILE_MODE17 0x0655
+#define regGB_TILE_MODE17_BASE_IDX 0
+#define regGB_TILE_MODE18 0x0656
+#define regGB_TILE_MODE18_BASE_IDX 0
+#define regGB_TILE_MODE19 0x0657
+#define regGB_TILE_MODE19_BASE_IDX 0
+#define regGB_TILE_MODE20 0x0658
+#define regGB_TILE_MODE20_BASE_IDX 0
+#define regGB_TILE_MODE21 0x0659
+#define regGB_TILE_MODE21_BASE_IDX 0
+#define regGB_TILE_MODE22 0x065a
+#define regGB_TILE_MODE22_BASE_IDX 0
+#define regGB_TILE_MODE23 0x065b
+#define regGB_TILE_MODE23_BASE_IDX 0
+#define regGB_TILE_MODE24 0x065c
+#define regGB_TILE_MODE24_BASE_IDX 0
+#define regGB_TILE_MODE25 0x065d
+#define regGB_TILE_MODE25_BASE_IDX 0
+#define regGB_TILE_MODE26 0x065e
+#define regGB_TILE_MODE26_BASE_IDX 0
+#define regGB_TILE_MODE27 0x065f
+#define regGB_TILE_MODE27_BASE_IDX 0
+#define regGB_TILE_MODE28 0x0660
+#define regGB_TILE_MODE28_BASE_IDX 0
+#define regGB_TILE_MODE29 0x0661
+#define regGB_TILE_MODE29_BASE_IDX 0
+#define regGB_TILE_MODE30 0x0662
+#define regGB_TILE_MODE30_BASE_IDX 0
+#define regGB_TILE_MODE31 0x0663
+#define regGB_TILE_MODE31_BASE_IDX 0
+#define regGB_MACROTILE_MODE0 0x0664
+#define regGB_MACROTILE_MODE0_BASE_IDX 0
+#define regGB_MACROTILE_MODE1 0x0665
+#define regGB_MACROTILE_MODE1_BASE_IDX 0
+#define regGB_MACROTILE_MODE2 0x0666
+#define regGB_MACROTILE_MODE2_BASE_IDX 0
+#define regGB_MACROTILE_MODE3 0x0667
+#define regGB_MACROTILE_MODE3_BASE_IDX 0
+#define regGB_MACROTILE_MODE4 0x0668
+#define regGB_MACROTILE_MODE4_BASE_IDX 0
+#define regGB_MACROTILE_MODE5 0x0669
+#define regGB_MACROTILE_MODE5_BASE_IDX 0
+#define regGB_MACROTILE_MODE6 0x066a
+#define regGB_MACROTILE_MODE6_BASE_IDX 0
+#define regGB_MACROTILE_MODE7 0x066b
+#define regGB_MACROTILE_MODE7_BASE_IDX 0
+#define regGB_MACROTILE_MODE8 0x066c
+#define regGB_MACROTILE_MODE8_BASE_IDX 0
+#define regGB_MACROTILE_MODE9 0x066d
+#define regGB_MACROTILE_MODE9_BASE_IDX 0
+#define regGB_MACROTILE_MODE10 0x066e
+#define regGB_MACROTILE_MODE10_BASE_IDX 0
+#define regGB_MACROTILE_MODE11 0x066f
+#define regGB_MACROTILE_MODE11_BASE_IDX 0
+#define regGB_MACROTILE_MODE12 0x0670
+#define regGB_MACROTILE_MODE12_BASE_IDX 0
+#define regGB_MACROTILE_MODE13 0x0671
+#define regGB_MACROTILE_MODE13_BASE_IDX 0
+#define regGB_MACROTILE_MODE14 0x0672
+#define regGB_MACROTILE_MODE14_BASE_IDX 0
+#define regGB_MACROTILE_MODE15 0x0673
+#define regGB_MACROTILE_MODE15_BASE_IDX 0
+#define regCB_HW_CONTROL 0x0680
+#define regCB_HW_CONTROL_BASE_IDX 0
+#define regCB_HW_CONTROL_1 0x0681
+#define regCB_HW_CONTROL_1_BASE_IDX 0
+#define regCB_HW_CONTROL_2 0x0682
+#define regCB_HW_CONTROL_2_BASE_IDX 0
+#define regCB_HW_CONTROL_3 0x0683
+#define regCB_HW_CONTROL_3_BASE_IDX 0
+#define regCB_HW_MEM_ARBITER_RD 0x0686
+#define regCB_HW_MEM_ARBITER_RD_BASE_IDX 0
+#define regCB_HW_MEM_ARBITER_WR 0x0687
+#define regCB_HW_MEM_ARBITER_WR_BASE_IDX 0
+#define regCB_DCC_CONFIG 0x0688
+#define regCB_DCC_CONFIG_BASE_IDX 0
+#define regGC_USER_RB_REDUNDANCY 0x06de
+#define regGC_USER_RB_REDUNDANCY_BASE_IDX 0
+#define regGC_USER_RB_BACKEND_DISABLE 0x06df
+#define regGC_USER_RB_BACKEND_DISABLE_BASE_IDX 0
+
+
+// addressBlock: gc_rlcpdec
+// base address: 0x3b000
+#define regRLC_CNTL 0x4c00
+#define regRLC_CNTL_BASE_IDX 1
+#define regRLC_STAT 0x4c04
+#define regRLC_STAT_BASE_IDX 1
+#define regRLC_SAFE_MODE 0x4c05
+#define regRLC_SAFE_MODE_BASE_IDX 1
+#define regRLC_MEM_SLP_CNTL 0x4c06
+#define regRLC_MEM_SLP_CNTL_BASE_IDX 1
+#define regRLC_RLCV_SAFE_MODE 0x4c08
+#define regRLC_RLCV_SAFE_MODE_BASE_IDX 1
+#define regRLC_RLCV_COMMAND 0x4c0a
+#define regRLC_RLCV_COMMAND_BASE_IDX 1
+#define regRLC_REFCLOCK_TIMESTAMP_LSB 0x4c0c
+#define regRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX 1
+#define regRLC_REFCLOCK_TIMESTAMP_MSB 0x4c0d
+#define regRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX 1
+#define regRLC_GPM_TIMER_INT_0 0x4c0e
+#define regRLC_GPM_TIMER_INT_0_BASE_IDX 1
+#define regRLC_GPM_TIMER_INT_1 0x4c0f
+#define regRLC_GPM_TIMER_INT_1_BASE_IDX 1
+#define regRLC_GPM_TIMER_INT_2 0x4c10
+#define regRLC_GPM_TIMER_INT_2_BASE_IDX 1
+#define regRLC_GPM_TIMER_CTRL 0x4c11
+#define regRLC_GPM_TIMER_CTRL_BASE_IDX 1
+#define regRLC_LB_CNTR_MAX 0x4c12
+#define regRLC_LB_CNTR_MAX_BASE_IDX 1
+#define regRLC_GPM_TIMER_STAT 0x4c13
+#define regRLC_GPM_TIMER_STAT_BASE_IDX 1
+#define regRLC_GPM_TIMER_INT_3 0x4c15
+#define regRLC_GPM_TIMER_INT_3_BASE_IDX 1
+#define regRLC_SERDES_WR_NONCU_MASTER_MASK_1 0x4c16
+#define regRLC_SERDES_WR_NONCU_MASTER_MASK_1_BASE_IDX 1
+#define regRLC_SERDES_NONCU_MASTER_BUSY_1 0x4c17
+#define regRLC_SERDES_NONCU_MASTER_BUSY_1_BASE_IDX 1
+#define regRLC_INT_STAT 0x4c18
+#define regRLC_INT_STAT_BASE_IDX 1
+#define regRLC_LB_CNTL 0x4c19
+#define regRLC_LB_CNTL_BASE_IDX 1
+#define regRLC_MGCG_CTRL 0x4c1a
+#define regRLC_MGCG_CTRL_BASE_IDX 1
+#define regRLC_LB_CNTR_INIT 0x4c1b
+#define regRLC_LB_CNTR_INIT_BASE_IDX 1
+#define regRLC_LOAD_BALANCE_CNTR 0x4c1c
+#define regRLC_LOAD_BALANCE_CNTR_BASE_IDX 1
+#define regRLC_JUMP_TABLE_RESTORE 0x4c1e
+#define regRLC_JUMP_TABLE_RESTORE_BASE_IDX 1
+#define regRLC_PG_DELAY_2 0x4c1f
+#define regRLC_PG_DELAY_2_BASE_IDX 1
+#define regRLC_GPU_CLOCK_COUNT_LSB 0x4c24
+#define regRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX 1
+#define regRLC_GPU_CLOCK_COUNT_MSB 0x4c25
+#define regRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX 1
+#define regRLC_CAPTURE_GPU_CLOCK_COUNT 0x4c26
+#define regRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX 1
+#define regRLC_UCODE_CNTL 0x4c27
+#define regRLC_UCODE_CNTL_BASE_IDX 1
+#define regRLC_GPM_THREAD_RESET 0x4c28
+#define regRLC_GPM_THREAD_RESET_BASE_IDX 1
+#define regRLC_GPM_CP_DMA_COMPLETE_T0 0x4c29
+#define regRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX 1
+#define regRLC_GPM_CP_DMA_COMPLETE_T1 0x4c2a
+#define regRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX 1
+#define regRLC_CLK_COUNT_GFXCLK_LSB 0x4c30
+#define regRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX 1
+#define regRLC_CLK_COUNT_GFXCLK_MSB 0x4c31
+#define regRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX 1
+#define regRLC_CLK_COUNT_REFCLK_LSB 0x4c32
+#define regRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX 1
+#define regRLC_CLK_COUNT_REFCLK_MSB 0x4c33
+#define regRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX 1
+#define regRLC_CLK_COUNT_CTRL 0x4c34
+#define regRLC_CLK_COUNT_CTRL_BASE_IDX 1
+#define regRLC_CLK_COUNT_STAT 0x4c35
+#define regRLC_CLK_COUNT_STAT_BASE_IDX 1
+#define regRLC_GPM_STAT 0x4c40
+#define regRLC_GPM_STAT_BASE_IDX 1
+#define regRLC_GPU_CLOCK_32_RES_SEL 0x4c41
+#define regRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX 1
+#define regRLC_GPU_CLOCK_32 0x4c42
+#define regRLC_GPU_CLOCK_32_BASE_IDX 1
+#define regRLC_PG_CNTL 0x4c43
+#define regRLC_PG_CNTL_BASE_IDX 1
+#define regRLC_GPM_THREAD_PRIORITY 0x4c44
+#define regRLC_GPM_THREAD_PRIORITY_BASE_IDX 1
+#define regRLC_GPM_THREAD_ENABLE 0x4c45
+#define regRLC_GPM_THREAD_ENABLE_BASE_IDX 1
+#define regRLC_CGTT_MGCG_OVERRIDE 0x4c48
+#define regRLC_CGTT_MGCG_OVERRIDE_BASE_IDX 1
+#define regRLC_CGCG_CGLS_CTRL 0x4c49
+#define regRLC_CGCG_CGLS_CTRL_BASE_IDX 1
+#define regRLC_CGCG_RAMP_CTRL 0x4c4a
+#define regRLC_CGCG_RAMP_CTRL_BASE_IDX 1
+#define regRLC_DYN_PG_STATUS 0x4c4b
+#define regRLC_DYN_PG_STATUS_BASE_IDX 1
+#define regRLC_DYN_PG_REQUEST 0x4c4c
+#define regRLC_DYN_PG_REQUEST_BASE_IDX 1
+#define regRLC_PG_DELAY 0x4c4d
+#define regRLC_PG_DELAY_BASE_IDX 1
+#define regRLC_CU_STATUS 0x4c4e
+#define regRLC_CU_STATUS_BASE_IDX 1
+#define regRLC_LB_INIT_CU_MASK 0x4c4f
+#define regRLC_LB_INIT_CU_MASK_BASE_IDX 1
+#define regRLC_LB_ALWAYS_ACTIVE_CU_MASK 0x4c50
+#define regRLC_LB_ALWAYS_ACTIVE_CU_MASK_BASE_IDX 1
+#define regRLC_LB_PARAMS 0x4c51
+#define regRLC_LB_PARAMS_BASE_IDX 1
+#define regRLC_THREAD1_DELAY 0x4c52
+#define regRLC_THREAD1_DELAY_BASE_IDX 1
+#define regRLC_PG_ALWAYS_ON_CU_MASK 0x4c53
+#define regRLC_PG_ALWAYS_ON_CU_MASK_BASE_IDX 1
+#define regRLC_MAX_PG_CU 0x4c54
+#define regRLC_MAX_PG_CU_BASE_IDX 1
+#define regRLC_AUTO_PG_CTRL 0x4c55
+#define regRLC_AUTO_PG_CTRL_BASE_IDX 1
+#define regRLC_SERDES_RD_PENDING 0x4c58
+#define regRLC_SERDES_RD_PENDING_BASE_IDX 1
+#define regRLC_SERDES_RD_MASTER_INDEX 0x4c59
+#define regRLC_SERDES_RD_MASTER_INDEX_BASE_IDX 1
+#define regRLC_SERDES_RD_DATA_0 0x4c5a
+#define regRLC_SERDES_RD_DATA_0_BASE_IDX 1
+#define regRLC_SERDES_RD_DATA_1 0x4c5b
+#define regRLC_SERDES_RD_DATA_1_BASE_IDX 1
+#define regRLC_SERDES_RD_DATA_2 0x4c5c
+#define regRLC_SERDES_RD_DATA_2_BASE_IDX 1
+#define regRLC_SERDES_WR_CU_MASTER_MASK 0x4c5d
+#define regRLC_SERDES_WR_CU_MASTER_MASK_BASE_IDX 1
+#define regRLC_SERDES_WR_NONCU_MASTER_MASK 0x4c5e
+#define regRLC_SERDES_WR_NONCU_MASTER_MASK_BASE_IDX 1
+#define regRLC_SERDES_WR_CTRL 0x4c5f
+#define regRLC_SERDES_WR_CTRL_BASE_IDX 1
+#define regRLC_SERDES_WR_DATA 0x4c60
+#define regRLC_SERDES_WR_DATA_BASE_IDX 1
+#define regRLC_SERDES_CU_MASTER_BUSY 0x4c61
+#define regRLC_SERDES_CU_MASTER_BUSY_BASE_IDX 1
+#define regRLC_SERDES_NONCU_MASTER_BUSY 0x4c62
+#define regRLC_SERDES_NONCU_MASTER_BUSY_BASE_IDX 1
+#define regRLC_GPM_GENERAL_0 0x4c63
+#define regRLC_GPM_GENERAL_0_BASE_IDX 1
+#define regRLC_GPM_GENERAL_1 0x4c64
+#define regRLC_GPM_GENERAL_1_BASE_IDX 1
+#define regRLC_GPM_GENERAL_2 0x4c65
+#define regRLC_GPM_GENERAL_2_BASE_IDX 1
+#define regRLC_GPM_GENERAL_3 0x4c66
+#define regRLC_GPM_GENERAL_3_BASE_IDX 1
+#define regRLC_GPM_GENERAL_4 0x4c67
+#define regRLC_GPM_GENERAL_4_BASE_IDX 1
+#define regRLC_GPM_GENERAL_5 0x4c68
+#define regRLC_GPM_GENERAL_5_BASE_IDX 1
+#define regRLC_GPM_GENERAL_6 0x4c69
+#define regRLC_GPM_GENERAL_6_BASE_IDX 1
+#define regRLC_GPM_GENERAL_7 0x4c6a
+#define regRLC_GPM_GENERAL_7_BASE_IDX 1
+#define regRLC_GPM_SCRATCH_ADDR 0x4c6c
+#define regRLC_GPM_SCRATCH_ADDR_BASE_IDX 1
+#define regRLC_GPM_SCRATCH_DATA 0x4c6d
+#define regRLC_GPM_SCRATCH_DATA_BASE_IDX 1
+#define regRLC_STATIC_PG_STATUS 0x4c6e
+#define regRLC_STATIC_PG_STATUS_BASE_IDX 1
+#define regRLC_SPM_MC_CNTL 0x4c71
+#define regRLC_SPM_MC_CNTL_BASE_IDX 1
+#define regRLC_SPM_INT_CNTL 0x4c72
+#define regRLC_SPM_INT_CNTL_BASE_IDX 1
+#define regRLC_SPM_INT_STATUS 0x4c73
+#define regRLC_SPM_INT_STATUS_BASE_IDX 1
+#define regRLC_GPM_LOG_SIZE 0x4c77
+#define regRLC_GPM_LOG_SIZE_BASE_IDX 1
+#define regRLC_PG_DELAY_3 0x4c78
+#define regRLC_PG_DELAY_3_BASE_IDX 1
+#define regRLC_GPR_REG1 0x4c79
+#define regRLC_GPR_REG1_BASE_IDX 1
+#define regRLC_GPR_REG2 0x4c7a
+#define regRLC_GPR_REG2_BASE_IDX 1
+#define regRLC_GPM_LOG_CONT 0x4c7b
+#define regRLC_GPM_LOG_CONT_BASE_IDX 1
+#define regRLC_GPM_INT_DISABLE_TH0 0x4c7c
+#define regRLC_GPM_INT_DISABLE_TH0_BASE_IDX 1
+#define regRLC_GPM_INT_FORCE_TH0 0x4c7e
+#define regRLC_GPM_INT_FORCE_TH0_BASE_IDX 1
+#define regRLC_GPM_INT_FORCE_TH1 0x4c7f
+#define regRLC_GPM_INT_FORCE_TH1_BASE_IDX 1
+#define regRLC_SRM_CNTL 0x4c80
+#define regRLC_SRM_CNTL_BASE_IDX 1
+#define regRLC_SRM_ARAM_ADDR 0x4c83
+#define regRLC_SRM_ARAM_ADDR_BASE_IDX 1
+#define regRLC_SRM_ARAM_DATA 0x4c84
+#define regRLC_SRM_ARAM_DATA_BASE_IDX 1
+#define regRLC_SRM_DRAM_ADDR 0x4c85
+#define regRLC_SRM_DRAM_ADDR_BASE_IDX 1
+#define regRLC_SRM_DRAM_DATA 0x4c86
+#define regRLC_SRM_DRAM_DATA_BASE_IDX 1
+#define regRLC_SRM_GPM_COMMAND 0x4c87
+#define regRLC_SRM_GPM_COMMAND_BASE_IDX 1
+#define regRLC_SRM_GPM_COMMAND_STATUS 0x4c88
+#define regRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX 1
+#define regRLC_SRM_RLCV_COMMAND 0x4c89
+#define regRLC_SRM_RLCV_COMMAND_BASE_IDX 1
+#define regRLC_SRM_RLCV_COMMAND_STATUS 0x4c8a
+#define regRLC_SRM_RLCV_COMMAND_STATUS_BASE_IDX 1
+#define regRLC_SRM_INDEX_CNTL_ADDR_0 0x4c8b
+#define regRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX 1
+#define regRLC_SRM_INDEX_CNTL_ADDR_1 0x4c8c
+#define regRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX 1
+#define regRLC_SRM_INDEX_CNTL_ADDR_2 0x4c8d
+#define regRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX 1
+#define regRLC_SRM_INDEX_CNTL_ADDR_3 0x4c8e
+#define regRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX 1
+#define regRLC_SRM_INDEX_CNTL_ADDR_4 0x4c8f
+#define regRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX 1
+#define regRLC_SRM_INDEX_CNTL_ADDR_5 0x4c90
+#define regRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX 1
+#define regRLC_SRM_INDEX_CNTL_ADDR_6 0x4c91
+#define regRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX 1
+#define regRLC_SRM_INDEX_CNTL_ADDR_7 0x4c92
+#define regRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX 1
+#define regRLC_SRM_INDEX_CNTL_DATA_0 0x4c93
+#define regRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX 1
+#define regRLC_SRM_INDEX_CNTL_DATA_1 0x4c94
+#define regRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX 1
+#define regRLC_SRM_INDEX_CNTL_DATA_2 0x4c95
+#define regRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX 1
+#define regRLC_SRM_INDEX_CNTL_DATA_3 0x4c96
+#define regRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX 1
+#define regRLC_SRM_INDEX_CNTL_DATA_4 0x4c97
+#define regRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX 1
+#define regRLC_SRM_INDEX_CNTL_DATA_5 0x4c98
+#define regRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX 1
+#define regRLC_SRM_INDEX_CNTL_DATA_6 0x4c99
+#define regRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX 1
+#define regRLC_SRM_INDEX_CNTL_DATA_7 0x4c9a
+#define regRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX 1
+#define regRLC_SRM_STAT 0x4c9b
+#define regRLC_SRM_STAT_BASE_IDX 1
+#define regRLC_SRM_GPM_ABORT 0x4c9c
+#define regRLC_SRM_GPM_ABORT_BASE_IDX 1
+#define regRLC_CSIB_ADDR_LO 0x4ca2
+#define regRLC_CSIB_ADDR_LO_BASE_IDX 1
+#define regRLC_CSIB_ADDR_HI 0x4ca3
+#define regRLC_CSIB_ADDR_HI_BASE_IDX 1
+#define regRLC_CSIB_LENGTH 0x4ca4
+#define regRLC_CSIB_LENGTH_BASE_IDX 1
+#define regRLC_CP_SCHEDULERS 0x4caa
+#define regRLC_CP_SCHEDULERS_BASE_IDX 1
+#define regRLC_GPM_GENERAL_8 0x4cad
+#define regRLC_GPM_GENERAL_8_BASE_IDX 1
+#define regRLC_GPM_GENERAL_9 0x4cae
+#define regRLC_GPM_GENERAL_9_BASE_IDX 1
+#define regRLC_GPM_GENERAL_10 0x4caf
+#define regRLC_GPM_GENERAL_10_BASE_IDX 1
+#define regRLC_GPM_GENERAL_11 0x4cb0
+#define regRLC_GPM_GENERAL_11_BASE_IDX 1
+#define regRLC_GPM_GENERAL_12 0x4cb1
+#define regRLC_GPM_GENERAL_12_BASE_IDX 1
+#define regRLC_GPM_UTCL1_CNTL_0 0x4cb2
+#define regRLC_GPM_UTCL1_CNTL_0_BASE_IDX 1
+#define regRLC_GPM_UTCL1_CNTL_1 0x4cb3
+#define regRLC_GPM_UTCL1_CNTL_1_BASE_IDX 1
+#define regRLC_GPM_UTCL1_CNTL_2 0x4cb4
+#define regRLC_GPM_UTCL1_CNTL_2_BASE_IDX 1
+#define regRLC_SPM_UTCL1_CNTL 0x4cb5
+#define regRLC_SPM_UTCL1_CNTL_BASE_IDX 1
+#define regRLC_UTCL1_STATUS_2 0x4cb6
+#define regRLC_UTCL1_STATUS_2_BASE_IDX 1
+#define regRLC_LB_THR_CONFIG_2 0x4cb8
+#define regRLC_LB_THR_CONFIG_2_BASE_IDX 1
+#define regRLC_LB_THR_CONFIG_3 0x4cb9
+#define regRLC_LB_THR_CONFIG_3_BASE_IDX 1
+#define regRLC_LB_THR_CONFIG_4 0x4cba
+#define regRLC_LB_THR_CONFIG_4_BASE_IDX 1
+#define regRLC_SPM_UTCL1_ERROR_1 0x4cbc
+#define regRLC_SPM_UTCL1_ERROR_1_BASE_IDX 1
+#define regRLC_SPM_UTCL1_ERROR_2 0x4cbd
+#define regRLC_SPM_UTCL1_ERROR_2_BASE_IDX 1
+#define regRLC_GPM_UTCL1_TH0_ERROR_1 0x4cbe
+#define regRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX 1
+#define regRLC_LB_THR_CONFIG_1 0x4cbf
+#define regRLC_LB_THR_CONFIG_1_BASE_IDX 1
+#define regRLC_GPM_UTCL1_TH0_ERROR_2 0x4cc0
+#define regRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX 1
+#define regRLC_GPM_UTCL1_TH1_ERROR_1 0x4cc1
+#define regRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX 1
+#define regRLC_GPM_UTCL1_TH1_ERROR_2 0x4cc2
+#define regRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX 1
+#define regRLC_GPM_UTCL1_TH2_ERROR_1 0x4cc3
+#define regRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX 1
+#define regRLC_GPM_UTCL1_TH2_ERROR_2 0x4cc4
+#define regRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX 1
+#define regRLC_SEMAPHORE_0 0x4cc7
+#define regRLC_SEMAPHORE_0_BASE_IDX 1
+#define regRLC_SEMAPHORE_1 0x4cc8
+#define regRLC_SEMAPHORE_1_BASE_IDX 1
+#define regRLC_CP_EOF_INT 0x4cca
+#define regRLC_CP_EOF_INT_BASE_IDX 1
+#define regRLC_CP_EOF_INT_CNT 0x4ccb
+#define regRLC_CP_EOF_INT_CNT_BASE_IDX 1
+#define regRLC_SPARE_INT 0x4ccc
+#define regRLC_SPARE_INT_BASE_IDX 1
+#define regRLC_PREWALKER_UTCL1_CNTL 0x4ccd
+#define regRLC_PREWALKER_UTCL1_CNTL_BASE_IDX 1
+#define regRLC_PREWALKER_UTCL1_TRIG 0x4cce
+#define regRLC_PREWALKER_UTCL1_TRIG_BASE_IDX 1
+#define regRLC_PREWALKER_UTCL1_ADDR_LSB 0x4ccf
+#define regRLC_PREWALKER_UTCL1_ADDR_LSB_BASE_IDX 1
+#define regRLC_PREWALKER_UTCL1_ADDR_MSB 0x4cd0
+#define regRLC_PREWALKER_UTCL1_ADDR_MSB_BASE_IDX 1
+#define regRLC_PREWALKER_UTCL1_SIZE_LSB 0x4cd1
+#define regRLC_PREWALKER_UTCL1_SIZE_LSB_BASE_IDX 1
+#define regRLC_PREWALKER_UTCL1_SIZE_MSB 0x4cd2
+#define regRLC_PREWALKER_UTCL1_SIZE_MSB_BASE_IDX 1
+#define regRLC_DSM_TRIG 0x4cd3
+#define regRLC_DSM_TRIG_BASE_IDX 1
+#define regRLC_UTCL1_STATUS 0x4cd4
+#define regRLC_UTCL1_STATUS_BASE_IDX 1
+#define regRLC_R2I_CNTL_0 0x4cd5
+#define regRLC_R2I_CNTL_0_BASE_IDX 1
+#define regRLC_R2I_CNTL_1 0x4cd6
+#define regRLC_R2I_CNTL_1_BASE_IDX 1
+#define regRLC_R2I_CNTL_2 0x4cd7
+#define regRLC_R2I_CNTL_2_BASE_IDX 1
+#define regRLC_R2I_CNTL_3 0x4cd8
+#define regRLC_R2I_CNTL_3_BASE_IDX 1
+#define regRLC_UTCL2_CNTL 0x4cd9
+#define regRLC_UTCL2_CNTL_BASE_IDX 1
+#define regRLC_LBPW_CU_STAT 0x4cda
+#define regRLC_LBPW_CU_STAT_BASE_IDX 1
+#define regRLC_DS_CNTL 0x4cdb
+#define regRLC_DS_CNTL_BASE_IDX 1
+#define regRLC_GPM_INT_STAT_TH0 0x4cdc
+#define regRLC_GPM_INT_STAT_TH0_BASE_IDX 1
+#define regRLC_GPM_GENERAL_13 0x4cdd
+#define regRLC_GPM_GENERAL_13_BASE_IDX 1
+#define regRLC_GPM_GENERAL_14 0x4cde
+#define regRLC_GPM_GENERAL_14_BASE_IDX 1
+#define regRLC_GPM_GENERAL_15 0x4cdf
+#define regRLC_GPM_GENERAL_15_BASE_IDX 1
+#define regRLC_SPARE_INT_1 0x4ce0
+#define regRLC_SPARE_INT_1_BASE_IDX 1
+#define regRLC_RLCV_SPARE_INT_1 0x4ce1
+#define regRLC_RLCV_SPARE_INT_1_BASE_IDX 1
+#define regRLC_SEMAPHORE_2 0x4ce3
+#define regRLC_SEMAPHORE_2_BASE_IDX 1
+#define regRLC_SEMAPHORE_3 0x4ce4
+#define regRLC_SEMAPHORE_3_BASE_IDX 1
+#define regRLC_GPU_CLOCK_COUNT_LSB_1 0x4ce8
+#define regRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX 1
+#define regRLC_GPU_CLOCK_COUNT_MSB_1 0x4ce9
+#define regRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX 1
+#define regRLC_CAPTURE_GPU_CLOCK_COUNT_1 0x4cea
+#define regRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX 1
+#define regRLC_GPU_CLOCK_COUNT_LSB_2 0x4ceb
+#define regRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX 1
+#define regRLC_GPU_CLOCK_COUNT_MSB_2 0x4cec
+#define regRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX 1
+#define regRLC_CAPTURE_GPU_CLOCK_COUNT_2 0x4cef
+#define regRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX 1
+#define regRLC_CPG_STAT_INVAL 0x4d09
+#define regRLC_CPG_STAT_INVAL_BASE_IDX 1
+#define regRLC_EDC_CNT 0x4d40
+#define regRLC_EDC_CNT_BASE_IDX 1
+#define regRLC_EDC_CNT2 0x4d41
+#define regRLC_EDC_CNT2_BASE_IDX 1
+#define regRLC_DSM_CNTL 0x4d42
+#define regRLC_DSM_CNTL_BASE_IDX 1
+#define regRLC_DSM_CNTLA 0x4d43
+#define regRLC_DSM_CNTLA_BASE_IDX 1
+#define regRLC_DSM_CNTL2 0x4d44
+#define regRLC_DSM_CNTL2_BASE_IDX 1
+#define regRLC_DSM_CNTL2A 0x4d45
+#define regRLC_DSM_CNTL2A_BASE_IDX 1
+#define regRLC_RLCV_SPARE_INT 0x4f30
+#define regRLC_RLCV_SPARE_INT_BASE_IDX 1
+
+
+// addressBlock: gc_rmi_rmidec
+// base address: 0x9e00
+#define regRMI_GENERAL_CNTL 0x0780
+#define regRMI_GENERAL_CNTL_BASE_IDX 0
+#define regRMI_GENERAL_CNTL1 0x0781
+#define regRMI_GENERAL_CNTL1_BASE_IDX 0
+#define regRMI_GENERAL_STATUS 0x0782
+#define regRMI_GENERAL_STATUS_BASE_IDX 0
+#define regRMI_SUBBLOCK_STATUS0 0x0783
+#define regRMI_SUBBLOCK_STATUS0_BASE_IDX 0
+#define regRMI_SUBBLOCK_STATUS1 0x0784
+#define regRMI_SUBBLOCK_STATUS1_BASE_IDX 0
+#define regRMI_SUBBLOCK_STATUS2 0x0785
+#define regRMI_SUBBLOCK_STATUS2_BASE_IDX 0
+#define regRMI_SUBBLOCK_STATUS3 0x0786
+#define regRMI_SUBBLOCK_STATUS3_BASE_IDX 0
+#define regRMI_XBAR_CONFIG 0x0787
+#define regRMI_XBAR_CONFIG_BASE_IDX 0
+#define regRMI_PROBE_POP_LOGIC_CNTL 0x0788
+#define regRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX 0
+#define regRMI_UTC_XNACK_N_MISC_CNTL 0x0789
+#define regRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX 0
+#define regRMI_DEMUX_CNTL 0x078a
+#define regRMI_DEMUX_CNTL_BASE_IDX 0
+#define regRMI_UTCL1_CNTL1 0x078b
+#define regRMI_UTCL1_CNTL1_BASE_IDX 0
+#define regRMI_UTCL1_CNTL2 0x078c
+#define regRMI_UTCL1_CNTL2_BASE_IDX 0
+#define regRMI_UTC_UNIT_CONFIG 0x078d
+#define regRMI_UTC_UNIT_CONFIG_BASE_IDX 0
+#define regRMI_TCIW_FORMATTER0_CNTL 0x078e
+#define regRMI_TCIW_FORMATTER0_CNTL_BASE_IDX 0
+#define regRMI_TCIW_FORMATTER1_CNTL 0x078f
+#define regRMI_TCIW_FORMATTER1_CNTL_BASE_IDX 0
+#define regRMI_SCOREBOARD_CNTL 0x0790
+#define regRMI_SCOREBOARD_CNTL_BASE_IDX 0
+#define regRMI_SCOREBOARD_STATUS0 0x0791
+#define regRMI_SCOREBOARD_STATUS0_BASE_IDX 0
+#define regRMI_SCOREBOARD_STATUS1 0x0792
+#define regRMI_SCOREBOARD_STATUS1_BASE_IDX 0
+#define regRMI_SCOREBOARD_STATUS2 0x0793
+#define regRMI_SCOREBOARD_STATUS2_BASE_IDX 0
+#define regRMI_XBAR_ARBITER_CONFIG 0x0794
+#define regRMI_XBAR_ARBITER_CONFIG_BASE_IDX 0
+#define regRMI_XBAR_ARBITER_CONFIG_1 0x0795
+#define regRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX 0
+#define regRMI_CLOCK_CNTRL 0x0796
+#define regRMI_CLOCK_CNTRL_BASE_IDX 0
+#define regRMI_UTCL1_STATUS 0x0797
+#define regRMI_UTCL1_STATUS_BASE_IDX 0
+#define regRMI_SPARE 0x079e
+#define regRMI_SPARE_BASE_IDX 0
+#define regRMI_SPARE_1 0x079f
+#define regRMI_SPARE_1_BASE_IDX 0
+#define regRMI_SPARE_2 0x07a0
+#define regRMI_SPARE_2_BASE_IDX 0
+
+
+// addressBlock: gc_shdec
+// base address: 0xb000
+#define regSPI_SHADER_PGM_RSRC3_PS 0x0c07
+#define regSPI_SHADER_PGM_RSRC3_PS_BASE_IDX 0
+#define regSPI_SHADER_PGM_LO_PS 0x0c08
+#define regSPI_SHADER_PGM_LO_PS_BASE_IDX 0
+#define regSPI_SHADER_PGM_HI_PS 0x0c09
+#define regSPI_SHADER_PGM_HI_PS_BASE_IDX 0
+#define regSPI_SHADER_PGM_RSRC1_PS 0x0c0a
+#define regSPI_SHADER_PGM_RSRC1_PS_BASE_IDX 0
+#define regSPI_SHADER_PGM_RSRC2_PS 0x0c0b
+#define regSPI_SHADER_PGM_RSRC2_PS_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_PS_0 0x0c0c
+#define regSPI_SHADER_USER_DATA_PS_0_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_PS_1 0x0c0d
+#define regSPI_SHADER_USER_DATA_PS_1_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_PS_2 0x0c0e
+#define regSPI_SHADER_USER_DATA_PS_2_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_PS_3 0x0c0f
+#define regSPI_SHADER_USER_DATA_PS_3_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_PS_4 0x0c10
+#define regSPI_SHADER_USER_DATA_PS_4_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_PS_5 0x0c11
+#define regSPI_SHADER_USER_DATA_PS_5_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_PS_6 0x0c12
+#define regSPI_SHADER_USER_DATA_PS_6_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_PS_7 0x0c13
+#define regSPI_SHADER_USER_DATA_PS_7_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_PS_8 0x0c14
+#define regSPI_SHADER_USER_DATA_PS_8_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_PS_9 0x0c15
+#define regSPI_SHADER_USER_DATA_PS_9_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_PS_10 0x0c16
+#define regSPI_SHADER_USER_DATA_PS_10_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_PS_11 0x0c17
+#define regSPI_SHADER_USER_DATA_PS_11_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_PS_12 0x0c18
+#define regSPI_SHADER_USER_DATA_PS_12_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_PS_13 0x0c19
+#define regSPI_SHADER_USER_DATA_PS_13_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_PS_14 0x0c1a
+#define regSPI_SHADER_USER_DATA_PS_14_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_PS_15 0x0c1b
+#define regSPI_SHADER_USER_DATA_PS_15_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_PS_16 0x0c1c
+#define regSPI_SHADER_USER_DATA_PS_16_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_PS_17 0x0c1d
+#define regSPI_SHADER_USER_DATA_PS_17_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_PS_18 0x0c1e
+#define regSPI_SHADER_USER_DATA_PS_18_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_PS_19 0x0c1f
+#define regSPI_SHADER_USER_DATA_PS_19_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_PS_20 0x0c20
+#define regSPI_SHADER_USER_DATA_PS_20_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_PS_21 0x0c21
+#define regSPI_SHADER_USER_DATA_PS_21_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_PS_22 0x0c22
+#define regSPI_SHADER_USER_DATA_PS_22_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_PS_23 0x0c23
+#define regSPI_SHADER_USER_DATA_PS_23_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_PS_24 0x0c24
+#define regSPI_SHADER_USER_DATA_PS_24_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_PS_25 0x0c25
+#define regSPI_SHADER_USER_DATA_PS_25_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_PS_26 0x0c26
+#define regSPI_SHADER_USER_DATA_PS_26_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_PS_27 0x0c27
+#define regSPI_SHADER_USER_DATA_PS_27_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_PS_28 0x0c28
+#define regSPI_SHADER_USER_DATA_PS_28_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_PS_29 0x0c29
+#define regSPI_SHADER_USER_DATA_PS_29_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_PS_30 0x0c2a
+#define regSPI_SHADER_USER_DATA_PS_30_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_PS_31 0x0c2b
+#define regSPI_SHADER_USER_DATA_PS_31_BASE_IDX 0
+#define regSPI_SHADER_PGM_RSRC3_VS 0x0c46
+#define regSPI_SHADER_PGM_RSRC3_VS_BASE_IDX 0
+#define regSPI_SHADER_LATE_ALLOC_VS 0x0c47
+#define regSPI_SHADER_LATE_ALLOC_VS_BASE_IDX 0
+#define regSPI_SHADER_PGM_LO_VS 0x0c48
+#define regSPI_SHADER_PGM_LO_VS_BASE_IDX 0
+#define regSPI_SHADER_PGM_HI_VS 0x0c49
+#define regSPI_SHADER_PGM_HI_VS_BASE_IDX 0
+#define regSPI_SHADER_PGM_RSRC1_VS 0x0c4a
+#define regSPI_SHADER_PGM_RSRC1_VS_BASE_IDX 0
+#define regSPI_SHADER_PGM_RSRC2_VS 0x0c4b
+#define regSPI_SHADER_PGM_RSRC2_VS_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_VS_0 0x0c4c
+#define regSPI_SHADER_USER_DATA_VS_0_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_VS_1 0x0c4d
+#define regSPI_SHADER_USER_DATA_VS_1_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_VS_2 0x0c4e
+#define regSPI_SHADER_USER_DATA_VS_2_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_VS_3 0x0c4f
+#define regSPI_SHADER_USER_DATA_VS_3_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_VS_4 0x0c50
+#define regSPI_SHADER_USER_DATA_VS_4_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_VS_5 0x0c51
+#define regSPI_SHADER_USER_DATA_VS_5_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_VS_6 0x0c52
+#define regSPI_SHADER_USER_DATA_VS_6_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_VS_7 0x0c53
+#define regSPI_SHADER_USER_DATA_VS_7_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_VS_8 0x0c54
+#define regSPI_SHADER_USER_DATA_VS_8_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_VS_9 0x0c55
+#define regSPI_SHADER_USER_DATA_VS_9_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_VS_10 0x0c56
+#define regSPI_SHADER_USER_DATA_VS_10_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_VS_11 0x0c57
+#define regSPI_SHADER_USER_DATA_VS_11_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_VS_12 0x0c58
+#define regSPI_SHADER_USER_DATA_VS_12_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_VS_13 0x0c59
+#define regSPI_SHADER_USER_DATA_VS_13_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_VS_14 0x0c5a
+#define regSPI_SHADER_USER_DATA_VS_14_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_VS_15 0x0c5b
+#define regSPI_SHADER_USER_DATA_VS_15_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_VS_16 0x0c5c
+#define regSPI_SHADER_USER_DATA_VS_16_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_VS_17 0x0c5d
+#define regSPI_SHADER_USER_DATA_VS_17_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_VS_18 0x0c5e
+#define regSPI_SHADER_USER_DATA_VS_18_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_VS_19 0x0c5f
+#define regSPI_SHADER_USER_DATA_VS_19_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_VS_20 0x0c60
+#define regSPI_SHADER_USER_DATA_VS_20_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_VS_21 0x0c61
+#define regSPI_SHADER_USER_DATA_VS_21_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_VS_22 0x0c62
+#define regSPI_SHADER_USER_DATA_VS_22_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_VS_23 0x0c63
+#define regSPI_SHADER_USER_DATA_VS_23_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_VS_24 0x0c64
+#define regSPI_SHADER_USER_DATA_VS_24_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_VS_25 0x0c65
+#define regSPI_SHADER_USER_DATA_VS_25_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_VS_26 0x0c66
+#define regSPI_SHADER_USER_DATA_VS_26_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_VS_27 0x0c67
+#define regSPI_SHADER_USER_DATA_VS_27_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_VS_28 0x0c68
+#define regSPI_SHADER_USER_DATA_VS_28_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_VS_29 0x0c69
+#define regSPI_SHADER_USER_DATA_VS_29_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_VS_30 0x0c6a
+#define regSPI_SHADER_USER_DATA_VS_30_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_VS_31 0x0c6b
+#define regSPI_SHADER_USER_DATA_VS_31_BASE_IDX 0
+#define regSPI_SHADER_PGM_RSRC2_GS_VS 0x0c7c
+#define regSPI_SHADER_PGM_RSRC2_GS_VS_BASE_IDX 0
+#define regSPI_SHADER_PGM_RSRC4_GS 0x0c81
+#define regSPI_SHADER_PGM_RSRC4_GS_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ADDR_LO_GS 0x0c82
+#define regSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ADDR_HI_GS 0x0c83
+#define regSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX 0
+#define regSPI_SHADER_PGM_LO_ES 0x0c84
+#define regSPI_SHADER_PGM_LO_ES_BASE_IDX 0
+#define regSPI_SHADER_PGM_HI_ES 0x0c85
+#define regSPI_SHADER_PGM_HI_ES_BASE_IDX 0
+#define regSPI_SHADER_PGM_RSRC3_GS 0x0c87
+#define regSPI_SHADER_PGM_RSRC3_GS_BASE_IDX 0
+#define regSPI_SHADER_PGM_LO_GS 0x0c88
+#define regSPI_SHADER_PGM_LO_GS_BASE_IDX 0
+#define regSPI_SHADER_PGM_HI_GS 0x0c89
+#define regSPI_SHADER_PGM_HI_GS_BASE_IDX 0
+#define regSPI_SHADER_PGM_RSRC1_GS 0x0c8a
+#define regSPI_SHADER_PGM_RSRC1_GS_BASE_IDX 0
+#define regSPI_SHADER_PGM_RSRC2_GS 0x0c8b
+#define regSPI_SHADER_PGM_RSRC2_GS_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ES_0 0x0ccc
+#define regSPI_SHADER_USER_DATA_ES_0_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ES_1 0x0ccd
+#define regSPI_SHADER_USER_DATA_ES_1_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ES_2 0x0cce
+#define regSPI_SHADER_USER_DATA_ES_2_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ES_3 0x0ccf
+#define regSPI_SHADER_USER_DATA_ES_3_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ES_4 0x0cd0
+#define regSPI_SHADER_USER_DATA_ES_4_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ES_5 0x0cd1
+#define regSPI_SHADER_USER_DATA_ES_5_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ES_6 0x0cd2
+#define regSPI_SHADER_USER_DATA_ES_6_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ES_7 0x0cd3
+#define regSPI_SHADER_USER_DATA_ES_7_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ES_8 0x0cd4
+#define regSPI_SHADER_USER_DATA_ES_8_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ES_9 0x0cd5
+#define regSPI_SHADER_USER_DATA_ES_9_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ES_10 0x0cd6
+#define regSPI_SHADER_USER_DATA_ES_10_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ES_11 0x0cd7
+#define regSPI_SHADER_USER_DATA_ES_11_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ES_12 0x0cd8
+#define regSPI_SHADER_USER_DATA_ES_12_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ES_13 0x0cd9
+#define regSPI_SHADER_USER_DATA_ES_13_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ES_14 0x0cda
+#define regSPI_SHADER_USER_DATA_ES_14_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ES_15 0x0cdb
+#define regSPI_SHADER_USER_DATA_ES_15_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ES_16 0x0cdc
+#define regSPI_SHADER_USER_DATA_ES_16_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ES_17 0x0cdd
+#define regSPI_SHADER_USER_DATA_ES_17_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ES_18 0x0cde
+#define regSPI_SHADER_USER_DATA_ES_18_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ES_19 0x0cdf
+#define regSPI_SHADER_USER_DATA_ES_19_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ES_20 0x0ce0
+#define regSPI_SHADER_USER_DATA_ES_20_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ES_21 0x0ce1
+#define regSPI_SHADER_USER_DATA_ES_21_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ES_22 0x0ce2
+#define regSPI_SHADER_USER_DATA_ES_22_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ES_23 0x0ce3
+#define regSPI_SHADER_USER_DATA_ES_23_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ES_24 0x0ce4
+#define regSPI_SHADER_USER_DATA_ES_24_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ES_25 0x0ce5
+#define regSPI_SHADER_USER_DATA_ES_25_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ES_26 0x0ce6
+#define regSPI_SHADER_USER_DATA_ES_26_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ES_27 0x0ce7
+#define regSPI_SHADER_USER_DATA_ES_27_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ES_28 0x0ce8
+#define regSPI_SHADER_USER_DATA_ES_28_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ES_29 0x0ce9
+#define regSPI_SHADER_USER_DATA_ES_29_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ES_30 0x0cea
+#define regSPI_SHADER_USER_DATA_ES_30_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ES_31 0x0ceb
+#define regSPI_SHADER_USER_DATA_ES_31_BASE_IDX 0
+#define regSPI_SHADER_PGM_RSRC4_HS 0x0d01
+#define regSPI_SHADER_PGM_RSRC4_HS_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ADDR_LO_HS 0x0d02
+#define regSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_ADDR_HI_HS 0x0d03
+#define regSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX 0
+#define regSPI_SHADER_PGM_LO_LS 0x0d04
+#define regSPI_SHADER_PGM_LO_LS_BASE_IDX 0
+#define regSPI_SHADER_PGM_HI_LS 0x0d05
+#define regSPI_SHADER_PGM_HI_LS_BASE_IDX 0
+#define regSPI_SHADER_PGM_RSRC3_HS 0x0d07
+#define regSPI_SHADER_PGM_RSRC3_HS_BASE_IDX 0
+#define regSPI_SHADER_PGM_LO_HS 0x0d08
+#define regSPI_SHADER_PGM_LO_HS_BASE_IDX 0
+#define regSPI_SHADER_PGM_HI_HS 0x0d09
+#define regSPI_SHADER_PGM_HI_HS_BASE_IDX 0
+#define regSPI_SHADER_PGM_RSRC1_HS 0x0d0a
+#define regSPI_SHADER_PGM_RSRC1_HS_BASE_IDX 0
+#define regSPI_SHADER_PGM_RSRC2_HS 0x0d0b
+#define regSPI_SHADER_PGM_RSRC2_HS_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_LS_0 0x0d0c
+#define regSPI_SHADER_USER_DATA_LS_0_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_LS_1 0x0d0d
+#define regSPI_SHADER_USER_DATA_LS_1_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_LS_2 0x0d0e
+#define regSPI_SHADER_USER_DATA_LS_2_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_LS_3 0x0d0f
+#define regSPI_SHADER_USER_DATA_LS_3_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_LS_4 0x0d10
+#define regSPI_SHADER_USER_DATA_LS_4_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_LS_5 0x0d11
+#define regSPI_SHADER_USER_DATA_LS_5_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_LS_6 0x0d12
+#define regSPI_SHADER_USER_DATA_LS_6_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_LS_7 0x0d13
+#define regSPI_SHADER_USER_DATA_LS_7_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_LS_8 0x0d14
+#define regSPI_SHADER_USER_DATA_LS_8_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_LS_9 0x0d15
+#define regSPI_SHADER_USER_DATA_LS_9_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_LS_10 0x0d16
+#define regSPI_SHADER_USER_DATA_LS_10_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_LS_11 0x0d17
+#define regSPI_SHADER_USER_DATA_LS_11_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_LS_12 0x0d18
+#define regSPI_SHADER_USER_DATA_LS_12_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_LS_13 0x0d19
+#define regSPI_SHADER_USER_DATA_LS_13_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_LS_14 0x0d1a
+#define regSPI_SHADER_USER_DATA_LS_14_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_LS_15 0x0d1b
+#define regSPI_SHADER_USER_DATA_LS_15_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_LS_16 0x0d1c
+#define regSPI_SHADER_USER_DATA_LS_16_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_LS_17 0x0d1d
+#define regSPI_SHADER_USER_DATA_LS_17_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_LS_18 0x0d1e
+#define regSPI_SHADER_USER_DATA_LS_18_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_LS_19 0x0d1f
+#define regSPI_SHADER_USER_DATA_LS_19_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_LS_20 0x0d20
+#define regSPI_SHADER_USER_DATA_LS_20_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_LS_21 0x0d21
+#define regSPI_SHADER_USER_DATA_LS_21_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_LS_22 0x0d22
+#define regSPI_SHADER_USER_DATA_LS_22_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_LS_23 0x0d23
+#define regSPI_SHADER_USER_DATA_LS_23_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_LS_24 0x0d24
+#define regSPI_SHADER_USER_DATA_LS_24_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_LS_25 0x0d25
+#define regSPI_SHADER_USER_DATA_LS_25_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_LS_26 0x0d26
+#define regSPI_SHADER_USER_DATA_LS_26_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_LS_27 0x0d27
+#define regSPI_SHADER_USER_DATA_LS_27_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_LS_28 0x0d28
+#define regSPI_SHADER_USER_DATA_LS_28_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_LS_29 0x0d29
+#define regSPI_SHADER_USER_DATA_LS_29_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_LS_30 0x0d2a
+#define regSPI_SHADER_USER_DATA_LS_30_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_LS_31 0x0d2b
+#define regSPI_SHADER_USER_DATA_LS_31_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_COMMON_0 0x0d4c
+#define regSPI_SHADER_USER_DATA_COMMON_0_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_COMMON_1 0x0d4d
+#define regSPI_SHADER_USER_DATA_COMMON_1_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_COMMON_2 0x0d4e
+#define regSPI_SHADER_USER_DATA_COMMON_2_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_COMMON_3 0x0d4f
+#define regSPI_SHADER_USER_DATA_COMMON_3_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_COMMON_4 0x0d50
+#define regSPI_SHADER_USER_DATA_COMMON_4_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_COMMON_5 0x0d51
+#define regSPI_SHADER_USER_DATA_COMMON_5_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_COMMON_6 0x0d52
+#define regSPI_SHADER_USER_DATA_COMMON_6_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_COMMON_7 0x0d53
+#define regSPI_SHADER_USER_DATA_COMMON_7_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_COMMON_8 0x0d54
+#define regSPI_SHADER_USER_DATA_COMMON_8_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_COMMON_9 0x0d55
+#define regSPI_SHADER_USER_DATA_COMMON_9_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_COMMON_10 0x0d56
+#define regSPI_SHADER_USER_DATA_COMMON_10_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_COMMON_11 0x0d57
+#define regSPI_SHADER_USER_DATA_COMMON_11_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_COMMON_12 0x0d58
+#define regSPI_SHADER_USER_DATA_COMMON_12_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_COMMON_13 0x0d59
+#define regSPI_SHADER_USER_DATA_COMMON_13_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_COMMON_14 0x0d5a
+#define regSPI_SHADER_USER_DATA_COMMON_14_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_COMMON_15 0x0d5b
+#define regSPI_SHADER_USER_DATA_COMMON_15_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_COMMON_16 0x0d5c
+#define regSPI_SHADER_USER_DATA_COMMON_16_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_COMMON_17 0x0d5d
+#define regSPI_SHADER_USER_DATA_COMMON_17_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_COMMON_18 0x0d5e
+#define regSPI_SHADER_USER_DATA_COMMON_18_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_COMMON_19 0x0d5f
+#define regSPI_SHADER_USER_DATA_COMMON_19_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_COMMON_20 0x0d60
+#define regSPI_SHADER_USER_DATA_COMMON_20_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_COMMON_21 0x0d61
+#define regSPI_SHADER_USER_DATA_COMMON_21_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_COMMON_22 0x0d62
+#define regSPI_SHADER_USER_DATA_COMMON_22_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_COMMON_23 0x0d63
+#define regSPI_SHADER_USER_DATA_COMMON_23_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_COMMON_24 0x0d64
+#define regSPI_SHADER_USER_DATA_COMMON_24_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_COMMON_25 0x0d65
+#define regSPI_SHADER_USER_DATA_COMMON_25_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_COMMON_26 0x0d66
+#define regSPI_SHADER_USER_DATA_COMMON_26_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_COMMON_27 0x0d67
+#define regSPI_SHADER_USER_DATA_COMMON_27_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_COMMON_28 0x0d68
+#define regSPI_SHADER_USER_DATA_COMMON_28_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_COMMON_29 0x0d69
+#define regSPI_SHADER_USER_DATA_COMMON_29_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_COMMON_30 0x0d6a
+#define regSPI_SHADER_USER_DATA_COMMON_30_BASE_IDX 0
+#define regSPI_SHADER_USER_DATA_COMMON_31 0x0d6b
+#define regSPI_SHADER_USER_DATA_COMMON_31_BASE_IDX 0
+#define regCOMPUTE_DISPATCH_INITIATOR 0x0e00
+#define regCOMPUTE_DISPATCH_INITIATOR_BASE_IDX 0
+#define regCOMPUTE_DIM_X 0x0e01
+#define regCOMPUTE_DIM_X_BASE_IDX 0
+#define regCOMPUTE_DIM_Y 0x0e02
+#define regCOMPUTE_DIM_Y_BASE_IDX 0
+#define regCOMPUTE_DIM_Z 0x0e03
+#define regCOMPUTE_DIM_Z_BASE_IDX 0
+#define regCOMPUTE_START_X 0x0e04
+#define regCOMPUTE_START_X_BASE_IDX 0
+#define regCOMPUTE_START_Y 0x0e05
+#define regCOMPUTE_START_Y_BASE_IDX 0
+#define regCOMPUTE_START_Z 0x0e06
+#define regCOMPUTE_START_Z_BASE_IDX 0
+#define regCOMPUTE_NUM_THREAD_X 0x0e07
+#define regCOMPUTE_NUM_THREAD_X_BASE_IDX 0
+#define regCOMPUTE_NUM_THREAD_Y 0x0e08
+#define regCOMPUTE_NUM_THREAD_Y_BASE_IDX 0
+#define regCOMPUTE_NUM_THREAD_Z 0x0e09
+#define regCOMPUTE_NUM_THREAD_Z_BASE_IDX 0
+#define regCOMPUTE_PIPELINESTAT_ENABLE 0x0e0a
+#define regCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX 0
+#define regCOMPUTE_PERFCOUNT_ENABLE 0x0e0b
+#define regCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX 0
+#define regCOMPUTE_PGM_LO 0x0e0c
+#define regCOMPUTE_PGM_LO_BASE_IDX 0
+#define regCOMPUTE_PGM_HI 0x0e0d
+#define regCOMPUTE_PGM_HI_BASE_IDX 0
+#define regCOMPUTE_DISPATCH_PKT_ADDR_LO 0x0e0e
+#define regCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX 0
+#define regCOMPUTE_DISPATCH_PKT_ADDR_HI 0x0e0f
+#define regCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX 0
+#define regCOMPUTE_DISPATCH_SCRATCH_BASE_LO 0x0e10
+#define regCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX 0
+#define regCOMPUTE_DISPATCH_SCRATCH_BASE_HI 0x0e11
+#define regCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX 0
+#define regCOMPUTE_PGM_RSRC1 0x0e12
+#define regCOMPUTE_PGM_RSRC1_BASE_IDX 0
+#define regCOMPUTE_PGM_RSRC2 0x0e13
+#define regCOMPUTE_PGM_RSRC2_BASE_IDX 0
+#define regCOMPUTE_VMID 0x0e14
+#define regCOMPUTE_VMID_BASE_IDX 0
+#define regCOMPUTE_RESOURCE_LIMITS 0x0e15
+#define regCOMPUTE_RESOURCE_LIMITS_BASE_IDX 0
+#define regCOMPUTE_STATIC_THREAD_MGMT_SE0 0x0e16
+#define regCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX 0
+#define regCOMPUTE_STATIC_THREAD_MGMT_SE1 0x0e17
+#define regCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX 0
+#define regCOMPUTE_TMPRING_SIZE 0x0e18
+#define regCOMPUTE_TMPRING_SIZE_BASE_IDX 0
+#define regCOMPUTE_STATIC_THREAD_MGMT_SE2 0x0e19
+#define regCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX 0
+#define regCOMPUTE_STATIC_THREAD_MGMT_SE3 0x0e1a
+#define regCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX 0
+#define regCOMPUTE_RESTART_X 0x0e1b
+#define regCOMPUTE_RESTART_X_BASE_IDX 0
+#define regCOMPUTE_RESTART_Y 0x0e1c
+#define regCOMPUTE_RESTART_Y_BASE_IDX 0
+#define regCOMPUTE_RESTART_Z 0x0e1d
+#define regCOMPUTE_RESTART_Z_BASE_IDX 0
+#define regCOMPUTE_THREAD_TRACE_ENABLE 0x0e1e
+#define regCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX 0
+#define regCOMPUTE_MISC_RESERVED 0x0e1f
+#define regCOMPUTE_MISC_RESERVED_BASE_IDX 0
+#define regCOMPUTE_DISPATCH_ID 0x0e20
+#define regCOMPUTE_DISPATCH_ID_BASE_IDX 0
+#define regCOMPUTE_THREADGROUP_ID 0x0e21
+#define regCOMPUTE_THREADGROUP_ID_BASE_IDX 0
+#define regCOMPUTE_RELAUNCH 0x0e22
+#define regCOMPUTE_RELAUNCH_BASE_IDX 0
+#define regCOMPUTE_WAVE_RESTORE_ADDR_LO 0x0e23
+#define regCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX 0
+#define regCOMPUTE_WAVE_RESTORE_ADDR_HI 0x0e24
+#define regCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX 0
+#define regCOMPUTE_STATIC_THREAD_MGMT_SE4 0x0e25
+#define regCOMPUTE_STATIC_THREAD_MGMT_SE4_BASE_IDX 0
+#define regCOMPUTE_STATIC_THREAD_MGMT_SE5 0x0e26
+#define regCOMPUTE_STATIC_THREAD_MGMT_SE5_BASE_IDX 0
+#define regCOMPUTE_STATIC_THREAD_MGMT_SE6 0x0e27
+#define regCOMPUTE_STATIC_THREAD_MGMT_SE6_BASE_IDX 0
+#define regCOMPUTE_STATIC_THREAD_MGMT_SE7 0x0e28
+#define regCOMPUTE_STATIC_THREAD_MGMT_SE7_BASE_IDX 0
+#define regCOMPUTE_RESTART_X2 0x0e29
+#define regCOMPUTE_RESTART_X2_BASE_IDX 0
+#define regCOMPUTE_RESTART_Y2 0x0e2a
+#define regCOMPUTE_RESTART_Y2_BASE_IDX 0
+#define regCOMPUTE_RESTART_Z2 0x0e2b
+#define regCOMPUTE_RESTART_Z2_BASE_IDX 0
+#define regCOMPUTE_SHADER_CHKSUM 0x0e2c
+#define regCOMPUTE_SHADER_CHKSUM_BASE_IDX 0
+#define regCOMPUTE_PGM_RSRC3 0x0e2d
+#define regCOMPUTE_PGM_RSRC3_BASE_IDX 0
+#define regCOMPUTE_USER_DATA_0 0x0e40
+#define regCOMPUTE_USER_DATA_0_BASE_IDX 0
+#define regCOMPUTE_USER_DATA_1 0x0e41
+#define regCOMPUTE_USER_DATA_1_BASE_IDX 0
+#define regCOMPUTE_USER_DATA_2 0x0e42
+#define regCOMPUTE_USER_DATA_2_BASE_IDX 0
+#define regCOMPUTE_USER_DATA_3 0x0e43
+#define regCOMPUTE_USER_DATA_3_BASE_IDX 0
+#define regCOMPUTE_USER_DATA_4 0x0e44
+#define regCOMPUTE_USER_DATA_4_BASE_IDX 0
+#define regCOMPUTE_USER_DATA_5 0x0e45
+#define regCOMPUTE_USER_DATA_5_BASE_IDX 0
+#define regCOMPUTE_USER_DATA_6 0x0e46
+#define regCOMPUTE_USER_DATA_6_BASE_IDX 0
+#define regCOMPUTE_USER_DATA_7 0x0e47
+#define regCOMPUTE_USER_DATA_7_BASE_IDX 0
+#define regCOMPUTE_USER_DATA_8 0x0e48
+#define regCOMPUTE_USER_DATA_8_BASE_IDX 0
+#define regCOMPUTE_USER_DATA_9 0x0e49
+#define regCOMPUTE_USER_DATA_9_BASE_IDX 0
+#define regCOMPUTE_USER_DATA_10 0x0e4a
+#define regCOMPUTE_USER_DATA_10_BASE_IDX 0
+#define regCOMPUTE_USER_DATA_11 0x0e4b
+#define regCOMPUTE_USER_DATA_11_BASE_IDX 0
+#define regCOMPUTE_USER_DATA_12 0x0e4c
+#define regCOMPUTE_USER_DATA_12_BASE_IDX 0
+#define regCOMPUTE_USER_DATA_13 0x0e4d
+#define regCOMPUTE_USER_DATA_13_BASE_IDX 0
+#define regCOMPUTE_USER_DATA_14 0x0e4e
+#define regCOMPUTE_USER_DATA_14_BASE_IDX 0
+#define regCOMPUTE_USER_DATA_15 0x0e4f
+#define regCOMPUTE_USER_DATA_15_BASE_IDX 0
+#define regCOMPUTE_DISPATCH_END 0x0e7e
+#define regCOMPUTE_DISPATCH_END_BASE_IDX 0
+#define regCOMPUTE_NOWHERE 0x0e7f
+#define regCOMPUTE_NOWHERE_BASE_IDX 0
+
+
+// addressBlock: gc_shsdec
+// base address: 0x9000
+#define regSX_DEBUG_1 0x0419
+#define regSX_DEBUG_1_BASE_IDX 0
+#define regSPI_PS_MAX_WAVE_ID 0x043a
+#define regSPI_PS_MAX_WAVE_ID_BASE_IDX 0
+#define regSPI_START_PHASE 0x043b
+#define regSPI_START_PHASE_BASE_IDX 0
+#define regSPI_GFX_CNTL 0x043c
+#define regSPI_GFX_CNTL_BASE_IDX 0
+#define regSPI_DSM_CNTL 0x0443
+#define regSPI_DSM_CNTL_BASE_IDX 0
+#define regSPI_DSM_CNTL2 0x0444
+#define regSPI_DSM_CNTL2_BASE_IDX 0
+#define regSPI_EDC_CNT 0x0445
+#define regSPI_EDC_CNT_BASE_IDX 0
+#define regSPI_CONFIG_PS_CU_EN 0x0452
+#define regSPI_CONFIG_PS_CU_EN_BASE_IDX 0
+#define regSPI_WF_LIFETIME_CNTL 0x04aa
+#define regSPI_WF_LIFETIME_CNTL_BASE_IDX 0
+#define regSPI_WF_LIFETIME_LIMIT_0 0x04ab
+#define regSPI_WF_LIFETIME_LIMIT_0_BASE_IDX 0
+#define regSPI_WF_LIFETIME_LIMIT_1 0x04ac
+#define regSPI_WF_LIFETIME_LIMIT_1_BASE_IDX 0
+#define regSPI_WF_LIFETIME_LIMIT_2 0x04ad
+#define regSPI_WF_LIFETIME_LIMIT_2_BASE_IDX 0
+#define regSPI_WF_LIFETIME_LIMIT_3 0x04ae
+#define regSPI_WF_LIFETIME_LIMIT_3_BASE_IDX 0
+#define regSPI_WF_LIFETIME_LIMIT_4 0x04af
+#define regSPI_WF_LIFETIME_LIMIT_4_BASE_IDX 0
+#define regSPI_WF_LIFETIME_LIMIT_5 0x04b0
+#define regSPI_WF_LIFETIME_LIMIT_5_BASE_IDX 0
+#define regSPI_WF_LIFETIME_LIMIT_6 0x04b1
+#define regSPI_WF_LIFETIME_LIMIT_6_BASE_IDX 0
+#define regSPI_WF_LIFETIME_LIMIT_7 0x04b2
+#define regSPI_WF_LIFETIME_LIMIT_7_BASE_IDX 0
+#define regSPI_WF_LIFETIME_LIMIT_8 0x04b3
+#define regSPI_WF_LIFETIME_LIMIT_8_BASE_IDX 0
+#define regSPI_WF_LIFETIME_LIMIT_9 0x04b4
+#define regSPI_WF_LIFETIME_LIMIT_9_BASE_IDX 0
+#define regSPI_WF_LIFETIME_STATUS_0 0x04b5
+#define regSPI_WF_LIFETIME_STATUS_0_BASE_IDX 0
+#define regSPI_WF_LIFETIME_STATUS_1 0x04b6
+#define regSPI_WF_LIFETIME_STATUS_1_BASE_IDX 0
+#define regSPI_WF_LIFETIME_STATUS_2 0x04b7
+#define regSPI_WF_LIFETIME_STATUS_2_BASE_IDX 0
+#define regSPI_WF_LIFETIME_STATUS_3 0x04b8
+#define regSPI_WF_LIFETIME_STATUS_3_BASE_IDX 0
+#define regSPI_WF_LIFETIME_STATUS_4 0x04b9
+#define regSPI_WF_LIFETIME_STATUS_4_BASE_IDX 0
+#define regSPI_WF_LIFETIME_STATUS_5 0x04ba
+#define regSPI_WF_LIFETIME_STATUS_5_BASE_IDX 0
+#define regSPI_WF_LIFETIME_STATUS_6 0x04bb
+#define regSPI_WF_LIFETIME_STATUS_6_BASE_IDX 0
+#define regSPI_WF_LIFETIME_STATUS_7 0x04bc
+#define regSPI_WF_LIFETIME_STATUS_7_BASE_IDX 0
+#define regSPI_WF_LIFETIME_STATUS_8 0x04bd
+#define regSPI_WF_LIFETIME_STATUS_8_BASE_IDX 0
+#define regSPI_WF_LIFETIME_STATUS_9 0x04be
+#define regSPI_WF_LIFETIME_STATUS_9_BASE_IDX 0
+#define regSPI_WF_LIFETIME_STATUS_10 0x04bf
+#define regSPI_WF_LIFETIME_STATUS_10_BASE_IDX 0
+#define regSPI_WF_LIFETIME_STATUS_11 0x04c0
+#define regSPI_WF_LIFETIME_STATUS_11_BASE_IDX 0
+#define regSPI_WF_LIFETIME_STATUS_12 0x04c1
+#define regSPI_WF_LIFETIME_STATUS_12_BASE_IDX 0
+#define regSPI_WF_LIFETIME_STATUS_13 0x04c2
+#define regSPI_WF_LIFETIME_STATUS_13_BASE_IDX 0
+#define regSPI_WF_LIFETIME_STATUS_14 0x04c3
+#define regSPI_WF_LIFETIME_STATUS_14_BASE_IDX 0
+#define regSPI_WF_LIFETIME_STATUS_15 0x04c4
+#define regSPI_WF_LIFETIME_STATUS_15_BASE_IDX 0
+#define regSPI_WF_LIFETIME_STATUS_16 0x04c5
+#define regSPI_WF_LIFETIME_STATUS_16_BASE_IDX 0
+#define regSPI_WF_LIFETIME_STATUS_17 0x04c6
+#define regSPI_WF_LIFETIME_STATUS_17_BASE_IDX 0
+#define regSPI_WF_LIFETIME_STATUS_18 0x04c7
+#define regSPI_WF_LIFETIME_STATUS_18_BASE_IDX 0
+#define regSPI_WF_LIFETIME_STATUS_19 0x04c8
+#define regSPI_WF_LIFETIME_STATUS_19_BASE_IDX 0
+#define regSPI_WF_LIFETIME_STATUS_20 0x04c9
+#define regSPI_WF_LIFETIME_STATUS_20_BASE_IDX 0
+#define regSPI_LB_CTR_CTRL 0x04d4
+#define regSPI_LB_CTR_CTRL_BASE_IDX 0
+#define regSPI_LB_CU_MASK 0x04d5
+#define regSPI_LB_CU_MASK_BASE_IDX 0
+#define regSPI_LB_DATA_REG 0x04d6
+#define regSPI_LB_DATA_REG_BASE_IDX 0
+#define regSPI_PG_ENABLE_STATIC_CU_MASK 0x04d7
+#define regSPI_PG_ENABLE_STATIC_CU_MASK_BASE_IDX 0
+#define regSPI_GDS_CREDITS 0x04d8
+#define regSPI_GDS_CREDITS_BASE_IDX 0
+#define regSPI_SX_EXPORT_BUFFER_SIZES 0x04d9
+#define regSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX 0
+#define regSPI_SX_SCOREBOARD_BUFFER_SIZES 0x04da
+#define regSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX 0
+#define regSPI_CSQ_WF_ACTIVE_STATUS 0x04db
+#define regSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX 0
+#define regSPI_CSQ_WF_ACTIVE_COUNT_0 0x04dc
+#define regSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX 0
+#define regSPI_CSQ_WF_ACTIVE_COUNT_1 0x04dd
+#define regSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX 0
+#define regSPI_CSQ_WF_ACTIVE_COUNT_2 0x04de
+#define regSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX 0
+#define regSPI_CSQ_WF_ACTIVE_COUNT_3 0x04df
+#define regSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX 0
+#define regSPI_CSQ_WF_ACTIVE_COUNT_4 0x04e0
+#define regSPI_CSQ_WF_ACTIVE_COUNT_4_BASE_IDX 0
+#define regSPI_CSQ_WF_ACTIVE_COUNT_5 0x04e1
+#define regSPI_CSQ_WF_ACTIVE_COUNT_5_BASE_IDX 0
+#define regSPI_CSQ_WF_ACTIVE_COUNT_6 0x04e2
+#define regSPI_CSQ_WF_ACTIVE_COUNT_6_BASE_IDX 0
+#define regSPI_CSQ_WF_ACTIVE_COUNT_7 0x04e3
+#define regSPI_CSQ_WF_ACTIVE_COUNT_7_BASE_IDX 0
+#define regSPI_LB_DATA_WAVES 0x04e4
+#define regSPI_LB_DATA_WAVES_BASE_IDX 0
+#define regSPI_LB_DATA_PERCU_WAVE_HSGS 0x04e5
+#define regSPI_LB_DATA_PERCU_WAVE_HSGS_BASE_IDX 0
+#define regSPI_LB_DATA_PERCU_WAVE_VSPS 0x04e6
+#define regSPI_LB_DATA_PERCU_WAVE_VSPS_BASE_IDX 0
+#define regSPI_LB_DATA_PERCU_WAVE_CS 0x04e7
+#define regSPI_LB_DATA_PERCU_WAVE_CS_BASE_IDX 0
+#define regSPI_P0_TRAP_SCREEN_PSBA_LO 0x04ec
+#define regSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX 0
+#define regSPI_P0_TRAP_SCREEN_PSBA_HI 0x04ed
+#define regSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX 0
+#define regSPI_P0_TRAP_SCREEN_PSMA_LO 0x04ee
+#define regSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX 0
+#define regSPI_P0_TRAP_SCREEN_PSMA_HI 0x04ef
+#define regSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX 0
+#define regSPI_P0_TRAP_SCREEN_GPR_MIN 0x04f0
+#define regSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX 0
+#define regSPI_P1_TRAP_SCREEN_PSBA_LO 0x04f1
+#define regSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX 0
+#define regSPI_P1_TRAP_SCREEN_PSBA_HI 0x04f2
+#define regSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX 0
+#define regSPI_P1_TRAP_SCREEN_PSMA_LO 0x04f3
+#define regSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX 0
+#define regSPI_P1_TRAP_SCREEN_PSMA_HI 0x04f4
+#define regSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX 0
+#define regSPI_P1_TRAP_SCREEN_GPR_MIN 0x04f5
+#define regSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX 0
+
+
+// addressBlock: gc_spipdec
+// base address: 0xc700
+#define regSPI_ARB_PRIORITY 0x11c0
+#define regSPI_ARB_PRIORITY_BASE_IDX 0
+#define regSPI_ARB_CYCLES_0 0x11c1
+#define regSPI_ARB_CYCLES_0_BASE_IDX 0
+#define regSPI_ARB_CYCLES_1 0x11c2
+#define regSPI_ARB_CYCLES_1_BASE_IDX 0
+#define regSPI_WCL_PIPE_PERCENT_GFX 0x11c7
+#define regSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX 0
+#define regSPI_WCL_PIPE_PERCENT_HP3D 0x11c8
+#define regSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX 0
+#define regSPI_WCL_PIPE_PERCENT_CS0 0x11c9
+#define regSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX 0
+#define regSPI_WCL_PIPE_PERCENT_CS1 0x11ca
+#define regSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX 0
+#define regSPI_WCL_PIPE_PERCENT_CS2 0x11cb
+#define regSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX 0
+#define regSPI_WCL_PIPE_PERCENT_CS3 0x11cc
+#define regSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX 0
+#define regSPI_WCL_PIPE_PERCENT_CS4 0x11cd
+#define regSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX 0
+#define regSPI_WCL_PIPE_PERCENT_CS5 0x11ce
+#define regSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX 0
+#define regSPI_WCL_PIPE_PERCENT_CS6 0x11cf
+#define regSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX 0
+#define regSPI_WCL_PIPE_PERCENT_CS7 0x11d0
+#define regSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX 0
+#define regSPI_GDBG_WAVE_CNTL 0x11d1
+#define regSPI_GDBG_WAVE_CNTL_BASE_IDX 0
+#define regSPI_GDBG_TRAP_CONFIG 0x11d2
+#define regSPI_GDBG_TRAP_CONFIG_BASE_IDX 0
+#define regSPI_GDBG_PER_VMID_CNTL 0x11d3
+#define regSPI_GDBG_PER_VMID_CNTL_BASE_IDX 0
+#define regSPI_GDBG_WAVE_CNTL3 0x11d5
+#define regSPI_GDBG_WAVE_CNTL3_BASE_IDX 0
+#define regSPI_GDBG_TRAP_DATA0 0x11d8
+#define regSPI_GDBG_TRAP_DATA0_BASE_IDX 0
+#define regSPI_GDBG_TRAP_DATA1 0x11d9
+#define regSPI_GDBG_TRAP_DATA1_BASE_IDX 0
+#define regSPI_COMPUTE_QUEUE_RESET 0x11db
+#define regSPI_COMPUTE_QUEUE_RESET_BASE_IDX 0
+#define regSPI_RESOURCE_RESERVE_CU_0 0x11dc
+#define regSPI_RESOURCE_RESERVE_CU_0_BASE_IDX 0
+#define regSPI_RESOURCE_RESERVE_CU_1 0x11dd
+#define regSPI_RESOURCE_RESERVE_CU_1_BASE_IDX 0
+#define regSPI_RESOURCE_RESERVE_CU_2 0x11de
+#define regSPI_RESOURCE_RESERVE_CU_2_BASE_IDX 0
+#define regSPI_RESOURCE_RESERVE_CU_3 0x11df
+#define regSPI_RESOURCE_RESERVE_CU_3_BASE_IDX 0
+#define regSPI_RESOURCE_RESERVE_CU_4 0x11e0
+#define regSPI_RESOURCE_RESERVE_CU_4_BASE_IDX 0
+#define regSPI_RESOURCE_RESERVE_CU_5 0x11e1
+#define regSPI_RESOURCE_RESERVE_CU_5_BASE_IDX 0
+#define regSPI_RESOURCE_RESERVE_CU_6 0x11e2
+#define regSPI_RESOURCE_RESERVE_CU_6_BASE_IDX 0
+#define regSPI_RESOURCE_RESERVE_CU_7 0x11e3
+#define regSPI_RESOURCE_RESERVE_CU_7_BASE_IDX 0
+#define regSPI_RESOURCE_RESERVE_CU_8 0x11e4
+#define regSPI_RESOURCE_RESERVE_CU_8_BASE_IDX 0
+#define regSPI_RESOURCE_RESERVE_CU_9 0x11e5
+#define regSPI_RESOURCE_RESERVE_CU_9_BASE_IDX 0
+#define regSPI_RESOURCE_RESERVE_EN_CU_0 0x11e6
+#define regSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX 0
+#define regSPI_RESOURCE_RESERVE_EN_CU_1 0x11e7
+#define regSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX 0
+#define regSPI_RESOURCE_RESERVE_EN_CU_2 0x11e8
+#define regSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX 0
+#define regSPI_RESOURCE_RESERVE_EN_CU_3 0x11e9
+#define regSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX 0
+#define regSPI_RESOURCE_RESERVE_EN_CU_4 0x11ea
+#define regSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX 0
+#define regSPI_RESOURCE_RESERVE_EN_CU_5 0x11eb
+#define regSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX 0
+#define regSPI_RESOURCE_RESERVE_EN_CU_6 0x11ec
+#define regSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX 0
+#define regSPI_RESOURCE_RESERVE_EN_CU_7 0x11ed
+#define regSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX 0
+#define regSPI_RESOURCE_RESERVE_EN_CU_8 0x11ee
+#define regSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX 0
+#define regSPI_RESOURCE_RESERVE_EN_CU_9 0x11ef
+#define regSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX 0
+#define regSPI_RESOURCE_RESERVE_CU_10 0x11f0
+#define regSPI_RESOURCE_RESERVE_CU_10_BASE_IDX 0
+#define regSPI_RESOURCE_RESERVE_CU_11 0x11f1
+#define regSPI_RESOURCE_RESERVE_CU_11_BASE_IDX 0
+#define regSPI_RESOURCE_RESERVE_EN_CU_10 0x11f2
+#define regSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX 0
+#define regSPI_RESOURCE_RESERVE_EN_CU_11 0x11f3
+#define regSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX 0
+#define regSPI_RESOURCE_RESERVE_CU_12 0x11f4
+#define regSPI_RESOURCE_RESERVE_CU_12_BASE_IDX 0
+#define regSPI_RESOURCE_RESERVE_CU_13 0x11f5
+#define regSPI_RESOURCE_RESERVE_CU_13_BASE_IDX 0
+#define regSPI_RESOURCE_RESERVE_CU_14 0x11f6
+#define regSPI_RESOURCE_RESERVE_CU_14_BASE_IDX 0
+#define regSPI_RESOURCE_RESERVE_CU_15 0x11f7
+#define regSPI_RESOURCE_RESERVE_CU_15_BASE_IDX 0
+#define regSPI_RESOURCE_RESERVE_EN_CU_12 0x11f8
+#define regSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX 0
+#define regSPI_RESOURCE_RESERVE_EN_CU_13 0x11f9
+#define regSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX 0
+#define regSPI_RESOURCE_RESERVE_EN_CU_14 0x11fa
+#define regSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX 0
+#define regSPI_RESOURCE_RESERVE_EN_CU_15 0x11fb
+#define regSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX 0
+#define regSPI_COMPUTE_WF_CTX_SAVE 0x11fc
+#define regSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX 0
+#define regSPI_ARB_CNTL_0 0x11fd
+#define regSPI_ARB_CNTL_0_BASE_IDX 0
+
+
+// addressBlock: gc_sqdec
+// base address: 0x8c00
+#define regSQ_CONFIG 0x0300
+#define regSQ_CONFIG_BASE_IDX 0
+#define regSQC_CONFIG 0x0301
+#define regSQC_CONFIG_BASE_IDX 0
+#define regLDS_CONFIG 0x0302
+#define regLDS_CONFIG_BASE_IDX 0
+#define regSQ_RANDOM_WAVE_PRI 0x0303
+#define regSQ_RANDOM_WAVE_PRI_BASE_IDX 0
+#define regSQ_REG_CREDITS 0x0304
+#define regSQ_REG_CREDITS_BASE_IDX 0
+#define regSQ_FIFO_SIZES 0x0305
+#define regSQ_FIFO_SIZES_BASE_IDX 0
+#define regSQ_DSM_CNTL 0x0306
+#define regSQ_DSM_CNTL_BASE_IDX 0
+#define regSQ_DSM_CNTL2 0x0307
+#define regSQ_DSM_CNTL2_BASE_IDX 0
+#define regSQ_RUNTIME_CONFIG 0x0308
+#define regSQ_RUNTIME_CONFIG_BASE_IDX 0
+#define regSQ_DEBUG_STS_GLOBAL 0x0309
+#define regSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
+#define regSH_MEM_BASES 0x030a
+#define regSH_MEM_BASES_BASE_IDX 0
+#define regSQ_TIMEOUT_CONFIG 0x030b
+#define regSQ_TIMEOUT_CONFIG_BASE_IDX 0
+#define regSQ_TIMEOUT_STATUS 0x030c
+#define regSQ_TIMEOUT_STATUS_BASE_IDX 0
+#define regSH_MEM_CONFIG 0x030d
+#define regSH_MEM_CONFIG_BASE_IDX 0
+#define regSP_MFMA_PORTD_RD_CONFIG 0x030e
+#define regSP_MFMA_PORTD_RD_CONFIG_BASE_IDX 0
+#define regSH_CAC_CONFIG 0x030f
+#define regSH_CAC_CONFIG_BASE_IDX 0
+#define regSQ_DEBUG_STS_GLOBAL2 0x0310
+#define regSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
+#define regSQ_DEBUG_STS_GLOBAL3 0x0311
+#define regSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0
+#define regCC_GC_SHADER_RATE_CONFIG 0x0312
+#define regCC_GC_SHADER_RATE_CONFIG_BASE_IDX 0
+#define regGC_USER_SHADER_RATE_CONFIG 0x0313
+#define regGC_USER_SHADER_RATE_CONFIG_BASE_IDX 0
+#define regSQ_INTERRUPT_AUTO_MASK 0x0314
+#define regSQ_INTERRUPT_AUTO_MASK_BASE_IDX 0
+#define regSQ_INTERRUPT_MSG_CTRL 0x0315
+#define regSQ_INTERRUPT_MSG_CTRL_BASE_IDX 0
+#define regSQ_DEBUG_PERFCOUNT_TRAP 0x0316
+#define regSQ_DEBUG_PERFCOUNT_TRAP_BASE_IDX 0
+#define regSQ_UTCL1_CNTL1 0x0317
+#define regSQ_UTCL1_CNTL1_BASE_IDX 0
+#define regSQ_UTCL1_CNTL2 0x0318
+#define regSQ_UTCL1_CNTL2_BASE_IDX 0
+#define regSQ_UTCL1_STATUS 0x0319
+#define regSQ_UTCL1_STATUS_BASE_IDX 0
+#define regSQ_FED_INTERRUPT_STATUS 0x031a
+#define regSQ_FED_INTERRUPT_STATUS_BASE_IDX 0
+#define regSQ_CGTS_CONFIG 0x031b
+#define regSQ_CGTS_CONFIG_BASE_IDX 0
+#define regSQ_SHADER_TBA_LO 0x031c
+#define regSQ_SHADER_TBA_LO_BASE_IDX 0
+#define regSQ_SHADER_TBA_HI 0x031d
+#define regSQ_SHADER_TBA_HI_BASE_IDX 0
+#define regSQ_SHADER_TMA_LO 0x031e
+#define regSQ_SHADER_TMA_LO_BASE_IDX 0
+#define regSQ_SHADER_TMA_HI 0x031f
+#define regSQ_SHADER_TMA_HI_BASE_IDX 0
+#define regSQC_DSM_CNTL 0x0320
+#define regSQC_DSM_CNTL_BASE_IDX 0
+#define regSQC_DSM_CNTLA 0x0321
+#define regSQC_DSM_CNTLA_BASE_IDX 0
+#define regSQC_DSM_CNTLB 0x0322
+#define regSQC_DSM_CNTLB_BASE_IDX 0
+#define regSQC_DSM_CNTL2 0x0325
+#define regSQC_DSM_CNTL2_BASE_IDX 0
+#define regSQC_DSM_CNTL2A 0x0326
+#define regSQC_DSM_CNTL2A_BASE_IDX 0
+#define regSQC_DSM_CNTL2B 0x0327
+#define regSQC_DSM_CNTL2B_BASE_IDX 0
+#define regSQC_DSM_CNTL2E 0x032a
+#define regSQC_DSM_CNTL2E_BASE_IDX 0
+#define regSQC_EDC_FUE_CNTL 0x032b
+#define regSQC_EDC_FUE_CNTL_BASE_IDX 0
+#define regSQC_EDC_CNT2 0x032c
+#define regSQC_EDC_CNT2_BASE_IDX 0
+#define regSQC_EDC_CNT3 0x032d
+#define regSQC_EDC_CNT3_BASE_IDX 0
+#define regSQC_EDC_PARITY_CNT3 0x032e
+#define regSQC_EDC_PARITY_CNT3_BASE_IDX 0
+#define regSQ_DEBUG 0x0332
+#define regSQ_DEBUG_BASE_IDX 0
+#define regSQ_REG_TIMESTAMP 0x0374
+#define regSQ_REG_TIMESTAMP_BASE_IDX 0
+#define regSQ_CMD_TIMESTAMP 0x0375
+#define regSQ_CMD_TIMESTAMP_BASE_IDX 0
+#define regSQ_HOSTTRAP_STATUS 0x0376
+#define regSQ_HOSTTRAP_STATUS_BASE_IDX 0
+#define regSQ_IND_INDEX 0x0378
+#define regSQ_IND_INDEX_BASE_IDX 0
+#define regSQ_IND_DATA 0x0379
+#define regSQ_IND_DATA_BASE_IDX 0
+#define regSQ_CONFIG1 0x037a
+#define regSQ_CONFIG1_BASE_IDX 0
+#define regSQ_CMD 0x037b
+#define regSQ_CMD_BASE_IDX 0
+#define regSQ_TIME_HI 0x037c
+#define regSQ_TIME_HI_BASE_IDX 0
+#define regSQ_TIME_LO 0x037d
+#define regSQ_TIME_LO_BASE_IDX 0
+#define regSQ_DS_0 0x037f
+#define regSQ_DS_0_BASE_IDX 0
+#define regSQ_DS_1 0x037f
+#define regSQ_DS_1_BASE_IDX 0
+#define regSQ_EXP_0 0x037f
+#define regSQ_EXP_0_BASE_IDX 0
+#define regSQ_EXP_1 0x037f
+#define regSQ_EXP_1_BASE_IDX 0
+#define regSQ_FLAT_0 0x037f
+#define regSQ_FLAT_0_BASE_IDX 0
+#define regSQ_FLAT_1 0x037f
+#define regSQ_FLAT_1_BASE_IDX 0
+#define regSQ_GLBL_0 0x037f
+#define regSQ_GLBL_0_BASE_IDX 0
+#define regSQ_GLBL_1 0x037f
+#define regSQ_GLBL_1_BASE_IDX 0
+#define regSQ_INST 0x037f
+#define regSQ_INST_BASE_IDX 0
+#define regSQ_MIMG_0 0x037f
+#define regSQ_MIMG_0_BASE_IDX 0
+#define regSQ_MIMG_1 0x037f
+#define regSQ_MIMG_1_BASE_IDX 0
+#define regSQ_MTBUF_0 0x037f
+#define regSQ_MTBUF_0_BASE_IDX 0
+#define regSQ_MTBUF_1 0x037f
+#define regSQ_MTBUF_1_BASE_IDX 0
+#define regSQ_MUBUF_0 0x037f
+#define regSQ_MUBUF_0_BASE_IDX 0
+#define regSQ_MUBUF_1 0x037f
+#define regSQ_MUBUF_1_BASE_IDX 0
+#define regSQ_SCRATCH_0 0x037f
+#define regSQ_SCRATCH_0_BASE_IDX 0
+#define regSQ_SCRATCH_1 0x037f
+#define regSQ_SCRATCH_1_BASE_IDX 0
+#define regSQ_SMEM_0 0x037f
+#define regSQ_SMEM_0_BASE_IDX 0
+#define regSQ_SMEM_1 0x037f
+#define regSQ_SMEM_1_BASE_IDX 0
+#define regSQ_SOP1 0x037f
+#define regSQ_SOP1_BASE_IDX 0
+#define regSQ_SOP2 0x037f
+#define regSQ_SOP2_BASE_IDX 0
+#define regSQ_SOPC 0x037f
+#define regSQ_SOPC_BASE_IDX 0
+#define regSQ_SOPK 0x037f
+#define regSQ_SOPK_BASE_IDX 0
+#define regSQ_SOPP 0x037f
+#define regSQ_SOPP_BASE_IDX 0
+#define regSQ_VINTRP 0x037f
+#define regSQ_VINTRP_BASE_IDX 0
+#define regSQ_VOP1 0x037f
+#define regSQ_VOP1_BASE_IDX 0
+#define regSQ_VOP2 0x037f
+#define regSQ_VOP2_BASE_IDX 0
+#define regSQ_VOP3P_0 0x037f
+#define regSQ_VOP3P_0_BASE_IDX 0
+#define regSQ_VOP3P_1 0x037f
+#define regSQ_VOP3P_1_BASE_IDX 0
+#define regSQ_VOP3P_MFMA_0 0x037f
+#define regSQ_VOP3P_MFMA_0_BASE_IDX 0
+#define regSQ_VOP3P_MFMA_1 0x037f
+#define regSQ_VOP3P_MFMA_1_BASE_IDX 0
+#define regSQ_VOP3_0 0x037f
+#define regSQ_VOP3_0_BASE_IDX 0
+#define regSQ_VOP3_0_SDST_ENC 0x037f
+#define regSQ_VOP3_0_SDST_ENC_BASE_IDX 0
+#define regSQ_VOP3_1 0x037f
+#define regSQ_VOP3_1_BASE_IDX 0
+#define regSQ_VOPC 0x037f
+#define regSQ_VOPC_BASE_IDX 0
+#define regSQ_VOP_DPP 0x037f
+#define regSQ_VOP_DPP_BASE_IDX 0
+#define regSQ_VOP_SDWA 0x037f
+#define regSQ_VOP_SDWA_BASE_IDX 0
+#define regSQ_VOP_SDWA_SDST_ENC 0x037f
+#define regSQ_VOP_SDWA_SDST_ENC_BASE_IDX 0
+#define regSQ_LB_CTR_CTRL 0x0398
+#define regSQ_LB_CTR_CTRL_BASE_IDX 0
+#define regSQ_LB_DATA0 0x0399
+#define regSQ_LB_DATA0_BASE_IDX 0
+#define regSQ_LB_DATA1 0x039a
+#define regSQ_LB_DATA1_BASE_IDX 0
+#define regSQ_LB_DATA2 0x039b
+#define regSQ_LB_DATA2_BASE_IDX 0
+#define regSQ_LB_DATA3 0x039c
+#define regSQ_LB_DATA3_BASE_IDX 0
+#define regSQ_LB_CTR_SEL 0x039d
+#define regSQ_LB_CTR_SEL_BASE_IDX 0
+#define regSQ_LB_CTR0_CU 0x039e
+#define regSQ_LB_CTR0_CU_BASE_IDX 0
+#define regSQ_LB_CTR1_CU 0x039f
+#define regSQ_LB_CTR1_CU_BASE_IDX 0
+#define regSQ_LB_CTR2_CU 0x03a0
+#define regSQ_LB_CTR2_CU_BASE_IDX 0
+#define regSQ_LB_CTR3_CU 0x03a1
+#define regSQ_LB_CTR3_CU_BASE_IDX 0
+#define regSQC_EDC_CNT 0x03a2
+#define regSQC_EDC_CNT_BASE_IDX 0
+#define regSQ_EDC_SEC_CNT 0x03a3
+#define regSQ_EDC_SEC_CNT_BASE_IDX 0
+#define regSQ_EDC_DED_CNT 0x03a4
+#define regSQ_EDC_DED_CNT_BASE_IDX 0
+#define regSQ_EDC_INFO 0x03a5
+#define regSQ_EDC_INFO_BASE_IDX 0
+#define regSQ_EDC_CNT 0x03a6
+#define regSQ_EDC_CNT_BASE_IDX 0
+#define regSQ_EDC_FUE_CNTL 0x03a7
+#define regSQ_EDC_FUE_CNTL_BASE_IDX 0
+#define regSQ_THREAD_TRACE_WORD_CMN 0x03b0
+#define regSQ_THREAD_TRACE_WORD_CMN_BASE_IDX 0
+#define regSQ_THREAD_TRACE_WORD_EVENT 0x03b0
+#define regSQ_THREAD_TRACE_WORD_EVENT_BASE_IDX 0
+#define regSQ_THREAD_TRACE_WORD_INST 0x03b0
+#define regSQ_THREAD_TRACE_WORD_INST_BASE_IDX 0
+#define regSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0x03b0
+#define regSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_BASE_IDX 0
+#define regSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0x03b0
+#define regSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_BASE_IDX 0
+#define regSQ_THREAD_TRACE_WORD_ISSUE 0x03b0
+#define regSQ_THREAD_TRACE_WORD_ISSUE_BASE_IDX 0
+#define regSQ_THREAD_TRACE_WORD_MISC 0x03b0
+#define regSQ_THREAD_TRACE_WORD_MISC_BASE_IDX 0
+#define regSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0x03b0
+#define regSQ_THREAD_TRACE_WORD_PERF_1_OF_2_BASE_IDX 0
+#define regSQ_THREAD_TRACE_WORD_REG_1_OF_2 0x03b0
+#define regSQ_THREAD_TRACE_WORD_REG_1_OF_2_BASE_IDX 0
+#define regSQ_THREAD_TRACE_WORD_REG_2_OF_2 0x03b0
+#define regSQ_THREAD_TRACE_WORD_REG_2_OF_2_BASE_IDX 0
+#define regSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 0x03b0
+#define regSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_BASE_IDX 0
+#define regSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 0x03b0
+#define regSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_BASE_IDX 0
+#define regSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0x03b0
+#define regSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_BASE_IDX 0
+#define regSQ_THREAD_TRACE_WORD_WAVE 0x03b0
+#define regSQ_THREAD_TRACE_WORD_WAVE_BASE_IDX 0
+#define regSQ_THREAD_TRACE_WORD_WAVE_START 0x03b0
+#define regSQ_THREAD_TRACE_WORD_WAVE_START_BASE_IDX 0
+#define regSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0x03b1
+#define regSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_BASE_IDX 0
+#define regSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0x03b1
+#define regSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_BASE_IDX 0
+#define regSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0x03b1
+#define regSQ_THREAD_TRACE_WORD_PERF_2_OF_2_BASE_IDX 0
+#define regSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0x03b1
+#define regSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_BASE_IDX 0
+#define regSQ_WREXEC_EXEC_HI 0x03b1
+#define regSQ_WREXEC_EXEC_HI_BASE_IDX 0
+#define regSQ_WREXEC_EXEC_LO 0x03b1
+#define regSQ_WREXEC_EXEC_LO_BASE_IDX 0
+#define regSQ_BUF_RSRC_WORD0 0x03c0
+#define regSQ_BUF_RSRC_WORD0_BASE_IDX 0
+#define regSQ_BUF_RSRC_WORD1 0x03c1
+#define regSQ_BUF_RSRC_WORD1_BASE_IDX 0
+#define regSQ_BUF_RSRC_WORD2 0x03c2
+#define regSQ_BUF_RSRC_WORD2_BASE_IDX 0
+#define regSQ_BUF_RSRC_WORD3 0x03c3
+#define regSQ_BUF_RSRC_WORD3_BASE_IDX 0
+#define regSQ_IMG_RSRC_WORD0 0x03c4
+#define regSQ_IMG_RSRC_WORD0_BASE_IDX 0
+#define regSQ_IMG_RSRC_WORD1 0x03c5
+#define regSQ_IMG_RSRC_WORD1_BASE_IDX 0
+#define regSQ_IMG_RSRC_WORD2 0x03c6
+#define regSQ_IMG_RSRC_WORD2_BASE_IDX 0
+#define regSQ_IMG_RSRC_WORD3 0x03c7
+#define regSQ_IMG_RSRC_WORD3_BASE_IDX 0
+#define regSQ_IMG_RSRC_WORD4 0x03c8
+#define regSQ_IMG_RSRC_WORD4_BASE_IDX 0
+#define regSQ_IMG_RSRC_WORD5 0x03c9
+#define regSQ_IMG_RSRC_WORD5_BASE_IDX 0
+#define regSQ_IMG_RSRC_WORD6 0x03ca
+#define regSQ_IMG_RSRC_WORD6_BASE_IDX 0
+#define regSQ_IMG_RSRC_WORD7 0x03cb
+#define regSQ_IMG_RSRC_WORD7_BASE_IDX 0
+#define regSQ_IMG_SAMP_WORD0 0x03cc
+#define regSQ_IMG_SAMP_WORD0_BASE_IDX 0
+#define regSQ_IMG_SAMP_WORD1 0x03cd
+#define regSQ_IMG_SAMP_WORD1_BASE_IDX 0
+#define regSQ_IMG_SAMP_WORD2 0x03ce
+#define regSQ_IMG_SAMP_WORD2_BASE_IDX 0
+#define regSQ_IMG_SAMP_WORD3 0x03cf
+#define regSQ_IMG_SAMP_WORD3_BASE_IDX 0
+#define regSQ_FLAT_SCRATCH_WORD0 0x03d0
+#define regSQ_FLAT_SCRATCH_WORD0_BASE_IDX 0
+#define regSQ_FLAT_SCRATCH_WORD1 0x03d1
+#define regSQ_FLAT_SCRATCH_WORD1_BASE_IDX 0
+#define regSQ_M0_GPR_IDX_WORD 0x03d2
+#define regSQ_M0_GPR_IDX_WORD_BASE_IDX 0
+#define regSQC_ICACHE_UTCL1_CNTL1 0x03d3
+#define regSQC_ICACHE_UTCL1_CNTL1_BASE_IDX 0
+#define regSQC_ICACHE_UTCL1_CNTL2 0x03d4
+#define regSQC_ICACHE_UTCL1_CNTL2_BASE_IDX 0
+#define regSQC_DCACHE_UTCL1_CNTL1 0x03d5
+#define regSQC_DCACHE_UTCL1_CNTL1_BASE_IDX 0
+#define regSQC_DCACHE_UTCL1_CNTL2 0x03d6
+#define regSQC_DCACHE_UTCL1_CNTL2_BASE_IDX 0
+#define regSQC_ICACHE_UTCL1_STATUS 0x03d7
+#define regSQC_ICACHE_UTCL1_STATUS_BASE_IDX 0
+#define regSQC_DCACHE_UTCL1_STATUS 0x03d8
+#define regSQC_DCACHE_UTCL1_STATUS_BASE_IDX 0
+
+
+// addressBlock: gc_tcdec
+// base address: 0xac00
+#define regTCP_INVALIDATE 0x0b00
+#define regTCP_INVALIDATE_BASE_IDX 0
+#define regTCP_STATUS 0x0b01
+#define regTCP_STATUS_BASE_IDX 0
+#define regTCP_CHAN_STEER_0 0x0b03
+#define regTCP_CHAN_STEER_0_BASE_IDX 0
+#define regTCP_CHAN_STEER_1 0x0b04
+#define regTCP_CHAN_STEER_1_BASE_IDX 0
+#define regTCP_ADDR_CONFIG 0x0b05
+#define regTCP_ADDR_CONFIG_BASE_IDX 0
+#define regTCP_CHAN_STEER_2 0x0b09
+#define regTCP_CHAN_STEER_2_BASE_IDX 0
+#define regTCP_CHAN_STEER_3 0x0b0a
+#define regTCP_CHAN_STEER_3_BASE_IDX 0
+#define regTCP_CHAN_STEER_4 0x0b0b
+#define regTCP_CHAN_STEER_4_BASE_IDX 0
+#define regTCP_CHAN_STEER_5 0x0b0c
+#define regTCP_CHAN_STEER_5_BASE_IDX 0
+#define regTCP_EDC_CNT 0x0b17
+#define regTCP_EDC_CNT_BASE_IDX 0
+#define regTCP_EDC_CNT_NEW 0x0b18
+#define regTCP_EDC_CNT_NEW_BASE_IDX 0
+#define regTC_CFG_L1_LOAD_POLICY0 0x0b1a
+#define regTC_CFG_L1_LOAD_POLICY0_BASE_IDX 0
+#define regTC_CFG_L1_LOAD_POLICY1 0x0b1b
+#define regTC_CFG_L1_LOAD_POLICY1_BASE_IDX 0
+#define regTC_CFG_L1_STORE_POLICY 0x0b1c
+#define regTC_CFG_L1_STORE_POLICY_BASE_IDX 0
+#define regTC_CFG_L2_LOAD_POLICY0 0x0b1d
+#define regTC_CFG_L2_LOAD_POLICY0_BASE_IDX 0
+#define regTC_CFG_L2_LOAD_POLICY1 0x0b1e
+#define regTC_CFG_L2_LOAD_POLICY1_BASE_IDX 0
+#define regTC_CFG_L2_STORE_POLICY0 0x0b1f
+#define regTC_CFG_L2_STORE_POLICY0_BASE_IDX 0
+#define regTC_CFG_L2_STORE_POLICY1 0x0b20
+#define regTC_CFG_L2_STORE_POLICY1_BASE_IDX 0
+#define regTC_CFG_L2_ATOMIC_POLICY 0x0b21
+#define regTC_CFG_L2_ATOMIC_POLICY_BASE_IDX 0
+#define regTC_CFG_L1_VOLATILE 0x0b22
+#define regTC_CFG_L1_VOLATILE_BASE_IDX 0
+#define regTC_CFG_L2_VOLATILE 0x0b23
+#define regTC_CFG_L2_VOLATILE_BASE_IDX 0
+#define regTCI_MISC 0x0b5c
+#define regTCI_MISC_BASE_IDX 0
+#define regTCI_CNTL_3 0x0b5d
+#define regTCI_CNTL_3_BASE_IDX 0
+#define regTCI_DSM_CNTL 0x0b5e
+#define regTCI_DSM_CNTL_BASE_IDX 0
+#define regTCI_DSM_CNTL2 0x0b5f
+#define regTCI_DSM_CNTL2_BASE_IDX 0
+#define regTCI_EDC_CNT 0x0b60
+#define regTCI_EDC_CNT_BASE_IDX 0
+#define regTCI_STATUS 0x0b61
+#define regTCI_STATUS_BASE_IDX 0
+#define regTCI_CNTL_1 0x0b62
+#define regTCI_CNTL_1_BASE_IDX 0
+#define regTCI_CNTL_2 0x0b63
+#define regTCI_CNTL_2_BASE_IDX 0
+#define regTCC_CTRL 0x0b80
+#define regTCC_CTRL_BASE_IDX 0
+#define regTCC_CTRL2 0x0b81
+#define regTCC_CTRL2_BASE_IDX 0
+#define regTCC_EDC_CNT 0x0b82
+#define regTCC_EDC_CNT_BASE_IDX 0
+#define regTCC_EDC_CNT2 0x0b83
+#define regTCC_EDC_CNT2_BASE_IDX 0
+#define regTCC_REDUNDANCY 0x0b84
+#define regTCC_REDUNDANCY_BASE_IDX 0
+#define regTCC_EXE_DISABLE 0x0b85
+#define regTCC_EXE_DISABLE_BASE_IDX 0
+#define regTCC_DSM_CNTL 0x0b86
+#define regTCC_DSM_CNTL_BASE_IDX 0
+#define regTCC_DSM_CNTLA 0x0b87
+#define regTCC_DSM_CNTLA_BASE_IDX 0
+#define regTCC_DSM_CNTL2 0x0b88
+#define regTCC_DSM_CNTL2_BASE_IDX 0
+#define regTCC_DSM_CNTL2A 0x0b89
+#define regTCC_DSM_CNTL2A_BASE_IDX 0
+#define regTCC_DSM_CNTL2B 0x0b8a
+#define regTCC_DSM_CNTL2B_BASE_IDX 0
+#define regTCC_WBINVL2 0x0b8b
+#define regTCC_WBINVL2_BASE_IDX 0
+#define regTCC_SOFT_RESET 0x0b8c
+#define regTCC_SOFT_RESET_BASE_IDX 0
+#define regTCC_DSM_CNTL3 0x0b8e
+#define regTCC_DSM_CNTL3_BASE_IDX 0
+#define regTCA_CTRL 0x0bc0
+#define regTCA_CTRL_BASE_IDX 0
+#define regTCA_BURST_MASK 0x0bc1
+#define regTCA_BURST_MASK_BASE_IDX 0
+#define regTCA_BURST_CTRL 0x0bc2
+#define regTCA_BURST_CTRL_BASE_IDX 0
+#define regTCA_DSM_CNTL 0x0bc3
+#define regTCA_DSM_CNTL_BASE_IDX 0
+#define regTCA_DSM_CNTL2 0x0bc4
+#define regTCA_DSM_CNTL2_BASE_IDX 0
+#define regTCA_EDC_CNT 0x0bc5
+#define regTCA_EDC_CNT_BASE_IDX 0
+#define regTCX_CTRL 0x0bc6
+#define regTCX_CTRL_BASE_IDX 0
+#define regTCX_DSM_CNTL 0x0bc7
+#define regTCX_DSM_CNTL_BASE_IDX 0
+#define regTCX_DSM_CNTL2 0x0bc8
+#define regTCX_DSM_CNTL2_BASE_IDX 0
+#define regTCX_EDC_CNT 0x0bc9
+#define regTCX_EDC_CNT_BASE_IDX 0
+#define regTCX_EDC_CNT2 0x0bca
+#define regTCX_EDC_CNT2_BASE_IDX 0
+
+
+// addressBlock: gc_tcpdec
+// base address: 0xca80
+#define regTCP_WATCH0_ADDR_H 0x12a0
+#define regTCP_WATCH0_ADDR_H_BASE_IDX 0
+#define regTCP_WATCH0_ADDR_L 0x12a1
+#define regTCP_WATCH0_ADDR_L_BASE_IDX 0
+#define regTCP_WATCH0_CNTL 0x12a2
+#define regTCP_WATCH0_CNTL_BASE_IDX 0
+#define regTCP_WATCH1_ADDR_H 0x12a3
+#define regTCP_WATCH1_ADDR_H_BASE_IDX 0
+#define regTCP_WATCH1_ADDR_L 0x12a4
+#define regTCP_WATCH1_ADDR_L_BASE_IDX 0
+#define regTCP_WATCH1_CNTL 0x12a5
+#define regTCP_WATCH1_CNTL_BASE_IDX 0
+#define regTCP_WATCH2_ADDR_H 0x12a6
+#define regTCP_WATCH2_ADDR_H_BASE_IDX 0
+#define regTCP_WATCH2_ADDR_L 0x12a7
+#define regTCP_WATCH2_ADDR_L_BASE_IDX 0
+#define regTCP_WATCH2_CNTL 0x12a8
+#define regTCP_WATCH2_CNTL_BASE_IDX 0
+#define regTCP_WATCH3_ADDR_H 0x12a9
+#define regTCP_WATCH3_ADDR_H_BASE_IDX 0
+#define regTCP_WATCH3_ADDR_L 0x12aa
+#define regTCP_WATCH3_ADDR_L_BASE_IDX 0
+#define regTCP_WATCH3_CNTL 0x12ab
+#define regTCP_WATCH3_CNTL_BASE_IDX 0
+#define regTCP_GATCL1_CNTL 0x12b0
+#define regTCP_GATCL1_CNTL_BASE_IDX 0
+#define regTCP_ATC_EDC_GATCL1_CNT 0x12b1
+#define regTCP_ATC_EDC_GATCL1_CNT_BASE_IDX 0
+#define regTCP_GATCL1_DSM_CNTL 0x12b2
+#define regTCP_GATCL1_DSM_CNTL_BASE_IDX 0
+#define regTCP_DSM_CNTL 0x12b3
+#define regTCP_DSM_CNTL_BASE_IDX 0
+#define regTCP_UTCL1_CNTL1 0x12b5
+#define regTCP_UTCL1_CNTL1_BASE_IDX 0
+#define regTCP_UTCL1_CNTL2 0x12b6
+#define regTCP_UTCL1_CNTL2_BASE_IDX 0
+#define regTCP_UTCL1_STATUS 0x12b7
+#define regTCP_UTCL1_STATUS_BASE_IDX 0
+#define regTCP_DSM_CNTL2 0x12b8
+#define regTCP_DSM_CNTL2_BASE_IDX 0
+#define regTCP_PERFCOUNTER_FILTER 0x12b9
+#define regTCP_PERFCOUNTER_FILTER_BASE_IDX 0
+#define regTCP_PERFCOUNTER_FILTER_EN 0x12ba
+#define regTCP_PERFCOUNTER_FILTER_EN_BASE_IDX 0
+
+
+// addressBlock: gc_tpdec
+// base address: 0x9400
+#define regTD_STATUS 0x0526
+#define regTD_STATUS_BASE_IDX 0
+#define regTD_EDC_CNT 0x052e
+#define regTD_EDC_CNT_BASE_IDX 0
+#define regTD_DSM_CNTL 0x052f
+#define regTD_DSM_CNTL_BASE_IDX 0
+#define regTD_DSM_CNTL2 0x0530
+#define regTD_DSM_CNTL2_BASE_IDX 0
+#define regTD_SCRATCH 0x0533
+#define regTD_SCRATCH_BASE_IDX 0
+#define regTA_CNTL 0x0541
+#define regTA_CNTL_BASE_IDX 0
+#define regTA_CNTL_AUX 0x0542
+#define regTA_CNTL_AUX_BASE_IDX 0
+#define regTA_FEATURE_CNTL 0x0543
+#define regTA_FEATURE_CNTL_BASE_IDX 0
+#define regTA_STATUS 0x0548
+#define regTA_STATUS_BASE_IDX 0
+#define regTA_SCRATCH 0x0564
+#define regTA_SCRATCH_BASE_IDX 0
+#define regTA_DSM_CNTL 0x0584
+#define regTA_DSM_CNTL_BASE_IDX 0
+#define regTA_DSM_CNTL2 0x0585
+#define regTA_DSM_CNTL2_BASE_IDX 0
+#define regTA_EDC_CNT 0x0586
+#define regTA_EDC_CNT_BASE_IDX 0
+
+
+// addressBlock: gc_utcl2_atcl2dec
+// base address: 0xa000
+#define regATC_L2_CNTL 0x0800
+#define regATC_L2_CNTL_BASE_IDX 0
+#define regATC_L2_CNTL2 0x0801
+#define regATC_L2_CNTL2_BASE_IDX 0
+#define regATC_L2_CACHE_DATA0 0x0804
+#define regATC_L2_CACHE_DATA0_BASE_IDX 0
+#define regATC_L2_CACHE_DATA1 0x0805
+#define regATC_L2_CACHE_DATA1_BASE_IDX 0
+#define regATC_L2_CACHE_DATA2 0x0806
+#define regATC_L2_CACHE_DATA2_BASE_IDX 0
+#define regATC_L2_CACHE_DATA3 0x0807
+#define regATC_L2_CACHE_DATA3_BASE_IDX 0
+#define regATC_L2_CNTL3 0x0808
+#define regATC_L2_CNTL3_BASE_IDX 0
+#define regATC_L2_STATUS 0x0809
+#define regATC_L2_STATUS_BASE_IDX 0
+#define regATC_L2_STATUS2 0x080a
+#define regATC_L2_STATUS2_BASE_IDX 0
+#define regATC_L2_MISC_CG 0x080b
+#define regATC_L2_MISC_CG_BASE_IDX 0
+#define regATC_L2_MEM_POWER_LS 0x080c
+#define regATC_L2_MEM_POWER_LS_BASE_IDX 0
+#define regATC_L2_CGTT_CLK_CTRL 0x080d
+#define regATC_L2_CGTT_CLK_CTRL_BASE_IDX 0
+#define regATC_L2_CACHE_4K_DSM_INDEX 0x080e
+#define regATC_L2_CACHE_4K_DSM_INDEX_BASE_IDX 0
+#define regATC_L2_CACHE_32K_DSM_INDEX 0x080f
+#define regATC_L2_CACHE_32K_DSM_INDEX_BASE_IDX 0
+#define regATC_L2_CACHE_2M_DSM_INDEX 0x0810
+#define regATC_L2_CACHE_2M_DSM_INDEX_BASE_IDX 0
+#define regATC_L2_CACHE_4K_DSM_CNTL 0x0811
+#define regATC_L2_CACHE_4K_DSM_CNTL_BASE_IDX 0
+#define regATC_L2_CACHE_32K_DSM_CNTL 0x0812
+#define regATC_L2_CACHE_32K_DSM_CNTL_BASE_IDX 0
+#define regATC_L2_CACHE_2M_DSM_CNTL 0x0813
+#define regATC_L2_CACHE_2M_DSM_CNTL_BASE_IDX 0
+#define regATC_L2_CNTL4 0x0814
+#define regATC_L2_CNTL4_BASE_IDX 0
+#define regATC_L2_MM_GROUP_RT_CLASSES 0x0815
+#define regATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0
+
+
+// addressBlock: gc_utcl2_atcl2pfcntldec
+// base address: 0x37500
+#define regATC_L2_PERFCOUNTER0_CFG 0x3d40
+#define regATC_L2_PERFCOUNTER0_CFG_BASE_IDX 1
+#define regATC_L2_PERFCOUNTER1_CFG 0x3d41
+#define regATC_L2_PERFCOUNTER1_CFG_BASE_IDX 1
+#define regATC_L2_PERFCOUNTER_RSLT_CNTL 0x3d42
+#define regATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
+
+
+// addressBlock: gc_utcl2_atcl2pfcntrdec
+// base address: 0x35400
+#define regATC_L2_PERFCOUNTER_LO 0x3500
+#define regATC_L2_PERFCOUNTER_LO_BASE_IDX 1
+#define regATC_L2_PERFCOUNTER_HI 0x3501
+#define regATC_L2_PERFCOUNTER_HI_BASE_IDX 1
+
+
+// addressBlock: gc_utcl2_l2tlbdec
+// base address: 0xa640
+#define regL2TLB_TLB0_STATUS 0x0991
+#define regL2TLB_TLB0_STATUS_BASE_IDX 0
+#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO 0x0993
+#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX 0
+#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI 0x0994
+#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX 0
+#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO 0x0995
+#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX 0
+#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI 0x0996
+#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX 0
+
+
+// addressBlock: gc_utcl2_l2tlbpldec
+// base address: 0x37570
+#define regL2TLB_PERFCOUNTER0_CFG 0x3d5c
+#define regL2TLB_PERFCOUNTER0_CFG_BASE_IDX 1
+#define regL2TLB_PERFCOUNTER1_CFG 0x3d5d
+#define regL2TLB_PERFCOUNTER1_CFG_BASE_IDX 1
+#define regL2TLB_PERFCOUNTER2_CFG 0x3d5e
+#define regL2TLB_PERFCOUNTER2_CFG_BASE_IDX 1
+#define regL2TLB_PERFCOUNTER3_CFG 0x3d5f
+#define regL2TLB_PERFCOUNTER3_CFG_BASE_IDX 1
+#define regL2TLB_PERFCOUNTER_RSLT_CNTL 0x3d60
+#define regL2TLB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
+
+
+// addressBlock: gc_utcl2_l2tlbprdec
+// base address: 0x35460
+#define regL2TLB_PERFCOUNTER_LO 0x3518
+#define regL2TLB_PERFCOUNTER_LO_BASE_IDX 1
+#define regL2TLB_PERFCOUNTER_HI 0x3519
+#define regL2TLB_PERFCOUNTER_HI_BASE_IDX 1
+
+
+// addressBlock: gc_utcl2_vml2pfdec
+// base address: 0xa100
+#define regVM_L2_CNTL 0x0840
+#define regVM_L2_CNTL_BASE_IDX 0
+#define regVM_L2_CNTL2 0x0841
+#define regVM_L2_CNTL2_BASE_IDX 0
+#define regVM_L2_CNTL3 0x0842
+#define regVM_L2_CNTL3_BASE_IDX 0
+#define regVM_L2_STATUS 0x0843
+#define regVM_L2_STATUS_BASE_IDX 0
+#define regVM_DUMMY_PAGE_FAULT_CNTL 0x0844
+#define regVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0
+#define regVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0845
+#define regVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0
+#define regVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0846
+#define regVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0
+#define regVM_L2_PROTECTION_FAULT_CNTL 0x0847
+#define regVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0
+#define regVM_L2_PROTECTION_FAULT_CNTL2 0x0848
+#define regVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0
+#define regVM_L2_PROTECTION_FAULT_MM_CNTL3 0x0849
+#define regVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0
+#define regVM_L2_PROTECTION_FAULT_MM_CNTL4 0x084a
+#define regVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0
+#define regVM_L2_PROTECTION_FAULT_STATUS 0x084b
+#define regVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0
+#define regVM_L2_PROTECTION_FAULT_ADDR_LO32 0x084c
+#define regVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0
+#define regVM_L2_PROTECTION_FAULT_ADDR_HI32 0x084d
+#define regVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0
+#define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x084e
+#define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0
+#define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x084f
+#define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0
+#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0851
+#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0
+#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0852
+#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0
+#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0853
+#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0
+#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0854
+#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0
+#define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0855
+#define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0
+#define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0856
+#define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0
+#define regVM_L2_CNTL4 0x0857
+#define regVM_L2_CNTL4_BASE_IDX 0
+#define regVM_L2_MM_GROUP_RT_CLASSES 0x0858
+#define regVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0
+#define regVM_L2_BANK_SELECT_RESERVED_CID 0x0859
+#define regVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0
+#define regVM_L2_BANK_SELECT_RESERVED_CID2 0x085a
+#define regVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0
+#define regVM_L2_CACHE_PARITY_CNTL 0x085b
+#define regVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0
+#define regVM_L2_CGTT_CLK_CTRL 0x085e
+#define regVM_L2_CGTT_CLK_CTRL_BASE_IDX 0
+#define regVM_L2_CGTT_BUSY_CTRL 0x085f
+#define regVM_L2_CGTT_BUSY_CTRL_BASE_IDX 0
+#define regVML2_MEM_ECC_INDEX 0x0861
+#define regVML2_MEM_ECC_INDEX_BASE_IDX 0
+#define regVML2_WALKER_MEM_ECC_INDEX 0x0862
+#define regVML2_WALKER_MEM_ECC_INDEX_BASE_IDX 0
+#define regUTCL2_MEM_ECC_INDEX 0x0863
+#define regUTCL2_MEM_ECC_INDEX_BASE_IDX 0
+#define regVML2_MEM_ECC_CNTL 0x0864
+#define regVML2_MEM_ECC_CNTL_BASE_IDX 0
+#define regVML2_WALKER_MEM_ECC_CNTL 0x0865
+#define regVML2_WALKER_MEM_ECC_CNTL_BASE_IDX 0
+#define regUTCL2_MEM_ECC_CNTL 0x0866
+#define regUTCL2_MEM_ECC_CNTL_BASE_IDX 0
+#define regVML2_MEM_ECC_STATUS 0x0867
+#define regVML2_MEM_ECC_STATUS_BASE_IDX 0
+#define regVML2_WALKER_MEM_ECC_STATUS 0x0868
+#define regVML2_WALKER_MEM_ECC_STATUS_BASE_IDX 0
+#define regUTCL2_MEM_ECC_STATUS 0x0869
+#define regUTCL2_MEM_ECC_STATUS_BASE_IDX 0
+#define regUTCL2_EDC_MODE 0x086a
+#define regUTCL2_EDC_MODE_BASE_IDX 0
+#define regUTCL2_EDC_CONFIG 0x086b
+#define regUTCL2_EDC_CONFIG_BASE_IDX 0
+
+
+// addressBlock: gc_utcl2_vml2pldec
+// base address: 0x37530
+#define regMC_VM_L2_PERFCOUNTER0_CFG 0x3d4c
+#define regMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 1
+#define regMC_VM_L2_PERFCOUNTER1_CFG 0x3d4d
+#define regMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 1
+#define regMC_VM_L2_PERFCOUNTER2_CFG 0x3d4e
+#define regMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 1
+#define regMC_VM_L2_PERFCOUNTER3_CFG 0x3d4f
+#define regMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 1
+#define regMC_VM_L2_PERFCOUNTER4_CFG 0x3d50
+#define regMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 1
+#define regMC_VM_L2_PERFCOUNTER5_CFG 0x3d51
+#define regMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1
+#define regMC_VM_L2_PERFCOUNTER6_CFG 0x3d52
+#define regMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 1
+#define regMC_VM_L2_PERFCOUNTER7_CFG 0x3d53
+#define regMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 1
+#define regMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x3d54
+#define regMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
+
+
+// addressBlock: gc_utcl2_vml2prdec
+// base address: 0x35420
+#define regMC_VM_L2_PERFCOUNTER_LO 0x3508
+#define regMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 1
+#define regMC_VM_L2_PERFCOUNTER_HI 0x3509
+#define regMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 1
+
+
+// addressBlock: gc_utcl2_vml2vcdec
+// base address: 0xa200
+#define regVM_CONTEXT0_CNTL 0x0880
+#define regVM_CONTEXT0_CNTL_BASE_IDX 0
+#define regVM_CONTEXT1_CNTL 0x0881
+#define regVM_CONTEXT1_CNTL_BASE_IDX 0
+#define regVM_CONTEXT2_CNTL 0x0882
+#define regVM_CONTEXT2_CNTL_BASE_IDX 0
+#define regVM_CONTEXT3_CNTL 0x0883
+#define regVM_CONTEXT3_CNTL_BASE_IDX 0
+#define regVM_CONTEXT4_CNTL 0x0884
+#define regVM_CONTEXT4_CNTL_BASE_IDX 0
+#define regVM_CONTEXT5_CNTL 0x0885
+#define regVM_CONTEXT5_CNTL_BASE_IDX 0
+#define regVM_CONTEXT6_CNTL 0x0886
+#define regVM_CONTEXT6_CNTL_BASE_IDX 0
+#define regVM_CONTEXT7_CNTL 0x0887
+#define regVM_CONTEXT7_CNTL_BASE_IDX 0
+#define regVM_CONTEXT8_CNTL 0x0888
+#define regVM_CONTEXT8_CNTL_BASE_IDX 0
+#define regVM_CONTEXT9_CNTL 0x0889
+#define regVM_CONTEXT9_CNTL_BASE_IDX 0
+#define regVM_CONTEXT10_CNTL 0x088a
+#define regVM_CONTEXT10_CNTL_BASE_IDX 0
+#define regVM_CONTEXT11_CNTL 0x088b
+#define regVM_CONTEXT11_CNTL_BASE_IDX 0
+#define regVM_CONTEXT12_CNTL 0x088c
+#define regVM_CONTEXT12_CNTL_BASE_IDX 0
+#define regVM_CONTEXT13_CNTL 0x088d
+#define regVM_CONTEXT13_CNTL_BASE_IDX 0
+#define regVM_CONTEXT14_CNTL 0x088e
+#define regVM_CONTEXT14_CNTL_BASE_IDX 0
+#define regVM_CONTEXT15_CNTL 0x088f
+#define regVM_CONTEXT15_CNTL_BASE_IDX 0
+#define regVM_CONTEXTS_DISABLE 0x0890
+#define regVM_CONTEXTS_DISABLE_BASE_IDX 0
+#define regVM_INVALIDATE_ENG0_SEM 0x0891
+#define regVM_INVALIDATE_ENG0_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG1_SEM 0x0892
+#define regVM_INVALIDATE_ENG1_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG2_SEM 0x0893
+#define regVM_INVALIDATE_ENG2_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG3_SEM 0x0894
+#define regVM_INVALIDATE_ENG3_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG4_SEM 0x0895
+#define regVM_INVALIDATE_ENG4_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG5_SEM 0x0896
+#define regVM_INVALIDATE_ENG5_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG6_SEM 0x0897
+#define regVM_INVALIDATE_ENG6_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG7_SEM 0x0898
+#define regVM_INVALIDATE_ENG7_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG8_SEM 0x0899
+#define regVM_INVALIDATE_ENG8_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG9_SEM 0x089a
+#define regVM_INVALIDATE_ENG9_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG10_SEM 0x089b
+#define regVM_INVALIDATE_ENG10_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG11_SEM 0x089c
+#define regVM_INVALIDATE_ENG11_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG12_SEM 0x089d
+#define regVM_INVALIDATE_ENG12_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG13_SEM 0x089e
+#define regVM_INVALIDATE_ENG13_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG14_SEM 0x089f
+#define regVM_INVALIDATE_ENG14_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG15_SEM 0x08a0
+#define regVM_INVALIDATE_ENG15_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG16_SEM 0x08a1
+#define regVM_INVALIDATE_ENG16_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG17_SEM 0x08a2
+#define regVM_INVALIDATE_ENG17_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG0_REQ 0x08a3
+#define regVM_INVALIDATE_ENG0_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG1_REQ 0x08a4
+#define regVM_INVALIDATE_ENG1_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG2_REQ 0x08a5
+#define regVM_INVALIDATE_ENG2_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG3_REQ 0x08a6
+#define regVM_INVALIDATE_ENG3_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG4_REQ 0x08a7
+#define regVM_INVALIDATE_ENG4_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG5_REQ 0x08a8
+#define regVM_INVALIDATE_ENG5_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG6_REQ 0x08a9
+#define regVM_INVALIDATE_ENG6_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG7_REQ 0x08aa
+#define regVM_INVALIDATE_ENG7_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG8_REQ 0x08ab
+#define regVM_INVALIDATE_ENG8_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG9_REQ 0x08ac
+#define regVM_INVALIDATE_ENG9_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG10_REQ 0x08ad
+#define regVM_INVALIDATE_ENG10_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG11_REQ 0x08ae
+#define regVM_INVALIDATE_ENG11_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG12_REQ 0x08af
+#define regVM_INVALIDATE_ENG12_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG13_REQ 0x08b0
+#define regVM_INVALIDATE_ENG13_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG14_REQ 0x08b1
+#define regVM_INVALIDATE_ENG14_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG15_REQ 0x08b2
+#define regVM_INVALIDATE_ENG15_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG16_REQ 0x08b3
+#define regVM_INVALIDATE_ENG16_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG17_REQ 0x08b4
+#define regVM_INVALIDATE_ENG17_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG0_ACK 0x08b5
+#define regVM_INVALIDATE_ENG0_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG1_ACK 0x08b6
+#define regVM_INVALIDATE_ENG1_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG2_ACK 0x08b7
+#define regVM_INVALIDATE_ENG2_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG3_ACK 0x08b8
+#define regVM_INVALIDATE_ENG3_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG4_ACK 0x08b9
+#define regVM_INVALIDATE_ENG4_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG5_ACK 0x08ba
+#define regVM_INVALIDATE_ENG5_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG6_ACK 0x08bb
+#define regVM_INVALIDATE_ENG6_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG7_ACK 0x08bc
+#define regVM_INVALIDATE_ENG7_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG8_ACK 0x08bd
+#define regVM_INVALIDATE_ENG8_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG9_ACK 0x08be
+#define regVM_INVALIDATE_ENG9_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG10_ACK 0x08bf
+#define regVM_INVALIDATE_ENG10_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG11_ACK 0x08c0
+#define regVM_INVALIDATE_ENG11_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG12_ACK 0x08c1
+#define regVM_INVALIDATE_ENG12_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG13_ACK 0x08c2
+#define regVM_INVALIDATE_ENG13_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG14_ACK 0x08c3
+#define regVM_INVALIDATE_ENG14_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG15_ACK 0x08c4
+#define regVM_INVALIDATE_ENG15_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG16_ACK 0x08c5
+#define regVM_INVALIDATE_ENG16_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG17_ACK 0x08c6
+#define regVM_INVALIDATE_ENG17_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x08c7
+#define regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x08c8
+#define regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x08c9
+#define regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x08ca
+#define regVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x08cb
+#define regVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x08cc
+#define regVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x08cd
+#define regVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x08ce
+#define regVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x08cf
+#define regVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x08d0
+#define regVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x08d1
+#define regVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x08d2
+#define regVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x08d3
+#define regVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x08d4
+#define regVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x08d5
+#define regVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x08d6
+#define regVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x08d7
+#define regVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x08d8
+#define regVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x08d9
+#define regVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x08da
+#define regVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x08db
+#define regVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x08dc
+#define regVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x08dd
+#define regVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x08de
+#define regVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x08df
+#define regVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x08e0
+#define regVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x08e1
+#define regVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x08e2
+#define regVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x08e3
+#define regVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x08e4
+#define regVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x08e5
+#define regVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x08e6
+#define regVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x08e7
+#define regVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x08e8
+#define regVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x08e9
+#define regVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x08ea
+#define regVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x08eb
+#define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x08ec
+#define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x08ed
+#define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x08ee
+#define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x08ef
+#define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x08f0
+#define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x08f1
+#define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x08f2
+#define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x08f3
+#define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x08f4
+#define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x08f5
+#define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x08f6
+#define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x08f7
+#define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x08f8
+#define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x08f9
+#define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x08fa
+#define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x08fb
+#define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x08fc
+#define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x08fd
+#define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x08fe
+#define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x08ff
+#define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0900
+#define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0901
+#define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0902
+#define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x0903
+#define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x0904
+#define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x0905
+#define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x0906
+#define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x0907
+#define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x0908
+#define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x0909
+#define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x090a
+#define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x090b
+#define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x090c
+#define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x090d
+#define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x090e
+#define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x090f
+#define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x0910
+#define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0911
+#define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0912
+#define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0913
+#define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0914
+#define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0915
+#define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x0916
+#define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0917
+#define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0918
+#define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x0919
+#define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x091a
+#define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x091b
+#define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x091c
+#define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x091d
+#define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x091e
+#define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x091f
+#define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0920
+#define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0921
+#define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0922
+#define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0923
+#define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0924
+#define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0925
+#define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x0926
+#define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x0927
+#define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x0928
+#define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x0929
+#define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x092a
+#define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x092b
+#define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x092c
+#define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x092d
+#define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x092e
+#define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x092f
+#define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0930
+#define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0931
+#define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0932
+#define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0933
+#define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0934
+#define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0935
+#define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0936
+#define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0937
+#define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0938
+#define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0939
+#define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x093a
+#define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x093b
+#define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x093c
+#define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x093d
+#define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x093e
+#define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x093f
+#define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0940
+#define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0941
+#define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0942
+#define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0943
+#define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0944
+#define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0945
+#define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0946
+#define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0947
+#define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0948
+#define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0949
+#define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x094a
+#define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+
+
+// addressBlock: gc_utcl2_vmsharedhvdec
+// base address: 0x3ea00
+#define regMC_VM_FB_SIZE_OFFSET_VF0 0x5a80
+#define regMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 1
+#define regMC_VM_FB_SIZE_OFFSET_VF1 0x5a81
+#define regMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 1
+#define regMC_VM_FB_SIZE_OFFSET_VF2 0x5a82
+#define regMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 1
+#define regMC_VM_FB_SIZE_OFFSET_VF3 0x5a83
+#define regMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 1
+#define regMC_VM_FB_SIZE_OFFSET_VF4 0x5a84
+#define regMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 1
+#define regMC_VM_FB_SIZE_OFFSET_VF5 0x5a85
+#define regMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 1
+#define regMC_VM_FB_SIZE_OFFSET_VF6 0x5a86
+#define regMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 1
+#define regMC_VM_FB_SIZE_OFFSET_VF7 0x5a87
+#define regMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 1
+#define regMC_VM_FB_SIZE_OFFSET_VF8 0x5a88
+#define regMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 1
+#define regMC_VM_FB_SIZE_OFFSET_VF9 0x5a89
+#define regMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 1
+#define regMC_VM_FB_SIZE_OFFSET_VF10 0x5a8a
+#define regMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 1
+#define regMC_VM_FB_SIZE_OFFSET_VF11 0x5a8b
+#define regMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 1
+#define regMC_VM_FB_SIZE_OFFSET_VF12 0x5a8c
+#define regMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 1
+#define regMC_VM_FB_SIZE_OFFSET_VF13 0x5a8d
+#define regMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 1
+#define regMC_VM_FB_SIZE_OFFSET_VF14 0x5a8e
+#define regMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 1
+#define regMC_VM_FB_SIZE_OFFSET_VF15 0x5a8f
+#define regMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 1
+#define regMC_VM_MARC_BASE_LO_0 0x5a91
+#define regMC_VM_MARC_BASE_LO_0_BASE_IDX 1
+#define regMC_VM_MARC_BASE_LO_1 0x5a92
+#define regMC_VM_MARC_BASE_LO_1_BASE_IDX 1
+#define regMC_VM_MARC_BASE_LO_2 0x5a93
+#define regMC_VM_MARC_BASE_LO_2_BASE_IDX 1
+#define regMC_VM_MARC_BASE_LO_3 0x5a94
+#define regMC_VM_MARC_BASE_LO_3_BASE_IDX 1
+#define regMC_VM_MARC_BASE_HI_0 0x5a95
+#define regMC_VM_MARC_BASE_HI_0_BASE_IDX 1
+#define regMC_VM_MARC_BASE_HI_1 0x5a96
+#define regMC_VM_MARC_BASE_HI_1_BASE_IDX 1
+#define regMC_VM_MARC_BASE_HI_2 0x5a97
+#define regMC_VM_MARC_BASE_HI_2_BASE_IDX 1
+#define regMC_VM_MARC_BASE_HI_3 0x5a98
+#define regMC_VM_MARC_BASE_HI_3_BASE_IDX 1
+#define regMC_VM_MARC_RELOC_LO_0 0x5a99
+#define regMC_VM_MARC_RELOC_LO_0_BASE_IDX 1
+#define regMC_VM_MARC_RELOC_LO_1 0x5a9a
+#define regMC_VM_MARC_RELOC_LO_1_BASE_IDX 1
+#define regMC_VM_MARC_RELOC_LO_2 0x5a9b
+#define regMC_VM_MARC_RELOC_LO_2_BASE_IDX 1
+#define regMC_VM_MARC_RELOC_LO_3 0x5a9c
+#define regMC_VM_MARC_RELOC_LO_3_BASE_IDX 1
+#define regMC_VM_MARC_RELOC_HI_0 0x5a9d
+#define regMC_VM_MARC_RELOC_HI_0_BASE_IDX 1
+#define regMC_VM_MARC_RELOC_HI_1 0x5a9e
+#define regMC_VM_MARC_RELOC_HI_1_BASE_IDX 1
+#define regMC_VM_MARC_RELOC_HI_2 0x5a9f
+#define regMC_VM_MARC_RELOC_HI_2_BASE_IDX 1
+#define regMC_VM_MARC_RELOC_HI_3 0x5aa0
+#define regMC_VM_MARC_RELOC_HI_3_BASE_IDX 1
+#define regMC_VM_MARC_LEN_LO_0 0x5aa1
+#define regMC_VM_MARC_LEN_LO_0_BASE_IDX 1
+#define regMC_VM_MARC_LEN_LO_1 0x5aa2
+#define regMC_VM_MARC_LEN_LO_1_BASE_IDX 1
+#define regMC_VM_MARC_LEN_LO_2 0x5aa3
+#define regMC_VM_MARC_LEN_LO_2_BASE_IDX 1
+#define regMC_VM_MARC_LEN_LO_3 0x5aa4
+#define regMC_VM_MARC_LEN_LO_3_BASE_IDX 1
+#define regMC_VM_MARC_LEN_HI_0 0x5aa5
+#define regMC_VM_MARC_LEN_HI_0_BASE_IDX 1
+#define regMC_VM_MARC_LEN_HI_1 0x5aa6
+#define regMC_VM_MARC_LEN_HI_1_BASE_IDX 1
+#define regMC_VM_MARC_LEN_HI_2 0x5aa7
+#define regMC_VM_MARC_LEN_HI_2_BASE_IDX 1
+#define regMC_VM_MARC_LEN_HI_3 0x5aa8
+#define regMC_VM_MARC_LEN_HI_3_BASE_IDX 1
+#define regVM_PCIE_ATS_CNTL 0x5aab
+#define regVM_PCIE_ATS_CNTL_BASE_IDX 1
+#define regVM_PCIE_ATS_CNTL_VF_0 0x5aac
+#define regVM_PCIE_ATS_CNTL_VF_0_BASE_IDX 1
+#define regVM_PCIE_ATS_CNTL_VF_1 0x5aad
+#define regVM_PCIE_ATS_CNTL_VF_1_BASE_IDX 1
+#define regVM_PCIE_ATS_CNTL_VF_2 0x5aae
+#define regVM_PCIE_ATS_CNTL_VF_2_BASE_IDX 1
+#define regVM_PCIE_ATS_CNTL_VF_3 0x5aaf
+#define regVM_PCIE_ATS_CNTL_VF_3_BASE_IDX 1
+#define regVM_PCIE_ATS_CNTL_VF_4 0x5ab0
+#define regVM_PCIE_ATS_CNTL_VF_4_BASE_IDX 1
+#define regVM_PCIE_ATS_CNTL_VF_5 0x5ab1
+#define regVM_PCIE_ATS_CNTL_VF_5_BASE_IDX 1
+#define regVM_PCIE_ATS_CNTL_VF_6 0x5ab2
+#define regVM_PCIE_ATS_CNTL_VF_6_BASE_IDX 1
+#define regVM_PCIE_ATS_CNTL_VF_7 0x5ab3
+#define regVM_PCIE_ATS_CNTL_VF_7_BASE_IDX 1
+#define regVM_PCIE_ATS_CNTL_VF_8 0x5ab4
+#define regVM_PCIE_ATS_CNTL_VF_8_BASE_IDX 1
+#define regVM_PCIE_ATS_CNTL_VF_9 0x5ab5
+#define regVM_PCIE_ATS_CNTL_VF_9_BASE_IDX 1
+#define regVM_PCIE_ATS_CNTL_VF_10 0x5ab6
+#define regVM_PCIE_ATS_CNTL_VF_10_BASE_IDX 1
+#define regVM_PCIE_ATS_CNTL_VF_11 0x5ab7
+#define regVM_PCIE_ATS_CNTL_VF_11_BASE_IDX 1
+#define regVM_PCIE_ATS_CNTL_VF_12 0x5ab8
+#define regVM_PCIE_ATS_CNTL_VF_12_BASE_IDX 1
+#define regVM_PCIE_ATS_CNTL_VF_13 0x5ab9
+#define regVM_PCIE_ATS_CNTL_VF_13_BASE_IDX 1
+#define regVM_PCIE_ATS_CNTL_VF_14 0x5aba
+#define regVM_PCIE_ATS_CNTL_VF_14_BASE_IDX 1
+#define regVM_PCIE_ATS_CNTL_VF_15 0x5abb
+#define regVM_PCIE_ATS_CNTL_VF_15_BASE_IDX 1
+#define regMC_SHARED_ACTIVE_FCN_ID 0x5abc
+#define regMC_SHARED_ACTIVE_FCN_ID_BASE_IDX 1
+#define regMC_VM_XGMI_GPUIOV_ENABLE 0x5abd
+#define regMC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX 1
+
+
+// addressBlock: gc_utcl2_vmsharedpfdec
+// base address: 0xa590
+#define regMC_VM_FB_OFFSET 0x096b
+#define regMC_VM_FB_OFFSET_BASE_IDX 0
+#define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x096c
+#define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0
+#define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x096d
+#define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0
+#define regMC_VM_STEERING 0x096e
+#define regMC_VM_STEERING_BASE_IDX 0
+#define regMC_SHARED_VIRT_RESET_REQ 0x096f
+#define regMC_SHARED_VIRT_RESET_REQ_BASE_IDX 0
+#define regMC_MEM_POWER_LS 0x0970
+#define regMC_MEM_POWER_LS_BASE_IDX 0
+#define regMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x0971
+#define regMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0
+#define regMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x0972
+#define regMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0
+#define regMC_VM_APT_CNTL 0x0973
+#define regMC_VM_APT_CNTL_BASE_IDX 0
+#define regMC_VM_LOCAL_HBM_ADDRESS_START 0x0974
+#define regMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 0
+#define regMC_VM_LOCAL_HBM_ADDRESS_END 0x0975
+#define regMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 0
+#define regMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x0976
+#define regMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 0
+#define regUTCL2_CGTT_CLK_CTRL 0x0977
+#define regUTCL2_CGTT_CLK_CTRL_BASE_IDX 0
+#define regMC_VM_XGMI_LFB_CNTL 0x0978
+#define regMC_VM_XGMI_LFB_CNTL_BASE_IDX 0
+#define regMC_VM_XGMI_LFB_SIZE 0x0979
+#define regMC_VM_XGMI_LFB_SIZE_BASE_IDX 0
+#define regMC_VM_CACHEABLE_DRAM_CNTL 0x097a
+#define regMC_VM_CACHEABLE_DRAM_CNTL_BASE_IDX 0
+#define regMC_VM_HOST_MAPPING 0x097b
+#define regMC_VM_HOST_MAPPING_BASE_IDX 0
+
+
+// addressBlock: gc_utcl2_vmsharedvcdec
+// base address: 0xa600
+#define regMC_VM_FB_LOCATION_BASE 0x0980
+#define regMC_VM_FB_LOCATION_BASE_BASE_IDX 0
+#define regMC_VM_FB_LOCATION_TOP 0x0981
+#define regMC_VM_FB_LOCATION_TOP_BASE_IDX 0
+#define regMC_VM_AGP_TOP 0x0982
+#define regMC_VM_AGP_TOP_BASE_IDX 0
+#define regMC_VM_AGP_BOT 0x0983
+#define regMC_VM_AGP_BOT_BASE_IDX 0
+#define regMC_VM_AGP_BASE 0x0984
+#define regMC_VM_AGP_BASE_BASE_IDX 0
+#define regMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0985
+#define regMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0
+#define regMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0986
+#define regMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0
+#define regMC_VM_MX_L1_TLB_CNTL 0x0987
+#define regMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0
+
+
+// addressBlock: gccacind
+// base address: 0x0
+#define ixGC_CAC_CNTL 0x0000
+#define ixGC_CAC_OVR_SEL 0x0001
+#define ixGC_CAC_OVR_VAL 0x0002
+#define ixGC_CAC_WEIGHT_BCI_0 0x0003
+#define ixGC_CAC_WEIGHT_CB_0 0x0004
+#define ixGC_CAC_WEIGHT_CB_1 0x0005
+#define ixGC_CAC_WEIGHT_CP_0 0x0008
+#define ixGC_CAC_WEIGHT_CP_1 0x0009
+#define ixGC_CAC_WEIGHT_DB_0 0x000a
+#define ixGC_CAC_WEIGHT_DB_1 0x000b
+#define ixGC_CAC_WEIGHT_GDS_0 0x000e
+#define ixGC_CAC_WEIGHT_GDS_1 0x000f
+#define ixGC_CAC_WEIGHT_IA_0 0x0010
+#define ixGC_CAC_WEIGHT_LDS_0 0x0011
+#define ixGC_CAC_WEIGHT_LDS_1 0x0012
+#define ixGC_CAC_WEIGHT_PA_0 0x0013
+#define ixGC_CAC_WEIGHT_PC_0 0x0014
+#define ixGC_CAC_WEIGHT_SC_0 0x0015
+#define ixGC_CAC_WEIGHT_SPI_0 0x0016
+#define ixGC_CAC_WEIGHT_SPI_1 0x0017
+#define ixGC_CAC_WEIGHT_SPI_2 0x0018
+#define ixGC_CAC_WEIGHT_SQ_0 0x001a
+#define ixGC_CAC_WEIGHT_SQ_1 0x001b
+#define ixGC_CAC_WEIGHT_SQ_2 0x001c
+#define ixGC_CAC_WEIGHT_SQ_3 0x001d
+#define ixGC_CAC_WEIGHT_SQ_4 0x001e
+#define ixGC_CAC_WEIGHT_SX_0 0x001f
+#define ixGC_CAC_WEIGHT_SXRB_0 0x0020
+#define ixGC_CAC_WEIGHT_TA_0 0x0021
+#define ixGC_CAC_WEIGHT_TCC_0 0x0022
+#define ixGC_CAC_WEIGHT_TCC_1 0x0023
+#define ixGC_CAC_WEIGHT_TCC_2 0x0024
+#define ixGC_CAC_WEIGHT_TCP_0 0x0025
+#define ixGC_CAC_WEIGHT_TCP_1 0x0026
+#define ixGC_CAC_WEIGHT_TCP_2 0x0027
+#define ixGC_CAC_WEIGHT_TD_0 0x0028
+#define ixGC_CAC_WEIGHT_TD_1 0x0029
+#define ixGC_CAC_WEIGHT_TD_2 0x002a
+#define ixGC_CAC_WEIGHT_VGT_0 0x002b
+#define ixGC_CAC_WEIGHT_VGT_1 0x002c
+#define ixGC_CAC_WEIGHT_WD_0 0x002d
+#define ixGC_CAC_WEIGHT_CU_0 0x0032
+#define ixGC_CAC_ACC_BCI0 0x0042
+#define ixGC_CAC_ACC_CB0 0x0043
+#define ixGC_CAC_ACC_CB1 0x0044
+#define ixGC_CAC_ACC_CB2 0x0045
+#define ixGC_CAC_ACC_CB3 0x0046
+#define ixGC_CAC_ACC_CP0 0x004b
+#define ixGC_CAC_ACC_CP1 0x004c
+#define ixGC_CAC_ACC_CP2 0x004d
+#define ixGC_CAC_ACC_DB0 0x004e
+#define ixGC_CAC_ACC_DB1 0x004f
+#define ixGC_CAC_ACC_DB2 0x0050
+#define ixGC_CAC_ACC_DB3 0x0051
+#define ixGC_CAC_ACC_GDS0 0x0056
+#define ixGC_CAC_ACC_GDS1 0x0057
+#define ixGC_CAC_ACC_GDS2 0x0058
+#define ixGC_CAC_ACC_GDS3 0x0059
+#define ixGC_CAC_ACC_IA0 0x005a
+#define ixGC_CAC_ACC_LDS0 0x005b
+#define ixGC_CAC_ACC_LDS1 0x005c
+#define ixGC_CAC_ACC_LDS2 0x005d
+#define ixGC_CAC_ACC_LDS3 0x005e
+#define ixGC_CAC_ACC_PA0 0x005f
+#define ixGC_CAC_ACC_PA1 0x0060
+#define ixGC_CAC_ACC_PC0 0x0061
+#define ixGC_CAC_ACC_SC0 0x0062
+#define ixGC_CAC_ACC_SPI0 0x0063
+#define ixGC_CAC_ACC_SPI1 0x0064
+#define ixGC_CAC_ACC_SPI2 0x0065
+#define ixGC_CAC_ACC_SPI3 0x0066
+#define ixGC_CAC_ACC_SPI4 0x0067
+#define ixGC_CAC_ACC_SPI5 0x0068
+#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_0 0x006f
+#define ixGC_CAC_ACC_EA0 0x0070
+#define ixGC_CAC_ACC_EA1 0x0071
+#define ixGC_CAC_ACC_EA2 0x0072
+#define ixGC_CAC_ACC_EA3 0x0073
+#define ixGC_CAC_ACC_UTCL2_ATCL20 0x0074
+#define ixGC_CAC_OVRD_EA 0x0075
+#define ixGC_CAC_OVRD_UTCL2_ATCL2 0x0076
+#define ixGC_CAC_WEIGHT_EA_0 0x0077
+#define ixGC_CAC_WEIGHT_EA_1 0x0078
+#define ixGC_CAC_WEIGHT_RMI_0 0x0079
+#define ixGC_CAC_ACC_RMI0 0x007a
+#define ixGC_CAC_OVRD_RMI 0x007b
+#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_1 0x007c
+#define ixGC_CAC_ACC_UTCL2_ATCL21 0x007d
+#define ixGC_CAC_ACC_UTCL2_ATCL22 0x007e
+#define ixGC_CAC_ACC_UTCL2_ATCL23 0x007f
+#define ixGC_CAC_ACC_EA4 0x0080
+#define ixGC_CAC_ACC_EA5 0x0081
+#define ixGC_CAC_WEIGHT_EA_2 0x0082
+#define ixGC_CAC_ACC_SQ0_LOWER 0x0089
+#define ixGC_CAC_ACC_SQ0_UPPER 0x008a
+#define ixGC_CAC_ACC_SQ1_LOWER 0x008b
+#define ixGC_CAC_ACC_SQ1_UPPER 0x008c
+#define ixGC_CAC_ACC_SQ2_LOWER 0x008d
+#define ixGC_CAC_ACC_SQ2_UPPER 0x008e
+#define ixGC_CAC_ACC_SQ3_LOWER 0x008f
+#define ixGC_CAC_ACC_SQ3_UPPER 0x0090
+#define ixGC_CAC_ACC_SQ4_LOWER 0x0091
+#define ixGC_CAC_ACC_SQ4_UPPER 0x0092
+#define ixGC_CAC_ACC_SQ5_LOWER 0x0093
+#define ixGC_CAC_ACC_SQ5_UPPER 0x0094
+#define ixGC_CAC_ACC_SQ6_LOWER 0x0095
+#define ixGC_CAC_ACC_SQ6_UPPER 0x0096
+#define ixGC_CAC_ACC_SQ7_LOWER 0x0097
+#define ixGC_CAC_ACC_SQ7_UPPER 0x0098
+#define ixGC_CAC_ACC_SQ8_LOWER 0x0099
+#define ixGC_CAC_ACC_SQ8_UPPER 0x009a
+#define ixGC_CAC_ACC_SX0 0x009b
+#define ixGC_CAC_ACC_SXRB0 0x009c
+#define ixGC_CAC_ACC_SXRB1 0x009d
+#define ixGC_CAC_ACC_TA0 0x009e
+#define ixGC_CAC_ACC_TCC0 0x009f
+#define ixGC_CAC_ACC_TCC1 0x00a0
+#define ixGC_CAC_ACC_TCC2 0x00a1
+#define ixGC_CAC_ACC_TCC3 0x00a2
+#define ixGC_CAC_ACC_TCC4 0x00a3
+#define ixGC_CAC_ACC_TCP0 0x00a4
+#define ixGC_CAC_ACC_TCP1 0x00a5
+#define ixGC_CAC_ACC_TCP2 0x00a6
+#define ixGC_CAC_ACC_TCP3 0x00a7
+#define ixGC_CAC_ACC_TCP4 0x00a8
+#define ixGC_CAC_ACC_TD0 0x00a9
+#define ixGC_CAC_ACC_TD1 0x00aa
+#define ixGC_CAC_ACC_TD2 0x00ab
+#define ixGC_CAC_ACC_TD3 0x00ac
+#define ixGC_CAC_ACC_TD4 0x00ad
+#define ixGC_CAC_ACC_TD5 0x00ae
+#define ixGC_CAC_ACC_VGT0 0x00af
+#define ixGC_CAC_ACC_VGT1 0x00b0
+#define ixGC_CAC_ACC_VGT2 0x00b1
+#define ixGC_CAC_ACC_WD0 0x00b2
+#define ixGC_CAC_ACC_CU0 0x00ba
+#define ixGC_CAC_ACC_CU1 0x00bb
+#define ixGC_CAC_ACC_CU2 0x00bc
+#define ixGC_CAC_ACC_CU3 0x00bd
+#define ixGC_CAC_ACC_CU4 0x00be
+#define ixGC_CAC_ACC_CU5 0x00bf
+#define ixGC_CAC_ACC_CU6 0x00c0
+#define ixGC_CAC_ACC_CU7 0x00c1
+#define ixGC_CAC_ACC_CU8 0x00c2
+#define ixGC_CAC_ACC_CU9 0x00c3
+#define ixGC_CAC_ACC_CU10 0x00c4
+#define ixGC_CAC_ACC_CU11 0x00c5
+#define ixGC_CAC_ACC_CU12 0x00c6
+#define ixGC_CAC_ACC_CU13 0x00c7
+#define ixGC_CAC_OVRD_BCI 0x00da
+#define ixGC_CAC_OVRD_CB 0x00db
+#define ixGC_CAC_OVRD_CP 0x00dd
+#define ixGC_CAC_OVRD_DB 0x00de
+#define ixGC_CAC_OVRD_GDS 0x00e0
+#define ixGC_CAC_OVRD_IA 0x00e1
+#define ixGC_CAC_OVRD_LDS 0x00e2
+#define ixGC_CAC_OVRD_PA 0x00e3
+#define ixGC_CAC_OVRD_PC 0x00e4
+#define ixGC_CAC_OVRD_SC 0x00e5
+#define ixGC_CAC_OVRD_SPI 0x00e6
+#define ixGC_CAC_OVRD_CU 0x00e7
+#define ixGC_CAC_OVRD_SQ 0x00e8
+#define ixGC_CAC_OVRD_SX 0x00e9
+#define ixGC_CAC_OVRD_SXRB 0x00ea
+#define ixGC_CAC_OVRD_TA 0x00eb
+#define ixGC_CAC_OVRD_TCC 0x00ec
+#define ixGC_CAC_OVRD_TCP 0x00ed
+#define ixGC_CAC_OVRD_TD 0x00ee
+#define ixGC_CAC_OVRD_VGT 0x00ef
+#define ixGC_CAC_OVRD_WD 0x00f0
+#define ixGC_CAC_ACC_BCI1 0x00ff
+#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_2 0x0100
+#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_0 0x0101
+#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_1 0x0102
+#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_2 0x0103
+#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_3 0x0104
+#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_4 0x0105
+#define ixGC_CAC_WEIGHT_UTCL2_VML2_0 0x0106
+#define ixGC_CAC_WEIGHT_UTCL2_VML2_1 0x0107
+#define ixGC_CAC_WEIGHT_UTCL2_VML2_2 0x0108
+#define ixGC_CAC_ACC_UTCL2_ATCL24 0x0109
+#define ixGC_CAC_ACC_UTCL2_ROUTER0 0x010a
+#define ixGC_CAC_ACC_UTCL2_ROUTER1 0x010b
+#define ixGC_CAC_ACC_UTCL2_ROUTER2 0x010c
+#define ixGC_CAC_ACC_UTCL2_ROUTER3 0x010d
+#define ixGC_CAC_ACC_UTCL2_ROUTER4 0x010e
+#define ixGC_CAC_ACC_UTCL2_ROUTER5 0x010f
+#define ixGC_CAC_ACC_UTCL2_ROUTER6 0x0110
+#define ixGC_CAC_ACC_UTCL2_ROUTER7 0x0111
+#define ixGC_CAC_ACC_UTCL2_ROUTER8 0x0112
+#define ixGC_CAC_ACC_UTCL2_ROUTER9 0x0113
+#define ixGC_CAC_ACC_UTCL2_VML20 0x0114
+#define ixGC_CAC_ACC_UTCL2_VML21 0x0115
+#define ixGC_CAC_ACC_UTCL2_VML22 0x0116
+#define ixGC_CAC_ACC_UTCL2_VML23 0x0117
+#define ixGC_CAC_ACC_UTCL2_VML24 0x0118
+#define ixGC_CAC_OVRD_UTCL2_ROUTER 0x0119
+#define ixGC_CAC_OVRD_UTCL2_VML2 0x011a
+#define ixGC_CAC_WEIGHT_UTCL2_WALKER_0 0x011b
+#define ixGC_CAC_WEIGHT_UTCL2_WALKER_1 0x011c
+#define ixGC_CAC_WEIGHT_UTCL2_WALKER_2 0x011d
+#define ixGC_CAC_ACC_UTCL2_WALKER0 0x011e
+#define ixGC_CAC_ACC_UTCL2_WALKER1 0x011f
+#define ixGC_CAC_ACC_UTCL2_WALKER2 0x0120
+#define ixGC_CAC_ACC_UTCL2_WALKER3 0x0121
+#define ixGC_CAC_ACC_UTCL2_WALKER4 0x0122
+#define ixGC_CAC_OVRD_UTCL2_WALKER 0x0123
+#define ixEDC_STALL_PATTERN_1_2 0x0130
+#define ixEDC_STALL_PATTERN_3_4 0x0131
+#define ixEDC_STALL_PATTERN_5_6 0x0132
+#define ixEDC_STALL_PATTERN_7 0x0133
+#define ixPCC_STALL_PATTERN_1_2 0x0134
+#define ixPCC_STALL_PATTERN_3_4 0x0135
+#define ixPCC_STALL_PATTERN_5_6 0x0136
+#define ixPCC_STALL_PATTERN_7 0x0137
+#define ixPCC_THROT_REINCR_FIRST_PATN_1_8 0x0138
+#define ixPCC_THROT_REINCR_FIRST_PATN_9_16 0x0139
+#define ixPCC_THROT_REINCR_FIRST_PATN_17_20 0x0140
+#define ixPCC_THROT_DECR_FIRST_PATN_1_4 0x0141
+#define ixPCC_THROT_DECR_FIRST_PATN_5_7 0x0142
+#define ixPWRBRK_STALL_PATTERN_CTRL 0x0143
+#define ixPWRBRK_STALL_PATTERN_1_2 0x0144
+#define ixPWRBRK_STALL_PATTERN_3_4 0x0145
+#define ixPWRBRK_STALL_PATTERN_5_6 0x0146
+#define ixPWRBRK_STALL_PATTERN_7 0x0147
+#define ixPCC_PWRBRK_HYSTERESIS_CTRL 0x0148
+#define ixFIXED_PATTERN_PERF_COUNTER_CTRL 0x015f
+#define ixFIXED_PATTERN_PERF_COUNTER_1 0x0160
+#define ixFIXED_PATTERN_PERF_COUNTER_2 0x0161
+#define ixFIXED_PATTERN_PERF_COUNTER_3 0x0162
+#define ixFIXED_PATTERN_PERF_COUNTER_4 0x0163
+#define ixFIXED_PATTERN_PERF_COUNTER_5 0x0164
+#define ixFIXED_PATTERN_PERF_COUNTER_6 0x0165
+#define ixFIXED_PATTERN_PERF_COUNTER_7 0x0166
+#define ixFIXED_PATTERN_PERF_COUNTER_8 0x0167
+#define ixFIXED_PATTERN_PERF_COUNTER_9 0x0168
+#define ixFIXED_PATTERN_PERF_COUNTER_10 0x0169
+
+
+// addressBlock: secacind
+// base address: 0x0
+#define ixSE_CAC_CNTL 0x0000
+#define ixSE_CAC_OVR_SEL 0x0001
+#define ixSE_CAC_OVR_VAL 0x0002
+
+
+// addressBlock: sqind
+// base address: 0x0
+#define ixSQ_DEBUG_STS_LOCAL 0x0008
+#define ixSQ_DEBUG_CTRL_LOCAL 0x0009
+#define ixSQ_WAVE_VALID_AND_IDLE 0x000a
+#define ixSQ_WAVE_MODE 0x0011
+#define ixSQ_WAVE_STATUS 0x0012
+#define ixSQ_WAVE_TRAPSTS 0x0013
+#define ixSQ_WAVE_HW_ID 0x0014
+#define ixSQ_WAVE_GPR_ALLOC 0x0015
+#define ixSQ_WAVE_LDS_ALLOC 0x0016
+#define ixSQ_WAVE_IB_STS 0x0017
+#define ixSQ_WAVE_PC_LO 0x0018
+#define ixSQ_WAVE_PC_HI 0x0019
+#define ixSQ_WAVE_INST_DW0 0x001a
+#define ixSQ_WAVE_INST_DW1 0x001b
+#define ixSQ_WAVE_IB_DBG0 0x001c
+#define ixSQ_WAVE_IB_DBG1 0x001d
+#define ixSQ_WAVE_FLUSH_IB 0x001e
+#define ixSQ_WAVE_TTMP0 0x026c
+#define ixSQ_WAVE_TTMP1 0x026d
+#define ixSQ_WAVE_TTMP3 0x026f
+#define ixSQ_WAVE_TTMP4 0x0270
+#define ixSQ_WAVE_TTMP5 0x0271
+#define ixSQ_WAVE_TTMP6 0x0272
+#define ixSQ_WAVE_TTMP7 0x0273
+#define ixSQ_WAVE_TTMP8 0x0274
+#define ixSQ_WAVE_TTMP9 0x0275
+#define ixSQ_WAVE_TTMP10 0x0276
+#define ixSQ_WAVE_TTMP11 0x0277
+#define ixSQ_WAVE_TTMP12 0x0278
+#define ixSQ_WAVE_TTMP13 0x0279
+#define ixSQ_WAVE_TTMP14 0x027a
+#define ixSQ_WAVE_TTMP15 0x027b
+#define ixSQ_WAVE_M0 0x027c
+#define ixSQ_WAVE_EXEC_LO 0x027e
+#define ixSQ_WAVE_EXEC_HI 0x027f
+#define ixSQ_INTERRUPT_WORD_AUTO_CTXID 0x20c0
+#define ixSQ_INTERRUPT_WORD_AUTO_HI 0x20c0
+#define ixSQ_INTERRUPT_WORD_AUTO_LO 0x20c0
+#define ixSQ_INTERRUPT_WORD_CMN_CTXID 0x20c0
+#define ixSQ_INTERRUPT_WORD_CMN_HI 0x20c0
+#define ixSQ_INTERRUPT_WORD_WAVE_CTXID 0x20c0
+#define ixSQ_INTERRUPT_WORD_WAVE_HI 0x20c0
+#define ixSQ_INTERRUPT_WORD_WAVE_LO 0x20c0
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h
new file mode 100644
index 000000000000..bc4d2997cb51
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h
@@ -0,0 +1,32949 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef _gc_9_4_2_SH_MASK_HEADER
+#define _gc_9_4_2_SH_MASK_HEADER
+
+
+// addressBlock: didtind
+//DIDT_SQ_CTRL0
+#define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
+#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x1
+#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x3
+#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
+#define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5
+#define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6
+#define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7
+#define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8
+#define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18
+#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19
+#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a
+#define DIDT_SQ_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT 0x1b
+#define DIDT_SQ_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT 0x1c
+#define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
+#define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0x00000006L
+#define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L
+#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
+#define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L
+#define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L
+#define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L
+#define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L
+#define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L
+#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L
+#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L
+#define DIDT_SQ_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK 0x08000000L
+#define DIDT_SQ_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK 0x10000000L
+//DIDT_SQ_CTRL2
+#define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
+#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
+#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
+#define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
+#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
+#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
+//DIDT_SQ_STALL_CTRL
+#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0
+#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6
+#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc
+#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12
+#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL
+#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L
+#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L
+#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L
+//DIDT_SQ_TUNING_CTRL
+#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0
+#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
+#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL
+#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L
+//DIDT_SQ_STALL_AUTO_RELEASE_CTRL
+#define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0
+#define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL
+//DIDT_SQ_CTRL3
+#define DIDT_SQ_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0
+#define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1
+#define DIDT_SQ_CTRL3__THROTTLE_POLICY__SHIFT 0x2
+#define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
+#define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9
+#define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
+#define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16
+#define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17
+#define DIDT_SQ_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18
+#define DIDT_SQ_CTRL3__DIDT_STALL_SEL__SHIFT 0x19
+#define DIDT_SQ_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b
+#define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c
+#define DIDT_SQ_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L
+#define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L
+#define DIDT_SQ_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL
+#define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
+#define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L
+#define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L
+#define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L
+#define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L
+#define DIDT_SQ_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L
+#define DIDT_SQ_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L
+#define DIDT_SQ_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L
+#define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L
+//DIDT_SQ_STALL_PATTERN_1_2
+#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0
+#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10
+#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL
+#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L
+//DIDT_SQ_STALL_PATTERN_3_4
+#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0
+#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10
+#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL
+#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L
+//DIDT_SQ_STALL_PATTERN_5_6
+#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0
+#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10
+#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL
+#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L
+//DIDT_SQ_STALL_PATTERN_7
+#define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0
+#define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL
+//DIDT_SQ_MPD_SCALE_FACTOR
+#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT 0x0
+#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT 0x4
+#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT 0x8
+#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT 0xc
+#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT 0x10
+#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT 0x14
+#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT 0x18
+#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT 0x1c
+#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK 0x0000000FL
+#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK 0x000000F0L
+#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK 0x00000F00L
+#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK 0x0000F000L
+#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK 0x000F0000L
+#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK 0x00F00000L
+#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK 0x0F000000L
+#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK 0xF0000000L
+//DIDT_SQ_THROTTLE_CNTL0
+#define DIDT_SQ_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN__SHIFT 0x0
+#define DIDT_SQ_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT 0x1
+#define DIDT_SQ_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT 0x2
+#define DIDT_SQ_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT 0xd
+#define DIDT_SQ_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN_MASK 0x00000001L
+#define DIDT_SQ_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL_MASK 0x00000002L
+#define DIDT_SQ_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK 0x00001FFCL
+#define DIDT_SQ_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK 0x00FFE000L
+//DIDT_SQ_THROTTLE_CNTL1
+#define DIDT_SQ_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT 0x0
+#define DIDT_SQ_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT 0x5
+#define DIDT_SQ_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa
+#define DIDT_SQ_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT 0xf
+#define DIDT_SQ_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK 0x0000001FL
+#define DIDT_SQ_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK 0x000003E0L
+#define DIDT_SQ_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK 0x00007C00L
+#define DIDT_SQ_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK 0x000F8000L
+//DIDT_SQ_THROTTLE_CNTL_STATUS
+#define DIDT_SQ_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE__SHIFT 0x0
+#define DIDT_SQ_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE_MASK 0x00000003L
+//DIDT_SQ_WEIGHT0_3
+#define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT 0x0
+#define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT 0x8
+#define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT 0x10
+#define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT 0x18
+#define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL
+#define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L
+#define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L
+#define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L
+//DIDT_SQ_WEIGHT4_7
+#define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT 0x0
+#define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT 0x8
+#define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT 0x10
+#define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT 0x18
+#define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL
+#define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L
+#define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L
+#define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L
+//DIDT_SQ_WEIGHT8_11
+#define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT 0x0
+#define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT 0x8
+#define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT 0x10
+#define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT 0x18
+#define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL
+#define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L
+#define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L
+#define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L
+//DIDT_SQ_EDC_CTRL
+#define DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT 0x0
+#define DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
+#define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
+#define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
+#define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
+#define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9
+#define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11
+#define DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT 0x12
+#define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13
+#define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15
+#define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16
+#define DIDT_SQ_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT 0x17
+#define DIDT_SQ_EDC_CTRL__EDC_EN_MASK 0x00000001L
+#define DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
+#define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
+#define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
+#define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
+#define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L
+#define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L
+#define DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L
+#define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L
+#define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L
+#define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L
+#define DIDT_SQ_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK 0x00800000L
+//DIDT_SQ_THROTTLE_CTRL
+#define DIDT_SQ_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT 0x0
+#define DIDT_SQ_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x1
+#define DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT 0x2
+#define DIDT_SQ_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT 0x3
+#define DIDT_SQ_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK 0x00000001L
+#define DIDT_SQ_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000002L
+#define DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK 0x00000004L
+#define DIDT_SQ_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000008L
+//DIDT_SQ_EDC_STALL_PATTERN_1_2
+#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0
+#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10
+#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL
+#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L
+//DIDT_SQ_EDC_STALL_PATTERN_3_4
+#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0
+#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10
+#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL
+#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L
+//DIDT_SQ_EDC_STALL_PATTERN_5_6
+#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0
+#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10
+#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL
+#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L
+//DIDT_SQ_EDC_STALL_PATTERN_7
+#define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0
+#define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL
+//DIDT_SQ_EDC_STATUS
+#define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0
+#define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1
+#define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L
+#define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL
+//DIDT_SQ_EDC_STALL_DELAY_1
+#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0__SHIFT 0x0
+#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1__SHIFT 0x8
+#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2__SHIFT 0x10
+#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3__SHIFT 0x18
+#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0_MASK 0x000000FFL
+#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1_MASK 0x0000FF00L
+#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2_MASK 0x00FF0000L
+#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3_MASK 0xFF000000L
+//DIDT_SQ_EDC_STALL_DELAY_2
+#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4__SHIFT 0x0
+#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5__SHIFT 0x8
+#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6__SHIFT 0x10
+#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7__SHIFT 0x18
+#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4_MASK 0x000000FFL
+#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5_MASK 0x0000FF00L
+#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6_MASK 0x00FF0000L
+#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7_MASK 0xFF000000L
+//DIDT_SQ_EDC_STALL_DELAY_3
+#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8__SHIFT 0x0
+#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9__SHIFT 0x8
+#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10__SHIFT 0x10
+#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11__SHIFT 0x18
+#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8_MASK 0x000000FFL
+#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9_MASK 0x0000FF00L
+#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10_MASK 0x00FF0000L
+#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11_MASK 0xFF000000L
+//DIDT_SQ_EDC_STALL_DELAY_4
+#define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12__SHIFT 0x0
+#define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ13__SHIFT 0x8
+#define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12_MASK 0x000000FFL
+#define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ13_MASK 0x0000FF00L
+//DIDT_SQ_EDC_OVERFLOW
+#define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0
+#define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1
+#define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L
+#define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL
+//DIDT_SQ_EDC_ROLLING_POWER_DELTA
+#define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0
+#define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL
+//DIDT_DB_CTRL0
+#define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
+#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x1
+#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x3
+#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
+#define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5
+#define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6
+#define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7
+#define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8
+#define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18
+#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19
+#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a
+#define DIDT_DB_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT 0x1b
+#define DIDT_DB_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT 0x1c
+#define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
+#define DIDT_DB_CTRL0__PHASE_OFFSET_MASK 0x00000006L
+#define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L
+#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
+#define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L
+#define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L
+#define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L
+#define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L
+#define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L
+#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L
+#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L
+#define DIDT_DB_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK 0x08000000L
+#define DIDT_DB_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK 0x10000000L
+//DIDT_DB_CTRL2
+#define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
+#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
+#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
+#define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
+#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
+#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
+//DIDT_DB_STALL_CTRL
+#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0
+#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6
+#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc
+#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12
+#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL
+#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L
+#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L
+#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L
+//DIDT_DB_TUNING_CTRL
+#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0
+#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
+#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL
+#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L
+//DIDT_DB_STALL_AUTO_RELEASE_CTRL
+#define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0
+#define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL
+//DIDT_DB_CTRL3
+#define DIDT_DB_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0
+#define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1
+#define DIDT_DB_CTRL3__THROTTLE_POLICY__SHIFT 0x2
+#define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
+#define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9
+#define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
+#define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16
+#define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17
+#define DIDT_DB_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18
+#define DIDT_DB_CTRL3__DIDT_STALL_SEL__SHIFT 0x19
+#define DIDT_DB_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b
+#define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c
+#define DIDT_DB_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L
+#define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L
+#define DIDT_DB_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL
+#define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
+#define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L
+#define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L
+#define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L
+#define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L
+#define DIDT_DB_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L
+#define DIDT_DB_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L
+#define DIDT_DB_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L
+#define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L
+//DIDT_DB_STALL_PATTERN_1_2
+#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0
+#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10
+#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL
+#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L
+//DIDT_DB_STALL_PATTERN_3_4
+#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0
+#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10
+#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL
+#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L
+//DIDT_DB_STALL_PATTERN_5_6
+#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0
+#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10
+#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL
+#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L
+//DIDT_DB_STALL_PATTERN_7
+#define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0
+#define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL
+//DIDT_DB_MPD_SCALE_FACTOR
+#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT 0x0
+#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT 0x4
+#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT 0x8
+#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT 0xc
+#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT 0x10
+#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT 0x14
+#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT 0x18
+#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT 0x1c
+#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK 0x0000000FL
+#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK 0x000000F0L
+#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK 0x00000F00L
+#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK 0x0000F000L
+#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK 0x000F0000L
+#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK 0x00F00000L
+#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK 0x0F000000L
+#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK 0xF0000000L
+//DIDT_DB_THROTTLE_CNTL0
+#define DIDT_DB_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN__SHIFT 0x0
+#define DIDT_DB_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT 0x1
+#define DIDT_DB_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT 0x2
+#define DIDT_DB_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT 0xd
+#define DIDT_DB_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN_MASK 0x00000001L
+#define DIDT_DB_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL_MASK 0x00000002L
+#define DIDT_DB_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK 0x00001FFCL
+#define DIDT_DB_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK 0x00FFE000L
+//DIDT_DB_THROTTLE_CNTL1
+#define DIDT_DB_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT 0x0
+#define DIDT_DB_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT 0x5
+#define DIDT_DB_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa
+#define DIDT_DB_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT 0xf
+#define DIDT_DB_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK 0x0000001FL
+#define DIDT_DB_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK 0x000003E0L
+#define DIDT_DB_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK 0x00007C00L
+#define DIDT_DB_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK 0x000F8000L
+//DIDT_DB_THROTTLE_CNTL_STATUS
+#define DIDT_DB_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE__SHIFT 0x0
+#define DIDT_DB_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE_MASK 0x00000003L
+//DIDT_DB_WEIGHT0_3
+#define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT 0x0
+#define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT 0x8
+#define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT 0x10
+#define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT 0x18
+#define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL
+#define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L
+#define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L
+#define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L
+//DIDT_DB_WEIGHT4_7
+#define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT 0x0
+#define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT 0x8
+#define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT 0x10
+#define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT 0x18
+#define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL
+#define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L
+#define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L
+#define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L
+//DIDT_DB_WEIGHT8_11
+#define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT 0x0
+#define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT 0x8
+#define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT 0x10
+#define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT 0x18
+#define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL
+#define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L
+#define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L
+#define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L
+//DIDT_DB_EDC_CTRL
+#define DIDT_DB_EDC_CTRL__EDC_EN__SHIFT 0x0
+#define DIDT_DB_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
+#define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
+#define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
+#define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
+#define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9
+#define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11
+#define DIDT_DB_EDC_CTRL__GC_EDC_EN__SHIFT 0x12
+#define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13
+#define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15
+#define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16
+#define DIDT_DB_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT 0x17
+#define DIDT_DB_EDC_CTRL__EDC_EN_MASK 0x00000001L
+#define DIDT_DB_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
+#define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
+#define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
+#define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
+#define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L
+#define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L
+#define DIDT_DB_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L
+#define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L
+#define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L
+#define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L
+#define DIDT_DB_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK 0x00800000L
+//DIDT_DB_THROTTLE_CTRL
+#define DIDT_DB_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT 0x0
+#define DIDT_DB_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x1
+#define DIDT_DB_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT 0x2
+#define DIDT_DB_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT 0x3
+#define DIDT_DB_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK 0x00000001L
+#define DIDT_DB_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000002L
+#define DIDT_DB_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK 0x00000004L
+#define DIDT_DB_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000008L
+//DIDT_DB_EDC_STALL_PATTERN_1_2
+#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0
+#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10
+#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL
+#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L
+//DIDT_DB_EDC_STALL_PATTERN_3_4
+#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0
+#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10
+#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL
+#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L
+//DIDT_DB_EDC_STALL_PATTERN_5_6
+#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0
+#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10
+#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL
+#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L
+//DIDT_DB_EDC_STALL_PATTERN_7
+#define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0
+#define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL
+//DIDT_DB_EDC_STATUS
+#define DIDT_DB_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0
+#define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1
+#define DIDT_DB_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L
+#define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL
+//DIDT_DB_EDC_STALL_DELAY_1
+#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0__SHIFT 0x0
+#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1__SHIFT 0x6
+#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB2__SHIFT 0xc
+#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB3__SHIFT 0x12
+#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0_MASK 0x0000003FL
+#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1_MASK 0x00000FC0L
+#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB2_MASK 0x0003F000L
+#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB3_MASK 0x00FC0000L
+//DIDT_DB_EDC_OVERFLOW
+#define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0
+#define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1
+#define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L
+#define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL
+//DIDT_DB_EDC_ROLLING_POWER_DELTA
+#define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0
+#define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL
+//DIDT_TD_CTRL0
+#define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
+#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x1
+#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x3
+#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
+#define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5
+#define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6
+#define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7
+#define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8
+#define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18
+#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19
+#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a
+#define DIDT_TD_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT 0x1b
+#define DIDT_TD_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT 0x1c
+#define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
+#define DIDT_TD_CTRL0__PHASE_OFFSET_MASK 0x00000006L
+#define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L
+#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
+#define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L
+#define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L
+#define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L
+#define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L
+#define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L
+#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L
+#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L
+#define DIDT_TD_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK 0x08000000L
+#define DIDT_TD_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK 0x10000000L
+//DIDT_TD_CTRL2
+#define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
+#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
+#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
+#define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
+#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
+#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
+//DIDT_TD_STALL_CTRL
+#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0
+#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6
+#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc
+#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12
+#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL
+#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L
+#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L
+#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L
+//DIDT_TD_TUNING_CTRL
+#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0
+#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
+#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL
+#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L
+//DIDT_TD_STALL_AUTO_RELEASE_CTRL
+#define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0
+#define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL
+//DIDT_TD_CTRL3
+#define DIDT_TD_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0
+#define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1
+#define DIDT_TD_CTRL3__THROTTLE_POLICY__SHIFT 0x2
+#define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
+#define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9
+#define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
+#define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16
+#define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17
+#define DIDT_TD_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18
+#define DIDT_TD_CTRL3__DIDT_STALL_SEL__SHIFT 0x19
+#define DIDT_TD_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b
+#define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c
+#define DIDT_TD_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L
+#define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L
+#define DIDT_TD_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL
+#define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
+#define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L
+#define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L
+#define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L
+#define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L
+#define DIDT_TD_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L
+#define DIDT_TD_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L
+#define DIDT_TD_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L
+#define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L
+//DIDT_TD_STALL_PATTERN_1_2
+#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0
+#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10
+#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL
+#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L
+//DIDT_TD_STALL_PATTERN_3_4
+#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0
+#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10
+#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL
+#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L
+//DIDT_TD_STALL_PATTERN_5_6
+#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0
+#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10
+#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL
+#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L
+//DIDT_TD_STALL_PATTERN_7
+#define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0
+#define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL
+//DIDT_TD_MPD_SCALE_FACTOR
+#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT 0x0
+#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT 0x4
+#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT 0x8
+#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT 0xc
+#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT 0x10
+#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT 0x14
+#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT 0x18
+#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT 0x1c
+#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK 0x0000000FL
+#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK 0x000000F0L
+#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK 0x00000F00L
+#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK 0x0000F000L
+#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK 0x000F0000L
+#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK 0x00F00000L
+#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK 0x0F000000L
+#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK 0xF0000000L
+//DIDT_TD_THROTTLE_CNTL0
+#define DIDT_TD_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN__SHIFT 0x0
+#define DIDT_TD_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT 0x1
+#define DIDT_TD_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT 0x2
+#define DIDT_TD_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT 0xd
+#define DIDT_TD_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN_MASK 0x00000001L
+#define DIDT_TD_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL_MASK 0x00000002L
+#define DIDT_TD_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK 0x00001FFCL
+#define DIDT_TD_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK 0x00FFE000L
+//DIDT_TD_THROTTLE_CNTL1
+#define DIDT_TD_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT 0x0
+#define DIDT_TD_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT 0x5
+#define DIDT_TD_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa
+#define DIDT_TD_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT 0xf
+#define DIDT_TD_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK 0x0000001FL
+#define DIDT_TD_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK 0x000003E0L
+#define DIDT_TD_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK 0x00007C00L
+#define DIDT_TD_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK 0x000F8000L
+//DIDT_TD_THROTTLE_CNTL_STATUS
+#define DIDT_TD_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE__SHIFT 0x0
+#define DIDT_TD_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE_MASK 0x00000003L
+//DIDT_TD_WEIGHT0_3
+#define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT 0x0
+#define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT 0x8
+#define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT 0x10
+#define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT 0x18
+#define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL
+#define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L
+#define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L
+#define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L
+//DIDT_TD_WEIGHT4_7
+#define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT 0x0
+#define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT 0x8
+#define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT 0x10
+#define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT 0x18
+#define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL
+#define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L
+#define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L
+#define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L
+//DIDT_TD_WEIGHT8_11
+#define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT 0x0
+#define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT 0x8
+#define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT 0x10
+#define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT 0x18
+#define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL
+#define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L
+#define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L
+#define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L
+//DIDT_TD_EDC_CTRL
+#define DIDT_TD_EDC_CTRL__EDC_EN__SHIFT 0x0
+#define DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
+#define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
+#define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
+#define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
+#define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9
+#define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11
+#define DIDT_TD_EDC_CTRL__GC_EDC_EN__SHIFT 0x12
+#define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13
+#define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15
+#define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16
+#define DIDT_TD_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT 0x17
+#define DIDT_TD_EDC_CTRL__EDC_EN_MASK 0x00000001L
+#define DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
+#define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
+#define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
+#define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
+#define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L
+#define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L
+#define DIDT_TD_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L
+#define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L
+#define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L
+#define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L
+#define DIDT_TD_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK 0x00800000L
+//DIDT_TD_THROTTLE_CTRL
+#define DIDT_TD_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT 0x0
+#define DIDT_TD_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x1
+#define DIDT_TD_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT 0x2
+#define DIDT_TD_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT 0x3
+#define DIDT_TD_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK 0x00000001L
+#define DIDT_TD_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000002L
+#define DIDT_TD_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK 0x00000004L
+#define DIDT_TD_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000008L
+//DIDT_TD_EDC_STALL_PATTERN_1_2
+#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0
+#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10
+#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL
+#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L
+//DIDT_TD_EDC_STALL_PATTERN_3_4
+#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0
+#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10
+#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL
+#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L
+//DIDT_TD_EDC_STALL_PATTERN_5_6
+#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0
+#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10
+#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL
+#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L
+//DIDT_TD_EDC_STALL_PATTERN_7
+#define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0
+#define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL
+//DIDT_TD_EDC_STATUS
+#define DIDT_TD_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0
+#define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1
+#define DIDT_TD_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L
+#define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL
+//DIDT_TD_EDC_STALL_DELAY_1
+#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0__SHIFT 0x0
+#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1__SHIFT 0x8
+#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2__SHIFT 0x10
+#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3__SHIFT 0x18
+#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0_MASK 0x000000FFL
+#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1_MASK 0x0000FF00L
+#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2_MASK 0x00FF0000L
+#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3_MASK 0xFF000000L
+//DIDT_TD_EDC_STALL_DELAY_2
+#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4__SHIFT 0x0
+#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5__SHIFT 0x8
+#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6__SHIFT 0x10
+#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7__SHIFT 0x18
+#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4_MASK 0x000000FFL
+#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5_MASK 0x0000FF00L
+#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6_MASK 0x00FF0000L
+#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7_MASK 0xFF000000L
+//DIDT_TD_EDC_STALL_DELAY_3
+#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8__SHIFT 0x0
+#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9__SHIFT 0x8
+#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD10__SHIFT 0x10
+#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD11__SHIFT 0x18
+#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8_MASK 0x000000FFL
+#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9_MASK 0x0000FF00L
+#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD10_MASK 0x00FF0000L
+#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD11_MASK 0xFF000000L
+//DIDT_TD_EDC_STALL_DELAY_4
+#define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD12__SHIFT 0x0
+#define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD13__SHIFT 0x8
+#define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD12_MASK 0x000000FFL
+#define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD13_MASK 0x0000FF00L
+//DIDT_TD_EDC_OVERFLOW
+#define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0
+#define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1
+#define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L
+#define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL
+//DIDT_TD_EDC_ROLLING_POWER_DELTA
+#define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0
+#define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL
+//DIDT_TCP_CTRL0
+#define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
+#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x1
+#define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT 0x3
+#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
+#define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5
+#define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6
+#define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7
+#define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8
+#define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18
+#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19
+#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a
+#define DIDT_TCP_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT 0x1b
+#define DIDT_TCP_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT 0x1c
+#define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
+#define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK 0x00000006L
+#define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L
+#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
+#define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L
+#define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L
+#define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L
+#define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L
+#define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L
+#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L
+#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L
+#define DIDT_TCP_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK 0x08000000L
+#define DIDT_TCP_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK 0x10000000L
+//DIDT_TCP_CTRL2
+#define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
+#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
+#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
+#define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
+#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
+#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
+//DIDT_TCP_STALL_CTRL
+#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0
+#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6
+#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc
+#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12
+#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL
+#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L
+#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L
+#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L
+//DIDT_TCP_TUNING_CTRL
+#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0
+#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
+#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL
+#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L
+//DIDT_TCP_STALL_AUTO_RELEASE_CTRL
+#define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0
+#define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL
+//DIDT_TCP_CTRL3
+#define DIDT_TCP_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0
+#define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1
+#define DIDT_TCP_CTRL3__THROTTLE_POLICY__SHIFT 0x2
+#define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
+#define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9
+#define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
+#define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16
+#define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17
+#define DIDT_TCP_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18
+#define DIDT_TCP_CTRL3__DIDT_STALL_SEL__SHIFT 0x19
+#define DIDT_TCP_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b
+#define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c
+#define DIDT_TCP_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L
+#define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L
+#define DIDT_TCP_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL
+#define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
+#define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L
+#define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L
+#define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L
+#define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L
+#define DIDT_TCP_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L
+#define DIDT_TCP_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L
+#define DIDT_TCP_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L
+#define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L
+//DIDT_TCP_STALL_PATTERN_1_2
+#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0
+#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10
+#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL
+#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L
+//DIDT_TCP_STALL_PATTERN_3_4
+#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0
+#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10
+#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL
+#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L
+//DIDT_TCP_STALL_PATTERN_5_6
+#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0
+#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10
+#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL
+#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L
+//DIDT_TCP_STALL_PATTERN_7
+#define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0
+#define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL
+//DIDT_TCP_MPD_SCALE_FACTOR
+#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT 0x0
+#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT 0x4
+#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT 0x8
+#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT 0xc
+#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT 0x10
+#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT 0x14
+#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT 0x18
+#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT 0x1c
+#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK 0x0000000FL
+#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK 0x000000F0L
+#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK 0x00000F00L
+#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK 0x0000F000L
+#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK 0x000F0000L
+#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK 0x00F00000L
+#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK 0x0F000000L
+#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK 0xF0000000L
+//DIDT_TCP_THROTTLE_CNTL0
+#define DIDT_TCP_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN__SHIFT 0x0
+#define DIDT_TCP_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT 0x1
+#define DIDT_TCP_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT 0x2
+#define DIDT_TCP_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT 0xd
+#define DIDT_TCP_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN_MASK 0x00000001L
+#define DIDT_TCP_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL_MASK 0x00000002L
+#define DIDT_TCP_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK 0x00001FFCL
+#define DIDT_TCP_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK 0x00FFE000L
+//DIDT_TCP_THROTTLE_CNTL1
+#define DIDT_TCP_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT 0x0
+#define DIDT_TCP_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT 0x5
+#define DIDT_TCP_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa
+#define DIDT_TCP_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT 0xf
+#define DIDT_TCP_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK 0x0000001FL
+#define DIDT_TCP_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK 0x000003E0L
+#define DIDT_TCP_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK 0x00007C00L
+#define DIDT_TCP_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK 0x000F8000L
+//DIDT_TCP_THROTTLE_CNTL_STATUS
+#define DIDT_TCP_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE__SHIFT 0x0
+#define DIDT_TCP_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE_MASK 0x00000003L
+//DIDT_TCP_WEIGHT0_3
+#define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT 0x0
+#define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT 0x8
+#define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT 0x10
+#define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT 0x18
+#define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL
+#define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L
+#define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L
+#define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L
+//DIDT_TCP_WEIGHT4_7
+#define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT 0x0
+#define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT 0x8
+#define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT 0x10
+#define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT 0x18
+#define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL
+#define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L
+#define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L
+#define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L
+//DIDT_TCP_WEIGHT8_11
+#define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT 0x0
+#define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT 0x8
+#define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT 0x10
+#define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT 0x18
+#define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL
+#define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L
+#define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L
+#define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L
+//DIDT_TCP_EDC_CTRL
+#define DIDT_TCP_EDC_CTRL__EDC_EN__SHIFT 0x0
+#define DIDT_TCP_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
+#define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
+#define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
+#define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
+#define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9
+#define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11
+#define DIDT_TCP_EDC_CTRL__GC_EDC_EN__SHIFT 0x12
+#define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13
+#define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15
+#define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16
+#define DIDT_TCP_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT 0x17
+#define DIDT_TCP_EDC_CTRL__EDC_EN_MASK 0x00000001L
+#define DIDT_TCP_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
+#define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
+#define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
+#define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
+#define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L
+#define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L
+#define DIDT_TCP_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L
+#define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L
+#define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L
+#define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L
+#define DIDT_TCP_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK 0x00800000L
+//DIDT_TCP_THROTTLE_CTRL
+#define DIDT_TCP_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT 0x0
+#define DIDT_TCP_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x1
+#define DIDT_TCP_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT 0x2
+#define DIDT_TCP_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT 0x3
+#define DIDT_TCP_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK 0x00000001L
+#define DIDT_TCP_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000002L
+#define DIDT_TCP_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK 0x00000004L
+#define DIDT_TCP_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000008L
+//DIDT_TCP_EDC_STALL_PATTERN_1_2
+#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0
+#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10
+#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL
+#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L
+//DIDT_TCP_EDC_STALL_PATTERN_3_4
+#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0
+#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10
+#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL
+#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L
+//DIDT_TCP_EDC_STALL_PATTERN_5_6
+#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0
+#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10
+#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL
+#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L
+//DIDT_TCP_EDC_STALL_PATTERN_7
+#define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0
+#define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL
+//DIDT_TCP_EDC_STATUS
+#define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0
+#define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1
+#define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L
+#define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL
+//DIDT_TCP_EDC_STALL_DELAY_1
+#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0__SHIFT 0x0
+#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1__SHIFT 0x8
+#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2__SHIFT 0x10
+#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3__SHIFT 0x18
+#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0_MASK 0x000000FFL
+#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1_MASK 0x0000FF00L
+#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2_MASK 0x00FF0000L
+#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3_MASK 0xFF000000L
+//DIDT_TCP_EDC_STALL_DELAY_2
+#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4__SHIFT 0x0
+#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5__SHIFT 0x8
+#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6__SHIFT 0x10
+#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7__SHIFT 0x18
+#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4_MASK 0x000000FFL
+#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5_MASK 0x0000FF00L
+#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6_MASK 0x00FF0000L
+#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7_MASK 0xFF000000L
+//DIDT_TCP_EDC_STALL_DELAY_3
+#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8__SHIFT 0x0
+#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9__SHIFT 0x8
+#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP10__SHIFT 0x10
+#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP11__SHIFT 0x18
+#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8_MASK 0x000000FFL
+#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9_MASK 0x0000FF00L
+#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP10_MASK 0x00FF0000L
+#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP11_MASK 0xFF000000L
+//DIDT_TCP_EDC_STALL_DELAY_4
+#define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP12__SHIFT 0x0
+#define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP13__SHIFT 0x8
+#define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP12_MASK 0x000000FFL
+#define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP13_MASK 0x0000FF00L
+//DIDT_TCP_EDC_OVERFLOW
+#define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0
+#define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1
+#define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L
+#define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL
+//DIDT_TCP_EDC_ROLLING_POWER_DELTA
+#define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0
+#define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL
+//DIDT_SQ_STALL_EVENT_COUNTER
+#define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0
+#define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL
+//DIDT_DB_STALL_EVENT_COUNTER
+#define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0
+#define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL
+//DIDT_TD_STALL_EVENT_COUNTER
+#define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0
+#define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL
+//DIDT_TCP_STALL_EVENT_COUNTER
+#define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0
+#define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL
+//DIDT_DBR_STALL_EVENT_COUNTER
+#define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0
+#define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL
+//DIDT_SQ_EDC_PCC_PERF_COUNTER
+#define DIDT_SQ_EDC_PCC_PERF_COUNTER__PERF_COUNTER__SHIFT 0x0
+#define DIDT_SQ_EDC_PCC_PERF_COUNTER__PERF_COUNTER_MASK 0xFFFFFFFFL
+//DIDT_TD_EDC_PCC_PERF_COUNTER
+#define DIDT_TD_EDC_PCC_PERF_COUNTER__PERF_COUNTER__SHIFT 0x0
+#define DIDT_TD_EDC_PCC_PERF_COUNTER__PERF_COUNTER_MASK 0xFFFFFFFFL
+//DIDT_TCP_EDC_PCC_PERF_COUNTER
+#define DIDT_TCP_EDC_PCC_PERF_COUNTER__PERF_COUNTER__SHIFT 0x0
+#define DIDT_TCP_EDC_PCC_PERF_COUNTER__PERF_COUNTER_MASK 0xFFFFFFFFL
+//DIDT_DB_EDC_PCC_PERF_COUNTER
+#define DIDT_DB_EDC_PCC_PERF_COUNTER__PERF_COUNTER__SHIFT 0x0
+#define DIDT_DB_EDC_PCC_PERF_COUNTER__PERF_COUNTER_MASK 0xFFFFFFFFL
+//DIDT_DBR_EDC_PCC_PERF_COUNTER
+#define DIDT_DBR_EDC_PCC_PERF_COUNTER__PERF_COUNTER__SHIFT 0x0
+#define DIDT_DBR_EDC_PCC_PERF_COUNTER__PERF_COUNTER_MASK 0xFFFFFFFFL
+//DIDT_SQ_CTRL1
+#define DIDT_SQ_CTRL1__MIN_POWER__SHIFT 0x0
+#define DIDT_SQ_CTRL1__MAX_POWER__SHIFT 0x10
+#define DIDT_SQ_CTRL1__MIN_POWER_MASK 0x0000FFFFL
+#define DIDT_SQ_CTRL1__MAX_POWER_MASK 0xFFFF0000L
+//DIDT_SQ_EDC_THRESHOLD
+#define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
+#define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
+//DIDT_DB_CTRL1
+#define DIDT_DB_CTRL1__MIN_POWER__SHIFT 0x0
+#define DIDT_DB_CTRL1__MAX_POWER__SHIFT 0x10
+#define DIDT_DB_CTRL1__MIN_POWER_MASK 0x0000FFFFL
+#define DIDT_DB_CTRL1__MAX_POWER_MASK 0xFFFF0000L
+//DIDT_DB_EDC_THRESHOLD
+#define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
+#define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
+//DIDT_TD_CTRL1
+#define DIDT_TD_CTRL1__MIN_POWER__SHIFT 0x0
+#define DIDT_TD_CTRL1__MAX_POWER__SHIFT 0x10
+#define DIDT_TD_CTRL1__MIN_POWER_MASK 0x0000FFFFL
+#define DIDT_TD_CTRL1__MAX_POWER_MASK 0xFFFF0000L
+//DIDT_TD_EDC_THRESHOLD
+#define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
+#define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
+//DIDT_TCP_CTRL1
+#define DIDT_TCP_CTRL1__MIN_POWER__SHIFT 0x0
+#define DIDT_TCP_CTRL1__MAX_POWER__SHIFT 0x10
+#define DIDT_TCP_CTRL1__MIN_POWER_MASK 0x0000FFFFL
+#define DIDT_TCP_CTRL1__MAX_POWER_MASK 0xFFFF0000L
+//DIDT_TCP_EDC_THRESHOLD
+#define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
+#define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
+
+
+// addressBlock: gc_cpdec
+//CP_CPC_STATUS
+#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0
+#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1
+#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2
+#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3
+#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4
+#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5
+#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6
+#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7
+#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa
+#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb
+#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc
+#define CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT 0xd
+#define CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT 0xe
+#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d
+#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e
+#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f
+#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x00000001L
+#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x00000002L
+#define CP_CPC_STATUS__DC0_BUSY_MASK 0x00000004L
+#define CP_CPC_STATUS__DC1_BUSY_MASK 0x00000008L
+#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x00000010L
+#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x00000020L
+#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x00000040L
+#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x00000080L
+#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x00000400L
+#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x00000800L
+#define CP_CPC_STATUS__QU_BUSY_MASK 0x00001000L
+#define CP_CPC_STATUS__UTCL2IU_BUSY_MASK 0x00002000L
+#define CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK 0x00004000L
+#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000L
+#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000L
+#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000L
+//CP_CPC_BUSY_STAT
+#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0
+#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1
+#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2
+#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3
+#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4
+#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5
+#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6
+#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7
+#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8
+#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9
+#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa
+#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb
+#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc
+#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd
+#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10
+#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11
+#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12
+#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13
+#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14
+#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15
+#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16
+#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17
+#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18
+#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19
+#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a
+#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b
+#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c
+#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d
+#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x00000001L
+#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x00000002L
+#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x00000004L
+#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x00000008L
+#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x00000010L
+#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x00000020L
+#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x00000040L
+#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x00000080L
+#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x00000100L
+#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x00000200L
+#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x00000400L
+#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x00000800L
+#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x00001000L
+#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x00002000L
+#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x00010000L
+#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x00020000L
+#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x00040000L
+#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x00080000L
+#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x00100000L
+#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x00200000L
+#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x00400000L
+#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x00800000L
+#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x01000000L
+#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x02000000L
+#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x04000000L
+#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x08000000L
+#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000L
+#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000L
+//CP_CPC_STALLED_STAT1
+#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3
+#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4
+#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6
+#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd
+#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15
+#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x16
+#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x17
+#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT 0x18
+#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x00000008L
+#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x00000010L
+#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x00000040L
+#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x00000100L
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x00000200L
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x00000400L
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x00002000L
+#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x00010000L
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x00020000L
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x00040000L
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x00200000L
+#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00400000L
+#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00800000L
+#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK 0x01000000L
+//CP_CPF_STATUS
+#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0
+#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1
+#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4
+#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5
+#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6
+#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7
+#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8
+#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9
+#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa
+#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb
+#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc
+#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd
+#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe
+#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf
+#define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10
+#define CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT 0x11
+#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a
+#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b
+#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c
+#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e
+#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f
+#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x00000001L
+#define CP_CPF_STATUS__CSF_BUSY_MASK 0x00000002L
+#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x00000010L
+#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x00000020L
+#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x00000040L
+#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x00000080L
+#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x00000100L
+#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x00000200L
+#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x00000400L
+#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x00000800L
+#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x00001000L
+#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x00002000L
+#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x00004000L
+#define CP_CPF_STATUS__HQD_BUSY_MASK 0x00008000L
+#define CP_CPF_STATUS__PRT_BUSY_MASK 0x00010000L
+#define CP_CPF_STATUS__UTCL2IU_BUSY_MASK 0x00020000L
+#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x04000000L
+#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x08000000L
+#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000L
+#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000L
+#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000L
+//CP_CPF_BUSY_STAT
+#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
+#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1
+#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2
+#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3
+#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4
+#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5
+#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6
+#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7
+#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8
+#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9
+#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb
+#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc
+#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd
+#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe
+#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf
+#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10
+#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11
+#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12
+#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13
+#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14
+#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15
+#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16
+#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17
+#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18
+#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19
+#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a
+#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b
+#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c
+#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d
+#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e
+#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f
+#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L
+#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x00000002L
+#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x00000004L
+#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000008L
+#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x00000010L
+#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x00000020L
+#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x00000040L
+#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x00000080L
+#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x00000100L
+#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x00000200L
+#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x00000800L
+#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x00001000L
+#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x00002000L
+#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x00004000L
+#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x00008000L
+#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x00010000L
+#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x00020000L
+#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x00040000L
+#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x00080000L
+#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x00100000L
+#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x00200000L
+#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x00400000L
+#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x00800000L
+#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x01000000L
+#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x02000000L
+#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x04000000L
+#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x08000000L
+#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000L
+#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000L
+#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000L
+#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000L
+//CP_CPF_STALLED_STAT1
+#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0
+#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1
+#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2
+#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3
+#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5
+#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6
+#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x7
+#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x8
+#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT 0x9
+#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT 0xa
+#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT 0xb
+#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x00000001L
+#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x00000002L
+#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x00000004L
+#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x00000008L
+#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x00000020L
+#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x00000040L
+#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00000080L
+#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00000100L
+#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK 0x00000200L
+#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK 0x00000400L
+#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK 0x00000800L
+//CP_CPC_GRBM_FREE_COUNT
+#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
+#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL
+//CP_CPC_PRIV_VIOLATION_ADDR
+#define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR__SHIFT 0x0
+#define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR_MASK 0x0000FFFFL
+//CP_MEC_CNTL
+#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4
+#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10
+#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11
+#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12
+#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13
+#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14
+#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15
+#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c
+#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d
+#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e
+#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f
+#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x00000010L
+#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x00010000L
+#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x00020000L
+#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x00040000L
+#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x00080000L
+#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x00100000L
+#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x00200000L
+#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000L
+#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000L
+#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000L
+#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000L
+//CP_MEC_ME1_HEADER_DUMP
+#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
+#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL
+//CP_MEC_ME2_HEADER_DUMP
+#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
+#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL
+//CP_CPC_SCRATCH_INDEX
+#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
+#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL
+//CP_CPC_SCRATCH_DATA
+#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
+#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL
+//CP_CPF_GRBM_FREE_COUNT
+#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
+#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x00000007L
+//CP_CPC_HALT_HYST_COUNT
+#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0
+#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0x0000000FL
+//CP_CE_COMPARE_COUNT
+#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0
+#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xFFFFFFFFL
+//CP_CE_DE_COUNT
+#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
+#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL
+//CP_DE_CE_COUNT
+#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0
+#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL
+//CP_DE_LAST_INVAL_COUNT
+#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0
+#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xFFFFFFFFL
+//CP_DE_DE_COUNT
+#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
+#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL
+//CP_STALLED_STAT3
+#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
+#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1
+#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2
+#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3
+#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4
+#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5
+#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6
+#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7
+#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa
+#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb
+#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc
+#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd
+#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe
+#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf
+#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10
+#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11
+#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT 0x12
+#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x13
+#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT 0x14
+#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L
+#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x00000002L
+#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x00000004L
+#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x00000008L
+#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x00000010L
+#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x00000020L
+#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x00000040L
+#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x00000080L
+#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x00000400L
+#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x00000800L
+#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x00001000L
+#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x00002000L
+#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x00004000L
+#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x00008000L
+#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x00010000L
+#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00020000L
+#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK 0x00040000L
+#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK 0x00080000L
+#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK 0x00100000L
+//CP_STALLED_STAT1
+#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0
+#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2
+#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4
+#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa
+#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb
+#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc
+#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd
+#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe
+#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c
+#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d
+#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x00000001L
+#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x00000004L
+#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x00000010L
+#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x00000400L
+#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x00000800L
+#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x00001000L
+#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00002000L
+#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x00004000L
+#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x00008000L
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x00800000L
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x01000000L
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x02000000L
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x04000000L
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x08000000L
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000L
+#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000L
+//CP_STALLED_STAT2
+#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
+#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1
+#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2
+#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4
+#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5
+#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8
+#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9
+#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa
+#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb
+#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc
+#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd
+#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe
+#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf
+#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10
+#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11
+#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12
+#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13
+#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14
+#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15
+#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16
+#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17
+#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18
+#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19
+#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a
+#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b
+#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c
+#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d
+#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e
+#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f
+#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L
+#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x00000002L
+#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x00000004L
+#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x00000010L
+#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x00000020L
+#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x00000100L
+#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x00000200L
+#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x00000400L
+#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x00000800L
+#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x00001000L
+#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x00002000L
+#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x00004000L
+#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x00008000L
+#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00010000L
+#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00020000L
+#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x00040000L
+#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x00080000L
+#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00100000L
+#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x00200000L
+#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x00400000L
+#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x00800000L
+#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x01000000L
+#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x02000000L
+#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x04000000L
+#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x08000000L
+#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000L
+#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000L
+#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000L
+#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000L
+//CP_BUSY_STAT
+#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
+#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6
+#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7
+#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8
+#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9
+#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa
+#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc
+#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd
+#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe
+#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf
+#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11
+#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12
+#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13
+#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14
+#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15
+#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16
+#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L
+#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x00000040L
+#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x00000080L
+#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x00000100L
+#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x00000200L
+#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x00000400L
+#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x00001000L
+#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x00002000L
+#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x00004000L
+#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x00008000L
+#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x00020000L
+#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x00040000L
+#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x00080000L
+#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x00100000L
+#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x00200000L
+#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x00400000L
+//CP_STAT
+#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9
+#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa
+#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb
+#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc
+#define CP_STAT__DC_BUSY__SHIFT 0xd
+#define CP_STAT__UTCL2IU_BUSY__SHIFT 0xe
+#define CP_STAT__PFP_BUSY__SHIFT 0xf
+#define CP_STAT__MEQ_BUSY__SHIFT 0x10
+#define CP_STAT__ME_BUSY__SHIFT 0x11
+#define CP_STAT__QUERY_BUSY__SHIFT 0x12
+#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13
+#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14
+#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15
+#define CP_STAT__DMA_BUSY__SHIFT 0x16
+#define CP_STAT__RCIU_BUSY__SHIFT 0x17
+#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18
+#define CP_STAT__CE_BUSY__SHIFT 0x1a
+#define CP_STAT__TCIU_BUSY__SHIFT 0x1b
+#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c
+#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d
+#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e
+#define CP_STAT__CP_BUSY__SHIFT 0x1f
+#define CP_STAT__ROQ_RING_BUSY_MASK 0x00000200L
+#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x00000400L
+#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x00000800L
+#define CP_STAT__ROQ_STATE_BUSY_MASK 0x00001000L
+#define CP_STAT__DC_BUSY_MASK 0x00002000L
+#define CP_STAT__UTCL2IU_BUSY_MASK 0x00004000L
+#define CP_STAT__PFP_BUSY_MASK 0x00008000L
+#define CP_STAT__MEQ_BUSY_MASK 0x00010000L
+#define CP_STAT__ME_BUSY_MASK 0x00020000L
+#define CP_STAT__QUERY_BUSY_MASK 0x00040000L
+#define CP_STAT__SEMAPHORE_BUSY_MASK 0x00080000L
+#define CP_STAT__INTERRUPT_BUSY_MASK 0x00100000L
+#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x00200000L
+#define CP_STAT__DMA_BUSY_MASK 0x00400000L
+#define CP_STAT__RCIU_BUSY_MASK 0x00800000L
+#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x01000000L
+#define CP_STAT__CE_BUSY_MASK 0x04000000L
+#define CP_STAT__TCIU_BUSY_MASK 0x08000000L
+#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000L
+#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000L
+#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000L
+#define CP_STAT__CP_BUSY_MASK 0x80000000L
+//CP_ME_HEADER_DUMP
+#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0
+#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xFFFFFFFFL
+//CP_PFP_HEADER_DUMP
+#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0
+#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xFFFFFFFFL
+//CP_GRBM_FREE_COUNT
+#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
+#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8
+#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10
+#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL
+#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x00003F00L
+#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x003F0000L
+//CP_CE_HEADER_DUMP
+#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0
+#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xFFFFFFFFL
+//CP_PFP_INSTR_PNTR
+#define CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
+#define CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
+//CP_ME_INSTR_PNTR
+#define CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
+#define CP_ME_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
+//CP_CE_INSTR_PNTR
+#define CP_CE_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
+#define CP_CE_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
+//CP_MEC1_INSTR_PNTR
+#define CP_MEC1_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
+#define CP_MEC1_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
+//CP_MEC2_INSTR_PNTR
+#define CP_MEC2_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
+#define CP_MEC2_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
+//CP_CSF_STAT
+#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8
+#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x0001FF00L
+//CP_ME_CNTL
+#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4
+#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6
+#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8
+#define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10
+#define CP_ME_CNTL__CE_PIPE1_RESET__SHIFT 0x11
+#define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12
+#define CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT 0x13
+#define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14
+#define CP_ME_CNTL__ME_PIPE1_RESET__SHIFT 0x15
+#define CP_ME_CNTL__CE_HALT__SHIFT 0x18
+#define CP_ME_CNTL__CE_STEP__SHIFT 0x19
+#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a
+#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b
+#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c
+#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d
+#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x00000010L
+#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x00000040L
+#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x00000100L
+#define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x00010000L
+#define CP_ME_CNTL__CE_PIPE1_RESET_MASK 0x00020000L
+#define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x00040000L
+#define CP_ME_CNTL__PFP_PIPE1_RESET_MASK 0x00080000L
+#define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x00100000L
+#define CP_ME_CNTL__ME_PIPE1_RESET_MASK 0x00200000L
+#define CP_ME_CNTL__CE_HALT_MASK 0x01000000L
+#define CP_ME_CNTL__CE_STEP_MASK 0x02000000L
+#define CP_ME_CNTL__PFP_HALT_MASK 0x04000000L
+#define CP_ME_CNTL__PFP_STEP_MASK 0x08000000L
+#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L
+#define CP_ME_CNTL__ME_STEP_MASK 0x20000000L
+//CP_CNTX_STAT
+#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0
+#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8
+#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14
+#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c
+#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0x000000FFL
+#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x00000700L
+#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0x0FF00000L
+#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000L
+//CP_ME_PREEMPTION
+#define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0
+#define CP_ME_PREEMPTION__OBSOLETE_MASK 0x00000001L
+//CP_ROQ_THRESHOLDS
+#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0
+#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8
+#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0x000000FFL
+#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0x0000FF00L
+//CP_MEQ_STQ_THRESHOLD
+#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0
+#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0x000000FFL
+//CP_RB2_RPTR
+#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0
+#define CP_RB2_RPTR__RB_RPTR_MASK 0x000FFFFFL
+//CP_RB1_RPTR
+#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0
+#define CP_RB1_RPTR__RB_RPTR_MASK 0x000FFFFFL
+//CP_RB0_RPTR
+#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0
+#define CP_RB0_RPTR__RB_RPTR_MASK 0x000FFFFFL
+//CP_RB_RPTR
+#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0
+#define CP_RB_RPTR__RB_RPTR_MASK 0x000FFFFFL
+//CP_RB_WPTR_DELAY
+#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0
+#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c
+#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0FFFFFFFL
+#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xF0000000L
+//CP_RB_WPTR_POLL_CNTL
+#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0
+#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0x0000FFFFL
+#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//CP_ROQ1_THRESHOLDS
+#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0
+#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8
+#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10
+#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18
+#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0x000000FFL
+#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0x0000FF00L
+#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0x00FF0000L
+#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xFF000000L
+//CP_ROQ2_THRESHOLDS
+#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0
+#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8
+#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10
+#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18
+#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0x000000FFL
+#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0x0000FF00L
+#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x00FF0000L
+#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xFF000000L
+//CP_STQ_THRESHOLDS
+#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0
+#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8
+#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10
+#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0x000000FFL
+#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0x0000FF00L
+#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0x00FF0000L
+//CP_QUEUE_THRESHOLDS
+#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0
+#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8
+#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x0000003FL
+#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x00003F00L
+//CP_MEQ_THRESHOLDS
+#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0
+#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8
+#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0x000000FFL
+#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0x0000FF00L
+//CP_ROQ_AVAIL
+#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0
+#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10
+#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x000007FFL
+#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x07FF0000L
+//CP_STQ_AVAIL
+#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0
+#define CP_STQ_AVAIL__STQ_CNT_MASK 0x000001FFL
+//CP_ROQ2_AVAIL
+#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0
+#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x000007FFL
+//CP_MEQ_AVAIL
+#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0
+#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x000003FFL
+//CP_CMD_INDEX
+#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0
+#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc
+#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10
+#define CP_CMD_INDEX__CMD_INDEX_MASK 0x000007FFL
+#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x00003000L
+#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00070000L
+//CP_CMD_DATA
+#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0
+#define CP_CMD_DATA__CMD_DATA_MASK 0xFFFFFFFFL
+//CP_ROQ_RB_STAT
+#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0
+#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10
+#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x000003FFL
+#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x03FF0000L
+//CP_ROQ_IB1_STAT
+#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0
+#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10
+#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x000003FFL
+#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x03FF0000L
+//CP_ROQ_IB2_STAT
+#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0
+#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10
+#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x000003FFL
+#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x03FF0000L
+//CP_STQ_STAT
+#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0
+#define CP_STQ_STAT__STQ_RPTR_MASK 0x000003FFL
+//CP_STQ_WR_STAT
+#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0
+#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x000003FFL
+//CP_MEQ_STAT
+#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0
+#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10
+#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003FFL
+#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03FF0000L
+//CP_CEQ1_AVAIL
+#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0
+#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10
+#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x000007FFL
+#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x07FF0000L
+//CP_CEQ2_AVAIL
+#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0
+#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x000007FFL
+//CP_CE_ROQ_RB_STAT
+#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0
+#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10
+#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x000003FFL
+#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x03FF0000L
+//CP_CE_ROQ_IB1_STAT
+#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0
+#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10
+#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x000003FFL
+#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x03FF0000L
+//CP_CE_ROQ_IB2_STAT
+#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0
+#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10
+#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x000003FFL
+#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x03FF0000L
+#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16
+#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
+#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x00400000L
+#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L
+//CP_PRIV_VIOLATION_ADDR
+#define CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR__SHIFT 0x0
+#define CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR_MASK 0x0000FFFFL
+
+
+// addressBlock: gc_cppdec
+//CP_EOPQ_WAIT_TIME
+#define CP_EOPQ_WAIT_TIME__WAIT_TIME__SHIFT 0x0
+#define CP_EOPQ_WAIT_TIME__SCALE_COUNT__SHIFT 0xa
+#define CP_EOPQ_WAIT_TIME__WAIT_TIME_MASK 0x000003FFL
+#define CP_EOPQ_WAIT_TIME__SCALE_COUNT_MASK 0x0003FC00L
+//CP_CPC_MGCG_SYNC_CNTL
+#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0
+#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8
+#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0x000000FFL
+#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0x0000FF00L
+//CPC_INT_INFO
+#define CPC_INT_INFO__ADDR_HI__SHIFT 0x0
+#define CPC_INT_INFO__TYPE__SHIFT 0x10
+#define CPC_INT_INFO__VMID__SHIFT 0x14
+#define CPC_INT_INFO__QUEUE_ID__SHIFT 0x1c
+#define CPC_INT_INFO__ADDR_HI_MASK 0x0000FFFFL
+#define CPC_INT_INFO__TYPE_MASK 0x00010000L
+#define CPC_INT_INFO__VMID_MASK 0x00F00000L
+#define CPC_INT_INFO__QUEUE_ID_MASK 0x70000000L
+//CP_VIRT_STATUS
+#define CP_VIRT_STATUS__VIRT_STATUS__SHIFT 0x0
+#define CP_VIRT_STATUS__VIRT_STATUS_MASK 0xFFFFFFFFL
+//CPC_INT_ADDR
+#define CPC_INT_ADDR__ADDR__SHIFT 0x0
+#define CPC_INT_ADDR__ADDR_MASK 0xFFFFFFFFL
+//CPC_INT_PASID
+#define CPC_INT_PASID__PASID__SHIFT 0x0
+#define CPC_INT_PASID__PASID_MASK 0x0000FFFFL
+//CP_GFX_ERROR
+#define CP_GFX_ERROR__EDC_ERROR_ID__SHIFT 0x0
+#define CP_GFX_ERROR__SUA_ERROR__SHIFT 0x4
+#define CP_GFX_ERROR__RSVD1_ERROR__SHIFT 0x5
+#define CP_GFX_ERROR__RSVD2_ERROR__SHIFT 0x6
+#define CP_GFX_ERROR__SEM_UTCL1_ERROR__SHIFT 0x7
+#define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR__SHIFT 0x8
+#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR__SHIFT 0x9
+#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR__SHIFT 0xa
+#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR__SHIFT 0xb
+#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR__SHIFT 0xc
+#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR__SHIFT 0xd
+#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR__SHIFT 0xe
+#define CP_GFX_ERROR__APPEND_UTCL1_ERROR__SHIFT 0xf
+#define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR__SHIFT 0x10
+#define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR__SHIFT 0x11
+#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0x12
+#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x13
+#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR__SHIFT 0x14
+#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR__SHIFT 0x15
+#define CP_GFX_ERROR__CE_TC_UTCL1_ERROR__SHIFT 0x16
+#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR__SHIFT 0x17
+#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR__SHIFT 0x18
+#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR__SHIFT 0x19
+#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR__SHIFT 0x1a
+#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR__SHIFT 0x1b
+#define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR__SHIFT 0x1c
+#define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR__SHIFT 0x1d
+#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR__SHIFT 0x1e
+#define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR__SHIFT 0x1f
+#define CP_GFX_ERROR__EDC_ERROR_ID_MASK 0x0000000FL
+#define CP_GFX_ERROR__SUA_ERROR_MASK 0x00000010L
+#define CP_GFX_ERROR__RSVD1_ERROR_MASK 0x00000020L
+#define CP_GFX_ERROR__RSVD2_ERROR_MASK 0x00000040L
+#define CP_GFX_ERROR__SEM_UTCL1_ERROR_MASK 0x00000080L
+#define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR_MASK 0x00000100L
+#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR_MASK 0x00000200L
+#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR_MASK 0x00000400L
+#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR_MASK 0x00000800L
+#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR_MASK 0x00001000L
+#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR_MASK 0x00002000L
+#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR_MASK 0x00004000L
+#define CP_GFX_ERROR__APPEND_UTCL1_ERROR_MASK 0x00008000L
+#define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR_MASK 0x00010000L
+#define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR_MASK 0x00020000L
+#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00040000L
+#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00080000L
+#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR_MASK 0x00100000L
+#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR_MASK 0x00200000L
+#define CP_GFX_ERROR__CE_TC_UTCL1_ERROR_MASK 0x00400000L
+#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR_MASK 0x00800000L
+#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR_MASK 0x01000000L
+#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR_MASK 0x02000000L
+#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR_MASK 0x04000000L
+#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR_MASK 0x08000000L
+#define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR_MASK 0x10000000L
+#define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR_MASK 0x20000000L
+#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR_MASK 0x40000000L
+#define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR_MASK 0x80000000L
+//CPG_UTCL1_CNTL
+#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
+#define CPG_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17
+#define CPG_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
+#define CPG_UTCL1_CNTL__BYPASS__SHIFT 0x19
+#define CPG_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
+#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
+#define CPG_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
+#define CPG_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
+#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e
+#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
+#define CPG_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L
+#define CPG_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
+#define CPG_UTCL1_CNTL__BYPASS_MASK 0x02000000L
+#define CPG_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
+#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
+#define CPG_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
+#define CPG_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
+#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L
+//CPC_UTCL1_CNTL
+#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
+#define CPC_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
+#define CPC_UTCL1_CNTL__BYPASS__SHIFT 0x19
+#define CPC_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
+#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
+#define CPC_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
+#define CPC_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
+#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e
+#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
+#define CPC_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
+#define CPC_UTCL1_CNTL__BYPASS_MASK 0x02000000L
+#define CPC_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
+#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
+#define CPC_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
+#define CPC_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
+#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L
+//CPF_UTCL1_CNTL
+#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
+#define CPF_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17
+#define CPF_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
+#define CPF_UTCL1_CNTL__BYPASS__SHIFT 0x19
+#define CPF_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
+#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
+#define CPF_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
+#define CPF_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
+#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e
+#define CPF_UTCL1_CNTL__FORCE_NO_EXE__SHIFT 0x1f
+#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
+#define CPF_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L
+#define CPF_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
+#define CPF_UTCL1_CNTL__BYPASS_MASK 0x02000000L
+#define CPF_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
+#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
+#define CPF_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
+#define CPF_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
+#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L
+#define CPF_UTCL1_CNTL__FORCE_NO_EXE_MASK 0x80000000L
+//CP_AQL_SMM_STATUS
+#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM__SHIFT 0x0
+#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM_MASK 0xFFFFFFFFL
+//CP_RB0_BASE
+#define CP_RB0_BASE__RB_BASE__SHIFT 0x0
+#define CP_RB0_BASE__RB_BASE_MASK 0xFFFFFFFFL
+//CP_RB_BASE
+#define CP_RB_BASE__RB_BASE__SHIFT 0x0
+#define CP_RB_BASE__RB_BASE_MASK 0xFFFFFFFFL
+//CP_RB0_CNTL
+#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0
+#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8
+#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x11
+#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14
+#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
+#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b
+#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
+#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x0000003FL
+#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x00003F00L
+#define CP_RB0_CNTL__BUF_SWAP_MASK 0x00060000L
+#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x00300000L
+#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L
+#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x01000000L
+#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x08000000L
+#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
+//CP_RB_CNTL
+#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0
+#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8
+#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14
+#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
+#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b
+#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
+#define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003FL
+#define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003F00L
+#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x00300000L
+#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L
+#define CP_RB_CNTL__CACHE_POLICY_MASK 0x01000000L
+#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L
+#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
+//CP_RB_RPTR_WR
+#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0
+#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000FFFFFL
+//CP_RB0_RPTR_ADDR
+#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
+#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL
+//CP_RB_RPTR_ADDR
+#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
+#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL
+//CP_RB0_RPTR_ADDR_HI
+#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
+#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL
+//CP_RB_RPTR_ADDR_HI
+#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
+#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL
+//CP_RB0_BUFSZ_MASK
+#define CP_RB0_BUFSZ_MASK__DATA__SHIFT 0x0
+#define CP_RB0_BUFSZ_MASK__DATA_MASK 0x000FFFFFL
+//CP_RB_BUFSZ_MASK
+#define CP_RB_BUFSZ_MASK__DATA__SHIFT 0x0
+#define CP_RB_BUFSZ_MASK__DATA_MASK 0x000FFFFFL
+//CP_RB_WPTR_POLL_ADDR_LO
+#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2
+#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xFFFFFFFCL
+//CP_RB_WPTR_POLL_ADDR_HI
+#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0
+#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0x0000FFFFL
+//CP_INT_CNTL
+#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
+#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x12
+#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
+#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
+#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x15
+#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
+#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L
+#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x00040000L
+#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
+#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
+#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x00200000L
+#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
+#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_INT_STATUS
+#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
+#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
+#define CP_INT_STATUS__GPF_INT_STAT__SHIFT 0x10
+#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
+#define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x12
+#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13
+#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14
+#define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x15
+#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16
+#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17
+#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18
+#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
+#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d
+#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e
+#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f
+#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L
+#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
+#define CP_INT_STATUS__GPF_INT_STAT_MASK 0x00010000L
+#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
+#define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x00040000L
+#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x00080000L
+#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
+#define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x00200000L
+#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x00400000L
+#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x00800000L
+#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
+#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x04000000L
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
+#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000L
+#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000L
+#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000L
+//CP_DEVICE_ID
+#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define CP_DEVICE_ID__DEVICE_ID_MASK 0x000000FFL
+//CP_ME0_PIPE_PRIORITY_CNTS
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L
+//CP_RING_PRIORITY_CNTS
+#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
+#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
+#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
+#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
+#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL
+#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L
+#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L
+#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L
+//CP_ME0_PIPE0_PRIORITY
+#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_RING0_PRIORITY
+#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_RING0_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_ME0_PIPE1_PRIORITY
+#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_RING1_PRIORITY
+#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_RING1_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_ME0_PIPE2_PRIORITY
+#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_RING2_PRIORITY
+#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_RING2_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_FATAL_ERROR
+#define CP_FATAL_ERROR__CPF_FATAL_ERROR__SHIFT 0x0
+#define CP_FATAL_ERROR__CPG_FATAL_ERROR__SHIFT 0x1
+#define CP_FATAL_ERROR__GFX_HALT_PROC__SHIFT 0x2
+#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR__SHIFT 0x3
+#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN__SHIFT 0x4
+#define CP_FATAL_ERROR__CPF_FATAL_ERROR_MASK 0x00000001L
+#define CP_FATAL_ERROR__CPG_FATAL_ERROR_MASK 0x00000002L
+#define CP_FATAL_ERROR__GFX_HALT_PROC_MASK 0x00000004L
+#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR_MASK 0x00000008L
+#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN_MASK 0x00000010L
+//CP_RB_VMID
+#define CP_RB_VMID__RB0_VMID__SHIFT 0x0
+#define CP_RB_VMID__RB1_VMID__SHIFT 0x8
+#define CP_RB_VMID__RB2_VMID__SHIFT 0x10
+#define CP_RB_VMID__RB0_VMID_MASK 0x0000000FL
+#define CP_RB_VMID__RB1_VMID_MASK 0x00000F00L
+#define CP_RB_VMID__RB2_VMID_MASK 0x000F0000L
+//CP_ME0_PIPE0_VMID
+#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0
+#define CP_ME0_PIPE0_VMID__VMID_MASK 0x0000000FL
+//CP_ME0_PIPE1_VMID
+#define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0
+#define CP_ME0_PIPE1_VMID__VMID_MASK 0x0000000FL
+//CP_RB0_WPTR
+#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0
+#define CP_RB0_WPTR__RB_WPTR_MASK 0xFFFFFFFFL
+//CP_RB_WPTR
+#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0
+#define CP_RB_WPTR__RB_WPTR_MASK 0xFFFFFFFFL
+//CP_RB0_WPTR_HI
+#define CP_RB0_WPTR_HI__RB_WPTR__SHIFT 0x0
+#define CP_RB0_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL
+//CP_RB_WPTR_HI
+#define CP_RB_WPTR_HI__RB_WPTR__SHIFT 0x0
+#define CP_RB_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL
+//CP_RB1_WPTR
+#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0
+#define CP_RB1_WPTR__RB_WPTR_MASK 0xFFFFFFFFL
+//CP_RB1_WPTR_HI
+#define CP_RB1_WPTR_HI__RB_WPTR__SHIFT 0x0
+#define CP_RB1_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL
+//CP_RB2_WPTR
+#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0
+#define CP_RB2_WPTR__RB_WPTR_MASK 0x000FFFFFL
+//CP_RB_DOORBELL_CONTROL
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L
+//CP_RB_DOORBELL_RANGE_LOWER
+#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2
+#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x0FFFFFFCL
+//CP_RB_DOORBELL_RANGE_UPPER
+#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2
+#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL
+//CP_MEC_DOORBELL_RANGE_LOWER
+#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2
+#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x0FFFFFFCL
+//CP_MEC_DOORBELL_RANGE_UPPER
+#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2
+#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL
+//CPG_UTCL1_ERROR
+#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0
+#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L
+//CPC_UTCL1_ERROR
+#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0
+#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L
+//CP_RB1_BASE
+#define CP_RB1_BASE__RB_BASE__SHIFT 0x0
+#define CP_RB1_BASE__RB_BASE_MASK 0xFFFFFFFFL
+//CP_RB1_CNTL
+#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0
+#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8
+#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14
+#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
+#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b
+#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
+#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x0000003FL
+#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x00003F00L
+#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x00300000L
+#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L
+#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x01000000L
+#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x08000000L
+#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
+//CP_RB1_RPTR_ADDR
+#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
+#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL
+//CP_RB1_RPTR_ADDR_HI
+#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
+#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL
+//CP_RB2_BASE
+#define CP_RB2_BASE__RB_BASE__SHIFT 0x0
+#define CP_RB2_BASE__RB_BASE_MASK 0xFFFFFFFFL
+//CP_RB2_CNTL
+#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0
+#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8
+#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14
+#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
+#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b
+#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
+#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x0000003FL
+#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x00003F00L
+#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x00300000L
+#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L
+#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x01000000L
+#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x08000000L
+#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
+//CP_RB2_RPTR_ADDR
+#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
+#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL
+//CP_RB2_RPTR_ADDR_HI
+#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
+#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL
+//CP_RB0_ACTIVE
+#define CP_RB0_ACTIVE__ACTIVE__SHIFT 0x0
+#define CP_RB0_ACTIVE__ACTIVE_MASK 0x00000001L
+//CP_RB_ACTIVE
+#define CP_RB_ACTIVE__ACTIVE__SHIFT 0x0
+#define CP_RB_ACTIVE__ACTIVE_MASK 0x00000001L
+//CP_INT_CNTL_RING0
+#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
+#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_INT_CNTL_RING0__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x12
+#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
+#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
+#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x15
+#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
+#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L
+#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_INT_CNTL_RING0__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x00040000L
+#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
+#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
+#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x00200000L
+#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
+#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_INT_CNTL_RING1
+#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
+#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_INT_CNTL_RING1__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT 0x12
+#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
+#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
+#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT 0x15
+#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
+#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L
+#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK 0x00040000L
+#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
+#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
+#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK 0x00200000L
+#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
+#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_INT_CNTL_RING2
+#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
+#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_INT_CNTL_RING2__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT 0x12
+#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
+#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
+#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT 0x15
+#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
+#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L
+#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_INT_CNTL_RING2__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK 0x00040000L
+#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
+#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
+#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK 0x00200000L
+#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
+#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_INT_STATUS_RING0
+#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
+#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
+#define CP_INT_STATUS_RING0__GPF_INT_STAT__SHIFT 0x10
+#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
+#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x12
+#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x13
+#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14
+#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x15
+#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16
+#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17
+#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18
+#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a
+#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
+#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d
+#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e
+#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f
+#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L
+#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
+#define CP_INT_STATUS_RING0__GPF_INT_STAT_MASK 0x00010000L
+#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
+#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x00040000L
+#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x00080000L
+#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
+#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x00200000L
+#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x00400000L
+#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x00800000L
+#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
+#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x04000000L
+#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
+#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000L
+#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000L
+#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000L
+//CP_INT_STATUS_RING1
+#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
+#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
+#define CP_INT_STATUS_RING1__GPF_INT_STAT__SHIFT 0x10
+#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
+#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT 0x12
+#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13
+#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14
+#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT 0x15
+#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16
+#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17
+#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18
+#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a
+#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
+#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d
+#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e
+#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f
+#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L
+#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
+#define CP_INT_STATUS_RING1__GPF_INT_STAT_MASK 0x00010000L
+#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
+#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK 0x00040000L
+#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x00080000L
+#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
+#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK 0x00200000L
+#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x00400000L
+#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x00800000L
+#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
+#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x04000000L
+#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
+#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000L
+#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000L
+#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000L
+//CP_INT_STATUS_RING2
+#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
+#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
+#define CP_INT_STATUS_RING2__GPF_INT_STAT__SHIFT 0x10
+#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
+#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT 0x12
+#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13
+#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14
+#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT 0x15
+#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16
+#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17
+#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18
+#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a
+#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
+#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d
+#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e
+#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f
+#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L
+#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
+#define CP_INT_STATUS_RING2__GPF_INT_STAT_MASK 0x00010000L
+#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
+#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK 0x00040000L
+#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x00080000L
+#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
+#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK 0x00200000L
+#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x00400000L
+#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x00800000L
+#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
+#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x04000000L
+#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
+#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000L
+#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000L
+#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000L
+//CP_ME_F32_INTERRUPT
+#define CP_ME_F32_INTERRUPT__ECC_ERROR_INT__SHIFT 0x0
+#define CP_ME_F32_INTERRUPT__TIME_STAMP_INT__SHIFT 0x1
+#define CP_ME_F32_INTERRUPT__ME_F32_INT_2__SHIFT 0x2
+#define CP_ME_F32_INTERRUPT__ME_F32_INT_3__SHIFT 0x3
+#define CP_ME_F32_INTERRUPT__ECC_ERROR_INT_MASK 0x00000001L
+#define CP_ME_F32_INTERRUPT__TIME_STAMP_INT_MASK 0x00000002L
+#define CP_ME_F32_INTERRUPT__ME_F32_INT_2_MASK 0x00000004L
+#define CP_ME_F32_INTERRUPT__ME_F32_INT_3_MASK 0x00000008L
+//CP_PFP_F32_INTERRUPT
+#define CP_PFP_F32_INTERRUPT__ECC_ERROR_INT__SHIFT 0x0
+#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
+#define CP_PFP_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT 0x2
+#define CP_PFP_F32_INTERRUPT__PFP_F32_INT_3__SHIFT 0x3
+#define CP_PFP_F32_INTERRUPT__ECC_ERROR_INT_MASK 0x00000001L
+#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L
+#define CP_PFP_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK 0x00000004L
+#define CP_PFP_F32_INTERRUPT__PFP_F32_INT_3_MASK 0x00000008L
+//CP_CE_F32_INTERRUPT
+#define CP_CE_F32_INTERRUPT__ECC_ERROR_INT__SHIFT 0x0
+#define CP_CE_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT 0x1
+#define CP_CE_F32_INTERRUPT__CE_F32_INT_2__SHIFT 0x2
+#define CP_CE_F32_INTERRUPT__CE_F32_INT_3__SHIFT 0x3
+#define CP_CE_F32_INTERRUPT__ECC_ERROR_INT_MASK 0x00000001L
+#define CP_CE_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK 0x00000002L
+#define CP_CE_F32_INTERRUPT__CE_F32_INT_2_MASK 0x00000004L
+#define CP_CE_F32_INTERRUPT__CE_F32_INT_3_MASK 0x00000008L
+//CP_MEC1_F32_INTERRUPT
+#define CP_MEC1_F32_INTERRUPT__EDC_ROQ_FED_INT__SHIFT 0x0
+#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
+#define CP_MEC1_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT 0x2
+#define CP_MEC1_F32_INTERRUPT__EDC_TC_FED_INT__SHIFT 0x3
+#define CP_MEC1_F32_INTERRUPT__EDC_GDS_FED_INT__SHIFT 0x4
+#define CP_MEC1_F32_INTERRUPT__EDC_SCRATCH_FED_INT__SHIFT 0x5
+#define CP_MEC1_F32_INTERRUPT__WAVE_RESTORE_INT__SHIFT 0x6
+#define CP_MEC1_F32_INTERRUPT__SUA_VIOLATION_INT__SHIFT 0x7
+#define CP_MEC1_F32_INTERRUPT__EDC_DMA_FED_INT__SHIFT 0x8
+#define CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT__SHIFT 0x9
+#define CP_MEC1_F32_INTERRUPT__GPF_INT_CPF__SHIFT 0xa
+#define CP_MEC1_F32_INTERRUPT__GPF_INT_DMA__SHIFT 0xb
+#define CP_MEC1_F32_INTERRUPT__GPF_INT_CPC__SHIFT 0xc
+#define CP_MEC1_F32_INTERRUPT__EDC_SR_MEM_FED_INT__SHIFT 0xd
+#define CP_MEC1_F32_INTERRUPT__QUEUE_MESSAGE_INT__SHIFT 0xe
+#define CP_MEC1_F32_INTERRUPT__FATAL_EDC_ERROR_INT__SHIFT 0xf
+#define CP_MEC1_F32_INTERRUPT__EDC_ROQ_FED_INT_MASK 0x00000001L
+#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L
+#define CP_MEC1_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK 0x00000004L
+#define CP_MEC1_F32_INTERRUPT__EDC_TC_FED_INT_MASK 0x00000008L
+#define CP_MEC1_F32_INTERRUPT__EDC_GDS_FED_INT_MASK 0x00000010L
+#define CP_MEC1_F32_INTERRUPT__EDC_SCRATCH_FED_INT_MASK 0x00000020L
+#define CP_MEC1_F32_INTERRUPT__WAVE_RESTORE_INT_MASK 0x00000040L
+#define CP_MEC1_F32_INTERRUPT__SUA_VIOLATION_INT_MASK 0x00000080L
+#define CP_MEC1_F32_INTERRUPT__EDC_DMA_FED_INT_MASK 0x00000100L
+#define CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT_MASK 0x00000200L
+#define CP_MEC1_F32_INTERRUPT__GPF_INT_CPF_MASK 0x00000400L
+#define CP_MEC1_F32_INTERRUPT__GPF_INT_DMA_MASK 0x00000800L
+#define CP_MEC1_F32_INTERRUPT__GPF_INT_CPC_MASK 0x00001000L
+#define CP_MEC1_F32_INTERRUPT__EDC_SR_MEM_FED_INT_MASK 0x00002000L
+#define CP_MEC1_F32_INTERRUPT__QUEUE_MESSAGE_INT_MASK 0x00004000L
+#define CP_MEC1_F32_INTERRUPT__FATAL_EDC_ERROR_INT_MASK 0x00008000L
+//CP_MEC2_F32_INTERRUPT
+#define CP_MEC2_F32_INTERRUPT__EDC_ROQ_FED_INT__SHIFT 0x0
+#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
+#define CP_MEC2_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT 0x2
+#define CP_MEC2_F32_INTERRUPT__EDC_TC_FED_INT__SHIFT 0x3
+#define CP_MEC2_F32_INTERRUPT__EDC_GDS_FED_INT__SHIFT 0x4
+#define CP_MEC2_F32_INTERRUPT__EDC_SCRATCH_FED_INT__SHIFT 0x5
+#define CP_MEC2_F32_INTERRUPT__WAVE_RESTORE_INT__SHIFT 0x6
+#define CP_MEC2_F32_INTERRUPT__SUA_VIOLATION_INT__SHIFT 0x7
+#define CP_MEC2_F32_INTERRUPT__EDC_DMA_FED_INT__SHIFT 0x8
+#define CP_MEC2_F32_INTERRUPT__IQ_TIMER_INT__SHIFT 0x9
+#define CP_MEC2_F32_INTERRUPT__GPF_INT_CPF__SHIFT 0xa
+#define CP_MEC2_F32_INTERRUPT__GPF_INT_DMA__SHIFT 0xb
+#define CP_MEC2_F32_INTERRUPT__GPF_INT_CPC__SHIFT 0xc
+#define CP_MEC2_F32_INTERRUPT__EDC_SR_MEM_FED_INT__SHIFT 0xd
+#define CP_MEC2_F32_INTERRUPT__QUEUE_MESSAGE_INT__SHIFT 0xe
+#define CP_MEC2_F32_INTERRUPT__FATAL_EDC_ERROR_INT__SHIFT 0xf
+#define CP_MEC2_F32_INTERRUPT__EDC_ROQ_FED_INT_MASK 0x00000001L
+#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L
+#define CP_MEC2_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK 0x00000004L
+#define CP_MEC2_F32_INTERRUPT__EDC_TC_FED_INT_MASK 0x00000008L
+#define CP_MEC2_F32_INTERRUPT__EDC_GDS_FED_INT_MASK 0x00000010L
+#define CP_MEC2_F32_INTERRUPT__EDC_SCRATCH_FED_INT_MASK 0x00000020L
+#define CP_MEC2_F32_INTERRUPT__WAVE_RESTORE_INT_MASK 0x00000040L
+#define CP_MEC2_F32_INTERRUPT__SUA_VIOLATION_INT_MASK 0x00000080L
+#define CP_MEC2_F32_INTERRUPT__EDC_DMA_FED_INT_MASK 0x00000100L
+#define CP_MEC2_F32_INTERRUPT__IQ_TIMER_INT_MASK 0x00000200L
+#define CP_MEC2_F32_INTERRUPT__GPF_INT_CPF_MASK 0x00000400L
+#define CP_MEC2_F32_INTERRUPT__GPF_INT_DMA_MASK 0x00000800L
+#define CP_MEC2_F32_INTERRUPT__GPF_INT_CPC_MASK 0x00001000L
+#define CP_MEC2_F32_INTERRUPT__EDC_SR_MEM_FED_INT_MASK 0x00002000L
+#define CP_MEC2_F32_INTERRUPT__QUEUE_MESSAGE_INT_MASK 0x00004000L
+#define CP_MEC2_F32_INTERRUPT__FATAL_EDC_ERROR_INT_MASK 0x00008000L
+//CP_PWR_CNTL
+#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x0
+#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x1
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0xb
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x11
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x12
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13
+#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x00000001L
+#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x00000002L
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x00000100L
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x00000200L
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x00000400L
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x00000800L
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x00010000L
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x00020000L
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x00040000L
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x00080000L
+//CP_MEM_SLP_CNTL
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0
+#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1
+#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
+#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT 0x7
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10
+#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L
+#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x00000002L
+#define CP_MEM_SLP_CNTL__RESERVED_MASK 0x0000007CL
+#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0x0000FF00L
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0x00FF0000L
+#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xFF000000L
+//CP_ECC_DMA_FIRST_OCCURRENCE
+#define CP_ECC_DMA_FIRST_OCCURRENCE__INTERFACE__SHIFT 0x0
+#define CP_ECC_DMA_FIRST_OCCURRENCE__CLIENT__SHIFT 0x4
+#define CP_ECC_DMA_FIRST_OCCURRENCE__ME__SHIFT 0x8
+#define CP_ECC_DMA_FIRST_OCCURRENCE__PIPE__SHIFT 0xa
+#define CP_ECC_DMA_FIRST_OCCURRENCE__QUEUE__SHIFT 0xc
+#define CP_ECC_DMA_FIRST_OCCURRENCE__VMID__SHIFT 0x10
+#define CP_ECC_DMA_FIRST_OCCURRENCE__INTERFACE_MASK 0x00000003L
+#define CP_ECC_DMA_FIRST_OCCURRENCE__CLIENT_MASK 0x000000F0L
+#define CP_ECC_DMA_FIRST_OCCURRENCE__ME_MASK 0x00000300L
+#define CP_ECC_DMA_FIRST_OCCURRENCE__PIPE_MASK 0x00000C00L
+#define CP_ECC_DMA_FIRST_OCCURRENCE__QUEUE_MASK 0x00007000L
+#define CP_ECC_DMA_FIRST_OCCURRENCE__VMID_MASK 0x000F0000L
+//CP_ECC_FIRSTOCCURRENCE
+#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0
+#define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x4
+#define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x8
+#define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa
+#define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT 0xc
+#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10
+#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x00000003L
+#define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0x000000F0L
+#define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x00000300L
+#define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0x00000C00L
+#define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK 0x00007000L
+#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0x000F0000L
+//CP_ECC_FIRSTOCCURRENCE_RING0
+#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x0
+#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xFFFFFFFFL
+//CP_ECC_FIRSTOCCURRENCE_RING1
+#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT 0x0
+#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK 0xFFFFFFFFL
+//CP_ECC_FIRSTOCCURRENCE_RING2
+#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT 0x0
+#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK 0xFFFFFFFFL
+//GB_EDC_MODE
+#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0xf
+#define GB_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10
+#define GB_EDC_MODE__GATE_FUE__SHIFT 0x11
+#define GB_EDC_MODE__DED_MODE__SHIFT 0x14
+#define GB_EDC_MODE__PROP_FED__SHIFT 0x1d
+#define GB_EDC_MODE__BYPASS__SHIFT 0x1f
+#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x00008000L
+#define GB_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L
+#define GB_EDC_MODE__GATE_FUE_MASK 0x00020000L
+#define GB_EDC_MODE__DED_MODE_MASK 0x00300000L
+#define GB_EDC_MODE__PROP_FED_MASK 0x20000000L
+#define GB_EDC_MODE__BYPASS_MASK 0x80000000L
+//CP_PQ_WPTR_POLL_CNTL
+#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0
+#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT__SHIFT 0x1d
+#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e
+#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f
+#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0x000000FFL
+#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT_MASK 0x20000000L
+#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000L
+#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000L
+//CP_PQ_WPTR_POLL_CNTL1
+#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0
+#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xFFFFFFFFL
+//CP_ME1_PIPE0_INT_CNTL
+#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
+#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
+#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
+#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_ME1_PIPE1_INT_CNTL
+#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
+#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
+#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
+#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_ME1_PIPE2_INT_CNTL
+#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
+#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
+#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
+#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_ME1_PIPE3_INT_CNTL
+#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
+#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
+#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
+#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_ME2_PIPE0_INT_CNTL
+#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
+#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
+#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
+#define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_ME2_PIPE1_INT_CNTL
+#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
+#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
+#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
+#define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_ME2_PIPE2_INT_CNTL
+#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
+#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
+#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
+#define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_ME2_PIPE3_INT_CNTL
+#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
+#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
+#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
+#define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_ME1_PIPE0_INT_STATUS
+#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
+#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
+#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
+#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
+#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
+#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
+#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
+#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
+#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
+#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
+#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
+//CP_ME1_PIPE1_INT_STATUS
+#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
+#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
+#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
+#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
+#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
+#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
+#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
+#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
+#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
+#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
+#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
+//CP_ME1_PIPE2_INT_STATUS
+#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
+#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
+#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
+#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
+#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
+#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
+#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
+#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
+#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
+#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
+#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
+//CP_ME1_PIPE3_INT_STATUS
+#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
+#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
+#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
+#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
+#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
+#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
+#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
+#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
+#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
+#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
+#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
+//CP_ME2_PIPE0_INT_STATUS
+#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
+#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
+#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
+#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
+#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
+#define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
+#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
+#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
+#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
+#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
+#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
+//CP_ME2_PIPE1_INT_STATUS
+#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
+#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
+#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
+#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
+#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
+#define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
+#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
+#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
+#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
+#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
+#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
+//CP_ME2_PIPE2_INT_STATUS
+#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
+#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
+#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
+#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
+#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
+#define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
+#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
+#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
+#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
+#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
+#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
+//CP_ME2_PIPE3_INT_STATUS
+#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
+#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
+#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
+#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
+#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
+#define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
+#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
+#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
+#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
+#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
+#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
+#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
+#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L
+#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
+#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L
+//CC_GC_EDC_CONFIG
+#define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1
+#define CC_GC_EDC_CONFIG__ENABLE_IRRITATOR_CLK__SHIFT 0x2
+#define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x00000002L
+#define CC_GC_EDC_CONFIG__ENABLE_IRRITATOR_CLK_MASK 0x00000004L
+//CP_ME1_PIPE_PRIORITY_CNTS
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L
+//CP_ME1_PIPE0_PRIORITY
+#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_ME1_PIPE1_PRIORITY
+#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_ME1_PIPE2_PRIORITY
+#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_ME1_PIPE3_PRIORITY
+#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_ME2_PIPE_PRIORITY_CNTS
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L
+//CP_ME2_PIPE0_PRIORITY
+#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_ME2_PIPE1_PRIORITY
+#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_ME2_PIPE2_PRIORITY
+#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_ME2_PIPE3_PRIORITY
+#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_CE_PRGRM_CNTR_START
+#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0
+#define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x000007FFL
+//CP_PFP_PRGRM_CNTR_START
+#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0
+#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0x00001FFFL
+//CP_ME_PRGRM_CNTR_START
+#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0
+#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0x00000FFFL
+//CP_MEC1_PRGRM_CNTR_START
+#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0
+#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0x0000FFFFL
+//CP_MEC2_PRGRM_CNTR_START
+#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0
+#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0x0000FFFFL
+//CP_CE_INTR_ROUTINE_START
+#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0
+#define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x000007FFL
+//CP_PFP_INTR_ROUTINE_START
+#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0
+#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0x00001FFFL
+//CP_ME_INTR_ROUTINE_START
+#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0
+#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0x00000FFFL
+//CP_MEC1_INTR_ROUTINE_START
+#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0
+#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0x0000FFFFL
+//CP_MEC2_INTR_ROUTINE_START
+#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0
+#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0x0000FFFFL
+//CP_CONTEXT_CNTL
+#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0
+#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4
+#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10
+#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14
+#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x00000007L
+#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x00000070L
+#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x00070000L
+#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x00700000L
+//CP_MAX_CONTEXT
+#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0
+#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x00000007L
+//CP_IQ_WAIT_TIME1
+#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0
+#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8
+#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10
+#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18
+#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0x000000FFL
+#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0x0000FF00L
+#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0x00FF0000L
+#define CP_IQ_WAIT_TIME1__GWS_MASK 0xFF000000L
+//CP_IQ_WAIT_TIME2
+#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0
+#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8
+#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10
+#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18
+#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0x000000FFL
+#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0x0000FF00L
+#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0x00FF0000L
+#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xFF000000L
+//CP_RB0_BASE_HI
+#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0
+#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0x000000FFL
+//CP_RB1_BASE_HI
+#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0
+#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0x000000FFL
+//CP_VMID_RESET
+#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0
+#define CP_VMID_RESET__RESET_REQUEST_MASK 0x0000FFFFL
+//CPC_INT_CNTL
+#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CPC_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
+#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
+#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
+#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
+#define CPC_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
+#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CPC_INT_STATUS
+#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CPC_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
+#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
+#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
+#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
+#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
+#define CPC_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
+#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
+#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
+#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
+#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
+#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
+#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
+#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
+#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
+//CP_VMID_PREEMPT
+#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0
+#define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x10
+#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0x0000FFFFL
+#define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0x000F0000L
+//CPC_INT_CNTX_ID
+#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0
+#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL
+//CP_PQ_STATUS
+#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0
+#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1
+#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x00000001L
+#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x00000002L
+//CP_CPC_IC_BASE_LO
+#define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc
+#define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L
+//CP_CPC_IC_BASE_HI
+#define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0
+#define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL
+//CP_CPC_IC_BASE_CNTL
+#define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0
+#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_CPC_IC_BASE_CNTL__VMID_MASK 0x0000000FL
+#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x01000000L
+//CP_CPC_IC_OP_CNTL
+#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0
+#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4
+#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5
+#define CP_CPC_IC_OP_CNTL__ICACHE_INVALIDATED__SHIFT 0x6
+#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L
+#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L
+#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L
+#define CP_CPC_IC_OP_CNTL__ICACHE_INVALIDATED_MASK 0x00000040L
+//CP_MEC1_F32_INT_DIS
+#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0
+#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1
+#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2
+#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3
+#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4
+#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5
+#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6
+#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7
+#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8
+#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9
+#define CP_MEC1_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa
+#define CP_MEC1_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb
+#define CP_MEC1_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc
+#define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0xd
+#define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe
+#define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0xf
+#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L
+#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L
+#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L
+#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L
+#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L
+#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L
+#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L
+#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L
+#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L
+#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L
+#define CP_MEC1_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L
+#define CP_MEC1_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L
+#define CP_MEC1_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L
+#define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L
+#define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L
+#define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L
+//CP_MEC2_F32_INT_DIS
+#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0
+#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1
+#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2
+#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3
+#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4
+#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5
+#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6
+#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7
+#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8
+#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9
+#define CP_MEC2_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa
+#define CP_MEC2_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb
+#define CP_MEC2_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc
+#define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0xd
+#define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe
+#define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0xf
+#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L
+#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L
+#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L
+#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L
+#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L
+#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L
+#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L
+#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L
+#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L
+#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L
+#define CP_MEC2_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L
+#define CP_MEC2_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L
+#define CP_MEC2_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L
+#define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L
+#define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L
+#define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L
+//CP_VMID_STATUS
+#define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x0
+#define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10
+#define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0x0000FFFFL
+#define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xFFFF0000L
+
+
+// addressBlock: gc_cppdec2
+//CP_RB_DOORBELL_CONTROL_SCH_0
+#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN__SHIFT 0x1e
+#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT__SHIFT 0x1f
+#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
+#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN_MASK 0x40000000L
+#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT_MASK 0x80000000L
+//CP_RB_DOORBELL_CONTROL_SCH_1
+#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN__SHIFT 0x1e
+#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT__SHIFT 0x1f
+#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
+#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN_MASK 0x40000000L
+#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT_MASK 0x80000000L
+//CP_RB_DOORBELL_CONTROL_SCH_2
+#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN__SHIFT 0x1e
+#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT__SHIFT 0x1f
+#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
+#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN_MASK 0x40000000L
+#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT_MASK 0x80000000L
+//CP_RB_DOORBELL_CONTROL_SCH_3
+#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN__SHIFT 0x1e
+#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT__SHIFT 0x1f
+#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
+#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN_MASK 0x40000000L
+#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT_MASK 0x80000000L
+//CP_RB_DOORBELL_CONTROL_SCH_4
+#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN__SHIFT 0x1e
+#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT__SHIFT 0x1f
+#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
+#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN_MASK 0x40000000L
+#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT_MASK 0x80000000L
+//CP_RB_DOORBELL_CONTROL_SCH_5
+#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN__SHIFT 0x1e
+#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT__SHIFT 0x1f
+#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
+#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN_MASK 0x40000000L
+#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT_MASK 0x80000000L
+//CP_RB_DOORBELL_CONTROL_SCH_6
+#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN__SHIFT 0x1e
+#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT__SHIFT 0x1f
+#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
+#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN_MASK 0x40000000L
+#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT_MASK 0x80000000L
+//CP_RB_DOORBELL_CONTROL_SCH_7
+#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN__SHIFT 0x1e
+#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT__SHIFT 0x1f
+#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
+#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN_MASK 0x40000000L
+#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT_MASK 0x80000000L
+//CP_RB_DOORBELL_CLEAR
+#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE__SHIFT 0x0
+#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR__SHIFT 0x8
+#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR__SHIFT 0x9
+#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR__SHIFT 0xa
+#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR__SHIFT 0xb
+#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR__SHIFT 0xc
+#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR__SHIFT 0xd
+#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE_MASK 0x00000007L
+#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR_MASK 0x00000100L
+#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR_MASK 0x00000200L
+#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR_MASK 0x00000400L
+#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR_MASK 0x00000800L
+#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR_MASK 0x00001000L
+#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR_MASK 0x00002000L
+//CPF_EDC_TAG_CNT
+#define CPF_EDC_TAG_CNT__DED_COUNT__SHIFT 0x0
+#define CPF_EDC_TAG_CNT__SEC_COUNT__SHIFT 0x2
+#define CPF_EDC_TAG_CNT__DED_COUNT_MASK 0x00000003L
+#define CPF_EDC_TAG_CNT__SEC_COUNT_MASK 0x0000000CL
+//CPF_EDC_ROQ_CNT
+#define CPF_EDC_ROQ_CNT__DED_COUNT_ME1__SHIFT 0x0
+#define CPF_EDC_ROQ_CNT__SEC_COUNT_ME1__SHIFT 0x2
+#define CPF_EDC_ROQ_CNT__DED_COUNT_ME2__SHIFT 0x4
+#define CPF_EDC_ROQ_CNT__SEC_COUNT_ME2__SHIFT 0x6
+#define CPF_EDC_ROQ_CNT__DED_COUNT_ME1_MASK 0x00000003L
+#define CPF_EDC_ROQ_CNT__SEC_COUNT_ME1_MASK 0x0000000CL
+#define CPF_EDC_ROQ_CNT__DED_COUNT_ME2_MASK 0x00000030L
+#define CPF_EDC_ROQ_CNT__SEC_COUNT_ME2_MASK 0x000000C0L
+//CPG_EDC_TAG_CNT
+#define CPG_EDC_TAG_CNT__DED_COUNT__SHIFT 0x0
+#define CPG_EDC_TAG_CNT__SEC_COUNT__SHIFT 0x2
+#define CPG_EDC_TAG_CNT__DED_COUNT_MASK 0x00000003L
+#define CPG_EDC_TAG_CNT__SEC_COUNT_MASK 0x0000000CL
+//CPG_EDC_DMA_CNT
+#define CPG_EDC_DMA_CNT__ROQ_DED_COUNT__SHIFT 0x0
+#define CPG_EDC_DMA_CNT__ROQ_SEC_COUNT__SHIFT 0x2
+#define CPG_EDC_DMA_CNT__TAG_DED_COUNT__SHIFT 0x4
+#define CPG_EDC_DMA_CNT__TAG_SEC_COUNT__SHIFT 0x6
+#define CPG_EDC_DMA_CNT__ROQ_DED_COUNT_MASK 0x00000003L
+#define CPG_EDC_DMA_CNT__ROQ_SEC_COUNT_MASK 0x0000000CL
+#define CPG_EDC_DMA_CNT__TAG_DED_COUNT_MASK 0x00000030L
+#define CPG_EDC_DMA_CNT__TAG_SEC_COUNT_MASK 0x000000C0L
+//CPC_EDC_SCRATCH_CNT
+#define CPC_EDC_SCRATCH_CNT__DED_COUNT__SHIFT 0x0
+#define CPC_EDC_SCRATCH_CNT__SEC_COUNT__SHIFT 0x2
+#define CPC_EDC_SCRATCH_CNT__DED_COUNT_MASK 0x00000003L
+#define CPC_EDC_SCRATCH_CNT__SEC_COUNT_MASK 0x0000000CL
+//CPC_EDC_UCODE_CNT
+#define CPC_EDC_UCODE_CNT__DED_COUNT__SHIFT 0x0
+#define CPC_EDC_UCODE_CNT__SEC_COUNT__SHIFT 0x2
+#define CPC_EDC_UCODE_CNT__DED_COUNT_MASK 0x00000003L
+#define CPC_EDC_UCODE_CNT__SEC_COUNT_MASK 0x0000000CL
+//DC_EDC_STATE_CNT
+#define DC_EDC_STATE_CNT__DED_COUNT_ME1__SHIFT 0x0
+#define DC_EDC_STATE_CNT__SEC_COUNT_ME1__SHIFT 0x2
+#define DC_EDC_STATE_CNT__DED_COUNT_ME1_MASK 0x00000003L
+#define DC_EDC_STATE_CNT__SEC_COUNT_ME1_MASK 0x0000000CL
+//DC_EDC_CSINVOC_CNT
+#define DC_EDC_CSINVOC_CNT__DED_COUNT_ME1__SHIFT 0x0
+#define DC_EDC_CSINVOC_CNT__SEC_COUNT_ME1__SHIFT 0x2
+#define DC_EDC_CSINVOC_CNT__DED_COUNT1_ME1__SHIFT 0x4
+#define DC_EDC_CSINVOC_CNT__SEC_COUNT1_ME1__SHIFT 0x6
+#define DC_EDC_CSINVOC_CNT__DED_COUNT_ME1_MASK 0x00000003L
+#define DC_EDC_CSINVOC_CNT__SEC_COUNT_ME1_MASK 0x0000000CL
+#define DC_EDC_CSINVOC_CNT__DED_COUNT1_ME1_MASK 0x00000030L
+#define DC_EDC_CSINVOC_CNT__SEC_COUNT1_ME1_MASK 0x000000C0L
+//DC_EDC_RESTORE_CNT
+#define DC_EDC_RESTORE_CNT__DED_COUNT_ME1__SHIFT 0x0
+#define DC_EDC_RESTORE_CNT__SEC_COUNT_ME1__SHIFT 0x2
+#define DC_EDC_RESTORE_CNT__DED_COUNT1_ME1__SHIFT 0x4
+#define DC_EDC_RESTORE_CNT__SEC_COUNT1_ME1__SHIFT 0x6
+#define DC_EDC_RESTORE_CNT__DED_COUNT_ME1_MASK 0x00000003L
+#define DC_EDC_RESTORE_CNT__SEC_COUNT_ME1_MASK 0x0000000CL
+#define DC_EDC_RESTORE_CNT__DED_COUNT1_ME1_MASK 0x00000030L
+#define DC_EDC_RESTORE_CNT__SEC_COUNT1_ME1_MASK 0x000000C0L
+//CP_CPF_DSM_CNTL
+#define CP_CPF_DSM_CNTL__CPF0_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define CP_CPF_DSM_CNTL__CPF0_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define CP_CPF_DSM_CNTL__CPF1_DSM_IRRITATOR_DATA__SHIFT 0x3
+#define CP_CPF_DSM_CNTL__CPF1_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define CP_CPF_DSM_CNTL__CPF2_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define CP_CPF_DSM_CNTL__CPF2_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define CP_CPF_DSM_CNTL__CPF0_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define CP_CPF_DSM_CNTL__CPF0_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define CP_CPF_DSM_CNTL__CPF1_DSM_IRRITATOR_DATA_MASK 0x00000018L
+#define CP_CPF_DSM_CNTL__CPF1_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define CP_CPF_DSM_CNTL__CPF2_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define CP_CPF_DSM_CNTL__CPF2_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+//CP_CPG_DSM_CNTL
+#define CP_CPG_DSM_CNTL__CPG0_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define CP_CPG_DSM_CNTL__CPG0_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define CP_CPG_DSM_CNTL__CPG1_DSM_IRRITATOR_DATA__SHIFT 0x3
+#define CP_CPG_DSM_CNTL__CPG1_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define CP_CPG_DSM_CNTL__CPG2_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define CP_CPG_DSM_CNTL__CPG2_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define CP_CPG_DSM_CNTL__CPG0_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define CP_CPG_DSM_CNTL__CPG0_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define CP_CPG_DSM_CNTL__CPG1_DSM_IRRITATOR_DATA_MASK 0x00000018L
+#define CP_CPG_DSM_CNTL__CPG1_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define CP_CPG_DSM_CNTL__CPG2_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define CP_CPG_DSM_CNTL__CPG2_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+//CP_CPC_DSM_CNTL
+#define CP_CPC_DSM_CNTL__CPC0_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define CP_CPC_DSM_CNTL__CPC0_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define CP_CPC_DSM_CNTL__CPC1_DSM_IRRITATOR_DATA__SHIFT 0x3
+#define CP_CPC_DSM_CNTL__CPC1_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define CP_CPC_DSM_CNTL__CPC2_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define CP_CPC_DSM_CNTL__CPC2_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define CP_CPC_DSM_CNTL__CPC3_DSM_IRRITATOR_DATA__SHIFT 0x9
+#define CP_CPC_DSM_CNTL__CPC3_ENABLE_SINGLE_WRITE__SHIFT 0xb
+#define CP_CPC_DSM_CNTL__CPC4_DSM_IRRITATOR_DATA__SHIFT 0xc
+#define CP_CPC_DSM_CNTL__CPC4_ENABLE_SINGLE_WRITE__SHIFT 0xe
+#define CP_CPC_DSM_CNTL__CPC5_DSM_IRRITATOR_DATA__SHIFT 0xf
+#define CP_CPC_DSM_CNTL__CPC5_ENABLE_SINGLE_WRITE__SHIFT 0x11
+#define CP_CPC_DSM_CNTL__CPC6_DSM_IRRITATOR_DATA__SHIFT 0x12
+#define CP_CPC_DSM_CNTL__CPC6_ENABLE_SINGLE_WRITE__SHIFT 0x14
+#define CP_CPC_DSM_CNTL__CPC7_DSM_IRRITATOR_DATA__SHIFT 0x15
+#define CP_CPC_DSM_CNTL__CPC7_ENABLE_SINGLE_WRITE__SHIFT 0x17
+#define CP_CPC_DSM_CNTL__CPC8_DSM_IRRITATOR_DATA__SHIFT 0x18
+#define CP_CPC_DSM_CNTL__CPC8_ENABLE_SINGLE_WRITE__SHIFT 0x1a
+#define CP_CPC_DSM_CNTL__CPC0_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define CP_CPC_DSM_CNTL__CPC0_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define CP_CPC_DSM_CNTL__CPC1_DSM_IRRITATOR_DATA_MASK 0x00000018L
+#define CP_CPC_DSM_CNTL__CPC1_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define CP_CPC_DSM_CNTL__CPC2_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define CP_CPC_DSM_CNTL__CPC2_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define CP_CPC_DSM_CNTL__CPC3_DSM_IRRITATOR_DATA_MASK 0x00000600L
+#define CP_CPC_DSM_CNTL__CPC3_ENABLE_SINGLE_WRITE_MASK 0x00000800L
+#define CP_CPC_DSM_CNTL__CPC4_DSM_IRRITATOR_DATA_MASK 0x00003000L
+#define CP_CPC_DSM_CNTL__CPC4_ENABLE_SINGLE_WRITE_MASK 0x00004000L
+#define CP_CPC_DSM_CNTL__CPC5_DSM_IRRITATOR_DATA_MASK 0x00018000L
+#define CP_CPC_DSM_CNTL__CPC5_ENABLE_SINGLE_WRITE_MASK 0x00020000L
+#define CP_CPC_DSM_CNTL__CPC6_DSM_IRRITATOR_DATA_MASK 0x000C0000L
+#define CP_CPC_DSM_CNTL__CPC6_ENABLE_SINGLE_WRITE_MASK 0x00100000L
+#define CP_CPC_DSM_CNTL__CPC7_DSM_IRRITATOR_DATA_MASK 0x00600000L
+#define CP_CPC_DSM_CNTL__CPC7_ENABLE_SINGLE_WRITE_MASK 0x00800000L
+#define CP_CPC_DSM_CNTL__CPC8_DSM_IRRITATOR_DATA_MASK 0x03000000L
+#define CP_CPC_DSM_CNTL__CPC8_ENABLE_SINGLE_WRITE_MASK 0x04000000L
+//CP_CPF_DSM_CNTL2
+#define CP_CPF_DSM_CNTL2__CPF0_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define CP_CPF_DSM_CNTL2__CPF0_SELECT_INJECT_DELAY__SHIFT 0x2
+#define CP_CPF_DSM_CNTL2__CPF1_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define CP_CPF_DSM_CNTL2__CPF1_SELECT_INJECT_DELAY__SHIFT 0x5
+#define CP_CPF_DSM_CNTL2__CPF2_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define CP_CPF_DSM_CNTL2__CPF2_SELECT_INJECT_DELAY__SHIFT 0x8
+#define CP_CPF_DSM_CNTL2__CPF0_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define CP_CPF_DSM_CNTL2__CPF0_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define CP_CPF_DSM_CNTL2__CPF1_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define CP_CPF_DSM_CNTL2__CPF1_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define CP_CPF_DSM_CNTL2__CPF2_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define CP_CPF_DSM_CNTL2__CPF2_SELECT_INJECT_DELAY_MASK 0x00000100L
+//CP_CPG_DSM_CNTL2
+#define CP_CPG_DSM_CNTL2__CPG0_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define CP_CPG_DSM_CNTL2__CPG0_SELECT_INJECT_DELAY__SHIFT 0x2
+#define CP_CPG_DSM_CNTL2__CPG1_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define CP_CPG_DSM_CNTL2__CPG1_SELECT_INJECT_DELAY__SHIFT 0x5
+#define CP_CPG_DSM_CNTL2__CPG2_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define CP_CPG_DSM_CNTL2__CPG2_SELECT_INJECT_DELAY__SHIFT 0x8
+#define CP_CPG_DSM_CNTL2__CPG0_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define CP_CPG_DSM_CNTL2__CPG0_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define CP_CPG_DSM_CNTL2__CPG1_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define CP_CPG_DSM_CNTL2__CPG1_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define CP_CPG_DSM_CNTL2__CPG2_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define CP_CPG_DSM_CNTL2__CPG2_SELECT_INJECT_DELAY_MASK 0x00000100L
+//CP_CPC_DSM_CNTL2
+#define CP_CPC_DSM_CNTL2__CPC0_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define CP_CPC_DSM_CNTL2__CPC0_SELECT_INJECT_DELAY__SHIFT 0x2
+#define CP_CPC_DSM_CNTL2__CPC1_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define CP_CPC_DSM_CNTL2__CPC1_SELECT_INJECT_DELAY__SHIFT 0x5
+#define CP_CPC_DSM_CNTL2__CPC2_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define CP_CPC_DSM_CNTL2__CPC2_SELECT_INJECT_DELAY__SHIFT 0x8
+#define CP_CPC_DSM_CNTL2__CPC3_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define CP_CPC_DSM_CNTL2__CPC3_SELECT_INJECT_DELAY__SHIFT 0xb
+#define CP_CPC_DSM_CNTL2__CPC4_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define CP_CPC_DSM_CNTL2__CPC4_SELECT_INJECT_DELAY__SHIFT 0xe
+#define CP_CPC_DSM_CNTL2__CPC5_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define CP_CPC_DSM_CNTL2__CPC5_SELECT_INJECT_DELAY__SHIFT 0x11
+#define CP_CPC_DSM_CNTL2__CPC6_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define CP_CPC_DSM_CNTL2__CPC6_SELECT_INJECT_DELAY__SHIFT 0x14
+#define CP_CPC_DSM_CNTL2__CPC7_ENABLE_ERROR_INJECT__SHIFT 0x15
+#define CP_CPC_DSM_CNTL2__CPC7_SELECT_INJECT_DELAY__SHIFT 0x17
+#define CP_CPC_DSM_CNTL2__CPC8_ENABLE_ERROR_INJECT__SHIFT 0x18
+#define CP_CPC_DSM_CNTL2__CPC8_SELECT_INJECT_DELAY__SHIFT 0x1a
+#define CP_CPC_DSM_CNTL2__CPC0_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define CP_CPC_DSM_CNTL2__CPC0_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define CP_CPC_DSM_CNTL2__CPC1_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define CP_CPC_DSM_CNTL2__CPC1_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define CP_CPC_DSM_CNTL2__CPC2_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define CP_CPC_DSM_CNTL2__CPC2_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define CP_CPC_DSM_CNTL2__CPC3_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define CP_CPC_DSM_CNTL2__CPC3_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define CP_CPC_DSM_CNTL2__CPC4_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define CP_CPC_DSM_CNTL2__CPC4_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define CP_CPC_DSM_CNTL2__CPC5_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define CP_CPC_DSM_CNTL2__CPC5_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define CP_CPC_DSM_CNTL2__CPC6_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define CP_CPC_DSM_CNTL2__CPC6_SELECT_INJECT_DELAY_MASK 0x00100000L
+#define CP_CPC_DSM_CNTL2__CPC7_ENABLE_ERROR_INJECT_MASK 0x00600000L
+#define CP_CPC_DSM_CNTL2__CPC7_SELECT_INJECT_DELAY_MASK 0x00800000L
+#define CP_CPC_DSM_CNTL2__CPC8_ENABLE_ERROR_INJECT_MASK 0x03000000L
+#define CP_CPC_DSM_CNTL2__CPC8_SELECT_INJECT_DELAY_MASK 0x04000000L
+//CP_CPF_DSM_CNTL2A
+#define CP_CPF_DSM_CNTL2A__CPF_INJECT_DELAY__SHIFT 0x0
+#define CP_CPF_DSM_CNTL2A__CPF_INJECT_DELAY_MASK 0x0000003FL
+//CP_CPG_DSM_CNTL2A
+#define CP_CPG_DSM_CNTL2A__CPG_INJECT_DELAY__SHIFT 0x0
+#define CP_CPG_DSM_CNTL2A__CPG_INJECT_DELAY_MASK 0x0000003FL
+//CP_CPC_DSM_CNTL2A
+#define CP_CPC_DSM_CNTL2A__CPC_INJECT_DELAY__SHIFT 0x0
+#define CP_CPC_DSM_CNTL2A__CPC_INJECT_DELAY_MASK 0x0000003FL
+//CP_EDC_FUE_CNTL
+#define CP_EDC_FUE_CNTL__CP_FUE_MASK__SHIFT 0x0
+#define CP_EDC_FUE_CNTL__SPI_FUE_MASK__SHIFT 0x1
+#define CP_EDC_FUE_CNTL__GDS_FUE_MASK__SHIFT 0x2
+#define CP_EDC_FUE_CNTL__TC_RLC_FUE_MASK__SHIFT 0x3
+#define CP_EDC_FUE_CNTL__TC_CPG_FUE_MASK__SHIFT 0x4
+#define CP_EDC_FUE_CNTL__TCA_FUE_MASK__SHIFT 0x5
+#define CP_EDC_FUE_CNTL__TCC_FUE_MASK__SHIFT 0x6
+#define CP_EDC_FUE_CNTL__UTCL2_FUE_MASK__SHIFT 0x7
+#define CP_EDC_FUE_CNTL__CP_FUE_FLAG__SHIFT 0x10
+#define CP_EDC_FUE_CNTL__SPI_FUE_FLAG__SHIFT 0x11
+#define CP_EDC_FUE_CNTL__GDS_FUE_FLAG__SHIFT 0x12
+#define CP_EDC_FUE_CNTL__TC_RLC_FUE_FLAG__SHIFT 0x13
+#define CP_EDC_FUE_CNTL__TC_CPG_FUE_FLAG__SHIFT 0x14
+#define CP_EDC_FUE_CNTL__TCA_FUE_FLAG__SHIFT 0x15
+#define CP_EDC_FUE_CNTL__TCC_FUE_FLAG__SHIFT 0x16
+#define CP_EDC_FUE_CNTL__UTCL2_FUE_FLAG__SHIFT 0x17
+#define CP_EDC_FUE_CNTL__CP_FUE_MASK_MASK 0x00000001L
+#define CP_EDC_FUE_CNTL__SPI_FUE_MASK_MASK 0x00000002L
+#define CP_EDC_FUE_CNTL__GDS_FUE_MASK_MASK 0x00000004L
+#define CP_EDC_FUE_CNTL__TC_RLC_FUE_MASK_MASK 0x00000008L
+#define CP_EDC_FUE_CNTL__TC_CPG_FUE_MASK_MASK 0x00000010L
+#define CP_EDC_FUE_CNTL__TCA_FUE_MASK_MASK 0x00000020L
+#define CP_EDC_FUE_CNTL__TCC_FUE_MASK_MASK 0x00000040L
+#define CP_EDC_FUE_CNTL__UTCL2_FUE_MASK_MASK 0x00000080L
+#define CP_EDC_FUE_CNTL__CP_FUE_FLAG_MASK 0x00010000L
+#define CP_EDC_FUE_CNTL__SPI_FUE_FLAG_MASK 0x00020000L
+#define CP_EDC_FUE_CNTL__GDS_FUE_FLAG_MASK 0x00040000L
+#define CP_EDC_FUE_CNTL__TC_RLC_FUE_FLAG_MASK 0x00080000L
+#define CP_EDC_FUE_CNTL__TC_CPG_FUE_FLAG_MASK 0x00100000L
+#define CP_EDC_FUE_CNTL__TCA_FUE_FLAG_MASK 0x00200000L
+#define CP_EDC_FUE_CNTL__TCC_FUE_FLAG_MASK 0x00400000L
+#define CP_EDC_FUE_CNTL__UTCL2_FUE_FLAG_MASK 0x00800000L
+//CP_GFX_MQD_CONTROL
+#define CP_GFX_MQD_CONTROL__VMID__SHIFT 0x0
+#define CP_GFX_MQD_CONTROL__PRIV_STATE__SHIFT 0x8
+#define CP_GFX_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17
+#define CP_GFX_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18
+#define CP_GFX_MQD_CONTROL__VMID_MASK 0x0000000FL
+#define CP_GFX_MQD_CONTROL__PRIV_STATE_MASK 0x00000100L
+#define CP_GFX_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L
+#define CP_GFX_MQD_CONTROL__CACHE_POLICY_MASK 0x01000000L
+//CP_GFX_MQD_BASE_ADDR
+#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2
+#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL
+//CP_GFX_MQD_BASE_ADDR_HI
+#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
+#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL
+//CP_RB_STATUS
+#define CP_RB_STATUS__DOORBELL_UPDATED__SHIFT 0x0
+#define CP_RB_STATUS__DOORBELL_ENABLE__SHIFT 0x1
+#define CP_RB_STATUS__DOORBELL_UPDATED_MASK 0x00000001L
+#define CP_RB_STATUS__DOORBELL_ENABLE_MASK 0x00000002L
+//CPG_UTCL1_STATUS
+#define CPG_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
+#define CPG_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
+#define CPG_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
+#define CPG_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
+#define CPG_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
+#define CPG_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
+#define CPG_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
+#define CPG_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
+#define CPG_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
+#define CPG_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
+#define CPG_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
+#define CPG_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
+//CPC_UTCL1_STATUS
+#define CPC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
+#define CPC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
+#define CPC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
+#define CPC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
+#define CPC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
+#define CPC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
+#define CPC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
+#define CPC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
+#define CPC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
+#define CPC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
+#define CPC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
+#define CPC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
+//CPF_UTCL1_STATUS
+#define CPF_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
+#define CPF_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
+#define CPF_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
+#define CPF_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
+#define CPF_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
+#define CPF_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
+#define CPF_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
+#define CPF_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
+#define CPF_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
+#define CPF_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
+#define CPF_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
+#define CPF_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
+//CP_SD_CNTL
+#define CP_SD_CNTL__CPF_EN__SHIFT 0x0
+#define CP_SD_CNTL__CPG_EN__SHIFT 0x1
+#define CP_SD_CNTL__CPC_EN__SHIFT 0x2
+#define CP_SD_CNTL__RLC_EN__SHIFT 0x3
+#define CP_SD_CNTL__SPI_EN__SHIFT 0x4
+#define CP_SD_CNTL__WD_EN__SHIFT 0x5
+#define CP_SD_CNTL__IA_EN__SHIFT 0x6
+#define CP_SD_CNTL__PA_EN__SHIFT 0x7
+#define CP_SD_CNTL__RMI_EN__SHIFT 0x8
+#define CP_SD_CNTL__EA_EN__SHIFT 0x9
+#define CP_SD_CNTL__CPF_EN_MASK 0x00000001L
+#define CP_SD_CNTL__CPG_EN_MASK 0x00000002L
+#define CP_SD_CNTL__CPC_EN_MASK 0x00000004L
+#define CP_SD_CNTL__RLC_EN_MASK 0x00000008L
+#define CP_SD_CNTL__SPI_EN_MASK 0x00000010L
+#define CP_SD_CNTL__WD_EN_MASK 0x00000020L
+#define CP_SD_CNTL__IA_EN_MASK 0x00000040L
+#define CP_SD_CNTL__PA_EN_MASK 0x00000080L
+#define CP_SD_CNTL__RMI_EN_MASK 0x00000100L
+#define CP_SD_CNTL__EA_EN_MASK 0x00000200L
+//CP_SOFT_RESET_CNTL
+#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET__SHIFT 0x0
+#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET__SHIFT 0x1
+#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET__SHIFT 0x2
+#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET__SHIFT 0x3
+#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET__SHIFT 0x4
+#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET__SHIFT 0x5
+#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET__SHIFT 0x6
+#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET_MASK 0x00000001L
+#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET_MASK 0x00000002L
+#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET_MASK 0x00000004L
+#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET_MASK 0x00000008L
+#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET_MASK 0x00000010L
+#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET_MASK 0x00000020L
+#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET_MASK 0x00000040L
+//CP_CPC_GFX_CNTL
+#define CP_CPC_GFX_CNTL__QUEUEID__SHIFT 0x0
+#define CP_CPC_GFX_CNTL__PIPEID__SHIFT 0x3
+#define CP_CPC_GFX_CNTL__MEID__SHIFT 0x5
+#define CP_CPC_GFX_CNTL__VALID__SHIFT 0x7
+#define CP_CPC_GFX_CNTL__QUEUEID_MASK 0x00000007L
+#define CP_CPC_GFX_CNTL__PIPEID_MASK 0x00000018L
+#define CP_CPC_GFX_CNTL__MEID_MASK 0x00000060L
+#define CP_CPC_GFX_CNTL__VALID_MASK 0x00000080L
+
+
+// addressBlock: gc_cpphqddec
+//CP_HQD_GFX_CONTROL
+#define CP_HQD_GFX_CONTROL__MESSAGE__SHIFT 0x0
+#define CP_HQD_GFX_CONTROL__MISC__SHIFT 0x4
+#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT 0xf
+#define CP_HQD_GFX_CONTROL__MESSAGE_MASK 0x0000000FL
+#define CP_HQD_GFX_CONTROL__MISC_MASK 0x00007FF0L
+#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN_MASK 0x00008000L
+//CP_HQD_GFX_STATUS
+#define CP_HQD_GFX_STATUS__STATUS__SHIFT 0x0
+#define CP_HQD_GFX_STATUS__STATUS_MASK 0x0000FFFFL
+//CP_HPD_ROQ_OFFSETS
+#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0
+#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8
+#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10
+#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x00000007L
+#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x00003F00L
+#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x003F0000L
+//CP_HPD_STATUS0
+#define CP_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0
+#define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5
+#define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8
+#define CP_HPD_STATUS0__FETCHING_MQD__SHIFT 0x10
+#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB__SHIFT 0x11
+#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ__SHIFT 0x12
+#define CP_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT 0x14
+#define CP_HPD_STATUS0__FORCE_QUEUE__SHIFT 0x1f
+#define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x0000001FL
+#define CP_HPD_STATUS0__MAPPED_QUEUE_MASK 0x000000E0L
+#define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0x0000FF00L
+#define CP_HPD_STATUS0__FETCHING_MQD_MASK 0x00010000L
+#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB_MASK 0x00020000L
+#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ_MASK 0x00040000L
+#define CP_HPD_STATUS0__FORCE_QUEUE_STATE_MASK 0x01F00000L
+#define CP_HPD_STATUS0__FORCE_QUEUE_MASK 0x80000000L
+//CP_HPD_UTCL1_CNTL
+#define CP_HPD_UTCL1_CNTL__SELECT__SHIFT 0x0
+#define CP_HPD_UTCL1_CNTL__SELECT_MASK 0x0000000FL
+//CP_HPD_UTCL1_ERROR
+#define CP_HPD_UTCL1_ERROR__ADDR_HI__SHIFT 0x0
+#define CP_HPD_UTCL1_ERROR__TYPE__SHIFT 0x10
+#define CP_HPD_UTCL1_ERROR__VMID__SHIFT 0x14
+#define CP_HPD_UTCL1_ERROR__ADDR_HI_MASK 0x0000FFFFL
+#define CP_HPD_UTCL1_ERROR__TYPE_MASK 0x00010000L
+#define CP_HPD_UTCL1_ERROR__VMID_MASK 0x00F00000L
+//CP_HPD_UTCL1_ERROR_ADDR
+#define CP_HPD_UTCL1_ERROR_ADDR__ADDR__SHIFT 0xc
+#define CP_HPD_UTCL1_ERROR_ADDR__ADDR_MASK 0xFFFFF000L
+//CP_MQD_BASE_ADDR
+#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2
+#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL
+//CP_MQD_BASE_ADDR_HI
+#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
+#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL
+//CP_HQD_ACTIVE
+#define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0
+#define CP_HQD_ACTIVE__BUSY_GATE__SHIFT 0x1
+#define CP_HQD_ACTIVE__ACTIVE_MASK 0x00000001L
+#define CP_HQD_ACTIVE__BUSY_GATE_MASK 0x00000002L
+//CP_HQD_VMID
+#define CP_HQD_VMID__VMID__SHIFT 0x0
+#define CP_HQD_VMID__IB_VMID__SHIFT 0x8
+#define CP_HQD_VMID__VQID__SHIFT 0x10
+#define CP_HQD_VMID__VMID_MASK 0x0000000FL
+#define CP_HQD_VMID__IB_VMID_MASK 0x00000F00L
+#define CP_HQD_VMID__VQID_MASK 0x03FF0000L
+//CP_HQD_PERSISTENT_STATE
+#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0
+#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8
+#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN__SHIFT 0x15
+#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT 0x16
+#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN__SHIFT 0x17
+#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN__SHIFT 0x18
+#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN__SHIFT 0x19
+#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN__SHIFT 0x1a
+#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN__SHIFT 0x1b
+#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT 0x1c
+#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d
+#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT 0x1e
+#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f
+#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x00000001L
+#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x0003FF00L
+#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN_MASK 0x00200000L
+#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN_MASK 0x00400000L
+#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN_MASK 0x00800000L
+#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN_MASK 0x01000000L
+#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN_MASK 0x02000000L
+#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN_MASK 0x04000000L
+#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN_MASK 0x08000000L
+#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK 0x10000000L
+#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK 0x20000000L
+#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK 0x40000000L
+#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000L
+//CP_HQD_PIPE_PRIORITY
+#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0
+#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x00000003L
+//CP_HQD_QUEUE_PRIORITY
+#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0
+#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0x0000000FL
+//CP_HQD_QUANTUM
+#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0
+#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4
+#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8
+#define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f
+#define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x00000001L
+#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x00000010L
+#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x00003F00L
+#define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000L
+//CP_HQD_PQ_BASE
+#define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0
+#define CP_HQD_PQ_BASE__ADDR_MASK 0xFFFFFFFFL
+//CP_HQD_PQ_BASE_HI
+#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0
+#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0x000000FFL
+//CP_HQD_PQ_RPTR
+#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0
+#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xFFFFFFFFL
+//CP_HQD_PQ_RPTR_REPORT_ADDR
+#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2
+#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xFFFFFFFCL
+//CP_HQD_PQ_RPTR_REPORT_ADDR_HI
+#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0
+#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0x0000FFFFL
+//CP_HQD_PQ_WPTR_POLL_ADDR
+#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x3
+#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xFFFFFFF8L
+//CP_HQD_PQ_WPTR_POLL_ADDR_HI
+#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0
+#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0x0000FFFFL
+//CP_HQD_PQ_DOORBELL_CONTROL
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK 0x00000001L
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000L
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000L
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L
+//CP_HQD_PQ_CONTROL
+#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0
+#define CP_HQD_PQ_CONTROL__WPTR_CARRY__SHIFT 0x6
+#define CP_HQD_PQ_CONTROL__RPTR_CARRY__SHIFT 0x7
+#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8
+#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT 0xe
+#define CP_HQD_PQ_CONTROL__PQ_EMPTY__SHIFT 0xf
+#define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN__SHIFT 0x10
+#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x11
+#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14
+#define CP_HQD_PQ_CONTROL__TMZ__SHIFT 0x16
+#define CP_HQD_PQ_CONTROL__EXE_DISABLE__SHIFT 0x17
+#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18
+#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19
+#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b
+#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c
+#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d
+#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e
+#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f
+#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x0000003FL
+#define CP_HQD_PQ_CONTROL__WPTR_CARRY_MASK 0x00000040L
+#define CP_HQD_PQ_CONTROL__RPTR_CARRY_MASK 0x00000080L
+#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x00003F00L
+#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN_MASK 0x00004000L
+#define CP_HQD_PQ_CONTROL__PQ_EMPTY_MASK 0x00008000L
+#define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN_MASK 0x00010000L
+#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x00060000L
+#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x00300000L
+#define CP_HQD_PQ_CONTROL__TMZ_MASK 0x00400000L
+#define CP_HQD_PQ_CONTROL__EXE_DISABLE_MASK 0x00800000L
+#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x01000000L
+#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x06000000L
+#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x08000000L
+#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000L
+#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK 0x20000000L
+#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000L
+#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000L
+//CP_HQD_IB_BASE_ADDR
+#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2
+#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xFFFFFFFCL
+//CP_HQD_IB_BASE_ADDR_HI
+#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0
+#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0x0000FFFFL
+//CP_HQD_IB_RPTR
+#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0
+#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0x000FFFFFL
+//CP_HQD_IB_CONTROL
+#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0
+#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14
+#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT 0x17
+#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18
+#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f
+#define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0x000FFFFFL
+#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x00300000L
+#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE_MASK 0x00800000L
+#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x01000000L
+#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000L
+//CP_HQD_IQ_TIMER
+#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0
+#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8
+#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb
+#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc
+#define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe
+#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10
+#define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16
+#define CP_HQD_IQ_TIMER__EXE_DISABLE__SHIFT 0x17
+#define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18
+#define CP_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT 0x19
+#define CP_HQD_IQ_TIMER__REARM_TIMER__SHIFT 0x1c
+#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d
+#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e
+#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f
+#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0x000000FFL
+#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x00000700L
+#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x00000800L
+#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x00003000L
+#define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0x0000C000L
+#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x003F0000L
+#define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x00400000L
+#define CP_HQD_IQ_TIMER__EXE_DISABLE_MASK 0x00800000L
+#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x01000000L
+#define CP_HQD_IQ_TIMER__QUEUE_TYPE_MASK 0x02000000L
+#define CP_HQD_IQ_TIMER__REARM_TIMER_MASK 0x10000000L
+#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000L
+#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000L
+#define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000L
+//CP_HQD_IQ_RPTR
+#define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0
+#define CP_HQD_IQ_RPTR__OFFSET_MASK 0x0000003FL
+//CP_HQD_DEQUEUE_REQUEST
+#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0
+#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4
+#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8
+#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9
+#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa
+#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x00000007L
+#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x00000010L
+#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x00000100L
+#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x00000200L
+#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x00000400L
+//CP_HQD_DMA_OFFLOAD
+#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
+#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L
+//CP_HQD_OFFLOAD
+#define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
+#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1
+#define CP_HQD_OFFLOAD__AQL_OFFLOAD__SHIFT 0x2
+#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN__SHIFT 0x3
+#define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4
+#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5
+#define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L
+#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x00000002L
+#define CP_HQD_OFFLOAD__AQL_OFFLOAD_MASK 0x00000004L
+#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN_MASK 0x00000008L
+#define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK 0x00000010L
+#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x00000020L
+//CP_HQD_SEMA_CMD
+#define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0
+#define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1
+#define CP_HQD_SEMA_CMD__RETRY_MASK 0x00000001L
+#define CP_HQD_SEMA_CMD__RESULT_MASK 0x00000006L
+//CP_HQD_MSG_TYPE
+#define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0
+#define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT 0x4
+#define CP_HQD_MSG_TYPE__ACTION_MASK 0x00000007L
+#define CP_HQD_MSG_TYPE__SAVE_STATE_MASK 0x00000070L
+//CP_HQD_ATOMIC0_PREOP_LO
+#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0
+#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL
+//CP_HQD_ATOMIC0_PREOP_HI
+#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0
+#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL
+//CP_HQD_ATOMIC1_PREOP_LO
+#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0
+#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL
+//CP_HQD_ATOMIC1_PREOP_HI
+#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0
+#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL
+//CP_HQD_HQ_SCHEDULER0
+#define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT 0x0
+#define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK 0xFFFFFFFFL
+//CP_HQD_HQ_STATUS0
+#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0
+#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT 0x2
+#define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT 0x4
+#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT 0x7
+#define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8
+#define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT 0x9
+#define CP_HQD_HQ_STATUS0__RSVR_29_10__SHIFT 0xa
+#define CP_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT 0x1e
+#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN__SHIFT 0x1f
+#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x00000003L
+#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK 0x0000000CL
+#define CP_HQD_HQ_STATUS0__RSV_6_4_MASK 0x00000070L
+#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK 0x00000080L
+#define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK 0x00000100L
+#define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK 0x00000200L
+#define CP_HQD_HQ_STATUS0__RSVR_29_10_MASK 0x3FFFFC00L
+#define CP_HQD_HQ_STATUS0__QUEUE_IDLE_MASK 0x40000000L
+#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN_MASK 0x80000000L
+//CP_HQD_HQ_CONTROL0
+#define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT 0x0
+#define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xFFFFFFFFL
+//CP_HQD_HQ_SCHEDULER1
+#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0
+#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xFFFFFFFFL
+//CP_MQD_CONTROL
+#define CP_MQD_CONTROL__VMID__SHIFT 0x0
+#define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8
+#define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc
+#define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd
+#define CP_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17
+#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18
+#define CP_MQD_CONTROL__VMID_MASK 0x0000000FL
+#define CP_MQD_CONTROL__PRIV_STATE_MASK 0x00000100L
+#define CP_MQD_CONTROL__PROCESSING_MQD_MASK 0x00001000L
+#define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x00002000L
+#define CP_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L
+#define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x01000000L
+//CP_HQD_HQ_STATUS1
+#define CP_HQD_HQ_STATUS1__STATUS__SHIFT 0x0
+#define CP_HQD_HQ_STATUS1__STATUS_MASK 0xFFFFFFFFL
+//CP_HQD_HQ_CONTROL1
+#define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT 0x0
+#define CP_HQD_HQ_CONTROL1__CONTROL_MASK 0xFFFFFFFFL
+//CP_HQD_EOP_BASE_ADDR
+#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//CP_HQD_EOP_BASE_ADDR_HI
+#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
+#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x000000FFL
+//CP_HQD_EOP_CONTROL
+#define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0
+#define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8
+#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc
+#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd
+#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe
+#define CP_HQD_EOP_CONTROL__HALT_FETCHER__SHIFT 0x15
+#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN__SHIFT 0x16
+#define CP_HQD_EOP_CONTROL__EXE_DISABLE__SHIFT 0x17
+#define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18
+#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT 0x1d
+#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f
+#define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x0000003FL
+#define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK 0x00000100L
+#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x00001000L
+#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x00002000L
+#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x00004000L
+#define CP_HQD_EOP_CONTROL__HALT_FETCHER_MASK 0x00200000L
+#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN_MASK 0x00400000L
+#define CP_HQD_EOP_CONTROL__EXE_DISABLE_MASK 0x00800000L
+#define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK 0x01000000L
+#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK 0x60000000L
+#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000L
+//CP_HQD_EOP_RPTR
+#define CP_HQD_EOP_RPTR__RPTR__SHIFT 0x0
+#define CP_HQD_EOP_RPTR__RESET_FETCHER__SHIFT 0x1c
+#define CP_HQD_EOP_RPTR__DEQUEUE_PEND__SHIFT 0x1d
+#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT 0x1e
+#define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT 0x1f
+#define CP_HQD_EOP_RPTR__RPTR_MASK 0x00001FFFL
+#define CP_HQD_EOP_RPTR__RESET_FETCHER_MASK 0x10000000L
+#define CP_HQD_EOP_RPTR__DEQUEUE_PEND_MASK 0x20000000L
+#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000L
+#define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK 0x80000000L
+//CP_HQD_EOP_WPTR
+#define CP_HQD_EOP_WPTR__WPTR__SHIFT 0x0
+#define CP_HQD_EOP_WPTR__EOP_EMPTY__SHIFT 0xf
+#define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT 0x10
+#define CP_HQD_EOP_WPTR__WPTR_MASK 0x00001FFFL
+#define CP_HQD_EOP_WPTR__EOP_EMPTY_MASK 0x00008000L
+#define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK 0x1FFF0000L
+//CP_HQD_EOP_EVENTS
+#define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT 0x0
+#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT 0x10
+#define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK 0x00000FFFL
+#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK 0x00010000L
+//CP_HQD_CTX_SAVE_BASE_ADDR_LO
+#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc
+#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xFFFFF000L
+//CP_HQD_CTX_SAVE_BASE_ADDR_HI
+#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
+//CP_HQD_CTX_SAVE_CONTROL
+#define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3
+#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT 0x17
+#define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK 0x00000008L
+#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE_MASK 0x00800000L
+//CP_HQD_CNTL_STACK_OFFSET
+#define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2
+#define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK 0x0000FFFCL
+//CP_HQD_CNTL_STACK_SIZE
+#define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT 0xc
+#define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK 0x0000F000L
+//CP_HQD_WG_STATE_OFFSET
+#define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT 0x2
+#define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x07FFFFFCL
+//CP_HQD_CTX_SAVE_SIZE
+#define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT 0xc
+#define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK 0x07FFF000L
+//CP_HQD_GDS_RESOURCE_STATE
+#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT 0x0
+#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT 0x1
+#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT 0x4
+#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT 0xc
+#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK 0x00000001L
+#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK 0x00000002L
+#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK 0x000003F0L
+#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK 0x0003F000L
+//CP_HQD_ERROR
+#define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT 0x0
+#define CP_HQD_ERROR__SUA_ERROR__SHIFT 0x4
+#define CP_HQD_ERROR__AQL_ERROR__SHIFT 0x5
+#define CP_HQD_ERROR__PQ_UTCL1_ERROR__SHIFT 0x8
+#define CP_HQD_ERROR__IB_UTCL1_ERROR__SHIFT 0x9
+#define CP_HQD_ERROR__EOP_UTCL1_ERROR__SHIFT 0xa
+#define CP_HQD_ERROR__IQ_UTCL1_ERROR__SHIFT 0xb
+#define CP_HQD_ERROR__RRPT_UTCL1_ERROR__SHIFT 0xc
+#define CP_HQD_ERROR__WPP_UTCL1_ERROR__SHIFT 0xd
+#define CP_HQD_ERROR__SEM_UTCL1_ERROR__SHIFT 0xe
+#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0xf
+#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x10
+#define CP_HQD_ERROR__SR_UTCL1_ERROR__SHIFT 0x11
+#define CP_HQD_ERROR__QU_UTCL1_ERROR__SHIFT 0x12
+#define CP_HQD_ERROR__TC_UTCL1_ERROR__SHIFT 0x13
+#define CP_HQD_ERROR__EDC_ERROR_ID_MASK 0x0000000FL
+#define CP_HQD_ERROR__SUA_ERROR_MASK 0x00000010L
+#define CP_HQD_ERROR__AQL_ERROR_MASK 0x00000020L
+#define CP_HQD_ERROR__PQ_UTCL1_ERROR_MASK 0x00000100L
+#define CP_HQD_ERROR__IB_UTCL1_ERROR_MASK 0x00000200L
+#define CP_HQD_ERROR__EOP_UTCL1_ERROR_MASK 0x00000400L
+#define CP_HQD_ERROR__IQ_UTCL1_ERROR_MASK 0x00000800L
+#define CP_HQD_ERROR__RRPT_UTCL1_ERROR_MASK 0x00001000L
+#define CP_HQD_ERROR__WPP_UTCL1_ERROR_MASK 0x00002000L
+#define CP_HQD_ERROR__SEM_UTCL1_ERROR_MASK 0x00004000L
+#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00008000L
+#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00010000L
+#define CP_HQD_ERROR__SR_UTCL1_ERROR_MASK 0x00020000L
+#define CP_HQD_ERROR__QU_UTCL1_ERROR_MASK 0x00040000L
+#define CP_HQD_ERROR__TC_UTCL1_ERROR_MASK 0x00080000L
+//CP_HQD_EOP_WPTR_MEM
+#define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0
+#define CP_HQD_EOP_WPTR_MEM__WPTR_MASK 0x00001FFFL
+//CP_HQD_AQL_CONTROL
+#define CP_HQD_AQL_CONTROL__CONTROL0__SHIFT 0x0
+#define CP_HQD_AQL_CONTROL__CONTROL0_EN__SHIFT 0xf
+#define CP_HQD_AQL_CONTROL__CONTROL1__SHIFT 0x10
+#define CP_HQD_AQL_CONTROL__CONTROL1_EN__SHIFT 0x1f
+#define CP_HQD_AQL_CONTROL__CONTROL0_MASK 0x00007FFFL
+#define CP_HQD_AQL_CONTROL__CONTROL0_EN_MASK 0x00008000L
+#define CP_HQD_AQL_CONTROL__CONTROL1_MASK 0x7FFF0000L
+#define CP_HQD_AQL_CONTROL__CONTROL1_EN_MASK 0x80000000L
+//CP_HQD_PQ_WPTR_LO
+#define CP_HQD_PQ_WPTR_LO__OFFSET__SHIFT 0x0
+#define CP_HQD_PQ_WPTR_LO__OFFSET_MASK 0xFFFFFFFFL
+//CP_HQD_PQ_WPTR_HI
+#define CP_HQD_PQ_WPTR_HI__DATA__SHIFT 0x0
+#define CP_HQD_PQ_WPTR_HI__DATA_MASK 0xFFFFFFFFL
+
+
+
+
+// addressBlock: gc_didtdec
+//DIDT_IND_INDEX
+#define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT 0x0
+#define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK 0xFFFFFFFFL
+//DIDT_IND_DATA
+#define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT 0x0
+#define DIDT_IND_DATA__DIDT_IND_DATA_MASK 0xFFFFFFFFL
+//DIDT_INDEX_AUTO_INCR_EN
+#define DIDT_INDEX_AUTO_INCR_EN__DIDT_INDEX_AUTO_INCR_EN__SHIFT 0x0
+#define DIDT_INDEX_AUTO_INCR_EN__DIDT_INDEX_AUTO_INCR_EN_MASK 0x00000001L
+
+
+// addressBlock: gc_ea_gceadec
+//GCEA_DRAM_RD_CLI2GRP_MAP0
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//GCEA_DRAM_RD_CLI2GRP_MAP1
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//GCEA_DRAM_WR_CLI2GRP_MAP0
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//GCEA_DRAM_WR_CLI2GRP_MAP1
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//GCEA_DRAM_RD_GRP2VC_MAP
+#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
+#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
+#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
+#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
+#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
+#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
+#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
+#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
+//GCEA_DRAM_WR_GRP2VC_MAP
+#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
+#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
+#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
+#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
+#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
+#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
+#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
+#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
+//GCEA_DRAM_RD_LAZY
+#define GCEA_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0
+#define GCEA_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3
+#define GCEA_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6
+#define GCEA_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9
+#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
+#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
+#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b
+#define GCEA_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L
+#define GCEA_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L
+#define GCEA_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L
+#define GCEA_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L
+#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
+#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
+#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L
+//GCEA_DRAM_WR_LAZY
+#define GCEA_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0
+#define GCEA_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3
+#define GCEA_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6
+#define GCEA_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9
+#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
+#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
+#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b
+#define GCEA_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L
+#define GCEA_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L
+#define GCEA_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L
+#define GCEA_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L
+#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
+#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
+#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L
+//GCEA_DRAM_RD_CAM_CNTL
+#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
+#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
+#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
+#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
+#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
+#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
+#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
+#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
+#define GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c
+#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
+#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
+#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
+#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
+#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
+#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
+#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
+#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
+#define GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L
+//GCEA_DRAM_WR_CAM_CNTL
+#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
+#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
+#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
+#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
+#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
+#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
+#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
+#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
+#define GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c
+#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
+#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
+#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
+#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
+#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
+#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
+#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
+#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
+#define GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L
+//GCEA_DRAM_PAGE_BURST
+#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0
+#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8
+#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10
+#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18
+#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL
+#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
+#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
+#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L
+//GCEA_DRAM_RD_PRI_AGE
+#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//GCEA_DRAM_WR_PRI_AGE
+#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//GCEA_DRAM_RD_PRI_QUEUING
+#define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//GCEA_DRAM_WR_PRI_QUEUING
+#define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//GCEA_DRAM_RD_PRI_FIXED
+#define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//GCEA_DRAM_WR_PRI_FIXED
+#define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//GCEA_DRAM_RD_PRI_URGENCY
+#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//GCEA_DRAM_WR_PRI_URGENCY
+#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//GCEA_DRAM_RD_PRI_QUANT_PRI1
+#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GCEA_DRAM_RD_PRI_QUANT_PRI2
+#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GCEA_DRAM_RD_PRI_QUANT_PRI3
+#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GCEA_DRAM_WR_PRI_QUANT_PRI1
+#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GCEA_DRAM_WR_PRI_QUANT_PRI2
+#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GCEA_DRAM_WR_PRI_QUANT_PRI3
+#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GCEA_ADDRNORM_BASE_ADDR0
+#define GCEA_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0
+#define GCEA_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2
+#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7
+#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9
+#define GCEA_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc
+#define GCEA_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L
+#define GCEA_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L
+#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define GCEA_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L
+//GCEA_ADDRNORM_LIMIT_ADDR0
+#define GCEA_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0
+#define GCEA_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc
+#define GCEA_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL
+#define GCEA_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L
+//GCEA_ADDRNORM_BASE_ADDR1
+#define GCEA_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0
+#define GCEA_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2
+#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7
+#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9
+#define GCEA_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc
+#define GCEA_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L
+#define GCEA_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L
+#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define GCEA_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L
+//GCEA_ADDRNORM_LIMIT_ADDR1
+#define GCEA_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0
+#define GCEA_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc
+#define GCEA_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL
+#define GCEA_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L
+//GCEA_ADDRNORM_OFFSET_ADDR1
+#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0
+#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0xc
+#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L
+#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0x00FFF000L
+//GCEA_ADDRNORM_BASE_ADDR2
+#define GCEA_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0
+#define GCEA_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define GCEA_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2
+#define GCEA_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x7
+#define GCEA_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define GCEA_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9
+#define GCEA_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc
+#define GCEA_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L
+#define GCEA_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define GCEA_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define GCEA_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x00000080L
+#define GCEA_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define GCEA_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define GCEA_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L
+//GCEA_ADDRNORM_LIMIT_ADDR2
+#define GCEA_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0
+#define GCEA_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc
+#define GCEA_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL
+#define GCEA_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L
+//GCEA_ADDRNORM_BASE_ADDR3
+#define GCEA_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0
+#define GCEA_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define GCEA_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2
+#define GCEA_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x7
+#define GCEA_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define GCEA_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9
+#define GCEA_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc
+#define GCEA_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L
+#define GCEA_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define GCEA_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define GCEA_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x00000080L
+#define GCEA_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define GCEA_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define GCEA_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L
+//GCEA_ADDRNORM_LIMIT_ADDR3
+#define GCEA_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0
+#define GCEA_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc
+#define GCEA_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL
+#define GCEA_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L
+//GCEA_ADDRNORM_OFFSET_ADDR3
+#define GCEA_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0
+#define GCEA_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0xc
+#define GCEA_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L
+#define GCEA_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0x00FFF000L
+//GCEA_ADDRNORM_MEGABASE_ADDR0
+#define GCEA_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0
+#define GCEA_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define GCEA_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2
+#define GCEA_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7
+#define GCEA_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define GCEA_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9
+#define GCEA_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR__SHIFT 0xc
+#define GCEA_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L
+#define GCEA_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define GCEA_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define GCEA_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L
+#define GCEA_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define GCEA_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define GCEA_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L
+//GCEA_ADDRNORM_MEGALIMIT_ADDR0
+#define GCEA_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0
+#define GCEA_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc
+#define GCEA_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL
+#define GCEA_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L
+//GCEA_ADDRNORM_MEGABASE_ADDR1
+#define GCEA_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0
+#define GCEA_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define GCEA_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2
+#define GCEA_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7
+#define GCEA_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define GCEA_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9
+#define GCEA_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR__SHIFT 0xc
+#define GCEA_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L
+#define GCEA_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define GCEA_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define GCEA_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L
+#define GCEA_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define GCEA_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define GCEA_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L
+//GCEA_ADDRNORM_MEGALIMIT_ADDR1
+#define GCEA_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0
+#define GCEA_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc
+#define GCEA_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL
+#define GCEA_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L
+//GCEA_ADDRNORMDRAM_HOLE_CNTL
+#define GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0
+#define GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7
+#define GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L
+#define GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L
+//GCEA_ADDRNORMGMI_HOLE_CNTL
+#define GCEA_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0
+#define GCEA_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7
+#define GCEA_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L
+#define GCEA_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L
+//GCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG
+#define GCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0
+#define GCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6
+#define GCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL
+#define GCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L
+//GCEA_ADDRNORMGMI_NP2_CHANNEL_CFG
+#define GCEA_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0
+#define GCEA_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6
+#define GCEA_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL
+#define GCEA_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L
+//GCEA_ADDRDEC_BANK_CFG
+#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0
+#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6
+#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc
+#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf
+#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12
+#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13
+#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL
+#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L
+#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L
+#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L
+#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L
+#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L
+//GCEA_ADDRDEC_MISC_CFG
+#define GCEA_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0
+#define GCEA_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1
+#define GCEA_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2
+#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8
+#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9
+#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc
+#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11
+#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16
+#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18
+#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a
+#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d
+#define GCEA_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L
+#define GCEA_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L
+#define GCEA_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L
+#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L
+#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L
+#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L
+#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L
+#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L
+#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L
+#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L
+#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L
+//GCEA_ADDRDECDRAM_HARVEST_ENABLE
+#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0
+#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1
+#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2
+#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3
+#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4
+#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5
+#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L
+#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L
+#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L
+#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L
+#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L
+#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L
+//GCEA_ADDRDECGMI_HARVEST_ENABLE
+#define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0
+#define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1
+#define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2
+#define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3
+#define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4
+#define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5
+#define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L
+#define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L
+#define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L
+#define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L
+#define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L
+#define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L
+//GCEA_ADDRDEC0_BASE_ADDR_CS0
+#define GCEA_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC0_BASE_ADDR_CS1
+#define GCEA_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC0_BASE_ADDR_CS2
+#define GCEA_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC0_BASE_ADDR_CS3
+#define GCEA_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC0_BASE_ADDR_SECCS0
+#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC0_BASE_ADDR_SECCS1
+#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC0_BASE_ADDR_SECCS2
+#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC0_BASE_ADDR_SECCS3
+#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC0_ADDR_MASK_CS01
+#define GCEA_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
+#define GCEA_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC0_ADDR_MASK_CS23
+#define GCEA_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
+#define GCEA_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC0_ADDR_MASK_SECCS01
+#define GCEA_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
+#define GCEA_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC0_ADDR_MASK_SECCS23
+#define GCEA_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
+#define GCEA_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC0_ADDR_CFG_CS01
+#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1
+#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
+#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
+#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
+#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
+#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
+#define GCEA_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f
+#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
+#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
+#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
+#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
+#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
+#define GCEA_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L
+//GCEA_ADDRDEC0_ADDR_CFG_CS23
+#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1
+#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
+#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
+#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
+#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
+#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
+#define GCEA_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f
+#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
+#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
+#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
+#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
+#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
+#define GCEA_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L
+//GCEA_ADDRDEC0_ADDR_SEL_CS01
+#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0
+#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4
+#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8
+#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc
+#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10
+#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
+#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
+#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
+#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
+#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
+#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
+#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L
+#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
+#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
+//GCEA_ADDRDEC0_ADDR_SEL_CS23
+#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0
+#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4
+#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8
+#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc
+#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10
+#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
+#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
+#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
+#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
+#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
+#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
+#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L
+#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
+#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
+//GCEA_ADDRDEC0_ADDR_SEL2_CS01
+#define GCEA_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0
+#define GCEA_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc
+#define GCEA_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL
+#define GCEA_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L
+//GCEA_ADDRDEC0_ADDR_SEL2_CS23
+#define GCEA_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0
+#define GCEA_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc
+#define GCEA_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL
+#define GCEA_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L
+//GCEA_ADDRDEC0_COL_SEL_LO_CS01
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
+//GCEA_ADDRDEC0_COL_SEL_LO_CS23
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
+//GCEA_ADDRDEC0_COL_SEL_HI_CS01
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
+//GCEA_ADDRDEC0_COL_SEL_HI_CS23
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
+//GCEA_ADDRDEC0_RM_SEL_CS01
+#define GCEA_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0
+#define GCEA_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4
+#define GCEA_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8
+#define GCEA_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
+#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define GCEA_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL
+#define GCEA_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L
+#define GCEA_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L
+#define GCEA_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
+#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//GCEA_ADDRDEC0_RM_SEL_CS23
+#define GCEA_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0
+#define GCEA_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4
+#define GCEA_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8
+#define GCEA_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
+#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define GCEA_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL
+#define GCEA_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L
+#define GCEA_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L
+#define GCEA_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
+#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//GCEA_ADDRDEC0_RM_SEL_SECCS01
+#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0
+#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4
+#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8
+#define GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
+#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
+#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
+#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
+#define GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
+#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//GCEA_ADDRDEC0_RM_SEL_SECCS23
+#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0
+#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4
+#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8
+#define GCEA_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
+#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
+#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
+#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
+#define GCEA_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
+#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//GCEA_ADDRDEC1_BASE_ADDR_CS0
+#define GCEA_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC1_BASE_ADDR_CS1
+#define GCEA_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC1_BASE_ADDR_CS2
+#define GCEA_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC1_BASE_ADDR_CS3
+#define GCEA_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC1_BASE_ADDR_SECCS0
+#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC1_BASE_ADDR_SECCS1
+#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC1_BASE_ADDR_SECCS2
+#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC1_BASE_ADDR_SECCS3
+#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC1_ADDR_MASK_CS01
+#define GCEA_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
+#define GCEA_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC1_ADDR_MASK_CS23
+#define GCEA_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
+#define GCEA_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC1_ADDR_MASK_SECCS01
+#define GCEA_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
+#define GCEA_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC1_ADDR_MASK_SECCS23
+#define GCEA_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
+#define GCEA_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC1_ADDR_CFG_CS01
+#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1
+#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
+#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
+#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
+#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
+#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
+#define GCEA_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f
+#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
+#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
+#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
+#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
+#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
+#define GCEA_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L
+//GCEA_ADDRDEC1_ADDR_CFG_CS23
+#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1
+#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
+#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
+#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
+#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
+#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
+#define GCEA_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f
+#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
+#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
+#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
+#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
+#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
+#define GCEA_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L
+//GCEA_ADDRDEC1_ADDR_SEL_CS01
+#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0
+#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4
+#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8
+#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc
+#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10
+#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
+#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
+#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
+#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
+#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
+#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
+#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L
+#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
+#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
+//GCEA_ADDRDEC1_ADDR_SEL_CS23
+#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0
+#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4
+#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8
+#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc
+#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10
+#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
+#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
+#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
+#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
+#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
+#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
+#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L
+#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
+#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
+//GCEA_ADDRDEC1_ADDR_SEL2_CS01
+#define GCEA_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0
+#define GCEA_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc
+#define GCEA_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL
+#define GCEA_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L
+//GCEA_ADDRDEC1_ADDR_SEL2_CS23
+#define GCEA_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0
+#define GCEA_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc
+#define GCEA_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL
+#define GCEA_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L
+//GCEA_ADDRDEC1_COL_SEL_LO_CS01
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
+//GCEA_ADDRDEC1_COL_SEL_LO_CS23
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
+//GCEA_ADDRDEC1_COL_SEL_HI_CS01
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
+//GCEA_ADDRDEC1_COL_SEL_HI_CS23
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
+//GCEA_ADDRDEC1_RM_SEL_CS01
+#define GCEA_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0
+#define GCEA_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4
+#define GCEA_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8
+#define GCEA_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
+#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define GCEA_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL
+#define GCEA_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L
+#define GCEA_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L
+#define GCEA_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
+#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//GCEA_ADDRDEC1_RM_SEL_CS23
+#define GCEA_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0
+#define GCEA_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4
+#define GCEA_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8
+#define GCEA_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
+#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define GCEA_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL
+#define GCEA_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L
+#define GCEA_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L
+#define GCEA_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
+#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//GCEA_ADDRDEC1_RM_SEL_SECCS01
+#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0
+#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4
+#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8
+#define GCEA_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
+#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
+#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
+#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
+#define GCEA_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
+#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//GCEA_ADDRDEC1_RM_SEL_SECCS23
+#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0
+#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4
+#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8
+#define GCEA_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
+#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
+#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
+#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
+#define GCEA_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
+#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//GCEA_ADDRDEC2_BASE_ADDR_CS0
+#define GCEA_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC2_BASE_ADDR_CS1
+#define GCEA_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC2_BASE_ADDR_CS2
+#define GCEA_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC2_BASE_ADDR_CS3
+#define GCEA_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC2_BASE_ADDR_SECCS0
+#define GCEA_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC2_BASE_ADDR_SECCS1
+#define GCEA_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC2_BASE_ADDR_SECCS2
+#define GCEA_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC2_BASE_ADDR_SECCS3
+#define GCEA_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC2_ADDR_MASK_CS01
+#define GCEA_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
+#define GCEA_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC2_ADDR_MASK_CS23
+#define GCEA_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
+#define GCEA_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC2_ADDR_MASK_SECCS01
+#define GCEA_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
+#define GCEA_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC2_ADDR_MASK_SECCS23
+#define GCEA_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
+#define GCEA_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC2_ADDR_CFG_CS01
+#define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1
+#define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
+#define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
+#define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
+#define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
+#define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
+#define GCEA_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f
+#define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
+#define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
+#define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
+#define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
+#define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
+#define GCEA_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L
+//GCEA_ADDRDEC2_ADDR_CFG_CS23
+#define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1
+#define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
+#define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
+#define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
+#define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
+#define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
+#define GCEA_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f
+#define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
+#define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
+#define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
+#define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
+#define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
+#define GCEA_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L
+//GCEA_ADDRDEC2_ADDR_SEL_CS01
+#define GCEA_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0
+#define GCEA_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4
+#define GCEA_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8
+#define GCEA_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc
+#define GCEA_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10
+#define GCEA_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
+#define GCEA_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
+#define GCEA_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
+#define GCEA_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
+#define GCEA_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
+#define GCEA_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
+#define GCEA_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L
+#define GCEA_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
+#define GCEA_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
+//GCEA_ADDRDEC2_ADDR_SEL_CS23
+#define GCEA_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0
+#define GCEA_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4
+#define GCEA_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8
+#define GCEA_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc
+#define GCEA_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10
+#define GCEA_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
+#define GCEA_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
+#define GCEA_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
+#define GCEA_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
+#define GCEA_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
+#define GCEA_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
+#define GCEA_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L
+#define GCEA_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
+#define GCEA_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
+//GCEA_ADDRDEC2_ADDR_SEL2_CS01
+#define GCEA_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0
+#define GCEA_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc
+#define GCEA_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL
+#define GCEA_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L
+//GCEA_ADDRDEC2_ADDR_SEL2_CS23
+#define GCEA_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0
+#define GCEA_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc
+#define GCEA_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL
+#define GCEA_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L
+//GCEA_ADDRDEC2_COL_SEL_LO_CS01
+#define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0
+#define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4
+#define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8
+#define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc
+#define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10
+#define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14
+#define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18
+#define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
+#define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
+#define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
+#define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
+#define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
+#define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
+#define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
+#define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
+#define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
+//GCEA_ADDRDEC2_COL_SEL_LO_CS23
+#define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0
+#define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4
+#define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8
+#define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc
+#define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10
+#define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14
+#define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18
+#define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
+#define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
+#define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
+#define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
+#define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
+#define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
+#define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
+#define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
+#define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
+//GCEA_ADDRDEC2_COL_SEL_HI_CS01
+#define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0
+#define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4
+#define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8
+#define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc
+#define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10
+#define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14
+#define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18
+#define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
+#define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
+#define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
+#define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
+#define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
+#define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
+#define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
+#define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
+#define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
+//GCEA_ADDRDEC2_COL_SEL_HI_CS23
+#define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0
+#define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4
+#define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8
+#define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc
+#define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10
+#define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14
+#define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18
+#define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
+#define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
+#define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
+#define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
+#define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
+#define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
+#define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
+#define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
+#define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
+//GCEA_ADDRDEC2_RM_SEL_CS01
+#define GCEA_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0
+#define GCEA_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4
+#define GCEA_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8
+#define GCEA_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
+#define GCEA_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define GCEA_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define GCEA_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL
+#define GCEA_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L
+#define GCEA_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L
+#define GCEA_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
+#define GCEA_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define GCEA_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//GCEA_ADDRDEC2_RM_SEL_CS23
+#define GCEA_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0
+#define GCEA_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4
+#define GCEA_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8
+#define GCEA_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
+#define GCEA_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define GCEA_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define GCEA_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL
+#define GCEA_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L
+#define GCEA_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L
+#define GCEA_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
+#define GCEA_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define GCEA_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//GCEA_ADDRDEC2_RM_SEL_SECCS01
+#define GCEA_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0
+#define GCEA_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4
+#define GCEA_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8
+#define GCEA_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
+#define GCEA_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define GCEA_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define GCEA_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
+#define GCEA_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
+#define GCEA_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
+#define GCEA_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
+#define GCEA_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define GCEA_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//GCEA_ADDRDEC2_RM_SEL_SECCS23
+#define GCEA_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0
+#define GCEA_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4
+#define GCEA_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8
+#define GCEA_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
+#define GCEA_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define GCEA_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define GCEA_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
+#define GCEA_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
+#define GCEA_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
+#define GCEA_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
+#define GCEA_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define GCEA_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//GCEA_ADDRNORMDRAM_GLOBAL_CNTL
+//GCEA_ADDRNORMGMI_GLOBAL_CNTL
+//GCEA_ADDRNORM_MEGACONTROL_ADDR0
+#define GCEA_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0
+#define GCEA_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL
+//GCEA_ADDRNORM_MEGACONTROL_ADDR1
+#define GCEA_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0
+#define GCEA_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL
+//GCEA_ADDRNORMDRAM_MASKING
+#define GCEA_ADDRNORMDRAM_MASKING__ADDRHI_MASK__SHIFT 0x0
+#define GCEA_ADDRNORMDRAM_MASKING__ADDRHI_MASK_MASK 0x00000FFFL
+//GCEA_ADDRNORMGMI_MASKING
+#define GCEA_ADDRNORMGMI_MASKING__ADDRHI_MASK__SHIFT 0x0
+#define GCEA_ADDRNORMGMI_MASKING__ADDRHI_MASK_MASK 0x00000FFFL
+//GCEA_IO_RD_CLI2GRP_MAP0
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//GCEA_IO_RD_CLI2GRP_MAP1
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//GCEA_IO_WR_CLI2GRP_MAP0
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//GCEA_IO_WR_CLI2GRP_MAP1
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//GCEA_IO_RD_COMBINE_FLUSH
+#define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0
+#define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4
+#define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8
+#define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc
+#define GCEA_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10
+#define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL
+#define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L
+#define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L
+#define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L
+#define GCEA_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L
+//GCEA_IO_WR_COMBINE_FLUSH
+#define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0
+#define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4
+#define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8
+#define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc
+#define GCEA_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10
+#define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL
+#define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L
+#define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L
+#define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L
+#define GCEA_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L
+//GCEA_IO_GROUP_BURST
+#define GCEA_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0
+#define GCEA_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8
+#define GCEA_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10
+#define GCEA_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18
+#define GCEA_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL
+#define GCEA_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
+#define GCEA_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
+#define GCEA_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L
+//GCEA_IO_RD_PRI_AGE
+#define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//GCEA_IO_WR_PRI_AGE
+#define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//GCEA_IO_RD_PRI_QUEUING
+#define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//GCEA_IO_WR_PRI_QUEUING
+#define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//GCEA_IO_RD_PRI_FIXED
+#define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//GCEA_IO_WR_PRI_FIXED
+#define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//GCEA_IO_RD_PRI_URGENCY
+#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//GCEA_IO_WR_PRI_URGENCY
+#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//GCEA_IO_RD_PRI_URGENCY_MASKING
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L
+//GCEA_IO_WR_PRI_URGENCY_MASKING
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L
+//GCEA_IO_RD_PRI_QUANT_PRI1
+#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GCEA_IO_RD_PRI_QUANT_PRI2
+#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GCEA_IO_RD_PRI_QUANT_PRI3
+#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GCEA_IO_WR_PRI_QUANT_PRI1
+#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GCEA_IO_WR_PRI_QUANT_PRI2
+#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GCEA_IO_WR_PRI_QUANT_PRI3
+#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GCEA_MISC
+#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0
+#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1
+#define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2
+#define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3
+#define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4
+#define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5
+#define GCEA_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6
+#define GCEA_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7
+#define GCEA_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8
+#define GCEA_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9
+#define GCEA_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa
+#define GCEA_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb
+#define GCEA_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc
+#define GCEA_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd
+#define GCEA_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe
+#define GCEA_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf
+#define GCEA_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11
+#define GCEA_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13
+#define GCEA_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15
+#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a
+#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b
+#define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c
+#define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d
+#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e
+#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f
+#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L
+#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L
+#define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L
+#define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L
+#define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L
+#define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L
+#define GCEA_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L
+#define GCEA_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L
+#define GCEA_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L
+#define GCEA_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L
+#define GCEA_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L
+#define GCEA_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L
+#define GCEA_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L
+#define GCEA_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L
+#define GCEA_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L
+#define GCEA_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L
+#define GCEA_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L
+#define GCEA_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L
+#define GCEA_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L
+#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L
+#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L
+#define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L
+#define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L
+#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L
+#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L
+//GCEA_LATENCY_SAMPLING
+#define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0
+#define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1
+#define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2
+#define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3
+#define GCEA_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4
+#define GCEA_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5
+#define GCEA_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6
+#define GCEA_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7
+#define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8
+#define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9
+#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa
+#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb
+#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc
+#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd
+#define GCEA_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe
+#define GCEA_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16
+#define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L
+#define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L
+#define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L
+#define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L
+#define GCEA_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L
+#define GCEA_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L
+#define GCEA_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L
+#define GCEA_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L
+#define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L
+#define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L
+#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L
+#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L
+#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L
+#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L
+#define GCEA_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L
+#define GCEA_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L
+//GCEA_PERFCOUNTER_LO
+#define GCEA_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define GCEA_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//GCEA_PERFCOUNTER_HI
+#define GCEA_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define GCEA_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define GCEA_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define GCEA_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//GCEA_PERFCOUNTER0_CFG
+#define GCEA_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define GCEA_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define GCEA_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define GCEA_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define GCEA_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define GCEA_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define GCEA_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//GCEA_PERFCOUNTER1_CFG
+#define GCEA_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define GCEA_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define GCEA_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define GCEA_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define GCEA_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define GCEA_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define GCEA_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+
+
+// addressBlock: gc_ea_gceadec2
+//GCEA_PERFCOUNTER_RSLT_CNTL
+#define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+//GCEA_EDC_CNT
+#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0
+#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2
+#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4
+#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6
+#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8
+#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa
+#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc
+#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe
+#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10
+#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12
+#define GCEA_EDC_CNT__IOWR_DATAMEM_SEC_COUNT__SHIFT 0x14
+#define GCEA_EDC_CNT__IOWR_DATAMEM_DED_COUNT__SHIFT 0x16
+#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x18
+#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x1a
+#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x1c
+#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1e
+#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
+#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
+#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
+#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
+#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
+#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
+#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L
+#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L
+#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L
+#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L
+#define GCEA_EDC_CNT__IOWR_DATAMEM_SEC_COUNT_MASK 0x00300000L
+#define GCEA_EDC_CNT__IOWR_DATAMEM_DED_COUNT_MASK 0x00C00000L
+#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x03000000L
+#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x0C000000L
+#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x30000000L
+#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0xC0000000L
+//GCEA_EDC_CNT2
+#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0
+#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2
+#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4
+#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6
+#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8
+#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa
+#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc
+#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe
+#define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10
+#define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12
+#define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14
+#define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16
+#define GCEA_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT 0x18
+#define GCEA_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT 0x1a
+#define GCEA_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT 0x1c
+#define GCEA_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT 0x1e
+#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
+#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
+#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
+#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
+#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
+#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
+#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L
+#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L
+#define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L
+#define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L
+#define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L
+#define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L
+#define GCEA_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK 0x03000000L
+#define GCEA_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK 0x0C000000L
+#define GCEA_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK 0x30000000L
+#define GCEA_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK 0xC0000000L
+//GCEA_DSM_CNTL
+#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3
+#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9
+#define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb
+#define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc
+#define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
+#define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf
+#define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11
+#define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12
+#define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14
+#define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15
+#define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17
+#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
+#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L
+#define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
+#define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L
+#define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
+#define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L
+#define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L
+#define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L
+#define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L
+#define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L
+#define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L
+//GCEA_DSM_CNTLA
+#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3
+#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9
+#define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb
+#define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc
+#define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
+#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf
+#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11
+#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12
+#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14
+#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
+#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L
+#define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
+#define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L
+#define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
+#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L
+#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L
+#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L
+#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L
+//GCEA_DSM_CNTLB
+//GCEA_DSM_CNTL2
+#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5
+#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8
+#define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb
+#define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe
+#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11
+#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14
+#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15
+#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17
+#define GCEA_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
+#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L
+#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L
+#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L
+#define GCEA_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
+//GCEA_DSM_CNTL2A
+#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5
+#define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8
+#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb
+#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe
+#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11
+#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14
+#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L
+//GCEA_DSM_CNTL2B
+//GCEA_TCC_XBR_CREDITS
+#define GCEA_TCC_XBR_CREDITS__DRAM_RD_LIMIT__SHIFT 0x0
+#define GCEA_TCC_XBR_CREDITS__DRAM_RD_RESERVE__SHIFT 0x6
+#define GCEA_TCC_XBR_CREDITS__IO_RD_LIMIT__SHIFT 0x8
+#define GCEA_TCC_XBR_CREDITS__IO_RD_RESERVE__SHIFT 0xe
+#define GCEA_TCC_XBR_CREDITS__DRAM_WR_LIMIT__SHIFT 0x10
+#define GCEA_TCC_XBR_CREDITS__DRAM_WR_RESERVE__SHIFT 0x16
+#define GCEA_TCC_XBR_CREDITS__IO_WR_LIMIT__SHIFT 0x18
+#define GCEA_TCC_XBR_CREDITS__IO_WR_RESERVE__SHIFT 0x1e
+#define GCEA_TCC_XBR_CREDITS__DRAM_RD_LIMIT_MASK 0x0000003FL
+#define GCEA_TCC_XBR_CREDITS__DRAM_RD_RESERVE_MASK 0x000000C0L
+#define GCEA_TCC_XBR_CREDITS__IO_RD_LIMIT_MASK 0x00003F00L
+#define GCEA_TCC_XBR_CREDITS__IO_RD_RESERVE_MASK 0x0000C000L
+#define GCEA_TCC_XBR_CREDITS__DRAM_WR_LIMIT_MASK 0x003F0000L
+#define GCEA_TCC_XBR_CREDITS__DRAM_WR_RESERVE_MASK 0x00C00000L
+#define GCEA_TCC_XBR_CREDITS__IO_WR_LIMIT_MASK 0x3F000000L
+#define GCEA_TCC_XBR_CREDITS__IO_WR_RESERVE_MASK 0xC0000000L
+//GCEA_TCC_XBR_MAXBURST
+#define GCEA_TCC_XBR_MAXBURST__DRAM_RD__SHIFT 0x0
+#define GCEA_TCC_XBR_MAXBURST__IO_RD__SHIFT 0x4
+#define GCEA_TCC_XBR_MAXBURST__DRAM_WR__SHIFT 0x8
+#define GCEA_TCC_XBR_MAXBURST__IO_WR__SHIFT 0xc
+#define GCEA_TCC_XBR_MAXBURST__DRAM_RD_MASK 0x0000000FL
+#define GCEA_TCC_XBR_MAXBURST__IO_RD_MASK 0x000000F0L
+#define GCEA_TCC_XBR_MAXBURST__DRAM_WR_MASK 0x00000F00L
+#define GCEA_TCC_XBR_MAXBURST__IO_WR_MASK 0x0000F000L
+//GCEA_PROBE_CNTL
+#define GCEA_PROBE_CNTL__REQ2RSP_DELAY__SHIFT 0x0
+#define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE__SHIFT 0x5
+#define GCEA_PROBE_CNTL__REQ2RSP_DELAY_MASK 0x0000001FL
+#define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE_MASK 0x00000020L
+//GCEA_PROBE_MAP
+#define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTTCC__SHIFT 0x0
+#define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTTCC__SHIFT 0x1
+#define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTTCC__SHIFT 0x2
+#define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTTCC__SHIFT 0x3
+#define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTTCC__SHIFT 0x4
+#define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTTCC__SHIFT 0x5
+#define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTTCC__SHIFT 0x6
+#define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTTCC__SHIFT 0x7
+#define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTTCC__SHIFT 0x8
+#define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTTCC__SHIFT 0x9
+#define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC__SHIFT 0xa
+#define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTTCC__SHIFT 0xb
+#define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTTCC__SHIFT 0xc
+#define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTTCC__SHIFT 0xd
+#define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTTCC__SHIFT 0xe
+#define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTTCC__SHIFT 0xf
+#define GCEA_PROBE_MAP__INTLV_SIZE__SHIFT 0x10
+#define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTTCC_MASK 0x00000001L
+#define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTTCC_MASK 0x00000002L
+#define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTTCC_MASK 0x00000004L
+#define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTTCC_MASK 0x00000008L
+#define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTTCC_MASK 0x00000010L
+#define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTTCC_MASK 0x00000020L
+#define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTTCC_MASK 0x00000040L
+#define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTTCC_MASK 0x00000080L
+#define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTTCC_MASK 0x00000100L
+#define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTTCC_MASK 0x00000200L
+#define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC_MASK 0x00000400L
+#define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTTCC_MASK 0x00000800L
+#define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTTCC_MASK 0x00001000L
+#define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTTCC_MASK 0x00002000L
+#define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTTCC_MASK 0x00004000L
+#define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTTCC_MASK 0x00008000L
+#define GCEA_PROBE_MAP__INTLV_SIZE_MASK 0x00030000L
+//GCEA_ERR_STATUS
+#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0
+#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4
+#define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8
+#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa
+#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb
+#define GCEA_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc
+#define GCEA_ERR_STATUS__FUE_FLAG__SHIFT 0xd
+#define GCEA_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe
+#define GCEA_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf
+#define GCEA_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10
+#define GCEA_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11
+#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL
+#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L
+#define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L
+#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L
+#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L
+#define GCEA_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L
+#define GCEA_ERR_STATUS__FUE_FLAG_MASK 0x00002000L
+#define GCEA_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L
+#define GCEA_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L
+#define GCEA_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L
+#define GCEA_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L
+//GCEA_MISC2
+#define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0
+#define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1
+#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2
+#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7
+#define GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc
+#define GCEA_MISC2__BLOCK_REQUESTS__SHIFT 0xd
+#define GCEA_MISC2__REQUESTS_BLOCKED__SHIFT 0xe
+#define GCEA_MISC2__FGCLKEN_OVERRIDE__SHIFT 0xf
+#define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L
+#define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L
+#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL
+#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L
+#define GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L
+#define GCEA_MISC2__BLOCK_REQUESTS_MASK 0x00002000L
+#define GCEA_MISC2__REQUESTS_BLOCKED_MASK 0x00004000L
+#define GCEA_MISC2__FGCLKEN_OVERRIDE_MASK 0x00008000L
+//GCEA_DRAM_BANK_ARB
+#define GCEA_DRAM_BANK_ARB__AGEBASED_BANKARB__SHIFT 0x0
+#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_CYCLIM__SHIFT 0x1
+#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_REQLIM__SHIFT 0x9
+#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_STALLMODE__SHIFT 0xf
+#define GCEA_DRAM_BANK_ARB__DISABLE_STALLMODE_FIX__SHIFT 0x10
+#define GCEA_DRAM_BANK_ARB__AGEBASED_BANKARB_MASK 0x00000001L
+#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_CYCLIM_MASK 0x000001FEL
+#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_REQLIM_MASK 0x00007E00L
+#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_STALLMODE_MASK 0x00008000L
+#define GCEA_DRAM_BANK_ARB__DISABLE_STALLMODE_FIX_MASK 0x00010000L
+//GCEA_ADDRDEC_SELECT
+#define GCEA_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0
+#define GCEA_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5
+#define GCEA_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa
+#define GCEA_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf
+#define GCEA_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL
+#define GCEA_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L
+#define GCEA_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L
+#define GCEA_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L
+//GCEA_EDC_CNT3
+#define GCEA_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0
+#define GCEA_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2
+#define GCEA_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4
+#define GCEA_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6
+#define GCEA_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0x8
+#define GCEA_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xa
+#define GCEA_EDC_CNT3__MAM_A0MEM_SEC_COUNT__SHIFT 0xc
+#define GCEA_EDC_CNT3__MAM_A0MEM_DED_COUNT__SHIFT 0xe
+#define GCEA_EDC_CNT3__MAM_A1MEM_SEC_COUNT__SHIFT 0x10
+#define GCEA_EDC_CNT3__MAM_A1MEM_DED_COUNT__SHIFT 0x12
+#define GCEA_EDC_CNT3__MAM_A2MEM_SEC_COUNT__SHIFT 0x14
+#define GCEA_EDC_CNT3__MAM_A2MEM_DED_COUNT__SHIFT 0x16
+#define GCEA_EDC_CNT3__MAM_A3MEM_SEC_COUNT__SHIFT 0x18
+#define GCEA_EDC_CNT3__MAM_A3MEM_DED_COUNT__SHIFT 0x1a
+#define GCEA_EDC_CNT3__MAM_AFMEM_SEC_COUNT__SHIFT 0x1c
+#define GCEA_EDC_CNT3__MAM_AFMEM_DED_COUNT__SHIFT 0x1e
+#define GCEA_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L
+#define GCEA_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL
+#define GCEA_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L
+#define GCEA_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
+#define GCEA_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000300L
+#define GCEA_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00000C00L
+#define GCEA_EDC_CNT3__MAM_A0MEM_SEC_COUNT_MASK 0x00003000L
+#define GCEA_EDC_CNT3__MAM_A0MEM_DED_COUNT_MASK 0x0000C000L
+#define GCEA_EDC_CNT3__MAM_A1MEM_SEC_COUNT_MASK 0x00030000L
+#define GCEA_EDC_CNT3__MAM_A1MEM_DED_COUNT_MASK 0x000C0000L
+#define GCEA_EDC_CNT3__MAM_A2MEM_SEC_COUNT_MASK 0x00300000L
+#define GCEA_EDC_CNT3__MAM_A2MEM_DED_COUNT_MASK 0x00C00000L
+#define GCEA_EDC_CNT3__MAM_A3MEM_SEC_COUNT_MASK 0x03000000L
+#define GCEA_EDC_CNT3__MAM_A3MEM_DED_COUNT_MASK 0x0C000000L
+#define GCEA_EDC_CNT3__MAM_AFMEM_SEC_COUNT_MASK 0x30000000L
+#define GCEA_EDC_CNT3__MAM_AFMEM_DED_COUNT_MASK 0xC0000000L
+
+// addressBlock: gc_ea_pwrdec
+//GCEA_CGTT_CLK_CTRL
+#define GCEA_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define GCEA_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc
+#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14
+#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15
+#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16
+#define GCEA_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17
+#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c
+#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d
+#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e
+#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f
+#define GCEA_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define GCEA_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L
+#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L
+#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L
+#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L
+#define GCEA_CGTT_CLK_CTRL__SPARE1_MASK 0x0F800000L
+#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L
+#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L
+#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L
+#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L
+
+
+// addressBlock: gc_gccacdec
+//GC_CAC_CTRL_1
+#define GC_CAC_CTRL_1__CAC_WINDOW__SHIFT 0x0
+#define GC_CAC_CTRL_1__TDP_WINDOW__SHIFT 0x18
+#define GC_CAC_CTRL_1__CAC_WINDOW_MASK 0x00FFFFFFL
+#define GC_CAC_CTRL_1__TDP_WINDOW_MASK 0xFF000000L
+//GC_CAC_CTRL_2
+#define GC_CAC_CTRL_2__CAC_ENABLE__SHIFT 0x0
+#define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE__SHIFT 0x1
+#define GC_CAC_CTRL_2__GC_LCAC_ENABLE__SHIFT 0x2
+#define GC_CAC_CTRL_2__SE_LCAC_ENABLE__SHIFT 0x3
+#define GC_CAC_CTRL_2__CAC_ENABLE_MASK 0x00000001L
+#define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE_MASK 0x00000002L
+#define GC_CAC_CTRL_2__GC_LCAC_ENABLE_MASK 0x00000004L
+#define GC_CAC_CTRL_2__SE_LCAC_ENABLE_MASK 0x00000008L
+//GC_CAC_INDEX_AUTO_INCR_EN
+#define GC_CAC_INDEX_AUTO_INCR_EN__GC_CAC_INDEX_AUTO_INCR_EN__SHIFT 0x0
+#define GC_CAC_INDEX_AUTO_INCR_EN__GC_CAC_INDEX_AUTO_INCR_EN_MASK 0x00000001L
+//GC_CAC_AGGR_LOWER
+#define GC_CAC_AGGR_LOWER__AGGR_31_0__SHIFT 0x0
+#define GC_CAC_AGGR_LOWER__AGGR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_AGGR_UPPER
+#define GC_CAC_AGGR_UPPER__AGGR_63_32__SHIFT 0x0
+#define GC_CAC_AGGR_UPPER__AGGR_63_32_MASK 0xFFFFFFFFL
+//GC_EDC_PERF_COUNTER
+#define GC_EDC_PERF_COUNTER__EDC_PERF_COUNTER__SHIFT 0x0
+#define GC_EDC_PERF_COUNTER__EDC_PERF_COUNTER_MASK 0xFFFFFFFFL
+//PCC_PERF_COUNTER
+#define PCC_PERF_COUNTER__PCC_PERF_COUNTER__SHIFT 0x0
+#define PCC_PERF_COUNTER__PCC_PERF_COUNTER_MASK 0xFFFFFFFFL
+//GC_CAC_SOFT_CTRL
+#define GC_CAC_SOFT_CTRL__SOFT_SNAP__SHIFT 0x0
+#define GC_CAC_SOFT_CTRL__SOFT_SNAP_MASK 0x00000001L
+//GC_DIDT_CTRL0
+#define GC_DIDT_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
+#define GC_DIDT_CTRL0__PHASE_OFFSET__SHIFT 0x1
+#define GC_DIDT_CTRL0__DIDT_SW_RST__SHIFT 0x3
+#define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
+#define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x5
+#define GC_DIDT_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
+#define GC_DIDT_CTRL0__PHASE_OFFSET_MASK 0x00000006L
+#define GC_DIDT_CTRL0__DIDT_SW_RST_MASK 0x00000008L
+#define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
+#define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001E0L
+//GC_DIDT_CTRL1
+#define GC_DIDT_CTRL1__MIN_POWER__SHIFT 0x0
+#define GC_DIDT_CTRL1__MAX_POWER__SHIFT 0x10
+#define GC_DIDT_CTRL1__MIN_POWER_MASK 0x0000FFFFL
+#define GC_DIDT_CTRL1__MAX_POWER_MASK 0xFFFF0000L
+//GC_DIDT_CTRL2
+#define GC_DIDT_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
+#define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
+#define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
+#define GC_DIDT_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
+#define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
+#define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
+//GC_DIDT_WEIGHT
+#define GC_DIDT_WEIGHT__SQ_WEIGHT__SHIFT 0x0
+#define GC_DIDT_WEIGHT__DB_WEIGHT__SHIFT 0x8
+#define GC_DIDT_WEIGHT__TD_WEIGHT__SHIFT 0x10
+#define GC_DIDT_WEIGHT__TCP_WEIGHT__SHIFT 0x18
+#define GC_DIDT_WEIGHT__SQ_WEIGHT_MASK 0x000000FFL
+#define GC_DIDT_WEIGHT__DB_WEIGHT_MASK 0x0000FF00L
+#define GC_DIDT_WEIGHT__TD_WEIGHT_MASK 0x00FF0000L
+#define GC_DIDT_WEIGHT__TCP_WEIGHT_MASK 0xFF000000L
+//GC_THROTTLE_CTRL1
+#define GC_THROTTLE_CTRL1__PCC_FP_PROGRAM_STEP_EN__SHIFT 0x0
+#define GC_THROTTLE_CTRL1__PCC_PROGRAM_MIN_STEP__SHIFT 0x1
+#define GC_THROTTLE_CTRL1__PCC_PROGRAM_MAX_STEP__SHIFT 0x5
+#define GC_THROTTLE_CTRL1__PCC_PROGRAM_UPWARDS_STEP_SIZE__SHIFT 0xa
+#define GC_THROTTLE_CTRL1__PATTERN_EXTEND_EN__SHIFT 0xd
+#define GC_THROTTLE_CTRL1__PATTERN_EXTEND_MODE__SHIFT 0xe
+#define GC_THROTTLE_CTRL1__FIXED_PATTERN_SELECT__SHIFT 0x11
+#define GC_THROTTLE_CTRL1__FP_PATTERN_CLAMP_EN__SHIFT 0x13
+#define GC_THROTTLE_CTRL1__PWRBRK_STALL_EN__SHIFT 0x14
+#define GC_THROTTLE_CTRL1__PWRBRK_OVERRIDE__SHIFT 0x15
+#define GC_THROTTLE_CTRL1__PWRBRK_POLARITY_CNTL__SHIFT 0x16
+#define GC_THROTTLE_CTRL1__PWRBRK_PERF_COUNTER_EN__SHIFT 0x17
+#define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_UPWARDS_STEP_SIZE__SHIFT 0x18
+#define GC_THROTTLE_CTRL1__PCC_FP_PROGRAM_STEP_EN_MASK 0x00000001L
+#define GC_THROTTLE_CTRL1__PCC_PROGRAM_MIN_STEP_MASK 0x0000001EL
+#define GC_THROTTLE_CTRL1__PCC_PROGRAM_MAX_STEP_MASK 0x000003E0L
+#define GC_THROTTLE_CTRL1__PCC_PROGRAM_UPWARDS_STEP_SIZE_MASK 0x00001C00L
+#define GC_THROTTLE_CTRL1__PATTERN_EXTEND_EN_MASK 0x00002000L
+#define GC_THROTTLE_CTRL1__PATTERN_EXTEND_MODE_MASK 0x0001C000L
+#define GC_THROTTLE_CTRL1__FIXED_PATTERN_SELECT_MASK 0x00060000L
+#define GC_THROTTLE_CTRL1__FP_PATTERN_CLAMP_EN_MASK 0x00080000L
+#define GC_THROTTLE_CTRL1__PWRBRK_STALL_EN_MASK 0x00100000L
+#define GC_THROTTLE_CTRL1__PWRBRK_OVERRIDE_MASK 0x00200000L
+#define GC_THROTTLE_CTRL1__PWRBRK_POLARITY_CNTL_MASK 0x00400000L
+#define GC_THROTTLE_CTRL1__PWRBRK_PERF_COUNTER_EN_MASK 0x00800000L
+#define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_UPWARDS_STEP_SIZE_MASK 0x07000000L
+//GC_EDC_CTRL
+#define GC_EDC_CTRL__EDC_EN__SHIFT 0x0
+#define GC_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
+#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
+#define GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
+#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
+#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x9
+#define GC_EDC_CTRL__GC_EDC_ONLY_MODE__SHIFT 0xb
+#define GC_EDC_CTRL__EDC_THROTTLE_PATTERN_BIT_NUMS__SHIFT 0xc
+#define GC_EDC_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS__SHIFT 0x10
+#define GC_EDC_CTRL__RELEASE_STEP_INTERVAL__SHIFT 0x14
+#define GC_EDC_CTRL__EDC_LEVEL_SEL__SHIFT 0x1e
+#define GC_EDC_CTRL__PCC_DITHER_MODE__SHIFT 0x1f
+#define GC_EDC_CTRL__EDC_EN_MASK 0x00000001L
+#define GC_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
+#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
+#define GC_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
+#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
+#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00000200L
+#define GC_EDC_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000800L
+#define GC_EDC_CTRL__EDC_THROTTLE_PATTERN_BIT_NUMS_MASK 0x0000F000L
+#define GC_EDC_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS_MASK 0x000F0000L
+#define GC_EDC_CTRL__RELEASE_STEP_INTERVAL_MASK 0x3FF00000L
+#define GC_EDC_CTRL__EDC_LEVEL_SEL_MASK 0x40000000L
+#define GC_EDC_CTRL__PCC_DITHER_MODE_MASK 0x80000000L
+//GC_EDC_THRESHOLD
+#define GC_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
+#define GC_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
+//GC_EDC_STATUS
+#define GC_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x0
+#define GC_EDC_STATUS__THROTTLE_PATTERN_INDEX__SHIFT 0x3
+#define GC_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x00000007L
+#define GC_EDC_STATUS__THROTTLE_PATTERN_INDEX_MASK 0x000001F8L
+//GC_EDC_OVERFLOW
+#define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0
+#define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1
+#define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L
+#define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL
+//GC_EDC_ROLLING_POWER_DELTA
+#define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0
+#define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL
+//GC_EDC_CTRL1
+#define GC_EDC_CTRL1__PSM_THROTTLE_SRC_SEL__SHIFT 0x0
+#define GC_EDC_CTRL1__THROTTLE_SRC0_MASK__SHIFT 0x4
+#define GC_EDC_CTRL1__THROTTLE_SRC1_MASK__SHIFT 0x5
+#define GC_EDC_CTRL1__THROTTLE_SRC2_MASK__SHIFT 0x6
+#define GC_EDC_CTRL1__THROTTLE_SRC3_MASK__SHIFT 0x7
+#define GC_EDC_CTRL1__THROTTLE_SRC4_MASK__SHIFT 0x8
+#define GC_EDC_CTRL1__THROTTLE_SRC5_MASK__SHIFT 0x9
+#define GC_EDC_CTRL1__THROTTLE_SRC6_MASK__SHIFT 0xa
+#define GC_EDC_CTRL1__THROTTLE_SRC7_MASK__SHIFT 0xb
+#define GC_EDC_CTRL1__PSM_THROTTLE_SRC_SEL_MASK 0x0000000FL
+#define GC_EDC_CTRL1__THROTTLE_SRC0_MASK_MASK 0x00000010L
+#define GC_EDC_CTRL1__THROTTLE_SRC1_MASK_MASK 0x00000020L
+#define GC_EDC_CTRL1__THROTTLE_SRC2_MASK_MASK 0x00000040L
+#define GC_EDC_CTRL1__THROTTLE_SRC3_MASK_MASK 0x00000080L
+#define GC_EDC_CTRL1__THROTTLE_SRC4_MASK_MASK 0x00000100L
+#define GC_EDC_CTRL1__THROTTLE_SRC5_MASK_MASK 0x00000200L
+#define GC_EDC_CTRL1__THROTTLE_SRC6_MASK_MASK 0x00000400L
+#define GC_EDC_CTRL1__THROTTLE_SRC7_MASK_MASK 0x00000800L
+//GC_THROTTLE_CTRL2
+#define GC_THROTTLE_CTRL2__PWRBRK_FP_PROGRAM_STEP_EN__SHIFT 0x0
+#define GC_THROTTLE_CTRL2__PWRBRK_PROGRAM_MIN_STEP__SHIFT 0x1
+#define GC_THROTTLE_CTRL2__PWRBRK_PROGRAM_MAX_STEP__SHIFT 0x5
+#define GC_THROTTLE_CTRL2__PWRBRK_FP_PROGRAM_STEP_EN_MASK 0x00000001L
+#define GC_THROTTLE_CTRL2__PWRBRK_PROGRAM_MIN_STEP_MASK 0x0000001EL
+#define GC_THROTTLE_CTRL2__PWRBRK_PROGRAM_MAX_STEP_MASK 0x000003E0L
+//PWRBRK_PERF_COUNTER
+#define PWRBRK_PERF_COUNTER__PWRBRK_PERF_COUNTER__SHIFT 0x0
+#define PWRBRK_PERF_COUNTER__PWRBRK_PERF_COUNTER_MASK 0xFFFFFFFFL
+//GC_THROTTLE_CTRL
+#define GC_THROTTLE_CTRL__THROTTLE_CTRL_SW_RST__SHIFT 0x0
+#define GC_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT 0x1
+#define GC_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x2
+#define GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT 0x3
+#define GC_THROTTLE_CTRL__GC_EDC_OVERRIDE__SHIFT 0x4
+#define GC_THROTTLE_CTRL__NON_DITHER__SHIFT 0x5
+#define GC_THROTTLE_CTRL__PCC_OVERRIDE__SHIFT 0x7
+#define GC_THROTTLE_CTRL__GC_EDC_PERF_COUNTER_EN__SHIFT 0x8
+#define GC_THROTTLE_CTRL__PCC_PERF_COUNTER_EN__SHIFT 0x9
+#define GC_THROTTLE_CTRL__PCC_THROT_INCR_STEP_INTERVAL__SHIFT 0xa
+#define GC_THROTTLE_CTRL__PCC_FIXED_PATTERN_MIN__SHIFT 0x14
+#define GC_THROTTLE_CTRL__PCC_FIXED_PATTERN_MAX__SHIFT 0x19
+#define GC_THROTTLE_CTRL__INST_THROT_INCR__SHIFT 0x1e
+#define GC_THROTTLE_CTRL__INST_THROT_DECR__SHIFT 0x1f
+#define GC_THROTTLE_CTRL__THROTTLE_CTRL_SW_RST_MASK 0x00000001L
+#define GC_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK 0x00000002L
+#define GC_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000004L
+#define GC_THROTTLE_CTRL__PATTERN_MODE_MASK 0x00000008L
+#define GC_THROTTLE_CTRL__GC_EDC_OVERRIDE_MASK 0x00000010L
+#define GC_THROTTLE_CTRL__NON_DITHER_MASK 0x00000020L
+#define GC_THROTTLE_CTRL__PCC_OVERRIDE_MASK 0x00000080L
+#define GC_THROTTLE_CTRL__GC_EDC_PERF_COUNTER_EN_MASK 0x00000100L
+#define GC_THROTTLE_CTRL__PCC_PERF_COUNTER_EN_MASK 0x00000200L
+#define GC_THROTTLE_CTRL__PCC_THROT_INCR_STEP_INTERVAL_MASK 0x000FFC00L
+#define GC_THROTTLE_CTRL__PCC_FIXED_PATTERN_MIN_MASK 0x01F00000L
+#define GC_THROTTLE_CTRL__PCC_FIXED_PATTERN_MAX_MASK 0x3E000000L
+#define GC_THROTTLE_CTRL__INST_THROT_INCR_MASK 0x40000000L
+#define GC_THROTTLE_CTRL__INST_THROT_DECR_MASK 0x80000000L
+//GC_CAC_IND_INDEX
+#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR__SHIFT 0x0
+#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR_MASK 0xFFFFFFFFL
+//GC_CAC_IND_DATA
+#define GC_CAC_IND_DATA__GC_CAC_IND_DATA__SHIFT 0x0
+#define GC_CAC_IND_DATA__GC_CAC_IND_DATA_MASK 0xFFFFFFFFL
+//SE_CAC_IND_INDEX
+#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR__SHIFT 0x0
+#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR_MASK 0xFFFFFFFFL
+//SE_CAC_IND_DATA
+#define SE_CAC_IND_DATA__SE_CAC_IND_DATA__SHIFT 0x0
+#define SE_CAC_IND_DATA__SE_CAC_IND_DATA_MASK 0xFFFFFFFFL
+
+
+
+
+// addressBlock: gc_gdsdec
+//GDS_CONFIG
+#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1
+#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3
+#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5
+#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7
+#define GDS_CONFIG__SH4_GPR_PHASE_SEL__SHIFT 0x9
+#define GDS_CONFIG__SH5_GPR_PHASE_SEL__SHIFT 0xb
+#define GDS_CONFIG__SH6_GPR_PHASE_SEL__SHIFT 0xd
+#define GDS_CONFIG__SH7_GPR_PHASE_SEL__SHIFT 0xf
+#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x00000006L
+#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x00000018L
+#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x00000060L
+#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x00000180L
+#define GDS_CONFIG__SH4_GPR_PHASE_SEL_MASK 0x00000600L
+#define GDS_CONFIG__SH5_GPR_PHASE_SEL_MASK 0x00001800L
+#define GDS_CONFIG__SH6_GPR_PHASE_SEL_MASK 0x00006000L
+#define GDS_CONFIG__SH7_GPR_PHASE_SEL_MASK 0x00018000L
+//GDS_CNTL_STATUS
+#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0
+#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1
+#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2
+#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3
+#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4
+#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5
+#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6
+#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT 0x7
+#define GDS_CNTL_STATUS__DS_BUSY__SHIFT 0x8
+#define GDS_CNTL_STATUS__GWS_BUSY__SHIFT 0x9
+#define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0xa
+#define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT 0xb
+#define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT 0xc
+#define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT 0xd
+#define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT 0xe
+#define GDS_CNTL_STATUS__CREDIT_BUSY4__SHIFT 0xf
+#define GDS_CNTL_STATUS__CREDIT_BUSY5__SHIFT 0x10
+#define GDS_CNTL_STATUS__CREDIT_BUSY6__SHIFT 0x11
+#define GDS_CNTL_STATUS__CREDIT_BUSY7__SHIFT 0x12
+#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x00000001L
+#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x00000002L
+#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x00000004L
+#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x00000008L
+#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x00000010L
+#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x00000020L
+#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x00000040L
+#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK 0x00000080L
+#define GDS_CNTL_STATUS__DS_BUSY_MASK 0x00000100L
+#define GDS_CNTL_STATUS__GWS_BUSY_MASK 0x00000200L
+#define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK 0x00000400L
+#define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK 0x00000800L
+#define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK 0x00001000L
+#define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK 0x00002000L
+#define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK 0x00004000L
+#define GDS_CNTL_STATUS__CREDIT_BUSY4_MASK 0x00008000L
+#define GDS_CNTL_STATUS__CREDIT_BUSY5_MASK 0x00010000L
+#define GDS_CNTL_STATUS__CREDIT_BUSY6_MASK 0x00020000L
+#define GDS_CNTL_STATUS__CREDIT_BUSY7_MASK 0x00040000L
+//GDS_ENHANCE2
+#define GDS_ENHANCE2__MISC__SHIFT 0x0
+#define GDS_ENHANCE2__GDS_TD_INTERFACES_FGCG_OVERRIDE__SHIFT 0x10
+#define GDS_ENHANCE2__GDS_PHY_CMD_RAM_FGCG_OVERRIDE__SHIFT 0x11
+#define GDS_ENHANCE2__GDS_FED_IN_PROPAGATE__SHIFT 0x12
+#define GDS_ENHANCE2__UNUSED__SHIFT 0x13
+#define GDS_ENHANCE2__MISC_MASK 0x0000FFFFL
+#define GDS_ENHANCE2__GDS_TD_INTERFACES_FGCG_OVERRIDE_MASK 0x00010000L
+#define GDS_ENHANCE2__GDS_PHY_CMD_RAM_FGCG_OVERRIDE_MASK 0x00020000L
+#define GDS_ENHANCE2__GDS_FED_IN_PROPAGATE_MASK 0x00040000L
+#define GDS_ENHANCE2__UNUSED_MASK 0xFFF80000L
+//GDS_PROTECTION_FAULT
+#define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0
+#define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
+#define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2
+#define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3
+#define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6
+#define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa
+#define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc
+#define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
+#define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L
+#define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L
+#define GDS_PROTECTION_FAULT__GRBM_MASK 0x00000004L
+#define GDS_PROTECTION_FAULT__SH_ID_MASK 0x00000038L
+#define GDS_PROTECTION_FAULT__CU_ID_MASK 0x000003C0L
+#define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0x00000C00L
+#define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0x0000F000L
+#define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L
+//GDS_VM_PROTECTION_FAULT
+#define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0
+#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
+#define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2
+#define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3
+#define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4
+#define GDS_VM_PROTECTION_FAULT__TMZ__SHIFT 0x5
+#define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8
+#define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
+#define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L
+#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L
+#define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x00000004L
+#define GDS_VM_PROTECTION_FAULT__OA_MASK 0x00000008L
+#define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x00000010L
+#define GDS_VM_PROTECTION_FAULT__TMZ_MASK 0x00000020L
+#define GDS_VM_PROTECTION_FAULT__VMID_MASK 0x00000F00L
+#define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L
+//GDS_EDC_CNT
+#define GDS_EDC_CNT__GDS_MEM_DED__SHIFT 0x0
+#define GDS_EDC_CNT__GDS_MEM_SEC__SHIFT 0x4
+#define GDS_EDC_CNT__UNUSED__SHIFT 0x6
+#define GDS_EDC_CNT__GDS_MEM_DED_MASK 0x00000003L
+#define GDS_EDC_CNT__GDS_MEM_SEC_MASK 0x00000030L
+#define GDS_EDC_CNT__UNUSED_MASK 0xFFFFFFC0L
+//GDS_EDC_GRBM_CNT
+#define GDS_EDC_GRBM_CNT__DED__SHIFT 0x0
+#define GDS_EDC_GRBM_CNT__SEC__SHIFT 0x2
+#define GDS_EDC_GRBM_CNT__UNUSED__SHIFT 0x4
+#define GDS_EDC_GRBM_CNT__DED_MASK 0x00000003L
+#define GDS_EDC_GRBM_CNT__SEC_MASK 0x0000000CL
+#define GDS_EDC_GRBM_CNT__UNUSED_MASK 0xFFFFFFF0L
+//GDS_EDC_OA_DED
+#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0
+#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1
+#define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT 0x2
+#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED__SHIFT 0x3
+#define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT 0x4
+#define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT 0x5
+#define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT 0x6
+#define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT 0x7
+#define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT 0x8
+#define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT 0x9
+#define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0xa
+#define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT 0xb
+#define GDS_EDC_OA_DED__UNUSED1__SHIFT 0xc
+#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x00000001L
+#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x00000002L
+#define GDS_EDC_OA_DED__ME0_CS_DED_MASK 0x00000004L
+#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED_MASK 0x00000008L
+#define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK 0x00000010L
+#define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK 0x00000020L
+#define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK 0x00000040L
+#define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK 0x00000080L
+#define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK 0x00000100L
+#define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK 0x00000200L
+#define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK 0x00000400L
+#define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK 0x00000800L
+#define GDS_EDC_OA_DED__UNUSED1_MASK 0xFFFFF000L
+//GDS_DSM_CNTL
+#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0__SHIFT 0x0
+#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1__SHIFT 0x1
+#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0__SHIFT 0x3
+#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1__SHIFT 0x4
+#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0__SHIFT 0x6
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1__SHIFT 0x7
+#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0__SHIFT 0x9
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT 0xa
+#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0__SHIFT 0xc
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1__SHIFT 0xd
+#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
+#define GDS_DSM_CNTL__UNUSED__SHIFT 0xf
+#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0_MASK 0x00000001L
+#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1_MASK 0x00000002L
+#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0_MASK 0x00000008L
+#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1_MASK 0x00000010L
+#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0_MASK 0x00000040L
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1_MASK 0x00000080L
+#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0_MASK 0x00000200L
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1_MASK 0x00000400L
+#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0_MASK 0x00001000L
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1_MASK 0x00002000L
+#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
+#define GDS_DSM_CNTL__UNUSED_MASK 0xFFFF8000L
+//GDS_EDC_OA_PHY_CNT
+#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC__SHIFT 0x0
+#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED__SHIFT 0x2
+#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC__SHIFT 0x4
+#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED__SHIFT 0x6
+#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SEC__SHIFT 0x8
+#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_DED__SHIFT 0xa
+#define GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT 0xc
+#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC_MASK 0x00000003L
+#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED_MASK 0x0000000CL
+#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC_MASK 0x00000030L
+#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED_MASK 0x000000C0L
+#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SEC_MASK 0x00000300L
+#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_DED_MASK 0x00000C00L
+#define GDS_EDC_OA_PHY_CNT__UNUSED1_MASK 0xFFFFF000L
+//GDS_EDC_OA_PIPE_CNT
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC__SHIFT 0x0
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED__SHIFT 0x2
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC__SHIFT 0x4
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED__SHIFT 0x6
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC__SHIFT 0x8
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT 0xa
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC__SHIFT 0xc
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED__SHIFT 0xe
+#define GDS_EDC_OA_PIPE_CNT__UNUSED__SHIFT 0x10
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC_MASK 0x00000003L
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED_MASK 0x0000000CL
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC_MASK 0x00000030L
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED_MASK 0x000000C0L
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC_MASK 0x00000300L
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED_MASK 0x00000C00L
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC_MASK 0x00003000L
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED_MASK 0x0000C000L
+#define GDS_EDC_OA_PIPE_CNT__UNUSED_MASK 0xFFFF0000L
+//GDS_DSM_CNTL2
+#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY__SHIFT 0x5
+#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY__SHIFT 0x8
+#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY__SHIFT 0xb
+#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY__SHIFT 0xe
+#define GDS_DSM_CNTL2__UNUSED__SHIFT 0xf
+#define GDS_DSM_CNTL2__GDS_INJECT_DELAY__SHIFT 0x1a
+#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define GDS_DSM_CNTL2__UNUSED_MASK 0x03FF8000L
+#define GDS_DSM_CNTL2__GDS_INJECT_DELAY_MASK 0xFC000000L
+//GDS_WD_GDS_CSB
+#define GDS_WD_GDS_CSB__COUNTER__SHIFT 0x0
+#define GDS_WD_GDS_CSB__UNUSED__SHIFT 0xd
+#define GDS_WD_GDS_CSB__COUNTER_MASK 0x00001FFFL
+#define GDS_WD_GDS_CSB__UNUSED_MASK 0xFFFFE000L
+
+
+// addressBlock: gc_gdspdec
+//GDS_VMID0_BASE
+#define GDS_VMID0_BASE__BASE__SHIFT 0x0
+#define GDS_VMID0_BASE__BASE_MASK 0x0000FFFFL
+//GDS_VMID0_SIZE
+#define GDS_VMID0_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID0_SIZE__SIZE_MASK 0x0001FFFFL
+//GDS_VMID1_BASE
+#define GDS_VMID1_BASE__BASE__SHIFT 0x0
+#define GDS_VMID1_BASE__BASE_MASK 0x0000FFFFL
+//GDS_VMID1_SIZE
+#define GDS_VMID1_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID1_SIZE__SIZE_MASK 0x0001FFFFL
+//GDS_VMID2_BASE
+#define GDS_VMID2_BASE__BASE__SHIFT 0x0
+#define GDS_VMID2_BASE__BASE_MASK 0x0000FFFFL
+//GDS_VMID2_SIZE
+#define GDS_VMID2_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID2_SIZE__SIZE_MASK 0x0001FFFFL
+//GDS_VMID3_BASE
+#define GDS_VMID3_BASE__BASE__SHIFT 0x0
+#define GDS_VMID3_BASE__BASE_MASK 0x0000FFFFL
+//GDS_VMID3_SIZE
+#define GDS_VMID3_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID3_SIZE__SIZE_MASK 0x0001FFFFL
+//GDS_VMID4_BASE
+#define GDS_VMID4_BASE__BASE__SHIFT 0x0
+#define GDS_VMID4_BASE__BASE_MASK 0x0000FFFFL
+//GDS_VMID4_SIZE
+#define GDS_VMID4_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID4_SIZE__SIZE_MASK 0x0001FFFFL
+//GDS_VMID5_BASE
+#define GDS_VMID5_BASE__BASE__SHIFT 0x0
+#define GDS_VMID5_BASE__BASE_MASK 0x0000FFFFL
+//GDS_VMID5_SIZE
+#define GDS_VMID5_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID5_SIZE__SIZE_MASK 0x0001FFFFL
+//GDS_VMID6_BASE
+#define GDS_VMID6_BASE__BASE__SHIFT 0x0
+#define GDS_VMID6_BASE__BASE_MASK 0x0000FFFFL
+//GDS_VMID6_SIZE
+#define GDS_VMID6_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID6_SIZE__SIZE_MASK 0x0001FFFFL
+//GDS_VMID7_BASE
+#define GDS_VMID7_BASE__BASE__SHIFT 0x0
+#define GDS_VMID7_BASE__BASE_MASK 0x0000FFFFL
+//GDS_VMID7_SIZE
+#define GDS_VMID7_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID7_SIZE__SIZE_MASK 0x0001FFFFL
+//GDS_VMID8_BASE
+#define GDS_VMID8_BASE__BASE__SHIFT 0x0
+#define GDS_VMID8_BASE__BASE_MASK 0x0000FFFFL
+//GDS_VMID8_SIZE
+#define GDS_VMID8_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID8_SIZE__SIZE_MASK 0x0001FFFFL
+//GDS_VMID9_BASE
+#define GDS_VMID9_BASE__BASE__SHIFT 0x0
+#define GDS_VMID9_BASE__BASE_MASK 0x0000FFFFL
+//GDS_VMID9_SIZE
+#define GDS_VMID9_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID9_SIZE__SIZE_MASK 0x0001FFFFL
+//GDS_VMID10_BASE
+#define GDS_VMID10_BASE__BASE__SHIFT 0x0
+#define GDS_VMID10_BASE__BASE_MASK 0x0000FFFFL
+//GDS_VMID10_SIZE
+#define GDS_VMID10_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID10_SIZE__SIZE_MASK 0x0001FFFFL
+//GDS_VMID11_BASE
+#define GDS_VMID11_BASE__BASE__SHIFT 0x0
+#define GDS_VMID11_BASE__BASE_MASK 0x0000FFFFL
+//GDS_VMID11_SIZE
+#define GDS_VMID11_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID11_SIZE__SIZE_MASK 0x0001FFFFL
+//GDS_VMID12_BASE
+#define GDS_VMID12_BASE__BASE__SHIFT 0x0
+#define GDS_VMID12_BASE__BASE_MASK 0x0000FFFFL
+//GDS_VMID12_SIZE
+#define GDS_VMID12_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID12_SIZE__SIZE_MASK 0x0001FFFFL
+//GDS_VMID13_BASE
+#define GDS_VMID13_BASE__BASE__SHIFT 0x0
+#define GDS_VMID13_BASE__BASE_MASK 0x0000FFFFL
+//GDS_VMID13_SIZE
+#define GDS_VMID13_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID13_SIZE__SIZE_MASK 0x0001FFFFL
+//GDS_VMID14_BASE
+#define GDS_VMID14_BASE__BASE__SHIFT 0x0
+#define GDS_VMID14_BASE__BASE_MASK 0x0000FFFFL
+//GDS_VMID14_SIZE
+#define GDS_VMID14_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID14_SIZE__SIZE_MASK 0x0001FFFFL
+//GDS_VMID15_BASE
+#define GDS_VMID15_BASE__BASE__SHIFT 0x0
+#define GDS_VMID15_BASE__BASE_MASK 0x0000FFFFL
+//GDS_VMID15_SIZE
+#define GDS_VMID15_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID15_SIZE__SIZE_MASK 0x0001FFFFL
+//GDS_GWS_VMID0
+#define GDS_GWS_VMID0__BASE__SHIFT 0x0
+#define GDS_GWS_VMID0__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID0__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID0__SIZE_MASK 0x007F0000L
+//GDS_GWS_VMID1
+#define GDS_GWS_VMID1__BASE__SHIFT 0x0
+#define GDS_GWS_VMID1__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID1__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID1__SIZE_MASK 0x007F0000L
+//GDS_GWS_VMID2
+#define GDS_GWS_VMID2__BASE__SHIFT 0x0
+#define GDS_GWS_VMID2__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID2__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID2__SIZE_MASK 0x007F0000L
+//GDS_GWS_VMID3
+#define GDS_GWS_VMID3__BASE__SHIFT 0x0
+#define GDS_GWS_VMID3__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID3__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID3__SIZE_MASK 0x007F0000L
+//GDS_GWS_VMID4
+#define GDS_GWS_VMID4__BASE__SHIFT 0x0
+#define GDS_GWS_VMID4__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID4__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID4__SIZE_MASK 0x007F0000L
+//GDS_GWS_VMID5
+#define GDS_GWS_VMID5__BASE__SHIFT 0x0
+#define GDS_GWS_VMID5__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID5__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID5__SIZE_MASK 0x007F0000L
+//GDS_GWS_VMID6
+#define GDS_GWS_VMID6__BASE__SHIFT 0x0
+#define GDS_GWS_VMID6__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID6__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID6__SIZE_MASK 0x007F0000L
+//GDS_GWS_VMID7
+#define GDS_GWS_VMID7__BASE__SHIFT 0x0
+#define GDS_GWS_VMID7__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID7__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID7__SIZE_MASK 0x007F0000L
+//GDS_GWS_VMID8
+#define GDS_GWS_VMID8__BASE__SHIFT 0x0
+#define GDS_GWS_VMID8__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID8__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID8__SIZE_MASK 0x007F0000L
+//GDS_GWS_VMID9
+#define GDS_GWS_VMID9__BASE__SHIFT 0x0
+#define GDS_GWS_VMID9__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID9__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID9__SIZE_MASK 0x007F0000L
+//GDS_GWS_VMID10
+#define GDS_GWS_VMID10__BASE__SHIFT 0x0
+#define GDS_GWS_VMID10__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID10__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID10__SIZE_MASK 0x007F0000L
+//GDS_GWS_VMID11
+#define GDS_GWS_VMID11__BASE__SHIFT 0x0
+#define GDS_GWS_VMID11__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID11__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID11__SIZE_MASK 0x007F0000L
+//GDS_GWS_VMID12
+#define GDS_GWS_VMID12__BASE__SHIFT 0x0
+#define GDS_GWS_VMID12__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID12__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID12__SIZE_MASK 0x007F0000L
+//GDS_GWS_VMID13
+#define GDS_GWS_VMID13__BASE__SHIFT 0x0
+#define GDS_GWS_VMID13__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID13__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID13__SIZE_MASK 0x007F0000L
+//GDS_GWS_VMID14
+#define GDS_GWS_VMID14__BASE__SHIFT 0x0
+#define GDS_GWS_VMID14__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID14__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID14__SIZE_MASK 0x007F0000L
+//GDS_GWS_VMID15
+#define GDS_GWS_VMID15__BASE__SHIFT 0x0
+#define GDS_GWS_VMID15__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID15__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID15__SIZE_MASK 0x007F0000L
+//GDS_OA_VMID0
+#define GDS_OA_VMID0__MASK__SHIFT 0x0
+#define GDS_OA_VMID0__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID0__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID0__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID1
+#define GDS_OA_VMID1__MASK__SHIFT 0x0
+#define GDS_OA_VMID1__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID1__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID1__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID2
+#define GDS_OA_VMID2__MASK__SHIFT 0x0
+#define GDS_OA_VMID2__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID2__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID2__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID3
+#define GDS_OA_VMID3__MASK__SHIFT 0x0
+#define GDS_OA_VMID3__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID3__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID3__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID4
+#define GDS_OA_VMID4__MASK__SHIFT 0x0
+#define GDS_OA_VMID4__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID4__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID4__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID5
+#define GDS_OA_VMID5__MASK__SHIFT 0x0
+#define GDS_OA_VMID5__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID5__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID5__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID6
+#define GDS_OA_VMID6__MASK__SHIFT 0x0
+#define GDS_OA_VMID6__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID6__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID6__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID7
+#define GDS_OA_VMID7__MASK__SHIFT 0x0
+#define GDS_OA_VMID7__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID7__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID7__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID8
+#define GDS_OA_VMID8__MASK__SHIFT 0x0
+#define GDS_OA_VMID8__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID8__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID8__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID9
+#define GDS_OA_VMID9__MASK__SHIFT 0x0
+#define GDS_OA_VMID9__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID9__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID9__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID10
+#define GDS_OA_VMID10__MASK__SHIFT 0x0
+#define GDS_OA_VMID10__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID10__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID10__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID11
+#define GDS_OA_VMID11__MASK__SHIFT 0x0
+#define GDS_OA_VMID11__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID11__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID11__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID12
+#define GDS_OA_VMID12__MASK__SHIFT 0x0
+#define GDS_OA_VMID12__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID12__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID12__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID13
+#define GDS_OA_VMID13__MASK__SHIFT 0x0
+#define GDS_OA_VMID13__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID13__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID13__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID14
+#define GDS_OA_VMID14__MASK__SHIFT 0x0
+#define GDS_OA_VMID14__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID14__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID14__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID15
+#define GDS_OA_VMID15__MASK__SHIFT 0x0
+#define GDS_OA_VMID15__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID15__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID15__UNUSED_MASK 0xFFFF0000L
+//GDS_GWS_RESET0
+#define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT 0x0
+#define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT 0x1
+#define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT 0x2
+#define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT 0x3
+#define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT 0x4
+#define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT 0x5
+#define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT 0x6
+#define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT 0x7
+#define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT 0x8
+#define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT 0x9
+#define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa
+#define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT 0xb
+#define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT 0xc
+#define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT 0xd
+#define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT 0xe
+#define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT 0xf
+#define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT 0x10
+#define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT 0x11
+#define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT 0x12
+#define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT 0x13
+#define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x14
+#define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT 0x15
+#define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT 0x16
+#define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT 0x17
+#define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT 0x18
+#define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT 0x19
+#define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT 0x1a
+#define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT 0x1b
+#define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT 0x1c
+#define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d
+#define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT 0x1e
+#define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT 0x1f
+#define GDS_GWS_RESET0__RESOURCE0_RESET_MASK 0x00000001L
+#define GDS_GWS_RESET0__RESOURCE1_RESET_MASK 0x00000002L
+#define GDS_GWS_RESET0__RESOURCE2_RESET_MASK 0x00000004L
+#define GDS_GWS_RESET0__RESOURCE3_RESET_MASK 0x00000008L
+#define GDS_GWS_RESET0__RESOURCE4_RESET_MASK 0x00000010L
+#define GDS_GWS_RESET0__RESOURCE5_RESET_MASK 0x00000020L
+#define GDS_GWS_RESET0__RESOURCE6_RESET_MASK 0x00000040L
+#define GDS_GWS_RESET0__RESOURCE7_RESET_MASK 0x00000080L
+#define GDS_GWS_RESET0__RESOURCE8_RESET_MASK 0x00000100L
+#define GDS_GWS_RESET0__RESOURCE9_RESET_MASK 0x00000200L
+#define GDS_GWS_RESET0__RESOURCE10_RESET_MASK 0x00000400L
+#define GDS_GWS_RESET0__RESOURCE11_RESET_MASK 0x00000800L
+#define GDS_GWS_RESET0__RESOURCE12_RESET_MASK 0x00001000L
+#define GDS_GWS_RESET0__RESOURCE13_RESET_MASK 0x00002000L
+#define GDS_GWS_RESET0__RESOURCE14_RESET_MASK 0x00004000L
+#define GDS_GWS_RESET0__RESOURCE15_RESET_MASK 0x00008000L
+#define GDS_GWS_RESET0__RESOURCE16_RESET_MASK 0x00010000L
+#define GDS_GWS_RESET0__RESOURCE17_RESET_MASK 0x00020000L
+#define GDS_GWS_RESET0__RESOURCE18_RESET_MASK 0x00040000L
+#define GDS_GWS_RESET0__RESOURCE19_RESET_MASK 0x00080000L
+#define GDS_GWS_RESET0__RESOURCE20_RESET_MASK 0x00100000L
+#define GDS_GWS_RESET0__RESOURCE21_RESET_MASK 0x00200000L
+#define GDS_GWS_RESET0__RESOURCE22_RESET_MASK 0x00400000L
+#define GDS_GWS_RESET0__RESOURCE23_RESET_MASK 0x00800000L
+#define GDS_GWS_RESET0__RESOURCE24_RESET_MASK 0x01000000L
+#define GDS_GWS_RESET0__RESOURCE25_RESET_MASK 0x02000000L
+#define GDS_GWS_RESET0__RESOURCE26_RESET_MASK 0x04000000L
+#define GDS_GWS_RESET0__RESOURCE27_RESET_MASK 0x08000000L
+#define GDS_GWS_RESET0__RESOURCE28_RESET_MASK 0x10000000L
+#define GDS_GWS_RESET0__RESOURCE29_RESET_MASK 0x20000000L
+#define GDS_GWS_RESET0__RESOURCE30_RESET_MASK 0x40000000L
+#define GDS_GWS_RESET0__RESOURCE31_RESET_MASK 0x80000000L
+//GDS_GWS_RESET1
+#define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT 0x0
+#define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT 0x1
+#define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT 0x2
+#define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT 0x3
+#define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT 0x4
+#define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT 0x5
+#define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT 0x6
+#define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT 0x7
+#define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT 0x8
+#define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT 0x9
+#define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa
+#define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT 0xb
+#define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT 0xc
+#define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT 0xd
+#define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT 0xe
+#define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT 0xf
+#define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT 0x10
+#define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT 0x11
+#define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT 0x12
+#define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT 0x13
+#define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x14
+#define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT 0x15
+#define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT 0x16
+#define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT 0x17
+#define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT 0x18
+#define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT 0x19
+#define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT 0x1a
+#define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT 0x1b
+#define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT 0x1c
+#define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d
+#define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT 0x1e
+#define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT 0x1f
+#define GDS_GWS_RESET1__RESOURCE32_RESET_MASK 0x00000001L
+#define GDS_GWS_RESET1__RESOURCE33_RESET_MASK 0x00000002L
+#define GDS_GWS_RESET1__RESOURCE34_RESET_MASK 0x00000004L
+#define GDS_GWS_RESET1__RESOURCE35_RESET_MASK 0x00000008L
+#define GDS_GWS_RESET1__RESOURCE36_RESET_MASK 0x00000010L
+#define GDS_GWS_RESET1__RESOURCE37_RESET_MASK 0x00000020L
+#define GDS_GWS_RESET1__RESOURCE38_RESET_MASK 0x00000040L
+#define GDS_GWS_RESET1__RESOURCE39_RESET_MASK 0x00000080L
+#define GDS_GWS_RESET1__RESOURCE40_RESET_MASK 0x00000100L
+#define GDS_GWS_RESET1__RESOURCE41_RESET_MASK 0x00000200L
+#define GDS_GWS_RESET1__RESOURCE42_RESET_MASK 0x00000400L
+#define GDS_GWS_RESET1__RESOURCE43_RESET_MASK 0x00000800L
+#define GDS_GWS_RESET1__RESOURCE44_RESET_MASK 0x00001000L
+#define GDS_GWS_RESET1__RESOURCE45_RESET_MASK 0x00002000L
+#define GDS_GWS_RESET1__RESOURCE46_RESET_MASK 0x00004000L
+#define GDS_GWS_RESET1__RESOURCE47_RESET_MASK 0x00008000L
+#define GDS_GWS_RESET1__RESOURCE48_RESET_MASK 0x00010000L
+#define GDS_GWS_RESET1__RESOURCE49_RESET_MASK 0x00020000L
+#define GDS_GWS_RESET1__RESOURCE50_RESET_MASK 0x00040000L
+#define GDS_GWS_RESET1__RESOURCE51_RESET_MASK 0x00080000L
+#define GDS_GWS_RESET1__RESOURCE52_RESET_MASK 0x00100000L
+#define GDS_GWS_RESET1__RESOURCE53_RESET_MASK 0x00200000L
+#define GDS_GWS_RESET1__RESOURCE54_RESET_MASK 0x00400000L
+#define GDS_GWS_RESET1__RESOURCE55_RESET_MASK 0x00800000L
+#define GDS_GWS_RESET1__RESOURCE56_RESET_MASK 0x01000000L
+#define GDS_GWS_RESET1__RESOURCE57_RESET_MASK 0x02000000L
+#define GDS_GWS_RESET1__RESOURCE58_RESET_MASK 0x04000000L
+#define GDS_GWS_RESET1__RESOURCE59_RESET_MASK 0x08000000L
+#define GDS_GWS_RESET1__RESOURCE60_RESET_MASK 0x10000000L
+#define GDS_GWS_RESET1__RESOURCE61_RESET_MASK 0x20000000L
+#define GDS_GWS_RESET1__RESOURCE62_RESET_MASK 0x40000000L
+#define GDS_GWS_RESET1__RESOURCE63_RESET_MASK 0x80000000L
+//GDS_GWS_RESOURCE_RESET
+#define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x0
+#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x8
+#define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x00000001L
+#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0x0000FF00L
+//GDS_COMPUTE_MAX_WAVE_ID
+#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
+#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
+//GDS_OA_RESET_MASK
+#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT 0x0
+#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT 0x1
+#define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT 0x2
+#define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET__SHIFT 0x3
+#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT 0x4
+#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT 0x5
+#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT 0x6
+#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT 0x7
+#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT 0x8
+#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT 0x9
+#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa
+#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT 0xb
+#define GDS_OA_RESET_MASK__UNUSED1__SHIFT 0xc
+#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK 0x00000001L
+#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK 0x00000002L
+#define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK 0x00000004L
+#define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET_MASK 0x00000008L
+#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK 0x00000010L
+#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK 0x00000020L
+#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK 0x00000040L
+#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK 0x00000080L
+#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK 0x00000100L
+#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK 0x00000200L
+#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK 0x00000400L
+#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK 0x00000800L
+#define GDS_OA_RESET_MASK__UNUSED1_MASK 0xFFFFF000L
+//GDS_OA_RESET
+#define GDS_OA_RESET__RESET__SHIFT 0x0
+#define GDS_OA_RESET__PIPE_ID__SHIFT 0x8
+#define GDS_OA_RESET__RESET_MASK 0x00000001L
+#define GDS_OA_RESET__PIPE_ID_MASK 0x0000FF00L
+//GDS_ENHANCE
+#define GDS_ENHANCE__MISC__SHIFT 0x0
+#define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x10
+#define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x11
+#define GDS_ENHANCE__RD_BUF_TAG_MISS__SHIFT 0x12
+#define GDS_ENHANCE__GDSA_PC_CGTS_DIS__SHIFT 0x13
+#define GDS_ENHANCE__GDSO_PC_CGTS_DIS__SHIFT 0x14
+#define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE__SHIFT 0x15
+#define GDS_ENHANCE__GDS_CLK_ENHANCE_DIS__SHIFT 0x16
+#define GDS_ENHANCE__DS_MEM_CLK_GATE_DIS__SHIFT 0x17
+#define GDS_ENHANCE__UNUSED__SHIFT 0x18
+#define GDS_ENHANCE__MISC_MASK 0x0000FFFFL
+#define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x00010000L
+#define GDS_ENHANCE__CGPG_RESTORE_MASK 0x00020000L
+#define GDS_ENHANCE__RD_BUF_TAG_MISS_MASK 0x00040000L
+#define GDS_ENHANCE__GDSA_PC_CGTS_DIS_MASK 0x00080000L
+#define GDS_ENHANCE__GDSO_PC_CGTS_DIS_MASK 0x00100000L
+#define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE_MASK 0x00200000L
+#define GDS_ENHANCE__GDS_CLK_ENHANCE_DIS_MASK 0x00400000L
+#define GDS_ENHANCE__DS_MEM_CLK_GATE_DIS_MASK 0x00800000L
+#define GDS_ENHANCE__UNUSED_MASK 0xFF000000L
+//GDS_OA_CGPG_RESTORE
+#define GDS_OA_CGPG_RESTORE__VMID__SHIFT 0x0
+#define GDS_OA_CGPG_RESTORE__MEID__SHIFT 0x8
+#define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT 0xc
+#define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT 0x10
+#define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x14
+#define GDS_OA_CGPG_RESTORE__VMID_MASK 0x000000FFL
+#define GDS_OA_CGPG_RESTORE__MEID_MASK 0x00000F00L
+#define GDS_OA_CGPG_RESTORE__PIPEID_MASK 0x0000F000L
+#define GDS_OA_CGPG_RESTORE__QUEUEID_MASK 0x000F0000L
+#define GDS_OA_CGPG_RESTORE__UNUSED_MASK 0xFFF00000L
+//GDS_CS_CTXSW_STATUS
+#define GDS_CS_CTXSW_STATUS__R__SHIFT 0x0
+#define GDS_CS_CTXSW_STATUS__W__SHIFT 0x1
+#define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT 0x2
+#define GDS_CS_CTXSW_STATUS__R_MASK 0x00000001L
+#define GDS_CS_CTXSW_STATUS__W_MASK 0x00000002L
+#define GDS_CS_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL
+//GDS_CS_CTXSW_CNT0
+#define GDS_CS_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_CS_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_CS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
+#define GDS_CS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
+//GDS_CS_CTXSW_CNT1
+#define GDS_CS_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_CS_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_CS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
+#define GDS_CS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
+//GDS_CS_CTXSW_CNT2
+#define GDS_CS_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_CS_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_CS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
+#define GDS_CS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
+//GDS_CS_CTXSW_CNT3
+#define GDS_CS_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_CS_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_CS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
+#define GDS_CS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
+//GDS_GFX_CTXSW_STATUS
+#define GDS_GFX_CTXSW_STATUS__R__SHIFT 0x0
+#define GDS_GFX_CTXSW_STATUS__W__SHIFT 0x1
+#define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT 0x2
+#define GDS_GFX_CTXSW_STATUS__R_MASK 0x00000001L
+#define GDS_GFX_CTXSW_STATUS__W_MASK 0x00000002L
+#define GDS_GFX_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL
+//GDS_VS_CTXSW_CNT0
+#define GDS_VS_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_VS_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_VS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
+#define GDS_VS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
+//GDS_VS_CTXSW_CNT1
+#define GDS_VS_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_VS_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_VS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
+#define GDS_VS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
+//GDS_VS_CTXSW_CNT2
+#define GDS_VS_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_VS_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_VS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
+#define GDS_VS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
+//GDS_VS_CTXSW_CNT3
+#define GDS_VS_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_VS_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_VS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
+#define GDS_VS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
+//GDS_PS0_CTXSW_CNT0
+#define GDS_PS0_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_PS0_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_PS0_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
+#define GDS_PS0_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
+//GDS_PS0_CTXSW_CNT1
+#define GDS_PS0_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_PS0_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_PS0_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
+#define GDS_PS0_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
+//GDS_PS0_CTXSW_CNT2
+#define GDS_PS0_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_PS0_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_PS0_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
+#define GDS_PS0_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
+//GDS_PS0_CTXSW_CNT3
+#define GDS_PS0_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_PS0_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_PS0_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
+#define GDS_PS0_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
+//GDS_PS1_CTXSW_CNT0
+#define GDS_PS1_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_PS1_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_PS1_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
+#define GDS_PS1_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
+//GDS_PS1_CTXSW_CNT1
+#define GDS_PS1_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_PS1_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_PS1_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
+#define GDS_PS1_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
+//GDS_PS1_CTXSW_CNT2
+#define GDS_PS1_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_PS1_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_PS1_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
+#define GDS_PS1_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
+//GDS_PS1_CTXSW_CNT3
+#define GDS_PS1_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_PS1_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_PS1_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
+#define GDS_PS1_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
+//GDS_PS2_CTXSW_CNT0
+#define GDS_PS2_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_PS2_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_PS2_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
+#define GDS_PS2_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
+//GDS_PS2_CTXSW_CNT1
+#define GDS_PS2_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_PS2_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_PS2_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
+#define GDS_PS2_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
+//GDS_PS2_CTXSW_CNT2
+#define GDS_PS2_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_PS2_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_PS2_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
+#define GDS_PS2_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
+//GDS_PS2_CTXSW_CNT3
+#define GDS_PS2_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_PS2_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_PS2_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
+#define GDS_PS2_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
+//GDS_PS3_CTXSW_CNT0
+#define GDS_PS3_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_PS3_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_PS3_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
+#define GDS_PS3_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
+//GDS_PS3_CTXSW_CNT1
+#define GDS_PS3_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_PS3_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_PS3_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
+#define GDS_PS3_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
+//GDS_PS3_CTXSW_CNT2
+#define GDS_PS3_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_PS3_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_PS3_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
+#define GDS_PS3_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
+//GDS_PS3_CTXSW_CNT3
+#define GDS_PS3_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_PS3_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_PS3_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
+#define GDS_PS3_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
+//GDS_PS4_CTXSW_CNT0
+#define GDS_PS4_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_PS4_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_PS4_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
+#define GDS_PS4_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
+//GDS_PS4_CTXSW_CNT1
+#define GDS_PS4_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_PS4_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_PS4_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
+#define GDS_PS4_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
+//GDS_PS4_CTXSW_CNT2
+#define GDS_PS4_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_PS4_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_PS4_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
+#define GDS_PS4_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
+//GDS_PS4_CTXSW_CNT3
+#define GDS_PS4_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_PS4_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_PS4_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
+#define GDS_PS4_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
+//GDS_PS5_CTXSW_CNT0
+#define GDS_PS5_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_PS5_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_PS5_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
+#define GDS_PS5_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
+//GDS_PS5_CTXSW_CNT1
+#define GDS_PS5_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_PS5_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_PS5_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
+#define GDS_PS5_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
+//GDS_PS5_CTXSW_CNT2
+#define GDS_PS5_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_PS5_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_PS5_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
+#define GDS_PS5_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
+//GDS_PS5_CTXSW_CNT3
+#define GDS_PS5_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_PS5_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_PS5_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
+#define GDS_PS5_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
+//GDS_PS6_CTXSW_CNT0
+#define GDS_PS6_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_PS6_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_PS6_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
+#define GDS_PS6_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
+//GDS_PS6_CTXSW_CNT1
+#define GDS_PS6_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_PS6_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_PS6_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
+#define GDS_PS6_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
+//GDS_PS6_CTXSW_CNT2
+#define GDS_PS6_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_PS6_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_PS6_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
+#define GDS_PS6_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
+//GDS_PS6_CTXSW_CNT3
+#define GDS_PS6_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_PS6_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_PS6_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
+#define GDS_PS6_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
+//GDS_PS7_CTXSW_CNT0
+#define GDS_PS7_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_PS7_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_PS7_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
+#define GDS_PS7_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
+//GDS_PS7_CTXSW_CNT1
+#define GDS_PS7_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_PS7_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_PS7_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
+#define GDS_PS7_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
+//GDS_PS7_CTXSW_CNT2
+#define GDS_PS7_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_PS7_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_PS7_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
+#define GDS_PS7_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
+//GDS_PS7_CTXSW_CNT3
+#define GDS_PS7_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_PS7_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_PS7_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
+#define GDS_PS7_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
+//GDS_GS_CTXSW_CNT0
+#define GDS_GS_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_GS_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_GS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
+#define GDS_GS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
+//GDS_GS_CTXSW_CNT1
+#define GDS_GS_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_GS_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_GS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
+#define GDS_GS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
+//GDS_GS_CTXSW_CNT2
+#define GDS_GS_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_GS_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_GS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
+#define GDS_GS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
+//GDS_GS_CTXSW_CNT3
+#define GDS_GS_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_GS_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_GS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
+#define GDS_GS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
+
+
+// addressBlock: gc_gfxdec0
+//DB_RENDER_CONTROL
+#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0
+#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1
+#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2
+#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3
+#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4
+#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5
+#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6
+#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7
+#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8
+#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT 0xc
+#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x00000001L
+#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x00000002L
+#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x00000004L
+#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x00000008L
+#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x00000010L
+#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x00000020L
+#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x00000040L
+#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x00000080L
+#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0x00000F00L
+#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK 0x00001000L
+//DB_COUNT_CONTROL
+#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0
+#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1
+#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4
+#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8
+#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc
+#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10
+#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14
+#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18
+#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c
+#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x00000001L
+#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x00000002L
+#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x00000070L
+#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0x00000F00L
+#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0x0000F000L
+#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0x000F0000L
+#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0x00F00000L
+#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x0F000000L
+#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xF0000000L
+//DB_DEPTH_VIEW
+#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0
+#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd
+#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18
+#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19
+#define DB_DEPTH_VIEW__MIPID__SHIFT 0x1a
+#define DB_DEPTH_VIEW__SLICE_START_MASK 0x000007FFL
+#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0x00FFE000L
+#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x01000000L
+#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x02000000L
+#define DB_DEPTH_VIEW__MIPID_MASK 0x3C000000L
+//DB_RENDER_OVERRIDE
+#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0
+#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2
+#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4
+#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6
+#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7
+#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8
+#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9
+#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa
+#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc
+#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd
+#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf
+#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10
+#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11
+#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12
+#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13
+#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15
+#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a
+#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c
+#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e
+#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f
+#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x00000003L
+#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0x0000000CL
+#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x00000030L
+#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x00000040L
+#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x00000080L
+#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x00000100L
+#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x00000200L
+#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x00000400L
+#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x00000800L
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x00001000L
+#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x00006000L
+#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x00008000L
+#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x00010000L
+#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x00020000L
+#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x00040000L
+#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x00180000L
+#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x03E00000L
+#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x04000000L
+#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x08000000L
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000L
+#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000L
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000L
+#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000L
+//DB_RENDER_OVERRIDE2
+#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0
+#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2
+#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5
+#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6
+#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7
+#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8
+#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9
+#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa
+#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb
+#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc
+#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf
+#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12
+#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15
+#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16
+#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17
+#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL__SHIFT 0x19
+#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x00000003L
+#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x0000001CL
+#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x00000020L
+#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x00000040L
+#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x00000080L
+#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x00000100L
+#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x00000200L
+#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x00000400L
+#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x00000800L
+#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x00007000L
+#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x00038000L
+#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x001C0000L
+#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x00200000L
+#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x00400000L
+#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x00800000L
+#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL_MASK 0x02000000L
+//DB_HTILE_DATA_BASE
+#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0
+#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//DB_HTILE_DATA_BASE_HI
+#define DB_HTILE_DATA_BASE_HI__BASE_HI__SHIFT 0x0
+#define DB_HTILE_DATA_BASE_HI__BASE_HI_MASK 0x000000FFL
+//DB_DEPTH_SIZE
+#define DB_DEPTH_SIZE__X_MAX__SHIFT 0x0
+#define DB_DEPTH_SIZE__Y_MAX__SHIFT 0x10
+#define DB_DEPTH_SIZE__X_MAX_MASK 0x00003FFFL
+#define DB_DEPTH_SIZE__Y_MAX_MASK 0x3FFF0000L
+//DB_DEPTH_BOUNDS_MIN
+#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0
+#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xFFFFFFFFL
+//DB_DEPTH_BOUNDS_MAX
+#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0
+#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xFFFFFFFFL
+//DB_STENCIL_CLEAR
+#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0
+#define DB_STENCIL_CLEAR__CLEAR_MASK 0x000000FFL
+//DB_DEPTH_CLEAR
+#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0
+#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xFFFFFFFFL
+//PA_SC_SCREEN_SCISSOR_TL
+#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0
+#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10
+#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x0000FFFFL
+#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xFFFF0000L
+//PA_SC_SCREEN_SCISSOR_BR
+#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0
+#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10
+#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x0000FFFFL
+#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xFFFF0000L
+//DB_Z_INFO
+#define DB_Z_INFO__FORMAT__SHIFT 0x0
+#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2
+#define DB_Z_INFO__SW_MODE__SHIFT 0x4
+#define DB_Z_INFO__PARTIALLY_RESIDENT__SHIFT 0xc
+#define DB_Z_INFO__FAULT_BEHAVIOR__SHIFT 0xd
+#define DB_Z_INFO__ITERATE_FLUSH__SHIFT 0xf
+#define DB_Z_INFO__MAXMIP__SHIFT 0x10
+#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT 0x17
+#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
+#define DB_Z_INFO__READ_SIZE__SHIFT 0x1c
+#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d
+#define DB_Z_INFO__CLEAR_DISALLOWED__SHIFT 0x1e
+#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f
+#define DB_Z_INFO__FORMAT_MASK 0x00000003L
+#define DB_Z_INFO__NUM_SAMPLES_MASK 0x0000000CL
+#define DB_Z_INFO__SW_MODE_MASK 0x000001F0L
+#define DB_Z_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L
+#define DB_Z_INFO__FAULT_BEHAVIOR_MASK 0x00006000L
+#define DB_Z_INFO__ITERATE_FLUSH_MASK 0x00008000L
+#define DB_Z_INFO__MAXMIP_MASK 0x000F0000L
+#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK 0x07800000L
+#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L
+#define DB_Z_INFO__READ_SIZE_MASK 0x10000000L
+#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000L
+#define DB_Z_INFO__CLEAR_DISALLOWED_MASK 0x40000000L
+#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000L
+//DB_STENCIL_INFO
+#define DB_STENCIL_INFO__FORMAT__SHIFT 0x0
+#define DB_STENCIL_INFO__SW_MODE__SHIFT 0x4
+#define DB_STENCIL_INFO__PARTIALLY_RESIDENT__SHIFT 0xc
+#define DB_STENCIL_INFO__FAULT_BEHAVIOR__SHIFT 0xd
+#define DB_STENCIL_INFO__ITERATE_FLUSH__SHIFT 0xf
+#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
+#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d
+#define DB_STENCIL_INFO__CLEAR_DISALLOWED__SHIFT 0x1e
+#define DB_STENCIL_INFO__FORMAT_MASK 0x00000001L
+#define DB_STENCIL_INFO__SW_MODE_MASK 0x000001F0L
+#define DB_STENCIL_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L
+#define DB_STENCIL_INFO__FAULT_BEHAVIOR_MASK 0x00006000L
+#define DB_STENCIL_INFO__ITERATE_FLUSH_MASK 0x00008000L
+#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L
+#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000L
+#define DB_STENCIL_INFO__CLEAR_DISALLOWED_MASK 0x40000000L
+//DB_Z_READ_BASE
+#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0
+#define DB_Z_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//DB_Z_READ_BASE_HI
+#define DB_Z_READ_BASE_HI__BASE_HI__SHIFT 0x0
+#define DB_Z_READ_BASE_HI__BASE_HI_MASK 0x000000FFL
+//DB_STENCIL_READ_BASE
+#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0
+#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//DB_STENCIL_READ_BASE_HI
+#define DB_STENCIL_READ_BASE_HI__BASE_HI__SHIFT 0x0
+#define DB_STENCIL_READ_BASE_HI__BASE_HI_MASK 0x000000FFL
+//DB_Z_WRITE_BASE
+#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0
+#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//DB_Z_WRITE_BASE_HI
+#define DB_Z_WRITE_BASE_HI__BASE_HI__SHIFT 0x0
+#define DB_Z_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL
+//DB_STENCIL_WRITE_BASE
+#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0
+#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//DB_STENCIL_WRITE_BASE_HI
+#define DB_STENCIL_WRITE_BASE_HI__BASE_HI__SHIFT 0x0
+#define DB_STENCIL_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL
+//DB_DFSM_CONTROL
+#define DB_DFSM_CONTROL__PUNCHOUT_MODE__SHIFT 0x0
+#define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP__SHIFT 0x2
+#define DB_DFSM_CONTROL__DISALLOW_OVERFLOW__SHIFT 0x3
+#define DB_DFSM_CONTROL__PUNCHOUT_MODE_MASK 0x00000003L
+#define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP_MASK 0x00000004L
+#define DB_DFSM_CONTROL__DISALLOW_OVERFLOW_MASK 0x00000008L
+//DB_Z_INFO2
+#define DB_Z_INFO2__EPITCH__SHIFT 0x0
+#define DB_Z_INFO2__EPITCH_MASK 0x0000FFFFL
+//DB_STENCIL_INFO2
+#define DB_STENCIL_INFO2__EPITCH__SHIFT 0x0
+#define DB_STENCIL_INFO2__EPITCH_MASK 0x0000FFFFL
+//COHER_DEST_BASE_HI_0
+#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0
+#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0x000000FFL
+//COHER_DEST_BASE_HI_1
+#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0
+#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0x000000FFL
+//COHER_DEST_BASE_HI_2
+#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0
+#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0x000000FFL
+//COHER_DEST_BASE_HI_3
+#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0
+#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0x000000FFL
+//COHER_DEST_BASE_2
+#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0
+#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xFFFFFFFFL
+//COHER_DEST_BASE_3
+#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0
+#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xFFFFFFFFL
+//PA_SC_WINDOW_OFFSET
+#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0
+#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10
+#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x0000FFFFL
+#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xFFFF0000L
+//PA_SC_WINDOW_SCISSOR_TL
+#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0
+#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_WINDOW_SCISSOR_BR
+#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0
+#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10
+#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_CLIPRECT_RULE
+#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0
+#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0x0000FFFFL
+//PA_SC_CLIPRECT_0_TL
+#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7FFF0000L
+//PA_SC_CLIPRECT_0_BR
+#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_CLIPRECT_1_TL
+#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7FFF0000L
+//PA_SC_CLIPRECT_1_BR
+#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_CLIPRECT_2_TL
+#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7FFF0000L
+//PA_SC_CLIPRECT_2_BR
+#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_CLIPRECT_3_TL
+#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7FFF0000L
+//PA_SC_CLIPRECT_3_BR
+#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_EDGERULE
+#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0
+#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4
+#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8
+#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc
+#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12
+#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18
+#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c
+#define PA_SC_EDGERULE__ER_TRI_MASK 0x0000000FL
+#define PA_SC_EDGERULE__ER_POINT_MASK 0x000000F0L
+#define PA_SC_EDGERULE__ER_RECT_MASK 0x00000F00L
+#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x0003F000L
+#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0x00FC0000L
+#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0x0F000000L
+#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xF0000000L
+//PA_SU_HARDWARE_SCREEN_OFFSET
+#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0
+#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10
+#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x000001FFL
+#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x01FF0000L
+//CB_TARGET_MASK
+#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0
+#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4
+#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8
+#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc
+#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10
+#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14
+#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18
+#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c
+#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0x0000000FL
+#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0x000000F0L
+#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0x00000F00L
+#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0x0000F000L
+#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0x000F0000L
+#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0x00F00000L
+#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0x0F000000L
+#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xF0000000L
+//CB_SHADER_MASK
+#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0
+#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4
+#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8
+#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc
+#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10
+#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14
+#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18
+#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c
+#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0x0000000FL
+#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0x000000F0L
+#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0x00000F00L
+#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0x0000F000L
+#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0x000F0000L
+#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0x00F00000L
+#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0x0F000000L
+#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xF0000000L
+//PA_SC_GENERIC_SCISSOR_TL
+#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0
+#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10
+#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_GENERIC_SCISSOR_BR
+#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0
+#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10
+#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L
+//COHER_DEST_BASE_0
+#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0
+#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xFFFFFFFFL
+//COHER_DEST_BASE_1
+#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0
+#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_SCISSOR_0_TL
+#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_0_BR
+#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_1_TL
+#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_1_BR
+#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_2_TL
+#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_2_BR
+#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_3_TL
+#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_3_BR
+#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_4_TL
+#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_4_BR
+#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_5_TL
+#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_5_BR
+#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_6_TL
+#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_6_BR
+#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_7_TL
+#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_7_BR
+#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_8_TL
+#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_8_BR
+#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_9_TL
+#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_9_BR
+#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_10_TL
+#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_10_BR
+#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_11_TL
+#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_11_BR
+#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_12_TL
+#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_12_BR
+#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_13_TL
+#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_13_BR
+#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_14_TL
+#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_14_BR
+#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_15_TL
+#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_15_BR
+#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_ZMIN_0
+#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_0
+#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_1
+#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_1
+#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_2
+#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_2
+#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_3
+#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_3
+#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_4
+#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_4
+#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_5
+#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_5
+#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_6
+#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_6
+#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_7
+#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_7
+#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_8
+#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_8
+#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_9
+#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_9
+#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_10
+#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_10
+#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_11
+#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_11
+#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_12
+#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_12
+#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_13
+#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_13
+#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_14
+#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_14
+#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_15
+#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_15
+#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_RASTER_CONFIG
+#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0
+#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2
+#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4
+#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6
+#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7
+#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8
+#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa
+#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc
+#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe
+#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10
+#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12
+#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14
+#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18
+#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a
+#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1d
+#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x00000003L
+#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0x0000000CL
+#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x00000030L
+#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x00000040L
+#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x00000080L
+#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x00000300L
+#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0x00000C00L
+#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x00003000L
+#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0x0000C000L
+#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x00030000L
+#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0x000C0000L
+#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x00300000L
+#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x03000000L
+#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0x1C000000L
+#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0xE0000000L
+//PA_SC_RASTER_CONFIG_1
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x5
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x00000003L
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0x0000001CL
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x000000E0L
+//PA_SC_SCREEN_EXTENT_CONTROL
+#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0
+#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2
+#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x00000003L
+#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0x0000000CL
+//PA_SC_TILE_STEERING_OVERRIDE
+#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT 0x0
+#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE__SHIFT 0x1
+#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE__SHIFT 0x5
+#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK 0x00000001L
+#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE_MASK 0x00000006L
+#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE_MASK 0x00000060L
+//CP_PERFMON_CNTX_CNTL
+#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f
+#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000L
+//CP_PIPEID
+#define CP_PIPEID__PIPE_ID__SHIFT 0x0
+#define CP_PIPEID__PIPE_ID_MASK 0x00000003L
+//CP_RINGID
+#define CP_RINGID__RINGID__SHIFT 0x0
+#define CP_RINGID__RINGID_MASK 0x00000003L
+//CP_VMID
+#define CP_VMID__VMID__SHIFT 0x0
+#define CP_VMID__VMID_MASK 0x0000000FL
+//PA_SC_RIGHT_VERT_GRID
+#define PA_SC_RIGHT_VERT_GRID__LEFT_QTR__SHIFT 0x0
+#define PA_SC_RIGHT_VERT_GRID__LEFT_HALF__SHIFT 0x8
+#define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF__SHIFT 0x10
+#define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR__SHIFT 0x18
+#define PA_SC_RIGHT_VERT_GRID__LEFT_QTR_MASK 0x000000FFL
+#define PA_SC_RIGHT_VERT_GRID__LEFT_HALF_MASK 0x0000FF00L
+#define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF_MASK 0x00FF0000L
+#define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR_MASK 0xFF000000L
+//PA_SC_LEFT_VERT_GRID
+#define PA_SC_LEFT_VERT_GRID__LEFT_QTR__SHIFT 0x0
+#define PA_SC_LEFT_VERT_GRID__LEFT_HALF__SHIFT 0x8
+#define PA_SC_LEFT_VERT_GRID__RIGHT_HALF__SHIFT 0x10
+#define PA_SC_LEFT_VERT_GRID__RIGHT_QTR__SHIFT 0x18
+#define PA_SC_LEFT_VERT_GRID__LEFT_QTR_MASK 0x000000FFL
+#define PA_SC_LEFT_VERT_GRID__LEFT_HALF_MASK 0x0000FF00L
+#define PA_SC_LEFT_VERT_GRID__RIGHT_HALF_MASK 0x00FF0000L
+#define PA_SC_LEFT_VERT_GRID__RIGHT_QTR_MASK 0xFF000000L
+//PA_SC_HORIZ_GRID
+#define PA_SC_HORIZ_GRID__TOP_QTR__SHIFT 0x0
+#define PA_SC_HORIZ_GRID__TOP_HALF__SHIFT 0x8
+#define PA_SC_HORIZ_GRID__BOT_HALF__SHIFT 0x10
+#define PA_SC_HORIZ_GRID__BOT_QTR__SHIFT 0x18
+#define PA_SC_HORIZ_GRID__TOP_QTR_MASK 0x000000FFL
+#define PA_SC_HORIZ_GRID__TOP_HALF_MASK 0x0000FF00L
+#define PA_SC_HORIZ_GRID__BOT_HALF_MASK 0x00FF0000L
+#define PA_SC_HORIZ_GRID__BOT_QTR_MASK 0xFF000000L
+//VGT_MULTI_PRIM_IB_RESET_INDX
+#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0
+#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xFFFFFFFFL
+//CB_BLEND_RED
+#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
+#define CB_BLEND_RED__BLEND_RED_MASK 0xFFFFFFFFL
+//CB_BLEND_GREEN
+#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
+#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xFFFFFFFFL
+//CB_BLEND_BLUE
+#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
+#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xFFFFFFFFL
+//CB_BLEND_ALPHA
+#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
+#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xFFFFFFFFL
+//CB_DCC_CONTROL
+#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE__SHIFT 0x1
+#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT 0x2
+#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01__SHIFT 0x8
+#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE__SHIFT 0x9
+#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0xa
+#define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01__SHIFT 0xc
+#define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE__SHIFT 0xd
+#define CB_DCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG__SHIFT 0xe
+#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
+#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE_MASK 0x00000002L
+#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK 0x0000007CL
+#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01_MASK 0x00000100L
+#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE_MASK 0x00000200L
+#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00000400L
+#define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01_MASK 0x00001000L
+#define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE_MASK 0x00002000L
+#define CB_DCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG_MASK 0x00004000L
+//DB_STENCIL_CONTROL
+#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0
+#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4
+#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8
+#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc
+#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10
+#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14
+#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0x0000000FL
+#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0x000000F0L
+#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0x00000F00L
+#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0x0000F000L
+#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0x000F0000L
+#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0x00F00000L
+//DB_STENCILREFMASK
+#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0
+#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8
+#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10
+#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18
+#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0x000000FFL
+#define DB_STENCILREFMASK__STENCILMASK_MASK 0x0000FF00L
+#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0x00FF0000L
+#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xFF000000L
+//DB_STENCILREFMASK_BF
+#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0
+#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8
+#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10
+#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18
+#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0x000000FFL
+#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0x0000FF00L
+#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0x00FF0000L
+#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xFF000000L
+//PA_CL_VPORT_XSCALE
+#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET
+#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE
+#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET
+#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE
+#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET
+#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_1
+#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_1
+#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_1
+#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_1
+#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_1
+#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_1
+#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_2
+#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_2
+#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_2
+#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_2
+#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_2
+#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_2
+#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_3
+#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_3
+#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_3
+#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_3
+#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_3
+#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_3
+#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_4
+#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_4
+#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_4
+#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_4
+#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_4
+#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_4
+#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_5
+#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_5
+#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_5
+#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_5
+#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_5
+#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_5
+#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_6
+#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_6
+#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_6
+#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_6
+#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_6
+#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_6
+#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_7
+#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_7
+#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_7
+#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_7
+#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_7
+#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_7
+#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_8
+#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_8
+#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_8
+#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_8
+#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_8
+#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_8
+#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_9
+#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_9
+#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_9
+#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_9
+#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_9
+#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_9
+#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_10
+#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_10
+#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_10
+#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_10
+#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_10
+#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_10
+#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_11
+#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_11
+#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_11
+#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_11
+#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_11
+#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_11
+#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_12
+#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_12
+#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_12
+#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_12
+#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_12
+#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_12
+#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_13
+#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_13
+#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_13
+#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_13
+#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_13
+#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_13
+#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_14
+#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_14
+#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_14
+#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_14
+#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_14
+#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_14
+#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_15
+#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_15
+#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_15
+#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_15
+#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_15
+#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_15
+#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_UCP_0_X
+#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_0_Y
+#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_0_Z
+#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_0_W
+#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_1_X
+#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_1_Y
+#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_1_Z
+#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_1_W
+#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_2_X
+#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_2_Y
+#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_2_Z
+#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_2_W
+#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_3_X
+#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_3_Y
+#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_3_Z
+#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_3_W
+#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_4_X
+#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_4_Y
+#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_4_Z
+#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_4_W
+#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_5_X
+#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_5_Y
+#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_5_Z
+#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_5_W
+#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_PROG_NEAR_CLIP_Z
+#define PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
+//SPI_PS_INPUT_CNTL_0
+#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_1
+#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_2
+#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_3
+#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_4
+#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_5
+#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_6
+#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_7
+#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_8
+#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_9
+#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_10
+#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_11
+#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_12
+#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_13
+#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_14
+#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_15
+#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_16
+#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_17
+#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_18
+#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_19
+#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_20
+#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_21
+#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_22
+#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_23
+#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_24
+#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_25
+#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_26
+#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_27
+#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_28
+#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_29
+#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_30
+#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_31
+#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK 0x02000000L
+//SPI_VS_OUT_CONFIG
+#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1
+#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x6
+#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x0000003EL
+#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x00000040L
+//SPI_PS_INPUT_ENA
+#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0
+#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1
+#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2
+#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3
+#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4
+#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5
+#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6
+#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
+#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8
+#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9
+#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa
+#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb
+#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc
+#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd
+#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe
+#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf
+#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x00000001L
+#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x00000002L
+#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x00000004L
+#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x00000008L
+#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x00000010L
+#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x00000020L
+#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x00000040L
+#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L
+#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x00000100L
+#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x00000200L
+#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x00000400L
+#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x00000800L
+#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x00001000L
+#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x00002000L
+#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x00004000L
+#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x00008000L
+//SPI_PS_INPUT_ADDR
+#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0
+#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1
+#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2
+#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3
+#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4
+#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5
+#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6
+#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
+#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8
+#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9
+#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa
+#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb
+#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc
+#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd
+#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe
+#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf
+#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x00000001L
+#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x00000002L
+#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x00000004L
+#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x00000008L
+#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x00000010L
+#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x00000020L
+#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x00000040L
+#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L
+#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x00000100L
+#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x00000200L
+#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x00000400L
+#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x00000800L
+#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x00001000L
+#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x00002000L
+#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x00004000L
+#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x00008000L
+//SPI_INTERP_CONTROL_0
+#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe
+#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x00000001L
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x00000002L
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x0000001CL
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0x000000E0L
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x00000700L
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x00003800L
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x00004000L
+//SPI_PS_IN_CONTROL
+#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0
+#define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN__SHIFT 0x7
+#define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC__SHIFT 0x8
+#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe
+#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x0000003FL
+#define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN_MASK 0x00000080L
+#define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC_MASK 0x00000100L
+#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x00004000L
+//SPI_BARYC_CNTL
+#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0
+#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4
+#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8
+#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc
+#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10
+#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14
+#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18
+#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x00000001L
+#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x00000010L
+#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x00000100L
+#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x00001000L
+#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x00030000L
+#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x00100000L
+#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x01000000L
+//SPI_TMPRING_SIZE
+#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0
+#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc
+#define SPI_TMPRING_SIZE__WAVES_MASK 0x00000FFFL
+#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x01FFF000L
+//SPI_SHADER_POS_FORMAT
+#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0
+#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4
+#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8
+#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc
+#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0x0000000FL
+#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0x000000F0L
+#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0x00000F00L
+#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0x0000F000L
+//SPI_SHADER_Z_FORMAT
+#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0
+#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0x0000000FL
+//SPI_SHADER_COL_FORMAT
+#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0
+#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4
+#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8
+#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc
+#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10
+#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14
+#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18
+#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c
+#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0x0000000FL
+#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0x000000F0L
+#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0x00000F00L
+#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0x0000F000L
+#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0x000F0000L
+#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0x00F00000L
+#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0x0F000000L
+#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xF0000000L
+//SX_PS_DOWNCONVERT
+#define SX_PS_DOWNCONVERT__MRT0__SHIFT 0x0
+#define SX_PS_DOWNCONVERT__MRT1__SHIFT 0x4
+#define SX_PS_DOWNCONVERT__MRT2__SHIFT 0x8
+#define SX_PS_DOWNCONVERT__MRT3__SHIFT 0xc
+#define SX_PS_DOWNCONVERT__MRT4__SHIFT 0x10
+#define SX_PS_DOWNCONVERT__MRT5__SHIFT 0x14
+#define SX_PS_DOWNCONVERT__MRT6__SHIFT 0x18
+#define SX_PS_DOWNCONVERT__MRT7__SHIFT 0x1c
+#define SX_PS_DOWNCONVERT__MRT0_MASK 0x0000000FL
+#define SX_PS_DOWNCONVERT__MRT1_MASK 0x000000F0L
+#define SX_PS_DOWNCONVERT__MRT2_MASK 0x00000F00L
+#define SX_PS_DOWNCONVERT__MRT3_MASK 0x0000F000L
+#define SX_PS_DOWNCONVERT__MRT4_MASK 0x000F0000L
+#define SX_PS_DOWNCONVERT__MRT5_MASK 0x00F00000L
+#define SX_PS_DOWNCONVERT__MRT6_MASK 0x0F000000L
+#define SX_PS_DOWNCONVERT__MRT7_MASK 0xF0000000L
+//SX_BLEND_OPT_EPSILON
+#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON__SHIFT 0x0
+#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON__SHIFT 0x4
+#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON__SHIFT 0x8
+#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON__SHIFT 0xc
+#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON__SHIFT 0x10
+#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON__SHIFT 0x14
+#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON__SHIFT 0x18
+#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON__SHIFT 0x1c
+#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON_MASK 0x0000000FL
+#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON_MASK 0x000000F0L
+#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON_MASK 0x00000F00L
+#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON_MASK 0x0000F000L
+#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON_MASK 0x000F0000L
+#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON_MASK 0x00F00000L
+#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON_MASK 0x0F000000L
+#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON_MASK 0xF0000000L
+//SX_BLEND_OPT_CONTROL
+#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE__SHIFT 0x0
+#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE__SHIFT 0x1
+#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE__SHIFT 0x4
+#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE__SHIFT 0x5
+#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE__SHIFT 0x8
+#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE__SHIFT 0x9
+#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE__SHIFT 0xc
+#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE__SHIFT 0xd
+#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE__SHIFT 0x10
+#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE__SHIFT 0x11
+#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE__SHIFT 0x14
+#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE__SHIFT 0x15
+#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE__SHIFT 0x18
+#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE__SHIFT 0x19
+#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE__SHIFT 0x1c
+#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE__SHIFT 0x1d
+#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE__SHIFT 0x1f
+#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE_MASK 0x00000001L
+#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE_MASK 0x00000002L
+#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE_MASK 0x00000010L
+#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE_MASK 0x00000020L
+#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE_MASK 0x00000100L
+#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE_MASK 0x00000200L
+#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE_MASK 0x00001000L
+#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE_MASK 0x00002000L
+#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE_MASK 0x00010000L
+#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE_MASK 0x00020000L
+#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE_MASK 0x00100000L
+#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE_MASK 0x00200000L
+#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE_MASK 0x01000000L
+#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE_MASK 0x02000000L
+#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE_MASK 0x10000000L
+#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE_MASK 0x20000000L
+#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE_MASK 0x80000000L
+//SX_MRT0_BLEND_OPT
+#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
+#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
+#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
+#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
+#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
+#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
+#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
+#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
+#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
+#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
+#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
+#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
+//SX_MRT1_BLEND_OPT
+#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
+#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
+#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
+#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
+#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
+#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
+#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
+#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
+#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
+#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
+#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
+#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
+//SX_MRT2_BLEND_OPT
+#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
+#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
+#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
+#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
+#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
+#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
+#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
+#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
+#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
+#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
+#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
+#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
+//SX_MRT3_BLEND_OPT
+#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
+#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
+#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
+#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
+#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
+#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
+#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
+#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
+#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
+#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
+#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
+#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
+//SX_MRT4_BLEND_OPT
+#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
+#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
+#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
+#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
+#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
+#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
+#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
+#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
+#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
+#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
+#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
+#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
+//SX_MRT5_BLEND_OPT
+#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
+#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
+#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
+#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
+#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
+#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
+#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
+#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
+#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
+#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
+#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
+#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
+//SX_MRT6_BLEND_OPT
+#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
+#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
+#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
+#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
+#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
+#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
+#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
+#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
+#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
+#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
+#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
+#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
+//SX_MRT7_BLEND_OPT
+#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
+#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
+#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
+#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
+#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
+#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
+#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
+#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
+#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
+#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
+#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
+#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
+//CB_BLEND0_CONTROL
+#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
+#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
+#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
+#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
+#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
+#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
+#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
+#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000L
+#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000L
+//CB_BLEND1_CONTROL
+#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
+#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
+#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
+#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
+#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
+#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
+#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
+#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000L
+#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000L
+//CB_BLEND2_CONTROL
+#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
+#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
+#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
+#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
+#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
+#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
+#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
+#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000L
+#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000L
+//CB_BLEND3_CONTROL
+#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
+#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
+#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
+#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
+#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
+#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
+#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
+#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000L
+#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000L
+//CB_BLEND4_CONTROL
+#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
+#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
+#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
+#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
+#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
+#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
+#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
+#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000L
+#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000L
+//CB_BLEND5_CONTROL
+#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
+#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
+#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
+#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
+#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
+#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
+#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
+#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000L
+#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000L
+//CB_BLEND6_CONTROL
+#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
+#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
+#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
+#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
+#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
+#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
+#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
+#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000L
+#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000L
+//CB_BLEND7_CONTROL
+#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
+#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
+#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
+#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
+#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
+#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
+#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
+#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000L
+#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000L
+//CB_MRT0_EPITCH
+#define CB_MRT0_EPITCH__EPITCH__SHIFT 0x0
+#define CB_MRT0_EPITCH__EPITCH_MASK 0x0000FFFFL
+//CB_MRT1_EPITCH
+#define CB_MRT1_EPITCH__EPITCH__SHIFT 0x0
+#define CB_MRT1_EPITCH__EPITCH_MASK 0x0000FFFFL
+//CB_MRT2_EPITCH
+#define CB_MRT2_EPITCH__EPITCH__SHIFT 0x0
+#define CB_MRT2_EPITCH__EPITCH_MASK 0x0000FFFFL
+//CB_MRT3_EPITCH
+#define CB_MRT3_EPITCH__EPITCH__SHIFT 0x0
+#define CB_MRT3_EPITCH__EPITCH_MASK 0x0000FFFFL
+//CB_MRT4_EPITCH
+#define CB_MRT4_EPITCH__EPITCH__SHIFT 0x0
+#define CB_MRT4_EPITCH__EPITCH_MASK 0x0000FFFFL
+//CB_MRT5_EPITCH
+#define CB_MRT5_EPITCH__EPITCH__SHIFT 0x0
+#define CB_MRT5_EPITCH__EPITCH_MASK 0x0000FFFFL
+//CB_MRT6_EPITCH
+#define CB_MRT6_EPITCH__EPITCH__SHIFT 0x0
+#define CB_MRT6_EPITCH__EPITCH_MASK 0x0000FFFFL
+//CB_MRT7_EPITCH
+#define CB_MRT7_EPITCH__EPITCH__SHIFT 0x0
+#define CB_MRT7_EPITCH__EPITCH_MASK 0x0000FFFFL
+//CS_COPY_STATE
+#define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
+#define CS_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L
+//GFX_COPY_STATE
+#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
+#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L
+//PA_CL_POINT_X_RAD
+#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_POINT_Y_RAD
+#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_POINT_SIZE
+#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_POINT_CULL_RAD
+#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL
+//VGT_DMA_BASE_HI
+#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0
+#define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0x0000FFFFL
+//VGT_DMA_BASE
+#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0
+#define VGT_DMA_BASE__BASE_ADDR_MASK 0xFFFFFFFFL
+//VGT_DRAW_INITIATOR
+#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0
+#define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x2
+#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x4
+#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5
+#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6
+#define VGT_DRAW_INITIATOR__UNROLLED_INST__SHIFT 0x7
+#define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC__SHIFT 0x8
+#define VGT_DRAW_INITIATOR__REG_RT_INDEX__SHIFT 0x1d
+#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x00000003L
+#define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0x0000000CL
+#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x00000010L
+#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00000020L
+#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x00000040L
+#define VGT_DRAW_INITIATOR__UNROLLED_INST_MASK 0x00000080L
+#define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC_MASK 0x00000100L
+#define VGT_DRAW_INITIATOR__REG_RT_INDEX_MASK 0xE0000000L
+//VGT_IMMED_DATA
+#define VGT_IMMED_DATA__DATA__SHIFT 0x0
+#define VGT_IMMED_DATA__DATA_MASK 0xFFFFFFFFL
+//VGT_EVENT_ADDRESS_REG
+#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0
+#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0x0FFFFFFFL
+//DB_DEPTH_CONTROL
+#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0
+#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1
+#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2
+#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3
+#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4
+#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7
+#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8
+#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14
+#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e
+#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f
+#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x00000001L
+#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x00000002L
+#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x00000004L
+#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x00000008L
+#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x00000070L
+#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x00000080L
+#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x00000700L
+#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x00700000L
+#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000L
+#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000L
+//DB_EQAA
+#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0
+#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4
+#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8
+#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc
+#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10
+#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11
+#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12
+#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13
+#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14
+#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15
+#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18
+#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b
+#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x00000007L
+#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x00000070L
+#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x00000700L
+#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x00007000L
+#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x00010000L
+#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x00020000L
+#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x00040000L
+#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x00080000L
+#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x00100000L
+#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x00200000L
+#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x07000000L
+#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x08000000L
+//CB_COLOR_CONTROL
+#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT 0x0
+#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
+#define CB_COLOR_CONTROL__MODE__SHIFT 0x4
+#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10
+#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK 0x00000001L
+#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x00000008L
+#define CB_COLOR_CONTROL__MODE_MASK 0x00000070L
+#define CB_COLOR_CONTROL__ROP3_MASK 0x00FF0000L
+//DB_SHADER_CONTROL
+#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0
+#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1
+#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2
+#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4
+#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6
+#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7
+#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8
+#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9
+#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa
+#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb
+#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc
+#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd
+#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT 0xf
+#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER__SHIFT 0x10
+#define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED__SHIFT 0x11
+#define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES__SHIFT 0x14
+#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x00000001L
+#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x00000002L
+#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x00000004L
+#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x00000030L
+#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x00000040L
+#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x00000080L
+#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x00000100L
+#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x00000200L
+#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x00000400L
+#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x00000800L
+#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x00001000L
+#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x00006000L
+#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK 0x00008000L
+#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER_MASK 0x00010000L
+#define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED_MASK 0x00020000L
+#define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES_MASK 0x00700000L
+//PA_CL_CLIP_CNTL
+#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0
+#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1
+#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2
+#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3
+#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4
+#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5
+#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd
+#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10
+#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15
+#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16
+#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18
+#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19
+#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a
+#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b
+#define PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA__SHIFT 0x1c
+#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x00000001L
+#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x00000002L
+#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x00000004L
+#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x00000008L
+#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x00000010L
+#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x00000020L
+#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x00002000L
+#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0x0000C000L
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L
+#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x00020000L
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L
+#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x00400000L
+#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x01000000L
+#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x02000000L
+#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x04000000L
+#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x08000000L
+#define PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA_MASK 0x10000000L
+//PA_SU_SC_MODE_CNTL
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0
+#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1
+#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2
+#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3
+#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5
+#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15
+#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF__SHIFT 0x16
+#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION__SHIFT 0x17
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L
+#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L
+#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L
+#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L
+#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000E0L
+#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L
+#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF_MASK 0x00400000L
+#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION_MASK 0x00800000L
+//PA_CL_VTE_CNTL
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5
+#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8
+#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9
+#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L
+#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L
+#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L
+#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L
+//PA_CL_VS_OUT_CNTL
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf
+#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10
+#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11
+#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12
+#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13
+#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14
+#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15
+#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16
+#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17
+#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18
+#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19
+#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT 0x1a
+#define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID__SHIFT 0x1b
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x00000001L
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x00000002L
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x00000004L
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x00000008L
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x00000010L
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x00000020L
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x00000040L
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x00000080L
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x00000100L
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x00000200L
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x00000400L
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x00000800L
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x00001000L
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x00002000L
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x00004000L
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x00008000L
+#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x00010000L
+#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x00020000L
+#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x00040000L
+#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x00080000L
+#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x00100000L
+#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x00200000L
+#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x00400000L
+#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x00800000L
+#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x01000000L
+#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x02000000L
+#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK 0x04000000L
+#define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID_MASK 0x08000000L
+//PA_CL_NANINF_CNTL
+#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0
+#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1
+#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2
+#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3
+#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4
+#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5
+#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6
+#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7
+#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8
+#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9
+#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa
+#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb
+#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc
+#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd
+#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe
+#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14
+#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x00000001L
+#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x00000002L
+#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x00000004L
+#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x00000008L
+#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x00000010L
+#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x00000020L
+#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x00000040L
+#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x00000080L
+#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x00000100L
+#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x00000200L
+#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x00000400L
+#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x00000800L
+#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x00001000L
+#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x00002000L
+#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x00004000L
+#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x00100000L
+//PA_SU_LINE_STIPPLE_CNTL
+#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0
+#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2
+#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3
+#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x4
+#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x00000003L
+#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x00000004L
+#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x00000008L
+#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x00000010L
+//PA_SU_LINE_STIPPLE_SCALE
+#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0
+#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xFFFFFFFFL
+//PA_SU_PRIM_FILTER_CNTL
+#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0
+#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1
+#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2
+#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3
+#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4
+#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5
+#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6
+#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7
+#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8
+#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e
+#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f
+#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000001L
+#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000002L
+#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000004L
+#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000008L
+#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x00000010L
+#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x00000020L
+#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x00000040L
+#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x00000080L
+#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0x0000FF00L
+#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000L
+#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000L
+//PA_SU_SMALL_PRIM_FILTER_CNTL
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE__SHIFT 0x0
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x1
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x2
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x3
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x4
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK 0x00000001L
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000002L
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000004L
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000008L
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000010L
+//PA_CL_OBJPRIM_ID_CNTL
+#define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL__SHIFT 0x0
+#define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID__SHIFT 0x1
+#define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID__SHIFT 0x2
+#define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL_MASK 0x00000001L
+#define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID_MASK 0x00000002L
+#define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID_MASK 0x00000004L
+//PA_CL_NGG_CNTL
+#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF__SHIFT 0x0
+#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA__SHIFT 0x1
+#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF_MASK 0x00000001L
+#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA_MASK 0x00000002L
+//PA_SU_OVER_RASTERIZATION_CNTL
+#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES__SHIFT 0x0
+#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES__SHIFT 0x1
+#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS__SHIFT 0x2
+#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES__SHIFT 0x3
+#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW__SHIFT 0x4
+#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES_MASK 0x00000001L
+#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES_MASK 0x00000002L
+#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS_MASK 0x00000004L
+#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES_MASK 0x00000008L
+#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW_MASK 0x00000010L
+//PA_STEREO_CNTL
+#define PA_STEREO_CNTL__EN_STEREO__SHIFT 0x0
+#define PA_STEREO_CNTL__STEREO_MODE__SHIFT 0x1
+#define PA_STEREO_CNTL__RT_SLICE_MODE__SHIFT 0x5
+#define PA_STEREO_CNTL__RT_SLICE_OFFSET__SHIFT 0x8
+#define PA_STEREO_CNTL__VP_ID_MODE__SHIFT 0xa
+#define PA_STEREO_CNTL__VP_ID_OFFSET__SHIFT 0xd
+#define PA_STEREO_CNTL__EN_STEREO_MASK 0x00000001L
+#define PA_STEREO_CNTL__STEREO_MODE_MASK 0x0000001EL
+#define PA_STEREO_CNTL__RT_SLICE_MODE_MASK 0x000000E0L
+#define PA_STEREO_CNTL__RT_SLICE_OFFSET_MASK 0x00000300L
+#define PA_STEREO_CNTL__VP_ID_MODE_MASK 0x00001C00L
+#define PA_STEREO_CNTL__VP_ID_OFFSET_MASK 0x0001E000L
+//PA_SU_POINT_SIZE
+#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0
+#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10
+#define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000FFFFL
+#define PA_SU_POINT_SIZE__WIDTH_MASK 0xFFFF0000L
+//PA_SU_POINT_MINMAX
+#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0
+#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10
+#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000FFFFL
+#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xFFFF0000L
+//PA_SU_LINE_CNTL
+#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0
+#define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000FFFFL
+//PA_SC_LINE_STIPPLE
+#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0
+#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c
+#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d
+#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000FFFFL
+#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00FF0000L
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L
+#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000L
+//VGT_OUTPUT_PATH_CNTL
+#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x0
+#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x00000007L
+//VGT_HOS_CNTL
+#define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x0
+#define VGT_HOS_CNTL__TESS_MODE_MASK 0x00000003L
+//VGT_HOS_MAX_TESS_LEVEL
+#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0
+#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xFFFFFFFFL
+//VGT_HOS_MIN_TESS_LEVEL
+#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0
+#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xFFFFFFFFL
+//VGT_HOS_REUSE_DEPTH
+#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x0
+#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0x000000FFL
+//VGT_GROUP_PRIM_TYPE
+#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x0
+#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0xe
+#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0xf
+#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x10
+#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x0000001FL
+#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x00004000L
+#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x00008000L
+#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x00070000L
+//VGT_GROUP_FIRST_DECR
+#define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x0
+#define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0x0000000FL
+//VGT_GROUP_DECR
+#define VGT_GROUP_DECR__DECR__SHIFT 0x0
+#define VGT_GROUP_DECR__DECR_MASK 0x0000000FL
+//VGT_GROUP_VECT_0_CNTL
+#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x0
+#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x1
+#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x2
+#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x3
+#define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x8
+#define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x10
+#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x00000001L
+#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x00000002L
+#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x00000004L
+#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x00000008L
+#define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0x0000FF00L
+#define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0x00FF0000L
+//VGT_GROUP_VECT_1_CNTL
+#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x0
+#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x1
+#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x2
+#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x3
+#define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x8
+#define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x10
+#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x00000001L
+#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x00000002L
+#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x00000004L
+#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x00000008L
+#define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0x0000FF00L
+#define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0x00FF0000L
+//VGT_GROUP_VECT_0_FMT_CNTL
+#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x0
+#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x4
+#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x8
+#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0xc
+#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x10
+#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x14
+#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x18
+#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x1c
+#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0x0000000FL
+#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0x000000F0L
+#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0x00000F00L
+#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0x0000F000L
+#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0x000F0000L
+#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0x00F00000L
+#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0x0F000000L
+#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xF0000000L
+//VGT_GROUP_VECT_1_FMT_CNTL
+#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x0
+#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x4
+#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x8
+#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0xc
+#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x10
+#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x14
+#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x18
+#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x1c
+#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0x0000000FL
+#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0x000000F0L
+#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0x00000F00L
+#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0x0000F000L
+#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0x000F0000L
+#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0x00F00000L
+#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0x0F000000L
+#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xF0000000L
+//VGT_GS_MODE
+#define VGT_GS_MODE__MODE__SHIFT 0x0
+#define VGT_GS_MODE__RESERVED_0__SHIFT 0x3
+#define VGT_GS_MODE__CUT_MODE__SHIFT 0x4
+#define VGT_GS_MODE__RESERVED_1__SHIFT 0x6
+#define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0xb
+#define VGT_GS_MODE__RESERVED_2__SHIFT 0xc
+#define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0xd
+#define VGT_GS_MODE__RESERVED_3__SHIFT 0xe
+#define VGT_GS_MODE__RESERVED_4__SHIFT 0xf
+#define VGT_GS_MODE__RESERVED_5__SHIFT 0x10
+#define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x11
+#define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x12
+#define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x13
+#define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x14
+#define VGT_GS_MODE__ONCHIP__SHIFT 0x15
+#define VGT_GS_MODE__MODE_MASK 0x00000007L
+#define VGT_GS_MODE__RESERVED_0_MASK 0x00000008L
+#define VGT_GS_MODE__CUT_MODE_MASK 0x00000030L
+#define VGT_GS_MODE__RESERVED_1_MASK 0x000007C0L
+#define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x00000800L
+#define VGT_GS_MODE__RESERVED_2_MASK 0x00001000L
+#define VGT_GS_MODE__ES_PASSTHRU_MASK 0x00002000L
+#define VGT_GS_MODE__RESERVED_3_MASK 0x00004000L
+#define VGT_GS_MODE__RESERVED_4_MASK 0x00008000L
+#define VGT_GS_MODE__RESERVED_5_MASK 0x00010000L
+#define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x00020000L
+#define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x00040000L
+#define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x00080000L
+#define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x00100000L
+#define VGT_GS_MODE__ONCHIP_MASK 0x00600000L
+//VGT_GS_ONCHIP_CNTL
+#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT 0x0
+#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT 0xb
+#define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP__SHIFT 0x16
+#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK 0x000007FFL
+#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK 0x003FF800L
+#define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP_MASK 0xFFC00000L
+//PA_SC_MODE_CNTL_0
+#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0
+#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1
+#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2
+#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3
+#define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD__SHIFT 0x4
+#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE__SHIFT 0x5
+#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB__SHIFT 0x6
+#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x00000001L
+#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x00000002L
+#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x00000004L
+#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x00000008L
+#define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD_MASK 0x00000010L
+#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE_MASK 0x00000020L
+#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB_MASK 0x00000040L
+//PA_SC_MODE_CNTL_1
+#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0
+#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1
+#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2
+#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3
+#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4
+#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7
+#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8
+#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9
+#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa
+#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb
+#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc
+#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd
+#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe
+#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf
+#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10
+#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11
+#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12
+#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13
+#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14
+#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18
+#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19
+#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a
+#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b
+#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c
+#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x00000001L
+#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x00000002L
+#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x00000004L
+#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x00000008L
+#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x00000070L
+#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x00000080L
+#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x00000100L
+#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x00000200L
+#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x00000400L
+#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x00000800L
+#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x00001000L
+#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x00002000L
+#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x00004000L
+#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x00008000L
+#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x00010000L
+#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x00020000L
+#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x00040000L
+#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x00080000L
+#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0x00F00000L
+#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x01000000L
+#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x02000000L
+#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x04000000L
+#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x08000000L
+#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000L
+//VGT_ENHANCE
+#define VGT_ENHANCE__MISC__SHIFT 0x0
+#define VGT_ENHANCE__MISC_MASK 0xFFFFFFFFL
+//VGT_GS_PER_ES
+#define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x0
+#define VGT_GS_PER_ES__GS_PER_ES_MASK 0x000007FFL
+//VGT_ES_PER_GS
+#define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x0
+#define VGT_ES_PER_GS__ES_PER_GS_MASK 0x000007FFL
+//VGT_GS_PER_VS
+#define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x0
+#define VGT_GS_PER_VS__GS_PER_VS_MASK 0x0000000FL
+//VGT_GSVS_RING_OFFSET_1
+#define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x0
+#define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x00007FFFL
+//VGT_GSVS_RING_OFFSET_2
+#define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x0
+#define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x00007FFFL
+//VGT_GSVS_RING_OFFSET_3
+#define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x0
+#define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x00007FFFL
+//VGT_GS_OUT_PRIM_TYPE
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x8
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x10
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x16
+#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x1f
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x0000003FL
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x00003F00L
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x003F0000L
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0x0FC00000L
+#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000L
+//IA_ENHANCE
+#define IA_ENHANCE__MISC__SHIFT 0x0
+#define IA_ENHANCE__MISC_MASK 0xFFFFFFFFL
+//VGT_DMA_SIZE
+#define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0
+#define VGT_DMA_SIZE__NUM_INDICES_MASK 0xFFFFFFFFL
+//VGT_DMA_MAX_SIZE
+#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0
+#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xFFFFFFFFL
+//VGT_DMA_INDEX_TYPE
+#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
+#define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x2
+#define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x4
+#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6
+#define VGT_DMA_INDEX_TYPE__PRIMGEN_EN__SHIFT 0x8
+#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9
+#define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa
+#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L
+#define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0x0000000CL
+#define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x00000030L
+#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x00000040L
+#define VGT_DMA_INDEX_TYPE__PRIMGEN_EN_MASK 0x00000100L
+#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x00000200L
+#define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x00000400L
+//WD_ENHANCE
+#define WD_ENHANCE__MISC__SHIFT 0x0
+#define WD_ENHANCE__MISC_MASK 0xFFFFFFFFL
+//VGT_PRIMITIVEID_EN
+#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x0
+#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x1
+#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE__SHIFT 0x2
+#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x00000001L
+#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x00000002L
+#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE_MASK 0x00000004L
+//VGT_DMA_NUM_INSTANCES
+#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0
+#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL
+//VGT_PRIMITIVEID_RESET
+#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0
+#define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xFFFFFFFFL
+//VGT_EVENT_INITIATOR
+#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0
+#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa
+#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b
+#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL
+#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L
+#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L
+//VGT_GS_MAX_PRIMS_PER_SUBGROUP
+#define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP__SHIFT 0x0
+#define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP_MASK 0x0000FFFFL
+//VGT_DRAW_PAYLOAD_CNTL
+#define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN__SHIFT 0x0
+#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX__SHIFT 0x1
+#define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID__SHIFT 0x2
+#define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN__SHIFT 0x3
+#define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN_MASK 0x00000001L
+#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK 0x00000002L
+#define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID_MASK 0x00000004L
+#define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN_MASK 0x00000008L
+//VGT_INSTANCE_STEP_RATE_0
+#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0
+#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xFFFFFFFFL
+//VGT_INSTANCE_STEP_RATE_1
+#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x0
+#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xFFFFFFFFL
+//IA_MULTI_VGT_PARAM_BC
+//VGT_ESGS_RING_ITEMSIZE
+#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0
+#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL
+//VGT_GSVS_RING_ITEMSIZE
+#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0
+#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL
+//VGT_REUSE_OFF
+#define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0
+#define VGT_REUSE_OFF__REUSE_OFF_MASK 0x00000001L
+//VGT_VTX_CNT_EN
+#define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x0
+#define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x00000001L
+//DB_HTILE_SURFACE
+#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1
+#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x2
+#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x3
+#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x4
+#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa
+#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10
+#define DB_HTILE_SURFACE__PIPE_ALIGNED__SHIFT 0x12
+#define DB_HTILE_SURFACE__RB_ALIGNED__SHIFT 0x13
+#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x00000002L
+#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x00000004L
+#define DB_HTILE_SURFACE__PRELOAD_MASK 0x00000008L
+#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x000003F0L
+#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0x0000FC00L
+#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x00010000L
+#define DB_HTILE_SURFACE__PIPE_ALIGNED_MASK 0x00040000L
+#define DB_HTILE_SURFACE__RB_ALIGNED_MASK 0x00080000L
+//DB_SRESULTS_COMPARE_STATE0
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc
+#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x00000007L
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0x00000FF0L
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0x000FF000L
+#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x01000000L
+//DB_SRESULTS_COMPARE_STATE1
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc
+#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x00000007L
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0x00000FF0L
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0x000FF000L
+#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x01000000L
+//DB_PRELOAD_CONTROL
+#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0
+#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8
+#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10
+#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18
+#define DB_PRELOAD_CONTROL__START_X_MASK 0x000000FFL
+#define DB_PRELOAD_CONTROL__START_Y_MASK 0x0000FF00L
+#define DB_PRELOAD_CONTROL__MAX_X_MASK 0x00FF0000L
+#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xFF000000L
+//VGT_STRMOUT_BUFFER_SIZE_0
+#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_VTX_STRIDE_0
+#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x0
+#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x000003FFL
+//VGT_STRMOUT_BUFFER_OFFSET_0
+#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_BUFFER_SIZE_1
+#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_VTX_STRIDE_1
+#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x0
+#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x000003FFL
+//VGT_STRMOUT_BUFFER_OFFSET_1
+#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_BUFFER_SIZE_2
+#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_VTX_STRIDE_2
+#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x0
+#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x000003FFL
+//VGT_STRMOUT_BUFFER_OFFSET_2
+#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_BUFFER_SIZE_3
+#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_VTX_STRIDE_3
+#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x0
+#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x000003FFL
+//VGT_STRMOUT_BUFFER_OFFSET_3
+#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_DRAW_OPAQUE_OFFSET
+#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0
+#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
+#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
+#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0
+#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x000001FFL
+//VGT_GS_MAX_VERT_OUT
+#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0
+#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x000007FFL
+//VGT_TESS_DISTRIBUTION
+#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT 0x0
+#define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT 0x8
+#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT 0x10
+#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT 0x18
+#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT__SHIFT 0x1d
+#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK 0x000000FFL
+#define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK 0x0000FF00L
+#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0x00FF0000L
+#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK 0x1F000000L
+#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT_MASK 0xE0000000L
+//VGT_SHADER_STAGES_EN
+#define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x0
+#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2
+#define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x3
+#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5
+#define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x6
+#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT 0x9
+#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT 0xa
+#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT 0xb
+#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT 0xc
+#define VGT_SHADER_STAGES_EN__PRIMGEN_EN__SHIFT 0xd
+#define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE__SHIFT 0xe
+#define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE__SHIFT 0xf
+#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH__SHIFT 0x13
+#define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x00000003L
+#define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x00000004L
+#define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x00000018L
+#define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x00000020L
+#define VGT_SHADER_STAGES_EN__VS_EN_MASK 0x000000C0L
+#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK 0x00000200L
+#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK 0x00000400L
+#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK 0x00000800L
+#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK 0x00001000L
+#define VGT_SHADER_STAGES_EN__PRIMGEN_EN_MASK 0x00002000L
+#define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE_MASK 0x00004000L
+#define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE_MASK 0x00078000L
+#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH_MASK 0x00180000L
+//VGT_LS_HS_CONFIG
+#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0
+#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8
+#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe
+#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0x000000FFL
+#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L
+#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0x000FC000L
+//VGT_GS_VERT_ITEMSIZE
+#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x0
+#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL
+//VGT_GS_VERT_ITEMSIZE_1
+#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x0
+#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x00007FFFL
+//VGT_GS_VERT_ITEMSIZE_2
+#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x0
+#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x00007FFFL
+//VGT_GS_VERT_ITEMSIZE_3
+#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x0
+#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x00007FFFL
+//VGT_TF_PARAM
+#define VGT_TF_PARAM__TYPE__SHIFT 0x0
+#define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2
+#define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5
+#define VGT_TF_PARAM__DEPRECATED__SHIFT 0x9
+#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe
+#define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0xf
+#define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT 0x11
+#define VGT_TF_PARAM__TYPE_MASK 0x00000003L
+#define VGT_TF_PARAM__PARTITIONING_MASK 0x0000001CL
+#define VGT_TF_PARAM__TOPOLOGY_MASK 0x000000E0L
+#define VGT_TF_PARAM__DEPRECATED_MASK 0x00000200L
+#define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x00004000L
+#define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x00008000L
+#define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK 0x00060000L
+//DB_ALPHA_TO_MASK
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe
+#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x00000001L
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x00000300L
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0x00000C00L
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x00003000L
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0x0000C000L
+#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x00010000L
+//VGT_DISPATCH_DRAW_INDEX
+#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT 0x0
+#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK 0xFFFFFFFFL
+//PA_SU_POLY_OFFSET_DB_FMT_CNTL
+#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0
+#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8
+#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0x000000FFL
+#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x00000100L
+//PA_SU_POLY_OFFSET_CLAMP
+#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0
+#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xFFFFFFFFL
+//PA_SU_POLY_OFFSET_FRONT_SCALE
+#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0
+#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xFFFFFFFFL
+//PA_SU_POLY_OFFSET_FRONT_OFFSET
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xFFFFFFFFL
+//PA_SU_POLY_OFFSET_BACK_SCALE
+#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0
+#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xFFFFFFFFL
+//PA_SU_POLY_OFFSET_BACK_OFFSET
+#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0
+#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xFFFFFFFFL
+//VGT_GS_INSTANCE_CNT
+#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0
+#define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2
+#define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x00000001L
+#define VGT_GS_INSTANCE_CNT__CNT_MASK 0x000001FCL
+//VGT_STRMOUT_CONFIG
+#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x0
+#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x1
+#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x2
+#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x3
+#define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x4
+#define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT__SHIFT 0x7
+#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x8
+#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x1f
+#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x00000001L
+#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x00000002L
+#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x00000004L
+#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x00000008L
+#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x00000070L
+#define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT_MASK 0x00000080L
+#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0x00000F00L
+#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000L
+//VGT_STRMOUT_BUFFER_CONFIG
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x4
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x8
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0xc
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0x0000000FL
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0x000000F0L
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0x00000F00L
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0x0000F000L
+//VGT_DMA_EVENT_INITIATOR
+#define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0
+#define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa
+#define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b
+#define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL
+#define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L
+#define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L
+//PA_SC_CENTROID_PRIORITY_0
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0x0000000FL
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0x000000F0L
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0x00000F00L
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0x0000F000L
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0x000F0000L
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0x00F00000L
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0x0F000000L
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xF0000000L
+//PA_SC_CENTROID_PRIORITY_1
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0x0000000FL
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0x000000F0L
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0x00000F00L
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0x0000F000L
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0x000F0000L
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0x00F00000L
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0x0F000000L
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xF0000000L
+//PA_SC_LINE_CNTL
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9
+#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa
+#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb
+#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc
+#define PA_SC_LINE_CNTL__EXTRA_DX_DY_PRECISION__SHIFT 0xd
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L
+#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L
+#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x00000800L
+#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x00001000L
+#define PA_SC_LINE_CNTL__EXTRA_DX_DY_PRECISION_MASK 0x00002000L
+//PA_SC_AA_CONFIG
+#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0
+#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4
+#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd
+#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14
+#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18
+#define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT__SHIFT 0x1a
+#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L
+#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x00000010L
+#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x0001E000L
+#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x00700000L
+#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x03000000L
+#define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT_MASK 0x0C000000L
+//PA_SU_VTX_CNTL
+#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0
+#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1
+#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3
+#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L
+#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L
+#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L
+//PA_CL_GB_VERT_CLIP_ADJ
+#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_GB_VERT_DISC_ADJ
+#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_GB_HORZ_CLIP_ADJ
+#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_GB_HORZ_DISC_ADJ
+#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xF0000000L
+//PA_SC_AA_MASK_X0Y0_X1Y0
+#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0
+#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10
+#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0x0000FFFFL
+#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xFFFF0000L
+//PA_SC_AA_MASK_X0Y1_X1Y1
+#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0
+#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10
+#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0x0000FFFFL
+#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xFFFF0000L
+//PA_SC_SHADER_CONTROL
+#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT 0x0
+#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID__SHIFT 0x2
+#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION__SHIFT 0x3
+#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK 0x00000003L
+#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID_MASK 0x00000004L
+#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION_MASK 0x00000008L
+//PA_SC_BINNER_CNTL_0
+#define PA_SC_BINNER_CNTL_0__BINNING_MODE__SHIFT 0x0
+#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X__SHIFT 0x2
+#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y__SHIFT 0x3
+#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND__SHIFT 0x4
+#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND__SHIFT 0x7
+#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT 0xa
+#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN__SHIFT 0xd
+#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM__SHIFT 0x12
+#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT 0x13
+#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION__SHIFT 0x1b
+#define PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION__SHIFT 0x1c
+#define PA_SC_BINNER_CNTL_0__BINNING_MODE_MASK 0x00000003L
+#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_MASK 0x00000004L
+#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_MASK 0x00000008L
+#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND_MASK 0x00000070L
+#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND_MASK 0x00000380L
+#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN_MASK 0x00001C00L
+#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN_MASK 0x0003E000L
+#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM_MASK 0x00040000L
+#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH_MASK 0x07F80000L
+#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION_MASK 0x08000000L
+#define PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION_MASK 0x10000000L
+//PA_SC_BINNER_CNTL_1
+#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT__SHIFT 0x0
+#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH__SHIFT 0x10
+#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT_MASK 0x0000FFFFL
+#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH_MASK 0xFFFF0000L
+//PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE__SHIFT 0x0
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT__SHIFT 0x1
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE__SHIFT 0x5
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT__SHIFT 0x6
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT 0xa
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT__SHIFT 0xb
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET__SHIFT 0xc
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL__SHIFT 0xd
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL__SHIFT 0xe
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE__SHIFT 0xf
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE__SHIFT 0x10
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x12
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x13
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE__SHIFT 0x14
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE__SHIFT 0x15
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE__SHIFT 0x16
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE__SHIFT 0x17
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE__SHIFT 0x18
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE_MASK 0x00000001L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT_MASK 0x0000001EL
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE_MASK 0x00000020L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT_MASK 0x000003C0L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE_MASK 0x00000400L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT_MASK 0x00000800L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET_MASK 0x00001000L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL_MASK 0x00002000L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL_MASK 0x00004000L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE_MASK 0x00008000L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE_MASK 0x00030000L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00040000L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00080000L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE_MASK 0x00100000L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE_MASK 0x00200000L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE_MASK 0x00400000L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE_MASK 0x00800000L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE_MASK 0x01000000L
+//PA_SC_NGG_MODE_CNTL
+#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE__SHIFT 0x0
+#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE_MASK 0x000007FFL
+//VGT_VERTEX_REUSE_BLOCK_CNTL
+#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x0
+#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0x000000FFL
+//VGT_OUT_DEALLOC_CNTL
+#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x0
+#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x0000007FL
+//CB_COLOR0_BASE
+#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR0_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR0_BASE_EXT
+#define CB_COLOR0_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR0_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR0_ATTRIB2
+#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
+#define CB_COLOR0_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
+#define CB_COLOR0_ATTRIB2__MAX_MIP__SHIFT 0x1c
+#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
+#define CB_COLOR0_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
+#define CB_COLOR0_ATTRIB2__MAX_MIP_MASK 0xF0000000L
+//CB_COLOR0_VIEW
+#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR0_VIEW__MIP_LEVEL__SHIFT 0x18
+#define CB_COLOR0_VIEW__SLICE_START_MASK 0x000007FFL
+#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0x00FFE000L
+#define CB_COLOR0_VIEW__MIP_LEVEL_MASK 0x0F000000L
+//CB_COLOR0_INFO
+#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR0_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR0_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR0_INFO__ENDIAN_MASK 0x00000003L
+#define CB_COLOR0_INFO__FORMAT_MASK 0x0000007CL
+#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x00000700L
+#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x00001800L
+#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x00002000L
+#define CB_COLOR0_INFO__COMPRESSION_MASK 0x00004000L
+#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x00008000L
+#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x00010000L
+#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x00020000L
+#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x00040000L
+#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
+#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
+#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
+#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
+#define CB_COLOR0_INFO__DCC_ENABLE_MASK 0x10000000L
+#define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
+//CB_COLOR0_ATTRIB
+#define CB_COLOR0_ATTRIB__MIP0_DEPTH__SHIFT 0x0
+#define CB_COLOR0_ATTRIB__META_LINEAR__SHIFT 0xb
+#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR0_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
+#define CB_COLOR0_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
+#define CB_COLOR0_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
+#define CB_COLOR0_ATTRIB__RB_ALIGNED__SHIFT 0x1e
+#define CB_COLOR0_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
+#define CB_COLOR0_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
+#define CB_COLOR0_ATTRIB__META_LINEAR_MASK 0x00000800L
+#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
+#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
+#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
+#define CB_COLOR0_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
+#define CB_COLOR0_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
+#define CB_COLOR0_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
+#define CB_COLOR0_ATTRIB__RB_ALIGNED_MASK 0x40000000L
+#define CB_COLOR0_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
+//CB_COLOR0_DCC_CONTROL
+#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR0_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12
+#define CB_COLOR0_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13
+#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
+#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
+#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
+#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
+#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
+#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
+#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
+#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
+#define CB_COLOR0_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L
+#define CB_COLOR0_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L
+//CB_COLOR0_CMASK
+#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR0_CMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR0_CMASK_BASE_EXT
+#define CB_COLOR0_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR0_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR0_FMASK
+#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR0_FMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR0_FMASK_BASE_EXT
+#define CB_COLOR0_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR0_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR0_CLEAR_WORD0
+#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
+//CB_COLOR0_CLEAR_WORD1
+#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
+//CB_COLOR0_DCC_BASE
+#define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR0_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR0_DCC_BASE_EXT
+#define CB_COLOR0_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR0_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR1_BASE
+#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR1_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR1_BASE_EXT
+#define CB_COLOR1_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR1_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR1_ATTRIB2
+#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
+#define CB_COLOR1_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
+#define CB_COLOR1_ATTRIB2__MAX_MIP__SHIFT 0x1c
+#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
+#define CB_COLOR1_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
+#define CB_COLOR1_ATTRIB2__MAX_MIP_MASK 0xF0000000L
+//CB_COLOR1_VIEW
+#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR1_VIEW__MIP_LEVEL__SHIFT 0x18
+#define CB_COLOR1_VIEW__SLICE_START_MASK 0x000007FFL
+#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0x00FFE000L
+#define CB_COLOR1_VIEW__MIP_LEVEL_MASK 0x0F000000L
+//CB_COLOR1_INFO
+#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR1_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR1_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR1_INFO__ENDIAN_MASK 0x00000003L
+#define CB_COLOR1_INFO__FORMAT_MASK 0x0000007CL
+#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x00000700L
+#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x00001800L
+#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x00002000L
+#define CB_COLOR1_INFO__COMPRESSION_MASK 0x00004000L
+#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x00008000L
+#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x00010000L
+#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x00020000L
+#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x00040000L
+#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
+#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
+#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
+#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
+#define CB_COLOR1_INFO__DCC_ENABLE_MASK 0x10000000L
+#define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
+//CB_COLOR1_ATTRIB
+#define CB_COLOR1_ATTRIB__MIP0_DEPTH__SHIFT 0x0
+#define CB_COLOR1_ATTRIB__META_LINEAR__SHIFT 0xb
+#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR1_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
+#define CB_COLOR1_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
+#define CB_COLOR1_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
+#define CB_COLOR1_ATTRIB__RB_ALIGNED__SHIFT 0x1e
+#define CB_COLOR1_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
+#define CB_COLOR1_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
+#define CB_COLOR1_ATTRIB__META_LINEAR_MASK 0x00000800L
+#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
+#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
+#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
+#define CB_COLOR1_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
+#define CB_COLOR1_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
+#define CB_COLOR1_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
+#define CB_COLOR1_ATTRIB__RB_ALIGNED_MASK 0x40000000L
+#define CB_COLOR1_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
+//CB_COLOR1_DCC_CONTROL
+#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR1_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12
+#define CB_COLOR1_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13
+#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
+#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
+#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
+#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
+#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
+#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
+#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
+#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
+#define CB_COLOR1_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L
+#define CB_COLOR1_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L
+//CB_COLOR1_CMASK
+#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR1_CMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR1_CMASK_BASE_EXT
+#define CB_COLOR1_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR1_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR1_FMASK
+#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR1_FMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR1_FMASK_BASE_EXT
+#define CB_COLOR1_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR1_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR1_CLEAR_WORD0
+#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
+//CB_COLOR1_CLEAR_WORD1
+#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
+//CB_COLOR1_DCC_BASE
+#define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR1_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR1_DCC_BASE_EXT
+#define CB_COLOR1_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR1_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR2_BASE
+#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR2_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR2_BASE_EXT
+#define CB_COLOR2_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR2_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR2_ATTRIB2
+#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
+#define CB_COLOR2_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
+#define CB_COLOR2_ATTRIB2__MAX_MIP__SHIFT 0x1c
+#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
+#define CB_COLOR2_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
+#define CB_COLOR2_ATTRIB2__MAX_MIP_MASK 0xF0000000L
+//CB_COLOR2_VIEW
+#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR2_VIEW__MIP_LEVEL__SHIFT 0x18
+#define CB_COLOR2_VIEW__SLICE_START_MASK 0x000007FFL
+#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0x00FFE000L
+#define CB_COLOR2_VIEW__MIP_LEVEL_MASK 0x0F000000L
+//CB_COLOR2_INFO
+#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR2_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR2_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR2_INFO__ENDIAN_MASK 0x00000003L
+#define CB_COLOR2_INFO__FORMAT_MASK 0x0000007CL
+#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x00000700L
+#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x00001800L
+#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x00002000L
+#define CB_COLOR2_INFO__COMPRESSION_MASK 0x00004000L
+#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x00008000L
+#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x00010000L
+#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x00020000L
+#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x00040000L
+#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
+#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
+#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
+#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
+#define CB_COLOR2_INFO__DCC_ENABLE_MASK 0x10000000L
+#define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
+//CB_COLOR2_ATTRIB
+#define CB_COLOR2_ATTRIB__MIP0_DEPTH__SHIFT 0x0
+#define CB_COLOR2_ATTRIB__META_LINEAR__SHIFT 0xb
+#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR2_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
+#define CB_COLOR2_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
+#define CB_COLOR2_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
+#define CB_COLOR2_ATTRIB__RB_ALIGNED__SHIFT 0x1e
+#define CB_COLOR2_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
+#define CB_COLOR2_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
+#define CB_COLOR2_ATTRIB__META_LINEAR_MASK 0x00000800L
+#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
+#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
+#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
+#define CB_COLOR2_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
+#define CB_COLOR2_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
+#define CB_COLOR2_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
+#define CB_COLOR2_ATTRIB__RB_ALIGNED_MASK 0x40000000L
+#define CB_COLOR2_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
+//CB_COLOR2_DCC_CONTROL
+#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR2_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12
+#define CB_COLOR2_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13
+#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
+#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
+#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
+#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
+#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
+#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
+#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
+#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
+#define CB_COLOR2_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L
+#define CB_COLOR2_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L
+//CB_COLOR2_CMASK
+#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR2_CMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR2_CMASK_BASE_EXT
+#define CB_COLOR2_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR2_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR2_FMASK
+#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR2_FMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR2_FMASK_BASE_EXT
+#define CB_COLOR2_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR2_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR2_CLEAR_WORD0
+#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
+//CB_COLOR2_CLEAR_WORD1
+#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
+//CB_COLOR2_DCC_BASE
+#define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR2_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR2_DCC_BASE_EXT
+#define CB_COLOR2_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR2_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR3_BASE
+#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR3_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR3_BASE_EXT
+#define CB_COLOR3_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR3_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR3_ATTRIB2
+#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
+#define CB_COLOR3_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
+#define CB_COLOR3_ATTRIB2__MAX_MIP__SHIFT 0x1c
+#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
+#define CB_COLOR3_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
+#define CB_COLOR3_ATTRIB2__MAX_MIP_MASK 0xF0000000L
+//CB_COLOR3_VIEW
+#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR3_VIEW__MIP_LEVEL__SHIFT 0x18
+#define CB_COLOR3_VIEW__SLICE_START_MASK 0x000007FFL
+#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0x00FFE000L
+#define CB_COLOR3_VIEW__MIP_LEVEL_MASK 0x0F000000L
+//CB_COLOR3_INFO
+#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR3_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR3_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR3_INFO__ENDIAN_MASK 0x00000003L
+#define CB_COLOR3_INFO__FORMAT_MASK 0x0000007CL
+#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x00000700L
+#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x00001800L
+#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x00002000L
+#define CB_COLOR3_INFO__COMPRESSION_MASK 0x00004000L
+#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x00008000L
+#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x00010000L
+#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x00020000L
+#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x00040000L
+#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
+#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
+#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
+#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
+#define CB_COLOR3_INFO__DCC_ENABLE_MASK 0x10000000L
+#define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
+//CB_COLOR3_ATTRIB
+#define CB_COLOR3_ATTRIB__MIP0_DEPTH__SHIFT 0x0
+#define CB_COLOR3_ATTRIB__META_LINEAR__SHIFT 0xb
+#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR3_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
+#define CB_COLOR3_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
+#define CB_COLOR3_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
+#define CB_COLOR3_ATTRIB__RB_ALIGNED__SHIFT 0x1e
+#define CB_COLOR3_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
+#define CB_COLOR3_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
+#define CB_COLOR3_ATTRIB__META_LINEAR_MASK 0x00000800L
+#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
+#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
+#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
+#define CB_COLOR3_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
+#define CB_COLOR3_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
+#define CB_COLOR3_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
+#define CB_COLOR3_ATTRIB__RB_ALIGNED_MASK 0x40000000L
+#define CB_COLOR3_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
+//CB_COLOR3_DCC_CONTROL
+#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR3_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12
+#define CB_COLOR3_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13
+#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
+#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
+#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
+#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
+#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
+#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
+#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
+#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
+#define CB_COLOR3_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L
+#define CB_COLOR3_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L
+//CB_COLOR3_CMASK
+#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR3_CMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR3_CMASK_BASE_EXT
+#define CB_COLOR3_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR3_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR3_FMASK
+#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR3_FMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR3_FMASK_BASE_EXT
+#define CB_COLOR3_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR3_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR3_CLEAR_WORD0
+#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
+//CB_COLOR3_CLEAR_WORD1
+#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
+//CB_COLOR3_DCC_BASE
+#define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR3_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR3_DCC_BASE_EXT
+#define CB_COLOR3_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR3_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR4_BASE
+#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR4_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR4_BASE_EXT
+#define CB_COLOR4_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR4_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR4_ATTRIB2
+#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
+#define CB_COLOR4_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
+#define CB_COLOR4_ATTRIB2__MAX_MIP__SHIFT 0x1c
+#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
+#define CB_COLOR4_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
+#define CB_COLOR4_ATTRIB2__MAX_MIP_MASK 0xF0000000L
+//CB_COLOR4_VIEW
+#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR4_VIEW__MIP_LEVEL__SHIFT 0x18
+#define CB_COLOR4_VIEW__SLICE_START_MASK 0x000007FFL
+#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0x00FFE000L
+#define CB_COLOR4_VIEW__MIP_LEVEL_MASK 0x0F000000L
+//CB_COLOR4_INFO
+#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR4_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR4_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR4_INFO__ENDIAN_MASK 0x00000003L
+#define CB_COLOR4_INFO__FORMAT_MASK 0x0000007CL
+#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x00000700L
+#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x00001800L
+#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x00002000L
+#define CB_COLOR4_INFO__COMPRESSION_MASK 0x00004000L
+#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x00008000L
+#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x00010000L
+#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x00020000L
+#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x00040000L
+#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
+#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
+#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
+#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
+#define CB_COLOR4_INFO__DCC_ENABLE_MASK 0x10000000L
+#define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
+//CB_COLOR4_ATTRIB
+#define CB_COLOR4_ATTRIB__MIP0_DEPTH__SHIFT 0x0
+#define CB_COLOR4_ATTRIB__META_LINEAR__SHIFT 0xb
+#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR4_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
+#define CB_COLOR4_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
+#define CB_COLOR4_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
+#define CB_COLOR4_ATTRIB__RB_ALIGNED__SHIFT 0x1e
+#define CB_COLOR4_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
+#define CB_COLOR4_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
+#define CB_COLOR4_ATTRIB__META_LINEAR_MASK 0x00000800L
+#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
+#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
+#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
+#define CB_COLOR4_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
+#define CB_COLOR4_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
+#define CB_COLOR4_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
+#define CB_COLOR4_ATTRIB__RB_ALIGNED_MASK 0x40000000L
+#define CB_COLOR4_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
+//CB_COLOR4_DCC_CONTROL
+#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR4_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12
+#define CB_COLOR4_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13
+#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
+#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
+#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
+#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
+#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
+#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
+#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
+#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
+#define CB_COLOR4_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L
+#define CB_COLOR4_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L
+//CB_COLOR4_CMASK
+#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR4_CMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR4_CMASK_BASE_EXT
+#define CB_COLOR4_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR4_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR4_FMASK
+#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR4_FMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR4_FMASK_BASE_EXT
+#define CB_COLOR4_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR4_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR4_CLEAR_WORD0
+#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
+//CB_COLOR4_CLEAR_WORD1
+#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
+//CB_COLOR4_DCC_BASE
+#define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR4_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR4_DCC_BASE_EXT
+#define CB_COLOR4_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR4_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR5_BASE
+#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR5_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR5_BASE_EXT
+#define CB_COLOR5_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR5_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR5_ATTRIB2
+#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
+#define CB_COLOR5_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
+#define CB_COLOR5_ATTRIB2__MAX_MIP__SHIFT 0x1c
+#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
+#define CB_COLOR5_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
+#define CB_COLOR5_ATTRIB2__MAX_MIP_MASK 0xF0000000L
+//CB_COLOR5_VIEW
+#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR5_VIEW__MIP_LEVEL__SHIFT 0x18
+#define CB_COLOR5_VIEW__SLICE_START_MASK 0x000007FFL
+#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0x00FFE000L
+#define CB_COLOR5_VIEW__MIP_LEVEL_MASK 0x0F000000L
+//CB_COLOR5_INFO
+#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR5_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR5_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR5_INFO__ENDIAN_MASK 0x00000003L
+#define CB_COLOR5_INFO__FORMAT_MASK 0x0000007CL
+#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x00000700L
+#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x00001800L
+#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x00002000L
+#define CB_COLOR5_INFO__COMPRESSION_MASK 0x00004000L
+#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x00008000L
+#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x00010000L
+#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x00020000L
+#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x00040000L
+#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
+#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
+#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
+#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
+#define CB_COLOR5_INFO__DCC_ENABLE_MASK 0x10000000L
+#define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
+//CB_COLOR5_ATTRIB
+#define CB_COLOR5_ATTRIB__MIP0_DEPTH__SHIFT 0x0
+#define CB_COLOR5_ATTRIB__META_LINEAR__SHIFT 0xb
+#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR5_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
+#define CB_COLOR5_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
+#define CB_COLOR5_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
+#define CB_COLOR5_ATTRIB__RB_ALIGNED__SHIFT 0x1e
+#define CB_COLOR5_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
+#define CB_COLOR5_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
+#define CB_COLOR5_ATTRIB__META_LINEAR_MASK 0x00000800L
+#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
+#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
+#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
+#define CB_COLOR5_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
+#define CB_COLOR5_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
+#define CB_COLOR5_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
+#define CB_COLOR5_ATTRIB__RB_ALIGNED_MASK 0x40000000L
+#define CB_COLOR5_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
+//CB_COLOR5_DCC_CONTROL
+#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR5_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12
+#define CB_COLOR5_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13
+#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
+#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
+#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
+#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
+#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
+#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
+#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
+#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
+#define CB_COLOR5_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L
+#define CB_COLOR5_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L
+//CB_COLOR5_CMASK
+#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR5_CMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR5_CMASK_BASE_EXT
+#define CB_COLOR5_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR5_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR5_FMASK
+#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR5_FMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR5_FMASK_BASE_EXT
+#define CB_COLOR5_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR5_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR5_CLEAR_WORD0
+#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
+//CB_COLOR5_CLEAR_WORD1
+#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
+//CB_COLOR5_DCC_BASE
+#define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR5_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR5_DCC_BASE_EXT
+#define CB_COLOR5_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR5_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR6_BASE
+#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR6_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR6_BASE_EXT
+#define CB_COLOR6_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR6_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR6_ATTRIB2
+#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
+#define CB_COLOR6_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
+#define CB_COLOR6_ATTRIB2__MAX_MIP__SHIFT 0x1c
+#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
+#define CB_COLOR6_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
+#define CB_COLOR6_ATTRIB2__MAX_MIP_MASK 0xF0000000L
+//CB_COLOR6_VIEW
+#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR6_VIEW__MIP_LEVEL__SHIFT 0x18
+#define CB_COLOR6_VIEW__SLICE_START_MASK 0x000007FFL
+#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0x00FFE000L
+#define CB_COLOR6_VIEW__MIP_LEVEL_MASK 0x0F000000L
+//CB_COLOR6_INFO
+#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR6_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR6_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR6_INFO__ENDIAN_MASK 0x00000003L
+#define CB_COLOR6_INFO__FORMAT_MASK 0x0000007CL
+#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x00000700L
+#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x00001800L
+#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x00002000L
+#define CB_COLOR6_INFO__COMPRESSION_MASK 0x00004000L
+#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x00008000L
+#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x00010000L
+#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x00020000L
+#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x00040000L
+#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
+#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
+#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
+#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
+#define CB_COLOR6_INFO__DCC_ENABLE_MASK 0x10000000L
+#define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
+//CB_COLOR6_ATTRIB
+#define CB_COLOR6_ATTRIB__MIP0_DEPTH__SHIFT 0x0
+#define CB_COLOR6_ATTRIB__META_LINEAR__SHIFT 0xb
+#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR6_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
+#define CB_COLOR6_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
+#define CB_COLOR6_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
+#define CB_COLOR6_ATTRIB__RB_ALIGNED__SHIFT 0x1e
+#define CB_COLOR6_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
+#define CB_COLOR6_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
+#define CB_COLOR6_ATTRIB__META_LINEAR_MASK 0x00000800L
+#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
+#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
+#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
+#define CB_COLOR6_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
+#define CB_COLOR6_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
+#define CB_COLOR6_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
+#define CB_COLOR6_ATTRIB__RB_ALIGNED_MASK 0x40000000L
+#define CB_COLOR6_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
+//CB_COLOR6_DCC_CONTROL
+#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR6_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12
+#define CB_COLOR6_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13
+#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
+#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
+#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
+#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
+#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
+#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
+#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
+#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
+#define CB_COLOR6_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L
+#define CB_COLOR6_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L
+//CB_COLOR6_CMASK
+#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR6_CMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR6_CMASK_BASE_EXT
+#define CB_COLOR6_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR6_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR6_FMASK
+#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR6_FMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR6_FMASK_BASE_EXT
+#define CB_COLOR6_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR6_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR6_CLEAR_WORD0
+#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
+//CB_COLOR6_CLEAR_WORD1
+#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
+//CB_COLOR6_DCC_BASE
+#define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR6_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR6_DCC_BASE_EXT
+#define CB_COLOR6_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR6_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR7_BASE
+#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR7_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR7_BASE_EXT
+#define CB_COLOR7_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR7_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR7_ATTRIB2
+#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
+#define CB_COLOR7_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
+#define CB_COLOR7_ATTRIB2__MAX_MIP__SHIFT 0x1c
+#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
+#define CB_COLOR7_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
+#define CB_COLOR7_ATTRIB2__MAX_MIP_MASK 0xF0000000L
+//CB_COLOR7_VIEW
+#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR7_VIEW__MIP_LEVEL__SHIFT 0x18
+#define CB_COLOR7_VIEW__SLICE_START_MASK 0x000007FFL
+#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0x00FFE000L
+#define CB_COLOR7_VIEW__MIP_LEVEL_MASK 0x0F000000L
+//CB_COLOR7_INFO
+#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR7_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR7_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR7_INFO__ENDIAN_MASK 0x00000003L
+#define CB_COLOR7_INFO__FORMAT_MASK 0x0000007CL
+#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x00000700L
+#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x00001800L
+#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x00002000L
+#define CB_COLOR7_INFO__COMPRESSION_MASK 0x00004000L
+#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x00008000L
+#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x00010000L
+#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x00020000L
+#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x00040000L
+#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
+#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
+#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
+#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
+#define CB_COLOR7_INFO__DCC_ENABLE_MASK 0x10000000L
+#define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
+//CB_COLOR7_ATTRIB
+#define CB_COLOR7_ATTRIB__MIP0_DEPTH__SHIFT 0x0
+#define CB_COLOR7_ATTRIB__META_LINEAR__SHIFT 0xb
+#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR7_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
+#define CB_COLOR7_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
+#define CB_COLOR7_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
+#define CB_COLOR7_ATTRIB__RB_ALIGNED__SHIFT 0x1e
+#define CB_COLOR7_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
+#define CB_COLOR7_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
+#define CB_COLOR7_ATTRIB__META_LINEAR_MASK 0x00000800L
+#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
+#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
+#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
+#define CB_COLOR7_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
+#define CB_COLOR7_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
+#define CB_COLOR7_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
+#define CB_COLOR7_ATTRIB__RB_ALIGNED_MASK 0x40000000L
+#define CB_COLOR7_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
+//CB_COLOR7_DCC_CONTROL
+#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR7_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12
+#define CB_COLOR7_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13
+#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
+#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
+#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
+#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
+#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
+#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
+#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
+#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
+#define CB_COLOR7_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L
+#define CB_COLOR7_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L
+//CB_COLOR7_CMASK
+#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR7_CMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR7_CMASK_BASE_EXT
+#define CB_COLOR7_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR7_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR7_FMASK
+#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR7_FMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR7_FMASK_BASE_EXT
+#define CB_COLOR7_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR7_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR7_CLEAR_WORD0
+#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
+//CB_COLOR7_CLEAR_WORD1
+#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
+//CB_COLOR7_DCC_BASE
+#define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR7_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR7_DCC_BASE_EXT
+#define CB_COLOR7_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR7_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
+
+
+// addressBlock: gc_gfxudec
+//CP_EOP_DONE_ADDR_LO
+#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2
+#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL
+//CP_EOP_DONE_ADDR_HI
+#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
+//CP_EOP_DONE_DATA_LO
+#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0
+#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xFFFFFFFFL
+//CP_EOP_DONE_DATA_HI
+#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0
+#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xFFFFFFFFL
+//CP_EOP_LAST_FENCE_LO
+#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0
+#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xFFFFFFFFL
+//CP_EOP_LAST_FENCE_HI
+#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0
+#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xFFFFFFFFL
+//CP_STREAM_OUT_ADDR_LO
+#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2
+#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xFFFFFFFCL
+//CP_STREAM_OUT_ADDR_HI
+#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0
+#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0x0000FFFFL
+//CP_NUM_PRIM_WRITTEN_COUNT0_LO
+#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_WRITTEN_COUNT0_HI
+#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_NEEDED_COUNT0_LO
+#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_NEEDED_COUNT0_HI
+#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_WRITTEN_COUNT1_LO
+#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_WRITTEN_COUNT1_HI
+#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_NEEDED_COUNT1_LO
+#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_NEEDED_COUNT1_HI
+#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_WRITTEN_COUNT2_LO
+#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_WRITTEN_COUNT2_HI
+#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_NEEDED_COUNT2_LO
+#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_NEEDED_COUNT2_HI
+#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_WRITTEN_COUNT3_LO
+#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_WRITTEN_COUNT3_HI
+#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_NEEDED_COUNT3_LO
+#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_NEEDED_COUNT3_HI
+#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xFFFFFFFFL
+//CP_PIPE_STATS_ADDR_LO
+#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2
+#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xFFFFFFFCL
+//CP_PIPE_STATS_ADDR_HI
+#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0
+#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0x0000FFFFL
+//CP_VGT_IAVERT_COUNT_LO
+#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0
+#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xFFFFFFFFL
+//CP_VGT_IAVERT_COUNT_HI
+#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0
+#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xFFFFFFFFL
+//CP_VGT_IAPRIM_COUNT_LO
+#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0
+#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xFFFFFFFFL
+//CP_VGT_IAPRIM_COUNT_HI
+#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0
+#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xFFFFFFFFL
+//CP_VGT_GSPRIM_COUNT_LO
+#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0
+#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xFFFFFFFFL
+//CP_VGT_GSPRIM_COUNT_HI
+#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0
+#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xFFFFFFFFL
+//CP_VGT_VSINVOC_COUNT_LO
+#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0
+#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xFFFFFFFFL
+//CP_VGT_VSINVOC_COUNT_HI
+#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0
+#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xFFFFFFFFL
+//CP_VGT_GSINVOC_COUNT_LO
+#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0
+#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xFFFFFFFFL
+//CP_VGT_GSINVOC_COUNT_HI
+#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0
+#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xFFFFFFFFL
+//CP_VGT_HSINVOC_COUNT_LO
+#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0
+#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xFFFFFFFFL
+//CP_VGT_HSINVOC_COUNT_HI
+#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0
+#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xFFFFFFFFL
+//CP_VGT_DSINVOC_COUNT_LO
+#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0
+#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xFFFFFFFFL
+//CP_VGT_DSINVOC_COUNT_HI
+#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0
+#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xFFFFFFFFL
+//CP_PA_CINVOC_COUNT_LO
+#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0
+#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xFFFFFFFFL
+//CP_PA_CINVOC_COUNT_HI
+#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0
+#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xFFFFFFFFL
+//CP_PA_CPRIM_COUNT_LO
+#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0
+#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xFFFFFFFFL
+//CP_PA_CPRIM_COUNT_HI
+#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0
+#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xFFFFFFFFL
+//CP_SC_PSINVOC_COUNT0_LO
+#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0
+#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xFFFFFFFFL
+//CP_SC_PSINVOC_COUNT0_HI
+#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0
+#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xFFFFFFFFL
+//CP_SC_PSINVOC_COUNT1_LO
+#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0
+#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xFFFFFFFFL
+//CP_SC_PSINVOC_COUNT1_HI
+#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0
+#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xFFFFFFFFL
+//CP_VGT_CSINVOC_COUNT_LO
+#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0
+#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xFFFFFFFFL
+//CP_VGT_CSINVOC_COUNT_HI
+#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0
+#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xFFFFFFFFL
+//CP_PIPE_STATS_CONTROL
+#define CP_PIPE_STATS_CONTROL__CACHE_POLICY__SHIFT 0x19
+#define CP_PIPE_STATS_CONTROL__CACHE_POLICY_MASK 0x02000000L
+//CP_STREAM_OUT_CONTROL
+#define CP_STREAM_OUT_CONTROL__CACHE_POLICY__SHIFT 0x19
+#define CP_STREAM_OUT_CONTROL__CACHE_POLICY_MASK 0x02000000L
+//CP_STRMOUT_CNTL
+#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0
+#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x00000001L
+//SCRATCH_REG0
+#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
+#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL
+//SCRATCH_REG1
+#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
+#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL
+//SCRATCH_REG2
+#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
+#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL
+//SCRATCH_REG3
+#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
+#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL
+//SCRATCH_REG4
+#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
+#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL
+//SCRATCH_REG5
+#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
+#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL
+//SCRATCH_REG6
+#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
+#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL
+//SCRATCH_REG7
+#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
+#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL
+//CP_APPEND_DATA_HI
+#define CP_APPEND_DATA_HI__DATA__SHIFT 0x0
+#define CP_APPEND_DATA_HI__DATA_MASK 0xFFFFFFFFL
+//CP_APPEND_LAST_CS_FENCE_HI
+#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE__SHIFT 0x0
+#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL
+//CP_APPEND_LAST_PS_FENCE_HI
+#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE__SHIFT 0x0
+#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL
+//SCRATCH_UMSK
+#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0
+#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10
+#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0x000000FFL
+#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x00030000L
+//SCRATCH_ADDR
+#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0
+#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xFFFFFFFFL
+//CP_PFP_ATOMIC_PREOP_LO
+#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
+#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL
+//CP_PFP_ATOMIC_PREOP_HI
+#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
+#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL
+//CP_PFP_GDS_ATOMIC0_PREOP_LO
+#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
+#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL
+//CP_PFP_GDS_ATOMIC0_PREOP_HI
+#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
+#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL
+//CP_PFP_GDS_ATOMIC1_PREOP_LO
+#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
+#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL
+//CP_PFP_GDS_ATOMIC1_PREOP_HI
+#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
+#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL
+//CP_APPEND_ADDR_LO
+#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2
+#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xFFFFFFFCL
+//CP_APPEND_ADDR_HI
+#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0
+#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10
+#define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT 0x19
+#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d
+#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0x0000FFFFL
+#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x00010000L
+#define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK 0x02000000L
+#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xE0000000L
+//CP_APPEND_DATA_LO
+#define CP_APPEND_DATA_LO__DATA__SHIFT 0x0
+#define CP_APPEND_DATA_LO__DATA_MASK 0xFFFFFFFFL
+//CP_APPEND_LAST_CS_FENCE_LO
+#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE__SHIFT 0x0
+#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL
+//CP_APPEND_LAST_PS_FENCE_LO
+#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE__SHIFT 0x0
+#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL
+//CP_ATOMIC_PREOP_LO
+#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
+#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL
+//CP_ME_ATOMIC_PREOP_LO
+#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
+#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL
+//CP_ATOMIC_PREOP_HI
+#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
+#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL
+//CP_ME_ATOMIC_PREOP_HI
+#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
+#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL
+//CP_GDS_ATOMIC0_PREOP_LO
+#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
+#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL
+//CP_ME_GDS_ATOMIC0_PREOP_LO
+#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
+#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL
+//CP_GDS_ATOMIC0_PREOP_HI
+#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
+#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL
+//CP_ME_GDS_ATOMIC0_PREOP_HI
+#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
+#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL
+//CP_GDS_ATOMIC1_PREOP_LO
+#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
+#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL
+//CP_ME_GDS_ATOMIC1_PREOP_LO
+#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
+#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL
+//CP_GDS_ATOMIC1_PREOP_HI
+#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
+#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL
+//CP_ME_GDS_ATOMIC1_PREOP_HI
+#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
+#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL
+//CP_ME_MC_WADDR_LO
+#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2
+#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xFFFFFFFCL
+//CP_ME_MC_WADDR_HI
+#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0
+#define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT 0x16
+#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0x0000FFFFL
+#define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK 0x00400000L
+//CP_ME_MC_WDATA_LO
+#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0
+#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xFFFFFFFFL
+//CP_ME_MC_WDATA_HI
+#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0
+#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xFFFFFFFFL
+//CP_ME_MC_RADDR_LO
+#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2
+#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xFFFFFFFCL
+//CP_ME_MC_RADDR_HI
+#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0
+#define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16
+#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0x0000FFFFL
+#define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK 0x00400000L
+//CP_SEM_WAIT_TIMER
+#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0
+#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xFFFFFFFFL
+//CP_SIG_SEM_ADDR_LO
+#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
+#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
+#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L
+#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L
+//CP_SIG_SEM_ADDR_HI
+#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
+#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
+#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
+#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
+#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
+#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL
+#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L
+#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L
+#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L
+#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L
+//CP_WAIT_REG_MEM_TIMEOUT
+#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0
+#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xFFFFFFFFL
+//CP_WAIT_SEM_ADDR_LO
+#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
+#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
+#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L
+#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L
+//CP_WAIT_SEM_ADDR_HI
+#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
+#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
+#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
+#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
+#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
+#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL
+#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L
+#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L
+#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L
+#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L
+//CP_DMA_PFP_CONTROL
+#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR__SHIFT 0xa
+#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
+#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14
+#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
+#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d
+#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L
+#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x00002000L
+#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x00300000L
+#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x02000000L
+#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000L
+//CP_DMA_ME_CONTROL
+#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR__SHIFT 0xa
+#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
+#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14
+#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
+#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d
+#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L
+#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x00002000L
+#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x00300000L
+#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x02000000L
+#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000L
+//CP_COHER_BASE_HI
+#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0
+#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL
+//CP_COHER_START_DELAY
+#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0
+#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x0000003FL
+//CP_COHER_CNTL
+#define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT 0x3
+#define CP_COHER_CNTL__TC_WC_ACTION_ENA__SHIFT 0x4
+#define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA__SHIFT 0x5
+#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf
+#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12
+#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16
+#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17
+#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19
+#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a
+#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b
+#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c
+#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d
+#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT 0x1e
+#define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK 0x00000008L
+#define CP_COHER_CNTL__TC_WC_ACTION_ENA_MASK 0x00000010L
+#define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA_MASK 0x00000020L
+#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x00008000L
+#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x00040000L
+#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x00400000L
+#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x00800000L
+#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x02000000L
+#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x04000000L
+#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x08000000L
+#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000L
+#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000L
+#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK 0x40000000L
+//CP_COHER_SIZE
+#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0
+#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL
+//CP_COHER_BASE
+#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0
+#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL
+//CP_COHER_STATUS
+#define CP_COHER_STATUS__MEID__SHIFT 0x18
+#define CP_COHER_STATUS__STATUS__SHIFT 0x1f
+#define CP_COHER_STATUS__MEID_MASK 0x03000000L
+#define CP_COHER_STATUS__STATUS_MASK 0x80000000L
+//CP_DMA_ME_SRC_ADDR
+#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0
+#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL
+//CP_DMA_ME_SRC_ADDR_HI
+#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
+#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL
+//CP_DMA_ME_DST_ADDR
+#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0
+#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL
+//CP_DMA_ME_DST_ADDR_HI
+#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
+#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL
+//CP_DMA_ME_COMMAND
+#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0
+#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a
+#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b
+#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c
+#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d
+#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e
+#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x1f
+#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL
+#define CP_DMA_ME_COMMAND__SAS_MASK 0x04000000L
+#define CP_DMA_ME_COMMAND__DAS_MASK 0x08000000L
+#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000L
+#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000L
+#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000L
+#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x80000000L
+//CP_DMA_PFP_SRC_ADDR
+#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0
+#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL
+//CP_DMA_PFP_SRC_ADDR_HI
+#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
+#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL
+//CP_DMA_PFP_DST_ADDR
+#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0
+#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL
+//CP_DMA_PFP_DST_ADDR_HI
+#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
+#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL
+//CP_DMA_PFP_COMMAND
+#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0
+#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a
+#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b
+#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c
+#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d
+#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e
+#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x1f
+#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL
+#define CP_DMA_PFP_COMMAND__SAS_MASK 0x04000000L
+#define CP_DMA_PFP_COMMAND__DAS_MASK 0x08000000L
+#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000L
+#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000L
+#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000L
+#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x80000000L
+//CP_DMA_CNTL
+#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL__SHIFT 0x0
+#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4
+#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10
+#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c
+#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d
+#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e
+#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL_MASK 0x00000001L
+#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x00000030L
+#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0x000F0000L
+#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000L
+#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000L
+#define CP_DMA_CNTL__PIO_COUNT_MASK 0xC0000000L
+//CP_DMA_READ_TAGS
+#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0
+#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c
+#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x03FFFFFFL
+#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000L
+//CP_COHER_SIZE_HI
+#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0
+#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL
+//CP_PFP_IB_CONTROL
+#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0
+#define CP_PFP_IB_CONTROL__IB_EN_MASK 0x000000FFL
+//CP_PFP_LOAD_CONTROL
+#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0
+#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1
+#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10
+#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18
+#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x00000001L
+#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x00000002L
+#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x00010000L
+#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x01000000L
+//CP_SCRATCH_INDEX
+#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
+#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000000FFL
+//CP_SCRATCH_DATA
+#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
+#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL
+//CP_RB_OFFSET
+#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0
+#define CP_RB_OFFSET__RB_OFFSET_MASK 0x000FFFFFL
+//CP_IB2_OFFSET
+#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
+#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL
+//CP_IB2_PREAMBLE_BEGIN
+#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0
+#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0x000FFFFFL
+//CP_IB2_PREAMBLE_END
+#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0
+#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0x000FFFFFL
+//CP_CE_IB1_OFFSET
+#define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
+#define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0x000FFFFFL
+//CP_CE_IB2_OFFSET
+#define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
+#define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL
+//CP_CE_COUNTER
+#define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0
+#define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL
+//CP_CE_RB_OFFSET
+#define CP_CE_RB_OFFSET__RB_OFFSET__SHIFT 0x0
+#define CP_CE_RB_OFFSET__RB_OFFSET_MASK 0x000FFFFFL
+//CP_CE_INIT_CMD_BUFSZ
+#define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ__SHIFT 0x0
+#define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ_MASK 0x00000FFFL
+//CP_CE_IB1_CMD_BUFSZ
+#define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0
+#define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL
+//CP_CE_IB2_CMD_BUFSZ
+#define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0
+#define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL
+//CP_IB2_CMD_BUFSZ
+#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0
+#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL
+//CP_ST_CMD_BUFSZ
+#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ__SHIFT 0x0
+#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ_MASK 0x000FFFFFL
+//CP_CE_INIT_BASE_LO
+#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5
+#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xFFFFFFE0L
+//CP_CE_INIT_BASE_HI
+#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0
+#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0x0000FFFFL
+//CP_CE_INIT_BUFSZ
+#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0
+#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0x00000FFFL
+//CP_CE_IB1_BASE_LO
+#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
+#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL
+//CP_CE_IB1_BASE_HI
+#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
+#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL
+//CP_CE_IB1_BUFSZ
+#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
+#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL
+//CP_CE_IB2_BASE_LO
+#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
+#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL
+//CP_CE_IB2_BASE_HI
+#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
+#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL
+//CP_CE_IB2_BUFSZ
+#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
+#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL
+//CP_IB2_BASE_LO
+#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
+#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL
+//CP_IB2_BASE_HI
+#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
+#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL
+//CP_IB2_BUFSZ
+#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
+#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL
+//CP_ST_BASE_LO
+#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2
+#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xFFFFFFFCL
+//CP_ST_BASE_HI
+#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0
+#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0x0000FFFFL
+//CP_ST_BUFSZ
+#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0
+#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000FFFFFL
+//CP_EOP_DONE_EVENT_CNTL
+#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0
+#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc
+#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY__SHIFT 0x19
+#define CP_EOP_DONE_EVENT_CNTL__EXECUTE__SHIFT 0x1c
+#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x0000007FL
+#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x0003F000L
+#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY_MASK 0x02000000L
+#define CP_EOP_DONE_EVENT_CNTL__EXECUTE_MASK 0x10000000L
+//CP_EOP_DONE_DATA_CNTL
+#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10
+#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18
+#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d
+#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x00030000L
+#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x07000000L
+#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xE0000000L
+//CP_EOP_DONE_CNTX_ID
+#define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x0
+#define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL
+//CP_PFP_COMPLETION_STATUS
+#define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT 0x0
+#define CP_PFP_COMPLETION_STATUS__STATUS_MASK 0x00000003L
+//CP_CE_COMPLETION_STATUS
+#define CP_CE_COMPLETION_STATUS__STATUS__SHIFT 0x0
+#define CP_CE_COMPLETION_STATUS__STATUS_MASK 0x00000003L
+//CP_PRED_NOT_VISIBLE
+#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT 0x0
+#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK 0x00000001L
+//CP_PFP_METADATA_BASE_ADDR
+#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0
+#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
+//CP_PFP_METADATA_BASE_ADDR_HI
+#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
+//CP_CE_METADATA_BASE_ADDR
+#define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0
+#define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
+//CP_CE_METADATA_BASE_ADDR_HI
+#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
+//CP_DRAW_INDX_INDR_ADDR
+#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT 0x0
+#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
+//CP_DRAW_INDX_INDR_ADDR_HI
+#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
+//CP_DISPATCH_INDR_ADDR
+#define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT 0x0
+#define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
+//CP_DISPATCH_INDR_ADDR_HI
+#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
+//CP_INDEX_BASE_ADDR
+#define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT 0x0
+#define CP_INDEX_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
+//CP_INDEX_BASE_ADDR_HI
+#define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
+//CP_INDEX_TYPE
+#define CP_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
+#define CP_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L
+//CP_GDS_BKUP_ADDR
+#define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT 0x0
+#define CP_GDS_BKUP_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
+//CP_GDS_BKUP_ADDR_HI
+#define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
+//CP_SAMPLE_STATUS
+#define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT 0x0
+#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT 0x1
+#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT 0x2
+#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT 0x3
+#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT 0x4
+#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT 0x5
+#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT 0x6
+#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT 0x7
+#define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK 0x00000001L
+#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK 0x00000002L
+#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK 0x00000004L
+#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK 0x00000008L
+#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK 0x00000010L
+#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK 0x00000020L
+#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK 0x00000040L
+#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK 0x00000080L
+//CP_ME_COHER_CNTL
+#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0
+#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1
+#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6
+#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7
+#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8
+#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9
+#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa
+#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb
+#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc
+#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd
+#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe
+#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13
+#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15
+#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x00000001L
+#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x00000002L
+#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x00000040L
+#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x00000080L
+#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x00000100L
+#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x00000200L
+#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x00000400L
+#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x00000800L
+#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x00001000L
+#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x00002000L
+#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x00004000L
+#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x00080000L
+#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x00200000L
+//CP_ME_COHER_SIZE
+#define CP_ME_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0
+#define CP_ME_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL
+//CP_ME_COHER_SIZE_HI
+#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0
+#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL
+//CP_ME_COHER_BASE
+#define CP_ME_COHER_BASE__COHER_BASE_256B__SHIFT 0x0
+#define CP_ME_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL
+//CP_ME_COHER_BASE_HI
+#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0
+#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL
+//CP_ME_COHER_STATUS
+#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0
+#define CP_ME_COHER_STATUS__STATUS__SHIFT 0x1f
+#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0x000000FFL
+#define CP_ME_COHER_STATUS__STATUS_MASK 0x80000000L
+//RLC_GPM_PERF_COUNT_0
+#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0
+#define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4
+#define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT 0x8
+#define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT 0xc
+#define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10
+#define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12
+#define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14
+#define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15
+#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0x0000000FL
+#define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0x000000F0L
+#define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK 0x00000F00L
+#define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK 0x0000F000L
+#define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x00030000L
+#define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0x000C0000L
+#define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x00100000L
+#define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xFFE00000L
+//RLC_GPM_PERF_COUNT_1
+#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0
+#define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4
+#define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT 0x8
+#define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT 0xc
+#define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10
+#define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12
+#define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14
+#define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15
+#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0x0000000FL
+#define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0x000000F0L
+#define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK 0x00000F00L
+#define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK 0x0000F000L
+#define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x00030000L
+#define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0x000C0000L
+#define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x00100000L
+#define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xFFE00000L
+//GRBM_GFX_INDEX
+#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0
+#define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x8
+#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10
+#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d
+#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e
+#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f
+#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0x000000FFL
+#define GRBM_GFX_INDEX__SH_INDEX_MASK 0x0000FF00L
+#define GRBM_GFX_INDEX__SE_INDEX_MASK 0x00FF0000L
+#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000L
+#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L
+#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000L
+//VGT_GSVS_RING_SIZE
+#define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x0
+#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xFFFFFFFFL
+//VGT_PRIMITIVE_TYPE
+#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0
+#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL
+//VGT_INDEX_TYPE
+#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
+#define VGT_INDEX_TYPE__PRIMGEN_EN__SHIFT 0x8
+#define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L
+#define VGT_INDEX_TYPE__PRIMGEN_EN_MASK 0x00000100L
+//VGT_STRMOUT_BUFFER_FILLED_SIZE_0
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_BUFFER_FILLED_SIZE_1
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_BUFFER_FILLED_SIZE_2
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_BUFFER_FILLED_SIZE_3
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xFFFFFFFFL
+//VGT_MAX_VTX_INDX
+#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0
+#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xFFFFFFFFL
+//VGT_MIN_VTX_INDX
+#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0
+#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xFFFFFFFFL
+//VGT_INDX_OFFSET
+#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0
+#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xFFFFFFFFL
+//VGT_MULTI_PRIM_IB_RESET_EN
+#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0
+#define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT 0x1
+#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x00000001L
+#define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK 0x00000002L
+//VGT_NUM_INDICES
+#define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0
+#define VGT_NUM_INDICES__NUM_INDICES_MASK 0xFFFFFFFFL
+//VGT_NUM_INSTANCES
+#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0
+#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL
+//VGT_TF_RING_SIZE
+#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0
+#define VGT_TF_RING_SIZE__SIZE_MASK 0x0000FFFFL
+//VGT_HS_OFFCHIP_PARAM
+#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0
+#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x9
+#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x000001FFL
+#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x00000600L
+//VGT_TF_MEMORY_BASE
+#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0
+#define VGT_TF_MEMORY_BASE__BASE_MASK 0xFFFFFFFFL
+//VGT_TF_MEMORY_BASE_HI
+#define VGT_TF_MEMORY_BASE_HI__BASE_HI__SHIFT 0x0
+#define VGT_TF_MEMORY_BASE_HI__BASE_HI_MASK 0x000000FFL
+//WD_POS_BUF_BASE
+#define WD_POS_BUF_BASE__BASE__SHIFT 0x0
+#define WD_POS_BUF_BASE__BASE_MASK 0xFFFFFFFFL
+//WD_POS_BUF_BASE_HI
+#define WD_POS_BUF_BASE_HI__BASE_HI__SHIFT 0x0
+#define WD_POS_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL
+//WD_CNTL_SB_BUF_BASE
+#define WD_CNTL_SB_BUF_BASE__BASE__SHIFT 0x0
+#define WD_CNTL_SB_BUF_BASE__BASE_MASK 0xFFFFFFFFL
+//WD_CNTL_SB_BUF_BASE_HI
+#define WD_CNTL_SB_BUF_BASE_HI__BASE_HI__SHIFT 0x0
+#define WD_CNTL_SB_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL
+//WD_INDEX_BUF_BASE
+#define WD_INDEX_BUF_BASE__BASE__SHIFT 0x0
+#define WD_INDEX_BUF_BASE__BASE_MASK 0xFFFFFFFFL
+//WD_INDEX_BUF_BASE_HI
+#define WD_INDEX_BUF_BASE_HI__BASE_HI__SHIFT 0x0
+#define WD_INDEX_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL
+//IA_MULTI_VGT_PARAM
+#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x0
+#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x10
+#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x11
+#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x12
+#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x13
+#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x14
+#define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC__SHIFT 0x15
+#define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV__SHIFT 0x16
+#define IA_MULTI_VGT_PARAM__HW_USE_ONLY__SHIFT 0x17
+#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0x0000FFFFL
+#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x00010000L
+#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x00020000L
+#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x00040000L
+#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x00080000L
+#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x00100000L
+#define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC_MASK 0x00200000L
+#define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV_MASK 0x00400000L
+#define IA_MULTI_VGT_PARAM__HW_USE_ONLY_MASK 0x00800000L
+//VGT_INSTANCE_BASE_ID
+#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT 0x0
+#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK 0xFFFFFFFFL
+//PA_SU_LINE_STIPPLE_VALUE
+#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0
+#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0x00FFFFFFL
+//PA_SC_LINE_STIPPLE_STATE
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000FL
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000FF00L
+//PA_SC_SCREEN_EXTENT_MIN_0
+#define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0
+#define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10
+#define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0x0000FFFFL
+#define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xFFFF0000L
+//PA_SC_SCREEN_EXTENT_MAX_0
+#define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0
+#define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10
+#define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0x0000FFFFL
+#define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xFFFF0000L
+//PA_SC_SCREEN_EXTENT_MIN_1
+#define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0
+#define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10
+#define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0x0000FFFFL
+#define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xFFFF0000L
+//PA_SC_SCREEN_EXTENT_MAX_1
+#define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0
+#define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10
+#define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0x0000FFFFL
+#define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xFFFF0000L
+//PA_SC_P3D_TRAP_SCREEN_HV_EN
+#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
+#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L
+#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L
+//PA_SC_P3D_TRAP_SCREEN_H
+#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL
+//PA_SC_P3D_TRAP_SCREEN_V
+#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL
+//PA_SC_P3D_TRAP_SCREEN_OCCURRENCE
+#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL
+//PA_SC_P3D_TRAP_SCREEN_COUNT
+#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL
+//PA_SC_HP3D_TRAP_SCREEN_HV_EN
+#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
+#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L
+#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L
+//PA_SC_HP3D_TRAP_SCREEN_H
+#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL
+//PA_SC_HP3D_TRAP_SCREEN_V
+#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL
+//PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE
+#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL
+//PA_SC_HP3D_TRAP_SCREEN_COUNT
+#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL
+//PA_SC_TRAP_SCREEN_HV_EN
+#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
+#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L
+#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L
+//PA_SC_TRAP_SCREEN_H
+#define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL
+//PA_SC_TRAP_SCREEN_V
+#define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL
+//PA_SC_TRAP_SCREEN_OCCURRENCE
+#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL
+//PA_SC_TRAP_SCREEN_COUNT
+#define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL
+//PA_STATE_STEREO_X
+#define PA_STATE_STEREO_X__STEREO_X_OFFSET__SHIFT 0x0
+#define PA_STATE_STEREO_X__STEREO_X_OFFSET_MASK 0xFFFFFFFFL
+//SQ_THREAD_TRACE_BASE
+#define SQ_THREAD_TRACE_BASE__ADDR__SHIFT 0x0
+#define SQ_THREAD_TRACE_BASE__ADDR_MASK 0xFFFFFFFFL
+//SQ_THREAD_TRACE_SIZE
+#define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT 0x0
+#define SQ_THREAD_TRACE_SIZE__SIZE_MASK 0x003FFFFFL
+//SQ_THREAD_TRACE_MASK
+#define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT 0x0
+#define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT 0x5
+#define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT 0x7
+#define SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT 0x8
+#define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT 0xc
+#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT 0xe
+#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT 0xf
+#define SQ_THREAD_TRACE_MASK__CU_SEL_MASK 0x0000001FL
+#define SQ_THREAD_TRACE_MASK__SH_SEL_MASK 0x00000020L
+#define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK 0x00000080L
+#define SQ_THREAD_TRACE_MASK__SIMD_EN_MASK 0x00000F00L
+#define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK 0x00003000L
+#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK 0x00004000L
+#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK 0x00008000L
+//SQ_THREAD_TRACE_TOKEN_MASK
+#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT 0x0
+#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT 0x10
+#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT 0x18
+#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK 0x0000FFFFL
+#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK 0x00FF0000L
+#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK 0x01000000L
+//SQ_THREAD_TRACE_PERF_MASK
+#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT 0x0
+#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT 0x10
+#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK 0x0000FFFFL
+#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK 0xFFFF0000L
+//SQ_THREAD_TRACE_CTRL
+#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT 0x1f
+#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK 0x80000000L
+//SQ_THREAD_TRACE_MODE
+#define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT 0x0
+#define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT 0x3
+#define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT 0x6
+#define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT 0x9
+#define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT 0xc
+#define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT 0xf
+#define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT 0x12
+#define SQ_THREAD_TRACE_MODE__MODE__SHIFT 0x15
+#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT 0x17
+#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT 0x19
+#define SQ_THREAD_TRACE_MODE__TC_PERF_EN__SHIFT 0x1a
+#define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT 0x1b
+#define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x1d
+#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT 0x1e
+#define SQ_THREAD_TRACE_MODE__WRAP__SHIFT 0x1f
+#define SQ_THREAD_TRACE_MODE__MASK_PS_MASK 0x00000007L
+#define SQ_THREAD_TRACE_MODE__MASK_VS_MASK 0x00000038L
+#define SQ_THREAD_TRACE_MODE__MASK_GS_MASK 0x000001C0L
+#define SQ_THREAD_TRACE_MODE__MASK_ES_MASK 0x00000E00L
+#define SQ_THREAD_TRACE_MODE__MASK_HS_MASK 0x00007000L
+#define SQ_THREAD_TRACE_MODE__MASK_LS_MASK 0x00038000L
+#define SQ_THREAD_TRACE_MODE__MASK_CS_MASK 0x001C0000L
+#define SQ_THREAD_TRACE_MODE__MODE_MASK 0x00600000L
+#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK 0x01800000L
+#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK 0x02000000L
+#define SQ_THREAD_TRACE_MODE__TC_PERF_EN_MASK 0x04000000L
+#define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK 0x18000000L
+#define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK 0x20000000L
+#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK 0x40000000L
+#define SQ_THREAD_TRACE_MODE__WRAP_MASK 0x80000000L
+//SQ_THREAD_TRACE_BASE2
+#define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT 0x0
+#define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK 0x0000000FL
+//SQ_THREAD_TRACE_TOKEN_MASK2
+#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT 0x0
+#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK 0xFFFFFFFFL
+//SQ_THREAD_TRACE_WPTR
+#define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT 0x0
+#define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT 0x1e
+#define SQ_THREAD_TRACE_WPTR__WPTR_MASK 0x3FFFFFFFL
+#define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK 0xC0000000L
+//SQ_THREAD_TRACE_STATUS
+#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0
+#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0x10
+#define SQ_THREAD_TRACE_STATUS__UTC_ERROR__SHIFT 0x1c
+#define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x1d
+#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x1e
+#define SQ_THREAD_TRACE_STATUS__FULL__SHIFT 0x1f
+#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x000003FFL
+#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x03FF0000L
+#define SQ_THREAD_TRACE_STATUS__UTC_ERROR_MASK 0x10000000L
+#define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK 0x20000000L
+#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x40000000L
+#define SQ_THREAD_TRACE_STATUS__FULL_MASK 0x80000000L
+//SQ_THREAD_TRACE_HIWATER
+#define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT 0x0
+#define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK 0x00000007L
+//SQ_THREAD_TRACE_CNTR
+#define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT 0x0
+#define SQ_THREAD_TRACE_CNTR__CNTR_MASK 0xFFFFFFFFL
+//SQ_THREAD_TRACE_USERDATA_0
+#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0
+#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xFFFFFFFFL
+//SQ_THREAD_TRACE_USERDATA_1
+#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0
+#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xFFFFFFFFL
+//SQ_THREAD_TRACE_USERDATA_2
+#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0
+#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xFFFFFFFFL
+//SQ_THREAD_TRACE_USERDATA_3
+#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0
+#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xFFFFFFFFL
+//SQC_CACHES
+#define SQC_CACHES__TARGET_INST__SHIFT 0x0
+#define SQC_CACHES__TARGET_DATA__SHIFT 0x1
+#define SQC_CACHES__INVALIDATE__SHIFT 0x2
+#define SQC_CACHES__WRITEBACK__SHIFT 0x3
+#define SQC_CACHES__VOL__SHIFT 0x4
+#define SQC_CACHES__COMPLETE__SHIFT 0x10
+#define SQC_CACHES__TARGET_INST_MASK 0x00000001L
+#define SQC_CACHES__TARGET_DATA_MASK 0x00000002L
+#define SQC_CACHES__INVALIDATE_MASK 0x00000004L
+#define SQC_CACHES__WRITEBACK_MASK 0x00000008L
+#define SQC_CACHES__VOL_MASK 0x00000010L
+#define SQC_CACHES__COMPLETE_MASK 0x00010000L
+//SQC_WRITEBACK
+#define SQC_WRITEBACK__DWB__SHIFT 0x0
+#define SQC_WRITEBACK__DIRTY__SHIFT 0x1
+#define SQC_WRITEBACK__DWB_MASK 0x00000001L
+#define SQC_WRITEBACK__DIRTY_MASK 0x00000002L
+//DB_OCCLUSION_COUNT0_LOW
+#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0
+#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
+//DB_OCCLUSION_COUNT0_HI
+#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0
+#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7FFFFFFFL
+//DB_OCCLUSION_COUNT1_LOW
+#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0
+#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
+//DB_OCCLUSION_COUNT1_HI
+#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0
+#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7FFFFFFFL
+//DB_OCCLUSION_COUNT2_LOW
+#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0
+#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
+//DB_OCCLUSION_COUNT2_HI
+#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0
+#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7FFFFFFFL
+//DB_OCCLUSION_COUNT3_LOW
+#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0
+#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
+//DB_OCCLUSION_COUNT3_HI
+#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0
+#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7FFFFFFFL
+//DB_ZPASS_COUNT_LOW
+#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0
+#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
+//DB_ZPASS_COUNT_HI
+#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0
+#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7FFFFFFFL
+//GDS_RD_ADDR
+#define GDS_RD_ADDR__READ_ADDR__SHIFT 0x0
+#define GDS_RD_ADDR__READ_ADDR_MASK 0xFFFFFFFFL
+//GDS_RD_DATA
+#define GDS_RD_DATA__READ_DATA__SHIFT 0x0
+#define GDS_RD_DATA__READ_DATA_MASK 0xFFFFFFFFL
+//GDS_RD_BURST_ADDR
+#define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x0
+#define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xFFFFFFFFL
+//GDS_RD_BURST_COUNT
+#define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x0
+#define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xFFFFFFFFL
+//GDS_RD_BURST_DATA
+#define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x0
+#define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xFFFFFFFFL
+//GDS_WR_ADDR
+#define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x0
+#define GDS_WR_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL
+//GDS_WR_DATA
+#define GDS_WR_DATA__WRITE_DATA__SHIFT 0x0
+#define GDS_WR_DATA__WRITE_DATA_MASK 0xFFFFFFFFL
+//GDS_WR_BURST_ADDR
+#define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x0
+#define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL
+//GDS_WR_BURST_DATA
+#define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x0
+#define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xFFFFFFFFL
+//GDS_WRITE_COMPLETE
+#define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x0
+#define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xFFFFFFFFL
+//GDS_ATOM_CNTL
+#define GDS_ATOM_CNTL__AINC__SHIFT 0x0
+#define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x6
+#define GDS_ATOM_CNTL__DMODE__SHIFT 0x8
+#define GDS_ATOM_CNTL__UNUSED2__SHIFT 0xa
+#define GDS_ATOM_CNTL__AINC_MASK 0x0000003FL
+#define GDS_ATOM_CNTL__UNUSED1_MASK 0x000000C0L
+#define GDS_ATOM_CNTL__DMODE_MASK 0x00000300L
+#define GDS_ATOM_CNTL__UNUSED2_MASK 0xFFFFFC00L
+//GDS_ATOM_COMPLETE
+#define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x0
+#define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x1
+#define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x00000001L
+#define GDS_ATOM_COMPLETE__UNUSED_MASK 0xFFFFFFFEL
+//GDS_ATOM_BASE
+#define GDS_ATOM_BASE__BASE__SHIFT 0x0
+#define GDS_ATOM_BASE__UNUSED__SHIFT 0x10
+#define GDS_ATOM_BASE__BASE_MASK 0x0000FFFFL
+#define GDS_ATOM_BASE__UNUSED_MASK 0xFFFF0000L
+//GDS_ATOM_SIZE
+#define GDS_ATOM_SIZE__SIZE__SHIFT 0x0
+#define GDS_ATOM_SIZE__UNUSED__SHIFT 0x10
+#define GDS_ATOM_SIZE__SIZE_MASK 0x0000FFFFL
+#define GDS_ATOM_SIZE__UNUSED_MASK 0xFFFF0000L
+//GDS_ATOM_OFFSET0
+#define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x0
+#define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x8
+#define GDS_ATOM_OFFSET0__OFFSET0_MASK 0x000000FFL
+#define GDS_ATOM_OFFSET0__UNUSED_MASK 0xFFFFFF00L
+//GDS_ATOM_OFFSET1
+#define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x0
+#define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x8
+#define GDS_ATOM_OFFSET1__OFFSET1_MASK 0x000000FFL
+#define GDS_ATOM_OFFSET1__UNUSED_MASK 0xFFFFFF00L
+//GDS_ATOM_DST
+#define GDS_ATOM_DST__DST__SHIFT 0x0
+#define GDS_ATOM_DST__DST_MASK 0xFFFFFFFFL
+//GDS_ATOM_OP
+#define GDS_ATOM_OP__OP__SHIFT 0x0
+#define GDS_ATOM_OP__UNUSED__SHIFT 0x8
+#define GDS_ATOM_OP__OP_MASK 0x000000FFL
+#define GDS_ATOM_OP__UNUSED_MASK 0xFFFFFF00L
+//GDS_ATOM_SRC0
+#define GDS_ATOM_SRC0__DATA__SHIFT 0x0
+#define GDS_ATOM_SRC0__DATA_MASK 0xFFFFFFFFL
+//GDS_ATOM_SRC0_U
+#define GDS_ATOM_SRC0_U__DATA__SHIFT 0x0
+#define GDS_ATOM_SRC0_U__DATA_MASK 0xFFFFFFFFL
+//GDS_ATOM_SRC1
+#define GDS_ATOM_SRC1__DATA__SHIFT 0x0
+#define GDS_ATOM_SRC1__DATA_MASK 0xFFFFFFFFL
+//GDS_ATOM_SRC1_U
+#define GDS_ATOM_SRC1_U__DATA__SHIFT 0x0
+#define GDS_ATOM_SRC1_U__DATA_MASK 0xFFFFFFFFL
+//GDS_ATOM_READ0
+#define GDS_ATOM_READ0__DATA__SHIFT 0x0
+#define GDS_ATOM_READ0__DATA_MASK 0xFFFFFFFFL
+//GDS_ATOM_READ0_U
+#define GDS_ATOM_READ0_U__DATA__SHIFT 0x0
+#define GDS_ATOM_READ0_U__DATA_MASK 0xFFFFFFFFL
+//GDS_ATOM_READ1
+#define GDS_ATOM_READ1__DATA__SHIFT 0x0
+#define GDS_ATOM_READ1__DATA_MASK 0xFFFFFFFFL
+//GDS_ATOM_READ1_U
+#define GDS_ATOM_READ1_U__DATA__SHIFT 0x0
+#define GDS_ATOM_READ1_U__DATA_MASK 0xFFFFFFFFL
+//GDS_GWS_RESOURCE_CNTL
+#define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x0
+#define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x6
+#define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x0000003FL
+#define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xFFFFFFC0L
+//GDS_GWS_RESOURCE
+#define GDS_GWS_RESOURCE__FLAG__SHIFT 0x0
+#define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x1
+#define GDS_GWS_RESOURCE__TYPE__SHIFT 0xe
+#define GDS_GWS_RESOURCE__DED__SHIFT 0xf
+#define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0x10
+#define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x11
+#define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x1d
+#define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x1e
+#define GDS_GWS_RESOURCE__HALTED__SHIFT 0x1f
+#define GDS_GWS_RESOURCE__FLAG_MASK 0x00000001L
+#define GDS_GWS_RESOURCE__COUNTER_MASK 0x00003FFEL
+#define GDS_GWS_RESOURCE__TYPE_MASK 0x00004000L
+#define GDS_GWS_RESOURCE__DED_MASK 0x00008000L
+#define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x00010000L
+#define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x1FFE0000L
+#define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x20000000L
+#define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x40000000L
+#define GDS_GWS_RESOURCE__HALTED_MASK 0x80000000L
+//GDS_GWS_RESOURCE_CNT
+#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x0
+#define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x10
+#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0x0000FFFFL
+#define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_CNTL
+#define GDS_OA_CNTL__INDEX__SHIFT 0x0
+#define GDS_OA_CNTL__UNUSED__SHIFT 0x4
+#define GDS_OA_CNTL__INDEX_MASK 0x0000000FL
+#define GDS_OA_CNTL__UNUSED_MASK 0xFFFFFFF0L
+//GDS_OA_COUNTER
+#define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT 0x0
+#define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK 0xFFFFFFFFL
+//GDS_OA_ADDRESS
+#define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT 0x0
+#define GDS_OA_ADDRESS__CRAWLER__SHIFT 0x10
+#define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x14
+#define GDS_OA_ADDRESS__UNUSED__SHIFT 0x16
+#define GDS_OA_ADDRESS__NO_ALLOC__SHIFT 0x1e
+#define GDS_OA_ADDRESS__ENABLE__SHIFT 0x1f
+#define GDS_OA_ADDRESS__DS_ADDRESS_MASK 0x0000FFFFL
+#define GDS_OA_ADDRESS__CRAWLER_MASK 0x000F0000L
+#define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK 0x00300000L
+#define GDS_OA_ADDRESS__UNUSED_MASK 0x3FC00000L
+#define GDS_OA_ADDRESS__NO_ALLOC_MASK 0x40000000L
+#define GDS_OA_ADDRESS__ENABLE_MASK 0x80000000L
+//GDS_OA_INCDEC
+#define GDS_OA_INCDEC__VALUE__SHIFT 0x0
+#define GDS_OA_INCDEC__INCDEC__SHIFT 0x1f
+#define GDS_OA_INCDEC__VALUE_MASK 0x7FFFFFFFL
+#define GDS_OA_INCDEC__INCDEC_MASK 0x80000000L
+//GDS_OA_RING_SIZE
+#define GDS_OA_RING_SIZE__RING_SIZE__SHIFT 0x0
+#define GDS_OA_RING_SIZE__RING_SIZE_MASK 0xFFFFFFFFL
+//SPI_CONFIG_CNTL
+#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0
+#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15
+#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18
+#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19
+#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x1a
+#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x1b
+#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA__SHIFT 0x1c
+#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA__SHIFT 0x1d
+#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL__SHIFT 0x1e
+#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x001FFFFFL
+#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0x00E00000L
+#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x01000000L
+#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x02000000L
+#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x04000000L
+#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x08000000L
+#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA_MASK 0x10000000L
+#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA_MASK 0x20000000L
+#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL_MASK 0xC0000000L
+//SPI_CONFIG_CNTL_1
+#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0
+#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4
+#define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE__SHIFT 0x5
+#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x6
+#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7
+#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x8
+#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x9
+#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa
+#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE__SHIFT 0xe
+#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE__SHIFT 0xf
+#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x10
+#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0x0000000FL
+#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x00000010L
+#define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE_MASK 0x00000020L
+#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x00000040L
+#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x00000080L
+#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x00000100L
+#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x00000200L
+#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x00003C00L
+#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE_MASK 0x00004000L
+#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE_MASK 0x00008000L
+#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xFFFF0000L
+//SPI_CONFIG_CNTL_2
+#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT 0x0
+#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT 0x4
+#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK 0x0000000FL
+#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK 0x000000F0L
+//SPI_WAVE_LIMIT_CNTL
+#define SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN__SHIFT 0x0
+#define SPI_WAVE_LIMIT_CNTL__VS_WAVE_GRAN__SHIFT 0x2
+#define SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN__SHIFT 0x4
+#define SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN__SHIFT 0x6
+#define SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN_MASK 0x00000003L
+#define SPI_WAVE_LIMIT_CNTL__VS_WAVE_GRAN_MASK 0x0000000CL
+#define SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN_MASK 0x00000030L
+#define SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN_MASK 0x000000C0L
+
+
+// addressBlock: gc_grbmdec
+//GRBM_CNTL
+#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0
+#define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f
+#define GRBM_CNTL__READ_TIMEOUT_MASK 0x000000FFL
+#define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000L
+//GRBM_SKEW_CNTL
+#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0
+#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6
+#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000003FL
+#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0x00000FC0L
+//GRBM_STATUS2
+#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0
+#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4
+#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5
+#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6
+#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7
+#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8
+#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9
+#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa
+#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb
+#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc
+#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd
+#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe
+#define GRBM_STATUS2__UTCL2_BUSY__SHIFT 0xf
+#define GRBM_STATUS2__EA_BUSY__SHIFT 0x10
+#define GRBM_STATUS2__RMI_BUSY__SHIFT 0x11
+#define GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT 0x12
+#define GRBM_STATUS2__CPF_RQ_PENDING__SHIFT 0x13
+#define GRBM_STATUS2__EA_LINK_BUSY__SHIFT 0x14
+#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18
+#define GRBM_STATUS2__TC_BUSY__SHIFT 0x19
+#define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT 0x1a
+#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c
+#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d
+#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e
+#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000FL
+#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x00000010L
+#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x00000020L
+#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x00000040L
+#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x00000080L
+#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x00000100L
+#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x00000200L
+#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x00000400L
+#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x00000800L
+#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x00001000L
+#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x00002000L
+#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x00004000L
+#define GRBM_STATUS2__UTCL2_BUSY_MASK 0x00008000L
+#define GRBM_STATUS2__EA_BUSY_MASK 0x00010000L
+#define GRBM_STATUS2__RMI_BUSY_MASK 0x00020000L
+#define GRBM_STATUS2__UTCL2_RQ_PENDING_MASK 0x00040000L
+#define GRBM_STATUS2__CPF_RQ_PENDING_MASK 0x00080000L
+#define GRBM_STATUS2__EA_LINK_BUSY_MASK 0x00100000L
+#define GRBM_STATUS2__RLC_BUSY_MASK 0x01000000L
+#define GRBM_STATUS2__TC_BUSY_MASK 0x02000000L
+#define GRBM_STATUS2__TCC_CC_RESIDENT_MASK 0x04000000L
+#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000L
+#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000L
+#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000L
+//GRBM_PWR_CNTL
+#define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0
+#define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2
+#define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4
+#define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6
+#define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe
+#define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf
+#define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x00000003L
+#define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0x0000000CL
+#define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x00000030L
+#define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0x000000C0L
+#define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x00004000L
+#define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x00008000L
+//GRBM_STATUS
+#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0
+#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7
+#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8
+#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9
+#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc
+#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd
+#define GRBM_STATUS__TA_BUSY__SHIFT 0xe
+#define GRBM_STATUS__GDS_BUSY__SHIFT 0xf
+#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10
+#define GRBM_STATUS__VGT_BUSY__SHIFT 0x11
+#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12
+#define GRBM_STATUS__IA_BUSY__SHIFT 0x13
+#define GRBM_STATUS__SX_BUSY__SHIFT 0x14
+#define GRBM_STATUS__WD_BUSY__SHIFT 0x15
+#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16
+#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17
+#define GRBM_STATUS__SC_BUSY__SHIFT 0x18
+#define GRBM_STATUS__PA_BUSY__SHIFT 0x19
+#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a
+#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c
+#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d
+#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e
+#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f
+#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000FL
+#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x00000080L
+#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x00000100L
+#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x00000200L
+#define GRBM_STATUS__DB_CLEAN_MASK 0x00001000L
+#define GRBM_STATUS__CB_CLEAN_MASK 0x00002000L
+#define GRBM_STATUS__TA_BUSY_MASK 0x00004000L
+#define GRBM_STATUS__GDS_BUSY_MASK 0x00008000L
+#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x00010000L
+#define GRBM_STATUS__VGT_BUSY_MASK 0x00020000L
+#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x00040000L
+#define GRBM_STATUS__IA_BUSY_MASK 0x00080000L
+#define GRBM_STATUS__SX_BUSY_MASK 0x00100000L
+#define GRBM_STATUS__WD_BUSY_MASK 0x00200000L
+#define GRBM_STATUS__SPI_BUSY_MASK 0x00400000L
+#define GRBM_STATUS__BCI_BUSY_MASK 0x00800000L
+#define GRBM_STATUS__SC_BUSY_MASK 0x01000000L
+#define GRBM_STATUS__PA_BUSY_MASK 0x02000000L
+#define GRBM_STATUS__DB_BUSY_MASK 0x04000000L
+#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000L
+#define GRBM_STATUS__CP_BUSY_MASK 0x20000000L
+#define GRBM_STATUS__CB_BUSY_MASK 0x40000000L
+#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000L
+//GRBM_STATUS_SE0
+#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1
+#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2
+#define GRBM_STATUS_SE0__TA_BUSY_SE4__SHIFT 0x3
+#define GRBM_STATUS_SE0__SX_BUSY_SE4__SHIFT 0x4
+#define GRBM_STATUS_SE0__SPI_BUSY_SE4__SHIFT 0x5
+#define GRBM_STATUS_SE0__RMI_BUSY__SHIFT 0x15
+#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16
+#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17
+#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18
+#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19
+#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a
+#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b
+#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d
+#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e
+#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f
+#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x00000002L
+#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x00000004L
+#define GRBM_STATUS_SE0__TA_BUSY_SE4_MASK 0x00000008L
+#define GRBM_STATUS_SE0__SX_BUSY_SE4_MASK 0x00000010L
+#define GRBM_STATUS_SE0__SPI_BUSY_SE4_MASK 0x00000020L
+#define GRBM_STATUS_SE0__RMI_BUSY_MASK 0x00200000L
+#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x00400000L
+#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x00800000L
+#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x01000000L
+#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x02000000L
+#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x04000000L
+#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x08000000L
+#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000L
+#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000L
+#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000L
+//GRBM_STATUS_SE1
+#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1
+#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2
+#define GRBM_STATUS_SE1__TA_BUSY_SE5__SHIFT 0x3
+#define GRBM_STATUS_SE1__SX_BUSY_SE5__SHIFT 0x4
+#define GRBM_STATUS_SE1__SPI_BUSY_SE5__SHIFT 0x5
+#define GRBM_STATUS_SE1__RMI_BUSY__SHIFT 0x15
+#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16
+#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17
+#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18
+#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19
+#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a
+#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b
+#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d
+#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e
+#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f
+#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x00000002L
+#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x00000004L
+#define GRBM_STATUS_SE1__TA_BUSY_SE5_MASK 0x00000008L
+#define GRBM_STATUS_SE1__SX_BUSY_SE5_MASK 0x00000010L
+#define GRBM_STATUS_SE1__SPI_BUSY_SE5_MASK 0x00000020L
+#define GRBM_STATUS_SE1__RMI_BUSY_MASK 0x00200000L
+#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x00400000L
+#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x00800000L
+#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x01000000L
+#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x02000000L
+#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x04000000L
+#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x08000000L
+#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000L
+#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000L
+#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000L
+//GRBM_SOFT_RESET
+#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0
+#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2
+#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10
+#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11
+#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12
+#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13
+#define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14
+#define GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT 0x16
+#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L
+#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x00000004L
+#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x00010000L
+#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x00020000L
+#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x00040000L
+#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x00080000L
+#define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x00100000L
+#define GRBM_SOFT_RESET__SOFT_RESET_EA_MASK 0x00400000L
+//GRBM_GFX_CLKEN_CNTL
+#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
+#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
+#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000FL
+#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001F00L
+//GRBM_WAIT_IDLE_CLOCKS
+#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0
+#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0x000000FFL
+//GRBM_STATUS_SE2
+#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1
+#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2
+#define GRBM_STATUS_SE2__TA_BUSY_SE6__SHIFT 0x3
+#define GRBM_STATUS_SE2__SX_BUSY_SE6__SHIFT 0x4
+#define GRBM_STATUS_SE2__SPI_BUSY_SE6__SHIFT 0x5
+#define GRBM_STATUS_SE2__RMI_BUSY__SHIFT 0x15
+#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16
+#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17
+#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18
+#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19
+#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a
+#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b
+#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d
+#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e
+#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f
+#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x00000002L
+#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x00000004L
+#define GRBM_STATUS_SE2__TA_BUSY_SE6_MASK 0x00000008L
+#define GRBM_STATUS_SE2__SX_BUSY_SE6_MASK 0x00000010L
+#define GRBM_STATUS_SE2__SPI_BUSY_SE6_MASK 0x00000020L
+#define GRBM_STATUS_SE2__RMI_BUSY_MASK 0x00200000L
+#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x00400000L
+#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x00800000L
+#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x01000000L
+#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x02000000L
+#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x04000000L
+#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x08000000L
+#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000L
+#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000L
+#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000L
+//GRBM_STATUS_SE3
+#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1
+#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2
+#define GRBM_STATUS_SE3__TA_BUSY_SE7__SHIFT 0x3
+#define GRBM_STATUS_SE3__SX_BUSY_SE7__SHIFT 0x4
+#define GRBM_STATUS_SE3__SPI_BUSY_SE7__SHIFT 0x5
+#define GRBM_STATUS_SE3__RMI_BUSY__SHIFT 0x15
+#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16
+#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17
+#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18
+#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19
+#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a
+#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b
+#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d
+#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e
+#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f
+#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x00000002L
+#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x00000004L
+#define GRBM_STATUS_SE3__TA_BUSY_SE7_MASK 0x00000008L
+#define GRBM_STATUS_SE3__SX_BUSY_SE7_MASK 0x00000010L
+#define GRBM_STATUS_SE3__SPI_BUSY_SE7_MASK 0x00000020L
+#define GRBM_STATUS_SE3__RMI_BUSY_MASK 0x00200000L
+#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x00400000L
+#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x00800000L
+#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x01000000L
+#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x02000000L
+#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x04000000L
+#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x08000000L
+#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000L
+#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000L
+#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000L
+//GRBM_READ_ERROR
+#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2
+#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14
+#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16
+#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f
+#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003FFFCL
+#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x00300000L
+#define GRBM_READ_ERROR__READ_MEID_MASK 0x00C00000L
+#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L
+//GRBM_READ_ERROR2
+#define GRBM_READ_ERROR2__READ_REQUESTER_CPF__SHIFT 0x10
+#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12
+#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f
+#define GRBM_READ_ERROR2__READ_REQUESTER_CPF_MASK 0x00010000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x00040000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x00080000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x00100000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x00200000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x00400000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x00800000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x01000000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x02000000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x04000000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x08000000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000L
+//GRBM_INT_CNTL
+#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0
+#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13
+#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x00000001L
+#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x00080000L
+//GRBM_TRAP_OP
+#define GRBM_TRAP_OP__RW__SHIFT 0x0
+#define GRBM_TRAP_OP__RW_MASK 0x00000001L
+//GRBM_TRAP_ADDR
+#define GRBM_TRAP_ADDR__DATA__SHIFT 0x0
+#define GRBM_TRAP_ADDR__DATA_MASK 0x0003FFFFL
+//GRBM_TRAP_ADDR_MSK
+#define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0
+#define GRBM_TRAP_ADDR_MSK__DATA_MASK 0x0003FFFFL
+//GRBM_TRAP_WD
+#define GRBM_TRAP_WD__DATA__SHIFT 0x0
+#define GRBM_TRAP_WD__DATA_MASK 0xFFFFFFFFL
+//GRBM_TRAP_WD_MSK
+#define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0
+#define GRBM_TRAP_WD_MSK__DATA_MASK 0xFFFFFFFFL
+//GRBM_WRITE_ERROR
+#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0
+#define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2
+#define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x5
+#define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc
+#define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd
+#define GRBM_WRITE_ERROR__TMZ__SHIFT 0x11
+#define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14
+#define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16
+#define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f
+#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x00000001L
+#define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x0000001CL
+#define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x000001E0L
+#define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x00001000L
+#define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x0001E000L
+#define GRBM_WRITE_ERROR__TMZ_MASK 0x00020000L
+#define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x00300000L
+#define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0x00C00000L
+#define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000L
+//GRBM_CHIP_REVISION
+#define GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0
+#define GRBM_CHIP_REVISION__CHIP_REVISION_MASK 0x000000FFL
+//GRBM_GFX_CNTL
+#define GRBM_GFX_CNTL__PIPEID__SHIFT 0x0
+#define GRBM_GFX_CNTL__MEID__SHIFT 0x2
+#define GRBM_GFX_CNTL__VMID__SHIFT 0x4
+#define GRBM_GFX_CNTL__QUEUEID__SHIFT 0x8
+#define GRBM_GFX_CNTL__PIPEID_MASK 0x00000003L
+#define GRBM_GFX_CNTL__MEID_MASK 0x0000000CL
+#define GRBM_GFX_CNTL__VMID_MASK 0x000000F0L
+#define GRBM_GFX_CNTL__QUEUEID_MASK 0x00000700L
+//GRBM_IH_CREDIT
+#define GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
+#define GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10
+#define GRBM_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
+#define GRBM_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L
+//GRBM_PWR_CNTL2
+#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT 0x10
+#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT 0x14
+#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK 0x00010000L
+#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK 0x00100000L
+//GRBM_UTCL2_INVAL_RANGE_START
+#define GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT 0x0
+#define GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK 0x0003FFFFL
+//GRBM_UTCL2_INVAL_RANGE_END
+#define GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT 0x0
+#define GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK 0x0003FFFFL
+//GRBM_CHICKEN_BITS
+#define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ__SHIFT 0x0
+#define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ_MASK 0x00000001L
+//GRBM_FENCE_RANGE0
+#define GRBM_FENCE_RANGE0__START__SHIFT 0x0
+#define GRBM_FENCE_RANGE0__END__SHIFT 0x10
+#define GRBM_FENCE_RANGE0__START_MASK 0x0000FFFFL
+#define GRBM_FENCE_RANGE0__END_MASK 0xFFFF0000L
+//GRBM_FENCE_RANGE1
+#define GRBM_FENCE_RANGE1__START__SHIFT 0x0
+#define GRBM_FENCE_RANGE1__END__SHIFT 0x10
+#define GRBM_FENCE_RANGE1__START_MASK 0x0000FFFFL
+#define GRBM_FENCE_RANGE1__END_MASK 0xFFFF0000L
+//GRBM_NOWHERE
+#define GRBM_NOWHERE__DATA__SHIFT 0x0
+#define GRBM_NOWHERE__DATA_MASK 0xFFFFFFFFL
+//GRBM_SCRATCH_REG0
+#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
+#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL
+//GRBM_SCRATCH_REG1
+#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
+#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL
+//GRBM_SCRATCH_REG2
+#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
+#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL
+//GRBM_SCRATCH_REG3
+#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
+#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL
+//GRBM_SCRATCH_REG4
+#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
+#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL
+//GRBM_SCRATCH_REG5
+#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
+#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL
+//GRBM_SCRATCH_REG6
+#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
+#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL
+//GRBM_SCRATCH_REG7
+#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
+#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL
+//VIOLATION_DATA_ASYNC_VF_PROG
+#define VIOLATION_DATA_ASYNC_VF_PROG__SSRCID__SHIFT 0x0
+#define VIOLATION_DATA_ASYNC_VF_PROG__VFID__SHIFT 0x4
+#define VIOLATION_DATA_ASYNC_VF_PROG__VIOLATION_ERROR__SHIFT 0x1f
+#define VIOLATION_DATA_ASYNC_VF_PROG__SSRCID_MASK 0x0000000FL
+#define VIOLATION_DATA_ASYNC_VF_PROG__VFID_MASK 0x000003F0L
+#define VIOLATION_DATA_ASYNC_VF_PROG__VIOLATION_ERROR_MASK 0x80000000L
+
+
+// addressBlock: gc_hypdec
+//CP_HYP_PFP_UCODE_ADDR
+#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL
+//CP_PFP_UCODE_ADDR
+#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL
+//CP_HYP_PFP_UCODE_DATA
+#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
+//CP_PFP_UCODE_DATA
+#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
+//CP_HYP_ME_UCODE_ADDR
+#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR_MASK 0x00001FFFL
+//CP_ME_RAM_RADDR
+#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0
+#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x00001FFFL
+//CP_ME_RAM_WADDR
+#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0
+#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x00001FFFL
+//CP_HYP_ME_UCODE_DATA
+#define CP_HYP_ME_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define CP_HYP_ME_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
+//CP_ME_RAM_DATA
+#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0
+#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xFFFFFFFFL
+//CP_CE_UCODE_ADDR
+#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL
+//CP_HYP_CE_UCODE_ADDR
+#define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL
+//CP_CE_UCODE_DATA
+#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
+//CP_HYP_CE_UCODE_DATA
+#define CP_HYP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define CP_HYP_CE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
+//CP_HYP_MEC1_UCODE_ADDR
+#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL
+//CP_MEC_ME1_UCODE_ADDR
+#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL
+//CP_HYP_MEC1_UCODE_DATA
+#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
+//CP_MEC_ME1_UCODE_DATA
+#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
+//CP_HYP_MEC2_UCODE_ADDR
+#define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL
+//CP_MEC_ME2_UCODE_ADDR
+#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL
+//CP_HYP_MEC2_UCODE_DATA
+#define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
+//CP_MEC_ME2_UCODE_DATA
+#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_UCODE_ADDR
+#define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xe
+#define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL
+#define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xFFFFC000L
+//RLC_GPM_UCODE_DATA
+#define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
+//GRBM_GFX_INDEX_SR_SELECT
+#define GRBM_GFX_INDEX_SR_SELECT__INDEX__SHIFT 0x0
+#define GRBM_GFX_INDEX_SR_SELECT__VF_PF__SHIFT 0x1f
+#define GRBM_GFX_INDEX_SR_SELECT__INDEX_MASK 0x00000007L
+#define GRBM_GFX_INDEX_SR_SELECT__VF_PF_MASK 0x80000000L
+//GRBM_GFX_INDEX_SR_DATA
+#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX__SHIFT 0x0
+#define GRBM_GFX_INDEX_SR_DATA__SH_INDEX__SHIFT 0x8
+#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX__SHIFT 0x10
+#define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES__SHIFT 0x1d
+#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e
+#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f
+#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX_MASK 0x000000FFL
+#define GRBM_GFX_INDEX_SR_DATA__SH_INDEX_MASK 0x0000FF00L
+#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX_MASK 0x00FF0000L
+#define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES_MASK 0x20000000L
+#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L
+#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES_MASK 0x80000000L
+//GRBM_GFX_CNTL_SR_SELECT
+#define GRBM_GFX_CNTL_SR_SELECT__INDEX__SHIFT 0x0
+#define GRBM_GFX_CNTL_SR_SELECT__VF_PF__SHIFT 0x1f
+#define GRBM_GFX_CNTL_SR_SELECT__INDEX_MASK 0x00000007L
+#define GRBM_GFX_CNTL_SR_SELECT__VF_PF_MASK 0x80000000L
+//GRBM_GFX_CNTL_SR_DATA
+#define GRBM_GFX_CNTL_SR_DATA__PIPEID__SHIFT 0x0
+#define GRBM_GFX_CNTL_SR_DATA__MEID__SHIFT 0x2
+#define GRBM_GFX_CNTL_SR_DATA__VMID__SHIFT 0x4
+#define GRBM_GFX_CNTL_SR_DATA__QUEUEID__SHIFT 0x8
+#define GRBM_GFX_CNTL_SR_DATA__PIPEID_MASK 0x00000003L
+#define GRBM_GFX_CNTL_SR_DATA__MEID_MASK 0x0000000CL
+#define GRBM_GFX_CNTL_SR_DATA__VMID_MASK 0x000000F0L
+#define GRBM_GFX_CNTL_SR_DATA__QUEUEID_MASK 0x00000700L
+//GRBM_CAM_INDEX
+#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0
+#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x00000007L
+//GRBM_HYP_CAM_INDEX
+#define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT 0x0
+#define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK 0x00000007L
+//GRBM_CAM_DATA
+#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0
+#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
+#define GRBM_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL
+#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L
+//GRBM_HYP_CAM_DATA
+#define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT 0x0
+#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
+#define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL
+#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L
+//RLC_GPU_IOV_VF_ENABLE
+#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT 0x0
+#define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT 0x1
+#define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x10
+#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK 0x00000001L
+#define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK 0x0000FFFEL
+#define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK 0xFFFF0000L
+//RLC_GPU_IOV_CFG_REG6
+#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT 0x0
+#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT 0x7
+#define RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT 0x8
+#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT 0xa
+#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK 0x0000007FL
+#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK 0x00000080L
+#define RLC_GPU_IOV_CFG_REG6__RESERVED_MASK 0x00000300L
+#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK 0xFFFFFC00L
+//RLC_GPU_IOV_CFG_REG8
+#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT 0x0
+#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK 0xFFFFFFFFL
+//RLC_RLCV_TIMER_INT_0
+#define RLC_RLCV_TIMER_INT_0__TIMER__SHIFT 0x0
+#define RLC_RLCV_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL
+//RLC_RLCV_TIMER_CTRL
+#define RLC_RLCV_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0
+#define RLC_RLCV_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1
+#define RLC_RLCV_TIMER_CTRL__RESERVED__SHIFT 0x2
+#define RLC_RLCV_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L
+#define RLC_RLCV_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L
+#define RLC_RLCV_TIMER_CTRL__RESERVED_MASK 0xFFFFFFFCL
+//RLC_RLCV_TIMER_STAT
+#define RLC_RLCV_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0
+#define RLC_RLCV_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1
+#define RLC_RLCV_TIMER_STAT__RESERVED__SHIFT 0x2
+#define RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT 0x8
+#define RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT 0x9
+#define RLC_RLCV_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L
+#define RLC_RLCV_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L
+#define RLC_RLCV_TIMER_STAT__RESERVED_MASK 0x000000FCL
+#define RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK 0x00000100L
+#define RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK 0x00000200L
+//RLC_GPU_IOV_VF_DOORBELL_STATUS
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS__SHIFT 0x0
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED__SHIFT 0x10
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS__SHIFT 0x1f
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_MASK 0x0000FFFFL
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED_MASK 0x7FFF0000L
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS_MASK 0x80000000L
+//RLC_GPU_IOV_VF_DOORBELL_STATUS_SET
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET__SHIFT 0x0
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED__SHIFT 0x10
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET__SHIFT 0x1f
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET_MASK 0x0000FFFFL
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED_MASK 0x7FFF0000L
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET_MASK 0x80000000L
+//RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR__SHIFT 0x0
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED__SHIFT 0x10
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR__SHIFT 0x1f
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR_MASK 0x0000FFFFL
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED_MASK 0x7FFF0000L
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR_MASK 0x80000000L
+//RLC_GPU_IOV_VF_MASK
+#define RLC_GPU_IOV_VF_MASK__VF_MASK__SHIFT 0x0
+#define RLC_GPU_IOV_VF_MASK__RESERVED__SHIFT 0x10
+#define RLC_GPU_IOV_VF_MASK__VF_MASK_MASK 0x0000FFFFL
+#define RLC_GPU_IOV_VF_MASK__RESERVED_MASK 0xFFFF0000L
+//RLC_HYP_SEMAPHORE_0
+#define RLC_HYP_SEMAPHORE_0__CLIENT_ID__SHIFT 0x0
+#define RLC_HYP_SEMAPHORE_0__RESERVED__SHIFT 0x5
+#define RLC_HYP_SEMAPHORE_0__CLIENT_ID_MASK 0x0000001FL
+#define RLC_HYP_SEMAPHORE_0__RESERVED_MASK 0xFFFFFFE0L
+//RLC_HYP_SEMAPHORE_1
+#define RLC_HYP_SEMAPHORE_1__CLIENT_ID__SHIFT 0x0
+#define RLC_HYP_SEMAPHORE_1__RESERVED__SHIFT 0x5
+#define RLC_HYP_SEMAPHORE_1__CLIENT_ID_MASK 0x0000001FL
+#define RLC_HYP_SEMAPHORE_1__RESERVED_MASK 0xFFFFFFE0L
+//RLC_CLK_CNTL
+#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL__SHIFT 0x0
+#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL__SHIFT 0x2
+#define RLC_CLK_CNTL__RLC_GPM_CLK_CNTL__SHIFT 0x4
+#define RLC_CLK_CNTL__RLC_CMN_CLK_CNTL__SHIFT 0x5
+#define RLC_CLK_CNTL__RLC_TC_CLK_CNTL__SHIFT 0x6
+#define RLC_CLK_CNTL__RLC_SPP_CLK_CNTL__SHIFT 0x7
+#define RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE__SHIFT 0x8
+#define RLC_CLK_CNTL__RLC_EDC_OVERRIDE__SHIFT 0x9
+#define RLC_CLK_CNTL__RESERVED_11_10__SHIFT 0xa
+#define RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE__SHIFT 0xc
+#define RLC_CLK_CNTL__RESERVED_1__SHIFT 0xe
+#define RLC_CLK_CNTL__RLC_UTCL2_FGCG_OVERRIDE__SHIFT 0x12
+#define RLC_CLK_CNTL__RESERVED__SHIFT 0x13
+#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL_MASK 0x00000003L
+#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK 0x0000000CL
+#define RLC_CLK_CNTL__RLC_GPM_CLK_CNTL_MASK 0x00000010L
+#define RLC_CLK_CNTL__RLC_CMN_CLK_CNTL_MASK 0x00000020L
+#define RLC_CLK_CNTL__RLC_TC_CLK_CNTL_MASK 0x00000040L
+#define RLC_CLK_CNTL__RLC_SPP_CLK_CNTL_MASK 0x00000080L
+#define RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK 0x00000100L
+#define RLC_CLK_CNTL__RLC_EDC_OVERRIDE_MASK 0x00000200L
+#define RLC_CLK_CNTL__RESERVED_11_10_MASK 0x00000C00L
+#define RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE_MASK 0x00001000L
+#define RLC_CLK_CNTL__RESERVED_1_MASK 0x0003C000L
+#define RLC_CLK_CNTL__RLC_UTCL2_FGCG_OVERRIDE_MASK 0x00040000L
+#define RLC_CLK_CNTL__RESERVED_MASK 0xFFF80000L
+//RLC_GPU_IOV_SCH_BLOCK
+#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID__SHIFT 0x0
+#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver__SHIFT 0x4
+#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size__SHIFT 0x8
+#define RLC_GPU_IOV_SCH_BLOCK__RESERVED__SHIFT 0x10
+#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID_MASK 0x0000000FL
+#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver_MASK 0x000000F0L
+#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size_MASK 0x00007F00L
+#define RLC_GPU_IOV_SCH_BLOCK__RESERVED_MASK 0x7FFF0000L
+//RLC_GPU_IOV_CFG_REG1
+#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT 0x0
+#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT 0x4
+#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT 0x5
+#define RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT 0x6
+#define RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT 0x8
+#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT 0x10
+#define RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT 0x18
+#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK 0x0000000FL
+#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK 0x00000010L
+#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L
+#define RLC_GPU_IOV_CFG_REG1__RESERVED_MASK 0x000000C0L
+#define RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK 0x0000FF00L
+#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK 0x00FF0000L
+#define RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK 0xFF000000L
+//RLC_GPU_IOV_CFG_REG2
+#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT 0x0
+#define RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT 0x4
+#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK 0x0000000FL
+#define RLC_GPU_IOV_CFG_REG2__RESERVED_MASK 0xFFFFFFF0L
+//RLC_GPU_IOV_VM_BUSY_STATUS
+#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
+#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_SCH_0
+#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS__SHIFT 0x0
+#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_ACTIVE_FCN_ID
+#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0
+#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4
+#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f
+#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0x0000000FL
+#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L
+#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L
+//RLC_GPU_IOV_SCH_3
+#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def__SHIFT 0x0
+#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_SCH_1
+#define RLC_GPU_IOV_SCH_1__DATA__SHIFT 0x0
+#define RLC_GPU_IOV_SCH_1__DATA_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_SCH_2
+#define RLC_GPU_IOV_SCH_2__DATA__SHIFT 0x0
+#define RLC_GPU_IOV_SCH_2__DATA_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_INT_STAT
+#define RLC_GPU_IOV_INT_STAT__STATUS__SHIFT 0x0
+#define RLC_GPU_IOV_INT_STAT__STATUS_MASK 0xFFFFFFFFL
+//RLC_RLCV_TIMER_INT_1
+#define RLC_RLCV_TIMER_INT_1__TIMER__SHIFT 0x0
+#define RLC_RLCV_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_UCODE_ADDR
+#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT 0xc
+#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL
+#define RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK 0xFFFFF000L
+//RLC_GPU_IOV_UCODE_DATA
+#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_SCRATCH_ADDR
+#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT 0x0
+#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED__SHIFT 0x9
+#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK 0x000001FFL
+#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED_MASK 0xFFFFFE00L
+//RLC_GPU_IOV_SCRATCH_DATA
+#define RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT 0x0
+#define RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_F32_CNTL
+#define RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT 0x0
+#define RLC_GPU_IOV_F32_CNTL__RESERVED__SHIFT 0x1
+#define RLC_GPU_IOV_F32_CNTL__ENABLE_MASK 0x00000001L
+#define RLC_GPU_IOV_F32_CNTL__RESERVED_MASK 0xFFFFFFFEL
+//RLC_GPU_IOV_F32_RESET
+#define RLC_GPU_IOV_F32_RESET__RESET__SHIFT 0x0
+#define RLC_GPU_IOV_F32_RESET__RESERVED__SHIFT 0x1
+#define RLC_GPU_IOV_F32_RESET__RESET_MASK 0x00000001L
+#define RLC_GPU_IOV_F32_RESET__RESERVED_MASK 0xFFFFFFFEL
+//RLC_GPU_IOV_SDMA0_STATUS
+#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED__SHIFT 0x0
+#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED__SHIFT 0x1
+#define RLC_GPU_IOV_SDMA0_STATUS__SAVED__SHIFT 0x8
+#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1__SHIFT 0x9
+#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT 0xc
+#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2__SHIFT 0xd
+#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED_MASK 0x00000001L
+#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_MASK 0x000000FEL
+#define RLC_GPU_IOV_SDMA0_STATUS__SAVED_MASK 0x00000100L
+#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1_MASK 0x00000E00L
+#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED_MASK 0x00001000L
+#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2_MASK 0xFFFFE000L
+//RLC_GPU_IOV_SDMA1_STATUS
+#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED__SHIFT 0x0
+#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED__SHIFT 0x1
+#define RLC_GPU_IOV_SDMA1_STATUS__SAVED__SHIFT 0x8
+#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1__SHIFT 0x9
+#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED__SHIFT 0xc
+#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2__SHIFT 0xd
+#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED_MASK 0x00000001L
+#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_MASK 0x000000FEL
+#define RLC_GPU_IOV_SDMA1_STATUS__SAVED_MASK 0x00000100L
+#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1_MASK 0x00000E00L
+#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED_MASK 0x00001000L
+#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2_MASK 0xFFFFE000L
+//RLC_GPU_IOV_VIRT_RESET_REQ
+#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0
+#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED__SHIFT 0x10
+#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT 0x1f
+#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK 0x0000FFFFL
+#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED_MASK 0x7FFF0000L
+#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK 0x80000000L
+//RLC_GPU_IOV_RLC_RESPONSE
+#define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT 0x0
+#define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_INT_DISABLE
+#define RLC_GPU_IOV_INT_DISABLE__DISABLE__SHIFT 0x0
+#define RLC_GPU_IOV_INT_DISABLE__DISABLE_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_INT_FORCE
+#define RLC_GPU_IOV_INT_FORCE__FORCE__SHIFT 0x0
+#define RLC_GPU_IOV_INT_FORCE__FORCE_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_SDMA0_BUSY_STATUS
+#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
+#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_SDMA1_BUSY_STATUS
+#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
+#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL
+//RLC_HYP_SEMAPHORE_2
+#define RLC_HYP_SEMAPHORE_2__CLIENT_ID__SHIFT 0x0
+#define RLC_HYP_SEMAPHORE_2__RESERVED__SHIFT 0x5
+#define RLC_HYP_SEMAPHORE_2__CLIENT_ID_MASK 0x0000001FL
+#define RLC_HYP_SEMAPHORE_2__RESERVED_MASK 0xFFFFFFE0L
+//RLC_HYP_SEMAPHORE_3
+#define RLC_HYP_SEMAPHORE_3__CLIENT_ID__SHIFT 0x0
+#define RLC_HYP_SEMAPHORE_3__RESERVED__SHIFT 0x5
+#define RLC_HYP_SEMAPHORE_3__CLIENT_ID_MASK 0x0000001FL
+#define RLC_HYP_SEMAPHORE_3__RESERVED_MASK 0xFFFFFFE0L
+//RLC_GPU_IOV_SDMA2_STATUS
+#define RLC_GPU_IOV_SDMA2_STATUS__PREEMPTED__SHIFT 0x0
+#define RLC_GPU_IOV_SDMA2_STATUS__RESERVED__SHIFT 0x1
+#define RLC_GPU_IOV_SDMA2_STATUS__SAVED__SHIFT 0x8
+#define RLC_GPU_IOV_SDMA2_STATUS__RESERVED1__SHIFT 0x9
+#define RLC_GPU_IOV_SDMA2_STATUS__RESTORED__SHIFT 0xc
+#define RLC_GPU_IOV_SDMA2_STATUS__RESERVED2__SHIFT 0xd
+#define RLC_GPU_IOV_SDMA2_STATUS__PREEMPTED_MASK 0x00000001L
+#define RLC_GPU_IOV_SDMA2_STATUS__RESERVED_MASK 0x000000FEL
+#define RLC_GPU_IOV_SDMA2_STATUS__SAVED_MASK 0x00000100L
+#define RLC_GPU_IOV_SDMA2_STATUS__RESERVED1_MASK 0x00000E00L
+#define RLC_GPU_IOV_SDMA2_STATUS__RESTORED_MASK 0x00001000L
+#define RLC_GPU_IOV_SDMA2_STATUS__RESERVED2_MASK 0xFFFFE000L
+//RLC_GPU_IOV_SDMA3_STATUS
+#define RLC_GPU_IOV_SDMA3_STATUS__PREEMPTED__SHIFT 0x0
+#define RLC_GPU_IOV_SDMA3_STATUS__RESERVED__SHIFT 0x1
+#define RLC_GPU_IOV_SDMA3_STATUS__SAVED__SHIFT 0x8
+#define RLC_GPU_IOV_SDMA3_STATUS__RESERVED1__SHIFT 0x9
+#define RLC_GPU_IOV_SDMA3_STATUS__RESTORED__SHIFT 0xc
+#define RLC_GPU_IOV_SDMA3_STATUS__RESERVED2__SHIFT 0xd
+#define RLC_GPU_IOV_SDMA3_STATUS__PREEMPTED_MASK 0x00000001L
+#define RLC_GPU_IOV_SDMA3_STATUS__RESERVED_MASK 0x000000FEL
+#define RLC_GPU_IOV_SDMA3_STATUS__SAVED_MASK 0x00000100L
+#define RLC_GPU_IOV_SDMA3_STATUS__RESERVED1_MASK 0x00000E00L
+#define RLC_GPU_IOV_SDMA3_STATUS__RESTORED_MASK 0x00001000L
+#define RLC_GPU_IOV_SDMA3_STATUS__RESERVED2_MASK 0xFFFFE000L
+//RLC_GPU_IOV_SDMA4_STATUS
+#define RLC_GPU_IOV_SDMA4_STATUS__PREEMPTED__SHIFT 0x0
+#define RLC_GPU_IOV_SDMA4_STATUS__RESERVED__SHIFT 0x1
+#define RLC_GPU_IOV_SDMA4_STATUS__SAVED__SHIFT 0x8
+#define RLC_GPU_IOV_SDMA4_STATUS__RESERVED1__SHIFT 0x9
+#define RLC_GPU_IOV_SDMA4_STATUS__RESTORED__SHIFT 0xc
+#define RLC_GPU_IOV_SDMA4_STATUS__RESERVED2__SHIFT 0xd
+#define RLC_GPU_IOV_SDMA4_STATUS__PREEMPTED_MASK 0x00000001L
+#define RLC_GPU_IOV_SDMA4_STATUS__RESERVED_MASK 0x000000FEL
+#define RLC_GPU_IOV_SDMA4_STATUS__SAVED_MASK 0x00000100L
+#define RLC_GPU_IOV_SDMA4_STATUS__RESERVED1_MASK 0x00000E00L
+#define RLC_GPU_IOV_SDMA4_STATUS__RESTORED_MASK 0x00001000L
+#define RLC_GPU_IOV_SDMA4_STATUS__RESERVED2_MASK 0xFFFFE000L
+//RLC_GPU_IOV_SDMA5_STATUS
+#define RLC_GPU_IOV_SDMA5_STATUS__PREEMPTED__SHIFT 0x0
+#define RLC_GPU_IOV_SDMA5_STATUS__RESERVED__SHIFT 0x1
+#define RLC_GPU_IOV_SDMA5_STATUS__SAVED__SHIFT 0x8
+#define RLC_GPU_IOV_SDMA5_STATUS__RESERVED1__SHIFT 0x9
+#define RLC_GPU_IOV_SDMA5_STATUS__RESTORED__SHIFT 0xc
+#define RLC_GPU_IOV_SDMA5_STATUS__RESERVED2__SHIFT 0xd
+#define RLC_GPU_IOV_SDMA5_STATUS__PREEMPTED_MASK 0x00000001L
+#define RLC_GPU_IOV_SDMA5_STATUS__RESERVED_MASK 0x000000FEL
+#define RLC_GPU_IOV_SDMA5_STATUS__SAVED_MASK 0x00000100L
+#define RLC_GPU_IOV_SDMA5_STATUS__RESERVED1_MASK 0x00000E00L
+#define RLC_GPU_IOV_SDMA5_STATUS__RESTORED_MASK 0x00001000L
+#define RLC_GPU_IOV_SDMA5_STATUS__RESERVED2_MASK 0xFFFFE000L
+//RLC_GPU_IOV_SDMA6_STATUS
+#define RLC_GPU_IOV_SDMA6_STATUS__PREEMPTED__SHIFT 0x0
+#define RLC_GPU_IOV_SDMA6_STATUS__RESERVED__SHIFT 0x1
+#define RLC_GPU_IOV_SDMA6_STATUS__SAVED__SHIFT 0x8
+#define RLC_GPU_IOV_SDMA6_STATUS__RESERVED1__SHIFT 0x9
+#define RLC_GPU_IOV_SDMA6_STATUS__RESTORED__SHIFT 0xc
+#define RLC_GPU_IOV_SDMA6_STATUS__RESERVED2__SHIFT 0xd
+#define RLC_GPU_IOV_SDMA6_STATUS__PREEMPTED_MASK 0x00000001L
+#define RLC_GPU_IOV_SDMA6_STATUS__RESERVED_MASK 0x000000FEL
+#define RLC_GPU_IOV_SDMA6_STATUS__SAVED_MASK 0x00000100L
+#define RLC_GPU_IOV_SDMA6_STATUS__RESERVED1_MASK 0x00000E00L
+#define RLC_GPU_IOV_SDMA6_STATUS__RESTORED_MASK 0x00001000L
+#define RLC_GPU_IOV_SDMA6_STATUS__RESERVED2_MASK 0xFFFFE000L
+//RLC_GPU_IOV_SDMA7_STATUS
+#define RLC_GPU_IOV_SDMA7_STATUS__PREEMPTED__SHIFT 0x0
+#define RLC_GPU_IOV_SDMA7_STATUS__RESERVED__SHIFT 0x1
+#define RLC_GPU_IOV_SDMA7_STATUS__SAVED__SHIFT 0x8
+#define RLC_GPU_IOV_SDMA7_STATUS__RESERVED1__SHIFT 0x9
+#define RLC_GPU_IOV_SDMA7_STATUS__RESTORED__SHIFT 0xc
+#define RLC_GPU_IOV_SDMA7_STATUS__RESERVED2__SHIFT 0xd
+#define RLC_GPU_IOV_SDMA7_STATUS__PREEMPTED_MASK 0x00000001L
+#define RLC_GPU_IOV_SDMA7_STATUS__RESERVED_MASK 0x000000FEL
+#define RLC_GPU_IOV_SDMA7_STATUS__SAVED_MASK 0x00000100L
+#define RLC_GPU_IOV_SDMA7_STATUS__RESERVED1_MASK 0x00000E00L
+#define RLC_GPU_IOV_SDMA7_STATUS__RESTORED_MASK 0x00001000L
+#define RLC_GPU_IOV_SDMA7_STATUS__RESERVED2_MASK 0xFFFFE000L
+//RLC_GPU_IOV_SDMA2_BUSY_STATUS
+#define RLC_GPU_IOV_SDMA2_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
+#define RLC_GPU_IOV_SDMA2_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_SDMA3_BUSY_STATUS
+#define RLC_GPU_IOV_SDMA3_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
+#define RLC_GPU_IOV_SDMA3_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_SDMA4_BUSY_STATUS
+#define RLC_GPU_IOV_SDMA4_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
+#define RLC_GPU_IOV_SDMA4_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_SDMA5_BUSY_STATUS
+#define RLC_GPU_IOV_SDMA5_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
+#define RLC_GPU_IOV_SDMA5_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_SDMA6_BUSY_STATUS
+#define RLC_GPU_IOV_SDMA6_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
+#define RLC_GPU_IOV_SDMA6_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_SDMA7_BUSY_STATUS
+#define RLC_GPU_IOV_SDMA7_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
+#define RLC_GPU_IOV_SDMA7_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL
+
+
+// addressBlock: gc_padec
+//VGT_VTX_VECT_EJECT_REG
+#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0
+#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x0000007FL
+//VGT_DMA_DATA_FIFO_DEPTH
+#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0
+#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH__SHIFT 0x9
+#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x000001FFL
+#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH_MASK 0x0007FE00L
+//VGT_DMA_REQ_FIFO_DEPTH
+#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0
+#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x0000003FL
+//VGT_DRAW_INIT_FIFO_DEPTH
+#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0
+#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x0000003FL
+//VGT_LAST_COPY_STATE
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
+#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L
+#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00070000L
+//VGT_CACHE_INVALIDATION
+#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0
+#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT 0x4
+#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x5
+#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6
+#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9
+#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb
+#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc
+#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd
+#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10
+#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG__SHIFT 0x15
+#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1__SHIFT 0x16
+#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2__SHIFT 0x19
+#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE__SHIFT 0x1c
+#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI__SHIFT 0x1d
+#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x00000003L
+#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK 0x00000010L
+#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x00000020L
+#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0x000000C0L
+#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x00000200L
+#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x00000800L
+#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x00001000L
+#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x00002000L
+#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x001F0000L
+#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_MASK 0x00200000L
+#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1_MASK 0x01C00000L
+#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2_MASK 0x0E000000L
+#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE_MASK 0x10000000L
+#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI_MASK 0x20000000L
+//VGT_STRMOUT_DELAY
+#define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0
+#define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8
+#define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb
+#define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe
+#define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11
+#define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0x000000FFL
+#define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x00000700L
+#define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x00003800L
+#define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x0001C000L
+#define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0x000E0000L
+//VGT_FIFO_DEPTHS
+#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0
+#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7
+#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8
+#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT 0x16
+#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x0000007FL
+#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x00000080L
+#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x003FFF00L
+#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK 0x0FC00000L
+//VGT_GS_VERTEX_REUSE
+#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0
+#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x0000001FL
+//VGT_MC_LAT_CNTL
+#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0
+#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x0000000FL
+//IA_CNTL_STATUS
+#define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x0
+#define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x1
+#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x2
+#define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x3
+#define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x4
+#define IA_CNTL_STATUS__IA_BUSY_MASK 0x00000001L
+#define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x00000002L
+#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x00000004L
+#define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x00000008L
+#define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x00000010L
+//VGT_CNTL_STATUS
+#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2
+#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3
+#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4
+#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5
+#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6
+#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7
+#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8
+#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9
+#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY__SHIFT 0xa
+#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000002L
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000004L
+#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000008L
+#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x00000010L
+#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000020L
+#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x00000040L
+#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x00000080L
+#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x00000100L
+#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x00000200L
+#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY_MASK 0x00000400L
+//WD_CNTL_STATUS
+#define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0
+#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1
+#define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2
+#define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3
+#define WD_CNTL_STATUS__WD_BUSY_MASK 0x00000001L
+#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x00000002L
+#define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x00000004L
+#define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x00000008L
+//CC_GC_PRIM_CONFIG
+#define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
+#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
+#define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L
+#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L
+//GC_USER_PRIM_CONFIG
+#define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
+#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
+#define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L
+#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L
+//WD_QOS
+#define WD_QOS__DRAW_STALL__SHIFT 0x0
+#define WD_QOS__DRAW_STALL_MASK 0x00000001L
+//WD_UTCL1_CNTL
+#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
+#define WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17
+#define WD_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
+#define WD_UTCL1_CNTL__BYPASS__SHIFT 0x19
+#define WD_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
+#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
+#define WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
+#define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
+#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
+#define WD_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L
+#define WD_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
+#define WD_UTCL1_CNTL__BYPASS_MASK 0x02000000L
+#define WD_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
+#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
+#define WD_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
+#define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
+//WD_UTCL1_STATUS
+#define WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
+#define WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
+#define WD_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
+#define WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
+#define WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
+#define WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
+#define WD_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
+#define WD_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
+#define WD_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
+#define WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
+#define WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
+#define WD_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
+//IA_UTCL1_CNTL
+#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
+#define IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17
+#define IA_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
+#define IA_UTCL1_CNTL__BYPASS__SHIFT 0x19
+#define IA_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
+#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
+#define IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
+#define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
+#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
+#define IA_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L
+#define IA_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
+#define IA_UTCL1_CNTL__BYPASS_MASK 0x02000000L
+#define IA_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
+#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
+#define IA_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
+#define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
+//IA_UTCL1_STATUS
+#define IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
+#define IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
+#define IA_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
+#define IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
+#define IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
+#define IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
+#define IA_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
+#define IA_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
+#define IA_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
+#define IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
+#define IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
+#define IA_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
+//VGT_SYS_CONFIG
+#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0
+#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1
+#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7
+#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x00000001L
+#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x0000007EL
+#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x00000080L
+//VGT_VS_MAX_WAVE_ID
+#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
+#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
+//VGT_GS_MAX_WAVE_ID
+#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
+#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
+//GFX_PIPE_CONTROL
+#define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0
+#define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd
+#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10
+#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x00001FFFL
+#define GFX_PIPE_CONTROL__RESERVED_MASK 0x0000E000L
+#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x00010000L
+//CC_GC_SHADER_ARRAY_CONFIG
+#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10
+#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L
+//GC_USER_SHADER_ARRAY_CONFIG
+#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10
+#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L
+//VGT_DMA_PRIMITIVE_TYPE
+#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0
+#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL
+//VGT_DMA_CONTROL
+#define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0
+#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11
+#define VGT_DMA_CONTROL__SWITCH_ON_EOI__SHIFT 0x13
+#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14
+#define VGT_DMA_CONTROL__EN_INST_OPT_BASIC__SHIFT 0x15
+#define VGT_DMA_CONTROL__EN_INST_OPT_ADV__SHIFT 0x16
+#define VGT_DMA_CONTROL__HW_USE_ONLY__SHIFT 0x17
+#define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0x0000FFFFL
+#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x00020000L
+#define VGT_DMA_CONTROL__SWITCH_ON_EOI_MASK 0x00080000L
+#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x00100000L
+#define VGT_DMA_CONTROL__EN_INST_OPT_BASIC_MASK 0x00200000L
+#define VGT_DMA_CONTROL__EN_INST_OPT_ADV_MASK 0x00400000L
+#define VGT_DMA_CONTROL__HW_USE_ONLY_MASK 0x00800000L
+//VGT_DMA_LS_HS_CONFIG
+#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8
+#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L
+//WD_BUF_RESOURCE_1
+#define WD_BUF_RESOURCE_1__POS_BUF_SIZE__SHIFT 0x0
+#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE__SHIFT 0x10
+#define WD_BUF_RESOURCE_1__POS_BUF_SIZE_MASK 0x0000FFFFL
+#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE_MASK 0xFFFF0000L
+//WD_BUF_RESOURCE_2
+#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE__SHIFT 0x0
+#define WD_BUF_RESOURCE_2__ADDR_MODE__SHIFT 0xf
+#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE__SHIFT 0x10
+#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE_MASK 0x00001FFFL
+#define WD_BUF_RESOURCE_2__ADDR_MODE_MASK 0x00008000L
+#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE_MASK 0xFFFF0000L
+//PA_CL_CNTL_STATUS
+#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT 0x0
+#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED__SHIFT 0x1
+#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED__SHIFT 0x2
+#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED_MASK 0x00000001L
+#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED_MASK 0x00000002L
+#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED_MASK 0x00000004L
+//PA_CL_ENHANCE
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0
+#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1
+#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3
+#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4
+#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT 0x6
+#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT 0x7
+#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT 0x8
+#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT 0x9
+#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT 0xb
+#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT 0xc
+#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT 0xe
+#define PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE__SHIFT 0x11
+#define PA_CL_ENHANCE__OUTPUT_SWITCH_TO_LEGACY_EVENT__SHIFT 0x12
+#define PA_CL_ENHANCE__NO_SWITCH_TO_LEGACY_AFTER_VMID_RESET__SHIFT 0x13
+#define PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE__SHIFT 0x14
+#define PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE__SHIFT 0x15
+#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c
+#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d
+#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e
+#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L
+#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x00000006L
+#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x00000008L
+#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x00000010L
+#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK 0x00000040L
+#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK 0x00000080L
+#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK 0x00000100L
+#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK 0x00000600L
+#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK 0x00000800L
+#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK 0x00003000L
+#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK 0x0001C000L
+#define PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE_MASK 0x00020000L
+#define PA_CL_ENHANCE__OUTPUT_SWITCH_TO_LEGACY_EVENT_MASK 0x00040000L
+#define PA_CL_ENHANCE__NO_SWITCH_TO_LEGACY_AFTER_VMID_RESET_MASK 0x00080000L
+#define PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE_MASK 0x00100000L
+#define PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE_MASK 0x00200000L
+#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L
+#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L
+#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L
+#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L
+//PA_SU_CNTL_STATUS
+#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f
+#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L
+//PA_SC_FIFO_DEPTH_CNTL
+#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0
+#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x000003FFL
+//PA_SC_P3D_TRAP_SCREEN_HV_LOCK
+#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L
+//PA_SC_HP3D_TRAP_SCREEN_HV_LOCK
+#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L
+//PA_SC_TRAP_SCREEN_HV_LOCK
+#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L
+//PA_SC_FORCE_EOV_MAX_CNTS
+#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0
+#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10
+#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0x0000FFFFL
+#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xFFFF0000L
+//PA_SC_BINNER_EVENT_CNTL_0
+#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT 0x0
+#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT 0x2
+#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT 0x4
+#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT 0x6
+#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT 0x8
+#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT 0xa
+#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT 0xc
+#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT 0xe
+#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT 0x10
+#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9__SHIFT 0x12
+#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT 0x14
+#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT 0x16
+#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT 0x18
+#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT 0x1a
+#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT 0x1c
+#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT 0x1e
+#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK 0x00000003L
+#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK 0x0000000CL
+#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK 0x00000030L
+#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK 0x000000C0L
+#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK 0x00000300L
+#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK 0x00000C00L
+#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK 0x00003000L
+#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK 0x0000C000L
+#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK 0x00030000L
+#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9_MASK 0x000C0000L
+#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK 0x00300000L
+#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK 0x00C00000L
+#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK 0x03000000L
+#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK 0x0C000000L
+#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK 0x30000000L
+#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK 0xC0000000L
+//PA_SC_BINNER_EVENT_CNTL_1
+#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT 0x0
+#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT 0x2
+#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT 0x4
+#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT 0x6
+#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT 0x8
+#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE__SHIFT 0xa
+#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT 0xc
+#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT 0xe
+#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT 0x10
+#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT 0x12
+#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT 0x14
+#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT 0x16
+#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT 0x18
+#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT__SHIFT 0x1a
+#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT 0x1c
+#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT 0x1e
+#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK 0x00000003L
+#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK 0x0000000CL
+#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK 0x00000030L
+#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK 0x000000C0L
+#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK 0x00000300L
+#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE_MASK 0x00000C00L
+#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK 0x00003000L
+#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK 0x0000C000L
+#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK 0x00030000L
+#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK 0x000C0000L
+#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK 0x00300000L
+#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK 0x00C00000L
+#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK 0x03000000L
+#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT_MASK 0x0C000000L
+#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK 0x30000000L
+#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK 0xC0000000L
+//PA_SC_BINNER_EVENT_CNTL_2
+#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT 0x0
+#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT 0x2
+#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT 0x4
+#define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE__SHIFT 0x6
+#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT 0x8
+#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT 0xa
+#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT 0xc
+#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT 0xe
+#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT 0x10
+#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS__SHIFT 0x12
+#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT 0x14
+#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT 0x16
+#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT 0x18
+#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT 0x1a
+#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT 0x1c
+#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT 0x1e
+#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK 0x00000003L
+#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK 0x0000000CL
+#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK 0x00000030L
+#define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE_MASK 0x000000C0L
+#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK 0x00000300L
+#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK 0x00000C00L
+#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK 0x00003000L
+#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK 0x0000C000L
+#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK 0x00030000L
+#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS_MASK 0x000C0000L
+#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK 0x00300000L
+#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK 0x00C00000L
+#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK 0x03000000L
+#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK 0x0C000000L
+#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK 0x30000000L
+#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK 0xC0000000L
+//PA_SC_BINNER_EVENT_CNTL_3
+#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT 0x0
+#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT 0x2
+#define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST__SHIFT 0x4
+#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT 0x6
+#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT 0x8
+#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT 0xa
+#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH__SHIFT 0xc
+#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT 0xe
+#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT 0x10
+#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT 0x12
+#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT 0x14
+#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT 0x16
+#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT 0x18
+#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT 0x1a
+#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE__SHIFT 0x1c
+#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63__SHIFT 0x1e
+#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK 0x00000003L
+#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK 0x0000000CL
+#define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST_MASK 0x00000030L
+#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK 0x000000C0L
+#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK 0x00000300L
+#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK 0x00000C00L
+#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH_MASK 0x00003000L
+#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK 0x0000C000L
+#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK 0x00030000L
+#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK 0x000C0000L
+#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK 0x00300000L
+#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK 0x00C00000L
+#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK 0x03000000L
+#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK 0x0C000000L
+#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE_MASK 0x30000000L
+#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63_MASK 0xC0000000L
+//PA_SC_BINNER_TIMEOUT_COUNTER
+#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT 0x0
+#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK 0xFFFFFFFFL
+//PA_SC_BINNER_PERF_CNTL_0
+#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0x0
+#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0xa
+#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x14
+#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x17
+#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000003FFL
+#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000FFC00L
+#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x00700000L
+#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x03800000L
+//PA_SC_BINNER_PERF_CNTL_1
+#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x0
+#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x5
+#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT 0xa
+#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x0000001FL
+#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x000003E0L
+#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK 0x03FFFC00L
+//PA_SC_BINNER_PERF_CNTL_2
+#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT 0x0
+#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT 0xb
+#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK 0x000007FFL
+#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK 0x003FF800L
+//PA_SC_BINNER_PERF_CNTL_3
+#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT 0x0
+#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK 0xFFFFFFFFL
+//PA_SC_ENHANCE_2
+#define PA_SC_ENHANCE_2__RESERVED_0__SHIFT 0x0
+#define PA_SC_ENHANCE_2__RESERVED_1__SHIFT 0x1
+#define PA_SC_ENHANCE_2__RESERVED_2__SHIFT 0x2
+#define PA_SC_ENHANCE_2__RESERVED_3__SHIFT 0x3
+#define PA_SC_ENHANCE_2__RESERVED_4__SHIFT 0x4
+#define PA_SC_ENHANCE_2__RESERVED_5__SHIFT 0x5
+#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_COMPOUND_INDEX_EN__SHIFT 0x6
+#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PIPELINE_PRIMID__SHIFT 0x7
+#define PA_SC_ENHANCE_2__RSVD__SHIFT 0x8
+#define PA_SC_ENHANCE_2__RESERVED_0_MASK 0x00000001L
+#define PA_SC_ENHANCE_2__RESERVED_1_MASK 0x00000002L
+#define PA_SC_ENHANCE_2__RESERVED_2_MASK 0x00000004L
+#define PA_SC_ENHANCE_2__RESERVED_3_MASK 0x00000008L
+#define PA_SC_ENHANCE_2__RESERVED_4_MASK 0x00000010L
+#define PA_SC_ENHANCE_2__RESERVED_5_MASK 0x00000020L
+#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_COMPOUND_INDEX_EN_MASK 0x00000040L
+#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PIPELINE_PRIMID_MASK 0x00000080L
+#define PA_SC_ENHANCE_2__RSVD_MASK 0xFFFFFF00L
+//PA_SC_FIFO_SIZE
+#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0
+#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6
+#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf
+#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x15
+#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x0000003FL
+#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x00007FC0L
+#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x001F8000L
+#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xFFE00000L
+//PA_SC_IF_FIFO_SIZE
+#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0
+#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6
+#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc
+#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12
+#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x0000003FL
+#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0x00000FC0L
+#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x0003F000L
+#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0x00FC0000L
+//PA_SC_PKR_WAVE_TABLE_CNTL
+#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT 0x0
+#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL
+//PA_UTCL1_CNTL1
+#define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
+#define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1
+#define PA_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
+#define PA_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
+#define PA_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
+#define PA_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
+#define PA_UTCL1_CNTL1__SPARE__SHIFT 0x10
+#define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
+#define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
+#define PA_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13
+#define PA_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17
+#define PA_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18
+#define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID__SHIFT 0x19
+#define PA_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
+#define PA_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
+#define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
+#define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
+#define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
+#define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L
+#define PA_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
+#define PA_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
+#define PA_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
+#define PA_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
+#define PA_UTCL1_CNTL1__SPARE_MASK 0x00010000L
+#define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
+#define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
+#define PA_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L
+#define PA_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L
+#define PA_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L
+#define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID_MASK 0x02000000L
+#define PA_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
+#define PA_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
+#define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
+#define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
+//PA_UTCL1_CNTL2
+#define PA_UTCL1_CNTL2__SPARE1__SHIFT 0x0
+#define PA_UTCL1_CNTL2__SPARE2__SHIFT 0x8
+#define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
+#define PA_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
+#define PA_UTCL1_CNTL2__SPARE3__SHIFT 0xb
+#define PA_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
+#define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT__SHIFT 0xd
+#define PA_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
+#define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
+#define PA_UTCL1_CNTL2__SPARE4__SHIFT 0x10
+#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
+#define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13
+#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14
+#define PA_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15
+#define PA_UTCL1_CNTL2__SPARE5__SHIFT 0x19
+#define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
+#define PA_UTCL1_CNTL2__RESERVED__SHIFT 0x1b
+#define PA_UTCL1_CNTL2__SPARE1_MASK 0x000000FFL
+#define PA_UTCL1_CNTL2__SPARE2_MASK 0x00000100L
+#define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
+#define PA_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
+#define PA_UTCL1_CNTL2__SPARE3_MASK 0x00000800L
+#define PA_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
+#define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT_MASK 0x00002000L
+#define PA_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
+#define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
+#define PA_UTCL1_CNTL2__SPARE4_MASK 0x00030000L
+#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
+#define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L
+#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
+#define PA_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L
+#define PA_UTCL1_CNTL2__SPARE5_MASK 0x02000000L
+#define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
+#define PA_UTCL1_CNTL2__RESERVED_MASK 0xF8000000L
+//PA_SIDEBAND_REQUEST_DELAYS
+#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY__SHIFT 0x0
+#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY__SHIFT 0x10
+#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY_MASK 0x0000FFFFL
+#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY_MASK 0xFFFF0000L
+//PA_SC_ENHANCE
+#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0
+#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1
+#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2
+#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3
+#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4
+#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5
+#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x6
+#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x7
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0x8
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0x9
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xa
+#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xb
+#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xc
+#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xd
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0xe
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0xf
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x10
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x11
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x12
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x13
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x14
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x15
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x16
+#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x17
+#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18
+#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x19
+#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1a
+#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1b
+#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c
+#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT 0x1d
+#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x00000001L
+#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x00000002L
+#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x00000004L
+#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x00000008L
+#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x00000010L
+#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x00000020L
+#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x00000040L
+#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x00000080L
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x00000100L
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x00000200L
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x00000400L
+#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x00000800L
+#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x00001000L
+#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x00002000L
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x00004000L
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x00008000L
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x00010000L
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x00020000L
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x00040000L
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x00080000L
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x00100000L
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x00200000L
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x00400000L
+#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x00800000L
+#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L
+#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x02000000L
+#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x04000000L
+#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x08000000L
+#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK 0x10000000L
+#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK 0x20000000L
+//PA_SC_ENHANCE_1
+#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT 0x0
+#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT 0x1
+#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT 0x3
+#define PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT 0x4
+#define PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT 0x5
+#define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT 0x6
+#define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT 0x7
+#define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT 0x8
+#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT 0x9
+#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT 0xa
+#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT 0xb
+#define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT 0xd
+#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE__SHIFT 0xe
+#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION__SHIFT 0xf
+#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT 0x10
+#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING__SHIFT 0x11
+#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT 0x12
+#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT 0x13
+#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT 0x14
+#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT 0x15
+#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT 0x16
+#define PA_SC_ENHANCE_1__DISABLE_INTF_CG__SHIFT 0x17
+#define PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18
+#define PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER__SHIFT 0x19
+#define PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION__SHIFT 0x1a
+#define PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE__SHIFT 0x1b
+#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX__SHIFT 0x1c
+#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1__SHIFT 0x1d
+#define PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI__SHIFT 0x1e
+#define PA_SC_ENHANCE_1__RSVD__SHIFT 0x1f
+#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK 0x00000001L
+#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK 0x00000006L
+#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK 0x00000008L
+#define PA_SC_ENHANCE_1__BYPASS_PBB_MASK 0x00000010L
+#define PA_SC_ENHANCE_1__ECO_SPARE0_MASK 0x00000020L
+#define PA_SC_ENHANCE_1__ECO_SPARE1_MASK 0x00000040L
+#define PA_SC_ENHANCE_1__ECO_SPARE2_MASK 0x00000080L
+#define PA_SC_ENHANCE_1__ECO_SPARE3_MASK 0x00000100L
+#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK 0x00000200L
+#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK 0x00000400L
+#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK 0x00000800L
+#define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK 0x00002000L
+#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE_MASK 0x00004000L
+#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION_MASK 0x00008000L
+#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK 0x00010000L
+#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING_MASK 0x00020000L
+#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK 0x00040000L
+#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK 0x00080000L
+#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK 0x00100000L
+#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK 0x00200000L
+#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK 0x00400000L
+#define PA_SC_ENHANCE_1__DISABLE_INTF_CG_MASK 0x00800000L
+#define PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L
+#define PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER_MASK 0x02000000L
+#define PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION_MASK 0x04000000L
+#define PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE_MASK 0x08000000L
+#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_MASK 0x10000000L
+#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1_MASK 0x20000000L
+#define PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI_MASK 0x40000000L
+#define PA_SC_ENHANCE_1__RSVD_MASK 0x80000000L
+//PA_SC_DSM_CNTL
+#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0
+#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT 0x1
+#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK 0x00000001L
+#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK 0x00000002L
+//PA_SC_TILE_STEERING_CREST_OVERRIDE
+#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT 0x0
+#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT 0x1
+#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT 0x5
+#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK 0x00000001L
+#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK 0x00000006L
+#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK 0x00000060L
+
+
+// addressBlock: gc_perfddec
+//CPG_PERFCOUNTER1_LO
+#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CPG_PERFCOUNTER1_HI
+#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CPG_PERFCOUNTER0_LO
+#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CPG_PERFCOUNTER0_HI
+#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CPC_PERFCOUNTER1_LO
+#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CPC_PERFCOUNTER1_HI
+#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CPC_PERFCOUNTER0_LO
+#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CPC_PERFCOUNTER0_HI
+#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CPF_PERFCOUNTER1_LO
+#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CPF_PERFCOUNTER1_HI
+#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CPF_PERFCOUNTER0_LO
+#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CPF_PERFCOUNTER0_HI
+#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CPF_LATENCY_STATS_DATA
+#define CPF_LATENCY_STATS_DATA__DATA__SHIFT 0x0
+#define CPF_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL
+//CPG_LATENCY_STATS_DATA
+#define CPG_LATENCY_STATS_DATA__DATA__SHIFT 0x0
+#define CPG_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL
+//CPC_LATENCY_STATS_DATA
+#define CPC_LATENCY_STATS_DATA__DATA__SHIFT 0x0
+#define CPC_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL
+//GRBM_PERFCOUNTER0_LO
+#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GRBM_PERFCOUNTER0_HI
+#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GRBM_PERFCOUNTER1_LO
+#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GRBM_PERFCOUNTER1_HI
+#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GRBM_SE0_PERFCOUNTER_LO
+#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GRBM_SE0_PERFCOUNTER_HI
+#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GRBM_SE1_PERFCOUNTER_LO
+#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GRBM_SE1_PERFCOUNTER_HI
+#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GRBM_SE2_PERFCOUNTER_LO
+#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GRBM_SE2_PERFCOUNTER_HI
+#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GRBM_SE3_PERFCOUNTER_LO
+#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GRBM_SE3_PERFCOUNTER_HI
+#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//WD_PERFCOUNTER0_LO
+#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//WD_PERFCOUNTER0_HI
+#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//WD_PERFCOUNTER1_LO
+#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//WD_PERFCOUNTER1_HI
+#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//WD_PERFCOUNTER2_LO
+#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//WD_PERFCOUNTER2_HI
+#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//WD_PERFCOUNTER3_LO
+#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//WD_PERFCOUNTER3_HI
+#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//IA_PERFCOUNTER0_LO
+#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//IA_PERFCOUNTER0_HI
+#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//IA_PERFCOUNTER1_LO
+#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//IA_PERFCOUNTER1_HI
+#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//IA_PERFCOUNTER2_LO
+#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//IA_PERFCOUNTER2_HI
+#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//IA_PERFCOUNTER3_LO
+#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//IA_PERFCOUNTER3_HI
+#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//VGT_PERFCOUNTER0_LO
+#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//VGT_PERFCOUNTER0_HI
+#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//VGT_PERFCOUNTER1_LO
+#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//VGT_PERFCOUNTER1_HI
+#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//VGT_PERFCOUNTER2_LO
+#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//VGT_PERFCOUNTER2_HI
+#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//VGT_PERFCOUNTER3_LO
+#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//VGT_PERFCOUNTER3_HI
+#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//PA_SU_PERFCOUNTER0_LO
+#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SU_PERFCOUNTER0_HI
+#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL
+//PA_SU_PERFCOUNTER1_LO
+#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SU_PERFCOUNTER1_HI
+#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL
+//PA_SU_PERFCOUNTER2_LO
+#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SU_PERFCOUNTER2_HI
+#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL
+//PA_SU_PERFCOUNTER3_LO
+#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SU_PERFCOUNTER3_HI
+#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL
+//PA_SC_PERFCOUNTER0_LO
+#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER0_HI
+#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER1_LO
+#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER1_HI
+#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER2_LO
+#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER2_HI
+#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER3_LO
+#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER3_HI
+#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER4_LO
+#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER4_HI
+#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER5_LO
+#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER5_HI
+#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER6_LO
+#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER6_HI
+#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER7_LO
+#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER7_HI
+#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER0_HI
+#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER0_LO
+#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER1_HI
+#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER1_LO
+#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER2_HI
+#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER2_LO
+#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER3_HI
+#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER3_LO
+#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER4_HI
+#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER4_LO
+#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER5_HI
+#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER5_LO
+#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER0_LO
+#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER0_HI
+#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER1_LO
+#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER1_HI
+#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER2_LO
+#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER2_HI
+#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER3_LO
+#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER3_HI
+#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER4_LO
+#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER4_HI
+#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER5_LO
+#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER5_HI
+#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER6_LO
+#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER6_HI
+#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER7_LO
+#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER7_HI
+#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER8_LO
+#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER8_HI
+#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER9_LO
+#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER9_HI
+#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER10_LO
+#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER10_HI
+#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER11_LO
+#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER11_HI
+#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER12_LO
+#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER12_HI
+#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER13_LO
+#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER13_HI
+#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER14_LO
+#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER14_HI
+#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER15_LO
+#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER15_HI
+#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SX_PERFCOUNTER0_LO
+#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SX_PERFCOUNTER0_HI
+#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SX_PERFCOUNTER1_LO
+#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SX_PERFCOUNTER1_HI
+#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SX_PERFCOUNTER2_LO
+#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SX_PERFCOUNTER2_HI
+#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SX_PERFCOUNTER3_LO
+#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SX_PERFCOUNTER3_HI
+#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GDS_PERFCOUNTER0_LO
+#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GDS_PERFCOUNTER0_HI
+#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GDS_PERFCOUNTER1_LO
+#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GDS_PERFCOUNTER1_HI
+#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GDS_PERFCOUNTER2_LO
+#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GDS_PERFCOUNTER2_HI
+#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GDS_PERFCOUNTER3_LO
+#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GDS_PERFCOUNTER3_HI
+#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TA_PERFCOUNTER0_LO
+#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TA_PERFCOUNTER0_HI
+#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TA_PERFCOUNTER1_LO
+#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TA_PERFCOUNTER1_HI
+#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TD_PERFCOUNTER0_LO
+#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TD_PERFCOUNTER0_HI
+#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TD_PERFCOUNTER1_LO
+#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TD_PERFCOUNTER1_HI
+#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TCP_PERFCOUNTER0_LO
+#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TCP_PERFCOUNTER0_HI
+#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TCP_PERFCOUNTER1_LO
+#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TCP_PERFCOUNTER1_HI
+#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TCP_PERFCOUNTER2_LO
+#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TCP_PERFCOUNTER2_HI
+#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TCP_PERFCOUNTER3_LO
+#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TCP_PERFCOUNTER3_HI
+#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TCC_PERFCOUNTER0_LO
+#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TCC_PERFCOUNTER0_HI
+#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TCC_PERFCOUNTER1_LO
+#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TCC_PERFCOUNTER1_HI
+#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TCC_PERFCOUNTER2_LO
+#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TCC_PERFCOUNTER2_HI
+#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TCC_PERFCOUNTER3_LO
+#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TCC_PERFCOUNTER3_HI
+#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TCA_PERFCOUNTER0_LO
+#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TCA_PERFCOUNTER0_HI
+#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TCA_PERFCOUNTER1_LO
+#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TCA_PERFCOUNTER1_HI
+#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TCA_PERFCOUNTER2_LO
+#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TCA_PERFCOUNTER2_HI
+#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TCA_PERFCOUNTER3_LO
+#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TCA_PERFCOUNTER3_HI
+#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CB_PERFCOUNTER0_LO
+#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CB_PERFCOUNTER0_HI
+#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CB_PERFCOUNTER1_LO
+#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CB_PERFCOUNTER1_HI
+#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CB_PERFCOUNTER2_LO
+#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CB_PERFCOUNTER2_HI
+#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CB_PERFCOUNTER3_LO
+#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CB_PERFCOUNTER3_HI
+#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//DB_PERFCOUNTER0_LO
+#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//DB_PERFCOUNTER0_HI
+#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//DB_PERFCOUNTER1_LO
+#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//DB_PERFCOUNTER1_HI
+#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//DB_PERFCOUNTER2_LO
+#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//DB_PERFCOUNTER2_HI
+#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//DB_PERFCOUNTER3_LO
+#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//DB_PERFCOUNTER3_HI
+#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//RLC_PERFCOUNTER0_LO
+#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//RLC_PERFCOUNTER0_HI
+#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//RLC_PERFCOUNTER1_LO
+#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//RLC_PERFCOUNTER1_HI
+#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//RMI_PERFCOUNTER0_LO
+#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//RMI_PERFCOUNTER0_HI
+#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//RMI_PERFCOUNTER1_LO
+#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//RMI_PERFCOUNTER1_HI
+#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//RMI_PERFCOUNTER2_LO
+#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//RMI_PERFCOUNTER2_HI
+#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//RMI_PERFCOUNTER3_LO
+#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//RMI_PERFCOUNTER3_HI
+#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: gc_perfsdec
+//CPG_PERFCOUNTER1_SELECT
+#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0
+#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa
+#define CPG_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
+#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18
+#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c
+#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL
+#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L
+#define CPG_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L
+#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L
+#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L
+//CPG_PERFCOUNTER0_SELECT1
+#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0
+#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa
+#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18
+#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c
+#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL
+#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L
+#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L
+#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L
+//CPG_PERFCOUNTER0_SELECT
+#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0
+#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa
+#define CPG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
+#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18
+#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c
+#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL
+#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L
+#define CPG_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L
+#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L
+#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L
+//CPC_PERFCOUNTER1_SELECT
+#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0
+#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa
+#define CPC_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
+#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18
+#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c
+#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL
+#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L
+#define CPC_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L
+#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L
+#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L
+//CPC_PERFCOUNTER0_SELECT1
+#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0
+#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa
+#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18
+#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c
+#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL
+#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L
+#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L
+#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L
+//CPF_PERFCOUNTER1_SELECT
+#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0
+#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa
+#define CPF_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
+#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18
+#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c
+#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL
+#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L
+#define CPF_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L
+#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L
+#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L
+//CPF_PERFCOUNTER0_SELECT1
+#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0
+#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa
+#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18
+#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c
+#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL
+#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L
+#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L
+#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L
+//CPF_PERFCOUNTER0_SELECT
+#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0
+#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa
+#define CPF_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
+#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18
+#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c
+#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL
+#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L
+#define CPF_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L
+#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L
+#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L
+//CP_PERFMON_CNTL
+#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4
+#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8
+#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
+#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000FL
+#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0x000000F0L
+#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L
+#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L
+//CPC_PERFCOUNTER0_SELECT
+#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0
+#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa
+#define CPC_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
+#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18
+#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c
+#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL
+#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L
+#define CPC_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L
+#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L
+#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L
+//CPF_TC_PERF_COUNTER_WINDOW_SELECT
+#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0
+#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e
+#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f
+#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x00000007L
+#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L
+#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L
+//CPG_TC_PERF_COUNTER_WINDOW_SELECT
+#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0
+#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e
+#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f
+#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x0000001FL
+#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L
+#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L
+//CPF_LATENCY_STATS_SELECT
+#define CPF_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0
+#define CPF_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e
+#define CPF_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f
+#define CPF_LATENCY_STATS_SELECT__INDEX_MASK 0x0000000FL
+#define CPF_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L
+#define CPF_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L
+//CPG_LATENCY_STATS_SELECT
+#define CPG_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0
+#define CPG_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e
+#define CPG_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f
+#define CPG_LATENCY_STATS_SELECT__INDEX_MASK 0x0000001FL
+#define CPG_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L
+#define CPG_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L
+//CPC_LATENCY_STATS_SELECT
+#define CPC_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0
+#define CPC_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e
+#define CPC_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f
+#define CPC_LATENCY_STATS_SELECT__INDEX_MASK 0x00000007L
+#define CPC_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L
+#define CPC_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L
+//CP_DRAW_OBJECT
+#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0
+#define CP_DRAW_OBJECT__OBJECT_MASK 0xFFFFFFFFL
+//CP_DRAW_OBJECT_COUNTER
+#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0
+#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0x0000FFFFL
+//CP_DRAW_WINDOW_MASK_HI
+#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0
+#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xFFFFFFFFL
+//CP_DRAW_WINDOW_HI
+#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0
+#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xFFFFFFFFL
+//CP_DRAW_WINDOW_LO
+#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0
+#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10
+#define CP_DRAW_WINDOW_LO__MIN_MASK 0x0000FFFFL
+#define CP_DRAW_WINDOW_LO__MAX_MASK 0xFFFF0000L
+//CP_DRAW_WINDOW_CNTL
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2
+#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x00000001L
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x00000002L
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x00000004L
+#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x00000100L
+//GRBM_PERFCOUNTER0_SELECT
+#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc
+#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
+#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
+#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
+#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17
+#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
+#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
+#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
+#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
+#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
+#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d
+#define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e
+#define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f
+#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003FL
+#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
+#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
+#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
+#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
+#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L
+#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
+#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
+#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
+#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
+#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
+#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
+#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
+#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L
+#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L
+#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L
+#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L
+#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L
+#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L
+#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L
+#define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L
+#define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L
+//GRBM_PERFCOUNTER1_SELECT
+#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc
+#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
+#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
+#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
+#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17
+#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
+#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
+#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
+#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
+#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
+#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d
+#define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e
+#define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f
+#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003FL
+#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
+#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
+#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
+#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
+#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L
+#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
+#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
+#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
+#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
+#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
+#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
+#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
+#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L
+#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L
+#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L
+#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L
+#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L
+#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L
+#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L
+#define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L
+#define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L
+//GRBM_SE0_PERFCOUNTER_SELECT
+#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
+#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
+#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
+#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16
+#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_SE4__SHIFT 0x17
+#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_SE4__SHIFT 0x18
+#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_SE4__SHIFT 0x19
+#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL
+#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
+#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
+#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
+#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
+#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L
+#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
+#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
+#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
+#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
+#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
+#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
+#define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
+#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_SE4_MASK 0x00800000L
+#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_SE4_MASK 0x01000000L
+#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_SE4_MASK 0x02000000L
+//GRBM_SE1_PERFCOUNTER_SELECT
+#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
+#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
+#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
+#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16
+#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_SE5__SHIFT 0x17
+#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_SE5__SHIFT 0x18
+#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_SE5__SHIFT 0x19
+#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL
+#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
+#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
+#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
+#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
+#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L
+#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
+#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
+#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
+#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
+#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
+#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
+#define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
+#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_SE5_MASK 0x00800000L
+#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_SE5_MASK 0x01000000L
+#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_SE5_MASK 0x02000000L
+//GRBM_SE2_PERFCOUNTER_SELECT
+#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
+#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
+#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
+#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16
+#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_SE6__SHIFT 0x17
+#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_SE6__SHIFT 0x18
+#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_SE6__SHIFT 0x19
+#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL
+#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
+#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
+#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
+#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
+#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L
+#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
+#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
+#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
+#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
+#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
+#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
+#define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
+#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_SE6_MASK 0x00800000L
+#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_SE6_MASK 0x01000000L
+#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_SE6_MASK 0x02000000L
+//GRBM_SE3_PERFCOUNTER_SELECT
+#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
+#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
+#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
+#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16
+#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_SE7__SHIFT 0x17
+#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_SE7__SHIFT 0x18
+#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_SE7__SHIFT 0x19
+#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL
+#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
+#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
+#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
+#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
+#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L
+#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
+#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
+#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
+#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
+#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
+#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
+#define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
+#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_SE7_MASK 0x00800000L
+#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_SE7_MASK 0x01000000L
+#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_SE7_MASK 0x02000000L
+//WD_PERFCOUNTER0_SELECT
+#define WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL
+#define WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//WD_PERFCOUNTER1_SELECT
+#define WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL
+#define WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//WD_PERFCOUNTER2_SELECT
+#define WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL
+#define WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//WD_PERFCOUNTER3_SELECT
+#define WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL
+#define WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//IA_PERFCOUNTER0_SELECT
+#define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//IA_PERFCOUNTER1_SELECT
+#define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL
+#define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//IA_PERFCOUNTER2_SELECT
+#define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL
+#define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//IA_PERFCOUNTER3_SELECT
+#define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL
+#define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//IA_PERFCOUNTER0_SELECT1
+#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//VGT_PERFCOUNTER0_SELECT
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//VGT_PERFCOUNTER1_SELECT
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//VGT_PERFCOUNTER2_SELECT
+#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL
+#define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//VGT_PERFCOUNTER3_SELECT
+#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL
+#define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//VGT_PERFCOUNTER0_SELECT1
+#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//VGT_PERFCOUNTER1_SELECT1
+#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
+#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//VGT_PERFCOUNTER_SEID_MASK
+#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT 0x0
+#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK 0x000000FFL
+//PA_SU_PERFCOUNTER0_SELECT
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//PA_SU_PERFCOUNTER0_SELECT1
+#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//PA_SU_PERFCOUNTER1_SELECT
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//PA_SU_PERFCOUNTER1_SELECT1
+#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
+#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//PA_SU_PERFCOUNTER2_SELECT
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
+#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//PA_SU_PERFCOUNTER3_SELECT
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
+#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//PA_SC_PERFCOUNTER0_SELECT
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//PA_SC_PERFCOUNTER0_SELECT1
+#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//PA_SC_PERFCOUNTER1_SELECT
+#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+//PA_SC_PERFCOUNTER2_SELECT
+#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
+//PA_SC_PERFCOUNTER3_SELECT
+#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
+//PA_SC_PERFCOUNTER4_SELECT
+#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL
+//PA_SC_PERFCOUNTER5_SELECT
+#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL
+//PA_SC_PERFCOUNTER6_SELECT
+#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000003FFL
+//PA_SC_PERFCOUNTER7_SELECT
+#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000003FFL
+//SPI_PERFCOUNTER0_SELECT
+#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define SPI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define SPI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//SPI_PERFCOUNTER1_SELECT
+#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define SPI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define SPI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//SPI_PERFCOUNTER2_SELECT
+#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
+#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
+#define SPI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
+#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define SPI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//SPI_PERFCOUNTER3_SELECT
+#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
+#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18
+#define SPI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
+#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define SPI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//SPI_PERFCOUNTER0_SELECT1
+#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//SPI_PERFCOUNTER1_SELECT1
+#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
+#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//SPI_PERFCOUNTER2_SELECT1
+#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0
+#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
+#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18
+#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//SPI_PERFCOUNTER3_SELECT1
+#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0
+#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa
+#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18
+#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//SPI_PERFCOUNTER4_SELECT
+#define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000000FFL
+//SPI_PERFCOUNTER5_SELECT
+#define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000000FFL
+//SPI_PERFCOUNTER_BINS
+#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0
+#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4
+#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8
+#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc
+#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10
+#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14
+#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18
+#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c
+#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0x0000000FL
+#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0x000000F0L
+#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0x00000F00L
+#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0x0000F000L
+#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0x000F0000L
+#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0x00F00000L
+#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0x0F000000L
+#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xF0000000L
+//SQ_PERFCOUNTER0_SELECT
+#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
+#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK 0x0F000000L
+#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER1_SELECT
+#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
+#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK 0x0F000000L
+#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER2_SELECT
+#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
+#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK 0x0F000000L
+#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER3_SELECT
+#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
+#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK 0x0F000000L
+#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER4_SELECT
+#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
+#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK 0x0F000000L
+#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER5_SELECT
+#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
+#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK 0x0F000000L
+#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER6_SELECT
+#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
+#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK 0x0F000000L
+#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER7_SELECT
+#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
+#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK 0x0F000000L
+#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER8_SELECT
+#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
+#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK 0x0F000000L
+#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER9_SELECT
+#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
+#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK 0x0F000000L
+#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER10_SELECT
+#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
+#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK 0x0F000000L
+#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER11_SELECT
+#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
+#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK 0x0F000000L
+#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER12_SELECT
+#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
+#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK 0x0F000000L
+#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER13_SELECT
+#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
+#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK 0x0F000000L
+#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER14_SELECT
+#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
+#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK 0x0F000000L
+#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER15_SELECT
+#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
+#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK 0x0F000000L
+#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER_CTRL
+#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0
+#define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x1
+#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2
+#define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x3
+#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4
+#define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x5
+#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6
+#define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x8
+#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0xd
+#define SQ_PERFCOUNTER_CTRL__VMID_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x00000001L
+#define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x00000002L
+#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x00000004L
+#define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x00000008L
+#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x00000010L
+#define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x00000020L
+#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x00000040L
+#define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x00001F00L
+#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x00002000L
+#define SQ_PERFCOUNTER_CTRL__VMID_MASK_MASK 0xFFFF0000L
+//SQ_PERFCOUNTER_MASK
+#define SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT 0x0
+#define SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER_MASK__SH0_MASK_MASK 0x0000FFFFL
+#define SQ_PERFCOUNTER_MASK__SH1_MASK_MASK 0xFFFF0000L
+//SQ_PERFCOUNTER_CTRL2
+#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0
+#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x00000001L
+//SX_PERFCOUNTER0_SELECT
+#define SX_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define SX_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define SX_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define SX_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define SX_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define SX_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define SX_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define SX_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//SX_PERFCOUNTER1_SELECT
+#define SX_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define SX_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define SX_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define SX_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define SX_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define SX_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define SX_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define SX_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//SX_PERFCOUNTER2_SELECT
+#define SX_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define SX_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define SX_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
+#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define SX_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//SX_PERFCOUNTER3_SELECT
+#define SX_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define SX_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define SX_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
+#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define SX_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//SX_PERFCOUNTER0_SELECT1
+#define SX_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define SX_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define SX_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define SX_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define SX_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define SX_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define SX_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define SX_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//SX_PERFCOUNTER1_SELECT1
+#define SX_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define SX_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define SX_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
+#define SX_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define SX_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define SX_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define SX_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define SX_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//GDS_PERFCOUNTER0_SELECT
+#define GDS_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define GDS_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define GDS_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define GDS_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define GDS_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define GDS_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define GDS_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define GDS_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//GDS_PERFCOUNTER1_SELECT
+#define GDS_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define GDS_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define GDS_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define GDS_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define GDS_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define GDS_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define GDS_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define GDS_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//GDS_PERFCOUNTER2_SELECT
+#define GDS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define GDS_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
+#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define GDS_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
+#define GDS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define GDS_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
+#define GDS_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define GDS_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define GDS_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//GDS_PERFCOUNTER3_SELECT
+#define GDS_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define GDS_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
+#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define GDS_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18
+#define GDS_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define GDS_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
+#define GDS_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define GDS_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define GDS_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//GDS_PERFCOUNTER0_SELECT1
+#define GDS_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define GDS_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define GDS_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define GDS_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define GDS_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define GDS_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define GDS_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define GDS_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//TA_PERFCOUNTER0_SELECT
+#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL
+#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003FC00L
+#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//TA_PERFCOUNTER0_SELECT1
+#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000FFL
+#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003FC00L
+#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//TA_PERFCOUNTER1_SELECT
+#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL
+#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//TD_PERFCOUNTER0_SELECT
+#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL
+#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003FC00L
+#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//TD_PERFCOUNTER0_SELECT1
+#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000FFL
+#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003FC00L
+#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//TD_PERFCOUNTER1_SELECT
+#define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL
+#define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//TCP_PERFCOUNTER0_SELECT
+#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//TCP_PERFCOUNTER0_SELECT1
+#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//TCP_PERFCOUNTER1_SELECT
+#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//TCP_PERFCOUNTER1_SELECT1
+#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
+#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//TCP_PERFCOUNTER2_SELECT
+#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
+#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//TCP_PERFCOUNTER3_SELECT
+#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
+#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//TCC_PERFCOUNTER0_SELECT
+#define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//TCC_PERFCOUNTER0_SELECT1
+#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
+#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
+#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L
+#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L
+//TCC_PERFCOUNTER1_SELECT
+#define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//TCC_PERFCOUNTER1_SELECT1
+#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18
+#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c
+#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L
+#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L
+//TCC_PERFCOUNTER2_SELECT
+#define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
+#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//TCC_PERFCOUNTER3_SELECT
+#define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
+#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//TCA_PERFCOUNTER0_SELECT
+#define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//TCA_PERFCOUNTER0_SELECT1
+#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
+#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
+#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L
+#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L
+//TCA_PERFCOUNTER1_SELECT
+#define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//TCA_PERFCOUNTER1_SELECT1
+#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18
+#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c
+#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L
+#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L
+//TCA_PERFCOUNTER2_SELECT
+#define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
+#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//TCA_PERFCOUNTER3_SELECT
+#define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
+#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//CB_PERFCOUNTER_FILTER
+#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0
+#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1
+#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4
+#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5
+#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa
+#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb
+#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc
+#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd
+#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11
+#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12
+#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15
+#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16
+#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x00000001L
+#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0x0000000EL
+#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x00000010L
+#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x000003E0L
+#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x00000400L
+#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x00000800L
+#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x00001000L
+#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0x0000E000L
+#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x00020000L
+#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x001C0000L
+#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x00200000L
+#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0x00C00000L
+//CB_PERFCOUNTER0_SELECT
+#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL
+#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L
+#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//CB_PERFCOUNTER0_SELECT1
+#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL
+#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L
+#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//CB_PERFCOUNTER1_SELECT
+#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL
+#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//CB_PERFCOUNTER2_SELECT
+#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL
+#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//CB_PERFCOUNTER3_SELECT
+#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL
+#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//DB_PERFCOUNTER0_SELECT
+#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//DB_PERFCOUNTER0_SELECT1
+#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//DB_PERFCOUNTER1_SELECT
+#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//DB_PERFCOUNTER1_SELECT1
+#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
+#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//DB_PERFCOUNTER2_SELECT
+#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
+#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
+#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
+#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//DB_PERFCOUNTER3_SELECT
+#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
+#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18
+#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
+#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//RLC_SPM_PERFMON_CNTL
+#define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x0
+#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc
+#define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xe
+#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10
+#define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0x00000FFFL
+#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x00003000L
+#define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0x0000C000L
+#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xFFFF0000L
+//RLC_SPM_PERFMON_RING_BASE_LO
+#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0
+#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xFFFFFFFFL
+//RLC_SPM_PERFMON_RING_BASE_HI
+#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0
+#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10
+#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0x0000FFFFL
+#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xFFFF0000L
+//RLC_SPM_PERFMON_RING_SIZE
+#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0
+#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xFFFFFFFFL
+//RLC_SPM_PERFMON_SEGMENT_SIZE
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x8
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x1f
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0x000000FFL
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x00000700L
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0x0000F800L
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x001F0000L
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x03E00000L
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7C000000L
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000L
+//RLC_SPM_SE_MUXSEL_ADDR
+#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
+#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xFFFFFFFFL
+//RLC_SPM_SE_MUXSEL_DATA
+#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
+#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xFFFFFFFFL
+//RLC_SPM_CPG_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_CPC_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_CPF_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_CB_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_DB_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_PA_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_GDS_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_IA_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_SC_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_TCC_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_TCA_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_TCP_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_TA_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_TD_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_VGT_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_SPI_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_SQG_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_SX_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_GLOBAL_MUXSEL_ADDR
+#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
+#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xFFFFFFFFL
+//RLC_SPM_GLOBAL_MUXSEL_DATA
+#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
+#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xFFFFFFFFL
+//RLC_SPM_RING_RDPTR
+#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0
+#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xFFFFFFFFL
+//RLC_SPM_SEGMENT_THRESHOLD
+#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0
+#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0xFFFFFFFFL
+//RLC_SPM_RMI_PERFMON_SAMPLE_DELAY
+#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_PERFMON_SAMPLE_DELAY_MAX
+#define RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__PERFMON_MAX_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__RESERVED__SHIFT 0x8
+#define RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__PERFMON_MAX_SAMPLE_DELAY_MASK 0x000000FFL
+#define RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1
+#define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__PERFMON_SEGMENT_SIZE_CORE1__SHIFT 0x0
+#define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__RESERVED1__SHIFT 0x7
+#define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__SE4_NUM_LINE__SHIFT 0xc
+#define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__SE5_NUM_LINE__SHIFT 0x11
+#define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__SE6_NUM_LINE__SHIFT 0x16
+#define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__SE7_NUM_LINE__SHIFT 0x1b
+#define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__PERFMON_SEGMENT_SIZE_CORE1_MASK 0x0000007FL
+#define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__RESERVED1_MASK 0x00000F80L
+#define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__SE4_NUM_LINE_MASK 0x0001F000L
+#define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__SE5_NUM_LINE_MASK 0x003E0000L
+#define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__SE6_NUM_LINE_MASK 0x07C00000L
+#define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__SE7_NUM_LINE_MASK 0xF8000000L
+//RLC_PERFMON_CLK_CNTL_UCODE
+#define RLC_PERFMON_CLK_CNTL_UCODE__PERFMON_CLOCK_STATE__SHIFT 0x0
+#define RLC_PERFMON_CLK_CNTL_UCODE__PERFMON_CLOCK_STATE_MASK 0x00000001L
+//RLC_PERFMON_CLK_CNTL
+#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE__SHIFT 0x0
+#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK 0x00000001L
+//RLC_PERFMON_CNTL
+#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
+#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000007L
+#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L
+//RLC_PERFCOUNTER0_SELECT
+#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x00FFL
+//RLC_PERFCOUNTER1_SELECT
+#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x00FFL
+//RLC_GPU_IOV_PERF_CNT_CNTL
+#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE__SHIFT 0x0
+#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT__SHIFT 0x1
+#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET__SHIFT 0x2
+#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED__SHIFT 0x3
+#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE_MASK 0x00000001L
+#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT_MASK 0x00000002L
+#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET_MASK 0x00000004L
+#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED_MASK 0xFFFFFFF8L
+//RLC_GPU_IOV_PERF_CNT_WR_ADDR
+#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID__SHIFT 0x0
+#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID__SHIFT 0x4
+#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED__SHIFT 0x6
+#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID_MASK 0x0000000FL
+#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID_MASK 0x00000030L
+#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED_MASK 0xFFFFFFC0L
+//RLC_GPU_IOV_PERF_CNT_WR_DATA
+#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA__SHIFT 0x0
+#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA_MASK 0x0000000FL
+//RLC_GPU_IOV_PERF_CNT_RD_ADDR
+#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID__SHIFT 0x0
+#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID__SHIFT 0x4
+#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED__SHIFT 0x6
+#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID_MASK 0x0000000FL
+#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID_MASK 0x00000030L
+#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED_MASK 0xFFFFFFC0L
+//RLC_GPU_IOV_PERF_CNT_RD_DATA
+#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA__SHIFT 0x0
+#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA_MASK 0x0000000FL
+//RMI_PERFCOUNTER0_SELECT
+#define RMI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define RMI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define RMI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL
+#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L
+#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define RMI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//RMI_PERFCOUNTER0_SELECT1
+#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL
+#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L
+#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//RMI_PERFCOUNTER1_SELECT
+#define RMI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define RMI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define RMI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL
+#define RMI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//RMI_PERFCOUNTER2_SELECT
+#define RMI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
+#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
+#define RMI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define RMI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL
+#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x0007FC00L
+#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define RMI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//RMI_PERFCOUNTER2_SELECT1
+#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0
+#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
+#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18
+#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000001FFL
+#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x0007FC00L
+#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//RMI_PERFCOUNTER3_SELECT
+#define RMI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define RMI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define RMI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL
+#define RMI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//RMI_PERF_COUNTER_CNTL
+#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL__SHIFT 0x0
+#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL__SHIFT 0x2
+#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL__SHIFT 0x4
+#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0__SHIFT 0x6
+#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1__SHIFT 0x8
+#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT 0xa
+#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID__SHIFT 0xe
+#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD__SHIFT 0x13
+#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET__SHIFT 0x19
+#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL__SHIFT 0x1a
+#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL_MASK 0x00000003L
+#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL_MASK 0x0000000CL
+#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL_MASK 0x00000030L
+#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0_MASK 0x000000C0L
+#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1_MASK 0x00000300L
+#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID_MASK 0x00003C00L
+#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID_MASK 0x0007C000L
+#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD_MASK 0x01F80000L
+#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET_MASK 0x02000000L
+#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL_MASK 0x04000000L
+
+
+// addressBlock: gc_pwrdec
+//CGTS_SM_CTRL_REG
+#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0
+#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4
+#define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0xc
+#define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x10
+#define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x11
+#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14
+#define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x15
+#define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16
+#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x17
+#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x18
+#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0x0000000FL
+#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0x00000FF0L
+#define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x00001000L
+#define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x00010000L
+#define CGTS_SM_CTRL_REG__SM_MODE_MASK 0x000E0000L
+#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x00100000L
+#define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x00200000L
+#define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x00400000L
+#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x00800000L
+#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xFF000000L
+//CGTS_RD_CTRL_REG
+#define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x0
+#define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x8
+#define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x0000001FL
+#define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x00001F00L
+//CGTS_RD_REG
+#define CGTS_RD_REG__READ_DATA__SHIFT 0x0
+#define CGTS_RD_REG__READ_DATA_MASK 0x00003FFFL
+//CGTS_TCC_DISABLE
+#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10
+#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L
+//CGTS_USER_TCC_DISABLE
+#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10
+#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L
+//CGTS_TCC_DISABLE2
+#define CGTS_TCC_DISABLE2__TCC_DISABLE__SHIFT 0x10
+#define CGTS_TCC_DISABLE2__TCC_DISABLE_MASK 0xFFFF0000L
+//CGTS_USER_TCC_DISABLE2
+#define CGTS_USER_TCC_DISABLE2__TCC_DISABLE__SHIFT 0x10
+#define CGTS_USER_TCC_DISABLE2__TCC_DISABLE_MASK 0xFFFF0000L
+//CGTS_CU0_SP0_CTRL_REG
+#define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU0_SP0_CTRL_REG__SP00_MASK 0x0000007FL
+#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU0_SP0_CTRL_REG__SP01_MASK 0x007F0000L
+#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU0_LDS_SQ_CTRL_REG
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU0_TA_SQC_CTRL_REG
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU0_SP1_CTRL_REG
+#define CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU0_SP1_CTRL_REG__SP10_MASK 0x0000007FL
+#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU0_SP1_CTRL_REG__SP11_MASK 0x007F0000L
+#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU1_SP0_CTRL_REG
+#define CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU1_SP0_CTRL_REG__SP00_MASK 0x0000007FL
+#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU1_SP0_CTRL_REG__SP01_MASK 0x007F0000L
+#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU1_LDS_SQ_CTRL_REG
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU1_TA_SQC_CTRL_REG
+#define CGTS_CU1_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU1_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
+#define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+//CGTS_CU1_SP1_CTRL_REG
+#define CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU1_SP1_CTRL_REG__SP10_MASK 0x0000007FL
+#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU1_SP1_CTRL_REG__SP11_MASK 0x007F0000L
+#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU2_SP0_CTRL_REG
+#define CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU2_SP0_CTRL_REG__SP00_MASK 0x0000007FL
+#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU2_SP0_CTRL_REG__SP01_MASK 0x007F0000L
+#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU2_LDS_SQ_CTRL_REG
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU2_TA_SQC_CTRL_REG
+#define CGTS_CU2_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU2_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
+#define CGTS_CU2_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
+#define CGTS_CU2_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU2_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU2_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU2_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
+#define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU2_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
+#define CGTS_CU2_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU2_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU2_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU2_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU2_SP1_CTRL_REG
+#define CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU2_SP1_CTRL_REG__SP10_MASK 0x0000007FL
+#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU2_SP1_CTRL_REG__SP11_MASK 0x007F0000L
+#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU3_SP0_CTRL_REG
+#define CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU3_SP0_CTRL_REG__SP00_MASK 0x0000007FL
+#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU3_SP0_CTRL_REG__SP01_MASK 0x007F0000L
+#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU3_LDS_SQ_CTRL_REG
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU3_TA_SQC_CTRL_REG
+#define CGTS_CU3_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU3_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
+#define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+//CGTS_CU3_SP1_CTRL_REG
+#define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU3_SP1_CTRL_REG__SP10_MASK 0x0000007FL
+#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU3_SP1_CTRL_REG__SP11_MASK 0x007F0000L
+#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU4_SP0_CTRL_REG
+#define CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU4_SP0_CTRL_REG__SP00_MASK 0x0000007FL
+#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU4_SP0_CTRL_REG__SP01_MASK 0x007F0000L
+#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU4_LDS_SQ_CTRL_REG
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU4_TA_SQC_CTRL_REG
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU4_SP1_CTRL_REG
+#define CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU4_SP1_CTRL_REG__SP10_MASK 0x0000007FL
+#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU4_SP1_CTRL_REG__SP11_MASK 0x007F0000L
+#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU5_SP0_CTRL_REG
+#define CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU5_SP0_CTRL_REG__SP00_MASK 0x0000007FL
+#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x007F0000L
+#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU5_LDS_SQ_CTRL_REG
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU5_TA_SQC_CTRL_REG
+#define CGTS_CU5_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU5_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
+#define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+//CGTS_CU5_SP1_CTRL_REG
+#define CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU5_SP1_CTRL_REG__SP10_MASK 0x0000007FL
+#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU5_SP1_CTRL_REG__SP11_MASK 0x007F0000L
+#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU6_SP0_CTRL_REG
+#define CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU6_SP0_CTRL_REG__SP00_MASK 0x0000007FL
+#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU6_SP0_CTRL_REG__SP01_MASK 0x007F0000L
+#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU6_LDS_SQ_CTRL_REG
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU6_TA_SQC_CTRL_REG
+#define CGTS_CU6_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU6_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
+#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
+#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU6_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
+#define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
+#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU6_SP1_CTRL_REG
+#define CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU6_SP1_CTRL_REG__SP10_MASK 0x0000007FL
+#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU6_SP1_CTRL_REG__SP11_MASK 0x007F0000L
+#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU7_SP0_CTRL_REG
+#define CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU7_SP0_CTRL_REG__SP00_MASK 0x0000007FL
+#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU7_SP0_CTRL_REG__SP01_MASK 0x007F0000L
+#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU7_LDS_SQ_CTRL_REG
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU7_TA_SQC_CTRL_REG
+#define CGTS_CU7_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU7_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
+#define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+//CGTS_CU7_SP1_CTRL_REG
+#define CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU7_SP1_CTRL_REG__SP10_MASK 0x0000007FL
+#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU7_SP1_CTRL_REG__SP11_MASK 0x007F0000L
+#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU8_SP0_CTRL_REG
+#define CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU8_SP0_CTRL_REG__SP00_MASK 0x0000007FL
+#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU8_SP0_CTRL_REG__SP01_MASK 0x007F0000L
+#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU8_LDS_SQ_CTRL_REG
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU8_TA_SQC_CTRL_REG
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU8_SP1_CTRL_REG
+#define CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU8_SP1_CTRL_REG__SP10_MASK 0x0000007FL
+#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU8_SP1_CTRL_REG__SP11_MASK 0x007F0000L
+#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU9_SP0_CTRL_REG
+#define CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU9_SP0_CTRL_REG__SP00_MASK 0x0000007FL
+#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU9_SP0_CTRL_REG__SP01_MASK 0x007F0000L
+#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU9_LDS_SQ_CTRL_REG
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU9_TA_SQC_CTRL_REG
+#define CGTS_CU9_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU9_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
+#define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+//CGTS_CU9_SP1_CTRL_REG
+#define CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU9_SP1_CTRL_REG__SP10_MASK 0x0000007FL
+#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU9_SP1_CTRL_REG__SP11_MASK 0x007F0000L
+#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU10_SP0_CTRL_REG
+#define CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU10_SP0_CTRL_REG__SP00_MASK 0x0000007FL
+#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU10_SP0_CTRL_REG__SP01_MASK 0x007F0000L
+#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU10_LDS_SQ_CTRL_REG
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU10_TA_SQC_CTRL_REG
+#define CGTS_CU10_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU10_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
+#define CGTS_CU10_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
+#define CGTS_CU10_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU10_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU10_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU10_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
+#define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU10_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
+#define CGTS_CU10_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU10_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU10_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU10_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU10_SP1_CTRL_REG
+#define CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU10_SP1_CTRL_REG__SP10_MASK 0x0000007FL
+#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU10_SP1_CTRL_REG__SP11_MASK 0x007F0000L
+#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU11_SP0_CTRL_REG
+#define CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU11_SP0_CTRL_REG__SP00_MASK 0x0000007FL
+#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU11_SP0_CTRL_REG__SP01_MASK 0x007F0000L
+#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU11_LDS_SQ_CTRL_REG
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU11_TA_SQC_CTRL_REG
+#define CGTS_CU11_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU11_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
+#define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+//CGTS_CU11_SP1_CTRL_REG
+#define CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU11_SP1_CTRL_REG__SP10_MASK 0x0000007FL
+#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU11_SP1_CTRL_REG__SP11_MASK 0x007F0000L
+#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU12_SP0_CTRL_REG
+#define CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU12_SP0_CTRL_REG__SP00_MASK 0x0000007FL
+#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU12_SP0_CTRL_REG__SP01_MASK 0x007F0000L
+#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU12_LDS_SQ_CTRL_REG
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU12_TA_SQC_CTRL_REG
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU12_SP1_CTRL_REG
+#define CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU12_SP1_CTRL_REG__SP10_MASK 0x0000007FL
+#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU12_SP1_CTRL_REG__SP11_MASK 0x007F0000L
+#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU13_SP0_CTRL_REG
+#define CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU13_SP0_CTRL_REG__SP00_MASK 0x0000007FL
+#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU13_SP0_CTRL_REG__SP01_MASK 0x007F0000L
+#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU13_LDS_SQ_CTRL_REG
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU13_TA_SQC_CTRL_REG
+#define CGTS_CU13_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU13_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
+#define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+//CGTS_CU13_SP1_CTRL_REG
+#define CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU13_SP1_CTRL_REG__SP10_MASK 0x0000007FL
+#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU13_SP1_CTRL_REG__SP11_MASK 0x007F0000L
+#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU14_SP0_CTRL_REG
+#define CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU14_SP0_CTRL_REG__SP00_MASK 0x0000007FL
+#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU14_SP0_CTRL_REG__SP01_MASK 0x007F0000L
+#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU14_LDS_SQ_CTRL_REG
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU14_TA_SQC_CTRL_REG
+#define CGTS_CU14_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU14_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
+#define CGTS_CU14_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
+#define CGTS_CU14_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU14_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU14_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU14_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
+#define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU14_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
+#define CGTS_CU14_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU14_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU14_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU14_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU14_SP1_CTRL_REG
+#define CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU14_SP1_CTRL_REG__SP10_MASK 0x0000007FL
+#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU14_SP1_CTRL_REG__SP11_MASK 0x007F0000L
+#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU15_SP0_CTRL_REG
+#define CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU15_SP0_CTRL_REG__SP00_MASK 0x0000007FL
+#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU15_SP0_CTRL_REG__SP01_MASK 0x007F0000L
+#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU15_LDS_SQ_CTRL_REG
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU15_TA_SQC_CTRL_REG
+#define CGTS_CU15_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU15_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
+#define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+//CGTS_CU15_SP1_CTRL_REG
+#define CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU15_SP1_CTRL_REG__SP10_MASK 0x0000007FL
+#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU15_SP1_CTRL_REG__SP11_MASK 0x007F0000L
+#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
+#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
+#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
+#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
+//CGTS_CU0_TCPI_CTRL_REG
+#define CGTS_CU0_TCPI_CTRL_REG__TCPI__SHIFT 0x0
+#define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
+#define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU0_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
+#define CGTS_CU0_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
+#define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU0_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
+//CGTS_CU1_TCPI_CTRL_REG
+#define CGTS_CU1_TCPI_CTRL_REG__TCPI__SHIFT 0x0
+#define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
+#define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU1_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
+#define CGTS_CU1_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
+#define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU1_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
+//CGTS_CU2_TCPI_CTRL_REG
+#define CGTS_CU2_TCPI_CTRL_REG__TCPI__SHIFT 0x0
+#define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
+#define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU2_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
+#define CGTS_CU2_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
+#define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU2_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
+//CGTS_CU3_TCPI_CTRL_REG
+#define CGTS_CU3_TCPI_CTRL_REG__TCPI__SHIFT 0x0
+#define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
+#define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU3_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
+#define CGTS_CU3_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
+#define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU3_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
+//CGTS_CU4_TCPI_CTRL_REG
+#define CGTS_CU4_TCPI_CTRL_REG__TCPI__SHIFT 0x0
+#define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
+#define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU4_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
+#define CGTS_CU4_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
+#define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU4_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
+//CGTS_CU5_TCPI_CTRL_REG
+#define CGTS_CU5_TCPI_CTRL_REG__TCPI__SHIFT 0x0
+#define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
+#define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU5_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
+#define CGTS_CU5_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
+#define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU5_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
+//CGTS_CU6_TCPI_CTRL_REG
+#define CGTS_CU6_TCPI_CTRL_REG__TCPI__SHIFT 0x0
+#define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
+#define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU6_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
+#define CGTS_CU6_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
+#define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU6_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
+//CGTS_CU7_TCPI_CTRL_REG
+#define CGTS_CU7_TCPI_CTRL_REG__TCPI__SHIFT 0x0
+#define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
+#define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU7_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
+#define CGTS_CU7_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
+#define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU7_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
+//CGTS_CU8_TCPI_CTRL_REG
+#define CGTS_CU8_TCPI_CTRL_REG__TCPI__SHIFT 0x0
+#define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
+#define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU8_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
+#define CGTS_CU8_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
+#define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU8_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
+//CGTS_CU9_TCPI_CTRL_REG
+#define CGTS_CU9_TCPI_CTRL_REG__TCPI__SHIFT 0x0
+#define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
+#define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU9_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
+#define CGTS_CU9_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
+#define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU9_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
+//CGTS_CU10_TCPI_CTRL_REG
+#define CGTS_CU10_TCPI_CTRL_REG__TCPI__SHIFT 0x0
+#define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
+#define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU10_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
+#define CGTS_CU10_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
+#define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU10_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
+//CGTS_CU11_TCPI_CTRL_REG
+#define CGTS_CU11_TCPI_CTRL_REG__TCPI__SHIFT 0x0
+#define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
+#define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU11_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
+#define CGTS_CU11_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
+#define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU11_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
+//CGTS_CU12_TCPI_CTRL_REG
+#define CGTS_CU12_TCPI_CTRL_REG__TCPI__SHIFT 0x0
+#define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
+#define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU12_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
+#define CGTS_CU12_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
+#define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU12_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
+//CGTS_CU13_TCPI_CTRL_REG
+#define CGTS_CU13_TCPI_CTRL_REG__TCPI__SHIFT 0x0
+#define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
+#define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU13_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
+#define CGTS_CU13_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
+#define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU13_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
+//CGTS_CU14_TCPI_CTRL_REG
+#define CGTS_CU14_TCPI_CTRL_REG__TCPI__SHIFT 0x0
+#define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
+#define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU14_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
+#define CGTS_CU14_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
+#define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU14_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
+//CGTS_CU15_TCPI_CTRL_REG
+#define CGTS_CU15_TCPI_CTRL_REG__TCPI__SHIFT 0x0
+#define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
+#define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU15_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
+#define CGTS_CU15_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
+#define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
+#define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
+#define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
+#define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
+#define CGTS_CU15_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
+//CGTT_SPI_PS_CLK_CTRL
+#define CGTT_SPI_PS_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_SPI_PS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x10
+#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x11
+#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x12
+#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x13
+#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x14
+#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x15
+#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x16
+#define CGTT_SPI_PS_CLK_CTRL__GRP6_OVERRIDE__SHIFT 0x18
+#define CGTT_SPI_PS_CLK_CTRL__GRP5_OVERRIDE__SHIFT 0x19
+#define CGTT_SPI_PS_CLK_CTRL__GRP4_OVERRIDE__SHIFT 0x1a
+#define CGTT_SPI_PS_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b
+#define CGTT_SPI_PS_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c
+#define CGTT_SPI_PS_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d
+#define CGTT_SPI_PS_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e
+#define CGTT_SPI_PS_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_SPI_PS_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_SPI_PS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00010000L
+#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00020000L
+#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00040000L
+#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00080000L
+#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00100000L
+#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00200000L
+#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00400000L
+#define CGTT_SPI_PS_CLK_CTRL__GRP6_OVERRIDE_MASK 0x01000000L
+#define CGTT_SPI_PS_CLK_CTRL__GRP5_OVERRIDE_MASK 0x02000000L
+#define CGTT_SPI_PS_CLK_CTRL__GRP4_OVERRIDE_MASK 0x04000000L
+#define CGTT_SPI_PS_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L
+#define CGTT_SPI_PS_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L
+#define CGTT_SPI_PS_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L
+#define CGTT_SPI_PS_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L
+#define CGTT_SPI_PS_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
+//CGTT_SPIS_CLK_CTRL
+#define CGTT_SPIS_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_SPIS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x10
+#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x11
+#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x12
+#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x13
+#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x14
+#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x15
+#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x16
+#define CGTT_SPIS_CLK_CTRL__GRP6_OVERRIDE__SHIFT 0x18
+#define CGTT_SPIS_CLK_CTRL__GRP5_OVERRIDE__SHIFT 0x19
+#define CGTT_SPIS_CLK_CTRL__GRP4_OVERRIDE__SHIFT 0x1a
+#define CGTT_SPIS_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b
+#define CGTT_SPIS_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c
+#define CGTT_SPIS_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d
+#define CGTT_SPIS_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e
+#define CGTT_SPIS_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_SPIS_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_SPIS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00010000L
+#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00020000L
+#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00040000L
+#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00080000L
+#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00100000L
+#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00200000L
+#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00400000L
+#define CGTT_SPIS_CLK_CTRL__GRP6_OVERRIDE_MASK 0x01000000L
+#define CGTT_SPIS_CLK_CTRL__GRP5_OVERRIDE_MASK 0x02000000L
+#define CGTT_SPIS_CLK_CTRL__GRP4_OVERRIDE_MASK 0x04000000L
+#define CGTT_SPIS_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L
+#define CGTT_SPIS_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L
+#define CGTT_SPIS_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L
+#define CGTT_SPIS_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L
+#define CGTT_SPIS_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
+//CGTT_SPI_CLK_CTRL
+#define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x14
+#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x15
+#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x16
+#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c
+#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d
+#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e
+#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00100000L
+#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00200000L
+#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00400000L
+#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L
+#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L
+#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L
+#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
+//CGTT_PC_CLK_CTRL
+#define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_PC_CLK_CTRL__PC_RAM_FGCG_OVERRIDE__SHIFT 0x11
+#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12
+#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18
+#define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE__SHIFT 0x19
+#define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE__SHIFT 0x1a
+#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b
+#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c
+#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d
+#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e
+#define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_PC_CLK_CTRL__PC_RAM_FGCG_OVERRIDE_MASK 0x00020000L
+#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00FC0000L
+#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L
+#define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE_MASK 0x02000000L
+#define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE_MASK 0x04000000L
+#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L
+#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L
+#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L
+#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L
+#define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
+//CGTT_BCI_CLK_CTRL
+#define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0xc
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x18
+#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x19
+#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x1a
+#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b
+#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c
+#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d
+#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e
+#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0x0000F000L
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x01000000L
+#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x02000000L
+#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x04000000L
+#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L
+#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L
+#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L
+#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L
+#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
+//CGTT_PA_CLK_CTRL
+#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d
+#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e
+#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x1f
+#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000L
+#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000L
+#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000L
+//CGTT_SC_CLK_CTRL0
+#define CGTT_SC_CLK_CTRL0__ON_DELAY__SHIFT 0x0
+#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE__SHIFT 0x10
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x11
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x12
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x13
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x14
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x15
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x16
+#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE__SHIFT 0x17
+#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE__SHIFT 0x18
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x19
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1a
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1b
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1c
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1d
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1e
+#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT 0x1f
+#define CGTT_SC_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL
+#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE_MASK 0x00010000L
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00020000L
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00040000L
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00080000L
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00100000L
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00200000L
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00400000L
+#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE_MASK 0x00800000L
+#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE_MASK 0x01000000L
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x02000000L
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x04000000L
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x08000000L
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x10000000L
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x20000000L
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x40000000L
+#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE_MASK 0x80000000L
+//CGTT_SC_CLK_CTRL1
+#define CGTT_SC_CLK_CTRL1__ON_DELAY__SHIFT 0x0
+#define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE__SHIFT 0x11
+#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE__SHIFT 0x12
+#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE__SHIFT 0x13
+#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE__SHIFT 0x14
+#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE__SHIFT 0x15
+#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE__SHIFT 0x16
+#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE__SHIFT 0x19
+#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE__SHIFT 0x1a
+#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE__SHIFT 0x1b
+#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE__SHIFT 0x1c
+#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE__SHIFT 0x1d
+#define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE__SHIFT 0x1e
+#define CGTT_SC_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL
+#define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE_MASK 0x00020000L
+#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE_MASK 0x00040000L
+#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE_MASK 0x00080000L
+#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE_MASK 0x00100000L
+#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE_MASK 0x00200000L
+#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE_MASK 0x00400000L
+#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE_MASK 0x02000000L
+#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE_MASK 0x04000000L
+#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE_MASK 0x08000000L
+#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE_MASK 0x10000000L
+#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE_MASK 0x20000000L
+#define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE_MASK 0x40000000L
+//CGTT_SC_CLK_CTRL2
+#define CGTT_SC_CLK_CTRL2__ON_DELAY__SHIFT 0x0
+#define CGTT_SC_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SC_CLK_CTRL2__SCF_SCB_INTF_CLK_OVERRIDE__SHIFT 0x1b
+#define CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE__SHIFT 0x1c
+#define CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE__SHIFT 0x1d
+#define CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE__SHIFT 0x1e
+#define CGTT_SC_CLK_CTRL2__ON_DELAY_MASK 0x0000000FL
+#define CGTT_SC_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_SC_CLK_CTRL2__SCF_SCB_INTF_CLK_OVERRIDE_MASK 0x08000000L
+#define CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE_MASK 0x10000000L
+#define CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE_MASK 0x20000000L
+#define CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE_MASK 0x40000000L
+//CGTT_SQG_CLK_CTRL
+#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT 0x1c
+#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d
+#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
+#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK 0x10000000L
+#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L
+#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L
+#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
+//SQ_ALU_CLK_CTRL
+#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
+#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
+#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL
+#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L
+//SQ_TEX_CLK_CTRL
+#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
+#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
+#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL
+#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L
+//SQ_LDS_CLK_CTRL
+#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
+#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
+#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL
+#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L
+//SQ_POWER_THROTTLE
+#define SQ_POWER_THROTTLE__MIN_POWER__SHIFT 0x0
+#define SQ_POWER_THROTTLE__MAX_POWER__SHIFT 0x10
+#define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT 0x1e
+#define SQ_POWER_THROTTLE__MIN_POWER_MASK 0x00003FFFL
+#define SQ_POWER_THROTTLE__MAX_POWER_MASK 0x3FFF0000L
+#define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK 0xC0000000L
+//SQ_POWER_THROTTLE2
+#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT 0x0
+#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
+#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
+#define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT 0x1f
+#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK 0x00003FFFL
+#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
+#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
+#define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK 0x80000000L
+//CGTT_SX_CLK_CTRL0
+#define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x0
+#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0xc
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL
+#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0x0000F000L
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L
+//CGTT_SX_CLK_CTRL1
+#define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x0
+#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0xc
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL
+#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0x0000F000L
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000L
+//CGTT_SX_CLK_CTRL2
+#define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x0
+#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0xd
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0x0000000FL
+#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0x0000E000L
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000L
+//CGTT_SX_CLK_CTRL3
+#define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x0
+#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0xd
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0x0000000FL
+#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0x0000E000L
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000L
+//CGTT_SX_CLK_CTRL4
+#define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x0
+#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0xc
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0x0000000FL
+#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0x0000F000L
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000L
+//TD_CGTT_CTRL
+#define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x0
+#define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define TD_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL
+#define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//TA_CGTT_CTRL
+#define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x0
+#define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define TA_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL
+#define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//CGTT_TCI_CLK_CTRL
+#define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_TCI_CLK_CTRL__SPARE__SHIFT 0xc
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_TCI_CLK_CTRL__SPARE_MASK 0x0000F000L
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//CGTT_GDS_CLK_CTRL
+#define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//CGTT_TCP_TCR_CLK_CTRL
+#define CGTT_TCP_TCR_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_TCP_TCR_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_TCP_TCR_CLK_CTRL__SPARE__SHIFT 0xc
+#define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_TCP_TCR_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_TCP_TCR_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_TCP_TCR_CLK_CTRL__SPARE_MASK 0x0000F000L
+#define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//CGTT_TCI_TCR_CLK_CTRL
+#define CGTT_TCI_TCR_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_TCI_TCR_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_TCI_TCR_CLK_CTRL__SPARE__SHIFT 0xc
+#define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_TCI_TCR_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_TCI_TCR_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_TCI_TCR_CLK_CTRL__SPARE_MASK 0x0000F000L
+#define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//TCX_CGTT_SCLK_CTRL
+#define TCX_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define TCX_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+//DB_CGTT_CLK_CTRL_0
+#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0
+#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4
+#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f
+#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0x0000000FL
+#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0x0000F000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x01000000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x02000000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x04000000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x08000000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000L
+//CB_CGTT_SCLK_CTRL
+#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//TCC_CGTT_SCLK_CTRL
+#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//TCC_CGTT_SCLK_CTRL2
+#define TCC_CGTT_SCLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4
+#define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b
+#define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c
+#define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d
+#define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e
+#define TCC_CGTT_SCLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE4_MASK 0x08000000L
+#define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000L
+#define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000L
+#define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000L
+//TCC_CGTT_SCLK_CTRL3
+#define TCC_CGTT_SCLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE18__SHIFT 0xc
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE17__SHIFT 0xd
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE16__SHIFT 0xe
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE15__SHIFT 0xf
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE14__SHIFT 0x10
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE13__SHIFT 0x11
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE12__SHIFT 0x12
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE11__SHIFT 0x13
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE10__SHIFT 0x14
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE9__SHIFT 0x15
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE8__SHIFT 0x17
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE7__SHIFT 0x18
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e
+#define TCC_CGTT_SCLK_CTRL3__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE18_MASK 0x00001000L
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE17_MASK 0x00002000L
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE16_MASK 0x00004000L
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE15_MASK 0x00008000L
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE14_MASK 0x00010000L
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE13_MASK 0x00020000L
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE12_MASK 0x00040000L
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE11_MASK 0x00080000L
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE10_MASK 0x00100000L
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE9_MASK 0x00200000L
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE8_MASK 0x00800000L
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE7_MASK 0x01000000L
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE6_MASK 0x02000000L
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE5_MASK 0x04000000L
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE4_MASK 0x08000000L
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000L
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000L
+#define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000L
+//TCA_CGTT_SCLK_CTRL
+#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//CGTT_CP_CLK_CTRL
+#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
+#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
+#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
+#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L
+#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
+#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
+//CGTT_CPF_CLK_CTRL
+#define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
+#define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
+//CGTT_CPC_CLK_CTRL
+#define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
+#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
+#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
+#define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L
+#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
+#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
+//CGTT_RLC_CLK_CTRL
+#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
+#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
+#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
+#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
+//RLC_GFX_RM_CNTL
+#define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID__SHIFT 0x0
+#define RLC_GFX_RM_CNTL__RESERVED__SHIFT 0x1
+#define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID_MASK 0x00000001L
+#define RLC_GFX_RM_CNTL__RESERVED_MASK 0xFFFFFFFEL
+//RMI_CGTT_SCLK_CTRL
+#define RMI_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
+#define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define RMI_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//SE_CAC_CGTT_CLK_CTRL
+#define SE_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DIDT_REG__SHIFT 0x1d
+#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
+#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
+#define SE_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DIDT_REG_MASK 0x20000000L
+#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
+#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
+//GC_CAC_CGTT_CLK_CTRL
+#define GC_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
+#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
+#define GC_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
+#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
+//GRBM_CGTT_CLK_CNTL
+#define GRBM_CGTT_CLK_CNTL__ON_DELAY__SHIFT 0x0
+#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS__SHIFT 0x4
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
+#define GRBM_CGTT_CLK_CNTL__ON_DELAY_MASK 0x0000000FL
+#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
+
+
+// addressBlock: gc_rbdec
+//DB_DEBUG
+#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0
+#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1
+#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2
+#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3
+#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4
+#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6
+#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7
+#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8
+#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa
+#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc
+#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe
+#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf
+#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10
+#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11
+#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12
+#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13
+#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15
+#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16
+#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17
+#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18
+#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c
+#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d
+#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e
+#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f
+#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x00000001L
+#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x00000002L
+#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x00000004L
+#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x00000008L
+#define DB_DEBUG__FORCE_Z_MODE_MASK 0x00000030L
+#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x00000040L
+#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x00000080L
+#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x00000300L
+#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0x00000C00L
+#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x00003000L
+#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x00004000L
+#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x00008000L
+#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x00010000L
+#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x00020000L
+#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x00040000L
+#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x00180000L
+#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x00200000L
+#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x00400000L
+#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x00800000L
+#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0x0F000000L
+#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000L
+#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000L
+#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000L
+#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000L
+//DB_DEBUG2
+#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0
+#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1
+#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2
+#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3
+#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4
+#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL__SHIFT 0x5
+#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ__SHIFT 0x6
+#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL__SHIFT 0x7
+#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE__SHIFT 0x8
+#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9
+#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe
+#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0xf
+#define DB_DEBUG2__RESERVED__SHIFT 0x10
+#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11
+#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12
+#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13
+#define DB_DEBUG2__DISABLE_VR_OBJ_PRIM_ID__SHIFT 0x1a
+#define DB_DEBUG2__DISABLE_VR_PS_INVOKE__SHIFT 0x1b
+#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c
+#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d
+#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e
+#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f
+#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x00000001L
+#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x00000002L
+#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x00000004L
+#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x00000008L
+#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x00000010L
+#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_MASK 0x00000020L
+#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ_MASK 0x00000040L
+#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL_MASK 0x00000080L
+#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE_MASK 0x00000100L
+#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x00003E00L
+#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x00004000L
+#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x00008000L
+#define DB_DEBUG2__RESERVED_MASK 0x00010000L
+#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x00020000L
+#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x00040000L
+#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x00080000L
+#define DB_DEBUG2__DISABLE_VR_OBJ_PRIM_ID_MASK 0x04000000L
+#define DB_DEBUG2__DISABLE_VR_PS_INVOKE_MASK 0x08000000L
+#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000L
+#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000L
+#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000L
+#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000L
+//DB_DEBUG3
+#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION__SHIFT 0x0
+#define DB_DEBUG3__ROUND_ZRANGE_CORRECTION__SHIFT 0x1
+#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2
+#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3
+#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4
+#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5
+#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6
+#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7
+#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8
+#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9
+#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa
+#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb
+#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc
+#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd
+#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe
+#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf
+#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x10
+#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11
+#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12
+#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13
+#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14
+#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15
+#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16
+#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17
+#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18
+#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19
+#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a
+#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b
+#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c
+#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d
+#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE__SHIFT 0x1e
+#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK__SHIFT 0x1f
+#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION_MASK 0x00000001L
+#define DB_DEBUG3__ROUND_ZRANGE_CORRECTION_MASK 0x00000002L
+#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x00000004L
+#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x00000008L
+#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x00000010L
+#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x00000020L
+#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x00000040L
+#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x00000080L
+#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x00000100L
+#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x00000200L
+#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x00000400L
+#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x00000800L
+#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x00001000L
+#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x00002000L
+#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x00004000L
+#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x00008000L
+#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x00010000L
+#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x00020000L
+#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x00040000L
+#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x00080000L
+#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x00100000L
+#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x00200000L
+#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x00400000L
+#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x00800000L
+#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x01000000L
+#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x02000000L
+#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x04000000L
+#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x08000000L
+#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000L
+#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000L
+#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE_MASK 0x40000000L
+#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK_MASK 0x80000000L
+//DB_DEBUG4
+#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0
+#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1
+#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2
+#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3
+#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF__SHIFT 0x4
+#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT 0x5
+#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT 0x6
+#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN__SHIFT 0x7
+#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS__SHIFT 0x8
+#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR__SHIFT 0x9
+#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT 0xa
+#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR__SHIFT 0xb
+#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK__SHIFT 0xc
+#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP__SHIFT 0xd
+#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION__SHIFT 0xe
+#define DB_DEBUG4__DISABLE_TS_WRITE_L0__SHIFT 0xf
+#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE__SHIFT 0x10
+#define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT__SHIFT 0x11
+#define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT__SHIFT 0x12
+#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x13
+#define DB_DEBUG4__DISABLE_8PPC_OBJPRIMID_WHEN_NO_SHADER_EXPORTS__SHIFT 0x1e
+#define DB_DEBUG4__FULL_TILE_CACHE_EVICT_ON_HALF_FULL__SHIFT 0x1f
+#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x00000001L
+#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x00000002L
+#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x00000004L
+#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x00000008L
+#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF_MASK 0x00000010L
+#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK 0x00000020L
+#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK 0x00000040L
+#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN_MASK 0x00000080L
+#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS_MASK 0x00000100L
+#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR_MASK 0x00000200L
+#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR_MASK 0x00000400L
+#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR_MASK 0x00000800L
+#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK_MASK 0x00001000L
+#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP_MASK 0x00002000L
+#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION_MASK 0x00004000L
+#define DB_DEBUG4__DISABLE_TS_WRITE_L0_MASK 0x00008000L
+#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE_MASK 0x00010000L
+#define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT_MASK 0x00020000L
+#define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT_MASK 0x00040000L
+#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0x3FF80000L
+#define DB_DEBUG4__DISABLE_8PPC_OBJPRIMID_WHEN_NO_SHADER_EXPORTS_MASK 0x40000000L
+#define DB_DEBUG4__FULL_TILE_CACHE_EVICT_ON_HALF_FULL_MASK 0x80000000L
+//DB_CREDIT_LIMIT
+#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0
+#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5
+#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa
+#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18
+#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x0000001FL
+#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x000003E0L
+#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x00001C00L
+#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7F000000L
+//DB_WATERMARKS
+#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0
+#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x5
+#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0xb
+#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0xf
+#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x14
+#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x1e
+#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x1f
+#define DB_WATERMARKS__DEPTH_FREE_MASK 0x0000001FL
+#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x000007E0L
+#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x00007800L
+#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0x000F8000L
+#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x0FF00000L
+#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000L
+#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000L
+//DB_SUBTILE_CONTROL
+#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0
+#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2
+#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4
+#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6
+#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8
+#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa
+#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc
+#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe
+#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10
+#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12
+#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x00000003L
+#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0x0000000CL
+#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x00000030L
+#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0x000000C0L
+#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x00000300L
+#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0x00000C00L
+#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x00003000L
+#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0x0000C000L
+#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x00030000L
+#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0x000C0000L
+//DB_FREE_CACHELINES
+#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0
+#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x7
+#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0xe
+#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x14
+#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x18
+#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x0000007FL
+#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x00003F80L
+#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x000FC000L
+#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x00F00000L
+#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xFF000000L
+//DB_FIFO_DEPTH1
+#define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS__SHIFT 0x0
+#define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS__SHIFT 0x5
+#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa
+#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x10
+#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x15
+#define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS_MASK 0x0000001FL
+#define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS_MASK 0x000003E0L
+#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0x0000FC00L
+#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x001F0000L
+#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1FE00000L
+//DB_FIFO_DEPTH2
+#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0
+#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8
+#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0xf
+#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19
+#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0x000000FFL
+#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x00007F00L
+#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x01FF8000L
+#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xFE000000L
+//DB_EXCEPTION_CONTROL
+#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE__SHIFT 0x0
+#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE__SHIFT 0x1
+#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE__SHIFT 0x2
+#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE_MASK 0x00000001L
+#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE_MASK 0x00000002L
+#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE_MASK 0x00000004L
+//DB_RING_CONTROL
+#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0
+#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x00000003L
+//DB_MEM_ARB_WATERMARKS
+#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK__SHIFT 0x0
+#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK__SHIFT 0x8
+#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK__SHIFT 0x10
+#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK__SHIFT 0x18
+#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK_MASK 0x00000007L
+#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK_MASK 0x00000700L
+#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK_MASK 0x00070000L
+#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK_MASK 0x07000000L
+//DB_RMI_CACHE_POLICY
+#define DB_RMI_CACHE_POLICY__Z_RD__SHIFT 0x0
+#define DB_RMI_CACHE_POLICY__S_RD__SHIFT 0x1
+#define DB_RMI_CACHE_POLICY__HTILE_RD__SHIFT 0x2
+#define DB_RMI_CACHE_POLICY__Z_WR__SHIFT 0x8
+#define DB_RMI_CACHE_POLICY__S_WR__SHIFT 0x9
+#define DB_RMI_CACHE_POLICY__HTILE_WR__SHIFT 0xa
+#define DB_RMI_CACHE_POLICY__ZPCPSD_WR__SHIFT 0xb
+#define DB_RMI_CACHE_POLICY__CC_RD__SHIFT 0x10
+#define DB_RMI_CACHE_POLICY__FMASK_RD__SHIFT 0x11
+#define DB_RMI_CACHE_POLICY__CMASK_RD__SHIFT 0x12
+#define DB_RMI_CACHE_POLICY__DCC_RD__SHIFT 0x13
+#define DB_RMI_CACHE_POLICY__CC_WR__SHIFT 0x18
+#define DB_RMI_CACHE_POLICY__FMASK_WR__SHIFT 0x19
+#define DB_RMI_CACHE_POLICY__CMASK_WR__SHIFT 0x1a
+#define DB_RMI_CACHE_POLICY__DCC_WR__SHIFT 0x1b
+#define DB_RMI_CACHE_POLICY__Z_RD_MASK 0x00000001L
+#define DB_RMI_CACHE_POLICY__S_RD_MASK 0x00000002L
+#define DB_RMI_CACHE_POLICY__HTILE_RD_MASK 0x00000004L
+#define DB_RMI_CACHE_POLICY__Z_WR_MASK 0x00000100L
+#define DB_RMI_CACHE_POLICY__S_WR_MASK 0x00000200L
+#define DB_RMI_CACHE_POLICY__HTILE_WR_MASK 0x00000400L
+#define DB_RMI_CACHE_POLICY__ZPCPSD_WR_MASK 0x00000800L
+#define DB_RMI_CACHE_POLICY__CC_RD_MASK 0x00010000L
+#define DB_RMI_CACHE_POLICY__FMASK_RD_MASK 0x00020000L
+#define DB_RMI_CACHE_POLICY__CMASK_RD_MASK 0x00040000L
+#define DB_RMI_CACHE_POLICY__DCC_RD_MASK 0x00080000L
+#define DB_RMI_CACHE_POLICY__CC_WR_MASK 0x01000000L
+#define DB_RMI_CACHE_POLICY__FMASK_WR_MASK 0x02000000L
+#define DB_RMI_CACHE_POLICY__CMASK_WR_MASK 0x04000000L
+#define DB_RMI_CACHE_POLICY__DCC_WR_MASK 0x08000000L
+//DB_DFSM_CONFIG
+#define DB_DFSM_CONFIG__BYPASS_DFSM__SHIFT 0x0
+#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT__SHIFT 0x1
+#define DB_DFSM_CONFIG__DISABLE_POPS__SHIFT 0x2
+#define DB_DFSM_CONFIG__FORCE_FLUSH__SHIFT 0x3
+#define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH__SHIFT 0x8
+#define DB_DFSM_CONFIG__BYPASS_DFSM_MASK 0x00000001L
+#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT_MASK 0x00000002L
+#define DB_DFSM_CONFIG__DISABLE_POPS_MASK 0x00000004L
+#define DB_DFSM_CONFIG__FORCE_FLUSH_MASK 0x00000008L
+#define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH_MASK 0x00007F00L
+//DB_DFSM_WATERMARK
+#define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK__SHIFT 0x0
+#define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK__SHIFT 0x10
+#define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK_MASK 0x0000FFFFL
+#define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK_MASK 0xFFFF0000L
+//DB_DFSM_TILES_IN_FLIGHT
+#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0
+#define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT__SHIFT 0x10
+#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL
+#define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT_MASK 0xFFFF0000L
+//DB_DFSM_PRIMS_IN_FLIGHT
+#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0
+#define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT__SHIFT 0x10
+#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL
+#define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT_MASK 0xFFFF0000L
+//DB_DFSM_WATCHDOG
+#define DB_DFSM_WATCHDOG__TIMER_TARGET__SHIFT 0x0
+#define DB_DFSM_WATCHDOG__TIMER_TARGET_MASK 0xFFFFFFFFL
+//DB_DFSM_FLUSH_ENABLE
+#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS__SHIFT 0x0
+#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU__SHIFT 0x18
+#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS__SHIFT 0x1c
+#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS_MASK 0x000003FFL
+#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU_MASK 0x0F000000L
+#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS_MASK 0xF0000000L
+//DB_DFSM_FLUSH_AUX_EVENT
+#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A__SHIFT 0x0
+#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B__SHIFT 0x8
+#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C__SHIFT 0x10
+#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D__SHIFT 0x18
+#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A_MASK 0x000000FFL
+#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B_MASK 0x0000FF00L
+#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C_MASK 0x00FF0000L
+#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D_MASK 0xFF000000L
+//CC_RB_REDUNDANCY
+#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
+#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
+#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
+#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
+#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L
+#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L
+#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L
+#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L
+//CC_RB_BACKEND_DISABLE
+#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
+#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L
+//GB_ADDR_CONFIG
+#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6
+#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
+#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
+#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15
+#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a
+#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+#define GB_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f
+#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
+#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
+#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
+#define GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
+#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
+#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
+#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L
+#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
+#define GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L
+#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
+#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
+#define GB_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L
+//GB_BACKEND_MAP
+#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0
+#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xFFFFFFFFL
+//GB_GPU_ID
+#define GB_GPU_ID__GPU_ID__SHIFT 0x0
+#define GB_GPU_ID__GPU_ID_MASK 0x0000000FL
+//CC_RB_DAISY_CHAIN
+#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0
+#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4
+#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8
+#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc
+#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10
+#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14
+#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18
+#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c
+#define CC_RB_DAISY_CHAIN__RB_0_MASK 0x0000000FL
+#define CC_RB_DAISY_CHAIN__RB_1_MASK 0x000000F0L
+#define CC_RB_DAISY_CHAIN__RB_2_MASK 0x00000F00L
+#define CC_RB_DAISY_CHAIN__RB_3_MASK 0x0000F000L
+#define CC_RB_DAISY_CHAIN__RB_4_MASK 0x000F0000L
+#define CC_RB_DAISY_CHAIN__RB_5_MASK 0x00F00000L
+#define CC_RB_DAISY_CHAIN__RB_6_MASK 0x0F000000L
+#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xF0000000L
+//GB_ADDR_CONFIG_READ
+#define GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0
+#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6
+#define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc
+#define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13
+#define GB_ADDR_CONFIG_READ__NUM_GPUS__SHIFT 0x15
+#define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a
+#define GB_ADDR_CONFIG_READ__ROW_SIZE__SHIFT 0x1c
+#define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES__SHIFT 0x1e
+#define GB_ADDR_CONFIG_READ__SE_ENABLE__SHIFT 0x1f
+#define GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L
+#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
+#define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
+#define GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L
+#define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
+#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L
+#define GB_ADDR_CONFIG_READ__NUM_GPUS_MASK 0x00E00000L
+#define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
+#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L
+#define GB_ADDR_CONFIG_READ__ROW_SIZE_MASK 0x30000000L
+#define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES_MASK 0x40000000L
+#define GB_ADDR_CONFIG_READ__SE_ENABLE_MASK 0x80000000L
+//GB_TILE_MODE0
+#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE1
+#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE2
+#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE3
+#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE4
+#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE5
+#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE6
+#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE7
+#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE8
+#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE9
+#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE10
+#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE11
+#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE12
+#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE13
+#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE14
+#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE15
+#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE16
+#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE17
+#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE18
+#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE19
+#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE20
+#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE21
+#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE22
+#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE23
+#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE24
+#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE25
+#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE26
+#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE27
+#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE28
+#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE29
+#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE30
+#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE31
+#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_MACROTILE_MODE0
+#define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE1
+#define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE2
+#define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE3
+#define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE4
+#define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE5
+#define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE6
+#define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE7
+#define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE8
+#define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE9
+#define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE10
+#define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE11
+#define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE12
+#define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE13
+#define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE14
+#define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE15
+#define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0x000000C0L
+//CB_HW_CONTROL
+#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0
+#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6
+#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc
+#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10
+#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12
+#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13
+#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15
+#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16
+#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b
+#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c
+#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d
+#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e
+#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f
+#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0x0000000FL
+#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x000003C0L
+#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0x0000F000L
+#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x00010000L
+#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x00040000L
+#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x00080000L
+#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x00100000L
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x00200000L
+#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x00400000L
+#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x00800000L
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x01000000L
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x02000000L
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x04000000L
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x08000000L
+#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000L
+#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000L
+#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000L
+#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000L
+//CB_HW_CONTROL_1
+#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0
+#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5
+#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb
+#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11
+#define CB_HW_CONTROL_1__RMI_CREDITS__SHIFT 0x1a
+#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x0000001FL
+#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x000007E0L
+#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x0001F800L
+#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x03FE0000L
+#define CB_HW_CONTROL_1__RMI_CREDITS_MASK 0xFC000000L
+//CB_HW_CONTROL_2
+#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0
+#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8
+#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf
+#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x18
+#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x1c
+#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0x000000FFL
+#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x00007F00L
+#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x007F8000L
+#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0x0F000000L
+#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xF0000000L
+//CB_HW_CONTROL_3
+#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0
+#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x1
+#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT 0x2
+#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT 0x3
+#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT 0x4
+#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x5
+#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x7
+#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT 0x8
+#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT 0x9
+#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT 0xa
+#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION__SHIFT 0xb
+#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967__SHIFT 0xc
+#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657__SHIFT 0xd
+#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542__SHIFT 0xe
+#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH__SHIFT 0xf
+#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH__SHIFT 0x10
+#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC__SHIFT 0x11
+#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC__SHIFT 0x12
+#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC__SHIFT 0x13
+#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM__SHIFT 0x14
+#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC__SHIFT 0x15
+#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC__SHIFT 0x16
+#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC__SHIFT 0x17
+#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM__SHIFT 0x18
+#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT__SHIFT 0x19
+#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING__SHIFT 0x1a
+#define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX__SHIFT 0x1b
+#define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS__SHIFT 0x1c
+#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x00000001L
+#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x00000002L
+#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK 0x00000004L
+#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK 0x00000008L
+#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK 0x00000010L
+#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x00000020L
+#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x00000080L
+#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK 0x00000100L
+#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK 0x00000200L
+#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK 0x00000400L
+#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION_MASK 0x00000800L
+#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967_MASK 0x00001000L
+#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657_MASK 0x00002000L
+#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542_MASK 0x00004000L
+#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH_MASK 0x00008000L
+#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH_MASK 0x00010000L
+#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC_MASK 0x00020000L
+#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC_MASK 0x00040000L
+#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC_MASK 0x00080000L
+#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM_MASK 0x00100000L
+#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC_MASK 0x00200000L
+#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC_MASK 0x00400000L
+#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC_MASK 0x00800000L
+#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM_MASK 0x01000000L
+#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT_MASK 0x02000000L
+#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING_MASK 0x04000000L
+#define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX_MASK 0x08000000L
+#define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS_MASK 0x30000000L
+//CB_HW_MEM_ARBITER_RD
+#define CB_HW_MEM_ARBITER_RD__MODE__SHIFT 0x0
+#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE__SHIFT 0x2
+#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE__SHIFT 0x6
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC__SHIFT 0xa
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC__SHIFT 0xc
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM__SHIFT 0xe
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC__SHIFT 0x10
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS__SHIFT 0x12
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS__SHIFT 0x14
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS__SHIFT 0x16
+#define CB_HW_MEM_ARBITER_RD__SCALE_AGE__SHIFT 0x17
+#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT__SHIFT 0x1a
+#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d
+#define CB_HW_MEM_ARBITER_RD__MODE_MASK 0x00000003L
+#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE_MASK 0x0000003CL
+#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE_MASK 0x000003C0L
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC_MASK 0x00000C00L
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC_MASK 0x00003000L
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM_MASK 0x0000C000L
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC_MASK 0x00030000L
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS_MASK 0x000C0000L
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS_MASK 0x00300000L
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS_MASK 0x00400000L
+#define CB_HW_MEM_ARBITER_RD__SCALE_AGE_MASK 0x03800000L
+#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT_MASK 0x1C000000L
+#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L
+//CB_HW_MEM_ARBITER_WR
+#define CB_HW_MEM_ARBITER_WR__MODE__SHIFT 0x0
+#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE__SHIFT 0x2
+#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE__SHIFT 0x6
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC__SHIFT 0xa
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC__SHIFT 0xc
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM__SHIFT 0xe
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC__SHIFT 0x10
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS__SHIFT 0x12
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS__SHIFT 0x14
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK__SHIFT 0x16
+#define CB_HW_MEM_ARBITER_WR__SCALE_AGE__SHIFT 0x17
+#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT__SHIFT 0x1a
+#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d
+#define CB_HW_MEM_ARBITER_WR__MODE_MASK 0x00000003L
+#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE_MASK 0x0000003CL
+#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE_MASK 0x000003C0L
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC_MASK 0x00000C00L
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC_MASK 0x00003000L
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM_MASK 0x0000C000L
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC_MASK 0x00030000L
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS_MASK 0x000C0000L
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS_MASK 0x00300000L
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK_MASK 0x00400000L
+#define CB_HW_MEM_ARBITER_WR__SCALE_AGE_MASK 0x03800000L
+#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT_MASK 0x1C000000L
+#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L
+//CB_DCC_CONFIG
+#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT 0x0
+#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT 0x5
+#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT 0x6
+#define CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE__SHIFT 0x7
+#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x10
+#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT 0x18
+#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x1c
+#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK 0x0000001FL
+#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK 0x00000020L
+#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK 0x00000040L
+#define CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE_MASK 0x00000080L
+#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x007F0000L
+#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK 0x0F000000L
+#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xF0000000L
+//GC_USER_RB_REDUNDANCY
+#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
+#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
+#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
+#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
+#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L
+#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L
+#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L
+#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L
+//GC_USER_RB_BACKEND_DISABLE
+#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
+#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L
+
+
+// addressBlock: gc_rlcpdec
+//RLC_CNTL
+#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0
+#define RLC_CNTL__FORCE_RETRY__SHIFT 0x1
+#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2
+#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3
+#define RLC_CNTL__RESERVED__SHIFT 0x4
+#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x00000001L
+#define RLC_CNTL__FORCE_RETRY_MASK 0x00000002L
+#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x00000004L
+#define RLC_CNTL__RLC_STEP_F32_MASK 0x00000008L
+#define RLC_CNTL__RESERVED_MASK 0xFFFFFFF0L
+//RLC_STAT
+#define RLC_STAT__RLC_BUSY__SHIFT 0x0
+#define RLC_STAT__RLC_SRM_BUSY__SHIFT 0x1
+#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x2
+#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x3
+#define RLC_STAT__MC_BUSY__SHIFT 0x4
+#define RLC_STAT__RLC_THREAD_0_BUSY__SHIFT 0x5
+#define RLC_STAT__RLC_THREAD_1_BUSY__SHIFT 0x6
+#define RLC_STAT__RLC_THREAD_2_BUSY__SHIFT 0x7
+#define RLC_STAT__RESERVED__SHIFT 0x8
+#define RLC_STAT__RLC_BUSY_MASK 0x00000001L
+#define RLC_STAT__RLC_SRM_BUSY_MASK 0x00000002L
+#define RLC_STAT__RLC_GPM_BUSY_MASK 0x00000004L
+#define RLC_STAT__RLC_SPM_BUSY_MASK 0x00000008L
+#define RLC_STAT__MC_BUSY_MASK 0x00000010L
+#define RLC_STAT__RLC_THREAD_0_BUSY_MASK 0x00000020L
+#define RLC_STAT__RLC_THREAD_1_BUSY_MASK 0x00000040L
+#define RLC_STAT__RLC_THREAD_2_BUSY_MASK 0x00000080L
+#define RLC_STAT__RESERVED_MASK 0xFFFFFF00L
+//RLC_SAFE_MODE
+#define RLC_SAFE_MODE__CMD__SHIFT 0x0
+#define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1
+#define RLC_SAFE_MODE__RESERVED1__SHIFT 0x5
+#define RLC_SAFE_MODE__RESPONSE__SHIFT 0x8
+#define RLC_SAFE_MODE__RESERVED__SHIFT 0xc
+#define RLC_SAFE_MODE__CMD_MASK 0x00000001L
+#define RLC_SAFE_MODE__MESSAGE_MASK 0x0000001EL
+#define RLC_SAFE_MODE__RESERVED1_MASK 0x000000E0L
+#define RLC_SAFE_MODE__RESPONSE_MASK 0x00000F00L
+#define RLC_SAFE_MODE__RESERVED_MASK 0xFFFFF000L
+//RLC_MEM_SLP_CNTL
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0
+#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1
+#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
+#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT 0x7
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10
+#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x00000001L
+#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L
+#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x0000007CL
+#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0x0000FF00L
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0x00FF0000L
+#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xFF000000L
+//RLC_RLCV_SAFE_MODE
+#define RLC_RLCV_SAFE_MODE__CMD__SHIFT 0x0
+#define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT 0x1
+#define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT 0x5
+#define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT 0x8
+#define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT 0xc
+#define RLC_RLCV_SAFE_MODE__CMD_MASK 0x00000001L
+#define RLC_RLCV_SAFE_MODE__MESSAGE_MASK 0x0000001EL
+#define RLC_RLCV_SAFE_MODE__RESERVED1_MASK 0x000000E0L
+#define RLC_RLCV_SAFE_MODE__RESPONSE_MASK 0x00000F00L
+#define RLC_RLCV_SAFE_MODE__RESERVED_MASK 0xFFFFF000L
+//RLC_RLCV_COMMAND
+#define RLC_RLCV_COMMAND__CMD__SHIFT 0x0
+#define RLC_RLCV_COMMAND__RESERVED__SHIFT 0x4
+#define RLC_RLCV_COMMAND__CMD_MASK 0x0000000FL
+#define RLC_RLCV_COMMAND__RESERVED_MASK 0xFFFFFFF0L
+//RLC_REFCLOCK_TIMESTAMP_LSB
+#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB__SHIFT 0x0
+#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB_MASK 0xFFFFFFFFL
+//RLC_REFCLOCK_TIMESTAMP_MSB
+#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB__SHIFT 0x0
+#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB_MASK 0xFFFFFFFFL
+//RLC_GPM_TIMER_INT_0
+#define RLC_GPM_TIMER_INT_0__TIMER__SHIFT 0x0
+#define RLC_GPM_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL
+//RLC_GPM_TIMER_INT_1
+#define RLC_GPM_TIMER_INT_1__TIMER__SHIFT 0x0
+#define RLC_GPM_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL
+//RLC_GPM_TIMER_INT_2
+#define RLC_GPM_TIMER_INT_2__TIMER__SHIFT 0x0
+#define RLC_GPM_TIMER_INT_2__TIMER_MASK 0xFFFFFFFFL
+//RLC_GPM_TIMER_CTRL
+#define RLC_GPM_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0
+#define RLC_GPM_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1
+#define RLC_GPM_TIMER_CTRL__TIMER_2_EN__SHIFT 0x2
+#define RLC_GPM_TIMER_CTRL__TIMER_3_EN__SHIFT 0x3
+#define RLC_GPM_TIMER_CTRL__RESERVED__SHIFT 0x4
+#define RLC_GPM_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L
+#define RLC_GPM_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L
+#define RLC_GPM_TIMER_CTRL__TIMER_2_EN_MASK 0x00000004L
+#define RLC_GPM_TIMER_CTRL__TIMER_3_EN_MASK 0x00000008L
+#define RLC_GPM_TIMER_CTRL__RESERVED_MASK 0xFFFFFFF0L
+//RLC_LB_CNTR_MAX
+#define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x0
+#define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xFFFFFFFFL
+//RLC_GPM_TIMER_STAT
+#define RLC_GPM_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0
+#define RLC_GPM_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1
+#define RLC_GPM_TIMER_STAT__TIMER_2_STAT__SHIFT 0x2
+#define RLC_GPM_TIMER_STAT__TIMER_3_STAT__SHIFT 0x3
+#define RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT 0x8
+#define RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT 0x9
+#define RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC__SHIFT 0xa
+#define RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC__SHIFT 0xb
+#define RLC_GPM_TIMER_STAT__RESERVED__SHIFT 0xc
+#define RLC_GPM_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L
+#define RLC_GPM_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L
+#define RLC_GPM_TIMER_STAT__TIMER_2_STAT_MASK 0x00000004L
+#define RLC_GPM_TIMER_STAT__TIMER_3_STAT_MASK 0x00000008L
+#define RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK 0x00000100L
+#define RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK 0x00000200L
+#define RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC_MASK 0x00000400L
+#define RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC_MASK 0x00000800L
+#define RLC_GPM_TIMER_STAT__RESERVED_MASK 0xFFFFF000L
+//RLC_GPM_TIMER_INT_3
+#define RLC_GPM_TIMER_INT_3__TIMER__SHIFT 0x0
+#define RLC_GPM_TIMER_INT_3__TIMER_MASK 0xFFFFFFFFL
+//RLC_SERDES_WR_NONCU_MASTER_MASK_1
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1__SHIFT 0x0
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1__SHIFT 0x10
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1__SHIFT 0x11
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK__SHIFT 0x12
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1__SHIFT 0x13
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK__SHIFT 0x14
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK__SHIFT 0x15
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK__SHIFT 0x16
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK__SHIFT 0x17
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK__SHIFT 0x18
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED__SHIFT 0x19
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1_MASK 0x0000FFFFL
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1_MASK 0x00010000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1_MASK 0x00020000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK_MASK 0x00040000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1_MASK 0x00080000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK_MASK 0x00100000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK_MASK 0x00200000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK_MASK 0x00400000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK_MASK 0x00800000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK_MASK 0x01000000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_MASK 0xFE000000L
+//RLC_SERDES_NONCU_MASTER_BUSY_1
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1__SHIFT 0x0
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1__SHIFT 0x10
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1__SHIFT 0x11
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1__SHIFT 0x12
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1__SHIFT 0x13
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY__SHIFT 0x14
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY__SHIFT 0x15
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY__SHIFT 0x16
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY__SHIFT 0x17
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY__SHIFT 0x18
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED__SHIFT 0x19
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1_MASK 0x0000FFFFL
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1_MASK 0x00010000L
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1_MASK 0x00020000L
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1_MASK 0x00040000L
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1_MASK 0x00080000L
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY_MASK 0x00100000L
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY_MASK 0x00200000L
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY_MASK 0x00400000L
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY_MASK 0x00800000L
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY_MASK 0x01000000L
+#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_MASK 0xFE000000L
+//RLC_INT_STAT
+#define RLC_INT_STAT__LAST_CP_RLC_INT_ID__SHIFT 0x0
+#define RLC_INT_STAT__CP_RLC_INT_PENDING__SHIFT 0x8
+#define RLC_INT_STAT__RESERVED__SHIFT 0x9
+#define RLC_INT_STAT__LAST_CP_RLC_INT_ID_MASK 0x000000FFL
+#define RLC_INT_STAT__CP_RLC_INT_PENDING_MASK 0x00000100L
+#define RLC_INT_STAT__RESERVED_MASK 0xFFFFFE00L
+//RLC_LB_CNTL
+#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x0
+#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x1
+#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x2
+#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x3
+#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x4
+#define RLC_LB_CNTL__RESERVED__SHIFT 0xc
+#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x00000001L
+#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x00000002L
+#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x00000004L
+#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x00000008L
+#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0x00000FF0L
+#define RLC_LB_CNTL__RESERVED_MASK 0xFFFFF000L
+//RLC_MGCG_CTRL
+#define RLC_MGCG_CTRL__MGCG_EN__SHIFT 0x0
+#define RLC_MGCG_CTRL__SILICON_EN__SHIFT 0x1
+#define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT 0x2
+#define RLC_MGCG_CTRL__ON_DELAY__SHIFT 0x3
+#define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT 0x7
+#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL__SHIFT 0xf
+#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL__SHIFT 0x10
+#define RLC_MGCG_CTRL__SPARE__SHIFT 0x11
+#define RLC_MGCG_CTRL__MGCG_EN_MASK 0x00000001L
+#define RLC_MGCG_CTRL__SILICON_EN_MASK 0x00000002L
+#define RLC_MGCG_CTRL__SIMULATION_EN_MASK 0x00000004L
+#define RLC_MGCG_CTRL__ON_DELAY_MASK 0x00000078L
+#define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK 0x00007F80L
+#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL_MASK 0x00008000L
+#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL_MASK 0x00010000L
+#define RLC_MGCG_CTRL__SPARE_MASK 0xFFFE0000L
+//RLC_LB_CNTR_INIT
+#define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x0
+#define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xFFFFFFFFL
+//RLC_LOAD_BALANCE_CNTR
+#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0
+#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xFFFFFFFFL
+//RLC_JUMP_TABLE_RESTORE
+#define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0
+#define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xFFFFFFFFL
+//RLC_PG_DELAY_2
+#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0
+#define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8
+#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT 0x10
+#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0x000000FFL
+#define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0x0000FF00L
+#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK 0xFFFF0000L
+//RLC_GPU_CLOCK_COUNT_LSB
+#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0
+#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL
+//RLC_GPU_CLOCK_COUNT_MSB
+#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0
+#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL
+//RLC_CAPTURE_GPU_CLOCK_COUNT
+#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0
+#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1
+#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x00000001L
+#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xFFFFFFFEL
+//RLC_UCODE_CNTL
+#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0
+#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xFFFFFFFFL
+//RLC_GPM_THREAD_RESET
+#define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT 0x0
+#define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT 0x1
+#define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT 0x2
+#define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT 0x3
+#define RLC_GPM_THREAD_RESET__RESERVED__SHIFT 0x4
+#define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK 0x00000001L
+#define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK 0x00000002L
+#define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK 0x00000004L
+#define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK 0x00000008L
+#define RLC_GPM_THREAD_RESET__RESERVED_MASK 0xFFFFFFF0L
+//RLC_GPM_CP_DMA_COMPLETE_T0
+#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA__SHIFT 0x0
+#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED__SHIFT 0x1
+#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA_MASK 0x00000001L
+#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED_MASK 0xFFFFFFFEL
+//RLC_GPM_CP_DMA_COMPLETE_T1
+#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA__SHIFT 0x0
+#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED__SHIFT 0x1
+#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA_MASK 0x00000001L
+#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED_MASK 0xFFFFFFFEL
+//RLC_CLK_COUNT_GFXCLK_LSB
+#define RLC_CLK_COUNT_GFXCLK_LSB__COUNTER__SHIFT 0x0
+#define RLC_CLK_COUNT_GFXCLK_LSB__COUNTER_MASK 0xFFFFFFFFL
+//RLC_CLK_COUNT_GFXCLK_MSB
+#define RLC_CLK_COUNT_GFXCLK_MSB__COUNTER__SHIFT 0x0
+#define RLC_CLK_COUNT_GFXCLK_MSB__COUNTER_MASK 0xFFFFFFFFL
+//RLC_CLK_COUNT_REFCLK_LSB
+#define RLC_CLK_COUNT_REFCLK_LSB__COUNTER__SHIFT 0x0
+#define RLC_CLK_COUNT_REFCLK_LSB__COUNTER_MASK 0xFFFFFFFFL
+//RLC_CLK_COUNT_REFCLK_MSB
+#define RLC_CLK_COUNT_REFCLK_MSB__COUNTER__SHIFT 0x0
+#define RLC_CLK_COUNT_REFCLK_MSB__COUNTER_MASK 0xFFFFFFFFL
+//RLC_CLK_COUNT_CTRL
+#define RLC_CLK_COUNT_CTRL__GFXCLK_RUN__SHIFT 0x0
+#define RLC_CLK_COUNT_CTRL__GFXCLK_RESET__SHIFT 0x1
+#define RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE__SHIFT 0x2
+#define RLC_CLK_COUNT_CTRL__REFCLK_RUN__SHIFT 0x3
+#define RLC_CLK_COUNT_CTRL__REFCLK_RESET__SHIFT 0x4
+#define RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE__SHIFT 0x5
+#define RLC_CLK_COUNT_CTRL__GFXCLK_RUN_MASK 0x00000001L
+#define RLC_CLK_COUNT_CTRL__GFXCLK_RESET_MASK 0x00000002L
+#define RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE_MASK 0x00000004L
+#define RLC_CLK_COUNT_CTRL__REFCLK_RUN_MASK 0x00000008L
+#define RLC_CLK_COUNT_CTRL__REFCLK_RESET_MASK 0x00000010L
+#define RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE_MASK 0x00000020L
+//RLC_CLK_COUNT_STAT
+#define RLC_CLK_COUNT_STAT__GFXCLK_VALID__SHIFT 0x0
+#define RLC_CLK_COUNT_STAT__REFCLK_VALID__SHIFT 0x1
+#define RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC__SHIFT 0x2
+#define RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC__SHIFT 0x3
+#define RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC__SHIFT 0x4
+#define RLC_CLK_COUNT_STAT__RESERVED__SHIFT 0x5
+#define RLC_CLK_COUNT_STAT__GFXCLK_VALID_MASK 0x00000001L
+#define RLC_CLK_COUNT_STAT__REFCLK_VALID_MASK 0x00000002L
+#define RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC_MASK 0x00000004L
+#define RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC_MASK 0x00000008L
+#define RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC_MASK 0x00000010L
+#define RLC_CLK_COUNT_STAT__RESERVED_MASK 0xFFFFFFE0L
+//RLC_GPM_STAT
+#define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0
+#define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1
+#define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2
+#define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3
+#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4
+#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5
+#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6
+#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7
+#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8
+#define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9
+#define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa
+#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb
+#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc
+#define RLC_GPM_STAT__STATIC_CU_POWERING_UP__SHIFT 0xd
+#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN__SHIFT 0xe
+#define RLC_GPM_STAT__DYN_CU_POWERING_UP__SHIFT 0xf
+#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN__SHIFT 0x10
+#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11
+#define RLC_GPM_STAT__CMP_power_status__SHIFT 0x12
+#define RLC_GPM_STAT__RESERVED_1__SHIFT 0x13
+#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT 0x15
+#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT 0x16
+#define RLC_GPM_STAT__FGCG_OVERRIDE_STATUS__SHIFT 0x17
+#define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18
+#define RLC_GPM_STAT__RLC_BUSY_MASK 0x00000001L
+#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L
+#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L
+#define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x00000008L
+#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x00000010L
+#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x00000020L
+#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x00000040L
+#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x00000080L
+#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x00000100L
+#define RLC_GPM_STAT__SAVING_REGISTERS_MASK 0x00000200L
+#define RLC_GPM_STAT__RESTORING_REGISTERS_MASK 0x00000400L
+#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x00000800L
+#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x00001000L
+#define RLC_GPM_STAT__STATIC_CU_POWERING_UP_MASK 0x00002000L
+#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN_MASK 0x00004000L
+#define RLC_GPM_STAT__DYN_CU_POWERING_UP_MASK 0x00008000L
+#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN_MASK 0x00010000L
+#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x00020000L
+#define RLC_GPM_STAT__CMP_power_status_MASK 0x00040000L
+#define RLC_GPM_STAT__RESERVED_1_MASK 0x00180000L
+#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK 0x00200000L
+#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE_MASK 0x00400000L
+#define RLC_GPM_STAT__FGCG_OVERRIDE_STATUS_MASK 0x00800000L
+#define RLC_GPM_STAT__PG_ERROR_STATUS_MASK 0xFF000000L
+//RLC_GPU_CLOCK_32_RES_SEL
+#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0
+#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6
+#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x0000003FL
+#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xFFFFFFC0L
+//RLC_GPU_CLOCK_32
+#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0
+#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xFFFFFFFFL
+//RLC_PG_CNTL
+#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0
+#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1
+#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x2
+#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x3
+#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT 0x4
+#define RLC_PG_CNTL__RESERVED__SHIFT 0x5
+#define RLC_PG_CNTL__PG_OVERRIDE__SHIFT 0xe
+#define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT 0xf
+#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10
+#define RLC_PG_CNTL__RESERVED1__SHIFT 0x14
+#define RLC_PG_CNTL__Ultra_Low_Voltage_Enable__SHIFT 0x15
+#define RLC_PG_CNTL__RESERVED2__SHIFT 0x16
+#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L
+#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L
+#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x00000004L
+#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x00000008L
+#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK 0x00000010L
+#define RLC_PG_CNTL__RESERVED_MASK 0x00003FE0L
+#define RLC_PG_CNTL__PG_OVERRIDE_MASK 0x00004000L
+#define RLC_PG_CNTL__CP_PG_DISABLE_MASK 0x00008000L
+#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x00010000L
+#define RLC_PG_CNTL__RESERVED1_MASK 0x00100000L
+#define RLC_PG_CNTL__Ultra_Low_Voltage_Enable_MASK 0x00200000L
+#define RLC_PG_CNTL__RESERVED2_MASK 0x00C00000L
+//RLC_GPM_THREAD_PRIORITY
+#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0
+#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8
+#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10
+#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18
+#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0x000000FFL
+#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0x0000FF00L
+#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0x00FF0000L
+#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xFF000000L
+//RLC_GPM_THREAD_ENABLE
+#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0
+#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1
+#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2
+#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3
+#define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4
+#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x00000001L
+#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x00000002L
+#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x00000004L
+#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x00000008L
+#define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xFFFFFFF0L
+//RLC_CGTT_MGCG_OVERRIDE
+#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_0__SHIFT 0x0
+#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE__SHIFT 0x1
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE__SHIFT 0x2
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE__SHIFT 0x3
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE__SHIFT 0x4
+#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE__SHIFT 0x5
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE__SHIFT 0x6
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE__SHIFT 0x7
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE__SHIFT 0x8
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE__SHIFT 0x9
+#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_15_10__SHIFT 0xa
+#define RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY__SHIFT 0x10
+#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_17__SHIFT 0x11
+#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_0_MASK 0x00000001L
+#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK 0x00000002L
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK 0x00000004L
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK 0x00000008L
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK 0x00000010L
+#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK 0x00000020L
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK 0x00000040L
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK 0x00000080L
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK 0x00000100L
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK 0x00000200L
+#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_15_10_MASK 0x0000FC00L
+#define RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK 0x00010000L
+#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_17_MASK 0xFFFE0000L
+//RLC_CGCG_CGLS_CTRL
+#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0
+#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1
+#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2
+#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8
+#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b
+#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c
+#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d
+#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT 0x1f
+#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L
+#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x00000002L
+#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL
+#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L
+#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x08000000L
+#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L
+#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000L
+#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK 0x80000000L
+//RLC_CGCG_RAMP_CTRL
+#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0
+#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4
+#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8
+#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc
+#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10
+#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c
+#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0x0000000FL
+#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L
+#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0x00000F00L
+#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0x0000F000L
+#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0x0FFF0000L
+#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xF0000000L
+//RLC_DYN_PG_STATUS
+#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0
+#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xFFFFFFFFL
+//RLC_DYN_PG_REQUEST
+#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x0
+#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xFFFFFFFFL
+//RLC_PG_DELAY
+#define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0
+#define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8
+#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10
+#define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18
+#define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0x000000FFL
+#define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0x0000FF00L
+#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0x00FF0000L
+#define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xFF000000L
+//RLC_CU_STATUS
+#define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x0
+#define RLC_CU_STATUS__WORK_PENDING_MASK 0xFFFFFFFFL
+//RLC_LB_INIT_CU_MASK
+#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x0
+#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xFFFFFFFFL
+//RLC_LB_ALWAYS_ACTIVE_CU_MASK
+#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x0
+#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xFFFFFFFFL
+//RLC_LB_PARAMS
+#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x0
+#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x1
+#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x8
+#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x10
+#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x00000001L
+#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0x000000FEL
+#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0x0000FF00L
+#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xFFFF0000L
+//RLC_THREAD1_DELAY
+#define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x0
+#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x8
+#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x10
+#define RLC_THREAD1_DELAY__SPARE__SHIFT 0x18
+#define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0x000000FFL
+#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0x0000FF00L
+#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0x00FF0000L
+#define RLC_THREAD1_DELAY__SPARE_MASK 0xFF000000L
+//RLC_PG_ALWAYS_ON_CU_MASK
+#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x0
+#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xFFFFFFFFL
+//RLC_MAX_PG_CU
+#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x0
+#define RLC_MAX_PG_CU__SPARE__SHIFT 0x8
+#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0x000000FFL
+#define RLC_MAX_PG_CU__SPARE_MASK 0xFFFFFF00L
+//RLC_AUTO_PG_CTRL
+#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0
+#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1
+#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2
+#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3
+#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13
+#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L
+#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x00000002L
+#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L
+#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x0007FFF8L
+#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xFFF80000L
+//RLC_SERDES_RD_PENDING
+#define RLC_SERDES_RD_PENDING__RD_PENDING__SHIFT 0x0
+#define RLC_SERDES_RD_PENDING__RD_PENDING_MASK 0x00000001L
+//RLC_SERDES_RD_MASTER_INDEX
+#define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x0
+#define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x4
+#define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x6
+#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x9
+#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0xc
+#define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0xd
+#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0x11
+#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x13
+#define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0x0000000FL
+#define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x00000030L
+#define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x000001C0L
+#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x00000E00L
+#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x00001000L
+#define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x0001E000L
+#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0x00060000L
+#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xFFF80000L
+//RLC_SERDES_RD_DATA_0
+#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0
+#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xFFFFFFFFL
+//RLC_SERDES_RD_DATA_1
+#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0
+#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xFFFFFFFFL
+//RLC_SERDES_RD_DATA_2
+#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0
+#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xFFFFFFFFL
+//RLC_SERDES_WR_CU_MASTER_MASK
+#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT 0x0
+#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK 0xFFFFFFFFL
+//RLC_SERDES_WR_NONCU_MASTER_MASK
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT 0x0
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT 0x10
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK__SHIFT 0x11
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT 0x12
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT 0x13
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT 0x14
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT 0x15
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT 0x16
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT 0x17
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK__SHIFT 0x18
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK__SHIFT 0x19
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT 0x1a
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK 0x0000FFFFL
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK 0x00010000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK_MASK 0x00020000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK 0x00040000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK 0x00080000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK 0x00100000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK 0x00200000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK 0x00400000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK 0x00800000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK_MASK 0x01000000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK_MASK 0x02000000L
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK 0xFC000000L
+//RLC_SERDES_WR_CTRL
+#define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x0
+#define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x8
+#define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x9
+#define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0xa
+#define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0xb
+#define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0xc
+#define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0xd
+#define RLC_SERDES_WR_CTRL__RDDATA_RESET__SHIFT 0xe
+#define RLC_SERDES_WR_CTRL__SHORT_FORMAT__SHIFT 0xf
+#define RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT 0x10
+#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE__SHIFT 0x1a
+#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR__SHIFT 0x1b
+#define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x1c
+#define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0x000000FFL
+#define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x00000100L
+#define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x00000200L
+#define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x00000400L
+#define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x00000800L
+#define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x00001000L
+#define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x00002000L
+#define RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK 0x00004000L
+#define RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK 0x00008000L
+#define RLC_SERDES_WR_CTRL__BPM_DATA_MASK 0x03FF0000L
+#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK 0x04000000L
+#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK 0x08000000L
+#define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xF0000000L
+//RLC_SERDES_WR_DATA
+#define RLC_SERDES_WR_DATA__DATA__SHIFT 0x0
+#define RLC_SERDES_WR_DATA__DATA_MASK 0xFFFFFFFFL
+//RLC_SERDES_CU_MASTER_BUSY
+#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT 0x0
+#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK 0xFFFFFFFFL
+//RLC_SERDES_NONCU_MASTER_BUSY
+#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT 0x0
+#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT 0x10
+#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY__SHIFT 0x11
+#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT 0x12
+#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT 0x13
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT 0x14
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT 0x15
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT 0x16
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT 0x17
+#define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY__SHIFT 0x18
+#define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY__SHIFT 0x19
+#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT 0x1a
+#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK 0x0000FFFFL
+#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK 0x00010000L
+#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY_MASK 0x00020000L
+#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK 0x00040000L
+#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK 0x00080000L
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK 0x00100000L
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK 0x00200000L
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK 0x00400000L
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK 0x00800000L
+#define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY_MASK 0x01000000L
+#define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY_MASK 0x02000000L
+#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK 0xFC000000L
+//RLC_GPM_GENERAL_0
+#define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_0__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_1
+#define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_1__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_2
+#define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_2__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_3
+#define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_3__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_4
+#define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_4__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_5
+#define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_5__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_6
+#define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_6__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_7
+#define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_7__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_SCRATCH_ADDR
+#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0
+#define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x9
+#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x000001FFL
+#define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xFFFFFE00L
+//RLC_GPM_SCRATCH_DATA
+#define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0
+#define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL
+//RLC_STATIC_PG_STATUS
+#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0
+#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xFFFFFFFFL
+//RLC_SPM_MC_CNTL
+#define RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT 0x0
+#define RLC_SPM_MC_CNTL__RLC_SPM_POLICY__SHIFT 0x4
+#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR__SHIFT 0x5
+#define RLC_SPM_MC_CNTL__RLC_SPM_FED__SHIFT 0x6
+#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER__SHIFT 0x7
+#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE__SHIFT 0x8
+#define RLC_SPM_MC_CNTL__RESERVED__SHIFT 0xa
+#define RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK 0x0000000FL
+#define RLC_SPM_MC_CNTL__RLC_SPM_POLICY_MASK 0x00000010L
+#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR_MASK 0x00000020L
+#define RLC_SPM_MC_CNTL__RLC_SPM_FED_MASK 0x00000040L
+#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER_MASK 0x00000080L
+#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_MASK 0x00000300L
+#define RLC_SPM_MC_CNTL__RESERVED_MASK 0xFFFFFC00L
+//RLC_SPM_INT_CNTL
+#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0
+#define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1
+#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x00000001L
+#define RLC_SPM_INT_CNTL__RESERVED_MASK 0xFFFFFFFEL
+//RLC_SPM_INT_STATUS
+#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0
+#define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1
+#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x00000001L
+#define RLC_SPM_INT_STATUS__RESERVED_MASK 0xFFFFFFFEL
+//RLC_GPM_LOG_SIZE
+#define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x0
+#define RLC_GPM_LOG_SIZE__SIZE_MASK 0xFFFFFFFFL
+//RLC_PG_DELAY_3
+#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT 0x0
+#define RLC_PG_DELAY_3__RESERVED__SHIFT 0x8
+#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK 0x000000FFL
+#define RLC_PG_DELAY_3__RESERVED_MASK 0xFFFFFF00L
+//RLC_GPR_REG1
+#define RLC_GPR_REG1__DATA__SHIFT 0x0
+#define RLC_GPR_REG1__DATA_MASK 0xFFFFFFFFL
+//RLC_GPR_REG2
+#define RLC_GPR_REG2__DATA__SHIFT 0x0
+#define RLC_GPR_REG2__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_LOG_CONT
+#define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0
+#define RLC_GPM_LOG_CONT__CONT_MASK 0xFFFFFFFFL
+//RLC_GPM_INT_DISABLE_TH0
+#define RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT 0x0
+#define RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK 0xFFFFFFFFL
+//RLC_GPM_INT_FORCE_TH0
+#define RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT 0x0
+#define RLC_GPM_INT_FORCE_TH0__FORCE_MASK 0xFFFFFFFFL
+//RLC_GPM_INT_FORCE_TH1
+#define RLC_GPM_INT_FORCE_TH1__FORCE__SHIFT 0x0
+#define RLC_GPM_INT_FORCE_TH1__FORCE_MASK 0xFFFFFFFFL
+//RLC_SRM_CNTL
+#define RLC_SRM_CNTL__SRM_ENABLE__SHIFT 0x0
+#define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT 0x1
+#define RLC_SRM_CNTL__RESERVED__SHIFT 0x2
+#define RLC_SRM_CNTL__SRM_ENABLE_MASK 0x00000001L
+#define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK 0x00000002L
+#define RLC_SRM_CNTL__RESERVED_MASK 0xFFFFFFFCL
+//RLC_SRM_ARAM_ADDR
+#define RLC_SRM_ARAM_ADDR__ADDR__SHIFT 0x0
+#define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT 0xc
+#define RLC_SRM_ARAM_ADDR__ADDR_MASK 0x00000FFFL
+#define RLC_SRM_ARAM_ADDR__RESERVED_MASK 0xFFFFF000L
+//RLC_SRM_ARAM_DATA
+#define RLC_SRM_ARAM_DATA__DATA__SHIFT 0x0
+#define RLC_SRM_ARAM_DATA__DATA_MASK 0xFFFFFFFFL
+//RLC_SRM_DRAM_ADDR
+#define RLC_SRM_DRAM_ADDR__ADDR__SHIFT 0x0
+#define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT 0xc
+#define RLC_SRM_DRAM_ADDR__ADDR_MASK 0x00000FFFL
+#define RLC_SRM_DRAM_ADDR__RESERVED_MASK 0xFFFFF000L
+//RLC_SRM_DRAM_DATA
+#define RLC_SRM_DRAM_DATA__DATA__SHIFT 0x0
+#define RLC_SRM_DRAM_DATA__DATA_MASK 0xFFFFFFFFL
+//RLC_SRM_GPM_COMMAND
+#define RLC_SRM_GPM_COMMAND__OP__SHIFT 0x0
+#define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT 0x1
+#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT 0x2
+#define RLC_SRM_GPM_COMMAND__SIZE__SHIFT 0x5
+#define RLC_SRM_GPM_COMMAND__RESERVED_16__SHIFT 0x10
+#define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT 0x11
+#define RLC_SRM_GPM_COMMAND__RESERVED_30_29__SHIFT 0x1d
+#define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT 0x1f
+#define RLC_SRM_GPM_COMMAND__OP_MASK 0x00000001L
+#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK 0x00000002L
+#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK 0x0000001CL
+#define RLC_SRM_GPM_COMMAND__SIZE_MASK 0x0000FFE0L
+#define RLC_SRM_GPM_COMMAND__RESERVED_16_MASK 0x00010000L
+#define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK 0x1FFE0000L
+#define RLC_SRM_GPM_COMMAND__RESERVED_30_29_MASK 0x60000000L
+#define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK 0x80000000L
+//RLC_SRM_GPM_COMMAND_STATUS
+#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0
+#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1
+#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT 0x2
+#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L
+#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L
+#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL
+//RLC_SRM_RLCV_COMMAND
+#define RLC_SRM_RLCV_COMMAND__OP__SHIFT 0x0
+#define RLC_SRM_RLCV_COMMAND__RESERVED__SHIFT 0x1
+#define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT 0x4
+#define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT 0x10
+#define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT 0x1c
+#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT 0x1f
+#define RLC_SRM_RLCV_COMMAND__OP_MASK 0x00000001L
+#define RLC_SRM_RLCV_COMMAND__RESERVED_MASK 0x0000000EL
+#define RLC_SRM_RLCV_COMMAND__SIZE_MASK 0x0000FFF0L
+#define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK 0x0FFF0000L
+#define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK 0x70000000L
+#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK 0x80000000L
+//RLC_SRM_RLCV_COMMAND_STATUS
+#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0
+#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1
+#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT 0x2
+#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L
+#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L
+#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL
+//RLC_SRM_INDEX_CNTL_ADDR_0
+#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK 0x0000FFFFL
+#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK 0xFFFF0000L
+//RLC_SRM_INDEX_CNTL_ADDR_1
+#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK 0x0000FFFFL
+#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK 0xFFFF0000L
+//RLC_SRM_INDEX_CNTL_ADDR_2
+#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK 0x0000FFFFL
+#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK 0xFFFF0000L
+//RLC_SRM_INDEX_CNTL_ADDR_3
+#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK 0x0000FFFFL
+#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK 0xFFFF0000L
+//RLC_SRM_INDEX_CNTL_ADDR_4
+#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK 0x0000FFFFL
+#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK 0xFFFF0000L
+//RLC_SRM_INDEX_CNTL_ADDR_5
+#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK 0x0000FFFFL
+#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK 0xFFFF0000L
+//RLC_SRM_INDEX_CNTL_ADDR_6
+#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK 0x0000FFFFL
+#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK 0xFFFF0000L
+//RLC_SRM_INDEX_CNTL_ADDR_7
+#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK 0x0000FFFFL
+#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK 0xFFFF0000L
+//RLC_SRM_INDEX_CNTL_DATA_0
+#define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK 0xFFFFFFFFL
+//RLC_SRM_INDEX_CNTL_DATA_1
+#define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK 0xFFFFFFFFL
+//RLC_SRM_INDEX_CNTL_DATA_2
+#define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK 0xFFFFFFFFL
+//RLC_SRM_INDEX_CNTL_DATA_3
+#define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK 0xFFFFFFFFL
+//RLC_SRM_INDEX_CNTL_DATA_4
+#define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK 0xFFFFFFFFL
+//RLC_SRM_INDEX_CNTL_DATA_5
+#define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK 0xFFFFFFFFL
+//RLC_SRM_INDEX_CNTL_DATA_6
+#define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK 0xFFFFFFFFL
+//RLC_SRM_INDEX_CNTL_DATA_7
+#define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK 0xFFFFFFFFL
+//RLC_SRM_STAT
+#define RLC_SRM_STAT__SRM_BUSY__SHIFT 0x0
+#define RLC_SRM_STAT__SRM_BUSY_DELAY__SHIFT 0x1
+#define RLC_SRM_STAT__RESERVED__SHIFT 0x2
+#define RLC_SRM_STAT__SRM_BUSY_MASK 0x00000001L
+#define RLC_SRM_STAT__SRM_BUSY_DELAY_MASK 0x00000002L
+#define RLC_SRM_STAT__RESERVED_MASK 0xFFFFFFFCL
+//RLC_SRM_GPM_ABORT
+#define RLC_SRM_GPM_ABORT__ABORT__SHIFT 0x0
+#define RLC_SRM_GPM_ABORT__RESERVED__SHIFT 0x1
+#define RLC_SRM_GPM_ABORT__ABORT_MASK 0x00000001L
+#define RLC_SRM_GPM_ABORT__RESERVED_MASK 0xFFFFFFFEL
+//RLC_CSIB_ADDR_LO
+#define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT 0x0
+#define RLC_CSIB_ADDR_LO__ADDRESS_MASK 0xFFFFFFFFL
+//RLC_CSIB_ADDR_HI
+#define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT 0x0
+#define RLC_CSIB_ADDR_HI__ADDRESS_MASK 0x0000FFFFL
+//RLC_CSIB_LENGTH
+#define RLC_CSIB_LENGTH__LENGTH__SHIFT 0x0
+#define RLC_CSIB_LENGTH__LENGTH_MASK 0xFFFFFFFFL
+//RLC_CP_SCHEDULERS
+#define RLC_CP_SCHEDULERS__scheduler0__SHIFT 0x0
+#define RLC_CP_SCHEDULERS__scheduler1__SHIFT 0x8
+#define RLC_CP_SCHEDULERS__scheduler2__SHIFT 0x10
+#define RLC_CP_SCHEDULERS__scheduler3__SHIFT 0x18
+#define RLC_CP_SCHEDULERS__scheduler0_MASK 0x000000FFL
+#define RLC_CP_SCHEDULERS__scheduler1_MASK 0x0000FF00L
+#define RLC_CP_SCHEDULERS__scheduler2_MASK 0x00FF0000L
+#define RLC_CP_SCHEDULERS__scheduler3_MASK 0xFF000000L
+//RLC_GPM_GENERAL_8
+#define RLC_GPM_GENERAL_8__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_8__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_9
+#define RLC_GPM_GENERAL_9__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_9__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_10
+#define RLC_GPM_GENERAL_10__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_10__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_11
+#define RLC_GPM_GENERAL_11__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_11__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_12
+#define RLC_GPM_GENERAL_12__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_12__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_UTCL1_CNTL_0
+#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT__SHIFT 0x0
+#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE__SHIFT 0x18
+#define RLC_GPM_UTCL1_CNTL_0__BYPASS__SHIFT 0x19
+#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE__SHIFT 0x1a
+#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE__SHIFT 0x1b
+#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP__SHIFT 0x1c
+#define RLC_GPM_UTCL1_CNTL_0__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
+#define RLC_GPM_UTCL1_CNTL_0__RESERVED__SHIFT 0x1e
+#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
+#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE_MASK 0x01000000L
+#define RLC_GPM_UTCL1_CNTL_0__BYPASS_MASK 0x02000000L
+#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE_MASK 0x04000000L
+#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE_MASK 0x08000000L
+#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP_MASK 0x10000000L
+#define RLC_GPM_UTCL1_CNTL_0__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
+#define RLC_GPM_UTCL1_CNTL_0__RESERVED_MASK 0xC0000000L
+//RLC_GPM_UTCL1_CNTL_1
+#define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT__SHIFT 0x0
+#define RLC_GPM_UTCL1_CNTL_1__DROP_MODE__SHIFT 0x18
+#define RLC_GPM_UTCL1_CNTL_1__BYPASS__SHIFT 0x19
+#define RLC_GPM_UTCL1_CNTL_1__INVALIDATE__SHIFT 0x1a
+#define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE__SHIFT 0x1b
+#define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP__SHIFT 0x1c
+#define RLC_GPM_UTCL1_CNTL_1__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
+#define RLC_GPM_UTCL1_CNTL_1__RESERVED__SHIFT 0x1e
+#define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
+#define RLC_GPM_UTCL1_CNTL_1__DROP_MODE_MASK 0x01000000L
+#define RLC_GPM_UTCL1_CNTL_1__BYPASS_MASK 0x02000000L
+#define RLC_GPM_UTCL1_CNTL_1__INVALIDATE_MASK 0x04000000L
+#define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE_MASK 0x08000000L
+#define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP_MASK 0x10000000L
+#define RLC_GPM_UTCL1_CNTL_1__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
+#define RLC_GPM_UTCL1_CNTL_1__RESERVED_MASK 0xC0000000L
+//RLC_GPM_UTCL1_CNTL_2
+#define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT__SHIFT 0x0
+#define RLC_GPM_UTCL1_CNTL_2__DROP_MODE__SHIFT 0x18
+#define RLC_GPM_UTCL1_CNTL_2__BYPASS__SHIFT 0x19
+#define RLC_GPM_UTCL1_CNTL_2__INVALIDATE__SHIFT 0x1a
+#define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE__SHIFT 0x1b
+#define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP__SHIFT 0x1c
+#define RLC_GPM_UTCL1_CNTL_2__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
+#define RLC_GPM_UTCL1_CNTL_2__RESERVED__SHIFT 0x1e
+#define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
+#define RLC_GPM_UTCL1_CNTL_2__DROP_MODE_MASK 0x01000000L
+#define RLC_GPM_UTCL1_CNTL_2__BYPASS_MASK 0x02000000L
+#define RLC_GPM_UTCL1_CNTL_2__INVALIDATE_MASK 0x04000000L
+#define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE_MASK 0x08000000L
+#define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP_MASK 0x10000000L
+#define RLC_GPM_UTCL1_CNTL_2__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
+#define RLC_GPM_UTCL1_CNTL_2__RESERVED_MASK 0xC0000000L
+//RLC_SPM_UTCL1_CNTL
+#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
+#define RLC_SPM_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
+#define RLC_SPM_UTCL1_CNTL__BYPASS__SHIFT 0x19
+#define RLC_SPM_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
+#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
+#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
+#define RLC_SPM_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
+#define RLC_SPM_UTCL1_CNTL__RESERVED__SHIFT 0x1e
+#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
+#define RLC_SPM_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
+#define RLC_SPM_UTCL1_CNTL__BYPASS_MASK 0x02000000L
+#define RLC_SPM_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
+#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
+#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
+#define RLC_SPM_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
+#define RLC_SPM_UTCL1_CNTL__RESERVED_MASK 0xC0000000L
+//RLC_UTCL1_STATUS_2
+#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY__SHIFT 0x0
+#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY__SHIFT 0x1
+#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY__SHIFT 0x2
+#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY__SHIFT 0x3
+#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY__SHIFT 0x4
+#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans__SHIFT 0x5
+#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans__SHIFT 0x6
+#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans__SHIFT 0x7
+#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans__SHIFT 0x8
+#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans__SHIFT 0x9
+#define RLC_UTCL1_STATUS_2__RESERVED__SHIFT 0xa
+#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY_MASK 0x00000001L
+#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY_MASK 0x00000002L
+#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY_MASK 0x00000004L
+#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY_MASK 0x00000008L
+#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY_MASK 0x00000010L
+#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans_MASK 0x00000020L
+#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans_MASK 0x00000040L
+#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans_MASK 0x00000080L
+#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans_MASK 0x00000100L
+#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans_MASK 0x00000200L
+#define RLC_UTCL1_STATUS_2__RESERVED_MASK 0xFFFFFC00L
+//RLC_LB_THR_CONFIG_2
+#define RLC_LB_THR_CONFIG_2__DATA__SHIFT 0x0
+#define RLC_LB_THR_CONFIG_2__DATA_MASK 0xFFFFFFFFL
+//RLC_LB_THR_CONFIG_3
+#define RLC_LB_THR_CONFIG_3__DATA__SHIFT 0x0
+#define RLC_LB_THR_CONFIG_3__DATA_MASK 0xFFFFFFFFL
+//RLC_LB_THR_CONFIG_4
+#define RLC_LB_THR_CONFIG_4__DATA__SHIFT 0x0
+#define RLC_LB_THR_CONFIG_4__DATA_MASK 0xFFFFFFFFL
+//RLC_SPM_UTCL1_ERROR_1
+#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError__SHIFT 0x0
+#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2
+#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6
+#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError_MASK 0x00000003L
+#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL
+#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L
+//RLC_SPM_UTCL1_ERROR_2
+#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0
+#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL
+//RLC_GPM_UTCL1_TH0_ERROR_1
+#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError__SHIFT 0x0
+#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2
+#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6
+#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError_MASK 0x00000003L
+#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL
+#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L
+//RLC_LB_THR_CONFIG_1
+#define RLC_LB_THR_CONFIG_1__DATA__SHIFT 0x0
+#define RLC_LB_THR_CONFIG_1__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_UTCL1_TH0_ERROR_2
+#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0
+#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL
+//RLC_GPM_UTCL1_TH1_ERROR_1
+#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError__SHIFT 0x0
+#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2
+#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6
+#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError_MASK 0x00000003L
+#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL
+#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L
+//RLC_GPM_UTCL1_TH1_ERROR_2
+#define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0
+#define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL
+//RLC_GPM_UTCL1_TH2_ERROR_1
+#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError__SHIFT 0x0
+#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2
+#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6
+#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError_MASK 0x00000003L
+#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL
+#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L
+//RLC_GPM_UTCL1_TH2_ERROR_2
+#define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0
+#define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL
+//RLC_SEMAPHORE_0
+#define RLC_SEMAPHORE_0__CLIENT_ID__SHIFT 0x0
+#define RLC_SEMAPHORE_0__RESERVED__SHIFT 0x5
+#define RLC_SEMAPHORE_0__CLIENT_ID_MASK 0x0000001FL
+#define RLC_SEMAPHORE_0__RESERVED_MASK 0xFFFFFFE0L
+//RLC_SEMAPHORE_1
+#define RLC_SEMAPHORE_1__CLIENT_ID__SHIFT 0x0
+#define RLC_SEMAPHORE_1__RESERVED__SHIFT 0x5
+#define RLC_SEMAPHORE_1__CLIENT_ID_MASK 0x0000001FL
+#define RLC_SEMAPHORE_1__RESERVED_MASK 0xFFFFFFE0L
+//RLC_CP_EOF_INT
+#define RLC_CP_EOF_INT__INTERRUPT__SHIFT 0x0
+#define RLC_CP_EOF_INT__RESERVED__SHIFT 0x1
+#define RLC_CP_EOF_INT__INTERRUPT_MASK 0x00000001L
+#define RLC_CP_EOF_INT__RESERVED_MASK 0xFFFFFFFEL
+//RLC_CP_EOF_INT_CNT
+#define RLC_CP_EOF_INT_CNT__CNT__SHIFT 0x0
+#define RLC_CP_EOF_INT_CNT__CNT_MASK 0xFFFFFFFFL
+//RLC_SPARE_INT
+#define RLC_SPARE_INT__INTERRUPT__SHIFT 0x0
+#define RLC_SPARE_INT__RESERVED__SHIFT 0x1
+#define RLC_SPARE_INT__INTERRUPT_MASK 0x00000001L
+#define RLC_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL
+//RLC_PREWALKER_UTCL1_CNTL
+#define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
+#define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
+#define RLC_PREWALKER_UTCL1_CNTL__BYPASS__SHIFT 0x19
+#define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
+#define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
+#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
+#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
+#define RLC_PREWALKER_UTCL1_CNTL__RESERVED__SHIFT 0x1e
+#define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
+#define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
+#define RLC_PREWALKER_UTCL1_CNTL__BYPASS_MASK 0x02000000L
+#define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
+#define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
+#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
+#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
+#define RLC_PREWALKER_UTCL1_CNTL__RESERVED_MASK 0xC0000000L
+//RLC_PREWALKER_UTCL1_TRIG
+#define RLC_PREWALKER_UTCL1_TRIG__VALID__SHIFT 0x0
+#define RLC_PREWALKER_UTCL1_TRIG__VMID__SHIFT 0x1
+#define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE__SHIFT 0x5
+#define RLC_PREWALKER_UTCL1_TRIG__READ_PERM__SHIFT 0x6
+#define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM__SHIFT 0x7
+#define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM__SHIFT 0x8
+#define RLC_PREWALKER_UTCL1_TRIG__RESERVED__SHIFT 0x9
+#define RLC_PREWALKER_UTCL1_TRIG__READY__SHIFT 0x1f
+#define RLC_PREWALKER_UTCL1_TRIG__VALID_MASK 0x00000001L
+#define RLC_PREWALKER_UTCL1_TRIG__VMID_MASK 0x0000001EL
+#define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE_MASK 0x00000020L
+#define RLC_PREWALKER_UTCL1_TRIG__READ_PERM_MASK 0x00000040L
+#define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM_MASK 0x00000080L
+#define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM_MASK 0x00000100L
+#define RLC_PREWALKER_UTCL1_TRIG__RESERVED_MASK 0x7FFFFE00L
+#define RLC_PREWALKER_UTCL1_TRIG__READY_MASK 0x80000000L
+//RLC_PREWALKER_UTCL1_ADDR_LSB
+#define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB__SHIFT 0x0
+#define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB_MASK 0xFFFFFFFFL
+//RLC_PREWALKER_UTCL1_ADDR_MSB
+#define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB__SHIFT 0x0
+#define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB_MASK 0x0000FFFFL
+//RLC_PREWALKER_UTCL1_SIZE_LSB
+#define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB__SHIFT 0x0
+#define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB_MASK 0xFFFFFFFFL
+//RLC_PREWALKER_UTCL1_SIZE_MSB
+#define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB__SHIFT 0x0
+#define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB_MASK 0x00000003L
+//RLC_DSM_TRIG
+#define RLC_DSM_TRIG__START__SHIFT 0x0
+#define RLC_DSM_TRIG__START_MASK 0x00000001L
+//RLC_UTCL1_STATUS
+#define RLC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
+#define RLC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
+#define RLC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
+#define RLC_UTCL1_STATUS__RESERVED__SHIFT 0x3
+#define RLC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
+#define RLC_UTCL1_STATUS__RESERVED_1__SHIFT 0xe
+#define RLC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
+#define RLC_UTCL1_STATUS__RESERVED_2__SHIFT 0x16
+#define RLC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
+#define RLC_UTCL1_STATUS__RESERVED_3__SHIFT 0x1e
+#define RLC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
+#define RLC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
+#define RLC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
+#define RLC_UTCL1_STATUS__RESERVED_MASK 0x000000F8L
+#define RLC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
+#define RLC_UTCL1_STATUS__RESERVED_1_MASK 0x0000C000L
+#define RLC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
+#define RLC_UTCL1_STATUS__RESERVED_2_MASK 0x00C00000L
+#define RLC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
+#define RLC_UTCL1_STATUS__RESERVED_3_MASK 0xC0000000L
+//RLC_R2I_CNTL_0
+#define RLC_R2I_CNTL_0__Data__SHIFT 0x0
+#define RLC_R2I_CNTL_0__Data_MASK 0xFFFFFFFFL
+//RLC_R2I_CNTL_1
+#define RLC_R2I_CNTL_1__Data__SHIFT 0x0
+#define RLC_R2I_CNTL_1__Data_MASK 0xFFFFFFFFL
+//RLC_R2I_CNTL_2
+#define RLC_R2I_CNTL_2__Data__SHIFT 0x0
+#define RLC_R2I_CNTL_2__Data_MASK 0xFFFFFFFFL
+//RLC_R2I_CNTL_3
+#define RLC_R2I_CNTL_3__Data__SHIFT 0x0
+#define RLC_R2I_CNTL_3__Data_MASK 0xFFFFFFFFL
+//RLC_UTCL2_CNTL
+#define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x0
+#define RLC_UTCL2_CNTL__RESERVED__SHIFT 0x1
+#define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE_MASK 0x00000001L
+#define RLC_UTCL2_CNTL__RESERVED_MASK 0xFFFFFFFEL
+//RLC_LBPW_CU_STAT
+#define RLC_LBPW_CU_STAT__MAX_CU__SHIFT 0x0
+#define RLC_LBPW_CU_STAT__ON_CU__SHIFT 0x10
+#define RLC_LBPW_CU_STAT__MAX_CU_MASK 0x0000FFFFL
+#define RLC_LBPW_CU_STAT__ON_CU_MASK 0xFFFF0000L
+//RLC_DS_CNTL
+#define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK__SHIFT 0x0
+#define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK__SHIFT 0x1
+#define RLC_DS_CNTL__RESRVED__SHIFT 0x2
+#define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK__SHIFT 0x10
+#define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK__SHIFT 0x11
+#define RLC_DS_CNTL__RESRVED_1__SHIFT 0x12
+#define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK_MASK 0x00000001L
+#define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK_MASK 0x00000002L
+#define RLC_DS_CNTL__RESRVED_MASK 0x0000FFFCL
+#define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK_MASK 0x00010000L
+#define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK_MASK 0x00020000L
+#define RLC_DS_CNTL__RESRVED_1_MASK 0xFFFC0000L
+//RLC_GPM_INT_STAT_TH0
+#define RLC_GPM_INT_STAT_TH0__STATUS__SHIFT 0x0
+#define RLC_GPM_INT_STAT_TH0__STATUS_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_13
+#define RLC_GPM_GENERAL_13__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_13__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_14
+#define RLC_GPM_GENERAL_14__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_14__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_15
+#define RLC_GPM_GENERAL_15__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_15__DATA_MASK 0xFFFFFFFFL
+//RLC_SPARE_INT_1
+#define RLC_SPARE_INT_1__INTERRUPT__SHIFT 0x0
+#define RLC_SPARE_INT_1__RESERVED__SHIFT 0x1
+#define RLC_SPARE_INT_1__INTERRUPT_MASK 0x00000001L
+#define RLC_SPARE_INT_1__RESERVED_MASK 0xFFFFFFFEL
+//RLC_RLCV_SPARE_INT_1
+#define RLC_RLCV_SPARE_INT_1__INTERRUPT__SHIFT 0x0
+#define RLC_RLCV_SPARE_INT_1__RESERVED__SHIFT 0x1
+#define RLC_RLCV_SPARE_INT_1__INTERRUPT_MASK 0x00000001L
+#define RLC_RLCV_SPARE_INT_1__RESERVED_MASK 0xFFFFFFFEL
+//RLC_SEMAPHORE_2
+#define RLC_SEMAPHORE_2__CLIENT_ID__SHIFT 0x0
+#define RLC_SEMAPHORE_2__RESERVED__SHIFT 0x5
+#define RLC_SEMAPHORE_2__CLIENT_ID_MASK 0x0000001FL
+#define RLC_SEMAPHORE_2__RESERVED_MASK 0xFFFFFFE0L
+//RLC_SEMAPHORE_3
+#define RLC_SEMAPHORE_3__CLIENT_ID__SHIFT 0x0
+#define RLC_SEMAPHORE_3__RESERVED__SHIFT 0x5
+#define RLC_SEMAPHORE_3__CLIENT_ID_MASK 0x0000001FL
+#define RLC_SEMAPHORE_3__RESERVED_MASK 0xFFFFFFE0L
+//RLC_GPU_CLOCK_COUNT_LSB_1
+#define RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB__SHIFT 0x0
+#define RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL
+//RLC_GPU_CLOCK_COUNT_MSB_1
+#define RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB__SHIFT 0x0
+#define RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL
+//RLC_CAPTURE_GPU_CLOCK_COUNT_1
+#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE__SHIFT 0x0
+#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED__SHIFT 0x1
+#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE_MASK 0x00000001L
+#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED_MASK 0xFFFFFFFEL
+//RLC_GPU_CLOCK_COUNT_LSB_2
+#define RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB__SHIFT 0x0
+#define RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL
+//RLC_GPU_CLOCK_COUNT_MSB_2
+#define RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB__SHIFT 0x0
+#define RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL
+//RLC_CAPTURE_GPU_CLOCK_COUNT_2
+#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE__SHIFT 0x0
+#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED__SHIFT 0x1
+#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE_MASK 0x00000001L
+#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED_MASK 0xFFFFFFFEL
+//RLC_CPG_STAT_INVAL
+#define RLC_CPG_STAT_INVAL__CPG_stat_inval__SHIFT 0x0
+#define RLC_CPG_STAT_INVAL__CPG_stat_inval_MASK 0x00000001L
+//RLC_EDC_CNT
+#define RLC_EDC_CNT__RLCG_INSTR_RAM_SEC_COUNT__SHIFT 0x0
+#define RLC_EDC_CNT__RLCG_INSTR_RAM_DED_COUNT__SHIFT 0x2
+#define RLC_EDC_CNT__RLCG_SCRATCH_RAM_SEC_COUNT__SHIFT 0x4
+#define RLC_EDC_CNT__RLCG_SCRATCH_RAM_DED_COUNT__SHIFT 0x6
+#define RLC_EDC_CNT__RLCV_INSTR_RAM_SEC_COUNT__SHIFT 0x8
+#define RLC_EDC_CNT__RLCV_INSTR_RAM_DED_COUNT__SHIFT 0xa
+#define RLC_EDC_CNT__RLCV_SCRATCH_RAM_SEC_COUNT__SHIFT 0xc
+#define RLC_EDC_CNT__RLCV_SCRATCH_RAM_DED_COUNT__SHIFT 0xe
+#define RLC_EDC_CNT__RLC_TCTAG_RAM_SEC_COUNT__SHIFT 0x10
+#define RLC_EDC_CNT__RLC_TCTAG_RAM_DED_COUNT__SHIFT 0x12
+#define RLC_EDC_CNT__RLC_SPM_SCRATCH_RAM_SEC_COUNT__SHIFT 0x14
+#define RLC_EDC_CNT__RLC_SPM_SCRATCH_RAM_DED_COUNT__SHIFT 0x16
+#define RLC_EDC_CNT__RLC_SRM_DATA_RAM_SEC_COUNT__SHIFT 0x18
+#define RLC_EDC_CNT__RLC_SRM_DATA_RAM_DED_COUNT__SHIFT 0x1a
+#define RLC_EDC_CNT__RLC_SRM_ADDR_RAM_SEC_COUNT__SHIFT 0x1c
+#define RLC_EDC_CNT__RLC_SRM_ADDR_RAM_DED_COUNT__SHIFT 0x1e
+#define RLC_EDC_CNT__RLCG_INSTR_RAM_SEC_COUNT_MASK 0x00000003L
+#define RLC_EDC_CNT__RLCG_INSTR_RAM_DED_COUNT_MASK 0x0000000CL
+#define RLC_EDC_CNT__RLCG_SCRATCH_RAM_SEC_COUNT_MASK 0x00000030L
+#define RLC_EDC_CNT__RLCG_SCRATCH_RAM_DED_COUNT_MASK 0x000000C0L
+#define RLC_EDC_CNT__RLCV_INSTR_RAM_SEC_COUNT_MASK 0x00000300L
+#define RLC_EDC_CNT__RLCV_INSTR_RAM_DED_COUNT_MASK 0x00000C00L
+#define RLC_EDC_CNT__RLCV_SCRATCH_RAM_SEC_COUNT_MASK 0x00003000L
+#define RLC_EDC_CNT__RLCV_SCRATCH_RAM_DED_COUNT_MASK 0x0000C000L
+#define RLC_EDC_CNT__RLC_TCTAG_RAM_SEC_COUNT_MASK 0x00030000L
+#define RLC_EDC_CNT__RLC_TCTAG_RAM_DED_COUNT_MASK 0x000C0000L
+#define RLC_EDC_CNT__RLC_SPM_SCRATCH_RAM_SEC_COUNT_MASK 0x00300000L
+#define RLC_EDC_CNT__RLC_SPM_SCRATCH_RAM_DED_COUNT_MASK 0x00C00000L
+#define RLC_EDC_CNT__RLC_SRM_DATA_RAM_SEC_COUNT_MASK 0x03000000L
+#define RLC_EDC_CNT__RLC_SRM_DATA_RAM_DED_COUNT_MASK 0x0C000000L
+#define RLC_EDC_CNT__RLC_SRM_ADDR_RAM_SEC_COUNT_MASK 0x30000000L
+#define RLC_EDC_CNT__RLC_SRM_ADDR_RAM_DED_COUNT_MASK 0xC0000000L
+//RLC_EDC_CNT2
+#define RLC_EDC_CNT2__RLC_SPM_SE0_SCRATCH_RAM_SEC_COUNT__SHIFT 0x0
+#define RLC_EDC_CNT2__RLC_SPM_SE0_SCRATCH_RAM_DED_COUNT__SHIFT 0x2
+#define RLC_EDC_CNT2__RLC_SPM_SE1_SCRATCH_RAM_SEC_COUNT__SHIFT 0x4
+#define RLC_EDC_CNT2__RLC_SPM_SE1_SCRATCH_RAM_DED_COUNT__SHIFT 0x6
+#define RLC_EDC_CNT2__RLC_SPM_SE2_SCRATCH_RAM_SEC_COUNT__SHIFT 0x8
+#define RLC_EDC_CNT2__RLC_SPM_SE2_SCRATCH_RAM_DED_COUNT__SHIFT 0xa
+#define RLC_EDC_CNT2__RLC_SPM_SE3_SCRATCH_RAM_SEC_COUNT__SHIFT 0xc
+#define RLC_EDC_CNT2__RLC_SPM_SE3_SCRATCH_RAM_DED_COUNT__SHIFT 0xe
+#define RLC_EDC_CNT2__RLC_SPM_SE4_SCRATCH_RAM_SEC_COUNT__SHIFT 0x10
+#define RLC_EDC_CNT2__RLC_SPM_SE4_SCRATCH_RAM_DED_COUNT__SHIFT 0x12
+#define RLC_EDC_CNT2__RLC_SPM_SE5_SCRATCH_RAM_SEC_COUNT__SHIFT 0x14
+#define RLC_EDC_CNT2__RLC_SPM_SE5_SCRATCH_RAM_DED_COUNT__SHIFT 0x16
+#define RLC_EDC_CNT2__RLC_SPM_SE6_SCRATCH_RAM_SEC_COUNT__SHIFT 0x18
+#define RLC_EDC_CNT2__RLC_SPM_SE6_SCRATCH_RAM_DED_COUNT__SHIFT 0x1a
+#define RLC_EDC_CNT2__RLC_SPM_SE7_SCRATCH_RAM_SEC_COUNT__SHIFT 0x1c
+#define RLC_EDC_CNT2__RLC_SPM_SE7_SCRATCH_RAM_DED_COUNT__SHIFT 0x1e
+#define RLC_EDC_CNT2__RLC_SPM_SE0_SCRATCH_RAM_SEC_COUNT_MASK 0x00000003L
+#define RLC_EDC_CNT2__RLC_SPM_SE0_SCRATCH_RAM_DED_COUNT_MASK 0x0000000CL
+#define RLC_EDC_CNT2__RLC_SPM_SE1_SCRATCH_RAM_SEC_COUNT_MASK 0x00000030L
+#define RLC_EDC_CNT2__RLC_SPM_SE1_SCRATCH_RAM_DED_COUNT_MASK 0x000000C0L
+#define RLC_EDC_CNT2__RLC_SPM_SE2_SCRATCH_RAM_SEC_COUNT_MASK 0x00000300L
+#define RLC_EDC_CNT2__RLC_SPM_SE2_SCRATCH_RAM_DED_COUNT_MASK 0x00000C00L
+#define RLC_EDC_CNT2__RLC_SPM_SE3_SCRATCH_RAM_SEC_COUNT_MASK 0x00003000L
+#define RLC_EDC_CNT2__RLC_SPM_SE3_SCRATCH_RAM_DED_COUNT_MASK 0x0000C000L
+#define RLC_EDC_CNT2__RLC_SPM_SE4_SCRATCH_RAM_SEC_COUNT_MASK 0x00030000L
+#define RLC_EDC_CNT2__RLC_SPM_SE4_SCRATCH_RAM_DED_COUNT_MASK 0x000C0000L
+#define RLC_EDC_CNT2__RLC_SPM_SE5_SCRATCH_RAM_SEC_COUNT_MASK 0x00300000L
+#define RLC_EDC_CNT2__RLC_SPM_SE5_SCRATCH_RAM_DED_COUNT_MASK 0x00C00000L
+#define RLC_EDC_CNT2__RLC_SPM_SE6_SCRATCH_RAM_SEC_COUNT_MASK 0x03000000L
+#define RLC_EDC_CNT2__RLC_SPM_SE6_SCRATCH_RAM_DED_COUNT_MASK 0x0C000000L
+#define RLC_EDC_CNT2__RLC_SPM_SE7_SCRATCH_RAM_SEC_COUNT_MASK 0x30000000L
+#define RLC_EDC_CNT2__RLC_SPM_SE7_SCRATCH_RAM_DED_COUNT_MASK 0xC0000000L
+//RLC_DSM_CNTL
+#define RLC_DSM_CNTL__RLCG_INSTR_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0
+#define RLC_DSM_CNTL__RLCG_INSTR_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
+#define RLC_DSM_CNTL__RLCG_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0x3
+#define RLC_DSM_CNTL__RLCG_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x5
+#define RLC_DSM_CNTL__RLCV_INSTR_RAM_IRRITATOR_DATA_SEL__SHIFT 0x6
+#define RLC_DSM_CNTL__RLCV_INSTR_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x8
+#define RLC_DSM_CNTL__RLCV_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0x9
+#define RLC_DSM_CNTL__RLCV_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0xb
+#define RLC_DSM_CNTL__RLC_TCTAG_RAM_IRRITATOR_DATA_SEL__SHIFT 0xc
+#define RLC_DSM_CNTL__RLC_TCTAG_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0xe
+#define RLC_DSM_CNTL__RLC_SPM_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0xf
+#define RLC_DSM_CNTL__RLC_SPM_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x11
+#define RLC_DSM_CNTL__RLC_SRM_DATA_RAM_IRRITATOR_DATA_SEL__SHIFT 0x12
+#define RLC_DSM_CNTL__RLC_SRM_DATA_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x14
+#define RLC_DSM_CNTL__RLC_SRM_ADDR_RAM_IRRITATOR_DATA_SEL__SHIFT 0x15
+#define RLC_DSM_CNTL__RLC_SRM_ADDR_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x17
+#define RLC_DSM_CNTL__RLCG_INSTR_RAM_IRRITATOR_DATA_SEL_MASK 0x00000003L
+#define RLC_DSM_CNTL__RLCG_INSTR_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L
+#define RLC_DSM_CNTL__RLCG_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x00000018L
+#define RLC_DSM_CNTL__RLCG_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L
+#define RLC_DSM_CNTL__RLCV_INSTR_RAM_IRRITATOR_DATA_SEL_MASK 0x000000C0L
+#define RLC_DSM_CNTL__RLCV_INSTR_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L
+#define RLC_DSM_CNTL__RLCV_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x00000600L
+#define RLC_DSM_CNTL__RLCV_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L
+#define RLC_DSM_CNTL__RLC_TCTAG_RAM_IRRITATOR_DATA_SEL_MASK 0x00003000L
+#define RLC_DSM_CNTL__RLC_TCTAG_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L
+#define RLC_DSM_CNTL__RLC_SPM_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x00018000L
+#define RLC_DSM_CNTL__RLC_SPM_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L
+#define RLC_DSM_CNTL__RLC_SRM_DATA_RAM_IRRITATOR_DATA_SEL_MASK 0x000C0000L
+#define RLC_DSM_CNTL__RLC_SRM_DATA_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L
+#define RLC_DSM_CNTL__RLC_SRM_ADDR_RAM_IRRITATOR_DATA_SEL_MASK 0x00600000L
+#define RLC_DSM_CNTL__RLC_SRM_ADDR_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L
+//RLC_DSM_CNTLA
+#define RLC_DSM_CNTLA__RLC_SPM_SE0_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0
+#define RLC_DSM_CNTLA__RLC_SPM_SE0_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
+#define RLC_DSM_CNTLA__RLC_SPM_SE1_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0x3
+#define RLC_DSM_CNTLA__RLC_SPM_SE1_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x5
+#define RLC_DSM_CNTLA__RLC_SPM_SE2_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0x6
+#define RLC_DSM_CNTLA__RLC_SPM_SE2_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x8
+#define RLC_DSM_CNTLA__RLC_SPM_SE3_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0x9
+#define RLC_DSM_CNTLA__RLC_SPM_SE3_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0xb
+#define RLC_DSM_CNTLA__RLC_SPM_SE4_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0xc
+#define RLC_DSM_CNTLA__RLC_SPM_SE4_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0xe
+#define RLC_DSM_CNTLA__RLC_SPM_SE5_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0xf
+#define RLC_DSM_CNTLA__RLC_SPM_SE5_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x11
+#define RLC_DSM_CNTLA__RLC_SPM_SE6_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0x12
+#define RLC_DSM_CNTLA__RLC_SPM_SE6_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x14
+#define RLC_DSM_CNTLA__RLC_SPM_SE7_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0x15
+#define RLC_DSM_CNTLA__RLC_SPM_SE7_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x17
+#define RLC_DSM_CNTLA__RLC_SPM_SE0_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x00000003L
+#define RLC_DSM_CNTLA__RLC_SPM_SE0_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L
+#define RLC_DSM_CNTLA__RLC_SPM_SE1_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x00000018L
+#define RLC_DSM_CNTLA__RLC_SPM_SE1_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L
+#define RLC_DSM_CNTLA__RLC_SPM_SE2_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x000000C0L
+#define RLC_DSM_CNTLA__RLC_SPM_SE2_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L
+#define RLC_DSM_CNTLA__RLC_SPM_SE3_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x00000600L
+#define RLC_DSM_CNTLA__RLC_SPM_SE3_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L
+#define RLC_DSM_CNTLA__RLC_SPM_SE4_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x00003000L
+#define RLC_DSM_CNTLA__RLC_SPM_SE4_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L
+#define RLC_DSM_CNTLA__RLC_SPM_SE5_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x00018000L
+#define RLC_DSM_CNTLA__RLC_SPM_SE5_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L
+#define RLC_DSM_CNTLA__RLC_SPM_SE6_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x000C0000L
+#define RLC_DSM_CNTLA__RLC_SPM_SE6_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L
+#define RLC_DSM_CNTLA__RLC_SPM_SE7_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x00600000L
+#define RLC_DSM_CNTLA__RLC_SPM_SE7_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L
+//RLC_DSM_CNTL2
+#define RLC_DSM_CNTL2__RLCG_INSTR_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define RLC_DSM_CNTL2__RLCG_INSTR_RAM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define RLC_DSM_CNTL2__RLCG_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define RLC_DSM_CNTL2__RLCG_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0x5
+#define RLC_DSM_CNTL2__RLCV_INSTR_RAM_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define RLC_DSM_CNTL2__RLCV_INSTR_RAM_SELECT_INJECT_DELAY__SHIFT 0x8
+#define RLC_DSM_CNTL2__RLCV_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define RLC_DSM_CNTL2__RLCV_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0xb
+#define RLC_DSM_CNTL2__RLC_TCTAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define RLC_DSM_CNTL2__RLC_TCTAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe
+#define RLC_DSM_CNTL2__RLC_SPM_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define RLC_DSM_CNTL2__RLC_SPM_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0x11
+#define RLC_DSM_CNTL2__RLC_SRM_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define RLC_DSM_CNTL2__RLC_SRM_DATA_RAM_SELECT_INJECT_DELAY__SHIFT 0x14
+#define RLC_DSM_CNTL2__RLC_SRM_ADDR_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15
+#define RLC_DSM_CNTL2__RLC_SRM_ADDR_RAM_SELECT_INJECT_DELAY__SHIFT 0x17
+#define RLC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
+#define RLC_DSM_CNTL2__RLCG_INSTR_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define RLC_DSM_CNTL2__RLCG_INSTR_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define RLC_DSM_CNTL2__RLCG_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define RLC_DSM_CNTL2__RLCG_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define RLC_DSM_CNTL2__RLCV_INSTR_RAM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define RLC_DSM_CNTL2__RLCV_INSTR_RAM_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define RLC_DSM_CNTL2__RLCV_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define RLC_DSM_CNTL2__RLCV_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define RLC_DSM_CNTL2__RLC_TCTAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define RLC_DSM_CNTL2__RLC_TCTAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define RLC_DSM_CNTL2__RLC_SPM_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define RLC_DSM_CNTL2__RLC_SPM_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define RLC_DSM_CNTL2__RLC_SRM_DATA_RAM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define RLC_DSM_CNTL2__RLC_SRM_DATA_RAM_SELECT_INJECT_DELAY_MASK 0x00100000L
+#define RLC_DSM_CNTL2__RLC_SRM_ADDR_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L
+#define RLC_DSM_CNTL2__RLC_SRM_ADDR_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L
+#define RLC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
+//RLC_DSM_CNTL2A
+#define RLC_DSM_CNTL2A__RLC_SPM_SE0_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define RLC_DSM_CNTL2A__RLC_SPM_SE0_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define RLC_DSM_CNTL2A__RLC_SPM_SE1_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define RLC_DSM_CNTL2A__RLC_SPM_SE1_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0x5
+#define RLC_DSM_CNTL2A__RLC_SPM_SE2_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define RLC_DSM_CNTL2A__RLC_SPM_SE2_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0x8
+#define RLC_DSM_CNTL2A__RLC_SPM_SE3_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define RLC_DSM_CNTL2A__RLC_SPM_SE3_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0xb
+#define RLC_DSM_CNTL2A__RLC_SPM_SE4_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define RLC_DSM_CNTL2A__RLC_SPM_SE4_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0xe
+#define RLC_DSM_CNTL2A__RLC_SPM_SE5_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define RLC_DSM_CNTL2A__RLC_SPM_SE5_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0x11
+#define RLC_DSM_CNTL2A__RLC_SPM_SE6_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define RLC_DSM_CNTL2A__RLC_SPM_SE6_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0x14
+#define RLC_DSM_CNTL2A__RLC_SPM_SE7_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15
+#define RLC_DSM_CNTL2A__RLC_SPM_SE7_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0x17
+#define RLC_DSM_CNTL2A__RLC_SPM_SE0_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define RLC_DSM_CNTL2A__RLC_SPM_SE0_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define RLC_DSM_CNTL2A__RLC_SPM_SE1_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define RLC_DSM_CNTL2A__RLC_SPM_SE1_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define RLC_DSM_CNTL2A__RLC_SPM_SE2_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define RLC_DSM_CNTL2A__RLC_SPM_SE2_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define RLC_DSM_CNTL2A__RLC_SPM_SE3_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define RLC_DSM_CNTL2A__RLC_SPM_SE3_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define RLC_DSM_CNTL2A__RLC_SPM_SE4_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define RLC_DSM_CNTL2A__RLC_SPM_SE4_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define RLC_DSM_CNTL2A__RLC_SPM_SE5_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define RLC_DSM_CNTL2A__RLC_SPM_SE5_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define RLC_DSM_CNTL2A__RLC_SPM_SE6_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define RLC_DSM_CNTL2A__RLC_SPM_SE6_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00100000L
+#define RLC_DSM_CNTL2A__RLC_SPM_SE7_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L
+#define RLC_DSM_CNTL2A__RLC_SPM_SE7_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L
+//RLC_RLCV_SPARE_INT
+#define RLC_RLCV_SPARE_INT__INTERRUPT__SHIFT 0x0
+#define RLC_RLCV_SPARE_INT__RESERVED__SHIFT 0x1
+#define RLC_RLCV_SPARE_INT__INTERRUPT_MASK 0x00000001L
+#define RLC_RLCV_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL
+
+
+// addressBlock: gc_rmi_rmidec
+//RMI_GENERAL_CNTL
+#define RMI_GENERAL_CNTL__BURST_DISABLE__SHIFT 0x0
+#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE__SHIFT 0x1
+#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG__SHIFT 0x11
+#define RMI_GENERAL_CNTL__RB0_HARVEST_EN__SHIFT 0x13
+#define RMI_GENERAL_CNTL__RB1_HARVEST_EN__SHIFT 0x14
+#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE__SHIFT 0x15
+#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE__SHIFT 0x19
+#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK__SHIFT 0x1a
+#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK__SHIFT 0x1b
+#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK__SHIFT 0x1c
+#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK__SHIFT 0x1d
+#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK__SHIFT 0x1e
+#define RMI_GENERAL_CNTL__BURST_DISABLE_MASK 0x00000001L
+#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE_MASK 0x0001FFFEL
+#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_MASK 0x00060000L
+#define RMI_GENERAL_CNTL__RB0_HARVEST_EN_MASK 0x00080000L
+#define RMI_GENERAL_CNTL__RB1_HARVEST_EN_MASK 0x00100000L
+#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE_MASK 0x01E00000L
+#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE_MASK 0x02000000L
+#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK_MASK 0x04000000L
+#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK_MASK 0x08000000L
+#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK_MASK 0x10000000L
+#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK_MASK 0x20000000L
+#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK_MASK 0x40000000L
+//RMI_GENERAL_CNTL1
+#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE__SHIFT 0x0
+#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE__SHIFT 0x4
+#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE__SHIFT 0x6
+#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK__SHIFT 0x8
+#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE__SHIFT 0x9
+#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT 0xa
+#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN__SHIFT 0xb
+#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN__SHIFT 0xc
+#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE_MASK 0x0000000FL
+#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE_MASK 0x00000030L
+#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE_MASK 0x000000C0L
+#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK_MASK 0x00000100L
+#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE_MASK 0x00000200L
+#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_MASK 0x00000400L
+#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN_MASK 0x00000800L
+#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN_MASK 0x00001000L
+//RMI_GENERAL_STATUS
+#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED__SHIFT 0x0
+#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR__SHIFT 0x1
+#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR__SHIFT 0x2
+#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR__SHIFT 0x3
+#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR__SHIFT 0x4
+#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY__SHIFT 0x5
+#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY__SHIFT 0x6
+#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY__SHIFT 0x7
+#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY__SHIFT 0x8
+#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY__SHIFT 0x9
+#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT 0xa
+#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xb
+#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xc
+#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY__SHIFT 0xd
+#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY__SHIFT 0xe
+#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY__SHIFT 0xf
+#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x10
+#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x11
+#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY__SHIFT 0x12
+#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY__SHIFT 0x13
+#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY__SHIFT 0x14
+#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED__SHIFT 0x15
+#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY__SHIFT 0x1d
+#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL__SHIFT 0x1e
+#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR__SHIFT 0x1f
+#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED_MASK 0x00000001L
+#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR_MASK 0x00000002L
+#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR_MASK 0x00000004L
+#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR_MASK 0x00000008L
+#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR_MASK 0x00000010L
+#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY_MASK 0x00000020L
+#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY_MASK 0x00000040L
+#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY_MASK 0x00000080L
+#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY_MASK 0x00000100L
+#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY_MASK 0x00000200L
+#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY_MASK 0x00000400L
+#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00000800L
+#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00001000L
+#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY_MASK 0x00002000L
+#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY_MASK 0x00004000L
+#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY_MASK 0x00008000L
+#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00010000L
+#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00020000L
+#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY_MASK 0x00040000L
+#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY_MASK 0x00080000L
+#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY_MASK 0x00100000L
+#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED_MASK 0x1FE00000L
+#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY_MASK 0x20000000L
+#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL_MASK 0x40000000L
+#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK 0x80000000L
+//RMI_SUBBLOCK_STATUS0
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0__SHIFT 0x0
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0__SHIFT 0x7
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0__SHIFT 0x8
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1__SHIFT 0x9
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1__SHIFT 0x10
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1__SHIFT 0x11
+#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT__SHIFT 0x12
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0_MASK 0x0000007FL
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0_MASK 0x00000080L
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0_MASK 0x00000100L
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1_MASK 0x0000FE00L
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1_MASK 0x00010000L
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1_MASK 0x00020000L
+#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT_MASK 0x0FFC0000L
+//RMI_SUBBLOCK_STATUS1
+#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE__SHIFT 0x0
+#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT 0xa
+#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT__SHIFT 0x14
+#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE_MASK 0x000003FFL
+#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE_MASK 0x000FFC00L
+#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT_MASK 0x3FF00000L
+//RMI_SUBBLOCK_STATUS2
+#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED__SHIFT 0x0
+#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED__SHIFT 0x9
+#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED_MASK 0x000001FFL
+#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED_MASK 0x0003FE00L
+//RMI_SUBBLOCK_STATUS3
+#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL__SHIFT 0x0
+#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT 0xa
+#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL_MASK 0x000003FFL
+#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL_MASK 0x000FFC00L
+//RMI_XBAR_CONFIG
+#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE__SHIFT 0x0
+#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE__SHIFT 0x2
+#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE__SHIFT 0x6
+#define RMI_XBAR_CONFIG__ARBITER_DIS__SHIFT 0x7
+#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ__SHIFT 0x8
+#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE__SHIFT 0xc
+#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0__SHIFT 0xd
+#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1__SHIFT 0xe
+#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE_MASK 0x00000003L
+#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE_MASK 0x0000003CL
+#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE_MASK 0x00000040L
+#define RMI_XBAR_CONFIG__ARBITER_DIS_MASK 0x00000080L
+#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_MASK 0x00000F00L
+#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE_MASK 0x00001000L
+#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0_MASK 0x00002000L
+#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1_MASK 0x00004000L
+//RMI_PROBE_POP_LOGIC_CNTL
+#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH__SHIFT 0x0
+#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS__SHIFT 0x7
+#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2__SHIFT 0x8
+#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT 0xa
+#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS__SHIFT 0x11
+#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH_MASK 0x0000007FL
+#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS_MASK 0x00000080L
+#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2_MASK 0x00000300L
+#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH_MASK 0x0001FC00L
+#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS_MASK 0x00020000L
+//RMI_UTC_XNACK_N_MISC_CNTL
+#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC__SHIFT 0x0
+#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE__SHIFT 0x8
+#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE__SHIFT 0xc
+#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE__SHIFT 0xd
+#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC_MASK 0x000000FFL
+#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE_MASK 0x00000F00L
+#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE_MASK 0x00001000L
+#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE_MASK 0x00002000L
+//RMI_DEMUX_CNTL
+#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL__SHIFT 0x0
+#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x1
+#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x4
+#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x6
+#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE__SHIFT 0xe
+#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL__SHIFT 0x10
+#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x11
+#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x14
+#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x16
+#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE__SHIFT 0x1e
+#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_MASK 0x00000001L
+#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000002L
+#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE_MASK 0x00000030L
+#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE_MASK 0x00003FC0L
+#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_MASK 0x0000C000L
+#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_MASK 0x00010000L
+#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00020000L
+#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00300000L
+#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE_MASK 0x3FC00000L
+#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_MASK 0xC0000000L
+//RMI_UTCL1_CNTL1
+#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
+#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
+#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
+#define RMI_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
+#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
+#define RMI_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
+#define RMI_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10
+#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
+#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
+#define RMI_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13
+#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17
+#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18
+#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
+#define RMI_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
+#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
+#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
+#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
+#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
+#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
+#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
+#define RMI_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
+#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
+#define RMI_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
+#define RMI_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L
+#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
+#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
+#define RMI_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L
+#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L
+#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L
+#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
+#define RMI_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
+#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
+#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
+#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
+//RMI_UTCL1_CNTL2
+#define RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT 0x0
+#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
+#define RMI_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
+#define RMI_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb
+#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
+#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
+#define RMI_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
+#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
+#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE__SHIFT 0x10
+#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
+#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR__SHIFT 0x13
+#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID__SHIFT 0x14
+#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID__SHIFT 0x15
+#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ__SHIFT 0x19
+#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
+#define RMI_UTCL1_CNTL2__UTC_SPARE_MASK 0x000000FFL
+#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
+#define RMI_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
+#define RMI_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L
+#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
+#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
+#define RMI_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
+#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
+#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE_MASK 0x00030000L
+#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
+#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK 0x00080000L
+#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
+#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID_MASK 0x01E00000L
+#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ_MASK 0x02000000L
+#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
+//RMI_UTC_UNIT_CONFIG
+#define RMI_UTC_UNIT_CONFIG__TMZ_REQ_EN__SHIFT 0x0
+#define RMI_UTC_UNIT_CONFIG__TMZ_REQ_EN_MASK 0x0000FFFFL
+//RMI_TCIW_FORMATTER0_CNTL
+#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE__SHIFT 0x0
+#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW__SHIFT 0x1
+#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9
+#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA__SHIFT 0x13
+#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b
+#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE__SHIFT 0x1c
+#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS__SHIFT 0x1d
+#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST__SHIFT 0x1e
+#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA__SHIFT 0x1f
+#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE_MASK 0x00000001L
+#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW_MASK 0x000001FEL
+#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L
+#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_MASK 0x07F80000L
+#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L
+#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE_MASK 0x10000000L
+#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS_MASK 0x20000000L
+#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST_MASK 0x40000000L
+#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA_MASK 0x80000000L
+//RMI_TCIW_FORMATTER1_CNTL
+#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE__SHIFT 0x0
+#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW__SHIFT 0x1
+#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9
+#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA__SHIFT 0x13
+#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b
+#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE__SHIFT 0x1c
+#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS__SHIFT 0x1d
+#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST__SHIFT 0x1e
+#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA__SHIFT 0x1f
+#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE_MASK 0x00000001L
+#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW_MASK 0x000001FEL
+#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L
+#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_MASK 0x07F80000L
+#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L
+#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE_MASK 0x10000000L
+#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS_MASK 0x20000000L
+#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST_MASK 0x40000000L
+#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA_MASK 0x80000000L
+//RMI_SCOREBOARD_CNTL
+#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH__SHIFT 0x0
+#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0__SHIFT 0x1
+#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH__SHIFT 0x2
+#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1__SHIFT 0x3
+#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1__SHIFT 0x4
+#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN__SHIFT 0x5
+#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE__SHIFT 0x6
+#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0__SHIFT 0x7
+#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN__SHIFT 0x8
+#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE__SHIFT 0x9
+#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH_MASK 0x00000001L
+#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0_MASK 0x00000002L
+#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH_MASK 0x00000004L
+#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1_MASK 0x00000008L
+#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1_MASK 0x00000010L
+#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN_MASK 0x00000020L
+#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE_MASK 0x00000040L
+#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0_MASK 0x00000080L
+#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN_MASK 0x00000100L
+#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE_MASK 0x001FFE00L
+//RMI_SCOREBOARD_STATUS0
+#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID__SHIFT 0x0
+#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG__SHIFT 0x1
+#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID__SHIFT 0x2
+#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE__SHIFT 0x12
+#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE__SHIFT 0x13
+#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE__SHIFT 0x14
+#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE__SHIFT 0x15
+#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID_MASK 0x00000001L
+#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG_MASK 0x00000002L
+#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID_MASK 0x0003FFFCL
+#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE_MASK 0x00040000L
+#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE_MASK 0x00080000L
+#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE_MASK 0x00100000L
+#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE_MASK 0x00200000L
+//RMI_SCOREBOARD_STATUS1
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0__SHIFT 0x0
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0__SHIFT 0xc
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0__SHIFT 0xd
+#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED__SHIFT 0xe
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1__SHIFT 0xf
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1__SHIFT 0x1b
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1__SHIFT 0x1c
+#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1__SHIFT 0x1d
+#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0__SHIFT 0x1e
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0_MASK 0x00000FFFL
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0_MASK 0x00001000L
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0_MASK 0x00002000L
+#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED_MASK 0x00004000L
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1_MASK 0x07FF8000L
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1_MASK 0x08000000L
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1_MASK 0x10000000L
+#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1_MASK 0x20000000L
+#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0_MASK 0x40000000L
+//RMI_SCOREBOARD_STATUS2
+#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0__SHIFT 0x0
+#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0__SHIFT 0xc
+#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1__SHIFT 0xd
+#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1__SHIFT 0x19
+#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1__SHIFT 0x1a
+#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0__SHIFT 0x1b
+#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0__SHIFT 0x1c
+#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1__SHIFT 0x1d
+#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0__SHIFT 0x1e
+#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1__SHIFT 0x1f
+#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0_MASK 0x00000FFFL
+#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0_MASK 0x00001000L
+#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1_MASK 0x01FFE000L
+#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1_MASK 0x02000000L
+#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1_MASK 0x04000000L
+#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0_MASK 0x08000000L
+#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0_MASK 0x10000000L
+#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1_MASK 0x20000000L
+#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0_MASK 0x40000000L
+#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1_MASK 0x80000000L
+//RMI_XBAR_ARBITER_CONFIG
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE__SHIFT 0x0
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x2
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL__SHIFT 0x3
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x4
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x6
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x8
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE__SHIFT 0x10
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x12
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL__SHIFT 0x13
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x14
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x16
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x18
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_MASK 0x00000003L
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00000004L
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_MASK 0x00000008L
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000010L
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE_MASK 0x000000C0L
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE_MASK 0x0000FF00L
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_MASK 0x00030000L
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00040000L
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_MASK 0x00080000L
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00100000L
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00C00000L
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE_MASK 0xFF000000L
+//RMI_XBAR_ARBITER_CONFIG_1
+#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD__SHIFT 0x0
+#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR__SHIFT 0x8
+#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD__SHIFT 0x10
+#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR__SHIFT 0x18
+#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD_MASK 0x000000FFL
+#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR_MASK 0x0000FF00L
+#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD_MASK 0x00FF0000L
+#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR_MASK 0xFF000000L
+//RMI_CLOCK_CNTRL
+#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK__SHIFT 0x0
+#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK__SHIFT 0x5
+#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT 0xa
+#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK__SHIFT 0xf
+#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK__SHIFT 0x14
+#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK__SHIFT 0x19
+#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK_MASK 0x0000001FL
+#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK_MASK 0x000003E0L
+#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK_MASK 0x00007C00L
+#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK_MASK 0x000F8000L
+#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK_MASK 0x01F00000L
+#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK_MASK 0x3E000000L
+//RMI_UTCL1_STATUS
+#define RMI_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
+#define RMI_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
+#define RMI_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
+#define RMI_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
+#define RMI_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
+#define RMI_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
+//RMI_SPARE
+#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING__SHIFT 0x0
+#define RMI_SPARE__SPARE_BIT_1__SHIFT 0x1
+#define RMI_SPARE__SPARE_BIT_2__SHIFT 0x2
+#define RMI_SPARE__SPARE_BIT_3__SHIFT 0x3
+#define RMI_SPARE__SPARE_BIT_4__SHIFT 0x4
+#define RMI_SPARE__SPARE_BIT_5__SHIFT 0x5
+#define RMI_SPARE__SPARE_BIT_6__SHIFT 0x6
+#define RMI_SPARE__SPARE_BIT_7__SHIFT 0x7
+#define RMI_SPARE__SPARE_BIT_8_0__SHIFT 0x8
+#define RMI_SPARE__SPARE_BIT_16_0__SHIFT 0x10
+#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING_MASK 0x00000001L
+#define RMI_SPARE__SPARE_BIT_1_MASK 0x00000002L
+#define RMI_SPARE__SPARE_BIT_2_MASK 0x00000004L
+#define RMI_SPARE__SPARE_BIT_3_MASK 0x00000008L
+#define RMI_SPARE__SPARE_BIT_4_MASK 0x00000010L
+#define RMI_SPARE__SPARE_BIT_5_MASK 0x00000020L
+#define RMI_SPARE__SPARE_BIT_6_MASK 0x00000040L
+#define RMI_SPARE__SPARE_BIT_7_MASK 0x00000080L
+#define RMI_SPARE__SPARE_BIT_8_0_MASK 0x0000FF00L
+#define RMI_SPARE__SPARE_BIT_16_0_MASK 0xFFFF0000L
+//RMI_SPARE_1
+#define RMI_SPARE_1__SPARE_BIT_8__SHIFT 0x0
+#define RMI_SPARE_1__SPARE_BIT_9__SHIFT 0x1
+#define RMI_SPARE_1__SPARE_BIT_10__SHIFT 0x2
+#define RMI_SPARE_1__SPARE_BIT_11__SHIFT 0x3
+#define RMI_SPARE_1__SPARE_BIT_12__SHIFT 0x4
+#define RMI_SPARE_1__SPARE_BIT_13__SHIFT 0x5
+#define RMI_SPARE_1__SPARE_BIT_14__SHIFT 0x6
+#define RMI_SPARE_1__SPARE_BIT_15__SHIFT 0x7
+#define RMI_SPARE_1__SPARE_BIT_8_1__SHIFT 0x8
+#define RMI_SPARE_1__SPARE_BIT_16_1__SHIFT 0x10
+#define RMI_SPARE_1__SPARE_BIT_8_MASK 0x00000001L
+#define RMI_SPARE_1__SPARE_BIT_9_MASK 0x00000002L
+#define RMI_SPARE_1__SPARE_BIT_10_MASK 0x00000004L
+#define RMI_SPARE_1__SPARE_BIT_11_MASK 0x00000008L
+#define RMI_SPARE_1__SPARE_BIT_12_MASK 0x00000010L
+#define RMI_SPARE_1__SPARE_BIT_13_MASK 0x00000020L
+#define RMI_SPARE_1__SPARE_BIT_14_MASK 0x00000040L
+#define RMI_SPARE_1__SPARE_BIT_15_MASK 0x00000080L
+#define RMI_SPARE_1__SPARE_BIT_8_1_MASK 0x0000FF00L
+#define RMI_SPARE_1__SPARE_BIT_16_1_MASK 0xFFFF0000L
+//RMI_SPARE_2
+#define RMI_SPARE_2__SPARE_BIT_16__SHIFT 0x0
+#define RMI_SPARE_2__SPARE_BIT_17__SHIFT 0x1
+#define RMI_SPARE_2__SPARE_BIT_18__SHIFT 0x2
+#define RMI_SPARE_2__SPARE_BIT_19__SHIFT 0x3
+#define RMI_SPARE_2__SPARE_BIT_20__SHIFT 0x4
+#define RMI_SPARE_2__SPARE_BIT_21__SHIFT 0x5
+#define RMI_SPARE_2__SPARE_BIT_22__SHIFT 0x6
+#define RMI_SPARE_2__SPARE_BIT_23__SHIFT 0x7
+#define RMI_SPARE_2__SPARE_BIT_4_0__SHIFT 0x8
+#define RMI_SPARE_2__SPARE_BIT_4_1__SHIFT 0xc
+#define RMI_SPARE_2__SPARE_BIT_8_2__SHIFT 0x10
+#define RMI_SPARE_2__SPARE_BIT_8_3__SHIFT 0x18
+#define RMI_SPARE_2__SPARE_BIT_16_MASK 0x00000001L
+#define RMI_SPARE_2__SPARE_BIT_17_MASK 0x00000002L
+#define RMI_SPARE_2__SPARE_BIT_18_MASK 0x00000004L
+#define RMI_SPARE_2__SPARE_BIT_19_MASK 0x00000008L
+#define RMI_SPARE_2__SPARE_BIT_20_MASK 0x00000010L
+#define RMI_SPARE_2__SPARE_BIT_21_MASK 0x00000020L
+#define RMI_SPARE_2__SPARE_BIT_22_MASK 0x00000040L
+#define RMI_SPARE_2__SPARE_BIT_23_MASK 0x00000080L
+#define RMI_SPARE_2__SPARE_BIT_4_0_MASK 0x00000F00L
+#define RMI_SPARE_2__SPARE_BIT_4_1_MASK 0x0000F000L
+#define RMI_SPARE_2__SPARE_BIT_8_2_MASK 0x00FF0000L
+#define RMI_SPARE_2__SPARE_BIT_8_3_MASK 0xFF000000L
+
+
+// addressBlock: gc_shdec
+//SPI_SHADER_PGM_RSRC3_PS
+#define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE__SHIFT 0x1a
+#define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0x0000FFFFL
+#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK 0x003F0000L
+#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L
+#define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE_MASK 0x3C000000L
+//SPI_SHADER_PGM_LO_PS
+#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_HI_PS
+#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0xFFL
+//SPI_SHADER_PGM_RSRC1_PS
+#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x15
+#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x17
+#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18
+#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL__SHIFT 0x1d
+#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x0000003FL
+#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x000003C0L
+#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0x00000C00L
+#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0x000FF000L
+#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x00100000L
+#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x00200000L
+#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x00800000L
+#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x01000000L
+#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL_MASK 0x20000000L
+//SPI_SHADER_PGM_RSRC2_PS
+#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x8
+#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID__SHIFT 0x19
+#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION__SHIFT 0x1a
+#define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0__SHIFT 0x1b
+#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB__SHIFT 0x1c
+#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x00000001L
+#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x0000003EL
+#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x00000040L
+#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x00000080L
+#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0x0000FF00L
+#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x01FF0000L
+#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID_MASK 0x02000000L
+#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION_MASK 0x04000000L
+#define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0_MASK 0x08000000L
+#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB_MASK 0x10000000L
+//SPI_SHADER_USER_DATA_PS_0
+#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_1
+#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_2
+#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_3
+#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_4
+#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_5
+#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_6
+#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_7
+#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_8
+#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_9
+#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_10
+#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_11
+#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_12
+#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_13
+#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_14
+#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_15
+#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_16
+#define SPI_SHADER_USER_DATA_PS_16__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_16__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_17
+#define SPI_SHADER_USER_DATA_PS_17__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_17__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_18
+#define SPI_SHADER_USER_DATA_PS_18__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_18__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_19
+#define SPI_SHADER_USER_DATA_PS_19__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_19__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_20
+#define SPI_SHADER_USER_DATA_PS_20__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_20__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_21
+#define SPI_SHADER_USER_DATA_PS_21__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_21__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_22
+#define SPI_SHADER_USER_DATA_PS_22__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_22__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_23
+#define SPI_SHADER_USER_DATA_PS_23__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_23__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_24
+#define SPI_SHADER_USER_DATA_PS_24__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_24__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_25
+#define SPI_SHADER_USER_DATA_PS_25__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_25__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_26
+#define SPI_SHADER_USER_DATA_PS_26__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_26__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_27
+#define SPI_SHADER_USER_DATA_PS_27__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_27__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_28
+#define SPI_SHADER_USER_DATA_PS_28__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_28__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_29
+#define SPI_SHADER_USER_DATA_PS_29__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_29__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_30
+#define SPI_SHADER_USER_DATA_PS_30__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_30__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_31
+#define SPI_SHADER_USER_DATA_PS_31__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_31__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_RSRC3_VS
+#define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE__SHIFT 0x1a
+#define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK 0x0000FFFFL
+#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK 0x003F0000L
+#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L
+#define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE_MASK 0x3C000000L
+//SPI_SHADER_LATE_ALLOC_VS
+#define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT 0x0
+#define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK 0x0000003FL
+//SPI_SHADER_PGM_LO_VS
+#define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_HI_VS
+#define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0xFFL
+//SPI_SHADER_PGM_RSRC1_VS
+#define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x15
+#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x17
+#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x18
+#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x1a
+#define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL__SHIFT 0x1f
+#define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x0000003FL
+#define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x000003C0L
+#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0x00000C00L
+#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0x000FF000L
+#define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x00100000L
+#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x00200000L
+#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x00800000L
+#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x03000000L
+#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x04000000L
+#define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL_MASK 0x80000000L
+//SPI_SHADER_PGM_RSRC2_VS
+#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x8
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x9
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0xb
+#define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0xd
+#define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT 0x18
+#define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0__SHIFT 0x1b
+#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB__SHIFT 0x1c
+#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x00000001L
+#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x0000003EL
+#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x00000040L
+#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x00000080L
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x00000100L
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x00000200L
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x00000400L
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x00000800L
+#define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x00001000L
+#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x003FE000L
+#define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN_MASK 0x00400000L
+#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK 0x01000000L
+#define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0_MASK 0x08000000L
+#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB_MASK 0x10000000L
+//SPI_SHADER_USER_DATA_VS_0
+#define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_1
+#define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_2
+#define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_3
+#define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_4
+#define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_5
+#define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_6
+#define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_7
+#define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_8
+#define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_9
+#define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_10
+#define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_11
+#define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_12
+#define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_13
+#define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_14
+#define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_15
+#define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_16
+#define SPI_SHADER_USER_DATA_VS_16__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_16__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_17
+#define SPI_SHADER_USER_DATA_VS_17__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_17__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_18
+#define SPI_SHADER_USER_DATA_VS_18__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_18__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_19
+#define SPI_SHADER_USER_DATA_VS_19__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_19__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_20
+#define SPI_SHADER_USER_DATA_VS_20__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_20__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_21
+#define SPI_SHADER_USER_DATA_VS_21__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_21__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_22
+#define SPI_SHADER_USER_DATA_VS_22__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_22__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_23
+#define SPI_SHADER_USER_DATA_VS_23__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_23__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_24
+#define SPI_SHADER_USER_DATA_VS_24__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_24__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_25
+#define SPI_SHADER_USER_DATA_VS_25__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_25__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_26
+#define SPI_SHADER_USER_DATA_VS_26__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_26__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_27
+#define SPI_SHADER_USER_DATA_VS_27__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_27__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_28
+#define SPI_SHADER_USER_DATA_VS_28__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_28__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_29
+#define SPI_SHADER_USER_DATA_VS_29__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_29__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_30
+#define SPI_SHADER_USER_DATA_VS_30__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_30__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_31
+#define SPI_SHADER_USER_DATA_VS_31__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_31__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_RSRC2_GS_VS
+#define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN__SHIFT 0x12
+#define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE__SHIFT 0x13
+#define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0__SHIFT 0x1b
+#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB__SHIFT 0x1c
+#define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN_MASK 0x00000001L
+#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MASK 0x0000003EL
+#define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT_MASK 0x00000040L
+#define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN_MASK 0x0000FF80L
+#define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT_MASK 0x00030000L
+#define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN_MASK 0x00040000L
+#define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE_MASK 0x07F80000L
+#define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0_MASK 0x08000000L
+#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB_MASK 0x10000000L
+//SPI_SHADER_PGM_RSRC4_GS
+#define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH_MASK 0x0000007FL
+#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS_MASK 0x00003F80L
+//SPI_SHADER_USER_DATA_ADDR_LO_GS
+#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ADDR_HI_GS
+#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_LO_ES
+#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_HI_ES
+#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0xFFL
+//SPI_SHADER_PGM_RSRC3_GS
+#define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE__SHIFT 0x1a
+#define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0x0000FFFFL
+#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK 0x003F0000L
+#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L
+#define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE_MASK 0x3C000000L
+//SPI_SHADER_PGM_LO_GS
+#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_HI_GS
+#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xFFL
+//SPI_SHADER_PGM_RSRC1_GS
+#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x15
+#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x17
+#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18
+#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT__SHIFT 0x1d
+#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL__SHIFT 0x1f
+#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x0000003FL
+#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x000003C0L
+#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0x00000C00L
+#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0x000FF000L
+#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x00100000L
+#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x00200000L
+#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x00800000L
+#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x01000000L
+#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT_MASK 0x60000000L
+#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL_MASK 0x80000000L
+//SPI_SHADER_PGM_RSRC2_GS
+#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN__SHIFT 0x12
+#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE__SHIFT 0x13
+#define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0__SHIFT 0x1b
+#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB__SHIFT 0x1c
+#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x00000001L
+#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x0000003EL
+#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x00000040L
+#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0x0000FF80L
+#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT_MASK 0x00030000L
+#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN_MASK 0x00040000L
+#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE_MASK 0x07F80000L
+#define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0_MASK 0x08000000L
+#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB_MASK 0x10000000L
+//SPI_SHADER_USER_DATA_ES_0
+#define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_1
+#define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_2
+#define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_3
+#define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_4
+#define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_5
+#define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_6
+#define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_7
+#define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_8
+#define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_9
+#define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_10
+#define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_11
+#define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_12
+#define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_13
+#define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_14
+#define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_15
+#define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_16
+#define SPI_SHADER_USER_DATA_ES_16__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_16__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_17
+#define SPI_SHADER_USER_DATA_ES_17__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_17__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_18
+#define SPI_SHADER_USER_DATA_ES_18__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_18__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_19
+#define SPI_SHADER_USER_DATA_ES_19__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_19__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_20
+#define SPI_SHADER_USER_DATA_ES_20__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_20__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_21
+#define SPI_SHADER_USER_DATA_ES_21__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_21__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_22
+#define SPI_SHADER_USER_DATA_ES_22__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_22__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_23
+#define SPI_SHADER_USER_DATA_ES_23__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_23__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_24
+#define SPI_SHADER_USER_DATA_ES_24__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_24__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_25
+#define SPI_SHADER_USER_DATA_ES_25__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_25__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_26
+#define SPI_SHADER_USER_DATA_ES_26__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_26__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_27
+#define SPI_SHADER_USER_DATA_ES_27__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_27__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_28
+#define SPI_SHADER_USER_DATA_ES_28__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_28__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_29
+#define SPI_SHADER_USER_DATA_ES_29__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_29__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_30
+#define SPI_SHADER_USER_DATA_ES_30__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_30__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_31
+#define SPI_SHADER_USER_DATA_ES_31__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_31__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_RSRC4_HS
+#define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH_MASK 0x0000007FL
+//SPI_SHADER_USER_DATA_ADDR_LO_HS
+#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ADDR_HI_HS
+#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_LO_LS
+#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_HI_LS
+#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0xFFL
+//SPI_SHADER_PGM_RSRC3_HS
+#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC3_HS__CU_EN__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK 0x0000003FL
+#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK 0x000003C0L
+#define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE_MASK 0x00003C00L
+#define SPI_SHADER_PGM_RSRC3_HS__CU_EN_MASK 0xFFFF0000L
+//SPI_SHADER_PGM_LO_HS
+#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_HI_HS
+#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xFFL
+//SPI_SHADER_PGM_RSRC1_HS
+#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x15
+#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x17
+#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT__SHIFT 0x1c
+#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL__SHIFT 0x1e
+#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x0000003FL
+#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x000003C0L
+#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0x00000C00L
+#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0x000FF000L
+#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x00100000L
+#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x00200000L
+#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x00800000L
+#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT_MASK 0x30000000L
+#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL_MASK 0x40000000L
+//SPI_SHADER_PGM_RSRC2_HS
+#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0__SHIFT 0x1b
+#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB__SHIFT 0x1c
+#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x00000001L
+#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x0000003EL
+#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x00000040L
+#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x0000FF80L
+#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE_MASK 0x01FF0000L
+#define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0_MASK 0x08000000L
+#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB_MASK 0x10000000L
+//SPI_SHADER_USER_DATA_LS_0
+#define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_1
+#define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_2
+#define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_3
+#define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_4
+#define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_5
+#define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_6
+#define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_7
+#define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_8
+#define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_9
+#define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_10
+#define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_11
+#define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_12
+#define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_13
+#define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_14
+#define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_15
+#define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_16
+#define SPI_SHADER_USER_DATA_LS_16__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_16__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_17
+#define SPI_SHADER_USER_DATA_LS_17__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_17__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_18
+#define SPI_SHADER_USER_DATA_LS_18__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_18__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_19
+#define SPI_SHADER_USER_DATA_LS_19__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_19__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_20
+#define SPI_SHADER_USER_DATA_LS_20__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_20__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_21
+#define SPI_SHADER_USER_DATA_LS_21__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_21__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_22
+#define SPI_SHADER_USER_DATA_LS_22__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_22__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_23
+#define SPI_SHADER_USER_DATA_LS_23__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_23__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_24
+#define SPI_SHADER_USER_DATA_LS_24__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_24__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_25
+#define SPI_SHADER_USER_DATA_LS_25__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_25__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_26
+#define SPI_SHADER_USER_DATA_LS_26__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_26__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_27
+#define SPI_SHADER_USER_DATA_LS_27__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_27__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_28
+#define SPI_SHADER_USER_DATA_LS_28__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_28__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_29
+#define SPI_SHADER_USER_DATA_LS_29__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_29__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_30
+#define SPI_SHADER_USER_DATA_LS_30__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_30__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_31
+#define SPI_SHADER_USER_DATA_LS_31__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_31__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_0
+#define SPI_SHADER_USER_DATA_COMMON_0__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_0__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_1
+#define SPI_SHADER_USER_DATA_COMMON_1__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_1__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_2
+#define SPI_SHADER_USER_DATA_COMMON_2__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_2__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_3
+#define SPI_SHADER_USER_DATA_COMMON_3__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_3__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_4
+#define SPI_SHADER_USER_DATA_COMMON_4__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_4__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_5
+#define SPI_SHADER_USER_DATA_COMMON_5__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_5__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_6
+#define SPI_SHADER_USER_DATA_COMMON_6__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_6__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_7
+#define SPI_SHADER_USER_DATA_COMMON_7__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_7__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_8
+#define SPI_SHADER_USER_DATA_COMMON_8__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_8__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_9
+#define SPI_SHADER_USER_DATA_COMMON_9__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_9__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_10
+#define SPI_SHADER_USER_DATA_COMMON_10__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_10__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_11
+#define SPI_SHADER_USER_DATA_COMMON_11__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_11__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_12
+#define SPI_SHADER_USER_DATA_COMMON_12__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_12__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_13
+#define SPI_SHADER_USER_DATA_COMMON_13__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_13__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_14
+#define SPI_SHADER_USER_DATA_COMMON_14__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_14__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_15
+#define SPI_SHADER_USER_DATA_COMMON_15__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_15__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_16
+#define SPI_SHADER_USER_DATA_COMMON_16__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_16__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_17
+#define SPI_SHADER_USER_DATA_COMMON_17__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_17__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_18
+#define SPI_SHADER_USER_DATA_COMMON_18__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_18__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_19
+#define SPI_SHADER_USER_DATA_COMMON_19__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_19__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_20
+#define SPI_SHADER_USER_DATA_COMMON_20__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_20__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_21
+#define SPI_SHADER_USER_DATA_COMMON_21__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_21__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_22
+#define SPI_SHADER_USER_DATA_COMMON_22__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_22__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_23
+#define SPI_SHADER_USER_DATA_COMMON_23__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_23__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_24
+#define SPI_SHADER_USER_DATA_COMMON_24__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_24__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_25
+#define SPI_SHADER_USER_DATA_COMMON_25__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_25__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_26
+#define SPI_SHADER_USER_DATA_COMMON_26__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_26__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_27
+#define SPI_SHADER_USER_DATA_COMMON_27__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_27__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_28
+#define SPI_SHADER_USER_DATA_COMMON_28__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_28__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_29
+#define SPI_SHADER_USER_DATA_COMMON_29__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_29__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_30
+#define SPI_SHADER_USER_DATA_COMMON_30__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_30__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_COMMON_31
+#define SPI_SHADER_USER_DATA_COMMON_31__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_COMMON_31__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_DISPATCH_INITIATOR
+#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0
+#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1
+#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2
+#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3
+#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4
+#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5
+#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6
+#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa
+#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb
+#define COMPUTE_DISPATCH_INITIATOR__RESERVED__SHIFT 0xc
+#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe
+#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x00000001L
+#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x00000002L
+#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x00000004L
+#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x00000008L
+#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x00000010L
+#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x00000020L
+#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x00000040L
+#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x00000400L
+#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x00000800L
+#define COMPUTE_DISPATCH_INITIATOR__RESERVED_MASK 0x00001000L
+#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x00004000L
+//COMPUTE_DIM_X
+#define COMPUTE_DIM_X__SIZE__SHIFT 0x0
+#define COMPUTE_DIM_X__SIZE_MASK 0xFFFFFFFFL
+//COMPUTE_DIM_Y
+#define COMPUTE_DIM_Y__SIZE__SHIFT 0x0
+#define COMPUTE_DIM_Y__SIZE_MASK 0xFFFFFFFFL
+//COMPUTE_DIM_Z
+#define COMPUTE_DIM_Z__SIZE__SHIFT 0x0
+#define COMPUTE_DIM_Z__SIZE_MASK 0xFFFFFFFFL
+//COMPUTE_START_X
+#define COMPUTE_START_X__START__SHIFT 0x0
+#define COMPUTE_START_X__START_MASK 0xFFFFFFFFL
+//COMPUTE_START_Y
+#define COMPUTE_START_Y__START__SHIFT 0x0
+#define COMPUTE_START_Y__START_MASK 0xFFFFFFFFL
+//COMPUTE_START_Z
+#define COMPUTE_START_Z__START__SHIFT 0x0
+#define COMPUTE_START_Z__START_MASK 0xFFFFFFFFL
+//COMPUTE_NUM_THREAD_X
+#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0
+#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10
+#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0x0000FFFFL
+#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L
+//COMPUTE_NUM_THREAD_Y
+#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0
+#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10
+#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0x0000FFFFL
+#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L
+//COMPUTE_NUM_THREAD_Z
+#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0
+#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10
+#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0x0000FFFFL
+#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L
+//COMPUTE_PIPELINESTAT_ENABLE
+#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0
+#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x00000001L
+//COMPUTE_PERFCOUNT_ENABLE
+#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0
+#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x00000001L
+//COMPUTE_PGM_LO
+#define COMPUTE_PGM_LO__DATA__SHIFT 0x0
+#define COMPUTE_PGM_LO__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_PGM_HI
+#define COMPUTE_PGM_HI__DATA__SHIFT 0x0
+#define COMPUTE_PGM_HI__DATA_MASK 0x000000FFL
+//COMPUTE_DISPATCH_PKT_ADDR_LO
+#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA__SHIFT 0x0
+#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_DISPATCH_PKT_ADDR_HI
+#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA__SHIFT 0x0
+#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA_MASK 0x000000FFL
+//COMPUTE_DISPATCH_SCRATCH_BASE_LO
+#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA__SHIFT 0x0
+#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_DISPATCH_SCRATCH_BASE_HI
+#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA__SHIFT 0x0
+#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA_MASK 0x000000FFL
+//COMPUTE_PGM_RSRC1
+#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0
+#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6
+#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa
+#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc
+#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14
+#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15
+#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17
+#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18
+#define COMPUTE_PGM_RSRC1__FP16_OVFL__SHIFT 0x1a
+#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x0000003FL
+#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x000003C0L
+#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0x00000C00L
+#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0x000FF000L
+#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x00100000L
+#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x00200000L
+#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x00800000L
+#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x01000000L
+#define COMPUTE_PGM_RSRC1__FP16_OVFL_MASK 0x04000000L
+//COMPUTE_PGM_RSRC2
+#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0
+#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1
+#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6
+#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7
+#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8
+#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9
+#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa
+#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb
+#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd
+#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf
+#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18
+#define COMPUTE_PGM_RSRC2__SKIP_USGPR0__SHIFT 0x1f
+#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x00000001L
+#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x0000003EL
+#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x00000040L
+#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x00000080L
+#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x00000100L
+#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x00000200L
+#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x00000400L
+#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x00001800L
+#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x00006000L
+#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0x00FF8000L
+#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7F000000L
+#define COMPUTE_PGM_RSRC2__SKIP_USGPR0_MASK 0x80000000L
+//COMPUTE_VMID
+#define COMPUTE_VMID__DATA__SHIFT 0x0
+#define COMPUTE_VMID__DATA_MASK 0x0000000FL
+//COMPUTE_RESOURCE_LIMITS
+#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0
+#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc
+#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10
+#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16
+#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17
+#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18
+#define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE__SHIFT 0x1b
+#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x000003FFL
+#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0x0000F000L
+#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x003F0000L
+#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x00400000L
+#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x00800000L
+#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x07000000L
+#define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE_MASK 0x78000000L
+//COMPUTE_STATIC_THREAD_MGMT_SE0
+#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x0
+#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x10
+#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0x0000FFFFL
+#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xFFFF0000L
+//COMPUTE_STATIC_THREAD_MGMT_SE1
+#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x0
+#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x10
+#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0x0000FFFFL
+#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xFFFF0000L
+//COMPUTE_TMPRING_SIZE
+#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0
+#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc
+#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0x00000FFFL
+#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x01FFF000L
+//COMPUTE_STATIC_THREAD_MGMT_SE2
+#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT 0x0
+#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT 0x10
+#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK 0x0000FFFFL
+#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK 0xFFFF0000L
+//COMPUTE_STATIC_THREAD_MGMT_SE3
+#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT 0x0
+#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT 0x10
+#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK 0x0000FFFFL
+#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK 0xFFFF0000L
+//COMPUTE_RESTART_X
+#define COMPUTE_RESTART_X__RESTART__SHIFT 0x0
+#define COMPUTE_RESTART_X__RESTART_MASK 0xFFFFFFFFL
+//COMPUTE_RESTART_Y
+#define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0
+#define COMPUTE_RESTART_Y__RESTART_MASK 0xFFFFFFFFL
+//COMPUTE_RESTART_Z
+#define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0
+#define COMPUTE_RESTART_Z__RESTART_MASK 0xFFFFFFFFL
+//COMPUTE_THREAD_TRACE_ENABLE
+#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0
+#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x00000001L
+//COMPUTE_MISC_RESERVED
+#define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0
+#define COMPUTE_MISC_RESERVED__SEND_SEID_CORE1__SHIFT 0x2
+#define COMPUTE_MISC_RESERVED__RESTORE_CORE_ID__SHIFT 0x4
+#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x5
+#define COMPUTE_MISC_RESERVED__CRAWLER_DONE_CORE0__SHIFT 0x11
+#define COMPUTE_MISC_RESERVED__CRAWLER_DONE_CORE1__SHIFT 0x12
+#define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x00000003L
+#define COMPUTE_MISC_RESERVED__SEND_SEID_CORE1_MASK 0x0000000CL
+#define COMPUTE_MISC_RESERVED__RESTORE_CORE_ID_MASK 0x00000010L
+#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x0001FFE0L
+#define COMPUTE_MISC_RESERVED__CRAWLER_DONE_CORE0_MASK 0x00020000L
+#define COMPUTE_MISC_RESERVED__CRAWLER_DONE_CORE1_MASK 0x00040000L
+//COMPUTE_DISPATCH_ID
+#define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x0
+#define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xFFFFFFFFL
+//COMPUTE_THREADGROUP_ID
+#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x0
+#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xFFFFFFFFL
+//COMPUTE_RELAUNCH
+#define COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x0
+#define COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x1e
+#define COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x1f
+#define COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3FFFFFFFL
+#define COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000L
+#define COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000L
+//COMPUTE_WAVE_RESTORE_ADDR_LO
+#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x0
+#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xFFFFFFFFL
+//COMPUTE_WAVE_RESTORE_ADDR_HI
+#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x0
+#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0xFFFFL
+//COMPUTE_STATIC_THREAD_MGMT_SE4
+#define COMPUTE_STATIC_THREAD_MGMT_SE4__SH0_CU_EN__SHIFT 0x0
+#define COMPUTE_STATIC_THREAD_MGMT_SE4__SH1_CU_EN__SHIFT 0x10
+#define COMPUTE_STATIC_THREAD_MGMT_SE4__SH0_CU_EN_MASK 0x0000FFFFL
+#define COMPUTE_STATIC_THREAD_MGMT_SE4__SH1_CU_EN_MASK 0xFFFF0000L
+//COMPUTE_STATIC_THREAD_MGMT_SE5
+#define COMPUTE_STATIC_THREAD_MGMT_SE5__SH0_CU_EN__SHIFT 0x0
+#define COMPUTE_STATIC_THREAD_MGMT_SE5__SH1_CU_EN__SHIFT 0x10
+#define COMPUTE_STATIC_THREAD_MGMT_SE5__SH0_CU_EN_MASK 0x0000FFFFL
+#define COMPUTE_STATIC_THREAD_MGMT_SE5__SH1_CU_EN_MASK 0xFFFF0000L
+//COMPUTE_STATIC_THREAD_MGMT_SE6
+#define COMPUTE_STATIC_THREAD_MGMT_SE6__SH0_CU_EN__SHIFT 0x0
+#define COMPUTE_STATIC_THREAD_MGMT_SE6__SH1_CU_EN__SHIFT 0x10
+#define COMPUTE_STATIC_THREAD_MGMT_SE6__SH0_CU_EN_MASK 0x0000FFFFL
+#define COMPUTE_STATIC_THREAD_MGMT_SE6__SH1_CU_EN_MASK 0xFFFF0000L
+//COMPUTE_STATIC_THREAD_MGMT_SE7
+#define COMPUTE_STATIC_THREAD_MGMT_SE7__SH0_CU_EN__SHIFT 0x0
+#define COMPUTE_STATIC_THREAD_MGMT_SE7__SH1_CU_EN__SHIFT 0x10
+#define COMPUTE_STATIC_THREAD_MGMT_SE7__SH0_CU_EN_MASK 0x0000FFFFL
+#define COMPUTE_STATIC_THREAD_MGMT_SE7__SH1_CU_EN_MASK 0xFFFF0000L
+//COMPUTE_RESTART_X2
+#define COMPUTE_RESTART_X2__RESTART__SHIFT 0x0
+#define COMPUTE_RESTART_X2__RESTART_MASK 0xFFFFFFFFL
+//COMPUTE_RESTART_Y2
+#define COMPUTE_RESTART_Y2__RESTART__SHIFT 0x0
+#define COMPUTE_RESTART_Y2__RESTART_MASK 0xFFFFFFFFL
+//COMPUTE_RESTART_Z2
+#define COMPUTE_RESTART_Z2__RESTART__SHIFT 0x0
+#define COMPUTE_RESTART_Z2__RESTART_MASK 0xFFFFFFFFL
+//COMPUTE_SHADER_CHKSUM
+#define COMPUTE_SHADER_CHKSUM__CHECKSUM__SHIFT 0x0
+#define COMPUTE_SHADER_CHKSUM__CHECKSUM_MASK 0xFFFFFFFFL
+//COMPUTE_PGM_RSRC3
+#define COMPUTE_PGM_RSRC3__ACCUM_OFFSET__SHIFT 0x0
+#define COMPUTE_PGM_RSRC3__TG_SPLIT__SHIFT 0x10
+#define COMPUTE_PGM_RSRC3__ACCUM_OFFSET_MASK 0x0000003FL
+#define COMPUTE_PGM_RSRC3__TG_SPLIT_MASK 0x00010000L
+//COMPUTE_USER_DATA_0
+#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_0__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_1
+#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_1__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_2
+#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_2__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_3
+#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_3__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_4
+#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_4__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_5
+#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_5__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_6
+#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_6__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_7
+#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_7__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_8
+#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_8__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_9
+#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_9__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_10
+#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_10__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_11
+#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_11__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_12
+#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_12__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_13
+#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_13__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_14
+#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_14__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_15
+#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_15__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_DISPATCH_END
+#define COMPUTE_DISPATCH_END__DATA__SHIFT 0x0
+#define COMPUTE_DISPATCH_END__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_NOWHERE
+#define COMPUTE_NOWHERE__DATA__SHIFT 0x0
+#define COMPUTE_NOWHERE__DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: gc_shsdec
+//SX_DEBUG_1
+#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0
+#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x8
+#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x9
+#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0xa
+#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT__SHIFT 0xb
+#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT__SHIFT 0xc
+#define SX_DEBUG_1__DISABLE_REP_FGCG__SHIFT 0xd
+#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0xe
+#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x0000007FL
+#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x00000100L
+#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS_MASK 0x00000200L
+#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x00000400L
+#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT_MASK 0x00000800L
+#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT_MASK 0x00001000L
+#define SX_DEBUG_1__DISABLE_REP_FGCG_MASK 0x00002000L
+#define SX_DEBUG_1__DEBUG_DATA_MASK 0xFFFFC000L
+//SPI_PS_MAX_WAVE_ID
+#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
+#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID__SHIFT 0x10
+#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
+#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID_MASK 0x03FF0000L
+//SPI_START_PHASE
+#define SPI_START_PHASE__VGPR_START_PHASE__SHIFT 0x0
+#define SPI_START_PHASE__SGPR_START_PHASE__SHIFT 0x2
+#define SPI_START_PHASE__WAVE_START_PHASE__SHIFT 0x4
+#define SPI_START_PHASE__SPI_TD_GAP__SHIFT 0x6
+#define SPI_START_PHASE__VGPR_START_PHASE_MASK 0x00000003L
+#define SPI_START_PHASE__SGPR_START_PHASE_MASK 0x0000000CL
+#define SPI_START_PHASE__WAVE_START_PHASE_MASK 0x00000030L
+#define SPI_START_PHASE__SPI_TD_GAP_MASK 0x000003C0L
+//SPI_GFX_CNTL
+#define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x0
+#define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x00000001L
+//SPI_DSM_CNTL
+#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define SPI_DSM_CNTL__SPI_GDS_EXPREQ_MEM_DSM_IRRITATOR_DATA__SHIFT 0x3
+#define SPI_DSM_CNTL__SPI_GDS_EXPREQ_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define SPI_DSM_CNTL__SPI_WB_GRANT_30_MEM_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define SPI_DSM_CNTL__SPI_WB_GRANT_30_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define SPI_DSM_CNTL__SPI_LIFE_CNT_MEM_DSM_IRRITATOR_DATA__SHIFT 0xc
+#define SPI_DSM_CNTL__SPI_LIFE_CNT_MEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
+#define SPI_DSM_CNTL__UNUSED__SHIFT 0xf
+#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define SPI_DSM_CNTL__SPI_GDS_EXPREQ_MEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
+#define SPI_DSM_CNTL__SPI_GDS_EXPREQ_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define SPI_DSM_CNTL__SPI_WB_GRANT_30_MEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define SPI_DSM_CNTL__SPI_WB_GRANT_30_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define SPI_DSM_CNTL__SPI_LIFE_CNT_MEM_DSM_IRRITATOR_DATA_MASK 0x00003000L
+#define SPI_DSM_CNTL__SPI_LIFE_CNT_MEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
+#define SPI_DSM_CNTL__UNUSED_MASK 0xFFFF8000L
+//SPI_DSM_CNTL2
+#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY__SHIFT 0x4
+#define SPI_DSM_CNTL2__SPI_GDS_EXPREQ_MEM_ENABLE_ERROR_INJECT__SHIFT 0xa
+#define SPI_DSM_CNTL2__SPI_GDS_EXPREQ_MEM_SELECT_INJECT_DELAY__SHIFT 0xc
+#define SPI_DSM_CNTL2__SPI_WB_GRANT_30_MEM_ENABLE_ERROR_INJECT__SHIFT 0xd
+#define SPI_DSM_CNTL2__SPI_WB_GRANT_30_MEM_SELECT_INJECT_DELAY__SHIFT 0xf
+#define SPI_DSM_CNTL2__SPI_LIFE_CNT_MEM_ENABLE_ERROR_INJECT__SHIFT 0x13
+#define SPI_DSM_CNTL2__SPI_LIFE_CNT_MEM_SELECT_INJECT_DELAY__SHIFT 0x15
+#define SPI_DSM_CNTL2__UNUSED__SHIFT 0x16
+#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY_MASK 0x000003F0L
+#define SPI_DSM_CNTL2__SPI_GDS_EXPREQ_MEM_ENABLE_ERROR_INJECT_MASK 0x00000C00L
+#define SPI_DSM_CNTL2__SPI_GDS_EXPREQ_MEM_SELECT_INJECT_DELAY_MASK 0x00001000L
+#define SPI_DSM_CNTL2__SPI_WB_GRANT_30_MEM_ENABLE_ERROR_INJECT_MASK 0x00006000L
+#define SPI_DSM_CNTL2__SPI_WB_GRANT_30_MEM_SELECT_INJECT_DELAY_MASK 0x00008000L
+#define SPI_DSM_CNTL2__SPI_LIFE_CNT_MEM_ENABLE_ERROR_INJECT_MASK 0x00180000L
+#define SPI_DSM_CNTL2__SPI_LIFE_CNT_MEM_SELECT_INJECT_DELAY_MASK 0x00200000L
+#define SPI_DSM_CNTL2__UNUSED_MASK 0xFFC00000L
+//SPI_EDC_CNT
+#define SPI_EDC_CNT__SPI_SR_MEM_SEC_COUNT__SHIFT 0x0
+#define SPI_EDC_CNT__SPI_SR_MEM_DED_COUNT__SHIFT 0x2
+#define SPI_EDC_CNT__SPI_GDS_EXPREQ_SEC_COUNT__SHIFT 0x4
+#define SPI_EDC_CNT__SPI_GDS_EXPREQ_DED_COUNT__SHIFT 0x6
+#define SPI_EDC_CNT__SPI_WB_GRANT_30_SEC_COUNT__SHIFT 0x8
+#define SPI_EDC_CNT__SPI_WB_GRANT_30_DED_COUNT__SHIFT 0xa
+#define SPI_EDC_CNT__SPI_LIFE_CNT_SEC_COUNT__SHIFT 0x10
+#define SPI_EDC_CNT__SPI_LIFE_CNT_DED_COUNT__SHIFT 0x12
+#define SPI_EDC_CNT__SPI_SR_MEM_SEC_COUNT_MASK 0x00000003L
+#define SPI_EDC_CNT__SPI_SR_MEM_DED_COUNT_MASK 0x0000000CL
+#define SPI_EDC_CNT__SPI_GDS_EXPREQ_SEC_COUNT_MASK 0x00000030L
+#define SPI_EDC_CNT__SPI_GDS_EXPREQ_DED_COUNT_MASK 0x000000C0L
+#define SPI_EDC_CNT__SPI_WB_GRANT_30_SEC_COUNT_MASK 0x00000300L
+#define SPI_EDC_CNT__SPI_WB_GRANT_30_DED_COUNT_MASK 0x00000C00L
+#define SPI_EDC_CNT__SPI_LIFE_CNT_SEC_COUNT_MASK 0x00030000L
+#define SPI_EDC_CNT__SPI_LIFE_CNT_DED_COUNT_MASK 0x000C0000L
+//SPI_CONFIG_PS_CU_EN
+#define SPI_CONFIG_PS_CU_EN__ENABLE__SHIFT 0x0
+#define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN__SHIFT 0x1
+#define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN__SHIFT 0x10
+#define SPI_CONFIG_PS_CU_EN__ENABLE_MASK 0x00000001L
+#define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN_MASK 0x0000FFFEL
+#define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN_MASK 0xFFFF0000L
+//SPI_WF_LIFETIME_CNTL
+#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0
+#define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4
+#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0x0000000FL
+#define SPI_WF_LIFETIME_CNTL__EN_MASK 0x00000010L
+//SPI_WF_LIFETIME_LIMIT_0
+#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000L
+//SPI_WF_LIFETIME_LIMIT_1
+#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000L
+//SPI_WF_LIFETIME_LIMIT_2
+#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000L
+//SPI_WF_LIFETIME_LIMIT_3
+#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000L
+//SPI_WF_LIFETIME_LIMIT_4
+#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000L
+//SPI_WF_LIFETIME_LIMIT_5
+#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000L
+//SPI_WF_LIFETIME_LIMIT_6
+#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000L
+//SPI_WF_LIFETIME_LIMIT_7
+#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000L
+//SPI_WF_LIFETIME_LIMIT_8
+#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000L
+//SPI_WF_LIFETIME_LIMIT_9
+#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_0
+#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_1
+#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_2
+#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_3
+#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_4
+#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_5
+#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_6
+#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_7
+#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_8
+#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_9
+#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_10
+#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_11
+#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_12
+#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_13
+#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_14
+#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_15
+#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_16
+#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_17
+#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_18
+#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_19
+#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_20
+#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000L
+//SPI_LB_CTR_CTRL
+#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0
+#define SPI_LB_CTR_CTRL__WAVES_SELECT__SHIFT 0x1
+#define SPI_LB_CTR_CTRL__CLEAR_ON_READ__SHIFT 0x3
+#define SPI_LB_CTR_CTRL__RESET_COUNTS__SHIFT 0x4
+#define SPI_LB_CTR_CTRL__LOAD_MASK 0x00000001L
+#define SPI_LB_CTR_CTRL__WAVES_SELECT_MASK 0x00000006L
+#define SPI_LB_CTR_CTRL__CLEAR_ON_READ_MASK 0x00000008L
+#define SPI_LB_CTR_CTRL__RESET_COUNTS_MASK 0x00000010L
+//SPI_LB_CU_MASK
+#define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x0
+#define SPI_LB_CU_MASK__CU_MASK_MASK 0xFFFFL
+//SPI_LB_DATA_REG
+#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0
+#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xFFFFFFFFL
+//SPI_PG_ENABLE_STATIC_CU_MASK
+#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x0
+#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0xFFFFL
+//SPI_GDS_CREDITS
+#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0
+#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8
+#define SPI_GDS_CREDITS__UNUSED__SHIFT 0x10
+#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0x000000FFL
+#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0x0000FF00L
+#define SPI_GDS_CREDITS__UNUSED_MASK 0xFFFF0000L
+//SPI_SX_EXPORT_BUFFER_SIZES
+#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0
+#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10
+#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0x0000FFFFL
+#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xFFFF0000L
+//SPI_SX_SCOREBOARD_BUFFER_SIZES
+#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0
+#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10
+#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0x0000FFFFL
+#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xFFFF0000L
+//SPI_CSQ_WF_ACTIVE_STATUS
+#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xFFFFFFFFL
+//SPI_CSQ_WF_ACTIVE_COUNT_0
+#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS__SHIFT 0x10
+#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000001FFL
+#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS_MASK 0x01FF0000L
+//SPI_CSQ_WF_ACTIVE_COUNT_1
+#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS__SHIFT 0x10
+#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000001FFL
+#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS_MASK 0x01FF0000L
+//SPI_CSQ_WF_ACTIVE_COUNT_2
+#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS__SHIFT 0x10
+#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x000001FFL
+#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS_MASK 0x01FF0000L
+//SPI_CSQ_WF_ACTIVE_COUNT_3
+#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS__SHIFT 0x10
+#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x000001FFL
+#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS_MASK 0x01FF0000L
+//SPI_CSQ_WF_ACTIVE_COUNT_4
+#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS__SHIFT 0x10
+#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x000001FFL
+#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS_MASK 0x01FF0000L
+//SPI_CSQ_WF_ACTIVE_COUNT_5
+#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS__SHIFT 0x10
+#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x000001FFL
+#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS_MASK 0x01FF0000L
+//SPI_CSQ_WF_ACTIVE_COUNT_6
+#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS__SHIFT 0x10
+#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x000001FFL
+#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS_MASK 0x01FF0000L
+//SPI_CSQ_WF_ACTIVE_COUNT_7
+#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS__SHIFT 0x10
+#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x000001FFL
+#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS_MASK 0x01FF0000L
+//SPI_LB_DATA_WAVES
+#define SPI_LB_DATA_WAVES__COUNT0__SHIFT 0x0
+#define SPI_LB_DATA_WAVES__COUNT1__SHIFT 0x10
+#define SPI_LB_DATA_WAVES__COUNT0_MASK 0x0000FFFFL
+#define SPI_LB_DATA_WAVES__COUNT1_MASK 0xFFFF0000L
+//SPI_LB_DATA_PERCU_WAVE_HSGS
+#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS__SHIFT 0x0
+#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS__SHIFT 0x10
+#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS_MASK 0x0000FFFFL
+#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS_MASK 0xFFFF0000L
+//SPI_LB_DATA_PERCU_WAVE_VSPS
+#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS__SHIFT 0x0
+#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS__SHIFT 0x10
+#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS_MASK 0x0000FFFFL
+#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS_MASK 0xFFFF0000L
+//SPI_LB_DATA_PERCU_WAVE_CS
+#define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE__SHIFT 0x0
+#define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE_MASK 0xFFFFL
+//SPI_P0_TRAP_SCREEN_PSBA_LO
+#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
+#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_P0_TRAP_SCREEN_PSBA_HI
+#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
+#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL
+//SPI_P0_TRAP_SCREEN_PSMA_LO
+#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
+#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_P0_TRAP_SCREEN_PSMA_HI
+#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
+#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL
+//SPI_P0_TRAP_SCREEN_GPR_MIN
+#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
+#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
+#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL
+#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L
+//SPI_P1_TRAP_SCREEN_PSBA_LO
+#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
+#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_P1_TRAP_SCREEN_PSBA_HI
+#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
+#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL
+//SPI_P1_TRAP_SCREEN_PSMA_LO
+#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
+#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_P1_TRAP_SCREEN_PSMA_HI
+#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
+#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL
+//SPI_P1_TRAP_SCREEN_GPR_MIN
+#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
+#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
+#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL
+#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L
+
+
+// addressBlock: gc_spipdec
+//SPI_ARB_PRIORITY
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9
+#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc
+#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe
+#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10
+#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x00000007L
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x00000038L
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x000001C0L
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0x00000E00L
+#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x00003000L
+#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0x0000C000L
+#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x00030000L
+#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0x000C0000L
+//SPI_ARB_CYCLES_0
+#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0
+#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10
+#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0x0000FFFFL
+#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xFFFF0000L
+//SPI_ARB_CYCLES_1
+#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0
+#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10
+#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0x0000FFFFL
+#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xFFFF0000L
+//SPI_WCL_PIPE_PERCENT_GFX
+#define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE__SHIFT 0x7
+#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT 0xc
+#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE__SHIFT 0x11
+#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT 0x16
+#define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x0000007FL
+#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE_MASK 0x00000F80L
+#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK 0x0001F000L
+#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE_MASK 0x003E0000L
+#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK 0x07C00000L
+//SPI_WCL_PIPE_PERCENT_HP3D
+#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT 0xc
+#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT 0x16
+#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x0000007FL
+#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK 0x0001F000L
+#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK 0x07C00000L
+//SPI_WCL_PIPE_PERCENT_CS0
+#define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x7FL
+//SPI_WCL_PIPE_PERCENT_CS1
+#define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x7FL
+//SPI_WCL_PIPE_PERCENT_CS2
+#define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x7FL
+//SPI_WCL_PIPE_PERCENT_CS3
+#define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x7FL
+//SPI_WCL_PIPE_PERCENT_CS4
+#define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x7FL
+//SPI_WCL_PIPE_PERCENT_CS5
+#define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x7FL
+//SPI_WCL_PIPE_PERCENT_CS6
+#define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x7FL
+//SPI_WCL_PIPE_PERCENT_CS7
+#define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x7FL
+//SPI_GDBG_WAVE_CNTL
+#define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT 0x0
+#define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x01L
+//SPI_GDBG_TRAP_CONFIG
+#define SPI_GDBG_TRAP_CONFIG__PIPE0_EN__SHIFT 0x0
+#define SPI_GDBG_TRAP_CONFIG__PIPE1_EN__SHIFT 0x8
+#define SPI_GDBG_TRAP_CONFIG__PIPE2_EN__SHIFT 0x10
+#define SPI_GDBG_TRAP_CONFIG__PIPE3_EN__SHIFT 0x18
+#define SPI_GDBG_TRAP_CONFIG__PIPE0_EN_MASK 0x000000FFL
+#define SPI_GDBG_TRAP_CONFIG__PIPE1_EN_MASK 0x0000FF00L
+#define SPI_GDBG_TRAP_CONFIG__PIPE2_EN_MASK 0x00FF0000L
+#define SPI_GDBG_TRAP_CONFIG__PIPE3_EN_MASK 0xFF000000L
+//SPI_GDBG_PER_VMID_CNTL
+#define SPI_GDBG_PER_VMID_CNTL__STALL_VMID__SHIFT 0x0
+#define SPI_GDBG_PER_VMID_CNTL__LAUNCH_MODE__SHIFT 0x1
+#define SPI_GDBG_PER_VMID_CNTL__TRAP_EN__SHIFT 0x3
+#define SPI_GDBG_PER_VMID_CNTL__EXCP_EN__SHIFT 0x4
+#define SPI_GDBG_PER_VMID_CNTL__EXCP_REPLACE__SHIFT 0xd
+#define SPI_GDBG_PER_VMID_CNTL__STALL_VMID_MASK 0x0001L
+#define SPI_GDBG_PER_VMID_CNTL__LAUNCH_MODE_MASK 0x0006L
+#define SPI_GDBG_PER_VMID_CNTL__TRAP_EN_MASK 0x0008L
+#define SPI_GDBG_PER_VMID_CNTL__EXCP_EN_MASK 0x1FF0L
+#define SPI_GDBG_PER_VMID_CNTL__EXCP_REPLACE_MASK 0x2000L
+//SPI_GDBG_WAVE_CNTL3
+#define SPI_GDBG_WAVE_CNTL3__STALL_PS__SHIFT 0x0
+#define SPI_GDBG_WAVE_CNTL3__STALL_VS__SHIFT 0x1
+#define SPI_GDBG_WAVE_CNTL3__STALL_GS__SHIFT 0x2
+#define SPI_GDBG_WAVE_CNTL3__STALL_HS__SHIFT 0x3
+#define SPI_GDBG_WAVE_CNTL3__STALL_CSG__SHIFT 0x4
+#define SPI_GDBG_WAVE_CNTL3__STALL_CS0__SHIFT 0x5
+#define SPI_GDBG_WAVE_CNTL3__STALL_CS1__SHIFT 0x6
+#define SPI_GDBG_WAVE_CNTL3__STALL_CS2__SHIFT 0x7
+#define SPI_GDBG_WAVE_CNTL3__STALL_CS3__SHIFT 0x8
+#define SPI_GDBG_WAVE_CNTL3__STALL_CS4__SHIFT 0x9
+#define SPI_GDBG_WAVE_CNTL3__STALL_CS5__SHIFT 0xa
+#define SPI_GDBG_WAVE_CNTL3__STALL_CS6__SHIFT 0xb
+#define SPI_GDBG_WAVE_CNTL3__STALL_CS7__SHIFT 0xc
+#define SPI_GDBG_WAVE_CNTL3__STALL_DURATION__SHIFT 0xd
+#define SPI_GDBG_WAVE_CNTL3__STALL_MULT__SHIFT 0x1c
+#define SPI_GDBG_WAVE_CNTL3__STALL_PS_MASK 0x00000001L
+#define SPI_GDBG_WAVE_CNTL3__STALL_VS_MASK 0x00000002L
+#define SPI_GDBG_WAVE_CNTL3__STALL_GS_MASK 0x00000004L
+#define SPI_GDBG_WAVE_CNTL3__STALL_HS_MASK 0x00000008L
+#define SPI_GDBG_WAVE_CNTL3__STALL_CSG_MASK 0x00000010L
+#define SPI_GDBG_WAVE_CNTL3__STALL_CS0_MASK 0x00000020L
+#define SPI_GDBG_WAVE_CNTL3__STALL_CS1_MASK 0x00000040L
+#define SPI_GDBG_WAVE_CNTL3__STALL_CS2_MASK 0x00000080L
+#define SPI_GDBG_WAVE_CNTL3__STALL_CS3_MASK 0x00000100L
+#define SPI_GDBG_WAVE_CNTL3__STALL_CS4_MASK 0x00000200L
+#define SPI_GDBG_WAVE_CNTL3__STALL_CS5_MASK 0x00000400L
+#define SPI_GDBG_WAVE_CNTL3__STALL_CS6_MASK 0x00000800L
+#define SPI_GDBG_WAVE_CNTL3__STALL_CS7_MASK 0x00001000L
+#define SPI_GDBG_WAVE_CNTL3__STALL_DURATION_MASK 0x0FFFE000L
+#define SPI_GDBG_WAVE_CNTL3__STALL_MULT_MASK 0x10000000L
+//SPI_GDBG_TRAP_DATA0
+#define SPI_GDBG_TRAP_DATA0__DATA__SHIFT 0x0
+#define SPI_GDBG_TRAP_DATA0__DATA_MASK 0xFFFFFFFFL
+//SPI_GDBG_TRAP_DATA1
+#define SPI_GDBG_TRAP_DATA1__DATA__SHIFT 0x0
+#define SPI_GDBG_TRAP_DATA1__DATA_MASK 0xFFFFFFFFL
+//SPI_COMPUTE_QUEUE_RESET
+#define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0
+#define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x01L
+//SPI_RESOURCE_RESERVE_CU_0
+#define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_1
+#define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_2
+#define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_3
+#define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_4
+#define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_5
+#define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_6
+#define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_7
+#define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_8
+#define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_9
+#define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_EN_CU_0
+#define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_1
+#define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_2
+#define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_3
+#define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_4
+#define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_5
+#define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_6
+#define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_7
+#define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_8
+#define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_9
+#define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_CU_10
+#define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_11
+#define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_EN_CU_10
+#define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_11
+#define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_CU_12
+#define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_13
+#define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_14
+#define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_15
+#define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_EN_CU_12
+#define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_13
+#define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_14
+#define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_15
+#define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_COMPUTE_WF_CTX_SAVE
+#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT 0x0
+#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT 0x1
+#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT 0x2
+#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT 0x1e
+#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT 0x1f
+#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK 0x00000001L
+#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK 0x00000002L
+#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK 0x00000004L
+#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK 0x40000000L
+#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK 0x80000000L
+//SPI_ARB_CNTL_0
+#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT__SHIFT 0x0
+#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT__SHIFT 0x4
+#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT__SHIFT 0x8
+#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT_MASK 0x0000000FL
+#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT_MASK 0x000000F0L
+#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT_MASK 0x00000F00L
+
+
+// addressBlock: gc_sqdec
+//SQ_CONFIG
+#define SQ_CONFIG__DISABLE_BARRIER_WAITCNT__SHIFT 0x0
+#define SQ_CONFIG__DISABLE_REPEATER_FGCG_CLOCK_GATING__SHIFT 0x1
+#define SQ_CONFIG__DISABLE_SPIPRIO_OVER_USERPRIO__SHIFT 0x2
+#define SQ_CONFIG__OVERRIDE_SP_MAI_ALU_BUSY__SHIFT 0x3
+#define SQ_CONFIG__DISABLE_RAM_CLOCK_GATING__SHIFT 0x4
+#define SQ_CONFIG__DISABLE_MAI_CO_EXEC__SHIFT 0x5
+#define SQ_CONFIG__OVERRIDE_MAI_ALU_BUSY__SHIFT 0x6
+#define SQ_CONFIG__OVERRIDE_ALU_BUSY__SHIFT 0x7
+#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY__SHIFT 0xb
+#define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0xc
+#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0xd
+#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0xe
+#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0xf
+#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE__SHIFT 0x10
+#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE__SHIFT 0x11
+#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT 0x12
+#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT 0x13
+#define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT 0x15
+#define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP__SHIFT 0x1c
+#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING__SHIFT 0x1d
+#define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE__SHIFT 0x1e
+#define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE__SHIFT 0x1f
+#define SQ_CONFIG__DISABLE_BARRIER_WAITCNT_MASK 0x00000001L
+#define SQ_CONFIG__DISABLE_REPEATER_FGCG_CLOCK_GATING_MASK 0x00000002L
+#define SQ_CONFIG__DISABLE_SPIPRIO_OVER_USERPRIO_MASK 0x00000004L
+#define SQ_CONFIG__OVERRIDE_SP_MAI_ALU_BUSY_MASK 0x00000008L
+#define SQ_CONFIG__DISABLE_RAM_CLOCK_GATING_MASK 0x00000010L
+#define SQ_CONFIG__DISABLE_MAI_CO_EXEC_MASK 0x00000020L
+#define SQ_CONFIG__OVERRIDE_MAI_ALU_BUSY_MASK 0x00000040L
+#define SQ_CONFIG__OVERRIDE_ALU_BUSY_MASK 0x00000080L
+#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY_MASK 0x00000800L
+#define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x00001000L
+#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x00002000L
+#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x00004000L
+#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x00008000L
+#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE_MASK 0x00010000L
+#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE_MASK 0x00020000L
+#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK 0x00040000L
+#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK 0x00180000L
+#define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK 0x0FE00000L
+#define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP_MASK 0x10000000L
+#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING_MASK 0x20000000L
+#define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE_MASK 0x40000000L
+#define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE_MASK 0x80000000L
+//SQC_CONFIG
+#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0
+#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2
+#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4
+#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6
+#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7
+#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8
+#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb
+#define SQC_CONFIG__EVICT_LRU__SHIFT 0xc
+#define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xe
+#define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xf
+#define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0x10
+#define SQC_CONFIG__INST_PRF_COUNT__SHIFT 0x18
+#define SQC_CONFIG__INST_PRF_FILTER_DIS__SHIFT 0x1d
+#define SQC_CONFIG__DISABLE_PREFETCH_CROSS_4K_BOUNDARY_CHECK__SHIFT 0x1e
+#define SQC_CONFIG__MEM_LS_DISABLE__SHIFT 0x1f
+#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x00000003L
+#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0x0000000CL
+#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x00000030L
+#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x00000040L
+#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x00000080L
+#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x00000100L
+#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x00000800L
+#define SQC_CONFIG__EVICT_LRU_MASK 0x00003000L
+#define SQC_CONFIG__FORCE_2_BANK_MASK 0x00004000L
+#define SQC_CONFIG__FORCE_1_BANK_MASK 0x00008000L
+#define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0x00FF0000L
+#define SQC_CONFIG__INST_PRF_COUNT_MASK 0x1F000000L
+#define SQC_CONFIG__INST_PRF_FILTER_DIS_MASK 0x20000000L
+#define SQC_CONFIG__DISABLE_PREFETCH_CROSS_4K_BOUNDARY_CHECK_MASK 0x40000000L
+#define SQC_CONFIG__MEM_LS_DISABLE_MASK 0x80000000L
+//LDS_CONFIG
+#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT 0x0
+#define LDS_CONFIG__TMZ_VIOLATION_REPORTING__SHIFT 0x1
+#define LDS_CONFIG__DISABLE_RAM_CLOCK_GATING__SHIFT 0x2
+#define LDS_CONFIG__DISABLE_IDXCLK_MGCG__SHIFT 0x3
+#define LDS_CONFIG__DISABLE_MEMCLK_MGCG__SHIFT 0x4
+#define LDS_CONFIG__DISABLE_ATTRCLK_MGCG__SHIFT 0x5
+#define LDS_CONFIG__DISABLE_ATODFPCLK_MGCG__SHIFT 0x6
+#define LDS_CONFIG__DISABLE_PHASE_FGCG__SHIFT 0x7
+#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING_MASK 0x00000001L
+#define LDS_CONFIG__TMZ_VIOLATION_REPORTING_MASK 0x00000002L
+#define LDS_CONFIG__DISABLE_RAM_CLOCK_GATING_MASK 0x00000004L
+#define LDS_CONFIG__DISABLE_IDXCLK_MGCG_MASK 0x00000008L
+#define LDS_CONFIG__DISABLE_MEMCLK_MGCG_MASK 0x00000010L
+#define LDS_CONFIG__DISABLE_ATTRCLK_MGCG_MASK 0x00000020L
+#define LDS_CONFIG__DISABLE_ATODFPCLK_MGCG_MASK 0x00000040L
+#define LDS_CONFIG__DISABLE_PHASE_FGCG_MASK 0x00000080L
+//SQ_RANDOM_WAVE_PRI
+#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0
+#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7
+#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa
+#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x0000007FL
+#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x00000380L
+#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x007FFC00L
+//SQ_REG_CREDITS
+#define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x0
+#define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x8
+#define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x1c
+#define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d
+#define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x1e
+#define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x1f
+#define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x0000003FL
+#define SQ_REG_CREDITS__CMD_CREDITS_MASK 0x00000F00L
+#define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000L
+#define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000L
+#define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000L
+#define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000L
+//SQ_FIFO_SIZES
+#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0
+#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8
+#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x10
+#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12
+#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0x0000000FL
+#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0x00000F00L
+#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x00030000L
+#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0x000C0000L
+//SQ_DSM_CNTL
+#define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0
+#define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1
+#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2
+#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3
+#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8
+#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9
+#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11
+#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14
+#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15
+#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18
+#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19
+#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a
+#define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x00000001L
+#define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x00000002L
+#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x00000004L
+#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x00000008L
+#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x00000100L
+#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x00000200L
+#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x00000400L
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x00010000L
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x00020000L
+#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x00040000L
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x00080000L
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x00100000L
+#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x00200000L
+#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x01000000L
+#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x02000000L
+#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x04000000L
+//SQ_DSM_CNTL2
+#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT 0x2
+#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT 0x5
+#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT 0x8
+#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT 0xb
+#define SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT 0xe
+#define SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT 0x14
+#define SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT 0x1a
+#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK 0x000FC000L
+#define SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK 0x03F00000L
+#define SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK 0xFC000000L
+//SQ_RUNTIME_CONFIG
+#define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST__SHIFT 0x0
+#define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST_MASK 0x00000001L
+//SQ_DEBUG_STS_GLOBAL
+#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x0
+#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x1
+#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x4
+#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x10
+#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x00000001L
+#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x00000002L
+#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0x0000FFF0L
+#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0x0FFF0000L
+//SH_MEM_BASES
+#define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0
+#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10
+#define SH_MEM_BASES__PRIVATE_BASE_MASK 0x0000FFFFL
+#define SH_MEM_BASES__SHARED_BASE_MASK 0xFFFF0000L
+//SQ_TIMEOUT_CONFIG
+#define SQ_TIMEOUT_CONFIG__PERIOD_SEL__SHIFT 0x0
+#define SQ_TIMEOUT_CONFIG__TIMEOUT_FATAL_DISABLE__SHIFT 0x6
+#define SQ_TIMEOUT_CONFIG__PERIOD_SEL_MASK 0x0000003FL
+#define SQ_TIMEOUT_CONFIG__TIMEOUT_FATAL_DISABLE_MASK 0x00000040L
+//SQ_TIMEOUT_STATUS
+#define SQ_TIMEOUT_STATUS__WAVE_TIMEOUT__SHIFT 0x0
+#define SQ_TIMEOUT_STATUS__WAVE_TIMEOUT_MASK 0xFFFFFFFFL
+//SH_MEM_CONFIG
+#define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0
+#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x3
+#define SH_MEM_CONFIG__RETRY_DISABLE__SHIFT 0xc
+#define SH_MEM_CONFIG__PRIVATE_NV__SHIFT 0xd
+#define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x00000001L
+#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x00000018L
+#define SH_MEM_CONFIG__RETRY_DISABLE_MASK 0x00001000L
+#define SH_MEM_CONFIG__PRIVATE_NV_MASK 0x00002000L
+//SP_MFMA_PORTD_RD_CONFIG
+#define SP_MFMA_PORTD_RD_CONFIG__SET__SHIFT 0x0
+#define SP_MFMA_PORTD_RD_CONFIG__TYPE__SHIFT 0x1
+#define SP_MFMA_PORTD_RD_CONFIG__LAST_PASS__SHIFT 0x4
+#define SP_MFMA_PORTD_RD_CONFIG__PORTD_PATTERN__SHIFT 0x9
+#define SP_MFMA_PORTD_RD_CONFIG__SET_MASK 0x00000001L
+#define SP_MFMA_PORTD_RD_CONFIG__TYPE_MASK 0x0000000EL
+#define SP_MFMA_PORTD_RD_CONFIG__LAST_PASS_MASK 0x000001F0L
+#define SP_MFMA_PORTD_RD_CONFIG__PORTD_PATTERN_MASK 0x1FFFFE00L
+//SH_CAC_CONFIG
+#define SH_CAC_CONFIG__SQG_UTCL1_REPEATER_FGCG_DISABLE__SHIFT 0x0
+#define SH_CAC_CONFIG__SQC_UTCL1_REPEATER_FGCG_DISABLE__SHIFT 0x1
+#define SH_CAC_CONFIG__SPI_SQ_CMD_REPEATER_FGCG_DISABLE__SHIFT 0x2
+#define SH_CAC_CONFIG__SQ_MSG_REPEATER_FGCG_DISABLE__SHIFT 0x3
+#define SH_CAC_CONFIG__SQC_TC_REPEATER_FGCG_DISABLE__SHIFT 0x4
+#define SH_CAC_CONFIG__SQC_SQ_REPEATER_FGCG_DISABLE__SHIFT 0x5
+#define SH_CAC_CONFIG__SQG_TC_REPEATER_FGCG_DISABLE__SHIFT 0x6
+#define SH_CAC_CONFIG__SQC_DISABLE_RAM_CLOCK_GATING__SHIFT 0x8
+#define SH_CAC_CONFIG__SQG_DISABLE_RAM_CLOCK_GATING__SHIFT 0x9
+#define SH_CAC_CONFIG__SQC_MGCG_CLOCK_OFF_DELAY_CNT__SHIFT 0x10
+#define SH_CAC_CONFIG__SQC_MGCG_DISABLE__SHIFT 0x14
+#define SH_CAC_CONFIG__SQG_UTCL1_REPEATER_FGCG_DISABLE_MASK 0x00000001L
+#define SH_CAC_CONFIG__SQC_UTCL1_REPEATER_FGCG_DISABLE_MASK 0x00000002L
+#define SH_CAC_CONFIG__SPI_SQ_CMD_REPEATER_FGCG_DISABLE_MASK 0x00000004L
+#define SH_CAC_CONFIG__SQ_MSG_REPEATER_FGCG_DISABLE_MASK 0x00000008L
+#define SH_CAC_CONFIG__SQC_TC_REPEATER_FGCG_DISABLE_MASK 0x00000010L
+#define SH_CAC_CONFIG__SQC_SQ_REPEATER_FGCG_DISABLE_MASK 0x00000020L
+#define SH_CAC_CONFIG__SQG_TC_REPEATER_FGCG_DISABLE_MASK 0x00000040L
+#define SH_CAC_CONFIG__SQC_DISABLE_RAM_CLOCK_GATING_MASK 0x00000100L
+#define SH_CAC_CONFIG__SQG_DISABLE_RAM_CLOCK_GATING_MASK 0x00000200L
+#define SH_CAC_CONFIG__SQC_MGCG_CLOCK_OFF_DELAY_CNT_MASK 0x000F0000L
+#define SH_CAC_CONFIG__SQC_MGCG_DISABLE_MASK 0x0FF00000L
+//SQ_DEBUG_STS_GLOBAL2
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x0
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x8
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT 0x10
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT 0x18
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0x000000FFL
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0x0000FF00L
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK 0x00FF0000L
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK 0xFF000000L
+//SQ_DEBUG_STS_GLOBAL3
+#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT 0x0
+#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT 0x4
+#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK 0x0000000FL
+#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK 0x000003F0L
+//CC_GC_SHADER_RATE_CONFIG
+#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1
+#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
+#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4
+#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L
+#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L
+#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L
+//GC_USER_SHADER_RATE_CONFIG
+#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1
+#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
+#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4
+#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L
+#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L
+#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L
+//SQ_INTERRUPT_AUTO_MASK
+#define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0
+#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0x00FFFFFFL
+//SQ_INTERRUPT_MSG_CTRL
+#define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0
+#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x00000001L
+//SQ_DEBUG_PERFCOUNT_TRAP
+#define SQ_DEBUG_PERFCOUNT_TRAP__ENABLE__SHIFT 0x0
+#define SQ_DEBUG_PERFCOUNT_TRAP__COUNTER__SHIFT 0x1
+#define SQ_DEBUG_PERFCOUNT_TRAP__LIMIT__SHIFT 0x4
+#define SQ_DEBUG_PERFCOUNT_TRAP__ENABLE_MASK 0x00000001L
+#define SQ_DEBUG_PERFCOUNT_TRAP__COUNTER_MASK 0x0000000EL
+#define SQ_DEBUG_PERFCOUNT_TRAP__LIMIT_MASK 0x0FFFFFF0L
+//SQ_UTCL1_CNTL1
+#define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
+#define SQ_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
+#define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
+#define SQ_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
+#define SQ_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
+#define SQ_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
+#define SQ_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10
+#define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
+#define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
+#define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13
+#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17
+#define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18
+#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL__SHIFT 0x19
+#define SQ_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
+#define SQ_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
+#define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
+#define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
+#define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
+#define SQ_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
+#define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
+#define SQ_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
+#define SQ_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
+#define SQ_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
+#define SQ_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L
+#define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
+#define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
+#define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L
+#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L
+#define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L
+#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_MASK 0x02000000L
+#define SQ_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
+#define SQ_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
+#define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
+#define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
+//SQ_UTCL1_CNTL2
+#define SQ_UTCL1_CNTL2__SPARE__SHIFT 0x0
+#define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8
+#define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
+#define SQ_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
+#define SQ_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb
+#define SQ_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
+#define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
+#define SQ_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
+#define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
+#define SQ_UTCL1_CNTL2__RETRY_TIMER__SHIFT 0x10
+#define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
+#define SQ_UTCL1_CNTL2__PREFETCH_PAGE__SHIFT 0x1c
+#define SQ_UTCL1_CNTL2__SPARE_MASK 0x000000FFL
+#define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L
+#define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
+#define SQ_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
+#define SQ_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L
+#define SQ_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
+#define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
+#define SQ_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
+#define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
+#define SQ_UTCL1_CNTL2__RETRY_TIMER_MASK 0x007F0000L
+#define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
+#define SQ_UTCL1_CNTL2__PREFETCH_PAGE_MASK 0xF0000000L
+//SQ_UTCL1_STATUS
+#define SQ_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
+#define SQ_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
+#define SQ_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
+#define SQ_UTCL1_STATUS__RESERVED__SHIFT 0x3
+#define SQ_UTCL1_STATUS__UNUSED__SHIFT 0x10
+#define SQ_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
+#define SQ_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
+#define SQ_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
+#define SQ_UTCL1_STATUS__RESERVED_MASK 0x0000FFF8L
+#define SQ_UTCL1_STATUS__UNUSED_MASK 0xFFFF0000L
+//SQ_FED_INTERRUPT_STATUS
+#define SQ_FED_INTERRUPT_STATUS__INTERRUPT_STATUS__SHIFT 0x0
+#define SQ_FED_INTERRUPT_STATUS__INTERRUPT_SIMD_ID__SHIFT 0x2
+#define SQ_FED_INTERRUPT_STATUS__INTERRUPT_WAVE_ID__SHIFT 0x4
+#define SQ_FED_INTERRUPT_STATUS__INTERRUPT_CU_ID__SHIFT 0x8
+#define SQ_FED_INTERRUPT_STATUS__INTERRUPT_VM_ID__SHIFT 0xc
+#define SQ_FED_INTERRUPT_STATUS__TO_IH_DISABLE__SHIFT 0x11
+#define SQ_FED_INTERRUPT_STATUS__FED_HALT_DISABLE__SHIFT 0x12
+#define SQ_FED_INTERRUPT_STATUS__INTERRUPT_STATUS_MASK 0x00000001L
+#define SQ_FED_INTERRUPT_STATUS__INTERRUPT_SIMD_ID_MASK 0x0000000CL
+#define SQ_FED_INTERRUPT_STATUS__INTERRUPT_WAVE_ID_MASK 0x000000F0L
+#define SQ_FED_INTERRUPT_STATUS__INTERRUPT_CU_ID_MASK 0x00000F00L
+#define SQ_FED_INTERRUPT_STATUS__INTERRUPT_VM_ID_MASK 0x0000F000L
+#define SQ_FED_INTERRUPT_STATUS__TO_IH_DISABLE_MASK 0x00020000L
+#define SQ_FED_INTERRUPT_STATUS__FED_HALT_DISABLE_MASK 0x00040000L
+//SQ_CGTS_CONFIG
+#define SQ_CGTS_CONFIG__DGEMM_EXTRA_BUSY_PASS__SHIFT 0x0
+#define SQ_CGTS_CONFIG__XDL_EXTRA_BUSY_PASS__SHIFT 0x4
+#define SQ_CGTS_CONFIG__VALU_EXTRA_BUSY_PASS__SHIFT 0x8
+#define SQ_CGTS_CONFIG__DLOP_EXTRA_BUSY_PASS__SHIFT 0xc
+#define SQ_CGTS_CONFIG__XDL_EXTRA_GAP_PASS__SHIFT 0x10
+#define SQ_CGTS_CONFIG__DGEMM_EXTRA_GAP_PASS__SHIFT 0x12
+#define SQ_CGTS_CONFIG__DGEMM_EXTRA_BUSY_PASS_MASK 0x0000000FL
+#define SQ_CGTS_CONFIG__XDL_EXTRA_BUSY_PASS_MASK 0x000000F0L
+#define SQ_CGTS_CONFIG__VALU_EXTRA_BUSY_PASS_MASK 0x00000F00L
+#define SQ_CGTS_CONFIG__DLOP_EXTRA_BUSY_PASS_MASK 0x0000F000L
+#define SQ_CGTS_CONFIG__XDL_EXTRA_GAP_PASS_MASK 0x00030000L
+#define SQ_CGTS_CONFIG__DGEMM_EXTRA_GAP_PASS_MASK 0x000C0000L
+//SQ_SHADER_TBA_LO
+#define SQ_SHADER_TBA_LO__ADDR_LO__SHIFT 0x0
+#define SQ_SHADER_TBA_LO__ADDR_LO_MASK 0xFFFFFFFFL
+//SQ_SHADER_TBA_HI
+#define SQ_SHADER_TBA_HI__ADDR_HI__SHIFT 0x0
+#define SQ_SHADER_TBA_HI__ADDR_HI_MASK 0x000000FFL
+//SQ_SHADER_TMA_LO
+#define SQ_SHADER_TMA_LO__ADDR_LO__SHIFT 0x0
+#define SQ_SHADER_TMA_LO__ADDR_LO_MASK 0xFFFFFFFFL
+//SQ_SHADER_TMA_HI
+#define SQ_SHADER_TMA_HI__ADDR_HI__SHIFT 0x0
+#define SQ_SHADER_TMA_HI__ADDR_HI_MASK 0x000000FFL
+//SQC_DSM_CNTL
+#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x3
+#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x9
+#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0xb
+#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0xc
+#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0xe
+#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0xf
+#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x11
+#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x12
+#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14
+#define SQC_DSM_CNTL__DATA_CU3_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x15
+#define SQC_DSM_CNTL__DATA_CU3_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x17
+#define SQC_DSM_CNTL__DATA_CU3_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x18
+#define SQC_DSM_CNTL__DATA_CU3_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x1a
+#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000018L
+#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000600L
+#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000800L
+#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00003000L
+#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00004000L
+#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00018000L
+#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00020000L
+#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L
+#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L
+#define SQC_DSM_CNTL__DATA_CU3_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00600000L
+#define SQC_DSM_CNTL__DATA_CU3_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00800000L
+#define SQC_DSM_CNTL__DATA_CU3_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x03000000L
+#define SQC_DSM_CNTL__DATA_CU3_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x04000000L
+//SQC_DSM_CNTLA
+#define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3
+#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9
+#define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb
+#define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc
+#define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe
+#define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf
+#define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11
+#define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12
+#define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14
+#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15
+#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17
+#define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18
+#define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a
+#define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L
+#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L
+#define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
+#define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L
+#define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
+#define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L
+#define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L
+#define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L
+#define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L
+#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L
+#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L
+#define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L
+#define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L
+//SQC_DSM_CNTLB
+#define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3
+#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9
+#define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb
+#define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc
+#define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe
+#define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf
+#define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11
+#define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12
+#define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14
+#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15
+#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17
+#define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18
+#define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a
+#define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L
+#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L
+#define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
+#define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L
+#define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
+#define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L
+#define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L
+#define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L
+#define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L
+#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L
+#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L
+#define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L
+#define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L
+//SQC_DSM_CNTL2
+#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x2
+#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x5
+#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x8
+#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0xb
+#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0xe
+#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x11
+#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x14
+#define SQC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
+#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00100000L
+#define SQC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
+//SQC_DSM_CNTL2A
+#define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5
+#define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8
+#define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb
+#define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe
+#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11
+#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14
+#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15
+#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17
+#define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18
+#define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a
+#define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L
+#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L
+#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L
+#define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L
+#define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L
+//SQC_DSM_CNTL2B
+#define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5
+#define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8
+#define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb
+#define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe
+#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11
+#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14
+#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15
+#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17
+#define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18
+#define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a
+#define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L
+#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L
+#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L
+#define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L
+#define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L
+//SQC_DSM_CNTL2E
+#define SQC_DSM_CNTL2E__DATA_CU3_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define SQC_DSM_CNTL2E__DATA_CU3_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x2
+#define SQC_DSM_CNTL2E__DATA_CU3_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define SQC_DSM_CNTL2E__DATA_CU3_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x5
+#define SQC_DSM_CNTL2E__DATA_CU3_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define SQC_DSM_CNTL2E__DATA_CU3_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define SQC_DSM_CNTL2E__DATA_CU3_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define SQC_DSM_CNTL2E__DATA_CU3_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000020L
+//SQC_EDC_FUE_CNTL
+#define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0
+#define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10
+#define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL
+#define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L
+//SQC_EDC_CNT2
+#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x0
+#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT__SHIFT 0x2
+#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0x4
+#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT__SHIFT 0x6
+#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x8
+#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT__SHIFT 0xa
+#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0xc
+#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT__SHIFT 0xe
+#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x10
+#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT__SHIFT 0x12
+#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SEC_COUNT__SHIFT 0x14
+#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_DED_COUNT__SHIFT 0x16
+#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000003L
+#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT_MASK 0x0000000CL
+#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00000030L
+#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT_MASK 0x000000C0L
+#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000300L
+#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT_MASK 0x00000C00L
+#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00003000L
+#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT_MASK 0x0000C000L
+#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT_MASK 0x00030000L
+#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT_MASK 0x000C0000L
+#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SEC_COUNT_MASK 0x00300000L
+#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_DED_COUNT_MASK 0x00C00000L
+//SQC_EDC_CNT3
+#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x0
+#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT__SHIFT 0x2
+#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0x4
+#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT__SHIFT 0x6
+#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x8
+#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT__SHIFT 0xa
+#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0xc
+#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT__SHIFT 0xe
+#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SEC_COUNT__SHIFT 0x10
+#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_DED_COUNT__SHIFT 0x12
+#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000003L
+#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT_MASK 0x0000000CL
+#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00000030L
+#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT_MASK 0x000000C0L
+#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000300L
+#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT_MASK 0x00000C00L
+#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00003000L
+#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT_MASK 0x0000C000L
+#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SEC_COUNT_MASK 0x00030000L
+#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_DED_COUNT_MASK 0x000C0000L
+//SQC_EDC_PARITY_CNT3
+#define SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_SEC_COUNT__SHIFT 0x0
+#define SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_DED_COUNT__SHIFT 0x2
+#define SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_SEC_COUNT__SHIFT 0x4
+#define SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_DED_COUNT__SHIFT 0x6
+#define SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_SEC_COUNT__SHIFT 0x8
+#define SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_DED_COUNT__SHIFT 0xa
+#define SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_SEC_COUNT__SHIFT 0xc
+#define SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_DED_COUNT__SHIFT 0xe
+#define SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SEC_COUNT__SHIFT 0x10
+#define SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_DED_COUNT__SHIFT 0x12
+#define SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_SEC_COUNT__SHIFT 0x14
+#define SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_DED_COUNT__SHIFT 0x16
+#define SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_SEC_COUNT__SHIFT 0x18
+#define SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_DED_COUNT__SHIFT 0x1a
+#define SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_SEC_COUNT__SHIFT 0x1c
+#define SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_DED_COUNT__SHIFT 0x1e
+#define SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_SEC_COUNT_MASK 0x00000003L
+#define SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_DED_COUNT_MASK 0x0000000CL
+#define SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_SEC_COUNT_MASK 0x00000030L
+#define SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_DED_COUNT_MASK 0x000000C0L
+#define SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_SEC_COUNT_MASK 0x00000300L
+#define SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_DED_COUNT_MASK 0x00000C00L
+#define SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_SEC_COUNT_MASK 0x00003000L
+#define SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_DED_COUNT_MASK 0x0000C000L
+#define SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SEC_COUNT_MASK 0x00030000L
+#define SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_DED_COUNT_MASK 0x000C0000L
+#define SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_SEC_COUNT_MASK 0x00300000L
+#define SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_DED_COUNT_MASK 0x00C00000L
+#define SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_SEC_COUNT_MASK 0x03000000L
+#define SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_DED_COUNT_MASK 0x0C000000L
+#define SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_SEC_COUNT_MASK 0x30000000L
+#define SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_DED_COUNT_MASK 0xC0000000L
+//SQ_DEBUG
+#define SQ_DEBUG__SINGLE_MEMOP__SHIFT 0x0
+#define SQ_DEBUG__SINGLE_MEMOP_MASK 0x00000001L
+//SQ_REG_TIMESTAMP
+#define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT 0x0
+#define SQ_REG_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL
+//SQ_CMD_TIMESTAMP
+#define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0
+#define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL
+//SQ_HOSTTRAP_STATUS
+#define SQ_HOSTTRAP_STATUS__HTPENDINGCOUNT__SHIFT 0x0
+#define SQ_HOSTTRAP_STATUS__HTPENDING_OVERRIDE__SHIFT 0x8
+#define SQ_HOSTTRAP_STATUS__HTPENDINGCOUNT_MASK 0x000000FFL
+#define SQ_HOSTTRAP_STATUS__HTPENDING_OVERRIDE_MASK 0x00000100L
+//SQ_IND_INDEX
+#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0
+#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4
+#define SQ_IND_INDEX__THREAD_ID__SHIFT 0x6
+#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xc
+#define SQ_IND_INDEX__FORCE_READ__SHIFT 0xd
+#define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0xe
+#define SQ_IND_INDEX__UNINDEXED__SHIFT 0xf
+#define SQ_IND_INDEX__INDEX__SHIFT 0x10
+#define SQ_IND_INDEX__WAVE_ID_MASK 0x0000000FL
+#define SQ_IND_INDEX__SIMD_ID_MASK 0x00000030L
+#define SQ_IND_INDEX__THREAD_ID_MASK 0x00000FC0L
+#define SQ_IND_INDEX__AUTO_INCR_MASK 0x00001000L
+#define SQ_IND_INDEX__FORCE_READ_MASK 0x00002000L
+#define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x00004000L
+#define SQ_IND_INDEX__UNINDEXED_MASK 0x00008000L
+#define SQ_IND_INDEX__INDEX_MASK 0xFFFF0000L
+//SQ_IND_DATA
+#define SQ_IND_DATA__DATA__SHIFT 0x0
+#define SQ_IND_DATA__DATA_MASK 0xFFFFFFFFL
+//SQ_CONFIG1
+#define SQ_CONFIG1__DISABLE_XDL_PORTD_CO_EXEC__SHIFT 0x0
+#define SQ_CONFIG1__DISABLE_MGCG_ON_IBUF__SHIFT 0x1
+#define SQ_CONFIG1__DISABLE_MGCG_ON_PERF__SHIFT 0x2
+#define SQ_CONFIG1__DISABLE_MGCG_ON_EXP__SHIFT 0x3
+#define SQ_CONFIG1__DISABLE_MGCG_ON_SCA__SHIFT 0x4
+#define SQ_CONFIG1__DISABLE_MGCG_ON_SREG__SHIFT 0x5
+#define SQ_CONFIG1__DISABLE_MGCG_ON_VDEC__SHIFT 0x6
+#define SQ_CONFIG1__DISABLE_XNACK_CHECK_IN_RETRY_DISABLE__SHIFT 0xc
+#define SQ_CONFIG1__DISABLE_BARRIER_ADDR_WATCH__SHIFT 0xd
+#define SQ_CONFIG1__DISABLE_BARRIER_MEMVIOL_WAIT__SHIFT 0xe
+#define SQ_CONFIG1__DISABLE_BARRIER_MEMVIOL_BACKOFF__SHIFT 0xf
+#define SQ_CONFIG1__SP_FGCG_REP_OVERRIDE__SHIFT 0x18
+#define SQ_CONFIG1__DPMACC_MGCG_OVERRIDE__SHIFT 0x19
+#define SQ_CONFIG1__XDLMACC_MGCG_OVERRIDE__SHIFT 0x1a
+#define SQ_CONFIG1__TRANSMACC_MGCG_OVERRIDE__SHIFT 0x1b
+#define SQ_CONFIG1__SPMACC_MGCG_OVERRIDE__SHIFT 0x1c
+#define SQ_CONFIG1__DPMACC_DGEMM2X_MGCG_OVERRIDE__SHIFT 0x1d
+#define SQ_CONFIG1__DISABLE_SP_VGPR_READ_SKIP__SHIFT 0x1e
+#define SQ_CONFIG1__SP_SRC_1ST_BUFFER_MGCG_OVERRIDE__SHIFT 0x1f
+#define SQ_CONFIG1__DISABLE_XDL_PORTD_CO_EXEC_MASK 0x00000001L
+#define SQ_CONFIG1__DISABLE_MGCG_ON_IBUF_MASK 0x00000002L
+#define SQ_CONFIG1__DISABLE_MGCG_ON_PERF_MASK 0x00000004L
+#define SQ_CONFIG1__DISABLE_MGCG_ON_EXP_MASK 0x00000008L
+#define SQ_CONFIG1__DISABLE_MGCG_ON_SCA_MASK 0x00000010L
+#define SQ_CONFIG1__DISABLE_MGCG_ON_SREG_MASK 0x00000020L
+#define SQ_CONFIG1__DISABLE_MGCG_ON_VDEC_MASK 0x00000040L
+#define SQ_CONFIG1__DISABLE_XNACK_CHECK_IN_RETRY_DISABLE_MASK 0x00001000L
+#define SQ_CONFIG1__DISABLE_BARRIER_ADDR_WATCH_MASK 0x00002000L
+#define SQ_CONFIG1__DISABLE_BARRIER_MEMVIOL_WAIT_MASK 0x00004000L
+#define SQ_CONFIG1__DISABLE_BARRIER_MEMVIOL_BACKOFF_MASK 0x00008000L
+#define SQ_CONFIG1__SP_FGCG_REP_OVERRIDE_MASK 0x01000000L
+#define SQ_CONFIG1__DPMACC_MGCG_OVERRIDE_MASK 0x02000000L
+#define SQ_CONFIG1__XDLMACC_MGCG_OVERRIDE_MASK 0x04000000L
+#define SQ_CONFIG1__TRANSMACC_MGCG_OVERRIDE_MASK 0x08000000L
+#define SQ_CONFIG1__SPMACC_MGCG_OVERRIDE_MASK 0x10000000L
+#define SQ_CONFIG1__DPMACC_DGEMM2X_MGCG_OVERRIDE_MASK 0x20000000L
+#define SQ_CONFIG1__DISABLE_SP_VGPR_READ_SKIP_MASK 0x40000000L
+#define SQ_CONFIG1__SP_SRC_1ST_BUFFER_MGCG_OVERRIDE_MASK 0x80000000L
+//SQ_CMD
+#define SQ_CMD__CMD__SHIFT 0x0
+#define SQ_CMD__MODE__SHIFT 0x4
+#define SQ_CMD__CHECK_VMID__SHIFT 0x7
+#define SQ_CMD__DATA__SHIFT 0x8
+#define SQ_CMD__WAVE_ID__SHIFT 0x10
+#define SQ_CMD__SIMD_ID__SHIFT 0x14
+#define SQ_CMD__QUEUE_ID__SHIFT 0x18
+#define SQ_CMD__VM_ID__SHIFT 0x1c
+#define SQ_CMD__CMD_MASK 0x00000007L
+#define SQ_CMD__MODE_MASK 0x00000070L
+#define SQ_CMD__CHECK_VMID_MASK 0x00000080L
+#define SQ_CMD__DATA_MASK 0x00000F00L
+#define SQ_CMD__WAVE_ID_MASK 0x000F0000L
+#define SQ_CMD__SIMD_ID_MASK 0x00300000L
+#define SQ_CMD__QUEUE_ID_MASK 0x07000000L
+#define SQ_CMD__VM_ID_MASK 0xF0000000L
+//SQ_TIME_HI
+#define SQ_TIME_HI__TIME__SHIFT 0x0
+#define SQ_TIME_HI__TIME_MASK 0xFFFFFFFFL
+//SQ_TIME_LO
+#define SQ_TIME_LO__TIME__SHIFT 0x0
+#define SQ_TIME_LO__TIME_MASK 0xFFFFFFFFL
+//SQ_DS_0
+#define SQ_DS_0__OFFSET0__SHIFT 0x0
+#define SQ_DS_0__OFFSET1__SHIFT 0x8
+#define SQ_DS_0__GDS__SHIFT 0x10
+#define SQ_DS_0__OP__SHIFT 0x11
+#define SQ_DS_0__ACC__SHIFT 0x19
+#define SQ_DS_0__ENCODING__SHIFT 0x1a
+#define SQ_DS_0__OFFSET0_MASK 0x000000FFL
+#define SQ_DS_0__OFFSET1_MASK 0x0000FF00L
+#define SQ_DS_0__GDS_MASK 0x00010000L
+#define SQ_DS_0__OP_MASK 0x01FE0000L
+#define SQ_DS_0__ACC_MASK 0x02000000L
+#define SQ_DS_0__ENCODING_MASK 0xFC000000L
+//SQ_DS_1
+#define SQ_DS_1__ADDR__SHIFT 0x0
+#define SQ_DS_1__DATA0__SHIFT 0x8
+#define SQ_DS_1__DATA1__SHIFT 0x10
+#define SQ_DS_1__VDST__SHIFT 0x18
+#define SQ_DS_1__ADDR_MASK 0x000000FFL
+#define SQ_DS_1__DATA0_MASK 0x0000FF00L
+#define SQ_DS_1__DATA1_MASK 0x00FF0000L
+#define SQ_DS_1__VDST_MASK 0xFF000000L
+//SQ_EXP_0
+#define SQ_EXP_0__EN__SHIFT 0x0
+#define SQ_EXP_0__TGT__SHIFT 0x4
+#define SQ_EXP_0__COMPR__SHIFT 0xa
+#define SQ_EXP_0__DONE__SHIFT 0xb
+#define SQ_EXP_0__VM__SHIFT 0xc
+#define SQ_EXP_0__ENCODING__SHIFT 0x1a
+#define SQ_EXP_0__EN_MASK 0x0000000FL
+#define SQ_EXP_0__TGT_MASK 0x000003F0L
+#define SQ_EXP_0__COMPR_MASK 0x00000400L
+#define SQ_EXP_0__DONE_MASK 0x00000800L
+#define SQ_EXP_0__VM_MASK 0x00001000L
+#define SQ_EXP_0__ENCODING_MASK 0xFC000000L
+//SQ_EXP_1
+#define SQ_EXP_1__VSRC0__SHIFT 0x0
+#define SQ_EXP_1__VSRC1__SHIFT 0x8
+#define SQ_EXP_1__VSRC2__SHIFT 0x10
+#define SQ_EXP_1__VSRC3__SHIFT 0x18
+#define SQ_EXP_1__VSRC0_MASK 0x000000FFL
+#define SQ_EXP_1__VSRC1_MASK 0x0000FF00L
+#define SQ_EXP_1__VSRC2_MASK 0x00FF0000L
+#define SQ_EXP_1__VSRC3_MASK 0xFF000000L
+//SQ_FLAT_0
+#define SQ_FLAT_0__OFFSET__SHIFT 0x0
+#define SQ_FLAT_0__LDS__SHIFT 0xd
+#define SQ_FLAT_0__SEG__SHIFT 0xe
+#define SQ_FLAT_0__GLC__SHIFT 0x10
+#define SQ_FLAT_0__SLC__SHIFT 0x11
+#define SQ_FLAT_0__OP__SHIFT 0x12
+#define SQ_FLAT_0__SCC__SHIFT 0x19
+#define SQ_FLAT_0__ENCODING__SHIFT 0x1a
+#define SQ_FLAT_0__OFFSET_MASK 0x00000FFFL
+#define SQ_FLAT_0__LDS_MASK 0x00002000L
+#define SQ_FLAT_0__SEG_MASK 0x0000C000L
+#define SQ_FLAT_0__GLC_MASK 0x00010000L
+#define SQ_FLAT_0__SLC_MASK 0x00020000L
+#define SQ_FLAT_0__OP_MASK 0x01FC0000L
+#define SQ_FLAT_0__SCC_MASK 0x02000000L
+#define SQ_FLAT_0__ENCODING_MASK 0xFC000000L
+//SQ_FLAT_1
+#define SQ_FLAT_1__ADDR__SHIFT 0x0
+#define SQ_FLAT_1__DATA__SHIFT 0x8
+#define SQ_FLAT_1__SADDR__SHIFT 0x10
+#define SQ_FLAT_1__ACC__SHIFT 0x17
+#define SQ_FLAT_1__VDST__SHIFT 0x18
+#define SQ_FLAT_1__ADDR_MASK 0x000000FFL
+#define SQ_FLAT_1__DATA_MASK 0x0000FF00L
+#define SQ_FLAT_1__SADDR_MASK 0x007F0000L
+#define SQ_FLAT_1__ACC_MASK 0x00800000L
+#define SQ_FLAT_1__VDST_MASK 0xFF000000L
+//SQ_GLBL_0
+#define SQ_GLBL_0__OFFSET__SHIFT 0x0
+#define SQ_GLBL_0__LDS__SHIFT 0xd
+#define SQ_GLBL_0__SEG__SHIFT 0xe
+#define SQ_GLBL_0__GLC__SHIFT 0x10
+#define SQ_GLBL_0__SLC__SHIFT 0x11
+#define SQ_GLBL_0__OP__SHIFT 0x12
+#define SQ_GLBL_0__SCC__SHIFT 0x19
+#define SQ_GLBL_0__ENCODING__SHIFT 0x1a
+#define SQ_GLBL_0__OFFSET_MASK 0x00001FFFL
+#define SQ_GLBL_0__LDS_MASK 0x00002000L
+#define SQ_GLBL_0__SEG_MASK 0x0000C000L
+#define SQ_GLBL_0__GLC_MASK 0x00010000L
+#define SQ_GLBL_0__SLC_MASK 0x00020000L
+#define SQ_GLBL_0__OP_MASK 0x01FC0000L
+#define SQ_GLBL_0__SCC_MASK 0x02000000L
+#define SQ_GLBL_0__ENCODING_MASK 0xFC000000L
+//SQ_GLBL_1
+#define SQ_GLBL_1__ADDR__SHIFT 0x0
+#define SQ_GLBL_1__DATA__SHIFT 0x8
+#define SQ_GLBL_1__SADDR__SHIFT 0x10
+#define SQ_GLBL_1__ACC__SHIFT 0x17
+#define SQ_GLBL_1__VDST__SHIFT 0x18
+#define SQ_GLBL_1__ADDR_MASK 0x000000FFL
+#define SQ_GLBL_1__DATA_MASK 0x0000FF00L
+#define SQ_GLBL_1__SADDR_MASK 0x007F0000L
+#define SQ_GLBL_1__ACC_MASK 0x00800000L
+#define SQ_GLBL_1__VDST_MASK 0xFF000000L
+//SQ_INST
+#define SQ_INST__ENCODING__SHIFT 0x0
+#define SQ_INST__ENCODING_MASK 0xFFFFFFFFL
+//SQ_MIMG_0
+#define SQ_MIMG_0__OPM__SHIFT 0x0
+#define SQ_MIMG_0__SCC__SHIFT 0x7
+#define SQ_MIMG_0__DMASK__SHIFT 0x8
+#define SQ_MIMG_0__UNORM__SHIFT 0xc
+#define SQ_MIMG_0__GLC__SHIFT 0xd
+#define SQ_MIMG_0__DA__SHIFT 0xe
+#define SQ_MIMG_0__A16__SHIFT 0xf
+#define SQ_MIMG_0__ACC__SHIFT 0x10
+#define SQ_MIMG_0__LWE__SHIFT 0x11
+#define SQ_MIMG_0__OP__SHIFT 0x12
+#define SQ_MIMG_0__SLC__SHIFT 0x19
+#define SQ_MIMG_0__ENCODING__SHIFT 0x1a
+#define SQ_MIMG_0__OPM_MASK 0x00000001L
+#define SQ_MIMG_0__SCC_MASK 0x00000080L
+#define SQ_MIMG_0__DMASK_MASK 0x00000F00L
+#define SQ_MIMG_0__UNORM_MASK 0x00001000L
+#define SQ_MIMG_0__GLC_MASK 0x00002000L
+#define SQ_MIMG_0__DA_MASK 0x00004000L
+#define SQ_MIMG_0__A16_MASK 0x00008000L
+#define SQ_MIMG_0__ACC_MASK 0x00010000L
+#define SQ_MIMG_0__LWE_MASK 0x00020000L
+#define SQ_MIMG_0__OP_MASK 0x01FC0000L
+#define SQ_MIMG_0__SLC_MASK 0x02000000L
+#define SQ_MIMG_0__ENCODING_MASK 0xFC000000L
+//SQ_MIMG_1
+#define SQ_MIMG_1__VADDR__SHIFT 0x0
+#define SQ_MIMG_1__VDATA__SHIFT 0x8
+#define SQ_MIMG_1__SRSRC__SHIFT 0x10
+#define SQ_MIMG_1__SSAMP__SHIFT 0x15
+#define SQ_MIMG_1__D16__SHIFT 0x1f
+#define SQ_MIMG_1__VADDR_MASK 0x000000FFL
+#define SQ_MIMG_1__VDATA_MASK 0x0000FF00L
+#define SQ_MIMG_1__SRSRC_MASK 0x001F0000L
+#define SQ_MIMG_1__SSAMP_MASK 0x03E00000L
+#define SQ_MIMG_1__D16_MASK 0x80000000L
+//SQ_MTBUF_0
+#define SQ_MTBUF_0__OFFSET__SHIFT 0x0
+#define SQ_MTBUF_0__OFFEN__SHIFT 0xc
+#define SQ_MTBUF_0__IDXEN__SHIFT 0xd
+#define SQ_MTBUF_0__GLC__SHIFT 0xe
+#define SQ_MTBUF_0__OP__SHIFT 0xf
+#define SQ_MTBUF_0__DFMT__SHIFT 0x13
+#define SQ_MTBUF_0__NFMT__SHIFT 0x17
+#define SQ_MTBUF_0__ENCODING__SHIFT 0x1a
+#define SQ_MTBUF_0__OFFSET_MASK 0x00000FFFL
+#define SQ_MTBUF_0__OFFEN_MASK 0x00001000L
+#define SQ_MTBUF_0__IDXEN_MASK 0x00002000L
+#define SQ_MTBUF_0__GLC_MASK 0x00004000L
+#define SQ_MTBUF_0__OP_MASK 0x00078000L
+#define SQ_MTBUF_0__DFMT_MASK 0x00780000L
+#define SQ_MTBUF_0__NFMT_MASK 0x03800000L
+#define SQ_MTBUF_0__ENCODING_MASK 0xFC000000L
+//SQ_MTBUF_1
+#define SQ_MTBUF_1__VADDR__SHIFT 0x0
+#define SQ_MTBUF_1__VDATA__SHIFT 0x8
+#define SQ_MTBUF_1__SRSRC__SHIFT 0x10
+#define SQ_MTBUF_1__SCC__SHIFT 0x15
+#define SQ_MTBUF_1__SLC__SHIFT 0x16
+#define SQ_MTBUF_1__ACC__SHIFT 0x17
+#define SQ_MTBUF_1__SOFFSET__SHIFT 0x18
+#define SQ_MTBUF_1__VADDR_MASK 0x000000FFL
+#define SQ_MTBUF_1__VDATA_MASK 0x0000FF00L
+#define SQ_MTBUF_1__SRSRC_MASK 0x001F0000L
+#define SQ_MTBUF_1__SCC_MASK 0x00200000L
+#define SQ_MTBUF_1__SLC_MASK 0x00400000L
+#define SQ_MTBUF_1__ACC_MASK 0x00800000L
+#define SQ_MTBUF_1__SOFFSET_MASK 0xFF000000L
+//SQ_MUBUF_0
+#define SQ_MUBUF_0__OFFSET__SHIFT 0x0
+#define SQ_MUBUF_0__OFFEN__SHIFT 0xc
+#define SQ_MUBUF_0__IDXEN__SHIFT 0xd
+#define SQ_MUBUF_0__GLC__SHIFT 0xe
+#define SQ_MUBUF_0__SCC__SHIFT 0xf
+#define SQ_MUBUF_0__LDS__SHIFT 0x10
+#define SQ_MUBUF_0__SLC__SHIFT 0x11
+#define SQ_MUBUF_0__OP__SHIFT 0x12
+#define SQ_MUBUF_0__ENCODING__SHIFT 0x1a
+#define SQ_MUBUF_0__OFFSET_MASK 0x00000FFFL
+#define SQ_MUBUF_0__OFFEN_MASK 0x00001000L
+#define SQ_MUBUF_0__IDXEN_MASK 0x00002000L
+#define SQ_MUBUF_0__GLC_MASK 0x00004000L
+#define SQ_MUBUF_0__SCC_MASK 0x00008000L
+#define SQ_MUBUF_0__LDS_MASK 0x00010000L
+#define SQ_MUBUF_0__SLC_MASK 0x00020000L
+#define SQ_MUBUF_0__OP_MASK 0x01FC0000L
+#define SQ_MUBUF_0__ENCODING_MASK 0xFC000000L
+//SQ_MUBUF_1
+#define SQ_MUBUF_1__VADDR__SHIFT 0x0
+#define SQ_MUBUF_1__VDATA__SHIFT 0x8
+#define SQ_MUBUF_1__SRSRC__SHIFT 0x10
+#define SQ_MUBUF_1__ACC__SHIFT 0x17
+#define SQ_MUBUF_1__SOFFSET__SHIFT 0x18
+#define SQ_MUBUF_1__VADDR_MASK 0x000000FFL
+#define SQ_MUBUF_1__VDATA_MASK 0x0000FF00L
+#define SQ_MUBUF_1__SRSRC_MASK 0x001F0000L
+#define SQ_MUBUF_1__ACC_MASK 0x00800000L
+#define SQ_MUBUF_1__SOFFSET_MASK 0xFF000000L
+//SQ_SCRATCH_0
+#define SQ_SCRATCH_0__OFFSET__SHIFT 0x0
+#define SQ_SCRATCH_0__LDS__SHIFT 0xd
+#define SQ_SCRATCH_0__SEG__SHIFT 0xe
+#define SQ_SCRATCH_0__GLC__SHIFT 0x10
+#define SQ_SCRATCH_0__SLC__SHIFT 0x11
+#define SQ_SCRATCH_0__OP__SHIFT 0x12
+#define SQ_SCRATCH_0__SCC__SHIFT 0x19
+#define SQ_SCRATCH_0__ENCODING__SHIFT 0x1a
+#define SQ_SCRATCH_0__OFFSET_MASK 0x00001FFFL
+#define SQ_SCRATCH_0__LDS_MASK 0x00002000L
+#define SQ_SCRATCH_0__SEG_MASK 0x0000C000L
+#define SQ_SCRATCH_0__GLC_MASK 0x00010000L
+#define SQ_SCRATCH_0__SLC_MASK 0x00020000L
+#define SQ_SCRATCH_0__OP_MASK 0x01FC0000L
+#define SQ_SCRATCH_0__SCC_MASK 0x02000000L
+#define SQ_SCRATCH_0__ENCODING_MASK 0xFC000000L
+//SQ_SCRATCH_1
+#define SQ_SCRATCH_1__ADDR__SHIFT 0x0
+#define SQ_SCRATCH_1__DATA__SHIFT 0x8
+#define SQ_SCRATCH_1__SADDR__SHIFT 0x10
+#define SQ_SCRATCH_1__ACC__SHIFT 0x17
+#define SQ_SCRATCH_1__VDST__SHIFT 0x18
+#define SQ_SCRATCH_1__ADDR_MASK 0x000000FFL
+#define SQ_SCRATCH_1__DATA_MASK 0x0000FF00L
+#define SQ_SCRATCH_1__SADDR_MASK 0x007F0000L
+#define SQ_SCRATCH_1__ACC_MASK 0x00800000L
+#define SQ_SCRATCH_1__VDST_MASK 0xFF000000L
+//SQ_SMEM_0
+#define SQ_SMEM_0__SBASE__SHIFT 0x0
+#define SQ_SMEM_0__SDATA__SHIFT 0x6
+#define SQ_SMEM_0__SOFFSET_EN__SHIFT 0xe
+#define SQ_SMEM_0__NV__SHIFT 0xf
+#define SQ_SMEM_0__GLC__SHIFT 0x10
+#define SQ_SMEM_0__IMM__SHIFT 0x11
+#define SQ_SMEM_0__OP__SHIFT 0x12
+#define SQ_SMEM_0__ENCODING__SHIFT 0x1a
+#define SQ_SMEM_0__SBASE_MASK 0x0000003FL
+#define SQ_SMEM_0__SDATA_MASK 0x00001FC0L
+#define SQ_SMEM_0__SOFFSET_EN_MASK 0x00004000L
+#define SQ_SMEM_0__NV_MASK 0x00008000L
+#define SQ_SMEM_0__GLC_MASK 0x00010000L
+#define SQ_SMEM_0__IMM_MASK 0x00020000L
+#define SQ_SMEM_0__OP_MASK 0x03FC0000L
+#define SQ_SMEM_0__ENCODING_MASK 0xFC000000L
+//SQ_SMEM_1
+#define SQ_SMEM_1__OFFSET__SHIFT 0x0
+#define SQ_SMEM_1__SOFFSET__SHIFT 0x19
+#define SQ_SMEM_1__OFFSET_MASK 0x001FFFFFL
+#define SQ_SMEM_1__SOFFSET_MASK 0xFE000000L
+//SQ_SOP1
+#define SQ_SOP1__SSRC0__SHIFT 0x0
+#define SQ_SOP1__OP__SHIFT 0x8
+#define SQ_SOP1__SDST__SHIFT 0x10
+#define SQ_SOP1__ENCODING__SHIFT 0x17
+#define SQ_SOP1__SSRC0_MASK 0x000000FFL
+#define SQ_SOP1__OP_MASK 0x0000FF00L
+#define SQ_SOP1__SDST_MASK 0x007F0000L
+#define SQ_SOP1__ENCODING_MASK 0xFF800000L
+//SQ_SOP2
+#define SQ_SOP2__SSRC0__SHIFT 0x0
+#define SQ_SOP2__SSRC1__SHIFT 0x8
+#define SQ_SOP2__SDST__SHIFT 0x10
+#define SQ_SOP2__OP__SHIFT 0x17
+#define SQ_SOP2__ENCODING__SHIFT 0x1e
+#define SQ_SOP2__SSRC0_MASK 0x000000FFL
+#define SQ_SOP2__SSRC1_MASK 0x0000FF00L
+#define SQ_SOP2__SDST_MASK 0x007F0000L
+#define SQ_SOP2__OP_MASK 0x3F800000L
+#define SQ_SOP2__ENCODING_MASK 0xC0000000L
+//SQ_SOPC
+#define SQ_SOPC__SSRC0__SHIFT 0x0
+#define SQ_SOPC__SSRC1__SHIFT 0x8
+#define SQ_SOPC__OP__SHIFT 0x10
+#define SQ_SOPC__ENCODING__SHIFT 0x17
+#define SQ_SOPC__SSRC0_MASK 0x000000FFL
+#define SQ_SOPC__SSRC1_MASK 0x0000FF00L
+#define SQ_SOPC__OP_MASK 0x007F0000L
+#define SQ_SOPC__ENCODING_MASK 0xFF800000L
+//SQ_SOPK
+#define SQ_SOPK__SIMM16__SHIFT 0x0
+#define SQ_SOPK__SDST__SHIFT 0x10
+#define SQ_SOPK__OP__SHIFT 0x17
+#define SQ_SOPK__ENCODING__SHIFT 0x1c
+#define SQ_SOPK__SIMM16_MASK 0x0000FFFFL
+#define SQ_SOPK__SDST_MASK 0x007F0000L
+#define SQ_SOPK__OP_MASK 0x0F800000L
+#define SQ_SOPK__ENCODING_MASK 0xF0000000L
+//SQ_SOPP
+#define SQ_SOPP__SIMM16__SHIFT 0x0
+#define SQ_SOPP__OP__SHIFT 0x10
+#define SQ_SOPP__ENCODING__SHIFT 0x17
+#define SQ_SOPP__SIMM16_MASK 0x0000FFFFL
+#define SQ_SOPP__OP_MASK 0x007F0000L
+#define SQ_SOPP__ENCODING_MASK 0xFF800000L
+//SQ_VINTRP
+#define SQ_VINTRP__VSRC__SHIFT 0x0
+#define SQ_VINTRP__ATTRCHAN__SHIFT 0x8
+#define SQ_VINTRP__ATTR__SHIFT 0xa
+#define SQ_VINTRP__OP__SHIFT 0x10
+#define SQ_VINTRP__VDST__SHIFT 0x12
+#define SQ_VINTRP__ENCODING__SHIFT 0x1a
+#define SQ_VINTRP__VSRC_MASK 0x000000FFL
+#define SQ_VINTRP__ATTRCHAN_MASK 0x00000300L
+#define SQ_VINTRP__ATTR_MASK 0x0000FC00L
+#define SQ_VINTRP__OP_MASK 0x00030000L
+#define SQ_VINTRP__VDST_MASK 0x03FC0000L
+#define SQ_VINTRP__ENCODING_MASK 0xFC000000L
+//SQ_VOP1
+#define SQ_VOP1__SRC0__SHIFT 0x0
+#define SQ_VOP1__OP__SHIFT 0x9
+#define SQ_VOP1__VDST__SHIFT 0x11
+#define SQ_VOP1__ENCODING__SHIFT 0x19
+#define SQ_VOP1__SRC0_MASK 0x000001FFL
+#define SQ_VOP1__OP_MASK 0x0001FE00L
+#define SQ_VOP1__VDST_MASK 0x01FE0000L
+#define SQ_VOP1__ENCODING_MASK 0xFE000000L
+//SQ_VOP2
+#define SQ_VOP2__SRC0__SHIFT 0x0
+#define SQ_VOP2__VSRC1__SHIFT 0x9
+#define SQ_VOP2__VDST__SHIFT 0x11
+#define SQ_VOP2__OP__SHIFT 0x19
+#define SQ_VOP2__ENCODING__SHIFT 0x1f
+#define SQ_VOP2__SRC0_MASK 0x000001FFL
+#define SQ_VOP2__VSRC1_MASK 0x0001FE00L
+#define SQ_VOP2__VDST_MASK 0x01FE0000L
+#define SQ_VOP2__OP_MASK 0x7E000000L
+#define SQ_VOP2__ENCODING_MASK 0x80000000L
+//SQ_VOP3P_0
+#define SQ_VOP3P_0__VDST__SHIFT 0x0
+#define SQ_VOP3P_0__NEG_HI__SHIFT 0x8
+#define SQ_VOP3P_0__OP_SEL__SHIFT 0xb
+#define SQ_VOP3P_0__OP_SEL_HI_2__SHIFT 0xe
+#define SQ_VOP3P_0__CLAMP__SHIFT 0xf
+#define SQ_VOP3P_0__OP__SHIFT 0x10
+#define SQ_VOP3P_0__ENCODING__SHIFT 0x17
+#define SQ_VOP3P_0__VDST_MASK 0x000000FFL
+#define SQ_VOP3P_0__NEG_HI_MASK 0x00000700L
+#define SQ_VOP3P_0__OP_SEL_MASK 0x00003800L
+#define SQ_VOP3P_0__OP_SEL_HI_2_MASK 0x00004000L
+#define SQ_VOP3P_0__CLAMP_MASK 0x00008000L
+#define SQ_VOP3P_0__OP_MASK 0x007F0000L
+#define SQ_VOP3P_0__ENCODING_MASK 0xFF800000L
+//SQ_VOP3P_1
+#define SQ_VOP3P_1__SRC0__SHIFT 0x0
+#define SQ_VOP3P_1__SRC1__SHIFT 0x9
+#define SQ_VOP3P_1__SRC2__SHIFT 0x12
+#define SQ_VOP3P_1__OP_SEL_HI__SHIFT 0x1b
+#define SQ_VOP3P_1__NEG__SHIFT 0x1d
+#define SQ_VOP3P_1__SRC0_MASK 0x000001FFL
+#define SQ_VOP3P_1__SRC1_MASK 0x0003FE00L
+#define SQ_VOP3P_1__SRC2_MASK 0x07FC0000L
+#define SQ_VOP3P_1__OP_SEL_HI_MASK 0x18000000L
+#define SQ_VOP3P_1__NEG_MASK 0xE0000000L
+//SQ_VOP3P_MFMA_0
+#define SQ_VOP3P_MFMA_0__VDST__SHIFT 0x0
+#define SQ_VOP3P_MFMA_0__CBSZ__SHIFT 0x8
+#define SQ_VOP3P_MFMA_0__ABID__SHIFT 0xb
+#define SQ_VOP3P_MFMA_0__ACC_CD__SHIFT 0xf
+#define SQ_VOP3P_MFMA_0__OP__SHIFT 0x10
+#define SQ_VOP3P_MFMA_0__ENCODING__SHIFT 0x17
+#define SQ_VOP3P_MFMA_0__VDST_MASK 0x000000FFL
+#define SQ_VOP3P_MFMA_0__CBSZ_MASK 0x00000700L
+#define SQ_VOP3P_MFMA_0__ABID_MASK 0x00007800L
+#define SQ_VOP3P_MFMA_0__ACC_CD_MASK 0x00008000L
+#define SQ_VOP3P_MFMA_0__OP_MASK 0x007F0000L
+#define SQ_VOP3P_MFMA_0__ENCODING_MASK 0xFF800000L
+//SQ_VOP3P_MFMA_1
+#define SQ_VOP3P_MFMA_1__SRC0__SHIFT 0x0
+#define SQ_VOP3P_MFMA_1__SRC1__SHIFT 0x9
+#define SQ_VOP3P_MFMA_1__SRC2__SHIFT 0x12
+#define SQ_VOP3P_MFMA_1__ACC__SHIFT 0x1b
+#define SQ_VOP3P_MFMA_1__BLGP__SHIFT 0x1d
+#define SQ_VOP3P_MFMA_1__SRC0_MASK 0x000001FFL
+#define SQ_VOP3P_MFMA_1__SRC1_MASK 0x0003FE00L
+#define SQ_VOP3P_MFMA_1__SRC2_MASK 0x07FC0000L
+#define SQ_VOP3P_MFMA_1__ACC_MASK 0x18000000L
+#define SQ_VOP3P_MFMA_1__BLGP_MASK 0xE0000000L
+//SQ_VOP3_0
+#define SQ_VOP3_0__VDST__SHIFT 0x0
+#define SQ_VOP3_0__ABS__SHIFT 0x8
+#define SQ_VOP3_0__OP_SEL__SHIFT 0xb
+#define SQ_VOP3_0__CLAMP__SHIFT 0xf
+#define SQ_VOP3_0__OP__SHIFT 0x10
+#define SQ_VOP3_0__ENCODING__SHIFT 0x1a
+#define SQ_VOP3_0__VDST_MASK 0x000000FFL
+#define SQ_VOP3_0__ABS_MASK 0x00000700L
+#define SQ_VOP3_0__OP_SEL_MASK 0x00007800L
+#define SQ_VOP3_0__CLAMP_MASK 0x00008000L
+#define SQ_VOP3_0__OP_MASK 0x03FF0000L
+#define SQ_VOP3_0__ENCODING_MASK 0xFC000000L
+//SQ_VOP3_0_SDST_ENC
+#define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x0
+#define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x8
+#define SQ_VOP3_0_SDST_ENC__CLAMP__SHIFT 0xf
+#define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x10
+#define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x1a
+#define SQ_VOP3_0_SDST_ENC__VDST_MASK 0x000000FFL
+#define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x00007F00L
+#define SQ_VOP3_0_SDST_ENC__CLAMP_MASK 0x00008000L
+#define SQ_VOP3_0_SDST_ENC__OP_MASK 0x03FF0000L
+#define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xFC000000L
+//SQ_VOP3_1
+#define SQ_VOP3_1__SRC0__SHIFT 0x0
+#define SQ_VOP3_1__SRC1__SHIFT 0x9
+#define SQ_VOP3_1__SRC2__SHIFT 0x12
+#define SQ_VOP3_1__OMOD__SHIFT 0x1b
+#define SQ_VOP3_1__NEG__SHIFT 0x1d
+#define SQ_VOP3_1__SRC0_MASK 0x000001FFL
+#define SQ_VOP3_1__SRC1_MASK 0x0003FE00L
+#define SQ_VOP3_1__SRC2_MASK 0x07FC0000L
+#define SQ_VOP3_1__OMOD_MASK 0x18000000L
+#define SQ_VOP3_1__NEG_MASK 0xE0000000L
+//SQ_VOPC
+#define SQ_VOPC__SRC0__SHIFT 0x0
+#define SQ_VOPC__VSRC1__SHIFT 0x9
+#define SQ_VOPC__OP__SHIFT 0x11
+#define SQ_VOPC__ENCODING__SHIFT 0x19
+#define SQ_VOPC__SRC0_MASK 0x000001FFL
+#define SQ_VOPC__VSRC1_MASK 0x0001FE00L
+#define SQ_VOPC__OP_MASK 0x01FE0000L
+#define SQ_VOPC__ENCODING_MASK 0xFE000000L
+//SQ_VOP_DPP
+#define SQ_VOP_DPP__SRC0__SHIFT 0x0
+#define SQ_VOP_DPP__DPP_CTRL__SHIFT 0x8
+#define SQ_VOP_DPP__BOUND_CTRL__SHIFT 0x13
+#define SQ_VOP_DPP__SRC0_NEG__SHIFT 0x14
+#define SQ_VOP_DPP__SRC0_ABS__SHIFT 0x15
+#define SQ_VOP_DPP__SRC1_NEG__SHIFT 0x16
+#define SQ_VOP_DPP__SRC1_ABS__SHIFT 0x17
+#define SQ_VOP_DPP__BANK_MASK__SHIFT 0x18
+#define SQ_VOP_DPP__ROW_MASK__SHIFT 0x1c
+#define SQ_VOP_DPP__SRC0_MASK 0x000000FFL
+#define SQ_VOP_DPP__DPP_CTRL_MASK 0x0001FF00L
+#define SQ_VOP_DPP__BOUND_CTRL_MASK 0x00080000L
+#define SQ_VOP_DPP__SRC0_NEG_MASK 0x00100000L
+#define SQ_VOP_DPP__SRC0_ABS_MASK 0x00200000L
+#define SQ_VOP_DPP__SRC1_NEG_MASK 0x00400000L
+#define SQ_VOP_DPP__SRC1_ABS_MASK 0x00800000L
+#define SQ_VOP_DPP__BANK_MASK_MASK 0x0F000000L
+#define SQ_VOP_DPP__ROW_MASK_MASK 0xF0000000L
+//SQ_VOP_SDWA
+#define SQ_VOP_SDWA__SRC0__SHIFT 0x0
+#define SQ_VOP_SDWA__DST_SEL__SHIFT 0x8
+#define SQ_VOP_SDWA__DST_UNUSED__SHIFT 0xb
+#define SQ_VOP_SDWA__CLAMP__SHIFT 0xd
+#define SQ_VOP_SDWA__OMOD__SHIFT 0xe
+#define SQ_VOP_SDWA__SRC0_SEL__SHIFT 0x10
+#define SQ_VOP_SDWA__SRC0_SEXT__SHIFT 0x13
+#define SQ_VOP_SDWA__SRC0_NEG__SHIFT 0x14
+#define SQ_VOP_SDWA__SRC0_ABS__SHIFT 0x15
+#define SQ_VOP_SDWA__S0__SHIFT 0x17
+#define SQ_VOP_SDWA__SRC1_SEL__SHIFT 0x18
+#define SQ_VOP_SDWA__SRC1_SEXT__SHIFT 0x1b
+#define SQ_VOP_SDWA__SRC1_NEG__SHIFT 0x1c
+#define SQ_VOP_SDWA__SRC1_ABS__SHIFT 0x1d
+#define SQ_VOP_SDWA__S1__SHIFT 0x1f
+#define SQ_VOP_SDWA__SRC0_MASK 0x000000FFL
+#define SQ_VOP_SDWA__DST_SEL_MASK 0x00000700L
+#define SQ_VOP_SDWA__DST_UNUSED_MASK 0x00001800L
+#define SQ_VOP_SDWA__CLAMP_MASK 0x00002000L
+#define SQ_VOP_SDWA__OMOD_MASK 0x0000C000L
+#define SQ_VOP_SDWA__SRC0_SEL_MASK 0x00070000L
+#define SQ_VOP_SDWA__SRC0_SEXT_MASK 0x00080000L
+#define SQ_VOP_SDWA__SRC0_NEG_MASK 0x00100000L
+#define SQ_VOP_SDWA__SRC0_ABS_MASK 0x00200000L
+#define SQ_VOP_SDWA__S0_MASK 0x00800000L
+#define SQ_VOP_SDWA__SRC1_SEL_MASK 0x07000000L
+#define SQ_VOP_SDWA__SRC1_SEXT_MASK 0x08000000L
+#define SQ_VOP_SDWA__SRC1_NEG_MASK 0x10000000L
+#define SQ_VOP_SDWA__SRC1_ABS_MASK 0x20000000L
+#define SQ_VOP_SDWA__S1_MASK 0x80000000L
+//SQ_VOP_SDWA_SDST_ENC
+#define SQ_VOP_SDWA_SDST_ENC__SRC0__SHIFT 0x0
+#define SQ_VOP_SDWA_SDST_ENC__SDST__SHIFT 0x8
+#define SQ_VOP_SDWA_SDST_ENC__SD__SHIFT 0xf
+#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL__SHIFT 0x10
+#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT__SHIFT 0x13
+#define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG__SHIFT 0x14
+#define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS__SHIFT 0x15
+#define SQ_VOP_SDWA_SDST_ENC__S0__SHIFT 0x17
+#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL__SHIFT 0x18
+#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT__SHIFT 0x1b
+#define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG__SHIFT 0x1c
+#define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS__SHIFT 0x1d
+#define SQ_VOP_SDWA_SDST_ENC__S1__SHIFT 0x1f
+#define SQ_VOP_SDWA_SDST_ENC__SRC0_MASK 0x000000FFL
+#define SQ_VOP_SDWA_SDST_ENC__SDST_MASK 0x00007F00L
+#define SQ_VOP_SDWA_SDST_ENC__SD_MASK 0x00008000L
+#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL_MASK 0x00070000L
+#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT_MASK 0x00080000L
+#define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG_MASK 0x00100000L
+#define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS_MASK 0x00200000L
+#define SQ_VOP_SDWA_SDST_ENC__S0_MASK 0x00800000L
+#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL_MASK 0x07000000L
+#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT_MASK 0x08000000L
+#define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG_MASK 0x10000000L
+#define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS_MASK 0x20000000L
+#define SQ_VOP_SDWA_SDST_ENC__S1_MASK 0x80000000L
+//SQ_LB_CTR_CTRL
+#define SQ_LB_CTR_CTRL__START__SHIFT 0x0
+#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1
+#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2
+#define SQ_LB_CTR_CTRL__START_MASK 0x00000001L
+#define SQ_LB_CTR_CTRL__LOAD_MASK 0x00000002L
+#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x00000004L
+//SQ_LB_DATA0
+#define SQ_LB_DATA0__DATA__SHIFT 0x0
+#define SQ_LB_DATA0__DATA_MASK 0xFFFFFFFFL
+//SQ_LB_DATA1
+#define SQ_LB_DATA1__DATA__SHIFT 0x0
+#define SQ_LB_DATA1__DATA_MASK 0xFFFFFFFFL
+//SQ_LB_DATA2
+#define SQ_LB_DATA2__DATA__SHIFT 0x0
+#define SQ_LB_DATA2__DATA_MASK 0xFFFFFFFFL
+//SQ_LB_DATA3
+#define SQ_LB_DATA3__DATA__SHIFT 0x0
+#define SQ_LB_DATA3__DATA_MASK 0xFFFFFFFFL
+//SQ_LB_CTR_SEL
+#define SQ_LB_CTR_SEL__SEL0__SHIFT 0x0
+#define SQ_LB_CTR_SEL__SEL1__SHIFT 0x4
+#define SQ_LB_CTR_SEL__SEL2__SHIFT 0x8
+#define SQ_LB_CTR_SEL__SEL3__SHIFT 0xc
+#define SQ_LB_CTR_SEL__SEL0_MASK 0x0000000FL
+#define SQ_LB_CTR_SEL__SEL1_MASK 0x000000F0L
+#define SQ_LB_CTR_SEL__SEL2_MASK 0x00000F00L
+#define SQ_LB_CTR_SEL__SEL3_MASK 0x0000F000L
+//SQ_LB_CTR0_CU
+#define SQ_LB_CTR0_CU__SH0_MASK__SHIFT 0x0
+#define SQ_LB_CTR0_CU__SH1_MASK__SHIFT 0x10
+#define SQ_LB_CTR0_CU__SH0_MASK_MASK 0x0000FFFFL
+#define SQ_LB_CTR0_CU__SH1_MASK_MASK 0xFFFF0000L
+//SQ_LB_CTR1_CU
+#define SQ_LB_CTR1_CU__SH0_MASK__SHIFT 0x0
+#define SQ_LB_CTR1_CU__SH1_MASK__SHIFT 0x10
+#define SQ_LB_CTR1_CU__SH0_MASK_MASK 0x0000FFFFL
+#define SQ_LB_CTR1_CU__SH1_MASK_MASK 0xFFFF0000L
+//SQ_LB_CTR2_CU
+#define SQ_LB_CTR2_CU__SH0_MASK__SHIFT 0x0
+#define SQ_LB_CTR2_CU__SH1_MASK__SHIFT 0x10
+#define SQ_LB_CTR2_CU__SH0_MASK_MASK 0x0000FFFFL
+#define SQ_LB_CTR2_CU__SH1_MASK_MASK 0xFFFF0000L
+//SQ_LB_CTR3_CU
+#define SQ_LB_CTR3_CU__SH0_MASK__SHIFT 0x0
+#define SQ_LB_CTR3_CU__SH1_MASK__SHIFT 0x10
+#define SQ_LB_CTR3_CU__SH0_MASK_MASK 0x0000FFFFL
+#define SQ_LB_CTR3_CU__SH1_MASK_MASK 0xFFFF0000L
+//SQC_EDC_CNT
+#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x0
+#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x2
+#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x4
+#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT__SHIFT 0x6
+#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x8
+#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT__SHIFT 0xa
+#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT__SHIFT 0xc
+#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT__SHIFT 0xe
+#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x10
+#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x12
+#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x14
+#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT__SHIFT 0x16
+#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x18
+#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x1a
+#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x1c
+#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT__SHIFT 0x1e
+#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000003L
+#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT_MASK 0x0000000CL
+#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT_MASK 0x00000030L
+#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT_MASK 0x000000C0L
+#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000300L
+#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT_MASK 0x00000C00L
+#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT_MASK 0x00003000L
+#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT_MASK 0x0000C000L
+#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00030000L
+#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT_MASK 0x000C0000L
+#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT_MASK 0x00300000L
+#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT_MASK 0x00C00000L
+#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT_MASK 0x03000000L
+#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT_MASK 0x0C000000L
+#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT_MASK 0x30000000L
+#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT_MASK 0xC0000000L
+//SQ_EDC_SEC_CNT
+#define SQ_EDC_SEC_CNT__LDS_SEC__SHIFT 0x0
+#define SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT 0x8
+#define SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT 0x10
+#define SQ_EDC_SEC_CNT__LDS_SEC_MASK 0x000000FFL
+#define SQ_EDC_SEC_CNT__SGPR_SEC_MASK 0x0000FF00L
+#define SQ_EDC_SEC_CNT__VGPR_SEC_MASK 0x00FF0000L
+//SQ_EDC_DED_CNT
+#define SQ_EDC_DED_CNT__LDS_DED__SHIFT 0x0
+#define SQ_EDC_DED_CNT__SGPR_DED__SHIFT 0x8
+#define SQ_EDC_DED_CNT__VGPR_DED__SHIFT 0x10
+#define SQ_EDC_DED_CNT__LDS_DED_MASK 0x000000FFL
+#define SQ_EDC_DED_CNT__SGPR_DED_MASK 0x0000FF00L
+#define SQ_EDC_DED_CNT__VGPR_DED_MASK 0x00FF0000L
+//SQ_EDC_INFO
+#define SQ_EDC_INFO__WAVE_ID__SHIFT 0x0
+#define SQ_EDC_INFO__SIMD_ID__SHIFT 0x4
+#define SQ_EDC_INFO__SOURCE__SHIFT 0x6
+#define SQ_EDC_INFO__VM_ID__SHIFT 0x9
+#define SQ_EDC_INFO__WAVE_ID_MASK 0x0000000FL
+#define SQ_EDC_INFO__SIMD_ID_MASK 0x00000030L
+#define SQ_EDC_INFO__SOURCE_MASK 0x000001C0L
+#define SQ_EDC_INFO__VM_ID_MASK 0x00001E00L
+//SQ_EDC_CNT
+#define SQ_EDC_CNT__LDS_D_SEC_COUNT__SHIFT 0x0
+#define SQ_EDC_CNT__LDS_D_DED_COUNT__SHIFT 0x2
+#define SQ_EDC_CNT__LDS_I_SEC_COUNT__SHIFT 0x4
+#define SQ_EDC_CNT__LDS_I_DED_COUNT__SHIFT 0x6
+#define SQ_EDC_CNT__SGPR_SEC_COUNT__SHIFT 0x8
+#define SQ_EDC_CNT__SGPR_DED_COUNT__SHIFT 0xa
+#define SQ_EDC_CNT__VGPR0_SEC_COUNT__SHIFT 0xc
+#define SQ_EDC_CNT__VGPR0_DED_COUNT__SHIFT 0xe
+#define SQ_EDC_CNT__VGPR1_SEC_COUNT__SHIFT 0x10
+#define SQ_EDC_CNT__VGPR1_DED_COUNT__SHIFT 0x12
+#define SQ_EDC_CNT__VGPR2_SEC_COUNT__SHIFT 0x14
+#define SQ_EDC_CNT__VGPR2_DED_COUNT__SHIFT 0x16
+#define SQ_EDC_CNT__VGPR3_SEC_COUNT__SHIFT 0x18
+#define SQ_EDC_CNT__VGPR3_DED_COUNT__SHIFT 0x1a
+#define SQ_EDC_CNT__LDS_D_SEC_COUNT_MASK 0x00000003L
+#define SQ_EDC_CNT__LDS_D_DED_COUNT_MASK 0x0000000CL
+#define SQ_EDC_CNT__LDS_I_SEC_COUNT_MASK 0x00000030L
+#define SQ_EDC_CNT__LDS_I_DED_COUNT_MASK 0x000000C0L
+#define SQ_EDC_CNT__SGPR_SEC_COUNT_MASK 0x00000300L
+#define SQ_EDC_CNT__SGPR_DED_COUNT_MASK 0x00000C00L
+#define SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK 0x00003000L
+#define SQ_EDC_CNT__VGPR0_DED_COUNT_MASK 0x0000C000L
+#define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK 0x00030000L
+#define SQ_EDC_CNT__VGPR1_DED_COUNT_MASK 0x000C0000L
+#define SQ_EDC_CNT__VGPR2_SEC_COUNT_MASK 0x00300000L
+#define SQ_EDC_CNT__VGPR2_DED_COUNT_MASK 0x00C00000L
+#define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK 0x03000000L
+#define SQ_EDC_CNT__VGPR3_DED_COUNT_MASK 0x0C000000L
+//SQ_EDC_FUE_CNTL
+#define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0
+#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10
+#define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL
+#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L
+//SQ_THREAD_TRACE_WORD_CMN
+#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0x000FL
+#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x0010L
+//SQ_THREAD_TRACE_WORD_EVENT
+#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x6
+#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0xa
+#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0x000FL
+#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x0010L
+#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x0020L
+#define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x01C0L
+#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0xFC00L
+//SQ_THREAD_TRACE_WORD_INST
+#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x9
+#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0xb
+#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0x000FL
+#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x0010L
+#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x01E0L
+#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x0600L
+#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0xF800L
+//SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x9
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR__SHIFT 0xf
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x10
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x00000010L
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x000001E0L
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x00000600L
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR_MASK 0x00008000L
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xFFFF0000L
+//SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x6
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0xa
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0xe
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x10
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x00000010L
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x00000020L
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x000003C0L
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x00003C00L
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0x0000C000L
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xFFFF0000L
+//SQ_THREAD_TRACE_WORD_ISSUE
+#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x8
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0xa
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0xc
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0xe
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x10
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x12
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x14
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x16
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x18
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x1a
+#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0x0000000FL
+#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x00000010L
+#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x00000060L
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x00000300L
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0x00000C00L
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x00003000L
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0x0000C000L
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x00030000L
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0x000C0000L
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x00300000L
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0x00C00000L
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x03000000L
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0x0C000000L
+//SQ_THREAD_TRACE_WORD_MISC
+#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0xc
+#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0xd
+#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0x000FL
+#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0x0FF0L
+#define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x1000L
+#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0xE000L
+//SQ_THREAD_TRACE_WORD_PERF_1_OF_2
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x6
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0xa
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0xc
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x19
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x00000010L
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x00000020L
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x000003C0L
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0x00000C00L
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x01FFF000L
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xFE000000L
+//SQ_THREAD_TRACE_WORD_REG_1_OF_2
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x7
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x9
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0xa
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0xe
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0xf
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x10
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x00000010L
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x00000060L
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x00000180L
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x00000200L
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x00001C00L
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x00004000L
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x00008000L
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xFFFF0000L
+//SQ_THREAD_TRACE_WORD_REG_2_OF_2
+#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xFFFFFFFFL
+//SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT 0x7
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT 0x9
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT 0x10
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK 0x00000010L
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK 0x00000060L
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK 0x00000180L
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK 0x0000FE00L
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK 0xFFFF0000L
+//SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2
+#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK 0x0000FFFFL
+//SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2
+#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x10
+#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
+#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xFFFF0000L
+//SQ_THREAD_TRACE_WORD_WAVE
+#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x6
+#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0xa
+#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0xe
+#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0x000FL
+#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x0010L
+#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x0020L
+#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x03C0L
+#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x3C00L
+#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0xC000L
+//SQ_THREAD_TRACE_WORD_WAVE_START
+#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x6
+#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0xa
+#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0xe
+#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x10
+#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x15
+#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x16
+#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d
+#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0x0000000FL
+#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x00000010L
+#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x00000020L
+#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x000003C0L
+#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x00003C00L
+#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0x0000C000L
+#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x001F0000L
+#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x00200000L
+#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1FC00000L
+#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xE0000000L
+//SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2
+#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0x00FFFFFFL
+//SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0xFFFFL
+//SQ_THREAD_TRACE_WORD_PERF_2_OF_2
+#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x6
+#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x13
+#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x0000003FL
+#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x0007FFC0L
+#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xFFF80000L
+//SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2
+#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xFFFFFFFFL
+//SQ_WREXEC_EXEC_HI
+#define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT 0x0
+#define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT 0x1a
+#define SQ_WREXEC_EXEC_HI__ATC__SHIFT 0x1b
+#define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT 0x1c
+#define SQ_WREXEC_EXEC_HI__MSB__SHIFT 0x1f
+#define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK 0x0000FFFFL
+#define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK 0x04000000L
+#define SQ_WREXEC_EXEC_HI__ATC_MASK 0x08000000L
+#define SQ_WREXEC_EXEC_HI__MTYPE_MASK 0x70000000L
+#define SQ_WREXEC_EXEC_HI__MSB_MASK 0x80000000L
+//SQ_WREXEC_EXEC_LO
+#define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT 0x0
+#define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK 0xFFFFFFFFL
+//SQ_BUF_RSRC_WORD0
+#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0
+#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL
+//SQ_BUF_RSRC_WORD1
+#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0
+#define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x10
+#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x1e
+#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x1f
+#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x0000FFFFL
+#define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3FFF0000L
+#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000L
+#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000L
+//SQ_BUF_RSRC_WORD2
+#define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x0
+#define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xFFFFFFFFL
+//SQ_BUF_RSRC_WORD3
+#define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x0
+#define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3
+#define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6
+#define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x9
+#define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0xc
+#define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0xf
+#define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE__SHIFT 0x13
+#define SQ_BUF_RSRC_WORD3__USER_VM_MODE__SHIFT 0x14
+#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x15
+#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x17
+#define SQ_BUF_RSRC_WORD3__NV__SHIFT 0x1b
+#define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x1e
+#define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L
+#define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L
+#define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L
+#define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L
+#define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x00007000L
+#define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x00078000L
+#define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE_MASK 0x00080000L
+#define SQ_BUF_RSRC_WORD3__USER_VM_MODE_MASK 0x00100000L
+#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x00600000L
+#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x00800000L
+#define SQ_BUF_RSRC_WORD3__NV_MASK 0x08000000L
+#define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xC0000000L
+//SQ_IMG_RSRC_WORD0
+#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL
+//SQ_IMG_RSRC_WORD1
+#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x8
+#define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x14
+#define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x1a
+#define SQ_IMG_RSRC_WORD1__NV__SHIFT 0x1e
+#define SQ_IMG_RSRC_WORD1__META_DIRECT__SHIFT 0x1f
+#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x000000FFL
+#define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0x000FFF00L
+#define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x03F00000L
+#define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3C000000L
+#define SQ_IMG_RSRC_WORD1__NV_MASK 0x40000000L
+#define SQ_IMG_RSRC_WORD1__META_DIRECT_MASK 0x80000000L
+//SQ_IMG_RSRC_WORD2
+#define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0xe
+#define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x1c
+#define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x00003FFFL
+#define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0x0FFFC000L
+#define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000L
+//SQ_IMG_RSRC_WORD3
+#define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3
+#define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6
+#define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x9
+#define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0xc
+#define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x10
+#define SQ_IMG_RSRC_WORD3__SW_MODE__SHIFT 0x14
+#define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x1c
+#define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L
+#define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L
+#define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L
+#define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L
+#define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0x0000F000L
+#define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0x000F0000L
+#define SQ_IMG_RSRC_WORD3__SW_MODE_MASK 0x01F00000L
+#define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xF0000000L
+//SQ_IMG_RSRC_WORD4
+#define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0xd
+#define SQ_IMG_RSRC_WORD4__BC_SWIZZLE__SHIFT 0x1d
+#define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x00001FFFL
+#define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x1FFFE000L
+#define SQ_IMG_RSRC_WORD4__BC_SWIZZLE_MASK 0xE0000000L
+//SQ_IMG_RSRC_WORD5
+#define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD5__ARRAY_PITCH__SHIFT 0xd
+#define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS__SHIFT 0x11
+#define SQ_IMG_RSRC_WORD5__META_LINEAR__SHIFT 0x19
+#define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED__SHIFT 0x1a
+#define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED__SHIFT 0x1b
+#define SQ_IMG_RSRC_WORD5__MAX_MIP__SHIFT 0x1c
+#define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x00001FFFL
+#define SQ_IMG_RSRC_WORD5__ARRAY_PITCH_MASK 0x0001E000L
+#define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS_MASK 0x01FE0000L
+#define SQ_IMG_RSRC_WORD5__META_LINEAR_MASK 0x02000000L
+#define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED_MASK 0x04000000L
+#define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED_MASK 0x08000000L
+#define SQ_IMG_RSRC_WORD5__MAX_MIP_MASK 0xF0000000L
+//SQ_IMG_RSRC_WORD6
+#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0xc
+#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x14
+#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN__SHIFT 0x15
+#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB__SHIFT 0x16
+#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM__SHIFT 0x17
+#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS__SHIFT 0x18
+#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS__SHIFT 0x1c
+#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0x00000FFFL
+#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0x000FF000L
+#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x00100000L
+#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN_MASK 0x00200000L
+#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB_MASK 0x00400000L
+#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM_MASK 0x00800000L
+#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS_MASK 0x0F000000L
+#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS_MASK 0xF0000000L
+//SQ_IMG_RSRC_WORD7
+#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS_MASK 0xFFFFFFFFL
+//SQ_IMG_SAMP_WORD0
+#define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x0
+#define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x3
+#define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x6
+#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x9
+#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0xc
+#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0xf
+#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x10
+#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x13
+#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x14
+#define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x15
+#define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x1b
+#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x1c
+#define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d
+#define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x00000007L
+#define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x00000038L
+#define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x000001C0L
+#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0x00000E00L
+#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x00007000L
+#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x00008000L
+#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x00070000L
+#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x00080000L
+#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x00100000L
+#define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x07E00000L
+#define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x08000000L
+#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000L
+#define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000L
+//SQ_IMG_SAMP_WORD1
+#define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x0
+#define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0xc
+#define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x18
+#define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x1c
+#define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0x00000FFFL
+#define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0x00FFF000L
+#define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0x0F000000L
+#define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xF0000000L
+//SQ_IMG_SAMP_WORD2
+#define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x0
+#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0xe
+#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x14
+#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x16
+#define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x18
+#define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x1a
+#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x1c
+#define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT__SHIFT 0x1d
+#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x1e
+#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE__SHIFT 0x1f
+#define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x00003FFFL
+#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0x000FC000L
+#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x00300000L
+#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0x00C00000L
+#define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x03000000L
+#define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0x0C000000L
+#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000L
+#define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT_MASK 0x20000000L
+#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000L
+#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE_MASK 0x80000000L
+//SQ_IMG_SAMP_WORD3
+#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x0
+#define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA__SHIFT 0xc
+#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x1e
+#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0x00000FFFL
+#define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA_MASK 0x00001000L
+#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xC0000000L
+//SQ_FLAT_SCRATCH_WORD0
+#define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT 0x0
+#define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK 0x0007FFFFL
+//SQ_FLAT_SCRATCH_WORD1
+#define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT 0x0
+#define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK 0x00FFFFFFL
+//SQ_M0_GPR_IDX_WORD
+#define SQ_M0_GPR_IDX_WORD__INDEX__SHIFT 0x0
+#define SQ_M0_GPR_IDX_WORD__VSRC0_REL__SHIFT 0xc
+#define SQ_M0_GPR_IDX_WORD__VSRC1_REL__SHIFT 0xd
+#define SQ_M0_GPR_IDX_WORD__VSRC2_REL__SHIFT 0xe
+#define SQ_M0_GPR_IDX_WORD__VDST_REL__SHIFT 0xf
+#define SQ_M0_GPR_IDX_WORD__INDEX_MASK 0x000000FFL
+#define SQ_M0_GPR_IDX_WORD__VSRC0_REL_MASK 0x00001000L
+#define SQ_M0_GPR_IDX_WORD__VSRC1_REL_MASK 0x00002000L
+#define SQ_M0_GPR_IDX_WORD__VSRC2_REL_MASK 0x00004000L
+#define SQ_M0_GPR_IDX_WORD__VDST_REL_MASK 0x00008000L
+//SQC_ICACHE_UTCL1_CNTL1
+#define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
+#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
+#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
+#define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
+#define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
+#define SQC_ICACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
+#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
+#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
+#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13
+#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17
+#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18
+#define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
+#define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
+#define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
+#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
+#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
+#define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
+#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
+#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
+#define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
+#define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
+#define SQC_ICACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
+#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
+#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
+#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L
+#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L
+#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L
+#define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
+#define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
+#define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
+#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
+#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
+//SQC_ICACHE_UTCL1_CNTL2
+#define SQC_ICACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0
+#define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8
+#define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
+#define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
+#define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb
+#define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
+#define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
+#define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
+#define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
+#define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10
+#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
+#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13
+#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14
+#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15
+#define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
+#define SQC_ICACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL
+#define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L
+#define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
+#define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
+#define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L
+#define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
+#define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
+#define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
+#define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
+#define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L
+#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
+#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L
+#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
+#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L
+#define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
+//SQC_DCACHE_UTCL1_CNTL1
+#define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
+#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
+#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
+#define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
+#define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
+#define SQC_DCACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
+#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
+#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
+#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13
+#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17
+#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18
+#define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
+#define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
+#define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
+#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
+#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
+#define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
+#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
+#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
+#define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
+#define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
+#define SQC_DCACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
+#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
+#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
+#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L
+#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L
+#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L
+#define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
+#define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
+#define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
+#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
+#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
+//SQC_DCACHE_UTCL1_CNTL2
+#define SQC_DCACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0
+#define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8
+#define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
+#define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
+#define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb
+#define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
+#define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
+#define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
+#define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
+#define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10
+#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
+#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13
+#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14
+#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15
+#define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
+#define SQC_DCACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL
+#define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L
+#define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
+#define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
+#define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L
+#define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
+#define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
+#define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
+#define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
+#define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L
+#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
+#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L
+#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
+#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L
+#define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
+//SQC_ICACHE_UTCL1_STATUS
+#define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
+#define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
+#define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
+#define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
+#define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
+#define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
+//SQC_DCACHE_UTCL1_STATUS
+#define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
+#define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
+#define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
+#define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
+#define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
+#define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
+
+
+// addressBlock: gc_tcdec
+//TCP_INVALIDATE
+#define TCP_INVALIDATE__START__SHIFT 0x0
+#define TCP_INVALIDATE__START_MASK 0x00000001L
+//TCP_STATUS
+#define TCP_STATUS__TCP_BUSY__SHIFT 0x0
+#define TCP_STATUS__INPUT_BUSY__SHIFT 0x1
+#define TCP_STATUS__ADRS_BUSY__SHIFT 0x2
+#define TCP_STATUS__TAGRAMS_BUSY__SHIFT 0x3
+#define TCP_STATUS__CNTRL_BUSY__SHIFT 0x4
+#define TCP_STATUS__LFIFO_BUSY__SHIFT 0x5
+#define TCP_STATUS__READ_BUSY__SHIFT 0x6
+#define TCP_STATUS__FORMAT_BUSY__SHIFT 0x7
+#define TCP_STATUS__VM_BUSY__SHIFT 0x8
+#define TCP_STATUS__TCP_BUSY_MASK 0x00000001L
+#define TCP_STATUS__INPUT_BUSY_MASK 0x00000002L
+#define TCP_STATUS__ADRS_BUSY_MASK 0x00000004L
+#define TCP_STATUS__TAGRAMS_BUSY_MASK 0x00000008L
+#define TCP_STATUS__CNTRL_BUSY_MASK 0x00000010L
+#define TCP_STATUS__LFIFO_BUSY_MASK 0x00000020L
+#define TCP_STATUS__READ_BUSY_MASK 0x00000040L
+#define TCP_STATUS__FORMAT_BUSY_MASK 0x00000080L
+#define TCP_STATUS__VM_BUSY_MASK 0x00000100L
+//TCP_CHAN_STEER_0
+#define TCP_CHAN_STEER_0__CHAN0__SHIFT 0x0
+#define TCP_CHAN_STEER_0__CHAN1__SHIFT 0x5
+#define TCP_CHAN_STEER_0__CHAN2__SHIFT 0xa
+#define TCP_CHAN_STEER_0__CHAN3__SHIFT 0xf
+#define TCP_CHAN_STEER_0__CHAN4__SHIFT 0x14
+#define TCP_CHAN_STEER_0__CHAN5__SHIFT 0x19
+#define TCP_CHAN_STEER_0__CHAN0_MASK 0x0000001FL
+#define TCP_CHAN_STEER_0__CHAN1_MASK 0x000003E0L
+#define TCP_CHAN_STEER_0__CHAN2_MASK 0x00007C00L
+#define TCP_CHAN_STEER_0__CHAN3_MASK 0x000F8000L
+#define TCP_CHAN_STEER_0__CHAN4_MASK 0x01F00000L
+#define TCP_CHAN_STEER_0__CHAN5_MASK 0x3E000000L
+//TCP_CHAN_STEER_1
+#define TCP_CHAN_STEER_1__CHAN6__SHIFT 0x0
+#define TCP_CHAN_STEER_1__CHAN7__SHIFT 0x5
+#define TCP_CHAN_STEER_1__CHAN8__SHIFT 0xa
+#define TCP_CHAN_STEER_1__CHAN9__SHIFT 0xf
+#define TCP_CHAN_STEER_1__CHANA__SHIFT 0x14
+#define TCP_CHAN_STEER_1__CHAN6_MASK 0x0000001FL
+#define TCP_CHAN_STEER_1__CHAN7_MASK 0x000003E0L
+#define TCP_CHAN_STEER_1__CHAN8_MASK 0x00007C00L
+#define TCP_CHAN_STEER_1__CHAN9_MASK 0x000F8000L
+#define TCP_CHAN_STEER_1__CHANA_MASK 0x01F00000L
+//TCP_ADDR_CONFIG
+#define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT 0x0
+#define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x5
+#define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x7
+#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0xa
+#define TCP_ADDR_CONFIG__ENABLE64KHASH__SHIFT 0xb
+#define TCP_ADDR_CONFIG__ENABLE2MHASH__SHIFT 0xc
+#define TCP_ADDR_CONFIG__ENABLE1GHASH__SHIFT 0xd
+#define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0x0000001FL
+#define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x00000060L
+#define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x00000380L
+#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x00000400L
+#define TCP_ADDR_CONFIG__ENABLE64KHASH_MASK 0x00000800L
+#define TCP_ADDR_CONFIG__ENABLE2MHASH_MASK 0x00001000L
+#define TCP_ADDR_CONFIG__ENABLE1GHASH_MASK 0x00002000L
+//TCP_CHAN_STEER_2
+#define TCP_CHAN_STEER_2__CHANC__SHIFT 0x0
+#define TCP_CHAN_STEER_2__CHAND__SHIFT 0x5
+#define TCP_CHAN_STEER_2__CHANE__SHIFT 0xa
+#define TCP_CHAN_STEER_2__CHANF__SHIFT 0xf
+#define TCP_CHAN_STEER_2__CHAN10__SHIFT 0x14
+#define TCP_CHAN_STEER_2__CHAN11__SHIFT 0x19
+#define TCP_CHAN_STEER_2__CHANC_MASK 0x0000001FL
+#define TCP_CHAN_STEER_2__CHAND_MASK 0x000003E0L
+#define TCP_CHAN_STEER_2__CHANE_MASK 0x00007C00L
+#define TCP_CHAN_STEER_2__CHANF_MASK 0x000F8000L
+#define TCP_CHAN_STEER_2__CHAN10_MASK 0x01F00000L
+#define TCP_CHAN_STEER_2__CHAN11_MASK 0x3E000000L
+//TCP_CHAN_STEER_3
+#define TCP_CHAN_STEER_3__CHAN12__SHIFT 0x0
+#define TCP_CHAN_STEER_3__CHAN13__SHIFT 0x5
+#define TCP_CHAN_STEER_3__CHAN14__SHIFT 0xa
+#define TCP_CHAN_STEER_3__CHAN15__SHIFT 0xf
+#define TCP_CHAN_STEER_3__CHAN16__SHIFT 0x14
+#define TCP_CHAN_STEER_3__CHAN17__SHIFT 0x19
+#define TCP_CHAN_STEER_3__CHAN12_MASK 0x0000001FL
+#define TCP_CHAN_STEER_3__CHAN13_MASK 0x000003E0L
+#define TCP_CHAN_STEER_3__CHAN14_MASK 0x00007C00L
+#define TCP_CHAN_STEER_3__CHAN15_MASK 0x000F8000L
+#define TCP_CHAN_STEER_3__CHAN16_MASK 0x01F00000L
+#define TCP_CHAN_STEER_3__CHAN17_MASK 0x3E000000L
+//TCP_CHAN_STEER_4
+#define TCP_CHAN_STEER_4__CHAN18__SHIFT 0x0
+#define TCP_CHAN_STEER_4__CHAN19__SHIFT 0x5
+#define TCP_CHAN_STEER_4__CHAN1A__SHIFT 0xa
+#define TCP_CHAN_STEER_4__CHAN1B__SHIFT 0xf
+#define TCP_CHAN_STEER_4__CHAN1C__SHIFT 0x14
+#define TCP_CHAN_STEER_4__CHAN1D__SHIFT 0x19
+#define TCP_CHAN_STEER_4__CHAN18_MASK 0x0000001FL
+#define TCP_CHAN_STEER_4__CHAN19_MASK 0x000003E0L
+#define TCP_CHAN_STEER_4__CHAN1A_MASK 0x00007C00L
+#define TCP_CHAN_STEER_4__CHAN1B_MASK 0x000F8000L
+#define TCP_CHAN_STEER_4__CHAN1C_MASK 0x01F00000L
+#define TCP_CHAN_STEER_4__CHAN1D_MASK 0x3E000000L
+//TCP_CHAN_STEER_5
+#define TCP_CHAN_STEER_5__CHAN1E__SHIFT 0x0
+#define TCP_CHAN_STEER_5__CHAN1F__SHIFT 0x5
+#define TCP_CHAN_STEER_5__CHAN1E_MASK 0x0000001FL
+#define TCP_CHAN_STEER_5__CHAN1F_MASK 0x000003E0L
+//TCP_EDC_CNT
+#define TCP_EDC_CNT__SEC_COUNT__SHIFT 0x0
+#define TCP_EDC_CNT__LFIFO_SED_COUNT__SHIFT 0x8
+#define TCP_EDC_CNT__DED_COUNT__SHIFT 0x10
+#define TCP_EDC_CNT__SEC_COUNT_MASK 0x000000FFL
+#define TCP_EDC_CNT__LFIFO_SED_COUNT_MASK 0x0000FF00L
+#define TCP_EDC_CNT__DED_COUNT_MASK 0x00FF0000L
+//TCP_EDC_CNT_NEW
+#define TCP_EDC_CNT_NEW__CACHE_RAM_SEC_COUNT__SHIFT 0x0
+#define TCP_EDC_CNT_NEW__CACHE_RAM_DED_COUNT__SHIFT 0x2
+#define TCP_EDC_CNT_NEW__LFIFO_RAM_SEC_COUNT__SHIFT 0x4
+#define TCP_EDC_CNT_NEW__LFIFO_RAM_DED_COUNT__SHIFT 0x6
+#define TCP_EDC_CNT_NEW__CMD_FIFO_SEC_COUNT__SHIFT 0x8
+#define TCP_EDC_CNT_NEW__CMD_FIFO_DED_COUNT__SHIFT 0xa
+#define TCP_EDC_CNT_NEW__VM_FIFO_SEC_COUNT__SHIFT 0xc
+#define TCP_EDC_CNT_NEW__VM_FIFO_DED_COUNT__SHIFT 0xe
+#define TCP_EDC_CNT_NEW__DB_RAM_SEC_COUNT__SHIFT 0x10
+#define TCP_EDC_CNT_NEW__DB_RAM_DED_COUNT__SHIFT 0x12
+#define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_SEC_COUNT__SHIFT 0x14
+#define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_DED_COUNT__SHIFT 0x16
+#define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_SEC_COUNT__SHIFT 0x18
+#define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_DED_COUNT__SHIFT 0x1a
+#define TCP_EDC_CNT_NEW__CACHE_RAM_SEC_COUNT_MASK 0x00000003L
+#define TCP_EDC_CNT_NEW__CACHE_RAM_DED_COUNT_MASK 0x0000000CL
+#define TCP_EDC_CNT_NEW__LFIFO_RAM_SEC_COUNT_MASK 0x00000030L
+#define TCP_EDC_CNT_NEW__LFIFO_RAM_DED_COUNT_MASK 0x000000C0L
+#define TCP_EDC_CNT_NEW__CMD_FIFO_SEC_COUNT_MASK 0x00000300L
+#define TCP_EDC_CNT_NEW__CMD_FIFO_DED_COUNT_MASK 0x00000C00L
+#define TCP_EDC_CNT_NEW__VM_FIFO_SEC_COUNT_MASK 0x00003000L
+#define TCP_EDC_CNT_NEW__VM_FIFO_DED_COUNT_MASK 0x0000C000L
+#define TCP_EDC_CNT_NEW__DB_RAM_SEC_COUNT_MASK 0x00030000L
+#define TCP_EDC_CNT_NEW__DB_RAM_DED_COUNT_MASK 0x000C0000L
+#define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_SEC_COUNT_MASK 0x00300000L
+#define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_DED_COUNT_MASK 0x00C00000L
+#define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_SEC_COUNT_MASK 0x03000000L
+#define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_DED_COUNT_MASK 0x0C000000L
+//TC_CFG_L1_LOAD_POLICY0
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT 0x0
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT 0x2
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT 0x4
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT 0x6
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT 0x8
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT 0xa
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT 0xc
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT 0xe
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT 0x10
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT 0x12
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT 0x14
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT 0x16
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT 0x18
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT 0x1a
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT 0x1c
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT 0x1e
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK 0x00000003L
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK 0x0000000CL
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK 0x00000030L
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK 0x000000C0L
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK 0x00000300L
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK 0x00000C00L
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK 0x00003000L
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK 0x0000C000L
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK 0x00030000L
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK 0x000C0000L
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK 0x00300000L
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK 0x00C00000L
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK 0x03000000L
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK 0x0C000000L
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK 0x30000000L
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK 0xC0000000L
+//TC_CFG_L1_LOAD_POLICY1
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT 0x0
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT 0x2
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT 0x4
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT 0x6
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT 0x8
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT 0xa
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT 0xc
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT 0xe
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT 0x10
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT 0x12
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT 0x14
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT 0x16
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT 0x18
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT 0x1a
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT 0x1c
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT 0x1e
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK 0x00000003L
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK 0x0000000CL
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK 0x00000030L
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK 0x000000C0L
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK 0x00000300L
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK 0x00000C00L
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK 0x00003000L
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK 0x0000C000L
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK 0x00030000L
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK 0x000C0000L
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK 0x00300000L
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK 0x00C00000L
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK 0x03000000L
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK 0x0C000000L
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK 0x30000000L
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK 0xC0000000L
+//TC_CFG_L1_STORE_POLICY
+#define TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT 0x0
+#define TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT 0x1
+#define TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT 0x2
+#define TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT 0x3
+#define TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT 0x4
+#define TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT 0x5
+#define TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT 0x6
+#define TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT 0x7
+#define TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT 0x8
+#define TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT 0x9
+#define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT 0xa
+#define TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT 0xb
+#define TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT 0xc
+#define TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT 0xd
+#define TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT 0xe
+#define TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT 0xf
+#define TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT 0x10
+#define TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT 0x11
+#define TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT 0x12
+#define TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT 0x13
+#define TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT 0x14
+#define TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT 0x15
+#define TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT 0x16
+#define TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT 0x17
+#define TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT 0x18
+#define TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT 0x19
+#define TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT 0x1a
+#define TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT 0x1b
+#define TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT 0x1c
+#define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT 0x1d
+#define TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT 0x1e
+#define TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT 0x1f
+#define TC_CFG_L1_STORE_POLICY__POLICY_0_MASK 0x00000001L
+#define TC_CFG_L1_STORE_POLICY__POLICY_1_MASK 0x00000002L
+#define TC_CFG_L1_STORE_POLICY__POLICY_2_MASK 0x00000004L
+#define TC_CFG_L1_STORE_POLICY__POLICY_3_MASK 0x00000008L
+#define TC_CFG_L1_STORE_POLICY__POLICY_4_MASK 0x00000010L
+#define TC_CFG_L1_STORE_POLICY__POLICY_5_MASK 0x00000020L
+#define TC_CFG_L1_STORE_POLICY__POLICY_6_MASK 0x00000040L
+#define TC_CFG_L1_STORE_POLICY__POLICY_7_MASK 0x00000080L
+#define TC_CFG_L1_STORE_POLICY__POLICY_8_MASK 0x00000100L
+#define TC_CFG_L1_STORE_POLICY__POLICY_9_MASK 0x00000200L
+#define TC_CFG_L1_STORE_POLICY__POLICY_10_MASK 0x00000400L
+#define TC_CFG_L1_STORE_POLICY__POLICY_11_MASK 0x00000800L
+#define TC_CFG_L1_STORE_POLICY__POLICY_12_MASK 0x00001000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_13_MASK 0x00002000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_14_MASK 0x00004000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_15_MASK 0x00008000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_16_MASK 0x00010000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_17_MASK 0x00020000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_18_MASK 0x00040000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_19_MASK 0x00080000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_20_MASK 0x00100000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_21_MASK 0x00200000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_22_MASK 0x00400000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_23_MASK 0x00800000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_24_MASK 0x01000000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_25_MASK 0x02000000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_26_MASK 0x04000000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_27_MASK 0x08000000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_28_MASK 0x10000000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_29_MASK 0x20000000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_30_MASK 0x40000000L
+#define TC_CFG_L1_STORE_POLICY__POLICY_31_MASK 0x80000000L
+//TC_CFG_L2_LOAD_POLICY0
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT 0x0
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT 0x2
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT 0x4
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT 0x6
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT 0x8
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT 0xa
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT 0xc
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT 0xe
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT 0x10
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT 0x12
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT 0x14
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT 0x16
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT 0x18
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT 0x1a
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT 0x1c
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT 0x1e
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK 0x00000003L
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK 0x0000000CL
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK 0x00000030L
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK 0x000000C0L
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK 0x00000300L
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK 0x00000C00L
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK 0x00003000L
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK 0x0000C000L
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK 0x00030000L
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK 0x000C0000L
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK 0x00300000L
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK 0x00C00000L
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK 0x03000000L
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK 0x0C000000L
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK 0x30000000L
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK 0xC0000000L
+//TC_CFG_L2_LOAD_POLICY1
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT 0x0
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT 0x2
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT 0x4
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT 0x6
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT 0x8
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT 0xa
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT 0xc
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT 0xe
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT 0x10
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT 0x12
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT 0x14
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT 0x16
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT 0x18
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT 0x1a
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT 0x1c
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT 0x1e
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK 0x00000003L
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK 0x0000000CL
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK 0x00000030L
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK 0x000000C0L
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK 0x00000300L
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK 0x00000C00L
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK 0x00003000L
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK 0x0000C000L
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK 0x00030000L
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK 0x000C0000L
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK 0x00300000L
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK 0x00C00000L
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK 0x03000000L
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK 0x0C000000L
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK 0x30000000L
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK 0xC0000000L
+//TC_CFG_L2_STORE_POLICY0
+#define TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT 0x0
+#define TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT 0x2
+#define TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT 0x4
+#define TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT 0x6
+#define TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT 0x8
+#define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT 0xa
+#define TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT 0xc
+#define TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT 0xe
+#define TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT 0x10
+#define TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT 0x12
+#define TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT 0x14
+#define TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT 0x16
+#define TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT 0x18
+#define TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT 0x1a
+#define TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT 0x1c
+#define TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT 0x1e
+#define TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK 0x00000003L
+#define TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK 0x0000000CL
+#define TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK 0x00000030L
+#define TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK 0x000000C0L
+#define TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK 0x00000300L
+#define TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK 0x00000C00L
+#define TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK 0x00003000L
+#define TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK 0x0000C000L
+#define TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK 0x00030000L
+#define TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK 0x000C0000L
+#define TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK 0x00300000L
+#define TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK 0x00C00000L
+#define TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK 0x03000000L
+#define TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK 0x0C000000L
+#define TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK 0x30000000L
+#define TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK 0xC0000000L
+//TC_CFG_L2_STORE_POLICY1
+#define TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT 0x0
+#define TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT 0x2
+#define TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT 0x4
+#define TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT 0x6
+#define TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT 0x8
+#define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT 0xa
+#define TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT 0xc
+#define TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT 0xe
+#define TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT 0x10
+#define TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT 0x12
+#define TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT 0x14
+#define TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT 0x16
+#define TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT 0x18
+#define TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT 0x1a
+#define TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT 0x1c
+#define TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT 0x1e
+#define TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK 0x00000003L
+#define TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK 0x0000000CL
+#define TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK 0x00000030L
+#define TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK 0x000000C0L
+#define TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK 0x00000300L
+#define TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK 0x00000C00L
+#define TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK 0x00003000L
+#define TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK 0x0000C000L
+#define TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK 0x00030000L
+#define TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK 0x000C0000L
+#define TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK 0x00300000L
+#define TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK 0x00C00000L
+#define TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK 0x03000000L
+#define TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK 0x0C000000L
+#define TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK 0x30000000L
+#define TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK 0xC0000000L
+//TC_CFG_L2_ATOMIC_POLICY
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT 0x0
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT 0x2
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT 0x4
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT 0x6
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT 0x8
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT 0xa
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT 0xc
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT 0xe
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT 0x10
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT 0x12
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT 0x14
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT 0x16
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT 0x18
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT 0x1a
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT 0x1c
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT 0x1e
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK 0x00000003L
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK 0x0000000CL
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK 0x00000030L
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK 0x000000C0L
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK 0x00000300L
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK 0x00000C00L
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK 0x00003000L
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK 0x0000C000L
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK 0x00030000L
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK 0x000C0000L
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK 0x00300000L
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK 0x00C00000L
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK 0x03000000L
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK 0x0C000000L
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK 0x30000000L
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK 0xC0000000L
+//TC_CFG_L1_VOLATILE
+#define TC_CFG_L1_VOLATILE__VOL__SHIFT 0x0
+#define TC_CFG_L1_VOLATILE__VOL_MASK 0x0000000FL
+//TC_CFG_L2_VOLATILE
+#define TC_CFG_L2_VOLATILE__VOL__SHIFT 0x0
+#define TC_CFG_L2_VOLATILE__VOL_MASK 0x0000000FL
+//TCI_MISC
+#define TCI_MISC__FGCG_REPEATER_DISABLE__SHIFT 0x0
+#define TCI_MISC__LEGACY_MGCG_DISABLE__SHIFT 0x1
+#define TCI_MISC__FGCG_REPEATER_DISABLE_MASK 0x00000001L
+#define TCI_MISC__LEGACY_MGCG_DISABLE_MASK 0x00000002L
+//TCI_CNTL_3
+#define TCI_CNTL_3__DISABLE_DOUBLING_L2_BANDWIDTH__SHIFT 0x0
+#define TCI_CNTL_3__COMBINING_DELAY_WINDOW__SHIFT 0x2
+#define TCI_CNTL_3__CHICKEN_BIT_TCR_MGCG__SHIFT 0x4
+#define TCI_CNTL_3__TCR_FGCG_REPEATER_DISABLE__SHIFT 0x7
+#define TCI_CNTL_3__DISABLE_DOUBLING_L2_BANDWIDTH_MASK 0x00000003L
+#define TCI_CNTL_3__COMBINING_DELAY_WINDOW_MASK 0x0000000CL
+#define TCI_CNTL_3__CHICKEN_BIT_TCR_MGCG_MASK 0x00000070L
+#define TCI_CNTL_3__TCR_FGCG_REPEATER_DISABLE_MASK 0x00000080L
+//TCI_DSM_CNTL
+#define TCI_DSM_CNTL__WRITE_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0
+#define TCI_DSM_CNTL__WRITE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
+#define TCI_DSM_CNTL__WRITE_RAM_IRRITATOR_DATA_SEL_MASK 0x00000003L
+#define TCI_DSM_CNTL__WRITE_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L
+//TCI_DSM_CNTL2
+#define TCI_DSM_CNTL2__WRITE_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define TCI_DSM_CNTL2__WRITE_RAM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define TCI_DSM_CNTL2__TCI_INJECT_DELAY__SHIFT 0x1a
+#define TCI_DSM_CNTL2__WRITE_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define TCI_DSM_CNTL2__WRITE_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define TCI_DSM_CNTL2__TCI_INJECT_DELAY_MASK 0xFC000000L
+//TCI_EDC_CNT
+#define TCI_EDC_CNT__WRITE_RAM_SEC_COUNT__SHIFT 0x0
+#define TCI_EDC_CNT__WRITE_RAM_DED_COUNT__SHIFT 0x2
+#define TCI_EDC_CNT__WRITE_RAM_SEC_COUNT_MASK 0x00000003L
+#define TCI_EDC_CNT__WRITE_RAM_DED_COUNT_MASK 0x0000000CL
+//TCI_STATUS
+#define TCI_STATUS__TCI_BUSY__SHIFT 0x0
+#define TCI_STATUS__TCI_BUSY_MASK 0x00000001L
+//TCI_CNTL_1
+#define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x0
+#define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x10
+#define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x18
+#define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0x0000FFFFL
+#define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0x00FF0000L
+#define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xFF000000L
+//TCI_CNTL_2
+#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x0
+#define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x1
+#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x00000001L
+#define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x000001FEL
+//TCC_CTRL
+#define TCC_CTRL__CACHE_SIZE__SHIFT 0x0
+#define TCC_CTRL__RATE__SHIFT 0x2
+#define TCC_CTRL__WRITEBACK_MARGIN__SHIFT 0x4
+#define TCC_CTRL__SRC_FIFO_SIZE__SHIFT 0xc
+#define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10
+#define TCC_CTRL__OUTPUT_FIFO_CLK_MODE__SHIFT 0x16
+#define TCC_CTRL__EXECUTE_CLK_MODE__SHIFT 0x17
+#define TCC_CTRL__RETURN_BUFFER_CLK_MODE__SHIFT 0x19
+#define TCC_CTRL__SRC_FIFO_CLK_MODE__SHIFT 0x1a
+#define TCC_CTRL__MC_WRITE_CLK_MODE__SHIFT 0x1b
+#define TCC_CTRL__LATENCY_FIFO_CLK_MODE__SHIFT 0x1c
+#define TCC_CTRL__CACHE_SIZE_MASK 0x00000003L
+#define TCC_CTRL__RATE_MASK 0x0000000CL
+#define TCC_CTRL__WRITEBACK_MARGIN_MASK 0x000000F0L
+#define TCC_CTRL__SRC_FIFO_SIZE_MASK 0x0000F000L
+#define TCC_CTRL__LATENCY_FIFO_SIZE_MASK 0x000F0000L
+#define TCC_CTRL__OUTPUT_FIFO_CLK_MODE_MASK 0x00400000L
+#define TCC_CTRL__EXECUTE_CLK_MODE_MASK 0x01800000L
+#define TCC_CTRL__RETURN_BUFFER_CLK_MODE_MASK 0x02000000L
+#define TCC_CTRL__SRC_FIFO_CLK_MODE_MASK 0x04000000L
+#define TCC_CTRL__MC_WRITE_CLK_MODE_MASK 0x08000000L
+#define TCC_CTRL__LATENCY_FIFO_CLK_MODE_MASK 0x10000000L
+//TCC_CTRL2
+#define TCC_CTRL2__PROBE_FIFO_SIZE__SHIFT 0x0
+#define TCC_CTRL2__INF_NAN_CLAMP__SHIFT 0x10
+#define TCC_CTRL2__PROBE_FILTER_CTRL__SHIFT 0x11
+#define TCC_CTRL2__WAIT_CLK_STABLE_CNT__SHIFT 0x12
+#define TCC_CTRL2__TCC_TCX_REPEATER_FGCG_DISABLE__SHIFT 0x17
+#define TCC_CTRL2__TCC_EA0_RDREQ_FGCG_DISABLE__SHIFT 0x18
+#define TCC_CTRL2__TCC_EA0_WRREQ_FGCG_DISABLE__SHIFT 0x19
+#define TCC_CTRL2__TCC_TCX_ACK_REPEATER_FGCG_DISABLE__SHIFT 0x1a
+#define TCC_CTRL2__TCC_TCA_HOLE_REPEATER_FGCG_DISABLE__SHIFT 0x1b
+#define TCC_CTRL2__TCC_TCA_RTN_REPEATER_FGCG_DISABLE__SHIFT 0x1c
+#define TCC_CTRL2__USE_EA_EARLYWRRET_ON_WRITEBACK__SHIFT 0x1d
+#define TCC_CTRL2__PROBE_FIFO_SIZE_MASK 0x0000000FL
+#define TCC_CTRL2__INF_NAN_CLAMP_MASK 0x00010000L
+#define TCC_CTRL2__PROBE_FILTER_CTRL_MASK 0x00020000L
+#define TCC_CTRL2__WAIT_CLK_STABLE_CNT_MASK 0x007C0000L
+#define TCC_CTRL2__TCC_TCX_REPEATER_FGCG_DISABLE_MASK 0x00800000L
+#define TCC_CTRL2__TCC_EA0_RDREQ_FGCG_DISABLE_MASK 0x01000000L
+#define TCC_CTRL2__TCC_EA0_WRREQ_FGCG_DISABLE_MASK 0x02000000L
+#define TCC_CTRL2__TCC_TCX_ACK_REPEATER_FGCG_DISABLE_MASK 0x04000000L
+#define TCC_CTRL2__TCC_TCA_HOLE_REPEATER_FGCG_DISABLE_MASK 0x08000000L
+#define TCC_CTRL2__TCC_TCA_RTN_REPEATER_FGCG_DISABLE_MASK 0x10000000L
+#define TCC_CTRL2__USE_EA_EARLYWRRET_ON_WRITEBACK_MASK 0x20000000L
+//TCC_EDC_CNT
+#define TCC_EDC_CNT__CACHE_DATA_SEC_COUNT__SHIFT 0x0
+#define TCC_EDC_CNT__CACHE_DATA_DED_COUNT__SHIFT 0x2
+#define TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT__SHIFT 0x4
+#define TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT__SHIFT 0x6
+#define TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT__SHIFT 0x8
+#define TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT__SHIFT 0xa
+#define TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT__SHIFT 0xc
+#define TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT__SHIFT 0xe
+#define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT__SHIFT 0x10
+#define TCC_EDC_CNT__SRC_FIFO_DED_COUNT__SHIFT 0x12
+#define TCC_EDC_CNT__LATENCY_FIFO_SEC_COUNT__SHIFT 0x14
+#define TCC_EDC_CNT__LATENCY_FIFO_DED_COUNT__SHIFT 0x16
+#define TCC_EDC_CNT__LATENCY_FIFO_NEXT_RAM_SEC_COUNT__SHIFT 0x18
+#define TCC_EDC_CNT__LATENCY_FIFO_NEXT_RAM_DED_COUNT__SHIFT 0x1a
+#define TCC_EDC_CNT__CACHE_DATA_SEC_COUNT_MASK 0x00000003L
+#define TCC_EDC_CNT__CACHE_DATA_DED_COUNT_MASK 0x0000000CL
+#define TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT_MASK 0x00000030L
+#define TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT_MASK 0x000000C0L
+#define TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT_MASK 0x00000300L
+#define TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT_MASK 0x00000C00L
+#define TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT_MASK 0x00003000L
+#define TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT_MASK 0x0000C000L
+#define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT_MASK 0x00030000L
+#define TCC_EDC_CNT__SRC_FIFO_DED_COUNT_MASK 0x000C0000L
+#define TCC_EDC_CNT__LATENCY_FIFO_SEC_COUNT_MASK 0x00300000L
+#define TCC_EDC_CNT__LATENCY_FIFO_DED_COUNT_MASK 0x00C00000L
+#define TCC_EDC_CNT__LATENCY_FIFO_NEXT_RAM_SEC_COUNT_MASK 0x03000000L
+#define TCC_EDC_CNT__LATENCY_FIFO_NEXT_RAM_DED_COUNT_MASK 0x0C000000L
+//TCC_EDC_CNT2
+#define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SEC_COUNT__SHIFT 0x0
+#define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_DED_COUNT__SHIFT 0x2
+#define TCC_EDC_CNT2__UC_ATOMIC_FIFO_SEC_COUNT__SHIFT 0x4
+#define TCC_EDC_CNT2__UC_ATOMIC_FIFO_DED_COUNT__SHIFT 0x6
+#define TCC_EDC_CNT2__WRITE_CACHE_READ_SEC_COUNT__SHIFT 0x8
+#define TCC_EDC_CNT2__WRITE_CACHE_READ_DED_COUNT__SHIFT 0xa
+#define TCC_EDC_CNT2__RETURN_CONTROL_SEC_COUNT__SHIFT 0xc
+#define TCC_EDC_CNT2__RETURN_CONTROL_DED_COUNT__SHIFT 0xe
+#define TCC_EDC_CNT2__IN_USE_TRANSFER_SEC_COUNT__SHIFT 0x10
+#define TCC_EDC_CNT2__IN_USE_TRANSFER_DED_COUNT__SHIFT 0x12
+#define TCC_EDC_CNT2__IN_USE_DEC_SEC_COUNT__SHIFT 0x14
+#define TCC_EDC_CNT2__IN_USE_DEC_DED_COUNT__SHIFT 0x16
+#define TCC_EDC_CNT2__WRITE_RETURN_SEC_COUNT__SHIFT 0x18
+#define TCC_EDC_CNT2__WRITE_RETURN_DED_COUNT__SHIFT 0x1a
+#define TCC_EDC_CNT2__RETURN_DATA_SEC_COUNT__SHIFT 0x1c
+#define TCC_EDC_CNT2__RETURN_DATA_DED_COUNT__SHIFT 0x1e
+#define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SEC_COUNT_MASK 0x00000003L
+#define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_DED_COUNT_MASK 0x0000000CL
+#define TCC_EDC_CNT2__UC_ATOMIC_FIFO_SEC_COUNT_MASK 0x00000030L
+#define TCC_EDC_CNT2__UC_ATOMIC_FIFO_DED_COUNT_MASK 0x000000C0L
+#define TCC_EDC_CNT2__WRITE_CACHE_READ_SEC_COUNT_MASK 0x00000300L
+#define TCC_EDC_CNT2__WRITE_CACHE_READ_DED_COUNT_MASK 0x00000C00L
+#define TCC_EDC_CNT2__RETURN_CONTROL_SEC_COUNT_MASK 0x00003000L
+#define TCC_EDC_CNT2__RETURN_CONTROL_DED_COUNT_MASK 0x0000C000L
+#define TCC_EDC_CNT2__IN_USE_TRANSFER_SEC_COUNT_MASK 0x00030000L
+#define TCC_EDC_CNT2__IN_USE_TRANSFER_DED_COUNT_MASK 0x000C0000L
+#define TCC_EDC_CNT2__IN_USE_DEC_SEC_COUNT_MASK 0x00300000L
+#define TCC_EDC_CNT2__IN_USE_DEC_DED_COUNT_MASK 0x00C00000L
+#define TCC_EDC_CNT2__WRITE_RETURN_SEC_COUNT_MASK 0x03000000L
+#define TCC_EDC_CNT2__WRITE_RETURN_DED_COUNT_MASK 0x0C000000L
+#define TCC_EDC_CNT2__RETURN_DATA_SEC_COUNT_MASK 0x30000000L
+#define TCC_EDC_CNT2__RETURN_DATA_DED_COUNT_MASK 0xC0000000L
+//TCC_REDUNDANCY
+#define TCC_REDUNDANCY__MC_SEL0__SHIFT 0x0
+#define TCC_REDUNDANCY__MC_SEL1__SHIFT 0x1
+#define TCC_REDUNDANCY__MC_SEL0_MASK 0x00000001L
+#define TCC_REDUNDANCY__MC_SEL1_MASK 0x00000002L
+//TCC_EXE_DISABLE
+#define TCC_EXE_DISABLE__EXE_DISABLE__SHIFT 0x1
+#define TCC_EXE_DISABLE__EXE_DISABLE_MASK 0x00000002L
+//TCC_DSM_CNTL
+#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL__SHIFT 0x0
+#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
+#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL__SHIFT 0x3
+#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE__SHIFT 0x5
+#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL__SHIFT 0x6
+#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE__SHIFT 0x8
+#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL__SHIFT 0x9
+#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE__SHIFT 0xb
+#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL__SHIFT 0xc
+#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE__SHIFT 0xe
+#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL__SHIFT 0xf
+#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE__SHIFT 0x11
+#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT 0x12
+#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT 0x14
+#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT 0x15
+#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT 0x17
+#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL__SHIFT 0x18
+#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE__SHIFT 0x1a
+#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL__SHIFT 0x1b
+#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE__SHIFT 0x1d
+#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL_MASK 0x00000003L
+#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L
+#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL_MASK 0x00000018L
+#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L
+#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL_MASK 0x000000C0L
+#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L
+#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL_MASK 0x00000600L
+#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L
+#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL_MASK 0x00003000L
+#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L
+#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL_MASK 0x00018000L
+#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L
+#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL_MASK 0x000C0000L
+#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L
+#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL_MASK 0x00600000L
+#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L
+#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL_MASK 0x03000000L
+#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE_MASK 0x04000000L
+#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL_MASK 0x18000000L
+#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE_MASK 0x20000000L
+//TCC_DSM_CNTLA
+#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x0
+#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
+#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x3
+#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x5
+#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL__SHIFT 0x6
+#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE__SHIFT 0x8
+#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL__SHIFT 0x9
+#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE__SHIFT 0xb
+#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL__SHIFT 0xc
+#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0xe
+#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL__SHIFT 0xf
+#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x11
+#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x12
+#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x14
+#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL__SHIFT 0x15
+#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE__SHIFT 0x17
+#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL__SHIFT 0x18
+#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE__SHIFT 0x1a
+#define TCC_DSM_CNTLA__OUTPUT_FIFOS_IRRITATOR_DATA_SEL__SHIFT 0x1b
+#define TCC_DSM_CNTLA__OUTPUT_FIFOS_IRRITATOR_SINGLE_WRITE__SHIFT 0x1d
+#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL_MASK 0x00000003L
+#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L
+#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL_MASK 0x00000018L
+#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L
+#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL_MASK 0x000000C0L
+#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L
+#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL_MASK 0x00000600L
+#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L
+#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL_MASK 0x00003000L
+#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L
+#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL_MASK 0x00018000L
+#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L
+#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL_MASK 0x000C0000L
+#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L
+#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL_MASK 0x00600000L
+#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L
+#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL_MASK 0x03000000L
+#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE_MASK 0x04000000L
+#define TCC_DSM_CNTLA__OUTPUT_FIFOS_IRRITATOR_DATA_SEL_MASK 0x18000000L
+#define TCC_DSM_CNTLA__OUTPUT_FIFOS_IRRITATOR_SINGLE_WRITE_MASK 0x20000000L
+//TCC_DSM_CNTL2
+#define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY__SHIFT 0x2
+#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY__SHIFT 0x5
+#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY__SHIFT 0x8
+#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY__SHIFT 0xb
+#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY__SHIFT 0xe
+#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY__SHIFT 0x11
+#define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY__SHIFT 0x14
+#define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT 0x15
+#define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY__SHIFT 0x17
+#define TCC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
+#define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY_MASK 0x00100000L
+#define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT_MASK 0x00600000L
+#define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY_MASK 0x00800000L
+#define TCC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
+//TCC_DSM_CNTL2A
+#define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY__SHIFT 0x2
+#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY__SHIFT 0x5
+#define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY__SHIFT 0x8
+#define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY__SHIFT 0xb
+#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY__SHIFT 0xe
+#define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY__SHIFT 0x11
+#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY__SHIFT 0x14
+#define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x15
+#define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY__SHIFT 0x17
+#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x18
+#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY__SHIFT 0x1a
+#define TCC_DSM_CNTL2A__OUTPUT_FIFOS_ENABLE_ERROR_INJECT__SHIFT 0x1b
+#define TCC_DSM_CNTL2A__OUTPUT_FIFOS_SELECT_INJECT_DELAY__SHIFT 0x1d
+#define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY_MASK 0x00100000L
+#define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT_MASK 0x00600000L
+#define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY_MASK 0x00800000L
+#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT_MASK 0x03000000L
+#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY_MASK 0x04000000L
+#define TCC_DSM_CNTL2A__OUTPUT_FIFOS_ENABLE_ERROR_INJECT_MASK 0x18000000L
+#define TCC_DSM_CNTL2A__OUTPUT_FIFOS_SELECT_INJECT_DELAY_MASK 0x20000000L
+//TCC_DSM_CNTL2B
+#define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY__SHIFT 0x2
+#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY__SHIFT 0x5
+#define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_SELECT_INJECT_DELAY__SHIFT 0xe
+#define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_IRRITATOR_DATA_SEL__SHIFT 0xf
+#define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_IRRITATOR_SINGLE_WRITE__SHIFT 0x11
+#define TCC_DSM_CNTL2B__RETRUN_BUFFER_LEVEL_BUBBLE_THRESHOLD__SHIFT 0x12
+#define TCC_DSM_CNTL2B__RTN_GO_FIFO_BUBBLE_THRESHOLD__SHIFT 0x18
+#define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_IRRITATOR_DATA_SEL_MASK 0x00018000L
+#define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L
+#define TCC_DSM_CNTL2B__RETRUN_BUFFER_LEVEL_BUBBLE_THRESHOLD_MASK 0x00FC0000L
+#define TCC_DSM_CNTL2B__RTN_GO_FIFO_BUBBLE_THRESHOLD_MASK 0x1F000000L
+//TCC_WBINVL2
+#define TCC_WBINVL2__DONE__SHIFT 0x4
+#define TCC_WBINVL2__DONE_MASK 0x00000010L
+//TCC_SOFT_RESET
+#define TCC_SOFT_RESET__HALT_FOR_RESET__SHIFT 0x0
+#define TCC_SOFT_RESET__HALT_FOR_RESET_MASK 0x00000001L
+//TCC_DSM_CNTL3
+#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_IRRITATOR_DATA_SEL__SHIFT 0x0
+#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
+#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_IRRITATOR_DATA_SEL__SHIFT 0x3
+#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_IRRITATOR_SINGLE_WRITE__SHIFT 0x5
+#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_IRRITATOR_DATA_SEL__SHIFT 0x6
+#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_IRRITATOR_SINGLE_WRITE__SHIFT 0x8
+#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_IRRITATOR_DATA_SEL__SHIFT 0x9
+#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_IRRITATOR_SINGLE_WRITE__SHIFT 0xb
+#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_SELECT_INJECT_DELAY__SHIFT 0xe
+#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_SELECT_INJECT_DELAY__SHIFT 0x11
+#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_SELECT_INJECT_DELAY__SHIFT 0x14
+#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_ENABLE_ERROR_INJECT__SHIFT 0x15
+#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_SELECT_INJECT_DELAY__SHIFT 0x17
+#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_IRRITATOR_DATA_SEL_MASK 0x00000003L
+#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L
+#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_IRRITATOR_DATA_SEL_MASK 0x00000018L
+#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L
+#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_IRRITATOR_DATA_SEL_MASK 0x000000C0L
+#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L
+#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_IRRITATOR_DATA_SEL_MASK 0x00000600L
+#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L
+#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_SELECT_INJECT_DELAY_MASK 0x00100000L
+#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_ENABLE_ERROR_INJECT_MASK 0x00600000L
+#define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_SELECT_INJECT_DELAY_MASK 0x00800000L
+//TCA_CTRL
+#define TCA_CTRL__HOLE_TIMEOUT__SHIFT 0x0
+#define TCA_CTRL__RB_STILL_4_PHASE__SHIFT 0x4
+#define TCA_CTRL__RB_AS_TCI__SHIFT 0x5
+#define TCA_CTRL__DISABLE_UTCL2_PRIORITY__SHIFT 0x6
+#define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER__SHIFT 0x7
+#define TCA_CTRL__TCA_TCC_FGCG_DISABLE__SHIFT 0x8
+#define TCA_CTRL__TCA_TCA_FGCG_DISABLE__SHIFT 0x9
+#define TCA_CTRL__TCA_TCH_FGCG_DISABLE__SHIFT 0xa
+#define TCA_CTRL__TCA_TCX_FGCG_DISABLE__SHIFT 0xb
+#define TCA_CTRL__TCA_RANDOM_REVERSE_PRIORITY_ENABLE__SHIFT 0xc
+#define TCA_CTRL__RTN_CREDIT_THRESHOLD__SHIFT 0xd
+#define TCA_CTRL__ACK_CREDIT_THRESHOLD__SHIFT 0x10
+#define TCA_CTRL__HOLE_TIMEOUT_MASK 0x0000000FL
+#define TCA_CTRL__RB_STILL_4_PHASE_MASK 0x00000010L
+#define TCA_CTRL__RB_AS_TCI_MASK 0x00000020L
+#define TCA_CTRL__DISABLE_UTCL2_PRIORITY_MASK 0x00000040L
+#define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER_MASK 0x00000080L
+#define TCA_CTRL__TCA_TCC_FGCG_DISABLE_MASK 0x00000100L
+#define TCA_CTRL__TCA_TCA_FGCG_DISABLE_MASK 0x00000200L
+#define TCA_CTRL__TCA_TCH_FGCG_DISABLE_MASK 0x00000400L
+#define TCA_CTRL__TCA_TCX_FGCG_DISABLE_MASK 0x00000800L
+#define TCA_CTRL__TCA_RANDOM_REVERSE_PRIORITY_ENABLE_MASK 0x00001000L
+#define TCA_CTRL__RTN_CREDIT_THRESHOLD_MASK 0x0000E000L
+#define TCA_CTRL__ACK_CREDIT_THRESHOLD_MASK 0x00070000L
+//TCA_BURST_MASK
+#define TCA_BURST_MASK__ADDR_MASK__SHIFT 0x0
+#define TCA_BURST_MASK__ADDR_MASK_MASK 0xFFFFFFFFL
+//TCA_BURST_CTRL
+#define TCA_BURST_CTRL__MAX_BURST__SHIFT 0x0
+#define TCA_BURST_CTRL__TCP_DISABLE__SHIFT 0x4
+#define TCA_BURST_CTRL__SQC_DISABLE__SHIFT 0x5
+#define TCA_BURST_CTRL__CPF_DISABLE__SHIFT 0x6
+#define TCA_BURST_CTRL__CPG_DISABLE__SHIFT 0x7
+#define TCA_BURST_CTRL__SQG_DISABLE__SHIFT 0xa
+#define TCA_BURST_CTRL__UTCL2_DISABLE__SHIFT 0xb
+#define TCA_BURST_CTRL__TPI_DISABLE__SHIFT 0xc
+#define TCA_BURST_CTRL__RLC_DISABLE__SHIFT 0xd
+#define TCA_BURST_CTRL__MAX_BURST_MASK 0x00000007L
+#define TCA_BURST_CTRL__TCP_DISABLE_MASK 0x00000010L
+#define TCA_BURST_CTRL__SQC_DISABLE_MASK 0x00000020L
+#define TCA_BURST_CTRL__CPF_DISABLE_MASK 0x00000040L
+#define TCA_BURST_CTRL__CPG_DISABLE_MASK 0x00000080L
+#define TCA_BURST_CTRL__SQG_DISABLE_MASK 0x00000400L
+#define TCA_BURST_CTRL__UTCL2_DISABLE_MASK 0x00000800L
+#define TCA_BURST_CTRL__TPI_DISABLE_MASK 0x00001000L
+#define TCA_BURST_CTRL__RLC_DISABLE_MASK 0x00002000L
+//TCA_DSM_CNTL
+#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT 0x0
+#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
+#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT 0x3
+#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT 0x5
+#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL_MASK 0x00000003L
+#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L
+#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL_MASK 0x00000018L
+#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L
+//TCA_DSM_CNTL2
+#define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY__SHIFT 0x2
+#define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY__SHIFT 0x5
+#define TCA_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
+#define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define TCA_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
+//TCA_EDC_CNT
+#define TCA_EDC_CNT__HOLE_FIFO_SEC_COUNT__SHIFT 0x0
+#define TCA_EDC_CNT__HOLE_FIFO_DED_COUNT__SHIFT 0x2
+#define TCA_EDC_CNT__REQ_FIFO_SEC_COUNT__SHIFT 0x4
+#define TCA_EDC_CNT__REQ_FIFO_DED_COUNT__SHIFT 0x6
+#define TCA_EDC_CNT__HOLE_FIFO_SEC_COUNT_MASK 0x00000003L
+#define TCA_EDC_CNT__HOLE_FIFO_DED_COUNT_MASK 0x0000000CL
+#define TCA_EDC_CNT__REQ_FIFO_SEC_COUNT_MASK 0x00000030L
+#define TCA_EDC_CNT__REQ_FIFO_DED_COUNT_MASK 0x000000C0L
+//TCX_CTRL
+#define TCX_CTRL__TCX_TCX_FGCG_DISABLE__SHIFT 0x0
+#define TCX_CTRL__TCX_TCR_FGCG_DISABLE__SHIFT 0x1
+#define TCX_CTRL__TCX_TCC_FGCG_DISABLE__SHIFT 0x2
+#define TCX_CTRL__TCX_TCX_FGCG_DISABLE_MASK 0x00000001L
+#define TCX_CTRL__TCX_TCR_FGCG_DISABLE_MASK 0x00000002L
+#define TCX_CTRL__TCX_TCC_FGCG_DISABLE_MASK 0x00000004L
+//TCX_DSM_CNTL
+#define TCX_DSM_CNTL__GROUP0_SED_IRRITATOR_DATA_SEL__SHIFT 0x0
+#define TCX_DSM_CNTL__GROUP1_SED_IRRITATOR_DATA_SEL__SHIFT 0x2
+#define TCX_DSM_CNTL__GROUP2_SED_IRRITATOR_DATA_SEL__SHIFT 0x4
+#define TCX_DSM_CNTL__GROUP3_SED_IRRITATOR_DATA_SEL__SHIFT 0x6
+#define TCX_DSM_CNTL__GROUP4_SED_IRRITATOR_DATA_SEL__SHIFT 0x8
+#define TCX_DSM_CNTL__GROUP5_SED_IRRITATOR_DATA_SEL__SHIFT 0xa
+#define TCX_DSM_CNTL__GROUP6_SED_IRRITATOR_DATA_SEL__SHIFT 0xc
+#define TCX_DSM_CNTL__GROUP7_SED_IRRITATOR_DATA_SEL__SHIFT 0xe
+#define TCX_DSM_CNTL__GROUP8_SED_IRRITATOR_DATA_SEL__SHIFT 0x10
+#define TCX_DSM_CNTL__GROUP9_SED_IRRITATOR_DATA_SEL__SHIFT 0x12
+#define TCX_DSM_CNTL__GROUP10_SED_IRRITATOR_DATA_SEL__SHIFT 0x14
+#define TCX_DSM_CNTL__GROUP11_SED_IRRITATOR_DATA_SEL__SHIFT 0x16
+#define TCX_DSM_CNTL__GROUP12_SED_IRRITATOR_DATA_SEL__SHIFT 0x18
+#define TCX_DSM_CNTL__GROUP13_SED_IRRITATOR_DATA_SEL__SHIFT 0x1a
+#define TCX_DSM_CNTL__GROUP14_SED_IRRITATOR_DATA_SEL__SHIFT 0x1c
+#define TCX_DSM_CNTL__SED_IRRITATOR_SINGLE_WRITE__SHIFT 0x1e
+#define TCX_DSM_CNTL__GROUP0_SED_IRRITATOR_DATA_SEL_MASK 0x00000003L
+#define TCX_DSM_CNTL__GROUP1_SED_IRRITATOR_DATA_SEL_MASK 0x0000000CL
+#define TCX_DSM_CNTL__GROUP2_SED_IRRITATOR_DATA_SEL_MASK 0x00000030L
+#define TCX_DSM_CNTL__GROUP3_SED_IRRITATOR_DATA_SEL_MASK 0x000000C0L
+#define TCX_DSM_CNTL__GROUP4_SED_IRRITATOR_DATA_SEL_MASK 0x00000300L
+#define TCX_DSM_CNTL__GROUP5_SED_IRRITATOR_DATA_SEL_MASK 0x00000C00L
+#define TCX_DSM_CNTL__GROUP6_SED_IRRITATOR_DATA_SEL_MASK 0x00003000L
+#define TCX_DSM_CNTL__GROUP7_SED_IRRITATOR_DATA_SEL_MASK 0x0000C000L
+#define TCX_DSM_CNTL__GROUP8_SED_IRRITATOR_DATA_SEL_MASK 0x00030000L
+#define TCX_DSM_CNTL__GROUP9_SED_IRRITATOR_DATA_SEL_MASK 0x000C0000L
+#define TCX_DSM_CNTL__GROUP10_SED_IRRITATOR_DATA_SEL_MASK 0x00300000L
+#define TCX_DSM_CNTL__GROUP11_SED_IRRITATOR_DATA_SEL_MASK 0x00C00000L
+#define TCX_DSM_CNTL__GROUP12_SED_IRRITATOR_DATA_SEL_MASK 0x03000000L
+#define TCX_DSM_CNTL__GROUP13_SED_IRRITATOR_DATA_SEL_MASK 0x0C000000L
+#define TCX_DSM_CNTL__GROUP14_SED_IRRITATOR_DATA_SEL_MASK 0x30000000L
+#define TCX_DSM_CNTL__SED_IRRITATOR_SINGLE_WRITE_MASK 0x40000000L
+//TCX_DSM_CNTL2
+#define TCX_DSM_CNTL2__SED_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define TCX_DSM_CNTL2__SED_SELECT_INJECT_DELAY__SHIFT 0x2
+#define TCX_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
+#define TCX_DSM_CNTL2__SED_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define TCX_DSM_CNTL2__SED_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define TCX_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
+//TCX_EDC_CNT
+#define TCX_EDC_CNT__GROUP0_SEC_COUNT__SHIFT 0x0
+#define TCX_EDC_CNT__GROUP0_DED_COUNT__SHIFT 0x2
+#define TCX_EDC_CNT__GROUP1_SEC_COUNT__SHIFT 0x4
+#define TCX_EDC_CNT__GROUP1_DED_COUNT__SHIFT 0x6
+#define TCX_EDC_CNT__GROUP2_SEC_COUNT__SHIFT 0x8
+#define TCX_EDC_CNT__GROUP2_DED_COUNT__SHIFT 0xa
+#define TCX_EDC_CNT__GROUP3_SEC_COUNT__SHIFT 0xc
+#define TCX_EDC_CNT__GROUP3_DED_COUNT__SHIFT 0xe
+#define TCX_EDC_CNT__GROUP4_SEC_COUNT__SHIFT 0x10
+#define TCX_EDC_CNT__GROUP4_DED_COUNT__SHIFT 0x12
+#define TCX_EDC_CNT__GROUP5_SED_COUNT__SHIFT 0x14
+#define TCX_EDC_CNT__GROUP6_SED_COUNT__SHIFT 0x16
+#define TCX_EDC_CNT__GROUP7_SED_COUNT__SHIFT 0x18
+#define TCX_EDC_CNT__GROUP8_SED_COUNT__SHIFT 0x1a
+#define TCX_EDC_CNT__GROUP9_SED_COUNT__SHIFT 0x1c
+#define TCX_EDC_CNT__GROUP10_SED_COUNT__SHIFT 0x1e
+#define TCX_EDC_CNT__GROUP0_SEC_COUNT_MASK 0x00000003L
+#define TCX_EDC_CNT__GROUP0_DED_COUNT_MASK 0x0000000CL
+#define TCX_EDC_CNT__GROUP1_SEC_COUNT_MASK 0x00000030L
+#define TCX_EDC_CNT__GROUP1_DED_COUNT_MASK 0x000000C0L
+#define TCX_EDC_CNT__GROUP2_SEC_COUNT_MASK 0x00000300L
+#define TCX_EDC_CNT__GROUP2_DED_COUNT_MASK 0x00000C00L
+#define TCX_EDC_CNT__GROUP3_SEC_COUNT_MASK 0x00003000L
+#define TCX_EDC_CNT__GROUP3_DED_COUNT_MASK 0x0000C000L
+#define TCX_EDC_CNT__GROUP4_SEC_COUNT_MASK 0x00030000L
+#define TCX_EDC_CNT__GROUP4_DED_COUNT_MASK 0x000C0000L
+#define TCX_EDC_CNT__GROUP5_SED_COUNT_MASK 0x00300000L
+#define TCX_EDC_CNT__GROUP6_SED_COUNT_MASK 0x00C00000L
+#define TCX_EDC_CNT__GROUP7_SED_COUNT_MASK 0x03000000L
+#define TCX_EDC_CNT__GROUP8_SED_COUNT_MASK 0x0C000000L
+#define TCX_EDC_CNT__GROUP9_SED_COUNT_MASK 0x30000000L
+#define TCX_EDC_CNT__GROUP10_SED_COUNT_MASK 0xC0000000L
+//TCX_EDC_CNT2
+#define TCX_EDC_CNT2__GROUP11_SED_COUNT__SHIFT 0x0
+#define TCX_EDC_CNT2__GROUP12_SED_COUNT__SHIFT 0x2
+#define TCX_EDC_CNT2__GROUP13_SED_COUNT__SHIFT 0x4
+#define TCX_EDC_CNT2__GROUP14_SED_COUNT__SHIFT 0x6
+#define TCX_EDC_CNT2__GROUP11_SED_COUNT_MASK 0x00000003L
+#define TCX_EDC_CNT2__GROUP12_SED_COUNT_MASK 0x0000000CL
+#define TCX_EDC_CNT2__GROUP13_SED_COUNT_MASK 0x00000030L
+#define TCX_EDC_CNT2__GROUP14_SED_COUNT_MASK 0x000000C0L
+
+
+// addressBlock: gc_tcpdec
+//TCP_WATCH0_ADDR_H
+#define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0
+#define TCP_WATCH0_ADDR_H__ADDR_MASK 0x0000FFFFL
+//TCP_WATCH0_ADDR_L
+#define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x6
+#define TCP_WATCH0_ADDR_L__ADDR_MASK 0xFFFFFFC0L
+//TCP_WATCH0_CNTL
+#define TCP_WATCH0_CNTL__MASK__SHIFT 0x0
+#define TCP_WATCH0_CNTL__VMID__SHIFT 0x18
+#define TCP_WATCH0_CNTL__ATC__SHIFT 0x1c
+#define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d
+#define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f
+#define TCP_WATCH0_CNTL__MASK_MASK 0x00FFFFFFL
+#define TCP_WATCH0_CNTL__VMID_MASK 0x0F000000L
+#define TCP_WATCH0_CNTL__ATC_MASK 0x10000000L
+#define TCP_WATCH0_CNTL__MODE_MASK 0x60000000L
+#define TCP_WATCH0_CNTL__VALID_MASK 0x80000000L
+//TCP_WATCH1_ADDR_H
+#define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0
+#define TCP_WATCH1_ADDR_H__ADDR_MASK 0x0000FFFFL
+//TCP_WATCH1_ADDR_L
+#define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x6
+#define TCP_WATCH1_ADDR_L__ADDR_MASK 0xFFFFFFC0L
+//TCP_WATCH1_CNTL
+#define TCP_WATCH1_CNTL__MASK__SHIFT 0x0
+#define TCP_WATCH1_CNTL__VMID__SHIFT 0x18
+#define TCP_WATCH1_CNTL__ATC__SHIFT 0x1c
+#define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d
+#define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f
+#define TCP_WATCH1_CNTL__MASK_MASK 0x00FFFFFFL
+#define TCP_WATCH1_CNTL__VMID_MASK 0x0F000000L
+#define TCP_WATCH1_CNTL__ATC_MASK 0x10000000L
+#define TCP_WATCH1_CNTL__MODE_MASK 0x60000000L
+#define TCP_WATCH1_CNTL__VALID_MASK 0x80000000L
+//TCP_WATCH2_ADDR_H
+#define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0
+#define TCP_WATCH2_ADDR_H__ADDR_MASK 0x0000FFFFL
+//TCP_WATCH2_ADDR_L
+#define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x6
+#define TCP_WATCH2_ADDR_L__ADDR_MASK 0xFFFFFFC0L
+//TCP_WATCH2_CNTL
+#define TCP_WATCH2_CNTL__MASK__SHIFT 0x0
+#define TCP_WATCH2_CNTL__VMID__SHIFT 0x18
+#define TCP_WATCH2_CNTL__ATC__SHIFT 0x1c
+#define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d
+#define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f
+#define TCP_WATCH2_CNTL__MASK_MASK 0x00FFFFFFL
+#define TCP_WATCH2_CNTL__VMID_MASK 0x0F000000L
+#define TCP_WATCH2_CNTL__ATC_MASK 0x10000000L
+#define TCP_WATCH2_CNTL__MODE_MASK 0x60000000L
+#define TCP_WATCH2_CNTL__VALID_MASK 0x80000000L
+//TCP_WATCH3_ADDR_H
+#define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0
+#define TCP_WATCH3_ADDR_H__ADDR_MASK 0x0000FFFFL
+//TCP_WATCH3_ADDR_L
+#define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x6
+#define TCP_WATCH3_ADDR_L__ADDR_MASK 0xFFFFFFC0L
+//TCP_WATCH3_CNTL
+#define TCP_WATCH3_CNTL__MASK__SHIFT 0x0
+#define TCP_WATCH3_CNTL__VMID__SHIFT 0x18
+#define TCP_WATCH3_CNTL__ATC__SHIFT 0x1c
+#define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d
+#define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f
+#define TCP_WATCH3_CNTL__MASK_MASK 0x00FFFFFFL
+#define TCP_WATCH3_CNTL__VMID_MASK 0x0F000000L
+#define TCP_WATCH3_CNTL__ATC_MASK 0x10000000L
+#define TCP_WATCH3_CNTL__MODE_MASK 0x60000000L
+#define TCP_WATCH3_CNTL__VALID_MASK 0x80000000L
+//TCP_GATCL1_CNTL
+#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID__SHIFT 0x19
+#define TCP_GATCL1_CNTL__FORCE_MISS__SHIFT 0x1a
+#define TCP_GATCL1_CNTL__FORCE_IN_ORDER__SHIFT 0x1b
+#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
+#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
+#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID_MASK 0x02000000L
+#define TCP_GATCL1_CNTL__FORCE_MISS_MASK 0x04000000L
+#define TCP_GATCL1_CNTL__FORCE_IN_ORDER_MASK 0x08000000L
+#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
+#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
+//TCP_ATC_EDC_GATCL1_CNT
+#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC__SHIFT 0x0
+#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC_MASK 0x000000FFL
+//TCP_GATCL1_DSM_CNTL
+#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0__SHIFT 0x0
+#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1__SHIFT 0x1
+#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A__SHIFT 0x2
+#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0_MASK 0x00000001L
+#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1_MASK 0x00000002L
+#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A_MASK 0x00000004L
+//TCP_DSM_CNTL
+#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0
+#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
+#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL__SHIFT 0x3
+#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x5
+#define TCP_DSM_CNTL__CMD_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x6
+#define TCP_DSM_CNTL__CMD_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x8
+#define TCP_DSM_CNTL__VM_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x9
+#define TCP_DSM_CNTL__VM_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0xb
+#define TCP_DSM_CNTL__DB_RAM_IRRITATOR_DATA_SEL__SHIFT 0xc
+#define TCP_DSM_CNTL__DB_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0xe
+#define TCP_DSM_CNTL__UTCL1_LFIFO0_IRRITATOR_DATA_SEL__SHIFT 0xf
+#define TCP_DSM_CNTL__UTCL1_LFIFO0_IRRITATOR_SINGLE_WRITE__SHIFT 0x11
+#define TCP_DSM_CNTL__UTCL1_LFIFO1_IRRITATOR_DATA_SEL__SHIFT 0x12
+#define TCP_DSM_CNTL__UTCL1_LFIFO1_IRRITATOR_SINGLE_WRITE__SHIFT 0x14
+#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL_MASK 0x00000003L
+#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L
+#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL_MASK 0x00000018L
+#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L
+#define TCP_DSM_CNTL__CMD_FIFO_IRRITATOR_DATA_SEL_MASK 0x000000C0L
+#define TCP_DSM_CNTL__CMD_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L
+#define TCP_DSM_CNTL__VM_FIFO_IRRITATOR_DATA_SEL_MASK 0x00000600L
+#define TCP_DSM_CNTL__VM_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L
+#define TCP_DSM_CNTL__DB_RAM_IRRITATOR_DATA_SEL_MASK 0x00003000L
+#define TCP_DSM_CNTL__DB_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L
+#define TCP_DSM_CNTL__UTCL1_LFIFO0_IRRITATOR_DATA_SEL_MASK 0x00018000L
+#define TCP_DSM_CNTL__UTCL1_LFIFO0_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L
+#define TCP_DSM_CNTL__UTCL1_LFIFO1_IRRITATOR_DATA_SEL_MASK 0x000C0000L
+#define TCP_DSM_CNTL__UTCL1_LFIFO1_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L
+//TCP_UTCL1_CNTL1
+#define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
+#define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1
+#define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
+#define TCP_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
+#define TCP_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
+#define TCP_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
+#define TCP_UTCL1_CNTL1__UTCL1_FGCG_REPEATER_DISABLE__SHIFT 0x10
+#define TCP_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13
+#define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17
+#define TCP_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18
+#define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
+#define TCP_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
+#define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
+#define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
+#define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
+#define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L
+#define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
+#define TCP_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
+#define TCP_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
+#define TCP_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
+#define TCP_UTCL1_CNTL1__UTCL1_FGCG_REPEATER_DISABLE_MASK 0x00010000L
+#define TCP_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L
+#define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L
+#define TCP_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L
+#define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
+#define TCP_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
+#define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
+#define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
+//TCP_UTCL1_CNTL2
+#define TCP_UTCL1_CNTL2__SPARE__SHIFT 0x0
+#define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
+#define TCP_UTCL1_CNTL2__ANY_LINE_VALID__SHIFT 0xa
+#define TCP_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
+#define TCP_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
+#define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
+#define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
+#define TCP_UTCL1_CNTL2__SPARE_MASK 0x000000FFL
+#define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
+#define TCP_UTCL1_CNTL2__ANY_LINE_VALID_MASK 0x00000400L
+#define TCP_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
+#define TCP_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
+#define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
+#define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
+//TCP_UTCL1_STATUS
+#define TCP_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
+#define TCP_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
+#define TCP_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
+#define TCP_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
+#define TCP_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
+#define TCP_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
+//TCP_DSM_CNTL2
+#define TCP_DSM_CNTL2__CACHE_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define TCP_DSM_CNTL2__CACHE_RAM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define TCP_DSM_CNTL2__LFIFO_RAM_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define TCP_DSM_CNTL2__LFIFO_RAM_SELECT_INJECT_DELAY__SHIFT 0x5
+#define TCP_DSM_CNTL2__CMD_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define TCP_DSM_CNTL2__CMD_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8
+#define TCP_DSM_CNTL2__VM_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define TCP_DSM_CNTL2__VM_FIFO_SELECT_INJECT_DELAY__SHIFT 0xb
+#define TCP_DSM_CNTL2__DB_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define TCP_DSM_CNTL2__DB_RAM_SELECT_INJECT_DELAY__SHIFT 0xe
+#define TCP_DSM_CNTL2__UTCL1_LFIFO0_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define TCP_DSM_CNTL2__UTCL1_LFIFO0_SELECT_INJECT_DELAY__SHIFT 0x11
+#define TCP_DSM_CNTL2__UTCL1_LFIFO1_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define TCP_DSM_CNTL2__UTCL1_LFIFO1_SELECT_INJECT_DELAY__SHIFT 0x14
+#define TCP_DSM_CNTL2__TCP_INJECT_DELAY__SHIFT 0x1a
+#define TCP_DSM_CNTL2__CACHE_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define TCP_DSM_CNTL2__CACHE_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define TCP_DSM_CNTL2__LFIFO_RAM_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define TCP_DSM_CNTL2__LFIFO_RAM_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define TCP_DSM_CNTL2__CMD_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define TCP_DSM_CNTL2__CMD_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define TCP_DSM_CNTL2__VM_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define TCP_DSM_CNTL2__VM_FIFO_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define TCP_DSM_CNTL2__DB_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define TCP_DSM_CNTL2__DB_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define TCP_DSM_CNTL2__UTCL1_LFIFO0_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define TCP_DSM_CNTL2__UTCL1_LFIFO0_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define TCP_DSM_CNTL2__UTCL1_LFIFO1_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define TCP_DSM_CNTL2__UTCL1_LFIFO1_SELECT_INJECT_DELAY_MASK 0x00100000L
+#define TCP_DSM_CNTL2__TCP_INJECT_DELAY_MASK 0xFC000000L
+//TCP_PERFCOUNTER_FILTER
+#define TCP_PERFCOUNTER_FILTER__BUFFER__SHIFT 0x0
+#define TCP_PERFCOUNTER_FILTER__FLAT__SHIFT 0x1
+#define TCP_PERFCOUNTER_FILTER__DIM__SHIFT 0x2
+#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT__SHIFT 0x5
+#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT__SHIFT 0xb
+#define TCP_PERFCOUNTER_FILTER__SW_MODE__SHIFT 0xf
+#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES__SHIFT 0x14
+#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE__SHIFT 0x16
+#define TCP_PERFCOUNTER_FILTER__GLC__SHIFT 0x19
+#define TCP_PERFCOUNTER_FILTER__SLC__SHIFT 0x1a
+#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE__SHIFT 0x1b
+#define TCP_PERFCOUNTER_FILTER__ADDR_MODE__SHIFT 0x1c
+#define TCP_PERFCOUNTER_FILTER__BUFFER_MASK 0x00000001L
+#define TCP_PERFCOUNTER_FILTER__FLAT_MASK 0x00000002L
+#define TCP_PERFCOUNTER_FILTER__DIM_MASK 0x0000001CL
+#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT_MASK 0x000007E0L
+#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT_MASK 0x00007800L
+#define TCP_PERFCOUNTER_FILTER__SW_MODE_MASK 0x000F8000L
+#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES_MASK 0x00300000L
+#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE_MASK 0x01C00000L
+#define TCP_PERFCOUNTER_FILTER__GLC_MASK 0x02000000L
+#define TCP_PERFCOUNTER_FILTER__SLC_MASK 0x04000000L
+#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE_MASK 0x08000000L
+#define TCP_PERFCOUNTER_FILTER__ADDR_MODE_MASK 0x70000000L
+//TCP_PERFCOUNTER_FILTER_EN
+#define TCP_PERFCOUNTER_FILTER_EN__BUFFER__SHIFT 0x0
+#define TCP_PERFCOUNTER_FILTER_EN__FLAT__SHIFT 0x1
+#define TCP_PERFCOUNTER_FILTER_EN__DIM__SHIFT 0x2
+#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT__SHIFT 0x3
+#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT__SHIFT 0x4
+#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE__SHIFT 0x5
+#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES__SHIFT 0x6
+#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE__SHIFT 0x7
+#define TCP_PERFCOUNTER_FILTER_EN__GLC__SHIFT 0x8
+#define TCP_PERFCOUNTER_FILTER_EN__SLC__SHIFT 0x9
+#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE__SHIFT 0xa
+#define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE__SHIFT 0xb
+#define TCP_PERFCOUNTER_FILTER_EN__BUFFER_MASK 0x00000001L
+#define TCP_PERFCOUNTER_FILTER_EN__FLAT_MASK 0x00000002L
+#define TCP_PERFCOUNTER_FILTER_EN__DIM_MASK 0x00000004L
+#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT_MASK 0x00000008L
+#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT_MASK 0x00000010L
+#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE_MASK 0x00000020L
+#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES_MASK 0x00000040L
+#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE_MASK 0x00000080L
+#define TCP_PERFCOUNTER_FILTER_EN__GLC_MASK 0x00000100L
+#define TCP_PERFCOUNTER_FILTER_EN__SLC_MASK 0x00000200L
+#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE_MASK 0x00000400L
+#define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE_MASK 0x00000800L
+
+
+// addressBlock: gc_tpdec
+//TD_STATUS
+#define TD_STATUS__BUSY__SHIFT 0x1f
+#define TD_STATUS__BUSY_MASK 0x80000000L
+//TD_EDC_CNT
+#define TD_EDC_CNT__SS_FIFO_LO_SEC_COUNT__SHIFT 0x0
+#define TD_EDC_CNT__SS_FIFO_LO_DED_COUNT__SHIFT 0x2
+#define TD_EDC_CNT__SS_FIFO_HI_SEC_COUNT__SHIFT 0x4
+#define TD_EDC_CNT__SS_FIFO_HI_DED_COUNT__SHIFT 0x6
+#define TD_EDC_CNT__CS_FIFO_SEC_COUNT__SHIFT 0x8
+#define TD_EDC_CNT__CS_FIFO_DED_COUNT__SHIFT 0xa
+#define TD_EDC_CNT__SS_FIFO_LO_SEC_COUNT_MASK 0x00000003L
+#define TD_EDC_CNT__SS_FIFO_LO_DED_COUNT_MASK 0x0000000CL
+#define TD_EDC_CNT__SS_FIFO_HI_SEC_COUNT_MASK 0x00000030L
+#define TD_EDC_CNT__SS_FIFO_HI_DED_COUNT_MASK 0x000000C0L
+#define TD_EDC_CNT__CS_FIFO_SEC_COUNT_MASK 0x00000300L
+#define TD_EDC_CNT__CS_FIFO_DED_COUNT_MASK 0x00000C00L
+//TD_DSM_CNTL
+#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA__SHIFT 0x3
+#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA_MASK 0x00000018L
+#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+//TD_DSM_CNTL2
+#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY__SHIFT 0x2
+#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY__SHIFT 0x5
+#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8
+#define TD_DSM_CNTL2__TD_INJECT_DELAY__SHIFT 0x1a
+#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define TD_DSM_CNTL2__TD_INJECT_DELAY_MASK 0xFC000000L
+//TD_SCRATCH
+#define TD_SCRATCH__SCRATCH__SHIFT 0x0
+#define TD_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL
+//TA_CNTL
+#define TA_CNTL__FX_XNACK_CREDIT__SHIFT 0x0
+#define TA_CNTL__SQ_XNACK_CREDIT__SHIFT 0x9
+#define TA_CNTL__TC_DATA_CREDIT__SHIFT 0xd
+#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10
+#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16
+#define TA_CNTL__FX_XNACK_CREDIT_MASK 0x0000007FL
+#define TA_CNTL__SQ_XNACK_CREDIT_MASK 0x00001E00L
+#define TA_CNTL__TC_DATA_CREDIT_MASK 0x0000E000L
+#define TA_CNTL__ALIGNER_CREDIT_MASK 0x001F0000L
+#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xFFC00000L
+//TA_CNTL_AUX
+#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0
+#define TA_CNTL_AUX__RESERVED__SHIFT 0x1
+#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE__SHIFT 0x5
+#define TA_CNTL_AUX__GATHERH_DST_SEL__SHIFT 0x6
+#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE__SHIFT 0x7
+#define TA_CNTL_AUX__NONIMG_ANISO_BYPASS__SHIFT 0x9
+#define TA_CNTL_AUX__ANISO_HALF_THRESH__SHIFT 0xa
+#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS__SHIFT 0xc
+#define TA_CNTL_AUX__ANISO_STEP_ORDER__SHIFT 0xd
+#define TA_CNTL_AUX__ANISO_STEP__SHIFT 0xe
+#define TA_CNTL_AUX__MINMAG_UNNORM__SHIFT 0xf
+#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10
+#define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT 0x11
+#define TA_CNTL_AUX__ANISO_TAP__SHIFT 0x12
+#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE__SHIFT 0x13
+#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT 0x14
+#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT 0x15
+#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT 0x16
+#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE__SHIFT 0x17
+#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE__SHIFT 0x18
+#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT 0x19
+#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT 0x1a
+#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE__SHIFT 0x1b
+#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP__SHIFT 0x1c
+#define TA_CNTL_AUX__TRUNC_SMALL_NEG__SHIFT 0x1d
+#define TA_CNTL_AUX__ARRAY_ROUND_MODE__SHIFT 0x1e
+#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x00000001L
+#define TA_CNTL_AUX__RESERVED_MASK 0x0000000EL
+#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE_MASK 0x00000020L
+#define TA_CNTL_AUX__GATHERH_DST_SEL_MASK 0x00000040L
+#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE_MASK 0x00000080L
+#define TA_CNTL_AUX__NONIMG_ANISO_BYPASS_MASK 0x00000200L
+#define TA_CNTL_AUX__ANISO_HALF_THRESH_MASK 0x00000C00L
+#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS_MASK 0x00001000L
+#define TA_CNTL_AUX__ANISO_STEP_ORDER_MASK 0x00002000L
+#define TA_CNTL_AUX__ANISO_STEP_MASK 0x00004000L
+#define TA_CNTL_AUX__MINMAG_UNNORM_MASK 0x00008000L
+#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x00010000L
+#define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK 0x00020000L
+#define TA_CNTL_AUX__ANISO_TAP_MASK 0x00040000L
+#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE_MASK 0x00080000L
+#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK 0x00100000L
+#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK 0x00200000L
+#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK 0x00400000L
+#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE_MASK 0x00800000L
+#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE_MASK 0x01000000L
+#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK 0x02000000L
+#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK 0x04000000L
+#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE_MASK 0x08000000L
+#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP_MASK 0x10000000L
+#define TA_CNTL_AUX__TRUNC_SMALL_NEG_MASK 0x20000000L
+#define TA_CNTL_AUX__ARRAY_ROUND_MODE_MASK 0xC0000000L
+//TA_FEATURE_CNTL
+#define TA_FEATURE_CNTL__ATOMIC_COALESCING_EN__SHIFT 0x4
+#define TA_FEATURE_CNTL__NONIMG_TA_FASTPATH__SHIFT 0xa
+#define TA_FEATURE_CNTL__TA_ACFIFO_CHICKEN__SHIFT 0xb
+#define TA_FEATURE_CNTL__TA_CAC_CHICKEN__SHIFT 0xc
+#define TA_FEATURE_CNTL__AFIFO_SPLIT_CHICKEN__SHIFT 0xd
+#define TA_FEATURE_CNTL__ATOMIC_COALESCING_EN_MASK 0x00000030L
+#define TA_FEATURE_CNTL__NONIMG_TA_FASTPATH_MASK 0x00000400L
+#define TA_FEATURE_CNTL__TA_ACFIFO_CHICKEN_MASK 0x00000800L
+#define TA_FEATURE_CNTL__TA_CAC_CHICKEN_MASK 0x00001000L
+#define TA_FEATURE_CNTL__AFIFO_SPLIT_CHICKEN_MASK 0x00002000L
+//TA_STATUS
+#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc
+#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd
+#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe
+#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10
+#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11
+#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12
+#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14
+#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15
+#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16
+#define TA_STATUS__IN_BUSY__SHIFT 0x18
+#define TA_STATUS__FG_BUSY__SHIFT 0x19
+#define TA_STATUS__LA_BUSY__SHIFT 0x1a
+#define TA_STATUS__FL_BUSY__SHIFT 0x1b
+#define TA_STATUS__TA_BUSY__SHIFT 0x1c
+#define TA_STATUS__FA_BUSY__SHIFT 0x1d
+#define TA_STATUS__AL_BUSY__SHIFT 0x1e
+#define TA_STATUS__BUSY__SHIFT 0x1f
+#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x00001000L
+#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x00002000L
+#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x00004000L
+#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x00010000L
+#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x00020000L
+#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x00040000L
+#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x00100000L
+#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x00200000L
+#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x00400000L
+#define TA_STATUS__IN_BUSY_MASK 0x01000000L
+#define TA_STATUS__FG_BUSY_MASK 0x02000000L
+#define TA_STATUS__LA_BUSY_MASK 0x04000000L
+#define TA_STATUS__FL_BUSY_MASK 0x08000000L
+#define TA_STATUS__TA_BUSY_MASK 0x10000000L
+#define TA_STATUS__FA_BUSY_MASK 0x20000000L
+#define TA_STATUS__AL_BUSY_MASK 0x40000000L
+#define TA_STATUS__BUSY_MASK 0x80000000L
+//TA_SCRATCH
+#define TA_SCRATCH__SCRATCH__SHIFT 0x0
+#define TA_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL
+//TA_DSM_CNTL
+#define TA_DSM_CNTL__TA_FS_DFIFO_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define TA_DSM_CNTL__TA_FS_DFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define TA_DSM_CNTL__TA_FL_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define TA_DSM_CNTL__TA_FL_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define TA_DSM_CNTL__TA_FX_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x9
+#define TA_DSM_CNTL__TA_FX_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0xb
+#define TA_DSM_CNTL__TA_FS_CFIFO_DSM_IRRITATOR_DATA__SHIFT 0xc
+#define TA_DSM_CNTL__TA_FS_CFIFO_ENABLE_SINGLE_WRITE__SHIFT 0xe
+#define TA_DSM_CNTL__TA_FS_AFIFO_LO_DSM_IRRITATOR_DATA__SHIFT 0xf
+#define TA_DSM_CNTL__TA_FS_AFIFO_LO_ENABLE_SINGLE_WRITE__SHIFT 0x11
+#define TA_DSM_CNTL__TA_FS_AFIFO_HI_DSM_IRRITATOR_DATA__SHIFT 0x12
+#define TA_DSM_CNTL__TA_FS_AFIFO_HI_ENABLE_SINGLE_WRITE__SHIFT 0x14
+#define TA_DSM_CNTL__TA_FS_DFIFO_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define TA_DSM_CNTL__TA_FS_DFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define TA_DSM_CNTL__TA_FL_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define TA_DSM_CNTL__TA_FL_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define TA_DSM_CNTL__TA_FX_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00000600L
+#define TA_DSM_CNTL__TA_FX_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000800L
+#define TA_DSM_CNTL__TA_FS_CFIFO_DSM_IRRITATOR_DATA_MASK 0x00003000L
+#define TA_DSM_CNTL__TA_FS_CFIFO_ENABLE_SINGLE_WRITE_MASK 0x00004000L
+#define TA_DSM_CNTL__TA_FS_AFIFO_LO_DSM_IRRITATOR_DATA_MASK 0x00018000L
+#define TA_DSM_CNTL__TA_FS_AFIFO_LO_ENABLE_SINGLE_WRITE_MASK 0x00020000L
+#define TA_DSM_CNTL__TA_FS_AFIFO_HI_DSM_IRRITATOR_DATA_MASK 0x000C0000L
+#define TA_DSM_CNTL__TA_FS_AFIFO_HI_ENABLE_SINGLE_WRITE_MASK 0x00100000L
+//TA_DSM_CNTL2
+#define TA_DSM_CNTL2__TA_FS_DFIFO_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define TA_DSM_CNTL2__TA_FS_DFIFO_SELECT_INJECT_DELAY__SHIFT 0x2
+#define TA_DSM_CNTL2__TA_FL_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define TA_DSM_CNTL2__TA_FL_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x8
+#define TA_DSM_CNTL2__TA_FX_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define TA_DSM_CNTL2__TA_FX_LFIFO_SELECT_INJECT_DELAY__SHIFT 0xb
+#define TA_DSM_CNTL2__TA_FS_CFIFO_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define TA_DSM_CNTL2__TA_FS_CFIFO_SELECT_INJECT_DELAY__SHIFT 0xe
+#define TA_DSM_CNTL2__TA_FS_AFIFO_LO_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define TA_DSM_CNTL2__TA_FS_AFIFO_LO_SELECT_INJECT_DELAY__SHIFT 0x11
+#define TA_DSM_CNTL2__TA_FS_AFIFO_HI_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define TA_DSM_CNTL2__TA_FS_AFIFO_HI_SELECT_INJECT_DELAY__SHIFT 0x14
+#define TA_DSM_CNTL2__TA_INJECT_DELAY__SHIFT 0x1a
+#define TA_DSM_CNTL2__TA_FS_DFIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define TA_DSM_CNTL2__TA_FS_DFIFO_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define TA_DSM_CNTL2__TA_FL_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define TA_DSM_CNTL2__TA_FL_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define TA_DSM_CNTL2__TA_FX_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define TA_DSM_CNTL2__TA_FX_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define TA_DSM_CNTL2__TA_FS_CFIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define TA_DSM_CNTL2__TA_FS_CFIFO_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define TA_DSM_CNTL2__TA_FS_AFIFO_LO_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define TA_DSM_CNTL2__TA_FS_AFIFO_LO_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define TA_DSM_CNTL2__TA_FS_AFIFO_HI_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define TA_DSM_CNTL2__TA_FS_AFIFO_HI_SELECT_INJECT_DELAY_MASK 0x00100000L
+#define TA_DSM_CNTL2__TA_INJECT_DELAY_MASK 0xFC000000L
+//TA_EDC_CNT
+#define TA_EDC_CNT__TA_FS_DFIFO_SEC_COUNT__SHIFT 0x0
+#define TA_EDC_CNT__TA_FS_DFIFO_DED_COUNT__SHIFT 0x2
+#define TA_EDC_CNT__TA_FS_AFIFO_LO_SEC_COUNT__SHIFT 0x4
+#define TA_EDC_CNT__TA_FS_AFIFO_LO_DED_COUNT__SHIFT 0x6
+#define TA_EDC_CNT__TA_FL_LFIFO_SEC_COUNT__SHIFT 0x8
+#define TA_EDC_CNT__TA_FL_LFIFO_DED_COUNT__SHIFT 0xa
+#define TA_EDC_CNT__TA_FX_LFIFO_SEC_COUNT__SHIFT 0xc
+#define TA_EDC_CNT__TA_FX_LFIFO_DED_COUNT__SHIFT 0xe
+#define TA_EDC_CNT__TA_FS_CFIFO_SEC_COUNT__SHIFT 0x10
+#define TA_EDC_CNT__TA_FS_CFIFO_DED_COUNT__SHIFT 0x12
+#define TA_EDC_CNT__TA_FS_AFIFO_HI_SEC_COUNT__SHIFT 0x14
+#define TA_EDC_CNT__TA_FS_AFIFO_HI_DED_COUNT__SHIFT 0x16
+#define TA_EDC_CNT__TA_FS_DFIFO_SEC_COUNT_MASK 0x00000003L
+#define TA_EDC_CNT__TA_FS_DFIFO_DED_COUNT_MASK 0x0000000CL
+#define TA_EDC_CNT__TA_FS_AFIFO_LO_SEC_COUNT_MASK 0x00000030L
+#define TA_EDC_CNT__TA_FS_AFIFO_LO_DED_COUNT_MASK 0x000000C0L
+#define TA_EDC_CNT__TA_FL_LFIFO_SEC_COUNT_MASK 0x00000300L
+#define TA_EDC_CNT__TA_FL_LFIFO_DED_COUNT_MASK 0x00000C00L
+#define TA_EDC_CNT__TA_FX_LFIFO_SEC_COUNT_MASK 0x00003000L
+#define TA_EDC_CNT__TA_FX_LFIFO_DED_COUNT_MASK 0x0000C000L
+#define TA_EDC_CNT__TA_FS_CFIFO_SEC_COUNT_MASK 0x00030000L
+#define TA_EDC_CNT__TA_FS_CFIFO_DED_COUNT_MASK 0x000C0000L
+#define TA_EDC_CNT__TA_FS_AFIFO_HI_SEC_COUNT_MASK 0x00300000L
+#define TA_EDC_CNT__TA_FS_AFIFO_HI_DED_COUNT_MASK 0x00C00000L
+
+
+// addressBlock: gc_utcl2_atcl2dec
+//ATC_L2_CNTL
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7
+#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT 0x8
+#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT 0xb
+#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0xe
+#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0xf
+#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x10
+#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0x13
+#define ATC_L2_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0x14
+#define ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE__SHIFT 0x16
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L
+#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK 0x00000300L
+#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK 0x00001800L
+#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00004000L
+#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00008000L
+#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00070000L
+#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00080000L
+#define ATC_L2_CNTL__FRAG_APT_INTXN_MODE_MASK 0x00300000L
+#define ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE_MASK 0x0FC00000L
+//ATC_L2_CNTL2
+#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0
+#define ATC_L2_CNTL2__NUM_BANKS_LOG2__SHIFT 0x6
+#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x9
+#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xb
+#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0xc
+#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xf
+#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x12
+#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL
+#define ATC_L2_CNTL2__NUM_BANKS_LOG2_MASK 0x000001C0L
+#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x00000600L
+#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000800L
+#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00007000L
+#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00038000L
+#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00FC0000L
+//ATC_L2_CACHE_DATA0
+#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0
+#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1
+#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2
+#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x17
+#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L
+#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L
+#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x007FFFFCL
+#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x07800000L
+//ATC_L2_CACHE_DATA1
+#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0
+#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL
+//ATC_L2_CACHE_DATA2
+#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0
+#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL
+//ATC_L2_CACHE_DATA3
+#define ATC_L2_CACHE_DATA3__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0
+#define ATC_L2_CACHE_DATA3__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL
+//ATC_L2_CNTL3
+#define ATC_L2_CNTL3__L2_SMALLK_FRAGMENT_SIZE__SHIFT 0x0
+#define ATC_L2_CNTL3__L2_MIDK_FRAGMENT_SIZE__SHIFT 0x6
+#define ATC_L2_CNTL3__L2_BIGK_FRAGMENT_SIZE__SHIFT 0xc
+#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x12
+#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x15
+#define ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x1b
+#define ATC_L2_CNTL3__REPEATER_FGCG_OFF__SHIFT 0x1e
+#define ATC_L2_CNTL3__L2_SMALLK_FRAGMENT_SIZE_MASK 0x0000003FL
+#define ATC_L2_CNTL3__L2_MIDK_FRAGMENT_SIZE_MASK 0x00000FC0L
+#define ATC_L2_CNTL3__L2_BIGK_FRAGMENT_SIZE_MASK 0x0003F000L
+#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x001C0000L
+#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x07E00000L
+#define ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x38000000L
+#define ATC_L2_CNTL3__REPEATER_FGCG_OFF_MASK 0x40000000L
+//ATC_L2_STATUS
+#define ATC_L2_STATUS__BUSY__SHIFT 0x0
+#define ATC_L2_STATUS__BUSY_MASK 0x00000001L
+//ATC_L2_STATUS2
+#define ATC_L2_STATUS2__UCE_MEM_ADDR__SHIFT 0x0
+#define ATC_L2_STATUS2__UCE_MEM_INST__SHIFT 0xc
+#define ATC_L2_STATUS2__UCE_SRT_CACHE__SHIFT 0x12
+#define ATC_L2_STATUS2__UCE__SHIFT 0x13
+#define ATC_L2_STATUS2__UCE_MEM_ADDR_MASK 0x00000FFFL
+#define ATC_L2_STATUS2__UCE_MEM_INST_MASK 0x0003F000L
+#define ATC_L2_STATUS2__UCE_SRT_CACHE_MASK 0x00040000L
+#define ATC_L2_STATUS2__UCE_MASK 0x00080000L
+//ATC_L2_MISC_CG
+#define ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6
+#define ATC_L2_MISC_CG__ENABLE__SHIFT 0x12
+#define ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L
+#define ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L
+#define ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L
+//ATC_L2_MEM_POWER_LS
+#define ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
+#define ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
+#define ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL
+#define ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L
+//ATC_L2_CGTT_CLK_CTRL
+#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
+#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
+#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
+#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
+#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
+#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
+//ATC_L2_CACHE_4K_DSM_INDEX
+#define ATC_L2_CACHE_4K_DSM_INDEX__INDEX__SHIFT 0x0
+#define ATC_L2_CACHE_4K_DSM_INDEX__INDEX_MASK 0x000000FFL
+//ATC_L2_CACHE_32K_DSM_INDEX
+#define ATC_L2_CACHE_32K_DSM_INDEX__INDEX__SHIFT 0x0
+#define ATC_L2_CACHE_32K_DSM_INDEX__INDEX_MASK 0x000000FFL
+//ATC_L2_CACHE_2M_DSM_INDEX
+#define ATC_L2_CACHE_2M_DSM_INDEX__INDEX__SHIFT 0x0
+#define ATC_L2_CACHE_2M_DSM_INDEX__INDEX_MASK 0x000000FFL
+//ATC_L2_CACHE_4K_DSM_CNTL
+#define ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY__SHIFT 0x0
+#define ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6
+#define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9
+#define ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb
+#define ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS__SHIFT 0xc
+#define ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT__SHIFT 0xd
+#define ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT__SHIFT 0xf
+#define ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE__SHIFT 0x11
+#define ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY_MASK 0x0000003FL
+#define ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L
+#define ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS_MASK 0x00001000L
+#define ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT_MASK 0x00006000L
+#define ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT_MASK 0x00018000L
+#define ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE_MASK 0x00020000L
+//ATC_L2_CACHE_32K_DSM_CNTL
+#define ATC_L2_CACHE_32K_DSM_CNTL__INJECT_DELAY__SHIFT 0x0
+#define ATC_L2_CACHE_32K_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6
+#define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9
+#define ATC_L2_CACHE_32K_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb
+#define ATC_L2_CACHE_32K_DSM_CNTL__WRITE_COUNTERS__SHIFT 0xc
+#define ATC_L2_CACHE_32K_DSM_CNTL__SEC_COUNT__SHIFT 0xd
+#define ATC_L2_CACHE_32K_DSM_CNTL__DED_COUNT__SHIFT 0xf
+#define ATC_L2_CACHE_32K_DSM_CNTL__TEST_FUE__SHIFT 0x11
+#define ATC_L2_CACHE_32K_DSM_CNTL__INJECT_DELAY_MASK 0x0000003FL
+#define ATC_L2_CACHE_32K_DSM_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define ATC_L2_CACHE_32K_DSM_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L
+#define ATC_L2_CACHE_32K_DSM_CNTL__WRITE_COUNTERS_MASK 0x00001000L
+#define ATC_L2_CACHE_32K_DSM_CNTL__SEC_COUNT_MASK 0x00006000L
+#define ATC_L2_CACHE_32K_DSM_CNTL__DED_COUNT_MASK 0x00018000L
+#define ATC_L2_CACHE_32K_DSM_CNTL__TEST_FUE_MASK 0x00020000L
+//ATC_L2_CACHE_2M_DSM_CNTL
+#define ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY__SHIFT 0x0
+#define ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6
+#define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9
+#define ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb
+#define ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS__SHIFT 0xc
+#define ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT__SHIFT 0xd
+#define ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT__SHIFT 0xf
+#define ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE__SHIFT 0x11
+#define ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY_MASK 0x0000003FL
+#define ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L
+#define ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS_MASK 0x00001000L
+#define ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT_MASK 0x00006000L
+#define ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT_MASK 0x00018000L
+#define ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE_MASK 0x00020000L
+//ATC_L2_CNTL4
+#define ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x0
+#define ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0xa
+#define ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000003FFL
+#define ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000FFC00L
+//ATC_L2_MM_GROUP_RT_CLASSES
+#define ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT 0x0
+#define ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK 0xFFFFFFFFL
+
+
+// addressBlock: gc_utcl2_atcl2pfcntldec
+//ATC_L2_PERFCOUNTER0_CFG
+#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//ATC_L2_PERFCOUNTER1_CFG
+#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//ATC_L2_PERFCOUNTER_RSLT_CNTL
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+
+
+// addressBlock: gc_utcl2_atcl2pfcntrdec
+//ATC_L2_PERFCOUNTER_LO
+#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//ATC_L2_PERFCOUNTER_HI
+#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+
+
+// addressBlock: gc_utcl2_l2tlbdec
+//L2TLB_TLB0_STATUS
+#define L2TLB_TLB0_STATUS__BUSY__SHIFT 0x0
+#define L2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
+#define L2TLB_TLB0_STATUS__BUSY_MASK 0x00000001L
+#define L2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
+//UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR__SHIFT 0x0
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR_MASK 0xFFFFFFFFL
+//UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR__SHIFT 0x0
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID__SHIFT 0x4
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID__SHIFT 0x9
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF__SHIFT 0xd
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA__SHIFT 0xe
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM__SHIFT 0x10
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM__SHIFT 0x11
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM__SHIFT 0x12
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID__SHIFT 0x13
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ__SHIFT 0x1f
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR_MASK 0x0000000FL
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID_MASK 0x000000F0L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID_MASK 0x00001E00L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF_MASK 0x00002000L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA_MASK 0x0000C000L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM_MASK 0x00010000L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM_MASK 0x00020000L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM_MASK 0x00040000L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID_MASK 0x0FF80000L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ_MASK 0x80000000L
+//UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR__SHIFT 0x0
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR_MASK 0xFFFFFFFFL
+//UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR__SHIFT 0x0
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS__SHIFT 0x4
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE__SHIFT 0x7
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP__SHIFT 0xd
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA__SHIFT 0xe
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO__SHIFT 0xf
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ__SHIFT 0x10
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE__SHIFT 0x11
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE__SHIFT 0x12
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG__SHIFT 0x14
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK__SHIFT 0x15
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK__SHIFT 0x1e
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR_MASK 0x0000000FL
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS_MASK 0x00000070L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE_MASK 0x00001F80L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP_MASK 0x00002000L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA_MASK 0x00004000L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO_MASK 0x00008000L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ_MASK 0x00010000L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE_MASK 0x00020000L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE_MASK 0x000C0000L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG_MASK 0x00100000L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK_MASK 0x00600000L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK_MASK 0x40000000L
+
+
+// addressBlock: gc_utcl2_l2tlbpldec
+//L2TLB_PERFCOUNTER0_CFG
+#define L2TLB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define L2TLB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define L2TLB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define L2TLB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define L2TLB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define L2TLB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define L2TLB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define L2TLB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define L2TLB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define L2TLB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//L2TLB_PERFCOUNTER1_CFG
+#define L2TLB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define L2TLB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define L2TLB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define L2TLB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define L2TLB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define L2TLB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define L2TLB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define L2TLB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define L2TLB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define L2TLB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//L2TLB_PERFCOUNTER2_CFG
+#define L2TLB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define L2TLB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define L2TLB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define L2TLB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define L2TLB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define L2TLB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
+#define L2TLB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define L2TLB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
+#define L2TLB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
+#define L2TLB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
+//L2TLB_PERFCOUNTER3_CFG
+#define L2TLB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define L2TLB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define L2TLB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define L2TLB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define L2TLB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define L2TLB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL
+#define L2TLB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define L2TLB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L
+#define L2TLB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L
+#define L2TLB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L
+//L2TLB_PERFCOUNTER_RSLT_CNTL
+#define L2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define L2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define L2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define L2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define L2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define L2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define L2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define L2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+
+
+// addressBlock: gc_utcl2_l2tlbprdec
+//L2TLB_PERFCOUNTER_LO
+#define L2TLB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define L2TLB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//L2TLB_PERFCOUNTER_HI
+#define L2TLB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define L2TLB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define L2TLB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define L2TLB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+
+
+// addressBlock: gc_utcl2_vml2pfdec
+//VM_L2_CNTL
+#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0
+#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1
+#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2
+#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4
+#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8
+#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9
+#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa
+#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
+#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc
+#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf
+#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12
+#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13
+#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15
+#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a
+#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L
+#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L
+#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL
+#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L
+#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L
+#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L
+#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L
+#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L
+#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L
+#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L
+#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L
+#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L
+#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L
+#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L
+//VM_L2_CNTL2
+#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0
+#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1
+#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15
+#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16
+#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17
+#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a
+#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c
+#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L
+#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L
+#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L
+#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L
+#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L
+#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L
+#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L
+//VM_L2_CNTL3
+#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0
+#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6
+#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8
+#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf
+#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14
+#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15
+#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18
+#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c
+#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d
+#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e
+#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f
+#define VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL
+#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L
+#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L
+#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L
+#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L
+#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L
+#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L
+#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L
+#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L
+#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L
+#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L
+//VM_L2_STATUS
+#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0
+#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1
+#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11
+#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12
+#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13
+#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14
+#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15
+#define VM_L2_STATUS__L2_BUSY_MASK 0x00000001L
+#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL
+#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L
+#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L
+#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L
+#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L
+#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L
+//VM_DUMMY_PAGE_FAULT_CNTL
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL
+//VM_DUMMY_PAGE_FAULT_ADDR_LO32
+#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0
+#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
+//VM_DUMMY_PAGE_FAULT_ADDR_HI32
+#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0
+#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL
+//VM_L2_PROTECTION_FAULT_CNTL
+#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1
+#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2
+#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3
+#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
+#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5
+#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6
+#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
+#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8
+#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9
+#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb
+#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd
+#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d
+#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e
+#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f
+#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L
+#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L
+#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L
+#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L
+#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L
+#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L
+#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L
+#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L
+#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L
+#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L
+#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L
+#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L
+#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L
+#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L
+#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L
+//VM_L2_PROTECTION_FAULT_CNTL2
+#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10
+#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11
+#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12
+#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13
+#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL
+#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L
+#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L
+#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L
+#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L
+//VM_L2_PROTECTION_FAULT_MM_CNTL3
+#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL
+//VM_L2_PROTECTION_FAULT_MM_CNTL4
+#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL
+//VM_L2_PROTECTION_FAULT_STATUS
+#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1
+#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4
+#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8
+#define VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9
+#define VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12
+#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13
+#define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14
+#define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18
+#define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19
+#define VM_L2_PROTECTION_FAULT_STATUS__UCE__SHIFT 0x1d
+#define VM_L2_PROTECTION_FAULT_STATUS__FED__SHIFT 0x1e
+#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L
+#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL
+#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L
+#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L
+#define VM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L
+#define VM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L
+#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L
+#define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L
+#define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L
+#define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L
+#define VM_L2_PROTECTION_FAULT_STATUS__UCE_MASK 0x20000000L
+#define VM_L2_PROTECTION_FAULT_STATUS__FED_MASK 0x40000000L
+//VM_L2_PROTECTION_FAULT_ADDR_LO32
+#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
+//VM_L2_PROTECTION_FAULT_ADDR_HI32
+#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL
+//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32
+#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
+//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32
+#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL
+//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32
+#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0
+#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL
+//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32
+#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0
+#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL
+//VM_L2_CNTL4
+#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0
+#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6
+#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7
+#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8
+#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12
+#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c
+#define VM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT 0x1d
+#define VM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT 0x1e
+#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL
+#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L
+#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L
+#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L
+#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L
+#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L
+#define VM_L2_CNTL4__GC_CH_FGCG_OFF_MASK 0x20000000L
+#define VM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK 0x40000000L
+//VM_L2_MM_GROUP_RT_CLASSES
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L
+//VM_L2_BANK_SELECT_RESERVED_CID
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
+#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L
+#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L
+//VM_L2_BANK_SELECT_RESERVED_CID2
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
+#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L
+#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L
+//VM_L2_CACHE_PARITY_CNTL
+#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0
+#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1
+#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc
+#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L
+#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L
+#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L
+//VM_L2_CGTT_CLK_CTRL
+#define VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
+#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
+#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
+#define VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
+#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
+#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
+//VM_L2_CGTT_BUSY_CTRL
+#define VM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0
+#define VM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x4
+#define VM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000000FL
+#define VM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000010L
+//VML2_MEM_ECC_INDEX
+#define VML2_MEM_ECC_INDEX__INDEX__SHIFT 0x0
+#define VML2_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL
+//VML2_WALKER_MEM_ECC_INDEX
+#define VML2_WALKER_MEM_ECC_INDEX__INDEX__SHIFT 0x0
+#define VML2_WALKER_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL
+//UTCL2_MEM_ECC_INDEX
+#define UTCL2_MEM_ECC_INDEX__INDEX__SHIFT 0x0
+#define UTCL2_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL
+//VML2_MEM_ECC_CNTL
+#define VML2_MEM_ECC_CNTL__INJECT_DELAY__SHIFT 0x0
+#define VML2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6
+#define VML2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define VML2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9
+#define VML2_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb
+#define VML2_MEM_ECC_CNTL__SEC_COUNT__SHIFT 0xc
+#define VML2_MEM_ECC_CNTL__DED_COUNT__SHIFT 0xe
+#define VML2_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT 0x10
+#define VML2_MEM_ECC_CNTL__TEST_FUE__SHIFT 0x11
+#define VML2_MEM_ECC_CNTL__INJECT_DELAY_MASK 0x0000003FL
+#define VML2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define VML2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define VML2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define VML2_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L
+#define VML2_MEM_ECC_CNTL__SEC_COUNT_MASK 0x00003000L
+#define VML2_MEM_ECC_CNTL__DED_COUNT_MASK 0x0000C000L
+#define VML2_MEM_ECC_CNTL__WRITE_COUNTERS_MASK 0x00010000L
+#define VML2_MEM_ECC_CNTL__TEST_FUE_MASK 0x00020000L
+//VML2_WALKER_MEM_ECC_CNTL
+#define VML2_WALKER_MEM_ECC_CNTL__INJECT_DELAY__SHIFT 0x0
+#define VML2_WALKER_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6
+#define VML2_WALKER_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define VML2_WALKER_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9
+#define VML2_WALKER_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb
+#define VML2_WALKER_MEM_ECC_CNTL__SEC_COUNT__SHIFT 0xc
+#define VML2_WALKER_MEM_ECC_CNTL__DED_COUNT__SHIFT 0xe
+#define VML2_WALKER_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT 0x10
+#define VML2_WALKER_MEM_ECC_CNTL__TEST_FUE__SHIFT 0x11
+#define VML2_WALKER_MEM_ECC_CNTL__INJECT_DELAY_MASK 0x0000003FL
+#define VML2_WALKER_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define VML2_WALKER_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define VML2_WALKER_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define VML2_WALKER_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L
+#define VML2_WALKER_MEM_ECC_CNTL__SEC_COUNT_MASK 0x00003000L
+#define VML2_WALKER_MEM_ECC_CNTL__DED_COUNT_MASK 0x0000C000L
+#define VML2_WALKER_MEM_ECC_CNTL__WRITE_COUNTERS_MASK 0x00010000L
+#define VML2_WALKER_MEM_ECC_CNTL__TEST_FUE_MASK 0x00020000L
+//UTCL2_MEM_ECC_CNTL
+#define UTCL2_MEM_ECC_CNTL__INJECT_DELAY__SHIFT 0x0
+#define UTCL2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6
+#define UTCL2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define UTCL2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9
+#define UTCL2_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb
+#define UTCL2_MEM_ECC_CNTL__SEC_COUNT__SHIFT 0xc
+#define UTCL2_MEM_ECC_CNTL__DED_COUNT__SHIFT 0xe
+#define UTCL2_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT 0x10
+#define UTCL2_MEM_ECC_CNTL__TEST_FUE__SHIFT 0x11
+#define UTCL2_MEM_ECC_CNTL__INJECT_DELAY_MASK 0x0000003FL
+#define UTCL2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define UTCL2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define UTCL2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define UTCL2_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L
+#define UTCL2_MEM_ECC_CNTL__SEC_COUNT_MASK 0x00003000L
+#define UTCL2_MEM_ECC_CNTL__DED_COUNT_MASK 0x0000C000L
+#define UTCL2_MEM_ECC_CNTL__WRITE_COUNTERS_MASK 0x00010000L
+#define UTCL2_MEM_ECC_CNTL__TEST_FUE_MASK 0x00020000L
+//VML2_MEM_ECC_STATUS
+#define VML2_MEM_ECC_STATUS__UCE__SHIFT 0x0
+#define VML2_MEM_ECC_STATUS__FED__SHIFT 0x1
+#define VML2_MEM_ECC_STATUS__UCE_MASK 0x00000001L
+#define VML2_MEM_ECC_STATUS__FED_MASK 0x00000002L
+//VML2_WALKER_MEM_ECC_STATUS
+#define VML2_WALKER_MEM_ECC_STATUS__UCE__SHIFT 0x0
+#define VML2_WALKER_MEM_ECC_STATUS__FED__SHIFT 0x1
+#define VML2_WALKER_MEM_ECC_STATUS__UCE_MASK 0x00000001L
+#define VML2_WALKER_MEM_ECC_STATUS__FED_MASK 0x00000002L
+//UTCL2_MEM_ECC_STATUS
+#define UTCL2_MEM_ECC_STATUS__UCE__SHIFT 0x0
+#define UTCL2_MEM_ECC_STATUS__FED__SHIFT 0x1
+#define UTCL2_MEM_ECC_STATUS__UCE_MASK 0x00000001L
+#define UTCL2_MEM_ECC_STATUS__FED_MASK 0x00000002L
+//UTCL2_EDC_MODE
+#define UTCL2_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0xf
+#define UTCL2_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10
+#define UTCL2_EDC_MODE__GATE_FUE__SHIFT 0x11
+#define UTCL2_EDC_MODE__DED_MODE__SHIFT 0x14
+#define UTCL2_EDC_MODE__PROP_FED__SHIFT 0x1d
+#define UTCL2_EDC_MODE__BYPASS__SHIFT 0x1f
+#define UTCL2_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x00008000L
+#define UTCL2_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L
+#define UTCL2_EDC_MODE__GATE_FUE_MASK 0x00020000L
+#define UTCL2_EDC_MODE__DED_MODE_MASK 0x00300000L
+#define UTCL2_EDC_MODE__PROP_FED_MASK 0x20000000L
+#define UTCL2_EDC_MODE__BYPASS_MASK 0x80000000L
+//UTCL2_EDC_CONFIG
+#define UTCL2_EDC_CONFIG__DIS_EDC__SHIFT 0x1
+#define UTCL2_EDC_CONFIG__DIS_EDC_MASK 0x00000002L
+
+
+// addressBlock: gc_utcl2_vml2pldec
+//MC_VM_L2_PERFCOUNTER0_CFG
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_L2_PERFCOUNTER1_CFG
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_L2_PERFCOUNTER2_CFG
+#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_L2_PERFCOUNTER3_CFG
+#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_L2_PERFCOUNTER4_CFG
+#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_L2_PERFCOUNTER5_CFG
+#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_L2_PERFCOUNTER6_CFG
+#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_L2_PERFCOUNTER7_CFG
+#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_L2_PERFCOUNTER_RSLT_CNTL
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+
+
+// addressBlock: gc_utcl2_vml2prdec
+//MC_VM_L2_PERFCOUNTER_LO
+#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//MC_VM_L2_PERFCOUNTER_HI
+#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+
+
+// addressBlock: gc_utcl2_vml2vcdec
+//VM_CONTEXT0_CNTL
+#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT1_CNTL
+#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT2_CNTL
+#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT3_CNTL
+#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT4_CNTL
+#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT5_CNTL
+#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT6_CNTL
+#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT7_CNTL
+#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT8_CNTL
+#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT9_CNTL
+#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT10_CNTL
+#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT11_CNTL
+#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT12_CNTL
+#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT13_CNTL
+#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT14_CNTL
+#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT15_CNTL
+#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXTS_DISABLE
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L
+//VM_INVALIDATE_ENG0_SEM
+#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG1_SEM
+#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG2_SEM
+#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG3_SEM
+#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG4_SEM
+#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG5_SEM
+#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG6_SEM
+#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG7_SEM
+#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG8_SEM
+#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG9_SEM
+#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG10_SEM
+#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG11_SEM
+#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG12_SEM
+#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG13_SEM
+#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG14_SEM
+#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG15_SEM
+#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG16_SEM
+#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG17_SEM
+#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG0_REQ
+#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG1_REQ
+#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG2_REQ
+#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG3_REQ
+#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG4_REQ
+#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG5_REQ
+#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG6_REQ
+#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG7_REQ
+#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG8_REQ
+#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG9_REQ
+#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG10_REQ
+#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG11_REQ
+#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG12_REQ
+#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG13_REQ
+#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG14_REQ
+#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG15_REQ
+#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG16_REQ
+#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG17_REQ
+#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG0_ACK
+#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG1_ACK
+#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG2_ACK
+#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG3_ACK
+#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG4_ACK
+#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG5_ACK
+#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG6_ACK
+#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG7_ACK
+#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG8_ACK
+#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG9_ACK
+#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG10_ACK
+#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG11_ACK
+#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG12_ACK
+#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG13_ACK
+#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG14_ACK
+#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG15_ACK
+#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG16_ACK
+#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG17_ACK
+#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG0_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG0_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG1_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG1_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG2_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG2_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG3_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG3_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG4_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG4_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG5_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG5_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG6_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG6_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG7_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG7_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG8_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG8_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG9_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG9_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG10_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG10_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG11_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG11_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG12_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG12_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG13_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG13_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG14_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG14_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG15_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG15_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG16_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG16_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG17_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG17_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+
+
+// addressBlock: gc_utcl2_vmsharedhvdec
+//MC_VM_FB_SIZE_OFFSET_VF0
+#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF1
+#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF2
+#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF3
+#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF4
+#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF5
+#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF6
+#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF7
+#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF8
+#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF9
+#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF10
+#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF11
+#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF12
+#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF13
+#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF14
+#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF15
+#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_MARC_BASE_LO_0
+#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc
+#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L
+//MC_VM_MARC_BASE_LO_1
+#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc
+#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L
+//MC_VM_MARC_BASE_LO_2
+#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc
+#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L
+//MC_VM_MARC_BASE_LO_3
+#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc
+#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L
+//MC_VM_MARC_BASE_HI_0
+#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0
+#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL
+//MC_VM_MARC_BASE_HI_1
+#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0
+#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL
+//MC_VM_MARC_BASE_HI_2
+#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0
+#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL
+//MC_VM_MARC_BASE_HI_3
+#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0
+#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL
+//MC_VM_MARC_RELOC_LO_0
+#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0
+#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1
+#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc
+#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L
+#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L
+#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L
+//MC_VM_MARC_RELOC_LO_1
+#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0
+#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1
+#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc
+#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L
+#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L
+#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L
+//MC_VM_MARC_RELOC_LO_2
+#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0
+#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1
+#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc
+#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L
+#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L
+#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L
+//MC_VM_MARC_RELOC_LO_3
+#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0
+#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1
+#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc
+#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L
+#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L
+#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L
+//MC_VM_MARC_RELOC_HI_0
+#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0
+#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL
+//MC_VM_MARC_RELOC_HI_1
+#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0
+#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL
+//MC_VM_MARC_RELOC_HI_2
+#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0
+#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL
+//MC_VM_MARC_RELOC_HI_3
+#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0
+#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL
+//MC_VM_MARC_LEN_LO_0
+#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc
+#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L
+//MC_VM_MARC_LEN_LO_1
+#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc
+#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L
+//MC_VM_MARC_LEN_LO_2
+#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc
+#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L
+//MC_VM_MARC_LEN_LO_3
+#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc
+#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L
+//MC_VM_MARC_LEN_HI_0
+#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0
+#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL
+//MC_VM_MARC_LEN_HI_1
+#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0
+#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL
+//MC_VM_MARC_LEN_HI_2
+#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0
+#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL
+//MC_VM_MARC_LEN_HI_3
+#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0
+#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL
+//VM_PCIE_ATS_CNTL
+#define VM_PCIE_ATS_CNTL__STU__SHIFT 0x10
+#define VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L
+#define VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_0
+#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_1
+#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_2
+#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_3
+#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_4
+#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_5
+#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_6
+#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_7
+#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_8
+#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_9
+#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_10
+#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_11
+#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_12
+#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_13
+#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_14
+#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_15
+#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L
+//MC_SHARED_ACTIVE_FCN_ID
+#define MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0
+#define MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f
+#define MC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
+#define MC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L
+//MC_VM_XGMI_GPUIOV_ENABLE
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0__SHIFT 0x0
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1__SHIFT 0x1
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2__SHIFT 0x2
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3__SHIFT 0x3
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4__SHIFT 0x4
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5__SHIFT 0x5
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6__SHIFT 0x6
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7__SHIFT 0x7
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8__SHIFT 0x8
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9__SHIFT 0x9
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10__SHIFT 0xa
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11__SHIFT 0xb
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12__SHIFT 0xc
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13__SHIFT 0xd
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14__SHIFT 0xe
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15__SHIFT 0xf
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF__SHIFT 0x1f
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0_MASK 0x00000001L
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1_MASK 0x00000002L
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2_MASK 0x00000004L
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3_MASK 0x00000008L
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4_MASK 0x00000010L
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5_MASK 0x00000020L
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6_MASK 0x00000040L
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7_MASK 0x00000080L
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8_MASK 0x00000100L
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9_MASK 0x00000200L
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10_MASK 0x00000400L
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11_MASK 0x00000800L
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12_MASK 0x00001000L
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13_MASK 0x00002000L
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14_MASK 0x00004000L
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15_MASK 0x00008000L
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF_MASK 0x80000000L
+
+
+// addressBlock: gc_utcl2_vmsharedpfdec
+//MC_VM_FB_OFFSET
+#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0
+#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL
+//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
+#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0
+#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL
+//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
+#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0
+#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL
+//MC_VM_STEERING
+#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0
+#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L
+//MC_SHARED_VIRT_RESET_REQ
+#define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0
+#define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f
+#define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL
+#define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L
+//MC_MEM_POWER_LS
+#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
+#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
+#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL
+#define MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L
+//MC_VM_CACHEABLE_DRAM_ADDRESS_START
+#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0
+#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x00FFFFFFL
+//MC_VM_CACHEABLE_DRAM_ADDRESS_END
+#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0
+#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x00FFFFFFL
+//MC_VM_APT_CNTL
+#define MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0
+#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1
+#define MC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT 0x2
+#define MC_VM_APT_CNTL__PERMS_GRANTED__SHIFT 0x3
+#define MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L
+#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L
+#define MC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK 0x00000004L
+#define MC_VM_APT_CNTL__PERMS_GRANTED_MASK 0x00000008L
+//MC_VM_LOCAL_HBM_ADDRESS_START
+#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0
+#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x00FFFFFFL
+//MC_VM_LOCAL_HBM_ADDRESS_END
+#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0
+#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x00FFFFFFL
+//MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL
+#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0
+#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L
+//UTCL2_CGTT_CLK_CTRL
+#define UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0xc
+#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
+#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
+#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
+#define UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L
+#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
+#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
+#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
+//MC_VM_XGMI_LFB_CNTL
+#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT 0x0
+#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT 0x4
+#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK 0x0000000FL
+#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK 0x000000F0L
+//MC_VM_XGMI_LFB_SIZE
+#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT 0x0
+#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK 0x0001FFFFL
+//MC_VM_CACHEABLE_DRAM_CNTL
+#define MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE__SHIFT 0x0
+#define MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE_MASK 0x00000001L
+//MC_VM_HOST_MAPPING
+#define MC_VM_HOST_MAPPING__MODE__SHIFT 0x0
+#define MC_VM_HOST_MAPPING__MODE_MASK 0x00000001L
+
+
+// addressBlock: gc_utcl2_vmsharedvcdec
+//MC_VM_FB_LOCATION_BASE
+#define MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0
+#define MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL
+//MC_VM_FB_LOCATION_TOP
+#define MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0
+#define MC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL
+//MC_VM_AGP_TOP
+#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0
+#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL
+//MC_VM_AGP_BOT
+#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0
+#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL
+//MC_VM_AGP_BASE
+#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0
+#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL
+//MC_VM_SYSTEM_APERTURE_LOW_ADDR
+#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0
+#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL
+//MC_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0
+#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL
+//MC_VM_MX_L1_TLB_CNTL
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0
+#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3
+#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6
+#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7
+#define MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb
+#define MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT 0xd
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L
+#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L
+#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L
+#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L
+#define MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L
+#define MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK 0x00002000L
+
+
+// addressBlock: gccacind
+//GC_CAC_CNTL
+#define GC_CAC_CNTL__CAC_FORCE_DISABLE__SHIFT 0x0
+#define GC_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x1
+#define GC_CAC_CNTL__CAC_BLOCK_ID__SHIFT 0x11
+#define GC_CAC_CNTL__CAC_SIGNAL_ID__SHIFT 0x17
+#define GC_CAC_CNTL__CAC_FORCE_DISABLE_MASK 0x00000001L
+#define GC_CAC_CNTL__CAC_THRESHOLD_MASK 0x0001FFFEL
+#define GC_CAC_CNTL__CAC_BLOCK_ID_MASK 0x007E0000L
+#define GC_CAC_CNTL__CAC_SIGNAL_ID_MASK 0x7F800000L
+//GC_CAC_OVR_SEL
+#define GC_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT 0x0
+#define GC_CAC_OVR_SEL__CAC_OVR_SEL_MASK 0xFFFFFFFFL
+//GC_CAC_OVR_VAL
+#define GC_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT 0x0
+#define GC_CAC_OVR_VAL__CAC_OVR_VAL_MASK 0xFFFFFFFFL
+//GC_CAC_WEIGHT_BCI_0
+#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_CB_0
+#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_CB_1
+#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_CP_0
+#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_CP_1
+#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2_MASK 0x0000FFFFL
+//GC_CAC_WEIGHT_DB_0
+#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_DB_1
+#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_GDS_0
+#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_GDS_1
+#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_IA_0
+#define GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0_MASK 0x0000FFFFL
+//GC_CAC_WEIGHT_LDS_0
+#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_LDS_1
+#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_PA_0
+#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_PC_0
+#define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0_MASK 0x0000FFFFL
+//GC_CAC_WEIGHT_SC_0
+#define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0_MASK 0x0000FFFFL
+//GC_CAC_WEIGHT_SPI_0
+#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_SPI_1
+#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_SPI_2
+#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4__SHIFT 0x0
+#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5__SHIFT 0x10
+#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_SQ_0
+#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_SQ_1
+#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_SQ_2
+#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4__SHIFT 0x0
+#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5__SHIFT 0x10
+#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_SQ_3
+#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6__SHIFT 0x0
+#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7__SHIFT 0x10
+#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_SQ_4
+#define GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8__SHIFT 0x0
+#define GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8_MASK 0x0000FFFFL
+//GC_CAC_WEIGHT_SX_0
+#define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0_MASK 0x0000FFFFL
+//GC_CAC_WEIGHT_SXRB_0
+#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0_MASK 0x0000FFFFL
+//GC_CAC_WEIGHT_TA_0
+#define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0_MASK 0x0000FFFFL
+//GC_CAC_WEIGHT_TCC_0
+#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_TCC_1
+#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_TCC_2
+#define GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4__SHIFT 0x0
+#define GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4_MASK 0x0000FFFFL
+//GC_CAC_WEIGHT_TCP_0
+#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_TCP_1
+#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_TCP_2
+#define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4__SHIFT 0x0
+#define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4_MASK 0x0000FFFFL
+//GC_CAC_WEIGHT_TD_0
+#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_TD_1
+#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_TD_2
+#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4__SHIFT 0x0
+#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5__SHIFT 0x10
+#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_VGT_0
+#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_VGT_1
+#define GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2_MASK 0x0000FFFFL
+//GC_CAC_WEIGHT_WD_0
+#define GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0_MASK 0x0000FFFFL
+//GC_CAC_WEIGHT_CU_0
+#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0_MASK 0x0000FFFFL
+//GC_CAC_ACC_BCI0
+#define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CB0
+#define GC_CAC_ACC_CB0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CB1
+#define GC_CAC_ACC_CB1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CB2
+#define GC_CAC_ACC_CB2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CB2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CB3
+#define GC_CAC_ACC_CB3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CB3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CP0
+#define GC_CAC_ACC_CP0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CP0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CP1
+#define GC_CAC_ACC_CP1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CP1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CP2
+#define GC_CAC_ACC_CP2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CP2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_DB0
+#define GC_CAC_ACC_DB0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_DB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_DB1
+#define GC_CAC_ACC_DB1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_DB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_DB2
+#define GC_CAC_ACC_DB2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_DB2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_DB3
+#define GC_CAC_ACC_DB3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_DB3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_GDS0
+#define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_GDS1
+#define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_GDS2
+#define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_GDS3
+#define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_IA0
+#define GC_CAC_ACC_IA0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_IA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_LDS0
+#define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_LDS1
+#define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_LDS2
+#define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_LDS3
+#define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_PA0
+#define GC_CAC_ACC_PA0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_PA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_PA1
+#define GC_CAC_ACC_PA1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_PA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_PC0
+#define GC_CAC_ACC_PC0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_PC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SC0
+#define GC_CAC_ACC_SC0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SPI0
+#define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SPI1
+#define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SPI2
+#define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SPI3
+#define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SPI4
+#define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SPI5
+#define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_WEIGHT_UTCL2_ATCL2_0
+#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1_MASK 0xFFFF0000L
+//GC_CAC_ACC_EA0
+#define GC_CAC_ACC_EA0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_EA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_EA1
+#define GC_CAC_ACC_EA1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_EA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_EA2
+#define GC_CAC_ACC_EA2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_EA2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_EA3
+#define GC_CAC_ACC_EA3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_EA3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ATCL20
+#define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_OVRD_EA
+#define GC_CAC_OVRD_EA__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_EA__OVRRD_VALUE__SHIFT 0x6
+#define GC_CAC_OVRD_EA__OVRRD_SELECT_MASK 0x0000003FL
+#define GC_CAC_OVRD_EA__OVRRD_VALUE_MASK 0x00000FC0L
+//GC_CAC_OVRD_UTCL2_ATCL2
+#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE__SHIFT 0x5
+#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT_MASK 0x0000001FL
+#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE_MASK 0x000003E0L
+//GC_CAC_WEIGHT_EA_0
+#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_EA_1
+#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_RMI_0
+#define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0_MASK 0x0000FFFFL
+//GC_CAC_ACC_RMI0
+#define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_OVRD_RMI
+#define GC_CAC_OVRD_RMI__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_RMI__OVRRD_VALUE__SHIFT 0x1
+#define GC_CAC_OVRD_RMI__OVRRD_SELECT_MASK 0x00000001L
+#define GC_CAC_OVRD_RMI__OVRRD_VALUE_MASK 0x00000002L
+//GC_CAC_WEIGHT_UTCL2_ATCL2_1
+#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3_MASK 0xFFFF0000L
+//GC_CAC_ACC_UTCL2_ATCL21
+#define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ATCL22
+#define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ATCL23
+#define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_EA4
+#define GC_CAC_ACC_EA4__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_EA4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_EA5
+#define GC_CAC_ACC_EA5__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_EA5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_WEIGHT_EA_2
+#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4__SHIFT 0x0
+#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5__SHIFT 0x10
+#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5_MASK 0xFFFF0000L
+//GC_CAC_ACC_SQ0_LOWER
+#define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SQ0_UPPER
+#define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
+#define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
+//GC_CAC_ACC_SQ1_LOWER
+#define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SQ1_UPPER
+#define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
+#define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
+//GC_CAC_ACC_SQ2_LOWER
+#define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SQ2_UPPER
+#define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
+#define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
+//GC_CAC_ACC_SQ3_LOWER
+#define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SQ3_UPPER
+#define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
+#define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
+//GC_CAC_ACC_SQ4_LOWER
+#define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SQ4_UPPER
+#define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
+#define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
+//GC_CAC_ACC_SQ5_LOWER
+#define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SQ5_UPPER
+#define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
+#define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
+//GC_CAC_ACC_SQ6_LOWER
+#define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SQ6_UPPER
+#define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
+#define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
+//GC_CAC_ACC_SQ7_LOWER
+#define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SQ7_UPPER
+#define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
+#define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
+//GC_CAC_ACC_SQ8_LOWER
+#define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SQ8_UPPER
+#define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
+#define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
+//GC_CAC_ACC_SX0
+#define GC_CAC_ACC_SX0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SX0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SXRB0
+#define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SXRB1
+#define GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TA0
+#define GC_CAC_ACC_TA0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TCC0
+#define GC_CAC_ACC_TCC0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TCC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TCC1
+#define GC_CAC_ACC_TCC1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TCC1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TCC2
+#define GC_CAC_ACC_TCC2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TCC2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TCC3
+#define GC_CAC_ACC_TCC3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TCC3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TCC4
+#define GC_CAC_ACC_TCC4__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TCC4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TCP0
+#define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TCP1
+#define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TCP2
+#define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TCP3
+#define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TCP4
+#define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TD0
+#define GC_CAC_ACC_TD0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TD0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TD1
+#define GC_CAC_ACC_TD1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TD1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TD2
+#define GC_CAC_ACC_TD2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TD2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TD3
+#define GC_CAC_ACC_TD3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TD3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TD4
+#define GC_CAC_ACC_TD4__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TD4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TD5
+#define GC_CAC_ACC_TD5__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TD5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_VGT0
+#define GC_CAC_ACC_VGT0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_VGT0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_VGT1
+#define GC_CAC_ACC_VGT1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_VGT1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_VGT2
+#define GC_CAC_ACC_VGT2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_VGT2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_WD0
+#define GC_CAC_ACC_WD0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_WD0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CU0
+#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CU1
+#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CU2
+#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CU3
+#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CU4
+#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CU5
+#define GC_CAC_ACC_CU5__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CU6
+#define GC_CAC_ACC_CU6__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CU7
+#define GC_CAC_ACC_CU7__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CU8
+#define GC_CAC_ACC_CU8__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CU9
+#define GC_CAC_ACC_CU9__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CU10
+#define GC_CAC_ACC_CU10__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU10__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CU11
+#define GC_CAC_ACC_CU11__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU11__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CU12
+#define GC_CAC_ACC_CU12__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU12__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CU13
+#define GC_CAC_ACC_CU13__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU13__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_OVRD_BCI
+#define GC_CAC_OVRD_BCI__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_BCI__OVRRD_VALUE__SHIFT 0x2
+#define GC_CAC_OVRD_BCI__OVRRD_SELECT_MASK 0x00000003L
+#define GC_CAC_OVRD_BCI__OVRRD_VALUE_MASK 0x0000000CL
+//GC_CAC_OVRD_CB
+#define GC_CAC_OVRD_CB__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_CB__OVRRD_VALUE__SHIFT 0x4
+#define GC_CAC_OVRD_CB__OVRRD_SELECT_MASK 0x0000000FL
+#define GC_CAC_OVRD_CB__OVRRD_VALUE_MASK 0x000000F0L
+//GC_CAC_OVRD_CP
+#define GC_CAC_OVRD_CP__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_CP__OVRRD_VALUE__SHIFT 0x3
+#define GC_CAC_OVRD_CP__OVRRD_SELECT_MASK 0x00000007L
+#define GC_CAC_OVRD_CP__OVRRD_VALUE_MASK 0x00000038L
+//GC_CAC_OVRD_DB
+#define GC_CAC_OVRD_DB__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_DB__OVRRD_VALUE__SHIFT 0x4
+#define GC_CAC_OVRD_DB__OVRRD_SELECT_MASK 0x0000000FL
+#define GC_CAC_OVRD_DB__OVRRD_VALUE_MASK 0x000000F0L
+//GC_CAC_OVRD_GDS
+#define GC_CAC_OVRD_GDS__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_GDS__OVRRD_VALUE__SHIFT 0x4
+#define GC_CAC_OVRD_GDS__OVRRD_SELECT_MASK 0x0000000FL
+#define GC_CAC_OVRD_GDS__OVRRD_VALUE_MASK 0x000000F0L
+//GC_CAC_OVRD_IA
+#define GC_CAC_OVRD_IA__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_IA__OVRRD_VALUE__SHIFT 0x1
+#define GC_CAC_OVRD_IA__OVRRD_SELECT_MASK 0x00000001L
+#define GC_CAC_OVRD_IA__OVRRD_VALUE_MASK 0x00000002L
+//GC_CAC_OVRD_LDS
+#define GC_CAC_OVRD_LDS__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_LDS__OVRRD_VALUE__SHIFT 0x4
+#define GC_CAC_OVRD_LDS__OVRRD_SELECT_MASK 0x0000000FL
+#define GC_CAC_OVRD_LDS__OVRRD_VALUE_MASK 0x000000F0L
+//GC_CAC_OVRD_PA
+#define GC_CAC_OVRD_PA__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_PA__OVRRD_VALUE__SHIFT 0x2
+#define GC_CAC_OVRD_PA__OVRRD_SELECT_MASK 0x00000003L
+#define GC_CAC_OVRD_PA__OVRRD_VALUE_MASK 0x0000000CL
+//GC_CAC_OVRD_PC
+#define GC_CAC_OVRD_PC__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_PC__OVRRD_VALUE__SHIFT 0x1
+#define GC_CAC_OVRD_PC__OVRRD_SELECT_MASK 0x00000001L
+#define GC_CAC_OVRD_PC__OVRRD_VALUE_MASK 0x00000002L
+//GC_CAC_OVRD_SC
+#define GC_CAC_OVRD_SC__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_SC__OVRRD_VALUE__SHIFT 0x1
+#define GC_CAC_OVRD_SC__OVRRD_SELECT_MASK 0x00000001L
+#define GC_CAC_OVRD_SC__OVRRD_VALUE_MASK 0x00000002L
+//GC_CAC_OVRD_SPI
+#define GC_CAC_OVRD_SPI__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_SPI__OVRRD_VALUE__SHIFT 0x6
+#define GC_CAC_OVRD_SPI__OVRRD_SELECT_MASK 0x0000003FL
+#define GC_CAC_OVRD_SPI__OVRRD_VALUE_MASK 0x00000FC0L
+//GC_CAC_OVRD_CU
+#define GC_CAC_OVRD_CU__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT 0x1
+#define GC_CAC_OVRD_CU__OVRRD_SELECT_MASK 0x00000001L
+#define GC_CAC_OVRD_CU__OVRRD_VALUE_MASK 0x00000002L
+//GC_CAC_OVRD_SQ
+#define GC_CAC_OVRD_SQ__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_SQ__OVRRD_VALUE__SHIFT 0x9
+#define GC_CAC_OVRD_SQ__OVRRD_SELECT_MASK 0x000001FFL
+#define GC_CAC_OVRD_SQ__OVRRD_VALUE_MASK 0x0003FE00L
+//GC_CAC_OVRD_SX
+#define GC_CAC_OVRD_SX__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_SX__OVRRD_VALUE__SHIFT 0x1
+#define GC_CAC_OVRD_SX__OVRRD_SELECT_MASK 0x00000001L
+#define GC_CAC_OVRD_SX__OVRRD_VALUE_MASK 0x00000002L
+//GC_CAC_OVRD_SXRB
+#define GC_CAC_OVRD_SXRB__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_SXRB__OVRRD_VALUE__SHIFT 0x1
+#define GC_CAC_OVRD_SXRB__OVRRD_SELECT_MASK 0x00000001L
+#define GC_CAC_OVRD_SXRB__OVRRD_VALUE_MASK 0x00000002L
+//GC_CAC_OVRD_TA
+#define GC_CAC_OVRD_TA__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_TA__OVRRD_VALUE__SHIFT 0x1
+#define GC_CAC_OVRD_TA__OVRRD_SELECT_MASK 0x00000001L
+#define GC_CAC_OVRD_TA__OVRRD_VALUE_MASK 0x00000002L
+//GC_CAC_OVRD_TCC
+#define GC_CAC_OVRD_TCC__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_TCC__OVRRD_VALUE__SHIFT 0x5
+#define GC_CAC_OVRD_TCC__OVRRD_SELECT_MASK 0x0000001FL
+#define GC_CAC_OVRD_TCC__OVRRD_VALUE_MASK 0x000003E0L
+//GC_CAC_OVRD_TCP
+#define GC_CAC_OVRD_TCP__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_TCP__OVRRD_VALUE__SHIFT 0x5
+#define GC_CAC_OVRD_TCP__OVRRD_SELECT_MASK 0x0000001FL
+#define GC_CAC_OVRD_TCP__OVRRD_VALUE_MASK 0x000003E0L
+//GC_CAC_OVRD_TD
+#define GC_CAC_OVRD_TD__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_TD__OVRRD_VALUE__SHIFT 0x6
+#define GC_CAC_OVRD_TD__OVRRD_SELECT_MASK 0x0000003FL
+#define GC_CAC_OVRD_TD__OVRRD_VALUE_MASK 0x00000FC0L
+//GC_CAC_OVRD_VGT
+#define GC_CAC_OVRD_VGT__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_VGT__OVRRD_VALUE__SHIFT 0x3
+#define GC_CAC_OVRD_VGT__OVRRD_SELECT_MASK 0x00000007L
+#define GC_CAC_OVRD_VGT__OVRRD_VALUE_MASK 0x00000038L
+//GC_CAC_OVRD_WD
+#define GC_CAC_OVRD_WD__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_WD__OVRRD_VALUE__SHIFT 0x1
+#define GC_CAC_OVRD_WD__OVRRD_SELECT_MASK 0x00000001L
+#define GC_CAC_OVRD_WD__OVRRD_VALUE_MASK 0x00000002L
+//GC_CAC_ACC_BCI1
+#define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_WEIGHT_UTCL2_ATCL2_2
+#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4_MASK 0x0000FFFFL
+//GC_CAC_WEIGHT_UTCL2_ROUTER_0
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_UTCL2_ROUTER_1
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_UTCL2_ROUTER_2
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_UTCL2_ROUTER_3
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_UTCL2_ROUTER_4
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_UTCL2_VML2_0
+#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_UTCL2_VML2_1
+#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_UTCL2_VML2_2
+#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4_MASK 0x0000FFFFL
+//GC_CAC_ACC_UTCL2_ATCL24
+#define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ROUTER0
+#define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ROUTER1
+#define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ROUTER2
+#define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ROUTER3
+#define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ROUTER4
+#define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ROUTER5
+#define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ROUTER6
+#define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ROUTER7
+#define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ROUTER8
+#define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ROUTER9
+#define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_VML20
+#define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_VML21
+#define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_VML22
+#define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_VML23
+#define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_VML24
+#define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_OVRD_UTCL2_ROUTER
+#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE__SHIFT 0xa
+#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT_MASK 0x000003FFL
+#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE_MASK 0x000FFC00L
+//GC_CAC_OVRD_UTCL2_VML2
+#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE__SHIFT 0x5
+#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT_MASK 0x0000001FL
+#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE_MASK 0x000003E0L
+//GC_CAC_WEIGHT_UTCL2_WALKER_0
+#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_UTCL2_WALKER_1
+#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_UTCL2_WALKER_2
+#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4_MASK 0x0000FFFFL
+//GC_CAC_ACC_UTCL2_WALKER0
+#define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_WALKER1
+#define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_WALKER2
+#define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_WALKER3
+#define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_WALKER4
+#define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_OVRD_UTCL2_WALKER
+#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE__SHIFT 0x5
+#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT_MASK 0x0000001FL
+#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE_MASK 0x000003E0L
+//EDC_STALL_PATTERN_1_2
+#define EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0
+#define EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10
+#define EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL
+#define EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L
+//EDC_STALL_PATTERN_3_4
+#define EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0
+#define EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10
+#define EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL
+#define EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L
+//EDC_STALL_PATTERN_5_6
+#define EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0
+#define EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10
+#define EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL
+#define EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L
+//EDC_STALL_PATTERN_7
+#define EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0
+#define EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL
+//PCC_STALL_PATTERN_1_2
+#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_1__SHIFT 0x0
+#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_2__SHIFT 0x10
+#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_1_MASK 0x00007FFFL
+#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_2_MASK 0x7FFF0000L
+//PCC_STALL_PATTERN_3_4
+#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_3__SHIFT 0x0
+#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_4__SHIFT 0x10
+#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_3_MASK 0x00007FFFL
+#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_4_MASK 0x7FFF0000L
+//PCC_STALL_PATTERN_5_6
+#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_5__SHIFT 0x0
+#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_6__SHIFT 0x10
+#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_5_MASK 0x00007FFFL
+#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_6_MASK 0x7FFF0000L
+//PCC_STALL_PATTERN_7
+#define PCC_STALL_PATTERN_7__PCC_STALL_PATTERN_7__SHIFT 0x0
+#define PCC_STALL_PATTERN_7__PCC_STALL_PATTERN_7_MASK 0x00007FFFL
+//PCC_THROT_REINCR_FIRST_PATN_1_8
+#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_1__SHIFT 0x0
+#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_2__SHIFT 0x4
+#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_3__SHIFT 0x8
+#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_4__SHIFT 0xc
+#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_5__SHIFT 0x10
+#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_6__SHIFT 0x14
+#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_7__SHIFT 0x18
+#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_8__SHIFT 0x1c
+#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_1_MASK 0x00000007L
+#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_2_MASK 0x00000070L
+#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_3_MASK 0x00000700L
+#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_4_MASK 0x00007000L
+#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_5_MASK 0x00070000L
+#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_6_MASK 0x00700000L
+#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_7_MASK 0x07000000L
+#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_8_MASK 0x70000000L
+//PCC_THROT_REINCR_FIRST_PATN_9_16
+#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_9__SHIFT 0x0
+#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_10__SHIFT 0x4
+#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_11__SHIFT 0x8
+#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_12__SHIFT 0xc
+#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_13__SHIFT 0x10
+#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_14__SHIFT 0x14
+#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_15__SHIFT 0x18
+#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_16__SHIFT 0x1c
+#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_9_MASK 0x00000007L
+#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_10_MASK 0x00000070L
+#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_11_MASK 0x00000700L
+#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_12_MASK 0x00007000L
+#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_13_MASK 0x00070000L
+#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_14_MASK 0x00700000L
+#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_15_MASK 0x07000000L
+#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_16_MASK 0x70000000L
+//PCC_THROT_REINCR_FIRST_PATN_17_20
+#define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_17__SHIFT 0x0
+#define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_18__SHIFT 0x4
+#define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_19__SHIFT 0x8
+#define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_20__SHIFT 0xc
+#define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_17_MASK 0x00000007L
+#define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_18_MASK 0x00000070L
+#define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_19_MASK 0x00000700L
+#define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_20_MASK 0x00007000L
+//PCC_THROT_DECR_FIRST_PATN_1_4
+#define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_1__SHIFT 0x0
+#define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_2__SHIFT 0x8
+#define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_3__SHIFT 0x10
+#define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_4__SHIFT 0x18
+#define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_1_MASK 0x0000001FL
+#define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_2_MASK 0x00001F00L
+#define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_3_MASK 0x001F0000L
+#define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_4_MASK 0x1F000000L
+//PCC_THROT_DECR_FIRST_PATN_5_7
+#define PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_5__SHIFT 0x0
+#define PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_6__SHIFT 0x8
+#define PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_7__SHIFT 0x10
+#define PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_5_MASK 0x0000001FL
+#define PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_6_MASK 0x00001F00L
+#define PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_7_MASK 0x001F0000L
+//PWRBRK_STALL_PATTERN_CTRL
+#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT 0x0
+#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT 0xa
+#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT 0xf
+#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT 0x14
+#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL_MASK 0x000003FFL
+#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP_MASK 0x00007C00L
+#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP_MASK 0x000F8000L
+#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS_MASK 0x00F00000L
+//PWRBRK_STALL_PATTERN_1_2
+#define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_1__SHIFT 0x0
+#define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_2__SHIFT 0x10
+#define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_1_MASK 0x00007FFFL
+#define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_2_MASK 0x7FFF0000L
+//PWRBRK_STALL_PATTERN_3_4
+#define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_3__SHIFT 0x0
+#define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_4__SHIFT 0x10
+#define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_3_MASK 0x00007FFFL
+#define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_4_MASK 0x7FFF0000L
+//PWRBRK_STALL_PATTERN_5_6
+#define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_5__SHIFT 0x0
+#define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_6__SHIFT 0x10
+#define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_5_MASK 0x00007FFFL
+#define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_6_MASK 0x7FFF0000L
+//PWRBRK_STALL_PATTERN_7
+#define PWRBRK_STALL_PATTERN_7__PWRBRK_STALL_PATTERN_7__SHIFT 0x0
+#define PWRBRK_STALL_PATTERN_7__PWRBRK_STALL_PATTERN_7_MASK 0x00007FFFL
+//PCC_PWRBRK_HYSTERESIS_CTRL
+#define PCC_PWRBRK_HYSTERESIS_CTRL__PWRBRK_MAX_HYSTERESIS__SHIFT 0x0
+#define PCC_PWRBRK_HYSTERESIS_CTRL__PWRBRK_MAX_HYSTERESIS_MASK 0x000000FFL
+//FIXED_PATTERN_PERF_COUNTER_CTRL
+#define FIXED_PATTERN_PERF_COUNTER_CTRL__FIXED_PATTERN_PERF_COUNTER_EN__SHIFT 0x0
+#define FIXED_PATTERN_PERF_COUNTER_CTRL__FIXED_PATTERN_LOG_INDEX__SHIFT 0x1
+#define FIXED_PATTERN_PERF_COUNTER_CTRL__FIXED_PATTERN_PERF_COUNTER_EN_MASK 0x00000001L
+#define FIXED_PATTERN_PERF_COUNTER_CTRL__FIXED_PATTERN_LOG_INDEX_MASK 0x0000003EL
+//FIXED_PATTERN_PERF_COUNTER_1
+#define FIXED_PATTERN_PERF_COUNTER_1__PERF_COUNTER__SHIFT 0x0
+#define FIXED_PATTERN_PERF_COUNTER_1__PERF_COUNTER_MASK 0x0001FFFFL
+//FIXED_PATTERN_PERF_COUNTER_2
+#define FIXED_PATTERN_PERF_COUNTER_2__PERF_COUNTER__SHIFT 0x0
+#define FIXED_PATTERN_PERF_COUNTER_2__PERF_COUNTER_MASK 0x0001FFFFL
+//FIXED_PATTERN_PERF_COUNTER_3
+#define FIXED_PATTERN_PERF_COUNTER_3__PERF_COUNTER__SHIFT 0x0
+#define FIXED_PATTERN_PERF_COUNTER_3__PERF_COUNTER_MASK 0x0001FFFFL
+//FIXED_PATTERN_PERF_COUNTER_4
+#define FIXED_PATTERN_PERF_COUNTER_4__PERF_COUNTER__SHIFT 0x0
+#define FIXED_PATTERN_PERF_COUNTER_4__PERF_COUNTER_MASK 0x0001FFFFL
+//FIXED_PATTERN_PERF_COUNTER_5
+#define FIXED_PATTERN_PERF_COUNTER_5__PERF_COUNTER__SHIFT 0x0
+#define FIXED_PATTERN_PERF_COUNTER_5__PERF_COUNTER_MASK 0x0001FFFFL
+//FIXED_PATTERN_PERF_COUNTER_6
+#define FIXED_PATTERN_PERF_COUNTER_6__PERF_COUNTER__SHIFT 0x0
+#define FIXED_PATTERN_PERF_COUNTER_6__PERF_COUNTER_MASK 0x0001FFFFL
+//FIXED_PATTERN_PERF_COUNTER_7
+#define FIXED_PATTERN_PERF_COUNTER_7__PERF_COUNTER__SHIFT 0x0
+#define FIXED_PATTERN_PERF_COUNTER_7__PERF_COUNTER_MASK 0x0001FFFFL
+//FIXED_PATTERN_PERF_COUNTER_8
+#define FIXED_PATTERN_PERF_COUNTER_8__PERF_COUNTER__SHIFT 0x0
+#define FIXED_PATTERN_PERF_COUNTER_8__PERF_COUNTER_MASK 0x0001FFFFL
+//FIXED_PATTERN_PERF_COUNTER_9
+#define FIXED_PATTERN_PERF_COUNTER_9__PERF_COUNTER__SHIFT 0x0
+#define FIXED_PATTERN_PERF_COUNTER_9__PERF_COUNTER_MASK 0x0001FFFFL
+//FIXED_PATTERN_PERF_COUNTER_10
+#define FIXED_PATTERN_PERF_COUNTER_10__PERF_COUNTER__SHIFT 0x0
+#define FIXED_PATTERN_PERF_COUNTER_10__PERF_COUNTER_MASK 0x0001FFFFL
+
+
+
+
+// addressBlock: secacind
+//SE_CAC_CNTL
+#define SE_CAC_CNTL__CAC_FORCE_DISABLE__SHIFT 0x0
+#define SE_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x1
+#define SE_CAC_CNTL__CAC_BLOCK_ID__SHIFT 0x11
+#define SE_CAC_CNTL__CAC_SIGNAL_ID__SHIFT 0x17
+#define SE_CAC_CNTL__CAC_FORCE_DISABLE_MASK 0x00000001L
+#define SE_CAC_CNTL__CAC_THRESHOLD_MASK 0x0001FFFEL
+#define SE_CAC_CNTL__CAC_BLOCK_ID_MASK 0x007E0000L
+#define SE_CAC_CNTL__CAC_SIGNAL_ID_MASK 0x7F800000L
+//SE_CAC_OVR_SEL
+#define SE_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT 0x0
+#define SE_CAC_OVR_SEL__CAC_OVR_SEL_MASK 0xFFFFFFFFL
+//SE_CAC_OVR_VAL
+#define SE_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT 0x0
+#define SE_CAC_OVR_VAL__CAC_OVR_VAL_MASK 0xFFFFFFFFL
+
+
+// addressBlock: sqind
+//SQ_DEBUG_STS_LOCAL
+#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x0
+#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x4
+#define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L
+#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x000003F0L
+//SQ_DEBUG_CTRL_LOCAL
+#define SQ_DEBUG_CTRL_LOCAL__UNUSED__SHIFT 0x0
+#define SQ_DEBUG_CTRL_LOCAL__PERF_SEL_INSTS_VALU_MFMA_NON_WAVE__SHIFT 0x8
+#define SQ_DEBUG_CTRL_LOCAL__PERF_SEL_INSTS_VALU_MFMA_MOPS_NON_WAVE__SHIFT 0x9
+#define SQ_DEBUG_CTRL_LOCAL__UNUSED_MASK 0x000000FFL
+#define SQ_DEBUG_CTRL_LOCAL__PERF_SEL_INSTS_VALU_MFMA_NON_WAVE_MASK 0x00000100L
+#define SQ_DEBUG_CTRL_LOCAL__PERF_SEL_INSTS_VALU_MFMA_MOPS_NON_WAVE_MASK 0x00000200L
+//SQ_WAVE_VALID_AND_IDLE
+#define SQ_WAVE_VALID_AND_IDLE__WAVE_SLOT__SHIFT 0x0
+#define SQ_WAVE_VALID_AND_IDLE__WAVE_SLOT_MASK 0xFFFFFFFFL
+//SQ_WAVE_MODE
+#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0
+#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4
+#define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x8
+#define SQ_WAVE_MODE__IEEE__SHIFT 0x9
+#define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa
+#define SQ_WAVE_MODE__EXCP_EN__SHIFT 0xc
+#define SQ_WAVE_MODE__FP16_OVFL__SHIFT 0x17
+#define SQ_WAVE_MODE__POPS_PACKER0__SHIFT 0x18
+#define SQ_WAVE_MODE__POPS_PACKER1__SHIFT 0x19
+#define SQ_WAVE_MODE__DISABLE_PERF__SHIFT 0x1a
+#define SQ_WAVE_MODE__GPR_IDX_EN__SHIFT 0x1b
+#define SQ_WAVE_MODE__VSKIP__SHIFT 0x1c
+#define SQ_WAVE_MODE__CSP__SHIFT 0x1d
+#define SQ_WAVE_MODE__FP_ROUND_MASK 0x0000000FL
+#define SQ_WAVE_MODE__FP_DENORM_MASK 0x000000F0L
+#define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x00000100L
+#define SQ_WAVE_MODE__IEEE_MASK 0x00000200L
+#define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x00000400L
+#define SQ_WAVE_MODE__EXCP_EN_MASK 0x001FF000L
+#define SQ_WAVE_MODE__FP16_OVFL_MASK 0x00800000L
+#define SQ_WAVE_MODE__POPS_PACKER0_MASK 0x01000000L
+#define SQ_WAVE_MODE__POPS_PACKER1_MASK 0x02000000L
+#define SQ_WAVE_MODE__DISABLE_PERF_MASK 0x04000000L
+#define SQ_WAVE_MODE__GPR_IDX_EN_MASK 0x08000000L
+#define SQ_WAVE_MODE__VSKIP_MASK 0x10000000L
+#define SQ_WAVE_MODE__CSP_MASK 0xE0000000L
+//SQ_WAVE_STATUS
+#define SQ_WAVE_STATUS__SCC__SHIFT 0x0
+#define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x1
+#define SQ_WAVE_STATUS__USER_PRIO__SHIFT 0x3
+#define SQ_WAVE_STATUS__PRIV__SHIFT 0x5
+#define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6
+#define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x7
+#define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x8
+#define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9
+#define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa
+#define SQ_WAVE_STATUS__IN_TG__SHIFT 0xb
+#define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0xc
+#define SQ_WAVE_STATUS__HALT__SHIFT 0xd
+#define SQ_WAVE_STATUS__TRAP__SHIFT 0xe
+#define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT 0xf
+#define SQ_WAVE_STATUS__VALID__SHIFT 0x10
+#define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x11
+#define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x12
+#define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x13
+#define SQ_WAVE_STATUS__ALLOW_REPLAY__SHIFT 0x16
+#define SQ_WAVE_STATUS__FATAL_HALT__SHIFT 0x17
+#define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x1b
+#define SQ_WAVE_STATUS__SCC_MASK 0x00000001L
+#define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x00000006L
+#define SQ_WAVE_STATUS__USER_PRIO_MASK 0x00000018L
+#define SQ_WAVE_STATUS__PRIV_MASK 0x00000020L
+#define SQ_WAVE_STATUS__TRAP_EN_MASK 0x00000040L
+#define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x00000080L
+#define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x00000100L
+#define SQ_WAVE_STATUS__EXECZ_MASK 0x00000200L
+#define SQ_WAVE_STATUS__VCCZ_MASK 0x00000400L
+#define SQ_WAVE_STATUS__IN_TG_MASK 0x00000800L
+#define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x00001000L
+#define SQ_WAVE_STATUS__HALT_MASK 0x00002000L
+#define SQ_WAVE_STATUS__TRAP_MASK 0x00004000L
+#define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK 0x00008000L
+#define SQ_WAVE_STATUS__VALID_MASK 0x00010000L
+#define SQ_WAVE_STATUS__ECC_ERR_MASK 0x00020000L
+#define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x00040000L
+#define SQ_WAVE_STATUS__PERF_EN_MASK 0x00080000L
+#define SQ_WAVE_STATUS__ALLOW_REPLAY_MASK 0x00400000L
+#define SQ_WAVE_STATUS__FATAL_HALT_MASK 0x00800000L
+#define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x08000000L
+//SQ_WAVE_TRAPSTS
+#define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x0
+#define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT 0xa
+#define SQ_WAVE_TRAPSTS__ILLEGAL_INST__SHIFT 0xb
+#define SQ_WAVE_TRAPSTS__EXCP_HI__SHIFT 0xc
+#define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x10
+#define SQ_WAVE_TRAPSTS__XNACK_ERROR__SHIFT 0x1c
+#define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x1d
+#define SQ_WAVE_TRAPSTS__EXCP_MASK 0x000001FFL
+#define SQ_WAVE_TRAPSTS__SAVECTX_MASK 0x00000400L
+#define SQ_WAVE_TRAPSTS__ILLEGAL_INST_MASK 0x00000800L
+#define SQ_WAVE_TRAPSTS__EXCP_HI_MASK 0x00007000L
+#define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x003F0000L
+#define SQ_WAVE_TRAPSTS__XNACK_ERROR_MASK 0x10000000L
+#define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xE0000000L
+//SQ_WAVE_HW_ID
+#define SQ_WAVE_HW_ID__WAVE_ID__SHIFT 0x0
+#define SQ_WAVE_HW_ID__SIMD_ID__SHIFT 0x4
+#define SQ_WAVE_HW_ID__PIPE_ID__SHIFT 0x6
+#define SQ_WAVE_HW_ID__CU_ID__SHIFT 0x8
+#define SQ_WAVE_HW_ID__SH_ID__SHIFT 0xc
+#define SQ_WAVE_HW_ID__SE_ID__SHIFT 0xd
+#define SQ_WAVE_HW_ID__TG_ID__SHIFT 0x10
+#define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x14
+#define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT 0x18
+#define SQ_WAVE_HW_ID__STATE_ID__SHIFT 0x1b
+#define SQ_WAVE_HW_ID__ME_ID__SHIFT 0x1e
+#define SQ_WAVE_HW_ID__WAVE_ID_MASK 0x0000000FL
+#define SQ_WAVE_HW_ID__SIMD_ID_MASK 0x00000030L
+#define SQ_WAVE_HW_ID__PIPE_ID_MASK 0x000000C0L
+#define SQ_WAVE_HW_ID__CU_ID_MASK 0x00000F00L
+#define SQ_WAVE_HW_ID__SH_ID_MASK 0x00001000L
+#define SQ_WAVE_HW_ID__SE_ID_MASK 0x0000E000L
+#define SQ_WAVE_HW_ID__TG_ID_MASK 0x000F0000L
+#define SQ_WAVE_HW_ID__VM_ID_MASK 0x00F00000L
+#define SQ_WAVE_HW_ID__QUEUE_ID_MASK 0x07000000L
+#define SQ_WAVE_HW_ID__STATE_ID_MASK 0x38000000L
+#define SQ_WAVE_HW_ID__ME_ID_MASK 0xC0000000L
+//SQ_WAVE_GPR_ALLOC
+#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0
+#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x6
+#define SQ_WAVE_GPR_ALLOC__ACCV_OFFSET__SHIFT 0xc
+#define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x12
+#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x18
+#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x0000003FL
+#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x00000FC0L
+#define SQ_WAVE_GPR_ALLOC__ACCV_OFFSET_MASK 0x0003F000L
+#define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x00FC0000L
+#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0x0F000000L
+//SQ_WAVE_LDS_ALLOC
+#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0
+#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc
+#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0x000000FFL
+#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x001FF000L
+//SQ_WAVE_IB_STS
+#define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x0
+#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x4
+#define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x8
+#define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0xc
+#define SQ_WAVE_IB_STS__FIRST_REPLAY__SHIFT 0xf
+#define SQ_WAVE_IB_STS__RCNT__SHIFT 0x10
+#define SQ_WAVE_IB_STS__VM_CNT_HI__SHIFT 0x16
+#define SQ_WAVE_IB_STS__VM_CNT_MASK 0x0000000FL
+#define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x00000070L
+#define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0x00000F00L
+#define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x00007000L
+#define SQ_WAVE_IB_STS__FIRST_REPLAY_MASK 0x00008000L
+#define SQ_WAVE_IB_STS__RCNT_MASK 0x001F0000L
+#define SQ_WAVE_IB_STS__VM_CNT_HI_MASK 0x00C00000L
+//SQ_WAVE_PC_LO
+#define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0
+#define SQ_WAVE_PC_LO__PC_LO_MASK 0xFFFFFFFFL
+//SQ_WAVE_PC_HI
+#define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0
+#define SQ_WAVE_PC_HI__PC_HI_MASK 0x0000FFFFL
+//SQ_WAVE_INST_DW0
+#define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x0
+#define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xFFFFFFFFL
+//SQ_WAVE_INST_DW1
+#define SQ_WAVE_INST_DW1__INST_DW1__SHIFT 0x0
+#define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xFFFFFFFFL
+//SQ_WAVE_IB_DBG0
+#define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x0
+#define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT 0x3
+#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT 0x4
+#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT 0x5
+#define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT 0x8
+#define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0xa
+#define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT 0x10
+#define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT 0x18
+#define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT 0x1a
+#define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT 0x1b
+#define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x1d
+#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT 0x1e
+#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI__SHIFT 0x1f
+#define SQ_WAVE_IB_DBG0__IBUF_ST_MASK 0x00000007L
+#define SQ_WAVE_IB_DBG0__PC_INVALID_MASK 0x00000008L
+#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK 0x00000010L
+#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK 0x000000E0L
+#define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK 0x00000300L
+#define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK 0x00000C00L
+#define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK 0x000F0000L
+#define SQ_WAVE_IB_DBG0__ECC_ST_MASK 0x03000000L
+#define SQ_WAVE_IB_DBG0__IS_HYB_MASK 0x04000000L
+#define SQ_WAVE_IB_DBG0__HYB_CNT_MASK 0x18000000L
+#define SQ_WAVE_IB_DBG0__KILL_MASK 0x20000000L
+#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK 0x40000000L
+#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI_MASK 0x80000000L
+//SQ_WAVE_IB_DBG1
+#define SQ_WAVE_IB_DBG1__IXNACK__SHIFT 0x0
+#define SQ_WAVE_IB_DBG1__XNACK__SHIFT 0x1
+#define SQ_WAVE_IB_DBG1__TA_NEED_RESET__SHIFT 0x2
+#define SQ_WAVE_IB_DBG1__XCNT__SHIFT 0x4
+#define SQ_WAVE_IB_DBG1__QCNT__SHIFT 0xb
+#define SQ_WAVE_IB_DBG1__RCNT__SHIFT 0x12
+#define SQ_WAVE_IB_DBG1__MISC_CNT__SHIFT 0x19
+#define SQ_WAVE_IB_DBG1__IXNACK_MASK 0x00000001L
+#define SQ_WAVE_IB_DBG1__XNACK_MASK 0x00000002L
+#define SQ_WAVE_IB_DBG1__TA_NEED_RESET_MASK 0x00000004L
+#define SQ_WAVE_IB_DBG1__XCNT_MASK 0x000001F0L
+#define SQ_WAVE_IB_DBG1__QCNT_MASK 0x0000F800L
+#define SQ_WAVE_IB_DBG1__RCNT_MASK 0x007C0000L
+#define SQ_WAVE_IB_DBG1__MISC_CNT_MASK 0xFE000000L
+//SQ_WAVE_FLUSH_IB
+#define SQ_WAVE_FLUSH_IB__UNUSED__SHIFT 0x0
+#define SQ_WAVE_FLUSH_IB__UNUSED_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP0
+#define SQ_WAVE_TTMP0__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP0__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP1
+#define SQ_WAVE_TTMP1__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP1__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP3
+#define SQ_WAVE_TTMP3__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP3__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP4
+#define SQ_WAVE_TTMP4__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP4__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP5
+#define SQ_WAVE_TTMP5__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP5__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP6
+#define SQ_WAVE_TTMP6__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP6__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP7
+#define SQ_WAVE_TTMP7__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP7__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP8
+#define SQ_WAVE_TTMP8__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP8__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP9
+#define SQ_WAVE_TTMP9__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP9__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP10
+#define SQ_WAVE_TTMP10__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP10__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP11
+#define SQ_WAVE_TTMP11__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP11__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP12
+#define SQ_WAVE_TTMP12__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP12__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP13
+#define SQ_WAVE_TTMP13__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP13__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP14
+#define SQ_WAVE_TTMP14__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP14__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP15
+#define SQ_WAVE_TTMP15__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP15__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_M0
+#define SQ_WAVE_M0__M0__SHIFT 0x0
+#define SQ_WAVE_M0__M0_MASK 0xFFFFFFFFL
+//SQ_WAVE_EXEC_LO
+#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0
+#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xFFFFFFFFL
+//SQ_WAVE_EXEC_HI
+#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0
+#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xFFFFFFFFL
+//SQ_INTERRUPT_WORD_AUTO_CTXID
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE__SHIFT 0x0
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT__SHIFT 0x1
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL__SHIFT 0x2
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP__SHIFT 0x3
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP__SHIFT 0x4
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW__SHIFT 0x5
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW__SHIFT 0x6
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW__SHIFT 0x7
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR__SHIFT 0x8
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID__SHIFT 0x18
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING__SHIFT 0x1a
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_MASK 0x0000001L
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT_MASK 0x0000002L
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL_MASK 0x0000004L
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP_MASK 0x0000008L
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP_MASK 0x0000010L
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW_MASK 0x0000020L
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW_MASK 0x0000040L
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW_MASK 0x0000080L
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR_MASK 0x0000100L
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID_MASK 0x3000000L
+#define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING_MASK 0xC000000L
+//SQ_INTERRUPT_WORD_AUTO_HI
+#define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID__SHIFT 0x8
+#define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING__SHIFT 0xa
+#define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID_MASK 0x300L
+#define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING_MASK 0xC00L
+//SQ_INTERRUPT_WORD_AUTO_LO
+#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE__SHIFT 0x0
+#define SQ_INTERRUPT_WORD_AUTO_LO__WLT__SHIFT 0x1
+#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL__SHIFT 0x2
+#define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP__SHIFT 0x3
+#define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP__SHIFT 0x4
+#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW__SHIFT 0x5
+#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW__SHIFT 0x6
+#define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW__SHIFT 0x7
+#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR__SHIFT 0x8
+#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_MASK 0x001L
+#define SQ_INTERRUPT_WORD_AUTO_LO__WLT_MASK 0x002L
+#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL_MASK 0x004L
+#define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP_MASK 0x008L
+#define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP_MASK 0x010L
+#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW_MASK 0x020L
+#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW_MASK 0x040L
+#define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW_MASK 0x080L
+#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR_MASK 0x100L
+//SQ_INTERRUPT_WORD_CMN_CTXID
+#define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID__SHIFT 0x18
+#define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING__SHIFT 0x1a
+#define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID_MASK 0x3000000L
+#define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING_MASK 0xC000000L
+//SQ_INTERRUPT_WORD_CMN_HI
+#define SQ_INTERRUPT_WORD_CMN_HI__SE_ID__SHIFT 0x8
+#define SQ_INTERRUPT_WORD_CMN_HI__ENCODING__SHIFT 0xa
+#define SQ_INTERRUPT_WORD_CMN_HI__SE_ID_MASK 0x300L
+#define SQ_INTERRUPT_WORD_CMN_HI__ENCODING_MASK 0xC00L
+//SQ_INTERRUPT_WORD_WAVE_CTXID
+#define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA__SHIFT 0x0
+#define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID__SHIFT 0xc
+#define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV__SHIFT 0xd
+#define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID__SHIFT 0xe
+#define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID__SHIFT 0x12
+#define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID__SHIFT 0x14
+#define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID__SHIFT 0x18
+#define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING__SHIFT 0x1a
+#define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA_MASK 0x0000FFFL
+#define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID_MASK 0x0001000L
+#define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV_MASK 0x0002000L
+#define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID_MASK 0x003C000L
+#define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID_MASK 0x00C0000L
+#define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID_MASK 0x0F00000L
+#define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID_MASK 0x3000000L
+#define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING_MASK 0xC000000L
+//SQ_INTERRUPT_WORD_WAVE_HI
+#define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID__SHIFT 0x0
+#define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID__SHIFT 0x4
+#define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID__SHIFT 0x8
+#define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING__SHIFT 0xa
+#define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID_MASK 0x00FL
+#define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID_MASK 0x0F0L
+#define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID_MASK 0x300L
+#define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING_MASK 0xC00L
+//SQ_INTERRUPT_WORD_WAVE_LO
+#define SQ_INTERRUPT_WORD_WAVE_LO__DATA__SHIFT 0x0
+#define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID__SHIFT 0x18
+#define SQ_INTERRUPT_WORD_WAVE_LO__PRIV__SHIFT 0x19
+#define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID__SHIFT 0x1a
+#define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID__SHIFT 0x1e
+#define SQ_INTERRUPT_WORD_WAVE_LO__DATA_MASK 0x00FFFFFFL
+#define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID_MASK 0x01000000L
+#define SQ_INTERRUPT_WORD_WAVE_LO__PRIV_MASK 0x02000000L
+#define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID_MASK 0x3C000000L
+#define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID_MASK 0xC0000000L
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_7_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_7_offset.h
new file mode 100644
index 000000000000..adb7a21e2a10
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_7_offset.h
@@ -0,0 +1,5125 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef _mmhub_1_7_OFFSET_HEADER
+#define _mmhub_1_7_OFFSET_HEADER
+
+
+
+// addressBlock: mmhub_dagb_dagbdec0
+// base address: 0x68000
+#define regDAGB0_RDCLI0 0x0000
+#define regDAGB0_RDCLI0_BASE_IDX 0
+#define regDAGB0_RDCLI1 0x0001
+#define regDAGB0_RDCLI1_BASE_IDX 0
+#define regDAGB0_RDCLI2 0x0002
+#define regDAGB0_RDCLI2_BASE_IDX 0
+#define regDAGB0_RDCLI3 0x0003
+#define regDAGB0_RDCLI3_BASE_IDX 0
+#define regDAGB0_RDCLI4 0x0004
+#define regDAGB0_RDCLI4_BASE_IDX 0
+#define regDAGB0_RDCLI5 0x0005
+#define regDAGB0_RDCLI5_BASE_IDX 0
+#define regDAGB0_RDCLI6 0x0006
+#define regDAGB0_RDCLI6_BASE_IDX 0
+#define regDAGB0_RDCLI7 0x0007
+#define regDAGB0_RDCLI7_BASE_IDX 0
+#define regDAGB0_RDCLI8 0x0008
+#define regDAGB0_RDCLI8_BASE_IDX 0
+#define regDAGB0_RDCLI9 0x0009
+#define regDAGB0_RDCLI9_BASE_IDX 0
+#define regDAGB0_RDCLI10 0x000a
+#define regDAGB0_RDCLI10_BASE_IDX 0
+#define regDAGB0_RDCLI11 0x000b
+#define regDAGB0_RDCLI11_BASE_IDX 0
+#define regDAGB0_RDCLI12 0x000c
+#define regDAGB0_RDCLI12_BASE_IDX 0
+#define regDAGB0_RDCLI13 0x000d
+#define regDAGB0_RDCLI13_BASE_IDX 0
+#define regDAGB0_RDCLI14 0x000e
+#define regDAGB0_RDCLI14_BASE_IDX 0
+#define regDAGB0_RDCLI15 0x000f
+#define regDAGB0_RDCLI15_BASE_IDX 0
+#define regDAGB0_RD_CNTL 0x0010
+#define regDAGB0_RD_CNTL_BASE_IDX 0
+#define regDAGB0_RD_GMI_CNTL 0x0011
+#define regDAGB0_RD_GMI_CNTL_BASE_IDX 0
+#define regDAGB0_RD_ADDR_DAGB 0x0012
+#define regDAGB0_RD_ADDR_DAGB_BASE_IDX 0
+#define regDAGB0_RD_OUTPUT_DAGB_MAX_BURST 0x0013
+#define regDAGB0_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
+#define regDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 0x0014
+#define regDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
+#define regDAGB0_RD_CGTT_CLK_CTRL 0x0015
+#define regDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x0016
+#define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB0_ATCVM_RD_CGTT_CLK_CTRL 0x0017
+#define regDAGB0_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x0018
+#define regDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
+#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x0019
+#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
+#define regDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x001a
+#define regDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
+#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x001b
+#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
+#define regDAGB0_RD_VC0_CNTL 0x001c
+#define regDAGB0_RD_VC0_CNTL_BASE_IDX 0
+#define regDAGB0_RD_VC1_CNTL 0x001d
+#define regDAGB0_RD_VC1_CNTL_BASE_IDX 0
+#define regDAGB0_RD_VC2_CNTL 0x001e
+#define regDAGB0_RD_VC2_CNTL_BASE_IDX 0
+#define regDAGB0_RD_VC3_CNTL 0x001f
+#define regDAGB0_RD_VC3_CNTL_BASE_IDX 0
+#define regDAGB0_RD_VC4_CNTL 0x0020
+#define regDAGB0_RD_VC4_CNTL_BASE_IDX 0
+#define regDAGB0_RD_VC5_CNTL 0x0021
+#define regDAGB0_RD_VC5_CNTL_BASE_IDX 0
+#define regDAGB0_RD_VC6_CNTL 0x0022
+#define regDAGB0_RD_VC6_CNTL_BASE_IDX 0
+#define regDAGB0_RD_VC7_CNTL 0x0023
+#define regDAGB0_RD_VC7_CNTL_BASE_IDX 0
+#define regDAGB0_RD_CNTL_MISC 0x0024
+#define regDAGB0_RD_CNTL_MISC_BASE_IDX 0
+#define regDAGB0_RD_TLB_CREDIT 0x0025
+#define regDAGB0_RD_TLB_CREDIT_BASE_IDX 0
+#define regDAGB0_RD_RDRET_CREDIT_CNTL 0x0026
+#define regDAGB0_RD_RDRET_CREDIT_CNTL_BASE_IDX 0
+#define regDAGB0_RD_RDRET_CREDIT_CNTL2 0x0027
+#define regDAGB0_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0
+#define regDAGB0_RDCLI_ASK_PENDING 0x0028
+#define regDAGB0_RDCLI_ASK_PENDING_BASE_IDX 0
+#define regDAGB0_RDCLI_GO_PENDING 0x0029
+#define regDAGB0_RDCLI_GO_PENDING_BASE_IDX 0
+#define regDAGB0_RDCLI_GBLSEND_PENDING 0x002a
+#define regDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 0
+#define regDAGB0_RDCLI_TLB_PENDING 0x002b
+#define regDAGB0_RDCLI_TLB_PENDING_BASE_IDX 0
+#define regDAGB0_RDCLI_OARB_PENDING 0x002c
+#define regDAGB0_RDCLI_OARB_PENDING_BASE_IDX 0
+#define regDAGB0_RDCLI_OSD_PENDING 0x002d
+#define regDAGB0_RDCLI_OSD_PENDING_BASE_IDX 0
+#define regDAGB0_WRCLI0 0x002e
+#define regDAGB0_WRCLI0_BASE_IDX 0
+#define regDAGB0_WRCLI1 0x002f
+#define regDAGB0_WRCLI1_BASE_IDX 0
+#define regDAGB0_WRCLI2 0x0030
+#define regDAGB0_WRCLI2_BASE_IDX 0
+#define regDAGB0_WRCLI3 0x0031
+#define regDAGB0_WRCLI3_BASE_IDX 0
+#define regDAGB0_WRCLI4 0x0032
+#define regDAGB0_WRCLI4_BASE_IDX 0
+#define regDAGB0_WRCLI5 0x0033
+#define regDAGB0_WRCLI5_BASE_IDX 0
+#define regDAGB0_WRCLI6 0x0034
+#define regDAGB0_WRCLI6_BASE_IDX 0
+#define regDAGB0_WRCLI7 0x0035
+#define regDAGB0_WRCLI7_BASE_IDX 0
+#define regDAGB0_WRCLI8 0x0036
+#define regDAGB0_WRCLI8_BASE_IDX 0
+#define regDAGB0_WRCLI9 0x0037
+#define regDAGB0_WRCLI9_BASE_IDX 0
+#define regDAGB0_WRCLI10 0x0038
+#define regDAGB0_WRCLI10_BASE_IDX 0
+#define regDAGB0_WRCLI11 0x0039
+#define regDAGB0_WRCLI11_BASE_IDX 0
+#define regDAGB0_WRCLI12 0x003a
+#define regDAGB0_WRCLI12_BASE_IDX 0
+#define regDAGB0_WRCLI13 0x003b
+#define regDAGB0_WRCLI13_BASE_IDX 0
+#define regDAGB0_WRCLI14 0x003c
+#define regDAGB0_WRCLI14_BASE_IDX 0
+#define regDAGB0_WRCLI15 0x003d
+#define regDAGB0_WRCLI15_BASE_IDX 0
+#define regDAGB0_WR_CNTL 0x003e
+#define regDAGB0_WR_CNTL_BASE_IDX 0
+#define regDAGB0_WR_GMI_CNTL 0x003f
+#define regDAGB0_WR_GMI_CNTL_BASE_IDX 0
+#define regDAGB0_WR_ADDR_DAGB 0x0040
+#define regDAGB0_WR_ADDR_DAGB_BASE_IDX 0
+#define regDAGB0_WR_OUTPUT_DAGB_MAX_BURST 0x0041
+#define regDAGB0_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
+#define regDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 0x0042
+#define regDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
+#define regDAGB0_WR_CGTT_CLK_CTRL 0x0043
+#define regDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x0044
+#define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB0_ATCVM_WR_CGTT_CLK_CTRL 0x0045
+#define regDAGB0_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x0046
+#define regDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
+#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x0047
+#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
+#define regDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x0048
+#define regDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
+#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x0049
+#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
+#define regDAGB0_WR_DATA_DAGB 0x004a
+#define regDAGB0_WR_DATA_DAGB_BASE_IDX 0
+#define regDAGB0_WR_DATA_DAGB_MAX_BURST0 0x004b
+#define regDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0
+#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x004c
+#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0
+#define regDAGB0_WR_DATA_DAGB_MAX_BURST1 0x004d
+#define regDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0
+#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x004e
+#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0
+#define regDAGB0_WR_VC0_CNTL 0x004f
+#define regDAGB0_WR_VC0_CNTL_BASE_IDX 0
+#define regDAGB0_WR_VC1_CNTL 0x0050
+#define regDAGB0_WR_VC1_CNTL_BASE_IDX 0
+#define regDAGB0_WR_VC2_CNTL 0x0051
+#define regDAGB0_WR_VC2_CNTL_BASE_IDX 0
+#define regDAGB0_WR_VC3_CNTL 0x0052
+#define regDAGB0_WR_VC3_CNTL_BASE_IDX 0
+#define regDAGB0_WR_VC4_CNTL 0x0053
+#define regDAGB0_WR_VC4_CNTL_BASE_IDX 0
+#define regDAGB0_WR_VC5_CNTL 0x0054
+#define regDAGB0_WR_VC5_CNTL_BASE_IDX 0
+#define regDAGB0_WR_VC6_CNTL 0x0055
+#define regDAGB0_WR_VC6_CNTL_BASE_IDX 0
+#define regDAGB0_WR_VC7_CNTL 0x0056
+#define regDAGB0_WR_VC7_CNTL_BASE_IDX 0
+#define regDAGB0_WR_CNTL_MISC 0x0057
+#define regDAGB0_WR_CNTL_MISC_BASE_IDX 0
+#define regDAGB0_WR_TLB_CREDIT 0x0058
+#define regDAGB0_WR_TLB_CREDIT_BASE_IDX 0
+#define regDAGB0_WR_DATA_CREDIT 0x0059
+#define regDAGB0_WR_DATA_CREDIT_BASE_IDX 0
+#define regDAGB0_WR_MISC_CREDIT 0x005a
+#define regDAGB0_WR_MISC_CREDIT_BASE_IDX 0
+#define regDAGB0_WR_OSD_CREDIT_CNTL1 0x005b
+#define regDAGB0_WR_OSD_CREDIT_CNTL1_BASE_IDX 0
+#define regDAGB0_WR_OSD_CREDIT_CNTL2 0x005c
+#define regDAGB0_WR_OSD_CREDIT_CNTL2_BASE_IDX 0
+#define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x005d
+#define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0
+#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE 0x005e
+#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0
+#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x005f
+#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0
+#define regDAGB0_WRCLI_ASK_PENDING 0x0060
+#define regDAGB0_WRCLI_ASK_PENDING_BASE_IDX 0
+#define regDAGB0_WRCLI_GO_PENDING 0x0061
+#define regDAGB0_WRCLI_GO_PENDING_BASE_IDX 0
+#define regDAGB0_WRCLI_GBLSEND_PENDING 0x0062
+#define regDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 0
+#define regDAGB0_WRCLI_TLB_PENDING 0x0063
+#define regDAGB0_WRCLI_TLB_PENDING_BASE_IDX 0
+#define regDAGB0_WRCLI_OARB_PENDING 0x0064
+#define regDAGB0_WRCLI_OARB_PENDING_BASE_IDX 0
+#define regDAGB0_WRCLI_OSD_PENDING 0x0065
+#define regDAGB0_WRCLI_OSD_PENDING_BASE_IDX 0
+#define regDAGB0_WRCLI_DBUS_ASK_PENDING 0x0066
+#define regDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0
+#define regDAGB0_WRCLI_DBUS_GO_PENDING 0x0067
+#define regDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 0
+#define regDAGB0_DAGB_DLY 0x0068
+#define regDAGB0_DAGB_DLY_BASE_IDX 0
+#define regDAGB0_CNTL_MISC 0x0069
+#define regDAGB0_CNTL_MISC_BASE_IDX 0
+#define regDAGB0_CNTL_MISC2 0x006a
+#define regDAGB0_CNTL_MISC2_BASE_IDX 0
+#define regDAGB0_FATAL_ERROR_CNTL 0x006b
+#define regDAGB0_FATAL_ERROR_CNTL_BASE_IDX 0
+#define regDAGB0_FATAL_ERROR_CLEAR 0x006c
+#define regDAGB0_FATAL_ERROR_CLEAR_BASE_IDX 0
+#define regDAGB0_FATAL_ERROR_STATUS0 0x006d
+#define regDAGB0_FATAL_ERROR_STATUS0_BASE_IDX 0
+#define regDAGB0_FATAL_ERROR_STATUS1 0x006e
+#define regDAGB0_FATAL_ERROR_STATUS1_BASE_IDX 0
+#define regDAGB0_FATAL_ERROR_STATUS2 0x006f
+#define regDAGB0_FATAL_ERROR_STATUS2_BASE_IDX 0
+#define regDAGB0_FATAL_ERROR_STATUS3 0x0070
+#define regDAGB0_FATAL_ERROR_STATUS3_BASE_IDX 0
+#define regDAGB0_FIFO_EMPTY 0x0071
+#define regDAGB0_FIFO_EMPTY_BASE_IDX 0
+#define regDAGB0_FIFO_FULL 0x0072
+#define regDAGB0_FIFO_FULL_BASE_IDX 0
+#define regDAGB0_WR_CREDITS_FULL 0x0073
+#define regDAGB0_WR_CREDITS_FULL_BASE_IDX 0
+#define regDAGB0_RD_CREDITS_FULL 0x0074
+#define regDAGB0_RD_CREDITS_FULL_BASE_IDX 0
+#define regDAGB0_PERFCOUNTER_LO 0x0075
+#define regDAGB0_PERFCOUNTER_LO_BASE_IDX 0
+#define regDAGB0_PERFCOUNTER_HI 0x0076
+#define regDAGB0_PERFCOUNTER_HI_BASE_IDX 0
+#define regDAGB0_PERFCOUNTER0_CFG 0x0077
+#define regDAGB0_PERFCOUNTER0_CFG_BASE_IDX 0
+#define regDAGB0_PERFCOUNTER1_CFG 0x0078
+#define regDAGB0_PERFCOUNTER1_CFG_BASE_IDX 0
+#define regDAGB0_PERFCOUNTER2_CFG 0x0079
+#define regDAGB0_PERFCOUNTER2_CFG_BASE_IDX 0
+#define regDAGB0_PERFCOUNTER_RSLT_CNTL 0x007a
+#define regDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+#define regDAGB0_L1TLB_REG_RW 0x007b
+#define regDAGB0_L1TLB_REG_RW_BASE_IDX 0
+#define regDAGB0_RESERVE1 0x007c
+#define regDAGB0_RESERVE1_BASE_IDX 0
+#define regDAGB0_RESERVE2 0x007d
+#define regDAGB0_RESERVE2_BASE_IDX 0
+#define regDAGB0_RESERVE3 0x007e
+#define regDAGB0_RESERVE3_BASE_IDX 0
+#define regDAGB0_RESERVE4 0x007f
+#define regDAGB0_RESERVE4_BASE_IDX 0
+
+
+// addressBlock: mmhub_dagb_dagbdec1
+// base address: 0x68200
+#define regDAGB1_RDCLI0 0x0080
+#define regDAGB1_RDCLI0_BASE_IDX 0
+#define regDAGB1_RDCLI1 0x0081
+#define regDAGB1_RDCLI1_BASE_IDX 0
+#define regDAGB1_RDCLI2 0x0082
+#define regDAGB1_RDCLI2_BASE_IDX 0
+#define regDAGB1_RDCLI3 0x0083
+#define regDAGB1_RDCLI3_BASE_IDX 0
+#define regDAGB1_RDCLI4 0x0084
+#define regDAGB1_RDCLI4_BASE_IDX 0
+#define regDAGB1_RDCLI5 0x0085
+#define regDAGB1_RDCLI5_BASE_IDX 0
+#define regDAGB1_RDCLI6 0x0086
+#define regDAGB1_RDCLI6_BASE_IDX 0
+#define regDAGB1_RDCLI7 0x0087
+#define regDAGB1_RDCLI7_BASE_IDX 0
+#define regDAGB1_RDCLI8 0x0088
+#define regDAGB1_RDCLI8_BASE_IDX 0
+#define regDAGB1_RDCLI9 0x0089
+#define regDAGB1_RDCLI9_BASE_IDX 0
+#define regDAGB1_RDCLI10 0x008a
+#define regDAGB1_RDCLI10_BASE_IDX 0
+#define regDAGB1_RDCLI11 0x008b
+#define regDAGB1_RDCLI11_BASE_IDX 0
+#define regDAGB1_RDCLI12 0x008c
+#define regDAGB1_RDCLI12_BASE_IDX 0
+#define regDAGB1_RDCLI13 0x008d
+#define regDAGB1_RDCLI13_BASE_IDX 0
+#define regDAGB1_RDCLI14 0x008e
+#define regDAGB1_RDCLI14_BASE_IDX 0
+#define regDAGB1_RDCLI15 0x008f
+#define regDAGB1_RDCLI15_BASE_IDX 0
+#define regDAGB1_RD_CNTL 0x0090
+#define regDAGB1_RD_CNTL_BASE_IDX 0
+#define regDAGB1_RD_GMI_CNTL 0x0091
+#define regDAGB1_RD_GMI_CNTL_BASE_IDX 0
+#define regDAGB1_RD_ADDR_DAGB 0x0092
+#define regDAGB1_RD_ADDR_DAGB_BASE_IDX 0
+#define regDAGB1_RD_OUTPUT_DAGB_MAX_BURST 0x0093
+#define regDAGB1_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
+#define regDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER 0x0094
+#define regDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
+#define regDAGB1_RD_CGTT_CLK_CTRL 0x0095
+#define regDAGB1_RD_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB1_L1TLB_RD_CGTT_CLK_CTRL 0x0096
+#define regDAGB1_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB1_ATCVM_RD_CGTT_CLK_CTRL 0x0097
+#define regDAGB1_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB1_RD_ADDR_DAGB_MAX_BURST0 0x0098
+#define regDAGB1_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
+#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0 0x0099
+#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
+#define regDAGB1_RD_ADDR_DAGB_MAX_BURST1 0x009a
+#define regDAGB1_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
+#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1 0x009b
+#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
+#define regDAGB1_RD_VC0_CNTL 0x009c
+#define regDAGB1_RD_VC0_CNTL_BASE_IDX 0
+#define regDAGB1_RD_VC1_CNTL 0x009d
+#define regDAGB1_RD_VC1_CNTL_BASE_IDX 0
+#define regDAGB1_RD_VC2_CNTL 0x009e
+#define regDAGB1_RD_VC2_CNTL_BASE_IDX 0
+#define regDAGB1_RD_VC3_CNTL 0x009f
+#define regDAGB1_RD_VC3_CNTL_BASE_IDX 0
+#define regDAGB1_RD_VC4_CNTL 0x00a0
+#define regDAGB1_RD_VC4_CNTL_BASE_IDX 0
+#define regDAGB1_RD_VC5_CNTL 0x00a1
+#define regDAGB1_RD_VC5_CNTL_BASE_IDX 0
+#define regDAGB1_RD_VC6_CNTL 0x00a2
+#define regDAGB1_RD_VC6_CNTL_BASE_IDX 0
+#define regDAGB1_RD_VC7_CNTL 0x00a3
+#define regDAGB1_RD_VC7_CNTL_BASE_IDX 0
+#define regDAGB1_RD_CNTL_MISC 0x00a4
+#define regDAGB1_RD_CNTL_MISC_BASE_IDX 0
+#define regDAGB1_RD_TLB_CREDIT 0x00a5
+#define regDAGB1_RD_TLB_CREDIT_BASE_IDX 0
+#define regDAGB1_RD_RDRET_CREDIT_CNTL 0x00a6
+#define regDAGB1_RD_RDRET_CREDIT_CNTL_BASE_IDX 0
+#define regDAGB1_RD_RDRET_CREDIT_CNTL2 0x00a7
+#define regDAGB1_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0
+#define regDAGB1_RDCLI_ASK_PENDING 0x00a8
+#define regDAGB1_RDCLI_ASK_PENDING_BASE_IDX 0
+#define regDAGB1_RDCLI_GO_PENDING 0x00a9
+#define regDAGB1_RDCLI_GO_PENDING_BASE_IDX 0
+#define regDAGB1_RDCLI_GBLSEND_PENDING 0x00aa
+#define regDAGB1_RDCLI_GBLSEND_PENDING_BASE_IDX 0
+#define regDAGB1_RDCLI_TLB_PENDING 0x00ab
+#define regDAGB1_RDCLI_TLB_PENDING_BASE_IDX 0
+#define regDAGB1_RDCLI_OARB_PENDING 0x00ac
+#define regDAGB1_RDCLI_OARB_PENDING_BASE_IDX 0
+#define regDAGB1_RDCLI_OSD_PENDING 0x00ad
+#define regDAGB1_RDCLI_OSD_PENDING_BASE_IDX 0
+#define regDAGB1_WRCLI0 0x00ae
+#define regDAGB1_WRCLI0_BASE_IDX 0
+#define regDAGB1_WRCLI1 0x00af
+#define regDAGB1_WRCLI1_BASE_IDX 0
+#define regDAGB1_WRCLI2 0x00b0
+#define regDAGB1_WRCLI2_BASE_IDX 0
+#define regDAGB1_WRCLI3 0x00b1
+#define regDAGB1_WRCLI3_BASE_IDX 0
+#define regDAGB1_WRCLI4 0x00b2
+#define regDAGB1_WRCLI4_BASE_IDX 0
+#define regDAGB1_WRCLI5 0x00b3
+#define regDAGB1_WRCLI5_BASE_IDX 0
+#define regDAGB1_WRCLI6 0x00b4
+#define regDAGB1_WRCLI6_BASE_IDX 0
+#define regDAGB1_WRCLI7 0x00b5
+#define regDAGB1_WRCLI7_BASE_IDX 0
+#define regDAGB1_WRCLI8 0x00b6
+#define regDAGB1_WRCLI8_BASE_IDX 0
+#define regDAGB1_WRCLI9 0x00b7
+#define regDAGB1_WRCLI9_BASE_IDX 0
+#define regDAGB1_WRCLI10 0x00b8
+#define regDAGB1_WRCLI10_BASE_IDX 0
+#define regDAGB1_WRCLI11 0x00b9
+#define regDAGB1_WRCLI11_BASE_IDX 0
+#define regDAGB1_WRCLI12 0x00ba
+#define regDAGB1_WRCLI12_BASE_IDX 0
+#define regDAGB1_WRCLI13 0x00bb
+#define regDAGB1_WRCLI13_BASE_IDX 0
+#define regDAGB1_WRCLI14 0x00bc
+#define regDAGB1_WRCLI14_BASE_IDX 0
+#define regDAGB1_WRCLI15 0x00bd
+#define regDAGB1_WRCLI15_BASE_IDX 0
+#define regDAGB1_WR_CNTL 0x00be
+#define regDAGB1_WR_CNTL_BASE_IDX 0
+#define regDAGB1_WR_GMI_CNTL 0x00bf
+#define regDAGB1_WR_GMI_CNTL_BASE_IDX 0
+#define regDAGB1_WR_ADDR_DAGB 0x00c0
+#define regDAGB1_WR_ADDR_DAGB_BASE_IDX 0
+#define regDAGB1_WR_OUTPUT_DAGB_MAX_BURST 0x00c1
+#define regDAGB1_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
+#define regDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER 0x00c2
+#define regDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
+#define regDAGB1_WR_CGTT_CLK_CTRL 0x00c3
+#define regDAGB1_WR_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB1_L1TLB_WR_CGTT_CLK_CTRL 0x00c4
+#define regDAGB1_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB1_ATCVM_WR_CGTT_CLK_CTRL 0x00c5
+#define regDAGB1_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB1_WR_ADDR_DAGB_MAX_BURST0 0x00c6
+#define regDAGB1_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
+#define regDAGB1_WR_ADDR_DAGB_LAZY_TIMER0 0x00c7
+#define regDAGB1_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
+#define regDAGB1_WR_ADDR_DAGB_MAX_BURST1 0x00c8
+#define regDAGB1_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
+#define regDAGB1_WR_ADDR_DAGB_LAZY_TIMER1 0x00c9
+#define regDAGB1_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
+#define regDAGB1_WR_DATA_DAGB 0x00ca
+#define regDAGB1_WR_DATA_DAGB_BASE_IDX 0
+#define regDAGB1_WR_DATA_DAGB_MAX_BURST0 0x00cb
+#define regDAGB1_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0
+#define regDAGB1_WR_DATA_DAGB_LAZY_TIMER0 0x00cc
+#define regDAGB1_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0
+#define regDAGB1_WR_DATA_DAGB_MAX_BURST1 0x00cd
+#define regDAGB1_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0
+#define regDAGB1_WR_DATA_DAGB_LAZY_TIMER1 0x00ce
+#define regDAGB1_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0
+#define regDAGB1_WR_VC0_CNTL 0x00cf
+#define regDAGB1_WR_VC0_CNTL_BASE_IDX 0
+#define regDAGB1_WR_VC1_CNTL 0x00d0
+#define regDAGB1_WR_VC1_CNTL_BASE_IDX 0
+#define regDAGB1_WR_VC2_CNTL 0x00d1
+#define regDAGB1_WR_VC2_CNTL_BASE_IDX 0
+#define regDAGB1_WR_VC3_CNTL 0x00d2
+#define regDAGB1_WR_VC3_CNTL_BASE_IDX 0
+#define regDAGB1_WR_VC4_CNTL 0x00d3
+#define regDAGB1_WR_VC4_CNTL_BASE_IDX 0
+#define regDAGB1_WR_VC5_CNTL 0x00d4
+#define regDAGB1_WR_VC5_CNTL_BASE_IDX 0
+#define regDAGB1_WR_VC6_CNTL 0x00d5
+#define regDAGB1_WR_VC6_CNTL_BASE_IDX 0
+#define regDAGB1_WR_VC7_CNTL 0x00d6
+#define regDAGB1_WR_VC7_CNTL_BASE_IDX 0
+#define regDAGB1_WR_CNTL_MISC 0x00d7
+#define regDAGB1_WR_CNTL_MISC_BASE_IDX 0
+#define regDAGB1_WR_TLB_CREDIT 0x00d8
+#define regDAGB1_WR_TLB_CREDIT_BASE_IDX 0
+#define regDAGB1_WR_DATA_CREDIT 0x00d9
+#define regDAGB1_WR_DATA_CREDIT_BASE_IDX 0
+#define regDAGB1_WR_MISC_CREDIT 0x00da
+#define regDAGB1_WR_MISC_CREDIT_BASE_IDX 0
+#define regDAGB1_WR_OSD_CREDIT_CNTL1 0x00db
+#define regDAGB1_WR_OSD_CREDIT_CNTL1_BASE_IDX 0
+#define regDAGB1_WR_OSD_CREDIT_CNTL2 0x00dc
+#define regDAGB1_WR_OSD_CREDIT_CNTL2_BASE_IDX 0
+#define regDAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x00dd
+#define regDAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0
+#define regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE 0x00de
+#define regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0
+#define regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x00df
+#define regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0
+#define regDAGB1_WRCLI_ASK_PENDING 0x00e0
+#define regDAGB1_WRCLI_ASK_PENDING_BASE_IDX 0
+#define regDAGB1_WRCLI_GO_PENDING 0x00e1
+#define regDAGB1_WRCLI_GO_PENDING_BASE_IDX 0
+#define regDAGB1_WRCLI_GBLSEND_PENDING 0x00e2
+#define regDAGB1_WRCLI_GBLSEND_PENDING_BASE_IDX 0
+#define regDAGB1_WRCLI_TLB_PENDING 0x00e3
+#define regDAGB1_WRCLI_TLB_PENDING_BASE_IDX 0
+#define regDAGB1_WRCLI_OARB_PENDING 0x00e4
+#define regDAGB1_WRCLI_OARB_PENDING_BASE_IDX 0
+#define regDAGB1_WRCLI_OSD_PENDING 0x00e5
+#define regDAGB1_WRCLI_OSD_PENDING_BASE_IDX 0
+#define regDAGB1_WRCLI_DBUS_ASK_PENDING 0x00e6
+#define regDAGB1_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0
+#define regDAGB1_WRCLI_DBUS_GO_PENDING 0x00e7
+#define regDAGB1_WRCLI_DBUS_GO_PENDING_BASE_IDX 0
+#define regDAGB1_DAGB_DLY 0x00e8
+#define regDAGB1_DAGB_DLY_BASE_IDX 0
+#define regDAGB1_CNTL_MISC 0x00e9
+#define regDAGB1_CNTL_MISC_BASE_IDX 0
+#define regDAGB1_CNTL_MISC2 0x00ea
+#define regDAGB1_CNTL_MISC2_BASE_IDX 0
+#define regDAGB1_FATAL_ERROR_CNTL 0x00eb
+#define regDAGB1_FATAL_ERROR_CNTL_BASE_IDX 0
+#define regDAGB1_FATAL_ERROR_CLEAR 0x00ec
+#define regDAGB1_FATAL_ERROR_CLEAR_BASE_IDX 0
+#define regDAGB1_FATAL_ERROR_STATUS0 0x00ed
+#define regDAGB1_FATAL_ERROR_STATUS0_BASE_IDX 0
+#define regDAGB1_FATAL_ERROR_STATUS1 0x00ee
+#define regDAGB1_FATAL_ERROR_STATUS1_BASE_IDX 0
+#define regDAGB1_FATAL_ERROR_STATUS2 0x00ef
+#define regDAGB1_FATAL_ERROR_STATUS2_BASE_IDX 0
+#define regDAGB1_FATAL_ERROR_STATUS3 0x00f0
+#define regDAGB1_FATAL_ERROR_STATUS3_BASE_IDX 0
+#define regDAGB1_FIFO_EMPTY 0x00f1
+#define regDAGB1_FIFO_EMPTY_BASE_IDX 0
+#define regDAGB1_FIFO_FULL 0x00f2
+#define regDAGB1_FIFO_FULL_BASE_IDX 0
+#define regDAGB1_WR_CREDITS_FULL 0x00f3
+#define regDAGB1_WR_CREDITS_FULL_BASE_IDX 0
+#define regDAGB1_RD_CREDITS_FULL 0x00f4
+#define regDAGB1_RD_CREDITS_FULL_BASE_IDX 0
+#define regDAGB1_PERFCOUNTER_LO 0x00f5
+#define regDAGB1_PERFCOUNTER_LO_BASE_IDX 0
+#define regDAGB1_PERFCOUNTER_HI 0x00f6
+#define regDAGB1_PERFCOUNTER_HI_BASE_IDX 0
+#define regDAGB1_PERFCOUNTER0_CFG 0x00f7
+#define regDAGB1_PERFCOUNTER0_CFG_BASE_IDX 0
+#define regDAGB1_PERFCOUNTER1_CFG 0x00f8
+#define regDAGB1_PERFCOUNTER1_CFG_BASE_IDX 0
+#define regDAGB1_PERFCOUNTER2_CFG 0x00f9
+#define regDAGB1_PERFCOUNTER2_CFG_BASE_IDX 0
+#define regDAGB1_PERFCOUNTER_RSLT_CNTL 0x00fa
+#define regDAGB1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+#define regDAGB1_L1TLB_REG_RW 0x00fb
+#define regDAGB1_L1TLB_REG_RW_BASE_IDX 0
+#define regDAGB1_RESERVE1 0x00fc
+#define regDAGB1_RESERVE1_BASE_IDX 0
+#define regDAGB1_RESERVE2 0x00fd
+#define regDAGB1_RESERVE2_BASE_IDX 0
+#define regDAGB1_RESERVE3 0x00fe
+#define regDAGB1_RESERVE3_BASE_IDX 0
+#define regDAGB1_RESERVE4 0x00ff
+#define regDAGB1_RESERVE4_BASE_IDX 0
+
+
+// addressBlock: mmhub_dagb_dagbdec2
+// base address: 0x68400
+#define regDAGB2_RDCLI0 0x0100
+#define regDAGB2_RDCLI0_BASE_IDX 0
+#define regDAGB2_RDCLI1 0x0101
+#define regDAGB2_RDCLI1_BASE_IDX 0
+#define regDAGB2_RDCLI2 0x0102
+#define regDAGB2_RDCLI2_BASE_IDX 0
+#define regDAGB2_RDCLI3 0x0103
+#define regDAGB2_RDCLI3_BASE_IDX 0
+#define regDAGB2_RDCLI4 0x0104
+#define regDAGB2_RDCLI4_BASE_IDX 0
+#define regDAGB2_RDCLI5 0x0105
+#define regDAGB2_RDCLI5_BASE_IDX 0
+#define regDAGB2_RDCLI6 0x0106
+#define regDAGB2_RDCLI6_BASE_IDX 0
+#define regDAGB2_RDCLI7 0x0107
+#define regDAGB2_RDCLI7_BASE_IDX 0
+#define regDAGB2_RDCLI8 0x0108
+#define regDAGB2_RDCLI8_BASE_IDX 0
+#define regDAGB2_RDCLI9 0x0109
+#define regDAGB2_RDCLI9_BASE_IDX 0
+#define regDAGB2_RDCLI10 0x010a
+#define regDAGB2_RDCLI10_BASE_IDX 0
+#define regDAGB2_RDCLI11 0x010b
+#define regDAGB2_RDCLI11_BASE_IDX 0
+#define regDAGB2_RDCLI12 0x010c
+#define regDAGB2_RDCLI12_BASE_IDX 0
+#define regDAGB2_RDCLI13 0x010d
+#define regDAGB2_RDCLI13_BASE_IDX 0
+#define regDAGB2_RDCLI14 0x010e
+#define regDAGB2_RDCLI14_BASE_IDX 0
+#define regDAGB2_RDCLI15 0x010f
+#define regDAGB2_RDCLI15_BASE_IDX 0
+#define regDAGB2_RD_CNTL 0x0110
+#define regDAGB2_RD_CNTL_BASE_IDX 0
+#define regDAGB2_RD_GMI_CNTL 0x0111
+#define regDAGB2_RD_GMI_CNTL_BASE_IDX 0
+#define regDAGB2_RD_ADDR_DAGB 0x0112
+#define regDAGB2_RD_ADDR_DAGB_BASE_IDX 0
+#define regDAGB2_RD_OUTPUT_DAGB_MAX_BURST 0x0113
+#define regDAGB2_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
+#define regDAGB2_RD_OUTPUT_DAGB_LAZY_TIMER 0x0114
+#define regDAGB2_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
+#define regDAGB2_RD_CGTT_CLK_CTRL 0x0115
+#define regDAGB2_RD_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB2_L1TLB_RD_CGTT_CLK_CTRL 0x0116
+#define regDAGB2_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB2_ATCVM_RD_CGTT_CLK_CTRL 0x0117
+#define regDAGB2_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB2_RD_ADDR_DAGB_MAX_BURST0 0x0118
+#define regDAGB2_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
+#define regDAGB2_RD_ADDR_DAGB_LAZY_TIMER0 0x0119
+#define regDAGB2_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
+#define regDAGB2_RD_ADDR_DAGB_MAX_BURST1 0x011a
+#define regDAGB2_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
+#define regDAGB2_RD_ADDR_DAGB_LAZY_TIMER1 0x011b
+#define regDAGB2_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
+#define regDAGB2_RD_VC0_CNTL 0x011c
+#define regDAGB2_RD_VC0_CNTL_BASE_IDX 0
+#define regDAGB2_RD_VC1_CNTL 0x011d
+#define regDAGB2_RD_VC1_CNTL_BASE_IDX 0
+#define regDAGB2_RD_VC2_CNTL 0x011e
+#define regDAGB2_RD_VC2_CNTL_BASE_IDX 0
+#define regDAGB2_RD_VC3_CNTL 0x011f
+#define regDAGB2_RD_VC3_CNTL_BASE_IDX 0
+#define regDAGB2_RD_VC4_CNTL 0x0120
+#define regDAGB2_RD_VC4_CNTL_BASE_IDX 0
+#define regDAGB2_RD_VC5_CNTL 0x0121
+#define regDAGB2_RD_VC5_CNTL_BASE_IDX 0
+#define regDAGB2_RD_VC6_CNTL 0x0122
+#define regDAGB2_RD_VC6_CNTL_BASE_IDX 0
+#define regDAGB2_RD_VC7_CNTL 0x0123
+#define regDAGB2_RD_VC7_CNTL_BASE_IDX 0
+#define regDAGB2_RD_CNTL_MISC 0x0124
+#define regDAGB2_RD_CNTL_MISC_BASE_IDX 0
+#define regDAGB2_RD_TLB_CREDIT 0x0125
+#define regDAGB2_RD_TLB_CREDIT_BASE_IDX 0
+#define regDAGB2_RD_RDRET_CREDIT_CNTL 0x0126
+#define regDAGB2_RD_RDRET_CREDIT_CNTL_BASE_IDX 0
+#define regDAGB2_RD_RDRET_CREDIT_CNTL2 0x0127
+#define regDAGB2_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0
+#define regDAGB2_RDCLI_ASK_PENDING 0x0128
+#define regDAGB2_RDCLI_ASK_PENDING_BASE_IDX 0
+#define regDAGB2_RDCLI_GO_PENDING 0x0129
+#define regDAGB2_RDCLI_GO_PENDING_BASE_IDX 0
+#define regDAGB2_RDCLI_GBLSEND_PENDING 0x012a
+#define regDAGB2_RDCLI_GBLSEND_PENDING_BASE_IDX 0
+#define regDAGB2_RDCLI_TLB_PENDING 0x012b
+#define regDAGB2_RDCLI_TLB_PENDING_BASE_IDX 0
+#define regDAGB2_RDCLI_OARB_PENDING 0x012c
+#define regDAGB2_RDCLI_OARB_PENDING_BASE_IDX 0
+#define regDAGB2_RDCLI_OSD_PENDING 0x012d
+#define regDAGB2_RDCLI_OSD_PENDING_BASE_IDX 0
+#define regDAGB2_WRCLI0 0x012e
+#define regDAGB2_WRCLI0_BASE_IDX 0
+#define regDAGB2_WRCLI1 0x012f
+#define regDAGB2_WRCLI1_BASE_IDX 0
+#define regDAGB2_WRCLI2 0x0130
+#define regDAGB2_WRCLI2_BASE_IDX 0
+#define regDAGB2_WRCLI3 0x0131
+#define regDAGB2_WRCLI3_BASE_IDX 0
+#define regDAGB2_WRCLI4 0x0132
+#define regDAGB2_WRCLI4_BASE_IDX 0
+#define regDAGB2_WRCLI5 0x0133
+#define regDAGB2_WRCLI5_BASE_IDX 0
+#define regDAGB2_WRCLI6 0x0134
+#define regDAGB2_WRCLI6_BASE_IDX 0
+#define regDAGB2_WRCLI7 0x0135
+#define regDAGB2_WRCLI7_BASE_IDX 0
+#define regDAGB2_WRCLI8 0x0136
+#define regDAGB2_WRCLI8_BASE_IDX 0
+#define regDAGB2_WRCLI9 0x0137
+#define regDAGB2_WRCLI9_BASE_IDX 0
+#define regDAGB2_WRCLI10 0x0138
+#define regDAGB2_WRCLI10_BASE_IDX 0
+#define regDAGB2_WRCLI11 0x0139
+#define regDAGB2_WRCLI11_BASE_IDX 0
+#define regDAGB2_WRCLI12 0x013a
+#define regDAGB2_WRCLI12_BASE_IDX 0
+#define regDAGB2_WRCLI13 0x013b
+#define regDAGB2_WRCLI13_BASE_IDX 0
+#define regDAGB2_WRCLI14 0x013c
+#define regDAGB2_WRCLI14_BASE_IDX 0
+#define regDAGB2_WRCLI15 0x013d
+#define regDAGB2_WRCLI15_BASE_IDX 0
+#define regDAGB2_WR_CNTL 0x013e
+#define regDAGB2_WR_CNTL_BASE_IDX 0
+#define regDAGB2_WR_GMI_CNTL 0x013f
+#define regDAGB2_WR_GMI_CNTL_BASE_IDX 0
+#define regDAGB2_WR_ADDR_DAGB 0x0140
+#define regDAGB2_WR_ADDR_DAGB_BASE_IDX 0
+#define regDAGB2_WR_OUTPUT_DAGB_MAX_BURST 0x0141
+#define regDAGB2_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
+#define regDAGB2_WR_OUTPUT_DAGB_LAZY_TIMER 0x0142
+#define regDAGB2_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
+#define regDAGB2_WR_CGTT_CLK_CTRL 0x0143
+#define regDAGB2_WR_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB2_L1TLB_WR_CGTT_CLK_CTRL 0x0144
+#define regDAGB2_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB2_ATCVM_WR_CGTT_CLK_CTRL 0x0145
+#define regDAGB2_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB2_WR_ADDR_DAGB_MAX_BURST0 0x0146
+#define regDAGB2_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
+#define regDAGB2_WR_ADDR_DAGB_LAZY_TIMER0 0x0147
+#define regDAGB2_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
+#define regDAGB2_WR_ADDR_DAGB_MAX_BURST1 0x0148
+#define regDAGB2_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
+#define regDAGB2_WR_ADDR_DAGB_LAZY_TIMER1 0x0149
+#define regDAGB2_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
+#define regDAGB2_WR_DATA_DAGB 0x014a
+#define regDAGB2_WR_DATA_DAGB_BASE_IDX 0
+#define regDAGB2_WR_DATA_DAGB_MAX_BURST0 0x014b
+#define regDAGB2_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0
+#define regDAGB2_WR_DATA_DAGB_LAZY_TIMER0 0x014c
+#define regDAGB2_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0
+#define regDAGB2_WR_DATA_DAGB_MAX_BURST1 0x014d
+#define regDAGB2_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0
+#define regDAGB2_WR_DATA_DAGB_LAZY_TIMER1 0x014e
+#define regDAGB2_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0
+#define regDAGB2_WR_VC0_CNTL 0x014f
+#define regDAGB2_WR_VC0_CNTL_BASE_IDX 0
+#define regDAGB2_WR_VC1_CNTL 0x0150
+#define regDAGB2_WR_VC1_CNTL_BASE_IDX 0
+#define regDAGB2_WR_VC2_CNTL 0x0151
+#define regDAGB2_WR_VC2_CNTL_BASE_IDX 0
+#define regDAGB2_WR_VC3_CNTL 0x0152
+#define regDAGB2_WR_VC3_CNTL_BASE_IDX 0
+#define regDAGB2_WR_VC4_CNTL 0x0153
+#define regDAGB2_WR_VC4_CNTL_BASE_IDX 0
+#define regDAGB2_WR_VC5_CNTL 0x0154
+#define regDAGB2_WR_VC5_CNTL_BASE_IDX 0
+#define regDAGB2_WR_VC6_CNTL 0x0155
+#define regDAGB2_WR_VC6_CNTL_BASE_IDX 0
+#define regDAGB2_WR_VC7_CNTL 0x0156
+#define regDAGB2_WR_VC7_CNTL_BASE_IDX 0
+#define regDAGB2_WR_CNTL_MISC 0x0157
+#define regDAGB2_WR_CNTL_MISC_BASE_IDX 0
+#define regDAGB2_WR_TLB_CREDIT 0x0158
+#define regDAGB2_WR_TLB_CREDIT_BASE_IDX 0
+#define regDAGB2_WR_DATA_CREDIT 0x0159
+#define regDAGB2_WR_DATA_CREDIT_BASE_IDX 0
+#define regDAGB2_WR_MISC_CREDIT 0x015a
+#define regDAGB2_WR_MISC_CREDIT_BASE_IDX 0
+#define regDAGB2_WR_OSD_CREDIT_CNTL1 0x015b
+#define regDAGB2_WR_OSD_CREDIT_CNTL1_BASE_IDX 0
+#define regDAGB2_WR_OSD_CREDIT_CNTL2 0x015c
+#define regDAGB2_WR_OSD_CREDIT_CNTL2_BASE_IDX 0
+#define regDAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x015d
+#define regDAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0
+#define regDAGB2_WRCLI_GPU_SNOOP_OVERRIDE 0x015e
+#define regDAGB2_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0
+#define regDAGB2_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x015f
+#define regDAGB2_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0
+#define regDAGB2_WRCLI_ASK_PENDING 0x0160
+#define regDAGB2_WRCLI_ASK_PENDING_BASE_IDX 0
+#define regDAGB2_WRCLI_GO_PENDING 0x0161
+#define regDAGB2_WRCLI_GO_PENDING_BASE_IDX 0
+#define regDAGB2_WRCLI_GBLSEND_PENDING 0x0162
+#define regDAGB2_WRCLI_GBLSEND_PENDING_BASE_IDX 0
+#define regDAGB2_WRCLI_TLB_PENDING 0x0163
+#define regDAGB2_WRCLI_TLB_PENDING_BASE_IDX 0
+#define regDAGB2_WRCLI_OARB_PENDING 0x0164
+#define regDAGB2_WRCLI_OARB_PENDING_BASE_IDX 0
+#define regDAGB2_WRCLI_OSD_PENDING 0x0165
+#define regDAGB2_WRCLI_OSD_PENDING_BASE_IDX 0
+#define regDAGB2_WRCLI_DBUS_ASK_PENDING 0x0166
+#define regDAGB2_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0
+#define regDAGB2_WRCLI_DBUS_GO_PENDING 0x0167
+#define regDAGB2_WRCLI_DBUS_GO_PENDING_BASE_IDX 0
+#define regDAGB2_DAGB_DLY 0x0168
+#define regDAGB2_DAGB_DLY_BASE_IDX 0
+#define regDAGB2_CNTL_MISC 0x0169
+#define regDAGB2_CNTL_MISC_BASE_IDX 0
+#define regDAGB2_CNTL_MISC2 0x016a
+#define regDAGB2_CNTL_MISC2_BASE_IDX 0
+#define regDAGB2_FATAL_ERROR_CNTL 0x016b
+#define regDAGB2_FATAL_ERROR_CNTL_BASE_IDX 0
+#define regDAGB2_FATAL_ERROR_CLEAR 0x016c
+#define regDAGB2_FATAL_ERROR_CLEAR_BASE_IDX 0
+#define regDAGB2_FATAL_ERROR_STATUS0 0x016d
+#define regDAGB2_FATAL_ERROR_STATUS0_BASE_IDX 0
+#define regDAGB2_FATAL_ERROR_STATUS1 0x016e
+#define regDAGB2_FATAL_ERROR_STATUS1_BASE_IDX 0
+#define regDAGB2_FATAL_ERROR_STATUS2 0x016f
+#define regDAGB2_FATAL_ERROR_STATUS2_BASE_IDX 0
+#define regDAGB2_FATAL_ERROR_STATUS3 0x0170
+#define regDAGB2_FATAL_ERROR_STATUS3_BASE_IDX 0
+#define regDAGB2_FIFO_EMPTY 0x0171
+#define regDAGB2_FIFO_EMPTY_BASE_IDX 0
+#define regDAGB2_FIFO_FULL 0x0172
+#define regDAGB2_FIFO_FULL_BASE_IDX 0
+#define regDAGB2_WR_CREDITS_FULL 0x0173
+#define regDAGB2_WR_CREDITS_FULL_BASE_IDX 0
+#define regDAGB2_RD_CREDITS_FULL 0x0174
+#define regDAGB2_RD_CREDITS_FULL_BASE_IDX 0
+#define regDAGB2_PERFCOUNTER_LO 0x0175
+#define regDAGB2_PERFCOUNTER_LO_BASE_IDX 0
+#define regDAGB2_PERFCOUNTER_HI 0x0176
+#define regDAGB2_PERFCOUNTER_HI_BASE_IDX 0
+#define regDAGB2_PERFCOUNTER0_CFG 0x0177
+#define regDAGB2_PERFCOUNTER0_CFG_BASE_IDX 0
+#define regDAGB2_PERFCOUNTER1_CFG 0x0178
+#define regDAGB2_PERFCOUNTER1_CFG_BASE_IDX 0
+#define regDAGB2_PERFCOUNTER2_CFG 0x0179
+#define regDAGB2_PERFCOUNTER2_CFG_BASE_IDX 0
+#define regDAGB2_PERFCOUNTER_RSLT_CNTL 0x017a
+#define regDAGB2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+#define regDAGB2_L1TLB_REG_RW 0x017b
+#define regDAGB2_L1TLB_REG_RW_BASE_IDX 0
+#define regDAGB2_RESERVE1 0x017c
+#define regDAGB2_RESERVE1_BASE_IDX 0
+#define regDAGB2_RESERVE2 0x017d
+#define regDAGB2_RESERVE2_BASE_IDX 0
+#define regDAGB2_RESERVE3 0x017e
+#define regDAGB2_RESERVE3_BASE_IDX 0
+#define regDAGB2_RESERVE4 0x017f
+#define regDAGB2_RESERVE4_BASE_IDX 0
+
+
+// addressBlock: mmhub_dagb_dagbdec3
+// base address: 0x68600
+#define regDAGB3_RDCLI0 0x0180
+#define regDAGB3_RDCLI0_BASE_IDX 0
+#define regDAGB3_RDCLI1 0x0181
+#define regDAGB3_RDCLI1_BASE_IDX 0
+#define regDAGB3_RDCLI2 0x0182
+#define regDAGB3_RDCLI2_BASE_IDX 0
+#define regDAGB3_RDCLI3 0x0183
+#define regDAGB3_RDCLI3_BASE_IDX 0
+#define regDAGB3_RDCLI4 0x0184
+#define regDAGB3_RDCLI4_BASE_IDX 0
+#define regDAGB3_RDCLI5 0x0185
+#define regDAGB3_RDCLI5_BASE_IDX 0
+#define regDAGB3_RDCLI6 0x0186
+#define regDAGB3_RDCLI6_BASE_IDX 0
+#define regDAGB3_RDCLI7 0x0187
+#define regDAGB3_RDCLI7_BASE_IDX 0
+#define regDAGB3_RDCLI8 0x0188
+#define regDAGB3_RDCLI8_BASE_IDX 0
+#define regDAGB3_RDCLI9 0x0189
+#define regDAGB3_RDCLI9_BASE_IDX 0
+#define regDAGB3_RDCLI10 0x018a
+#define regDAGB3_RDCLI10_BASE_IDX 0
+#define regDAGB3_RDCLI11 0x018b
+#define regDAGB3_RDCLI11_BASE_IDX 0
+#define regDAGB3_RDCLI12 0x018c
+#define regDAGB3_RDCLI12_BASE_IDX 0
+#define regDAGB3_RDCLI13 0x018d
+#define regDAGB3_RDCLI13_BASE_IDX 0
+#define regDAGB3_RDCLI14 0x018e
+#define regDAGB3_RDCLI14_BASE_IDX 0
+#define regDAGB3_RDCLI15 0x018f
+#define regDAGB3_RDCLI15_BASE_IDX 0
+#define regDAGB3_RD_CNTL 0x0190
+#define regDAGB3_RD_CNTL_BASE_IDX 0
+#define regDAGB3_RD_GMI_CNTL 0x0191
+#define regDAGB3_RD_GMI_CNTL_BASE_IDX 0
+#define regDAGB3_RD_ADDR_DAGB 0x0192
+#define regDAGB3_RD_ADDR_DAGB_BASE_IDX 0
+#define regDAGB3_RD_OUTPUT_DAGB_MAX_BURST 0x0193
+#define regDAGB3_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
+#define regDAGB3_RD_OUTPUT_DAGB_LAZY_TIMER 0x0194
+#define regDAGB3_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
+#define regDAGB3_RD_CGTT_CLK_CTRL 0x0195
+#define regDAGB3_RD_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB3_L1TLB_RD_CGTT_CLK_CTRL 0x0196
+#define regDAGB3_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB3_ATCVM_RD_CGTT_CLK_CTRL 0x0197
+#define regDAGB3_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB3_RD_ADDR_DAGB_MAX_BURST0 0x0198
+#define regDAGB3_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
+#define regDAGB3_RD_ADDR_DAGB_LAZY_TIMER0 0x0199
+#define regDAGB3_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
+#define regDAGB3_RD_ADDR_DAGB_MAX_BURST1 0x019a
+#define regDAGB3_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
+#define regDAGB3_RD_ADDR_DAGB_LAZY_TIMER1 0x019b
+#define regDAGB3_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
+#define regDAGB3_RD_VC0_CNTL 0x019c
+#define regDAGB3_RD_VC0_CNTL_BASE_IDX 0
+#define regDAGB3_RD_VC1_CNTL 0x019d
+#define regDAGB3_RD_VC1_CNTL_BASE_IDX 0
+#define regDAGB3_RD_VC2_CNTL 0x019e
+#define regDAGB3_RD_VC2_CNTL_BASE_IDX 0
+#define regDAGB3_RD_VC3_CNTL 0x019f
+#define regDAGB3_RD_VC3_CNTL_BASE_IDX 0
+#define regDAGB3_RD_VC4_CNTL 0x01a0
+#define regDAGB3_RD_VC4_CNTL_BASE_IDX 0
+#define regDAGB3_RD_VC5_CNTL 0x01a1
+#define regDAGB3_RD_VC5_CNTL_BASE_IDX 0
+#define regDAGB3_RD_VC6_CNTL 0x01a2
+#define regDAGB3_RD_VC6_CNTL_BASE_IDX 0
+#define regDAGB3_RD_VC7_CNTL 0x01a3
+#define regDAGB3_RD_VC7_CNTL_BASE_IDX 0
+#define regDAGB3_RD_CNTL_MISC 0x01a4
+#define regDAGB3_RD_CNTL_MISC_BASE_IDX 0
+#define regDAGB3_RD_TLB_CREDIT 0x01a5
+#define regDAGB3_RD_TLB_CREDIT_BASE_IDX 0
+#define regDAGB3_RD_RDRET_CREDIT_CNTL 0x01a6
+#define regDAGB3_RD_RDRET_CREDIT_CNTL_BASE_IDX 0
+#define regDAGB3_RD_RDRET_CREDIT_CNTL2 0x01a7
+#define regDAGB3_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0
+#define regDAGB3_RDCLI_ASK_PENDING 0x01a8
+#define regDAGB3_RDCLI_ASK_PENDING_BASE_IDX 0
+#define regDAGB3_RDCLI_GO_PENDING 0x01a9
+#define regDAGB3_RDCLI_GO_PENDING_BASE_IDX 0
+#define regDAGB3_RDCLI_GBLSEND_PENDING 0x01aa
+#define regDAGB3_RDCLI_GBLSEND_PENDING_BASE_IDX 0
+#define regDAGB3_RDCLI_TLB_PENDING 0x01ab
+#define regDAGB3_RDCLI_TLB_PENDING_BASE_IDX 0
+#define regDAGB3_RDCLI_OARB_PENDING 0x01ac
+#define regDAGB3_RDCLI_OARB_PENDING_BASE_IDX 0
+#define regDAGB3_RDCLI_OSD_PENDING 0x01ad
+#define regDAGB3_RDCLI_OSD_PENDING_BASE_IDX 0
+#define regDAGB3_WRCLI0 0x01ae
+#define regDAGB3_WRCLI0_BASE_IDX 0
+#define regDAGB3_WRCLI1 0x01af
+#define regDAGB3_WRCLI1_BASE_IDX 0
+#define regDAGB3_WRCLI2 0x01b0
+#define regDAGB3_WRCLI2_BASE_IDX 0
+#define regDAGB3_WRCLI3 0x01b1
+#define regDAGB3_WRCLI3_BASE_IDX 0
+#define regDAGB3_WRCLI4 0x01b2
+#define regDAGB3_WRCLI4_BASE_IDX 0
+#define regDAGB3_WRCLI5 0x01b3
+#define regDAGB3_WRCLI5_BASE_IDX 0
+#define regDAGB3_WRCLI6 0x01b4
+#define regDAGB3_WRCLI6_BASE_IDX 0
+#define regDAGB3_WRCLI7 0x01b5
+#define regDAGB3_WRCLI7_BASE_IDX 0
+#define regDAGB3_WRCLI8 0x01b6
+#define regDAGB3_WRCLI8_BASE_IDX 0
+#define regDAGB3_WRCLI9 0x01b7
+#define regDAGB3_WRCLI9_BASE_IDX 0
+#define regDAGB3_WRCLI10 0x01b8
+#define regDAGB3_WRCLI10_BASE_IDX 0
+#define regDAGB3_WRCLI11 0x01b9
+#define regDAGB3_WRCLI11_BASE_IDX 0
+#define regDAGB3_WRCLI12 0x01ba
+#define regDAGB3_WRCLI12_BASE_IDX 0
+#define regDAGB3_WRCLI13 0x01bb
+#define regDAGB3_WRCLI13_BASE_IDX 0
+#define regDAGB3_WRCLI14 0x01bc
+#define regDAGB3_WRCLI14_BASE_IDX 0
+#define regDAGB3_WRCLI15 0x01bd
+#define regDAGB3_WRCLI15_BASE_IDX 0
+#define regDAGB3_WR_CNTL 0x01be
+#define regDAGB3_WR_CNTL_BASE_IDX 0
+#define regDAGB3_WR_GMI_CNTL 0x01bf
+#define regDAGB3_WR_GMI_CNTL_BASE_IDX 0
+#define regDAGB3_WR_ADDR_DAGB 0x01c0
+#define regDAGB3_WR_ADDR_DAGB_BASE_IDX 0
+#define regDAGB3_WR_OUTPUT_DAGB_MAX_BURST 0x01c1
+#define regDAGB3_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
+#define regDAGB3_WR_OUTPUT_DAGB_LAZY_TIMER 0x01c2
+#define regDAGB3_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
+#define regDAGB3_WR_CGTT_CLK_CTRL 0x01c3
+#define regDAGB3_WR_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB3_L1TLB_WR_CGTT_CLK_CTRL 0x01c4
+#define regDAGB3_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB3_ATCVM_WR_CGTT_CLK_CTRL 0x01c5
+#define regDAGB3_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB3_WR_ADDR_DAGB_MAX_BURST0 0x01c6
+#define regDAGB3_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
+#define regDAGB3_WR_ADDR_DAGB_LAZY_TIMER0 0x01c7
+#define regDAGB3_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
+#define regDAGB3_WR_ADDR_DAGB_MAX_BURST1 0x01c8
+#define regDAGB3_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
+#define regDAGB3_WR_ADDR_DAGB_LAZY_TIMER1 0x01c9
+#define regDAGB3_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
+#define regDAGB3_WR_DATA_DAGB 0x01ca
+#define regDAGB3_WR_DATA_DAGB_BASE_IDX 0
+#define regDAGB3_WR_DATA_DAGB_MAX_BURST0 0x01cb
+#define regDAGB3_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0
+#define regDAGB3_WR_DATA_DAGB_LAZY_TIMER0 0x01cc
+#define regDAGB3_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0
+#define regDAGB3_WR_DATA_DAGB_MAX_BURST1 0x01cd
+#define regDAGB3_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0
+#define regDAGB3_WR_DATA_DAGB_LAZY_TIMER1 0x01ce
+#define regDAGB3_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0
+#define regDAGB3_WR_VC0_CNTL 0x01cf
+#define regDAGB3_WR_VC0_CNTL_BASE_IDX 0
+#define regDAGB3_WR_VC1_CNTL 0x01d0
+#define regDAGB3_WR_VC1_CNTL_BASE_IDX 0
+#define regDAGB3_WR_VC2_CNTL 0x01d1
+#define regDAGB3_WR_VC2_CNTL_BASE_IDX 0
+#define regDAGB3_WR_VC3_CNTL 0x01d2
+#define regDAGB3_WR_VC3_CNTL_BASE_IDX 0
+#define regDAGB3_WR_VC4_CNTL 0x01d3
+#define regDAGB3_WR_VC4_CNTL_BASE_IDX 0
+#define regDAGB3_WR_VC5_CNTL 0x01d4
+#define regDAGB3_WR_VC5_CNTL_BASE_IDX 0
+#define regDAGB3_WR_VC6_CNTL 0x01d5
+#define regDAGB3_WR_VC6_CNTL_BASE_IDX 0
+#define regDAGB3_WR_VC7_CNTL 0x01d6
+#define regDAGB3_WR_VC7_CNTL_BASE_IDX 0
+#define regDAGB3_WR_CNTL_MISC 0x01d7
+#define regDAGB3_WR_CNTL_MISC_BASE_IDX 0
+#define regDAGB3_WR_TLB_CREDIT 0x01d8
+#define regDAGB3_WR_TLB_CREDIT_BASE_IDX 0
+#define regDAGB3_WR_DATA_CREDIT 0x01d9
+#define regDAGB3_WR_DATA_CREDIT_BASE_IDX 0
+#define regDAGB3_WR_MISC_CREDIT 0x01da
+#define regDAGB3_WR_MISC_CREDIT_BASE_IDX 0
+#define regDAGB3_WR_OSD_CREDIT_CNTL1 0x01db
+#define regDAGB3_WR_OSD_CREDIT_CNTL1_BASE_IDX 0
+#define regDAGB3_WR_OSD_CREDIT_CNTL2 0x01dc
+#define regDAGB3_WR_OSD_CREDIT_CNTL2_BASE_IDX 0
+#define regDAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x01dd
+#define regDAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0
+#define regDAGB3_WRCLI_GPU_SNOOP_OVERRIDE 0x01de
+#define regDAGB3_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0
+#define regDAGB3_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x01df
+#define regDAGB3_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0
+#define regDAGB3_WRCLI_ASK_PENDING 0x01e0
+#define regDAGB3_WRCLI_ASK_PENDING_BASE_IDX 0
+#define regDAGB3_WRCLI_GO_PENDING 0x01e1
+#define regDAGB3_WRCLI_GO_PENDING_BASE_IDX 0
+#define regDAGB3_WRCLI_GBLSEND_PENDING 0x01e2
+#define regDAGB3_WRCLI_GBLSEND_PENDING_BASE_IDX 0
+#define regDAGB3_WRCLI_TLB_PENDING 0x01e3
+#define regDAGB3_WRCLI_TLB_PENDING_BASE_IDX 0
+#define regDAGB3_WRCLI_OARB_PENDING 0x01e4
+#define regDAGB3_WRCLI_OARB_PENDING_BASE_IDX 0
+#define regDAGB3_WRCLI_OSD_PENDING 0x01e5
+#define regDAGB3_WRCLI_OSD_PENDING_BASE_IDX 0
+#define regDAGB3_WRCLI_DBUS_ASK_PENDING 0x01e6
+#define regDAGB3_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0
+#define regDAGB3_WRCLI_DBUS_GO_PENDING 0x01e7
+#define regDAGB3_WRCLI_DBUS_GO_PENDING_BASE_IDX 0
+#define regDAGB3_DAGB_DLY 0x01e8
+#define regDAGB3_DAGB_DLY_BASE_IDX 0
+#define regDAGB3_CNTL_MISC 0x01e9
+#define regDAGB3_CNTL_MISC_BASE_IDX 0
+#define regDAGB3_CNTL_MISC2 0x01ea
+#define regDAGB3_CNTL_MISC2_BASE_IDX 0
+#define regDAGB3_FATAL_ERROR_CNTL 0x01eb
+#define regDAGB3_FATAL_ERROR_CNTL_BASE_IDX 0
+#define regDAGB3_FATAL_ERROR_CLEAR 0x01ec
+#define regDAGB3_FATAL_ERROR_CLEAR_BASE_IDX 0
+#define regDAGB3_FATAL_ERROR_STATUS0 0x01ed
+#define regDAGB3_FATAL_ERROR_STATUS0_BASE_IDX 0
+#define regDAGB3_FATAL_ERROR_STATUS1 0x01ee
+#define regDAGB3_FATAL_ERROR_STATUS1_BASE_IDX 0
+#define regDAGB3_FATAL_ERROR_STATUS2 0x01ef
+#define regDAGB3_FATAL_ERROR_STATUS2_BASE_IDX 0
+#define regDAGB3_FATAL_ERROR_STATUS3 0x01f0
+#define regDAGB3_FATAL_ERROR_STATUS3_BASE_IDX 0
+#define regDAGB3_FIFO_EMPTY 0x01f1
+#define regDAGB3_FIFO_EMPTY_BASE_IDX 0
+#define regDAGB3_FIFO_FULL 0x01f2
+#define regDAGB3_FIFO_FULL_BASE_IDX 0
+#define regDAGB3_WR_CREDITS_FULL 0x01f3
+#define regDAGB3_WR_CREDITS_FULL_BASE_IDX 0
+#define regDAGB3_RD_CREDITS_FULL 0x01f4
+#define regDAGB3_RD_CREDITS_FULL_BASE_IDX 0
+#define regDAGB3_PERFCOUNTER_LO 0x01f5
+#define regDAGB3_PERFCOUNTER_LO_BASE_IDX 0
+#define regDAGB3_PERFCOUNTER_HI 0x01f6
+#define regDAGB3_PERFCOUNTER_HI_BASE_IDX 0
+#define regDAGB3_PERFCOUNTER0_CFG 0x01f7
+#define regDAGB3_PERFCOUNTER0_CFG_BASE_IDX 0
+#define regDAGB3_PERFCOUNTER1_CFG 0x01f8
+#define regDAGB3_PERFCOUNTER1_CFG_BASE_IDX 0
+#define regDAGB3_PERFCOUNTER2_CFG 0x01f9
+#define regDAGB3_PERFCOUNTER2_CFG_BASE_IDX 0
+#define regDAGB3_PERFCOUNTER_RSLT_CNTL 0x01fa
+#define regDAGB3_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+#define regDAGB3_L1TLB_REG_RW 0x01fb
+#define regDAGB3_L1TLB_REG_RW_BASE_IDX 0
+#define regDAGB3_RESERVE1 0x01fc
+#define regDAGB3_RESERVE1_BASE_IDX 0
+#define regDAGB3_RESERVE2 0x01fd
+#define regDAGB3_RESERVE2_BASE_IDX 0
+#define regDAGB3_RESERVE3 0x01fe
+#define regDAGB3_RESERVE3_BASE_IDX 0
+#define regDAGB3_RESERVE4 0x01ff
+#define regDAGB3_RESERVE4_BASE_IDX 0
+
+
+// addressBlock: mmhub_dagb_dagbdec4
+// base address: 0x68800
+#define regDAGB4_RDCLI0 0x0200
+#define regDAGB4_RDCLI0_BASE_IDX 0
+#define regDAGB4_RDCLI1 0x0201
+#define regDAGB4_RDCLI1_BASE_IDX 0
+#define regDAGB4_RDCLI2 0x0202
+#define regDAGB4_RDCLI2_BASE_IDX 0
+#define regDAGB4_RDCLI3 0x0203
+#define regDAGB4_RDCLI3_BASE_IDX 0
+#define regDAGB4_RDCLI4 0x0204
+#define regDAGB4_RDCLI4_BASE_IDX 0
+#define regDAGB4_RDCLI5 0x0205
+#define regDAGB4_RDCLI5_BASE_IDX 0
+#define regDAGB4_RDCLI6 0x0206
+#define regDAGB4_RDCLI6_BASE_IDX 0
+#define regDAGB4_RDCLI7 0x0207
+#define regDAGB4_RDCLI7_BASE_IDX 0
+#define regDAGB4_RDCLI8 0x0208
+#define regDAGB4_RDCLI8_BASE_IDX 0
+#define regDAGB4_RDCLI9 0x0209
+#define regDAGB4_RDCLI9_BASE_IDX 0
+#define regDAGB4_RDCLI10 0x020a
+#define regDAGB4_RDCLI10_BASE_IDX 0
+#define regDAGB4_RDCLI11 0x020b
+#define regDAGB4_RDCLI11_BASE_IDX 0
+#define regDAGB4_RDCLI12 0x020c
+#define regDAGB4_RDCLI12_BASE_IDX 0
+#define regDAGB4_RDCLI13 0x020d
+#define regDAGB4_RDCLI13_BASE_IDX 0
+#define regDAGB4_RDCLI14 0x020e
+#define regDAGB4_RDCLI14_BASE_IDX 0
+#define regDAGB4_RDCLI15 0x020f
+#define regDAGB4_RDCLI15_BASE_IDX 0
+#define regDAGB4_RD_CNTL 0x0210
+#define regDAGB4_RD_CNTL_BASE_IDX 0
+#define regDAGB4_RD_GMI_CNTL 0x0211
+#define regDAGB4_RD_GMI_CNTL_BASE_IDX 0
+#define regDAGB4_RD_ADDR_DAGB 0x0212
+#define regDAGB4_RD_ADDR_DAGB_BASE_IDX 0
+#define regDAGB4_RD_OUTPUT_DAGB_MAX_BURST 0x0213
+#define regDAGB4_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
+#define regDAGB4_RD_OUTPUT_DAGB_LAZY_TIMER 0x0214
+#define regDAGB4_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
+#define regDAGB4_RD_CGTT_CLK_CTRL 0x0215
+#define regDAGB4_RD_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB4_L1TLB_RD_CGTT_CLK_CTRL 0x0216
+#define regDAGB4_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB4_ATCVM_RD_CGTT_CLK_CTRL 0x0217
+#define regDAGB4_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB4_RD_ADDR_DAGB_MAX_BURST0 0x0218
+#define regDAGB4_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
+#define regDAGB4_RD_ADDR_DAGB_LAZY_TIMER0 0x0219
+#define regDAGB4_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
+#define regDAGB4_RD_ADDR_DAGB_MAX_BURST1 0x021a
+#define regDAGB4_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
+#define regDAGB4_RD_ADDR_DAGB_LAZY_TIMER1 0x021b
+#define regDAGB4_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
+#define regDAGB4_RD_VC0_CNTL 0x021c
+#define regDAGB4_RD_VC0_CNTL_BASE_IDX 0
+#define regDAGB4_RD_VC1_CNTL 0x021d
+#define regDAGB4_RD_VC1_CNTL_BASE_IDX 0
+#define regDAGB4_RD_VC2_CNTL 0x021e
+#define regDAGB4_RD_VC2_CNTL_BASE_IDX 0
+#define regDAGB4_RD_VC3_CNTL 0x021f
+#define regDAGB4_RD_VC3_CNTL_BASE_IDX 0
+#define regDAGB4_RD_VC4_CNTL 0x0220
+#define regDAGB4_RD_VC4_CNTL_BASE_IDX 0
+#define regDAGB4_RD_VC5_CNTL 0x0221
+#define regDAGB4_RD_VC5_CNTL_BASE_IDX 0
+#define regDAGB4_RD_VC6_CNTL 0x0222
+#define regDAGB4_RD_VC6_CNTL_BASE_IDX 0
+#define regDAGB4_RD_VC7_CNTL 0x0223
+#define regDAGB4_RD_VC7_CNTL_BASE_IDX 0
+#define regDAGB4_RD_CNTL_MISC 0x0224
+#define regDAGB4_RD_CNTL_MISC_BASE_IDX 0
+#define regDAGB4_RD_TLB_CREDIT 0x0225
+#define regDAGB4_RD_TLB_CREDIT_BASE_IDX 0
+#define regDAGB4_RD_RDRET_CREDIT_CNTL 0x0226
+#define regDAGB4_RD_RDRET_CREDIT_CNTL_BASE_IDX 0
+#define regDAGB4_RD_RDRET_CREDIT_CNTL2 0x0227
+#define regDAGB4_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0
+#define regDAGB4_RDCLI_ASK_PENDING 0x0228
+#define regDAGB4_RDCLI_ASK_PENDING_BASE_IDX 0
+#define regDAGB4_RDCLI_GO_PENDING 0x0229
+#define regDAGB4_RDCLI_GO_PENDING_BASE_IDX 0
+#define regDAGB4_RDCLI_GBLSEND_PENDING 0x022a
+#define regDAGB4_RDCLI_GBLSEND_PENDING_BASE_IDX 0
+#define regDAGB4_RDCLI_TLB_PENDING 0x022b
+#define regDAGB4_RDCLI_TLB_PENDING_BASE_IDX 0
+#define regDAGB4_RDCLI_OARB_PENDING 0x022c
+#define regDAGB4_RDCLI_OARB_PENDING_BASE_IDX 0
+#define regDAGB4_RDCLI_OSD_PENDING 0x022d
+#define regDAGB4_RDCLI_OSD_PENDING_BASE_IDX 0
+#define regDAGB4_WRCLI0 0x022e
+#define regDAGB4_WRCLI0_BASE_IDX 0
+#define regDAGB4_WRCLI1 0x022f
+#define regDAGB4_WRCLI1_BASE_IDX 0
+#define regDAGB4_WRCLI2 0x0230
+#define regDAGB4_WRCLI2_BASE_IDX 0
+#define regDAGB4_WRCLI3 0x0231
+#define regDAGB4_WRCLI3_BASE_IDX 0
+#define regDAGB4_WRCLI4 0x0232
+#define regDAGB4_WRCLI4_BASE_IDX 0
+#define regDAGB4_WRCLI5 0x0233
+#define regDAGB4_WRCLI5_BASE_IDX 0
+#define regDAGB4_WRCLI6 0x0234
+#define regDAGB4_WRCLI6_BASE_IDX 0
+#define regDAGB4_WRCLI7 0x0235
+#define regDAGB4_WRCLI7_BASE_IDX 0
+#define regDAGB4_WRCLI8 0x0236
+#define regDAGB4_WRCLI8_BASE_IDX 0
+#define regDAGB4_WRCLI9 0x0237
+#define regDAGB4_WRCLI9_BASE_IDX 0
+#define regDAGB4_WRCLI10 0x0238
+#define regDAGB4_WRCLI10_BASE_IDX 0
+#define regDAGB4_WRCLI11 0x0239
+#define regDAGB4_WRCLI11_BASE_IDX 0
+#define regDAGB4_WRCLI12 0x023a
+#define regDAGB4_WRCLI12_BASE_IDX 0
+#define regDAGB4_WRCLI13 0x023b
+#define regDAGB4_WRCLI13_BASE_IDX 0
+#define regDAGB4_WRCLI14 0x023c
+#define regDAGB4_WRCLI14_BASE_IDX 0
+#define regDAGB4_WRCLI15 0x023d
+#define regDAGB4_WRCLI15_BASE_IDX 0
+#define regDAGB4_WR_CNTL 0x023e
+#define regDAGB4_WR_CNTL_BASE_IDX 0
+#define regDAGB4_WR_GMI_CNTL 0x023f
+#define regDAGB4_WR_GMI_CNTL_BASE_IDX 0
+#define regDAGB4_WR_ADDR_DAGB 0x0240
+#define regDAGB4_WR_ADDR_DAGB_BASE_IDX 0
+#define regDAGB4_WR_OUTPUT_DAGB_MAX_BURST 0x0241
+#define regDAGB4_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
+#define regDAGB4_WR_OUTPUT_DAGB_LAZY_TIMER 0x0242
+#define regDAGB4_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
+#define regDAGB4_WR_CGTT_CLK_CTRL 0x0243
+#define regDAGB4_WR_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB4_L1TLB_WR_CGTT_CLK_CTRL 0x0244
+#define regDAGB4_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB4_ATCVM_WR_CGTT_CLK_CTRL 0x0245
+#define regDAGB4_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB4_WR_ADDR_DAGB_MAX_BURST0 0x0246
+#define regDAGB4_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
+#define regDAGB4_WR_ADDR_DAGB_LAZY_TIMER0 0x0247
+#define regDAGB4_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
+#define regDAGB4_WR_ADDR_DAGB_MAX_BURST1 0x0248
+#define regDAGB4_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
+#define regDAGB4_WR_ADDR_DAGB_LAZY_TIMER1 0x0249
+#define regDAGB4_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
+#define regDAGB4_WR_DATA_DAGB 0x024a
+#define regDAGB4_WR_DATA_DAGB_BASE_IDX 0
+#define regDAGB4_WR_DATA_DAGB_MAX_BURST0 0x024b
+#define regDAGB4_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0
+#define regDAGB4_WR_DATA_DAGB_LAZY_TIMER0 0x024c
+#define regDAGB4_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0
+#define regDAGB4_WR_DATA_DAGB_MAX_BURST1 0x024d
+#define regDAGB4_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0
+#define regDAGB4_WR_DATA_DAGB_LAZY_TIMER1 0x024e
+#define regDAGB4_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0
+#define regDAGB4_WR_VC0_CNTL 0x024f
+#define regDAGB4_WR_VC0_CNTL_BASE_IDX 0
+#define regDAGB4_WR_VC1_CNTL 0x0250
+#define regDAGB4_WR_VC1_CNTL_BASE_IDX 0
+#define regDAGB4_WR_VC2_CNTL 0x0251
+#define regDAGB4_WR_VC2_CNTL_BASE_IDX 0
+#define regDAGB4_WR_VC3_CNTL 0x0252
+#define regDAGB4_WR_VC3_CNTL_BASE_IDX 0
+#define regDAGB4_WR_VC4_CNTL 0x0253
+#define regDAGB4_WR_VC4_CNTL_BASE_IDX 0
+#define regDAGB4_WR_VC5_CNTL 0x0254
+#define regDAGB4_WR_VC5_CNTL_BASE_IDX 0
+#define regDAGB4_WR_VC6_CNTL 0x0255
+#define regDAGB4_WR_VC6_CNTL_BASE_IDX 0
+#define regDAGB4_WR_VC7_CNTL 0x0256
+#define regDAGB4_WR_VC7_CNTL_BASE_IDX 0
+#define regDAGB4_WR_CNTL_MISC 0x0257
+#define regDAGB4_WR_CNTL_MISC_BASE_IDX 0
+#define regDAGB4_WR_TLB_CREDIT 0x0258
+#define regDAGB4_WR_TLB_CREDIT_BASE_IDX 0
+#define regDAGB4_WR_DATA_CREDIT 0x0259
+#define regDAGB4_WR_DATA_CREDIT_BASE_IDX 0
+#define regDAGB4_WR_MISC_CREDIT 0x025a
+#define regDAGB4_WR_MISC_CREDIT_BASE_IDX 0
+#define regDAGB4_WR_OSD_CREDIT_CNTL1 0x025b
+#define regDAGB4_WR_OSD_CREDIT_CNTL1_BASE_IDX 0
+#define regDAGB4_WR_OSD_CREDIT_CNTL2 0x025c
+#define regDAGB4_WR_OSD_CREDIT_CNTL2_BASE_IDX 0
+#define regDAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x025d
+#define regDAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0
+#define regDAGB4_WRCLI_GPU_SNOOP_OVERRIDE 0x025e
+#define regDAGB4_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0
+#define regDAGB4_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x025f
+#define regDAGB4_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0
+#define regDAGB4_WRCLI_ASK_PENDING 0x0260
+#define regDAGB4_WRCLI_ASK_PENDING_BASE_IDX 0
+#define regDAGB4_WRCLI_GO_PENDING 0x0261
+#define regDAGB4_WRCLI_GO_PENDING_BASE_IDX 0
+#define regDAGB4_WRCLI_GBLSEND_PENDING 0x0262
+#define regDAGB4_WRCLI_GBLSEND_PENDING_BASE_IDX 0
+#define regDAGB4_WRCLI_TLB_PENDING 0x0263
+#define regDAGB4_WRCLI_TLB_PENDING_BASE_IDX 0
+#define regDAGB4_WRCLI_OARB_PENDING 0x0264
+#define regDAGB4_WRCLI_OARB_PENDING_BASE_IDX 0
+#define regDAGB4_WRCLI_OSD_PENDING 0x0265
+#define regDAGB4_WRCLI_OSD_PENDING_BASE_IDX 0
+#define regDAGB4_WRCLI_DBUS_ASK_PENDING 0x0266
+#define regDAGB4_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0
+#define regDAGB4_WRCLI_DBUS_GO_PENDING 0x0267
+#define regDAGB4_WRCLI_DBUS_GO_PENDING_BASE_IDX 0
+#define regDAGB4_DAGB_DLY 0x0268
+#define regDAGB4_DAGB_DLY_BASE_IDX 0
+#define regDAGB4_CNTL_MISC 0x0269
+#define regDAGB4_CNTL_MISC_BASE_IDX 0
+#define regDAGB4_CNTL_MISC2 0x026a
+#define regDAGB4_CNTL_MISC2_BASE_IDX 0
+#define regDAGB4_FATAL_ERROR_CNTL 0x026b
+#define regDAGB4_FATAL_ERROR_CNTL_BASE_IDX 0
+#define regDAGB4_FATAL_ERROR_CLEAR 0x026c
+#define regDAGB4_FATAL_ERROR_CLEAR_BASE_IDX 0
+#define regDAGB4_FATAL_ERROR_STATUS0 0x026d
+#define regDAGB4_FATAL_ERROR_STATUS0_BASE_IDX 0
+#define regDAGB4_FATAL_ERROR_STATUS1 0x026e
+#define regDAGB4_FATAL_ERROR_STATUS1_BASE_IDX 0
+#define regDAGB4_FATAL_ERROR_STATUS2 0x026f
+#define regDAGB4_FATAL_ERROR_STATUS2_BASE_IDX 0
+#define regDAGB4_FATAL_ERROR_STATUS3 0x0270
+#define regDAGB4_FATAL_ERROR_STATUS3_BASE_IDX 0
+#define regDAGB4_FIFO_EMPTY 0x0271
+#define regDAGB4_FIFO_EMPTY_BASE_IDX 0
+#define regDAGB4_FIFO_FULL 0x0272
+#define regDAGB4_FIFO_FULL_BASE_IDX 0
+#define regDAGB4_WR_CREDITS_FULL 0x0273
+#define regDAGB4_WR_CREDITS_FULL_BASE_IDX 0
+#define regDAGB4_RD_CREDITS_FULL 0x0274
+#define regDAGB4_RD_CREDITS_FULL_BASE_IDX 0
+#define regDAGB4_PERFCOUNTER_LO 0x0275
+#define regDAGB4_PERFCOUNTER_LO_BASE_IDX 0
+#define regDAGB4_PERFCOUNTER_HI 0x0276
+#define regDAGB4_PERFCOUNTER_HI_BASE_IDX 0
+#define regDAGB4_PERFCOUNTER0_CFG 0x0277
+#define regDAGB4_PERFCOUNTER0_CFG_BASE_IDX 0
+#define regDAGB4_PERFCOUNTER1_CFG 0x0278
+#define regDAGB4_PERFCOUNTER1_CFG_BASE_IDX 0
+#define regDAGB4_PERFCOUNTER2_CFG 0x0279
+#define regDAGB4_PERFCOUNTER2_CFG_BASE_IDX 0
+#define regDAGB4_PERFCOUNTER_RSLT_CNTL 0x027a
+#define regDAGB4_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+#define regDAGB4_L1TLB_REG_RW 0x027b
+#define regDAGB4_L1TLB_REG_RW_BASE_IDX 0
+#define regDAGB4_RESERVE1 0x027c
+#define regDAGB4_RESERVE1_BASE_IDX 0
+#define regDAGB4_RESERVE2 0x027d
+#define regDAGB4_RESERVE2_BASE_IDX 0
+#define regDAGB4_RESERVE3 0x027e
+#define regDAGB4_RESERVE3_BASE_IDX 0
+#define regDAGB4_RESERVE4 0x027f
+#define regDAGB4_RESERVE4_BASE_IDX 0
+
+
+// addressBlock: mmhub_dagb_dagbdec5
+// base address: 0x68a00
+#define regDAGB5_RDCLI0 0x0280
+#define regDAGB5_RDCLI0_BASE_IDX 0
+#define regDAGB5_RDCLI1 0x0281
+#define regDAGB5_RDCLI1_BASE_IDX 0
+#define regDAGB5_RDCLI2 0x0282
+#define regDAGB5_RDCLI2_BASE_IDX 0
+#define regDAGB5_RDCLI3 0x0283
+#define regDAGB5_RDCLI3_BASE_IDX 0
+#define regDAGB5_RDCLI4 0x0284
+#define regDAGB5_RDCLI4_BASE_IDX 0
+#define regDAGB5_RDCLI5 0x0285
+#define regDAGB5_RDCLI5_BASE_IDX 0
+#define regDAGB5_RDCLI6 0x0286
+#define regDAGB5_RDCLI6_BASE_IDX 0
+#define regDAGB5_RDCLI7 0x0287
+#define regDAGB5_RDCLI7_BASE_IDX 0
+#define regDAGB5_RDCLI8 0x0288
+#define regDAGB5_RDCLI8_BASE_IDX 0
+#define regDAGB5_RDCLI9 0x0289
+#define regDAGB5_RDCLI9_BASE_IDX 0
+#define regDAGB5_RDCLI10 0x028a
+#define regDAGB5_RDCLI10_BASE_IDX 0
+#define regDAGB5_RDCLI11 0x028b
+#define regDAGB5_RDCLI11_BASE_IDX 0
+#define regDAGB5_RDCLI12 0x028c
+#define regDAGB5_RDCLI12_BASE_IDX 0
+#define regDAGB5_RDCLI13 0x028d
+#define regDAGB5_RDCLI13_BASE_IDX 0
+#define regDAGB5_RDCLI14 0x028e
+#define regDAGB5_RDCLI14_BASE_IDX 0
+#define regDAGB5_RDCLI15 0x028f
+#define regDAGB5_RDCLI15_BASE_IDX 0
+#define regDAGB5_RD_CNTL 0x0290
+#define regDAGB5_RD_CNTL_BASE_IDX 0
+#define regDAGB5_RD_GMI_CNTL 0x0291
+#define regDAGB5_RD_GMI_CNTL_BASE_IDX 0
+#define regDAGB5_RD_ADDR_DAGB 0x0292
+#define regDAGB5_RD_ADDR_DAGB_BASE_IDX 0
+#define regDAGB5_RD_OUTPUT_DAGB_MAX_BURST 0x0293
+#define regDAGB5_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
+#define regDAGB5_RD_OUTPUT_DAGB_LAZY_TIMER 0x0294
+#define regDAGB5_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
+#define regDAGB5_RD_CGTT_CLK_CTRL 0x0295
+#define regDAGB5_RD_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB5_L1TLB_RD_CGTT_CLK_CTRL 0x0296
+#define regDAGB5_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB5_ATCVM_RD_CGTT_CLK_CTRL 0x0297
+#define regDAGB5_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB5_RD_ADDR_DAGB_MAX_BURST0 0x0298
+#define regDAGB5_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
+#define regDAGB5_RD_ADDR_DAGB_LAZY_TIMER0 0x0299
+#define regDAGB5_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
+#define regDAGB5_RD_ADDR_DAGB_MAX_BURST1 0x029a
+#define regDAGB5_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
+#define regDAGB5_RD_ADDR_DAGB_LAZY_TIMER1 0x029b
+#define regDAGB5_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
+#define regDAGB5_RD_VC0_CNTL 0x029c
+#define regDAGB5_RD_VC0_CNTL_BASE_IDX 0
+#define regDAGB5_RD_VC1_CNTL 0x029d
+#define regDAGB5_RD_VC1_CNTL_BASE_IDX 0
+#define regDAGB5_RD_VC2_CNTL 0x029e
+#define regDAGB5_RD_VC2_CNTL_BASE_IDX 0
+#define regDAGB5_RD_VC3_CNTL 0x029f
+#define regDAGB5_RD_VC3_CNTL_BASE_IDX 0
+#define regDAGB5_RD_VC4_CNTL 0x02a0
+#define regDAGB5_RD_VC4_CNTL_BASE_IDX 0
+#define regDAGB5_RD_VC5_CNTL 0x02a1
+#define regDAGB5_RD_VC5_CNTL_BASE_IDX 0
+#define regDAGB5_RD_VC6_CNTL 0x02a2
+#define regDAGB5_RD_VC6_CNTL_BASE_IDX 0
+#define regDAGB5_RD_VC7_CNTL 0x02a3
+#define regDAGB5_RD_VC7_CNTL_BASE_IDX 0
+#define regDAGB5_RD_CNTL_MISC 0x02a4
+#define regDAGB5_RD_CNTL_MISC_BASE_IDX 0
+#define regDAGB5_RD_TLB_CREDIT 0x02a5
+#define regDAGB5_RD_TLB_CREDIT_BASE_IDX 0
+#define regDAGB5_RD_RDRET_CREDIT_CNTL 0x02a6
+#define regDAGB5_RD_RDRET_CREDIT_CNTL_BASE_IDX 0
+#define regDAGB5_RD_RDRET_CREDIT_CNTL2 0x02a7
+#define regDAGB5_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0
+#define regDAGB5_RDCLI_ASK_PENDING 0x02a8
+#define regDAGB5_RDCLI_ASK_PENDING_BASE_IDX 0
+#define regDAGB5_RDCLI_GO_PENDING 0x02a9
+#define regDAGB5_RDCLI_GO_PENDING_BASE_IDX 0
+#define regDAGB5_RDCLI_GBLSEND_PENDING 0x02aa
+#define regDAGB5_RDCLI_GBLSEND_PENDING_BASE_IDX 0
+#define regDAGB5_RDCLI_TLB_PENDING 0x02ab
+#define regDAGB5_RDCLI_TLB_PENDING_BASE_IDX 0
+#define regDAGB5_RDCLI_OARB_PENDING 0x02ac
+#define regDAGB5_RDCLI_OARB_PENDING_BASE_IDX 0
+#define regDAGB5_RDCLI_OSD_PENDING 0x02ad
+#define regDAGB5_RDCLI_OSD_PENDING_BASE_IDX 0
+#define regDAGB5_WRCLI0 0x02ae
+#define regDAGB5_WRCLI0_BASE_IDX 0
+#define regDAGB5_WRCLI1 0x02af
+#define regDAGB5_WRCLI1_BASE_IDX 0
+#define regDAGB5_WRCLI2 0x02b0
+#define regDAGB5_WRCLI2_BASE_IDX 0
+#define regDAGB5_WRCLI3 0x02b1
+#define regDAGB5_WRCLI3_BASE_IDX 0
+#define regDAGB5_WRCLI4 0x02b2
+#define regDAGB5_WRCLI4_BASE_IDX 0
+#define regDAGB5_WRCLI5 0x02b3
+#define regDAGB5_WRCLI5_BASE_IDX 0
+#define regDAGB5_WRCLI6 0x02b4
+#define regDAGB5_WRCLI6_BASE_IDX 0
+#define regDAGB5_WRCLI7 0x02b5
+#define regDAGB5_WRCLI7_BASE_IDX 0
+#define regDAGB5_WRCLI8 0x02b6
+#define regDAGB5_WRCLI8_BASE_IDX 0
+#define regDAGB5_WRCLI9 0x02b7
+#define regDAGB5_WRCLI9_BASE_IDX 0
+#define regDAGB5_WRCLI10 0x02b8
+#define regDAGB5_WRCLI10_BASE_IDX 0
+#define regDAGB5_WRCLI11 0x02b9
+#define regDAGB5_WRCLI11_BASE_IDX 0
+#define regDAGB5_WRCLI12 0x02ba
+#define regDAGB5_WRCLI12_BASE_IDX 0
+#define regDAGB5_WRCLI13 0x02bb
+#define regDAGB5_WRCLI13_BASE_IDX 0
+#define regDAGB5_WRCLI14 0x02bc
+#define regDAGB5_WRCLI14_BASE_IDX 0
+#define regDAGB5_WRCLI15 0x02bd
+#define regDAGB5_WRCLI15_BASE_IDX 0
+#define regDAGB5_WR_CNTL 0x02be
+#define regDAGB5_WR_CNTL_BASE_IDX 0
+#define regDAGB5_WR_GMI_CNTL 0x02bf
+#define regDAGB5_WR_GMI_CNTL_BASE_IDX 0
+#define regDAGB5_WR_ADDR_DAGB 0x02c0
+#define regDAGB5_WR_ADDR_DAGB_BASE_IDX 0
+#define regDAGB5_WR_OUTPUT_DAGB_MAX_BURST 0x02c1
+#define regDAGB5_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
+#define regDAGB5_WR_OUTPUT_DAGB_LAZY_TIMER 0x02c2
+#define regDAGB5_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
+#define regDAGB5_WR_CGTT_CLK_CTRL 0x02c3
+#define regDAGB5_WR_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB5_L1TLB_WR_CGTT_CLK_CTRL 0x02c4
+#define regDAGB5_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB5_ATCVM_WR_CGTT_CLK_CTRL 0x02c5
+#define regDAGB5_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB5_WR_ADDR_DAGB_MAX_BURST0 0x02c6
+#define regDAGB5_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
+#define regDAGB5_WR_ADDR_DAGB_LAZY_TIMER0 0x02c7
+#define regDAGB5_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
+#define regDAGB5_WR_ADDR_DAGB_MAX_BURST1 0x02c8
+#define regDAGB5_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
+#define regDAGB5_WR_ADDR_DAGB_LAZY_TIMER1 0x02c9
+#define regDAGB5_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
+#define regDAGB5_WR_DATA_DAGB 0x02ca
+#define regDAGB5_WR_DATA_DAGB_BASE_IDX 0
+#define regDAGB5_WR_DATA_DAGB_MAX_BURST0 0x02cb
+#define regDAGB5_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0
+#define regDAGB5_WR_DATA_DAGB_LAZY_TIMER0 0x02cc
+#define regDAGB5_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0
+#define regDAGB5_WR_DATA_DAGB_MAX_BURST1 0x02cd
+#define regDAGB5_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0
+#define regDAGB5_WR_DATA_DAGB_LAZY_TIMER1 0x02ce
+#define regDAGB5_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0
+#define regDAGB5_WR_VC0_CNTL 0x02cf
+#define regDAGB5_WR_VC0_CNTL_BASE_IDX 0
+#define regDAGB5_WR_VC1_CNTL 0x02d0
+#define regDAGB5_WR_VC1_CNTL_BASE_IDX 0
+#define regDAGB5_WR_VC2_CNTL 0x02d1
+#define regDAGB5_WR_VC2_CNTL_BASE_IDX 0
+#define regDAGB5_WR_VC3_CNTL 0x02d2
+#define regDAGB5_WR_VC3_CNTL_BASE_IDX 0
+#define regDAGB5_WR_VC4_CNTL 0x02d3
+#define regDAGB5_WR_VC4_CNTL_BASE_IDX 0
+#define regDAGB5_WR_VC5_CNTL 0x02d4
+#define regDAGB5_WR_VC5_CNTL_BASE_IDX 0
+#define regDAGB5_WR_VC6_CNTL 0x02d5
+#define regDAGB5_WR_VC6_CNTL_BASE_IDX 0
+#define regDAGB5_WR_VC7_CNTL 0x02d6
+#define regDAGB5_WR_VC7_CNTL_BASE_IDX 0
+#define regDAGB5_WR_CNTL_MISC 0x02d7
+#define regDAGB5_WR_CNTL_MISC_BASE_IDX 0
+#define regDAGB5_WR_TLB_CREDIT 0x02d8
+#define regDAGB5_WR_TLB_CREDIT_BASE_IDX 0
+#define regDAGB5_WR_DATA_CREDIT 0x02d9
+#define regDAGB5_WR_DATA_CREDIT_BASE_IDX 0
+#define regDAGB5_WR_MISC_CREDIT 0x02da
+#define regDAGB5_WR_MISC_CREDIT_BASE_IDX 0
+#define regDAGB5_WR_OSD_CREDIT_CNTL1 0x02db
+#define regDAGB5_WR_OSD_CREDIT_CNTL1_BASE_IDX 0
+#define regDAGB5_WR_OSD_CREDIT_CNTL2 0x02dc
+#define regDAGB5_WR_OSD_CREDIT_CNTL2_BASE_IDX 0
+#define regDAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x02dd
+#define regDAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0
+#define regDAGB5_WRCLI_GPU_SNOOP_OVERRIDE 0x02de
+#define regDAGB5_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0
+#define regDAGB5_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x02df
+#define regDAGB5_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0
+#define regDAGB5_WRCLI_ASK_PENDING 0x02e0
+#define regDAGB5_WRCLI_ASK_PENDING_BASE_IDX 0
+#define regDAGB5_WRCLI_GO_PENDING 0x02e1
+#define regDAGB5_WRCLI_GO_PENDING_BASE_IDX 0
+#define regDAGB5_WRCLI_GBLSEND_PENDING 0x02e2
+#define regDAGB5_WRCLI_GBLSEND_PENDING_BASE_IDX 0
+#define regDAGB5_WRCLI_TLB_PENDING 0x02e3
+#define regDAGB5_WRCLI_TLB_PENDING_BASE_IDX 0
+#define regDAGB5_WRCLI_OARB_PENDING 0x02e4
+#define regDAGB5_WRCLI_OARB_PENDING_BASE_IDX 0
+#define regDAGB5_WRCLI_OSD_PENDING 0x02e5
+#define regDAGB5_WRCLI_OSD_PENDING_BASE_IDX 0
+#define regDAGB5_WRCLI_DBUS_ASK_PENDING 0x02e6
+#define regDAGB5_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0
+#define regDAGB5_WRCLI_DBUS_GO_PENDING 0x02e7
+#define regDAGB5_WRCLI_DBUS_GO_PENDING_BASE_IDX 0
+#define regDAGB5_DAGB_DLY 0x02e8
+#define regDAGB5_DAGB_DLY_BASE_IDX 0
+#define regDAGB5_CNTL_MISC 0x02e9
+#define regDAGB5_CNTL_MISC_BASE_IDX 0
+#define regDAGB5_CNTL_MISC2 0x02ea
+#define regDAGB5_CNTL_MISC2_BASE_IDX 0
+#define regDAGB5_FATAL_ERROR_CNTL 0x02eb
+#define regDAGB5_FATAL_ERROR_CNTL_BASE_IDX 0
+#define regDAGB5_FATAL_ERROR_CLEAR 0x02ec
+#define regDAGB5_FATAL_ERROR_CLEAR_BASE_IDX 0
+#define regDAGB5_FATAL_ERROR_STATUS0 0x02ed
+#define regDAGB5_FATAL_ERROR_STATUS0_BASE_IDX 0
+#define regDAGB5_FATAL_ERROR_STATUS1 0x02ee
+#define regDAGB5_FATAL_ERROR_STATUS1_BASE_IDX 0
+#define regDAGB5_FATAL_ERROR_STATUS2 0x02ef
+#define regDAGB5_FATAL_ERROR_STATUS2_BASE_IDX 0
+#define regDAGB5_FATAL_ERROR_STATUS3 0x02f0
+#define regDAGB5_FATAL_ERROR_STATUS3_BASE_IDX 0
+#define regDAGB5_FIFO_EMPTY 0x02f1
+#define regDAGB5_FIFO_EMPTY_BASE_IDX 0
+#define regDAGB5_FIFO_FULL 0x02f2
+#define regDAGB5_FIFO_FULL_BASE_IDX 0
+#define regDAGB5_WR_CREDITS_FULL 0x02f3
+#define regDAGB5_WR_CREDITS_FULL_BASE_IDX 0
+#define regDAGB5_RD_CREDITS_FULL 0x02f4
+#define regDAGB5_RD_CREDITS_FULL_BASE_IDX 0
+#define regDAGB5_PERFCOUNTER_LO 0x02f5
+#define regDAGB5_PERFCOUNTER_LO_BASE_IDX 0
+#define regDAGB5_PERFCOUNTER_HI 0x02f6
+#define regDAGB5_PERFCOUNTER_HI_BASE_IDX 0
+#define regDAGB5_PERFCOUNTER0_CFG 0x02f7
+#define regDAGB5_PERFCOUNTER0_CFG_BASE_IDX 0
+#define regDAGB5_PERFCOUNTER1_CFG 0x02f8
+#define regDAGB5_PERFCOUNTER1_CFG_BASE_IDX 0
+#define regDAGB5_PERFCOUNTER2_CFG 0x02f9
+#define regDAGB5_PERFCOUNTER2_CFG_BASE_IDX 0
+#define regDAGB5_PERFCOUNTER_RSLT_CNTL 0x02fa
+#define regDAGB5_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+#define regDAGB5_L1TLB_REG_RW 0x02fb
+#define regDAGB5_L1TLB_REG_RW_BASE_IDX 0
+#define regDAGB5_RESERVE1 0x02fc
+#define regDAGB5_RESERVE1_BASE_IDX 0
+#define regDAGB5_RESERVE2 0x02fd
+#define regDAGB5_RESERVE2_BASE_IDX 0
+#define regDAGB5_RESERVE3 0x02fe
+#define regDAGB5_RESERVE3_BASE_IDX 0
+#define regDAGB5_RESERVE4 0x02ff
+#define regDAGB5_RESERVE4_BASE_IDX 0
+
+
+// addressBlock: mmhub_ea_mmeadec0
+// base address: 0x68c00
+#define regMMEA0_DRAM_RD_CLI2GRP_MAP0 0x0300
+#define regMMEA0_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA0_DRAM_RD_CLI2GRP_MAP1 0x0301
+#define regMMEA0_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA0_DRAM_WR_CLI2GRP_MAP0 0x0302
+#define regMMEA0_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA0_DRAM_WR_CLI2GRP_MAP1 0x0303
+#define regMMEA0_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA0_DRAM_RD_GRP2VC_MAP 0x0304
+#define regMMEA0_DRAM_RD_GRP2VC_MAP_BASE_IDX 0
+#define regMMEA0_DRAM_WR_GRP2VC_MAP 0x0305
+#define regMMEA0_DRAM_WR_GRP2VC_MAP_BASE_IDX 0
+#define regMMEA0_DRAM_RD_LAZY 0x0306
+#define regMMEA0_DRAM_RD_LAZY_BASE_IDX 0
+#define regMMEA0_DRAM_WR_LAZY 0x0307
+#define regMMEA0_DRAM_WR_LAZY_BASE_IDX 0
+#define regMMEA0_DRAM_RD_CAM_CNTL 0x0308
+#define regMMEA0_DRAM_RD_CAM_CNTL_BASE_IDX 0
+#define regMMEA0_DRAM_WR_CAM_CNTL 0x0309
+#define regMMEA0_DRAM_WR_CAM_CNTL_BASE_IDX 0
+#define regMMEA0_DRAM_PAGE_BURST 0x030a
+#define regMMEA0_DRAM_PAGE_BURST_BASE_IDX 0
+#define regMMEA0_DRAM_RD_PRI_AGE 0x030b
+#define regMMEA0_DRAM_RD_PRI_AGE_BASE_IDX 0
+#define regMMEA0_DRAM_WR_PRI_AGE 0x030c
+#define regMMEA0_DRAM_WR_PRI_AGE_BASE_IDX 0
+#define regMMEA0_DRAM_RD_PRI_QUEUING 0x030d
+#define regMMEA0_DRAM_RD_PRI_QUEUING_BASE_IDX 0
+#define regMMEA0_DRAM_WR_PRI_QUEUING 0x030e
+#define regMMEA0_DRAM_WR_PRI_QUEUING_BASE_IDX 0
+#define regMMEA0_DRAM_RD_PRI_FIXED 0x030f
+#define regMMEA0_DRAM_RD_PRI_FIXED_BASE_IDX 0
+#define regMMEA0_DRAM_WR_PRI_FIXED 0x0310
+#define regMMEA0_DRAM_WR_PRI_FIXED_BASE_IDX 0
+#define regMMEA0_DRAM_RD_PRI_URGENCY 0x0311
+#define regMMEA0_DRAM_RD_PRI_URGENCY_BASE_IDX 0
+#define regMMEA0_DRAM_WR_PRI_URGENCY 0x0312
+#define regMMEA0_DRAM_WR_PRI_URGENCY_BASE_IDX 0
+#define regMMEA0_DRAM_RD_PRI_QUANT_PRI1 0x0313
+#define regMMEA0_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA0_DRAM_RD_PRI_QUANT_PRI2 0x0314
+#define regMMEA0_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA0_DRAM_RD_PRI_QUANT_PRI3 0x0315
+#define regMMEA0_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA0_DRAM_WR_PRI_QUANT_PRI1 0x0316
+#define regMMEA0_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA0_DRAM_WR_PRI_QUANT_PRI2 0x0317
+#define regMMEA0_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA0_DRAM_WR_PRI_QUANT_PRI3 0x0318
+#define regMMEA0_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA0_GMI_RD_CLI2GRP_MAP0 0x0319
+#define regMMEA0_GMI_RD_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA0_GMI_RD_CLI2GRP_MAP1 0x031a
+#define regMMEA0_GMI_RD_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA0_GMI_WR_CLI2GRP_MAP0 0x031b
+#define regMMEA0_GMI_WR_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA0_GMI_WR_CLI2GRP_MAP1 0x031c
+#define regMMEA0_GMI_WR_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA0_GMI_RD_GRP2VC_MAP 0x031d
+#define regMMEA0_GMI_RD_GRP2VC_MAP_BASE_IDX 0
+#define regMMEA0_GMI_WR_GRP2VC_MAP 0x031e
+#define regMMEA0_GMI_WR_GRP2VC_MAP_BASE_IDX 0
+#define regMMEA0_GMI_RD_LAZY 0x031f
+#define regMMEA0_GMI_RD_LAZY_BASE_IDX 0
+#define regMMEA0_GMI_WR_LAZY 0x0320
+#define regMMEA0_GMI_WR_LAZY_BASE_IDX 0
+#define regMMEA0_GMI_RD_CAM_CNTL 0x0321
+#define regMMEA0_GMI_RD_CAM_CNTL_BASE_IDX 0
+#define regMMEA0_GMI_WR_CAM_CNTL 0x0322
+#define regMMEA0_GMI_WR_CAM_CNTL_BASE_IDX 0
+#define regMMEA0_GMI_PAGE_BURST 0x0323
+#define regMMEA0_GMI_PAGE_BURST_BASE_IDX 0
+#define regMMEA0_GMI_RD_PRI_AGE 0x0324
+#define regMMEA0_GMI_RD_PRI_AGE_BASE_IDX 0
+#define regMMEA0_GMI_WR_PRI_AGE 0x0325
+#define regMMEA0_GMI_WR_PRI_AGE_BASE_IDX 0
+#define regMMEA0_GMI_RD_PRI_QUEUING 0x0326
+#define regMMEA0_GMI_RD_PRI_QUEUING_BASE_IDX 0
+#define regMMEA0_GMI_WR_PRI_QUEUING 0x0327
+#define regMMEA0_GMI_WR_PRI_QUEUING_BASE_IDX 0
+#define regMMEA0_GMI_RD_PRI_FIXED 0x0328
+#define regMMEA0_GMI_RD_PRI_FIXED_BASE_IDX 0
+#define regMMEA0_GMI_WR_PRI_FIXED 0x0329
+#define regMMEA0_GMI_WR_PRI_FIXED_BASE_IDX 0
+#define regMMEA0_GMI_RD_PRI_URGENCY 0x032a
+#define regMMEA0_GMI_RD_PRI_URGENCY_BASE_IDX 0
+#define regMMEA0_GMI_WR_PRI_URGENCY 0x032b
+#define regMMEA0_GMI_WR_PRI_URGENCY_BASE_IDX 0
+#define regMMEA0_GMI_RD_PRI_URGENCY_MASKING 0x032c
+#define regMMEA0_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 0
+#define regMMEA0_GMI_WR_PRI_URGENCY_MASKING 0x032d
+#define regMMEA0_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 0
+#define regMMEA0_GMI_RD_PRI_QUANT_PRI1 0x032e
+#define regMMEA0_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA0_GMI_RD_PRI_QUANT_PRI2 0x032f
+#define regMMEA0_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA0_GMI_RD_PRI_QUANT_PRI3 0x0330
+#define regMMEA0_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA0_GMI_WR_PRI_QUANT_PRI1 0x0331
+#define regMMEA0_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA0_GMI_WR_PRI_QUANT_PRI2 0x0332
+#define regMMEA0_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA0_GMI_WR_PRI_QUANT_PRI3 0x0333
+#define regMMEA0_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA0_ADDRNORM_BASE_ADDR0 0x0334
+#define regMMEA0_ADDRNORM_BASE_ADDR0_BASE_IDX 0
+#define regMMEA0_ADDRNORM_LIMIT_ADDR0 0x0335
+#define regMMEA0_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0
+#define regMMEA0_ADDRNORM_BASE_ADDR1 0x0336
+#define regMMEA0_ADDRNORM_BASE_ADDR1_BASE_IDX 0
+#define regMMEA0_ADDRNORM_LIMIT_ADDR1 0x0337
+#define regMMEA0_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0
+#define regMMEA0_ADDRNORM_OFFSET_ADDR1 0x0338
+#define regMMEA0_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0
+#define regMMEA0_ADDRNORM_BASE_ADDR2 0x0339
+#define regMMEA0_ADDRNORM_BASE_ADDR2_BASE_IDX 0
+#define regMMEA0_ADDRNORM_LIMIT_ADDR2 0x033a
+#define regMMEA0_ADDRNORM_LIMIT_ADDR2_BASE_IDX 0
+#define regMMEA0_ADDRNORM_BASE_ADDR3 0x033b
+#define regMMEA0_ADDRNORM_BASE_ADDR3_BASE_IDX 0
+#define regMMEA0_ADDRNORM_LIMIT_ADDR3 0x033c
+#define regMMEA0_ADDRNORM_LIMIT_ADDR3_BASE_IDX 0
+#define regMMEA0_ADDRNORM_OFFSET_ADDR3 0x033d
+#define regMMEA0_ADDRNORM_OFFSET_ADDR3_BASE_IDX 0
+#define regMMEA0_ADDRNORM_MEGABASE_ADDR0 0x033e
+#define regMMEA0_ADDRNORM_MEGABASE_ADDR0_BASE_IDX 0
+#define regMMEA0_ADDRNORM_MEGALIMIT_ADDR0 0x033f
+#define regMMEA0_ADDRNORM_MEGALIMIT_ADDR0_BASE_IDX 0
+#define regMMEA0_ADDRNORM_MEGABASE_ADDR1 0x0340
+#define regMMEA0_ADDRNORM_MEGABASE_ADDR1_BASE_IDX 0
+#define regMMEA0_ADDRNORM_MEGALIMIT_ADDR1 0x0341
+#define regMMEA0_ADDRNORM_MEGALIMIT_ADDR1_BASE_IDX 0
+#define regMMEA0_ADDRNORMDRAM_HOLE_CNTL 0x0343
+#define regMMEA0_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0
+#define regMMEA0_ADDRNORMGMI_HOLE_CNTL 0x0344
+#define regMMEA0_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 0
+#define regMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0345
+#define regMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 0
+#define regMMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0346
+#define regMMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 0
+#define regMMEA0_ADDRDEC_BANK_CFG 0x0347
+#define regMMEA0_ADDRDEC_BANK_CFG_BASE_IDX 0
+#define regMMEA0_ADDRDEC_MISC_CFG 0x0348
+#define regMMEA0_ADDRDEC_MISC_CFG_BASE_IDX 0
+#define regMMEA0_ADDRDECDRAM_HARVEST_ENABLE 0x0353
+#define regMMEA0_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0
+#define regMMEA0_ADDRDECGMI_HARVEST_ENABLE 0x035e
+#define regMMEA0_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 0
+#define regMMEA0_ADDRDEC0_BASE_ADDR_CS0 0x035f
+#define regMMEA0_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0
+#define regMMEA0_ADDRDEC0_BASE_ADDR_CS1 0x0360
+#define regMMEA0_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0
+#define regMMEA0_ADDRDEC0_BASE_ADDR_CS2 0x0361
+#define regMMEA0_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0
+#define regMMEA0_ADDRDEC0_BASE_ADDR_CS3 0x0362
+#define regMMEA0_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0
+#define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS0 0x0363
+#define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0
+#define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS1 0x0364
+#define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0
+#define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS2 0x0365
+#define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0
+#define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS3 0x0366
+#define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0
+#define regMMEA0_ADDRDEC0_ADDR_MASK_CS01 0x0367
+#define regMMEA0_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0
+#define regMMEA0_ADDRDEC0_ADDR_MASK_CS23 0x0368
+#define regMMEA0_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0
+#define regMMEA0_ADDRDEC0_ADDR_MASK_SECCS01 0x0369
+#define regMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0
+#define regMMEA0_ADDRDEC0_ADDR_MASK_SECCS23 0x036a
+#define regMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0
+#define regMMEA0_ADDRDEC0_ADDR_CFG_CS01 0x036b
+#define regMMEA0_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0
+#define regMMEA0_ADDRDEC0_ADDR_CFG_CS23 0x036c
+#define regMMEA0_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0
+#define regMMEA0_ADDRDEC0_ADDR_SEL_CS01 0x036d
+#define regMMEA0_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0
+#define regMMEA0_ADDRDEC0_ADDR_SEL_CS23 0x036e
+#define regMMEA0_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0
+#define regMMEA0_ADDRDEC0_ADDR_SEL2_CS01 0x036f
+#define regMMEA0_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 0
+#define regMMEA0_ADDRDEC0_ADDR_SEL2_CS23 0x0370
+#define regMMEA0_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 0
+#define regMMEA0_ADDRDEC0_COL_SEL_LO_CS01 0x0371
+#define regMMEA0_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0
+#define regMMEA0_ADDRDEC0_COL_SEL_LO_CS23 0x0372
+#define regMMEA0_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0
+#define regMMEA0_ADDRDEC0_COL_SEL_HI_CS01 0x0373
+#define regMMEA0_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0
+#define regMMEA0_ADDRDEC0_COL_SEL_HI_CS23 0x0374
+#define regMMEA0_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0
+#define regMMEA0_ADDRDEC0_RM_SEL_CS01 0x0375
+#define regMMEA0_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0
+#define regMMEA0_ADDRDEC0_RM_SEL_CS23 0x0376
+#define regMMEA0_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0
+#define regMMEA0_ADDRDEC0_RM_SEL_SECCS01 0x0377
+#define regMMEA0_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0
+#define regMMEA0_ADDRDEC0_RM_SEL_SECCS23 0x0378
+#define regMMEA0_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0
+#define regMMEA0_ADDRDEC1_BASE_ADDR_CS0 0x0379
+#define regMMEA0_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0
+#define regMMEA0_ADDRDEC1_BASE_ADDR_CS1 0x037a
+#define regMMEA0_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0
+#define regMMEA0_ADDRDEC1_BASE_ADDR_CS2 0x037b
+#define regMMEA0_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0
+#define regMMEA0_ADDRDEC1_BASE_ADDR_CS3 0x037c
+#define regMMEA0_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0
+#define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS0 0x037d
+#define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0
+#define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS1 0x037e
+#define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0
+#define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS2 0x037f
+#define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0
+#define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS3 0x0380
+#define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0
+#define regMMEA0_ADDRDEC1_ADDR_MASK_CS01 0x0381
+#define regMMEA0_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0
+#define regMMEA0_ADDRDEC1_ADDR_MASK_CS23 0x0382
+#define regMMEA0_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0
+#define regMMEA0_ADDRDEC1_ADDR_MASK_SECCS01 0x0383
+#define regMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0
+#define regMMEA0_ADDRDEC1_ADDR_MASK_SECCS23 0x0384
+#define regMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0
+#define regMMEA0_ADDRDEC1_ADDR_CFG_CS01 0x0385
+#define regMMEA0_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0
+#define regMMEA0_ADDRDEC1_ADDR_CFG_CS23 0x0386
+#define regMMEA0_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0
+#define regMMEA0_ADDRDEC1_ADDR_SEL_CS01 0x0387
+#define regMMEA0_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0
+#define regMMEA0_ADDRDEC1_ADDR_SEL_CS23 0x0388
+#define regMMEA0_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0
+#define regMMEA0_ADDRDEC1_ADDR_SEL2_CS01 0x0389
+#define regMMEA0_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 0
+#define regMMEA0_ADDRDEC1_ADDR_SEL2_CS23 0x038a
+#define regMMEA0_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 0
+#define regMMEA0_ADDRDEC1_COL_SEL_LO_CS01 0x038b
+#define regMMEA0_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0
+#define regMMEA0_ADDRDEC1_COL_SEL_LO_CS23 0x038c
+#define regMMEA0_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0
+#define regMMEA0_ADDRDEC1_COL_SEL_HI_CS01 0x038d
+#define regMMEA0_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0
+#define regMMEA0_ADDRDEC1_COL_SEL_HI_CS23 0x038e
+#define regMMEA0_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0
+#define regMMEA0_ADDRDEC1_RM_SEL_CS01 0x038f
+#define regMMEA0_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0
+#define regMMEA0_ADDRDEC1_RM_SEL_CS23 0x0390
+#define regMMEA0_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0
+#define regMMEA0_ADDRDEC1_RM_SEL_SECCS01 0x0391
+#define regMMEA0_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0
+#define regMMEA0_ADDRDEC1_RM_SEL_SECCS23 0x0392
+#define regMMEA0_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0
+#define regMMEA0_ADDRDEC2_BASE_ADDR_CS0 0x0393
+#define regMMEA0_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 0
+#define regMMEA0_ADDRDEC2_BASE_ADDR_CS1 0x0394
+#define regMMEA0_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 0
+#define regMMEA0_ADDRDEC2_BASE_ADDR_CS2 0x0395
+#define regMMEA0_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 0
+#define regMMEA0_ADDRDEC2_BASE_ADDR_CS3 0x0396
+#define regMMEA0_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 0
+#define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS0 0x0397
+#define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 0
+#define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS1 0x0398
+#define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 0
+#define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS2 0x0399
+#define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 0
+#define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS3 0x039a
+#define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 0
+#define regMMEA0_ADDRDEC2_ADDR_MASK_CS01 0x039b
+#define regMMEA0_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 0
+#define regMMEA0_ADDRDEC2_ADDR_MASK_CS23 0x039c
+#define regMMEA0_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 0
+#define regMMEA0_ADDRDEC2_ADDR_MASK_SECCS01 0x039d
+#define regMMEA0_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 0
+#define regMMEA0_ADDRDEC2_ADDR_MASK_SECCS23 0x039e
+#define regMMEA0_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 0
+#define regMMEA0_ADDRDEC2_ADDR_CFG_CS01 0x039f
+#define regMMEA0_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 0
+#define regMMEA0_ADDRDEC2_ADDR_CFG_CS23 0x03a0
+#define regMMEA0_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 0
+#define regMMEA0_ADDRDEC2_ADDR_SEL_CS01 0x03a1
+#define regMMEA0_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 0
+#define regMMEA0_ADDRDEC2_ADDR_SEL_CS23 0x03a2
+#define regMMEA0_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 0
+#define regMMEA0_ADDRDEC2_ADDR_SEL2_CS01 0x03a3
+#define regMMEA0_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 0
+#define regMMEA0_ADDRDEC2_ADDR_SEL2_CS23 0x03a4
+#define regMMEA0_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 0
+#define regMMEA0_ADDRDEC2_COL_SEL_LO_CS01 0x03a5
+#define regMMEA0_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 0
+#define regMMEA0_ADDRDEC2_COL_SEL_LO_CS23 0x03a6
+#define regMMEA0_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 0
+#define regMMEA0_ADDRDEC2_COL_SEL_HI_CS01 0x03a7
+#define regMMEA0_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 0
+#define regMMEA0_ADDRDEC2_COL_SEL_HI_CS23 0x03a8
+#define regMMEA0_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 0
+#define regMMEA0_ADDRDEC2_RM_SEL_CS01 0x03a9
+#define regMMEA0_ADDRDEC2_RM_SEL_CS01_BASE_IDX 0
+#define regMMEA0_ADDRDEC2_RM_SEL_CS23 0x03aa
+#define regMMEA0_ADDRDEC2_RM_SEL_CS23_BASE_IDX 0
+#define regMMEA0_ADDRDEC2_RM_SEL_SECCS01 0x03ab
+#define regMMEA0_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 0
+#define regMMEA0_ADDRDEC2_RM_SEL_SECCS23 0x03ac
+#define regMMEA0_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 0
+#define regMMEA0_ADDRNORMDRAM_GLOBAL_CNTL 0x03ad
+#define regMMEA0_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 0
+#define regMMEA0_ADDRNORMGMI_GLOBAL_CNTL 0x03ae
+#define regMMEA0_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 0
+#define regMMEA0_ADDRNORM_MEGACONTROL_ADDR0 0x03d1
+#define regMMEA0_ADDRNORM_MEGACONTROL_ADDR0_BASE_IDX 0
+#define regMMEA0_ADDRNORM_MEGACONTROL_ADDR1 0x03d2
+#define regMMEA0_ADDRNORM_MEGACONTROL_ADDR1_BASE_IDX 0
+#define regMMEA0_ADDRNORMDRAM_MASKING 0x03d3
+#define regMMEA0_ADDRNORMDRAM_MASKING_BASE_IDX 0
+#define regMMEA0_ADDRNORMGMI_MASKING 0x03d4
+#define regMMEA0_ADDRNORMGMI_MASKING_BASE_IDX 0
+#define regMMEA0_IO_RD_CLI2GRP_MAP0 0x03d5
+#define regMMEA0_IO_RD_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA0_IO_RD_CLI2GRP_MAP1 0x03d6
+#define regMMEA0_IO_RD_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA0_IO_WR_CLI2GRP_MAP0 0x03d7
+#define regMMEA0_IO_WR_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA0_IO_WR_CLI2GRP_MAP1 0x03d8
+#define regMMEA0_IO_WR_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA0_IO_RD_COMBINE_FLUSH 0x03d9
+#define regMMEA0_IO_RD_COMBINE_FLUSH_BASE_IDX 0
+#define regMMEA0_IO_WR_COMBINE_FLUSH 0x03da
+#define regMMEA0_IO_WR_COMBINE_FLUSH_BASE_IDX 0
+#define regMMEA0_IO_GROUP_BURST 0x03db
+#define regMMEA0_IO_GROUP_BURST_BASE_IDX 0
+#define regMMEA0_IO_RD_PRI_AGE 0x03dc
+#define regMMEA0_IO_RD_PRI_AGE_BASE_IDX 0
+#define regMMEA0_IO_WR_PRI_AGE 0x03dd
+#define regMMEA0_IO_WR_PRI_AGE_BASE_IDX 0
+#define regMMEA0_IO_RD_PRI_QUEUING 0x03de
+#define regMMEA0_IO_RD_PRI_QUEUING_BASE_IDX 0
+#define regMMEA0_IO_WR_PRI_QUEUING 0x03df
+#define regMMEA0_IO_WR_PRI_QUEUING_BASE_IDX 0
+#define regMMEA0_IO_RD_PRI_FIXED 0x03e0
+#define regMMEA0_IO_RD_PRI_FIXED_BASE_IDX 0
+#define regMMEA0_IO_WR_PRI_FIXED 0x03e1
+#define regMMEA0_IO_WR_PRI_FIXED_BASE_IDX 0
+#define regMMEA0_IO_RD_PRI_URGENCY 0x03e2
+#define regMMEA0_IO_RD_PRI_URGENCY_BASE_IDX 0
+#define regMMEA0_IO_WR_PRI_URGENCY 0x03e3
+#define regMMEA0_IO_WR_PRI_URGENCY_BASE_IDX 0
+#define regMMEA0_IO_RD_PRI_URGENCY_MASKING 0x03e4
+#define regMMEA0_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0
+#define regMMEA0_IO_WR_PRI_URGENCY_MASKING 0x03e5
+#define regMMEA0_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0
+#define regMMEA0_IO_RD_PRI_QUANT_PRI1 0x03e6
+#define regMMEA0_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA0_IO_RD_PRI_QUANT_PRI2 0x03e7
+#define regMMEA0_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA0_IO_RD_PRI_QUANT_PRI3 0x03e8
+#define regMMEA0_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA0_IO_WR_PRI_QUANT_PRI1 0x03e9
+#define regMMEA0_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA0_IO_WR_PRI_QUANT_PRI2 0x03ea
+#define regMMEA0_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA0_IO_WR_PRI_QUANT_PRI3 0x03eb
+#define regMMEA0_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA0_SDP_ARB_DRAM 0x03ec
+#define regMMEA0_SDP_ARB_DRAM_BASE_IDX 0
+#define regMMEA0_SDP_ARB_GMI 0x03ed
+#define regMMEA0_SDP_ARB_GMI_BASE_IDX 0
+#define regMMEA0_SDP_ARB_FINAL 0x03ee
+#define regMMEA0_SDP_ARB_FINAL_BASE_IDX 0
+#define regMMEA0_SDP_DRAM_PRIORITY 0x03ef
+#define regMMEA0_SDP_DRAM_PRIORITY_BASE_IDX 0
+#define regMMEA0_SDP_GMI_PRIORITY 0x03f0
+#define regMMEA0_SDP_GMI_PRIORITY_BASE_IDX 0
+#define regMMEA0_SDP_IO_PRIORITY 0x03f1
+#define regMMEA0_SDP_IO_PRIORITY_BASE_IDX 0
+#define regMMEA0_SDP_CREDITS 0x03f2
+#define regMMEA0_SDP_CREDITS_BASE_IDX 0
+#define regMMEA0_SDP_TAG_RESERVE0 0x03f3
+#define regMMEA0_SDP_TAG_RESERVE0_BASE_IDX 0
+#define regMMEA0_SDP_TAG_RESERVE1 0x03f4
+#define regMMEA0_SDP_TAG_RESERVE1_BASE_IDX 0
+#define regMMEA0_SDP_VCC_RESERVE0 0x03f5
+#define regMMEA0_SDP_VCC_RESERVE0_BASE_IDX 0
+#define regMMEA0_SDP_VCC_RESERVE1 0x03f6
+#define regMMEA0_SDP_VCC_RESERVE1_BASE_IDX 0
+#define regMMEA0_SDP_VCD_RESERVE0 0x03f7
+#define regMMEA0_SDP_VCD_RESERVE0_BASE_IDX 0
+#define regMMEA0_SDP_VCD_RESERVE1 0x03f8
+#define regMMEA0_SDP_VCD_RESERVE1_BASE_IDX 0
+#define regMMEA0_SDP_REQ_CNTL 0x03f9
+#define regMMEA0_SDP_REQ_CNTL_BASE_IDX 0
+#define regMMEA0_MISC 0x03fa
+#define regMMEA0_MISC_BASE_IDX 0
+#define regMMEA0_LATENCY_SAMPLING 0x03fb
+#define regMMEA0_LATENCY_SAMPLING_BASE_IDX 0
+#define regMMEA0_PERFCOUNTER_LO 0x03fc
+#define regMMEA0_PERFCOUNTER_LO_BASE_IDX 0
+#define regMMEA0_PERFCOUNTER_HI 0x03fd
+#define regMMEA0_PERFCOUNTER_HI_BASE_IDX 0
+#define regMMEA0_PERFCOUNTER0_CFG 0x03fe
+#define regMMEA0_PERFCOUNTER0_CFG_BASE_IDX 0
+#define regMMEA0_PERFCOUNTER1_CFG 0x03ff
+#define regMMEA0_PERFCOUNTER1_CFG_BASE_IDX 0
+#define regMMEA0_PERFCOUNTER_RSLT_CNTL 0x0400
+#define regMMEA0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+#define regMMEA0_EDC_CNT 0x0406
+#define regMMEA0_EDC_CNT_BASE_IDX 0
+#define regMMEA0_EDC_CNT2 0x0407
+#define regMMEA0_EDC_CNT2_BASE_IDX 0
+#define regMMEA0_DSM_CNTL 0x0408
+#define regMMEA0_DSM_CNTL_BASE_IDX 0
+#define regMMEA0_DSM_CNTLA 0x0409
+#define regMMEA0_DSM_CNTLA_BASE_IDX 0
+#define regMMEA0_DSM_CNTLB 0x040a
+#define regMMEA0_DSM_CNTLB_BASE_IDX 0
+#define regMMEA0_DSM_CNTL2 0x040b
+#define regMMEA0_DSM_CNTL2_BASE_IDX 0
+#define regMMEA0_DSM_CNTL2A 0x040c
+#define regMMEA0_DSM_CNTL2A_BASE_IDX 0
+#define regMMEA0_DSM_CNTL2B 0x040d
+#define regMMEA0_DSM_CNTL2B_BASE_IDX 0
+#define regMMEA0_CGTT_CLK_CTRL 0x040f
+#define regMMEA0_CGTT_CLK_CTRL_BASE_IDX 0
+#define regMMEA0_EDC_MODE 0x0410
+#define regMMEA0_EDC_MODE_BASE_IDX 0
+#define regMMEA0_ERR_STATUS 0x0411
+#define regMMEA0_ERR_STATUS_BASE_IDX 0
+#define regMMEA0_MISC2 0x0412
+#define regMMEA0_MISC2_BASE_IDX 0
+#define regMMEA0_ADDRDEC_SELECT 0x0413
+#define regMMEA0_ADDRDEC_SELECT_BASE_IDX 0
+#define regMMEA0_EDC_CNT3 0x0414
+#define regMMEA0_EDC_CNT3_BASE_IDX 0
+#define regMMEA0_MISC_AON 0x0415
+#define regMMEA0_MISC_AON_BASE_IDX 0
+
+
+// addressBlock: mmhub_ea_mmeadec1
+// base address: 0x69100
+#define regMMEA1_DRAM_RD_CLI2GRP_MAP0 0x0440
+#define regMMEA1_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA1_DRAM_RD_CLI2GRP_MAP1 0x0441
+#define regMMEA1_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA1_DRAM_WR_CLI2GRP_MAP0 0x0442
+#define regMMEA1_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA1_DRAM_WR_CLI2GRP_MAP1 0x0443
+#define regMMEA1_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA1_DRAM_RD_GRP2VC_MAP 0x0444
+#define regMMEA1_DRAM_RD_GRP2VC_MAP_BASE_IDX 0
+#define regMMEA1_DRAM_WR_GRP2VC_MAP 0x0445
+#define regMMEA1_DRAM_WR_GRP2VC_MAP_BASE_IDX 0
+#define regMMEA1_DRAM_RD_LAZY 0x0446
+#define regMMEA1_DRAM_RD_LAZY_BASE_IDX 0
+#define regMMEA1_DRAM_WR_LAZY 0x0447
+#define regMMEA1_DRAM_WR_LAZY_BASE_IDX 0
+#define regMMEA1_DRAM_RD_CAM_CNTL 0x0448
+#define regMMEA1_DRAM_RD_CAM_CNTL_BASE_IDX 0
+#define regMMEA1_DRAM_WR_CAM_CNTL 0x0449
+#define regMMEA1_DRAM_WR_CAM_CNTL_BASE_IDX 0
+#define regMMEA1_DRAM_PAGE_BURST 0x044a
+#define regMMEA1_DRAM_PAGE_BURST_BASE_IDX 0
+#define regMMEA1_DRAM_RD_PRI_AGE 0x044b
+#define regMMEA1_DRAM_RD_PRI_AGE_BASE_IDX 0
+#define regMMEA1_DRAM_WR_PRI_AGE 0x044c
+#define regMMEA1_DRAM_WR_PRI_AGE_BASE_IDX 0
+#define regMMEA1_DRAM_RD_PRI_QUEUING 0x044d
+#define regMMEA1_DRAM_RD_PRI_QUEUING_BASE_IDX 0
+#define regMMEA1_DRAM_WR_PRI_QUEUING 0x044e
+#define regMMEA1_DRAM_WR_PRI_QUEUING_BASE_IDX 0
+#define regMMEA1_DRAM_RD_PRI_FIXED 0x044f
+#define regMMEA1_DRAM_RD_PRI_FIXED_BASE_IDX 0
+#define regMMEA1_DRAM_WR_PRI_FIXED 0x0450
+#define regMMEA1_DRAM_WR_PRI_FIXED_BASE_IDX 0
+#define regMMEA1_DRAM_RD_PRI_URGENCY 0x0451
+#define regMMEA1_DRAM_RD_PRI_URGENCY_BASE_IDX 0
+#define regMMEA1_DRAM_WR_PRI_URGENCY 0x0452
+#define regMMEA1_DRAM_WR_PRI_URGENCY_BASE_IDX 0
+#define regMMEA1_DRAM_RD_PRI_QUANT_PRI1 0x0453
+#define regMMEA1_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA1_DRAM_RD_PRI_QUANT_PRI2 0x0454
+#define regMMEA1_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA1_DRAM_RD_PRI_QUANT_PRI3 0x0455
+#define regMMEA1_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA1_DRAM_WR_PRI_QUANT_PRI1 0x0456
+#define regMMEA1_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA1_DRAM_WR_PRI_QUANT_PRI2 0x0457
+#define regMMEA1_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA1_DRAM_WR_PRI_QUANT_PRI3 0x0458
+#define regMMEA1_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA1_GMI_RD_CLI2GRP_MAP0 0x0459
+#define regMMEA1_GMI_RD_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA1_GMI_RD_CLI2GRP_MAP1 0x045a
+#define regMMEA1_GMI_RD_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA1_GMI_WR_CLI2GRP_MAP0 0x045b
+#define regMMEA1_GMI_WR_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA1_GMI_WR_CLI2GRP_MAP1 0x045c
+#define regMMEA1_GMI_WR_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA1_GMI_RD_GRP2VC_MAP 0x045d
+#define regMMEA1_GMI_RD_GRP2VC_MAP_BASE_IDX 0
+#define regMMEA1_GMI_WR_GRP2VC_MAP 0x045e
+#define regMMEA1_GMI_WR_GRP2VC_MAP_BASE_IDX 0
+#define regMMEA1_GMI_RD_LAZY 0x045f
+#define regMMEA1_GMI_RD_LAZY_BASE_IDX 0
+#define regMMEA1_GMI_WR_LAZY 0x0460
+#define regMMEA1_GMI_WR_LAZY_BASE_IDX 0
+#define regMMEA1_GMI_RD_CAM_CNTL 0x0461
+#define regMMEA1_GMI_RD_CAM_CNTL_BASE_IDX 0
+#define regMMEA1_GMI_WR_CAM_CNTL 0x0462
+#define regMMEA1_GMI_WR_CAM_CNTL_BASE_IDX 0
+#define regMMEA1_GMI_PAGE_BURST 0x0463
+#define regMMEA1_GMI_PAGE_BURST_BASE_IDX 0
+#define regMMEA1_GMI_RD_PRI_AGE 0x0464
+#define regMMEA1_GMI_RD_PRI_AGE_BASE_IDX 0
+#define regMMEA1_GMI_WR_PRI_AGE 0x0465
+#define regMMEA1_GMI_WR_PRI_AGE_BASE_IDX 0
+#define regMMEA1_GMI_RD_PRI_QUEUING 0x0466
+#define regMMEA1_GMI_RD_PRI_QUEUING_BASE_IDX 0
+#define regMMEA1_GMI_WR_PRI_QUEUING 0x0467
+#define regMMEA1_GMI_WR_PRI_QUEUING_BASE_IDX 0
+#define regMMEA1_GMI_RD_PRI_FIXED 0x0468
+#define regMMEA1_GMI_RD_PRI_FIXED_BASE_IDX 0
+#define regMMEA1_GMI_WR_PRI_FIXED 0x0469
+#define regMMEA1_GMI_WR_PRI_FIXED_BASE_IDX 0
+#define regMMEA1_GMI_RD_PRI_URGENCY 0x046a
+#define regMMEA1_GMI_RD_PRI_URGENCY_BASE_IDX 0
+#define regMMEA1_GMI_WR_PRI_URGENCY 0x046b
+#define regMMEA1_GMI_WR_PRI_URGENCY_BASE_IDX 0
+#define regMMEA1_GMI_RD_PRI_URGENCY_MASKING 0x046c
+#define regMMEA1_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 0
+#define regMMEA1_GMI_WR_PRI_URGENCY_MASKING 0x046d
+#define regMMEA1_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 0
+#define regMMEA1_GMI_RD_PRI_QUANT_PRI1 0x046e
+#define regMMEA1_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA1_GMI_RD_PRI_QUANT_PRI2 0x046f
+#define regMMEA1_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA1_GMI_RD_PRI_QUANT_PRI3 0x0470
+#define regMMEA1_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA1_GMI_WR_PRI_QUANT_PRI1 0x0471
+#define regMMEA1_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA1_GMI_WR_PRI_QUANT_PRI2 0x0472
+#define regMMEA1_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA1_GMI_WR_PRI_QUANT_PRI3 0x0473
+#define regMMEA1_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA1_ADDRNORM_BASE_ADDR0 0x0474
+#define regMMEA1_ADDRNORM_BASE_ADDR0_BASE_IDX 0
+#define regMMEA1_ADDRNORM_LIMIT_ADDR0 0x0475
+#define regMMEA1_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0
+#define regMMEA1_ADDRNORM_BASE_ADDR1 0x0476
+#define regMMEA1_ADDRNORM_BASE_ADDR1_BASE_IDX 0
+#define regMMEA1_ADDRNORM_LIMIT_ADDR1 0x0477
+#define regMMEA1_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0
+#define regMMEA1_ADDRNORM_OFFSET_ADDR1 0x0478
+#define regMMEA1_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0
+#define regMMEA1_ADDRNORM_BASE_ADDR2 0x0479
+#define regMMEA1_ADDRNORM_BASE_ADDR2_BASE_IDX 0
+#define regMMEA1_ADDRNORM_LIMIT_ADDR2 0x047a
+#define regMMEA1_ADDRNORM_LIMIT_ADDR2_BASE_IDX 0
+#define regMMEA1_ADDRNORM_BASE_ADDR3 0x047b
+#define regMMEA1_ADDRNORM_BASE_ADDR3_BASE_IDX 0
+#define regMMEA1_ADDRNORM_LIMIT_ADDR3 0x047c
+#define regMMEA1_ADDRNORM_LIMIT_ADDR3_BASE_IDX 0
+#define regMMEA1_ADDRNORM_OFFSET_ADDR3 0x047d
+#define regMMEA1_ADDRNORM_OFFSET_ADDR3_BASE_IDX 0
+#define regMMEA1_ADDRNORM_MEGABASE_ADDR0 0x047e
+#define regMMEA1_ADDRNORM_MEGABASE_ADDR0_BASE_IDX 0
+#define regMMEA1_ADDRNORM_MEGALIMIT_ADDR0 0x047f
+#define regMMEA1_ADDRNORM_MEGALIMIT_ADDR0_BASE_IDX 0
+#define regMMEA1_ADDRNORM_MEGABASE_ADDR1 0x0480
+#define regMMEA1_ADDRNORM_MEGABASE_ADDR1_BASE_IDX 0
+#define regMMEA1_ADDRNORM_MEGALIMIT_ADDR1 0x0481
+#define regMMEA1_ADDRNORM_MEGALIMIT_ADDR1_BASE_IDX 0
+#define regMMEA1_ADDRNORMDRAM_HOLE_CNTL 0x0483
+#define regMMEA1_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0
+#define regMMEA1_ADDRNORMGMI_HOLE_CNTL 0x0484
+#define regMMEA1_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 0
+#define regMMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0485
+#define regMMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 0
+#define regMMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0486
+#define regMMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 0
+#define regMMEA1_ADDRDEC_BANK_CFG 0x0487
+#define regMMEA1_ADDRDEC_BANK_CFG_BASE_IDX 0
+#define regMMEA1_ADDRDEC_MISC_CFG 0x0488
+#define regMMEA1_ADDRDEC_MISC_CFG_BASE_IDX 0
+#define regMMEA1_ADDRDECDRAM_HARVEST_ENABLE 0x0493
+#define regMMEA1_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0
+#define regMMEA1_ADDRDECGMI_HARVEST_ENABLE 0x049e
+#define regMMEA1_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 0
+#define regMMEA1_ADDRDEC0_BASE_ADDR_CS0 0x049f
+#define regMMEA1_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0
+#define regMMEA1_ADDRDEC0_BASE_ADDR_CS1 0x04a0
+#define regMMEA1_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0
+#define regMMEA1_ADDRDEC0_BASE_ADDR_CS2 0x04a1
+#define regMMEA1_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0
+#define regMMEA1_ADDRDEC0_BASE_ADDR_CS3 0x04a2
+#define regMMEA1_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0
+#define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS0 0x04a3
+#define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0
+#define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS1 0x04a4
+#define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0
+#define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS2 0x04a5
+#define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0
+#define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS3 0x04a6
+#define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0
+#define regMMEA1_ADDRDEC0_ADDR_MASK_CS01 0x04a7
+#define regMMEA1_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0
+#define regMMEA1_ADDRDEC0_ADDR_MASK_CS23 0x04a8
+#define regMMEA1_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0
+#define regMMEA1_ADDRDEC0_ADDR_MASK_SECCS01 0x04a9
+#define regMMEA1_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0
+#define regMMEA1_ADDRDEC0_ADDR_MASK_SECCS23 0x04aa
+#define regMMEA1_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0
+#define regMMEA1_ADDRDEC0_ADDR_CFG_CS01 0x04ab
+#define regMMEA1_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0
+#define regMMEA1_ADDRDEC0_ADDR_CFG_CS23 0x04ac
+#define regMMEA1_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0
+#define regMMEA1_ADDRDEC0_ADDR_SEL_CS01 0x04ad
+#define regMMEA1_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0
+#define regMMEA1_ADDRDEC0_ADDR_SEL_CS23 0x04ae
+#define regMMEA1_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0
+#define regMMEA1_ADDRDEC0_ADDR_SEL2_CS01 0x04af
+#define regMMEA1_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 0
+#define regMMEA1_ADDRDEC0_ADDR_SEL2_CS23 0x04b0
+#define regMMEA1_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 0
+#define regMMEA1_ADDRDEC0_COL_SEL_LO_CS01 0x04b1
+#define regMMEA1_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0
+#define regMMEA1_ADDRDEC0_COL_SEL_LO_CS23 0x04b2
+#define regMMEA1_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0
+#define regMMEA1_ADDRDEC0_COL_SEL_HI_CS01 0x04b3
+#define regMMEA1_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0
+#define regMMEA1_ADDRDEC0_COL_SEL_HI_CS23 0x04b4
+#define regMMEA1_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0
+#define regMMEA1_ADDRDEC0_RM_SEL_CS01 0x04b5
+#define regMMEA1_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0
+#define regMMEA1_ADDRDEC0_RM_SEL_CS23 0x04b6
+#define regMMEA1_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0
+#define regMMEA1_ADDRDEC0_RM_SEL_SECCS01 0x04b7
+#define regMMEA1_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0
+#define regMMEA1_ADDRDEC0_RM_SEL_SECCS23 0x04b8
+#define regMMEA1_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0
+#define regMMEA1_ADDRDEC1_BASE_ADDR_CS0 0x04b9
+#define regMMEA1_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0
+#define regMMEA1_ADDRDEC1_BASE_ADDR_CS1 0x04ba
+#define regMMEA1_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0
+#define regMMEA1_ADDRDEC1_BASE_ADDR_CS2 0x04bb
+#define regMMEA1_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0
+#define regMMEA1_ADDRDEC1_BASE_ADDR_CS3 0x04bc
+#define regMMEA1_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0
+#define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS0 0x04bd
+#define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0
+#define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS1 0x04be
+#define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0
+#define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS2 0x04bf
+#define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0
+#define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS3 0x04c0
+#define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0
+#define regMMEA1_ADDRDEC1_ADDR_MASK_CS01 0x04c1
+#define regMMEA1_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0
+#define regMMEA1_ADDRDEC1_ADDR_MASK_CS23 0x04c2
+#define regMMEA1_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0
+#define regMMEA1_ADDRDEC1_ADDR_MASK_SECCS01 0x04c3
+#define regMMEA1_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0
+#define regMMEA1_ADDRDEC1_ADDR_MASK_SECCS23 0x04c4
+#define regMMEA1_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0
+#define regMMEA1_ADDRDEC1_ADDR_CFG_CS01 0x04c5
+#define regMMEA1_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0
+#define regMMEA1_ADDRDEC1_ADDR_CFG_CS23 0x04c6
+#define regMMEA1_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0
+#define regMMEA1_ADDRDEC1_ADDR_SEL_CS01 0x04c7
+#define regMMEA1_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0
+#define regMMEA1_ADDRDEC1_ADDR_SEL_CS23 0x04c8
+#define regMMEA1_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0
+#define regMMEA1_ADDRDEC1_ADDR_SEL2_CS01 0x04c9
+#define regMMEA1_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 0
+#define regMMEA1_ADDRDEC1_ADDR_SEL2_CS23 0x04ca
+#define regMMEA1_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 0
+#define regMMEA1_ADDRDEC1_COL_SEL_LO_CS01 0x04cb
+#define regMMEA1_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0
+#define regMMEA1_ADDRDEC1_COL_SEL_LO_CS23 0x04cc
+#define regMMEA1_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0
+#define regMMEA1_ADDRDEC1_COL_SEL_HI_CS01 0x04cd
+#define regMMEA1_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0
+#define regMMEA1_ADDRDEC1_COL_SEL_HI_CS23 0x04ce
+#define regMMEA1_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0
+#define regMMEA1_ADDRDEC1_RM_SEL_CS01 0x04cf
+#define regMMEA1_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0
+#define regMMEA1_ADDRDEC1_RM_SEL_CS23 0x04d0
+#define regMMEA1_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0
+#define regMMEA1_ADDRDEC1_RM_SEL_SECCS01 0x04d1
+#define regMMEA1_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0
+#define regMMEA1_ADDRDEC1_RM_SEL_SECCS23 0x04d2
+#define regMMEA1_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0
+#define regMMEA1_ADDRDEC2_BASE_ADDR_CS0 0x04d3
+#define regMMEA1_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 0
+#define regMMEA1_ADDRDEC2_BASE_ADDR_CS1 0x04d4
+#define regMMEA1_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 0
+#define regMMEA1_ADDRDEC2_BASE_ADDR_CS2 0x04d5
+#define regMMEA1_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 0
+#define regMMEA1_ADDRDEC2_BASE_ADDR_CS3 0x04d6
+#define regMMEA1_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 0
+#define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS0 0x04d7
+#define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 0
+#define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS1 0x04d8
+#define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 0
+#define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS2 0x04d9
+#define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 0
+#define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS3 0x04da
+#define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 0
+#define regMMEA1_ADDRDEC2_ADDR_MASK_CS01 0x04db
+#define regMMEA1_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 0
+#define regMMEA1_ADDRDEC2_ADDR_MASK_CS23 0x04dc
+#define regMMEA1_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 0
+#define regMMEA1_ADDRDEC2_ADDR_MASK_SECCS01 0x04dd
+#define regMMEA1_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 0
+#define regMMEA1_ADDRDEC2_ADDR_MASK_SECCS23 0x04de
+#define regMMEA1_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 0
+#define regMMEA1_ADDRDEC2_ADDR_CFG_CS01 0x04df
+#define regMMEA1_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 0
+#define regMMEA1_ADDRDEC2_ADDR_CFG_CS23 0x04e0
+#define regMMEA1_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 0
+#define regMMEA1_ADDRDEC2_ADDR_SEL_CS01 0x04e1
+#define regMMEA1_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 0
+#define regMMEA1_ADDRDEC2_ADDR_SEL_CS23 0x04e2
+#define regMMEA1_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 0
+#define regMMEA1_ADDRDEC2_ADDR_SEL2_CS01 0x04e3
+#define regMMEA1_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 0
+#define regMMEA1_ADDRDEC2_ADDR_SEL2_CS23 0x04e4
+#define regMMEA1_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 0
+#define regMMEA1_ADDRDEC2_COL_SEL_LO_CS01 0x04e5
+#define regMMEA1_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 0
+#define regMMEA1_ADDRDEC2_COL_SEL_LO_CS23 0x04e6
+#define regMMEA1_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 0
+#define regMMEA1_ADDRDEC2_COL_SEL_HI_CS01 0x04e7
+#define regMMEA1_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 0
+#define regMMEA1_ADDRDEC2_COL_SEL_HI_CS23 0x04e8
+#define regMMEA1_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 0
+#define regMMEA1_ADDRDEC2_RM_SEL_CS01 0x04e9
+#define regMMEA1_ADDRDEC2_RM_SEL_CS01_BASE_IDX 0
+#define regMMEA1_ADDRDEC2_RM_SEL_CS23 0x04ea
+#define regMMEA1_ADDRDEC2_RM_SEL_CS23_BASE_IDX 0
+#define regMMEA1_ADDRDEC2_RM_SEL_SECCS01 0x04eb
+#define regMMEA1_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 0
+#define regMMEA1_ADDRDEC2_RM_SEL_SECCS23 0x04ec
+#define regMMEA1_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 0
+#define regMMEA1_ADDRNORMDRAM_GLOBAL_CNTL 0x04ed
+#define regMMEA1_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 0
+#define regMMEA1_ADDRNORMGMI_GLOBAL_CNTL 0x04ee
+#define regMMEA1_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 0
+#define regMMEA1_ADDRNORM_MEGACONTROL_ADDR0 0x0511
+#define regMMEA1_ADDRNORM_MEGACONTROL_ADDR0_BASE_IDX 0
+#define regMMEA1_ADDRNORM_MEGACONTROL_ADDR1 0x0512
+#define regMMEA1_ADDRNORM_MEGACONTROL_ADDR1_BASE_IDX 0
+#define regMMEA1_ADDRNORMDRAM_MASKING 0x0513
+#define regMMEA1_ADDRNORMDRAM_MASKING_BASE_IDX 0
+#define regMMEA1_ADDRNORMGMI_MASKING 0x0514
+#define regMMEA1_ADDRNORMGMI_MASKING_BASE_IDX 0
+#define regMMEA1_IO_RD_CLI2GRP_MAP0 0x0515
+#define regMMEA1_IO_RD_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA1_IO_RD_CLI2GRP_MAP1 0x0516
+#define regMMEA1_IO_RD_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA1_IO_WR_CLI2GRP_MAP0 0x0517
+#define regMMEA1_IO_WR_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA1_IO_WR_CLI2GRP_MAP1 0x0518
+#define regMMEA1_IO_WR_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA1_IO_RD_COMBINE_FLUSH 0x0519
+#define regMMEA1_IO_RD_COMBINE_FLUSH_BASE_IDX 0
+#define regMMEA1_IO_WR_COMBINE_FLUSH 0x051a
+#define regMMEA1_IO_WR_COMBINE_FLUSH_BASE_IDX 0
+#define regMMEA1_IO_GROUP_BURST 0x051b
+#define regMMEA1_IO_GROUP_BURST_BASE_IDX 0
+#define regMMEA1_IO_RD_PRI_AGE 0x051c
+#define regMMEA1_IO_RD_PRI_AGE_BASE_IDX 0
+#define regMMEA1_IO_WR_PRI_AGE 0x051d
+#define regMMEA1_IO_WR_PRI_AGE_BASE_IDX 0
+#define regMMEA1_IO_RD_PRI_QUEUING 0x051e
+#define regMMEA1_IO_RD_PRI_QUEUING_BASE_IDX 0
+#define regMMEA1_IO_WR_PRI_QUEUING 0x051f
+#define regMMEA1_IO_WR_PRI_QUEUING_BASE_IDX 0
+#define regMMEA1_IO_RD_PRI_FIXED 0x0520
+#define regMMEA1_IO_RD_PRI_FIXED_BASE_IDX 0
+#define regMMEA1_IO_WR_PRI_FIXED 0x0521
+#define regMMEA1_IO_WR_PRI_FIXED_BASE_IDX 0
+#define regMMEA1_IO_RD_PRI_URGENCY 0x0522
+#define regMMEA1_IO_RD_PRI_URGENCY_BASE_IDX 0
+#define regMMEA1_IO_WR_PRI_URGENCY 0x0523
+#define regMMEA1_IO_WR_PRI_URGENCY_BASE_IDX 0
+#define regMMEA1_IO_RD_PRI_URGENCY_MASKING 0x0524
+#define regMMEA1_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0
+#define regMMEA1_IO_WR_PRI_URGENCY_MASKING 0x0525
+#define regMMEA1_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0
+#define regMMEA1_IO_RD_PRI_QUANT_PRI1 0x0526
+#define regMMEA1_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA1_IO_RD_PRI_QUANT_PRI2 0x0527
+#define regMMEA1_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA1_IO_RD_PRI_QUANT_PRI3 0x0528
+#define regMMEA1_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA1_IO_WR_PRI_QUANT_PRI1 0x0529
+#define regMMEA1_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA1_IO_WR_PRI_QUANT_PRI2 0x052a
+#define regMMEA1_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA1_IO_WR_PRI_QUANT_PRI3 0x052b
+#define regMMEA1_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA1_SDP_ARB_DRAM 0x052c
+#define regMMEA1_SDP_ARB_DRAM_BASE_IDX 0
+#define regMMEA1_SDP_ARB_GMI 0x052d
+#define regMMEA1_SDP_ARB_GMI_BASE_IDX 0
+#define regMMEA1_SDP_ARB_FINAL 0x052e
+#define regMMEA1_SDP_ARB_FINAL_BASE_IDX 0
+#define regMMEA1_SDP_DRAM_PRIORITY 0x052f
+#define regMMEA1_SDP_DRAM_PRIORITY_BASE_IDX 0
+#define regMMEA1_SDP_GMI_PRIORITY 0x0530
+#define regMMEA1_SDP_GMI_PRIORITY_BASE_IDX 0
+#define regMMEA1_SDP_IO_PRIORITY 0x0531
+#define regMMEA1_SDP_IO_PRIORITY_BASE_IDX 0
+#define regMMEA1_SDP_CREDITS 0x0532
+#define regMMEA1_SDP_CREDITS_BASE_IDX 0
+#define regMMEA1_SDP_TAG_RESERVE0 0x0533
+#define regMMEA1_SDP_TAG_RESERVE0_BASE_IDX 0
+#define regMMEA1_SDP_TAG_RESERVE1 0x0534
+#define regMMEA1_SDP_TAG_RESERVE1_BASE_IDX 0
+#define regMMEA1_SDP_VCC_RESERVE0 0x0535
+#define regMMEA1_SDP_VCC_RESERVE0_BASE_IDX 0
+#define regMMEA1_SDP_VCC_RESERVE1 0x0536
+#define regMMEA1_SDP_VCC_RESERVE1_BASE_IDX 0
+#define regMMEA1_SDP_VCD_RESERVE0 0x0537
+#define regMMEA1_SDP_VCD_RESERVE0_BASE_IDX 0
+#define regMMEA1_SDP_VCD_RESERVE1 0x0538
+#define regMMEA1_SDP_VCD_RESERVE1_BASE_IDX 0
+#define regMMEA1_SDP_REQ_CNTL 0x0539
+#define regMMEA1_SDP_REQ_CNTL_BASE_IDX 0
+#define regMMEA1_MISC 0x053a
+#define regMMEA1_MISC_BASE_IDX 0
+#define regMMEA1_LATENCY_SAMPLING 0x053b
+#define regMMEA1_LATENCY_SAMPLING_BASE_IDX 0
+#define regMMEA1_PERFCOUNTER_LO 0x053c
+#define regMMEA1_PERFCOUNTER_LO_BASE_IDX 0
+#define regMMEA1_PERFCOUNTER_HI 0x053d
+#define regMMEA1_PERFCOUNTER_HI_BASE_IDX 0
+#define regMMEA1_PERFCOUNTER0_CFG 0x053e
+#define regMMEA1_PERFCOUNTER0_CFG_BASE_IDX 0
+#define regMMEA1_PERFCOUNTER1_CFG 0x053f
+#define regMMEA1_PERFCOUNTER1_CFG_BASE_IDX 0
+#define regMMEA1_PERFCOUNTER_RSLT_CNTL 0x0540
+#define regMMEA1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+#define regMMEA1_EDC_CNT 0x0546
+#define regMMEA1_EDC_CNT_BASE_IDX 0
+#define regMMEA1_EDC_CNT2 0x0547
+#define regMMEA1_EDC_CNT2_BASE_IDX 0
+#define regMMEA1_DSM_CNTL 0x0548
+#define regMMEA1_DSM_CNTL_BASE_IDX 0
+#define regMMEA1_DSM_CNTLA 0x0549
+#define regMMEA1_DSM_CNTLA_BASE_IDX 0
+#define regMMEA1_DSM_CNTLB 0x054a
+#define regMMEA1_DSM_CNTLB_BASE_IDX 0
+#define regMMEA1_DSM_CNTL2 0x054b
+#define regMMEA1_DSM_CNTL2_BASE_IDX 0
+#define regMMEA1_DSM_CNTL2A 0x054c
+#define regMMEA1_DSM_CNTL2A_BASE_IDX 0
+#define regMMEA1_DSM_CNTL2B 0x054d
+#define regMMEA1_DSM_CNTL2B_BASE_IDX 0
+#define regMMEA1_CGTT_CLK_CTRL 0x054f
+#define regMMEA1_CGTT_CLK_CTRL_BASE_IDX 0
+#define regMMEA1_EDC_MODE 0x0550
+#define regMMEA1_EDC_MODE_BASE_IDX 0
+#define regMMEA1_ERR_STATUS 0x0551
+#define regMMEA1_ERR_STATUS_BASE_IDX 0
+#define regMMEA1_MISC2 0x0552
+#define regMMEA1_MISC2_BASE_IDX 0
+#define regMMEA1_ADDRDEC_SELECT 0x0553
+#define regMMEA1_ADDRDEC_SELECT_BASE_IDX 0
+#define regMMEA1_EDC_CNT3 0x0554
+#define regMMEA1_EDC_CNT3_BASE_IDX 0
+#define regMMEA1_MISC_AON 0x0555
+#define regMMEA1_MISC_AON_BASE_IDX 0
+
+
+// addressBlock: mmhub_ea_mmeadec2
+// base address: 0x69600
+#define regMMEA2_DRAM_RD_CLI2GRP_MAP0 0x0580
+#define regMMEA2_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA2_DRAM_RD_CLI2GRP_MAP1 0x0581
+#define regMMEA2_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA2_DRAM_WR_CLI2GRP_MAP0 0x0582
+#define regMMEA2_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA2_DRAM_WR_CLI2GRP_MAP1 0x0583
+#define regMMEA2_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA2_DRAM_RD_GRP2VC_MAP 0x0584
+#define regMMEA2_DRAM_RD_GRP2VC_MAP_BASE_IDX 0
+#define regMMEA2_DRAM_WR_GRP2VC_MAP 0x0585
+#define regMMEA2_DRAM_WR_GRP2VC_MAP_BASE_IDX 0
+#define regMMEA2_DRAM_RD_LAZY 0x0586
+#define regMMEA2_DRAM_RD_LAZY_BASE_IDX 0
+#define regMMEA2_DRAM_WR_LAZY 0x0587
+#define regMMEA2_DRAM_WR_LAZY_BASE_IDX 0
+#define regMMEA2_DRAM_RD_CAM_CNTL 0x0588
+#define regMMEA2_DRAM_RD_CAM_CNTL_BASE_IDX 0
+#define regMMEA2_DRAM_WR_CAM_CNTL 0x0589
+#define regMMEA2_DRAM_WR_CAM_CNTL_BASE_IDX 0
+#define regMMEA2_DRAM_PAGE_BURST 0x058a
+#define regMMEA2_DRAM_PAGE_BURST_BASE_IDX 0
+#define regMMEA2_DRAM_RD_PRI_AGE 0x058b
+#define regMMEA2_DRAM_RD_PRI_AGE_BASE_IDX 0
+#define regMMEA2_DRAM_WR_PRI_AGE 0x058c
+#define regMMEA2_DRAM_WR_PRI_AGE_BASE_IDX 0
+#define regMMEA2_DRAM_RD_PRI_QUEUING 0x058d
+#define regMMEA2_DRAM_RD_PRI_QUEUING_BASE_IDX 0
+#define regMMEA2_DRAM_WR_PRI_QUEUING 0x058e
+#define regMMEA2_DRAM_WR_PRI_QUEUING_BASE_IDX 0
+#define regMMEA2_DRAM_RD_PRI_FIXED 0x058f
+#define regMMEA2_DRAM_RD_PRI_FIXED_BASE_IDX 0
+#define regMMEA2_DRAM_WR_PRI_FIXED 0x0590
+#define regMMEA2_DRAM_WR_PRI_FIXED_BASE_IDX 0
+#define regMMEA2_DRAM_RD_PRI_URGENCY 0x0591
+#define regMMEA2_DRAM_RD_PRI_URGENCY_BASE_IDX 0
+#define regMMEA2_DRAM_WR_PRI_URGENCY 0x0592
+#define regMMEA2_DRAM_WR_PRI_URGENCY_BASE_IDX 0
+#define regMMEA2_DRAM_RD_PRI_QUANT_PRI1 0x0593
+#define regMMEA2_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA2_DRAM_RD_PRI_QUANT_PRI2 0x0594
+#define regMMEA2_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA2_DRAM_RD_PRI_QUANT_PRI3 0x0595
+#define regMMEA2_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA2_DRAM_WR_PRI_QUANT_PRI1 0x0596
+#define regMMEA2_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA2_DRAM_WR_PRI_QUANT_PRI2 0x0597
+#define regMMEA2_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA2_DRAM_WR_PRI_QUANT_PRI3 0x0598
+#define regMMEA2_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA2_GMI_RD_CLI2GRP_MAP0 0x0599
+#define regMMEA2_GMI_RD_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA2_GMI_RD_CLI2GRP_MAP1 0x059a
+#define regMMEA2_GMI_RD_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA2_GMI_WR_CLI2GRP_MAP0 0x059b
+#define regMMEA2_GMI_WR_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA2_GMI_WR_CLI2GRP_MAP1 0x059c
+#define regMMEA2_GMI_WR_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA2_GMI_RD_GRP2VC_MAP 0x059d
+#define regMMEA2_GMI_RD_GRP2VC_MAP_BASE_IDX 0
+#define regMMEA2_GMI_WR_GRP2VC_MAP 0x059e
+#define regMMEA2_GMI_WR_GRP2VC_MAP_BASE_IDX 0
+#define regMMEA2_GMI_RD_LAZY 0x059f
+#define regMMEA2_GMI_RD_LAZY_BASE_IDX 0
+#define regMMEA2_GMI_WR_LAZY 0x05a0
+#define regMMEA2_GMI_WR_LAZY_BASE_IDX 0
+#define regMMEA2_GMI_RD_CAM_CNTL 0x05a1
+#define regMMEA2_GMI_RD_CAM_CNTL_BASE_IDX 0
+#define regMMEA2_GMI_WR_CAM_CNTL 0x05a2
+#define regMMEA2_GMI_WR_CAM_CNTL_BASE_IDX 0
+#define regMMEA2_GMI_PAGE_BURST 0x05a3
+#define regMMEA2_GMI_PAGE_BURST_BASE_IDX 0
+#define regMMEA2_GMI_RD_PRI_AGE 0x05a4
+#define regMMEA2_GMI_RD_PRI_AGE_BASE_IDX 0
+#define regMMEA2_GMI_WR_PRI_AGE 0x05a5
+#define regMMEA2_GMI_WR_PRI_AGE_BASE_IDX 0
+#define regMMEA2_GMI_RD_PRI_QUEUING 0x05a6
+#define regMMEA2_GMI_RD_PRI_QUEUING_BASE_IDX 0
+#define regMMEA2_GMI_WR_PRI_QUEUING 0x05a7
+#define regMMEA2_GMI_WR_PRI_QUEUING_BASE_IDX 0
+#define regMMEA2_GMI_RD_PRI_FIXED 0x05a8
+#define regMMEA2_GMI_RD_PRI_FIXED_BASE_IDX 0
+#define regMMEA2_GMI_WR_PRI_FIXED 0x05a9
+#define regMMEA2_GMI_WR_PRI_FIXED_BASE_IDX 0
+#define regMMEA2_GMI_RD_PRI_URGENCY 0x05aa
+#define regMMEA2_GMI_RD_PRI_URGENCY_BASE_IDX 0
+#define regMMEA2_GMI_WR_PRI_URGENCY 0x05ab
+#define regMMEA2_GMI_WR_PRI_URGENCY_BASE_IDX 0
+#define regMMEA2_GMI_RD_PRI_URGENCY_MASKING 0x05ac
+#define regMMEA2_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 0
+#define regMMEA2_GMI_WR_PRI_URGENCY_MASKING 0x05ad
+#define regMMEA2_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 0
+#define regMMEA2_GMI_RD_PRI_QUANT_PRI1 0x05ae
+#define regMMEA2_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA2_GMI_RD_PRI_QUANT_PRI2 0x05af
+#define regMMEA2_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA2_GMI_RD_PRI_QUANT_PRI3 0x05b0
+#define regMMEA2_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA2_GMI_WR_PRI_QUANT_PRI1 0x05b1
+#define regMMEA2_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA2_GMI_WR_PRI_QUANT_PRI2 0x05b2
+#define regMMEA2_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA2_GMI_WR_PRI_QUANT_PRI3 0x05b3
+#define regMMEA2_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA2_ADDRNORM_BASE_ADDR0 0x05b4
+#define regMMEA2_ADDRNORM_BASE_ADDR0_BASE_IDX 0
+#define regMMEA2_ADDRNORM_LIMIT_ADDR0 0x05b5
+#define regMMEA2_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0
+#define regMMEA2_ADDRNORM_BASE_ADDR1 0x05b6
+#define regMMEA2_ADDRNORM_BASE_ADDR1_BASE_IDX 0
+#define regMMEA2_ADDRNORM_LIMIT_ADDR1 0x05b7
+#define regMMEA2_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0
+#define regMMEA2_ADDRNORM_OFFSET_ADDR1 0x05b8
+#define regMMEA2_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0
+#define regMMEA2_ADDRNORM_BASE_ADDR2 0x05b9
+#define regMMEA2_ADDRNORM_BASE_ADDR2_BASE_IDX 0
+#define regMMEA2_ADDRNORM_LIMIT_ADDR2 0x05ba
+#define regMMEA2_ADDRNORM_LIMIT_ADDR2_BASE_IDX 0
+#define regMMEA2_ADDRNORM_BASE_ADDR3 0x05bb
+#define regMMEA2_ADDRNORM_BASE_ADDR3_BASE_IDX 0
+#define regMMEA2_ADDRNORM_LIMIT_ADDR3 0x05bc
+#define regMMEA2_ADDRNORM_LIMIT_ADDR3_BASE_IDX 0
+#define regMMEA2_ADDRNORM_OFFSET_ADDR3 0x05bd
+#define regMMEA2_ADDRNORM_OFFSET_ADDR3_BASE_IDX 0
+#define regMMEA2_ADDRNORM_MEGABASE_ADDR0 0x05be
+#define regMMEA2_ADDRNORM_MEGABASE_ADDR0_BASE_IDX 0
+#define regMMEA2_ADDRNORM_MEGALIMIT_ADDR0 0x05bf
+#define regMMEA2_ADDRNORM_MEGALIMIT_ADDR0_BASE_IDX 0
+#define regMMEA2_ADDRNORM_MEGABASE_ADDR1 0x05c0
+#define regMMEA2_ADDRNORM_MEGABASE_ADDR1_BASE_IDX 0
+#define regMMEA2_ADDRNORM_MEGALIMIT_ADDR1 0x05c1
+#define regMMEA2_ADDRNORM_MEGALIMIT_ADDR1_BASE_IDX 0
+#define regMMEA2_ADDRNORMDRAM_HOLE_CNTL 0x05c3
+#define regMMEA2_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0
+#define regMMEA2_ADDRNORMGMI_HOLE_CNTL 0x05c4
+#define regMMEA2_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 0
+#define regMMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x05c5
+#define regMMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 0
+#define regMMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG 0x05c6
+#define regMMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 0
+#define regMMEA2_ADDRDEC_BANK_CFG 0x05c7
+#define regMMEA2_ADDRDEC_BANK_CFG_BASE_IDX 0
+#define regMMEA2_ADDRDEC_MISC_CFG 0x05c8
+#define regMMEA2_ADDRDEC_MISC_CFG_BASE_IDX 0
+#define regMMEA2_ADDRDECDRAM_HARVEST_ENABLE 0x05d3
+#define regMMEA2_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0
+#define regMMEA2_ADDRDECGMI_HARVEST_ENABLE 0x05de
+#define regMMEA2_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 0
+#define regMMEA2_ADDRDEC0_BASE_ADDR_CS0 0x05df
+#define regMMEA2_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0
+#define regMMEA2_ADDRDEC0_BASE_ADDR_CS1 0x05e0
+#define regMMEA2_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0
+#define regMMEA2_ADDRDEC0_BASE_ADDR_CS2 0x05e1
+#define regMMEA2_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0
+#define regMMEA2_ADDRDEC0_BASE_ADDR_CS3 0x05e2
+#define regMMEA2_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0
+#define regMMEA2_ADDRDEC0_BASE_ADDR_SECCS0 0x05e3
+#define regMMEA2_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0
+#define regMMEA2_ADDRDEC0_BASE_ADDR_SECCS1 0x05e4
+#define regMMEA2_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0
+#define regMMEA2_ADDRDEC0_BASE_ADDR_SECCS2 0x05e5
+#define regMMEA2_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0
+#define regMMEA2_ADDRDEC0_BASE_ADDR_SECCS3 0x05e6
+#define regMMEA2_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0
+#define regMMEA2_ADDRDEC0_ADDR_MASK_CS01 0x05e7
+#define regMMEA2_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0
+#define regMMEA2_ADDRDEC0_ADDR_MASK_CS23 0x05e8
+#define regMMEA2_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0
+#define regMMEA2_ADDRDEC0_ADDR_MASK_SECCS01 0x05e9
+#define regMMEA2_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0
+#define regMMEA2_ADDRDEC0_ADDR_MASK_SECCS23 0x05ea
+#define regMMEA2_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0
+#define regMMEA2_ADDRDEC0_ADDR_CFG_CS01 0x05eb
+#define regMMEA2_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0
+#define regMMEA2_ADDRDEC0_ADDR_CFG_CS23 0x05ec
+#define regMMEA2_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0
+#define regMMEA2_ADDRDEC0_ADDR_SEL_CS01 0x05ed
+#define regMMEA2_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0
+#define regMMEA2_ADDRDEC0_ADDR_SEL_CS23 0x05ee
+#define regMMEA2_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0
+#define regMMEA2_ADDRDEC0_ADDR_SEL2_CS01 0x05ef
+#define regMMEA2_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 0
+#define regMMEA2_ADDRDEC0_ADDR_SEL2_CS23 0x05f0
+#define regMMEA2_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 0
+#define regMMEA2_ADDRDEC0_COL_SEL_LO_CS01 0x05f1
+#define regMMEA2_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0
+#define regMMEA2_ADDRDEC0_COL_SEL_LO_CS23 0x05f2
+#define regMMEA2_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0
+#define regMMEA2_ADDRDEC0_COL_SEL_HI_CS01 0x05f3
+#define regMMEA2_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0
+#define regMMEA2_ADDRDEC0_COL_SEL_HI_CS23 0x05f4
+#define regMMEA2_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0
+#define regMMEA2_ADDRDEC0_RM_SEL_CS01 0x05f5
+#define regMMEA2_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0
+#define regMMEA2_ADDRDEC0_RM_SEL_CS23 0x05f6
+#define regMMEA2_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0
+#define regMMEA2_ADDRDEC0_RM_SEL_SECCS01 0x05f7
+#define regMMEA2_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0
+#define regMMEA2_ADDRDEC0_RM_SEL_SECCS23 0x05f8
+#define regMMEA2_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0
+#define regMMEA2_ADDRDEC1_BASE_ADDR_CS0 0x05f9
+#define regMMEA2_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0
+#define regMMEA2_ADDRDEC1_BASE_ADDR_CS1 0x05fa
+#define regMMEA2_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0
+#define regMMEA2_ADDRDEC1_BASE_ADDR_CS2 0x05fb
+#define regMMEA2_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0
+#define regMMEA2_ADDRDEC1_BASE_ADDR_CS3 0x05fc
+#define regMMEA2_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0
+#define regMMEA2_ADDRDEC1_BASE_ADDR_SECCS0 0x05fd
+#define regMMEA2_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0
+#define regMMEA2_ADDRDEC1_BASE_ADDR_SECCS1 0x05fe
+#define regMMEA2_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0
+#define regMMEA2_ADDRDEC1_BASE_ADDR_SECCS2 0x05ff
+#define regMMEA2_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0
+#define regMMEA2_ADDRDEC1_BASE_ADDR_SECCS3 0x0600
+#define regMMEA2_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0
+#define regMMEA2_ADDRDEC1_ADDR_MASK_CS01 0x0601
+#define regMMEA2_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0
+#define regMMEA2_ADDRDEC1_ADDR_MASK_CS23 0x0602
+#define regMMEA2_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0
+#define regMMEA2_ADDRDEC1_ADDR_MASK_SECCS01 0x0603
+#define regMMEA2_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0
+#define regMMEA2_ADDRDEC1_ADDR_MASK_SECCS23 0x0604
+#define regMMEA2_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0
+#define regMMEA2_ADDRDEC1_ADDR_CFG_CS01 0x0605
+#define regMMEA2_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0
+#define regMMEA2_ADDRDEC1_ADDR_CFG_CS23 0x0606
+#define regMMEA2_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0
+#define regMMEA2_ADDRDEC1_ADDR_SEL_CS01 0x0607
+#define regMMEA2_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0
+#define regMMEA2_ADDRDEC1_ADDR_SEL_CS23 0x0608
+#define regMMEA2_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0
+#define regMMEA2_ADDRDEC1_ADDR_SEL2_CS01 0x0609
+#define regMMEA2_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 0
+#define regMMEA2_ADDRDEC1_ADDR_SEL2_CS23 0x060a
+#define regMMEA2_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 0
+#define regMMEA2_ADDRDEC1_COL_SEL_LO_CS01 0x060b
+#define regMMEA2_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0
+#define regMMEA2_ADDRDEC1_COL_SEL_LO_CS23 0x060c
+#define regMMEA2_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0
+#define regMMEA2_ADDRDEC1_COL_SEL_HI_CS01 0x060d
+#define regMMEA2_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0
+#define regMMEA2_ADDRDEC1_COL_SEL_HI_CS23 0x060e
+#define regMMEA2_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0
+#define regMMEA2_ADDRDEC1_RM_SEL_CS01 0x060f
+#define regMMEA2_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0
+#define regMMEA2_ADDRDEC1_RM_SEL_CS23 0x0610
+#define regMMEA2_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0
+#define regMMEA2_ADDRDEC1_RM_SEL_SECCS01 0x0611
+#define regMMEA2_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0
+#define regMMEA2_ADDRDEC1_RM_SEL_SECCS23 0x0612
+#define regMMEA2_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0
+#define regMMEA2_ADDRDEC2_BASE_ADDR_CS0 0x0613
+#define regMMEA2_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 0
+#define regMMEA2_ADDRDEC2_BASE_ADDR_CS1 0x0614
+#define regMMEA2_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 0
+#define regMMEA2_ADDRDEC2_BASE_ADDR_CS2 0x0615
+#define regMMEA2_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 0
+#define regMMEA2_ADDRDEC2_BASE_ADDR_CS3 0x0616
+#define regMMEA2_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 0
+#define regMMEA2_ADDRDEC2_BASE_ADDR_SECCS0 0x0617
+#define regMMEA2_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 0
+#define regMMEA2_ADDRDEC2_BASE_ADDR_SECCS1 0x0618
+#define regMMEA2_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 0
+#define regMMEA2_ADDRDEC2_BASE_ADDR_SECCS2 0x0619
+#define regMMEA2_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 0
+#define regMMEA2_ADDRDEC2_BASE_ADDR_SECCS3 0x061a
+#define regMMEA2_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 0
+#define regMMEA2_ADDRDEC2_ADDR_MASK_CS01 0x061b
+#define regMMEA2_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 0
+#define regMMEA2_ADDRDEC2_ADDR_MASK_CS23 0x061c
+#define regMMEA2_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 0
+#define regMMEA2_ADDRDEC2_ADDR_MASK_SECCS01 0x061d
+#define regMMEA2_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 0
+#define regMMEA2_ADDRDEC2_ADDR_MASK_SECCS23 0x061e
+#define regMMEA2_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 0
+#define regMMEA2_ADDRDEC2_ADDR_CFG_CS01 0x061f
+#define regMMEA2_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 0
+#define regMMEA2_ADDRDEC2_ADDR_CFG_CS23 0x0620
+#define regMMEA2_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 0
+#define regMMEA2_ADDRDEC2_ADDR_SEL_CS01 0x0621
+#define regMMEA2_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 0
+#define regMMEA2_ADDRDEC2_ADDR_SEL_CS23 0x0622
+#define regMMEA2_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 0
+#define regMMEA2_ADDRDEC2_ADDR_SEL2_CS01 0x0623
+#define regMMEA2_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 0
+#define regMMEA2_ADDRDEC2_ADDR_SEL2_CS23 0x0624
+#define regMMEA2_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 0
+#define regMMEA2_ADDRDEC2_COL_SEL_LO_CS01 0x0625
+#define regMMEA2_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 0
+#define regMMEA2_ADDRDEC2_COL_SEL_LO_CS23 0x0626
+#define regMMEA2_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 0
+#define regMMEA2_ADDRDEC2_COL_SEL_HI_CS01 0x0627
+#define regMMEA2_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 0
+#define regMMEA2_ADDRDEC2_COL_SEL_HI_CS23 0x0628
+#define regMMEA2_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 0
+#define regMMEA2_ADDRDEC2_RM_SEL_CS01 0x0629
+#define regMMEA2_ADDRDEC2_RM_SEL_CS01_BASE_IDX 0
+#define regMMEA2_ADDRDEC2_RM_SEL_CS23 0x062a
+#define regMMEA2_ADDRDEC2_RM_SEL_CS23_BASE_IDX 0
+#define regMMEA2_ADDRDEC2_RM_SEL_SECCS01 0x062b
+#define regMMEA2_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 0
+#define regMMEA2_ADDRDEC2_RM_SEL_SECCS23 0x062c
+#define regMMEA2_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 0
+#define regMMEA2_ADDRNORMDRAM_GLOBAL_CNTL 0x062d
+#define regMMEA2_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 0
+#define regMMEA2_ADDRNORMGMI_GLOBAL_CNTL 0x062e
+#define regMMEA2_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 0
+#define regMMEA2_ADDRNORM_MEGACONTROL_ADDR0 0x0651
+#define regMMEA2_ADDRNORM_MEGACONTROL_ADDR0_BASE_IDX 0
+#define regMMEA2_ADDRNORM_MEGACONTROL_ADDR1 0x0652
+#define regMMEA2_ADDRNORM_MEGACONTROL_ADDR1_BASE_IDX 0
+#define regMMEA2_ADDRNORMDRAM_MASKING 0x0653
+#define regMMEA2_ADDRNORMDRAM_MASKING_BASE_IDX 0
+#define regMMEA2_ADDRNORMGMI_MASKING 0x0654
+#define regMMEA2_ADDRNORMGMI_MASKING_BASE_IDX 0
+#define regMMEA2_IO_RD_CLI2GRP_MAP0 0x0655
+#define regMMEA2_IO_RD_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA2_IO_RD_CLI2GRP_MAP1 0x0656
+#define regMMEA2_IO_RD_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA2_IO_WR_CLI2GRP_MAP0 0x0657
+#define regMMEA2_IO_WR_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA2_IO_WR_CLI2GRP_MAP1 0x0658
+#define regMMEA2_IO_WR_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA2_IO_RD_COMBINE_FLUSH 0x0659
+#define regMMEA2_IO_RD_COMBINE_FLUSH_BASE_IDX 0
+#define regMMEA2_IO_WR_COMBINE_FLUSH 0x065a
+#define regMMEA2_IO_WR_COMBINE_FLUSH_BASE_IDX 0
+#define regMMEA2_IO_GROUP_BURST 0x065b
+#define regMMEA2_IO_GROUP_BURST_BASE_IDX 0
+#define regMMEA2_IO_RD_PRI_AGE 0x065c
+#define regMMEA2_IO_RD_PRI_AGE_BASE_IDX 0
+#define regMMEA2_IO_WR_PRI_AGE 0x065d
+#define regMMEA2_IO_WR_PRI_AGE_BASE_IDX 0
+#define regMMEA2_IO_RD_PRI_QUEUING 0x065e
+#define regMMEA2_IO_RD_PRI_QUEUING_BASE_IDX 0
+#define regMMEA2_IO_WR_PRI_QUEUING 0x065f
+#define regMMEA2_IO_WR_PRI_QUEUING_BASE_IDX 0
+#define regMMEA2_IO_RD_PRI_FIXED 0x0660
+#define regMMEA2_IO_RD_PRI_FIXED_BASE_IDX 0
+#define regMMEA2_IO_WR_PRI_FIXED 0x0661
+#define regMMEA2_IO_WR_PRI_FIXED_BASE_IDX 0
+#define regMMEA2_IO_RD_PRI_URGENCY 0x0662
+#define regMMEA2_IO_RD_PRI_URGENCY_BASE_IDX 0
+#define regMMEA2_IO_WR_PRI_URGENCY 0x0663
+#define regMMEA2_IO_WR_PRI_URGENCY_BASE_IDX 0
+#define regMMEA2_IO_RD_PRI_URGENCY_MASKING 0x0664
+#define regMMEA2_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0
+#define regMMEA2_IO_WR_PRI_URGENCY_MASKING 0x0665
+#define regMMEA2_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0
+#define regMMEA2_IO_RD_PRI_QUANT_PRI1 0x0666
+#define regMMEA2_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA2_IO_RD_PRI_QUANT_PRI2 0x0667
+#define regMMEA2_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA2_IO_RD_PRI_QUANT_PRI3 0x0668
+#define regMMEA2_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA2_IO_WR_PRI_QUANT_PRI1 0x0669
+#define regMMEA2_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA2_IO_WR_PRI_QUANT_PRI2 0x066a
+#define regMMEA2_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA2_IO_WR_PRI_QUANT_PRI3 0x066b
+#define regMMEA2_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA2_SDP_ARB_DRAM 0x066c
+#define regMMEA2_SDP_ARB_DRAM_BASE_IDX 0
+#define regMMEA2_SDP_ARB_GMI 0x066d
+#define regMMEA2_SDP_ARB_GMI_BASE_IDX 0
+#define regMMEA2_SDP_ARB_FINAL 0x066e
+#define regMMEA2_SDP_ARB_FINAL_BASE_IDX 0
+#define regMMEA2_SDP_DRAM_PRIORITY 0x066f
+#define regMMEA2_SDP_DRAM_PRIORITY_BASE_IDX 0
+#define regMMEA2_SDP_GMI_PRIORITY 0x0670
+#define regMMEA2_SDP_GMI_PRIORITY_BASE_IDX 0
+#define regMMEA2_SDP_IO_PRIORITY 0x0671
+#define regMMEA2_SDP_IO_PRIORITY_BASE_IDX 0
+#define regMMEA2_SDP_CREDITS 0x0672
+#define regMMEA2_SDP_CREDITS_BASE_IDX 0
+#define regMMEA2_SDP_TAG_RESERVE0 0x0673
+#define regMMEA2_SDP_TAG_RESERVE0_BASE_IDX 0
+#define regMMEA2_SDP_TAG_RESERVE1 0x0674
+#define regMMEA2_SDP_TAG_RESERVE1_BASE_IDX 0
+#define regMMEA2_SDP_VCC_RESERVE0 0x0675
+#define regMMEA2_SDP_VCC_RESERVE0_BASE_IDX 0
+#define regMMEA2_SDP_VCC_RESERVE1 0x0676
+#define regMMEA2_SDP_VCC_RESERVE1_BASE_IDX 0
+#define regMMEA2_SDP_VCD_RESERVE0 0x0677
+#define regMMEA2_SDP_VCD_RESERVE0_BASE_IDX 0
+#define regMMEA2_SDP_VCD_RESERVE1 0x0678
+#define regMMEA2_SDP_VCD_RESERVE1_BASE_IDX 0
+#define regMMEA2_SDP_REQ_CNTL 0x0679
+#define regMMEA2_SDP_REQ_CNTL_BASE_IDX 0
+#define regMMEA2_MISC 0x067a
+#define regMMEA2_MISC_BASE_IDX 0
+#define regMMEA2_LATENCY_SAMPLING 0x067b
+#define regMMEA2_LATENCY_SAMPLING_BASE_IDX 0
+#define regMMEA2_PERFCOUNTER_LO 0x067c
+#define regMMEA2_PERFCOUNTER_LO_BASE_IDX 0
+#define regMMEA2_PERFCOUNTER_HI 0x067d
+#define regMMEA2_PERFCOUNTER_HI_BASE_IDX 0
+#define regMMEA2_PERFCOUNTER0_CFG 0x067e
+#define regMMEA2_PERFCOUNTER0_CFG_BASE_IDX 0
+#define regMMEA2_PERFCOUNTER1_CFG 0x067f
+#define regMMEA2_PERFCOUNTER1_CFG_BASE_IDX 0
+#define regMMEA2_PERFCOUNTER_RSLT_CNTL 0x0680
+#define regMMEA2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+#define regMMEA2_EDC_CNT 0x0686
+#define regMMEA2_EDC_CNT_BASE_IDX 0
+#define regMMEA2_EDC_CNT2 0x0687
+#define regMMEA2_EDC_CNT2_BASE_IDX 0
+#define regMMEA2_DSM_CNTL 0x0688
+#define regMMEA2_DSM_CNTL_BASE_IDX 0
+#define regMMEA2_DSM_CNTLA 0x0689
+#define regMMEA2_DSM_CNTLA_BASE_IDX 0
+#define regMMEA2_DSM_CNTLB 0x068a
+#define regMMEA2_DSM_CNTLB_BASE_IDX 0
+#define regMMEA2_DSM_CNTL2 0x068b
+#define regMMEA2_DSM_CNTL2_BASE_IDX 0
+#define regMMEA2_DSM_CNTL2A 0x068c
+#define regMMEA2_DSM_CNTL2A_BASE_IDX 0
+#define regMMEA2_DSM_CNTL2B 0x068d
+#define regMMEA2_DSM_CNTL2B_BASE_IDX 0
+#define regMMEA2_CGTT_CLK_CTRL 0x068f
+#define regMMEA2_CGTT_CLK_CTRL_BASE_IDX 0
+#define regMMEA2_EDC_MODE 0x0690
+#define regMMEA2_EDC_MODE_BASE_IDX 0
+#define regMMEA2_ERR_STATUS 0x0691
+#define regMMEA2_ERR_STATUS_BASE_IDX 0
+#define regMMEA2_MISC2 0x0692
+#define regMMEA2_MISC2_BASE_IDX 0
+#define regMMEA2_ADDRDEC_SELECT 0x0693
+#define regMMEA2_ADDRDEC_SELECT_BASE_IDX 0
+#define regMMEA2_EDC_CNT3 0x0694
+#define regMMEA2_EDC_CNT3_BASE_IDX 0
+#define regMMEA2_MISC_AON 0x0695
+#define regMMEA2_MISC_AON_BASE_IDX 0
+
+
+// addressBlock: mmhub_ea_mmeadec3
+// base address: 0x69b00
+#define regMMEA3_DRAM_RD_CLI2GRP_MAP0 0x06c0
+#define regMMEA3_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA3_DRAM_RD_CLI2GRP_MAP1 0x06c1
+#define regMMEA3_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA3_DRAM_WR_CLI2GRP_MAP0 0x06c2
+#define regMMEA3_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA3_DRAM_WR_CLI2GRP_MAP1 0x06c3
+#define regMMEA3_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA3_DRAM_RD_GRP2VC_MAP 0x06c4
+#define regMMEA3_DRAM_RD_GRP2VC_MAP_BASE_IDX 0
+#define regMMEA3_DRAM_WR_GRP2VC_MAP 0x06c5
+#define regMMEA3_DRAM_WR_GRP2VC_MAP_BASE_IDX 0
+#define regMMEA3_DRAM_RD_LAZY 0x06c6
+#define regMMEA3_DRAM_RD_LAZY_BASE_IDX 0
+#define regMMEA3_DRAM_WR_LAZY 0x06c7
+#define regMMEA3_DRAM_WR_LAZY_BASE_IDX 0
+#define regMMEA3_DRAM_RD_CAM_CNTL 0x06c8
+#define regMMEA3_DRAM_RD_CAM_CNTL_BASE_IDX 0
+#define regMMEA3_DRAM_WR_CAM_CNTL 0x06c9
+#define regMMEA3_DRAM_WR_CAM_CNTL_BASE_IDX 0
+#define regMMEA3_DRAM_PAGE_BURST 0x06ca
+#define regMMEA3_DRAM_PAGE_BURST_BASE_IDX 0
+#define regMMEA3_DRAM_RD_PRI_AGE 0x06cb
+#define regMMEA3_DRAM_RD_PRI_AGE_BASE_IDX 0
+#define regMMEA3_DRAM_WR_PRI_AGE 0x06cc
+#define regMMEA3_DRAM_WR_PRI_AGE_BASE_IDX 0
+#define regMMEA3_DRAM_RD_PRI_QUEUING 0x06cd
+#define regMMEA3_DRAM_RD_PRI_QUEUING_BASE_IDX 0
+#define regMMEA3_DRAM_WR_PRI_QUEUING 0x06ce
+#define regMMEA3_DRAM_WR_PRI_QUEUING_BASE_IDX 0
+#define regMMEA3_DRAM_RD_PRI_FIXED 0x06cf
+#define regMMEA3_DRAM_RD_PRI_FIXED_BASE_IDX 0
+#define regMMEA3_DRAM_WR_PRI_FIXED 0x06d0
+#define regMMEA3_DRAM_WR_PRI_FIXED_BASE_IDX 0
+#define regMMEA3_DRAM_RD_PRI_URGENCY 0x06d1
+#define regMMEA3_DRAM_RD_PRI_URGENCY_BASE_IDX 0
+#define regMMEA3_DRAM_WR_PRI_URGENCY 0x06d2
+#define regMMEA3_DRAM_WR_PRI_URGENCY_BASE_IDX 0
+#define regMMEA3_DRAM_RD_PRI_QUANT_PRI1 0x06d3
+#define regMMEA3_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA3_DRAM_RD_PRI_QUANT_PRI2 0x06d4
+#define regMMEA3_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA3_DRAM_RD_PRI_QUANT_PRI3 0x06d5
+#define regMMEA3_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA3_DRAM_WR_PRI_QUANT_PRI1 0x06d6
+#define regMMEA3_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA3_DRAM_WR_PRI_QUANT_PRI2 0x06d7
+#define regMMEA3_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA3_DRAM_WR_PRI_QUANT_PRI3 0x06d8
+#define regMMEA3_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA3_GMI_RD_CLI2GRP_MAP0 0x06d9
+#define regMMEA3_GMI_RD_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA3_GMI_RD_CLI2GRP_MAP1 0x06da
+#define regMMEA3_GMI_RD_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA3_GMI_WR_CLI2GRP_MAP0 0x06db
+#define regMMEA3_GMI_WR_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA3_GMI_WR_CLI2GRP_MAP1 0x06dc
+#define regMMEA3_GMI_WR_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA3_GMI_RD_GRP2VC_MAP 0x06dd
+#define regMMEA3_GMI_RD_GRP2VC_MAP_BASE_IDX 0
+#define regMMEA3_GMI_WR_GRP2VC_MAP 0x06de
+#define regMMEA3_GMI_WR_GRP2VC_MAP_BASE_IDX 0
+#define regMMEA3_GMI_RD_LAZY 0x06df
+#define regMMEA3_GMI_RD_LAZY_BASE_IDX 0
+#define regMMEA3_GMI_WR_LAZY 0x06e0
+#define regMMEA3_GMI_WR_LAZY_BASE_IDX 0
+#define regMMEA3_GMI_RD_CAM_CNTL 0x06e1
+#define regMMEA3_GMI_RD_CAM_CNTL_BASE_IDX 0
+#define regMMEA3_GMI_WR_CAM_CNTL 0x06e2
+#define regMMEA3_GMI_WR_CAM_CNTL_BASE_IDX 0
+#define regMMEA3_GMI_PAGE_BURST 0x06e3
+#define regMMEA3_GMI_PAGE_BURST_BASE_IDX 0
+#define regMMEA3_GMI_RD_PRI_AGE 0x06e4
+#define regMMEA3_GMI_RD_PRI_AGE_BASE_IDX 0
+#define regMMEA3_GMI_WR_PRI_AGE 0x06e5
+#define regMMEA3_GMI_WR_PRI_AGE_BASE_IDX 0
+#define regMMEA3_GMI_RD_PRI_QUEUING 0x06e6
+#define regMMEA3_GMI_RD_PRI_QUEUING_BASE_IDX 0
+#define regMMEA3_GMI_WR_PRI_QUEUING 0x06e7
+#define regMMEA3_GMI_WR_PRI_QUEUING_BASE_IDX 0
+#define regMMEA3_GMI_RD_PRI_FIXED 0x06e8
+#define regMMEA3_GMI_RD_PRI_FIXED_BASE_IDX 0
+#define regMMEA3_GMI_WR_PRI_FIXED 0x06e9
+#define regMMEA3_GMI_WR_PRI_FIXED_BASE_IDX 0
+#define regMMEA3_GMI_RD_PRI_URGENCY 0x06ea
+#define regMMEA3_GMI_RD_PRI_URGENCY_BASE_IDX 0
+#define regMMEA3_GMI_WR_PRI_URGENCY 0x06eb
+#define regMMEA3_GMI_WR_PRI_URGENCY_BASE_IDX 0
+#define regMMEA3_GMI_RD_PRI_URGENCY_MASKING 0x06ec
+#define regMMEA3_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 0
+#define regMMEA3_GMI_WR_PRI_URGENCY_MASKING 0x06ed
+#define regMMEA3_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 0
+#define regMMEA3_GMI_RD_PRI_QUANT_PRI1 0x06ee
+#define regMMEA3_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA3_GMI_RD_PRI_QUANT_PRI2 0x06ef
+#define regMMEA3_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA3_GMI_RD_PRI_QUANT_PRI3 0x06f0
+#define regMMEA3_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA3_GMI_WR_PRI_QUANT_PRI1 0x06f1
+#define regMMEA3_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA3_GMI_WR_PRI_QUANT_PRI2 0x06f2
+#define regMMEA3_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA3_GMI_WR_PRI_QUANT_PRI3 0x06f3
+#define regMMEA3_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA3_ADDRNORM_BASE_ADDR0 0x06f4
+#define regMMEA3_ADDRNORM_BASE_ADDR0_BASE_IDX 0
+#define regMMEA3_ADDRNORM_LIMIT_ADDR0 0x06f5
+#define regMMEA3_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0
+#define regMMEA3_ADDRNORM_BASE_ADDR1 0x06f6
+#define regMMEA3_ADDRNORM_BASE_ADDR1_BASE_IDX 0
+#define regMMEA3_ADDRNORM_LIMIT_ADDR1 0x06f7
+#define regMMEA3_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0
+#define regMMEA3_ADDRNORM_OFFSET_ADDR1 0x06f8
+#define regMMEA3_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0
+#define regMMEA3_ADDRNORM_BASE_ADDR2 0x06f9
+#define regMMEA3_ADDRNORM_BASE_ADDR2_BASE_IDX 0
+#define regMMEA3_ADDRNORM_LIMIT_ADDR2 0x06fa
+#define regMMEA3_ADDRNORM_LIMIT_ADDR2_BASE_IDX 0
+#define regMMEA3_ADDRNORM_BASE_ADDR3 0x06fb
+#define regMMEA3_ADDRNORM_BASE_ADDR3_BASE_IDX 0
+#define regMMEA3_ADDRNORM_LIMIT_ADDR3 0x06fc
+#define regMMEA3_ADDRNORM_LIMIT_ADDR3_BASE_IDX 0
+#define regMMEA3_ADDRNORM_OFFSET_ADDR3 0x06fd
+#define regMMEA3_ADDRNORM_OFFSET_ADDR3_BASE_IDX 0
+#define regMMEA3_ADDRNORM_MEGABASE_ADDR0 0x06fe
+#define regMMEA3_ADDRNORM_MEGABASE_ADDR0_BASE_IDX 0
+#define regMMEA3_ADDRNORM_MEGALIMIT_ADDR0 0x06ff
+#define regMMEA3_ADDRNORM_MEGALIMIT_ADDR0_BASE_IDX 0
+#define regMMEA3_ADDRNORM_MEGABASE_ADDR1 0x0700
+#define regMMEA3_ADDRNORM_MEGABASE_ADDR1_BASE_IDX 0
+#define regMMEA3_ADDRNORM_MEGALIMIT_ADDR1 0x0701
+#define regMMEA3_ADDRNORM_MEGALIMIT_ADDR1_BASE_IDX 0
+#define regMMEA3_ADDRNORMDRAM_HOLE_CNTL 0x0703
+#define regMMEA3_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0
+#define regMMEA3_ADDRNORMGMI_HOLE_CNTL 0x0704
+#define regMMEA3_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 0
+#define regMMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0705
+#define regMMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 0
+#define regMMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0706
+#define regMMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 0
+#define regMMEA3_ADDRDEC_BANK_CFG 0x0707
+#define regMMEA3_ADDRDEC_BANK_CFG_BASE_IDX 0
+#define regMMEA3_ADDRDEC_MISC_CFG 0x0708
+#define regMMEA3_ADDRDEC_MISC_CFG_BASE_IDX 0
+#define regMMEA3_ADDRDECDRAM_HARVEST_ENABLE 0x0713
+#define regMMEA3_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0
+#define regMMEA3_ADDRDECGMI_HARVEST_ENABLE 0x071e
+#define regMMEA3_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 0
+#define regMMEA3_ADDRDEC0_BASE_ADDR_CS0 0x071f
+#define regMMEA3_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0
+#define regMMEA3_ADDRDEC0_BASE_ADDR_CS1 0x0720
+#define regMMEA3_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0
+#define regMMEA3_ADDRDEC0_BASE_ADDR_CS2 0x0721
+#define regMMEA3_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0
+#define regMMEA3_ADDRDEC0_BASE_ADDR_CS3 0x0722
+#define regMMEA3_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0
+#define regMMEA3_ADDRDEC0_BASE_ADDR_SECCS0 0x0723
+#define regMMEA3_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0
+#define regMMEA3_ADDRDEC0_BASE_ADDR_SECCS1 0x0724
+#define regMMEA3_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0
+#define regMMEA3_ADDRDEC0_BASE_ADDR_SECCS2 0x0725
+#define regMMEA3_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0
+#define regMMEA3_ADDRDEC0_BASE_ADDR_SECCS3 0x0726
+#define regMMEA3_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0
+#define regMMEA3_ADDRDEC0_ADDR_MASK_CS01 0x0727
+#define regMMEA3_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0
+#define regMMEA3_ADDRDEC0_ADDR_MASK_CS23 0x0728
+#define regMMEA3_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0
+#define regMMEA3_ADDRDEC0_ADDR_MASK_SECCS01 0x0729
+#define regMMEA3_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0
+#define regMMEA3_ADDRDEC0_ADDR_MASK_SECCS23 0x072a
+#define regMMEA3_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0
+#define regMMEA3_ADDRDEC0_ADDR_CFG_CS01 0x072b
+#define regMMEA3_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0
+#define regMMEA3_ADDRDEC0_ADDR_CFG_CS23 0x072c
+#define regMMEA3_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0
+#define regMMEA3_ADDRDEC0_ADDR_SEL_CS01 0x072d
+#define regMMEA3_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0
+#define regMMEA3_ADDRDEC0_ADDR_SEL_CS23 0x072e
+#define regMMEA3_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0
+#define regMMEA3_ADDRDEC0_ADDR_SEL2_CS01 0x072f
+#define regMMEA3_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 0
+#define regMMEA3_ADDRDEC0_ADDR_SEL2_CS23 0x0730
+#define regMMEA3_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 0
+#define regMMEA3_ADDRDEC0_COL_SEL_LO_CS01 0x0731
+#define regMMEA3_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0
+#define regMMEA3_ADDRDEC0_COL_SEL_LO_CS23 0x0732
+#define regMMEA3_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0
+#define regMMEA3_ADDRDEC0_COL_SEL_HI_CS01 0x0733
+#define regMMEA3_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0
+#define regMMEA3_ADDRDEC0_COL_SEL_HI_CS23 0x0734
+#define regMMEA3_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0
+#define regMMEA3_ADDRDEC0_RM_SEL_CS01 0x0735
+#define regMMEA3_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0
+#define regMMEA3_ADDRDEC0_RM_SEL_CS23 0x0736
+#define regMMEA3_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0
+#define regMMEA3_ADDRDEC0_RM_SEL_SECCS01 0x0737
+#define regMMEA3_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0
+#define regMMEA3_ADDRDEC0_RM_SEL_SECCS23 0x0738
+#define regMMEA3_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0
+#define regMMEA3_ADDRDEC1_BASE_ADDR_CS0 0x0739
+#define regMMEA3_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0
+#define regMMEA3_ADDRDEC1_BASE_ADDR_CS1 0x073a
+#define regMMEA3_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0
+#define regMMEA3_ADDRDEC1_BASE_ADDR_CS2 0x073b
+#define regMMEA3_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0
+#define regMMEA3_ADDRDEC1_BASE_ADDR_CS3 0x073c
+#define regMMEA3_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0
+#define regMMEA3_ADDRDEC1_BASE_ADDR_SECCS0 0x073d
+#define regMMEA3_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0
+#define regMMEA3_ADDRDEC1_BASE_ADDR_SECCS1 0x073e
+#define regMMEA3_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0
+#define regMMEA3_ADDRDEC1_BASE_ADDR_SECCS2 0x073f
+#define regMMEA3_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0
+#define regMMEA3_ADDRDEC1_BASE_ADDR_SECCS3 0x0740
+#define regMMEA3_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0
+#define regMMEA3_ADDRDEC1_ADDR_MASK_CS01 0x0741
+#define regMMEA3_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0
+#define regMMEA3_ADDRDEC1_ADDR_MASK_CS23 0x0742
+#define regMMEA3_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0
+#define regMMEA3_ADDRDEC1_ADDR_MASK_SECCS01 0x0743
+#define regMMEA3_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0
+#define regMMEA3_ADDRDEC1_ADDR_MASK_SECCS23 0x0744
+#define regMMEA3_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0
+#define regMMEA3_ADDRDEC1_ADDR_CFG_CS01 0x0745
+#define regMMEA3_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0
+#define regMMEA3_ADDRDEC1_ADDR_CFG_CS23 0x0746
+#define regMMEA3_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0
+#define regMMEA3_ADDRDEC1_ADDR_SEL_CS01 0x0747
+#define regMMEA3_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0
+#define regMMEA3_ADDRDEC1_ADDR_SEL_CS23 0x0748
+#define regMMEA3_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0
+#define regMMEA3_ADDRDEC1_ADDR_SEL2_CS01 0x0749
+#define regMMEA3_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 0
+#define regMMEA3_ADDRDEC1_ADDR_SEL2_CS23 0x074a
+#define regMMEA3_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 0
+#define regMMEA3_ADDRDEC1_COL_SEL_LO_CS01 0x074b
+#define regMMEA3_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0
+#define regMMEA3_ADDRDEC1_COL_SEL_LO_CS23 0x074c
+#define regMMEA3_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0
+#define regMMEA3_ADDRDEC1_COL_SEL_HI_CS01 0x074d
+#define regMMEA3_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0
+#define regMMEA3_ADDRDEC1_COL_SEL_HI_CS23 0x074e
+#define regMMEA3_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0
+#define regMMEA3_ADDRDEC1_RM_SEL_CS01 0x074f
+#define regMMEA3_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0
+#define regMMEA3_ADDRDEC1_RM_SEL_CS23 0x0750
+#define regMMEA3_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0
+#define regMMEA3_ADDRDEC1_RM_SEL_SECCS01 0x0751
+#define regMMEA3_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0
+#define regMMEA3_ADDRDEC1_RM_SEL_SECCS23 0x0752
+#define regMMEA3_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0
+#define regMMEA3_ADDRDEC2_BASE_ADDR_CS0 0x0753
+#define regMMEA3_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 0
+#define regMMEA3_ADDRDEC2_BASE_ADDR_CS1 0x0754
+#define regMMEA3_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 0
+#define regMMEA3_ADDRDEC2_BASE_ADDR_CS2 0x0755
+#define regMMEA3_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 0
+#define regMMEA3_ADDRDEC2_BASE_ADDR_CS3 0x0756
+#define regMMEA3_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 0
+#define regMMEA3_ADDRDEC2_BASE_ADDR_SECCS0 0x0757
+#define regMMEA3_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 0
+#define regMMEA3_ADDRDEC2_BASE_ADDR_SECCS1 0x0758
+#define regMMEA3_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 0
+#define regMMEA3_ADDRDEC2_BASE_ADDR_SECCS2 0x0759
+#define regMMEA3_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 0
+#define regMMEA3_ADDRDEC2_BASE_ADDR_SECCS3 0x075a
+#define regMMEA3_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 0
+#define regMMEA3_ADDRDEC2_ADDR_MASK_CS01 0x075b
+#define regMMEA3_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 0
+#define regMMEA3_ADDRDEC2_ADDR_MASK_CS23 0x075c
+#define regMMEA3_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 0
+#define regMMEA3_ADDRDEC2_ADDR_MASK_SECCS01 0x075d
+#define regMMEA3_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 0
+#define regMMEA3_ADDRDEC2_ADDR_MASK_SECCS23 0x075e
+#define regMMEA3_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 0
+#define regMMEA3_ADDRDEC2_ADDR_CFG_CS01 0x075f
+#define regMMEA3_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 0
+#define regMMEA3_ADDRDEC2_ADDR_CFG_CS23 0x0760
+#define regMMEA3_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 0
+#define regMMEA3_ADDRDEC2_ADDR_SEL_CS01 0x0761
+#define regMMEA3_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 0
+#define regMMEA3_ADDRDEC2_ADDR_SEL_CS23 0x0762
+#define regMMEA3_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 0
+#define regMMEA3_ADDRDEC2_ADDR_SEL2_CS01 0x0763
+#define regMMEA3_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 0
+#define regMMEA3_ADDRDEC2_ADDR_SEL2_CS23 0x0764
+#define regMMEA3_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 0
+#define regMMEA3_ADDRDEC2_COL_SEL_LO_CS01 0x0765
+#define regMMEA3_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 0
+#define regMMEA3_ADDRDEC2_COL_SEL_LO_CS23 0x0766
+#define regMMEA3_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 0
+#define regMMEA3_ADDRDEC2_COL_SEL_HI_CS01 0x0767
+#define regMMEA3_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 0
+#define regMMEA3_ADDRDEC2_COL_SEL_HI_CS23 0x0768
+#define regMMEA3_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 0
+#define regMMEA3_ADDRDEC2_RM_SEL_CS01 0x0769
+#define regMMEA3_ADDRDEC2_RM_SEL_CS01_BASE_IDX 0
+#define regMMEA3_ADDRDEC2_RM_SEL_CS23 0x076a
+#define regMMEA3_ADDRDEC2_RM_SEL_CS23_BASE_IDX 0
+#define regMMEA3_ADDRDEC2_RM_SEL_SECCS01 0x076b
+#define regMMEA3_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 0
+#define regMMEA3_ADDRDEC2_RM_SEL_SECCS23 0x076c
+#define regMMEA3_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 0
+#define regMMEA3_ADDRNORMDRAM_GLOBAL_CNTL 0x076d
+#define regMMEA3_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 0
+#define regMMEA3_ADDRNORMGMI_GLOBAL_CNTL 0x076e
+#define regMMEA3_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 0
+#define regMMEA3_ADDRNORM_MEGACONTROL_ADDR0 0x0791
+#define regMMEA3_ADDRNORM_MEGACONTROL_ADDR0_BASE_IDX 0
+#define regMMEA3_ADDRNORM_MEGACONTROL_ADDR1 0x0792
+#define regMMEA3_ADDRNORM_MEGACONTROL_ADDR1_BASE_IDX 0
+#define regMMEA3_ADDRNORMDRAM_MASKING 0x0793
+#define regMMEA3_ADDRNORMDRAM_MASKING_BASE_IDX 0
+#define regMMEA3_ADDRNORMGMI_MASKING 0x0794
+#define regMMEA3_ADDRNORMGMI_MASKING_BASE_IDX 0
+#define regMMEA3_IO_RD_CLI2GRP_MAP0 0x0795
+#define regMMEA3_IO_RD_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA3_IO_RD_CLI2GRP_MAP1 0x0796
+#define regMMEA3_IO_RD_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA3_IO_WR_CLI2GRP_MAP0 0x0797
+#define regMMEA3_IO_WR_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA3_IO_WR_CLI2GRP_MAP1 0x0798
+#define regMMEA3_IO_WR_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA3_IO_RD_COMBINE_FLUSH 0x0799
+#define regMMEA3_IO_RD_COMBINE_FLUSH_BASE_IDX 0
+#define regMMEA3_IO_WR_COMBINE_FLUSH 0x079a
+#define regMMEA3_IO_WR_COMBINE_FLUSH_BASE_IDX 0
+#define regMMEA3_IO_GROUP_BURST 0x079b
+#define regMMEA3_IO_GROUP_BURST_BASE_IDX 0
+#define regMMEA3_IO_RD_PRI_AGE 0x079c
+#define regMMEA3_IO_RD_PRI_AGE_BASE_IDX 0
+#define regMMEA3_IO_WR_PRI_AGE 0x079d
+#define regMMEA3_IO_WR_PRI_AGE_BASE_IDX 0
+#define regMMEA3_IO_RD_PRI_QUEUING 0x079e
+#define regMMEA3_IO_RD_PRI_QUEUING_BASE_IDX 0
+#define regMMEA3_IO_WR_PRI_QUEUING 0x079f
+#define regMMEA3_IO_WR_PRI_QUEUING_BASE_IDX 0
+#define regMMEA3_IO_RD_PRI_FIXED 0x07a0
+#define regMMEA3_IO_RD_PRI_FIXED_BASE_IDX 0
+#define regMMEA3_IO_WR_PRI_FIXED 0x07a1
+#define regMMEA3_IO_WR_PRI_FIXED_BASE_IDX 0
+#define regMMEA3_IO_RD_PRI_URGENCY 0x07a2
+#define regMMEA3_IO_RD_PRI_URGENCY_BASE_IDX 0
+#define regMMEA3_IO_WR_PRI_URGENCY 0x07a3
+#define regMMEA3_IO_WR_PRI_URGENCY_BASE_IDX 0
+#define regMMEA3_IO_RD_PRI_URGENCY_MASKING 0x07a4
+#define regMMEA3_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0
+#define regMMEA3_IO_WR_PRI_URGENCY_MASKING 0x07a5
+#define regMMEA3_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0
+#define regMMEA3_IO_RD_PRI_QUANT_PRI1 0x07a6
+#define regMMEA3_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA3_IO_RD_PRI_QUANT_PRI2 0x07a7
+#define regMMEA3_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA3_IO_RD_PRI_QUANT_PRI3 0x07a8
+#define regMMEA3_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA3_IO_WR_PRI_QUANT_PRI1 0x07a9
+#define regMMEA3_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA3_IO_WR_PRI_QUANT_PRI2 0x07aa
+#define regMMEA3_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA3_IO_WR_PRI_QUANT_PRI3 0x07ab
+#define regMMEA3_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA3_SDP_ARB_DRAM 0x07ac
+#define regMMEA3_SDP_ARB_DRAM_BASE_IDX 0
+#define regMMEA3_SDP_ARB_GMI 0x07ad
+#define regMMEA3_SDP_ARB_GMI_BASE_IDX 0
+#define regMMEA3_SDP_ARB_FINAL 0x07ae
+#define regMMEA3_SDP_ARB_FINAL_BASE_IDX 0
+#define regMMEA3_SDP_DRAM_PRIORITY 0x07af
+#define regMMEA3_SDP_DRAM_PRIORITY_BASE_IDX 0
+#define regMMEA3_SDP_GMI_PRIORITY 0x07b0
+#define regMMEA3_SDP_GMI_PRIORITY_BASE_IDX 0
+#define regMMEA3_SDP_IO_PRIORITY 0x07b1
+#define regMMEA3_SDP_IO_PRIORITY_BASE_IDX 0
+#define regMMEA3_SDP_CREDITS 0x07b2
+#define regMMEA3_SDP_CREDITS_BASE_IDX 0
+#define regMMEA3_SDP_TAG_RESERVE0 0x07b3
+#define regMMEA3_SDP_TAG_RESERVE0_BASE_IDX 0
+#define regMMEA3_SDP_TAG_RESERVE1 0x07b4
+#define regMMEA3_SDP_TAG_RESERVE1_BASE_IDX 0
+#define regMMEA3_SDP_VCC_RESERVE0 0x07b5
+#define regMMEA3_SDP_VCC_RESERVE0_BASE_IDX 0
+#define regMMEA3_SDP_VCC_RESERVE1 0x07b6
+#define regMMEA3_SDP_VCC_RESERVE1_BASE_IDX 0
+#define regMMEA3_SDP_VCD_RESERVE0 0x07b7
+#define regMMEA3_SDP_VCD_RESERVE0_BASE_IDX 0
+#define regMMEA3_SDP_VCD_RESERVE1 0x07b8
+#define regMMEA3_SDP_VCD_RESERVE1_BASE_IDX 0
+#define regMMEA3_SDP_REQ_CNTL 0x07b9
+#define regMMEA3_SDP_REQ_CNTL_BASE_IDX 0
+#define regMMEA3_MISC 0x07ba
+#define regMMEA3_MISC_BASE_IDX 0
+#define regMMEA3_LATENCY_SAMPLING 0x07bb
+#define regMMEA3_LATENCY_SAMPLING_BASE_IDX 0
+#define regMMEA3_PERFCOUNTER_LO 0x07bc
+#define regMMEA3_PERFCOUNTER_LO_BASE_IDX 0
+#define regMMEA3_PERFCOUNTER_HI 0x07bd
+#define regMMEA3_PERFCOUNTER_HI_BASE_IDX 0
+#define regMMEA3_PERFCOUNTER0_CFG 0x07be
+#define regMMEA3_PERFCOUNTER0_CFG_BASE_IDX 0
+#define regMMEA3_PERFCOUNTER1_CFG 0x07bf
+#define regMMEA3_PERFCOUNTER1_CFG_BASE_IDX 0
+#define regMMEA3_PERFCOUNTER_RSLT_CNTL 0x07c0
+#define regMMEA3_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+#define regMMEA3_EDC_CNT 0x07c6
+#define regMMEA3_EDC_CNT_BASE_IDX 0
+#define regMMEA3_EDC_CNT2 0x07c7
+#define regMMEA3_EDC_CNT2_BASE_IDX 0
+#define regMMEA3_DSM_CNTL 0x07c8
+#define regMMEA3_DSM_CNTL_BASE_IDX 0
+#define regMMEA3_DSM_CNTLA 0x07c9
+#define regMMEA3_DSM_CNTLA_BASE_IDX 0
+#define regMMEA3_DSM_CNTLB 0x07ca
+#define regMMEA3_DSM_CNTLB_BASE_IDX 0
+#define regMMEA3_DSM_CNTL2 0x07cb
+#define regMMEA3_DSM_CNTL2_BASE_IDX 0
+#define regMMEA3_DSM_CNTL2A 0x07cc
+#define regMMEA3_DSM_CNTL2A_BASE_IDX 0
+#define regMMEA3_DSM_CNTL2B 0x07cd
+#define regMMEA3_DSM_CNTL2B_BASE_IDX 0
+#define regMMEA3_CGTT_CLK_CTRL 0x07cf
+#define regMMEA3_CGTT_CLK_CTRL_BASE_IDX 0
+#define regMMEA3_EDC_MODE 0x07d0
+#define regMMEA3_EDC_MODE_BASE_IDX 0
+#define regMMEA3_ERR_STATUS 0x07d1
+#define regMMEA3_ERR_STATUS_BASE_IDX 0
+#define regMMEA3_MISC2 0x07d2
+#define regMMEA3_MISC2_BASE_IDX 0
+#define regMMEA3_ADDRDEC_SELECT 0x07d3
+#define regMMEA3_ADDRDEC_SELECT_BASE_IDX 0
+#define regMMEA3_EDC_CNT3 0x07d4
+#define regMMEA3_EDC_CNT3_BASE_IDX 0
+#define regMMEA3_MISC_AON 0x07d5
+#define regMMEA3_MISC_AON_BASE_IDX 0
+
+
+// addressBlock: mmhub_ea_mmeadec4
+// base address: 0x6a000
+#define regMMEA4_DRAM_RD_CLI2GRP_MAP0 0x0800
+#define regMMEA4_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA4_DRAM_RD_CLI2GRP_MAP1 0x0801
+#define regMMEA4_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA4_DRAM_WR_CLI2GRP_MAP0 0x0802
+#define regMMEA4_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA4_DRAM_WR_CLI2GRP_MAP1 0x0803
+#define regMMEA4_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA4_DRAM_RD_GRP2VC_MAP 0x0804
+#define regMMEA4_DRAM_RD_GRP2VC_MAP_BASE_IDX 0
+#define regMMEA4_DRAM_WR_GRP2VC_MAP 0x0805
+#define regMMEA4_DRAM_WR_GRP2VC_MAP_BASE_IDX 0
+#define regMMEA4_DRAM_RD_LAZY 0x0806
+#define regMMEA4_DRAM_RD_LAZY_BASE_IDX 0
+#define regMMEA4_DRAM_WR_LAZY 0x0807
+#define regMMEA4_DRAM_WR_LAZY_BASE_IDX 0
+#define regMMEA4_DRAM_RD_CAM_CNTL 0x0808
+#define regMMEA4_DRAM_RD_CAM_CNTL_BASE_IDX 0
+#define regMMEA4_DRAM_WR_CAM_CNTL 0x0809
+#define regMMEA4_DRAM_WR_CAM_CNTL_BASE_IDX 0
+#define regMMEA4_DRAM_PAGE_BURST 0x080a
+#define regMMEA4_DRAM_PAGE_BURST_BASE_IDX 0
+#define regMMEA4_DRAM_RD_PRI_AGE 0x080b
+#define regMMEA4_DRAM_RD_PRI_AGE_BASE_IDX 0
+#define regMMEA4_DRAM_WR_PRI_AGE 0x080c
+#define regMMEA4_DRAM_WR_PRI_AGE_BASE_IDX 0
+#define regMMEA4_DRAM_RD_PRI_QUEUING 0x080d
+#define regMMEA4_DRAM_RD_PRI_QUEUING_BASE_IDX 0
+#define regMMEA4_DRAM_WR_PRI_QUEUING 0x080e
+#define regMMEA4_DRAM_WR_PRI_QUEUING_BASE_IDX 0
+#define regMMEA4_DRAM_RD_PRI_FIXED 0x080f
+#define regMMEA4_DRAM_RD_PRI_FIXED_BASE_IDX 0
+#define regMMEA4_DRAM_WR_PRI_FIXED 0x0810
+#define regMMEA4_DRAM_WR_PRI_FIXED_BASE_IDX 0
+#define regMMEA4_DRAM_RD_PRI_URGENCY 0x0811
+#define regMMEA4_DRAM_RD_PRI_URGENCY_BASE_IDX 0
+#define regMMEA4_DRAM_WR_PRI_URGENCY 0x0812
+#define regMMEA4_DRAM_WR_PRI_URGENCY_BASE_IDX 0
+#define regMMEA4_DRAM_RD_PRI_QUANT_PRI1 0x0813
+#define regMMEA4_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA4_DRAM_RD_PRI_QUANT_PRI2 0x0814
+#define regMMEA4_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA4_DRAM_RD_PRI_QUANT_PRI3 0x0815
+#define regMMEA4_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA4_DRAM_WR_PRI_QUANT_PRI1 0x0816
+#define regMMEA4_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA4_DRAM_WR_PRI_QUANT_PRI2 0x0817
+#define regMMEA4_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA4_DRAM_WR_PRI_QUANT_PRI3 0x0818
+#define regMMEA4_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA4_GMI_RD_CLI2GRP_MAP0 0x0819
+#define regMMEA4_GMI_RD_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA4_GMI_RD_CLI2GRP_MAP1 0x081a
+#define regMMEA4_GMI_RD_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA4_GMI_WR_CLI2GRP_MAP0 0x081b
+#define regMMEA4_GMI_WR_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA4_GMI_WR_CLI2GRP_MAP1 0x081c
+#define regMMEA4_GMI_WR_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA4_GMI_RD_GRP2VC_MAP 0x081d
+#define regMMEA4_GMI_RD_GRP2VC_MAP_BASE_IDX 0
+#define regMMEA4_GMI_WR_GRP2VC_MAP 0x081e
+#define regMMEA4_GMI_WR_GRP2VC_MAP_BASE_IDX 0
+#define regMMEA4_GMI_RD_LAZY 0x081f
+#define regMMEA4_GMI_RD_LAZY_BASE_IDX 0
+#define regMMEA4_GMI_WR_LAZY 0x0820
+#define regMMEA4_GMI_WR_LAZY_BASE_IDX 0
+#define regMMEA4_GMI_RD_CAM_CNTL 0x0821
+#define regMMEA4_GMI_RD_CAM_CNTL_BASE_IDX 0
+#define regMMEA4_GMI_WR_CAM_CNTL 0x0822
+#define regMMEA4_GMI_WR_CAM_CNTL_BASE_IDX 0
+#define regMMEA4_GMI_PAGE_BURST 0x0823
+#define regMMEA4_GMI_PAGE_BURST_BASE_IDX 0
+#define regMMEA4_GMI_RD_PRI_AGE 0x0824
+#define regMMEA4_GMI_RD_PRI_AGE_BASE_IDX 0
+#define regMMEA4_GMI_WR_PRI_AGE 0x0825
+#define regMMEA4_GMI_WR_PRI_AGE_BASE_IDX 0
+#define regMMEA4_GMI_RD_PRI_QUEUING 0x0826
+#define regMMEA4_GMI_RD_PRI_QUEUING_BASE_IDX 0
+#define regMMEA4_GMI_WR_PRI_QUEUING 0x0827
+#define regMMEA4_GMI_WR_PRI_QUEUING_BASE_IDX 0
+#define regMMEA4_GMI_RD_PRI_FIXED 0x0828
+#define regMMEA4_GMI_RD_PRI_FIXED_BASE_IDX 0
+#define regMMEA4_GMI_WR_PRI_FIXED 0x0829
+#define regMMEA4_GMI_WR_PRI_FIXED_BASE_IDX 0
+#define regMMEA4_GMI_RD_PRI_URGENCY 0x082a
+#define regMMEA4_GMI_RD_PRI_URGENCY_BASE_IDX 0
+#define regMMEA4_GMI_WR_PRI_URGENCY 0x082b
+#define regMMEA4_GMI_WR_PRI_URGENCY_BASE_IDX 0
+#define regMMEA4_GMI_RD_PRI_URGENCY_MASKING 0x082c
+#define regMMEA4_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 0
+#define regMMEA4_GMI_WR_PRI_URGENCY_MASKING 0x082d
+#define regMMEA4_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 0
+#define regMMEA4_GMI_RD_PRI_QUANT_PRI1 0x082e
+#define regMMEA4_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA4_GMI_RD_PRI_QUANT_PRI2 0x082f
+#define regMMEA4_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA4_GMI_RD_PRI_QUANT_PRI3 0x0830
+#define regMMEA4_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA4_GMI_WR_PRI_QUANT_PRI1 0x0831
+#define regMMEA4_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA4_GMI_WR_PRI_QUANT_PRI2 0x0832
+#define regMMEA4_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA4_GMI_WR_PRI_QUANT_PRI3 0x0833
+#define regMMEA4_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA4_ADDRNORM_BASE_ADDR0 0x0834
+#define regMMEA4_ADDRNORM_BASE_ADDR0_BASE_IDX 0
+#define regMMEA4_ADDRNORM_LIMIT_ADDR0 0x0835
+#define regMMEA4_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0
+#define regMMEA4_ADDRNORM_BASE_ADDR1 0x0836
+#define regMMEA4_ADDRNORM_BASE_ADDR1_BASE_IDX 0
+#define regMMEA4_ADDRNORM_LIMIT_ADDR1 0x0837
+#define regMMEA4_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0
+#define regMMEA4_ADDRNORM_OFFSET_ADDR1 0x0838
+#define regMMEA4_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0
+#define regMMEA4_ADDRNORM_BASE_ADDR2 0x0839
+#define regMMEA4_ADDRNORM_BASE_ADDR2_BASE_IDX 0
+#define regMMEA4_ADDRNORM_LIMIT_ADDR2 0x083a
+#define regMMEA4_ADDRNORM_LIMIT_ADDR2_BASE_IDX 0
+#define regMMEA4_ADDRNORM_BASE_ADDR3 0x083b
+#define regMMEA4_ADDRNORM_BASE_ADDR3_BASE_IDX 0
+#define regMMEA4_ADDRNORM_LIMIT_ADDR3 0x083c
+#define regMMEA4_ADDRNORM_LIMIT_ADDR3_BASE_IDX 0
+#define regMMEA4_ADDRNORM_OFFSET_ADDR3 0x083d
+#define regMMEA4_ADDRNORM_OFFSET_ADDR3_BASE_IDX 0
+#define regMMEA4_ADDRNORM_MEGABASE_ADDR0 0x083e
+#define regMMEA4_ADDRNORM_MEGABASE_ADDR0_BASE_IDX 0
+#define regMMEA4_ADDRNORM_MEGALIMIT_ADDR0 0x083f
+#define regMMEA4_ADDRNORM_MEGALIMIT_ADDR0_BASE_IDX 0
+#define regMMEA4_ADDRNORM_MEGABASE_ADDR1 0x0840
+#define regMMEA4_ADDRNORM_MEGABASE_ADDR1_BASE_IDX 0
+#define regMMEA4_ADDRNORM_MEGALIMIT_ADDR1 0x0841
+#define regMMEA4_ADDRNORM_MEGALIMIT_ADDR1_BASE_IDX 0
+#define regMMEA4_ADDRNORMDRAM_HOLE_CNTL 0x0843
+#define regMMEA4_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0
+#define regMMEA4_ADDRNORMGMI_HOLE_CNTL 0x0844
+#define regMMEA4_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 0
+#define regMMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0845
+#define regMMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 0
+#define regMMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0846
+#define regMMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 0
+#define regMMEA4_ADDRDEC_BANK_CFG 0x0847
+#define regMMEA4_ADDRDEC_BANK_CFG_BASE_IDX 0
+#define regMMEA4_ADDRDEC_MISC_CFG 0x0848
+#define regMMEA4_ADDRDEC_MISC_CFG_BASE_IDX 0
+#define regMMEA4_ADDRDECDRAM_HARVEST_ENABLE 0x0853
+#define regMMEA4_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0
+#define regMMEA4_ADDRDECGMI_HARVEST_ENABLE 0x085e
+#define regMMEA4_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 0
+#define regMMEA4_ADDRDEC0_BASE_ADDR_CS0 0x085f
+#define regMMEA4_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0
+#define regMMEA4_ADDRDEC0_BASE_ADDR_CS1 0x0860
+#define regMMEA4_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0
+#define regMMEA4_ADDRDEC0_BASE_ADDR_CS2 0x0861
+#define regMMEA4_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0
+#define regMMEA4_ADDRDEC0_BASE_ADDR_CS3 0x0862
+#define regMMEA4_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0
+#define regMMEA4_ADDRDEC0_BASE_ADDR_SECCS0 0x0863
+#define regMMEA4_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0
+#define regMMEA4_ADDRDEC0_BASE_ADDR_SECCS1 0x0864
+#define regMMEA4_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0
+#define regMMEA4_ADDRDEC0_BASE_ADDR_SECCS2 0x0865
+#define regMMEA4_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0
+#define regMMEA4_ADDRDEC0_BASE_ADDR_SECCS3 0x0866
+#define regMMEA4_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0
+#define regMMEA4_ADDRDEC0_ADDR_MASK_CS01 0x0867
+#define regMMEA4_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0
+#define regMMEA4_ADDRDEC0_ADDR_MASK_CS23 0x0868
+#define regMMEA4_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0
+#define regMMEA4_ADDRDEC0_ADDR_MASK_SECCS01 0x0869
+#define regMMEA4_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0
+#define regMMEA4_ADDRDEC0_ADDR_MASK_SECCS23 0x086a
+#define regMMEA4_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0
+#define regMMEA4_ADDRDEC0_ADDR_CFG_CS01 0x086b
+#define regMMEA4_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0
+#define regMMEA4_ADDRDEC0_ADDR_CFG_CS23 0x086c
+#define regMMEA4_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0
+#define regMMEA4_ADDRDEC0_ADDR_SEL_CS01 0x086d
+#define regMMEA4_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0
+#define regMMEA4_ADDRDEC0_ADDR_SEL_CS23 0x086e
+#define regMMEA4_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0
+#define regMMEA4_ADDRDEC0_ADDR_SEL2_CS01 0x086f
+#define regMMEA4_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 0
+#define regMMEA4_ADDRDEC0_ADDR_SEL2_CS23 0x0870
+#define regMMEA4_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 0
+#define regMMEA4_ADDRDEC0_COL_SEL_LO_CS01 0x0871
+#define regMMEA4_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0
+#define regMMEA4_ADDRDEC0_COL_SEL_LO_CS23 0x0872
+#define regMMEA4_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0
+#define regMMEA4_ADDRDEC0_COL_SEL_HI_CS01 0x0873
+#define regMMEA4_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0
+#define regMMEA4_ADDRDEC0_COL_SEL_HI_CS23 0x0874
+#define regMMEA4_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0
+#define regMMEA4_ADDRDEC0_RM_SEL_CS01 0x0875
+#define regMMEA4_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0
+#define regMMEA4_ADDRDEC0_RM_SEL_CS23 0x0876
+#define regMMEA4_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0
+#define regMMEA4_ADDRDEC0_RM_SEL_SECCS01 0x0877
+#define regMMEA4_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0
+#define regMMEA4_ADDRDEC0_RM_SEL_SECCS23 0x0878
+#define regMMEA4_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0
+#define regMMEA4_ADDRDEC1_BASE_ADDR_CS0 0x0879
+#define regMMEA4_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0
+#define regMMEA4_ADDRDEC1_BASE_ADDR_CS1 0x087a
+#define regMMEA4_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0
+#define regMMEA4_ADDRDEC1_BASE_ADDR_CS2 0x087b
+#define regMMEA4_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0
+#define regMMEA4_ADDRDEC1_BASE_ADDR_CS3 0x087c
+#define regMMEA4_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0
+#define regMMEA4_ADDRDEC1_BASE_ADDR_SECCS0 0x087d
+#define regMMEA4_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0
+#define regMMEA4_ADDRDEC1_BASE_ADDR_SECCS1 0x087e
+#define regMMEA4_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0
+#define regMMEA4_ADDRDEC1_BASE_ADDR_SECCS2 0x087f
+#define regMMEA4_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0
+#define regMMEA4_ADDRDEC1_BASE_ADDR_SECCS3 0x0880
+#define regMMEA4_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0
+#define regMMEA4_ADDRDEC1_ADDR_MASK_CS01 0x0881
+#define regMMEA4_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0
+#define regMMEA4_ADDRDEC1_ADDR_MASK_CS23 0x0882
+#define regMMEA4_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0
+#define regMMEA4_ADDRDEC1_ADDR_MASK_SECCS01 0x0883
+#define regMMEA4_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0
+#define regMMEA4_ADDRDEC1_ADDR_MASK_SECCS23 0x0884
+#define regMMEA4_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0
+#define regMMEA4_ADDRDEC1_ADDR_CFG_CS01 0x0885
+#define regMMEA4_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0
+#define regMMEA4_ADDRDEC1_ADDR_CFG_CS23 0x0886
+#define regMMEA4_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0
+#define regMMEA4_ADDRDEC1_ADDR_SEL_CS01 0x0887
+#define regMMEA4_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0
+#define regMMEA4_ADDRDEC1_ADDR_SEL_CS23 0x0888
+#define regMMEA4_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0
+#define regMMEA4_ADDRDEC1_ADDR_SEL2_CS01 0x0889
+#define regMMEA4_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 0
+#define regMMEA4_ADDRDEC1_ADDR_SEL2_CS23 0x088a
+#define regMMEA4_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 0
+#define regMMEA4_ADDRDEC1_COL_SEL_LO_CS01 0x088b
+#define regMMEA4_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0
+#define regMMEA4_ADDRDEC1_COL_SEL_LO_CS23 0x088c
+#define regMMEA4_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0
+#define regMMEA4_ADDRDEC1_COL_SEL_HI_CS01 0x088d
+#define regMMEA4_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0
+#define regMMEA4_ADDRDEC1_COL_SEL_HI_CS23 0x088e
+#define regMMEA4_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0
+#define regMMEA4_ADDRDEC1_RM_SEL_CS01 0x088f
+#define regMMEA4_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0
+#define regMMEA4_ADDRDEC1_RM_SEL_CS23 0x0890
+#define regMMEA4_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0
+#define regMMEA4_ADDRDEC1_RM_SEL_SECCS01 0x0891
+#define regMMEA4_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0
+#define regMMEA4_ADDRDEC1_RM_SEL_SECCS23 0x0892
+#define regMMEA4_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0
+#define regMMEA4_ADDRDEC2_BASE_ADDR_CS0 0x0893
+#define regMMEA4_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 0
+#define regMMEA4_ADDRDEC2_BASE_ADDR_CS1 0x0894
+#define regMMEA4_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 0
+#define regMMEA4_ADDRDEC2_BASE_ADDR_CS2 0x0895
+#define regMMEA4_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 0
+#define regMMEA4_ADDRDEC2_BASE_ADDR_CS3 0x0896
+#define regMMEA4_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 0
+#define regMMEA4_ADDRDEC2_BASE_ADDR_SECCS0 0x0897
+#define regMMEA4_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 0
+#define regMMEA4_ADDRDEC2_BASE_ADDR_SECCS1 0x0898
+#define regMMEA4_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 0
+#define regMMEA4_ADDRDEC2_BASE_ADDR_SECCS2 0x0899
+#define regMMEA4_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 0
+#define regMMEA4_ADDRDEC2_BASE_ADDR_SECCS3 0x089a
+#define regMMEA4_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 0
+#define regMMEA4_ADDRDEC2_ADDR_MASK_CS01 0x089b
+#define regMMEA4_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 0
+#define regMMEA4_ADDRDEC2_ADDR_MASK_CS23 0x089c
+#define regMMEA4_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 0
+#define regMMEA4_ADDRDEC2_ADDR_MASK_SECCS01 0x089d
+#define regMMEA4_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 0
+#define regMMEA4_ADDRDEC2_ADDR_MASK_SECCS23 0x089e
+#define regMMEA4_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 0
+#define regMMEA4_ADDRDEC2_ADDR_CFG_CS01 0x089f
+#define regMMEA4_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 0
+#define regMMEA4_ADDRDEC2_ADDR_CFG_CS23 0x08a0
+#define regMMEA4_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 0
+#define regMMEA4_ADDRDEC2_ADDR_SEL_CS01 0x08a1
+#define regMMEA4_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 0
+#define regMMEA4_ADDRDEC2_ADDR_SEL_CS23 0x08a2
+#define regMMEA4_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 0
+#define regMMEA4_ADDRDEC2_ADDR_SEL2_CS01 0x08a3
+#define regMMEA4_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 0
+#define regMMEA4_ADDRDEC2_ADDR_SEL2_CS23 0x08a4
+#define regMMEA4_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 0
+#define regMMEA4_ADDRDEC2_COL_SEL_LO_CS01 0x08a5
+#define regMMEA4_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 0
+#define regMMEA4_ADDRDEC2_COL_SEL_LO_CS23 0x08a6
+#define regMMEA4_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 0
+#define regMMEA4_ADDRDEC2_COL_SEL_HI_CS01 0x08a7
+#define regMMEA4_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 0
+#define regMMEA4_ADDRDEC2_COL_SEL_HI_CS23 0x08a8
+#define regMMEA4_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 0
+#define regMMEA4_ADDRDEC2_RM_SEL_CS01 0x08a9
+#define regMMEA4_ADDRDEC2_RM_SEL_CS01_BASE_IDX 0
+#define regMMEA4_ADDRDEC2_RM_SEL_CS23 0x08aa
+#define regMMEA4_ADDRDEC2_RM_SEL_CS23_BASE_IDX 0
+#define regMMEA4_ADDRDEC2_RM_SEL_SECCS01 0x08ab
+#define regMMEA4_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 0
+#define regMMEA4_ADDRDEC2_RM_SEL_SECCS23 0x08ac
+#define regMMEA4_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 0
+#define regMMEA4_ADDRNORMDRAM_GLOBAL_CNTL 0x08ad
+#define regMMEA4_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 0
+#define regMMEA4_ADDRNORMGMI_GLOBAL_CNTL 0x08ae
+#define regMMEA4_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 0
+#define regMMEA4_ADDRNORM_MEGACONTROL_ADDR0 0x08d1
+#define regMMEA4_ADDRNORM_MEGACONTROL_ADDR0_BASE_IDX 0
+#define regMMEA4_ADDRNORM_MEGACONTROL_ADDR1 0x08d2
+#define regMMEA4_ADDRNORM_MEGACONTROL_ADDR1_BASE_IDX 0
+#define regMMEA4_ADDRNORMDRAM_MASKING 0x08d3
+#define regMMEA4_ADDRNORMDRAM_MASKING_BASE_IDX 0
+#define regMMEA4_ADDRNORMGMI_MASKING 0x08d4
+#define regMMEA4_ADDRNORMGMI_MASKING_BASE_IDX 0
+#define regMMEA4_IO_RD_CLI2GRP_MAP0 0x08d5
+#define regMMEA4_IO_RD_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA4_IO_RD_CLI2GRP_MAP1 0x08d6
+#define regMMEA4_IO_RD_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA4_IO_WR_CLI2GRP_MAP0 0x08d7
+#define regMMEA4_IO_WR_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA4_IO_WR_CLI2GRP_MAP1 0x08d8
+#define regMMEA4_IO_WR_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA4_IO_RD_COMBINE_FLUSH 0x08d9
+#define regMMEA4_IO_RD_COMBINE_FLUSH_BASE_IDX 0
+#define regMMEA4_IO_WR_COMBINE_FLUSH 0x08da
+#define regMMEA4_IO_WR_COMBINE_FLUSH_BASE_IDX 0
+#define regMMEA4_IO_GROUP_BURST 0x08db
+#define regMMEA4_IO_GROUP_BURST_BASE_IDX 0
+#define regMMEA4_IO_RD_PRI_AGE 0x08dc
+#define regMMEA4_IO_RD_PRI_AGE_BASE_IDX 0
+#define regMMEA4_IO_WR_PRI_AGE 0x08dd
+#define regMMEA4_IO_WR_PRI_AGE_BASE_IDX 0
+#define regMMEA4_IO_RD_PRI_QUEUING 0x08de
+#define regMMEA4_IO_RD_PRI_QUEUING_BASE_IDX 0
+#define regMMEA4_IO_WR_PRI_QUEUING 0x08df
+#define regMMEA4_IO_WR_PRI_QUEUING_BASE_IDX 0
+#define regMMEA4_IO_RD_PRI_FIXED 0x08e0
+#define regMMEA4_IO_RD_PRI_FIXED_BASE_IDX 0
+#define regMMEA4_IO_WR_PRI_FIXED 0x08e1
+#define regMMEA4_IO_WR_PRI_FIXED_BASE_IDX 0
+#define regMMEA4_IO_RD_PRI_URGENCY 0x08e2
+#define regMMEA4_IO_RD_PRI_URGENCY_BASE_IDX 0
+#define regMMEA4_IO_WR_PRI_URGENCY 0x08e3
+#define regMMEA4_IO_WR_PRI_URGENCY_BASE_IDX 0
+#define regMMEA4_IO_RD_PRI_URGENCY_MASKING 0x08e4
+#define regMMEA4_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0
+#define regMMEA4_IO_WR_PRI_URGENCY_MASKING 0x08e5
+#define regMMEA4_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0
+#define regMMEA4_IO_RD_PRI_QUANT_PRI1 0x08e6
+#define regMMEA4_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA4_IO_RD_PRI_QUANT_PRI2 0x08e7
+#define regMMEA4_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA4_IO_RD_PRI_QUANT_PRI3 0x08e8
+#define regMMEA4_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA4_IO_WR_PRI_QUANT_PRI1 0x08e9
+#define regMMEA4_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA4_IO_WR_PRI_QUANT_PRI2 0x08ea
+#define regMMEA4_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA4_IO_WR_PRI_QUANT_PRI3 0x08eb
+#define regMMEA4_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA4_SDP_ARB_DRAM 0x08ec
+#define regMMEA4_SDP_ARB_DRAM_BASE_IDX 0
+#define regMMEA4_SDP_ARB_GMI 0x08ed
+#define regMMEA4_SDP_ARB_GMI_BASE_IDX 0
+#define regMMEA4_SDP_ARB_FINAL 0x08ee
+#define regMMEA4_SDP_ARB_FINAL_BASE_IDX 0
+#define regMMEA4_SDP_DRAM_PRIORITY 0x08ef
+#define regMMEA4_SDP_DRAM_PRIORITY_BASE_IDX 0
+#define regMMEA4_SDP_GMI_PRIORITY 0x08f0
+#define regMMEA4_SDP_GMI_PRIORITY_BASE_IDX 0
+#define regMMEA4_SDP_IO_PRIORITY 0x08f1
+#define regMMEA4_SDP_IO_PRIORITY_BASE_IDX 0
+#define regMMEA4_SDP_CREDITS 0x08f2
+#define regMMEA4_SDP_CREDITS_BASE_IDX 0
+#define regMMEA4_SDP_TAG_RESERVE0 0x08f3
+#define regMMEA4_SDP_TAG_RESERVE0_BASE_IDX 0
+#define regMMEA4_SDP_TAG_RESERVE1 0x08f4
+#define regMMEA4_SDP_TAG_RESERVE1_BASE_IDX 0
+#define regMMEA4_SDP_VCC_RESERVE0 0x08f5
+#define regMMEA4_SDP_VCC_RESERVE0_BASE_IDX 0
+#define regMMEA4_SDP_VCC_RESERVE1 0x08f6
+#define regMMEA4_SDP_VCC_RESERVE1_BASE_IDX 0
+#define regMMEA4_SDP_VCD_RESERVE0 0x08f7
+#define regMMEA4_SDP_VCD_RESERVE0_BASE_IDX 0
+#define regMMEA4_SDP_VCD_RESERVE1 0x08f8
+#define regMMEA4_SDP_VCD_RESERVE1_BASE_IDX 0
+#define regMMEA4_SDP_REQ_CNTL 0x08f9
+#define regMMEA4_SDP_REQ_CNTL_BASE_IDX 0
+#define regMMEA4_MISC 0x08fa
+#define regMMEA4_MISC_BASE_IDX 0
+#define regMMEA4_LATENCY_SAMPLING 0x08fb
+#define regMMEA4_LATENCY_SAMPLING_BASE_IDX 0
+#define regMMEA4_PERFCOUNTER_LO 0x08fc
+#define regMMEA4_PERFCOUNTER_LO_BASE_IDX 0
+#define regMMEA4_PERFCOUNTER_HI 0x08fd
+#define regMMEA4_PERFCOUNTER_HI_BASE_IDX 0
+#define regMMEA4_PERFCOUNTER0_CFG 0x08fe
+#define regMMEA4_PERFCOUNTER0_CFG_BASE_IDX 0
+#define regMMEA4_PERFCOUNTER1_CFG 0x08ff
+#define regMMEA4_PERFCOUNTER1_CFG_BASE_IDX 0
+#define regMMEA4_PERFCOUNTER_RSLT_CNTL 0x0900
+#define regMMEA4_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+#define regMMEA4_EDC_CNT 0x0906
+#define regMMEA4_EDC_CNT_BASE_IDX 0
+#define regMMEA4_EDC_CNT2 0x0907
+#define regMMEA4_EDC_CNT2_BASE_IDX 0
+#define regMMEA4_DSM_CNTL 0x0908
+#define regMMEA4_DSM_CNTL_BASE_IDX 0
+#define regMMEA4_DSM_CNTLA 0x0909
+#define regMMEA4_DSM_CNTLA_BASE_IDX 0
+#define regMMEA4_DSM_CNTLB 0x090a
+#define regMMEA4_DSM_CNTLB_BASE_IDX 0
+#define regMMEA4_DSM_CNTL2 0x090b
+#define regMMEA4_DSM_CNTL2_BASE_IDX 0
+#define regMMEA4_DSM_CNTL2A 0x090c
+#define regMMEA4_DSM_CNTL2A_BASE_IDX 0
+#define regMMEA4_DSM_CNTL2B 0x090d
+#define regMMEA4_DSM_CNTL2B_BASE_IDX 0
+#define regMMEA4_CGTT_CLK_CTRL 0x090f
+#define regMMEA4_CGTT_CLK_CTRL_BASE_IDX 0
+#define regMMEA4_EDC_MODE 0x0910
+#define regMMEA4_EDC_MODE_BASE_IDX 0
+#define regMMEA4_ERR_STATUS 0x0911
+#define regMMEA4_ERR_STATUS_BASE_IDX 0
+#define regMMEA4_MISC2 0x0912
+#define regMMEA4_MISC2_BASE_IDX 0
+#define regMMEA4_ADDRDEC_SELECT 0x0913
+#define regMMEA4_ADDRDEC_SELECT_BASE_IDX 0
+#define regMMEA4_EDC_CNT3 0x0914
+#define regMMEA4_EDC_CNT3_BASE_IDX 0
+#define regMMEA4_MISC_AON 0x0915
+#define regMMEA4_MISC_AON_BASE_IDX 0
+
+
+// addressBlock: mmhub_ea_mmeadec5
+// base address: 0x6a500
+#define regMMEA5_DRAM_RD_CLI2GRP_MAP0 0x0940
+#define regMMEA5_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA5_DRAM_RD_CLI2GRP_MAP1 0x0941
+#define regMMEA5_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA5_DRAM_WR_CLI2GRP_MAP0 0x0942
+#define regMMEA5_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA5_DRAM_WR_CLI2GRP_MAP1 0x0943
+#define regMMEA5_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA5_DRAM_RD_GRP2VC_MAP 0x0944
+#define regMMEA5_DRAM_RD_GRP2VC_MAP_BASE_IDX 0
+#define regMMEA5_DRAM_WR_GRP2VC_MAP 0x0945
+#define regMMEA5_DRAM_WR_GRP2VC_MAP_BASE_IDX 0
+#define regMMEA5_DRAM_RD_LAZY 0x0946
+#define regMMEA5_DRAM_RD_LAZY_BASE_IDX 0
+#define regMMEA5_DRAM_WR_LAZY 0x0947
+#define regMMEA5_DRAM_WR_LAZY_BASE_IDX 0
+#define regMMEA5_DRAM_RD_CAM_CNTL 0x0948
+#define regMMEA5_DRAM_RD_CAM_CNTL_BASE_IDX 0
+#define regMMEA5_DRAM_WR_CAM_CNTL 0x0949
+#define regMMEA5_DRAM_WR_CAM_CNTL_BASE_IDX 0
+#define regMMEA5_DRAM_PAGE_BURST 0x094a
+#define regMMEA5_DRAM_PAGE_BURST_BASE_IDX 0
+#define regMMEA5_DRAM_RD_PRI_AGE 0x094b
+#define regMMEA5_DRAM_RD_PRI_AGE_BASE_IDX 0
+#define regMMEA5_DRAM_WR_PRI_AGE 0x094c
+#define regMMEA5_DRAM_WR_PRI_AGE_BASE_IDX 0
+#define regMMEA5_DRAM_RD_PRI_QUEUING 0x094d
+#define regMMEA5_DRAM_RD_PRI_QUEUING_BASE_IDX 0
+#define regMMEA5_DRAM_WR_PRI_QUEUING 0x094e
+#define regMMEA5_DRAM_WR_PRI_QUEUING_BASE_IDX 0
+#define regMMEA5_DRAM_RD_PRI_FIXED 0x094f
+#define regMMEA5_DRAM_RD_PRI_FIXED_BASE_IDX 0
+#define regMMEA5_DRAM_WR_PRI_FIXED 0x0950
+#define regMMEA5_DRAM_WR_PRI_FIXED_BASE_IDX 0
+#define regMMEA5_DRAM_RD_PRI_URGENCY 0x0951
+#define regMMEA5_DRAM_RD_PRI_URGENCY_BASE_IDX 0
+#define regMMEA5_DRAM_WR_PRI_URGENCY 0x0952
+#define regMMEA5_DRAM_WR_PRI_URGENCY_BASE_IDX 0
+#define regMMEA5_DRAM_RD_PRI_QUANT_PRI1 0x0953
+#define regMMEA5_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA5_DRAM_RD_PRI_QUANT_PRI2 0x0954
+#define regMMEA5_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA5_DRAM_RD_PRI_QUANT_PRI3 0x0955
+#define regMMEA5_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA5_DRAM_WR_PRI_QUANT_PRI1 0x0956
+#define regMMEA5_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA5_DRAM_WR_PRI_QUANT_PRI2 0x0957
+#define regMMEA5_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA5_DRAM_WR_PRI_QUANT_PRI3 0x0958
+#define regMMEA5_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA5_GMI_RD_CLI2GRP_MAP0 0x0959
+#define regMMEA5_GMI_RD_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA5_GMI_RD_CLI2GRP_MAP1 0x095a
+#define regMMEA5_GMI_RD_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA5_GMI_WR_CLI2GRP_MAP0 0x095b
+#define regMMEA5_GMI_WR_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA5_GMI_WR_CLI2GRP_MAP1 0x095c
+#define regMMEA5_GMI_WR_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA5_GMI_RD_GRP2VC_MAP 0x095d
+#define regMMEA5_GMI_RD_GRP2VC_MAP_BASE_IDX 0
+#define regMMEA5_GMI_WR_GRP2VC_MAP 0x095e
+#define regMMEA5_GMI_WR_GRP2VC_MAP_BASE_IDX 0
+#define regMMEA5_GMI_RD_LAZY 0x095f
+#define regMMEA5_GMI_RD_LAZY_BASE_IDX 0
+#define regMMEA5_GMI_WR_LAZY 0x0960
+#define regMMEA5_GMI_WR_LAZY_BASE_IDX 0
+#define regMMEA5_GMI_RD_CAM_CNTL 0x0961
+#define regMMEA5_GMI_RD_CAM_CNTL_BASE_IDX 0
+#define regMMEA5_GMI_WR_CAM_CNTL 0x0962
+#define regMMEA5_GMI_WR_CAM_CNTL_BASE_IDX 0
+#define regMMEA5_GMI_PAGE_BURST 0x0963
+#define regMMEA5_GMI_PAGE_BURST_BASE_IDX 0
+#define regMMEA5_GMI_RD_PRI_AGE 0x0964
+#define regMMEA5_GMI_RD_PRI_AGE_BASE_IDX 0
+#define regMMEA5_GMI_WR_PRI_AGE 0x0965
+#define regMMEA5_GMI_WR_PRI_AGE_BASE_IDX 0
+#define regMMEA5_GMI_RD_PRI_QUEUING 0x0966
+#define regMMEA5_GMI_RD_PRI_QUEUING_BASE_IDX 0
+#define regMMEA5_GMI_WR_PRI_QUEUING 0x0967
+#define regMMEA5_GMI_WR_PRI_QUEUING_BASE_IDX 0
+#define regMMEA5_GMI_RD_PRI_FIXED 0x0968
+#define regMMEA5_GMI_RD_PRI_FIXED_BASE_IDX 0
+#define regMMEA5_GMI_WR_PRI_FIXED 0x0969
+#define regMMEA5_GMI_WR_PRI_FIXED_BASE_IDX 0
+#define regMMEA5_GMI_RD_PRI_URGENCY 0x096a
+#define regMMEA5_GMI_RD_PRI_URGENCY_BASE_IDX 0
+#define regMMEA5_GMI_WR_PRI_URGENCY 0x096b
+#define regMMEA5_GMI_WR_PRI_URGENCY_BASE_IDX 0
+#define regMMEA5_GMI_RD_PRI_URGENCY_MASKING 0x096c
+#define regMMEA5_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 0
+#define regMMEA5_GMI_WR_PRI_URGENCY_MASKING 0x096d
+#define regMMEA5_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 0
+#define regMMEA5_GMI_RD_PRI_QUANT_PRI1 0x096e
+#define regMMEA5_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA5_GMI_RD_PRI_QUANT_PRI2 0x096f
+#define regMMEA5_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA5_GMI_RD_PRI_QUANT_PRI3 0x0970
+#define regMMEA5_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA5_GMI_WR_PRI_QUANT_PRI1 0x0971
+#define regMMEA5_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA5_GMI_WR_PRI_QUANT_PRI2 0x0972
+#define regMMEA5_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA5_GMI_WR_PRI_QUANT_PRI3 0x0973
+#define regMMEA5_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA5_ADDRNORM_BASE_ADDR0 0x0974
+#define regMMEA5_ADDRNORM_BASE_ADDR0_BASE_IDX 0
+#define regMMEA5_ADDRNORM_LIMIT_ADDR0 0x0975
+#define regMMEA5_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0
+#define regMMEA5_ADDRNORM_BASE_ADDR1 0x0976
+#define regMMEA5_ADDRNORM_BASE_ADDR1_BASE_IDX 0
+#define regMMEA5_ADDRNORM_LIMIT_ADDR1 0x0977
+#define regMMEA5_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0
+#define regMMEA5_ADDRNORM_OFFSET_ADDR1 0x0978
+#define regMMEA5_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0
+#define regMMEA5_ADDRNORM_BASE_ADDR2 0x0979
+#define regMMEA5_ADDRNORM_BASE_ADDR2_BASE_IDX 0
+#define regMMEA5_ADDRNORM_LIMIT_ADDR2 0x097a
+#define regMMEA5_ADDRNORM_LIMIT_ADDR2_BASE_IDX 0
+#define regMMEA5_ADDRNORM_BASE_ADDR3 0x097b
+#define regMMEA5_ADDRNORM_BASE_ADDR3_BASE_IDX 0
+#define regMMEA5_ADDRNORM_LIMIT_ADDR3 0x097c
+#define regMMEA5_ADDRNORM_LIMIT_ADDR3_BASE_IDX 0
+#define regMMEA5_ADDRNORM_OFFSET_ADDR3 0x097d
+#define regMMEA5_ADDRNORM_OFFSET_ADDR3_BASE_IDX 0
+#define regMMEA5_ADDRNORM_MEGABASE_ADDR0 0x097e
+#define regMMEA5_ADDRNORM_MEGABASE_ADDR0_BASE_IDX 0
+#define regMMEA5_ADDRNORM_MEGALIMIT_ADDR0 0x097f
+#define regMMEA5_ADDRNORM_MEGALIMIT_ADDR0_BASE_IDX 0
+#define regMMEA5_ADDRNORM_MEGABASE_ADDR1 0x0980
+#define regMMEA5_ADDRNORM_MEGABASE_ADDR1_BASE_IDX 0
+#define regMMEA5_ADDRNORM_MEGALIMIT_ADDR1 0x0981
+#define regMMEA5_ADDRNORM_MEGALIMIT_ADDR1_BASE_IDX 0
+#define regMMEA5_ADDRNORMDRAM_HOLE_CNTL 0x0983
+#define regMMEA5_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0
+#define regMMEA5_ADDRNORMGMI_HOLE_CNTL 0x0984
+#define regMMEA5_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 0
+#define regMMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0985
+#define regMMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 0
+#define regMMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0986
+#define regMMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 0
+#define regMMEA5_ADDRDEC_BANK_CFG 0x0987
+#define regMMEA5_ADDRDEC_BANK_CFG_BASE_IDX 0
+#define regMMEA5_ADDRDEC_MISC_CFG 0x0988
+#define regMMEA5_ADDRDEC_MISC_CFG_BASE_IDX 0
+#define regMMEA5_ADDRDECDRAM_HARVEST_ENABLE 0x0993
+#define regMMEA5_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0
+#define regMMEA5_ADDRDECGMI_HARVEST_ENABLE 0x099e
+#define regMMEA5_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 0
+#define regMMEA5_ADDRDEC0_BASE_ADDR_CS0 0x099f
+#define regMMEA5_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0
+#define regMMEA5_ADDRDEC0_BASE_ADDR_CS1 0x09a0
+#define regMMEA5_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0
+#define regMMEA5_ADDRDEC0_BASE_ADDR_CS2 0x09a1
+#define regMMEA5_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0
+#define regMMEA5_ADDRDEC0_BASE_ADDR_CS3 0x09a2
+#define regMMEA5_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0
+#define regMMEA5_ADDRDEC0_BASE_ADDR_SECCS0 0x09a3
+#define regMMEA5_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0
+#define regMMEA5_ADDRDEC0_BASE_ADDR_SECCS1 0x09a4
+#define regMMEA5_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0
+#define regMMEA5_ADDRDEC0_BASE_ADDR_SECCS2 0x09a5
+#define regMMEA5_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0
+#define regMMEA5_ADDRDEC0_BASE_ADDR_SECCS3 0x09a6
+#define regMMEA5_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0
+#define regMMEA5_ADDRDEC0_ADDR_MASK_CS01 0x09a7
+#define regMMEA5_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0
+#define regMMEA5_ADDRDEC0_ADDR_MASK_CS23 0x09a8
+#define regMMEA5_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0
+#define regMMEA5_ADDRDEC0_ADDR_MASK_SECCS01 0x09a9
+#define regMMEA5_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0
+#define regMMEA5_ADDRDEC0_ADDR_MASK_SECCS23 0x09aa
+#define regMMEA5_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0
+#define regMMEA5_ADDRDEC0_ADDR_CFG_CS01 0x09ab
+#define regMMEA5_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0
+#define regMMEA5_ADDRDEC0_ADDR_CFG_CS23 0x09ac
+#define regMMEA5_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0
+#define regMMEA5_ADDRDEC0_ADDR_SEL_CS01 0x09ad
+#define regMMEA5_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0
+#define regMMEA5_ADDRDEC0_ADDR_SEL_CS23 0x09ae
+#define regMMEA5_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0
+#define regMMEA5_ADDRDEC0_ADDR_SEL2_CS01 0x09af
+#define regMMEA5_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 0
+#define regMMEA5_ADDRDEC0_ADDR_SEL2_CS23 0x09b0
+#define regMMEA5_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 0
+#define regMMEA5_ADDRDEC0_COL_SEL_LO_CS01 0x09b1
+#define regMMEA5_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0
+#define regMMEA5_ADDRDEC0_COL_SEL_LO_CS23 0x09b2
+#define regMMEA5_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0
+#define regMMEA5_ADDRDEC0_COL_SEL_HI_CS01 0x09b3
+#define regMMEA5_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0
+#define regMMEA5_ADDRDEC0_COL_SEL_HI_CS23 0x09b4
+#define regMMEA5_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0
+#define regMMEA5_ADDRDEC0_RM_SEL_CS01 0x09b5
+#define regMMEA5_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0
+#define regMMEA5_ADDRDEC0_RM_SEL_CS23 0x09b6
+#define regMMEA5_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0
+#define regMMEA5_ADDRDEC0_RM_SEL_SECCS01 0x09b7
+#define regMMEA5_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0
+#define regMMEA5_ADDRDEC0_RM_SEL_SECCS23 0x09b8
+#define regMMEA5_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0
+#define regMMEA5_ADDRDEC1_BASE_ADDR_CS0 0x09b9
+#define regMMEA5_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0
+#define regMMEA5_ADDRDEC1_BASE_ADDR_CS1 0x09ba
+#define regMMEA5_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0
+#define regMMEA5_ADDRDEC1_BASE_ADDR_CS2 0x09bb
+#define regMMEA5_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0
+#define regMMEA5_ADDRDEC1_BASE_ADDR_CS3 0x09bc
+#define regMMEA5_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0
+#define regMMEA5_ADDRDEC1_BASE_ADDR_SECCS0 0x09bd
+#define regMMEA5_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0
+#define regMMEA5_ADDRDEC1_BASE_ADDR_SECCS1 0x09be
+#define regMMEA5_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0
+#define regMMEA5_ADDRDEC1_BASE_ADDR_SECCS2 0x09bf
+#define regMMEA5_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0
+#define regMMEA5_ADDRDEC1_BASE_ADDR_SECCS3 0x09c0
+#define regMMEA5_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0
+#define regMMEA5_ADDRDEC1_ADDR_MASK_CS01 0x09c1
+#define regMMEA5_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0
+#define regMMEA5_ADDRDEC1_ADDR_MASK_CS23 0x09c2
+#define regMMEA5_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0
+#define regMMEA5_ADDRDEC1_ADDR_MASK_SECCS01 0x09c3
+#define regMMEA5_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0
+#define regMMEA5_ADDRDEC1_ADDR_MASK_SECCS23 0x09c4
+#define regMMEA5_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0
+#define regMMEA5_ADDRDEC1_ADDR_CFG_CS01 0x09c5
+#define regMMEA5_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0
+#define regMMEA5_ADDRDEC1_ADDR_CFG_CS23 0x09c6
+#define regMMEA5_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0
+#define regMMEA5_ADDRDEC1_ADDR_SEL_CS01 0x09c7
+#define regMMEA5_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0
+#define regMMEA5_ADDRDEC1_ADDR_SEL_CS23 0x09c8
+#define regMMEA5_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0
+#define regMMEA5_ADDRDEC1_ADDR_SEL2_CS01 0x09c9
+#define regMMEA5_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 0
+#define regMMEA5_ADDRDEC1_ADDR_SEL2_CS23 0x09ca
+#define regMMEA5_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 0
+#define regMMEA5_ADDRDEC1_COL_SEL_LO_CS01 0x09cb
+#define regMMEA5_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0
+#define regMMEA5_ADDRDEC1_COL_SEL_LO_CS23 0x09cc
+#define regMMEA5_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0
+#define regMMEA5_ADDRDEC1_COL_SEL_HI_CS01 0x09cd
+#define regMMEA5_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0
+#define regMMEA5_ADDRDEC1_COL_SEL_HI_CS23 0x09ce
+#define regMMEA5_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0
+#define regMMEA5_ADDRDEC1_RM_SEL_CS01 0x09cf
+#define regMMEA5_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0
+#define regMMEA5_ADDRDEC1_RM_SEL_CS23 0x09d0
+#define regMMEA5_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0
+#define regMMEA5_ADDRDEC1_RM_SEL_SECCS01 0x09d1
+#define regMMEA5_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0
+#define regMMEA5_ADDRDEC1_RM_SEL_SECCS23 0x09d2
+#define regMMEA5_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0
+#define regMMEA5_ADDRDEC2_BASE_ADDR_CS0 0x09d3
+#define regMMEA5_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 0
+#define regMMEA5_ADDRDEC2_BASE_ADDR_CS1 0x09d4
+#define regMMEA5_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 0
+#define regMMEA5_ADDRDEC2_BASE_ADDR_CS2 0x09d5
+#define regMMEA5_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 0
+#define regMMEA5_ADDRDEC2_BASE_ADDR_CS3 0x09d6
+#define regMMEA5_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 0
+#define regMMEA5_ADDRDEC2_BASE_ADDR_SECCS0 0x09d7
+#define regMMEA5_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 0
+#define regMMEA5_ADDRDEC2_BASE_ADDR_SECCS1 0x09d8
+#define regMMEA5_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 0
+#define regMMEA5_ADDRDEC2_BASE_ADDR_SECCS2 0x09d9
+#define regMMEA5_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 0
+#define regMMEA5_ADDRDEC2_BASE_ADDR_SECCS3 0x09da
+#define regMMEA5_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 0
+#define regMMEA5_ADDRDEC2_ADDR_MASK_CS01 0x09db
+#define regMMEA5_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 0
+#define regMMEA5_ADDRDEC2_ADDR_MASK_CS23 0x09dc
+#define regMMEA5_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 0
+#define regMMEA5_ADDRDEC2_ADDR_MASK_SECCS01 0x09dd
+#define regMMEA5_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 0
+#define regMMEA5_ADDRDEC2_ADDR_MASK_SECCS23 0x09de
+#define regMMEA5_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 0
+#define regMMEA5_ADDRDEC2_ADDR_CFG_CS01 0x09df
+#define regMMEA5_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 0
+#define regMMEA5_ADDRDEC2_ADDR_CFG_CS23 0x09e0
+#define regMMEA5_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 0
+#define regMMEA5_ADDRDEC2_ADDR_SEL_CS01 0x09e1
+#define regMMEA5_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 0
+#define regMMEA5_ADDRDEC2_ADDR_SEL_CS23 0x09e2
+#define regMMEA5_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 0
+#define regMMEA5_ADDRDEC2_ADDR_SEL2_CS01 0x09e3
+#define regMMEA5_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 0
+#define regMMEA5_ADDRDEC2_ADDR_SEL2_CS23 0x09e4
+#define regMMEA5_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 0
+#define regMMEA5_ADDRDEC2_COL_SEL_LO_CS01 0x09e5
+#define regMMEA5_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 0
+#define regMMEA5_ADDRDEC2_COL_SEL_LO_CS23 0x09e6
+#define regMMEA5_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 0
+#define regMMEA5_ADDRDEC2_COL_SEL_HI_CS01 0x09e7
+#define regMMEA5_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 0
+#define regMMEA5_ADDRDEC2_COL_SEL_HI_CS23 0x09e8
+#define regMMEA5_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 0
+#define regMMEA5_ADDRDEC2_RM_SEL_CS01 0x09e9
+#define regMMEA5_ADDRDEC2_RM_SEL_CS01_BASE_IDX 0
+#define regMMEA5_ADDRDEC2_RM_SEL_CS23 0x09ea
+#define regMMEA5_ADDRDEC2_RM_SEL_CS23_BASE_IDX 0
+#define regMMEA5_ADDRDEC2_RM_SEL_SECCS01 0x09eb
+#define regMMEA5_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 0
+#define regMMEA5_ADDRDEC2_RM_SEL_SECCS23 0x09ec
+#define regMMEA5_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 0
+#define regMMEA5_ADDRNORMDRAM_GLOBAL_CNTL 0x09ed
+#define regMMEA5_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 0
+#define regMMEA5_ADDRNORMGMI_GLOBAL_CNTL 0x09ee
+#define regMMEA5_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 0
+#define regMMEA5_ADDRNORM_MEGACONTROL_ADDR0 0x0a11
+#define regMMEA5_ADDRNORM_MEGACONTROL_ADDR0_BASE_IDX 0
+#define regMMEA5_ADDRNORM_MEGACONTROL_ADDR1 0x0a12
+#define regMMEA5_ADDRNORM_MEGACONTROL_ADDR1_BASE_IDX 0
+#define regMMEA5_ADDRNORMDRAM_MASKING 0x0a13
+#define regMMEA5_ADDRNORMDRAM_MASKING_BASE_IDX 0
+#define regMMEA5_ADDRNORMGMI_MASKING 0x0a14
+#define regMMEA5_ADDRNORMGMI_MASKING_BASE_IDX 0
+#define regMMEA5_IO_RD_CLI2GRP_MAP0 0x0a15
+#define regMMEA5_IO_RD_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA5_IO_RD_CLI2GRP_MAP1 0x0a16
+#define regMMEA5_IO_RD_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA5_IO_WR_CLI2GRP_MAP0 0x0a17
+#define regMMEA5_IO_WR_CLI2GRP_MAP0_BASE_IDX 0
+#define regMMEA5_IO_WR_CLI2GRP_MAP1 0x0a18
+#define regMMEA5_IO_WR_CLI2GRP_MAP1_BASE_IDX 0
+#define regMMEA5_IO_RD_COMBINE_FLUSH 0x0a19
+#define regMMEA5_IO_RD_COMBINE_FLUSH_BASE_IDX 0
+#define regMMEA5_IO_WR_COMBINE_FLUSH 0x0a1a
+#define regMMEA5_IO_WR_COMBINE_FLUSH_BASE_IDX 0
+#define regMMEA5_IO_GROUP_BURST 0x0a1b
+#define regMMEA5_IO_GROUP_BURST_BASE_IDX 0
+#define regMMEA5_IO_RD_PRI_AGE 0x0a1c
+#define regMMEA5_IO_RD_PRI_AGE_BASE_IDX 0
+#define regMMEA5_IO_WR_PRI_AGE 0x0a1d
+#define regMMEA5_IO_WR_PRI_AGE_BASE_IDX 0
+#define regMMEA5_IO_RD_PRI_QUEUING 0x0a1e
+#define regMMEA5_IO_RD_PRI_QUEUING_BASE_IDX 0
+#define regMMEA5_IO_WR_PRI_QUEUING 0x0a1f
+#define regMMEA5_IO_WR_PRI_QUEUING_BASE_IDX 0
+#define regMMEA5_IO_RD_PRI_FIXED 0x0a20
+#define regMMEA5_IO_RD_PRI_FIXED_BASE_IDX 0
+#define regMMEA5_IO_WR_PRI_FIXED 0x0a21
+#define regMMEA5_IO_WR_PRI_FIXED_BASE_IDX 0
+#define regMMEA5_IO_RD_PRI_URGENCY 0x0a22
+#define regMMEA5_IO_RD_PRI_URGENCY_BASE_IDX 0
+#define regMMEA5_IO_WR_PRI_URGENCY 0x0a23
+#define regMMEA5_IO_WR_PRI_URGENCY_BASE_IDX 0
+#define regMMEA5_IO_RD_PRI_URGENCY_MASKING 0x0a24
+#define regMMEA5_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0
+#define regMMEA5_IO_WR_PRI_URGENCY_MASKING 0x0a25
+#define regMMEA5_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0
+#define regMMEA5_IO_RD_PRI_QUANT_PRI1 0x0a26
+#define regMMEA5_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA5_IO_RD_PRI_QUANT_PRI2 0x0a27
+#define regMMEA5_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA5_IO_RD_PRI_QUANT_PRI3 0x0a28
+#define regMMEA5_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA5_IO_WR_PRI_QUANT_PRI1 0x0a29
+#define regMMEA5_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0
+#define regMMEA5_IO_WR_PRI_QUANT_PRI2 0x0a2a
+#define regMMEA5_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0
+#define regMMEA5_IO_WR_PRI_QUANT_PRI3 0x0a2b
+#define regMMEA5_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0
+#define regMMEA5_SDP_ARB_DRAM 0x0a2c
+#define regMMEA5_SDP_ARB_DRAM_BASE_IDX 0
+#define regMMEA5_SDP_ARB_GMI 0x0a2d
+#define regMMEA5_SDP_ARB_GMI_BASE_IDX 0
+#define regMMEA5_SDP_ARB_FINAL 0x0a2e
+#define regMMEA5_SDP_ARB_FINAL_BASE_IDX 0
+#define regMMEA5_SDP_DRAM_PRIORITY 0x0a2f
+#define regMMEA5_SDP_DRAM_PRIORITY_BASE_IDX 0
+#define regMMEA5_SDP_GMI_PRIORITY 0x0a30
+#define regMMEA5_SDP_GMI_PRIORITY_BASE_IDX 0
+#define regMMEA5_SDP_IO_PRIORITY 0x0a31
+#define regMMEA5_SDP_IO_PRIORITY_BASE_IDX 0
+#define regMMEA5_SDP_CREDITS 0x0a32
+#define regMMEA5_SDP_CREDITS_BASE_IDX 0
+#define regMMEA5_SDP_TAG_RESERVE0 0x0a33
+#define regMMEA5_SDP_TAG_RESERVE0_BASE_IDX 0
+#define regMMEA5_SDP_TAG_RESERVE1 0x0a34
+#define regMMEA5_SDP_TAG_RESERVE1_BASE_IDX 0
+#define regMMEA5_SDP_VCC_RESERVE0 0x0a35
+#define regMMEA5_SDP_VCC_RESERVE0_BASE_IDX 0
+#define regMMEA5_SDP_VCC_RESERVE1 0x0a36
+#define regMMEA5_SDP_VCC_RESERVE1_BASE_IDX 0
+#define regMMEA5_SDP_VCD_RESERVE0 0x0a37
+#define regMMEA5_SDP_VCD_RESERVE0_BASE_IDX 0
+#define regMMEA5_SDP_VCD_RESERVE1 0x0a38
+#define regMMEA5_SDP_VCD_RESERVE1_BASE_IDX 0
+#define regMMEA5_SDP_REQ_CNTL 0x0a39
+#define regMMEA5_SDP_REQ_CNTL_BASE_IDX 0
+#define regMMEA5_MISC 0x0a3a
+#define regMMEA5_MISC_BASE_IDX 0
+#define regMMEA5_LATENCY_SAMPLING 0x0a3b
+#define regMMEA5_LATENCY_SAMPLING_BASE_IDX 0
+#define regMMEA5_PERFCOUNTER_LO 0x0a3c
+#define regMMEA5_PERFCOUNTER_LO_BASE_IDX 0
+#define regMMEA5_PERFCOUNTER_HI 0x0a3d
+#define regMMEA5_PERFCOUNTER_HI_BASE_IDX 0
+#define regMMEA5_PERFCOUNTER0_CFG 0x0a3e
+#define regMMEA5_PERFCOUNTER0_CFG_BASE_IDX 0
+#define regMMEA5_PERFCOUNTER1_CFG 0x0a3f
+#define regMMEA5_PERFCOUNTER1_CFG_BASE_IDX 0
+#define regMMEA5_PERFCOUNTER_RSLT_CNTL 0x0a40
+#define regMMEA5_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+#define regMMEA5_EDC_CNT 0x0a46
+#define regMMEA5_EDC_CNT_BASE_IDX 0
+#define regMMEA5_EDC_CNT2 0x0a47
+#define regMMEA5_EDC_CNT2_BASE_IDX 0
+#define regMMEA5_DSM_CNTL 0x0a48
+#define regMMEA5_DSM_CNTL_BASE_IDX 0
+#define regMMEA5_DSM_CNTLA 0x0a49
+#define regMMEA5_DSM_CNTLA_BASE_IDX 0
+#define regMMEA5_DSM_CNTLB 0x0a4a
+#define regMMEA5_DSM_CNTLB_BASE_IDX 0
+#define regMMEA5_DSM_CNTL2 0x0a4b
+#define regMMEA5_DSM_CNTL2_BASE_IDX 0
+#define regMMEA5_DSM_CNTL2A 0x0a4c
+#define regMMEA5_DSM_CNTL2A_BASE_IDX 0
+#define regMMEA5_DSM_CNTL2B 0x0a4d
+#define regMMEA5_DSM_CNTL2B_BASE_IDX 0
+#define regMMEA5_CGTT_CLK_CTRL 0x0a4f
+#define regMMEA5_CGTT_CLK_CTRL_BASE_IDX 0
+#define regMMEA5_EDC_MODE 0x0a50
+#define regMMEA5_EDC_MODE_BASE_IDX 0
+#define regMMEA5_ERR_STATUS 0x0a51
+#define regMMEA5_ERR_STATUS_BASE_IDX 0
+#define regMMEA5_MISC2 0x0a52
+#define regMMEA5_MISC2_BASE_IDX 0
+#define regMMEA5_ADDRDEC_SELECT 0x0a53
+#define regMMEA5_ADDRDEC_SELECT_BASE_IDX 0
+#define regMMEA5_EDC_CNT3 0x0a54
+#define regMMEA5_EDC_CNT3_BASE_IDX 0
+#define regMMEA5_MISC_AON 0x0a55
+#define regMMEA5_MISC_AON_BASE_IDX 0
+
+
+// addressBlock: mmhub_l1tlb_vml1dec
+// base address: 0x6ac00
+#define regMC_VM_MX_L1_TLB0_STATUS 0x0b08
+#define regMC_VM_MX_L1_TLB0_STATUS_BASE_IDX 0
+#define regMC_VM_MX_L1_TLB1_STATUS 0x0b09
+#define regMC_VM_MX_L1_TLB1_STATUS_BASE_IDX 0
+#define regMC_VM_MX_L1_TLB2_STATUS 0x0b0a
+#define regMC_VM_MX_L1_TLB2_STATUS_BASE_IDX 0
+#define regMC_VM_MX_L1_TLB3_STATUS 0x0b0b
+#define regMC_VM_MX_L1_TLB3_STATUS_BASE_IDX 0
+#define regMC_VM_MX_L1_TLB4_STATUS 0x0b0c
+#define regMC_VM_MX_L1_TLB4_STATUS_BASE_IDX 0
+#define regMC_VM_MX_L1_TLB5_STATUS 0x0b0d
+#define regMC_VM_MX_L1_TLB5_STATUS_BASE_IDX 0
+#define regMC_VM_MX_L1_TLB6_STATUS 0x0b0e
+#define regMC_VM_MX_L1_TLB6_STATUS_BASE_IDX 0
+#define regMC_VM_MX_L1_TLB7_STATUS 0x0b0f
+#define regMC_VM_MX_L1_TLB7_STATUS_BASE_IDX 0
+
+
+// addressBlock: mmhub_l1tlb_vml1pldec
+// base address: 0x6ac80
+#define regMC_VM_MX_L1_PERFCOUNTER0_CFG 0x0b20
+#define regMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX 0
+#define regMC_VM_MX_L1_PERFCOUNTER1_CFG 0x0b21
+#define regMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX 0
+#define regMC_VM_MX_L1_PERFCOUNTER2_CFG 0x0b22
+#define regMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX 0
+#define regMC_VM_MX_L1_PERFCOUNTER3_CFG 0x0b23
+#define regMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX 0
+#define regMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0x0b24
+#define regMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+
+
+// addressBlock: mmhub_l1tlb_vml1prdec
+// base address: 0x6acc0
+#define regMC_VM_MX_L1_PERFCOUNTER_LO 0x0b30
+#define regMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX 0
+#define regMC_VM_MX_L1_PERFCOUNTER_HI 0x0b31
+#define regMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX 0
+
+
+// addressBlock: mmhub_pctldec0
+// base address: 0x6aa00
+#define regPCTL0_CTRL 0x0a80
+#define regPCTL0_CTRL_BASE_IDX 0
+#define regPCTL0_MMHUB_DEEPSLEEP_IB 0x0a81
+#define regPCTL0_MMHUB_DEEPSLEEP_IB_BASE_IDX 0
+#define regPCTL0_MMHUB_DEEPSLEEP_OVERRIDE 0x0a82
+#define regPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 0
+#define regPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB 0x0a83
+#define regPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX 0
+#define regPCTL0_PG_IGNORE_DEEPSLEEP 0x0a84
+#define regPCTL0_PG_IGNORE_DEEPSLEEP_BASE_IDX 0
+#define regPCTL0_PG_IGNORE_DEEPSLEEP_IB 0x0a85
+#define regPCTL0_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX 0
+#define regPCTL0_SLICE0_CFG_DAGB_BUSY 0x0a86
+#define regPCTL0_SLICE0_CFG_DAGB_BUSY_BASE_IDX 0
+#define regPCTL0_SLICE0_CFG_DS_ALLOW 0x0a87
+#define regPCTL0_SLICE0_CFG_DS_ALLOW_BASE_IDX 0
+#define regPCTL0_SLICE0_CFG_DS_ALLOW_IB 0x0a88
+#define regPCTL0_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX 0
+#define regPCTL0_SLICE1_CFG_DAGB_BUSY 0x0a89
+#define regPCTL0_SLICE1_CFG_DAGB_BUSY_BASE_IDX 0
+#define regPCTL0_SLICE1_CFG_DS_ALLOW 0x0a8a
+#define regPCTL0_SLICE1_CFG_DS_ALLOW_BASE_IDX 0
+#define regPCTL0_SLICE1_CFG_DS_ALLOW_IB 0x0a8b
+#define regPCTL0_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX 0
+#define regPCTL0_SLICE2_CFG_DAGB_BUSY 0x0a8c
+#define regPCTL0_SLICE2_CFG_DAGB_BUSY_BASE_IDX 0
+#define regPCTL0_SLICE2_CFG_DS_ALLOW 0x0a8d
+#define regPCTL0_SLICE2_CFG_DS_ALLOW_BASE_IDX 0
+#define regPCTL0_SLICE2_CFG_DS_ALLOW_IB 0x0a8e
+#define regPCTL0_SLICE2_CFG_DS_ALLOW_IB_BASE_IDX 0
+#define regPCTL0_SLICE3_CFG_DAGB_BUSY 0x0a8f
+#define regPCTL0_SLICE3_CFG_DAGB_BUSY_BASE_IDX 0
+#define regPCTL0_SLICE3_CFG_DS_ALLOW 0x0a90
+#define regPCTL0_SLICE3_CFG_DS_ALLOW_BASE_IDX 0
+#define regPCTL0_SLICE3_CFG_DS_ALLOW_IB 0x0a91
+#define regPCTL0_SLICE3_CFG_DS_ALLOW_IB_BASE_IDX 0
+#define regPCTL0_SLICE4_CFG_DAGB_BUSY 0x0a92
+#define regPCTL0_SLICE4_CFG_DAGB_BUSY_BASE_IDX 0
+#define regPCTL0_SLICE4_CFG_DS_ALLOW 0x0a93
+#define regPCTL0_SLICE4_CFG_DS_ALLOW_BASE_IDX 0
+#define regPCTL0_SLICE4_CFG_DS_ALLOW_IB 0x0a94
+#define regPCTL0_SLICE4_CFG_DS_ALLOW_IB_BASE_IDX 0
+#define regPCTL0_SLICE5_CFG_DAGB_BUSY 0x0a95
+#define regPCTL0_SLICE5_CFG_DAGB_BUSY_BASE_IDX 0
+#define regPCTL0_SLICE5_CFG_DS_ALLOW 0x0a96
+#define regPCTL0_SLICE5_CFG_DS_ALLOW_BASE_IDX 0
+#define regPCTL0_SLICE5_CFG_DS_ALLOW_IB 0x0a97
+#define regPCTL0_SLICE5_CFG_DS_ALLOW_IB_BASE_IDX 0
+#define regPCTL0_UTCL2_MISC 0x0a98
+#define regPCTL0_UTCL2_MISC_BASE_IDX 0
+#define regPCTL0_SLICE0_MISC 0x0a99
+#define regPCTL0_SLICE0_MISC_BASE_IDX 0
+#define regPCTL0_SLICE1_MISC 0x0a9a
+#define regPCTL0_SLICE1_MISC_BASE_IDX 0
+#define regPCTL0_SLICE2_MISC 0x0a9b
+#define regPCTL0_SLICE2_MISC_BASE_IDX 0
+#define regPCTL0_SLICE3_MISC 0x0a9c
+#define regPCTL0_SLICE3_MISC_BASE_IDX 0
+#define regPCTL0_SLICE4_MISC 0x0a9d
+#define regPCTL0_SLICE4_MISC_BASE_IDX 0
+#define regPCTL0_SLICE5_MISC 0x0a9e
+#define regPCTL0_SLICE5_MISC_BASE_IDX 0
+
+
+// addressBlock: mmhub_utcl2_atcl2dec
+// base address: 0x6ad00
+#define regATC_L2_CNTL 0x0b40
+#define regATC_L2_CNTL_BASE_IDX 0
+#define regATC_L2_CNTL2 0x0b41
+#define regATC_L2_CNTL2_BASE_IDX 0
+#define regATC_L2_CACHE_DATA0 0x0b44
+#define regATC_L2_CACHE_DATA0_BASE_IDX 0
+#define regATC_L2_CACHE_DATA1 0x0b45
+#define regATC_L2_CACHE_DATA1_BASE_IDX 0
+#define regATC_L2_CACHE_DATA2 0x0b46
+#define regATC_L2_CACHE_DATA2_BASE_IDX 0
+#define regATC_L2_CACHE_DATA3 0x0b47
+#define regATC_L2_CACHE_DATA3_BASE_IDX 0
+#define regATC_L2_CNTL3 0x0b48
+#define regATC_L2_CNTL3_BASE_IDX 0
+#define regATC_L2_STATUS 0x0b49
+#define regATC_L2_STATUS_BASE_IDX 0
+#define regATC_L2_STATUS2 0x0b4a
+#define regATC_L2_STATUS2_BASE_IDX 0
+#define regATC_L2_MISC_CG 0x0b4b
+#define regATC_L2_MISC_CG_BASE_IDX 0
+#define regATC_L2_MEM_POWER_LS 0x0b4c
+#define regATC_L2_MEM_POWER_LS_BASE_IDX 0
+#define regATC_L2_CGTT_CLK_CTRL 0x0b4d
+#define regATC_L2_CGTT_CLK_CTRL_BASE_IDX 0
+#define regATC_L2_CACHE_4K_DSM_INDEX 0x0b4e
+#define regATC_L2_CACHE_4K_DSM_INDEX_BASE_IDX 0
+#define regATC_L2_CACHE_32K_DSM_INDEX 0x0b4f
+#define regATC_L2_CACHE_32K_DSM_INDEX_BASE_IDX 0
+#define regATC_L2_CACHE_2M_DSM_INDEX 0x0b50
+#define regATC_L2_CACHE_2M_DSM_INDEX_BASE_IDX 0
+#define regATC_L2_CACHE_4K_DSM_CNTL 0x0b51
+#define regATC_L2_CACHE_4K_DSM_CNTL_BASE_IDX 0
+#define regATC_L2_CACHE_32K_DSM_CNTL 0x0b52
+#define regATC_L2_CACHE_32K_DSM_CNTL_BASE_IDX 0
+#define regATC_L2_CACHE_2M_DSM_CNTL 0x0b53
+#define regATC_L2_CACHE_2M_DSM_CNTL_BASE_IDX 0
+#define regATC_L2_CNTL4 0x0b54
+#define regATC_L2_CNTL4_BASE_IDX 0
+#define regATC_L2_MM_GROUP_RT_CLASSES 0x0b55
+#define regATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0
+
+
+// addressBlock: mmhub_utcl2_atcl2pfcntldec
+// base address: 0x6b4d0
+#define regATC_L2_PERFCOUNTER0_CFG 0x0d34
+#define regATC_L2_PERFCOUNTER0_CFG_BASE_IDX 0
+#define regATC_L2_PERFCOUNTER1_CFG 0x0d35
+#define regATC_L2_PERFCOUNTER1_CFG_BASE_IDX 0
+#define regATC_L2_PERFCOUNTER_RSLT_CNTL 0x0d36
+#define regATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+
+
+// addressBlock: mmhub_utcl2_atcl2pfcntrdec
+// base address: 0x6b4c0
+#define regATC_L2_PERFCOUNTER_LO 0x0d30
+#define regATC_L2_PERFCOUNTER_LO_BASE_IDX 0
+#define regATC_L2_PERFCOUNTER_HI 0x0d31
+#define regATC_L2_PERFCOUNTER_HI_BASE_IDX 0
+
+
+// addressBlock: mmhub_utcl2_l2tlbdec
+// base address: 0x6b580
+#define regL2TLB_TLB0_STATUS 0x0d61
+#define regL2TLB_TLB0_STATUS_BASE_IDX 0
+#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO 0x0d63
+#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX 0
+#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI 0x0d64
+#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX 0
+#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO 0x0d65
+#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX 0
+#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI 0x0d66
+#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX 0
+
+
+// addressBlock: mmhub_utcl2_l2tlbpldec
+// base address: 0x6b5a0
+#define regL2TLB_PERFCOUNTER0_CFG 0x0d68
+#define regL2TLB_PERFCOUNTER0_CFG_BASE_IDX 0
+#define regL2TLB_PERFCOUNTER1_CFG 0x0d69
+#define regL2TLB_PERFCOUNTER1_CFG_BASE_IDX 0
+#define regL2TLB_PERFCOUNTER2_CFG 0x0d6a
+#define regL2TLB_PERFCOUNTER2_CFG_BASE_IDX 0
+#define regL2TLB_PERFCOUNTER3_CFG 0x0d6b
+#define regL2TLB_PERFCOUNTER3_CFG_BASE_IDX 0
+#define regL2TLB_PERFCOUNTER_RSLT_CNTL 0x0d6c
+#define regL2TLB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+
+
+// addressBlock: mmhub_utcl2_l2tlbprdec
+// base address: 0x6b5c0
+#define regL2TLB_PERFCOUNTER_LO 0x0d70
+#define regL2TLB_PERFCOUNTER_LO_BASE_IDX 0
+#define regL2TLB_PERFCOUNTER_HI 0x0d71
+#define regL2TLB_PERFCOUNTER_HI_BASE_IDX 0
+
+
+// addressBlock: mmhub_utcl2_vml2pfdec
+// base address: 0x6ae00
+#define regVM_L2_CNTL 0x0b80
+#define regVM_L2_CNTL_BASE_IDX 0
+#define regVM_L2_CNTL2 0x0b81
+#define regVM_L2_CNTL2_BASE_IDX 0
+#define regVM_L2_CNTL3 0x0b82
+#define regVM_L2_CNTL3_BASE_IDX 0
+#define regVM_L2_STATUS 0x0b83
+#define regVM_L2_STATUS_BASE_IDX 0
+#define regVM_DUMMY_PAGE_FAULT_CNTL 0x0b84
+#define regVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0
+#define regVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0b85
+#define regVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0
+#define regVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0b86
+#define regVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0
+#define regVM_L2_PROTECTION_FAULT_CNTL 0x0b87
+#define regVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0
+#define regVM_L2_PROTECTION_FAULT_CNTL2 0x0b88
+#define regVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0
+#define regVM_L2_PROTECTION_FAULT_MM_CNTL3 0x0b89
+#define regVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0
+#define regVM_L2_PROTECTION_FAULT_MM_CNTL4 0x0b8a
+#define regVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0
+#define regVM_L2_PROTECTION_FAULT_STATUS 0x0b8b
+#define regVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0
+#define regVM_L2_PROTECTION_FAULT_ADDR_LO32 0x0b8c
+#define regVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0
+#define regVM_L2_PROTECTION_FAULT_ADDR_HI32 0x0b8d
+#define regVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0
+#define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x0b8e
+#define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0
+#define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x0b8f
+#define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0
+#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0b91
+#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0
+#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0b92
+#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0
+#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0b93
+#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0
+#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0b94
+#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0
+#define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0b95
+#define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0
+#define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0b96
+#define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0
+#define regVM_L2_CNTL4 0x0b97
+#define regVM_L2_CNTL4_BASE_IDX 0
+#define regVM_L2_MM_GROUP_RT_CLASSES 0x0b98
+#define regVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0
+#define regVM_L2_BANK_SELECT_RESERVED_CID 0x0b99
+#define regVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0
+#define regVM_L2_BANK_SELECT_RESERVED_CID2 0x0b9a
+#define regVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0
+#define regVM_L2_CACHE_PARITY_CNTL 0x0b9b
+#define regVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0
+#define regVM_L2_CGTT_CLK_CTRL 0x0b9e
+#define regVM_L2_CGTT_CLK_CTRL_BASE_IDX 0
+#define regVM_L2_CGTT_BUSY_CTRL 0x0b9f
+#define regVM_L2_CGTT_BUSY_CTRL_BASE_IDX 0
+#define regVML2_MEM_ECC_INDEX 0x0ba1
+#define regVML2_MEM_ECC_INDEX_BASE_IDX 0
+#define regVML2_WALKER_MEM_ECC_INDEX 0x0ba2
+#define regVML2_WALKER_MEM_ECC_INDEX_BASE_IDX 0
+#define regUTCL2_MEM_ECC_INDEX 0x0ba3
+#define regUTCL2_MEM_ECC_INDEX_BASE_IDX 0
+#define regVML2_MEM_ECC_CNTL 0x0ba4
+#define regVML2_MEM_ECC_CNTL_BASE_IDX 0
+#define regVML2_WALKER_MEM_ECC_CNTL 0x0ba5
+#define regVML2_WALKER_MEM_ECC_CNTL_BASE_IDX 0
+#define regUTCL2_MEM_ECC_CNTL 0x0ba6
+#define regUTCL2_MEM_ECC_CNTL_BASE_IDX 0
+#define regVML2_MEM_ECC_STATUS 0x0ba7
+#define regVML2_MEM_ECC_STATUS_BASE_IDX 0
+#define regVML2_WALKER_MEM_ECC_STATUS 0x0ba8
+#define regVML2_WALKER_MEM_ECC_STATUS_BASE_IDX 0
+#define regUTCL2_MEM_ECC_STATUS 0x0ba9
+#define regUTCL2_MEM_ECC_STATUS_BASE_IDX 0
+#define regUTCL2_EDC_MODE 0x0baa
+#define regUTCL2_EDC_MODE_BASE_IDX 0
+#define regUTCL2_EDC_CONFIG 0x0bab
+#define regUTCL2_EDC_CONFIG_BASE_IDX 0
+
+
+// addressBlock: mmhub_utcl2_vml2pldec
+// base address: 0x6b500
+#define regMC_VM_L2_PERFCOUNTER0_CFG 0x0d40
+#define regMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 0
+#define regMC_VM_L2_PERFCOUNTER1_CFG 0x0d41
+#define regMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 0
+#define regMC_VM_L2_PERFCOUNTER2_CFG 0x0d42
+#define regMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 0
+#define regMC_VM_L2_PERFCOUNTER3_CFG 0x0d43
+#define regMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 0
+#define regMC_VM_L2_PERFCOUNTER4_CFG 0x0d44
+#define regMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 0
+#define regMC_VM_L2_PERFCOUNTER5_CFG 0x0d45
+#define regMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 0
+#define regMC_VM_L2_PERFCOUNTER6_CFG 0x0d46
+#define regMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 0
+#define regMC_VM_L2_PERFCOUNTER7_CFG 0x0d47
+#define regMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 0
+#define regMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x0d48
+#define regMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+
+
+// addressBlock: mmhub_utcl2_vml2prdec
+// base address: 0x6b540
+#define regMC_VM_L2_PERFCOUNTER_LO 0x0d50
+#define regMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 0
+#define regMC_VM_L2_PERFCOUNTER_HI 0x0d51
+#define regMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 0
+
+
+// addressBlock: mmhub_utcl2_vml2vcdec
+// base address: 0x6af00
+#define regVM_CONTEXT0_CNTL 0x0bc0
+#define regVM_CONTEXT0_CNTL_BASE_IDX 0
+#define regVM_CONTEXT1_CNTL 0x0bc1
+#define regVM_CONTEXT1_CNTL_BASE_IDX 0
+#define regVM_CONTEXT2_CNTL 0x0bc2
+#define regVM_CONTEXT2_CNTL_BASE_IDX 0
+#define regVM_CONTEXT3_CNTL 0x0bc3
+#define regVM_CONTEXT3_CNTL_BASE_IDX 0
+#define regVM_CONTEXT4_CNTL 0x0bc4
+#define regVM_CONTEXT4_CNTL_BASE_IDX 0
+#define regVM_CONTEXT5_CNTL 0x0bc5
+#define regVM_CONTEXT5_CNTL_BASE_IDX 0
+#define regVM_CONTEXT6_CNTL 0x0bc6
+#define regVM_CONTEXT6_CNTL_BASE_IDX 0
+#define regVM_CONTEXT7_CNTL 0x0bc7
+#define regVM_CONTEXT7_CNTL_BASE_IDX 0
+#define regVM_CONTEXT8_CNTL 0x0bc8
+#define regVM_CONTEXT8_CNTL_BASE_IDX 0
+#define regVM_CONTEXT9_CNTL 0x0bc9
+#define regVM_CONTEXT9_CNTL_BASE_IDX 0
+#define regVM_CONTEXT10_CNTL 0x0bca
+#define regVM_CONTEXT10_CNTL_BASE_IDX 0
+#define regVM_CONTEXT11_CNTL 0x0bcb
+#define regVM_CONTEXT11_CNTL_BASE_IDX 0
+#define regVM_CONTEXT12_CNTL 0x0bcc
+#define regVM_CONTEXT12_CNTL_BASE_IDX 0
+#define regVM_CONTEXT13_CNTL 0x0bcd
+#define regVM_CONTEXT13_CNTL_BASE_IDX 0
+#define regVM_CONTEXT14_CNTL 0x0bce
+#define regVM_CONTEXT14_CNTL_BASE_IDX 0
+#define regVM_CONTEXT15_CNTL 0x0bcf
+#define regVM_CONTEXT15_CNTL_BASE_IDX 0
+#define regVM_CONTEXTS_DISABLE 0x0bd0
+#define regVM_CONTEXTS_DISABLE_BASE_IDX 0
+#define regVM_INVALIDATE_ENG0_SEM 0x0bd1
+#define regVM_INVALIDATE_ENG0_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG1_SEM 0x0bd2
+#define regVM_INVALIDATE_ENG1_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG2_SEM 0x0bd3
+#define regVM_INVALIDATE_ENG2_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG3_SEM 0x0bd4
+#define regVM_INVALIDATE_ENG3_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG4_SEM 0x0bd5
+#define regVM_INVALIDATE_ENG4_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG5_SEM 0x0bd6
+#define regVM_INVALIDATE_ENG5_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG6_SEM 0x0bd7
+#define regVM_INVALIDATE_ENG6_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG7_SEM 0x0bd8
+#define regVM_INVALIDATE_ENG7_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG8_SEM 0x0bd9
+#define regVM_INVALIDATE_ENG8_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG9_SEM 0x0bda
+#define regVM_INVALIDATE_ENG9_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG10_SEM 0x0bdb
+#define regVM_INVALIDATE_ENG10_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG11_SEM 0x0bdc
+#define regVM_INVALIDATE_ENG11_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG12_SEM 0x0bdd
+#define regVM_INVALIDATE_ENG12_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG13_SEM 0x0bde
+#define regVM_INVALIDATE_ENG13_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG14_SEM 0x0bdf
+#define regVM_INVALIDATE_ENG14_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG15_SEM 0x0be0
+#define regVM_INVALIDATE_ENG15_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG16_SEM 0x0be1
+#define regVM_INVALIDATE_ENG16_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG17_SEM 0x0be2
+#define regVM_INVALIDATE_ENG17_SEM_BASE_IDX 0
+#define regVM_INVALIDATE_ENG0_REQ 0x0be3
+#define regVM_INVALIDATE_ENG0_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG1_REQ 0x0be4
+#define regVM_INVALIDATE_ENG1_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG2_REQ 0x0be5
+#define regVM_INVALIDATE_ENG2_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG3_REQ 0x0be6
+#define regVM_INVALIDATE_ENG3_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG4_REQ 0x0be7
+#define regVM_INVALIDATE_ENG4_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG5_REQ 0x0be8
+#define regVM_INVALIDATE_ENG5_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG6_REQ 0x0be9
+#define regVM_INVALIDATE_ENG6_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG7_REQ 0x0bea
+#define regVM_INVALIDATE_ENG7_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG8_REQ 0x0beb
+#define regVM_INVALIDATE_ENG8_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG9_REQ 0x0bec
+#define regVM_INVALIDATE_ENG9_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG10_REQ 0x0bed
+#define regVM_INVALIDATE_ENG10_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG11_REQ 0x0bee
+#define regVM_INVALIDATE_ENG11_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG12_REQ 0x0bef
+#define regVM_INVALIDATE_ENG12_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG13_REQ 0x0bf0
+#define regVM_INVALIDATE_ENG13_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG14_REQ 0x0bf1
+#define regVM_INVALIDATE_ENG14_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG15_REQ 0x0bf2
+#define regVM_INVALIDATE_ENG15_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG16_REQ 0x0bf3
+#define regVM_INVALIDATE_ENG16_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG17_REQ 0x0bf4
+#define regVM_INVALIDATE_ENG17_REQ_BASE_IDX 0
+#define regVM_INVALIDATE_ENG0_ACK 0x0bf5
+#define regVM_INVALIDATE_ENG0_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG1_ACK 0x0bf6
+#define regVM_INVALIDATE_ENG1_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG2_ACK 0x0bf7
+#define regVM_INVALIDATE_ENG2_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG3_ACK 0x0bf8
+#define regVM_INVALIDATE_ENG3_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG4_ACK 0x0bf9
+#define regVM_INVALIDATE_ENG4_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG5_ACK 0x0bfa
+#define regVM_INVALIDATE_ENG5_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG6_ACK 0x0bfb
+#define regVM_INVALIDATE_ENG6_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG7_ACK 0x0bfc
+#define regVM_INVALIDATE_ENG7_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG8_ACK 0x0bfd
+#define regVM_INVALIDATE_ENG8_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG9_ACK 0x0bfe
+#define regVM_INVALIDATE_ENG9_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG10_ACK 0x0bff
+#define regVM_INVALIDATE_ENG10_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG11_ACK 0x0c00
+#define regVM_INVALIDATE_ENG11_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG12_ACK 0x0c01
+#define regVM_INVALIDATE_ENG12_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG13_ACK 0x0c02
+#define regVM_INVALIDATE_ENG13_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG14_ACK 0x0c03
+#define regVM_INVALIDATE_ENG14_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG15_ACK 0x0c04
+#define regVM_INVALIDATE_ENG15_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG16_ACK 0x0c05
+#define regVM_INVALIDATE_ENG16_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG17_ACK 0x0c06
+#define regVM_INVALIDATE_ENG17_ACK_BASE_IDX 0
+#define regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x0c07
+#define regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x0c08
+#define regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x0c09
+#define regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x0c0a
+#define regVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x0c0b
+#define regVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x0c0c
+#define regVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x0c0d
+#define regVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x0c0e
+#define regVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x0c0f
+#define regVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x0c10
+#define regVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x0c11
+#define regVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x0c12
+#define regVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x0c13
+#define regVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x0c14
+#define regVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x0c15
+#define regVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x0c16
+#define regVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x0c17
+#define regVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x0c18
+#define regVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x0c19
+#define regVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x0c1a
+#define regVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x0c1b
+#define regVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x0c1c
+#define regVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x0c1d
+#define regVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x0c1e
+#define regVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x0c1f
+#define regVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x0c20
+#define regVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x0c21
+#define regVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x0c22
+#define regVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x0c23
+#define regVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x0c24
+#define regVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x0c25
+#define regVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x0c26
+#define regVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x0c27
+#define regVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x0c28
+#define regVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x0c29
+#define regVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0
+#define regVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x0c2a
+#define regVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0
+#define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x0c2b
+#define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x0c2c
+#define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0c2d
+#define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0c2e
+#define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0c2f
+#define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0c30
+#define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0c31
+#define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x0c32
+#define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0c33
+#define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0c34
+#define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x0c35
+#define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x0c36
+#define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0c37
+#define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0c38
+#define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x0c39
+#define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x0c3a
+#define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0c3b
+#define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0c3c
+#define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x0c3d
+#define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0c3e
+#define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x0c3f
+#define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0c40
+#define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0c41
+#define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0c42
+#define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x0c43
+#define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x0c44
+#define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x0c45
+#define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x0c46
+#define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x0c47
+#define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x0c48
+#define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x0c49
+#define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x0c4a
+#define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x0c4b
+#define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x0c4c
+#define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0c4d
+#define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0c4e
+#define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x0c4f
+#define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x0c50
+#define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0c51
+#define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0c52
+#define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0c53
+#define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0c54
+#define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0c55
+#define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x0c56
+#define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0c57
+#define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0c58
+#define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x0c59
+#define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x0c5a
+#define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0c5b
+#define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0c5c
+#define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x0c5d
+#define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x0c5e
+#define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x0c5f
+#define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0c60
+#define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0c61
+#define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0c62
+#define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0c63
+#define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0c64
+#define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0c65
+#define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x0c66
+#define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x0c67
+#define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x0c68
+#define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x0c69
+#define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x0c6a
+#define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x0c6b
+#define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x0c6c
+#define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0c6d
+#define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0c6e
+#define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x0c6f
+#define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0c70
+#define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0c71
+#define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0c72
+#define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0c73
+#define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0c74
+#define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0c75
+#define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0c76
+#define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0c77
+#define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0c78
+#define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0c79
+#define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x0c7a
+#define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0c7b
+#define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0c7c
+#define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x0c7d
+#define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x0c7e
+#define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x0c7f
+#define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0c80
+#define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0c81
+#define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0c82
+#define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0c83
+#define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0c84
+#define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0c85
+#define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0c86
+#define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0c87
+#define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0c88
+#define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0c89
+#define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x0c8a
+#define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+
+
+// addressBlock: mmhub_utcl2_vmsharedhvdec
+// base address: 0x6b380
+#define regMC_VM_FB_SIZE_OFFSET_VF0 0x0ce0
+#define regMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 0
+#define regMC_VM_FB_SIZE_OFFSET_VF1 0x0ce1
+#define regMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 0
+#define regMC_VM_FB_SIZE_OFFSET_VF2 0x0ce2
+#define regMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 0
+#define regMC_VM_FB_SIZE_OFFSET_VF3 0x0ce3
+#define regMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 0
+#define regMC_VM_FB_SIZE_OFFSET_VF4 0x0ce4
+#define regMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 0
+#define regMC_VM_FB_SIZE_OFFSET_VF5 0x0ce5
+#define regMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 0
+#define regMC_VM_FB_SIZE_OFFSET_VF6 0x0ce6
+#define regMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 0
+#define regMC_VM_FB_SIZE_OFFSET_VF7 0x0ce7
+#define regMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 0
+#define regMC_VM_FB_SIZE_OFFSET_VF8 0x0ce8
+#define regMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 0
+#define regMC_VM_FB_SIZE_OFFSET_VF9 0x0ce9
+#define regMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 0
+#define regMC_VM_FB_SIZE_OFFSET_VF10 0x0cea
+#define regMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 0
+#define regMC_VM_FB_SIZE_OFFSET_VF11 0x0ceb
+#define regMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 0
+#define regMC_VM_FB_SIZE_OFFSET_VF12 0x0cec
+#define regMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 0
+#define regMC_VM_FB_SIZE_OFFSET_VF13 0x0ced
+#define regMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 0
+#define regMC_VM_FB_SIZE_OFFSET_VF14 0x0cee
+#define regMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 0
+#define regMC_VM_FB_SIZE_OFFSET_VF15 0x0cef
+#define regMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 0
+#define regMC_VM_MARC_BASE_LO_0 0x0cf1
+#define regMC_VM_MARC_BASE_LO_0_BASE_IDX 0
+#define regMC_VM_MARC_BASE_LO_1 0x0cf2
+#define regMC_VM_MARC_BASE_LO_1_BASE_IDX 0
+#define regMC_VM_MARC_BASE_LO_2 0x0cf3
+#define regMC_VM_MARC_BASE_LO_2_BASE_IDX 0
+#define regMC_VM_MARC_BASE_LO_3 0x0cf4
+#define regMC_VM_MARC_BASE_LO_3_BASE_IDX 0
+#define regMC_VM_MARC_BASE_HI_0 0x0cf5
+#define regMC_VM_MARC_BASE_HI_0_BASE_IDX 0
+#define regMC_VM_MARC_BASE_HI_1 0x0cf6
+#define regMC_VM_MARC_BASE_HI_1_BASE_IDX 0
+#define regMC_VM_MARC_BASE_HI_2 0x0cf7
+#define regMC_VM_MARC_BASE_HI_2_BASE_IDX 0
+#define regMC_VM_MARC_BASE_HI_3 0x0cf8
+#define regMC_VM_MARC_BASE_HI_3_BASE_IDX 0
+#define regMC_VM_MARC_RELOC_LO_0 0x0cf9
+#define regMC_VM_MARC_RELOC_LO_0_BASE_IDX 0
+#define regMC_VM_MARC_RELOC_LO_1 0x0cfa
+#define regMC_VM_MARC_RELOC_LO_1_BASE_IDX 0
+#define regMC_VM_MARC_RELOC_LO_2 0x0cfb
+#define regMC_VM_MARC_RELOC_LO_2_BASE_IDX 0
+#define regMC_VM_MARC_RELOC_LO_3 0x0cfc
+#define regMC_VM_MARC_RELOC_LO_3_BASE_IDX 0
+#define regMC_VM_MARC_RELOC_HI_0 0x0cfd
+#define regMC_VM_MARC_RELOC_HI_0_BASE_IDX 0
+#define regMC_VM_MARC_RELOC_HI_1 0x0cfe
+#define regMC_VM_MARC_RELOC_HI_1_BASE_IDX 0
+#define regMC_VM_MARC_RELOC_HI_2 0x0cff
+#define regMC_VM_MARC_RELOC_HI_2_BASE_IDX 0
+#define regMC_VM_MARC_RELOC_HI_3 0x0d00
+#define regMC_VM_MARC_RELOC_HI_3_BASE_IDX 0
+#define regMC_VM_MARC_LEN_LO_0 0x0d01
+#define regMC_VM_MARC_LEN_LO_0_BASE_IDX 0
+#define regMC_VM_MARC_LEN_LO_1 0x0d02
+#define regMC_VM_MARC_LEN_LO_1_BASE_IDX 0
+#define regMC_VM_MARC_LEN_LO_2 0x0d03
+#define regMC_VM_MARC_LEN_LO_2_BASE_IDX 0
+#define regMC_VM_MARC_LEN_LO_3 0x0d04
+#define regMC_VM_MARC_LEN_LO_3_BASE_IDX 0
+#define regMC_VM_MARC_LEN_HI_0 0x0d05
+#define regMC_VM_MARC_LEN_HI_0_BASE_IDX 0
+#define regMC_VM_MARC_LEN_HI_1 0x0d06
+#define regMC_VM_MARC_LEN_HI_1_BASE_IDX 0
+#define regMC_VM_MARC_LEN_HI_2 0x0d07
+#define regMC_VM_MARC_LEN_HI_2_BASE_IDX 0
+#define regMC_VM_MARC_LEN_HI_3 0x0d08
+#define regMC_VM_MARC_LEN_HI_3_BASE_IDX 0
+#define regVM_PCIE_ATS_CNTL 0x0d0b
+#define regVM_PCIE_ATS_CNTL_BASE_IDX 0
+#define regVM_PCIE_ATS_CNTL_VF_0 0x0d0c
+#define regVM_PCIE_ATS_CNTL_VF_0_BASE_IDX 0
+#define regVM_PCIE_ATS_CNTL_VF_1 0x0d0d
+#define regVM_PCIE_ATS_CNTL_VF_1_BASE_IDX 0
+#define regVM_PCIE_ATS_CNTL_VF_2 0x0d0e
+#define regVM_PCIE_ATS_CNTL_VF_2_BASE_IDX 0
+#define regVM_PCIE_ATS_CNTL_VF_3 0x0d0f
+#define regVM_PCIE_ATS_CNTL_VF_3_BASE_IDX 0
+#define regVM_PCIE_ATS_CNTL_VF_4 0x0d10
+#define regVM_PCIE_ATS_CNTL_VF_4_BASE_IDX 0
+#define regVM_PCIE_ATS_CNTL_VF_5 0x0d11
+#define regVM_PCIE_ATS_CNTL_VF_5_BASE_IDX 0
+#define regVM_PCIE_ATS_CNTL_VF_6 0x0d12
+#define regVM_PCIE_ATS_CNTL_VF_6_BASE_IDX 0
+#define regVM_PCIE_ATS_CNTL_VF_7 0x0d13
+#define regVM_PCIE_ATS_CNTL_VF_7_BASE_IDX 0
+#define regVM_PCIE_ATS_CNTL_VF_8 0x0d14
+#define regVM_PCIE_ATS_CNTL_VF_8_BASE_IDX 0
+#define regVM_PCIE_ATS_CNTL_VF_9 0x0d15
+#define regVM_PCIE_ATS_CNTL_VF_9_BASE_IDX 0
+#define regVM_PCIE_ATS_CNTL_VF_10 0x0d16
+#define regVM_PCIE_ATS_CNTL_VF_10_BASE_IDX 0
+#define regVM_PCIE_ATS_CNTL_VF_11 0x0d17
+#define regVM_PCIE_ATS_CNTL_VF_11_BASE_IDX 0
+#define regVM_PCIE_ATS_CNTL_VF_12 0x0d18
+#define regVM_PCIE_ATS_CNTL_VF_12_BASE_IDX 0
+#define regVM_PCIE_ATS_CNTL_VF_13 0x0d19
+#define regVM_PCIE_ATS_CNTL_VF_13_BASE_IDX 0
+#define regVM_PCIE_ATS_CNTL_VF_14 0x0d1a
+#define regVM_PCIE_ATS_CNTL_VF_14_BASE_IDX 0
+#define regVM_PCIE_ATS_CNTL_VF_15 0x0d1b
+#define regVM_PCIE_ATS_CNTL_VF_15_BASE_IDX 0
+#define regMC_SHARED_ACTIVE_FCN_ID 0x0d1c
+#define regMC_SHARED_ACTIVE_FCN_ID_BASE_IDX 0
+#define regMC_VM_XGMI_GPUIOV_ENABLE 0x0d1d
+#define regMC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX 0
+
+
+// addressBlock: mmhub_utcl2_vmsharedpfdec
+// base address: 0x6b290
+#define regMC_VM_FB_OFFSET 0x0cab
+#define regMC_VM_FB_OFFSET_BASE_IDX 0
+#define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0cac
+#define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0
+#define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0cad
+#define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0
+#define regMC_VM_STEERING 0x0cae
+#define regMC_VM_STEERING_BASE_IDX 0
+#define regMC_SHARED_VIRT_RESET_REQ 0x0caf
+#define regMC_SHARED_VIRT_RESET_REQ_BASE_IDX 0
+#define regMC_MEM_POWER_LS 0x0cb0
+#define regMC_MEM_POWER_LS_BASE_IDX 0
+#define regMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x0cb1
+#define regMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0
+#define regMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x0cb2
+#define regMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0
+#define regMC_VM_APT_CNTL 0x0cb3
+#define regMC_VM_APT_CNTL_BASE_IDX 0
+#define regMC_VM_LOCAL_HBM_ADDRESS_START 0x0cb4
+#define regMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 0
+#define regMC_VM_LOCAL_HBM_ADDRESS_END 0x0cb5
+#define regMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 0
+#define regMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x0cb6
+#define regMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 0
+#define regUTCL2_CGTT_CLK_CTRL 0x0cb7
+#define regUTCL2_CGTT_CLK_CTRL_BASE_IDX 0
+#define regMC_VM_XGMI_LFB_CNTL 0x0cb8
+#define regMC_VM_XGMI_LFB_CNTL_BASE_IDX 0
+#define regMC_VM_XGMI_LFB_SIZE 0x0cb9
+#define regMC_VM_XGMI_LFB_SIZE_BASE_IDX 0
+#define regMC_VM_CACHEABLE_DRAM_CNTL 0x0cba
+#define regMC_VM_CACHEABLE_DRAM_CNTL_BASE_IDX 0
+#define regMC_VM_HOST_MAPPING 0x0cbb
+#define regMC_VM_HOST_MAPPING_BASE_IDX 0
+
+
+// addressBlock: mmhub_utcl2_vmsharedvcdec
+// base address: 0x6b300
+#define regMC_VM_FB_LOCATION_BASE 0x0cc0
+#define regMC_VM_FB_LOCATION_BASE_BASE_IDX 0
+#define regMC_VM_FB_LOCATION_TOP 0x0cc1
+#define regMC_VM_FB_LOCATION_TOP_BASE_IDX 0
+#define regMC_VM_AGP_TOP 0x0cc2
+#define regMC_VM_AGP_TOP_BASE_IDX 0
+#define regMC_VM_AGP_BOT 0x0cc3
+#define regMC_VM_AGP_BOT_BASE_IDX 0
+#define regMC_VM_AGP_BASE 0x0cc4
+#define regMC_VM_AGP_BASE_BASE_IDX 0
+#define regMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0cc5
+#define regMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0
+#define regMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0cc6
+#define regMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0
+#define regMC_VM_MX_L1_TLB_CNTL 0x0cc7
+#define regMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_7_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_7_sh_mask.h
new file mode 100644
index 000000000000..c1185f36c080
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_7_sh_mask.h
@@ -0,0 +1,32178 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef _mmhub_1_7_SH_MASK_HEADER
+#define _mmhub_1_7_SH_MASK_HEADER
+
+
+// addressBlock: mmhub_dagb_dagbdec0
+//DAGB0_RDCLI0
+#define DAGB0_RDCLI0__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI0__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI0__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI0__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI0__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI0__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI0__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI0__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI0__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI0__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI0__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI0__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI1
+#define DAGB0_RDCLI1__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI1__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI1__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI1__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI1__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI1__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI1__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI1__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI1__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI1__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI1__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI1__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI2
+#define DAGB0_RDCLI2__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI2__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI2__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI2__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI2__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI2__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI2__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI2__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI2__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI2__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI2__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI2__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI3
+#define DAGB0_RDCLI3__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI3__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI3__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI3__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI3__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI3__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI3__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI3__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI3__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI3__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI3__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI3__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI4
+#define DAGB0_RDCLI4__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI4__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI4__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI4__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI4__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI4__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI4__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI4__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI4__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI4__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI4__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI4__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI5
+#define DAGB0_RDCLI5__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI5__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI5__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI5__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI5__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI5__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI5__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI5__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI5__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI5__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI5__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI5__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI6
+#define DAGB0_RDCLI6__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI6__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI6__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI6__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI6__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI6__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI6__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI6__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI6__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI6__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI6__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI6__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI7
+#define DAGB0_RDCLI7__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI7__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI7__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI7__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI7__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI7__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI7__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI7__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI7__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI7__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI7__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI7__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI8
+#define DAGB0_RDCLI8__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI8__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI8__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI8__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI8__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI8__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI8__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI8__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI8__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI8__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI8__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI8__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI9
+#define DAGB0_RDCLI9__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI9__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI9__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI9__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI9__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI9__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI9__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI9__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI9__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI9__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI9__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI9__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI10
+#define DAGB0_RDCLI10__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI10__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI10__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI10__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI10__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI10__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI10__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI10__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI10__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI10__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI10__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI10__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI11
+#define DAGB0_RDCLI11__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI11__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI11__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI11__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI11__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI11__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI11__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI11__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI11__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI11__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI11__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI11__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI12
+#define DAGB0_RDCLI12__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI12__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI12__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI12__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI12__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI12__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI12__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI12__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI12__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI12__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI12__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI12__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI13
+#define DAGB0_RDCLI13__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI13__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI13__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI13__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI13__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI13__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI13__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI13__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI13__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI13__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI13__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI13__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI14
+#define DAGB0_RDCLI14__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI14__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI14__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI14__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI14__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI14__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI14__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI14__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI14__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI14__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI14__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI14__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI15
+#define DAGB0_RDCLI15__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI15__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI15__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI15__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI15__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI15__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI15__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI15__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI15__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI15__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI15__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI15__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RD_CNTL
+#define DAGB0_RD_CNTL__SCLK_FREQ__SHIFT 0x0
+#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4
+#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
+#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
+#define DAGB0_RD_CNTL__IO_LEVEL__SHIFT 0x11
+#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14
+#define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17
+#define DAGB0_RD_CNTL__FIX_JUMP__SHIFT 0x1a
+#define DAGB0_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL
+#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L
+#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L
+#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L
+#define DAGB0_RD_CNTL__IO_LEVEL_MASK 0x000E0000L
+#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L
+#define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L
+#define DAGB0_RD_CNTL__FIX_JUMP_MASK 0x04000000L
+//DAGB0_RD_GMI_CNTL
+#define DAGB0_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0
+#define DAGB0_RD_GMI_CNTL__LEVEL__SHIFT 0x6
+#define DAGB0_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9
+#define DAGB0_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd
+#define DAGB0_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL
+#define DAGB0_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L
+#define DAGB0_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L
+#define DAGB0_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L
+//DAGB0_RD_ADDR_DAGB
+#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0
+#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
+#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
+#define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7
+#define DAGB0_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd
+#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L
+#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
+#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
+#define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L
+#define DAGB0_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L
+//DAGB0_RD_OUTPUT_DAGB_MAX_BURST
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L
+//DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L
+//DAGB0_RD_CGTT_CLK_CTRL
+#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB0_L1TLB_RD_CGTT_CLK_CTRL
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB0_ATCVM_RD_CGTT_CLK_CTRL
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB0_RD_ADDR_DAGB_MAX_BURST0
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
+//DAGB0_RD_ADDR_DAGB_LAZY_TIMER0
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
+//DAGB0_RD_ADDR_DAGB_MAX_BURST1
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
+//DAGB0_RD_ADDR_DAGB_LAZY_TIMER1
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
+//DAGB0_RD_VC0_CNTL
+#define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_RD_VC1_CNTL
+#define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_RD_VC2_CNTL
+#define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_RD_VC3_CNTL
+#define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_RD_VC4_CNTL
+#define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_RD_VC5_CNTL
+#define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_RD_VC6_CNTL
+#define DAGB0_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_RD_VC6_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_RD_VC6_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_RD_VC7_CNTL
+#define DAGB0_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_RD_VC7_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_RD_VC7_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_RD_CNTL_MISC
+#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0
+#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6
+#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd
+#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13
+#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14
+#define DAGB0_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15
+#define DAGB0_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a
+#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL
+#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L
+#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L
+#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L
+#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L
+#define DAGB0_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L
+#define DAGB0_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L
+//DAGB0_RD_TLB_CREDIT
+#define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT 0x0
+#define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT 0x5
+#define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa
+#define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT 0xf
+#define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT 0x14
+#define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT 0x19
+#define DAGB0_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL
+#define DAGB0_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L
+#define DAGB0_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L
+#define DAGB0_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L
+#define DAGB0_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L
+#define DAGB0_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L
+//DAGB0_RD_RDRET_CREDIT_CNTL
+#define DAGB0_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT 0x0
+#define DAGB0_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT 0x6
+#define DAGB0_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT 0xc
+#define DAGB0_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT 0x12
+#define DAGB0_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT 0x18
+#define DAGB0_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT 0x1e
+#define DAGB0_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT 0x1f
+#define DAGB0_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK 0x0000003FL
+#define DAGB0_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK 0x00000FC0L
+#define DAGB0_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK 0x0003F000L
+#define DAGB0_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK 0x00FC0000L
+#define DAGB0_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK 0x3F000000L
+#define DAGB0_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK 0x40000000L
+#define DAGB0_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK 0x80000000L
+//DAGB0_RD_RDRET_CREDIT_CNTL2
+#define DAGB0_RD_RDRET_CREDIT_CNTL2__IO_CREDIT__SHIFT 0x0
+#define DAGB0_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT__SHIFT 0x6
+#define DAGB0_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT 0xc
+#define DAGB0_RD_RDRET_CREDIT_CNTL2__IO_CREDIT_MASK 0x0000003FL
+#define DAGB0_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT_MASK 0x00000FC0L
+#define DAGB0_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK 0x0007F000L
+//DAGB0_RDCLI_ASK_PENDING
+#define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_RDCLI_GO_PENDING
+#define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_RDCLI_GBLSEND_PENDING
+#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_RDCLI_TLB_PENDING
+#define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_RDCLI_OARB_PENDING
+#define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_RDCLI_OSD_PENDING
+#define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI0
+#define DAGB0_WRCLI0__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI0__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI0__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI0__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI0__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI0__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI0__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI0__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI0__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI0__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI0__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI0__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI1
+#define DAGB0_WRCLI1__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI1__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI1__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI1__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI1__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI1__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI1__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI1__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI1__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI1__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI1__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI1__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI2
+#define DAGB0_WRCLI2__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI2__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI2__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI2__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI2__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI2__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI2__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI2__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI2__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI2__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI2__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI2__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI3
+#define DAGB0_WRCLI3__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI3__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI3__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI3__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI3__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI3__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI3__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI3__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI3__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI3__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI3__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI3__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI4
+#define DAGB0_WRCLI4__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI4__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI4__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI4__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI4__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI4__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI4__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI4__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI4__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI4__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI4__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI4__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI5
+#define DAGB0_WRCLI5__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI5__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI5__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI5__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI5__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI5__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI5__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI5__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI5__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI5__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI5__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI5__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI6
+#define DAGB0_WRCLI6__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI6__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI6__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI6__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI6__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI6__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI6__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI6__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI6__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI6__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI6__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI6__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI7
+#define DAGB0_WRCLI7__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI7__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI7__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI7__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI7__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI7__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI7__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI7__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI7__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI7__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI7__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI7__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI8
+#define DAGB0_WRCLI8__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI8__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI8__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI8__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI8__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI8__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI8__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI8__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI8__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI8__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI8__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI8__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI9
+#define DAGB0_WRCLI9__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI9__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI9__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI9__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI9__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI9__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI9__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI9__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI9__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI9__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI9__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI9__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI10
+#define DAGB0_WRCLI10__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI10__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI10__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI10__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI10__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI10__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI10__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI10__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI10__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI10__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI10__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI10__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI11
+#define DAGB0_WRCLI11__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI11__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI11__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI11__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI11__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI11__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI11__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI11__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI11__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI11__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI11__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI11__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI12
+#define DAGB0_WRCLI12__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI12__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI12__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI12__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI12__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI12__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI12__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI12__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI12__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI12__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI12__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI12__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI13
+#define DAGB0_WRCLI13__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI13__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI13__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI13__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI13__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI13__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI13__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI13__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI13__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI13__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI13__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI13__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI14
+#define DAGB0_WRCLI14__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI14__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI14__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI14__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI14__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI14__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI14__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI14__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI14__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI14__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI14__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI14__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI15
+#define DAGB0_WRCLI15__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI15__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI15__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI15__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI15__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI15__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI15__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI15__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI15__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI15__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI15__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI15__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WR_CNTL
+#define DAGB0_WR_CNTL__SCLK_FREQ__SHIFT 0x0
+#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4
+#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
+#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
+#define DAGB0_WR_CNTL__IO_LEVEL__SHIFT 0x11
+#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14
+#define DAGB0_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17
+#define DAGB0_WR_CNTL__FIX_JUMP__SHIFT 0x1a
+#define DAGB0_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL
+#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L
+#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L
+#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L
+#define DAGB0_WR_CNTL__IO_LEVEL_MASK 0x000E0000L
+#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L
+#define DAGB0_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L
+#define DAGB0_WR_CNTL__FIX_JUMP_MASK 0x04000000L
+//DAGB0_WR_GMI_CNTL
+#define DAGB0_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0
+#define DAGB0_WR_GMI_CNTL__LEVEL__SHIFT 0x6
+#define DAGB0_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9
+#define DAGB0_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd
+#define DAGB0_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL
+#define DAGB0_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L
+#define DAGB0_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L
+#define DAGB0_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L
+//DAGB0_WR_ADDR_DAGB
+#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0
+#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
+#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
+#define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7
+#define DAGB0_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xd
+#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L
+#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
+#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
+#define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L
+#define DAGB0_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L
+//DAGB0_WR_OUTPUT_DAGB_MAX_BURST
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L
+//DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L
+//DAGB0_WR_CGTT_CLK_CTRL
+#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB0_L1TLB_WR_CGTT_CLK_CTRL
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB0_ATCVM_WR_CGTT_CLK_CTRL
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB0_WR_ADDR_DAGB_MAX_BURST0
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
+//DAGB0_WR_ADDR_DAGB_LAZY_TIMER0
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
+//DAGB0_WR_ADDR_DAGB_MAX_BURST1
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
+//DAGB0_WR_ADDR_DAGB_LAZY_TIMER1
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
+//DAGB0_WR_DATA_DAGB
+#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0
+#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
+#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
+#define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT 0x7
+#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L
+#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
+#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
+#define DAGB0_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L
+//DAGB0_WR_DATA_DAGB_MAX_BURST0
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
+//DAGB0_WR_DATA_DAGB_LAZY_TIMER0
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
+//DAGB0_WR_DATA_DAGB_MAX_BURST1
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
+//DAGB0_WR_DATA_DAGB_LAZY_TIMER1
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
+//DAGB0_WR_VC0_CNTL
+#define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_WR_VC1_CNTL
+#define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_WR_VC2_CNTL
+#define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_WR_VC3_CNTL
+#define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_WR_VC4_CNTL
+#define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_WR_VC5_CNTL
+#define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_WR_VC6_CNTL
+#define DAGB0_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_WR_VC6_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_WR_VC6_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_WR_VC7_CNTL
+#define DAGB0_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_WR_VC7_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_WR_VC7_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_WR_CNTL_MISC
+#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0
+#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6
+#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd
+#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13
+#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14
+#define DAGB0_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15
+#define DAGB0_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a
+#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL
+#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L
+#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L
+#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L
+#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L
+#define DAGB0_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L
+#define DAGB0_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L
+//DAGB0_WR_TLB_CREDIT
+#define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT 0x0
+#define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT 0x5
+#define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa
+#define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT 0xf
+#define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT 0x14
+#define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT 0x19
+#define DAGB0_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL
+#define DAGB0_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L
+#define DAGB0_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L
+#define DAGB0_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L
+#define DAGB0_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L
+#define DAGB0_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L
+//DAGB0_WR_DATA_CREDIT
+#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0
+#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8
+#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10
+#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18
+#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL
+#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L
+#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L
+#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L
+//DAGB0_WR_MISC_CREDIT
+#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0
+#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6
+#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9
+#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10
+#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL
+#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L
+#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L
+#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L
+//DAGB0_WR_OSD_CREDIT_CNTL1
+#define DAGB0_WR_OSD_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0
+#define DAGB0_WR_OSD_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x4
+#define DAGB0_WR_OSD_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0x8
+#define DAGB0_WR_OSD_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xc
+#define DAGB0_WR_OSD_CREDIT_CNTL1__IO_CREDIT__SHIFT 0x10
+#define DAGB0_WR_OSD_CREDIT_CNTL1__GMI_CREDIT__SHIFT 0x14
+#define DAGB0_WR_OSD_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x18
+#define DAGB0_WR_OSD_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000000FL
+#define DAGB0_WR_OSD_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000000F0L
+#define DAGB0_WR_OSD_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00000F00L
+#define DAGB0_WR_OSD_CREDIT_CNTL1__VC3_CREDIT_MASK 0x0000F000L
+#define DAGB0_WR_OSD_CREDIT_CNTL1__IO_CREDIT_MASK 0x000F0000L
+#define DAGB0_WR_OSD_CREDIT_CNTL1__GMI_CREDIT_MASK 0x00F00000L
+#define DAGB0_WR_OSD_CREDIT_CNTL1__POOL_CREDIT_MASK 0x3F000000L
+//DAGB0_WR_OSD_CREDIT_CNTL2
+#define DAGB0_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN__SHIFT 0x0
+#define DAGB0_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY__SHIFT 0x4
+#define DAGB0_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN_MASK 0x0000000FL
+#define DAGB0_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY_MASK 0x00000010L
+//DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x19
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1a
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1b
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1__SHIFT 0x1c
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2__SHIFT 0x1d
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x01F00000L
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x02000000L
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x04000000L
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK 0x08000000L
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1_MASK 0x10000000L
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2_MASK 0x20000000L
+//DAGB0_WRCLI_GPU_SNOOP_OVERRIDE
+#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0
+#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE
+#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0
+#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_ASK_PENDING
+#define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_GO_PENDING
+#define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_GBLSEND_PENDING
+#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_TLB_PENDING
+#define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_OARB_PENDING
+#define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_OSD_PENDING
+#define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_DBUS_ASK_PENDING
+#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_DBUS_GO_PENDING
+#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_DAGB_DLY
+#define DAGB0_DAGB_DLY__DLY__SHIFT 0x0
+#define DAGB0_DAGB_DLY__CLI__SHIFT 0x8
+#define DAGB0_DAGB_DLY__POS__SHIFT 0x10
+#define DAGB0_DAGB_DLY__DLY_MASK 0x000000FFL
+#define DAGB0_DAGB_DLY__CLI_MASK 0x0000FF00L
+#define DAGB0_DAGB_DLY__POS_MASK 0x000F0000L
+//DAGB0_CNTL_MISC
+#define DAGB0_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0
+#define DAGB0_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3
+#define DAGB0_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6
+#define DAGB0_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9
+#define DAGB0_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc
+#define DAGB0_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf
+#define DAGB0_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12
+#define DAGB0_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15
+#define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18
+#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e
+#define DAGB0_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L
+#define DAGB0_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L
+#define DAGB0_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L
+#define DAGB0_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L
+#define DAGB0_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L
+#define DAGB0_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L
+#define DAGB0_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L
+#define DAGB0_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L
+#define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L
+#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L
+//DAGB0_CNTL_MISC2
+#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0
+#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1
+#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2
+#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3
+#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4
+#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5
+#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6
+#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7
+#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8
+#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9
+#define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0xa
+#define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb
+#define DAGB0_CNTL_MISC2__HDP_CID__SHIFT 0xc
+#define DAGB0_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x11
+#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L
+#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L
+#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L
+#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L
+#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L
+#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L
+#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L
+#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L
+#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L
+#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L
+#define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L
+#define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L
+#define DAGB0_CNTL_MISC2__HDP_CID_MASK 0x0001F000L
+#define DAGB0_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x007E0000L
+//DAGB0_FATAL_ERROR_CNTL
+#define DAGB0_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT 0x0
+#define DAGB0_FATAL_ERROR_CNTL__FILTER_NUM_MASK 0x000003FFL
+//DAGB0_FATAL_ERROR_CLEAR
+#define DAGB0_FATAL_ERROR_CLEAR__CLEAR__SHIFT 0x0
+#define DAGB0_FATAL_ERROR_CLEAR__CLEAR_MASK 0x00000001L
+//DAGB0_FATAL_ERROR_STATUS0
+#define DAGB0_FATAL_ERROR_STATUS0__VALID__SHIFT 0x0
+#define DAGB0_FATAL_ERROR_STATUS0__CID__SHIFT 0x1
+#define DAGB0_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT 0x6
+#define DAGB0_FATAL_ERROR_STATUS0__VALID_MASK 0x00000001L
+#define DAGB0_FATAL_ERROR_STATUS0__CID_MASK 0x0000003EL
+#define DAGB0_FATAL_ERROR_STATUS0__ADDR_LO_MASK 0xFFFFFFC0L
+//DAGB0_FATAL_ERROR_STATUS1
+#define DAGB0_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT 0x0
+#define DAGB0_FATAL_ERROR_STATUS1__ADDR_HI_MASK 0x0001FFFFL
+//DAGB0_FATAL_ERROR_STATUS2
+#define DAGB0_FATAL_ERROR_STATUS2__TAG__SHIFT 0x0
+#define DAGB0_FATAL_ERROR_STATUS2__VFID__SHIFT 0x10
+#define DAGB0_FATAL_ERROR_STATUS2__VF__SHIFT 0x14
+#define DAGB0_FATAL_ERROR_STATUS2__SPACE__SHIFT 0x15
+#define DAGB0_FATAL_ERROR_STATUS2__IO__SHIFT 0x16
+#define DAGB0_FATAL_ERROR_STATUS2__SIZE__SHIFT 0x17
+#define DAGB0_FATAL_ERROR_STATUS2__FED__SHIFT 0x19
+#define DAGB0_FATAL_ERROR_STATUS2__TAG_MASK 0x0000FFFFL
+#define DAGB0_FATAL_ERROR_STATUS2__VFID_MASK 0x000F0000L
+#define DAGB0_FATAL_ERROR_STATUS2__VF_MASK 0x00100000L
+#define DAGB0_FATAL_ERROR_STATUS2__SPACE_MASK 0x00200000L
+#define DAGB0_FATAL_ERROR_STATUS2__IO_MASK 0x00400000L
+#define DAGB0_FATAL_ERROR_STATUS2__SIZE_MASK 0x00800000L
+#define DAGB0_FATAL_ERROR_STATUS2__FED_MASK 0x02000000L
+//DAGB0_FATAL_ERROR_STATUS3
+#define DAGB0_FATAL_ERROR_STATUS3__OP__SHIFT 0x6
+#define DAGB0_FATAL_ERROR_STATUS3__WRTMZ__SHIFT 0x10
+#define DAGB0_FATAL_ERROR_STATUS3__RDTMZ__SHIFT 0x11
+#define DAGB0_FATAL_ERROR_STATUS3__SNOOP__SHIFT 0x12
+#define DAGB0_FATAL_ERROR_STATUS3__INVAL__SHIFT 0x13
+#define DAGB0_FATAL_ERROR_STATUS3__NACK__SHIFT 0x14
+#define DAGB0_FATAL_ERROR_STATUS3__RO__SHIFT 0x16
+#define DAGB0_FATAL_ERROR_STATUS3__MEMLOG__SHIFT 0x17
+#define DAGB0_FATAL_ERROR_STATUS3__EOP__SHIFT 0x18
+#define DAGB0_FATAL_ERROR_STATUS3__OP_MASK 0x00001FC0L
+#define DAGB0_FATAL_ERROR_STATUS3__WRTMZ_MASK 0x00010000L
+#define DAGB0_FATAL_ERROR_STATUS3__RDTMZ_MASK 0x00020000L
+#define DAGB0_FATAL_ERROR_STATUS3__SNOOP_MASK 0x00040000L
+#define DAGB0_FATAL_ERROR_STATUS3__INVAL_MASK 0x00080000L
+#define DAGB0_FATAL_ERROR_STATUS3__NACK_MASK 0x00300000L
+#define DAGB0_FATAL_ERROR_STATUS3__RO_MASK 0x00400000L
+#define DAGB0_FATAL_ERROR_STATUS3__MEMLOG_MASK 0x00800000L
+#define DAGB0_FATAL_ERROR_STATUS3__EOP_MASK 0x01000000L
+//DAGB0_FIFO_EMPTY
+#define DAGB0_FIFO_EMPTY__EMPTY__SHIFT 0x0
+#define DAGB0_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL
+//DAGB0_FIFO_FULL
+#define DAGB0_FIFO_FULL__FULL__SHIFT 0x0
+#define DAGB0_FIFO_FULL__FULL_MASK 0x007FFFFFL
+//DAGB0_WR_CREDITS_FULL
+#define DAGB0_WR_CREDITS_FULL__FULL__SHIFT 0x0
+#define DAGB0_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL
+//DAGB0_RD_CREDITS_FULL
+#define DAGB0_RD_CREDITS_FULL__FULL__SHIFT 0x0
+#define DAGB0_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL
+//DAGB0_PERFCOUNTER_LO
+#define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//DAGB0_PERFCOUNTER_HI
+#define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//DAGB0_PERFCOUNTER0_CFG
+#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//DAGB0_PERFCOUNTER1_CFG
+#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//DAGB0_PERFCOUNTER2_CFG
+#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
+#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
+#define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
+#define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
+//DAGB0_PERFCOUNTER_RSLT_CNTL
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+//DAGB0_L1TLB_REG_RW
+#define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0
+#define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1
+#define DAGB0_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL__SHIFT 0x2
+#define DAGB0_L1TLB_REG_RW__WDAT_PARITY_CHECK__SHIFT 0x4
+#define DAGB0_L1TLB_REG_RW__DISABLE_RDRET_CHECK__SHIFT 0x5
+#define DAGB0_L1TLB_REG_RW__RESERVE__SHIFT 0x6
+#define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L
+#define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L
+#define DAGB0_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL_MASK 0x00000004L
+#define DAGB0_L1TLB_REG_RW__WDAT_PARITY_CHECK_MASK 0x00000010L
+#define DAGB0_L1TLB_REG_RW__DISABLE_RDRET_CHECK_MASK 0x00000020L
+#define DAGB0_L1TLB_REG_RW__RESERVE_MASK 0xFFFFFFC0L
+//DAGB0_RESERVE1
+#define DAGB0_RESERVE1__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE1__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE2
+#define DAGB0_RESERVE2__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE2__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE3
+#define DAGB0_RESERVE3__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE3__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE4
+#define DAGB0_RESERVE4__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE4__RESERVE_MASK 0xFFFFFFFFL
+
+
+// addressBlock: mmhub_dagb_dagbdec1
+//DAGB1_RDCLI0
+#define DAGB1_RDCLI0__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_RDCLI0__URG_HIGH__SHIFT 0x4
+#define DAGB1_RDCLI0__URG_LOW__SHIFT 0x8
+#define DAGB1_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_RDCLI0__MAX_BW__SHIFT 0xd
+#define DAGB1_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_RDCLI0__MIN_BW__SHIFT 0x16
+#define DAGB1_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_RDCLI0__MAX_OSD__SHIFT 0x1a
+#define DAGB1_RDCLI0__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_RDCLI0__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_RDCLI0__URG_LOW_MASK 0x00000F00L
+#define DAGB1_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_RDCLI0__MAX_BW_MASK 0x001FE000L
+#define DAGB1_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_RDCLI0__MIN_BW_MASK 0x01C00000L
+#define DAGB1_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_RDCLI0__MAX_OSD_MASK 0xFC000000L
+//DAGB1_RDCLI1
+#define DAGB1_RDCLI1__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_RDCLI1__URG_HIGH__SHIFT 0x4
+#define DAGB1_RDCLI1__URG_LOW__SHIFT 0x8
+#define DAGB1_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_RDCLI1__MAX_BW__SHIFT 0xd
+#define DAGB1_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_RDCLI1__MIN_BW__SHIFT 0x16
+#define DAGB1_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_RDCLI1__MAX_OSD__SHIFT 0x1a
+#define DAGB1_RDCLI1__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_RDCLI1__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_RDCLI1__URG_LOW_MASK 0x00000F00L
+#define DAGB1_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_RDCLI1__MAX_BW_MASK 0x001FE000L
+#define DAGB1_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_RDCLI1__MIN_BW_MASK 0x01C00000L
+#define DAGB1_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_RDCLI1__MAX_OSD_MASK 0xFC000000L
+//DAGB1_RDCLI2
+#define DAGB1_RDCLI2__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_RDCLI2__URG_HIGH__SHIFT 0x4
+#define DAGB1_RDCLI2__URG_LOW__SHIFT 0x8
+#define DAGB1_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_RDCLI2__MAX_BW__SHIFT 0xd
+#define DAGB1_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_RDCLI2__MIN_BW__SHIFT 0x16
+#define DAGB1_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_RDCLI2__MAX_OSD__SHIFT 0x1a
+#define DAGB1_RDCLI2__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_RDCLI2__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_RDCLI2__URG_LOW_MASK 0x00000F00L
+#define DAGB1_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_RDCLI2__MAX_BW_MASK 0x001FE000L
+#define DAGB1_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_RDCLI2__MIN_BW_MASK 0x01C00000L
+#define DAGB1_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_RDCLI2__MAX_OSD_MASK 0xFC000000L
+//DAGB1_RDCLI3
+#define DAGB1_RDCLI3__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_RDCLI3__URG_HIGH__SHIFT 0x4
+#define DAGB1_RDCLI3__URG_LOW__SHIFT 0x8
+#define DAGB1_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_RDCLI3__MAX_BW__SHIFT 0xd
+#define DAGB1_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_RDCLI3__MIN_BW__SHIFT 0x16
+#define DAGB1_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_RDCLI3__MAX_OSD__SHIFT 0x1a
+#define DAGB1_RDCLI3__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_RDCLI3__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_RDCLI3__URG_LOW_MASK 0x00000F00L
+#define DAGB1_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_RDCLI3__MAX_BW_MASK 0x001FE000L
+#define DAGB1_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_RDCLI3__MIN_BW_MASK 0x01C00000L
+#define DAGB1_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_RDCLI3__MAX_OSD_MASK 0xFC000000L
+//DAGB1_RDCLI4
+#define DAGB1_RDCLI4__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_RDCLI4__URG_HIGH__SHIFT 0x4
+#define DAGB1_RDCLI4__URG_LOW__SHIFT 0x8
+#define DAGB1_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_RDCLI4__MAX_BW__SHIFT 0xd
+#define DAGB1_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_RDCLI4__MIN_BW__SHIFT 0x16
+#define DAGB1_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_RDCLI4__MAX_OSD__SHIFT 0x1a
+#define DAGB1_RDCLI4__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_RDCLI4__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_RDCLI4__URG_LOW_MASK 0x00000F00L
+#define DAGB1_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_RDCLI4__MAX_BW_MASK 0x001FE000L
+#define DAGB1_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_RDCLI4__MIN_BW_MASK 0x01C00000L
+#define DAGB1_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_RDCLI4__MAX_OSD_MASK 0xFC000000L
+//DAGB1_RDCLI5
+#define DAGB1_RDCLI5__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_RDCLI5__URG_HIGH__SHIFT 0x4
+#define DAGB1_RDCLI5__URG_LOW__SHIFT 0x8
+#define DAGB1_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_RDCLI5__MAX_BW__SHIFT 0xd
+#define DAGB1_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_RDCLI5__MIN_BW__SHIFT 0x16
+#define DAGB1_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_RDCLI5__MAX_OSD__SHIFT 0x1a
+#define DAGB1_RDCLI5__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_RDCLI5__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_RDCLI5__URG_LOW_MASK 0x00000F00L
+#define DAGB1_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_RDCLI5__MAX_BW_MASK 0x001FE000L
+#define DAGB1_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_RDCLI5__MIN_BW_MASK 0x01C00000L
+#define DAGB1_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_RDCLI5__MAX_OSD_MASK 0xFC000000L
+//DAGB1_RDCLI6
+#define DAGB1_RDCLI6__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_RDCLI6__URG_HIGH__SHIFT 0x4
+#define DAGB1_RDCLI6__URG_LOW__SHIFT 0x8
+#define DAGB1_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_RDCLI6__MAX_BW__SHIFT 0xd
+#define DAGB1_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_RDCLI6__MIN_BW__SHIFT 0x16
+#define DAGB1_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_RDCLI6__MAX_OSD__SHIFT 0x1a
+#define DAGB1_RDCLI6__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_RDCLI6__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_RDCLI6__URG_LOW_MASK 0x00000F00L
+#define DAGB1_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_RDCLI6__MAX_BW_MASK 0x001FE000L
+#define DAGB1_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_RDCLI6__MIN_BW_MASK 0x01C00000L
+#define DAGB1_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_RDCLI6__MAX_OSD_MASK 0xFC000000L
+//DAGB1_RDCLI7
+#define DAGB1_RDCLI7__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_RDCLI7__URG_HIGH__SHIFT 0x4
+#define DAGB1_RDCLI7__URG_LOW__SHIFT 0x8
+#define DAGB1_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_RDCLI7__MAX_BW__SHIFT 0xd
+#define DAGB1_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_RDCLI7__MIN_BW__SHIFT 0x16
+#define DAGB1_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_RDCLI7__MAX_OSD__SHIFT 0x1a
+#define DAGB1_RDCLI7__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_RDCLI7__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_RDCLI7__URG_LOW_MASK 0x00000F00L
+#define DAGB1_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_RDCLI7__MAX_BW_MASK 0x001FE000L
+#define DAGB1_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_RDCLI7__MIN_BW_MASK 0x01C00000L
+#define DAGB1_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_RDCLI7__MAX_OSD_MASK 0xFC000000L
+//DAGB1_RDCLI8
+#define DAGB1_RDCLI8__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_RDCLI8__URG_HIGH__SHIFT 0x4
+#define DAGB1_RDCLI8__URG_LOW__SHIFT 0x8
+#define DAGB1_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_RDCLI8__MAX_BW__SHIFT 0xd
+#define DAGB1_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_RDCLI8__MIN_BW__SHIFT 0x16
+#define DAGB1_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_RDCLI8__MAX_OSD__SHIFT 0x1a
+#define DAGB1_RDCLI8__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_RDCLI8__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_RDCLI8__URG_LOW_MASK 0x00000F00L
+#define DAGB1_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_RDCLI8__MAX_BW_MASK 0x001FE000L
+#define DAGB1_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_RDCLI8__MIN_BW_MASK 0x01C00000L
+#define DAGB1_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_RDCLI8__MAX_OSD_MASK 0xFC000000L
+//DAGB1_RDCLI9
+#define DAGB1_RDCLI9__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_RDCLI9__URG_HIGH__SHIFT 0x4
+#define DAGB1_RDCLI9__URG_LOW__SHIFT 0x8
+#define DAGB1_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_RDCLI9__MAX_BW__SHIFT 0xd
+#define DAGB1_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_RDCLI9__MIN_BW__SHIFT 0x16
+#define DAGB1_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_RDCLI9__MAX_OSD__SHIFT 0x1a
+#define DAGB1_RDCLI9__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_RDCLI9__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_RDCLI9__URG_LOW_MASK 0x00000F00L
+#define DAGB1_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_RDCLI9__MAX_BW_MASK 0x001FE000L
+#define DAGB1_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_RDCLI9__MIN_BW_MASK 0x01C00000L
+#define DAGB1_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_RDCLI9__MAX_OSD_MASK 0xFC000000L
+//DAGB1_RDCLI10
+#define DAGB1_RDCLI10__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_RDCLI10__URG_HIGH__SHIFT 0x4
+#define DAGB1_RDCLI10__URG_LOW__SHIFT 0x8
+#define DAGB1_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_RDCLI10__MAX_BW__SHIFT 0xd
+#define DAGB1_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_RDCLI10__MIN_BW__SHIFT 0x16
+#define DAGB1_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_RDCLI10__MAX_OSD__SHIFT 0x1a
+#define DAGB1_RDCLI10__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_RDCLI10__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_RDCLI10__URG_LOW_MASK 0x00000F00L
+#define DAGB1_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_RDCLI10__MAX_BW_MASK 0x001FE000L
+#define DAGB1_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_RDCLI10__MIN_BW_MASK 0x01C00000L
+#define DAGB1_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_RDCLI10__MAX_OSD_MASK 0xFC000000L
+//DAGB1_RDCLI11
+#define DAGB1_RDCLI11__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_RDCLI11__URG_HIGH__SHIFT 0x4
+#define DAGB1_RDCLI11__URG_LOW__SHIFT 0x8
+#define DAGB1_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_RDCLI11__MAX_BW__SHIFT 0xd
+#define DAGB1_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_RDCLI11__MIN_BW__SHIFT 0x16
+#define DAGB1_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_RDCLI11__MAX_OSD__SHIFT 0x1a
+#define DAGB1_RDCLI11__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_RDCLI11__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_RDCLI11__URG_LOW_MASK 0x00000F00L
+#define DAGB1_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_RDCLI11__MAX_BW_MASK 0x001FE000L
+#define DAGB1_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_RDCLI11__MIN_BW_MASK 0x01C00000L
+#define DAGB1_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_RDCLI11__MAX_OSD_MASK 0xFC000000L
+//DAGB1_RDCLI12
+#define DAGB1_RDCLI12__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_RDCLI12__URG_HIGH__SHIFT 0x4
+#define DAGB1_RDCLI12__URG_LOW__SHIFT 0x8
+#define DAGB1_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_RDCLI12__MAX_BW__SHIFT 0xd
+#define DAGB1_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_RDCLI12__MIN_BW__SHIFT 0x16
+#define DAGB1_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_RDCLI12__MAX_OSD__SHIFT 0x1a
+#define DAGB1_RDCLI12__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_RDCLI12__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_RDCLI12__URG_LOW_MASK 0x00000F00L
+#define DAGB1_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_RDCLI12__MAX_BW_MASK 0x001FE000L
+#define DAGB1_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_RDCLI12__MIN_BW_MASK 0x01C00000L
+#define DAGB1_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_RDCLI12__MAX_OSD_MASK 0xFC000000L
+//DAGB1_RDCLI13
+#define DAGB1_RDCLI13__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_RDCLI13__URG_HIGH__SHIFT 0x4
+#define DAGB1_RDCLI13__URG_LOW__SHIFT 0x8
+#define DAGB1_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_RDCLI13__MAX_BW__SHIFT 0xd
+#define DAGB1_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_RDCLI13__MIN_BW__SHIFT 0x16
+#define DAGB1_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_RDCLI13__MAX_OSD__SHIFT 0x1a
+#define DAGB1_RDCLI13__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_RDCLI13__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_RDCLI13__URG_LOW_MASK 0x00000F00L
+#define DAGB1_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_RDCLI13__MAX_BW_MASK 0x001FE000L
+#define DAGB1_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_RDCLI13__MIN_BW_MASK 0x01C00000L
+#define DAGB1_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_RDCLI13__MAX_OSD_MASK 0xFC000000L
+//DAGB1_RDCLI14
+#define DAGB1_RDCLI14__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_RDCLI14__URG_HIGH__SHIFT 0x4
+#define DAGB1_RDCLI14__URG_LOW__SHIFT 0x8
+#define DAGB1_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_RDCLI14__MAX_BW__SHIFT 0xd
+#define DAGB1_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_RDCLI14__MIN_BW__SHIFT 0x16
+#define DAGB1_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_RDCLI14__MAX_OSD__SHIFT 0x1a
+#define DAGB1_RDCLI14__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_RDCLI14__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_RDCLI14__URG_LOW_MASK 0x00000F00L
+#define DAGB1_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_RDCLI14__MAX_BW_MASK 0x001FE000L
+#define DAGB1_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_RDCLI14__MIN_BW_MASK 0x01C00000L
+#define DAGB1_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_RDCLI14__MAX_OSD_MASK 0xFC000000L
+//DAGB1_RDCLI15
+#define DAGB1_RDCLI15__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_RDCLI15__URG_HIGH__SHIFT 0x4
+#define DAGB1_RDCLI15__URG_LOW__SHIFT 0x8
+#define DAGB1_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_RDCLI15__MAX_BW__SHIFT 0xd
+#define DAGB1_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_RDCLI15__MIN_BW__SHIFT 0x16
+#define DAGB1_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_RDCLI15__MAX_OSD__SHIFT 0x1a
+#define DAGB1_RDCLI15__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_RDCLI15__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_RDCLI15__URG_LOW_MASK 0x00000F00L
+#define DAGB1_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_RDCLI15__MAX_BW_MASK 0x001FE000L
+#define DAGB1_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_RDCLI15__MIN_BW_MASK 0x01C00000L
+#define DAGB1_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_RDCLI15__MAX_OSD_MASK 0xFC000000L
+//DAGB1_RD_CNTL
+#define DAGB1_RD_CNTL__SCLK_FREQ__SHIFT 0x0
+#define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4
+#define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
+#define DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
+#define DAGB1_RD_CNTL__IO_LEVEL__SHIFT 0x11
+#define DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14
+#define DAGB1_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17
+#define DAGB1_RD_CNTL__FIX_JUMP__SHIFT 0x1a
+#define DAGB1_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL
+#define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L
+#define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L
+#define DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L
+#define DAGB1_RD_CNTL__IO_LEVEL_MASK 0x000E0000L
+#define DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L
+#define DAGB1_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L
+#define DAGB1_RD_CNTL__FIX_JUMP_MASK 0x04000000L
+//DAGB1_RD_GMI_CNTL
+#define DAGB1_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0
+#define DAGB1_RD_GMI_CNTL__LEVEL__SHIFT 0x6
+#define DAGB1_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9
+#define DAGB1_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd
+#define DAGB1_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL
+#define DAGB1_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L
+#define DAGB1_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L
+#define DAGB1_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L
+//DAGB1_RD_ADDR_DAGB
+#define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0
+#define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
+#define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
+#define DAGB1_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7
+#define DAGB1_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd
+#define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L
+#define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
+#define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
+#define DAGB1_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L
+#define DAGB1_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L
+//DAGB1_RD_OUTPUT_DAGB_MAX_BURST
+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0
+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4
+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8
+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc
+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14
+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18
+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c
+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL
+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L
+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L
+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L
+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L
+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L
+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L
+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L
+//DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER
+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0
+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4
+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8
+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc
+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14
+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18
+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c
+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL
+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L
+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L
+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L
+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L
+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L
+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L
+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L
+//DAGB1_RD_CGTT_CLK_CTRL
+#define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB1_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB1_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB1_L1TLB_RD_CGTT_CLK_CTRL
+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB1_ATCVM_RD_CGTT_CLK_CTRL
+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB1_RD_ADDR_DAGB_MAX_BURST0
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
+//DAGB1_RD_ADDR_DAGB_LAZY_TIMER0
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
+//DAGB1_RD_ADDR_DAGB_MAX_BURST1
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
+//DAGB1_RD_ADDR_DAGB_LAZY_TIMER1
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
+//DAGB1_RD_VC0_CNTL
+#define DAGB1_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB1_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB1_RD_VC0_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB1_RD_VC0_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB1_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB1_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB1_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB1_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB1_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB1_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB1_RD_VC1_CNTL
+#define DAGB1_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB1_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB1_RD_VC1_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB1_RD_VC1_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB1_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB1_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB1_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB1_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB1_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB1_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB1_RD_VC2_CNTL
+#define DAGB1_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB1_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB1_RD_VC2_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB1_RD_VC2_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB1_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB1_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB1_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB1_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB1_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB1_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB1_RD_VC3_CNTL
+#define DAGB1_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB1_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB1_RD_VC3_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB1_RD_VC3_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB1_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB1_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB1_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB1_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB1_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB1_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB1_RD_VC4_CNTL
+#define DAGB1_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB1_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB1_RD_VC4_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB1_RD_VC4_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB1_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB1_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB1_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB1_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB1_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB1_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB1_RD_VC5_CNTL
+#define DAGB1_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB1_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB1_RD_VC5_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB1_RD_VC5_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB1_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB1_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB1_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB1_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB1_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB1_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB1_RD_VC6_CNTL
+#define DAGB1_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB1_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB1_RD_VC6_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB1_RD_VC6_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB1_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB1_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB1_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB1_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB1_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB1_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB1_RD_VC7_CNTL
+#define DAGB1_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB1_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB1_RD_VC7_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB1_RD_VC7_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB1_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB1_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB1_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB1_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB1_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB1_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB1_RD_CNTL_MISC
+#define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0
+#define DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6
+#define DAGB1_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd
+#define DAGB1_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13
+#define DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14
+#define DAGB1_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15
+#define DAGB1_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a
+#define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL
+#define DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L
+#define DAGB1_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L
+#define DAGB1_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L
+#define DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L
+#define DAGB1_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L
+#define DAGB1_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L
+//DAGB1_RD_TLB_CREDIT
+#define DAGB1_RD_TLB_CREDIT__TLB0__SHIFT 0x0
+#define DAGB1_RD_TLB_CREDIT__TLB1__SHIFT 0x5
+#define DAGB1_RD_TLB_CREDIT__TLB2__SHIFT 0xa
+#define DAGB1_RD_TLB_CREDIT__TLB3__SHIFT 0xf
+#define DAGB1_RD_TLB_CREDIT__TLB4__SHIFT 0x14
+#define DAGB1_RD_TLB_CREDIT__TLB5__SHIFT 0x19
+#define DAGB1_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL
+#define DAGB1_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L
+#define DAGB1_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L
+#define DAGB1_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L
+#define DAGB1_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L
+#define DAGB1_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L
+//DAGB1_RD_RDRET_CREDIT_CNTL
+#define DAGB1_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT 0x0
+#define DAGB1_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT 0x6
+#define DAGB1_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT 0xc
+#define DAGB1_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT 0x12
+#define DAGB1_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT 0x18
+#define DAGB1_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT 0x1e
+#define DAGB1_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT 0x1f
+#define DAGB1_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK 0x0000003FL
+#define DAGB1_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK 0x00000FC0L
+#define DAGB1_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK 0x0003F000L
+#define DAGB1_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK 0x00FC0000L
+#define DAGB1_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK 0x3F000000L
+#define DAGB1_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK 0x40000000L
+#define DAGB1_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK 0x80000000L
+//DAGB1_RD_RDRET_CREDIT_CNTL2
+#define DAGB1_RD_RDRET_CREDIT_CNTL2__IO_CREDIT__SHIFT 0x0
+#define DAGB1_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT__SHIFT 0x6
+#define DAGB1_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT 0xc
+#define DAGB1_RD_RDRET_CREDIT_CNTL2__IO_CREDIT_MASK 0x0000003FL
+#define DAGB1_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT_MASK 0x00000FC0L
+#define DAGB1_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK 0x0007F000L
+//DAGB1_RDCLI_ASK_PENDING
+#define DAGB1_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0
+#define DAGB1_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB1_RDCLI_GO_PENDING
+#define DAGB1_RDCLI_GO_PENDING__BUSY__SHIFT 0x0
+#define DAGB1_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB1_RDCLI_GBLSEND_PENDING
+#define DAGB1_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0
+#define DAGB1_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB1_RDCLI_TLB_PENDING
+#define DAGB1_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0
+#define DAGB1_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB1_RDCLI_OARB_PENDING
+#define DAGB1_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0
+#define DAGB1_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB1_RDCLI_OSD_PENDING
+#define DAGB1_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0
+#define DAGB1_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB1_WRCLI0
+#define DAGB1_WRCLI0__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_WRCLI0__URG_HIGH__SHIFT 0x4
+#define DAGB1_WRCLI0__URG_LOW__SHIFT 0x8
+#define DAGB1_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_WRCLI0__MAX_BW__SHIFT 0xd
+#define DAGB1_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_WRCLI0__MIN_BW__SHIFT 0x16
+#define DAGB1_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_WRCLI0__MAX_OSD__SHIFT 0x1a
+#define DAGB1_WRCLI0__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_WRCLI0__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_WRCLI0__URG_LOW_MASK 0x00000F00L
+#define DAGB1_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_WRCLI0__MAX_BW_MASK 0x001FE000L
+#define DAGB1_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_WRCLI0__MIN_BW_MASK 0x01C00000L
+#define DAGB1_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_WRCLI0__MAX_OSD_MASK 0xFC000000L
+//DAGB1_WRCLI1
+#define DAGB1_WRCLI1__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_WRCLI1__URG_HIGH__SHIFT 0x4
+#define DAGB1_WRCLI1__URG_LOW__SHIFT 0x8
+#define DAGB1_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_WRCLI1__MAX_BW__SHIFT 0xd
+#define DAGB1_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_WRCLI1__MIN_BW__SHIFT 0x16
+#define DAGB1_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_WRCLI1__MAX_OSD__SHIFT 0x1a
+#define DAGB1_WRCLI1__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_WRCLI1__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_WRCLI1__URG_LOW_MASK 0x00000F00L
+#define DAGB1_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_WRCLI1__MAX_BW_MASK 0x001FE000L
+#define DAGB1_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_WRCLI1__MIN_BW_MASK 0x01C00000L
+#define DAGB1_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_WRCLI1__MAX_OSD_MASK 0xFC000000L
+//DAGB1_WRCLI2
+#define DAGB1_WRCLI2__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_WRCLI2__URG_HIGH__SHIFT 0x4
+#define DAGB1_WRCLI2__URG_LOW__SHIFT 0x8
+#define DAGB1_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_WRCLI2__MAX_BW__SHIFT 0xd
+#define DAGB1_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_WRCLI2__MIN_BW__SHIFT 0x16
+#define DAGB1_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_WRCLI2__MAX_OSD__SHIFT 0x1a
+#define DAGB1_WRCLI2__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_WRCLI2__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_WRCLI2__URG_LOW_MASK 0x00000F00L
+#define DAGB1_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_WRCLI2__MAX_BW_MASK 0x001FE000L
+#define DAGB1_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_WRCLI2__MIN_BW_MASK 0x01C00000L
+#define DAGB1_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_WRCLI2__MAX_OSD_MASK 0xFC000000L
+//DAGB1_WRCLI3
+#define DAGB1_WRCLI3__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_WRCLI3__URG_HIGH__SHIFT 0x4
+#define DAGB1_WRCLI3__URG_LOW__SHIFT 0x8
+#define DAGB1_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_WRCLI3__MAX_BW__SHIFT 0xd
+#define DAGB1_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_WRCLI3__MIN_BW__SHIFT 0x16
+#define DAGB1_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_WRCLI3__MAX_OSD__SHIFT 0x1a
+#define DAGB1_WRCLI3__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_WRCLI3__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_WRCLI3__URG_LOW_MASK 0x00000F00L
+#define DAGB1_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_WRCLI3__MAX_BW_MASK 0x001FE000L
+#define DAGB1_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_WRCLI3__MIN_BW_MASK 0x01C00000L
+#define DAGB1_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_WRCLI3__MAX_OSD_MASK 0xFC000000L
+//DAGB1_WRCLI4
+#define DAGB1_WRCLI4__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_WRCLI4__URG_HIGH__SHIFT 0x4
+#define DAGB1_WRCLI4__URG_LOW__SHIFT 0x8
+#define DAGB1_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_WRCLI4__MAX_BW__SHIFT 0xd
+#define DAGB1_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_WRCLI4__MIN_BW__SHIFT 0x16
+#define DAGB1_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_WRCLI4__MAX_OSD__SHIFT 0x1a
+#define DAGB1_WRCLI4__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_WRCLI4__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_WRCLI4__URG_LOW_MASK 0x00000F00L
+#define DAGB1_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_WRCLI4__MAX_BW_MASK 0x001FE000L
+#define DAGB1_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_WRCLI4__MIN_BW_MASK 0x01C00000L
+#define DAGB1_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_WRCLI4__MAX_OSD_MASK 0xFC000000L
+//DAGB1_WRCLI5
+#define DAGB1_WRCLI5__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_WRCLI5__URG_HIGH__SHIFT 0x4
+#define DAGB1_WRCLI5__URG_LOW__SHIFT 0x8
+#define DAGB1_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_WRCLI5__MAX_BW__SHIFT 0xd
+#define DAGB1_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_WRCLI5__MIN_BW__SHIFT 0x16
+#define DAGB1_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_WRCLI5__MAX_OSD__SHIFT 0x1a
+#define DAGB1_WRCLI5__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_WRCLI5__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_WRCLI5__URG_LOW_MASK 0x00000F00L
+#define DAGB1_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_WRCLI5__MAX_BW_MASK 0x001FE000L
+#define DAGB1_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_WRCLI5__MIN_BW_MASK 0x01C00000L
+#define DAGB1_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_WRCLI5__MAX_OSD_MASK 0xFC000000L
+//DAGB1_WRCLI6
+#define DAGB1_WRCLI6__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_WRCLI6__URG_HIGH__SHIFT 0x4
+#define DAGB1_WRCLI6__URG_LOW__SHIFT 0x8
+#define DAGB1_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_WRCLI6__MAX_BW__SHIFT 0xd
+#define DAGB1_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_WRCLI6__MIN_BW__SHIFT 0x16
+#define DAGB1_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_WRCLI6__MAX_OSD__SHIFT 0x1a
+#define DAGB1_WRCLI6__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_WRCLI6__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_WRCLI6__URG_LOW_MASK 0x00000F00L
+#define DAGB1_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_WRCLI6__MAX_BW_MASK 0x001FE000L
+#define DAGB1_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_WRCLI6__MIN_BW_MASK 0x01C00000L
+#define DAGB1_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_WRCLI6__MAX_OSD_MASK 0xFC000000L
+//DAGB1_WRCLI7
+#define DAGB1_WRCLI7__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_WRCLI7__URG_HIGH__SHIFT 0x4
+#define DAGB1_WRCLI7__URG_LOW__SHIFT 0x8
+#define DAGB1_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_WRCLI7__MAX_BW__SHIFT 0xd
+#define DAGB1_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_WRCLI7__MIN_BW__SHIFT 0x16
+#define DAGB1_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_WRCLI7__MAX_OSD__SHIFT 0x1a
+#define DAGB1_WRCLI7__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_WRCLI7__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_WRCLI7__URG_LOW_MASK 0x00000F00L
+#define DAGB1_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_WRCLI7__MAX_BW_MASK 0x001FE000L
+#define DAGB1_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_WRCLI7__MIN_BW_MASK 0x01C00000L
+#define DAGB1_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_WRCLI7__MAX_OSD_MASK 0xFC000000L
+//DAGB1_WRCLI8
+#define DAGB1_WRCLI8__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_WRCLI8__URG_HIGH__SHIFT 0x4
+#define DAGB1_WRCLI8__URG_LOW__SHIFT 0x8
+#define DAGB1_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_WRCLI8__MAX_BW__SHIFT 0xd
+#define DAGB1_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_WRCLI8__MIN_BW__SHIFT 0x16
+#define DAGB1_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_WRCLI8__MAX_OSD__SHIFT 0x1a
+#define DAGB1_WRCLI8__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_WRCLI8__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_WRCLI8__URG_LOW_MASK 0x00000F00L
+#define DAGB1_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_WRCLI8__MAX_BW_MASK 0x001FE000L
+#define DAGB1_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_WRCLI8__MIN_BW_MASK 0x01C00000L
+#define DAGB1_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_WRCLI8__MAX_OSD_MASK 0xFC000000L
+//DAGB1_WRCLI9
+#define DAGB1_WRCLI9__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_WRCLI9__URG_HIGH__SHIFT 0x4
+#define DAGB1_WRCLI9__URG_LOW__SHIFT 0x8
+#define DAGB1_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_WRCLI9__MAX_BW__SHIFT 0xd
+#define DAGB1_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_WRCLI9__MIN_BW__SHIFT 0x16
+#define DAGB1_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_WRCLI9__MAX_OSD__SHIFT 0x1a
+#define DAGB1_WRCLI9__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_WRCLI9__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_WRCLI9__URG_LOW_MASK 0x00000F00L
+#define DAGB1_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_WRCLI9__MAX_BW_MASK 0x001FE000L
+#define DAGB1_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_WRCLI9__MIN_BW_MASK 0x01C00000L
+#define DAGB1_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_WRCLI9__MAX_OSD_MASK 0xFC000000L
+//DAGB1_WRCLI10
+#define DAGB1_WRCLI10__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_WRCLI10__URG_HIGH__SHIFT 0x4
+#define DAGB1_WRCLI10__URG_LOW__SHIFT 0x8
+#define DAGB1_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_WRCLI10__MAX_BW__SHIFT 0xd
+#define DAGB1_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_WRCLI10__MIN_BW__SHIFT 0x16
+#define DAGB1_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_WRCLI10__MAX_OSD__SHIFT 0x1a
+#define DAGB1_WRCLI10__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_WRCLI10__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_WRCLI10__URG_LOW_MASK 0x00000F00L
+#define DAGB1_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_WRCLI10__MAX_BW_MASK 0x001FE000L
+#define DAGB1_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_WRCLI10__MIN_BW_MASK 0x01C00000L
+#define DAGB1_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_WRCLI10__MAX_OSD_MASK 0xFC000000L
+//DAGB1_WRCLI11
+#define DAGB1_WRCLI11__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_WRCLI11__URG_HIGH__SHIFT 0x4
+#define DAGB1_WRCLI11__URG_LOW__SHIFT 0x8
+#define DAGB1_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_WRCLI11__MAX_BW__SHIFT 0xd
+#define DAGB1_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_WRCLI11__MIN_BW__SHIFT 0x16
+#define DAGB1_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_WRCLI11__MAX_OSD__SHIFT 0x1a
+#define DAGB1_WRCLI11__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_WRCLI11__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_WRCLI11__URG_LOW_MASK 0x00000F00L
+#define DAGB1_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_WRCLI11__MAX_BW_MASK 0x001FE000L
+#define DAGB1_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_WRCLI11__MIN_BW_MASK 0x01C00000L
+#define DAGB1_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_WRCLI11__MAX_OSD_MASK 0xFC000000L
+//DAGB1_WRCLI12
+#define DAGB1_WRCLI12__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_WRCLI12__URG_HIGH__SHIFT 0x4
+#define DAGB1_WRCLI12__URG_LOW__SHIFT 0x8
+#define DAGB1_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_WRCLI12__MAX_BW__SHIFT 0xd
+#define DAGB1_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_WRCLI12__MIN_BW__SHIFT 0x16
+#define DAGB1_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_WRCLI12__MAX_OSD__SHIFT 0x1a
+#define DAGB1_WRCLI12__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_WRCLI12__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_WRCLI12__URG_LOW_MASK 0x00000F00L
+#define DAGB1_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_WRCLI12__MAX_BW_MASK 0x001FE000L
+#define DAGB1_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_WRCLI12__MIN_BW_MASK 0x01C00000L
+#define DAGB1_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_WRCLI12__MAX_OSD_MASK 0xFC000000L
+//DAGB1_WRCLI13
+#define DAGB1_WRCLI13__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_WRCLI13__URG_HIGH__SHIFT 0x4
+#define DAGB1_WRCLI13__URG_LOW__SHIFT 0x8
+#define DAGB1_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_WRCLI13__MAX_BW__SHIFT 0xd
+#define DAGB1_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_WRCLI13__MIN_BW__SHIFT 0x16
+#define DAGB1_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_WRCLI13__MAX_OSD__SHIFT 0x1a
+#define DAGB1_WRCLI13__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_WRCLI13__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_WRCLI13__URG_LOW_MASK 0x00000F00L
+#define DAGB1_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_WRCLI13__MAX_BW_MASK 0x001FE000L
+#define DAGB1_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_WRCLI13__MIN_BW_MASK 0x01C00000L
+#define DAGB1_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_WRCLI13__MAX_OSD_MASK 0xFC000000L
+//DAGB1_WRCLI14
+#define DAGB1_WRCLI14__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_WRCLI14__URG_HIGH__SHIFT 0x4
+#define DAGB1_WRCLI14__URG_LOW__SHIFT 0x8
+#define DAGB1_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_WRCLI14__MAX_BW__SHIFT 0xd
+#define DAGB1_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_WRCLI14__MIN_BW__SHIFT 0x16
+#define DAGB1_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_WRCLI14__MAX_OSD__SHIFT 0x1a
+#define DAGB1_WRCLI14__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_WRCLI14__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_WRCLI14__URG_LOW_MASK 0x00000F00L
+#define DAGB1_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_WRCLI14__MAX_BW_MASK 0x001FE000L
+#define DAGB1_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_WRCLI14__MIN_BW_MASK 0x01C00000L
+#define DAGB1_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_WRCLI14__MAX_OSD_MASK 0xFC000000L
+//DAGB1_WRCLI15
+#define DAGB1_WRCLI15__VIRT_CHAN__SHIFT 0x0
+#define DAGB1_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB1_WRCLI15__URG_HIGH__SHIFT 0x4
+#define DAGB1_WRCLI15__URG_LOW__SHIFT 0x8
+#define DAGB1_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB1_WRCLI15__MAX_BW__SHIFT 0xd
+#define DAGB1_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB1_WRCLI15__MIN_BW__SHIFT 0x16
+#define DAGB1_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB1_WRCLI15__MAX_OSD__SHIFT 0x1a
+#define DAGB1_WRCLI15__VIRT_CHAN_MASK 0x00000007L
+#define DAGB1_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB1_WRCLI15__URG_HIGH_MASK 0x000000F0L
+#define DAGB1_WRCLI15__URG_LOW_MASK 0x00000F00L
+#define DAGB1_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB1_WRCLI15__MAX_BW_MASK 0x001FE000L
+#define DAGB1_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB1_WRCLI15__MIN_BW_MASK 0x01C00000L
+#define DAGB1_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB1_WRCLI15__MAX_OSD_MASK 0xFC000000L
+//DAGB1_WR_CNTL
+#define DAGB1_WR_CNTL__SCLK_FREQ__SHIFT 0x0
+#define DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4
+#define DAGB1_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
+#define DAGB1_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
+#define DAGB1_WR_CNTL__IO_LEVEL__SHIFT 0x11
+#define DAGB1_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14
+#define DAGB1_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17
+#define DAGB1_WR_CNTL__FIX_JUMP__SHIFT 0x1a
+#define DAGB1_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL
+#define DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L
+#define DAGB1_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L
+#define DAGB1_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L
+#define DAGB1_WR_CNTL__IO_LEVEL_MASK 0x000E0000L
+#define DAGB1_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L
+#define DAGB1_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L
+#define DAGB1_WR_CNTL__FIX_JUMP_MASK 0x04000000L
+//DAGB1_WR_GMI_CNTL
+#define DAGB1_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0
+#define DAGB1_WR_GMI_CNTL__LEVEL__SHIFT 0x6
+#define DAGB1_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9
+#define DAGB1_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd
+#define DAGB1_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL
+#define DAGB1_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L
+#define DAGB1_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L
+#define DAGB1_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L
+//DAGB1_WR_ADDR_DAGB
+#define DAGB1_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0
+#define DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
+#define DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
+#define DAGB1_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7
+#define DAGB1_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xd
+#define DAGB1_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L
+#define DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
+#define DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
+#define DAGB1_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L
+#define DAGB1_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L
+//DAGB1_WR_OUTPUT_DAGB_MAX_BURST
+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0
+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4
+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8
+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc
+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14
+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18
+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c
+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL
+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L
+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L
+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L
+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L
+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L
+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L
+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L
+//DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER
+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0
+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4
+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8
+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc
+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14
+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18
+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c
+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL
+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L
+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L
+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L
+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L
+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L
+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L
+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L
+//DAGB1_WR_CGTT_CLK_CTRL
+#define DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB1_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB1_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB1_L1TLB_WR_CGTT_CLK_CTRL
+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB1_ATCVM_WR_CGTT_CLK_CTRL
+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB1_WR_ADDR_DAGB_MAX_BURST0
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
+//DAGB1_WR_ADDR_DAGB_LAZY_TIMER0
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
+//DAGB1_WR_ADDR_DAGB_MAX_BURST1
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
+//DAGB1_WR_ADDR_DAGB_LAZY_TIMER1
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
+//DAGB1_WR_DATA_DAGB
+#define DAGB1_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0
+#define DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
+#define DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
+#define DAGB1_WR_DATA_DAGB__WHOAMI__SHIFT 0x7
+#define DAGB1_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L
+#define DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
+#define DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
+#define DAGB1_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L
+//DAGB1_WR_DATA_DAGB_MAX_BURST0
+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
+//DAGB1_WR_DATA_DAGB_LAZY_TIMER0
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
+//DAGB1_WR_DATA_DAGB_MAX_BURST1
+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
+//DAGB1_WR_DATA_DAGB_LAZY_TIMER1
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
+//DAGB1_WR_VC0_CNTL
+#define DAGB1_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB1_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB1_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB1_WR_VC0_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB1_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB1_WR_VC0_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB1_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB1_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB1_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB1_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB1_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB1_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB1_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB1_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB1_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB1_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB1_WR_VC1_CNTL
+#define DAGB1_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB1_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB1_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB1_WR_VC1_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB1_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB1_WR_VC1_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB1_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB1_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB1_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB1_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB1_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB1_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB1_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB1_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB1_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB1_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB1_WR_VC2_CNTL
+#define DAGB1_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB1_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB1_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB1_WR_VC2_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB1_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB1_WR_VC2_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB1_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB1_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB1_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB1_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB1_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB1_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB1_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB1_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB1_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB1_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB1_WR_VC3_CNTL
+#define DAGB1_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB1_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB1_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB1_WR_VC3_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB1_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB1_WR_VC3_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB1_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB1_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB1_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB1_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB1_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB1_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB1_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB1_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB1_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB1_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB1_WR_VC4_CNTL
+#define DAGB1_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB1_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB1_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB1_WR_VC4_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB1_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB1_WR_VC4_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB1_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB1_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB1_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB1_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB1_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB1_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB1_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB1_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB1_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB1_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB1_WR_VC5_CNTL
+#define DAGB1_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB1_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB1_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB1_WR_VC5_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB1_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB1_WR_VC5_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB1_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB1_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB1_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB1_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB1_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB1_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB1_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB1_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB1_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB1_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB1_WR_VC6_CNTL
+#define DAGB1_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB1_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB1_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB1_WR_VC6_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB1_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB1_WR_VC6_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB1_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB1_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB1_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB1_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB1_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB1_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB1_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB1_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB1_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB1_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB1_WR_VC7_CNTL
+#define DAGB1_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB1_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB1_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB1_WR_VC7_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB1_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB1_WR_VC7_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB1_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB1_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB1_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB1_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB1_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB1_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB1_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB1_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB1_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB1_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB1_WR_CNTL_MISC
+#define DAGB1_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0
+#define DAGB1_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6
+#define DAGB1_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd
+#define DAGB1_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13
+#define DAGB1_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14
+#define DAGB1_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15
+#define DAGB1_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a
+#define DAGB1_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL
+#define DAGB1_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L
+#define DAGB1_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L
+#define DAGB1_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L
+#define DAGB1_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L
+#define DAGB1_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L
+#define DAGB1_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L
+//DAGB1_WR_TLB_CREDIT
+#define DAGB1_WR_TLB_CREDIT__TLB0__SHIFT 0x0
+#define DAGB1_WR_TLB_CREDIT__TLB1__SHIFT 0x5
+#define DAGB1_WR_TLB_CREDIT__TLB2__SHIFT 0xa
+#define DAGB1_WR_TLB_CREDIT__TLB3__SHIFT 0xf
+#define DAGB1_WR_TLB_CREDIT__TLB4__SHIFT 0x14
+#define DAGB1_WR_TLB_CREDIT__TLB5__SHIFT 0x19
+#define DAGB1_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL
+#define DAGB1_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L
+#define DAGB1_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L
+#define DAGB1_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L
+#define DAGB1_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L
+#define DAGB1_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L
+//DAGB1_WR_DATA_CREDIT
+#define DAGB1_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0
+#define DAGB1_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8
+#define DAGB1_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10
+#define DAGB1_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18
+#define DAGB1_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL
+#define DAGB1_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L
+#define DAGB1_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L
+#define DAGB1_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L
+//DAGB1_WR_MISC_CREDIT
+#define DAGB1_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0
+#define DAGB1_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6
+#define DAGB1_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9
+#define DAGB1_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10
+#define DAGB1_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL
+#define DAGB1_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L
+#define DAGB1_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L
+#define DAGB1_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L
+//DAGB1_WR_OSD_CREDIT_CNTL1
+#define DAGB1_WR_OSD_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0
+#define DAGB1_WR_OSD_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x4
+#define DAGB1_WR_OSD_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0x8
+#define DAGB1_WR_OSD_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xc
+#define DAGB1_WR_OSD_CREDIT_CNTL1__IO_CREDIT__SHIFT 0x10
+#define DAGB1_WR_OSD_CREDIT_CNTL1__GMI_CREDIT__SHIFT 0x14
+#define DAGB1_WR_OSD_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x18
+#define DAGB1_WR_OSD_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000000FL
+#define DAGB1_WR_OSD_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000000F0L
+#define DAGB1_WR_OSD_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00000F00L
+#define DAGB1_WR_OSD_CREDIT_CNTL1__VC3_CREDIT_MASK 0x0000F000L
+#define DAGB1_WR_OSD_CREDIT_CNTL1__IO_CREDIT_MASK 0x000F0000L
+#define DAGB1_WR_OSD_CREDIT_CNTL1__GMI_CREDIT_MASK 0x00F00000L
+#define DAGB1_WR_OSD_CREDIT_CNTL1__POOL_CREDIT_MASK 0x3F000000L
+//DAGB1_WR_OSD_CREDIT_CNTL2
+#define DAGB1_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN__SHIFT 0x0
+#define DAGB1_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY__SHIFT 0x4
+#define DAGB1_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN_MASK 0x0000000FL
+#define DAGB1_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY_MASK 0x00000010L
+//DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1
+#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0
+#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5
+#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa
+#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf
+#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14
+#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x19
+#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1a
+#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1b
+#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1__SHIFT 0x1c
+#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2__SHIFT 0x1d
+#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL
+#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L
+#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L
+#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L
+#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x01F00000L
+#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x02000000L
+#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x04000000L
+#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK 0x08000000L
+#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1_MASK 0x10000000L
+#define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2_MASK 0x20000000L
+//DAGB1_WRCLI_GPU_SNOOP_OVERRIDE
+#define DAGB1_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0
+#define DAGB1_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL
+//DAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE
+#define DAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0
+#define DAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0xFFFFFFFFL
+//DAGB1_WRCLI_ASK_PENDING
+#define DAGB1_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0
+#define DAGB1_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB1_WRCLI_GO_PENDING
+#define DAGB1_WRCLI_GO_PENDING__BUSY__SHIFT 0x0
+#define DAGB1_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB1_WRCLI_GBLSEND_PENDING
+#define DAGB1_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0
+#define DAGB1_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB1_WRCLI_TLB_PENDING
+#define DAGB1_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0
+#define DAGB1_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB1_WRCLI_OARB_PENDING
+#define DAGB1_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0
+#define DAGB1_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB1_WRCLI_OSD_PENDING
+#define DAGB1_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0
+#define DAGB1_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB1_WRCLI_DBUS_ASK_PENDING
+#define DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0
+#define DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB1_WRCLI_DBUS_GO_PENDING
+#define DAGB1_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0
+#define DAGB1_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB1_DAGB_DLY
+#define DAGB1_DAGB_DLY__DLY__SHIFT 0x0
+#define DAGB1_DAGB_DLY__CLI__SHIFT 0x8
+#define DAGB1_DAGB_DLY__POS__SHIFT 0x10
+#define DAGB1_DAGB_DLY__DLY_MASK 0x000000FFL
+#define DAGB1_DAGB_DLY__CLI_MASK 0x0000FF00L
+#define DAGB1_DAGB_DLY__POS_MASK 0x000F0000L
+//DAGB1_CNTL_MISC
+#define DAGB1_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0
+#define DAGB1_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3
+#define DAGB1_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6
+#define DAGB1_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9
+#define DAGB1_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc
+#define DAGB1_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf
+#define DAGB1_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12
+#define DAGB1_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15
+#define DAGB1_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18
+#define DAGB1_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e
+#define DAGB1_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L
+#define DAGB1_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L
+#define DAGB1_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L
+#define DAGB1_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L
+#define DAGB1_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L
+#define DAGB1_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L
+#define DAGB1_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L
+#define DAGB1_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L
+#define DAGB1_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L
+#define DAGB1_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L
+//DAGB1_CNTL_MISC2
+#define DAGB1_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0
+#define DAGB1_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1
+#define DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2
+#define DAGB1_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3
+#define DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4
+#define DAGB1_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5
+#define DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6
+#define DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7
+#define DAGB1_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8
+#define DAGB1_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9
+#define DAGB1_CNTL_MISC2__SWAP_CTL__SHIFT 0xa
+#define DAGB1_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb
+#define DAGB1_CNTL_MISC2__HDP_CID__SHIFT 0xc
+#define DAGB1_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x11
+#define DAGB1_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L
+#define DAGB1_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L
+#define DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L
+#define DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L
+#define DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L
+#define DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L
+#define DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L
+#define DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L
+#define DAGB1_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L
+#define DAGB1_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L
+#define DAGB1_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L
+#define DAGB1_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L
+#define DAGB1_CNTL_MISC2__HDP_CID_MASK 0x0001F000L
+#define DAGB1_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x007E0000L
+//DAGB1_FATAL_ERROR_CNTL
+#define DAGB1_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT 0x0
+#define DAGB1_FATAL_ERROR_CNTL__FILTER_NUM_MASK 0x000003FFL
+//DAGB1_FATAL_ERROR_CLEAR
+#define DAGB1_FATAL_ERROR_CLEAR__CLEAR__SHIFT 0x0
+#define DAGB1_FATAL_ERROR_CLEAR__CLEAR_MASK 0x00000001L
+//DAGB1_FATAL_ERROR_STATUS0
+#define DAGB1_FATAL_ERROR_STATUS0__VALID__SHIFT 0x0
+#define DAGB1_FATAL_ERROR_STATUS0__CID__SHIFT 0x1
+#define DAGB1_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT 0x6
+#define DAGB1_FATAL_ERROR_STATUS0__VALID_MASK 0x00000001L
+#define DAGB1_FATAL_ERROR_STATUS0__CID_MASK 0x0000003EL
+#define DAGB1_FATAL_ERROR_STATUS0__ADDR_LO_MASK 0xFFFFFFC0L
+//DAGB1_FATAL_ERROR_STATUS1
+#define DAGB1_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT 0x0
+#define DAGB1_FATAL_ERROR_STATUS1__ADDR_HI_MASK 0x0001FFFFL
+//DAGB1_FATAL_ERROR_STATUS2
+#define DAGB1_FATAL_ERROR_STATUS2__TAG__SHIFT 0x0
+#define DAGB1_FATAL_ERROR_STATUS2__VFID__SHIFT 0x10
+#define DAGB1_FATAL_ERROR_STATUS2__VF__SHIFT 0x14
+#define DAGB1_FATAL_ERROR_STATUS2__SPACE__SHIFT 0x15
+#define DAGB1_FATAL_ERROR_STATUS2__IO__SHIFT 0x16
+#define DAGB1_FATAL_ERROR_STATUS2__SIZE__SHIFT 0x17
+#define DAGB1_FATAL_ERROR_STATUS2__FED__SHIFT 0x19
+#define DAGB1_FATAL_ERROR_STATUS2__TAG_MASK 0x0000FFFFL
+#define DAGB1_FATAL_ERROR_STATUS2__VFID_MASK 0x000F0000L
+#define DAGB1_FATAL_ERROR_STATUS2__VF_MASK 0x00100000L
+#define DAGB1_FATAL_ERROR_STATUS2__SPACE_MASK 0x00200000L
+#define DAGB1_FATAL_ERROR_STATUS2__IO_MASK 0x00400000L
+#define DAGB1_FATAL_ERROR_STATUS2__SIZE_MASK 0x00800000L
+#define DAGB1_FATAL_ERROR_STATUS2__FED_MASK 0x02000000L
+//DAGB1_FATAL_ERROR_STATUS3
+#define DAGB1_FATAL_ERROR_STATUS3__OP__SHIFT 0x6
+#define DAGB1_FATAL_ERROR_STATUS3__WRTMZ__SHIFT 0x10
+#define DAGB1_FATAL_ERROR_STATUS3__RDTMZ__SHIFT 0x11
+#define DAGB1_FATAL_ERROR_STATUS3__SNOOP__SHIFT 0x12
+#define DAGB1_FATAL_ERROR_STATUS3__INVAL__SHIFT 0x13
+#define DAGB1_FATAL_ERROR_STATUS3__NACK__SHIFT 0x14
+#define DAGB1_FATAL_ERROR_STATUS3__RO__SHIFT 0x16
+#define DAGB1_FATAL_ERROR_STATUS3__MEMLOG__SHIFT 0x17
+#define DAGB1_FATAL_ERROR_STATUS3__EOP__SHIFT 0x18
+#define DAGB1_FATAL_ERROR_STATUS3__OP_MASK 0x00001FC0L
+#define DAGB1_FATAL_ERROR_STATUS3__WRTMZ_MASK 0x00010000L
+#define DAGB1_FATAL_ERROR_STATUS3__RDTMZ_MASK 0x00020000L
+#define DAGB1_FATAL_ERROR_STATUS3__SNOOP_MASK 0x00040000L
+#define DAGB1_FATAL_ERROR_STATUS3__INVAL_MASK 0x00080000L
+#define DAGB1_FATAL_ERROR_STATUS3__NACK_MASK 0x00300000L
+#define DAGB1_FATAL_ERROR_STATUS3__RO_MASK 0x00400000L
+#define DAGB1_FATAL_ERROR_STATUS3__MEMLOG_MASK 0x00800000L
+#define DAGB1_FATAL_ERROR_STATUS3__EOP_MASK 0x01000000L
+//DAGB1_FIFO_EMPTY
+#define DAGB1_FIFO_EMPTY__EMPTY__SHIFT 0x0
+#define DAGB1_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL
+//DAGB1_FIFO_FULL
+#define DAGB1_FIFO_FULL__FULL__SHIFT 0x0
+#define DAGB1_FIFO_FULL__FULL_MASK 0x007FFFFFL
+//DAGB1_WR_CREDITS_FULL
+#define DAGB1_WR_CREDITS_FULL__FULL__SHIFT 0x0
+#define DAGB1_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL
+//DAGB1_RD_CREDITS_FULL
+#define DAGB1_RD_CREDITS_FULL__FULL__SHIFT 0x0
+#define DAGB1_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL
+//DAGB1_PERFCOUNTER_LO
+#define DAGB1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define DAGB1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//DAGB1_PERFCOUNTER_HI
+#define DAGB1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define DAGB1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//DAGB1_PERFCOUNTER0_CFG
+#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define DAGB1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define DAGB1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define DAGB1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define DAGB1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define DAGB1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define DAGB1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//DAGB1_PERFCOUNTER1_CFG
+#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define DAGB1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define DAGB1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define DAGB1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define DAGB1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define DAGB1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define DAGB1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//DAGB1_PERFCOUNTER2_CFG
+#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define DAGB1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define DAGB1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define DAGB1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
+#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define DAGB1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
+#define DAGB1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
+#define DAGB1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
+//DAGB1_PERFCOUNTER_RSLT_CNTL
+#define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+//DAGB1_L1TLB_REG_RW
+#define DAGB1_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0
+#define DAGB1_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1
+#define DAGB1_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL__SHIFT 0x2
+#define DAGB1_L1TLB_REG_RW__WDAT_PARITY_CHECK__SHIFT 0x4
+#define DAGB1_L1TLB_REG_RW__DISABLE_RDRET_CHECK__SHIFT 0x5
+#define DAGB1_L1TLB_REG_RW__RESERVE__SHIFT 0x6
+#define DAGB1_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L
+#define DAGB1_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L
+#define DAGB1_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL_MASK 0x00000004L
+#define DAGB1_L1TLB_REG_RW__WDAT_PARITY_CHECK_MASK 0x00000010L
+#define DAGB1_L1TLB_REG_RW__DISABLE_RDRET_CHECK_MASK 0x00000020L
+#define DAGB1_L1TLB_REG_RW__RESERVE_MASK 0xFFFFFFC0L
+//DAGB1_RESERVE1
+#define DAGB1_RESERVE1__RESERVE__SHIFT 0x0
+#define DAGB1_RESERVE1__RESERVE_MASK 0xFFFFFFFFL
+//DAGB1_RESERVE2
+#define DAGB1_RESERVE2__RESERVE__SHIFT 0x0
+#define DAGB1_RESERVE2__RESERVE_MASK 0xFFFFFFFFL
+//DAGB1_RESERVE3
+#define DAGB1_RESERVE3__RESERVE__SHIFT 0x0
+#define DAGB1_RESERVE3__RESERVE_MASK 0xFFFFFFFFL
+//DAGB1_RESERVE4
+#define DAGB1_RESERVE4__RESERVE__SHIFT 0x0
+#define DAGB1_RESERVE4__RESERVE_MASK 0xFFFFFFFFL
+
+
+// addressBlock: mmhub_dagb_dagbdec2
+//DAGB2_RDCLI0
+#define DAGB2_RDCLI0__VIRT_CHAN__SHIFT 0x0
+#define DAGB2_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB2_RDCLI0__URG_HIGH__SHIFT 0x4
+#define DAGB2_RDCLI0__URG_LOW__SHIFT 0x8
+#define DAGB2_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB2_RDCLI0__MAX_BW__SHIFT 0xd
+#define DAGB2_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB2_RDCLI0__MIN_BW__SHIFT 0x16
+#define DAGB2_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB2_RDCLI0__MAX_OSD__SHIFT 0x1a
+#define DAGB2_RDCLI0__VIRT_CHAN_MASK 0x00000007L
+#define DAGB2_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB2_RDCLI0__URG_HIGH_MASK 0x000000F0L
+#define DAGB2_RDCLI0__URG_LOW_MASK 0x00000F00L
+#define DAGB2_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB2_RDCLI0__MAX_BW_MASK 0x001FE000L
+#define DAGB2_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB2_RDCLI0__MIN_BW_MASK 0x01C00000L
+#define DAGB2_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB2_RDCLI0__MAX_OSD_MASK 0xFC000000L
+//DAGB2_RDCLI1
+#define DAGB2_RDCLI1__VIRT_CHAN__SHIFT 0x0
+#define DAGB2_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB2_RDCLI1__URG_HIGH__SHIFT 0x4
+#define DAGB2_RDCLI1__URG_LOW__SHIFT 0x8
+#define DAGB2_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB2_RDCLI1__MAX_BW__SHIFT 0xd
+#define DAGB2_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB2_RDCLI1__MIN_BW__SHIFT 0x16
+#define DAGB2_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB2_RDCLI1__MAX_OSD__SHIFT 0x1a
+#define DAGB2_RDCLI1__VIRT_CHAN_MASK 0x00000007L
+#define DAGB2_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB2_RDCLI1__URG_HIGH_MASK 0x000000F0L
+#define DAGB2_RDCLI1__URG_LOW_MASK 0x00000F00L
+#define DAGB2_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB2_RDCLI1__MAX_BW_MASK 0x001FE000L
+#define DAGB2_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB2_RDCLI1__MIN_BW_MASK 0x01C00000L
+#define DAGB2_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB2_RDCLI1__MAX_OSD_MASK 0xFC000000L
+//DAGB2_RDCLI2
+#define DAGB2_RDCLI2__VIRT_CHAN__SHIFT 0x0
+#define DAGB2_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB2_RDCLI2__URG_HIGH__SHIFT 0x4
+#define DAGB2_RDCLI2__URG_LOW__SHIFT 0x8
+#define DAGB2_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB2_RDCLI2__MAX_BW__SHIFT 0xd
+#define DAGB2_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB2_RDCLI2__MIN_BW__SHIFT 0x16
+#define DAGB2_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB2_RDCLI2__MAX_OSD__SHIFT 0x1a
+#define DAGB2_RDCLI2__VIRT_CHAN_MASK 0x00000007L
+#define DAGB2_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB2_RDCLI2__URG_HIGH_MASK 0x000000F0L
+#define DAGB2_RDCLI2__URG_LOW_MASK 0x00000F00L
+#define DAGB2_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB2_RDCLI2__MAX_BW_MASK 0x001FE000L
+#define DAGB2_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB2_RDCLI2__MIN_BW_MASK 0x01C00000L
+#define DAGB2_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB2_RDCLI2__MAX_OSD_MASK 0xFC000000L
+//DAGB2_RDCLI3
+#define DAGB2_RDCLI3__VIRT_CHAN__SHIFT 0x0
+#define DAGB2_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB2_RDCLI3__URG_HIGH__SHIFT 0x4
+#define DAGB2_RDCLI3__URG_LOW__SHIFT 0x8
+#define DAGB2_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB2_RDCLI3__MAX_BW__SHIFT 0xd
+#define DAGB2_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB2_RDCLI3__MIN_BW__SHIFT 0x16
+#define DAGB2_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB2_RDCLI3__MAX_OSD__SHIFT 0x1a
+#define DAGB2_RDCLI3__VIRT_CHAN_MASK 0x00000007L
+#define DAGB2_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB2_RDCLI3__URG_HIGH_MASK 0x000000F0L
+#define DAGB2_RDCLI3__URG_LOW_MASK 0x00000F00L
+#define DAGB2_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB2_RDCLI3__MAX_BW_MASK 0x001FE000L
+#define DAGB2_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB2_RDCLI3__MIN_BW_MASK 0x01C00000L
+#define DAGB2_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB2_RDCLI3__MAX_OSD_MASK 0xFC000000L
+//DAGB2_RDCLI4
+#define DAGB2_RDCLI4__VIRT_CHAN__SHIFT 0x0
+#define DAGB2_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB2_RDCLI4__URG_HIGH__SHIFT 0x4
+#define DAGB2_RDCLI4__URG_LOW__SHIFT 0x8
+#define DAGB2_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB2_RDCLI4__MAX_BW__SHIFT 0xd
+#define DAGB2_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB2_RDCLI4__MIN_BW__SHIFT 0x16
+#define DAGB2_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB2_RDCLI4__MAX_OSD__SHIFT 0x1a
+#define DAGB2_RDCLI4__VIRT_CHAN_MASK 0x00000007L
+#define DAGB2_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB2_RDCLI4__URG_HIGH_MASK 0x000000F0L
+#define DAGB2_RDCLI4__URG_LOW_MASK 0x00000F00L
+#define DAGB2_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB2_RDCLI4__MAX_BW_MASK 0x001FE000L
+#define DAGB2_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB2_RDCLI4__MIN_BW_MASK 0x01C00000L
+#define DAGB2_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB2_RDCLI4__MAX_OSD_MASK 0xFC000000L
+//DAGB2_RDCLI5
+#define DAGB2_RDCLI5__VIRT_CHAN__SHIFT 0x0
+#define DAGB2_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB2_RDCLI5__URG_HIGH__SHIFT 0x4
+#define DAGB2_RDCLI5__URG_LOW__SHIFT 0x8
+#define DAGB2_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB2_RDCLI5__MAX_BW__SHIFT 0xd
+#define DAGB2_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB2_RDCLI5__MIN_BW__SHIFT 0x16
+#define DAGB2_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB2_RDCLI5__MAX_OSD__SHIFT 0x1a
+#define DAGB2_RDCLI5__VIRT_CHAN_MASK 0x00000007L
+#define DAGB2_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB2_RDCLI5__URG_HIGH_MASK 0x000000F0L
+#define DAGB2_RDCLI5__URG_LOW_MASK 0x00000F00L
+#define DAGB2_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB2_RDCLI5__MAX_BW_MASK 0x001FE000L
+#define DAGB2_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB2_RDCLI5__MIN_BW_MASK 0x01C00000L
+#define DAGB2_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB2_RDCLI5__MAX_OSD_MASK 0xFC000000L
+//DAGB2_RDCLI6
+#define DAGB2_RDCLI6__VIRT_CHAN__SHIFT 0x0
+#define DAGB2_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB2_RDCLI6__URG_HIGH__SHIFT 0x4
+#define DAGB2_RDCLI6__URG_LOW__SHIFT 0x8
+#define DAGB2_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB2_RDCLI6__MAX_BW__SHIFT 0xd
+#define DAGB2_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB2_RDCLI6__MIN_BW__SHIFT 0x16
+#define DAGB2_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB2_RDCLI6__MAX_OSD__SHIFT 0x1a
+#define DAGB2_RDCLI6__VIRT_CHAN_MASK 0x00000007L
+#define DAGB2_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB2_RDCLI6__URG_HIGH_MASK 0x000000F0L
+#define DAGB2_RDCLI6__URG_LOW_MASK 0x00000F00L
+#define DAGB2_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB2_RDCLI6__MAX_BW_MASK 0x001FE000L
+#define DAGB2_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB2_RDCLI6__MIN_BW_MASK 0x01C00000L
+#define DAGB2_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB2_RDCLI6__MAX_OSD_MASK 0xFC000000L
+//DAGB2_RDCLI7
+#define DAGB2_RDCLI7__VIRT_CHAN__SHIFT 0x0
+#define DAGB2_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB2_RDCLI7__URG_HIGH__SHIFT 0x4
+#define DAGB2_RDCLI7__URG_LOW__SHIFT 0x8
+#define DAGB2_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB2_RDCLI7__MAX_BW__SHIFT 0xd
+#define DAGB2_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB2_RDCLI7__MIN_BW__SHIFT 0x16
+#define DAGB2_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB2_RDCLI7__MAX_OSD__SHIFT 0x1a
+#define DAGB2_RDCLI7__VIRT_CHAN_MASK 0x00000007L
+#define DAGB2_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB2_RDCLI7__URG_HIGH_MASK 0x000000F0L
+#define DAGB2_RDCLI7__URG_LOW_MASK 0x00000F00L
+#define DAGB2_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB2_RDCLI7__MAX_BW_MASK 0x001FE000L
+#define DAGB2_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB2_RDCLI7__MIN_BW_MASK 0x01C00000L
+#define DAGB2_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB2_RDCLI7__MAX_OSD_MASK 0xFC000000L
+//DAGB2_RDCLI8
+#define DAGB2_RDCLI8__VIRT_CHAN__SHIFT 0x0
+#define DAGB2_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB2_RDCLI8__URG_HIGH__SHIFT 0x4
+#define DAGB2_RDCLI8__URG_LOW__SHIFT 0x8
+#define DAGB2_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB2_RDCLI8__MAX_BW__SHIFT 0xd
+#define DAGB2_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB2_RDCLI8__MIN_BW__SHIFT 0x16
+#define DAGB2_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB2_RDCLI8__MAX_OSD__SHIFT 0x1a
+#define DAGB2_RDCLI8__VIRT_CHAN_MASK 0x00000007L
+#define DAGB2_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB2_RDCLI8__URG_HIGH_MASK 0x000000F0L
+#define DAGB2_RDCLI8__URG_LOW_MASK 0x00000F00L
+#define DAGB2_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB2_RDCLI8__MAX_BW_MASK 0x001FE000L
+#define DAGB2_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB2_RDCLI8__MIN_BW_MASK 0x01C00000L
+#define DAGB2_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB2_RDCLI8__MAX_OSD_MASK 0xFC000000L
+//DAGB2_RDCLI9
+#define DAGB2_RDCLI9__VIRT_CHAN__SHIFT 0x0
+#define DAGB2_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB2_RDCLI9__URG_HIGH__SHIFT 0x4
+#define DAGB2_RDCLI9__URG_LOW__SHIFT 0x8
+#define DAGB2_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB2_RDCLI9__MAX_BW__SHIFT 0xd
+#define DAGB2_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB2_RDCLI9__MIN_BW__SHIFT 0x16
+#define DAGB2_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB2_RDCLI9__MAX_OSD__SHIFT 0x1a
+#define DAGB2_RDCLI9__VIRT_CHAN_MASK 0x00000007L
+#define DAGB2_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB2_RDCLI9__URG_HIGH_MASK 0x000000F0L
+#define DAGB2_RDCLI9__URG_LOW_MASK 0x00000F00L
+#define DAGB2_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB2_RDCLI9__MAX_BW_MASK 0x001FE000L
+#define DAGB2_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB2_RDCLI9__MIN_BW_MASK 0x01C00000L
+#define DAGB2_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB2_RDCLI9__MAX_OSD_MASK 0xFC000000L
+//DAGB2_RDCLI10
+#define DAGB2_RDCLI10__VIRT_CHAN__SHIFT 0x0
+#define DAGB2_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB2_RDCLI10__URG_HIGH__SHIFT 0x4
+#define DAGB2_RDCLI10__URG_LOW__SHIFT 0x8
+#define DAGB2_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB2_RDCLI10__MAX_BW__SHIFT 0xd
+#define DAGB2_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB2_RDCLI10__MIN_BW__SHIFT 0x16
+#define DAGB2_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB2_RDCLI10__MAX_OSD__SHIFT 0x1a
+#define DAGB2_RDCLI10__VIRT_CHAN_MASK 0x00000007L
+#define DAGB2_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB2_RDCLI10__URG_HIGH_MASK 0x000000F0L
+#define DAGB2_RDCLI10__URG_LOW_MASK 0x00000F00L
+#define DAGB2_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB2_RDCLI10__MAX_BW_MASK 0x001FE000L
+#define DAGB2_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB2_RDCLI10__MIN_BW_MASK 0x01C00000L
+#define DAGB2_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB2_RDCLI10__MAX_OSD_MASK 0xFC000000L
+//DAGB2_RDCLI11
+#define DAGB2_RDCLI11__VIRT_CHAN__SHIFT 0x0
+#define DAGB2_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB2_RDCLI11__URG_HIGH__SHIFT 0x4
+#define DAGB2_RDCLI11__URG_LOW__SHIFT 0x8
+#define DAGB2_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB2_RDCLI11__MAX_BW__SHIFT 0xd
+#define DAGB2_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB2_RDCLI11__MIN_BW__SHIFT 0x16
+#define DAGB2_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB2_RDCLI11__MAX_OSD__SHIFT 0x1a
+#define DAGB2_RDCLI11__VIRT_CHAN_MASK 0x00000007L
+#define DAGB2_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB2_RDCLI11__URG_HIGH_MASK 0x000000F0L
+#define DAGB2_RDCLI11__URG_LOW_MASK 0x00000F00L
+#define DAGB2_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB2_RDCLI11__MAX_BW_MASK 0x001FE000L
+#define DAGB2_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB2_RDCLI11__MIN_BW_MASK 0x01C00000L
+#define DAGB2_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB2_RDCLI11__MAX_OSD_MASK 0xFC000000L
+//DAGB2_RDCLI12
+#define DAGB2_RDCLI12__VIRT_CHAN__SHIFT 0x0
+#define DAGB2_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB2_RDCLI12__URG_HIGH__SHIFT 0x4
+#define DAGB2_RDCLI12__URG_LOW__SHIFT 0x8
+#define DAGB2_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB2_RDCLI12__MAX_BW__SHIFT 0xd
+#define DAGB2_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB2_RDCLI12__MIN_BW__SHIFT 0x16
+#define DAGB2_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB2_RDCLI12__MAX_OSD__SHIFT 0x1a
+#define DAGB2_RDCLI12__VIRT_CHAN_MASK 0x00000007L
+#define DAGB2_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB2_RDCLI12__URG_HIGH_MASK 0x000000F0L
+#define DAGB2_RDCLI12__URG_LOW_MASK 0x00000F00L
+#define DAGB2_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB2_RDCLI12__MAX_BW_MASK 0x001FE000L
+#define DAGB2_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB2_RDCLI12__MIN_BW_MASK 0x01C00000L
+#define DAGB2_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB2_RDCLI12__MAX_OSD_MASK 0xFC000000L
+//DAGB2_RDCLI13
+#define DAGB2_RDCLI13__VIRT_CHAN__SHIFT 0x0
+#define DAGB2_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB2_RDCLI13__URG_HIGH__SHIFT 0x4
+#define DAGB2_RDCLI13__URG_LOW__SHIFT 0x8
+#define DAGB2_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB2_RDCLI13__MAX_BW__SHIFT 0xd
+#define DAGB2_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB2_RDCLI13__MIN_BW__SHIFT 0x16
+#define DAGB2_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB2_RDCLI13__MAX_OSD__SHIFT 0x1a
+#define DAGB2_RDCLI13__VIRT_CHAN_MASK 0x00000007L
+#define DAGB2_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB2_RDCLI13__URG_HIGH_MASK 0x000000F0L
+#define DAGB2_RDCLI13__URG_LOW_MASK 0x00000F00L
+#define DAGB2_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB2_RDCLI13__MAX_BW_MASK 0x001FE000L
+#define DAGB2_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB2_RDCLI13__MIN_BW_MASK 0x01C00000L
+#define DAGB2_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB2_RDCLI13__MAX_OSD_MASK 0xFC000000L
+//DAGB2_RDCLI14
+#define DAGB2_RDCLI14__VIRT_CHAN__SHIFT 0x0
+#define DAGB2_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB2_RDCLI14__URG_HIGH__SHIFT 0x4
+#define DAGB2_RDCLI14__URG_LOW__SHIFT 0x8
+#define DAGB2_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB2_RDCLI14__MAX_BW__SHIFT 0xd
+#define DAGB2_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB2_RDCLI14__MIN_BW__SHIFT 0x16
+#define DAGB2_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB2_RDCLI14__MAX_OSD__SHIFT 0x1a
+#define DAGB2_RDCLI14__VIRT_CHAN_MASK 0x00000007L
+#define DAGB2_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB2_RDCLI14__URG_HIGH_MASK 0x000000F0L
+#define DAGB2_RDCLI14__URG_LOW_MASK 0x00000F00L
+#define DAGB2_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB2_RDCLI14__MAX_BW_MASK 0x001FE000L
+#define DAGB2_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB2_RDCLI14__MIN_BW_MASK 0x01C00000L
+#define DAGB2_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB2_RDCLI14__MAX_OSD_MASK 0xFC000000L
+//DAGB2_RDCLI15
+#define DAGB2_RDCLI15__VIRT_CHAN__SHIFT 0x0
+#define DAGB2_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB2_RDCLI15__URG_HIGH__SHIFT 0x4
+#define DAGB2_RDCLI15__URG_LOW__SHIFT 0x8
+#define DAGB2_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB2_RDCLI15__MAX_BW__SHIFT 0xd
+#define DAGB2_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB2_RDCLI15__MIN_BW__SHIFT 0x16
+#define DAGB2_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB2_RDCLI15__MAX_OSD__SHIFT 0x1a
+#define DAGB2_RDCLI15__VIRT_CHAN_MASK 0x00000007L
+#define DAGB2_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB2_RDCLI15__URG_HIGH_MASK 0x000000F0L
+#define DAGB2_RDCLI15__URG_LOW_MASK 0x00000F00L
+#define DAGB2_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB2_RDCLI15__MAX_BW_MASK 0x001FE000L
+#define DAGB2_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB2_RDCLI15__MIN_BW_MASK 0x01C00000L
+#define DAGB2_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB2_RDCLI15__MAX_OSD_MASK 0xFC000000L
+//DAGB2_RD_CNTL
+#define DAGB2_RD_CNTL__SCLK_FREQ__SHIFT 0x0
+#define DAGB2_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4
+#define DAGB2_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
+#define DAGB2_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
+#define DAGB2_RD_CNTL__IO_LEVEL__SHIFT 0x11
+#define DAGB2_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14
+#define DAGB2_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17
+#define DAGB2_RD_CNTL__FIX_JUMP__SHIFT 0x1a
+#define DAGB2_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL
+#define DAGB2_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L
+#define DAGB2_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L
+#define DAGB2_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L
+#define DAGB2_RD_CNTL__IO_LEVEL_MASK 0x000E0000L
+#define DAGB2_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L
+#define DAGB2_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L
+#define DAGB2_RD_CNTL__FIX_JUMP_MASK 0x04000000L
+//DAGB2_RD_GMI_CNTL
+#define DAGB2_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0
+#define DAGB2_RD_GMI_CNTL__LEVEL__SHIFT 0x6
+#define DAGB2_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9
+#define DAGB2_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd
+#define DAGB2_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL
+#define DAGB2_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L
+#define DAGB2_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L
+#define DAGB2_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L
+//DAGB2_RD_ADDR_DAGB
+#define DAGB2_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0
+#define DAGB2_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
+#define DAGB2_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
+#define DAGB2_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7
+#define DAGB2_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd
+#define DAGB2_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L
+#define DAGB2_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
+#define DAGB2_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
+#define DAGB2_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L
+#define DAGB2_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L
+//DAGB2_RD_OUTPUT_DAGB_MAX_BURST
+#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0
+#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4
+#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8
+#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc
+#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
+#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14
+#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18
+#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c
+#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL
+#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L
+#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L
+#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L
+#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L
+#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L
+#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L
+#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L
+//DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER
+#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0
+#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4
+#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8
+#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc
+#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
+#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14
+#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18
+#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c
+#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL
+#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L
+#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L
+#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L
+#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L
+#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L
+#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L
+#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L
+//DAGB2_RD_CGTT_CLK_CTRL
+#define DAGB2_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB2_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB2_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB2_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB2_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB2_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB2_L1TLB_RD_CGTT_CLK_CTRL
+#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB2_ATCVM_RD_CGTT_CLK_CTRL
+#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB2_RD_ADDR_DAGB_MAX_BURST0
+#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
+#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
+#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
+#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
+#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
+#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
+#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
+#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
+#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
+#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
+#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
+#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
+#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
+#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
+#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
+#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
+//DAGB2_RD_ADDR_DAGB_LAZY_TIMER0
+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
+//DAGB2_RD_ADDR_DAGB_MAX_BURST1
+#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
+#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
+#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
+#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
+#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
+#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
+#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
+#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
+#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
+#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
+#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
+#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
+#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
+#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
+#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
+#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
+//DAGB2_RD_ADDR_DAGB_LAZY_TIMER1
+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
+//DAGB2_RD_VC0_CNTL
+#define DAGB2_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB2_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB2_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB2_RD_VC0_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB2_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB2_RD_VC0_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB2_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB2_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB2_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB2_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB2_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB2_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB2_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB2_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB2_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB2_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB2_RD_VC1_CNTL
+#define DAGB2_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB2_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB2_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB2_RD_VC1_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB2_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB2_RD_VC1_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB2_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB2_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB2_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB2_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB2_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB2_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB2_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB2_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB2_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB2_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB2_RD_VC2_CNTL
+#define DAGB2_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB2_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB2_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB2_RD_VC2_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB2_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB2_RD_VC2_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB2_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB2_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB2_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB2_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB2_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB2_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB2_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB2_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB2_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB2_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB2_RD_VC3_CNTL
+#define DAGB2_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB2_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB2_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB2_RD_VC3_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB2_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB2_RD_VC3_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB2_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB2_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB2_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB2_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB2_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB2_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB2_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB2_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB2_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB2_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB2_RD_VC4_CNTL
+#define DAGB2_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB2_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB2_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB2_RD_VC4_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB2_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB2_RD_VC4_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB2_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB2_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB2_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB2_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB2_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB2_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB2_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB2_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB2_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB2_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB2_RD_VC5_CNTL
+#define DAGB2_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB2_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB2_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB2_RD_VC5_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB2_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB2_RD_VC5_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB2_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB2_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB2_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB2_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB2_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB2_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB2_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB2_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB2_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB2_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB2_RD_VC6_CNTL
+#define DAGB2_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB2_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB2_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB2_RD_VC6_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB2_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB2_RD_VC6_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB2_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB2_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB2_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB2_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB2_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB2_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB2_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB2_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB2_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB2_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB2_RD_VC7_CNTL
+#define DAGB2_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB2_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB2_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB2_RD_VC7_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB2_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB2_RD_VC7_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB2_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB2_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB2_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB2_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB2_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB2_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB2_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB2_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB2_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB2_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB2_RD_CNTL_MISC
+#define DAGB2_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0
+#define DAGB2_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6
+#define DAGB2_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd
+#define DAGB2_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13
+#define DAGB2_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14
+#define DAGB2_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15
+#define DAGB2_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a
+#define DAGB2_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL
+#define DAGB2_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L
+#define DAGB2_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L
+#define DAGB2_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L
+#define DAGB2_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L
+#define DAGB2_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L
+#define DAGB2_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L
+//DAGB2_RD_TLB_CREDIT
+#define DAGB2_RD_TLB_CREDIT__TLB0__SHIFT 0x0
+#define DAGB2_RD_TLB_CREDIT__TLB1__SHIFT 0x5
+#define DAGB2_RD_TLB_CREDIT__TLB2__SHIFT 0xa
+#define DAGB2_RD_TLB_CREDIT__TLB3__SHIFT 0xf
+#define DAGB2_RD_TLB_CREDIT__TLB4__SHIFT 0x14
+#define DAGB2_RD_TLB_CREDIT__TLB5__SHIFT 0x19
+#define DAGB2_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL
+#define DAGB2_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L
+#define DAGB2_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L
+#define DAGB2_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L
+#define DAGB2_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L
+#define DAGB2_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L
+//DAGB2_RD_RDRET_CREDIT_CNTL
+#define DAGB2_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT 0x0
+#define DAGB2_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT 0x6
+#define DAGB2_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT 0xc
+#define DAGB2_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT 0x12
+#define DAGB2_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT 0x18
+#define DAGB2_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT 0x1e
+#define DAGB2_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT 0x1f
+#define DAGB2_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK 0x0000003FL
+#define DAGB2_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK 0x00000FC0L
+#define DAGB2_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK 0x0003F000L
+#define DAGB2_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK 0x00FC0000L
+#define DAGB2_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK 0x3F000000L
+#define DAGB2_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK 0x40000000L
+#define DAGB2_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK 0x80000000L
+//DAGB2_RD_RDRET_CREDIT_CNTL2
+#define DAGB2_RD_RDRET_CREDIT_CNTL2__IO_CREDIT__SHIFT 0x0
+#define DAGB2_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT__SHIFT 0x6
+#define DAGB2_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT 0xc
+#define DAGB2_RD_RDRET_CREDIT_CNTL2__IO_CREDIT_MASK 0x0000003FL
+#define DAGB2_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT_MASK 0x00000FC0L
+#define DAGB2_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK 0x0007F000L
+//DAGB2_RDCLI_ASK_PENDING
+#define DAGB2_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0
+#define DAGB2_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB2_RDCLI_GO_PENDING
+#define DAGB2_RDCLI_GO_PENDING__BUSY__SHIFT 0x0
+#define DAGB2_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB2_RDCLI_GBLSEND_PENDING
+#define DAGB2_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0
+#define DAGB2_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB2_RDCLI_TLB_PENDING
+#define DAGB2_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0
+#define DAGB2_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB2_RDCLI_OARB_PENDING
+#define DAGB2_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0
+#define DAGB2_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB2_RDCLI_OSD_PENDING
+#define DAGB2_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0
+#define DAGB2_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB2_WRCLI0
+#define DAGB2_WRCLI0__VIRT_CHAN__SHIFT 0x0
+#define DAGB2_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB2_WRCLI0__URG_HIGH__SHIFT 0x4
+#define DAGB2_WRCLI0__URG_LOW__SHIFT 0x8
+#define DAGB2_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB2_WRCLI0__MAX_BW__SHIFT 0xd
+#define DAGB2_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB2_WRCLI0__MIN_BW__SHIFT 0x16
+#define DAGB2_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB2_WRCLI0__MAX_OSD__SHIFT 0x1a
+#define DAGB2_WRCLI0__VIRT_CHAN_MASK 0x00000007L
+#define DAGB2_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB2_WRCLI0__URG_HIGH_MASK 0x000000F0L
+#define DAGB2_WRCLI0__URG_LOW_MASK 0x00000F00L
+#define DAGB2_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB2_WRCLI0__MAX_BW_MASK 0x001FE000L
+#define DAGB2_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB2_WRCLI0__MIN_BW_MASK 0x01C00000L
+#define DAGB2_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB2_WRCLI0__MAX_OSD_MASK 0xFC000000L
+//DAGB2_WRCLI1
+#define DAGB2_WRCLI1__VIRT_CHAN__SHIFT 0x0
+#define DAGB2_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB2_WRCLI1__URG_HIGH__SHIFT 0x4
+#define DAGB2_WRCLI1__URG_LOW__SHIFT 0x8
+#define DAGB2_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB2_WRCLI1__MAX_BW__SHIFT 0xd
+#define DAGB2_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB2_WRCLI1__MIN_BW__SHIFT 0x16
+#define DAGB2_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB2_WRCLI1__MAX_OSD__SHIFT 0x1a
+#define DAGB2_WRCLI1__VIRT_CHAN_MASK 0x00000007L
+#define DAGB2_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB2_WRCLI1__URG_HIGH_MASK 0x000000F0L
+#define DAGB2_WRCLI1__URG_LOW_MASK 0x00000F00L
+#define DAGB2_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB2_WRCLI1__MAX_BW_MASK 0x001FE000L
+#define DAGB2_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB2_WRCLI1__MIN_BW_MASK 0x01C00000L
+#define DAGB2_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB2_WRCLI1__MAX_OSD_MASK 0xFC000000L
+//DAGB2_WRCLI2
+#define DAGB2_WRCLI2__VIRT_CHAN__SHIFT 0x0
+#define DAGB2_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB2_WRCLI2__URG_HIGH__SHIFT 0x4
+#define DAGB2_WRCLI2__URG_LOW__SHIFT 0x8
+#define DAGB2_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB2_WRCLI2__MAX_BW__SHIFT 0xd
+#define DAGB2_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB2_WRCLI2__MIN_BW__SHIFT 0x16
+#define DAGB2_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB2_WRCLI2__MAX_OSD__SHIFT 0x1a
+#define DAGB2_WRCLI2__VIRT_CHAN_MASK 0x00000007L
+#define DAGB2_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB2_WRCLI2__URG_HIGH_MASK 0x000000F0L
+#define DAGB2_WRCLI2__URG_LOW_MASK 0x00000F00L
+#define DAGB2_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB2_WRCLI2__MAX_BW_MASK 0x001FE000L
+#define DAGB2_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB2_WRCLI2__MIN_BW_MASK 0x01C00000L
+#define DAGB2_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB2_WRCLI2__MAX_OSD_MASK 0xFC000000L
+//DAGB2_WRCLI3
+#define DAGB2_WRCLI3__VIRT_CHAN__SHIFT 0x0
+#define DAGB2_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB2_WRCLI3__URG_HIGH__SHIFT 0x4
+#define DAGB2_WRCLI3__URG_LOW__SHIFT 0x8
+#define DAGB2_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB2_WRCLI3__MAX_BW__SHIFT 0xd
+#define DAGB2_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB2_WRCLI3__MIN_BW__SHIFT 0x16
+#define DAGB2_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB2_WRCLI3__MAX_OSD__SHIFT 0x1a
+#define DAGB2_WRCLI3__VIRT_CHAN_MASK 0x00000007L
+#define DAGB2_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB2_WRCLI3__URG_HIGH_MASK 0x000000F0L
+#define DAGB2_WRCLI3__URG_LOW_MASK 0x00000F00L
+#define DAGB2_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB2_WRCLI3__MAX_BW_MASK 0x001FE000L
+#define DAGB2_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB2_WRCLI3__MIN_BW_MASK 0x01C00000L
+#define DAGB2_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB2_WRCLI3__MAX_OSD_MASK 0xFC000000L
+//DAGB2_WRCLI4
+#define DAGB2_WRCLI4__VIRT_CHAN__SHIFT 0x0
+#define DAGB2_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB2_WRCLI4__URG_HIGH__SHIFT 0x4
+#define DAGB2_WRCLI4__URG_LOW__SHIFT 0x8
+#define DAGB2_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB2_WRCLI4__MAX_BW__SHIFT 0xd
+#define DAGB2_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB2_WRCLI4__MIN_BW__SHIFT 0x16
+#define DAGB2_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB2_WRCLI4__MAX_OSD__SHIFT 0x1a
+#define DAGB2_WRCLI4__VIRT_CHAN_MASK 0x00000007L
+#define DAGB2_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB2_WRCLI4__URG_HIGH_MASK 0x000000F0L
+#define DAGB2_WRCLI4__URG_LOW_MASK 0x00000F00L
+#define DAGB2_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB2_WRCLI4__MAX_BW_MASK 0x001FE000L
+#define DAGB2_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB2_WRCLI4__MIN_BW_MASK 0x01C00000L
+#define DAGB2_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB2_WRCLI4__MAX_OSD_MASK 0xFC000000L
+//DAGB2_WRCLI5
+#define DAGB2_WRCLI5__VIRT_CHAN__SHIFT 0x0
+#define DAGB2_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB2_WRCLI5__URG_HIGH__SHIFT 0x4
+#define DAGB2_WRCLI5__URG_LOW__SHIFT 0x8
+#define DAGB2_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB2_WRCLI5__MAX_BW__SHIFT 0xd
+#define DAGB2_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB2_WRCLI5__MIN_BW__SHIFT 0x16
+#define DAGB2_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB2_WRCLI5__MAX_OSD__SHIFT 0x1a
+#define DAGB2_WRCLI5__VIRT_CHAN_MASK 0x00000007L
+#define DAGB2_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB2_WRCLI5__URG_HIGH_MASK 0x000000F0L
+#define DAGB2_WRCLI5__URG_LOW_MASK 0x00000F00L
+#define DAGB2_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB2_WRCLI5__MAX_BW_MASK 0x001FE000L
+#define DAGB2_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB2_WRCLI5__MIN_BW_MASK 0x01C00000L
+#define DAGB2_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB2_WRCLI5__MAX_OSD_MASK 0xFC000000L
+//DAGB2_WRCLI6
+#define DAGB2_WRCLI6__VIRT_CHAN__SHIFT 0x0
+#define DAGB2_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB2_WRCLI6__URG_HIGH__SHIFT 0x4
+#define DAGB2_WRCLI6__URG_LOW__SHIFT 0x8
+#define DAGB2_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB2_WRCLI6__MAX_BW__SHIFT 0xd
+#define DAGB2_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB2_WRCLI6__MIN_BW__SHIFT 0x16
+#define DAGB2_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB2_WRCLI6__MAX_OSD__SHIFT 0x1a
+#define DAGB2_WRCLI6__VIRT_CHAN_MASK 0x00000007L
+#define DAGB2_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB2_WRCLI6__URG_HIGH_MASK 0x000000F0L
+#define DAGB2_WRCLI6__URG_LOW_MASK 0x00000F00L
+#define DAGB2_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB2_WRCLI6__MAX_BW_MASK 0x001FE000L
+#define DAGB2_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB2_WRCLI6__MIN_BW_MASK 0x01C00000L
+#define DAGB2_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB2_WRCLI6__MAX_OSD_MASK 0xFC000000L
+//DAGB2_WRCLI7
+#define DAGB2_WRCLI7__VIRT_CHAN__SHIFT 0x0
+#define DAGB2_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB2_WRCLI7__URG_HIGH__SHIFT 0x4
+#define DAGB2_WRCLI7__URG_LOW__SHIFT 0x8
+#define DAGB2_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB2_WRCLI7__MAX_BW__SHIFT 0xd
+#define DAGB2_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB2_WRCLI7__MIN_BW__SHIFT 0x16
+#define DAGB2_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB2_WRCLI7__MAX_OSD__SHIFT 0x1a
+#define DAGB2_WRCLI7__VIRT_CHAN_MASK 0x00000007L
+#define DAGB2_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB2_WRCLI7__URG_HIGH_MASK 0x000000F0L
+#define DAGB2_WRCLI7__URG_LOW_MASK 0x00000F00L
+#define DAGB2_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB2_WRCLI7__MAX_BW_MASK 0x001FE000L
+#define DAGB2_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB2_WRCLI7__MIN_BW_MASK 0x01C00000L
+#define DAGB2_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB2_WRCLI7__MAX_OSD_MASK 0xFC000000L
+//DAGB2_WRCLI8
+#define DAGB2_WRCLI8__VIRT_CHAN__SHIFT 0x0
+#define DAGB2_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB2_WRCLI8__URG_HIGH__SHIFT 0x4
+#define DAGB2_WRCLI8__URG_LOW__SHIFT 0x8
+#define DAGB2_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB2_WRCLI8__MAX_BW__SHIFT 0xd
+#define DAGB2_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB2_WRCLI8__MIN_BW__SHIFT 0x16
+#define DAGB2_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB2_WRCLI8__MAX_OSD__SHIFT 0x1a
+#define DAGB2_WRCLI8__VIRT_CHAN_MASK 0x00000007L
+#define DAGB2_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB2_WRCLI8__URG_HIGH_MASK 0x000000F0L
+#define DAGB2_WRCLI8__URG_LOW_MASK 0x00000F00L
+#define DAGB2_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB2_WRCLI8__MAX_BW_MASK 0x001FE000L
+#define DAGB2_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB2_WRCLI8__MIN_BW_MASK 0x01C00000L
+#define DAGB2_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB2_WRCLI8__MAX_OSD_MASK 0xFC000000L
+//DAGB2_WRCLI9
+#define DAGB2_WRCLI9__VIRT_CHAN__SHIFT 0x0
+#define DAGB2_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB2_WRCLI9__URG_HIGH__SHIFT 0x4
+#define DAGB2_WRCLI9__URG_LOW__SHIFT 0x8
+#define DAGB2_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB2_WRCLI9__MAX_BW__SHIFT 0xd
+#define DAGB2_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB2_WRCLI9__MIN_BW__SHIFT 0x16
+#define DAGB2_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB2_WRCLI9__MAX_OSD__SHIFT 0x1a
+#define DAGB2_WRCLI9__VIRT_CHAN_MASK 0x00000007L
+#define DAGB2_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB2_WRCLI9__URG_HIGH_MASK 0x000000F0L
+#define DAGB2_WRCLI9__URG_LOW_MASK 0x00000F00L
+#define DAGB2_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB2_WRCLI9__MAX_BW_MASK 0x001FE000L
+#define DAGB2_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB2_WRCLI9__MIN_BW_MASK 0x01C00000L
+#define DAGB2_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB2_WRCLI9__MAX_OSD_MASK 0xFC000000L
+//DAGB2_WRCLI10
+#define DAGB2_WRCLI10__VIRT_CHAN__SHIFT 0x0
+#define DAGB2_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB2_WRCLI10__URG_HIGH__SHIFT 0x4
+#define DAGB2_WRCLI10__URG_LOW__SHIFT 0x8
+#define DAGB2_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB2_WRCLI10__MAX_BW__SHIFT 0xd
+#define DAGB2_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB2_WRCLI10__MIN_BW__SHIFT 0x16
+#define DAGB2_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB2_WRCLI10__MAX_OSD__SHIFT 0x1a
+#define DAGB2_WRCLI10__VIRT_CHAN_MASK 0x00000007L
+#define DAGB2_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB2_WRCLI10__URG_HIGH_MASK 0x000000F0L
+#define DAGB2_WRCLI10__URG_LOW_MASK 0x00000F00L
+#define DAGB2_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB2_WRCLI10__MAX_BW_MASK 0x001FE000L
+#define DAGB2_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB2_WRCLI10__MIN_BW_MASK 0x01C00000L
+#define DAGB2_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB2_WRCLI10__MAX_OSD_MASK 0xFC000000L
+//DAGB2_WRCLI11
+#define DAGB2_WRCLI11__VIRT_CHAN__SHIFT 0x0
+#define DAGB2_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB2_WRCLI11__URG_HIGH__SHIFT 0x4
+#define DAGB2_WRCLI11__URG_LOW__SHIFT 0x8
+#define DAGB2_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB2_WRCLI11__MAX_BW__SHIFT 0xd
+#define DAGB2_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB2_WRCLI11__MIN_BW__SHIFT 0x16
+#define DAGB2_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB2_WRCLI11__MAX_OSD__SHIFT 0x1a
+#define DAGB2_WRCLI11__VIRT_CHAN_MASK 0x00000007L
+#define DAGB2_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB2_WRCLI11__URG_HIGH_MASK 0x000000F0L
+#define DAGB2_WRCLI11__URG_LOW_MASK 0x00000F00L
+#define DAGB2_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB2_WRCLI11__MAX_BW_MASK 0x001FE000L
+#define DAGB2_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB2_WRCLI11__MIN_BW_MASK 0x01C00000L
+#define DAGB2_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB2_WRCLI11__MAX_OSD_MASK 0xFC000000L
+//DAGB2_WRCLI12
+#define DAGB2_WRCLI12__VIRT_CHAN__SHIFT 0x0
+#define DAGB2_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB2_WRCLI12__URG_HIGH__SHIFT 0x4
+#define DAGB2_WRCLI12__URG_LOW__SHIFT 0x8
+#define DAGB2_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB2_WRCLI12__MAX_BW__SHIFT 0xd
+#define DAGB2_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB2_WRCLI12__MIN_BW__SHIFT 0x16
+#define DAGB2_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB2_WRCLI12__MAX_OSD__SHIFT 0x1a
+#define DAGB2_WRCLI12__VIRT_CHAN_MASK 0x00000007L
+#define DAGB2_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB2_WRCLI12__URG_HIGH_MASK 0x000000F0L
+#define DAGB2_WRCLI12__URG_LOW_MASK 0x00000F00L
+#define DAGB2_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB2_WRCLI12__MAX_BW_MASK 0x001FE000L
+#define DAGB2_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB2_WRCLI12__MIN_BW_MASK 0x01C00000L
+#define DAGB2_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB2_WRCLI12__MAX_OSD_MASK 0xFC000000L
+//DAGB2_WRCLI13
+#define DAGB2_WRCLI13__VIRT_CHAN__SHIFT 0x0
+#define DAGB2_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB2_WRCLI13__URG_HIGH__SHIFT 0x4
+#define DAGB2_WRCLI13__URG_LOW__SHIFT 0x8
+#define DAGB2_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB2_WRCLI13__MAX_BW__SHIFT 0xd
+#define DAGB2_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB2_WRCLI13__MIN_BW__SHIFT 0x16
+#define DAGB2_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB2_WRCLI13__MAX_OSD__SHIFT 0x1a
+#define DAGB2_WRCLI13__VIRT_CHAN_MASK 0x00000007L
+#define DAGB2_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB2_WRCLI13__URG_HIGH_MASK 0x000000F0L
+#define DAGB2_WRCLI13__URG_LOW_MASK 0x00000F00L
+#define DAGB2_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB2_WRCLI13__MAX_BW_MASK 0x001FE000L
+#define DAGB2_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB2_WRCLI13__MIN_BW_MASK 0x01C00000L
+#define DAGB2_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB2_WRCLI13__MAX_OSD_MASK 0xFC000000L
+//DAGB2_WRCLI14
+#define DAGB2_WRCLI14__VIRT_CHAN__SHIFT 0x0
+#define DAGB2_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB2_WRCLI14__URG_HIGH__SHIFT 0x4
+#define DAGB2_WRCLI14__URG_LOW__SHIFT 0x8
+#define DAGB2_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB2_WRCLI14__MAX_BW__SHIFT 0xd
+#define DAGB2_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB2_WRCLI14__MIN_BW__SHIFT 0x16
+#define DAGB2_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB2_WRCLI14__MAX_OSD__SHIFT 0x1a
+#define DAGB2_WRCLI14__VIRT_CHAN_MASK 0x00000007L
+#define DAGB2_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB2_WRCLI14__URG_HIGH_MASK 0x000000F0L
+#define DAGB2_WRCLI14__URG_LOW_MASK 0x00000F00L
+#define DAGB2_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB2_WRCLI14__MAX_BW_MASK 0x001FE000L
+#define DAGB2_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB2_WRCLI14__MIN_BW_MASK 0x01C00000L
+#define DAGB2_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB2_WRCLI14__MAX_OSD_MASK 0xFC000000L
+//DAGB2_WRCLI15
+#define DAGB2_WRCLI15__VIRT_CHAN__SHIFT 0x0
+#define DAGB2_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB2_WRCLI15__URG_HIGH__SHIFT 0x4
+#define DAGB2_WRCLI15__URG_LOW__SHIFT 0x8
+#define DAGB2_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB2_WRCLI15__MAX_BW__SHIFT 0xd
+#define DAGB2_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB2_WRCLI15__MIN_BW__SHIFT 0x16
+#define DAGB2_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB2_WRCLI15__MAX_OSD__SHIFT 0x1a
+#define DAGB2_WRCLI15__VIRT_CHAN_MASK 0x00000007L
+#define DAGB2_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB2_WRCLI15__URG_HIGH_MASK 0x000000F0L
+#define DAGB2_WRCLI15__URG_LOW_MASK 0x00000F00L
+#define DAGB2_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB2_WRCLI15__MAX_BW_MASK 0x001FE000L
+#define DAGB2_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB2_WRCLI15__MIN_BW_MASK 0x01C00000L
+#define DAGB2_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB2_WRCLI15__MAX_OSD_MASK 0xFC000000L
+//DAGB2_WR_CNTL
+#define DAGB2_WR_CNTL__SCLK_FREQ__SHIFT 0x0
+#define DAGB2_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4
+#define DAGB2_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
+#define DAGB2_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
+#define DAGB2_WR_CNTL__IO_LEVEL__SHIFT 0x11
+#define DAGB2_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14
+#define DAGB2_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17
+#define DAGB2_WR_CNTL__FIX_JUMP__SHIFT 0x1a
+#define DAGB2_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL
+#define DAGB2_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L
+#define DAGB2_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L
+#define DAGB2_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L
+#define DAGB2_WR_CNTL__IO_LEVEL_MASK 0x000E0000L
+#define DAGB2_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L
+#define DAGB2_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L
+#define DAGB2_WR_CNTL__FIX_JUMP_MASK 0x04000000L
+//DAGB2_WR_GMI_CNTL
+#define DAGB2_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0
+#define DAGB2_WR_GMI_CNTL__LEVEL__SHIFT 0x6
+#define DAGB2_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9
+#define DAGB2_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd
+#define DAGB2_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL
+#define DAGB2_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L
+#define DAGB2_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L
+#define DAGB2_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L
+//DAGB2_WR_ADDR_DAGB
+#define DAGB2_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0
+#define DAGB2_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
+#define DAGB2_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
+#define DAGB2_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7
+#define DAGB2_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xd
+#define DAGB2_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L
+#define DAGB2_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
+#define DAGB2_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
+#define DAGB2_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L
+#define DAGB2_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L
+//DAGB2_WR_OUTPUT_DAGB_MAX_BURST
+#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0
+#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4
+#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8
+#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc
+#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
+#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14
+#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18
+#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c
+#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL
+#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L
+#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L
+#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L
+#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L
+#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L
+#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L
+#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L
+//DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER
+#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0
+#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4
+#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8
+#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc
+#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
+#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14
+#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18
+#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c
+#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL
+#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L
+#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L
+#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L
+#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L
+#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L
+#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L
+#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L
+//DAGB2_WR_CGTT_CLK_CTRL
+#define DAGB2_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB2_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB2_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB2_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB2_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB2_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB2_L1TLB_WR_CGTT_CLK_CTRL
+#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB2_ATCVM_WR_CGTT_CLK_CTRL
+#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB2_WR_ADDR_DAGB_MAX_BURST0
+#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
+#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
+#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
+#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
+#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
+#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
+#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
+#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
+#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
+#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
+#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
+#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
+#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
+#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
+#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
+#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
+//DAGB2_WR_ADDR_DAGB_LAZY_TIMER0
+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
+//DAGB2_WR_ADDR_DAGB_MAX_BURST1
+#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
+#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
+#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
+#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
+#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
+#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
+#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
+#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
+#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
+#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
+#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
+#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
+#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
+#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
+#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
+#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
+//DAGB2_WR_ADDR_DAGB_LAZY_TIMER1
+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
+//DAGB2_WR_DATA_DAGB
+#define DAGB2_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0
+#define DAGB2_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
+#define DAGB2_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
+#define DAGB2_WR_DATA_DAGB__WHOAMI__SHIFT 0x7
+#define DAGB2_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L
+#define DAGB2_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
+#define DAGB2_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
+#define DAGB2_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L
+//DAGB2_WR_DATA_DAGB_MAX_BURST0
+#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
+#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
+#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
+#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
+#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
+#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
+#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
+#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
+#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
+#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
+#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
+#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
+#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
+#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
+#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
+#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
+//DAGB2_WR_DATA_DAGB_LAZY_TIMER0
+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
+//DAGB2_WR_DATA_DAGB_MAX_BURST1
+#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
+#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
+#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
+#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
+#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
+#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
+#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
+#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
+#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
+#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
+#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
+#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
+#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
+#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
+#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
+#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
+//DAGB2_WR_DATA_DAGB_LAZY_TIMER1
+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
+//DAGB2_WR_VC0_CNTL
+#define DAGB2_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB2_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB2_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB2_WR_VC0_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB2_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB2_WR_VC0_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB2_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB2_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB2_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB2_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB2_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB2_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB2_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB2_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB2_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB2_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB2_WR_VC1_CNTL
+#define DAGB2_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB2_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB2_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB2_WR_VC1_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB2_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB2_WR_VC1_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB2_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB2_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB2_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB2_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB2_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB2_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB2_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB2_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB2_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB2_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB2_WR_VC2_CNTL
+#define DAGB2_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB2_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB2_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB2_WR_VC2_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB2_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB2_WR_VC2_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB2_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB2_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB2_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB2_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB2_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB2_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB2_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB2_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB2_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB2_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB2_WR_VC3_CNTL
+#define DAGB2_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB2_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB2_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB2_WR_VC3_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB2_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB2_WR_VC3_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB2_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB2_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB2_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB2_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB2_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB2_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB2_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB2_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB2_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB2_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB2_WR_VC4_CNTL
+#define DAGB2_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB2_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB2_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB2_WR_VC4_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB2_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB2_WR_VC4_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB2_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB2_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB2_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB2_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB2_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB2_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB2_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB2_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB2_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB2_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB2_WR_VC5_CNTL
+#define DAGB2_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB2_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB2_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB2_WR_VC5_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB2_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB2_WR_VC5_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB2_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB2_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB2_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB2_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB2_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB2_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB2_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB2_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB2_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB2_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB2_WR_VC6_CNTL
+#define DAGB2_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB2_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB2_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB2_WR_VC6_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB2_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB2_WR_VC6_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB2_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB2_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB2_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB2_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB2_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB2_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB2_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB2_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB2_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB2_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB2_WR_VC7_CNTL
+#define DAGB2_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB2_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB2_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB2_WR_VC7_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB2_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB2_WR_VC7_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB2_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB2_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB2_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB2_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB2_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB2_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB2_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB2_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB2_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB2_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB2_WR_CNTL_MISC
+#define DAGB2_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0
+#define DAGB2_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6
+#define DAGB2_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd
+#define DAGB2_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13
+#define DAGB2_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14
+#define DAGB2_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15
+#define DAGB2_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a
+#define DAGB2_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL
+#define DAGB2_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L
+#define DAGB2_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L
+#define DAGB2_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L
+#define DAGB2_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L
+#define DAGB2_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L
+#define DAGB2_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L
+//DAGB2_WR_TLB_CREDIT
+#define DAGB2_WR_TLB_CREDIT__TLB0__SHIFT 0x0
+#define DAGB2_WR_TLB_CREDIT__TLB1__SHIFT 0x5
+#define DAGB2_WR_TLB_CREDIT__TLB2__SHIFT 0xa
+#define DAGB2_WR_TLB_CREDIT__TLB3__SHIFT 0xf
+#define DAGB2_WR_TLB_CREDIT__TLB4__SHIFT 0x14
+#define DAGB2_WR_TLB_CREDIT__TLB5__SHIFT 0x19
+#define DAGB2_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL
+#define DAGB2_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L
+#define DAGB2_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L
+#define DAGB2_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L
+#define DAGB2_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L
+#define DAGB2_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L
+//DAGB2_WR_DATA_CREDIT
+#define DAGB2_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0
+#define DAGB2_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8
+#define DAGB2_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10
+#define DAGB2_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18
+#define DAGB2_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL
+#define DAGB2_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L
+#define DAGB2_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L
+#define DAGB2_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L
+//DAGB2_WR_MISC_CREDIT
+#define DAGB2_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0
+#define DAGB2_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6
+#define DAGB2_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9
+#define DAGB2_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10
+#define DAGB2_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL
+#define DAGB2_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L
+#define DAGB2_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L
+#define DAGB2_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L
+//DAGB2_WR_OSD_CREDIT_CNTL1
+#define DAGB2_WR_OSD_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0
+#define DAGB2_WR_OSD_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x4
+#define DAGB2_WR_OSD_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0x8
+#define DAGB2_WR_OSD_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xc
+#define DAGB2_WR_OSD_CREDIT_CNTL1__IO_CREDIT__SHIFT 0x10
+#define DAGB2_WR_OSD_CREDIT_CNTL1__GMI_CREDIT__SHIFT 0x14
+#define DAGB2_WR_OSD_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x18
+#define DAGB2_WR_OSD_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000000FL
+#define DAGB2_WR_OSD_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000000F0L
+#define DAGB2_WR_OSD_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00000F00L
+#define DAGB2_WR_OSD_CREDIT_CNTL1__VC3_CREDIT_MASK 0x0000F000L
+#define DAGB2_WR_OSD_CREDIT_CNTL1__IO_CREDIT_MASK 0x000F0000L
+#define DAGB2_WR_OSD_CREDIT_CNTL1__GMI_CREDIT_MASK 0x00F00000L
+#define DAGB2_WR_OSD_CREDIT_CNTL1__POOL_CREDIT_MASK 0x3F000000L
+//DAGB2_WR_OSD_CREDIT_CNTL2
+#define DAGB2_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN__SHIFT 0x0
+#define DAGB2_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY__SHIFT 0x4
+#define DAGB2_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN_MASK 0x0000000FL
+#define DAGB2_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY_MASK 0x00000010L
+//DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1
+#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0
+#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5
+#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa
+#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf
+#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14
+#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x19
+#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1a
+#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1b
+#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1__SHIFT 0x1c
+#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2__SHIFT 0x1d
+#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL
+#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L
+#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L
+#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L
+#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x01F00000L
+#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x02000000L
+#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x04000000L
+#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK 0x08000000L
+#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1_MASK 0x10000000L
+#define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2_MASK 0x20000000L
+//DAGB2_WRCLI_GPU_SNOOP_OVERRIDE
+#define DAGB2_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0
+#define DAGB2_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL
+//DAGB2_WRCLI_GPU_SNOOP_OVERRIDE_VALUE
+#define DAGB2_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0
+#define DAGB2_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0xFFFFFFFFL
+//DAGB2_WRCLI_ASK_PENDING
+#define DAGB2_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0
+#define DAGB2_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB2_WRCLI_GO_PENDING
+#define DAGB2_WRCLI_GO_PENDING__BUSY__SHIFT 0x0
+#define DAGB2_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB2_WRCLI_GBLSEND_PENDING
+#define DAGB2_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0
+#define DAGB2_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB2_WRCLI_TLB_PENDING
+#define DAGB2_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0
+#define DAGB2_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB2_WRCLI_OARB_PENDING
+#define DAGB2_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0
+#define DAGB2_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB2_WRCLI_OSD_PENDING
+#define DAGB2_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0
+#define DAGB2_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB2_WRCLI_DBUS_ASK_PENDING
+#define DAGB2_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0
+#define DAGB2_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB2_WRCLI_DBUS_GO_PENDING
+#define DAGB2_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0
+#define DAGB2_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB2_DAGB_DLY
+#define DAGB2_DAGB_DLY__DLY__SHIFT 0x0
+#define DAGB2_DAGB_DLY__CLI__SHIFT 0x8
+#define DAGB2_DAGB_DLY__POS__SHIFT 0x10
+#define DAGB2_DAGB_DLY__DLY_MASK 0x000000FFL
+#define DAGB2_DAGB_DLY__CLI_MASK 0x0000FF00L
+#define DAGB2_DAGB_DLY__POS_MASK 0x000F0000L
+//DAGB2_CNTL_MISC
+#define DAGB2_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0
+#define DAGB2_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3
+#define DAGB2_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6
+#define DAGB2_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9
+#define DAGB2_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc
+#define DAGB2_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf
+#define DAGB2_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12
+#define DAGB2_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15
+#define DAGB2_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18
+#define DAGB2_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e
+#define DAGB2_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L
+#define DAGB2_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L
+#define DAGB2_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L
+#define DAGB2_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L
+#define DAGB2_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L
+#define DAGB2_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L
+#define DAGB2_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L
+#define DAGB2_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L
+#define DAGB2_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L
+#define DAGB2_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L
+//DAGB2_CNTL_MISC2
+#define DAGB2_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0
+#define DAGB2_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1
+#define DAGB2_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2
+#define DAGB2_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3
+#define DAGB2_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4
+#define DAGB2_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5
+#define DAGB2_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6
+#define DAGB2_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7
+#define DAGB2_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8
+#define DAGB2_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9
+#define DAGB2_CNTL_MISC2__SWAP_CTL__SHIFT 0xa
+#define DAGB2_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb
+#define DAGB2_CNTL_MISC2__HDP_CID__SHIFT 0xc
+#define DAGB2_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x11
+#define DAGB2_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L
+#define DAGB2_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L
+#define DAGB2_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L
+#define DAGB2_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L
+#define DAGB2_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L
+#define DAGB2_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L
+#define DAGB2_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L
+#define DAGB2_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L
+#define DAGB2_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L
+#define DAGB2_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L
+#define DAGB2_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L
+#define DAGB2_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L
+#define DAGB2_CNTL_MISC2__HDP_CID_MASK 0x0001F000L
+#define DAGB2_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x007E0000L
+//DAGB2_FATAL_ERROR_CNTL
+#define DAGB2_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT 0x0
+#define DAGB2_FATAL_ERROR_CNTL__FILTER_NUM_MASK 0x000003FFL
+//DAGB2_FATAL_ERROR_CLEAR
+#define DAGB2_FATAL_ERROR_CLEAR__CLEAR__SHIFT 0x0
+#define DAGB2_FATAL_ERROR_CLEAR__CLEAR_MASK 0x00000001L
+//DAGB2_FATAL_ERROR_STATUS0
+#define DAGB2_FATAL_ERROR_STATUS0__VALID__SHIFT 0x0
+#define DAGB2_FATAL_ERROR_STATUS0__CID__SHIFT 0x1
+#define DAGB2_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT 0x6
+#define DAGB2_FATAL_ERROR_STATUS0__VALID_MASK 0x00000001L
+#define DAGB2_FATAL_ERROR_STATUS0__CID_MASK 0x0000003EL
+#define DAGB2_FATAL_ERROR_STATUS0__ADDR_LO_MASK 0xFFFFFFC0L
+//DAGB2_FATAL_ERROR_STATUS1
+#define DAGB2_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT 0x0
+#define DAGB2_FATAL_ERROR_STATUS1__ADDR_HI_MASK 0x0001FFFFL
+//DAGB2_FATAL_ERROR_STATUS2
+#define DAGB2_FATAL_ERROR_STATUS2__TAG__SHIFT 0x0
+#define DAGB2_FATAL_ERROR_STATUS2__VFID__SHIFT 0x10
+#define DAGB2_FATAL_ERROR_STATUS2__VF__SHIFT 0x14
+#define DAGB2_FATAL_ERROR_STATUS2__SPACE__SHIFT 0x15
+#define DAGB2_FATAL_ERROR_STATUS2__IO__SHIFT 0x16
+#define DAGB2_FATAL_ERROR_STATUS2__SIZE__SHIFT 0x17
+#define DAGB2_FATAL_ERROR_STATUS2__FED__SHIFT 0x19
+#define DAGB2_FATAL_ERROR_STATUS2__TAG_MASK 0x0000FFFFL
+#define DAGB2_FATAL_ERROR_STATUS2__VFID_MASK 0x000F0000L
+#define DAGB2_FATAL_ERROR_STATUS2__VF_MASK 0x00100000L
+#define DAGB2_FATAL_ERROR_STATUS2__SPACE_MASK 0x00200000L
+#define DAGB2_FATAL_ERROR_STATUS2__IO_MASK 0x00400000L
+#define DAGB2_FATAL_ERROR_STATUS2__SIZE_MASK 0x00800000L
+#define DAGB2_FATAL_ERROR_STATUS2__FED_MASK 0x02000000L
+//DAGB2_FATAL_ERROR_STATUS3
+#define DAGB2_FATAL_ERROR_STATUS3__OP__SHIFT 0x6
+#define DAGB2_FATAL_ERROR_STATUS3__WRTMZ__SHIFT 0x10
+#define DAGB2_FATAL_ERROR_STATUS3__RDTMZ__SHIFT 0x11
+#define DAGB2_FATAL_ERROR_STATUS3__SNOOP__SHIFT 0x12
+#define DAGB2_FATAL_ERROR_STATUS3__INVAL__SHIFT 0x13
+#define DAGB2_FATAL_ERROR_STATUS3__NACK__SHIFT 0x14
+#define DAGB2_FATAL_ERROR_STATUS3__RO__SHIFT 0x16
+#define DAGB2_FATAL_ERROR_STATUS3__MEMLOG__SHIFT 0x17
+#define DAGB2_FATAL_ERROR_STATUS3__EOP__SHIFT 0x18
+#define DAGB2_FATAL_ERROR_STATUS3__OP_MASK 0x00001FC0L
+#define DAGB2_FATAL_ERROR_STATUS3__WRTMZ_MASK 0x00010000L
+#define DAGB2_FATAL_ERROR_STATUS3__RDTMZ_MASK 0x00020000L
+#define DAGB2_FATAL_ERROR_STATUS3__SNOOP_MASK 0x00040000L
+#define DAGB2_FATAL_ERROR_STATUS3__INVAL_MASK 0x00080000L
+#define DAGB2_FATAL_ERROR_STATUS3__NACK_MASK 0x00300000L
+#define DAGB2_FATAL_ERROR_STATUS3__RO_MASK 0x00400000L
+#define DAGB2_FATAL_ERROR_STATUS3__MEMLOG_MASK 0x00800000L
+#define DAGB2_FATAL_ERROR_STATUS3__EOP_MASK 0x01000000L
+//DAGB2_FIFO_EMPTY
+#define DAGB2_FIFO_EMPTY__EMPTY__SHIFT 0x0
+#define DAGB2_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL
+//DAGB2_FIFO_FULL
+#define DAGB2_FIFO_FULL__FULL__SHIFT 0x0
+#define DAGB2_FIFO_FULL__FULL_MASK 0x007FFFFFL
+//DAGB2_WR_CREDITS_FULL
+#define DAGB2_WR_CREDITS_FULL__FULL__SHIFT 0x0
+#define DAGB2_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL
+//DAGB2_RD_CREDITS_FULL
+#define DAGB2_RD_CREDITS_FULL__FULL__SHIFT 0x0
+#define DAGB2_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL
+//DAGB2_PERFCOUNTER_LO
+#define DAGB2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define DAGB2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//DAGB2_PERFCOUNTER_HI
+#define DAGB2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define DAGB2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define DAGB2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define DAGB2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//DAGB2_PERFCOUNTER0_CFG
+#define DAGB2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define DAGB2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define DAGB2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define DAGB2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define DAGB2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define DAGB2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define DAGB2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define DAGB2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define DAGB2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define DAGB2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//DAGB2_PERFCOUNTER1_CFG
+#define DAGB2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define DAGB2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define DAGB2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define DAGB2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define DAGB2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define DAGB2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define DAGB2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define DAGB2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define DAGB2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define DAGB2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//DAGB2_PERFCOUNTER2_CFG
+#define DAGB2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define DAGB2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define DAGB2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define DAGB2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define DAGB2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define DAGB2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
+#define DAGB2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define DAGB2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
+#define DAGB2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
+#define DAGB2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
+//DAGB2_PERFCOUNTER_RSLT_CNTL
+#define DAGB2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define DAGB2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define DAGB2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define DAGB2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define DAGB2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define DAGB2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define DAGB2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define DAGB2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+//DAGB2_L1TLB_REG_RW
+#define DAGB2_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0
+#define DAGB2_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1
+#define DAGB2_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL__SHIFT 0x2
+#define DAGB2_L1TLB_REG_RW__WDAT_PARITY_CHECK__SHIFT 0x4
+#define DAGB2_L1TLB_REG_RW__DISABLE_RDRET_CHECK__SHIFT 0x5
+#define DAGB2_L1TLB_REG_RW__RESERVE__SHIFT 0x6
+#define DAGB2_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L
+#define DAGB2_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L
+#define DAGB2_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL_MASK 0x00000004L
+#define DAGB2_L1TLB_REG_RW__WDAT_PARITY_CHECK_MASK 0x00000010L
+#define DAGB2_L1TLB_REG_RW__DISABLE_RDRET_CHECK_MASK 0x00000020L
+#define DAGB2_L1TLB_REG_RW__RESERVE_MASK 0xFFFFFFC0L
+//DAGB2_RESERVE1
+#define DAGB2_RESERVE1__RESERVE__SHIFT 0x0
+#define DAGB2_RESERVE1__RESERVE_MASK 0xFFFFFFFFL
+//DAGB2_RESERVE2
+#define DAGB2_RESERVE2__RESERVE__SHIFT 0x0
+#define DAGB2_RESERVE2__RESERVE_MASK 0xFFFFFFFFL
+//DAGB2_RESERVE3
+#define DAGB2_RESERVE3__RESERVE__SHIFT 0x0
+#define DAGB2_RESERVE3__RESERVE_MASK 0xFFFFFFFFL
+//DAGB2_RESERVE4
+#define DAGB2_RESERVE4__RESERVE__SHIFT 0x0
+#define DAGB2_RESERVE4__RESERVE_MASK 0xFFFFFFFFL
+
+
+// addressBlock: mmhub_dagb_dagbdec3
+//DAGB3_RDCLI0
+#define DAGB3_RDCLI0__VIRT_CHAN__SHIFT 0x0
+#define DAGB3_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB3_RDCLI0__URG_HIGH__SHIFT 0x4
+#define DAGB3_RDCLI0__URG_LOW__SHIFT 0x8
+#define DAGB3_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB3_RDCLI0__MAX_BW__SHIFT 0xd
+#define DAGB3_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB3_RDCLI0__MIN_BW__SHIFT 0x16
+#define DAGB3_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB3_RDCLI0__MAX_OSD__SHIFT 0x1a
+#define DAGB3_RDCLI0__VIRT_CHAN_MASK 0x00000007L
+#define DAGB3_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB3_RDCLI0__URG_HIGH_MASK 0x000000F0L
+#define DAGB3_RDCLI0__URG_LOW_MASK 0x00000F00L
+#define DAGB3_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB3_RDCLI0__MAX_BW_MASK 0x001FE000L
+#define DAGB3_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB3_RDCLI0__MIN_BW_MASK 0x01C00000L
+#define DAGB3_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB3_RDCLI0__MAX_OSD_MASK 0xFC000000L
+//DAGB3_RDCLI1
+#define DAGB3_RDCLI1__VIRT_CHAN__SHIFT 0x0
+#define DAGB3_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB3_RDCLI1__URG_HIGH__SHIFT 0x4
+#define DAGB3_RDCLI1__URG_LOW__SHIFT 0x8
+#define DAGB3_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB3_RDCLI1__MAX_BW__SHIFT 0xd
+#define DAGB3_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB3_RDCLI1__MIN_BW__SHIFT 0x16
+#define DAGB3_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB3_RDCLI1__MAX_OSD__SHIFT 0x1a
+#define DAGB3_RDCLI1__VIRT_CHAN_MASK 0x00000007L
+#define DAGB3_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB3_RDCLI1__URG_HIGH_MASK 0x000000F0L
+#define DAGB3_RDCLI1__URG_LOW_MASK 0x00000F00L
+#define DAGB3_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB3_RDCLI1__MAX_BW_MASK 0x001FE000L
+#define DAGB3_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB3_RDCLI1__MIN_BW_MASK 0x01C00000L
+#define DAGB3_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB3_RDCLI1__MAX_OSD_MASK 0xFC000000L
+//DAGB3_RDCLI2
+#define DAGB3_RDCLI2__VIRT_CHAN__SHIFT 0x0
+#define DAGB3_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB3_RDCLI2__URG_HIGH__SHIFT 0x4
+#define DAGB3_RDCLI2__URG_LOW__SHIFT 0x8
+#define DAGB3_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB3_RDCLI2__MAX_BW__SHIFT 0xd
+#define DAGB3_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB3_RDCLI2__MIN_BW__SHIFT 0x16
+#define DAGB3_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB3_RDCLI2__MAX_OSD__SHIFT 0x1a
+#define DAGB3_RDCLI2__VIRT_CHAN_MASK 0x00000007L
+#define DAGB3_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB3_RDCLI2__URG_HIGH_MASK 0x000000F0L
+#define DAGB3_RDCLI2__URG_LOW_MASK 0x00000F00L
+#define DAGB3_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB3_RDCLI2__MAX_BW_MASK 0x001FE000L
+#define DAGB3_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB3_RDCLI2__MIN_BW_MASK 0x01C00000L
+#define DAGB3_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB3_RDCLI2__MAX_OSD_MASK 0xFC000000L
+//DAGB3_RDCLI3
+#define DAGB3_RDCLI3__VIRT_CHAN__SHIFT 0x0
+#define DAGB3_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB3_RDCLI3__URG_HIGH__SHIFT 0x4
+#define DAGB3_RDCLI3__URG_LOW__SHIFT 0x8
+#define DAGB3_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB3_RDCLI3__MAX_BW__SHIFT 0xd
+#define DAGB3_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB3_RDCLI3__MIN_BW__SHIFT 0x16
+#define DAGB3_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB3_RDCLI3__MAX_OSD__SHIFT 0x1a
+#define DAGB3_RDCLI3__VIRT_CHAN_MASK 0x00000007L
+#define DAGB3_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB3_RDCLI3__URG_HIGH_MASK 0x000000F0L
+#define DAGB3_RDCLI3__URG_LOW_MASK 0x00000F00L
+#define DAGB3_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB3_RDCLI3__MAX_BW_MASK 0x001FE000L
+#define DAGB3_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB3_RDCLI3__MIN_BW_MASK 0x01C00000L
+#define DAGB3_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB3_RDCLI3__MAX_OSD_MASK 0xFC000000L
+//DAGB3_RDCLI4
+#define DAGB3_RDCLI4__VIRT_CHAN__SHIFT 0x0
+#define DAGB3_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB3_RDCLI4__URG_HIGH__SHIFT 0x4
+#define DAGB3_RDCLI4__URG_LOW__SHIFT 0x8
+#define DAGB3_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB3_RDCLI4__MAX_BW__SHIFT 0xd
+#define DAGB3_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB3_RDCLI4__MIN_BW__SHIFT 0x16
+#define DAGB3_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB3_RDCLI4__MAX_OSD__SHIFT 0x1a
+#define DAGB3_RDCLI4__VIRT_CHAN_MASK 0x00000007L
+#define DAGB3_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB3_RDCLI4__URG_HIGH_MASK 0x000000F0L
+#define DAGB3_RDCLI4__URG_LOW_MASK 0x00000F00L
+#define DAGB3_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB3_RDCLI4__MAX_BW_MASK 0x001FE000L
+#define DAGB3_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB3_RDCLI4__MIN_BW_MASK 0x01C00000L
+#define DAGB3_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB3_RDCLI4__MAX_OSD_MASK 0xFC000000L
+//DAGB3_RDCLI5
+#define DAGB3_RDCLI5__VIRT_CHAN__SHIFT 0x0
+#define DAGB3_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB3_RDCLI5__URG_HIGH__SHIFT 0x4
+#define DAGB3_RDCLI5__URG_LOW__SHIFT 0x8
+#define DAGB3_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB3_RDCLI5__MAX_BW__SHIFT 0xd
+#define DAGB3_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB3_RDCLI5__MIN_BW__SHIFT 0x16
+#define DAGB3_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB3_RDCLI5__MAX_OSD__SHIFT 0x1a
+#define DAGB3_RDCLI5__VIRT_CHAN_MASK 0x00000007L
+#define DAGB3_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB3_RDCLI5__URG_HIGH_MASK 0x000000F0L
+#define DAGB3_RDCLI5__URG_LOW_MASK 0x00000F00L
+#define DAGB3_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB3_RDCLI5__MAX_BW_MASK 0x001FE000L
+#define DAGB3_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB3_RDCLI5__MIN_BW_MASK 0x01C00000L
+#define DAGB3_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB3_RDCLI5__MAX_OSD_MASK 0xFC000000L
+//DAGB3_RDCLI6
+#define DAGB3_RDCLI6__VIRT_CHAN__SHIFT 0x0
+#define DAGB3_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB3_RDCLI6__URG_HIGH__SHIFT 0x4
+#define DAGB3_RDCLI6__URG_LOW__SHIFT 0x8
+#define DAGB3_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB3_RDCLI6__MAX_BW__SHIFT 0xd
+#define DAGB3_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB3_RDCLI6__MIN_BW__SHIFT 0x16
+#define DAGB3_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB3_RDCLI6__MAX_OSD__SHIFT 0x1a
+#define DAGB3_RDCLI6__VIRT_CHAN_MASK 0x00000007L
+#define DAGB3_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB3_RDCLI6__URG_HIGH_MASK 0x000000F0L
+#define DAGB3_RDCLI6__URG_LOW_MASK 0x00000F00L
+#define DAGB3_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB3_RDCLI6__MAX_BW_MASK 0x001FE000L
+#define DAGB3_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB3_RDCLI6__MIN_BW_MASK 0x01C00000L
+#define DAGB3_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB3_RDCLI6__MAX_OSD_MASK 0xFC000000L
+//DAGB3_RDCLI7
+#define DAGB3_RDCLI7__VIRT_CHAN__SHIFT 0x0
+#define DAGB3_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB3_RDCLI7__URG_HIGH__SHIFT 0x4
+#define DAGB3_RDCLI7__URG_LOW__SHIFT 0x8
+#define DAGB3_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB3_RDCLI7__MAX_BW__SHIFT 0xd
+#define DAGB3_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB3_RDCLI7__MIN_BW__SHIFT 0x16
+#define DAGB3_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB3_RDCLI7__MAX_OSD__SHIFT 0x1a
+#define DAGB3_RDCLI7__VIRT_CHAN_MASK 0x00000007L
+#define DAGB3_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB3_RDCLI7__URG_HIGH_MASK 0x000000F0L
+#define DAGB3_RDCLI7__URG_LOW_MASK 0x00000F00L
+#define DAGB3_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB3_RDCLI7__MAX_BW_MASK 0x001FE000L
+#define DAGB3_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB3_RDCLI7__MIN_BW_MASK 0x01C00000L
+#define DAGB3_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB3_RDCLI7__MAX_OSD_MASK 0xFC000000L
+//DAGB3_RDCLI8
+#define DAGB3_RDCLI8__VIRT_CHAN__SHIFT 0x0
+#define DAGB3_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB3_RDCLI8__URG_HIGH__SHIFT 0x4
+#define DAGB3_RDCLI8__URG_LOW__SHIFT 0x8
+#define DAGB3_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB3_RDCLI8__MAX_BW__SHIFT 0xd
+#define DAGB3_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB3_RDCLI8__MIN_BW__SHIFT 0x16
+#define DAGB3_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB3_RDCLI8__MAX_OSD__SHIFT 0x1a
+#define DAGB3_RDCLI8__VIRT_CHAN_MASK 0x00000007L
+#define DAGB3_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB3_RDCLI8__URG_HIGH_MASK 0x000000F0L
+#define DAGB3_RDCLI8__URG_LOW_MASK 0x00000F00L
+#define DAGB3_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB3_RDCLI8__MAX_BW_MASK 0x001FE000L
+#define DAGB3_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB3_RDCLI8__MIN_BW_MASK 0x01C00000L
+#define DAGB3_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB3_RDCLI8__MAX_OSD_MASK 0xFC000000L
+//DAGB3_RDCLI9
+#define DAGB3_RDCLI9__VIRT_CHAN__SHIFT 0x0
+#define DAGB3_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB3_RDCLI9__URG_HIGH__SHIFT 0x4
+#define DAGB3_RDCLI9__URG_LOW__SHIFT 0x8
+#define DAGB3_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB3_RDCLI9__MAX_BW__SHIFT 0xd
+#define DAGB3_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB3_RDCLI9__MIN_BW__SHIFT 0x16
+#define DAGB3_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB3_RDCLI9__MAX_OSD__SHIFT 0x1a
+#define DAGB3_RDCLI9__VIRT_CHAN_MASK 0x00000007L
+#define DAGB3_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB3_RDCLI9__URG_HIGH_MASK 0x000000F0L
+#define DAGB3_RDCLI9__URG_LOW_MASK 0x00000F00L
+#define DAGB3_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB3_RDCLI9__MAX_BW_MASK 0x001FE000L
+#define DAGB3_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB3_RDCLI9__MIN_BW_MASK 0x01C00000L
+#define DAGB3_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB3_RDCLI9__MAX_OSD_MASK 0xFC000000L
+//DAGB3_RDCLI10
+#define DAGB3_RDCLI10__VIRT_CHAN__SHIFT 0x0
+#define DAGB3_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB3_RDCLI10__URG_HIGH__SHIFT 0x4
+#define DAGB3_RDCLI10__URG_LOW__SHIFT 0x8
+#define DAGB3_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB3_RDCLI10__MAX_BW__SHIFT 0xd
+#define DAGB3_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB3_RDCLI10__MIN_BW__SHIFT 0x16
+#define DAGB3_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB3_RDCLI10__MAX_OSD__SHIFT 0x1a
+#define DAGB3_RDCLI10__VIRT_CHAN_MASK 0x00000007L
+#define DAGB3_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB3_RDCLI10__URG_HIGH_MASK 0x000000F0L
+#define DAGB3_RDCLI10__URG_LOW_MASK 0x00000F00L
+#define DAGB3_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB3_RDCLI10__MAX_BW_MASK 0x001FE000L
+#define DAGB3_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB3_RDCLI10__MIN_BW_MASK 0x01C00000L
+#define DAGB3_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB3_RDCLI10__MAX_OSD_MASK 0xFC000000L
+//DAGB3_RDCLI11
+#define DAGB3_RDCLI11__VIRT_CHAN__SHIFT 0x0
+#define DAGB3_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB3_RDCLI11__URG_HIGH__SHIFT 0x4
+#define DAGB3_RDCLI11__URG_LOW__SHIFT 0x8
+#define DAGB3_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB3_RDCLI11__MAX_BW__SHIFT 0xd
+#define DAGB3_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB3_RDCLI11__MIN_BW__SHIFT 0x16
+#define DAGB3_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB3_RDCLI11__MAX_OSD__SHIFT 0x1a
+#define DAGB3_RDCLI11__VIRT_CHAN_MASK 0x00000007L
+#define DAGB3_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB3_RDCLI11__URG_HIGH_MASK 0x000000F0L
+#define DAGB3_RDCLI11__URG_LOW_MASK 0x00000F00L
+#define DAGB3_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB3_RDCLI11__MAX_BW_MASK 0x001FE000L
+#define DAGB3_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB3_RDCLI11__MIN_BW_MASK 0x01C00000L
+#define DAGB3_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB3_RDCLI11__MAX_OSD_MASK 0xFC000000L
+//DAGB3_RDCLI12
+#define DAGB3_RDCLI12__VIRT_CHAN__SHIFT 0x0
+#define DAGB3_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB3_RDCLI12__URG_HIGH__SHIFT 0x4
+#define DAGB3_RDCLI12__URG_LOW__SHIFT 0x8
+#define DAGB3_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB3_RDCLI12__MAX_BW__SHIFT 0xd
+#define DAGB3_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB3_RDCLI12__MIN_BW__SHIFT 0x16
+#define DAGB3_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB3_RDCLI12__MAX_OSD__SHIFT 0x1a
+#define DAGB3_RDCLI12__VIRT_CHAN_MASK 0x00000007L
+#define DAGB3_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB3_RDCLI12__URG_HIGH_MASK 0x000000F0L
+#define DAGB3_RDCLI12__URG_LOW_MASK 0x00000F00L
+#define DAGB3_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB3_RDCLI12__MAX_BW_MASK 0x001FE000L
+#define DAGB3_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB3_RDCLI12__MIN_BW_MASK 0x01C00000L
+#define DAGB3_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB3_RDCLI12__MAX_OSD_MASK 0xFC000000L
+//DAGB3_RDCLI13
+#define DAGB3_RDCLI13__VIRT_CHAN__SHIFT 0x0
+#define DAGB3_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB3_RDCLI13__URG_HIGH__SHIFT 0x4
+#define DAGB3_RDCLI13__URG_LOW__SHIFT 0x8
+#define DAGB3_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB3_RDCLI13__MAX_BW__SHIFT 0xd
+#define DAGB3_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB3_RDCLI13__MIN_BW__SHIFT 0x16
+#define DAGB3_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB3_RDCLI13__MAX_OSD__SHIFT 0x1a
+#define DAGB3_RDCLI13__VIRT_CHAN_MASK 0x00000007L
+#define DAGB3_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB3_RDCLI13__URG_HIGH_MASK 0x000000F0L
+#define DAGB3_RDCLI13__URG_LOW_MASK 0x00000F00L
+#define DAGB3_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB3_RDCLI13__MAX_BW_MASK 0x001FE000L
+#define DAGB3_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB3_RDCLI13__MIN_BW_MASK 0x01C00000L
+#define DAGB3_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB3_RDCLI13__MAX_OSD_MASK 0xFC000000L
+//DAGB3_RDCLI14
+#define DAGB3_RDCLI14__VIRT_CHAN__SHIFT 0x0
+#define DAGB3_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB3_RDCLI14__URG_HIGH__SHIFT 0x4
+#define DAGB3_RDCLI14__URG_LOW__SHIFT 0x8
+#define DAGB3_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB3_RDCLI14__MAX_BW__SHIFT 0xd
+#define DAGB3_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB3_RDCLI14__MIN_BW__SHIFT 0x16
+#define DAGB3_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB3_RDCLI14__MAX_OSD__SHIFT 0x1a
+#define DAGB3_RDCLI14__VIRT_CHAN_MASK 0x00000007L
+#define DAGB3_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB3_RDCLI14__URG_HIGH_MASK 0x000000F0L
+#define DAGB3_RDCLI14__URG_LOW_MASK 0x00000F00L
+#define DAGB3_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB3_RDCLI14__MAX_BW_MASK 0x001FE000L
+#define DAGB3_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB3_RDCLI14__MIN_BW_MASK 0x01C00000L
+#define DAGB3_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB3_RDCLI14__MAX_OSD_MASK 0xFC000000L
+//DAGB3_RDCLI15
+#define DAGB3_RDCLI15__VIRT_CHAN__SHIFT 0x0
+#define DAGB3_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB3_RDCLI15__URG_HIGH__SHIFT 0x4
+#define DAGB3_RDCLI15__URG_LOW__SHIFT 0x8
+#define DAGB3_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB3_RDCLI15__MAX_BW__SHIFT 0xd
+#define DAGB3_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB3_RDCLI15__MIN_BW__SHIFT 0x16
+#define DAGB3_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB3_RDCLI15__MAX_OSD__SHIFT 0x1a
+#define DAGB3_RDCLI15__VIRT_CHAN_MASK 0x00000007L
+#define DAGB3_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB3_RDCLI15__URG_HIGH_MASK 0x000000F0L
+#define DAGB3_RDCLI15__URG_LOW_MASK 0x00000F00L
+#define DAGB3_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB3_RDCLI15__MAX_BW_MASK 0x001FE000L
+#define DAGB3_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB3_RDCLI15__MIN_BW_MASK 0x01C00000L
+#define DAGB3_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB3_RDCLI15__MAX_OSD_MASK 0xFC000000L
+//DAGB3_RD_CNTL
+#define DAGB3_RD_CNTL__SCLK_FREQ__SHIFT 0x0
+#define DAGB3_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4
+#define DAGB3_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
+#define DAGB3_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
+#define DAGB3_RD_CNTL__IO_LEVEL__SHIFT 0x11
+#define DAGB3_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14
+#define DAGB3_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17
+#define DAGB3_RD_CNTL__FIX_JUMP__SHIFT 0x1a
+#define DAGB3_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL
+#define DAGB3_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L
+#define DAGB3_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L
+#define DAGB3_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L
+#define DAGB3_RD_CNTL__IO_LEVEL_MASK 0x000E0000L
+#define DAGB3_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L
+#define DAGB3_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L
+#define DAGB3_RD_CNTL__FIX_JUMP_MASK 0x04000000L
+//DAGB3_RD_GMI_CNTL
+#define DAGB3_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0
+#define DAGB3_RD_GMI_CNTL__LEVEL__SHIFT 0x6
+#define DAGB3_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9
+#define DAGB3_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd
+#define DAGB3_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL
+#define DAGB3_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L
+#define DAGB3_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L
+#define DAGB3_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L
+//DAGB3_RD_ADDR_DAGB
+#define DAGB3_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0
+#define DAGB3_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
+#define DAGB3_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
+#define DAGB3_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7
+#define DAGB3_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd
+#define DAGB3_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L
+#define DAGB3_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
+#define DAGB3_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
+#define DAGB3_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L
+#define DAGB3_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L
+//DAGB3_RD_OUTPUT_DAGB_MAX_BURST
+#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0
+#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4
+#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8
+#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc
+#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
+#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14
+#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18
+#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c
+#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL
+#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L
+#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L
+#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L
+#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L
+#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L
+#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L
+#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L
+//DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER
+#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0
+#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4
+#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8
+#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc
+#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
+#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14
+#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18
+#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c
+#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL
+#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L
+#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L
+#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L
+#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L
+#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L
+#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L
+#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L
+//DAGB3_RD_CGTT_CLK_CTRL
+#define DAGB3_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB3_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB3_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB3_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB3_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB3_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB3_L1TLB_RD_CGTT_CLK_CTRL
+#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB3_ATCVM_RD_CGTT_CLK_CTRL
+#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB3_RD_ADDR_DAGB_MAX_BURST0
+#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
+#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
+#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
+#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
+#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
+#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
+#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
+#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
+#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
+#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
+#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
+#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
+#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
+#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
+#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
+#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
+//DAGB3_RD_ADDR_DAGB_LAZY_TIMER0
+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
+//DAGB3_RD_ADDR_DAGB_MAX_BURST1
+#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
+#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
+#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
+#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
+#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
+#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
+#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
+#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
+#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
+#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
+#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
+#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
+#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
+#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
+#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
+#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
+//DAGB3_RD_ADDR_DAGB_LAZY_TIMER1
+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
+//DAGB3_RD_VC0_CNTL
+#define DAGB3_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB3_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB3_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB3_RD_VC0_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB3_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB3_RD_VC0_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB3_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB3_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB3_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB3_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB3_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB3_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB3_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB3_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB3_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB3_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB3_RD_VC1_CNTL
+#define DAGB3_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB3_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB3_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB3_RD_VC1_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB3_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB3_RD_VC1_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB3_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB3_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB3_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB3_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB3_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB3_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB3_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB3_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB3_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB3_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB3_RD_VC2_CNTL
+#define DAGB3_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB3_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB3_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB3_RD_VC2_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB3_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB3_RD_VC2_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB3_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB3_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB3_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB3_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB3_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB3_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB3_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB3_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB3_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB3_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB3_RD_VC3_CNTL
+#define DAGB3_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB3_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB3_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB3_RD_VC3_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB3_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB3_RD_VC3_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB3_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB3_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB3_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB3_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB3_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB3_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB3_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB3_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB3_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB3_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB3_RD_VC4_CNTL
+#define DAGB3_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB3_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB3_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB3_RD_VC4_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB3_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB3_RD_VC4_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB3_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB3_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB3_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB3_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB3_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB3_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB3_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB3_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB3_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB3_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB3_RD_VC5_CNTL
+#define DAGB3_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB3_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB3_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB3_RD_VC5_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB3_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB3_RD_VC5_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB3_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB3_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB3_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB3_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB3_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB3_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB3_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB3_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB3_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB3_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB3_RD_VC6_CNTL
+#define DAGB3_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB3_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB3_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB3_RD_VC6_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB3_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB3_RD_VC6_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB3_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB3_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB3_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB3_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB3_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB3_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB3_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB3_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB3_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB3_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB3_RD_VC7_CNTL
+#define DAGB3_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB3_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB3_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB3_RD_VC7_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB3_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB3_RD_VC7_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB3_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB3_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB3_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB3_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB3_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB3_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB3_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB3_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB3_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB3_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB3_RD_CNTL_MISC
+#define DAGB3_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0
+#define DAGB3_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6
+#define DAGB3_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd
+#define DAGB3_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13
+#define DAGB3_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14
+#define DAGB3_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15
+#define DAGB3_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a
+#define DAGB3_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL
+#define DAGB3_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L
+#define DAGB3_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L
+#define DAGB3_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L
+#define DAGB3_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L
+#define DAGB3_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L
+#define DAGB3_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L
+//DAGB3_RD_TLB_CREDIT
+#define DAGB3_RD_TLB_CREDIT__TLB0__SHIFT 0x0
+#define DAGB3_RD_TLB_CREDIT__TLB1__SHIFT 0x5
+#define DAGB3_RD_TLB_CREDIT__TLB2__SHIFT 0xa
+#define DAGB3_RD_TLB_CREDIT__TLB3__SHIFT 0xf
+#define DAGB3_RD_TLB_CREDIT__TLB4__SHIFT 0x14
+#define DAGB3_RD_TLB_CREDIT__TLB5__SHIFT 0x19
+#define DAGB3_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL
+#define DAGB3_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L
+#define DAGB3_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L
+#define DAGB3_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L
+#define DAGB3_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L
+#define DAGB3_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L
+//DAGB3_RD_RDRET_CREDIT_CNTL
+#define DAGB3_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT 0x0
+#define DAGB3_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT 0x6
+#define DAGB3_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT 0xc
+#define DAGB3_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT 0x12
+#define DAGB3_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT 0x18
+#define DAGB3_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT 0x1e
+#define DAGB3_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT 0x1f
+#define DAGB3_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK 0x0000003FL
+#define DAGB3_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK 0x00000FC0L
+#define DAGB3_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK 0x0003F000L
+#define DAGB3_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK 0x00FC0000L
+#define DAGB3_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK 0x3F000000L
+#define DAGB3_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK 0x40000000L
+#define DAGB3_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK 0x80000000L
+//DAGB3_RD_RDRET_CREDIT_CNTL2
+#define DAGB3_RD_RDRET_CREDIT_CNTL2__IO_CREDIT__SHIFT 0x0
+#define DAGB3_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT__SHIFT 0x6
+#define DAGB3_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT 0xc
+#define DAGB3_RD_RDRET_CREDIT_CNTL2__IO_CREDIT_MASK 0x0000003FL
+#define DAGB3_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT_MASK 0x00000FC0L
+#define DAGB3_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK 0x0007F000L
+//DAGB3_RDCLI_ASK_PENDING
+#define DAGB3_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0
+#define DAGB3_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB3_RDCLI_GO_PENDING
+#define DAGB3_RDCLI_GO_PENDING__BUSY__SHIFT 0x0
+#define DAGB3_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB3_RDCLI_GBLSEND_PENDING
+#define DAGB3_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0
+#define DAGB3_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB3_RDCLI_TLB_PENDING
+#define DAGB3_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0
+#define DAGB3_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB3_RDCLI_OARB_PENDING
+#define DAGB3_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0
+#define DAGB3_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB3_RDCLI_OSD_PENDING
+#define DAGB3_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0
+#define DAGB3_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB3_WRCLI0
+#define DAGB3_WRCLI0__VIRT_CHAN__SHIFT 0x0
+#define DAGB3_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB3_WRCLI0__URG_HIGH__SHIFT 0x4
+#define DAGB3_WRCLI0__URG_LOW__SHIFT 0x8
+#define DAGB3_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB3_WRCLI0__MAX_BW__SHIFT 0xd
+#define DAGB3_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB3_WRCLI0__MIN_BW__SHIFT 0x16
+#define DAGB3_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB3_WRCLI0__MAX_OSD__SHIFT 0x1a
+#define DAGB3_WRCLI0__VIRT_CHAN_MASK 0x00000007L
+#define DAGB3_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB3_WRCLI0__URG_HIGH_MASK 0x000000F0L
+#define DAGB3_WRCLI0__URG_LOW_MASK 0x00000F00L
+#define DAGB3_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB3_WRCLI0__MAX_BW_MASK 0x001FE000L
+#define DAGB3_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB3_WRCLI0__MIN_BW_MASK 0x01C00000L
+#define DAGB3_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB3_WRCLI0__MAX_OSD_MASK 0xFC000000L
+//DAGB3_WRCLI1
+#define DAGB3_WRCLI1__VIRT_CHAN__SHIFT 0x0
+#define DAGB3_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB3_WRCLI1__URG_HIGH__SHIFT 0x4
+#define DAGB3_WRCLI1__URG_LOW__SHIFT 0x8
+#define DAGB3_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB3_WRCLI1__MAX_BW__SHIFT 0xd
+#define DAGB3_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB3_WRCLI1__MIN_BW__SHIFT 0x16
+#define DAGB3_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB3_WRCLI1__MAX_OSD__SHIFT 0x1a
+#define DAGB3_WRCLI1__VIRT_CHAN_MASK 0x00000007L
+#define DAGB3_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB3_WRCLI1__URG_HIGH_MASK 0x000000F0L
+#define DAGB3_WRCLI1__URG_LOW_MASK 0x00000F00L
+#define DAGB3_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB3_WRCLI1__MAX_BW_MASK 0x001FE000L
+#define DAGB3_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB3_WRCLI1__MIN_BW_MASK 0x01C00000L
+#define DAGB3_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB3_WRCLI1__MAX_OSD_MASK 0xFC000000L
+//DAGB3_WRCLI2
+#define DAGB3_WRCLI2__VIRT_CHAN__SHIFT 0x0
+#define DAGB3_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB3_WRCLI2__URG_HIGH__SHIFT 0x4
+#define DAGB3_WRCLI2__URG_LOW__SHIFT 0x8
+#define DAGB3_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB3_WRCLI2__MAX_BW__SHIFT 0xd
+#define DAGB3_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB3_WRCLI2__MIN_BW__SHIFT 0x16
+#define DAGB3_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB3_WRCLI2__MAX_OSD__SHIFT 0x1a
+#define DAGB3_WRCLI2__VIRT_CHAN_MASK 0x00000007L
+#define DAGB3_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB3_WRCLI2__URG_HIGH_MASK 0x000000F0L
+#define DAGB3_WRCLI2__URG_LOW_MASK 0x00000F00L
+#define DAGB3_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB3_WRCLI2__MAX_BW_MASK 0x001FE000L
+#define DAGB3_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB3_WRCLI2__MIN_BW_MASK 0x01C00000L
+#define DAGB3_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB3_WRCLI2__MAX_OSD_MASK 0xFC000000L
+//DAGB3_WRCLI3
+#define DAGB3_WRCLI3__VIRT_CHAN__SHIFT 0x0
+#define DAGB3_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB3_WRCLI3__URG_HIGH__SHIFT 0x4
+#define DAGB3_WRCLI3__URG_LOW__SHIFT 0x8
+#define DAGB3_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB3_WRCLI3__MAX_BW__SHIFT 0xd
+#define DAGB3_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB3_WRCLI3__MIN_BW__SHIFT 0x16
+#define DAGB3_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB3_WRCLI3__MAX_OSD__SHIFT 0x1a
+#define DAGB3_WRCLI3__VIRT_CHAN_MASK 0x00000007L
+#define DAGB3_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB3_WRCLI3__URG_HIGH_MASK 0x000000F0L
+#define DAGB3_WRCLI3__URG_LOW_MASK 0x00000F00L
+#define DAGB3_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB3_WRCLI3__MAX_BW_MASK 0x001FE000L
+#define DAGB3_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB3_WRCLI3__MIN_BW_MASK 0x01C00000L
+#define DAGB3_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB3_WRCLI3__MAX_OSD_MASK 0xFC000000L
+//DAGB3_WRCLI4
+#define DAGB3_WRCLI4__VIRT_CHAN__SHIFT 0x0
+#define DAGB3_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB3_WRCLI4__URG_HIGH__SHIFT 0x4
+#define DAGB3_WRCLI4__URG_LOW__SHIFT 0x8
+#define DAGB3_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB3_WRCLI4__MAX_BW__SHIFT 0xd
+#define DAGB3_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB3_WRCLI4__MIN_BW__SHIFT 0x16
+#define DAGB3_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB3_WRCLI4__MAX_OSD__SHIFT 0x1a
+#define DAGB3_WRCLI4__VIRT_CHAN_MASK 0x00000007L
+#define DAGB3_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB3_WRCLI4__URG_HIGH_MASK 0x000000F0L
+#define DAGB3_WRCLI4__URG_LOW_MASK 0x00000F00L
+#define DAGB3_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB3_WRCLI4__MAX_BW_MASK 0x001FE000L
+#define DAGB3_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB3_WRCLI4__MIN_BW_MASK 0x01C00000L
+#define DAGB3_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB3_WRCLI4__MAX_OSD_MASK 0xFC000000L
+//DAGB3_WRCLI5
+#define DAGB3_WRCLI5__VIRT_CHAN__SHIFT 0x0
+#define DAGB3_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB3_WRCLI5__URG_HIGH__SHIFT 0x4
+#define DAGB3_WRCLI5__URG_LOW__SHIFT 0x8
+#define DAGB3_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB3_WRCLI5__MAX_BW__SHIFT 0xd
+#define DAGB3_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB3_WRCLI5__MIN_BW__SHIFT 0x16
+#define DAGB3_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB3_WRCLI5__MAX_OSD__SHIFT 0x1a
+#define DAGB3_WRCLI5__VIRT_CHAN_MASK 0x00000007L
+#define DAGB3_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB3_WRCLI5__URG_HIGH_MASK 0x000000F0L
+#define DAGB3_WRCLI5__URG_LOW_MASK 0x00000F00L
+#define DAGB3_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB3_WRCLI5__MAX_BW_MASK 0x001FE000L
+#define DAGB3_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB3_WRCLI5__MIN_BW_MASK 0x01C00000L
+#define DAGB3_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB3_WRCLI5__MAX_OSD_MASK 0xFC000000L
+//DAGB3_WRCLI6
+#define DAGB3_WRCLI6__VIRT_CHAN__SHIFT 0x0
+#define DAGB3_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB3_WRCLI6__URG_HIGH__SHIFT 0x4
+#define DAGB3_WRCLI6__URG_LOW__SHIFT 0x8
+#define DAGB3_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB3_WRCLI6__MAX_BW__SHIFT 0xd
+#define DAGB3_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB3_WRCLI6__MIN_BW__SHIFT 0x16
+#define DAGB3_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB3_WRCLI6__MAX_OSD__SHIFT 0x1a
+#define DAGB3_WRCLI6__VIRT_CHAN_MASK 0x00000007L
+#define DAGB3_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB3_WRCLI6__URG_HIGH_MASK 0x000000F0L
+#define DAGB3_WRCLI6__URG_LOW_MASK 0x00000F00L
+#define DAGB3_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB3_WRCLI6__MAX_BW_MASK 0x001FE000L
+#define DAGB3_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB3_WRCLI6__MIN_BW_MASK 0x01C00000L
+#define DAGB3_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB3_WRCLI6__MAX_OSD_MASK 0xFC000000L
+//DAGB3_WRCLI7
+#define DAGB3_WRCLI7__VIRT_CHAN__SHIFT 0x0
+#define DAGB3_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB3_WRCLI7__URG_HIGH__SHIFT 0x4
+#define DAGB3_WRCLI7__URG_LOW__SHIFT 0x8
+#define DAGB3_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB3_WRCLI7__MAX_BW__SHIFT 0xd
+#define DAGB3_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB3_WRCLI7__MIN_BW__SHIFT 0x16
+#define DAGB3_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB3_WRCLI7__MAX_OSD__SHIFT 0x1a
+#define DAGB3_WRCLI7__VIRT_CHAN_MASK 0x00000007L
+#define DAGB3_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB3_WRCLI7__URG_HIGH_MASK 0x000000F0L
+#define DAGB3_WRCLI7__URG_LOW_MASK 0x00000F00L
+#define DAGB3_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB3_WRCLI7__MAX_BW_MASK 0x001FE000L
+#define DAGB3_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB3_WRCLI7__MIN_BW_MASK 0x01C00000L
+#define DAGB3_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB3_WRCLI7__MAX_OSD_MASK 0xFC000000L
+//DAGB3_WRCLI8
+#define DAGB3_WRCLI8__VIRT_CHAN__SHIFT 0x0
+#define DAGB3_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB3_WRCLI8__URG_HIGH__SHIFT 0x4
+#define DAGB3_WRCLI8__URG_LOW__SHIFT 0x8
+#define DAGB3_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB3_WRCLI8__MAX_BW__SHIFT 0xd
+#define DAGB3_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB3_WRCLI8__MIN_BW__SHIFT 0x16
+#define DAGB3_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB3_WRCLI8__MAX_OSD__SHIFT 0x1a
+#define DAGB3_WRCLI8__VIRT_CHAN_MASK 0x00000007L
+#define DAGB3_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB3_WRCLI8__URG_HIGH_MASK 0x000000F0L
+#define DAGB3_WRCLI8__URG_LOW_MASK 0x00000F00L
+#define DAGB3_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB3_WRCLI8__MAX_BW_MASK 0x001FE000L
+#define DAGB3_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB3_WRCLI8__MIN_BW_MASK 0x01C00000L
+#define DAGB3_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB3_WRCLI8__MAX_OSD_MASK 0xFC000000L
+//DAGB3_WRCLI9
+#define DAGB3_WRCLI9__VIRT_CHAN__SHIFT 0x0
+#define DAGB3_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB3_WRCLI9__URG_HIGH__SHIFT 0x4
+#define DAGB3_WRCLI9__URG_LOW__SHIFT 0x8
+#define DAGB3_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB3_WRCLI9__MAX_BW__SHIFT 0xd
+#define DAGB3_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB3_WRCLI9__MIN_BW__SHIFT 0x16
+#define DAGB3_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB3_WRCLI9__MAX_OSD__SHIFT 0x1a
+#define DAGB3_WRCLI9__VIRT_CHAN_MASK 0x00000007L
+#define DAGB3_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB3_WRCLI9__URG_HIGH_MASK 0x000000F0L
+#define DAGB3_WRCLI9__URG_LOW_MASK 0x00000F00L
+#define DAGB3_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB3_WRCLI9__MAX_BW_MASK 0x001FE000L
+#define DAGB3_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB3_WRCLI9__MIN_BW_MASK 0x01C00000L
+#define DAGB3_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB3_WRCLI9__MAX_OSD_MASK 0xFC000000L
+//DAGB3_WRCLI10
+#define DAGB3_WRCLI10__VIRT_CHAN__SHIFT 0x0
+#define DAGB3_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB3_WRCLI10__URG_HIGH__SHIFT 0x4
+#define DAGB3_WRCLI10__URG_LOW__SHIFT 0x8
+#define DAGB3_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB3_WRCLI10__MAX_BW__SHIFT 0xd
+#define DAGB3_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB3_WRCLI10__MIN_BW__SHIFT 0x16
+#define DAGB3_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB3_WRCLI10__MAX_OSD__SHIFT 0x1a
+#define DAGB3_WRCLI10__VIRT_CHAN_MASK 0x00000007L
+#define DAGB3_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB3_WRCLI10__URG_HIGH_MASK 0x000000F0L
+#define DAGB3_WRCLI10__URG_LOW_MASK 0x00000F00L
+#define DAGB3_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB3_WRCLI10__MAX_BW_MASK 0x001FE000L
+#define DAGB3_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB3_WRCLI10__MIN_BW_MASK 0x01C00000L
+#define DAGB3_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB3_WRCLI10__MAX_OSD_MASK 0xFC000000L
+//DAGB3_WRCLI11
+#define DAGB3_WRCLI11__VIRT_CHAN__SHIFT 0x0
+#define DAGB3_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB3_WRCLI11__URG_HIGH__SHIFT 0x4
+#define DAGB3_WRCLI11__URG_LOW__SHIFT 0x8
+#define DAGB3_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB3_WRCLI11__MAX_BW__SHIFT 0xd
+#define DAGB3_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB3_WRCLI11__MIN_BW__SHIFT 0x16
+#define DAGB3_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB3_WRCLI11__MAX_OSD__SHIFT 0x1a
+#define DAGB3_WRCLI11__VIRT_CHAN_MASK 0x00000007L
+#define DAGB3_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB3_WRCLI11__URG_HIGH_MASK 0x000000F0L
+#define DAGB3_WRCLI11__URG_LOW_MASK 0x00000F00L
+#define DAGB3_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB3_WRCLI11__MAX_BW_MASK 0x001FE000L
+#define DAGB3_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB3_WRCLI11__MIN_BW_MASK 0x01C00000L
+#define DAGB3_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB3_WRCLI11__MAX_OSD_MASK 0xFC000000L
+//DAGB3_WRCLI12
+#define DAGB3_WRCLI12__VIRT_CHAN__SHIFT 0x0
+#define DAGB3_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB3_WRCLI12__URG_HIGH__SHIFT 0x4
+#define DAGB3_WRCLI12__URG_LOW__SHIFT 0x8
+#define DAGB3_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB3_WRCLI12__MAX_BW__SHIFT 0xd
+#define DAGB3_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB3_WRCLI12__MIN_BW__SHIFT 0x16
+#define DAGB3_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB3_WRCLI12__MAX_OSD__SHIFT 0x1a
+#define DAGB3_WRCLI12__VIRT_CHAN_MASK 0x00000007L
+#define DAGB3_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB3_WRCLI12__URG_HIGH_MASK 0x000000F0L
+#define DAGB3_WRCLI12__URG_LOW_MASK 0x00000F00L
+#define DAGB3_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB3_WRCLI12__MAX_BW_MASK 0x001FE000L
+#define DAGB3_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB3_WRCLI12__MIN_BW_MASK 0x01C00000L
+#define DAGB3_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB3_WRCLI12__MAX_OSD_MASK 0xFC000000L
+//DAGB3_WRCLI13
+#define DAGB3_WRCLI13__VIRT_CHAN__SHIFT 0x0
+#define DAGB3_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB3_WRCLI13__URG_HIGH__SHIFT 0x4
+#define DAGB3_WRCLI13__URG_LOW__SHIFT 0x8
+#define DAGB3_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB3_WRCLI13__MAX_BW__SHIFT 0xd
+#define DAGB3_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB3_WRCLI13__MIN_BW__SHIFT 0x16
+#define DAGB3_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB3_WRCLI13__MAX_OSD__SHIFT 0x1a
+#define DAGB3_WRCLI13__VIRT_CHAN_MASK 0x00000007L
+#define DAGB3_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB3_WRCLI13__URG_HIGH_MASK 0x000000F0L
+#define DAGB3_WRCLI13__URG_LOW_MASK 0x00000F00L
+#define DAGB3_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB3_WRCLI13__MAX_BW_MASK 0x001FE000L
+#define DAGB3_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB3_WRCLI13__MIN_BW_MASK 0x01C00000L
+#define DAGB3_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB3_WRCLI13__MAX_OSD_MASK 0xFC000000L
+//DAGB3_WRCLI14
+#define DAGB3_WRCLI14__VIRT_CHAN__SHIFT 0x0
+#define DAGB3_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB3_WRCLI14__URG_HIGH__SHIFT 0x4
+#define DAGB3_WRCLI14__URG_LOW__SHIFT 0x8
+#define DAGB3_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB3_WRCLI14__MAX_BW__SHIFT 0xd
+#define DAGB3_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB3_WRCLI14__MIN_BW__SHIFT 0x16
+#define DAGB3_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB3_WRCLI14__MAX_OSD__SHIFT 0x1a
+#define DAGB3_WRCLI14__VIRT_CHAN_MASK 0x00000007L
+#define DAGB3_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB3_WRCLI14__URG_HIGH_MASK 0x000000F0L
+#define DAGB3_WRCLI14__URG_LOW_MASK 0x00000F00L
+#define DAGB3_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB3_WRCLI14__MAX_BW_MASK 0x001FE000L
+#define DAGB3_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB3_WRCLI14__MIN_BW_MASK 0x01C00000L
+#define DAGB3_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB3_WRCLI14__MAX_OSD_MASK 0xFC000000L
+//DAGB3_WRCLI15
+#define DAGB3_WRCLI15__VIRT_CHAN__SHIFT 0x0
+#define DAGB3_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB3_WRCLI15__URG_HIGH__SHIFT 0x4
+#define DAGB3_WRCLI15__URG_LOW__SHIFT 0x8
+#define DAGB3_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB3_WRCLI15__MAX_BW__SHIFT 0xd
+#define DAGB3_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB3_WRCLI15__MIN_BW__SHIFT 0x16
+#define DAGB3_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB3_WRCLI15__MAX_OSD__SHIFT 0x1a
+#define DAGB3_WRCLI15__VIRT_CHAN_MASK 0x00000007L
+#define DAGB3_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB3_WRCLI15__URG_HIGH_MASK 0x000000F0L
+#define DAGB3_WRCLI15__URG_LOW_MASK 0x00000F00L
+#define DAGB3_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB3_WRCLI15__MAX_BW_MASK 0x001FE000L
+#define DAGB3_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB3_WRCLI15__MIN_BW_MASK 0x01C00000L
+#define DAGB3_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB3_WRCLI15__MAX_OSD_MASK 0xFC000000L
+//DAGB3_WR_CNTL
+#define DAGB3_WR_CNTL__SCLK_FREQ__SHIFT 0x0
+#define DAGB3_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4
+#define DAGB3_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
+#define DAGB3_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
+#define DAGB3_WR_CNTL__IO_LEVEL__SHIFT 0x11
+#define DAGB3_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14
+#define DAGB3_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17
+#define DAGB3_WR_CNTL__FIX_JUMP__SHIFT 0x1a
+#define DAGB3_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL
+#define DAGB3_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L
+#define DAGB3_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L
+#define DAGB3_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L
+#define DAGB3_WR_CNTL__IO_LEVEL_MASK 0x000E0000L
+#define DAGB3_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L
+#define DAGB3_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L
+#define DAGB3_WR_CNTL__FIX_JUMP_MASK 0x04000000L
+//DAGB3_WR_GMI_CNTL
+#define DAGB3_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0
+#define DAGB3_WR_GMI_CNTL__LEVEL__SHIFT 0x6
+#define DAGB3_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9
+#define DAGB3_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd
+#define DAGB3_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL
+#define DAGB3_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L
+#define DAGB3_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L
+#define DAGB3_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L
+//DAGB3_WR_ADDR_DAGB
+#define DAGB3_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0
+#define DAGB3_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
+#define DAGB3_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
+#define DAGB3_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7
+#define DAGB3_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xd
+#define DAGB3_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L
+#define DAGB3_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
+#define DAGB3_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
+#define DAGB3_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L
+#define DAGB3_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L
+//DAGB3_WR_OUTPUT_DAGB_MAX_BURST
+#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0
+#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4
+#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8
+#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc
+#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
+#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14
+#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18
+#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c
+#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL
+#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L
+#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L
+#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L
+#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L
+#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L
+#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L
+#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L
+//DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER
+#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0
+#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4
+#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8
+#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc
+#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
+#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14
+#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18
+#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c
+#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL
+#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L
+#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L
+#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L
+#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L
+#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L
+#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L
+#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L
+//DAGB3_WR_CGTT_CLK_CTRL
+#define DAGB3_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB3_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB3_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB3_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB3_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB3_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB3_L1TLB_WR_CGTT_CLK_CTRL
+#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB3_ATCVM_WR_CGTT_CLK_CTRL
+#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB3_WR_ADDR_DAGB_MAX_BURST0
+#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
+#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
+#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
+#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
+#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
+#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
+#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
+#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
+#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
+#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
+#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
+#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
+#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
+#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
+#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
+#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
+//DAGB3_WR_ADDR_DAGB_LAZY_TIMER0
+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
+//DAGB3_WR_ADDR_DAGB_MAX_BURST1
+#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
+#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
+#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
+#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
+#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
+#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
+#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
+#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
+#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
+#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
+#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
+#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
+#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
+#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
+#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
+#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
+//DAGB3_WR_ADDR_DAGB_LAZY_TIMER1
+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
+//DAGB3_WR_DATA_DAGB
+#define DAGB3_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0
+#define DAGB3_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
+#define DAGB3_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
+#define DAGB3_WR_DATA_DAGB__WHOAMI__SHIFT 0x7
+#define DAGB3_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L
+#define DAGB3_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
+#define DAGB3_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
+#define DAGB3_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L
+//DAGB3_WR_DATA_DAGB_MAX_BURST0
+#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
+#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
+#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
+#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
+#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
+#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
+#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
+#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
+#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
+#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
+#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
+#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
+#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
+#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
+#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
+#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
+//DAGB3_WR_DATA_DAGB_LAZY_TIMER0
+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
+//DAGB3_WR_DATA_DAGB_MAX_BURST1
+#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
+#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
+#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
+#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
+#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
+#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
+#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
+#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
+#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
+#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
+#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
+#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
+#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
+#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
+#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
+#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
+//DAGB3_WR_DATA_DAGB_LAZY_TIMER1
+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
+//DAGB3_WR_VC0_CNTL
+#define DAGB3_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB3_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB3_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB3_WR_VC0_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB3_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB3_WR_VC0_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB3_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB3_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB3_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB3_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB3_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB3_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB3_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB3_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB3_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB3_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB3_WR_VC1_CNTL
+#define DAGB3_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB3_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB3_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB3_WR_VC1_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB3_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB3_WR_VC1_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB3_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB3_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB3_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB3_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB3_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB3_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB3_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB3_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB3_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB3_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB3_WR_VC2_CNTL
+#define DAGB3_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB3_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB3_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB3_WR_VC2_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB3_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB3_WR_VC2_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB3_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB3_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB3_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB3_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB3_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB3_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB3_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB3_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB3_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB3_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB3_WR_VC3_CNTL
+#define DAGB3_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB3_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB3_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB3_WR_VC3_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB3_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB3_WR_VC3_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB3_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB3_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB3_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB3_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB3_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB3_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB3_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB3_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB3_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB3_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB3_WR_VC4_CNTL
+#define DAGB3_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB3_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB3_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB3_WR_VC4_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB3_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB3_WR_VC4_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB3_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB3_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB3_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB3_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB3_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB3_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB3_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB3_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB3_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB3_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB3_WR_VC5_CNTL
+#define DAGB3_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB3_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB3_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB3_WR_VC5_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB3_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB3_WR_VC5_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB3_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB3_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB3_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB3_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB3_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB3_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB3_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB3_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB3_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB3_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB3_WR_VC6_CNTL
+#define DAGB3_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB3_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB3_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB3_WR_VC6_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB3_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB3_WR_VC6_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB3_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB3_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB3_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB3_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB3_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB3_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB3_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB3_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB3_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB3_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB3_WR_VC7_CNTL
+#define DAGB3_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB3_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB3_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB3_WR_VC7_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB3_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB3_WR_VC7_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB3_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB3_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB3_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB3_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB3_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB3_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB3_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB3_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB3_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB3_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB3_WR_CNTL_MISC
+#define DAGB3_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0
+#define DAGB3_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6
+#define DAGB3_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd
+#define DAGB3_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13
+#define DAGB3_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14
+#define DAGB3_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15
+#define DAGB3_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a
+#define DAGB3_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL
+#define DAGB3_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L
+#define DAGB3_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L
+#define DAGB3_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L
+#define DAGB3_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L
+#define DAGB3_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L
+#define DAGB3_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L
+//DAGB3_WR_TLB_CREDIT
+#define DAGB3_WR_TLB_CREDIT__TLB0__SHIFT 0x0
+#define DAGB3_WR_TLB_CREDIT__TLB1__SHIFT 0x5
+#define DAGB3_WR_TLB_CREDIT__TLB2__SHIFT 0xa
+#define DAGB3_WR_TLB_CREDIT__TLB3__SHIFT 0xf
+#define DAGB3_WR_TLB_CREDIT__TLB4__SHIFT 0x14
+#define DAGB3_WR_TLB_CREDIT__TLB5__SHIFT 0x19
+#define DAGB3_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL
+#define DAGB3_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L
+#define DAGB3_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L
+#define DAGB3_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L
+#define DAGB3_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L
+#define DAGB3_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L
+//DAGB3_WR_DATA_CREDIT
+#define DAGB3_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0
+#define DAGB3_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8
+#define DAGB3_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10
+#define DAGB3_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18
+#define DAGB3_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL
+#define DAGB3_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L
+#define DAGB3_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L
+#define DAGB3_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L
+//DAGB3_WR_MISC_CREDIT
+#define DAGB3_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0
+#define DAGB3_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6
+#define DAGB3_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9
+#define DAGB3_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10
+#define DAGB3_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL
+#define DAGB3_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L
+#define DAGB3_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L
+#define DAGB3_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L
+//DAGB3_WR_OSD_CREDIT_CNTL1
+#define DAGB3_WR_OSD_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0
+#define DAGB3_WR_OSD_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x4
+#define DAGB3_WR_OSD_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0x8
+#define DAGB3_WR_OSD_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xc
+#define DAGB3_WR_OSD_CREDIT_CNTL1__IO_CREDIT__SHIFT 0x10
+#define DAGB3_WR_OSD_CREDIT_CNTL1__GMI_CREDIT__SHIFT 0x14
+#define DAGB3_WR_OSD_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x18
+#define DAGB3_WR_OSD_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000000FL
+#define DAGB3_WR_OSD_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000000F0L
+#define DAGB3_WR_OSD_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00000F00L
+#define DAGB3_WR_OSD_CREDIT_CNTL1__VC3_CREDIT_MASK 0x0000F000L
+#define DAGB3_WR_OSD_CREDIT_CNTL1__IO_CREDIT_MASK 0x000F0000L
+#define DAGB3_WR_OSD_CREDIT_CNTL1__GMI_CREDIT_MASK 0x00F00000L
+#define DAGB3_WR_OSD_CREDIT_CNTL1__POOL_CREDIT_MASK 0x3F000000L
+//DAGB3_WR_OSD_CREDIT_CNTL2
+#define DAGB3_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN__SHIFT 0x0
+#define DAGB3_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY__SHIFT 0x4
+#define DAGB3_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN_MASK 0x0000000FL
+#define DAGB3_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY_MASK 0x00000010L
+//DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1
+#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0
+#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5
+#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa
+#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf
+#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14
+#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x19
+#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1a
+#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1b
+#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1__SHIFT 0x1c
+#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2__SHIFT 0x1d
+#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL
+#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L
+#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L
+#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L
+#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x01F00000L
+#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x02000000L
+#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x04000000L
+#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK 0x08000000L
+#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1_MASK 0x10000000L
+#define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2_MASK 0x20000000L
+//DAGB3_WRCLI_GPU_SNOOP_OVERRIDE
+#define DAGB3_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0
+#define DAGB3_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL
+//DAGB3_WRCLI_GPU_SNOOP_OVERRIDE_VALUE
+#define DAGB3_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0
+#define DAGB3_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0xFFFFFFFFL
+//DAGB3_WRCLI_ASK_PENDING
+#define DAGB3_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0
+#define DAGB3_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB3_WRCLI_GO_PENDING
+#define DAGB3_WRCLI_GO_PENDING__BUSY__SHIFT 0x0
+#define DAGB3_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB3_WRCLI_GBLSEND_PENDING
+#define DAGB3_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0
+#define DAGB3_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB3_WRCLI_TLB_PENDING
+#define DAGB3_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0
+#define DAGB3_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB3_WRCLI_OARB_PENDING
+#define DAGB3_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0
+#define DAGB3_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB3_WRCLI_OSD_PENDING
+#define DAGB3_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0
+#define DAGB3_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB3_WRCLI_DBUS_ASK_PENDING
+#define DAGB3_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0
+#define DAGB3_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB3_WRCLI_DBUS_GO_PENDING
+#define DAGB3_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0
+#define DAGB3_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB3_DAGB_DLY
+#define DAGB3_DAGB_DLY__DLY__SHIFT 0x0
+#define DAGB3_DAGB_DLY__CLI__SHIFT 0x8
+#define DAGB3_DAGB_DLY__POS__SHIFT 0x10
+#define DAGB3_DAGB_DLY__DLY_MASK 0x000000FFL
+#define DAGB3_DAGB_DLY__CLI_MASK 0x0000FF00L
+#define DAGB3_DAGB_DLY__POS_MASK 0x000F0000L
+//DAGB3_CNTL_MISC
+#define DAGB3_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0
+#define DAGB3_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3
+#define DAGB3_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6
+#define DAGB3_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9
+#define DAGB3_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc
+#define DAGB3_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf
+#define DAGB3_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12
+#define DAGB3_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15
+#define DAGB3_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18
+#define DAGB3_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e
+#define DAGB3_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L
+#define DAGB3_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L
+#define DAGB3_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L
+#define DAGB3_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L
+#define DAGB3_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L
+#define DAGB3_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L
+#define DAGB3_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L
+#define DAGB3_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L
+#define DAGB3_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L
+#define DAGB3_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L
+//DAGB3_CNTL_MISC2
+#define DAGB3_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0
+#define DAGB3_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1
+#define DAGB3_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2
+#define DAGB3_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3
+#define DAGB3_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4
+#define DAGB3_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5
+#define DAGB3_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6
+#define DAGB3_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7
+#define DAGB3_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8
+#define DAGB3_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9
+#define DAGB3_CNTL_MISC2__SWAP_CTL__SHIFT 0xa
+#define DAGB3_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb
+#define DAGB3_CNTL_MISC2__HDP_CID__SHIFT 0xc
+#define DAGB3_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x11
+#define DAGB3_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L
+#define DAGB3_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L
+#define DAGB3_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L
+#define DAGB3_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L
+#define DAGB3_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L
+#define DAGB3_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L
+#define DAGB3_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L
+#define DAGB3_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L
+#define DAGB3_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L
+#define DAGB3_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L
+#define DAGB3_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L
+#define DAGB3_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L
+#define DAGB3_CNTL_MISC2__HDP_CID_MASK 0x0001F000L
+#define DAGB3_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x007E0000L
+//DAGB3_FATAL_ERROR_CNTL
+#define DAGB3_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT 0x0
+#define DAGB3_FATAL_ERROR_CNTL__FILTER_NUM_MASK 0x000003FFL
+//DAGB3_FATAL_ERROR_CLEAR
+#define DAGB3_FATAL_ERROR_CLEAR__CLEAR__SHIFT 0x0
+#define DAGB3_FATAL_ERROR_CLEAR__CLEAR_MASK 0x00000001L
+//DAGB3_FATAL_ERROR_STATUS0
+#define DAGB3_FATAL_ERROR_STATUS0__VALID__SHIFT 0x0
+#define DAGB3_FATAL_ERROR_STATUS0__CID__SHIFT 0x1
+#define DAGB3_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT 0x6
+#define DAGB3_FATAL_ERROR_STATUS0__VALID_MASK 0x00000001L
+#define DAGB3_FATAL_ERROR_STATUS0__CID_MASK 0x0000003EL
+#define DAGB3_FATAL_ERROR_STATUS0__ADDR_LO_MASK 0xFFFFFFC0L
+//DAGB3_FATAL_ERROR_STATUS1
+#define DAGB3_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT 0x0
+#define DAGB3_FATAL_ERROR_STATUS1__ADDR_HI_MASK 0x0001FFFFL
+//DAGB3_FATAL_ERROR_STATUS2
+#define DAGB3_FATAL_ERROR_STATUS2__TAG__SHIFT 0x0
+#define DAGB3_FATAL_ERROR_STATUS2__VFID__SHIFT 0x10
+#define DAGB3_FATAL_ERROR_STATUS2__VF__SHIFT 0x14
+#define DAGB3_FATAL_ERROR_STATUS2__SPACE__SHIFT 0x15
+#define DAGB3_FATAL_ERROR_STATUS2__IO__SHIFT 0x16
+#define DAGB3_FATAL_ERROR_STATUS2__SIZE__SHIFT 0x17
+#define DAGB3_FATAL_ERROR_STATUS2__FED__SHIFT 0x19
+#define DAGB3_FATAL_ERROR_STATUS2__TAG_MASK 0x0000FFFFL
+#define DAGB3_FATAL_ERROR_STATUS2__VFID_MASK 0x000F0000L
+#define DAGB3_FATAL_ERROR_STATUS2__VF_MASK 0x00100000L
+#define DAGB3_FATAL_ERROR_STATUS2__SPACE_MASK 0x00200000L
+#define DAGB3_FATAL_ERROR_STATUS2__IO_MASK 0x00400000L
+#define DAGB3_FATAL_ERROR_STATUS2__SIZE_MASK 0x00800000L
+#define DAGB3_FATAL_ERROR_STATUS2__FED_MASK 0x02000000L
+//DAGB3_FATAL_ERROR_STATUS3
+#define DAGB3_FATAL_ERROR_STATUS3__OP__SHIFT 0x6
+#define DAGB3_FATAL_ERROR_STATUS3__WRTMZ__SHIFT 0x10
+#define DAGB3_FATAL_ERROR_STATUS3__RDTMZ__SHIFT 0x11
+#define DAGB3_FATAL_ERROR_STATUS3__SNOOP__SHIFT 0x12
+#define DAGB3_FATAL_ERROR_STATUS3__INVAL__SHIFT 0x13
+#define DAGB3_FATAL_ERROR_STATUS3__NACK__SHIFT 0x14
+#define DAGB3_FATAL_ERROR_STATUS3__RO__SHIFT 0x16
+#define DAGB3_FATAL_ERROR_STATUS3__MEMLOG__SHIFT 0x17
+#define DAGB3_FATAL_ERROR_STATUS3__EOP__SHIFT 0x18
+#define DAGB3_FATAL_ERROR_STATUS3__OP_MASK 0x00001FC0L
+#define DAGB3_FATAL_ERROR_STATUS3__WRTMZ_MASK 0x00010000L
+#define DAGB3_FATAL_ERROR_STATUS3__RDTMZ_MASK 0x00020000L
+#define DAGB3_FATAL_ERROR_STATUS3__SNOOP_MASK 0x00040000L
+#define DAGB3_FATAL_ERROR_STATUS3__INVAL_MASK 0x00080000L
+#define DAGB3_FATAL_ERROR_STATUS3__NACK_MASK 0x00300000L
+#define DAGB3_FATAL_ERROR_STATUS3__RO_MASK 0x00400000L
+#define DAGB3_FATAL_ERROR_STATUS3__MEMLOG_MASK 0x00800000L
+#define DAGB3_FATAL_ERROR_STATUS3__EOP_MASK 0x01000000L
+//DAGB3_FIFO_EMPTY
+#define DAGB3_FIFO_EMPTY__EMPTY__SHIFT 0x0
+#define DAGB3_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL
+//DAGB3_FIFO_FULL
+#define DAGB3_FIFO_FULL__FULL__SHIFT 0x0
+#define DAGB3_FIFO_FULL__FULL_MASK 0x007FFFFFL
+//DAGB3_WR_CREDITS_FULL
+#define DAGB3_WR_CREDITS_FULL__FULL__SHIFT 0x0
+#define DAGB3_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL
+//DAGB3_RD_CREDITS_FULL
+#define DAGB3_RD_CREDITS_FULL__FULL__SHIFT 0x0
+#define DAGB3_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL
+//DAGB3_PERFCOUNTER_LO
+#define DAGB3_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define DAGB3_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//DAGB3_PERFCOUNTER_HI
+#define DAGB3_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define DAGB3_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define DAGB3_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define DAGB3_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//DAGB3_PERFCOUNTER0_CFG
+#define DAGB3_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define DAGB3_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define DAGB3_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define DAGB3_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define DAGB3_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define DAGB3_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define DAGB3_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define DAGB3_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define DAGB3_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define DAGB3_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//DAGB3_PERFCOUNTER1_CFG
+#define DAGB3_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define DAGB3_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define DAGB3_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define DAGB3_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define DAGB3_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define DAGB3_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define DAGB3_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define DAGB3_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define DAGB3_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define DAGB3_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//DAGB3_PERFCOUNTER2_CFG
+#define DAGB3_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define DAGB3_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define DAGB3_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define DAGB3_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define DAGB3_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define DAGB3_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
+#define DAGB3_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define DAGB3_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
+#define DAGB3_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
+#define DAGB3_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
+//DAGB3_PERFCOUNTER_RSLT_CNTL
+#define DAGB3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define DAGB3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define DAGB3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define DAGB3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define DAGB3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define DAGB3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define DAGB3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define DAGB3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+//DAGB3_L1TLB_REG_RW
+#define DAGB3_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0
+#define DAGB3_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1
+#define DAGB3_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL__SHIFT 0x2
+#define DAGB3_L1TLB_REG_RW__WDAT_PARITY_CHECK__SHIFT 0x4
+#define DAGB3_L1TLB_REG_RW__DISABLE_RDRET_CHECK__SHIFT 0x5
+#define DAGB3_L1TLB_REG_RW__RESERVE__SHIFT 0x6
+#define DAGB3_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L
+#define DAGB3_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L
+#define DAGB3_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL_MASK 0x00000004L
+#define DAGB3_L1TLB_REG_RW__WDAT_PARITY_CHECK_MASK 0x00000010L
+#define DAGB3_L1TLB_REG_RW__DISABLE_RDRET_CHECK_MASK 0x00000020L
+#define DAGB3_L1TLB_REG_RW__RESERVE_MASK 0xFFFFFFC0L
+//DAGB3_RESERVE1
+#define DAGB3_RESERVE1__RESERVE__SHIFT 0x0
+#define DAGB3_RESERVE1__RESERVE_MASK 0xFFFFFFFFL
+//DAGB3_RESERVE2
+#define DAGB3_RESERVE2__RESERVE__SHIFT 0x0
+#define DAGB3_RESERVE2__RESERVE_MASK 0xFFFFFFFFL
+//DAGB3_RESERVE3
+#define DAGB3_RESERVE3__RESERVE__SHIFT 0x0
+#define DAGB3_RESERVE3__RESERVE_MASK 0xFFFFFFFFL
+//DAGB3_RESERVE4
+#define DAGB3_RESERVE4__RESERVE__SHIFT 0x0
+#define DAGB3_RESERVE4__RESERVE_MASK 0xFFFFFFFFL
+
+
+// addressBlock: mmhub_dagb_dagbdec4
+//DAGB4_RDCLI0
+#define DAGB4_RDCLI0__VIRT_CHAN__SHIFT 0x0
+#define DAGB4_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB4_RDCLI0__URG_HIGH__SHIFT 0x4
+#define DAGB4_RDCLI0__URG_LOW__SHIFT 0x8
+#define DAGB4_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB4_RDCLI0__MAX_BW__SHIFT 0xd
+#define DAGB4_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB4_RDCLI0__MIN_BW__SHIFT 0x16
+#define DAGB4_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB4_RDCLI0__MAX_OSD__SHIFT 0x1a
+#define DAGB4_RDCLI0__VIRT_CHAN_MASK 0x00000007L
+#define DAGB4_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB4_RDCLI0__URG_HIGH_MASK 0x000000F0L
+#define DAGB4_RDCLI0__URG_LOW_MASK 0x00000F00L
+#define DAGB4_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB4_RDCLI0__MAX_BW_MASK 0x001FE000L
+#define DAGB4_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB4_RDCLI0__MIN_BW_MASK 0x01C00000L
+#define DAGB4_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB4_RDCLI0__MAX_OSD_MASK 0xFC000000L
+//DAGB4_RDCLI1
+#define DAGB4_RDCLI1__VIRT_CHAN__SHIFT 0x0
+#define DAGB4_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB4_RDCLI1__URG_HIGH__SHIFT 0x4
+#define DAGB4_RDCLI1__URG_LOW__SHIFT 0x8
+#define DAGB4_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB4_RDCLI1__MAX_BW__SHIFT 0xd
+#define DAGB4_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB4_RDCLI1__MIN_BW__SHIFT 0x16
+#define DAGB4_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB4_RDCLI1__MAX_OSD__SHIFT 0x1a
+#define DAGB4_RDCLI1__VIRT_CHAN_MASK 0x00000007L
+#define DAGB4_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB4_RDCLI1__URG_HIGH_MASK 0x000000F0L
+#define DAGB4_RDCLI1__URG_LOW_MASK 0x00000F00L
+#define DAGB4_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB4_RDCLI1__MAX_BW_MASK 0x001FE000L
+#define DAGB4_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB4_RDCLI1__MIN_BW_MASK 0x01C00000L
+#define DAGB4_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB4_RDCLI1__MAX_OSD_MASK 0xFC000000L
+//DAGB4_RDCLI2
+#define DAGB4_RDCLI2__VIRT_CHAN__SHIFT 0x0
+#define DAGB4_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB4_RDCLI2__URG_HIGH__SHIFT 0x4
+#define DAGB4_RDCLI2__URG_LOW__SHIFT 0x8
+#define DAGB4_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB4_RDCLI2__MAX_BW__SHIFT 0xd
+#define DAGB4_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB4_RDCLI2__MIN_BW__SHIFT 0x16
+#define DAGB4_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB4_RDCLI2__MAX_OSD__SHIFT 0x1a
+#define DAGB4_RDCLI2__VIRT_CHAN_MASK 0x00000007L
+#define DAGB4_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB4_RDCLI2__URG_HIGH_MASK 0x000000F0L
+#define DAGB4_RDCLI2__URG_LOW_MASK 0x00000F00L
+#define DAGB4_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB4_RDCLI2__MAX_BW_MASK 0x001FE000L
+#define DAGB4_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB4_RDCLI2__MIN_BW_MASK 0x01C00000L
+#define DAGB4_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB4_RDCLI2__MAX_OSD_MASK 0xFC000000L
+//DAGB4_RDCLI3
+#define DAGB4_RDCLI3__VIRT_CHAN__SHIFT 0x0
+#define DAGB4_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB4_RDCLI3__URG_HIGH__SHIFT 0x4
+#define DAGB4_RDCLI3__URG_LOW__SHIFT 0x8
+#define DAGB4_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB4_RDCLI3__MAX_BW__SHIFT 0xd
+#define DAGB4_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB4_RDCLI3__MIN_BW__SHIFT 0x16
+#define DAGB4_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB4_RDCLI3__MAX_OSD__SHIFT 0x1a
+#define DAGB4_RDCLI3__VIRT_CHAN_MASK 0x00000007L
+#define DAGB4_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB4_RDCLI3__URG_HIGH_MASK 0x000000F0L
+#define DAGB4_RDCLI3__URG_LOW_MASK 0x00000F00L
+#define DAGB4_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB4_RDCLI3__MAX_BW_MASK 0x001FE000L
+#define DAGB4_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB4_RDCLI3__MIN_BW_MASK 0x01C00000L
+#define DAGB4_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB4_RDCLI3__MAX_OSD_MASK 0xFC000000L
+//DAGB4_RDCLI4
+#define DAGB4_RDCLI4__VIRT_CHAN__SHIFT 0x0
+#define DAGB4_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB4_RDCLI4__URG_HIGH__SHIFT 0x4
+#define DAGB4_RDCLI4__URG_LOW__SHIFT 0x8
+#define DAGB4_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB4_RDCLI4__MAX_BW__SHIFT 0xd
+#define DAGB4_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB4_RDCLI4__MIN_BW__SHIFT 0x16
+#define DAGB4_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB4_RDCLI4__MAX_OSD__SHIFT 0x1a
+#define DAGB4_RDCLI4__VIRT_CHAN_MASK 0x00000007L
+#define DAGB4_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB4_RDCLI4__URG_HIGH_MASK 0x000000F0L
+#define DAGB4_RDCLI4__URG_LOW_MASK 0x00000F00L
+#define DAGB4_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB4_RDCLI4__MAX_BW_MASK 0x001FE000L
+#define DAGB4_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB4_RDCLI4__MIN_BW_MASK 0x01C00000L
+#define DAGB4_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB4_RDCLI4__MAX_OSD_MASK 0xFC000000L
+//DAGB4_RDCLI5
+#define DAGB4_RDCLI5__VIRT_CHAN__SHIFT 0x0
+#define DAGB4_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB4_RDCLI5__URG_HIGH__SHIFT 0x4
+#define DAGB4_RDCLI5__URG_LOW__SHIFT 0x8
+#define DAGB4_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB4_RDCLI5__MAX_BW__SHIFT 0xd
+#define DAGB4_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB4_RDCLI5__MIN_BW__SHIFT 0x16
+#define DAGB4_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB4_RDCLI5__MAX_OSD__SHIFT 0x1a
+#define DAGB4_RDCLI5__VIRT_CHAN_MASK 0x00000007L
+#define DAGB4_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB4_RDCLI5__URG_HIGH_MASK 0x000000F0L
+#define DAGB4_RDCLI5__URG_LOW_MASK 0x00000F00L
+#define DAGB4_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB4_RDCLI5__MAX_BW_MASK 0x001FE000L
+#define DAGB4_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB4_RDCLI5__MIN_BW_MASK 0x01C00000L
+#define DAGB4_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB4_RDCLI5__MAX_OSD_MASK 0xFC000000L
+//DAGB4_RDCLI6
+#define DAGB4_RDCLI6__VIRT_CHAN__SHIFT 0x0
+#define DAGB4_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB4_RDCLI6__URG_HIGH__SHIFT 0x4
+#define DAGB4_RDCLI6__URG_LOW__SHIFT 0x8
+#define DAGB4_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB4_RDCLI6__MAX_BW__SHIFT 0xd
+#define DAGB4_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB4_RDCLI6__MIN_BW__SHIFT 0x16
+#define DAGB4_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB4_RDCLI6__MAX_OSD__SHIFT 0x1a
+#define DAGB4_RDCLI6__VIRT_CHAN_MASK 0x00000007L
+#define DAGB4_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB4_RDCLI6__URG_HIGH_MASK 0x000000F0L
+#define DAGB4_RDCLI6__URG_LOW_MASK 0x00000F00L
+#define DAGB4_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB4_RDCLI6__MAX_BW_MASK 0x001FE000L
+#define DAGB4_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB4_RDCLI6__MIN_BW_MASK 0x01C00000L
+#define DAGB4_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB4_RDCLI6__MAX_OSD_MASK 0xFC000000L
+//DAGB4_RDCLI7
+#define DAGB4_RDCLI7__VIRT_CHAN__SHIFT 0x0
+#define DAGB4_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB4_RDCLI7__URG_HIGH__SHIFT 0x4
+#define DAGB4_RDCLI7__URG_LOW__SHIFT 0x8
+#define DAGB4_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB4_RDCLI7__MAX_BW__SHIFT 0xd
+#define DAGB4_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB4_RDCLI7__MIN_BW__SHIFT 0x16
+#define DAGB4_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB4_RDCLI7__MAX_OSD__SHIFT 0x1a
+#define DAGB4_RDCLI7__VIRT_CHAN_MASK 0x00000007L
+#define DAGB4_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB4_RDCLI7__URG_HIGH_MASK 0x000000F0L
+#define DAGB4_RDCLI7__URG_LOW_MASK 0x00000F00L
+#define DAGB4_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB4_RDCLI7__MAX_BW_MASK 0x001FE000L
+#define DAGB4_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB4_RDCLI7__MIN_BW_MASK 0x01C00000L
+#define DAGB4_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB4_RDCLI7__MAX_OSD_MASK 0xFC000000L
+//DAGB4_RDCLI8
+#define DAGB4_RDCLI8__VIRT_CHAN__SHIFT 0x0
+#define DAGB4_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB4_RDCLI8__URG_HIGH__SHIFT 0x4
+#define DAGB4_RDCLI8__URG_LOW__SHIFT 0x8
+#define DAGB4_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB4_RDCLI8__MAX_BW__SHIFT 0xd
+#define DAGB4_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB4_RDCLI8__MIN_BW__SHIFT 0x16
+#define DAGB4_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB4_RDCLI8__MAX_OSD__SHIFT 0x1a
+#define DAGB4_RDCLI8__VIRT_CHAN_MASK 0x00000007L
+#define DAGB4_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB4_RDCLI8__URG_HIGH_MASK 0x000000F0L
+#define DAGB4_RDCLI8__URG_LOW_MASK 0x00000F00L
+#define DAGB4_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB4_RDCLI8__MAX_BW_MASK 0x001FE000L
+#define DAGB4_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB4_RDCLI8__MIN_BW_MASK 0x01C00000L
+#define DAGB4_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB4_RDCLI8__MAX_OSD_MASK 0xFC000000L
+//DAGB4_RDCLI9
+#define DAGB4_RDCLI9__VIRT_CHAN__SHIFT 0x0
+#define DAGB4_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB4_RDCLI9__URG_HIGH__SHIFT 0x4
+#define DAGB4_RDCLI9__URG_LOW__SHIFT 0x8
+#define DAGB4_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB4_RDCLI9__MAX_BW__SHIFT 0xd
+#define DAGB4_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB4_RDCLI9__MIN_BW__SHIFT 0x16
+#define DAGB4_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB4_RDCLI9__MAX_OSD__SHIFT 0x1a
+#define DAGB4_RDCLI9__VIRT_CHAN_MASK 0x00000007L
+#define DAGB4_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB4_RDCLI9__URG_HIGH_MASK 0x000000F0L
+#define DAGB4_RDCLI9__URG_LOW_MASK 0x00000F00L
+#define DAGB4_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB4_RDCLI9__MAX_BW_MASK 0x001FE000L
+#define DAGB4_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB4_RDCLI9__MIN_BW_MASK 0x01C00000L
+#define DAGB4_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB4_RDCLI9__MAX_OSD_MASK 0xFC000000L
+//DAGB4_RDCLI10
+#define DAGB4_RDCLI10__VIRT_CHAN__SHIFT 0x0
+#define DAGB4_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB4_RDCLI10__URG_HIGH__SHIFT 0x4
+#define DAGB4_RDCLI10__URG_LOW__SHIFT 0x8
+#define DAGB4_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB4_RDCLI10__MAX_BW__SHIFT 0xd
+#define DAGB4_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB4_RDCLI10__MIN_BW__SHIFT 0x16
+#define DAGB4_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB4_RDCLI10__MAX_OSD__SHIFT 0x1a
+#define DAGB4_RDCLI10__VIRT_CHAN_MASK 0x00000007L
+#define DAGB4_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB4_RDCLI10__URG_HIGH_MASK 0x000000F0L
+#define DAGB4_RDCLI10__URG_LOW_MASK 0x00000F00L
+#define DAGB4_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB4_RDCLI10__MAX_BW_MASK 0x001FE000L
+#define DAGB4_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB4_RDCLI10__MIN_BW_MASK 0x01C00000L
+#define DAGB4_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB4_RDCLI10__MAX_OSD_MASK 0xFC000000L
+//DAGB4_RDCLI11
+#define DAGB4_RDCLI11__VIRT_CHAN__SHIFT 0x0
+#define DAGB4_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB4_RDCLI11__URG_HIGH__SHIFT 0x4
+#define DAGB4_RDCLI11__URG_LOW__SHIFT 0x8
+#define DAGB4_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB4_RDCLI11__MAX_BW__SHIFT 0xd
+#define DAGB4_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB4_RDCLI11__MIN_BW__SHIFT 0x16
+#define DAGB4_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB4_RDCLI11__MAX_OSD__SHIFT 0x1a
+#define DAGB4_RDCLI11__VIRT_CHAN_MASK 0x00000007L
+#define DAGB4_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB4_RDCLI11__URG_HIGH_MASK 0x000000F0L
+#define DAGB4_RDCLI11__URG_LOW_MASK 0x00000F00L
+#define DAGB4_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB4_RDCLI11__MAX_BW_MASK 0x001FE000L
+#define DAGB4_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB4_RDCLI11__MIN_BW_MASK 0x01C00000L
+#define DAGB4_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB4_RDCLI11__MAX_OSD_MASK 0xFC000000L
+//DAGB4_RDCLI12
+#define DAGB4_RDCLI12__VIRT_CHAN__SHIFT 0x0
+#define DAGB4_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB4_RDCLI12__URG_HIGH__SHIFT 0x4
+#define DAGB4_RDCLI12__URG_LOW__SHIFT 0x8
+#define DAGB4_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB4_RDCLI12__MAX_BW__SHIFT 0xd
+#define DAGB4_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB4_RDCLI12__MIN_BW__SHIFT 0x16
+#define DAGB4_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB4_RDCLI12__MAX_OSD__SHIFT 0x1a
+#define DAGB4_RDCLI12__VIRT_CHAN_MASK 0x00000007L
+#define DAGB4_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB4_RDCLI12__URG_HIGH_MASK 0x000000F0L
+#define DAGB4_RDCLI12__URG_LOW_MASK 0x00000F00L
+#define DAGB4_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB4_RDCLI12__MAX_BW_MASK 0x001FE000L
+#define DAGB4_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB4_RDCLI12__MIN_BW_MASK 0x01C00000L
+#define DAGB4_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB4_RDCLI12__MAX_OSD_MASK 0xFC000000L
+//DAGB4_RDCLI13
+#define DAGB4_RDCLI13__VIRT_CHAN__SHIFT 0x0
+#define DAGB4_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB4_RDCLI13__URG_HIGH__SHIFT 0x4
+#define DAGB4_RDCLI13__URG_LOW__SHIFT 0x8
+#define DAGB4_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB4_RDCLI13__MAX_BW__SHIFT 0xd
+#define DAGB4_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB4_RDCLI13__MIN_BW__SHIFT 0x16
+#define DAGB4_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB4_RDCLI13__MAX_OSD__SHIFT 0x1a
+#define DAGB4_RDCLI13__VIRT_CHAN_MASK 0x00000007L
+#define DAGB4_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB4_RDCLI13__URG_HIGH_MASK 0x000000F0L
+#define DAGB4_RDCLI13__URG_LOW_MASK 0x00000F00L
+#define DAGB4_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB4_RDCLI13__MAX_BW_MASK 0x001FE000L
+#define DAGB4_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB4_RDCLI13__MIN_BW_MASK 0x01C00000L
+#define DAGB4_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB4_RDCLI13__MAX_OSD_MASK 0xFC000000L
+//DAGB4_RDCLI14
+#define DAGB4_RDCLI14__VIRT_CHAN__SHIFT 0x0
+#define DAGB4_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB4_RDCLI14__URG_HIGH__SHIFT 0x4
+#define DAGB4_RDCLI14__URG_LOW__SHIFT 0x8
+#define DAGB4_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB4_RDCLI14__MAX_BW__SHIFT 0xd
+#define DAGB4_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB4_RDCLI14__MIN_BW__SHIFT 0x16
+#define DAGB4_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB4_RDCLI14__MAX_OSD__SHIFT 0x1a
+#define DAGB4_RDCLI14__VIRT_CHAN_MASK 0x00000007L
+#define DAGB4_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB4_RDCLI14__URG_HIGH_MASK 0x000000F0L
+#define DAGB4_RDCLI14__URG_LOW_MASK 0x00000F00L
+#define DAGB4_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB4_RDCLI14__MAX_BW_MASK 0x001FE000L
+#define DAGB4_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB4_RDCLI14__MIN_BW_MASK 0x01C00000L
+#define DAGB4_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB4_RDCLI14__MAX_OSD_MASK 0xFC000000L
+//DAGB4_RDCLI15
+#define DAGB4_RDCLI15__VIRT_CHAN__SHIFT 0x0
+#define DAGB4_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB4_RDCLI15__URG_HIGH__SHIFT 0x4
+#define DAGB4_RDCLI15__URG_LOW__SHIFT 0x8
+#define DAGB4_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB4_RDCLI15__MAX_BW__SHIFT 0xd
+#define DAGB4_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB4_RDCLI15__MIN_BW__SHIFT 0x16
+#define DAGB4_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB4_RDCLI15__MAX_OSD__SHIFT 0x1a
+#define DAGB4_RDCLI15__VIRT_CHAN_MASK 0x00000007L
+#define DAGB4_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB4_RDCLI15__URG_HIGH_MASK 0x000000F0L
+#define DAGB4_RDCLI15__URG_LOW_MASK 0x00000F00L
+#define DAGB4_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB4_RDCLI15__MAX_BW_MASK 0x001FE000L
+#define DAGB4_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB4_RDCLI15__MIN_BW_MASK 0x01C00000L
+#define DAGB4_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB4_RDCLI15__MAX_OSD_MASK 0xFC000000L
+//DAGB4_RD_CNTL
+#define DAGB4_RD_CNTL__SCLK_FREQ__SHIFT 0x0
+#define DAGB4_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4
+#define DAGB4_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
+#define DAGB4_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
+#define DAGB4_RD_CNTL__IO_LEVEL__SHIFT 0x11
+#define DAGB4_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14
+#define DAGB4_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17
+#define DAGB4_RD_CNTL__FIX_JUMP__SHIFT 0x1a
+#define DAGB4_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL
+#define DAGB4_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L
+#define DAGB4_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L
+#define DAGB4_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L
+#define DAGB4_RD_CNTL__IO_LEVEL_MASK 0x000E0000L
+#define DAGB4_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L
+#define DAGB4_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L
+#define DAGB4_RD_CNTL__FIX_JUMP_MASK 0x04000000L
+//DAGB4_RD_GMI_CNTL
+#define DAGB4_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0
+#define DAGB4_RD_GMI_CNTL__LEVEL__SHIFT 0x6
+#define DAGB4_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9
+#define DAGB4_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd
+#define DAGB4_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL
+#define DAGB4_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L
+#define DAGB4_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L
+#define DAGB4_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L
+//DAGB4_RD_ADDR_DAGB
+#define DAGB4_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0
+#define DAGB4_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
+#define DAGB4_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
+#define DAGB4_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7
+#define DAGB4_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd
+#define DAGB4_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L
+#define DAGB4_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
+#define DAGB4_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
+#define DAGB4_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L
+#define DAGB4_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L
+//DAGB4_RD_OUTPUT_DAGB_MAX_BURST
+#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0
+#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4
+#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8
+#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc
+#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
+#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14
+#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18
+#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c
+#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL
+#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L
+#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L
+#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L
+#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L
+#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L
+#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L
+#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L
+//DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER
+#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0
+#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4
+#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8
+#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc
+#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
+#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14
+#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18
+#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c
+#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL
+#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L
+#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L
+#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L
+#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L
+#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L
+#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L
+#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L
+//DAGB4_RD_CGTT_CLK_CTRL
+#define DAGB4_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB4_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB4_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB4_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB4_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB4_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB4_L1TLB_RD_CGTT_CLK_CTRL
+#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB4_ATCVM_RD_CGTT_CLK_CTRL
+#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB4_RD_ADDR_DAGB_MAX_BURST0
+#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
+#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
+#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
+#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
+#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
+#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
+#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
+#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
+#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
+#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
+#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
+#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
+#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
+#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
+#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
+#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
+//DAGB4_RD_ADDR_DAGB_LAZY_TIMER0
+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
+//DAGB4_RD_ADDR_DAGB_MAX_BURST1
+#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
+#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
+#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
+#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
+#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
+#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
+#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
+#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
+#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
+#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
+#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
+#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
+#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
+#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
+#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
+#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
+//DAGB4_RD_ADDR_DAGB_LAZY_TIMER1
+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
+//DAGB4_RD_VC0_CNTL
+#define DAGB4_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB4_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB4_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB4_RD_VC0_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB4_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB4_RD_VC0_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB4_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB4_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB4_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB4_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB4_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB4_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB4_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB4_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB4_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB4_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB4_RD_VC1_CNTL
+#define DAGB4_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB4_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB4_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB4_RD_VC1_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB4_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB4_RD_VC1_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB4_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB4_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB4_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB4_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB4_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB4_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB4_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB4_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB4_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB4_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB4_RD_VC2_CNTL
+#define DAGB4_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB4_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB4_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB4_RD_VC2_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB4_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB4_RD_VC2_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB4_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB4_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB4_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB4_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB4_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB4_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB4_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB4_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB4_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB4_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB4_RD_VC3_CNTL
+#define DAGB4_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB4_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB4_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB4_RD_VC3_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB4_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB4_RD_VC3_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB4_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB4_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB4_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB4_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB4_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB4_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB4_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB4_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB4_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB4_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB4_RD_VC4_CNTL
+#define DAGB4_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB4_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB4_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB4_RD_VC4_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB4_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB4_RD_VC4_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB4_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB4_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB4_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB4_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB4_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB4_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB4_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB4_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB4_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB4_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB4_RD_VC5_CNTL
+#define DAGB4_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB4_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB4_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB4_RD_VC5_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB4_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB4_RD_VC5_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB4_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB4_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB4_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB4_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB4_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB4_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB4_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB4_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB4_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB4_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB4_RD_VC6_CNTL
+#define DAGB4_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB4_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB4_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB4_RD_VC6_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB4_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB4_RD_VC6_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB4_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB4_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB4_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB4_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB4_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB4_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB4_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB4_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB4_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB4_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB4_RD_VC7_CNTL
+#define DAGB4_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB4_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB4_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB4_RD_VC7_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB4_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB4_RD_VC7_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB4_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB4_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB4_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB4_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB4_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB4_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB4_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB4_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB4_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB4_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB4_RD_CNTL_MISC
+#define DAGB4_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0
+#define DAGB4_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6
+#define DAGB4_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd
+#define DAGB4_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13
+#define DAGB4_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14
+#define DAGB4_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15
+#define DAGB4_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a
+#define DAGB4_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL
+#define DAGB4_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L
+#define DAGB4_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L
+#define DAGB4_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L
+#define DAGB4_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L
+#define DAGB4_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L
+#define DAGB4_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L
+//DAGB4_RD_TLB_CREDIT
+#define DAGB4_RD_TLB_CREDIT__TLB0__SHIFT 0x0
+#define DAGB4_RD_TLB_CREDIT__TLB1__SHIFT 0x5
+#define DAGB4_RD_TLB_CREDIT__TLB2__SHIFT 0xa
+#define DAGB4_RD_TLB_CREDIT__TLB3__SHIFT 0xf
+#define DAGB4_RD_TLB_CREDIT__TLB4__SHIFT 0x14
+#define DAGB4_RD_TLB_CREDIT__TLB5__SHIFT 0x19
+#define DAGB4_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL
+#define DAGB4_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L
+#define DAGB4_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L
+#define DAGB4_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L
+#define DAGB4_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L
+#define DAGB4_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L
+//DAGB4_RD_RDRET_CREDIT_CNTL
+#define DAGB4_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT 0x0
+#define DAGB4_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT 0x6
+#define DAGB4_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT 0xc
+#define DAGB4_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT 0x12
+#define DAGB4_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT 0x18
+#define DAGB4_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT 0x1e
+#define DAGB4_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT 0x1f
+#define DAGB4_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK 0x0000003FL
+#define DAGB4_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK 0x00000FC0L
+#define DAGB4_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK 0x0003F000L
+#define DAGB4_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK 0x00FC0000L
+#define DAGB4_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK 0x3F000000L
+#define DAGB4_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK 0x40000000L
+#define DAGB4_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK 0x80000000L
+//DAGB4_RD_RDRET_CREDIT_CNTL2
+#define DAGB4_RD_RDRET_CREDIT_CNTL2__IO_CREDIT__SHIFT 0x0
+#define DAGB4_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT__SHIFT 0x6
+#define DAGB4_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT 0xc
+#define DAGB4_RD_RDRET_CREDIT_CNTL2__IO_CREDIT_MASK 0x0000003FL
+#define DAGB4_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT_MASK 0x00000FC0L
+#define DAGB4_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK 0x0007F000L
+//DAGB4_RDCLI_ASK_PENDING
+#define DAGB4_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0
+#define DAGB4_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB4_RDCLI_GO_PENDING
+#define DAGB4_RDCLI_GO_PENDING__BUSY__SHIFT 0x0
+#define DAGB4_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB4_RDCLI_GBLSEND_PENDING
+#define DAGB4_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0
+#define DAGB4_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB4_RDCLI_TLB_PENDING
+#define DAGB4_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0
+#define DAGB4_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB4_RDCLI_OARB_PENDING
+#define DAGB4_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0
+#define DAGB4_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB4_RDCLI_OSD_PENDING
+#define DAGB4_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0
+#define DAGB4_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB4_WRCLI0
+#define DAGB4_WRCLI0__VIRT_CHAN__SHIFT 0x0
+#define DAGB4_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB4_WRCLI0__URG_HIGH__SHIFT 0x4
+#define DAGB4_WRCLI0__URG_LOW__SHIFT 0x8
+#define DAGB4_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB4_WRCLI0__MAX_BW__SHIFT 0xd
+#define DAGB4_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB4_WRCLI0__MIN_BW__SHIFT 0x16
+#define DAGB4_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB4_WRCLI0__MAX_OSD__SHIFT 0x1a
+#define DAGB4_WRCLI0__VIRT_CHAN_MASK 0x00000007L
+#define DAGB4_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB4_WRCLI0__URG_HIGH_MASK 0x000000F0L
+#define DAGB4_WRCLI0__URG_LOW_MASK 0x00000F00L
+#define DAGB4_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB4_WRCLI0__MAX_BW_MASK 0x001FE000L
+#define DAGB4_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB4_WRCLI0__MIN_BW_MASK 0x01C00000L
+#define DAGB4_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB4_WRCLI0__MAX_OSD_MASK 0xFC000000L
+//DAGB4_WRCLI1
+#define DAGB4_WRCLI1__VIRT_CHAN__SHIFT 0x0
+#define DAGB4_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB4_WRCLI1__URG_HIGH__SHIFT 0x4
+#define DAGB4_WRCLI1__URG_LOW__SHIFT 0x8
+#define DAGB4_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB4_WRCLI1__MAX_BW__SHIFT 0xd
+#define DAGB4_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB4_WRCLI1__MIN_BW__SHIFT 0x16
+#define DAGB4_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB4_WRCLI1__MAX_OSD__SHIFT 0x1a
+#define DAGB4_WRCLI1__VIRT_CHAN_MASK 0x00000007L
+#define DAGB4_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB4_WRCLI1__URG_HIGH_MASK 0x000000F0L
+#define DAGB4_WRCLI1__URG_LOW_MASK 0x00000F00L
+#define DAGB4_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB4_WRCLI1__MAX_BW_MASK 0x001FE000L
+#define DAGB4_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB4_WRCLI1__MIN_BW_MASK 0x01C00000L
+#define DAGB4_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB4_WRCLI1__MAX_OSD_MASK 0xFC000000L
+//DAGB4_WRCLI2
+#define DAGB4_WRCLI2__VIRT_CHAN__SHIFT 0x0
+#define DAGB4_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB4_WRCLI2__URG_HIGH__SHIFT 0x4
+#define DAGB4_WRCLI2__URG_LOW__SHIFT 0x8
+#define DAGB4_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB4_WRCLI2__MAX_BW__SHIFT 0xd
+#define DAGB4_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB4_WRCLI2__MIN_BW__SHIFT 0x16
+#define DAGB4_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB4_WRCLI2__MAX_OSD__SHIFT 0x1a
+#define DAGB4_WRCLI2__VIRT_CHAN_MASK 0x00000007L
+#define DAGB4_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB4_WRCLI2__URG_HIGH_MASK 0x000000F0L
+#define DAGB4_WRCLI2__URG_LOW_MASK 0x00000F00L
+#define DAGB4_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB4_WRCLI2__MAX_BW_MASK 0x001FE000L
+#define DAGB4_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB4_WRCLI2__MIN_BW_MASK 0x01C00000L
+#define DAGB4_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB4_WRCLI2__MAX_OSD_MASK 0xFC000000L
+//DAGB4_WRCLI3
+#define DAGB4_WRCLI3__VIRT_CHAN__SHIFT 0x0
+#define DAGB4_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB4_WRCLI3__URG_HIGH__SHIFT 0x4
+#define DAGB4_WRCLI3__URG_LOW__SHIFT 0x8
+#define DAGB4_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB4_WRCLI3__MAX_BW__SHIFT 0xd
+#define DAGB4_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB4_WRCLI3__MIN_BW__SHIFT 0x16
+#define DAGB4_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB4_WRCLI3__MAX_OSD__SHIFT 0x1a
+#define DAGB4_WRCLI3__VIRT_CHAN_MASK 0x00000007L
+#define DAGB4_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB4_WRCLI3__URG_HIGH_MASK 0x000000F0L
+#define DAGB4_WRCLI3__URG_LOW_MASK 0x00000F00L
+#define DAGB4_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB4_WRCLI3__MAX_BW_MASK 0x001FE000L
+#define DAGB4_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB4_WRCLI3__MIN_BW_MASK 0x01C00000L
+#define DAGB4_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB4_WRCLI3__MAX_OSD_MASK 0xFC000000L
+//DAGB4_WRCLI4
+#define DAGB4_WRCLI4__VIRT_CHAN__SHIFT 0x0
+#define DAGB4_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB4_WRCLI4__URG_HIGH__SHIFT 0x4
+#define DAGB4_WRCLI4__URG_LOW__SHIFT 0x8
+#define DAGB4_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB4_WRCLI4__MAX_BW__SHIFT 0xd
+#define DAGB4_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB4_WRCLI4__MIN_BW__SHIFT 0x16
+#define DAGB4_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB4_WRCLI4__MAX_OSD__SHIFT 0x1a
+#define DAGB4_WRCLI4__VIRT_CHAN_MASK 0x00000007L
+#define DAGB4_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB4_WRCLI4__URG_HIGH_MASK 0x000000F0L
+#define DAGB4_WRCLI4__URG_LOW_MASK 0x00000F00L
+#define DAGB4_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB4_WRCLI4__MAX_BW_MASK 0x001FE000L
+#define DAGB4_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB4_WRCLI4__MIN_BW_MASK 0x01C00000L
+#define DAGB4_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB4_WRCLI4__MAX_OSD_MASK 0xFC000000L
+//DAGB4_WRCLI5
+#define DAGB4_WRCLI5__VIRT_CHAN__SHIFT 0x0
+#define DAGB4_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB4_WRCLI5__URG_HIGH__SHIFT 0x4
+#define DAGB4_WRCLI5__URG_LOW__SHIFT 0x8
+#define DAGB4_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB4_WRCLI5__MAX_BW__SHIFT 0xd
+#define DAGB4_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB4_WRCLI5__MIN_BW__SHIFT 0x16
+#define DAGB4_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB4_WRCLI5__MAX_OSD__SHIFT 0x1a
+#define DAGB4_WRCLI5__VIRT_CHAN_MASK 0x00000007L
+#define DAGB4_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB4_WRCLI5__URG_HIGH_MASK 0x000000F0L
+#define DAGB4_WRCLI5__URG_LOW_MASK 0x00000F00L
+#define DAGB4_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB4_WRCLI5__MAX_BW_MASK 0x001FE000L
+#define DAGB4_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB4_WRCLI5__MIN_BW_MASK 0x01C00000L
+#define DAGB4_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB4_WRCLI5__MAX_OSD_MASK 0xFC000000L
+//DAGB4_WRCLI6
+#define DAGB4_WRCLI6__VIRT_CHAN__SHIFT 0x0
+#define DAGB4_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB4_WRCLI6__URG_HIGH__SHIFT 0x4
+#define DAGB4_WRCLI6__URG_LOW__SHIFT 0x8
+#define DAGB4_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB4_WRCLI6__MAX_BW__SHIFT 0xd
+#define DAGB4_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB4_WRCLI6__MIN_BW__SHIFT 0x16
+#define DAGB4_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB4_WRCLI6__MAX_OSD__SHIFT 0x1a
+#define DAGB4_WRCLI6__VIRT_CHAN_MASK 0x00000007L
+#define DAGB4_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB4_WRCLI6__URG_HIGH_MASK 0x000000F0L
+#define DAGB4_WRCLI6__URG_LOW_MASK 0x00000F00L
+#define DAGB4_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB4_WRCLI6__MAX_BW_MASK 0x001FE000L
+#define DAGB4_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB4_WRCLI6__MIN_BW_MASK 0x01C00000L
+#define DAGB4_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB4_WRCLI6__MAX_OSD_MASK 0xFC000000L
+//DAGB4_WRCLI7
+#define DAGB4_WRCLI7__VIRT_CHAN__SHIFT 0x0
+#define DAGB4_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB4_WRCLI7__URG_HIGH__SHIFT 0x4
+#define DAGB4_WRCLI7__URG_LOW__SHIFT 0x8
+#define DAGB4_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB4_WRCLI7__MAX_BW__SHIFT 0xd
+#define DAGB4_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB4_WRCLI7__MIN_BW__SHIFT 0x16
+#define DAGB4_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB4_WRCLI7__MAX_OSD__SHIFT 0x1a
+#define DAGB4_WRCLI7__VIRT_CHAN_MASK 0x00000007L
+#define DAGB4_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB4_WRCLI7__URG_HIGH_MASK 0x000000F0L
+#define DAGB4_WRCLI7__URG_LOW_MASK 0x00000F00L
+#define DAGB4_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB4_WRCLI7__MAX_BW_MASK 0x001FE000L
+#define DAGB4_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB4_WRCLI7__MIN_BW_MASK 0x01C00000L
+#define DAGB4_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB4_WRCLI7__MAX_OSD_MASK 0xFC000000L
+//DAGB4_WRCLI8
+#define DAGB4_WRCLI8__VIRT_CHAN__SHIFT 0x0
+#define DAGB4_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB4_WRCLI8__URG_HIGH__SHIFT 0x4
+#define DAGB4_WRCLI8__URG_LOW__SHIFT 0x8
+#define DAGB4_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB4_WRCLI8__MAX_BW__SHIFT 0xd
+#define DAGB4_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB4_WRCLI8__MIN_BW__SHIFT 0x16
+#define DAGB4_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB4_WRCLI8__MAX_OSD__SHIFT 0x1a
+#define DAGB4_WRCLI8__VIRT_CHAN_MASK 0x00000007L
+#define DAGB4_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB4_WRCLI8__URG_HIGH_MASK 0x000000F0L
+#define DAGB4_WRCLI8__URG_LOW_MASK 0x00000F00L
+#define DAGB4_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB4_WRCLI8__MAX_BW_MASK 0x001FE000L
+#define DAGB4_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB4_WRCLI8__MIN_BW_MASK 0x01C00000L
+#define DAGB4_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB4_WRCLI8__MAX_OSD_MASK 0xFC000000L
+//DAGB4_WRCLI9
+#define DAGB4_WRCLI9__VIRT_CHAN__SHIFT 0x0
+#define DAGB4_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB4_WRCLI9__URG_HIGH__SHIFT 0x4
+#define DAGB4_WRCLI9__URG_LOW__SHIFT 0x8
+#define DAGB4_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB4_WRCLI9__MAX_BW__SHIFT 0xd
+#define DAGB4_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB4_WRCLI9__MIN_BW__SHIFT 0x16
+#define DAGB4_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB4_WRCLI9__MAX_OSD__SHIFT 0x1a
+#define DAGB4_WRCLI9__VIRT_CHAN_MASK 0x00000007L
+#define DAGB4_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB4_WRCLI9__URG_HIGH_MASK 0x000000F0L
+#define DAGB4_WRCLI9__URG_LOW_MASK 0x00000F00L
+#define DAGB4_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB4_WRCLI9__MAX_BW_MASK 0x001FE000L
+#define DAGB4_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB4_WRCLI9__MIN_BW_MASK 0x01C00000L
+#define DAGB4_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB4_WRCLI9__MAX_OSD_MASK 0xFC000000L
+//DAGB4_WRCLI10
+#define DAGB4_WRCLI10__VIRT_CHAN__SHIFT 0x0
+#define DAGB4_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB4_WRCLI10__URG_HIGH__SHIFT 0x4
+#define DAGB4_WRCLI10__URG_LOW__SHIFT 0x8
+#define DAGB4_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB4_WRCLI10__MAX_BW__SHIFT 0xd
+#define DAGB4_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB4_WRCLI10__MIN_BW__SHIFT 0x16
+#define DAGB4_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB4_WRCLI10__MAX_OSD__SHIFT 0x1a
+#define DAGB4_WRCLI10__VIRT_CHAN_MASK 0x00000007L
+#define DAGB4_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB4_WRCLI10__URG_HIGH_MASK 0x000000F0L
+#define DAGB4_WRCLI10__URG_LOW_MASK 0x00000F00L
+#define DAGB4_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB4_WRCLI10__MAX_BW_MASK 0x001FE000L
+#define DAGB4_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB4_WRCLI10__MIN_BW_MASK 0x01C00000L
+#define DAGB4_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB4_WRCLI10__MAX_OSD_MASK 0xFC000000L
+//DAGB4_WRCLI11
+#define DAGB4_WRCLI11__VIRT_CHAN__SHIFT 0x0
+#define DAGB4_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB4_WRCLI11__URG_HIGH__SHIFT 0x4
+#define DAGB4_WRCLI11__URG_LOW__SHIFT 0x8
+#define DAGB4_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB4_WRCLI11__MAX_BW__SHIFT 0xd
+#define DAGB4_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB4_WRCLI11__MIN_BW__SHIFT 0x16
+#define DAGB4_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB4_WRCLI11__MAX_OSD__SHIFT 0x1a
+#define DAGB4_WRCLI11__VIRT_CHAN_MASK 0x00000007L
+#define DAGB4_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB4_WRCLI11__URG_HIGH_MASK 0x000000F0L
+#define DAGB4_WRCLI11__URG_LOW_MASK 0x00000F00L
+#define DAGB4_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB4_WRCLI11__MAX_BW_MASK 0x001FE000L
+#define DAGB4_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB4_WRCLI11__MIN_BW_MASK 0x01C00000L
+#define DAGB4_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB4_WRCLI11__MAX_OSD_MASK 0xFC000000L
+//DAGB4_WRCLI12
+#define DAGB4_WRCLI12__VIRT_CHAN__SHIFT 0x0
+#define DAGB4_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB4_WRCLI12__URG_HIGH__SHIFT 0x4
+#define DAGB4_WRCLI12__URG_LOW__SHIFT 0x8
+#define DAGB4_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB4_WRCLI12__MAX_BW__SHIFT 0xd
+#define DAGB4_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB4_WRCLI12__MIN_BW__SHIFT 0x16
+#define DAGB4_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB4_WRCLI12__MAX_OSD__SHIFT 0x1a
+#define DAGB4_WRCLI12__VIRT_CHAN_MASK 0x00000007L
+#define DAGB4_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB4_WRCLI12__URG_HIGH_MASK 0x000000F0L
+#define DAGB4_WRCLI12__URG_LOW_MASK 0x00000F00L
+#define DAGB4_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB4_WRCLI12__MAX_BW_MASK 0x001FE000L
+#define DAGB4_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB4_WRCLI12__MIN_BW_MASK 0x01C00000L
+#define DAGB4_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB4_WRCLI12__MAX_OSD_MASK 0xFC000000L
+//DAGB4_WRCLI13
+#define DAGB4_WRCLI13__VIRT_CHAN__SHIFT 0x0
+#define DAGB4_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB4_WRCLI13__URG_HIGH__SHIFT 0x4
+#define DAGB4_WRCLI13__URG_LOW__SHIFT 0x8
+#define DAGB4_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB4_WRCLI13__MAX_BW__SHIFT 0xd
+#define DAGB4_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB4_WRCLI13__MIN_BW__SHIFT 0x16
+#define DAGB4_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB4_WRCLI13__MAX_OSD__SHIFT 0x1a
+#define DAGB4_WRCLI13__VIRT_CHAN_MASK 0x00000007L
+#define DAGB4_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB4_WRCLI13__URG_HIGH_MASK 0x000000F0L
+#define DAGB4_WRCLI13__URG_LOW_MASK 0x00000F00L
+#define DAGB4_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB4_WRCLI13__MAX_BW_MASK 0x001FE000L
+#define DAGB4_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB4_WRCLI13__MIN_BW_MASK 0x01C00000L
+#define DAGB4_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB4_WRCLI13__MAX_OSD_MASK 0xFC000000L
+//DAGB4_WRCLI14
+#define DAGB4_WRCLI14__VIRT_CHAN__SHIFT 0x0
+#define DAGB4_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB4_WRCLI14__URG_HIGH__SHIFT 0x4
+#define DAGB4_WRCLI14__URG_LOW__SHIFT 0x8
+#define DAGB4_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB4_WRCLI14__MAX_BW__SHIFT 0xd
+#define DAGB4_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB4_WRCLI14__MIN_BW__SHIFT 0x16
+#define DAGB4_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB4_WRCLI14__MAX_OSD__SHIFT 0x1a
+#define DAGB4_WRCLI14__VIRT_CHAN_MASK 0x00000007L
+#define DAGB4_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB4_WRCLI14__URG_HIGH_MASK 0x000000F0L
+#define DAGB4_WRCLI14__URG_LOW_MASK 0x00000F00L
+#define DAGB4_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB4_WRCLI14__MAX_BW_MASK 0x001FE000L
+#define DAGB4_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB4_WRCLI14__MIN_BW_MASK 0x01C00000L
+#define DAGB4_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB4_WRCLI14__MAX_OSD_MASK 0xFC000000L
+//DAGB4_WRCLI15
+#define DAGB4_WRCLI15__VIRT_CHAN__SHIFT 0x0
+#define DAGB4_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB4_WRCLI15__URG_HIGH__SHIFT 0x4
+#define DAGB4_WRCLI15__URG_LOW__SHIFT 0x8
+#define DAGB4_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB4_WRCLI15__MAX_BW__SHIFT 0xd
+#define DAGB4_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB4_WRCLI15__MIN_BW__SHIFT 0x16
+#define DAGB4_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB4_WRCLI15__MAX_OSD__SHIFT 0x1a
+#define DAGB4_WRCLI15__VIRT_CHAN_MASK 0x00000007L
+#define DAGB4_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB4_WRCLI15__URG_HIGH_MASK 0x000000F0L
+#define DAGB4_WRCLI15__URG_LOW_MASK 0x00000F00L
+#define DAGB4_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB4_WRCLI15__MAX_BW_MASK 0x001FE000L
+#define DAGB4_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB4_WRCLI15__MIN_BW_MASK 0x01C00000L
+#define DAGB4_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB4_WRCLI15__MAX_OSD_MASK 0xFC000000L
+//DAGB4_WR_CNTL
+#define DAGB4_WR_CNTL__SCLK_FREQ__SHIFT 0x0
+#define DAGB4_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4
+#define DAGB4_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
+#define DAGB4_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
+#define DAGB4_WR_CNTL__IO_LEVEL__SHIFT 0x11
+#define DAGB4_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14
+#define DAGB4_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17
+#define DAGB4_WR_CNTL__FIX_JUMP__SHIFT 0x1a
+#define DAGB4_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL
+#define DAGB4_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L
+#define DAGB4_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L
+#define DAGB4_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L
+#define DAGB4_WR_CNTL__IO_LEVEL_MASK 0x000E0000L
+#define DAGB4_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L
+#define DAGB4_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L
+#define DAGB4_WR_CNTL__FIX_JUMP_MASK 0x04000000L
+//DAGB4_WR_GMI_CNTL
+#define DAGB4_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0
+#define DAGB4_WR_GMI_CNTL__LEVEL__SHIFT 0x6
+#define DAGB4_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9
+#define DAGB4_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd
+#define DAGB4_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL
+#define DAGB4_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L
+#define DAGB4_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L
+#define DAGB4_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L
+//DAGB4_WR_ADDR_DAGB
+#define DAGB4_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0
+#define DAGB4_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
+#define DAGB4_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
+#define DAGB4_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7
+#define DAGB4_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xd
+#define DAGB4_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L
+#define DAGB4_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
+#define DAGB4_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
+#define DAGB4_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L
+#define DAGB4_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L
+//DAGB4_WR_OUTPUT_DAGB_MAX_BURST
+#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0
+#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4
+#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8
+#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc
+#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
+#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14
+#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18
+#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c
+#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL
+#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L
+#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L
+#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L
+#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L
+#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L
+#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L
+#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L
+//DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER
+#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0
+#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4
+#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8
+#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc
+#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
+#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14
+#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18
+#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c
+#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL
+#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L
+#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L
+#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L
+#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L
+#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L
+#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L
+#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L
+//DAGB4_WR_CGTT_CLK_CTRL
+#define DAGB4_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB4_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB4_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB4_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB4_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB4_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB4_L1TLB_WR_CGTT_CLK_CTRL
+#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB4_ATCVM_WR_CGTT_CLK_CTRL
+#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB4_WR_ADDR_DAGB_MAX_BURST0
+#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
+#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
+#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
+#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
+#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
+#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
+#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
+#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
+#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
+#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
+#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
+#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
+#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
+#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
+#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
+#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
+//DAGB4_WR_ADDR_DAGB_LAZY_TIMER0
+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
+//DAGB4_WR_ADDR_DAGB_MAX_BURST1
+#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
+#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
+#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
+#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
+#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
+#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
+#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
+#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
+#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
+#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
+#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
+#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
+#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
+#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
+#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
+#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
+//DAGB4_WR_ADDR_DAGB_LAZY_TIMER1
+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
+//DAGB4_WR_DATA_DAGB
+#define DAGB4_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0
+#define DAGB4_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
+#define DAGB4_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
+#define DAGB4_WR_DATA_DAGB__WHOAMI__SHIFT 0x7
+#define DAGB4_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L
+#define DAGB4_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
+#define DAGB4_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
+#define DAGB4_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L
+//DAGB4_WR_DATA_DAGB_MAX_BURST0
+#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
+#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
+#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
+#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
+#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
+#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
+#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
+#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
+#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
+#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
+#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
+#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
+#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
+#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
+#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
+#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
+//DAGB4_WR_DATA_DAGB_LAZY_TIMER0
+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
+//DAGB4_WR_DATA_DAGB_MAX_BURST1
+#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
+#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
+#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
+#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
+#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
+#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
+#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
+#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
+#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
+#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
+#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
+#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
+#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
+#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
+#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
+#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
+//DAGB4_WR_DATA_DAGB_LAZY_TIMER1
+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
+//DAGB4_WR_VC0_CNTL
+#define DAGB4_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB4_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB4_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB4_WR_VC0_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB4_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB4_WR_VC0_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB4_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB4_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB4_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB4_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB4_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB4_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB4_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB4_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB4_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB4_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB4_WR_VC1_CNTL
+#define DAGB4_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB4_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB4_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB4_WR_VC1_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB4_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB4_WR_VC1_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB4_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB4_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB4_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB4_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB4_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB4_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB4_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB4_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB4_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB4_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB4_WR_VC2_CNTL
+#define DAGB4_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB4_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB4_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB4_WR_VC2_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB4_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB4_WR_VC2_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB4_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB4_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB4_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB4_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB4_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB4_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB4_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB4_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB4_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB4_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB4_WR_VC3_CNTL
+#define DAGB4_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB4_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB4_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB4_WR_VC3_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB4_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB4_WR_VC3_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB4_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB4_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB4_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB4_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB4_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB4_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB4_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB4_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB4_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB4_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB4_WR_VC4_CNTL
+#define DAGB4_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB4_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB4_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB4_WR_VC4_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB4_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB4_WR_VC4_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB4_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB4_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB4_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB4_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB4_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB4_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB4_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB4_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB4_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB4_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB4_WR_VC5_CNTL
+#define DAGB4_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB4_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB4_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB4_WR_VC5_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB4_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB4_WR_VC5_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB4_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB4_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB4_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB4_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB4_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB4_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB4_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB4_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB4_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB4_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB4_WR_VC6_CNTL
+#define DAGB4_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB4_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB4_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB4_WR_VC6_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB4_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB4_WR_VC6_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB4_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB4_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB4_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB4_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB4_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB4_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB4_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB4_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB4_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB4_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB4_WR_VC7_CNTL
+#define DAGB4_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB4_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB4_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB4_WR_VC7_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB4_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB4_WR_VC7_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB4_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB4_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB4_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB4_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB4_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB4_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB4_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB4_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB4_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB4_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB4_WR_CNTL_MISC
+#define DAGB4_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0
+#define DAGB4_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6
+#define DAGB4_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd
+#define DAGB4_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13
+#define DAGB4_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14
+#define DAGB4_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15
+#define DAGB4_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a
+#define DAGB4_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL
+#define DAGB4_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L
+#define DAGB4_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L
+#define DAGB4_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L
+#define DAGB4_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L
+#define DAGB4_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L
+#define DAGB4_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L
+//DAGB4_WR_TLB_CREDIT
+#define DAGB4_WR_TLB_CREDIT__TLB0__SHIFT 0x0
+#define DAGB4_WR_TLB_CREDIT__TLB1__SHIFT 0x5
+#define DAGB4_WR_TLB_CREDIT__TLB2__SHIFT 0xa
+#define DAGB4_WR_TLB_CREDIT__TLB3__SHIFT 0xf
+#define DAGB4_WR_TLB_CREDIT__TLB4__SHIFT 0x14
+#define DAGB4_WR_TLB_CREDIT__TLB5__SHIFT 0x19
+#define DAGB4_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL
+#define DAGB4_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L
+#define DAGB4_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L
+#define DAGB4_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L
+#define DAGB4_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L
+#define DAGB4_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L
+//DAGB4_WR_DATA_CREDIT
+#define DAGB4_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0
+#define DAGB4_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8
+#define DAGB4_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10
+#define DAGB4_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18
+#define DAGB4_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL
+#define DAGB4_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L
+#define DAGB4_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L
+#define DAGB4_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L
+//DAGB4_WR_MISC_CREDIT
+#define DAGB4_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0
+#define DAGB4_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6
+#define DAGB4_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9
+#define DAGB4_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10
+#define DAGB4_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL
+#define DAGB4_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L
+#define DAGB4_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L
+#define DAGB4_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L
+//DAGB4_WR_OSD_CREDIT_CNTL1
+#define DAGB4_WR_OSD_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0
+#define DAGB4_WR_OSD_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x4
+#define DAGB4_WR_OSD_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0x8
+#define DAGB4_WR_OSD_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xc
+#define DAGB4_WR_OSD_CREDIT_CNTL1__IO_CREDIT__SHIFT 0x10
+#define DAGB4_WR_OSD_CREDIT_CNTL1__GMI_CREDIT__SHIFT 0x14
+#define DAGB4_WR_OSD_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x18
+#define DAGB4_WR_OSD_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000000FL
+#define DAGB4_WR_OSD_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000000F0L
+#define DAGB4_WR_OSD_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00000F00L
+#define DAGB4_WR_OSD_CREDIT_CNTL1__VC3_CREDIT_MASK 0x0000F000L
+#define DAGB4_WR_OSD_CREDIT_CNTL1__IO_CREDIT_MASK 0x000F0000L
+#define DAGB4_WR_OSD_CREDIT_CNTL1__GMI_CREDIT_MASK 0x00F00000L
+#define DAGB4_WR_OSD_CREDIT_CNTL1__POOL_CREDIT_MASK 0x3F000000L
+//DAGB4_WR_OSD_CREDIT_CNTL2
+#define DAGB4_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN__SHIFT 0x0
+#define DAGB4_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY__SHIFT 0x4
+#define DAGB4_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN_MASK 0x0000000FL
+#define DAGB4_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY_MASK 0x00000010L
+//DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1
+#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0
+#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5
+#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa
+#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf
+#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14
+#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x19
+#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1a
+#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1b
+#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1__SHIFT 0x1c
+#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2__SHIFT 0x1d
+#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL
+#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L
+#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L
+#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L
+#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x01F00000L
+#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x02000000L
+#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x04000000L
+#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK 0x08000000L
+#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1_MASK 0x10000000L
+#define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2_MASK 0x20000000L
+//DAGB4_WRCLI_GPU_SNOOP_OVERRIDE
+#define DAGB4_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0
+#define DAGB4_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL
+//DAGB4_WRCLI_GPU_SNOOP_OVERRIDE_VALUE
+#define DAGB4_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0
+#define DAGB4_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0xFFFFFFFFL
+//DAGB4_WRCLI_ASK_PENDING
+#define DAGB4_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0
+#define DAGB4_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB4_WRCLI_GO_PENDING
+#define DAGB4_WRCLI_GO_PENDING__BUSY__SHIFT 0x0
+#define DAGB4_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB4_WRCLI_GBLSEND_PENDING
+#define DAGB4_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0
+#define DAGB4_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB4_WRCLI_TLB_PENDING
+#define DAGB4_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0
+#define DAGB4_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB4_WRCLI_OARB_PENDING
+#define DAGB4_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0
+#define DAGB4_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB4_WRCLI_OSD_PENDING
+#define DAGB4_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0
+#define DAGB4_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB4_WRCLI_DBUS_ASK_PENDING
+#define DAGB4_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0
+#define DAGB4_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB4_WRCLI_DBUS_GO_PENDING
+#define DAGB4_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0
+#define DAGB4_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB4_DAGB_DLY
+#define DAGB4_DAGB_DLY__DLY__SHIFT 0x0
+#define DAGB4_DAGB_DLY__CLI__SHIFT 0x8
+#define DAGB4_DAGB_DLY__POS__SHIFT 0x10
+#define DAGB4_DAGB_DLY__DLY_MASK 0x000000FFL
+#define DAGB4_DAGB_DLY__CLI_MASK 0x0000FF00L
+#define DAGB4_DAGB_DLY__POS_MASK 0x000F0000L
+//DAGB4_CNTL_MISC
+#define DAGB4_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0
+#define DAGB4_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3
+#define DAGB4_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6
+#define DAGB4_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9
+#define DAGB4_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc
+#define DAGB4_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf
+#define DAGB4_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12
+#define DAGB4_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15
+#define DAGB4_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18
+#define DAGB4_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e
+#define DAGB4_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L
+#define DAGB4_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L
+#define DAGB4_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L
+#define DAGB4_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L
+#define DAGB4_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L
+#define DAGB4_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L
+#define DAGB4_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L
+#define DAGB4_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L
+#define DAGB4_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L
+#define DAGB4_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L
+//DAGB4_CNTL_MISC2
+#define DAGB4_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0
+#define DAGB4_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1
+#define DAGB4_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2
+#define DAGB4_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3
+#define DAGB4_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4
+#define DAGB4_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5
+#define DAGB4_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6
+#define DAGB4_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7
+#define DAGB4_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8
+#define DAGB4_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9
+#define DAGB4_CNTL_MISC2__SWAP_CTL__SHIFT 0xa
+#define DAGB4_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb
+#define DAGB4_CNTL_MISC2__HDP_CID__SHIFT 0xc
+#define DAGB4_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x11
+#define DAGB4_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L
+#define DAGB4_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L
+#define DAGB4_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L
+#define DAGB4_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L
+#define DAGB4_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L
+#define DAGB4_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L
+#define DAGB4_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L
+#define DAGB4_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L
+#define DAGB4_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L
+#define DAGB4_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L
+#define DAGB4_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L
+#define DAGB4_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L
+#define DAGB4_CNTL_MISC2__HDP_CID_MASK 0x0001F000L
+#define DAGB4_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x007E0000L
+//DAGB4_FATAL_ERROR_CNTL
+#define DAGB4_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT 0x0
+#define DAGB4_FATAL_ERROR_CNTL__FILTER_NUM_MASK 0x000003FFL
+//DAGB4_FATAL_ERROR_CLEAR
+#define DAGB4_FATAL_ERROR_CLEAR__CLEAR__SHIFT 0x0
+#define DAGB4_FATAL_ERROR_CLEAR__CLEAR_MASK 0x00000001L
+//DAGB4_FATAL_ERROR_STATUS0
+#define DAGB4_FATAL_ERROR_STATUS0__VALID__SHIFT 0x0
+#define DAGB4_FATAL_ERROR_STATUS0__CID__SHIFT 0x1
+#define DAGB4_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT 0x6
+#define DAGB4_FATAL_ERROR_STATUS0__VALID_MASK 0x00000001L
+#define DAGB4_FATAL_ERROR_STATUS0__CID_MASK 0x0000003EL
+#define DAGB4_FATAL_ERROR_STATUS0__ADDR_LO_MASK 0xFFFFFFC0L
+//DAGB4_FATAL_ERROR_STATUS1
+#define DAGB4_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT 0x0
+#define DAGB4_FATAL_ERROR_STATUS1__ADDR_HI_MASK 0x0001FFFFL
+//DAGB4_FATAL_ERROR_STATUS2
+#define DAGB4_FATAL_ERROR_STATUS2__TAG__SHIFT 0x0
+#define DAGB4_FATAL_ERROR_STATUS2__VFID__SHIFT 0x10
+#define DAGB4_FATAL_ERROR_STATUS2__VF__SHIFT 0x14
+#define DAGB4_FATAL_ERROR_STATUS2__SPACE__SHIFT 0x15
+#define DAGB4_FATAL_ERROR_STATUS2__IO__SHIFT 0x16
+#define DAGB4_FATAL_ERROR_STATUS2__SIZE__SHIFT 0x17
+#define DAGB4_FATAL_ERROR_STATUS2__FED__SHIFT 0x19
+#define DAGB4_FATAL_ERROR_STATUS2__TAG_MASK 0x0000FFFFL
+#define DAGB4_FATAL_ERROR_STATUS2__VFID_MASK 0x000F0000L
+#define DAGB4_FATAL_ERROR_STATUS2__VF_MASK 0x00100000L
+#define DAGB4_FATAL_ERROR_STATUS2__SPACE_MASK 0x00200000L
+#define DAGB4_FATAL_ERROR_STATUS2__IO_MASK 0x00400000L
+#define DAGB4_FATAL_ERROR_STATUS2__SIZE_MASK 0x00800000L
+#define DAGB4_FATAL_ERROR_STATUS2__FED_MASK 0x02000000L
+//DAGB4_FATAL_ERROR_STATUS3
+#define DAGB4_FATAL_ERROR_STATUS3__OP__SHIFT 0x6
+#define DAGB4_FATAL_ERROR_STATUS3__WRTMZ__SHIFT 0x10
+#define DAGB4_FATAL_ERROR_STATUS3__RDTMZ__SHIFT 0x11
+#define DAGB4_FATAL_ERROR_STATUS3__SNOOP__SHIFT 0x12
+#define DAGB4_FATAL_ERROR_STATUS3__INVAL__SHIFT 0x13
+#define DAGB4_FATAL_ERROR_STATUS3__NACK__SHIFT 0x14
+#define DAGB4_FATAL_ERROR_STATUS3__RO__SHIFT 0x16
+#define DAGB4_FATAL_ERROR_STATUS3__MEMLOG__SHIFT 0x17
+#define DAGB4_FATAL_ERROR_STATUS3__EOP__SHIFT 0x18
+#define DAGB4_FATAL_ERROR_STATUS3__OP_MASK 0x00001FC0L
+#define DAGB4_FATAL_ERROR_STATUS3__WRTMZ_MASK 0x00010000L
+#define DAGB4_FATAL_ERROR_STATUS3__RDTMZ_MASK 0x00020000L
+#define DAGB4_FATAL_ERROR_STATUS3__SNOOP_MASK 0x00040000L
+#define DAGB4_FATAL_ERROR_STATUS3__INVAL_MASK 0x00080000L
+#define DAGB4_FATAL_ERROR_STATUS3__NACK_MASK 0x00300000L
+#define DAGB4_FATAL_ERROR_STATUS3__RO_MASK 0x00400000L
+#define DAGB4_FATAL_ERROR_STATUS3__MEMLOG_MASK 0x00800000L
+#define DAGB4_FATAL_ERROR_STATUS3__EOP_MASK 0x01000000L
+//DAGB4_FIFO_EMPTY
+#define DAGB4_FIFO_EMPTY__EMPTY__SHIFT 0x0
+#define DAGB4_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL
+//DAGB4_FIFO_FULL
+#define DAGB4_FIFO_FULL__FULL__SHIFT 0x0
+#define DAGB4_FIFO_FULL__FULL_MASK 0x007FFFFFL
+//DAGB4_WR_CREDITS_FULL
+#define DAGB4_WR_CREDITS_FULL__FULL__SHIFT 0x0
+#define DAGB4_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL
+//DAGB4_RD_CREDITS_FULL
+#define DAGB4_RD_CREDITS_FULL__FULL__SHIFT 0x0
+#define DAGB4_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL
+//DAGB4_PERFCOUNTER_LO
+#define DAGB4_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define DAGB4_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//DAGB4_PERFCOUNTER_HI
+#define DAGB4_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define DAGB4_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define DAGB4_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define DAGB4_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//DAGB4_PERFCOUNTER0_CFG
+#define DAGB4_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define DAGB4_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define DAGB4_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define DAGB4_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define DAGB4_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define DAGB4_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define DAGB4_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define DAGB4_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define DAGB4_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define DAGB4_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//DAGB4_PERFCOUNTER1_CFG
+#define DAGB4_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define DAGB4_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define DAGB4_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define DAGB4_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define DAGB4_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define DAGB4_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define DAGB4_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define DAGB4_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define DAGB4_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define DAGB4_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//DAGB4_PERFCOUNTER2_CFG
+#define DAGB4_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define DAGB4_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define DAGB4_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define DAGB4_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define DAGB4_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define DAGB4_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
+#define DAGB4_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define DAGB4_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
+#define DAGB4_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
+#define DAGB4_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
+//DAGB4_PERFCOUNTER_RSLT_CNTL
+#define DAGB4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define DAGB4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define DAGB4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define DAGB4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define DAGB4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define DAGB4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define DAGB4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define DAGB4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+//DAGB4_L1TLB_REG_RW
+#define DAGB4_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0
+#define DAGB4_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1
+#define DAGB4_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL__SHIFT 0x2
+#define DAGB4_L1TLB_REG_RW__WDAT_PARITY_CHECK__SHIFT 0x4
+#define DAGB4_L1TLB_REG_RW__DISABLE_RDRET_CHECK__SHIFT 0x5
+#define DAGB4_L1TLB_REG_RW__RESERVE__SHIFT 0x6
+#define DAGB4_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L
+#define DAGB4_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L
+#define DAGB4_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL_MASK 0x00000004L
+#define DAGB4_L1TLB_REG_RW__WDAT_PARITY_CHECK_MASK 0x00000010L
+#define DAGB4_L1TLB_REG_RW__DISABLE_RDRET_CHECK_MASK 0x00000020L
+#define DAGB4_L1TLB_REG_RW__RESERVE_MASK 0xFFFFFFC0L
+//DAGB4_RESERVE1
+#define DAGB4_RESERVE1__RESERVE__SHIFT 0x0
+#define DAGB4_RESERVE1__RESERVE_MASK 0xFFFFFFFFL
+//DAGB4_RESERVE2
+#define DAGB4_RESERVE2__RESERVE__SHIFT 0x0
+#define DAGB4_RESERVE2__RESERVE_MASK 0xFFFFFFFFL
+//DAGB4_RESERVE3
+#define DAGB4_RESERVE3__RESERVE__SHIFT 0x0
+#define DAGB4_RESERVE3__RESERVE_MASK 0xFFFFFFFFL
+//DAGB4_RESERVE4
+#define DAGB4_RESERVE4__RESERVE__SHIFT 0x0
+#define DAGB4_RESERVE4__RESERVE_MASK 0xFFFFFFFFL
+
+
+// addressBlock: mmhub_dagb_dagbdec5
+//DAGB5_RDCLI0
+#define DAGB5_RDCLI0__VIRT_CHAN__SHIFT 0x0
+#define DAGB5_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB5_RDCLI0__URG_HIGH__SHIFT 0x4
+#define DAGB5_RDCLI0__URG_LOW__SHIFT 0x8
+#define DAGB5_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB5_RDCLI0__MAX_BW__SHIFT 0xd
+#define DAGB5_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB5_RDCLI0__MIN_BW__SHIFT 0x16
+#define DAGB5_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB5_RDCLI0__MAX_OSD__SHIFT 0x1a
+#define DAGB5_RDCLI0__VIRT_CHAN_MASK 0x00000007L
+#define DAGB5_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB5_RDCLI0__URG_HIGH_MASK 0x000000F0L
+#define DAGB5_RDCLI0__URG_LOW_MASK 0x00000F00L
+#define DAGB5_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB5_RDCLI0__MAX_BW_MASK 0x001FE000L
+#define DAGB5_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB5_RDCLI0__MIN_BW_MASK 0x01C00000L
+#define DAGB5_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB5_RDCLI0__MAX_OSD_MASK 0xFC000000L
+//DAGB5_RDCLI1
+#define DAGB5_RDCLI1__VIRT_CHAN__SHIFT 0x0
+#define DAGB5_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB5_RDCLI1__URG_HIGH__SHIFT 0x4
+#define DAGB5_RDCLI1__URG_LOW__SHIFT 0x8
+#define DAGB5_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB5_RDCLI1__MAX_BW__SHIFT 0xd
+#define DAGB5_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB5_RDCLI1__MIN_BW__SHIFT 0x16
+#define DAGB5_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB5_RDCLI1__MAX_OSD__SHIFT 0x1a
+#define DAGB5_RDCLI1__VIRT_CHAN_MASK 0x00000007L
+#define DAGB5_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB5_RDCLI1__URG_HIGH_MASK 0x000000F0L
+#define DAGB5_RDCLI1__URG_LOW_MASK 0x00000F00L
+#define DAGB5_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB5_RDCLI1__MAX_BW_MASK 0x001FE000L
+#define DAGB5_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB5_RDCLI1__MIN_BW_MASK 0x01C00000L
+#define DAGB5_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB5_RDCLI1__MAX_OSD_MASK 0xFC000000L
+//DAGB5_RDCLI2
+#define DAGB5_RDCLI2__VIRT_CHAN__SHIFT 0x0
+#define DAGB5_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB5_RDCLI2__URG_HIGH__SHIFT 0x4
+#define DAGB5_RDCLI2__URG_LOW__SHIFT 0x8
+#define DAGB5_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB5_RDCLI2__MAX_BW__SHIFT 0xd
+#define DAGB5_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB5_RDCLI2__MIN_BW__SHIFT 0x16
+#define DAGB5_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB5_RDCLI2__MAX_OSD__SHIFT 0x1a
+#define DAGB5_RDCLI2__VIRT_CHAN_MASK 0x00000007L
+#define DAGB5_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB5_RDCLI2__URG_HIGH_MASK 0x000000F0L
+#define DAGB5_RDCLI2__URG_LOW_MASK 0x00000F00L
+#define DAGB5_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB5_RDCLI2__MAX_BW_MASK 0x001FE000L
+#define DAGB5_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB5_RDCLI2__MIN_BW_MASK 0x01C00000L
+#define DAGB5_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB5_RDCLI2__MAX_OSD_MASK 0xFC000000L
+//DAGB5_RDCLI3
+#define DAGB5_RDCLI3__VIRT_CHAN__SHIFT 0x0
+#define DAGB5_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB5_RDCLI3__URG_HIGH__SHIFT 0x4
+#define DAGB5_RDCLI3__URG_LOW__SHIFT 0x8
+#define DAGB5_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB5_RDCLI3__MAX_BW__SHIFT 0xd
+#define DAGB5_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB5_RDCLI3__MIN_BW__SHIFT 0x16
+#define DAGB5_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB5_RDCLI3__MAX_OSD__SHIFT 0x1a
+#define DAGB5_RDCLI3__VIRT_CHAN_MASK 0x00000007L
+#define DAGB5_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB5_RDCLI3__URG_HIGH_MASK 0x000000F0L
+#define DAGB5_RDCLI3__URG_LOW_MASK 0x00000F00L
+#define DAGB5_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB5_RDCLI3__MAX_BW_MASK 0x001FE000L
+#define DAGB5_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB5_RDCLI3__MIN_BW_MASK 0x01C00000L
+#define DAGB5_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB5_RDCLI3__MAX_OSD_MASK 0xFC000000L
+//DAGB5_RDCLI4
+#define DAGB5_RDCLI4__VIRT_CHAN__SHIFT 0x0
+#define DAGB5_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB5_RDCLI4__URG_HIGH__SHIFT 0x4
+#define DAGB5_RDCLI4__URG_LOW__SHIFT 0x8
+#define DAGB5_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB5_RDCLI4__MAX_BW__SHIFT 0xd
+#define DAGB5_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB5_RDCLI4__MIN_BW__SHIFT 0x16
+#define DAGB5_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB5_RDCLI4__MAX_OSD__SHIFT 0x1a
+#define DAGB5_RDCLI4__VIRT_CHAN_MASK 0x00000007L
+#define DAGB5_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB5_RDCLI4__URG_HIGH_MASK 0x000000F0L
+#define DAGB5_RDCLI4__URG_LOW_MASK 0x00000F00L
+#define DAGB5_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB5_RDCLI4__MAX_BW_MASK 0x001FE000L
+#define DAGB5_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB5_RDCLI4__MIN_BW_MASK 0x01C00000L
+#define DAGB5_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB5_RDCLI4__MAX_OSD_MASK 0xFC000000L
+//DAGB5_RDCLI5
+#define DAGB5_RDCLI5__VIRT_CHAN__SHIFT 0x0
+#define DAGB5_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB5_RDCLI5__URG_HIGH__SHIFT 0x4
+#define DAGB5_RDCLI5__URG_LOW__SHIFT 0x8
+#define DAGB5_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB5_RDCLI5__MAX_BW__SHIFT 0xd
+#define DAGB5_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB5_RDCLI5__MIN_BW__SHIFT 0x16
+#define DAGB5_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB5_RDCLI5__MAX_OSD__SHIFT 0x1a
+#define DAGB5_RDCLI5__VIRT_CHAN_MASK 0x00000007L
+#define DAGB5_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB5_RDCLI5__URG_HIGH_MASK 0x000000F0L
+#define DAGB5_RDCLI5__URG_LOW_MASK 0x00000F00L
+#define DAGB5_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB5_RDCLI5__MAX_BW_MASK 0x001FE000L
+#define DAGB5_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB5_RDCLI5__MIN_BW_MASK 0x01C00000L
+#define DAGB5_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB5_RDCLI5__MAX_OSD_MASK 0xFC000000L
+//DAGB5_RDCLI6
+#define DAGB5_RDCLI6__VIRT_CHAN__SHIFT 0x0
+#define DAGB5_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB5_RDCLI6__URG_HIGH__SHIFT 0x4
+#define DAGB5_RDCLI6__URG_LOW__SHIFT 0x8
+#define DAGB5_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB5_RDCLI6__MAX_BW__SHIFT 0xd
+#define DAGB5_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB5_RDCLI6__MIN_BW__SHIFT 0x16
+#define DAGB5_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB5_RDCLI6__MAX_OSD__SHIFT 0x1a
+#define DAGB5_RDCLI6__VIRT_CHAN_MASK 0x00000007L
+#define DAGB5_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB5_RDCLI6__URG_HIGH_MASK 0x000000F0L
+#define DAGB5_RDCLI6__URG_LOW_MASK 0x00000F00L
+#define DAGB5_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB5_RDCLI6__MAX_BW_MASK 0x001FE000L
+#define DAGB5_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB5_RDCLI6__MIN_BW_MASK 0x01C00000L
+#define DAGB5_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB5_RDCLI6__MAX_OSD_MASK 0xFC000000L
+//DAGB5_RDCLI7
+#define DAGB5_RDCLI7__VIRT_CHAN__SHIFT 0x0
+#define DAGB5_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB5_RDCLI7__URG_HIGH__SHIFT 0x4
+#define DAGB5_RDCLI7__URG_LOW__SHIFT 0x8
+#define DAGB5_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB5_RDCLI7__MAX_BW__SHIFT 0xd
+#define DAGB5_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB5_RDCLI7__MIN_BW__SHIFT 0x16
+#define DAGB5_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB5_RDCLI7__MAX_OSD__SHIFT 0x1a
+#define DAGB5_RDCLI7__VIRT_CHAN_MASK 0x00000007L
+#define DAGB5_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB5_RDCLI7__URG_HIGH_MASK 0x000000F0L
+#define DAGB5_RDCLI7__URG_LOW_MASK 0x00000F00L
+#define DAGB5_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB5_RDCLI7__MAX_BW_MASK 0x001FE000L
+#define DAGB5_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB5_RDCLI7__MIN_BW_MASK 0x01C00000L
+#define DAGB5_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB5_RDCLI7__MAX_OSD_MASK 0xFC000000L
+//DAGB5_RDCLI8
+#define DAGB5_RDCLI8__VIRT_CHAN__SHIFT 0x0
+#define DAGB5_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB5_RDCLI8__URG_HIGH__SHIFT 0x4
+#define DAGB5_RDCLI8__URG_LOW__SHIFT 0x8
+#define DAGB5_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB5_RDCLI8__MAX_BW__SHIFT 0xd
+#define DAGB5_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB5_RDCLI8__MIN_BW__SHIFT 0x16
+#define DAGB5_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB5_RDCLI8__MAX_OSD__SHIFT 0x1a
+#define DAGB5_RDCLI8__VIRT_CHAN_MASK 0x00000007L
+#define DAGB5_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB5_RDCLI8__URG_HIGH_MASK 0x000000F0L
+#define DAGB5_RDCLI8__URG_LOW_MASK 0x00000F00L
+#define DAGB5_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB5_RDCLI8__MAX_BW_MASK 0x001FE000L
+#define DAGB5_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB5_RDCLI8__MIN_BW_MASK 0x01C00000L
+#define DAGB5_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB5_RDCLI8__MAX_OSD_MASK 0xFC000000L
+//DAGB5_RDCLI9
+#define DAGB5_RDCLI9__VIRT_CHAN__SHIFT 0x0
+#define DAGB5_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB5_RDCLI9__URG_HIGH__SHIFT 0x4
+#define DAGB5_RDCLI9__URG_LOW__SHIFT 0x8
+#define DAGB5_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB5_RDCLI9__MAX_BW__SHIFT 0xd
+#define DAGB5_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB5_RDCLI9__MIN_BW__SHIFT 0x16
+#define DAGB5_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB5_RDCLI9__MAX_OSD__SHIFT 0x1a
+#define DAGB5_RDCLI9__VIRT_CHAN_MASK 0x00000007L
+#define DAGB5_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB5_RDCLI9__URG_HIGH_MASK 0x000000F0L
+#define DAGB5_RDCLI9__URG_LOW_MASK 0x00000F00L
+#define DAGB5_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB5_RDCLI9__MAX_BW_MASK 0x001FE000L
+#define DAGB5_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB5_RDCLI9__MIN_BW_MASK 0x01C00000L
+#define DAGB5_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB5_RDCLI9__MAX_OSD_MASK 0xFC000000L
+//DAGB5_RDCLI10
+#define DAGB5_RDCLI10__VIRT_CHAN__SHIFT 0x0
+#define DAGB5_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB5_RDCLI10__URG_HIGH__SHIFT 0x4
+#define DAGB5_RDCLI10__URG_LOW__SHIFT 0x8
+#define DAGB5_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB5_RDCLI10__MAX_BW__SHIFT 0xd
+#define DAGB5_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB5_RDCLI10__MIN_BW__SHIFT 0x16
+#define DAGB5_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB5_RDCLI10__MAX_OSD__SHIFT 0x1a
+#define DAGB5_RDCLI10__VIRT_CHAN_MASK 0x00000007L
+#define DAGB5_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB5_RDCLI10__URG_HIGH_MASK 0x000000F0L
+#define DAGB5_RDCLI10__URG_LOW_MASK 0x00000F00L
+#define DAGB5_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB5_RDCLI10__MAX_BW_MASK 0x001FE000L
+#define DAGB5_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB5_RDCLI10__MIN_BW_MASK 0x01C00000L
+#define DAGB5_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB5_RDCLI10__MAX_OSD_MASK 0xFC000000L
+//DAGB5_RDCLI11
+#define DAGB5_RDCLI11__VIRT_CHAN__SHIFT 0x0
+#define DAGB5_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB5_RDCLI11__URG_HIGH__SHIFT 0x4
+#define DAGB5_RDCLI11__URG_LOW__SHIFT 0x8
+#define DAGB5_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB5_RDCLI11__MAX_BW__SHIFT 0xd
+#define DAGB5_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB5_RDCLI11__MIN_BW__SHIFT 0x16
+#define DAGB5_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB5_RDCLI11__MAX_OSD__SHIFT 0x1a
+#define DAGB5_RDCLI11__VIRT_CHAN_MASK 0x00000007L
+#define DAGB5_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB5_RDCLI11__URG_HIGH_MASK 0x000000F0L
+#define DAGB5_RDCLI11__URG_LOW_MASK 0x00000F00L
+#define DAGB5_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB5_RDCLI11__MAX_BW_MASK 0x001FE000L
+#define DAGB5_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB5_RDCLI11__MIN_BW_MASK 0x01C00000L
+#define DAGB5_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB5_RDCLI11__MAX_OSD_MASK 0xFC000000L
+//DAGB5_RDCLI12
+#define DAGB5_RDCLI12__VIRT_CHAN__SHIFT 0x0
+#define DAGB5_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB5_RDCLI12__URG_HIGH__SHIFT 0x4
+#define DAGB5_RDCLI12__URG_LOW__SHIFT 0x8
+#define DAGB5_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB5_RDCLI12__MAX_BW__SHIFT 0xd
+#define DAGB5_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB5_RDCLI12__MIN_BW__SHIFT 0x16
+#define DAGB5_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB5_RDCLI12__MAX_OSD__SHIFT 0x1a
+#define DAGB5_RDCLI12__VIRT_CHAN_MASK 0x00000007L
+#define DAGB5_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB5_RDCLI12__URG_HIGH_MASK 0x000000F0L
+#define DAGB5_RDCLI12__URG_LOW_MASK 0x00000F00L
+#define DAGB5_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB5_RDCLI12__MAX_BW_MASK 0x001FE000L
+#define DAGB5_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB5_RDCLI12__MIN_BW_MASK 0x01C00000L
+#define DAGB5_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB5_RDCLI12__MAX_OSD_MASK 0xFC000000L
+//DAGB5_RDCLI13
+#define DAGB5_RDCLI13__VIRT_CHAN__SHIFT 0x0
+#define DAGB5_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB5_RDCLI13__URG_HIGH__SHIFT 0x4
+#define DAGB5_RDCLI13__URG_LOW__SHIFT 0x8
+#define DAGB5_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB5_RDCLI13__MAX_BW__SHIFT 0xd
+#define DAGB5_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB5_RDCLI13__MIN_BW__SHIFT 0x16
+#define DAGB5_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB5_RDCLI13__MAX_OSD__SHIFT 0x1a
+#define DAGB5_RDCLI13__VIRT_CHAN_MASK 0x00000007L
+#define DAGB5_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB5_RDCLI13__URG_HIGH_MASK 0x000000F0L
+#define DAGB5_RDCLI13__URG_LOW_MASK 0x00000F00L
+#define DAGB5_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB5_RDCLI13__MAX_BW_MASK 0x001FE000L
+#define DAGB5_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB5_RDCLI13__MIN_BW_MASK 0x01C00000L
+#define DAGB5_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB5_RDCLI13__MAX_OSD_MASK 0xFC000000L
+//DAGB5_RDCLI14
+#define DAGB5_RDCLI14__VIRT_CHAN__SHIFT 0x0
+#define DAGB5_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB5_RDCLI14__URG_HIGH__SHIFT 0x4
+#define DAGB5_RDCLI14__URG_LOW__SHIFT 0x8
+#define DAGB5_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB5_RDCLI14__MAX_BW__SHIFT 0xd
+#define DAGB5_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB5_RDCLI14__MIN_BW__SHIFT 0x16
+#define DAGB5_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB5_RDCLI14__MAX_OSD__SHIFT 0x1a
+#define DAGB5_RDCLI14__VIRT_CHAN_MASK 0x00000007L
+#define DAGB5_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB5_RDCLI14__URG_HIGH_MASK 0x000000F0L
+#define DAGB5_RDCLI14__URG_LOW_MASK 0x00000F00L
+#define DAGB5_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB5_RDCLI14__MAX_BW_MASK 0x001FE000L
+#define DAGB5_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB5_RDCLI14__MIN_BW_MASK 0x01C00000L
+#define DAGB5_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB5_RDCLI14__MAX_OSD_MASK 0xFC000000L
+//DAGB5_RDCLI15
+#define DAGB5_RDCLI15__VIRT_CHAN__SHIFT 0x0
+#define DAGB5_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB5_RDCLI15__URG_HIGH__SHIFT 0x4
+#define DAGB5_RDCLI15__URG_LOW__SHIFT 0x8
+#define DAGB5_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB5_RDCLI15__MAX_BW__SHIFT 0xd
+#define DAGB5_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB5_RDCLI15__MIN_BW__SHIFT 0x16
+#define DAGB5_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB5_RDCLI15__MAX_OSD__SHIFT 0x1a
+#define DAGB5_RDCLI15__VIRT_CHAN_MASK 0x00000007L
+#define DAGB5_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB5_RDCLI15__URG_HIGH_MASK 0x000000F0L
+#define DAGB5_RDCLI15__URG_LOW_MASK 0x00000F00L
+#define DAGB5_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB5_RDCLI15__MAX_BW_MASK 0x001FE000L
+#define DAGB5_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB5_RDCLI15__MIN_BW_MASK 0x01C00000L
+#define DAGB5_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB5_RDCLI15__MAX_OSD_MASK 0xFC000000L
+//DAGB5_RD_CNTL
+#define DAGB5_RD_CNTL__SCLK_FREQ__SHIFT 0x0
+#define DAGB5_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4
+#define DAGB5_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
+#define DAGB5_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
+#define DAGB5_RD_CNTL__IO_LEVEL__SHIFT 0x11
+#define DAGB5_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14
+#define DAGB5_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17
+#define DAGB5_RD_CNTL__FIX_JUMP__SHIFT 0x1a
+#define DAGB5_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL
+#define DAGB5_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L
+#define DAGB5_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L
+#define DAGB5_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L
+#define DAGB5_RD_CNTL__IO_LEVEL_MASK 0x000E0000L
+#define DAGB5_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L
+#define DAGB5_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L
+#define DAGB5_RD_CNTL__FIX_JUMP_MASK 0x04000000L
+//DAGB5_RD_GMI_CNTL
+#define DAGB5_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0
+#define DAGB5_RD_GMI_CNTL__LEVEL__SHIFT 0x6
+#define DAGB5_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9
+#define DAGB5_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd
+#define DAGB5_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL
+#define DAGB5_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L
+#define DAGB5_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L
+#define DAGB5_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L
+//DAGB5_RD_ADDR_DAGB
+#define DAGB5_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0
+#define DAGB5_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
+#define DAGB5_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
+#define DAGB5_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7
+#define DAGB5_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd
+#define DAGB5_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L
+#define DAGB5_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
+#define DAGB5_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
+#define DAGB5_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L
+#define DAGB5_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L
+//DAGB5_RD_OUTPUT_DAGB_MAX_BURST
+#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0
+#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4
+#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8
+#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc
+#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
+#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14
+#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18
+#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c
+#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL
+#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L
+#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L
+#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L
+#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L
+#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L
+#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L
+#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L
+//DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER
+#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0
+#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4
+#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8
+#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc
+#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
+#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14
+#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18
+#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c
+#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL
+#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L
+#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L
+#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L
+#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L
+#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L
+#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L
+#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L
+//DAGB5_RD_CGTT_CLK_CTRL
+#define DAGB5_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB5_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB5_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB5_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB5_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB5_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB5_L1TLB_RD_CGTT_CLK_CTRL
+#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB5_ATCVM_RD_CGTT_CLK_CTRL
+#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB5_RD_ADDR_DAGB_MAX_BURST0
+#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
+#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
+#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
+#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
+#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
+#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
+#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
+#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
+#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
+#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
+#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
+#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
+#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
+#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
+#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
+#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
+//DAGB5_RD_ADDR_DAGB_LAZY_TIMER0
+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
+//DAGB5_RD_ADDR_DAGB_MAX_BURST1
+#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
+#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
+#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
+#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
+#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
+#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
+#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
+#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
+#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
+#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
+#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
+#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
+#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
+#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
+#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
+#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
+//DAGB5_RD_ADDR_DAGB_LAZY_TIMER1
+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
+//DAGB5_RD_VC0_CNTL
+#define DAGB5_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB5_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB5_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB5_RD_VC0_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB5_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB5_RD_VC0_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB5_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB5_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB5_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB5_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB5_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB5_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB5_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB5_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB5_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB5_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB5_RD_VC1_CNTL
+#define DAGB5_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB5_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB5_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB5_RD_VC1_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB5_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB5_RD_VC1_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB5_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB5_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB5_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB5_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB5_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB5_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB5_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB5_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB5_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB5_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB5_RD_VC2_CNTL
+#define DAGB5_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB5_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB5_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB5_RD_VC2_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB5_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB5_RD_VC2_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB5_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB5_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB5_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB5_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB5_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB5_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB5_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB5_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB5_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB5_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB5_RD_VC3_CNTL
+#define DAGB5_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB5_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB5_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB5_RD_VC3_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB5_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB5_RD_VC3_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB5_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB5_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB5_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB5_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB5_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB5_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB5_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB5_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB5_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB5_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB5_RD_VC4_CNTL
+#define DAGB5_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB5_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB5_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB5_RD_VC4_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB5_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB5_RD_VC4_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB5_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB5_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB5_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB5_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB5_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB5_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB5_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB5_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB5_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB5_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB5_RD_VC5_CNTL
+#define DAGB5_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB5_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB5_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB5_RD_VC5_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB5_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB5_RD_VC5_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB5_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB5_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB5_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB5_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB5_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB5_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB5_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB5_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB5_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB5_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB5_RD_VC6_CNTL
+#define DAGB5_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB5_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB5_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB5_RD_VC6_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB5_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB5_RD_VC6_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB5_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB5_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB5_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB5_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB5_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB5_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB5_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB5_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB5_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB5_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB5_RD_VC7_CNTL
+#define DAGB5_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB5_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB5_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB5_RD_VC7_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB5_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB5_RD_VC7_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB5_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB5_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB5_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB5_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB5_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB5_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB5_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB5_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB5_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB5_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB5_RD_CNTL_MISC
+#define DAGB5_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0
+#define DAGB5_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6
+#define DAGB5_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd
+#define DAGB5_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13
+#define DAGB5_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14
+#define DAGB5_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15
+#define DAGB5_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a
+#define DAGB5_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL
+#define DAGB5_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L
+#define DAGB5_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L
+#define DAGB5_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L
+#define DAGB5_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L
+#define DAGB5_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L
+#define DAGB5_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L
+//DAGB5_RD_TLB_CREDIT
+#define DAGB5_RD_TLB_CREDIT__TLB0__SHIFT 0x0
+#define DAGB5_RD_TLB_CREDIT__TLB1__SHIFT 0x5
+#define DAGB5_RD_TLB_CREDIT__TLB2__SHIFT 0xa
+#define DAGB5_RD_TLB_CREDIT__TLB3__SHIFT 0xf
+#define DAGB5_RD_TLB_CREDIT__TLB4__SHIFT 0x14
+#define DAGB5_RD_TLB_CREDIT__TLB5__SHIFT 0x19
+#define DAGB5_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL
+#define DAGB5_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L
+#define DAGB5_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L
+#define DAGB5_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L
+#define DAGB5_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L
+#define DAGB5_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L
+//DAGB5_RD_RDRET_CREDIT_CNTL
+#define DAGB5_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT 0x0
+#define DAGB5_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT 0x6
+#define DAGB5_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT 0xc
+#define DAGB5_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT 0x12
+#define DAGB5_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT 0x18
+#define DAGB5_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT 0x1e
+#define DAGB5_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT 0x1f
+#define DAGB5_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK 0x0000003FL
+#define DAGB5_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK 0x00000FC0L
+#define DAGB5_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK 0x0003F000L
+#define DAGB5_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK 0x00FC0000L
+#define DAGB5_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK 0x3F000000L
+#define DAGB5_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK 0x40000000L
+#define DAGB5_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK 0x80000000L
+//DAGB5_RD_RDRET_CREDIT_CNTL2
+#define DAGB5_RD_RDRET_CREDIT_CNTL2__IO_CREDIT__SHIFT 0x0
+#define DAGB5_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT__SHIFT 0x6
+#define DAGB5_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT 0xc
+#define DAGB5_RD_RDRET_CREDIT_CNTL2__IO_CREDIT_MASK 0x0000003FL
+#define DAGB5_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT_MASK 0x00000FC0L
+#define DAGB5_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK 0x0007F000L
+//DAGB5_RDCLI_ASK_PENDING
+#define DAGB5_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0
+#define DAGB5_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB5_RDCLI_GO_PENDING
+#define DAGB5_RDCLI_GO_PENDING__BUSY__SHIFT 0x0
+#define DAGB5_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB5_RDCLI_GBLSEND_PENDING
+#define DAGB5_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0
+#define DAGB5_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB5_RDCLI_TLB_PENDING
+#define DAGB5_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0
+#define DAGB5_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB5_RDCLI_OARB_PENDING
+#define DAGB5_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0
+#define DAGB5_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB5_RDCLI_OSD_PENDING
+#define DAGB5_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0
+#define DAGB5_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB5_WRCLI0
+#define DAGB5_WRCLI0__VIRT_CHAN__SHIFT 0x0
+#define DAGB5_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB5_WRCLI0__URG_HIGH__SHIFT 0x4
+#define DAGB5_WRCLI0__URG_LOW__SHIFT 0x8
+#define DAGB5_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB5_WRCLI0__MAX_BW__SHIFT 0xd
+#define DAGB5_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB5_WRCLI0__MIN_BW__SHIFT 0x16
+#define DAGB5_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB5_WRCLI0__MAX_OSD__SHIFT 0x1a
+#define DAGB5_WRCLI0__VIRT_CHAN_MASK 0x00000007L
+#define DAGB5_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB5_WRCLI0__URG_HIGH_MASK 0x000000F0L
+#define DAGB5_WRCLI0__URG_LOW_MASK 0x00000F00L
+#define DAGB5_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB5_WRCLI0__MAX_BW_MASK 0x001FE000L
+#define DAGB5_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB5_WRCLI0__MIN_BW_MASK 0x01C00000L
+#define DAGB5_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB5_WRCLI0__MAX_OSD_MASK 0xFC000000L
+//DAGB5_WRCLI1
+#define DAGB5_WRCLI1__VIRT_CHAN__SHIFT 0x0
+#define DAGB5_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB5_WRCLI1__URG_HIGH__SHIFT 0x4
+#define DAGB5_WRCLI1__URG_LOW__SHIFT 0x8
+#define DAGB5_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB5_WRCLI1__MAX_BW__SHIFT 0xd
+#define DAGB5_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB5_WRCLI1__MIN_BW__SHIFT 0x16
+#define DAGB5_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB5_WRCLI1__MAX_OSD__SHIFT 0x1a
+#define DAGB5_WRCLI1__VIRT_CHAN_MASK 0x00000007L
+#define DAGB5_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB5_WRCLI1__URG_HIGH_MASK 0x000000F0L
+#define DAGB5_WRCLI1__URG_LOW_MASK 0x00000F00L
+#define DAGB5_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB5_WRCLI1__MAX_BW_MASK 0x001FE000L
+#define DAGB5_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB5_WRCLI1__MIN_BW_MASK 0x01C00000L
+#define DAGB5_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB5_WRCLI1__MAX_OSD_MASK 0xFC000000L
+//DAGB5_WRCLI2
+#define DAGB5_WRCLI2__VIRT_CHAN__SHIFT 0x0
+#define DAGB5_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB5_WRCLI2__URG_HIGH__SHIFT 0x4
+#define DAGB5_WRCLI2__URG_LOW__SHIFT 0x8
+#define DAGB5_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB5_WRCLI2__MAX_BW__SHIFT 0xd
+#define DAGB5_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB5_WRCLI2__MIN_BW__SHIFT 0x16
+#define DAGB5_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB5_WRCLI2__MAX_OSD__SHIFT 0x1a
+#define DAGB5_WRCLI2__VIRT_CHAN_MASK 0x00000007L
+#define DAGB5_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB5_WRCLI2__URG_HIGH_MASK 0x000000F0L
+#define DAGB5_WRCLI2__URG_LOW_MASK 0x00000F00L
+#define DAGB5_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB5_WRCLI2__MAX_BW_MASK 0x001FE000L
+#define DAGB5_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB5_WRCLI2__MIN_BW_MASK 0x01C00000L
+#define DAGB5_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB5_WRCLI2__MAX_OSD_MASK 0xFC000000L
+//DAGB5_WRCLI3
+#define DAGB5_WRCLI3__VIRT_CHAN__SHIFT 0x0
+#define DAGB5_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB5_WRCLI3__URG_HIGH__SHIFT 0x4
+#define DAGB5_WRCLI3__URG_LOW__SHIFT 0x8
+#define DAGB5_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB5_WRCLI3__MAX_BW__SHIFT 0xd
+#define DAGB5_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB5_WRCLI3__MIN_BW__SHIFT 0x16
+#define DAGB5_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB5_WRCLI3__MAX_OSD__SHIFT 0x1a
+#define DAGB5_WRCLI3__VIRT_CHAN_MASK 0x00000007L
+#define DAGB5_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB5_WRCLI3__URG_HIGH_MASK 0x000000F0L
+#define DAGB5_WRCLI3__URG_LOW_MASK 0x00000F00L
+#define DAGB5_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB5_WRCLI3__MAX_BW_MASK 0x001FE000L
+#define DAGB5_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB5_WRCLI3__MIN_BW_MASK 0x01C00000L
+#define DAGB5_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB5_WRCLI3__MAX_OSD_MASK 0xFC000000L
+//DAGB5_WRCLI4
+#define DAGB5_WRCLI4__VIRT_CHAN__SHIFT 0x0
+#define DAGB5_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB5_WRCLI4__URG_HIGH__SHIFT 0x4
+#define DAGB5_WRCLI4__URG_LOW__SHIFT 0x8
+#define DAGB5_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB5_WRCLI4__MAX_BW__SHIFT 0xd
+#define DAGB5_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB5_WRCLI4__MIN_BW__SHIFT 0x16
+#define DAGB5_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB5_WRCLI4__MAX_OSD__SHIFT 0x1a
+#define DAGB5_WRCLI4__VIRT_CHAN_MASK 0x00000007L
+#define DAGB5_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB5_WRCLI4__URG_HIGH_MASK 0x000000F0L
+#define DAGB5_WRCLI4__URG_LOW_MASK 0x00000F00L
+#define DAGB5_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB5_WRCLI4__MAX_BW_MASK 0x001FE000L
+#define DAGB5_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB5_WRCLI4__MIN_BW_MASK 0x01C00000L
+#define DAGB5_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB5_WRCLI4__MAX_OSD_MASK 0xFC000000L
+//DAGB5_WRCLI5
+#define DAGB5_WRCLI5__VIRT_CHAN__SHIFT 0x0
+#define DAGB5_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB5_WRCLI5__URG_HIGH__SHIFT 0x4
+#define DAGB5_WRCLI5__URG_LOW__SHIFT 0x8
+#define DAGB5_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB5_WRCLI5__MAX_BW__SHIFT 0xd
+#define DAGB5_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB5_WRCLI5__MIN_BW__SHIFT 0x16
+#define DAGB5_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB5_WRCLI5__MAX_OSD__SHIFT 0x1a
+#define DAGB5_WRCLI5__VIRT_CHAN_MASK 0x00000007L
+#define DAGB5_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB5_WRCLI5__URG_HIGH_MASK 0x000000F0L
+#define DAGB5_WRCLI5__URG_LOW_MASK 0x00000F00L
+#define DAGB5_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB5_WRCLI5__MAX_BW_MASK 0x001FE000L
+#define DAGB5_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB5_WRCLI5__MIN_BW_MASK 0x01C00000L
+#define DAGB5_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB5_WRCLI5__MAX_OSD_MASK 0xFC000000L
+//DAGB5_WRCLI6
+#define DAGB5_WRCLI6__VIRT_CHAN__SHIFT 0x0
+#define DAGB5_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB5_WRCLI6__URG_HIGH__SHIFT 0x4
+#define DAGB5_WRCLI6__URG_LOW__SHIFT 0x8
+#define DAGB5_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB5_WRCLI6__MAX_BW__SHIFT 0xd
+#define DAGB5_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB5_WRCLI6__MIN_BW__SHIFT 0x16
+#define DAGB5_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB5_WRCLI6__MAX_OSD__SHIFT 0x1a
+#define DAGB5_WRCLI6__VIRT_CHAN_MASK 0x00000007L
+#define DAGB5_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB5_WRCLI6__URG_HIGH_MASK 0x000000F0L
+#define DAGB5_WRCLI6__URG_LOW_MASK 0x00000F00L
+#define DAGB5_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB5_WRCLI6__MAX_BW_MASK 0x001FE000L
+#define DAGB5_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB5_WRCLI6__MIN_BW_MASK 0x01C00000L
+#define DAGB5_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB5_WRCLI6__MAX_OSD_MASK 0xFC000000L
+//DAGB5_WRCLI7
+#define DAGB5_WRCLI7__VIRT_CHAN__SHIFT 0x0
+#define DAGB5_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB5_WRCLI7__URG_HIGH__SHIFT 0x4
+#define DAGB5_WRCLI7__URG_LOW__SHIFT 0x8
+#define DAGB5_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB5_WRCLI7__MAX_BW__SHIFT 0xd
+#define DAGB5_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB5_WRCLI7__MIN_BW__SHIFT 0x16
+#define DAGB5_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB5_WRCLI7__MAX_OSD__SHIFT 0x1a
+#define DAGB5_WRCLI7__VIRT_CHAN_MASK 0x00000007L
+#define DAGB5_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB5_WRCLI7__URG_HIGH_MASK 0x000000F0L
+#define DAGB5_WRCLI7__URG_LOW_MASK 0x00000F00L
+#define DAGB5_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB5_WRCLI7__MAX_BW_MASK 0x001FE000L
+#define DAGB5_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB5_WRCLI7__MIN_BW_MASK 0x01C00000L
+#define DAGB5_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB5_WRCLI7__MAX_OSD_MASK 0xFC000000L
+//DAGB5_WRCLI8
+#define DAGB5_WRCLI8__VIRT_CHAN__SHIFT 0x0
+#define DAGB5_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB5_WRCLI8__URG_HIGH__SHIFT 0x4
+#define DAGB5_WRCLI8__URG_LOW__SHIFT 0x8
+#define DAGB5_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB5_WRCLI8__MAX_BW__SHIFT 0xd
+#define DAGB5_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB5_WRCLI8__MIN_BW__SHIFT 0x16
+#define DAGB5_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB5_WRCLI8__MAX_OSD__SHIFT 0x1a
+#define DAGB5_WRCLI8__VIRT_CHAN_MASK 0x00000007L
+#define DAGB5_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB5_WRCLI8__URG_HIGH_MASK 0x000000F0L
+#define DAGB5_WRCLI8__URG_LOW_MASK 0x00000F00L
+#define DAGB5_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB5_WRCLI8__MAX_BW_MASK 0x001FE000L
+#define DAGB5_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB5_WRCLI8__MIN_BW_MASK 0x01C00000L
+#define DAGB5_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB5_WRCLI8__MAX_OSD_MASK 0xFC000000L
+//DAGB5_WRCLI9
+#define DAGB5_WRCLI9__VIRT_CHAN__SHIFT 0x0
+#define DAGB5_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB5_WRCLI9__URG_HIGH__SHIFT 0x4
+#define DAGB5_WRCLI9__URG_LOW__SHIFT 0x8
+#define DAGB5_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB5_WRCLI9__MAX_BW__SHIFT 0xd
+#define DAGB5_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB5_WRCLI9__MIN_BW__SHIFT 0x16
+#define DAGB5_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB5_WRCLI9__MAX_OSD__SHIFT 0x1a
+#define DAGB5_WRCLI9__VIRT_CHAN_MASK 0x00000007L
+#define DAGB5_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB5_WRCLI9__URG_HIGH_MASK 0x000000F0L
+#define DAGB5_WRCLI9__URG_LOW_MASK 0x00000F00L
+#define DAGB5_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB5_WRCLI9__MAX_BW_MASK 0x001FE000L
+#define DAGB5_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB5_WRCLI9__MIN_BW_MASK 0x01C00000L
+#define DAGB5_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB5_WRCLI9__MAX_OSD_MASK 0xFC000000L
+//DAGB5_WRCLI10
+#define DAGB5_WRCLI10__VIRT_CHAN__SHIFT 0x0
+#define DAGB5_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB5_WRCLI10__URG_HIGH__SHIFT 0x4
+#define DAGB5_WRCLI10__URG_LOW__SHIFT 0x8
+#define DAGB5_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB5_WRCLI10__MAX_BW__SHIFT 0xd
+#define DAGB5_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB5_WRCLI10__MIN_BW__SHIFT 0x16
+#define DAGB5_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB5_WRCLI10__MAX_OSD__SHIFT 0x1a
+#define DAGB5_WRCLI10__VIRT_CHAN_MASK 0x00000007L
+#define DAGB5_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB5_WRCLI10__URG_HIGH_MASK 0x000000F0L
+#define DAGB5_WRCLI10__URG_LOW_MASK 0x00000F00L
+#define DAGB5_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB5_WRCLI10__MAX_BW_MASK 0x001FE000L
+#define DAGB5_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB5_WRCLI10__MIN_BW_MASK 0x01C00000L
+#define DAGB5_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB5_WRCLI10__MAX_OSD_MASK 0xFC000000L
+//DAGB5_WRCLI11
+#define DAGB5_WRCLI11__VIRT_CHAN__SHIFT 0x0
+#define DAGB5_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB5_WRCLI11__URG_HIGH__SHIFT 0x4
+#define DAGB5_WRCLI11__URG_LOW__SHIFT 0x8
+#define DAGB5_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB5_WRCLI11__MAX_BW__SHIFT 0xd
+#define DAGB5_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB5_WRCLI11__MIN_BW__SHIFT 0x16
+#define DAGB5_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB5_WRCLI11__MAX_OSD__SHIFT 0x1a
+#define DAGB5_WRCLI11__VIRT_CHAN_MASK 0x00000007L
+#define DAGB5_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB5_WRCLI11__URG_HIGH_MASK 0x000000F0L
+#define DAGB5_WRCLI11__URG_LOW_MASK 0x00000F00L
+#define DAGB5_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB5_WRCLI11__MAX_BW_MASK 0x001FE000L
+#define DAGB5_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB5_WRCLI11__MIN_BW_MASK 0x01C00000L
+#define DAGB5_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB5_WRCLI11__MAX_OSD_MASK 0xFC000000L
+//DAGB5_WRCLI12
+#define DAGB5_WRCLI12__VIRT_CHAN__SHIFT 0x0
+#define DAGB5_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB5_WRCLI12__URG_HIGH__SHIFT 0x4
+#define DAGB5_WRCLI12__URG_LOW__SHIFT 0x8
+#define DAGB5_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB5_WRCLI12__MAX_BW__SHIFT 0xd
+#define DAGB5_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB5_WRCLI12__MIN_BW__SHIFT 0x16
+#define DAGB5_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB5_WRCLI12__MAX_OSD__SHIFT 0x1a
+#define DAGB5_WRCLI12__VIRT_CHAN_MASK 0x00000007L
+#define DAGB5_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB5_WRCLI12__URG_HIGH_MASK 0x000000F0L
+#define DAGB5_WRCLI12__URG_LOW_MASK 0x00000F00L
+#define DAGB5_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB5_WRCLI12__MAX_BW_MASK 0x001FE000L
+#define DAGB5_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB5_WRCLI12__MIN_BW_MASK 0x01C00000L
+#define DAGB5_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB5_WRCLI12__MAX_OSD_MASK 0xFC000000L
+//DAGB5_WRCLI13
+#define DAGB5_WRCLI13__VIRT_CHAN__SHIFT 0x0
+#define DAGB5_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB5_WRCLI13__URG_HIGH__SHIFT 0x4
+#define DAGB5_WRCLI13__URG_LOW__SHIFT 0x8
+#define DAGB5_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB5_WRCLI13__MAX_BW__SHIFT 0xd
+#define DAGB5_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB5_WRCLI13__MIN_BW__SHIFT 0x16
+#define DAGB5_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB5_WRCLI13__MAX_OSD__SHIFT 0x1a
+#define DAGB5_WRCLI13__VIRT_CHAN_MASK 0x00000007L
+#define DAGB5_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB5_WRCLI13__URG_HIGH_MASK 0x000000F0L
+#define DAGB5_WRCLI13__URG_LOW_MASK 0x00000F00L
+#define DAGB5_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB5_WRCLI13__MAX_BW_MASK 0x001FE000L
+#define DAGB5_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB5_WRCLI13__MIN_BW_MASK 0x01C00000L
+#define DAGB5_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB5_WRCLI13__MAX_OSD_MASK 0xFC000000L
+//DAGB5_WRCLI14
+#define DAGB5_WRCLI14__VIRT_CHAN__SHIFT 0x0
+#define DAGB5_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB5_WRCLI14__URG_HIGH__SHIFT 0x4
+#define DAGB5_WRCLI14__URG_LOW__SHIFT 0x8
+#define DAGB5_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB5_WRCLI14__MAX_BW__SHIFT 0xd
+#define DAGB5_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB5_WRCLI14__MIN_BW__SHIFT 0x16
+#define DAGB5_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB5_WRCLI14__MAX_OSD__SHIFT 0x1a
+#define DAGB5_WRCLI14__VIRT_CHAN_MASK 0x00000007L
+#define DAGB5_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB5_WRCLI14__URG_HIGH_MASK 0x000000F0L
+#define DAGB5_WRCLI14__URG_LOW_MASK 0x00000F00L
+#define DAGB5_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB5_WRCLI14__MAX_BW_MASK 0x001FE000L
+#define DAGB5_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB5_WRCLI14__MIN_BW_MASK 0x01C00000L
+#define DAGB5_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB5_WRCLI14__MAX_OSD_MASK 0xFC000000L
+//DAGB5_WRCLI15
+#define DAGB5_WRCLI15__VIRT_CHAN__SHIFT 0x0
+#define DAGB5_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB5_WRCLI15__URG_HIGH__SHIFT 0x4
+#define DAGB5_WRCLI15__URG_LOW__SHIFT 0x8
+#define DAGB5_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB5_WRCLI15__MAX_BW__SHIFT 0xd
+#define DAGB5_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB5_WRCLI15__MIN_BW__SHIFT 0x16
+#define DAGB5_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB5_WRCLI15__MAX_OSD__SHIFT 0x1a
+#define DAGB5_WRCLI15__VIRT_CHAN_MASK 0x00000007L
+#define DAGB5_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB5_WRCLI15__URG_HIGH_MASK 0x000000F0L
+#define DAGB5_WRCLI15__URG_LOW_MASK 0x00000F00L
+#define DAGB5_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB5_WRCLI15__MAX_BW_MASK 0x001FE000L
+#define DAGB5_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB5_WRCLI15__MIN_BW_MASK 0x01C00000L
+#define DAGB5_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB5_WRCLI15__MAX_OSD_MASK 0xFC000000L
+//DAGB5_WR_CNTL
+#define DAGB5_WR_CNTL__SCLK_FREQ__SHIFT 0x0
+#define DAGB5_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4
+#define DAGB5_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
+#define DAGB5_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
+#define DAGB5_WR_CNTL__IO_LEVEL__SHIFT 0x11
+#define DAGB5_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14
+#define DAGB5_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17
+#define DAGB5_WR_CNTL__FIX_JUMP__SHIFT 0x1a
+#define DAGB5_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL
+#define DAGB5_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L
+#define DAGB5_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L
+#define DAGB5_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L
+#define DAGB5_WR_CNTL__IO_LEVEL_MASK 0x000E0000L
+#define DAGB5_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L
+#define DAGB5_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L
+#define DAGB5_WR_CNTL__FIX_JUMP_MASK 0x04000000L
+//DAGB5_WR_GMI_CNTL
+#define DAGB5_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0
+#define DAGB5_WR_GMI_CNTL__LEVEL__SHIFT 0x6
+#define DAGB5_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9
+#define DAGB5_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd
+#define DAGB5_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL
+#define DAGB5_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L
+#define DAGB5_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L
+#define DAGB5_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L
+//DAGB5_WR_ADDR_DAGB
+#define DAGB5_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0
+#define DAGB5_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
+#define DAGB5_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
+#define DAGB5_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7
+#define DAGB5_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xd
+#define DAGB5_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L
+#define DAGB5_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
+#define DAGB5_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
+#define DAGB5_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L
+#define DAGB5_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L
+//DAGB5_WR_OUTPUT_DAGB_MAX_BURST
+#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0
+#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4
+#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8
+#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc
+#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
+#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14
+#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18
+#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c
+#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL
+#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L
+#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L
+#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L
+#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L
+#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L
+#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L
+#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L
+//DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER
+#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0
+#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4
+#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8
+#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc
+#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
+#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14
+#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18
+#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c
+#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL
+#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L
+#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L
+#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L
+#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L
+#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L
+#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L
+#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L
+//DAGB5_WR_CGTT_CLK_CTRL
+#define DAGB5_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB5_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB5_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB5_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB5_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB5_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB5_L1TLB_WR_CGTT_CLK_CTRL
+#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB5_ATCVM_WR_CGTT_CLK_CTRL
+#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB5_WR_ADDR_DAGB_MAX_BURST0
+#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
+#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
+#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
+#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
+#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
+#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
+#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
+#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
+#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
+#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
+#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
+#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
+#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
+#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
+#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
+#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
+//DAGB5_WR_ADDR_DAGB_LAZY_TIMER0
+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
+//DAGB5_WR_ADDR_DAGB_MAX_BURST1
+#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
+#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
+#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
+#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
+#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
+#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
+#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
+#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
+#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
+#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
+#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
+#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
+#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
+#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
+#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
+#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
+//DAGB5_WR_ADDR_DAGB_LAZY_TIMER1
+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
+//DAGB5_WR_DATA_DAGB
+#define DAGB5_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0
+#define DAGB5_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
+#define DAGB5_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
+#define DAGB5_WR_DATA_DAGB__WHOAMI__SHIFT 0x7
+#define DAGB5_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L
+#define DAGB5_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
+#define DAGB5_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
+#define DAGB5_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L
+//DAGB5_WR_DATA_DAGB_MAX_BURST0
+#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
+#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
+#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
+#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
+#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
+#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
+#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
+#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
+#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
+#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
+#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
+#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
+#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
+#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
+#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
+#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
+//DAGB5_WR_DATA_DAGB_LAZY_TIMER0
+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
+//DAGB5_WR_DATA_DAGB_MAX_BURST1
+#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
+#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
+#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
+#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
+#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
+#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
+#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
+#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
+#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
+#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
+#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
+#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
+#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
+#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
+#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
+#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
+//DAGB5_WR_DATA_DAGB_LAZY_TIMER1
+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
+//DAGB5_WR_VC0_CNTL
+#define DAGB5_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB5_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB5_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB5_WR_VC0_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB5_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB5_WR_VC0_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB5_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB5_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB5_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB5_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB5_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB5_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB5_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB5_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB5_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB5_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB5_WR_VC1_CNTL
+#define DAGB5_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB5_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB5_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB5_WR_VC1_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB5_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB5_WR_VC1_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB5_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB5_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB5_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB5_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB5_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB5_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB5_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB5_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB5_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB5_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB5_WR_VC2_CNTL
+#define DAGB5_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB5_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB5_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB5_WR_VC2_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB5_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB5_WR_VC2_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB5_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB5_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB5_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB5_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB5_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB5_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB5_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB5_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB5_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB5_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB5_WR_VC3_CNTL
+#define DAGB5_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB5_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB5_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB5_WR_VC3_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB5_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB5_WR_VC3_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB5_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB5_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB5_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB5_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB5_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB5_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB5_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB5_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB5_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB5_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB5_WR_VC4_CNTL
+#define DAGB5_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB5_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB5_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB5_WR_VC4_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB5_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB5_WR_VC4_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB5_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB5_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB5_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB5_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB5_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB5_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB5_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB5_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB5_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB5_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB5_WR_VC5_CNTL
+#define DAGB5_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB5_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB5_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB5_WR_VC5_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB5_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB5_WR_VC5_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB5_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB5_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB5_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB5_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB5_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB5_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB5_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB5_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB5_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB5_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB5_WR_VC6_CNTL
+#define DAGB5_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB5_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB5_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB5_WR_VC6_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB5_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB5_WR_VC6_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB5_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB5_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB5_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB5_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB5_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB5_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB5_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB5_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB5_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB5_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB5_WR_VC7_CNTL
+#define DAGB5_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB5_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB5_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB5_WR_VC7_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB5_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB5_WR_VC7_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB5_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB5_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB5_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB5_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB5_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB5_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB5_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB5_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB5_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB5_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB5_WR_CNTL_MISC
+#define DAGB5_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0
+#define DAGB5_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6
+#define DAGB5_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd
+#define DAGB5_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13
+#define DAGB5_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14
+#define DAGB5_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15
+#define DAGB5_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a
+#define DAGB5_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL
+#define DAGB5_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L
+#define DAGB5_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L
+#define DAGB5_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L
+#define DAGB5_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L
+#define DAGB5_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L
+#define DAGB5_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L
+//DAGB5_WR_TLB_CREDIT
+#define DAGB5_WR_TLB_CREDIT__TLB0__SHIFT 0x0
+#define DAGB5_WR_TLB_CREDIT__TLB1__SHIFT 0x5
+#define DAGB5_WR_TLB_CREDIT__TLB2__SHIFT 0xa
+#define DAGB5_WR_TLB_CREDIT__TLB3__SHIFT 0xf
+#define DAGB5_WR_TLB_CREDIT__TLB4__SHIFT 0x14
+#define DAGB5_WR_TLB_CREDIT__TLB5__SHIFT 0x19
+#define DAGB5_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL
+#define DAGB5_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L
+#define DAGB5_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L
+#define DAGB5_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L
+#define DAGB5_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L
+#define DAGB5_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L
+//DAGB5_WR_DATA_CREDIT
+#define DAGB5_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0
+#define DAGB5_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8
+#define DAGB5_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10
+#define DAGB5_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18
+#define DAGB5_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL
+#define DAGB5_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L
+#define DAGB5_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L
+#define DAGB5_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L
+//DAGB5_WR_MISC_CREDIT
+#define DAGB5_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0
+#define DAGB5_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6
+#define DAGB5_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9
+#define DAGB5_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10
+#define DAGB5_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL
+#define DAGB5_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L
+#define DAGB5_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L
+#define DAGB5_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L
+//DAGB5_WR_OSD_CREDIT_CNTL1
+#define DAGB5_WR_OSD_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0
+#define DAGB5_WR_OSD_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x4
+#define DAGB5_WR_OSD_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0x8
+#define DAGB5_WR_OSD_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xc
+#define DAGB5_WR_OSD_CREDIT_CNTL1__IO_CREDIT__SHIFT 0x10
+#define DAGB5_WR_OSD_CREDIT_CNTL1__GMI_CREDIT__SHIFT 0x14
+#define DAGB5_WR_OSD_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x18
+#define DAGB5_WR_OSD_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000000FL
+#define DAGB5_WR_OSD_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000000F0L
+#define DAGB5_WR_OSD_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00000F00L
+#define DAGB5_WR_OSD_CREDIT_CNTL1__VC3_CREDIT_MASK 0x0000F000L
+#define DAGB5_WR_OSD_CREDIT_CNTL1__IO_CREDIT_MASK 0x000F0000L
+#define DAGB5_WR_OSD_CREDIT_CNTL1__GMI_CREDIT_MASK 0x00F00000L
+#define DAGB5_WR_OSD_CREDIT_CNTL1__POOL_CREDIT_MASK 0x3F000000L
+//DAGB5_WR_OSD_CREDIT_CNTL2
+#define DAGB5_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN__SHIFT 0x0
+#define DAGB5_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY__SHIFT 0x4
+#define DAGB5_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN_MASK 0x0000000FL
+#define DAGB5_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY_MASK 0x00000010L
+//DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1
+#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0
+#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5
+#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa
+#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf
+#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14
+#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x19
+#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1a
+#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1b
+#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1__SHIFT 0x1c
+#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2__SHIFT 0x1d
+#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL
+#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L
+#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L
+#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L
+#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x01F00000L
+#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x02000000L
+#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x04000000L
+#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK 0x08000000L
+#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1_MASK 0x10000000L
+#define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2_MASK 0x20000000L
+//DAGB5_WRCLI_GPU_SNOOP_OVERRIDE
+#define DAGB5_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0
+#define DAGB5_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL
+//DAGB5_WRCLI_GPU_SNOOP_OVERRIDE_VALUE
+#define DAGB5_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0
+#define DAGB5_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0xFFFFFFFFL
+//DAGB5_WRCLI_ASK_PENDING
+#define DAGB5_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0
+#define DAGB5_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB5_WRCLI_GO_PENDING
+#define DAGB5_WRCLI_GO_PENDING__BUSY__SHIFT 0x0
+#define DAGB5_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB5_WRCLI_GBLSEND_PENDING
+#define DAGB5_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0
+#define DAGB5_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB5_WRCLI_TLB_PENDING
+#define DAGB5_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0
+#define DAGB5_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB5_WRCLI_OARB_PENDING
+#define DAGB5_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0
+#define DAGB5_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB5_WRCLI_OSD_PENDING
+#define DAGB5_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0
+#define DAGB5_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB5_WRCLI_DBUS_ASK_PENDING
+#define DAGB5_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0
+#define DAGB5_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB5_WRCLI_DBUS_GO_PENDING
+#define DAGB5_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0
+#define DAGB5_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB5_DAGB_DLY
+#define DAGB5_DAGB_DLY__DLY__SHIFT 0x0
+#define DAGB5_DAGB_DLY__CLI__SHIFT 0x8
+#define DAGB5_DAGB_DLY__POS__SHIFT 0x10
+#define DAGB5_DAGB_DLY__DLY_MASK 0x000000FFL
+#define DAGB5_DAGB_DLY__CLI_MASK 0x0000FF00L
+#define DAGB5_DAGB_DLY__POS_MASK 0x000F0000L
+//DAGB5_CNTL_MISC
+#define DAGB5_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0
+#define DAGB5_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3
+#define DAGB5_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6
+#define DAGB5_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9
+#define DAGB5_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc
+#define DAGB5_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf
+#define DAGB5_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12
+#define DAGB5_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15
+#define DAGB5_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18
+#define DAGB5_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e
+#define DAGB5_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L
+#define DAGB5_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L
+#define DAGB5_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L
+#define DAGB5_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L
+#define DAGB5_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L
+#define DAGB5_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L
+#define DAGB5_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L
+#define DAGB5_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L
+#define DAGB5_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L
+#define DAGB5_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L
+//DAGB5_CNTL_MISC2
+#define DAGB5_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0
+#define DAGB5_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1
+#define DAGB5_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2
+#define DAGB5_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3
+#define DAGB5_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4
+#define DAGB5_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5
+#define DAGB5_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6
+#define DAGB5_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7
+#define DAGB5_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8
+#define DAGB5_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9
+#define DAGB5_CNTL_MISC2__SWAP_CTL__SHIFT 0xa
+#define DAGB5_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb
+#define DAGB5_CNTL_MISC2__HDP_CID__SHIFT 0xc
+#define DAGB5_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x11
+#define DAGB5_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L
+#define DAGB5_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L
+#define DAGB5_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L
+#define DAGB5_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L
+#define DAGB5_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L
+#define DAGB5_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L
+#define DAGB5_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L
+#define DAGB5_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L
+#define DAGB5_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L
+#define DAGB5_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L
+#define DAGB5_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L
+#define DAGB5_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L
+#define DAGB5_CNTL_MISC2__HDP_CID_MASK 0x0001F000L
+#define DAGB5_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x007E0000L
+//DAGB5_FATAL_ERROR_CNTL
+#define DAGB5_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT 0x0
+#define DAGB5_FATAL_ERROR_CNTL__FILTER_NUM_MASK 0x000003FFL
+//DAGB5_FATAL_ERROR_CLEAR
+#define DAGB5_FATAL_ERROR_CLEAR__CLEAR__SHIFT 0x0
+#define DAGB5_FATAL_ERROR_CLEAR__CLEAR_MASK 0x00000001L
+//DAGB5_FATAL_ERROR_STATUS0
+#define DAGB5_FATAL_ERROR_STATUS0__VALID__SHIFT 0x0
+#define DAGB5_FATAL_ERROR_STATUS0__CID__SHIFT 0x1
+#define DAGB5_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT 0x6
+#define DAGB5_FATAL_ERROR_STATUS0__VALID_MASK 0x00000001L
+#define DAGB5_FATAL_ERROR_STATUS0__CID_MASK 0x0000003EL
+#define DAGB5_FATAL_ERROR_STATUS0__ADDR_LO_MASK 0xFFFFFFC0L
+//DAGB5_FATAL_ERROR_STATUS1
+#define DAGB5_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT 0x0
+#define DAGB5_FATAL_ERROR_STATUS1__ADDR_HI_MASK 0x0001FFFFL
+//DAGB5_FATAL_ERROR_STATUS2
+#define DAGB5_FATAL_ERROR_STATUS2__TAG__SHIFT 0x0
+#define DAGB5_FATAL_ERROR_STATUS2__VFID__SHIFT 0x10
+#define DAGB5_FATAL_ERROR_STATUS2__VF__SHIFT 0x14
+#define DAGB5_FATAL_ERROR_STATUS2__SPACE__SHIFT 0x15
+#define DAGB5_FATAL_ERROR_STATUS2__IO__SHIFT 0x16
+#define DAGB5_FATAL_ERROR_STATUS2__SIZE__SHIFT 0x17
+#define DAGB5_FATAL_ERROR_STATUS2__FED__SHIFT 0x19
+#define DAGB5_FATAL_ERROR_STATUS2__TAG_MASK 0x0000FFFFL
+#define DAGB5_FATAL_ERROR_STATUS2__VFID_MASK 0x000F0000L
+#define DAGB5_FATAL_ERROR_STATUS2__VF_MASK 0x00100000L
+#define DAGB5_FATAL_ERROR_STATUS2__SPACE_MASK 0x00200000L
+#define DAGB5_FATAL_ERROR_STATUS2__IO_MASK 0x00400000L
+#define DAGB5_FATAL_ERROR_STATUS2__SIZE_MASK 0x00800000L
+#define DAGB5_FATAL_ERROR_STATUS2__FED_MASK 0x02000000L
+//DAGB5_FATAL_ERROR_STATUS3
+#define DAGB5_FATAL_ERROR_STATUS3__OP__SHIFT 0x6
+#define DAGB5_FATAL_ERROR_STATUS3__WRTMZ__SHIFT 0x10
+#define DAGB5_FATAL_ERROR_STATUS3__RDTMZ__SHIFT 0x11
+#define DAGB5_FATAL_ERROR_STATUS3__SNOOP__SHIFT 0x12
+#define DAGB5_FATAL_ERROR_STATUS3__INVAL__SHIFT 0x13
+#define DAGB5_FATAL_ERROR_STATUS3__NACK__SHIFT 0x14
+#define DAGB5_FATAL_ERROR_STATUS3__RO__SHIFT 0x16
+#define DAGB5_FATAL_ERROR_STATUS3__MEMLOG__SHIFT 0x17
+#define DAGB5_FATAL_ERROR_STATUS3__EOP__SHIFT 0x18
+#define DAGB5_FATAL_ERROR_STATUS3__OP_MASK 0x00001FC0L
+#define DAGB5_FATAL_ERROR_STATUS3__WRTMZ_MASK 0x00010000L
+#define DAGB5_FATAL_ERROR_STATUS3__RDTMZ_MASK 0x00020000L
+#define DAGB5_FATAL_ERROR_STATUS3__SNOOP_MASK 0x00040000L
+#define DAGB5_FATAL_ERROR_STATUS3__INVAL_MASK 0x00080000L
+#define DAGB5_FATAL_ERROR_STATUS3__NACK_MASK 0x00300000L
+#define DAGB5_FATAL_ERROR_STATUS3__RO_MASK 0x00400000L
+#define DAGB5_FATAL_ERROR_STATUS3__MEMLOG_MASK 0x00800000L
+#define DAGB5_FATAL_ERROR_STATUS3__EOP_MASK 0x01000000L
+//DAGB5_FIFO_EMPTY
+#define DAGB5_FIFO_EMPTY__EMPTY__SHIFT 0x0
+#define DAGB5_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL
+//DAGB5_FIFO_FULL
+#define DAGB5_FIFO_FULL__FULL__SHIFT 0x0
+#define DAGB5_FIFO_FULL__FULL_MASK 0x007FFFFFL
+//DAGB5_WR_CREDITS_FULL
+#define DAGB5_WR_CREDITS_FULL__FULL__SHIFT 0x0
+#define DAGB5_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL
+//DAGB5_RD_CREDITS_FULL
+#define DAGB5_RD_CREDITS_FULL__FULL__SHIFT 0x0
+#define DAGB5_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL
+//DAGB5_PERFCOUNTER_LO
+#define DAGB5_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define DAGB5_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//DAGB5_PERFCOUNTER_HI
+#define DAGB5_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define DAGB5_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define DAGB5_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define DAGB5_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//DAGB5_PERFCOUNTER0_CFG
+#define DAGB5_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define DAGB5_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define DAGB5_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define DAGB5_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define DAGB5_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define DAGB5_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define DAGB5_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define DAGB5_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define DAGB5_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define DAGB5_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//DAGB5_PERFCOUNTER1_CFG
+#define DAGB5_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define DAGB5_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define DAGB5_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define DAGB5_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define DAGB5_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define DAGB5_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define DAGB5_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define DAGB5_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define DAGB5_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define DAGB5_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//DAGB5_PERFCOUNTER2_CFG
+#define DAGB5_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define DAGB5_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define DAGB5_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define DAGB5_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define DAGB5_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define DAGB5_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
+#define DAGB5_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define DAGB5_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
+#define DAGB5_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
+#define DAGB5_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
+//DAGB5_PERFCOUNTER_RSLT_CNTL
+#define DAGB5_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define DAGB5_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define DAGB5_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define DAGB5_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define DAGB5_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define DAGB5_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define DAGB5_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define DAGB5_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+//DAGB5_L1TLB_REG_RW
+#define DAGB5_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0
+#define DAGB5_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1
+#define DAGB5_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL__SHIFT 0x2
+#define DAGB5_L1TLB_REG_RW__WDAT_PARITY_CHECK__SHIFT 0x4
+#define DAGB5_L1TLB_REG_RW__DISABLE_RDRET_CHECK__SHIFT 0x5
+#define DAGB5_L1TLB_REG_RW__RESERVE__SHIFT 0x6
+#define DAGB5_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L
+#define DAGB5_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L
+#define DAGB5_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL_MASK 0x00000004L
+#define DAGB5_L1TLB_REG_RW__WDAT_PARITY_CHECK_MASK 0x00000010L
+#define DAGB5_L1TLB_REG_RW__DISABLE_RDRET_CHECK_MASK 0x00000020L
+#define DAGB5_L1TLB_REG_RW__RESERVE_MASK 0xFFFFFFC0L
+//DAGB5_RESERVE1
+#define DAGB5_RESERVE1__RESERVE__SHIFT 0x0
+#define DAGB5_RESERVE1__RESERVE_MASK 0xFFFFFFFFL
+//DAGB5_RESERVE2
+#define DAGB5_RESERVE2__RESERVE__SHIFT 0x0
+#define DAGB5_RESERVE2__RESERVE_MASK 0xFFFFFFFFL
+//DAGB5_RESERVE3
+#define DAGB5_RESERVE3__RESERVE__SHIFT 0x0
+#define DAGB5_RESERVE3__RESERVE_MASK 0xFFFFFFFFL
+//DAGB5_RESERVE4
+#define DAGB5_RESERVE4__RESERVE__SHIFT 0x0
+#define DAGB5_RESERVE4__RESERVE_MASK 0xFFFFFFFFL
+
+
+// addressBlock: mmhub_ea_mmeadec0
+//MMEA0_DRAM_RD_CLI2GRP_MAP0
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA0_DRAM_RD_CLI2GRP_MAP1
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA0_DRAM_WR_CLI2GRP_MAP0
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA0_DRAM_WR_CLI2GRP_MAP1
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA0_DRAM_RD_GRP2VC_MAP
+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
+//MMEA0_DRAM_WR_GRP2VC_MAP
+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
+//MMEA0_DRAM_RD_LAZY
+#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0
+#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3
+#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6
+#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9
+#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
+#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
+#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b
+#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L
+#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L
+#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L
+#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L
+#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
+#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
+#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L
+//MMEA0_DRAM_WR_LAZY
+#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0
+#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3
+#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6
+#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9
+#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
+#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
+#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b
+#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L
+#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L
+#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L
+#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L
+#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
+#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
+#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L
+//MMEA0_DRAM_RD_CAM_CNTL
+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
+#define MMEA0_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c
+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
+#define MMEA0_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L
+//MMEA0_DRAM_WR_CAM_CNTL
+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
+#define MMEA0_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c
+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
+#define MMEA0_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L
+//MMEA0_DRAM_PAGE_BURST
+#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0
+#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8
+#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10
+#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18
+#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL
+#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
+#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
+#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L
+//MMEA0_DRAM_RD_PRI_AGE
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA0_DRAM_WR_PRI_AGE
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA0_DRAM_RD_PRI_QUEUING
+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA0_DRAM_WR_PRI_QUEUING
+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA0_DRAM_RD_PRI_FIXED
+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA0_DRAM_WR_PRI_FIXED
+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA0_DRAM_RD_PRI_URGENCY
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA0_DRAM_WR_PRI_URGENCY
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA0_DRAM_RD_PRI_QUANT_PRI1
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_DRAM_RD_PRI_QUANT_PRI2
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_DRAM_RD_PRI_QUANT_PRI3
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_DRAM_WR_PRI_QUANT_PRI1
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_DRAM_WR_PRI_QUANT_PRI2
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_DRAM_WR_PRI_QUANT_PRI3
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_GMI_RD_CLI2GRP_MAP0
+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA0_GMI_RD_CLI2GRP_MAP1
+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA0_GMI_WR_CLI2GRP_MAP0
+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA0_GMI_WR_CLI2GRP_MAP1
+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA0_GMI_RD_GRP2VC_MAP
+#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
+#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
+#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
+#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
+#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
+#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
+#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
+#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
+//MMEA0_GMI_WR_GRP2VC_MAP
+#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
+#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
+#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
+#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
+#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
+#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
+#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
+#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
+//MMEA0_GMI_RD_LAZY
+#define MMEA0_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0
+#define MMEA0_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3
+#define MMEA0_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6
+#define MMEA0_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9
+#define MMEA0_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
+#define MMEA0_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
+#define MMEA0_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b
+#define MMEA0_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L
+#define MMEA0_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L
+#define MMEA0_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L
+#define MMEA0_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L
+#define MMEA0_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
+#define MMEA0_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
+#define MMEA0_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L
+//MMEA0_GMI_WR_LAZY
+#define MMEA0_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0
+#define MMEA0_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3
+#define MMEA0_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6
+#define MMEA0_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9
+#define MMEA0_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
+#define MMEA0_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
+#define MMEA0_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b
+#define MMEA0_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L
+#define MMEA0_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L
+#define MMEA0_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L
+#define MMEA0_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L
+#define MMEA0_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
+#define MMEA0_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
+#define MMEA0_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L
+//MMEA0_GMI_RD_CAM_CNTL
+#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
+#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
+#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
+#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
+#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
+#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
+#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
+#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
+#define MMEA0_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c
+#define MMEA0_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d
+#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
+#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
+#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
+#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
+#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
+#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
+#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
+#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
+#define MMEA0_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L
+#define MMEA0_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L
+//MMEA0_GMI_WR_CAM_CNTL
+#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
+#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
+#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
+#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
+#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
+#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
+#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
+#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
+#define MMEA0_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c
+#define MMEA0_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d
+#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
+#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
+#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
+#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
+#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
+#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
+#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
+#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
+#define MMEA0_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L
+#define MMEA0_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L
+//MMEA0_GMI_PAGE_BURST
+#define MMEA0_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0
+#define MMEA0_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8
+#define MMEA0_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10
+#define MMEA0_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18
+#define MMEA0_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL
+#define MMEA0_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
+#define MMEA0_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
+#define MMEA0_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L
+//MMEA0_GMI_RD_PRI_AGE
+#define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA0_GMI_WR_PRI_AGE
+#define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA0_GMI_RD_PRI_QUEUING
+#define MMEA0_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA0_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA0_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA0_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA0_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA0_GMI_WR_PRI_QUEUING
+#define MMEA0_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA0_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA0_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA0_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA0_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA0_GMI_RD_PRI_FIXED
+#define MMEA0_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA0_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA0_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA0_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA0_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA0_GMI_WR_PRI_FIXED
+#define MMEA0_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA0_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA0_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA0_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA0_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA0_GMI_RD_PRI_URGENCY
+#define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA0_GMI_WR_PRI_URGENCY
+#define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA0_GMI_RD_PRI_URGENCY_MASKING
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L
+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L
+//MMEA0_GMI_WR_PRI_URGENCY_MASKING
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L
+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L
+//MMEA0_GMI_RD_PRI_QUANT_PRI1
+#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_GMI_RD_PRI_QUANT_PRI2
+#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_GMI_RD_PRI_QUANT_PRI3
+#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_GMI_WR_PRI_QUANT_PRI1
+#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_GMI_WR_PRI_QUANT_PRI2
+#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_GMI_WR_PRI_QUANT_PRI3
+#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_ADDRNORM_BASE_ADDR0
+#define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc
+#define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA0_ADDRNORM_LIMIT_ADDR0
+#define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc
+#define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA0_ADDRNORM_BASE_ADDR1
+#define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc
+#define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA0_ADDRNORM_LIMIT_ADDR1
+#define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc
+#define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA0_ADDRNORM_OFFSET_ADDR1
+#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0
+#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0xc
+#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L
+#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0x00FFF000L
+//MMEA0_ADDRNORM_BASE_ADDR2
+#define MMEA0_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA0_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA0_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc
+#define MMEA0_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA0_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA0_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA0_ADDRNORM_LIMIT_ADDR2
+#define MMEA0_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA0_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc
+#define MMEA0_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA0_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA0_ADDRNORM_BASE_ADDR3
+#define MMEA0_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA0_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA0_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc
+#define MMEA0_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA0_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA0_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA0_ADDRNORM_LIMIT_ADDR3
+#define MMEA0_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA0_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc
+#define MMEA0_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA0_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA0_ADDRNORM_OFFSET_ADDR3
+#define MMEA0_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0
+#define MMEA0_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0xc
+#define MMEA0_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L
+#define MMEA0_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0x00FFF000L
+//MMEA0_ADDRNORM_MEGABASE_ADDR0
+#define MMEA0_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA0_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA0_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA0_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA0_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA0_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA0_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR__SHIFT 0xc
+#define MMEA0_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA0_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA0_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA0_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA0_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA0_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA0_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA0_ADDRNORM_MEGALIMIT_ADDR0
+#define MMEA0_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA0_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc
+#define MMEA0_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA0_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA0_ADDRNORM_MEGABASE_ADDR1
+#define MMEA0_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA0_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA0_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA0_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA0_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA0_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA0_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR__SHIFT 0xc
+#define MMEA0_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA0_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA0_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA0_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA0_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA0_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA0_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA0_ADDRNORM_MEGALIMIT_ADDR1
+#define MMEA0_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA0_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc
+#define MMEA0_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA0_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA0_ADDRNORMDRAM_HOLE_CNTL
+#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0
+#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7
+#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L
+#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L
+//MMEA0_ADDRNORMGMI_HOLE_CNTL
+#define MMEA0_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0
+#define MMEA0_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7
+#define MMEA0_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L
+#define MMEA0_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L
+//MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG
+#define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0
+#define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6
+#define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL
+#define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L
+//MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG
+#define MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0
+#define MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6
+#define MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL
+#define MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L
+//MMEA0_ADDRDEC_BANK_CFG
+#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0
+#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6
+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc
+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf
+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12
+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13
+#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL
+#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L
+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L
+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L
+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L
+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L
+//MMEA0_ADDRDEC_MISC_CFG
+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0
+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1
+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2
+#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8
+#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9
+#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc
+#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11
+#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16
+#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18
+#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a
+#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d
+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L
+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L
+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L
+#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L
+#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L
+#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L
+#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L
+#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L
+#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L
+#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L
+#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L
+//MMEA0_ADDRDECDRAM_HARVEST_ENABLE
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L
+//MMEA0_ADDRDECGMI_HARVEST_ENABLE
+#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0
+#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1
+#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2
+#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3
+#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4
+#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5
+#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L
+#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L
+#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L
+#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L
+#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L
+#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L
+//MMEA0_ADDRDEC0_BASE_ADDR_CS0
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_BASE_ADDR_CS1
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_BASE_ADDR_CS2
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_BASE_ADDR_CS3
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_BASE_ADDR_SECCS0
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_BASE_ADDR_SECCS1
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_BASE_ADDR_SECCS2
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_BASE_ADDR_SECCS3
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_ADDR_MASK_CS01
+#define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
+#define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_ADDR_MASK_CS23
+#define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
+#define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_ADDR_MASK_SECCS01
+#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
+#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_ADDR_MASK_SECCS23
+#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
+#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_ADDR_CFG_CS01
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L
+//MMEA0_ADDRDEC0_ADDR_CFG_CS23
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L
+//MMEA0_ADDRDEC0_ADDR_SEL_CS01
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
+//MMEA0_ADDRDEC0_ADDR_SEL_CS23
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
+//MMEA0_ADDRDEC0_ADDR_SEL2_CS01
+#define MMEA0_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0
+#define MMEA0_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA0_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL
+#define MMEA0_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L
+//MMEA0_ADDRDEC0_ADDR_SEL2_CS23
+#define MMEA0_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0
+#define MMEA0_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA0_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL
+#define MMEA0_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L
+//MMEA0_ADDRDEC0_COL_SEL_LO_CS01
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
+//MMEA0_ADDRDEC0_COL_SEL_LO_CS23
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
+//MMEA0_ADDRDEC0_COL_SEL_HI_CS01
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
+//MMEA0_ADDRDEC0_COL_SEL_HI_CS23
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
+//MMEA0_ADDRDEC0_RM_SEL_CS01
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA0_ADDRDEC0_RM_SEL_CS23
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA0_ADDRDEC0_RM_SEL_SECCS01
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA0_ADDRDEC0_RM_SEL_SECCS23
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA0_ADDRDEC1_BASE_ADDR_CS0
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_BASE_ADDR_CS1
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_BASE_ADDR_CS2
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_BASE_ADDR_CS3
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_BASE_ADDR_SECCS0
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_BASE_ADDR_SECCS1
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_BASE_ADDR_SECCS2
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_BASE_ADDR_SECCS3
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_ADDR_MASK_CS01
+#define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
+#define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_ADDR_MASK_CS23
+#define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
+#define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_ADDR_MASK_SECCS01
+#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
+#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_ADDR_MASK_SECCS23
+#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
+#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_ADDR_CFG_CS01
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L
+//MMEA0_ADDRDEC1_ADDR_CFG_CS23
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L
+//MMEA0_ADDRDEC1_ADDR_SEL_CS01
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
+//MMEA0_ADDRDEC1_ADDR_SEL_CS23
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
+//MMEA0_ADDRDEC1_ADDR_SEL2_CS01
+#define MMEA0_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0
+#define MMEA0_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA0_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL
+#define MMEA0_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L
+//MMEA0_ADDRDEC1_ADDR_SEL2_CS23
+#define MMEA0_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0
+#define MMEA0_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA0_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL
+#define MMEA0_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L
+//MMEA0_ADDRDEC1_COL_SEL_LO_CS01
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
+//MMEA0_ADDRDEC1_COL_SEL_LO_CS23
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
+//MMEA0_ADDRDEC1_COL_SEL_HI_CS01
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
+//MMEA0_ADDRDEC1_COL_SEL_HI_CS23
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
+//MMEA0_ADDRDEC1_RM_SEL_CS01
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA0_ADDRDEC1_RM_SEL_CS23
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA0_ADDRDEC1_RM_SEL_SECCS01
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA0_ADDRDEC1_RM_SEL_SECCS23
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA0_ADDRDEC2_BASE_ADDR_CS0
+#define MMEA0_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC2_BASE_ADDR_CS1
+#define MMEA0_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC2_BASE_ADDR_CS2
+#define MMEA0_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC2_BASE_ADDR_CS3
+#define MMEA0_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC2_BASE_ADDR_SECCS0
+#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC2_BASE_ADDR_SECCS1
+#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC2_BASE_ADDR_SECCS2
+#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC2_BASE_ADDR_SECCS3
+#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC2_ADDR_MASK_CS01
+#define MMEA0_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
+#define MMEA0_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC2_ADDR_MASK_CS23
+#define MMEA0_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
+#define MMEA0_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC2_ADDR_MASK_SECCS01
+#define MMEA0_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
+#define MMEA0_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC2_ADDR_MASK_SECCS23
+#define MMEA0_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
+#define MMEA0_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC2_ADDR_CFG_CS01
+#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
+#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
+#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
+#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
+#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
+#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f
+#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
+#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
+#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
+#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L
+//MMEA0_ADDRDEC2_ADDR_CFG_CS23
+#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
+#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
+#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
+#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
+#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
+#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f
+#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
+#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
+#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
+#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L
+//MMEA0_ADDRDEC2_ADDR_SEL_CS01
+#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0
+#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4
+#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8
+#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc
+#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10
+#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
+#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
+#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
+#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L
+#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
+#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
+//MMEA0_ADDRDEC2_ADDR_SEL_CS23
+#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0
+#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4
+#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8
+#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc
+#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10
+#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
+#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
+#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
+#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L
+#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
+#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
+//MMEA0_ADDRDEC2_ADDR_SEL2_CS01
+#define MMEA0_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0
+#define MMEA0_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA0_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL
+#define MMEA0_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L
+//MMEA0_ADDRDEC2_ADDR_SEL2_CS23
+#define MMEA0_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0
+#define MMEA0_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA0_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL
+#define MMEA0_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L
+//MMEA0_ADDRDEC2_COL_SEL_LO_CS01
+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0
+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4
+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8
+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc
+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10
+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14
+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18
+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
+//MMEA0_ADDRDEC2_COL_SEL_LO_CS23
+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0
+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4
+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8
+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc
+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10
+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14
+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18
+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
+//MMEA0_ADDRDEC2_COL_SEL_HI_CS01
+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0
+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4
+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8
+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc
+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10
+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14
+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18
+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
+//MMEA0_ADDRDEC2_COL_SEL_HI_CS23
+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0
+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4
+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8
+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc
+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10
+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14
+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18
+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
+//MMEA0_ADDRDEC2_RM_SEL_CS01
+#define MMEA0_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0
+#define MMEA0_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4
+#define MMEA0_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8
+#define MMEA0_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA0_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA0_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA0_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA0_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA0_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA0_ADDRDEC2_RM_SEL_CS23
+#define MMEA0_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0
+#define MMEA0_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4
+#define MMEA0_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8
+#define MMEA0_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA0_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA0_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA0_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA0_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA0_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA0_ADDRDEC2_RM_SEL_SECCS01
+#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0
+#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4
+#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8
+#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
+#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA0_ADDRDEC2_RM_SEL_SECCS23
+#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0
+#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4
+#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8
+#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
+#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA0_ADDRNORMDRAM_GLOBAL_CNTL
+//MMEA0_ADDRNORMGMI_GLOBAL_CNTL
+//MMEA0_ADDRNORM_MEGACONTROL_ADDR0
+#define MMEA0_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0
+#define MMEA0_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL
+//MMEA0_ADDRNORM_MEGACONTROL_ADDR1
+#define MMEA0_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0
+#define MMEA0_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL
+//MMEA0_ADDRNORMDRAM_MASKING
+#define MMEA0_ADDRNORMDRAM_MASKING__ADDRHI_MASK__SHIFT 0x0
+#define MMEA0_ADDRNORMDRAM_MASKING__ADDRHI_MASK_MASK 0x00000FFFL
+//MMEA0_ADDRNORMGMI_MASKING
+#define MMEA0_ADDRNORMGMI_MASKING__ADDRHI_MASK__SHIFT 0x0
+#define MMEA0_ADDRNORMGMI_MASKING__ADDRHI_MASK_MASK 0x00000FFFL
+//MMEA0_IO_RD_CLI2GRP_MAP0
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA0_IO_RD_CLI2GRP_MAP1
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA0_IO_WR_CLI2GRP_MAP0
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA0_IO_WR_CLI2GRP_MAP1
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA0_IO_RD_COMBINE_FLUSH
+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0
+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4
+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8
+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc
+#define MMEA0_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10
+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL
+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L
+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L
+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L
+#define MMEA0_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L
+//MMEA0_IO_WR_COMBINE_FLUSH
+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0
+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4
+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8
+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc
+#define MMEA0_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10
+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL
+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L
+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L
+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L
+#define MMEA0_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L
+//MMEA0_IO_GROUP_BURST
+#define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0
+#define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8
+#define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10
+#define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18
+#define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL
+#define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
+#define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
+#define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L
+//MMEA0_IO_RD_PRI_AGE
+#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA0_IO_WR_PRI_AGE
+#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA0_IO_RD_PRI_QUEUING
+#define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA0_IO_WR_PRI_QUEUING
+#define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA0_IO_RD_PRI_FIXED
+#define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA0_IO_WR_PRI_FIXED
+#define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA0_IO_RD_PRI_URGENCY
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA0_IO_WR_PRI_URGENCY
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA0_IO_RD_PRI_URGENCY_MASKING
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L
+//MMEA0_IO_WR_PRI_URGENCY_MASKING
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L
+//MMEA0_IO_RD_PRI_QUANT_PRI1
+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_IO_RD_PRI_QUANT_PRI2
+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_IO_RD_PRI_QUANT_PRI3
+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_IO_WR_PRI_QUANT_PRI1
+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_IO_WR_PRI_QUANT_PRI2
+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_IO_WR_PRI_QUANT_PRI3
+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_SDP_ARB_DRAM
+#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0
+#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8
+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10
+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11
+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12
+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13
+#define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14
+#define MMEA0_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15
+#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL
+#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L
+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L
+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L
+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L
+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L
+#define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L
+#define MMEA0_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L
+//MMEA0_SDP_ARB_GMI
+#define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0
+#define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8
+#define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10
+#define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11
+#define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12
+#define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13
+#define MMEA0_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14
+#define MMEA0_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15
+#define MMEA0_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16
+#define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL
+#define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L
+#define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L
+#define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L
+#define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L
+#define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L
+#define MMEA0_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L
+#define MMEA0_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L
+#define MMEA0_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L
+//MMEA0_SDP_ARB_FINAL
+#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0
+#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5
+#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa
+#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18
+#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19
+#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a
+#define MMEA0_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b
+#define MMEA0_SDP_ARB_FINAL__DRAM_RD_THROTTLE__SHIFT 0x1c
+#define MMEA0_SDP_ARB_FINAL__DRAM_WR_THROTTLE__SHIFT 0x1d
+#define MMEA0_SDP_ARB_FINAL__GMI_RD_THROTTLE__SHIFT 0x1e
+#define MMEA0_SDP_ARB_FINAL__GMI_WR_THROTTLE__SHIFT 0x1f
+#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL
+#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L
+#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L
+#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L
+#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L
+#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L
+#define MMEA0_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L
+#define MMEA0_SDP_ARB_FINAL__DRAM_RD_THROTTLE_MASK 0x10000000L
+#define MMEA0_SDP_ARB_FINAL__DRAM_WR_THROTTLE_MASK 0x20000000L
+#define MMEA0_SDP_ARB_FINAL__GMI_RD_THROTTLE_MASK 0x40000000L
+#define MMEA0_SDP_ARB_FINAL__GMI_WR_THROTTLE_MASK 0x80000000L
+//MMEA0_SDP_DRAM_PRIORITY
+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
+//MMEA0_SDP_GMI_PRIORITY
+#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
+#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
+#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
+#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
+#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
+#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
+#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
+#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
+#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
+#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
+#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
+#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
+#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
+#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
+#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
+#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
+//MMEA0_SDP_IO_PRIORITY
+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
+//MMEA0_SDP_CREDITS
+#define MMEA0_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0
+#define MMEA0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8
+#define MMEA0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10
+#define MMEA0_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL
+#define MMEA0_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L
+#define MMEA0_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L
+//MMEA0_SDP_TAG_RESERVE0
+#define MMEA0_SDP_TAG_RESERVE0__VC0__SHIFT 0x0
+#define MMEA0_SDP_TAG_RESERVE0__VC1__SHIFT 0x8
+#define MMEA0_SDP_TAG_RESERVE0__VC2__SHIFT 0x10
+#define MMEA0_SDP_TAG_RESERVE0__VC3__SHIFT 0x18
+#define MMEA0_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL
+#define MMEA0_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L
+#define MMEA0_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L
+#define MMEA0_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L
+//MMEA0_SDP_TAG_RESERVE1
+#define MMEA0_SDP_TAG_RESERVE1__VC4__SHIFT 0x0
+#define MMEA0_SDP_TAG_RESERVE1__VC5__SHIFT 0x8
+#define MMEA0_SDP_TAG_RESERVE1__VC6__SHIFT 0x10
+#define MMEA0_SDP_TAG_RESERVE1__VC7__SHIFT 0x18
+#define MMEA0_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL
+#define MMEA0_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L
+#define MMEA0_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L
+#define MMEA0_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L
+//MMEA0_SDP_VCC_RESERVE0
+#define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0
+#define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6
+#define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc
+#define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12
+#define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18
+#define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL
+#define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L
+#define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L
+#define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L
+#define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L
+//MMEA0_SDP_VCC_RESERVE1
+#define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0
+#define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6
+#define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc
+#define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f
+#define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL
+#define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L
+#define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L
+#define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L
+//MMEA0_SDP_VCD_RESERVE0
+#define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0
+#define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6
+#define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc
+#define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12
+#define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18
+#define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL
+#define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L
+#define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L
+#define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L
+#define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L
+//MMEA0_SDP_VCD_RESERVE1
+#define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0
+#define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6
+#define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc
+#define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f
+#define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL
+#define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L
+#define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L
+#define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L
+//MMEA0_SDP_REQ_CNTL
+#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0
+#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1
+#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2
+#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3
+#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4
+#define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5
+#define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6
+#define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8
+#define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa
+#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L
+#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L
+#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L
+#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L
+#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L
+#define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L
+#define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L
+#define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L
+#define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L
+//MMEA0_MISC
+#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0
+#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1
+#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2
+#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3
+#define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4
+#define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd
+#define MMEA0_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe
+#define MMEA0_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf
+#define MMEA0_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11
+#define MMEA0_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13
+#define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15
+#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a
+#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b
+#define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c
+#define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d
+#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e
+#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f
+#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L
+#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L
+#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L
+#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L
+#define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L
+#define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L
+#define MMEA0_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L
+#define MMEA0_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L
+#define MMEA0_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L
+#define MMEA0_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L
+#define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L
+#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L
+#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L
+#define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L
+#define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L
+#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L
+#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L
+//MMEA0_LATENCY_SAMPLING
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L
+//MMEA0_PERFCOUNTER_LO
+#define MMEA0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MMEA0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//MMEA0_PERFCOUNTER_HI
+#define MMEA0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MMEA0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//MMEA0_PERFCOUNTER0_CFG
+#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMEA0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MMEA0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MMEA0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMEA0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMEA0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define MMEA0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//MMEA0_PERFCOUNTER1_CFG
+#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMEA0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MMEA0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MMEA0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMEA0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMEA0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define MMEA0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//MMEA0_PERFCOUNTER_RSLT_CNTL
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+//MMEA0_EDC_CNT
+#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0
+#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2
+#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4
+#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6
+#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8
+#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa
+#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc
+#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe
+#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10
+#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12
+#define MMEA0_EDC_CNT__IOWR_DATAMEM_SEC_COUNT__SHIFT 0x14
+#define MMEA0_EDC_CNT__IOWR_DATAMEM_DED_COUNT__SHIFT 0x16
+#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x18
+#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x1a
+#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x1c
+#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1e
+#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
+#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
+#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
+#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
+#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
+#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
+#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L
+#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L
+#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L
+#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L
+#define MMEA0_EDC_CNT__IOWR_DATAMEM_SEC_COUNT_MASK 0x00300000L
+#define MMEA0_EDC_CNT__IOWR_DATAMEM_DED_COUNT_MASK 0x00C00000L
+#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x03000000L
+#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x0C000000L
+#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x30000000L
+#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0xC0000000L
+//MMEA0_EDC_CNT2
+#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0
+#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2
+#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4
+#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6
+#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8
+#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa
+#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc
+#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe
+#define MMEA0_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10
+#define MMEA0_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12
+#define MMEA0_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14
+#define MMEA0_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16
+#define MMEA0_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT 0x18
+#define MMEA0_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT 0x1a
+#define MMEA0_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT 0x1c
+#define MMEA0_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT 0x1e
+#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
+#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
+#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
+#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
+#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
+#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
+#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L
+#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L
+#define MMEA0_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L
+#define MMEA0_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L
+#define MMEA0_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L
+#define MMEA0_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L
+#define MMEA0_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK 0x03000000L
+#define MMEA0_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK 0x0C000000L
+#define MMEA0_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK 0x30000000L
+#define MMEA0_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK 0xC0000000L
+//MMEA0_DSM_CNTL
+#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3
+#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9
+#define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb
+#define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc
+#define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
+#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf
+#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11
+#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12
+#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14
+#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15
+#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17
+#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
+#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L
+#define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
+#define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L
+#define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
+#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L
+#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L
+#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L
+#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L
+#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L
+#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L
+//MMEA0_DSM_CNTLA
+#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3
+#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9
+#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb
+#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc
+#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
+#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf
+#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11
+#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12
+#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14
+#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
+#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L
+#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
+#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L
+#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
+#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L
+#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L
+#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L
+#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L
+//MMEA0_DSM_CNTLB
+//MMEA0_DSM_CNTL2
+#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5
+#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8
+#define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb
+#define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe
+#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11
+#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14
+#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15
+#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17
+#define MMEA0_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
+#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L
+#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L
+#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L
+#define MMEA0_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
+//MMEA0_DSM_CNTL2A
+#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5
+#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8
+#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb
+#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe
+#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11
+#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14
+#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L
+//MMEA0_DSM_CNTL2B
+//MMEA0_CGTT_CLK_CTRL
+#define MMEA0_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define MMEA0_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc
+#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14
+#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15
+#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16
+#define MMEA0_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17
+#define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c
+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d
+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e
+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f
+#define MMEA0_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define MMEA0_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L
+#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L
+#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L
+#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L
+#define MMEA0_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L
+#define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L
+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L
+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L
+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L
+//MMEA0_EDC_MODE
+#define MMEA0_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10
+#define MMEA0_EDC_MODE__GATE_FUE__SHIFT 0x11
+#define MMEA0_EDC_MODE__DED_MODE__SHIFT 0x14
+#define MMEA0_EDC_MODE__PROP_FED__SHIFT 0x1d
+#define MMEA0_EDC_MODE__BYPASS__SHIFT 0x1f
+#define MMEA0_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L
+#define MMEA0_EDC_MODE__GATE_FUE_MASK 0x00020000L
+#define MMEA0_EDC_MODE__DED_MODE_MASK 0x00300000L
+#define MMEA0_EDC_MODE__PROP_FED_MASK 0x20000000L
+#define MMEA0_EDC_MODE__BYPASS_MASK 0x80000000L
+//MMEA0_ERR_STATUS
+#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0
+#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4
+#define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8
+#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa
+#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb
+#define MMEA0_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc
+#define MMEA0_ERR_STATUS__FUE_FLAG__SHIFT 0xd
+#define MMEA0_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe
+#define MMEA0_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf
+#define MMEA0_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10
+#define MMEA0_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11
+#define MMEA0_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12
+#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL
+#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L
+#define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L
+#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L
+#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L
+#define MMEA0_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L
+#define MMEA0_ERR_STATUS__FUE_FLAG_MASK 0x00002000L
+#define MMEA0_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L
+#define MMEA0_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L
+#define MMEA0_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L
+#define MMEA0_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L
+#define MMEA0_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L
+//MMEA0_MISC2
+#define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0
+#define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1
+#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2
+#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7
+#define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc
+#define MMEA0_MISC2__RRET_SWAP_MODE__SHIFT 0xd
+#define MMEA0_MISC2__BLOCK_REQUESTS__SHIFT 0xe
+#define MMEA0_MISC2__REQUESTS_BLOCKED__SHIFT 0xf
+#define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L
+#define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L
+#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL
+#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L
+#define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L
+#define MMEA0_MISC2__RRET_SWAP_MODE_MASK 0x00002000L
+#define MMEA0_MISC2__BLOCK_REQUESTS_MASK 0x00004000L
+#define MMEA0_MISC2__REQUESTS_BLOCKED_MASK 0x00008000L
+//MMEA0_ADDRDEC_SELECT
+#define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0
+#define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5
+#define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa
+#define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf
+#define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL
+#define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L
+#define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L
+#define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L
+//MMEA0_EDC_CNT3
+#define MMEA0_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0
+#define MMEA0_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2
+#define MMEA0_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4
+#define MMEA0_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6
+#define MMEA0_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0x8
+#define MMEA0_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xa
+#define MMEA0_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L
+#define MMEA0_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL
+#define MMEA0_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L
+#define MMEA0_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
+#define MMEA0_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000300L
+#define MMEA0_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00000C00L
+//MMEA0_MISC_AON
+#define MMEA0_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0
+#define MMEA0_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2
+#define MMEA0_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L
+#define MMEA0_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L
+
+
+// addressBlock: mmhub_ea_mmeadec1
+//MMEA1_DRAM_RD_CLI2GRP_MAP0
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA1_DRAM_RD_CLI2GRP_MAP1
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA1_DRAM_WR_CLI2GRP_MAP0
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA1_DRAM_WR_CLI2GRP_MAP1
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA1_DRAM_RD_GRP2VC_MAP
+#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
+#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
+#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
+#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
+#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
+#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
+#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
+#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
+//MMEA1_DRAM_WR_GRP2VC_MAP
+#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
+#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
+#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
+#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
+#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
+#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
+#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
+#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
+//MMEA1_DRAM_RD_LAZY
+#define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0
+#define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3
+#define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6
+#define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9
+#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
+#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
+#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b
+#define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L
+#define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L
+#define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L
+#define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L
+#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
+#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
+#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L
+//MMEA1_DRAM_WR_LAZY
+#define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0
+#define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3
+#define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6
+#define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9
+#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
+#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
+#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b
+#define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L
+#define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L
+#define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L
+#define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L
+#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
+#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
+#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L
+//MMEA1_DRAM_RD_CAM_CNTL
+#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
+#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
+#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
+#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
+#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
+#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
+#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
+#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
+#define MMEA1_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c
+#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
+#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
+#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
+#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
+#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
+#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
+#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
+#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
+#define MMEA1_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L
+//MMEA1_DRAM_WR_CAM_CNTL
+#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
+#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
+#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
+#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
+#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
+#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
+#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
+#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
+#define MMEA1_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c
+#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
+#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
+#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
+#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
+#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
+#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
+#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
+#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
+#define MMEA1_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L
+//MMEA1_DRAM_PAGE_BURST
+#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0
+#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8
+#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10
+#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18
+#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL
+#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
+#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
+#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L
+//MMEA1_DRAM_RD_PRI_AGE
+#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA1_DRAM_WR_PRI_AGE
+#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA1_DRAM_RD_PRI_QUEUING
+#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA1_DRAM_WR_PRI_QUEUING
+#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA1_DRAM_RD_PRI_FIXED
+#define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA1_DRAM_WR_PRI_FIXED
+#define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA1_DRAM_RD_PRI_URGENCY
+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA1_DRAM_WR_PRI_URGENCY
+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA1_DRAM_RD_PRI_QUANT_PRI1
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA1_DRAM_RD_PRI_QUANT_PRI2
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA1_DRAM_RD_PRI_QUANT_PRI3
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA1_DRAM_WR_PRI_QUANT_PRI1
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA1_DRAM_WR_PRI_QUANT_PRI2
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA1_DRAM_WR_PRI_QUANT_PRI3
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA1_GMI_RD_CLI2GRP_MAP0
+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA1_GMI_RD_CLI2GRP_MAP1
+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA1_GMI_WR_CLI2GRP_MAP0
+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA1_GMI_WR_CLI2GRP_MAP1
+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA1_GMI_RD_GRP2VC_MAP
+#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
+#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
+#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
+#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
+#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
+#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
+#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
+#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
+//MMEA1_GMI_WR_GRP2VC_MAP
+#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
+#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
+#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
+#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
+#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
+#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
+#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
+#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
+//MMEA1_GMI_RD_LAZY
+#define MMEA1_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0
+#define MMEA1_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3
+#define MMEA1_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6
+#define MMEA1_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9
+#define MMEA1_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
+#define MMEA1_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
+#define MMEA1_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b
+#define MMEA1_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L
+#define MMEA1_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L
+#define MMEA1_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L
+#define MMEA1_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L
+#define MMEA1_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
+#define MMEA1_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
+#define MMEA1_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L
+//MMEA1_GMI_WR_LAZY
+#define MMEA1_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0
+#define MMEA1_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3
+#define MMEA1_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6
+#define MMEA1_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9
+#define MMEA1_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
+#define MMEA1_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
+#define MMEA1_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b
+#define MMEA1_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L
+#define MMEA1_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L
+#define MMEA1_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L
+#define MMEA1_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L
+#define MMEA1_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
+#define MMEA1_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
+#define MMEA1_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L
+//MMEA1_GMI_RD_CAM_CNTL
+#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
+#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
+#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
+#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
+#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
+#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
+#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
+#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
+#define MMEA1_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c
+#define MMEA1_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d
+#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
+#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
+#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
+#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
+#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
+#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
+#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
+#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
+#define MMEA1_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L
+#define MMEA1_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L
+//MMEA1_GMI_WR_CAM_CNTL
+#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
+#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
+#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
+#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
+#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
+#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
+#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
+#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
+#define MMEA1_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c
+#define MMEA1_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d
+#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
+#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
+#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
+#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
+#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
+#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
+#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
+#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
+#define MMEA1_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L
+#define MMEA1_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L
+//MMEA1_GMI_PAGE_BURST
+#define MMEA1_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0
+#define MMEA1_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8
+#define MMEA1_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10
+#define MMEA1_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18
+#define MMEA1_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL
+#define MMEA1_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
+#define MMEA1_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
+#define MMEA1_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L
+//MMEA1_GMI_RD_PRI_AGE
+#define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA1_GMI_WR_PRI_AGE
+#define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA1_GMI_RD_PRI_QUEUING
+#define MMEA1_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA1_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA1_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA1_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA1_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA1_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA1_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA1_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA1_GMI_WR_PRI_QUEUING
+#define MMEA1_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA1_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA1_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA1_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA1_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA1_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA1_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA1_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA1_GMI_RD_PRI_FIXED
+#define MMEA1_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA1_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA1_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA1_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA1_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA1_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA1_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA1_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA1_GMI_WR_PRI_FIXED
+#define MMEA1_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA1_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA1_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA1_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA1_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA1_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA1_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA1_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA1_GMI_RD_PRI_URGENCY
+#define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA1_GMI_WR_PRI_URGENCY
+#define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA1_GMI_RD_PRI_URGENCY_MASKING
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L
+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L
+//MMEA1_GMI_WR_PRI_URGENCY_MASKING
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L
+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L
+//MMEA1_GMI_RD_PRI_QUANT_PRI1
+#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA1_GMI_RD_PRI_QUANT_PRI2
+#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA1_GMI_RD_PRI_QUANT_PRI3
+#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA1_GMI_WR_PRI_QUANT_PRI1
+#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA1_GMI_WR_PRI_QUANT_PRI2
+#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA1_GMI_WR_PRI_QUANT_PRI3
+#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA1_ADDRNORM_BASE_ADDR0
+#define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc
+#define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA1_ADDRNORM_LIMIT_ADDR0
+#define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc
+#define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA1_ADDRNORM_BASE_ADDR1
+#define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc
+#define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA1_ADDRNORM_LIMIT_ADDR1
+#define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc
+#define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA1_ADDRNORM_OFFSET_ADDR1
+#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0
+#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0xc
+#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L
+#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0x00FFF000L
+//MMEA1_ADDRNORM_BASE_ADDR2
+#define MMEA1_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA1_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA1_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc
+#define MMEA1_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA1_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA1_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA1_ADDRNORM_LIMIT_ADDR2
+#define MMEA1_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA1_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc
+#define MMEA1_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA1_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA1_ADDRNORM_BASE_ADDR3
+#define MMEA1_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA1_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA1_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc
+#define MMEA1_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA1_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA1_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA1_ADDRNORM_LIMIT_ADDR3
+#define MMEA1_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA1_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc
+#define MMEA1_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA1_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA1_ADDRNORM_OFFSET_ADDR3
+#define MMEA1_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0
+#define MMEA1_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0xc
+#define MMEA1_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L
+#define MMEA1_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0x00FFF000L
+//MMEA1_ADDRNORM_MEGABASE_ADDR0
+#define MMEA1_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA1_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA1_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA1_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA1_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA1_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA1_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR__SHIFT 0xc
+#define MMEA1_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA1_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA1_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA1_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA1_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA1_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA1_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA1_ADDRNORM_MEGALIMIT_ADDR0
+#define MMEA1_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA1_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc
+#define MMEA1_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA1_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA1_ADDRNORM_MEGABASE_ADDR1
+#define MMEA1_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA1_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA1_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA1_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA1_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA1_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA1_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR__SHIFT 0xc
+#define MMEA1_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA1_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA1_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA1_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA1_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA1_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA1_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA1_ADDRNORM_MEGALIMIT_ADDR1
+#define MMEA1_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA1_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc
+#define MMEA1_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA1_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA1_ADDRNORMDRAM_HOLE_CNTL
+#define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0
+#define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7
+#define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L
+#define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L
+//MMEA1_ADDRNORMGMI_HOLE_CNTL
+#define MMEA1_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0
+#define MMEA1_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7
+#define MMEA1_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L
+#define MMEA1_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L
+//MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG
+#define MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0
+#define MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6
+#define MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL
+#define MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L
+//MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG
+#define MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0
+#define MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6
+#define MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL
+#define MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L
+//MMEA1_ADDRDEC_BANK_CFG
+#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0
+#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6
+#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc
+#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf
+#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12
+#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13
+#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL
+#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L
+#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L
+#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L
+#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L
+#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L
+//MMEA1_ADDRDEC_MISC_CFG
+#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0
+#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1
+#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2
+#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8
+#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9
+#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc
+#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11
+#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16
+#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18
+#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a
+#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d
+#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L
+#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L
+#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L
+#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L
+#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L
+#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L
+#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L
+#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L
+#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L
+#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L
+#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L
+//MMEA1_ADDRDECDRAM_HARVEST_ENABLE
+#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0
+#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1
+#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2
+#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3
+#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4
+#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5
+#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L
+#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L
+#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L
+#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L
+#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L
+#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L
+//MMEA1_ADDRDECGMI_HARVEST_ENABLE
+#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0
+#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1
+#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2
+#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3
+#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4
+#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5
+#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L
+#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L
+#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L
+#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L
+#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L
+#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L
+//MMEA1_ADDRDEC0_BASE_ADDR_CS0
+#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0
+#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L
+#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC0_BASE_ADDR_CS1
+#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0
+#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L
+#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC0_BASE_ADDR_CS2
+#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0
+#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L
+#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC0_BASE_ADDR_CS3
+#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0
+#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L
+#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC0_BASE_ADDR_SECCS0
+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0
+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L
+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC0_BASE_ADDR_SECCS1
+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0
+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L
+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC0_BASE_ADDR_SECCS2
+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0
+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L
+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC0_BASE_ADDR_SECCS3
+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0
+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L
+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC0_ADDR_MASK_CS01
+#define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
+#define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC0_ADDR_MASK_CS23
+#define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
+#define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC0_ADDR_MASK_SECCS01
+#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
+#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC0_ADDR_MASK_SECCS23
+#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
+#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC0_ADDR_CFG_CS01
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L
+//MMEA1_ADDRDEC0_ADDR_CFG_CS23
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L
+//MMEA1_ADDRDEC0_ADDR_SEL_CS01
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
+//MMEA1_ADDRDEC0_ADDR_SEL_CS23
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
+//MMEA1_ADDRDEC0_ADDR_SEL2_CS01
+#define MMEA1_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0
+#define MMEA1_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA1_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL
+#define MMEA1_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L
+//MMEA1_ADDRDEC0_ADDR_SEL2_CS23
+#define MMEA1_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0
+#define MMEA1_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA1_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL
+#define MMEA1_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L
+//MMEA1_ADDRDEC0_COL_SEL_LO_CS01
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
+//MMEA1_ADDRDEC0_COL_SEL_LO_CS23
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
+//MMEA1_ADDRDEC0_COL_SEL_HI_CS01
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
+//MMEA1_ADDRDEC0_COL_SEL_HI_CS23
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
+//MMEA1_ADDRDEC0_RM_SEL_CS01
+#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0
+#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4
+#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8
+#define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA1_ADDRDEC0_RM_SEL_CS23
+#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0
+#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4
+#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8
+#define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA1_ADDRDEC0_RM_SEL_SECCS01
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA1_ADDRDEC0_RM_SEL_SECCS23
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA1_ADDRDEC1_BASE_ADDR_CS0
+#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0
+#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L
+#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC1_BASE_ADDR_CS1
+#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0
+#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L
+#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC1_BASE_ADDR_CS2
+#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0
+#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L
+#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC1_BASE_ADDR_CS3
+#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0
+#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L
+#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC1_BASE_ADDR_SECCS0
+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0
+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L
+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC1_BASE_ADDR_SECCS1
+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0
+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L
+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC1_BASE_ADDR_SECCS2
+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0
+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L
+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC1_BASE_ADDR_SECCS3
+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0
+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L
+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC1_ADDR_MASK_CS01
+#define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
+#define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC1_ADDR_MASK_CS23
+#define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
+#define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC1_ADDR_MASK_SECCS01
+#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
+#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC1_ADDR_MASK_SECCS23
+#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
+#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC1_ADDR_CFG_CS01
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L
+//MMEA1_ADDRDEC1_ADDR_CFG_CS23
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L
+//MMEA1_ADDRDEC1_ADDR_SEL_CS01
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
+//MMEA1_ADDRDEC1_ADDR_SEL_CS23
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
+//MMEA1_ADDRDEC1_ADDR_SEL2_CS01
+#define MMEA1_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0
+#define MMEA1_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA1_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL
+#define MMEA1_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L
+//MMEA1_ADDRDEC1_ADDR_SEL2_CS23
+#define MMEA1_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0
+#define MMEA1_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA1_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL
+#define MMEA1_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L
+//MMEA1_ADDRDEC1_COL_SEL_LO_CS01
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
+//MMEA1_ADDRDEC1_COL_SEL_LO_CS23
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
+//MMEA1_ADDRDEC1_COL_SEL_HI_CS01
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
+//MMEA1_ADDRDEC1_COL_SEL_HI_CS23
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
+//MMEA1_ADDRDEC1_RM_SEL_CS01
+#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0
+#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4
+#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8
+#define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA1_ADDRDEC1_RM_SEL_CS23
+#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0
+#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4
+#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8
+#define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA1_ADDRDEC1_RM_SEL_SECCS01
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA1_ADDRDEC1_RM_SEL_SECCS23
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA1_ADDRDEC2_BASE_ADDR_CS0
+#define MMEA1_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0
+#define MMEA1_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L
+#define MMEA1_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC2_BASE_ADDR_CS1
+#define MMEA1_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0
+#define MMEA1_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L
+#define MMEA1_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC2_BASE_ADDR_CS2
+#define MMEA1_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0
+#define MMEA1_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L
+#define MMEA1_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC2_BASE_ADDR_CS3
+#define MMEA1_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0
+#define MMEA1_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L
+#define MMEA1_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC2_BASE_ADDR_SECCS0
+#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0
+#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L
+#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC2_BASE_ADDR_SECCS1
+#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0
+#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L
+#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC2_BASE_ADDR_SECCS2
+#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0
+#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L
+#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC2_BASE_ADDR_SECCS3
+#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0
+#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
+#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L
+#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC2_ADDR_MASK_CS01
+#define MMEA1_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
+#define MMEA1_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC2_ADDR_MASK_CS23
+#define MMEA1_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
+#define MMEA1_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC2_ADDR_MASK_SECCS01
+#define MMEA1_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
+#define MMEA1_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC2_ADDR_MASK_SECCS23
+#define MMEA1_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
+#define MMEA1_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA1_ADDRDEC2_ADDR_CFG_CS01
+#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
+#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
+#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
+#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
+#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
+#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f
+#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
+#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
+#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
+#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L
+//MMEA1_ADDRDEC2_ADDR_CFG_CS23
+#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
+#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
+#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
+#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
+#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
+#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f
+#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
+#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
+#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
+#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L
+//MMEA1_ADDRDEC2_ADDR_SEL_CS01
+#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0
+#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4
+#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8
+#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc
+#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10
+#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
+#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
+#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
+#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L
+#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
+#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
+//MMEA1_ADDRDEC2_ADDR_SEL_CS23
+#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0
+#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4
+#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8
+#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc
+#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10
+#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
+#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
+#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
+#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L
+#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
+#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
+//MMEA1_ADDRDEC2_ADDR_SEL2_CS01
+#define MMEA1_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0
+#define MMEA1_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA1_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL
+#define MMEA1_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L
+//MMEA1_ADDRDEC2_ADDR_SEL2_CS23
+#define MMEA1_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0
+#define MMEA1_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA1_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL
+#define MMEA1_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L
+//MMEA1_ADDRDEC2_COL_SEL_LO_CS01
+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0
+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4
+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8
+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc
+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10
+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14
+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18
+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
+//MMEA1_ADDRDEC2_COL_SEL_LO_CS23
+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0
+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4
+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8
+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc
+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10
+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14
+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18
+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
+//MMEA1_ADDRDEC2_COL_SEL_HI_CS01
+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0
+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4
+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8
+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc
+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10
+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14
+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18
+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
+//MMEA1_ADDRDEC2_COL_SEL_HI_CS23
+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0
+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4
+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8
+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc
+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10
+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14
+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18
+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
+//MMEA1_ADDRDEC2_RM_SEL_CS01
+#define MMEA1_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0
+#define MMEA1_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4
+#define MMEA1_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8
+#define MMEA1_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA1_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA1_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA1_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA1_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA1_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA1_ADDRDEC2_RM_SEL_CS23
+#define MMEA1_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0
+#define MMEA1_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4
+#define MMEA1_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8
+#define MMEA1_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA1_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA1_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA1_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA1_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA1_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA1_ADDRDEC2_RM_SEL_SECCS01
+#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0
+#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4
+#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8
+#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
+#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA1_ADDRDEC2_RM_SEL_SECCS23
+#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0
+#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4
+#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8
+#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
+#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
+#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
+#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
+#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA1_ADDRNORMDRAM_GLOBAL_CNTL
+//MMEA1_ADDRNORMGMI_GLOBAL_CNTL
+//MMEA1_ADDRNORM_MEGACONTROL_ADDR0
+#define MMEA1_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0
+#define MMEA1_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL
+//MMEA1_ADDRNORM_MEGACONTROL_ADDR1
+#define MMEA1_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0
+#define MMEA1_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL
+//MMEA1_ADDRNORMDRAM_MASKING
+#define MMEA1_ADDRNORMDRAM_MASKING__ADDRHI_MASK__SHIFT 0x0
+#define MMEA1_ADDRNORMDRAM_MASKING__ADDRHI_MASK_MASK 0x00000FFFL
+//MMEA1_ADDRNORMGMI_MASKING
+#define MMEA1_ADDRNORMGMI_MASKING__ADDRHI_MASK__SHIFT 0x0
+#define MMEA1_ADDRNORMGMI_MASKING__ADDRHI_MASK_MASK 0x00000FFFL
+//MMEA1_IO_RD_CLI2GRP_MAP0
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA1_IO_RD_CLI2GRP_MAP1
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA1_IO_WR_CLI2GRP_MAP0
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA1_IO_WR_CLI2GRP_MAP1
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA1_IO_RD_COMBINE_FLUSH
+#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0
+#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4
+#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8
+#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc
+#define MMEA1_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10
+#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL
+#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L
+#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L
+#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L
+#define MMEA1_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L
+//MMEA1_IO_WR_COMBINE_FLUSH
+#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0
+#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4
+#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8
+#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc
+#define MMEA1_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10
+#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL
+#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L
+#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L
+#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L
+#define MMEA1_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L
+//MMEA1_IO_GROUP_BURST
+#define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0
+#define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8
+#define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10
+#define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18
+#define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL
+#define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
+#define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
+#define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L
+//MMEA1_IO_RD_PRI_AGE
+#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA1_IO_WR_PRI_AGE
+#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA1_IO_RD_PRI_QUEUING
+#define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA1_IO_WR_PRI_QUEUING
+#define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA1_IO_RD_PRI_FIXED
+#define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA1_IO_WR_PRI_FIXED
+#define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA1_IO_RD_PRI_URGENCY
+#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA1_IO_WR_PRI_URGENCY
+#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA1_IO_RD_PRI_URGENCY_MASKING
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L
+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L
+//MMEA1_IO_WR_PRI_URGENCY_MASKING
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L
+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L
+//MMEA1_IO_RD_PRI_QUANT_PRI1
+#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA1_IO_RD_PRI_QUANT_PRI2
+#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA1_IO_RD_PRI_QUANT_PRI3
+#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA1_IO_WR_PRI_QUANT_PRI1
+#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA1_IO_WR_PRI_QUANT_PRI2
+#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA1_IO_WR_PRI_QUANT_PRI3
+#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA1_SDP_ARB_DRAM
+#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0
+#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8
+#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10
+#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11
+#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12
+#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13
+#define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14
+#define MMEA1_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15
+#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL
+#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L
+#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L
+#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L
+#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L
+#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L
+#define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L
+#define MMEA1_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L
+//MMEA1_SDP_ARB_GMI
+#define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0
+#define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8
+#define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10
+#define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11
+#define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12
+#define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13
+#define MMEA1_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14
+#define MMEA1_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15
+#define MMEA1_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16
+#define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL
+#define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L
+#define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L
+#define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L
+#define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L
+#define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L
+#define MMEA1_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L
+#define MMEA1_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L
+#define MMEA1_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L
+//MMEA1_SDP_ARB_FINAL
+#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0
+#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5
+#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa
+#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf
+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11
+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12
+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13
+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14
+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15
+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16
+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17
+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18
+#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19
+#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a
+#define MMEA1_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b
+#define MMEA1_SDP_ARB_FINAL__DRAM_RD_THROTTLE__SHIFT 0x1c
+#define MMEA1_SDP_ARB_FINAL__DRAM_WR_THROTTLE__SHIFT 0x1d
+#define MMEA1_SDP_ARB_FINAL__GMI_RD_THROTTLE__SHIFT 0x1e
+#define MMEA1_SDP_ARB_FINAL__GMI_WR_THROTTLE__SHIFT 0x1f
+#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL
+#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L
+#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L
+#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L
+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L
+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L
+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L
+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L
+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L
+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L
+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L
+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L
+#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L
+#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L
+#define MMEA1_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L
+#define MMEA1_SDP_ARB_FINAL__DRAM_RD_THROTTLE_MASK 0x10000000L
+#define MMEA1_SDP_ARB_FINAL__DRAM_WR_THROTTLE_MASK 0x20000000L
+#define MMEA1_SDP_ARB_FINAL__GMI_RD_THROTTLE_MASK 0x40000000L
+#define MMEA1_SDP_ARB_FINAL__GMI_WR_THROTTLE_MASK 0x80000000L
+//MMEA1_SDP_DRAM_PRIORITY
+#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
+#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
+#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
+#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
+#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
+#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
+#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
+#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
+#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
+#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
+#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
+#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
+#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
+#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
+#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
+#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
+//MMEA1_SDP_GMI_PRIORITY
+#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
+#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
+#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
+#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
+#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
+#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
+#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
+#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
+#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
+#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
+#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
+#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
+#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
+#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
+#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
+#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
+//MMEA1_SDP_IO_PRIORITY
+#define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
+#define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
+#define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
+#define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
+#define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
+#define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
+#define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
+#define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
+#define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
+#define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
+#define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
+#define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
+#define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
+#define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
+#define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
+#define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
+//MMEA1_SDP_CREDITS
+#define MMEA1_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0
+#define MMEA1_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8
+#define MMEA1_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10
+#define MMEA1_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL
+#define MMEA1_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L
+#define MMEA1_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L
+//MMEA1_SDP_TAG_RESERVE0
+#define MMEA1_SDP_TAG_RESERVE0__VC0__SHIFT 0x0
+#define MMEA1_SDP_TAG_RESERVE0__VC1__SHIFT 0x8
+#define MMEA1_SDP_TAG_RESERVE0__VC2__SHIFT 0x10
+#define MMEA1_SDP_TAG_RESERVE0__VC3__SHIFT 0x18
+#define MMEA1_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL
+#define MMEA1_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L
+#define MMEA1_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L
+#define MMEA1_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L
+//MMEA1_SDP_TAG_RESERVE1
+#define MMEA1_SDP_TAG_RESERVE1__VC4__SHIFT 0x0
+#define MMEA1_SDP_TAG_RESERVE1__VC5__SHIFT 0x8
+#define MMEA1_SDP_TAG_RESERVE1__VC6__SHIFT 0x10
+#define MMEA1_SDP_TAG_RESERVE1__VC7__SHIFT 0x18
+#define MMEA1_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL
+#define MMEA1_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L
+#define MMEA1_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L
+#define MMEA1_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L
+//MMEA1_SDP_VCC_RESERVE0
+#define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0
+#define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6
+#define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc
+#define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12
+#define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18
+#define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL
+#define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L
+#define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L
+#define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L
+#define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L
+//MMEA1_SDP_VCC_RESERVE1
+#define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0
+#define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6
+#define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc
+#define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f
+#define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL
+#define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L
+#define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L
+#define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L
+//MMEA1_SDP_VCD_RESERVE0
+#define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0
+#define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6
+#define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc
+#define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12
+#define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18
+#define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL
+#define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L
+#define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L
+#define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L
+#define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L
+//MMEA1_SDP_VCD_RESERVE1
+#define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0
+#define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6
+#define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc
+#define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f
+#define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL
+#define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L
+#define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L
+#define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L
+//MMEA1_SDP_REQ_CNTL
+#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0
+#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1
+#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2
+#define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3
+#define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4
+#define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5
+#define MMEA1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6
+#define MMEA1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8
+#define MMEA1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa
+#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L
+#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L
+#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L
+#define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L
+#define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L
+#define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L
+#define MMEA1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L
+#define MMEA1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L
+#define MMEA1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L
+//MMEA1_MISC
+#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0
+#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1
+#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2
+#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3
+#define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4
+#define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5
+#define MMEA1_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6
+#define MMEA1_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7
+#define MMEA1_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8
+#define MMEA1_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9
+#define MMEA1_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa
+#define MMEA1_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb
+#define MMEA1_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc
+#define MMEA1_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd
+#define MMEA1_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe
+#define MMEA1_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf
+#define MMEA1_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11
+#define MMEA1_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13
+#define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15
+#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a
+#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b
+#define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c
+#define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d
+#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e
+#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f
+#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L
+#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L
+#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L
+#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L
+#define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L
+#define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L
+#define MMEA1_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L
+#define MMEA1_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L
+#define MMEA1_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L
+#define MMEA1_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L
+#define MMEA1_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L
+#define MMEA1_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L
+#define MMEA1_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L
+#define MMEA1_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L
+#define MMEA1_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L
+#define MMEA1_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L
+#define MMEA1_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L
+#define MMEA1_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L
+#define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L
+#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L
+#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L
+#define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L
+#define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L
+#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L
+#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L
+//MMEA1_LATENCY_SAMPLING
+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0
+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1
+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2
+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3
+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4
+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5
+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6
+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7
+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8
+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9
+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa
+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb
+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc
+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd
+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe
+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16
+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L
+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L
+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L
+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L
+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L
+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L
+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L
+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L
+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L
+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L
+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L
+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L
+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L
+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L
+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L
+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L
+//MMEA1_PERFCOUNTER_LO
+#define MMEA1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MMEA1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//MMEA1_PERFCOUNTER_HI
+#define MMEA1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MMEA1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//MMEA1_PERFCOUNTER0_CFG
+#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMEA1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MMEA1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MMEA1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMEA1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMEA1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define MMEA1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//MMEA1_PERFCOUNTER1_CFG
+#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMEA1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MMEA1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MMEA1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMEA1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMEA1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define MMEA1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//MMEA1_PERFCOUNTER_RSLT_CNTL
+#define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+//MMEA1_EDC_CNT
+#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0
+#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2
+#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4
+#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6
+#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8
+#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa
+#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc
+#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe
+#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10
+#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12
+#define MMEA1_EDC_CNT__IOWR_DATAMEM_SEC_COUNT__SHIFT 0x14
+#define MMEA1_EDC_CNT__IOWR_DATAMEM_DED_COUNT__SHIFT 0x16
+#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x18
+#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x1a
+#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x1c
+#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1e
+#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
+#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
+#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
+#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
+#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
+#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
+#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L
+#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L
+#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L
+#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L
+#define MMEA1_EDC_CNT__IOWR_DATAMEM_SEC_COUNT_MASK 0x00300000L
+#define MMEA1_EDC_CNT__IOWR_DATAMEM_DED_COUNT_MASK 0x00C00000L
+#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x03000000L
+#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x0C000000L
+#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x30000000L
+#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0xC0000000L
+//MMEA1_EDC_CNT2
+#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0
+#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2
+#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4
+#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6
+#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8
+#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa
+#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc
+#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe
+#define MMEA1_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10
+#define MMEA1_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12
+#define MMEA1_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14
+#define MMEA1_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16
+#define MMEA1_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT 0x18
+#define MMEA1_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT 0x1a
+#define MMEA1_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT 0x1c
+#define MMEA1_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT 0x1e
+#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
+#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
+#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
+#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
+#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
+#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
+#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L
+#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L
+#define MMEA1_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L
+#define MMEA1_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L
+#define MMEA1_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L
+#define MMEA1_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L
+#define MMEA1_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK 0x03000000L
+#define MMEA1_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK 0x0C000000L
+#define MMEA1_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK 0x30000000L
+#define MMEA1_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK 0xC0000000L
+//MMEA1_DSM_CNTL
+#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3
+#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9
+#define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb
+#define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc
+#define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
+#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf
+#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11
+#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12
+#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14
+#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15
+#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17
+#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
+#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L
+#define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
+#define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L
+#define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
+#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L
+#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L
+#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L
+#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L
+#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L
+#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L
+//MMEA1_DSM_CNTLA
+#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3
+#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9
+#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb
+#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc
+#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
+#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf
+#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11
+#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12
+#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14
+#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
+#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L
+#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
+#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L
+#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
+#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L
+#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L
+#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L
+#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L
+//MMEA1_DSM_CNTLB
+//MMEA1_DSM_CNTL2
+#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5
+#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8
+#define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb
+#define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe
+#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11
+#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14
+#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15
+#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17
+#define MMEA1_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
+#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L
+#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L
+#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L
+#define MMEA1_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
+//MMEA1_DSM_CNTL2A
+#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5
+#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8
+#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb
+#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe
+#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11
+#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14
+#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L
+//MMEA1_DSM_CNTL2B
+//MMEA1_CGTT_CLK_CTRL
+#define MMEA1_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define MMEA1_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc
+#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14
+#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15
+#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16
+#define MMEA1_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17
+#define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c
+#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d
+#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e
+#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f
+#define MMEA1_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define MMEA1_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L
+#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L
+#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L
+#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L
+#define MMEA1_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L
+#define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L
+#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L
+#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L
+#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L
+//MMEA1_EDC_MODE
+#define MMEA1_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10
+#define MMEA1_EDC_MODE__GATE_FUE__SHIFT 0x11
+#define MMEA1_EDC_MODE__DED_MODE__SHIFT 0x14
+#define MMEA1_EDC_MODE__PROP_FED__SHIFT 0x1d
+#define MMEA1_EDC_MODE__BYPASS__SHIFT 0x1f
+#define MMEA1_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L
+#define MMEA1_EDC_MODE__GATE_FUE_MASK 0x00020000L
+#define MMEA1_EDC_MODE__DED_MODE_MASK 0x00300000L
+#define MMEA1_EDC_MODE__PROP_FED_MASK 0x20000000L
+#define MMEA1_EDC_MODE__BYPASS_MASK 0x80000000L
+//MMEA1_ERR_STATUS
+#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0
+#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4
+#define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8
+#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa
+#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb
+#define MMEA1_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc
+#define MMEA1_ERR_STATUS__FUE_FLAG__SHIFT 0xd
+#define MMEA1_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe
+#define MMEA1_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf
+#define MMEA1_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10
+#define MMEA1_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11
+#define MMEA1_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12
+#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL
+#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L
+#define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L
+#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L
+#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L
+#define MMEA1_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L
+#define MMEA1_ERR_STATUS__FUE_FLAG_MASK 0x00002000L
+#define MMEA1_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L
+#define MMEA1_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L
+#define MMEA1_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L
+#define MMEA1_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L
+#define MMEA1_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L
+//MMEA1_MISC2
+#define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0
+#define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1
+#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2
+#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7
+#define MMEA1_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc
+#define MMEA1_MISC2__RRET_SWAP_MODE__SHIFT 0xd
+#define MMEA1_MISC2__BLOCK_REQUESTS__SHIFT 0xe
+#define MMEA1_MISC2__REQUESTS_BLOCKED__SHIFT 0xf
+#define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L
+#define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L
+#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL
+#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L
+#define MMEA1_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L
+#define MMEA1_MISC2__RRET_SWAP_MODE_MASK 0x00002000L
+#define MMEA1_MISC2__BLOCK_REQUESTS_MASK 0x00004000L
+#define MMEA1_MISC2__REQUESTS_BLOCKED_MASK 0x00008000L
+//MMEA1_ADDRDEC_SELECT
+#define MMEA1_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0
+#define MMEA1_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5
+#define MMEA1_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa
+#define MMEA1_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf
+#define MMEA1_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL
+#define MMEA1_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L
+#define MMEA1_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L
+#define MMEA1_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L
+//MMEA1_EDC_CNT3
+#define MMEA1_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0
+#define MMEA1_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2
+#define MMEA1_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4
+#define MMEA1_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6
+#define MMEA1_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0x8
+#define MMEA1_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xa
+#define MMEA1_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L
+#define MMEA1_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL
+#define MMEA1_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L
+#define MMEA1_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
+#define MMEA1_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000300L
+#define MMEA1_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00000C00L
+//MMEA1_MISC_AON
+#define MMEA1_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0
+#define MMEA1_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2
+#define MMEA1_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L
+#define MMEA1_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L
+
+
+// addressBlock: mmhub_ea_mmeadec2
+//MMEA2_DRAM_RD_CLI2GRP_MAP0
+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA2_DRAM_RD_CLI2GRP_MAP1
+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA2_DRAM_WR_CLI2GRP_MAP0
+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA2_DRAM_WR_CLI2GRP_MAP1
+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA2_DRAM_RD_GRP2VC_MAP
+#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
+#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
+#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
+#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
+#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
+#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
+#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
+#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
+//MMEA2_DRAM_WR_GRP2VC_MAP
+#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
+#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
+#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
+#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
+#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
+#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
+#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
+#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
+//MMEA2_DRAM_RD_LAZY
+#define MMEA2_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0
+#define MMEA2_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3
+#define MMEA2_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6
+#define MMEA2_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9
+#define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
+#define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
+#define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b
+#define MMEA2_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L
+#define MMEA2_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L
+#define MMEA2_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L
+#define MMEA2_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L
+#define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
+#define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
+#define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L
+//MMEA2_DRAM_WR_LAZY
+#define MMEA2_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0
+#define MMEA2_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3
+#define MMEA2_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6
+#define MMEA2_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9
+#define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
+#define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
+#define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b
+#define MMEA2_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L
+#define MMEA2_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L
+#define MMEA2_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L
+#define MMEA2_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L
+#define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
+#define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
+#define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L
+//MMEA2_DRAM_RD_CAM_CNTL
+#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
+#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
+#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
+#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
+#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
+#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
+#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
+#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
+#define MMEA2_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c
+#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
+#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
+#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
+#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
+#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
+#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
+#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
+#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
+#define MMEA2_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L
+//MMEA2_DRAM_WR_CAM_CNTL
+#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
+#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
+#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
+#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
+#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
+#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
+#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
+#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
+#define MMEA2_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c
+#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
+#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
+#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
+#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
+#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
+#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
+#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
+#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
+#define MMEA2_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L
+//MMEA2_DRAM_PAGE_BURST
+#define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0
+#define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8
+#define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10
+#define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18
+#define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL
+#define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
+#define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
+#define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L
+//MMEA2_DRAM_RD_PRI_AGE
+#define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA2_DRAM_WR_PRI_AGE
+#define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA2_DRAM_RD_PRI_QUEUING
+#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA2_DRAM_WR_PRI_QUEUING
+#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA2_DRAM_RD_PRI_FIXED
+#define MMEA2_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA2_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA2_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA2_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA2_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA2_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA2_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA2_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA2_DRAM_WR_PRI_FIXED
+#define MMEA2_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA2_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA2_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA2_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA2_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA2_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA2_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA2_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA2_DRAM_RD_PRI_URGENCY
+#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA2_DRAM_WR_PRI_URGENCY
+#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA2_DRAM_RD_PRI_QUANT_PRI1
+#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA2_DRAM_RD_PRI_QUANT_PRI2
+#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA2_DRAM_RD_PRI_QUANT_PRI3
+#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA2_DRAM_WR_PRI_QUANT_PRI1
+#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA2_DRAM_WR_PRI_QUANT_PRI2
+#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA2_DRAM_WR_PRI_QUANT_PRI3
+#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA2_GMI_RD_CLI2GRP_MAP0
+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA2_GMI_RD_CLI2GRP_MAP1
+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA2_GMI_WR_CLI2GRP_MAP0
+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA2_GMI_WR_CLI2GRP_MAP1
+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA2_GMI_RD_GRP2VC_MAP
+#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
+#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
+#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
+#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
+#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
+#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
+#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
+#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
+//MMEA2_GMI_WR_GRP2VC_MAP
+#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
+#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
+#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
+#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
+#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
+#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
+#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
+#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
+//MMEA2_GMI_RD_LAZY
+#define MMEA2_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0
+#define MMEA2_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3
+#define MMEA2_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6
+#define MMEA2_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9
+#define MMEA2_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
+#define MMEA2_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
+#define MMEA2_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b
+#define MMEA2_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L
+#define MMEA2_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L
+#define MMEA2_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L
+#define MMEA2_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L
+#define MMEA2_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
+#define MMEA2_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
+#define MMEA2_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L
+//MMEA2_GMI_WR_LAZY
+#define MMEA2_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0
+#define MMEA2_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3
+#define MMEA2_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6
+#define MMEA2_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9
+#define MMEA2_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
+#define MMEA2_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
+#define MMEA2_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b
+#define MMEA2_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L
+#define MMEA2_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L
+#define MMEA2_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L
+#define MMEA2_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L
+#define MMEA2_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
+#define MMEA2_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
+#define MMEA2_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L
+//MMEA2_GMI_RD_CAM_CNTL
+#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
+#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
+#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
+#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
+#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
+#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
+#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
+#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
+#define MMEA2_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c
+#define MMEA2_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d
+#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
+#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
+#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
+#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
+#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
+#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
+#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
+#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
+#define MMEA2_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L
+#define MMEA2_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L
+//MMEA2_GMI_WR_CAM_CNTL
+#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
+#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
+#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
+#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
+#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
+#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
+#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
+#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
+#define MMEA2_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c
+#define MMEA2_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d
+#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
+#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
+#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
+#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
+#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
+#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
+#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
+#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
+#define MMEA2_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L
+#define MMEA2_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L
+//MMEA2_GMI_PAGE_BURST
+#define MMEA2_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0
+#define MMEA2_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8
+#define MMEA2_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10
+#define MMEA2_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18
+#define MMEA2_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL
+#define MMEA2_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
+#define MMEA2_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
+#define MMEA2_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L
+//MMEA2_GMI_RD_PRI_AGE
+#define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA2_GMI_WR_PRI_AGE
+#define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA2_GMI_RD_PRI_QUEUING
+#define MMEA2_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA2_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA2_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA2_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA2_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA2_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA2_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA2_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA2_GMI_WR_PRI_QUEUING
+#define MMEA2_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA2_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA2_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA2_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA2_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA2_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA2_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA2_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA2_GMI_RD_PRI_FIXED
+#define MMEA2_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA2_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA2_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA2_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA2_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA2_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA2_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA2_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA2_GMI_WR_PRI_FIXED
+#define MMEA2_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA2_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA2_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA2_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA2_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA2_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA2_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA2_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA2_GMI_RD_PRI_URGENCY
+#define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA2_GMI_WR_PRI_URGENCY
+#define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA2_GMI_RD_PRI_URGENCY_MASKING
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L
+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L
+//MMEA2_GMI_WR_PRI_URGENCY_MASKING
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L
+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L
+//MMEA2_GMI_RD_PRI_QUANT_PRI1
+#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA2_GMI_RD_PRI_QUANT_PRI2
+#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA2_GMI_RD_PRI_QUANT_PRI3
+#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA2_GMI_WR_PRI_QUANT_PRI1
+#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA2_GMI_WR_PRI_QUANT_PRI2
+#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA2_GMI_WR_PRI_QUANT_PRI3
+#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA2_ADDRNORM_BASE_ADDR0
+#define MMEA2_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA2_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA2_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc
+#define MMEA2_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA2_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA2_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA2_ADDRNORM_LIMIT_ADDR0
+#define MMEA2_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA2_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc
+#define MMEA2_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA2_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA2_ADDRNORM_BASE_ADDR1
+#define MMEA2_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA2_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA2_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc
+#define MMEA2_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA2_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA2_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA2_ADDRNORM_LIMIT_ADDR1
+#define MMEA2_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA2_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc
+#define MMEA2_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA2_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA2_ADDRNORM_OFFSET_ADDR1
+#define MMEA2_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0
+#define MMEA2_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0xc
+#define MMEA2_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L
+#define MMEA2_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0x00FFF000L
+//MMEA2_ADDRNORM_BASE_ADDR2
+#define MMEA2_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA2_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA2_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc
+#define MMEA2_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA2_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA2_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA2_ADDRNORM_LIMIT_ADDR2
+#define MMEA2_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA2_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc
+#define MMEA2_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA2_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA2_ADDRNORM_BASE_ADDR3
+#define MMEA2_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA2_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA2_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc
+#define MMEA2_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA2_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA2_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA2_ADDRNORM_LIMIT_ADDR3
+#define MMEA2_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA2_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc
+#define MMEA2_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA2_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA2_ADDRNORM_OFFSET_ADDR3
+#define MMEA2_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0
+#define MMEA2_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0xc
+#define MMEA2_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L
+#define MMEA2_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0x00FFF000L
+//MMEA2_ADDRNORM_MEGABASE_ADDR0
+#define MMEA2_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA2_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA2_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA2_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA2_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA2_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA2_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR__SHIFT 0xc
+#define MMEA2_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA2_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA2_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA2_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA2_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA2_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA2_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA2_ADDRNORM_MEGALIMIT_ADDR0
+#define MMEA2_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA2_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc
+#define MMEA2_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA2_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA2_ADDRNORM_MEGABASE_ADDR1
+#define MMEA2_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA2_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA2_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA2_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA2_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA2_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA2_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR__SHIFT 0xc
+#define MMEA2_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA2_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA2_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA2_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA2_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA2_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA2_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA2_ADDRNORM_MEGALIMIT_ADDR1
+#define MMEA2_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA2_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc
+#define MMEA2_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA2_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA2_ADDRNORMDRAM_HOLE_CNTL
+#define MMEA2_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0
+#define MMEA2_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7
+#define MMEA2_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L
+#define MMEA2_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L
+//MMEA2_ADDRNORMGMI_HOLE_CNTL
+#define MMEA2_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0
+#define MMEA2_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7
+#define MMEA2_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L
+#define MMEA2_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L
+//MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG
+#define MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0
+#define MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6
+#define MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL
+#define MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L
+//MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG
+#define MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0
+#define MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6
+#define MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL
+#define MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L
+//MMEA2_ADDRDEC_BANK_CFG
+#define MMEA2_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0
+#define MMEA2_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6
+#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc
+#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf
+#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12
+#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13
+#define MMEA2_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL
+#define MMEA2_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L
+#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L
+#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L
+#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L
+#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L
+//MMEA2_ADDRDEC_MISC_CFG
+#define MMEA2_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0
+#define MMEA2_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1
+#define MMEA2_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2
+#define MMEA2_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8
+#define MMEA2_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9
+#define MMEA2_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc
+#define MMEA2_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11
+#define MMEA2_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16
+#define MMEA2_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18
+#define MMEA2_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a
+#define MMEA2_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d
+#define MMEA2_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L
+#define MMEA2_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L
+#define MMEA2_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L
+#define MMEA2_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L
+#define MMEA2_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L
+#define MMEA2_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L
+#define MMEA2_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L
+#define MMEA2_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L
+#define MMEA2_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L
+#define MMEA2_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L
+#define MMEA2_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L
+//MMEA2_ADDRDECDRAM_HARVEST_ENABLE
+#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0
+#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1
+#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2
+#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3
+#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4
+#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5
+#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L
+#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L
+#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L
+#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L
+#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L
+#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L
+//MMEA2_ADDRDECGMI_HARVEST_ENABLE
+#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0
+#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1
+#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2
+#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3
+#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4
+#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5
+#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L
+#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L
+#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L
+#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L
+#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L
+#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L
+//MMEA2_ADDRDEC0_BASE_ADDR_CS0
+#define MMEA2_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0
+#define MMEA2_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
+#define MMEA2_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L
+#define MMEA2_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC0_BASE_ADDR_CS1
+#define MMEA2_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0
+#define MMEA2_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
+#define MMEA2_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L
+#define MMEA2_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC0_BASE_ADDR_CS2
+#define MMEA2_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0
+#define MMEA2_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
+#define MMEA2_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L
+#define MMEA2_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC0_BASE_ADDR_CS3
+#define MMEA2_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0
+#define MMEA2_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
+#define MMEA2_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L
+#define MMEA2_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC0_BASE_ADDR_SECCS0
+#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0
+#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
+#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L
+#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC0_BASE_ADDR_SECCS1
+#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0
+#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
+#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L
+#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC0_BASE_ADDR_SECCS2
+#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0
+#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
+#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L
+#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC0_BASE_ADDR_SECCS3
+#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0
+#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
+#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L
+#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC0_ADDR_MASK_CS01
+#define MMEA2_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
+#define MMEA2_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC0_ADDR_MASK_CS23
+#define MMEA2_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
+#define MMEA2_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC0_ADDR_MASK_SECCS01
+#define MMEA2_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
+#define MMEA2_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC0_ADDR_MASK_SECCS23
+#define MMEA2_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
+#define MMEA2_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC0_ADDR_CFG_CS01
+#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
+#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
+#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
+#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
+#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
+#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f
+#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
+#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
+#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
+#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L
+//MMEA2_ADDRDEC0_ADDR_CFG_CS23
+#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
+#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
+#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
+#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
+#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
+#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f
+#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
+#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
+#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
+#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L
+//MMEA2_ADDRDEC0_ADDR_SEL_CS01
+#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0
+#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4
+#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8
+#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc
+#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10
+#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
+#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
+#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
+#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
+#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
+#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
+#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L
+#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
+#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
+//MMEA2_ADDRDEC0_ADDR_SEL_CS23
+#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0
+#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4
+#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8
+#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc
+#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10
+#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
+#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
+#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
+#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
+#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
+#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
+#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L
+#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
+#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
+//MMEA2_ADDRDEC0_ADDR_SEL2_CS01
+#define MMEA2_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0
+#define MMEA2_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA2_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL
+#define MMEA2_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L
+//MMEA2_ADDRDEC0_ADDR_SEL2_CS23
+#define MMEA2_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0
+#define MMEA2_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA2_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL
+#define MMEA2_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L
+//MMEA2_ADDRDEC0_COL_SEL_LO_CS01
+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0
+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4
+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8
+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc
+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10
+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14
+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18
+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
+//MMEA2_ADDRDEC0_COL_SEL_LO_CS23
+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0
+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4
+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8
+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc
+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10
+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14
+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18
+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
+//MMEA2_ADDRDEC0_COL_SEL_HI_CS01
+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0
+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4
+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8
+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc
+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10
+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14
+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18
+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
+//MMEA2_ADDRDEC0_COL_SEL_HI_CS23
+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0
+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4
+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8
+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc
+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10
+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14
+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18
+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
+//MMEA2_ADDRDEC0_RM_SEL_CS01
+#define MMEA2_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0
+#define MMEA2_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4
+#define MMEA2_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8
+#define MMEA2_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA2_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA2_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA2_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL
+#define MMEA2_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L
+#define MMEA2_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L
+#define MMEA2_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA2_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA2_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA2_ADDRDEC0_RM_SEL_CS23
+#define MMEA2_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0
+#define MMEA2_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4
+#define MMEA2_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8
+#define MMEA2_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA2_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA2_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA2_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL
+#define MMEA2_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L
+#define MMEA2_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L
+#define MMEA2_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA2_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA2_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA2_ADDRDEC0_RM_SEL_SECCS01
+#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0
+#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4
+#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8
+#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
+#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
+#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
+#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
+#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA2_ADDRDEC0_RM_SEL_SECCS23
+#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0
+#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4
+#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8
+#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
+#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
+#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
+#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
+#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA2_ADDRDEC1_BASE_ADDR_CS0
+#define MMEA2_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0
+#define MMEA2_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
+#define MMEA2_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L
+#define MMEA2_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC1_BASE_ADDR_CS1
+#define MMEA2_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0
+#define MMEA2_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
+#define MMEA2_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L
+#define MMEA2_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC1_BASE_ADDR_CS2
+#define MMEA2_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0
+#define MMEA2_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
+#define MMEA2_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L
+#define MMEA2_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC1_BASE_ADDR_CS3
+#define MMEA2_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0
+#define MMEA2_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
+#define MMEA2_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L
+#define MMEA2_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC1_BASE_ADDR_SECCS0
+#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0
+#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
+#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L
+#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC1_BASE_ADDR_SECCS1
+#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0
+#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
+#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L
+#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC1_BASE_ADDR_SECCS2
+#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0
+#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
+#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L
+#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC1_BASE_ADDR_SECCS3
+#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0
+#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
+#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L
+#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC1_ADDR_MASK_CS01
+#define MMEA2_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
+#define MMEA2_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC1_ADDR_MASK_CS23
+#define MMEA2_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
+#define MMEA2_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC1_ADDR_MASK_SECCS01
+#define MMEA2_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
+#define MMEA2_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC1_ADDR_MASK_SECCS23
+#define MMEA2_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
+#define MMEA2_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC1_ADDR_CFG_CS01
+#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
+#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
+#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
+#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
+#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
+#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f
+#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
+#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
+#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
+#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L
+//MMEA2_ADDRDEC1_ADDR_CFG_CS23
+#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
+#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
+#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
+#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
+#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
+#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f
+#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
+#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
+#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
+#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L
+//MMEA2_ADDRDEC1_ADDR_SEL_CS01
+#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0
+#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4
+#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8
+#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc
+#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10
+#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
+#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
+#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
+#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
+#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
+#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
+#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L
+#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
+#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
+//MMEA2_ADDRDEC1_ADDR_SEL_CS23
+#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0
+#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4
+#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8
+#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc
+#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10
+#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
+#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
+#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
+#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
+#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
+#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
+#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L
+#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
+#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
+//MMEA2_ADDRDEC1_ADDR_SEL2_CS01
+#define MMEA2_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0
+#define MMEA2_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA2_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL
+#define MMEA2_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L
+//MMEA2_ADDRDEC1_ADDR_SEL2_CS23
+#define MMEA2_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0
+#define MMEA2_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA2_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL
+#define MMEA2_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L
+//MMEA2_ADDRDEC1_COL_SEL_LO_CS01
+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0
+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4
+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8
+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc
+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10
+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14
+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18
+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
+//MMEA2_ADDRDEC1_COL_SEL_LO_CS23
+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0
+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4
+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8
+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc
+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10
+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14
+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18
+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
+//MMEA2_ADDRDEC1_COL_SEL_HI_CS01
+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0
+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4
+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8
+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc
+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10
+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14
+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18
+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
+//MMEA2_ADDRDEC1_COL_SEL_HI_CS23
+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0
+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4
+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8
+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc
+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10
+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14
+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18
+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
+//MMEA2_ADDRDEC1_RM_SEL_CS01
+#define MMEA2_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0
+#define MMEA2_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4
+#define MMEA2_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8
+#define MMEA2_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA2_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA2_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA2_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL
+#define MMEA2_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L
+#define MMEA2_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L
+#define MMEA2_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA2_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA2_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA2_ADDRDEC1_RM_SEL_CS23
+#define MMEA2_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0
+#define MMEA2_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4
+#define MMEA2_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8
+#define MMEA2_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA2_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA2_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA2_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL
+#define MMEA2_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L
+#define MMEA2_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L
+#define MMEA2_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA2_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA2_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA2_ADDRDEC1_RM_SEL_SECCS01
+#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0
+#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4
+#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8
+#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
+#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
+#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
+#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
+#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA2_ADDRDEC1_RM_SEL_SECCS23
+#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0
+#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4
+#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8
+#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
+#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
+#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
+#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
+#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA2_ADDRDEC2_BASE_ADDR_CS0
+#define MMEA2_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0
+#define MMEA2_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
+#define MMEA2_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L
+#define MMEA2_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC2_BASE_ADDR_CS1
+#define MMEA2_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0
+#define MMEA2_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
+#define MMEA2_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L
+#define MMEA2_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC2_BASE_ADDR_CS2
+#define MMEA2_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0
+#define MMEA2_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
+#define MMEA2_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L
+#define MMEA2_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC2_BASE_ADDR_CS3
+#define MMEA2_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0
+#define MMEA2_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
+#define MMEA2_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L
+#define MMEA2_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC2_BASE_ADDR_SECCS0
+#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0
+#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
+#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L
+#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC2_BASE_ADDR_SECCS1
+#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0
+#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
+#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L
+#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC2_BASE_ADDR_SECCS2
+#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0
+#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
+#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L
+#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC2_BASE_ADDR_SECCS3
+#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0
+#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
+#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L
+#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC2_ADDR_MASK_CS01
+#define MMEA2_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
+#define MMEA2_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC2_ADDR_MASK_CS23
+#define MMEA2_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
+#define MMEA2_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC2_ADDR_MASK_SECCS01
+#define MMEA2_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
+#define MMEA2_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC2_ADDR_MASK_SECCS23
+#define MMEA2_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
+#define MMEA2_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA2_ADDRDEC2_ADDR_CFG_CS01
+#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
+#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
+#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
+#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
+#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
+#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f
+#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
+#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
+#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
+#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L
+//MMEA2_ADDRDEC2_ADDR_CFG_CS23
+#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
+#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
+#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
+#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
+#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
+#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f
+#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
+#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
+#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
+#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L
+//MMEA2_ADDRDEC2_ADDR_SEL_CS01
+#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0
+#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4
+#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8
+#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc
+#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10
+#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
+#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
+#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
+#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
+#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
+#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
+#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L
+#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
+#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
+//MMEA2_ADDRDEC2_ADDR_SEL_CS23
+#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0
+#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4
+#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8
+#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc
+#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10
+#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
+#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
+#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
+#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
+#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
+#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
+#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L
+#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
+#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
+//MMEA2_ADDRDEC2_ADDR_SEL2_CS01
+#define MMEA2_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0
+#define MMEA2_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA2_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL
+#define MMEA2_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L
+//MMEA2_ADDRDEC2_ADDR_SEL2_CS23
+#define MMEA2_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0
+#define MMEA2_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA2_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL
+#define MMEA2_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L
+//MMEA2_ADDRDEC2_COL_SEL_LO_CS01
+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0
+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4
+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8
+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc
+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10
+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14
+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18
+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
+//MMEA2_ADDRDEC2_COL_SEL_LO_CS23
+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0
+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4
+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8
+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc
+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10
+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14
+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18
+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
+//MMEA2_ADDRDEC2_COL_SEL_HI_CS01
+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0
+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4
+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8
+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc
+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10
+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14
+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18
+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
+//MMEA2_ADDRDEC2_COL_SEL_HI_CS23
+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0
+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4
+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8
+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc
+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10
+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14
+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18
+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
+//MMEA2_ADDRDEC2_RM_SEL_CS01
+#define MMEA2_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0
+#define MMEA2_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4
+#define MMEA2_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8
+#define MMEA2_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA2_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA2_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA2_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL
+#define MMEA2_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L
+#define MMEA2_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L
+#define MMEA2_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA2_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA2_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA2_ADDRDEC2_RM_SEL_CS23
+#define MMEA2_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0
+#define MMEA2_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4
+#define MMEA2_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8
+#define MMEA2_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA2_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA2_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA2_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL
+#define MMEA2_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L
+#define MMEA2_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L
+#define MMEA2_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA2_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA2_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA2_ADDRDEC2_RM_SEL_SECCS01
+#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0
+#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4
+#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8
+#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
+#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
+#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
+#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
+#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA2_ADDRDEC2_RM_SEL_SECCS23
+#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0
+#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4
+#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8
+#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
+#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
+#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
+#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
+#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA2_ADDRNORMDRAM_GLOBAL_CNTL
+//MMEA2_ADDRNORMGMI_GLOBAL_CNTL
+//MMEA2_ADDRNORM_MEGACONTROL_ADDR0
+#define MMEA2_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0
+#define MMEA2_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL
+//MMEA2_ADDRNORM_MEGACONTROL_ADDR1
+#define MMEA2_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0
+#define MMEA2_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL
+//MMEA2_ADDRNORMDRAM_MASKING
+#define MMEA2_ADDRNORMDRAM_MASKING__ADDRHI_MASK__SHIFT 0x0
+#define MMEA2_ADDRNORMDRAM_MASKING__ADDRHI_MASK_MASK 0x00000FFFL
+//MMEA2_ADDRNORMGMI_MASKING
+#define MMEA2_ADDRNORMGMI_MASKING__ADDRHI_MASK__SHIFT 0x0
+#define MMEA2_ADDRNORMGMI_MASKING__ADDRHI_MASK_MASK 0x00000FFFL
+//MMEA2_IO_RD_CLI2GRP_MAP0
+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA2_IO_RD_CLI2GRP_MAP1
+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA2_IO_WR_CLI2GRP_MAP0
+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA2_IO_WR_CLI2GRP_MAP1
+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA2_IO_RD_COMBINE_FLUSH
+#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0
+#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4
+#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8
+#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc
+#define MMEA2_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10
+#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL
+#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L
+#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L
+#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L
+#define MMEA2_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L
+//MMEA2_IO_WR_COMBINE_FLUSH
+#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0
+#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4
+#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8
+#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc
+#define MMEA2_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10
+#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL
+#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L
+#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L
+#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L
+#define MMEA2_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L
+//MMEA2_IO_GROUP_BURST
+#define MMEA2_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0
+#define MMEA2_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8
+#define MMEA2_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10
+#define MMEA2_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18
+#define MMEA2_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL
+#define MMEA2_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
+#define MMEA2_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
+#define MMEA2_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L
+//MMEA2_IO_RD_PRI_AGE
+#define MMEA2_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA2_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA2_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA2_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA2_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA2_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA2_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA2_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA2_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA2_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA2_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA2_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA2_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA2_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA2_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA2_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA2_IO_WR_PRI_AGE
+#define MMEA2_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA2_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA2_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA2_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA2_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA2_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA2_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA2_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA2_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA2_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA2_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA2_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA2_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA2_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA2_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA2_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA2_IO_RD_PRI_QUEUING
+#define MMEA2_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA2_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA2_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA2_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA2_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA2_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA2_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA2_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA2_IO_WR_PRI_QUEUING
+#define MMEA2_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA2_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA2_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA2_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA2_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA2_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA2_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA2_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA2_IO_RD_PRI_FIXED
+#define MMEA2_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA2_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA2_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA2_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA2_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA2_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA2_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA2_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA2_IO_WR_PRI_FIXED
+#define MMEA2_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA2_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA2_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA2_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA2_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA2_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA2_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA2_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA2_IO_RD_PRI_URGENCY
+#define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA2_IO_WR_PRI_URGENCY
+#define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA2_IO_RD_PRI_URGENCY_MASKING
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L
+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L
+//MMEA2_IO_WR_PRI_URGENCY_MASKING
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L
+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L
+//MMEA2_IO_RD_PRI_QUANT_PRI1
+#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA2_IO_RD_PRI_QUANT_PRI2
+#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA2_IO_RD_PRI_QUANT_PRI3
+#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA2_IO_WR_PRI_QUANT_PRI1
+#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA2_IO_WR_PRI_QUANT_PRI2
+#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA2_IO_WR_PRI_QUANT_PRI3
+#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA2_SDP_ARB_DRAM
+#define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0
+#define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8
+#define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10
+#define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11
+#define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12
+#define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13
+#define MMEA2_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14
+#define MMEA2_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15
+#define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL
+#define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L
+#define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L
+#define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L
+#define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L
+#define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L
+#define MMEA2_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L
+#define MMEA2_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L
+//MMEA2_SDP_ARB_GMI
+#define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0
+#define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8
+#define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10
+#define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11
+#define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12
+#define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13
+#define MMEA2_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14
+#define MMEA2_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15
+#define MMEA2_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16
+#define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL
+#define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L
+#define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L
+#define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L
+#define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L
+#define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L
+#define MMEA2_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L
+#define MMEA2_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L
+#define MMEA2_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L
+//MMEA2_SDP_ARB_FINAL
+#define MMEA2_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0
+#define MMEA2_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5
+#define MMEA2_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa
+#define MMEA2_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf
+#define MMEA2_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11
+#define MMEA2_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12
+#define MMEA2_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13
+#define MMEA2_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14
+#define MMEA2_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15
+#define MMEA2_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16
+#define MMEA2_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17
+#define MMEA2_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18
+#define MMEA2_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19
+#define MMEA2_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a
+#define MMEA2_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b
+#define MMEA2_SDP_ARB_FINAL__DRAM_RD_THROTTLE__SHIFT 0x1c
+#define MMEA2_SDP_ARB_FINAL__DRAM_WR_THROTTLE__SHIFT 0x1d
+#define MMEA2_SDP_ARB_FINAL__GMI_RD_THROTTLE__SHIFT 0x1e
+#define MMEA2_SDP_ARB_FINAL__GMI_WR_THROTTLE__SHIFT 0x1f
+#define MMEA2_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL
+#define MMEA2_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L
+#define MMEA2_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L
+#define MMEA2_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L
+#define MMEA2_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L
+#define MMEA2_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L
+#define MMEA2_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L
+#define MMEA2_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L
+#define MMEA2_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L
+#define MMEA2_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L
+#define MMEA2_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L
+#define MMEA2_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L
+#define MMEA2_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L
+#define MMEA2_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L
+#define MMEA2_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L
+#define MMEA2_SDP_ARB_FINAL__DRAM_RD_THROTTLE_MASK 0x10000000L
+#define MMEA2_SDP_ARB_FINAL__DRAM_WR_THROTTLE_MASK 0x20000000L
+#define MMEA2_SDP_ARB_FINAL__GMI_RD_THROTTLE_MASK 0x40000000L
+#define MMEA2_SDP_ARB_FINAL__GMI_WR_THROTTLE_MASK 0x80000000L
+//MMEA2_SDP_DRAM_PRIORITY
+#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
+#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
+#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
+#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
+#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
+#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
+#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
+#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
+#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
+#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
+#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
+#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
+#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
+#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
+#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
+#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
+//MMEA2_SDP_GMI_PRIORITY
+#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
+#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
+#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
+#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
+#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
+#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
+#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
+#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
+#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
+#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
+#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
+#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
+#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
+#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
+#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
+#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
+//MMEA2_SDP_IO_PRIORITY
+#define MMEA2_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
+#define MMEA2_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
+#define MMEA2_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
+#define MMEA2_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
+#define MMEA2_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
+#define MMEA2_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
+#define MMEA2_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
+#define MMEA2_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
+#define MMEA2_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
+#define MMEA2_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
+#define MMEA2_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
+#define MMEA2_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
+#define MMEA2_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
+#define MMEA2_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
+#define MMEA2_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
+#define MMEA2_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
+//MMEA2_SDP_CREDITS
+#define MMEA2_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0
+#define MMEA2_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8
+#define MMEA2_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10
+#define MMEA2_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL
+#define MMEA2_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L
+#define MMEA2_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L
+//MMEA2_SDP_TAG_RESERVE0
+#define MMEA2_SDP_TAG_RESERVE0__VC0__SHIFT 0x0
+#define MMEA2_SDP_TAG_RESERVE0__VC1__SHIFT 0x8
+#define MMEA2_SDP_TAG_RESERVE0__VC2__SHIFT 0x10
+#define MMEA2_SDP_TAG_RESERVE0__VC3__SHIFT 0x18
+#define MMEA2_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL
+#define MMEA2_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L
+#define MMEA2_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L
+#define MMEA2_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L
+//MMEA2_SDP_TAG_RESERVE1
+#define MMEA2_SDP_TAG_RESERVE1__VC4__SHIFT 0x0
+#define MMEA2_SDP_TAG_RESERVE1__VC5__SHIFT 0x8
+#define MMEA2_SDP_TAG_RESERVE1__VC6__SHIFT 0x10
+#define MMEA2_SDP_TAG_RESERVE1__VC7__SHIFT 0x18
+#define MMEA2_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL
+#define MMEA2_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L
+#define MMEA2_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L
+#define MMEA2_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L
+//MMEA2_SDP_VCC_RESERVE0
+#define MMEA2_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0
+#define MMEA2_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6
+#define MMEA2_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc
+#define MMEA2_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12
+#define MMEA2_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18
+#define MMEA2_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL
+#define MMEA2_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L
+#define MMEA2_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L
+#define MMEA2_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L
+#define MMEA2_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L
+//MMEA2_SDP_VCC_RESERVE1
+#define MMEA2_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0
+#define MMEA2_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6
+#define MMEA2_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc
+#define MMEA2_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f
+#define MMEA2_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL
+#define MMEA2_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L
+#define MMEA2_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L
+#define MMEA2_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L
+//MMEA2_SDP_VCD_RESERVE0
+#define MMEA2_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0
+#define MMEA2_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6
+#define MMEA2_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc
+#define MMEA2_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12
+#define MMEA2_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18
+#define MMEA2_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL
+#define MMEA2_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L
+#define MMEA2_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L
+#define MMEA2_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L
+#define MMEA2_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L
+//MMEA2_SDP_VCD_RESERVE1
+#define MMEA2_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0
+#define MMEA2_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6
+#define MMEA2_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc
+#define MMEA2_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f
+#define MMEA2_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL
+#define MMEA2_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L
+#define MMEA2_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L
+#define MMEA2_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L
+//MMEA2_SDP_REQ_CNTL
+#define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0
+#define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1
+#define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2
+#define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3
+#define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4
+#define MMEA2_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5
+#define MMEA2_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6
+#define MMEA2_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8
+#define MMEA2_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa
+#define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L
+#define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L
+#define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L
+#define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L
+#define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L
+#define MMEA2_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L
+#define MMEA2_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L
+#define MMEA2_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L
+#define MMEA2_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L
+//MMEA2_MISC
+#define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0
+#define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1
+#define MMEA2_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2
+#define MMEA2_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3
+#define MMEA2_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4
+#define MMEA2_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5
+#define MMEA2_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6
+#define MMEA2_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7
+#define MMEA2_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8
+#define MMEA2_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9
+#define MMEA2_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa
+#define MMEA2_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb
+#define MMEA2_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc
+#define MMEA2_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd
+#define MMEA2_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe
+#define MMEA2_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf
+#define MMEA2_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11
+#define MMEA2_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13
+#define MMEA2_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15
+#define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a
+#define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b
+#define MMEA2_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c
+#define MMEA2_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d
+#define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e
+#define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f
+#define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L
+#define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L
+#define MMEA2_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L
+#define MMEA2_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L
+#define MMEA2_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L
+#define MMEA2_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L
+#define MMEA2_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L
+#define MMEA2_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L
+#define MMEA2_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L
+#define MMEA2_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L
+#define MMEA2_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L
+#define MMEA2_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L
+#define MMEA2_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L
+#define MMEA2_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L
+#define MMEA2_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L
+#define MMEA2_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L
+#define MMEA2_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L
+#define MMEA2_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L
+#define MMEA2_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L
+#define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L
+#define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L
+#define MMEA2_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L
+#define MMEA2_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L
+#define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L
+#define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L
+//MMEA2_LATENCY_SAMPLING
+#define MMEA2_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0
+#define MMEA2_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1
+#define MMEA2_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2
+#define MMEA2_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3
+#define MMEA2_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4
+#define MMEA2_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5
+#define MMEA2_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6
+#define MMEA2_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7
+#define MMEA2_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8
+#define MMEA2_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9
+#define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa
+#define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb
+#define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc
+#define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd
+#define MMEA2_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe
+#define MMEA2_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16
+#define MMEA2_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L
+#define MMEA2_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L
+#define MMEA2_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L
+#define MMEA2_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L
+#define MMEA2_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L
+#define MMEA2_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L
+#define MMEA2_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L
+#define MMEA2_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L
+#define MMEA2_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L
+#define MMEA2_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L
+#define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L
+#define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L
+#define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L
+#define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L
+#define MMEA2_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L
+#define MMEA2_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L
+//MMEA2_PERFCOUNTER_LO
+#define MMEA2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MMEA2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//MMEA2_PERFCOUNTER_HI
+#define MMEA2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MMEA2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MMEA2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define MMEA2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//MMEA2_PERFCOUNTER0_CFG
+#define MMEA2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MMEA2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMEA2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MMEA2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MMEA2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MMEA2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMEA2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMEA2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMEA2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define MMEA2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//MMEA2_PERFCOUNTER1_CFG
+#define MMEA2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MMEA2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMEA2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MMEA2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MMEA2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MMEA2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMEA2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMEA2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMEA2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define MMEA2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//MMEA2_PERFCOUNTER_RSLT_CNTL
+#define MMEA2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MMEA2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MMEA2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MMEA2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MMEA2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define MMEA2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define MMEA2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define MMEA2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+//MMEA2_EDC_CNT
+#define MMEA2_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0
+#define MMEA2_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2
+#define MMEA2_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4
+#define MMEA2_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6
+#define MMEA2_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8
+#define MMEA2_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa
+#define MMEA2_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc
+#define MMEA2_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe
+#define MMEA2_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10
+#define MMEA2_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12
+#define MMEA2_EDC_CNT__IOWR_DATAMEM_SEC_COUNT__SHIFT 0x14
+#define MMEA2_EDC_CNT__IOWR_DATAMEM_DED_COUNT__SHIFT 0x16
+#define MMEA2_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x18
+#define MMEA2_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x1a
+#define MMEA2_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x1c
+#define MMEA2_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1e
+#define MMEA2_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
+#define MMEA2_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
+#define MMEA2_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
+#define MMEA2_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
+#define MMEA2_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
+#define MMEA2_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
+#define MMEA2_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L
+#define MMEA2_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L
+#define MMEA2_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L
+#define MMEA2_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L
+#define MMEA2_EDC_CNT__IOWR_DATAMEM_SEC_COUNT_MASK 0x00300000L
+#define MMEA2_EDC_CNT__IOWR_DATAMEM_DED_COUNT_MASK 0x00C00000L
+#define MMEA2_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x03000000L
+#define MMEA2_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x0C000000L
+#define MMEA2_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x30000000L
+#define MMEA2_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0xC0000000L
+//MMEA2_EDC_CNT2
+#define MMEA2_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0
+#define MMEA2_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2
+#define MMEA2_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4
+#define MMEA2_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6
+#define MMEA2_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8
+#define MMEA2_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa
+#define MMEA2_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc
+#define MMEA2_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe
+#define MMEA2_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10
+#define MMEA2_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12
+#define MMEA2_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14
+#define MMEA2_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16
+#define MMEA2_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT 0x18
+#define MMEA2_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT 0x1a
+#define MMEA2_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT 0x1c
+#define MMEA2_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT 0x1e
+#define MMEA2_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
+#define MMEA2_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
+#define MMEA2_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
+#define MMEA2_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
+#define MMEA2_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
+#define MMEA2_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
+#define MMEA2_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L
+#define MMEA2_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L
+#define MMEA2_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L
+#define MMEA2_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L
+#define MMEA2_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L
+#define MMEA2_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L
+#define MMEA2_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK 0x03000000L
+#define MMEA2_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK 0x0C000000L
+#define MMEA2_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK 0x30000000L
+#define MMEA2_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK 0xC0000000L
+//MMEA2_DSM_CNTL
+#define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3
+#define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define MMEA2_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9
+#define MMEA2_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb
+#define MMEA2_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc
+#define MMEA2_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
+#define MMEA2_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf
+#define MMEA2_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11
+#define MMEA2_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12
+#define MMEA2_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14
+#define MMEA2_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15
+#define MMEA2_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17
+#define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
+#define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define MMEA2_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L
+#define MMEA2_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
+#define MMEA2_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L
+#define MMEA2_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
+#define MMEA2_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L
+#define MMEA2_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L
+#define MMEA2_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L
+#define MMEA2_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L
+#define MMEA2_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L
+#define MMEA2_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L
+//MMEA2_DSM_CNTLA
+#define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3
+#define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define MMEA2_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define MMEA2_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define MMEA2_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9
+#define MMEA2_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb
+#define MMEA2_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc
+#define MMEA2_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
+#define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf
+#define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11
+#define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12
+#define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14
+#define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
+#define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define MMEA2_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define MMEA2_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define MMEA2_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L
+#define MMEA2_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
+#define MMEA2_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L
+#define MMEA2_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
+#define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L
+#define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L
+#define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L
+#define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L
+//MMEA2_DSM_CNTLB
+//MMEA2_DSM_CNTL2
+#define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5
+#define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8
+#define MMEA2_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define MMEA2_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb
+#define MMEA2_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define MMEA2_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe
+#define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11
+#define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14
+#define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15
+#define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17
+#define MMEA2_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
+#define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define MMEA2_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define MMEA2_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define MMEA2_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define MMEA2_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L
+#define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L
+#define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L
+#define MMEA2_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
+//MMEA2_DSM_CNTL2A
+#define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5
+#define MMEA2_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define MMEA2_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8
+#define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb
+#define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe
+#define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11
+#define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14
+#define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define MMEA2_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define MMEA2_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L
+//MMEA2_DSM_CNTL2B
+//MMEA2_CGTT_CLK_CTRL
+#define MMEA2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define MMEA2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define MMEA2_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc
+#define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14
+#define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15
+#define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16
+#define MMEA2_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17
+#define MMEA2_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c
+#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d
+#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e
+#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f
+#define MMEA2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define MMEA2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define MMEA2_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L
+#define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L
+#define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L
+#define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L
+#define MMEA2_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L
+#define MMEA2_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L
+#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L
+#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L
+#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L
+//MMEA2_EDC_MODE
+#define MMEA2_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10
+#define MMEA2_EDC_MODE__GATE_FUE__SHIFT 0x11
+#define MMEA2_EDC_MODE__DED_MODE__SHIFT 0x14
+#define MMEA2_EDC_MODE__PROP_FED__SHIFT 0x1d
+#define MMEA2_EDC_MODE__BYPASS__SHIFT 0x1f
+#define MMEA2_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L
+#define MMEA2_EDC_MODE__GATE_FUE_MASK 0x00020000L
+#define MMEA2_EDC_MODE__DED_MODE_MASK 0x00300000L
+#define MMEA2_EDC_MODE__PROP_FED_MASK 0x20000000L
+#define MMEA2_EDC_MODE__BYPASS_MASK 0x80000000L
+//MMEA2_ERR_STATUS
+#define MMEA2_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0
+#define MMEA2_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4
+#define MMEA2_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8
+#define MMEA2_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa
+#define MMEA2_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb
+#define MMEA2_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc
+#define MMEA2_ERR_STATUS__FUE_FLAG__SHIFT 0xd
+#define MMEA2_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe
+#define MMEA2_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf
+#define MMEA2_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10
+#define MMEA2_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11
+#define MMEA2_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12
+#define MMEA2_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL
+#define MMEA2_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L
+#define MMEA2_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L
+#define MMEA2_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L
+#define MMEA2_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L
+#define MMEA2_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L
+#define MMEA2_ERR_STATUS__FUE_FLAG_MASK 0x00002000L
+#define MMEA2_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L
+#define MMEA2_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L
+#define MMEA2_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L
+#define MMEA2_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L
+#define MMEA2_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L
+//MMEA2_MISC2
+#define MMEA2_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0
+#define MMEA2_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1
+#define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2
+#define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7
+#define MMEA2_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc
+#define MMEA2_MISC2__RRET_SWAP_MODE__SHIFT 0xd
+#define MMEA2_MISC2__BLOCK_REQUESTS__SHIFT 0xe
+#define MMEA2_MISC2__REQUESTS_BLOCKED__SHIFT 0xf
+#define MMEA2_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L
+#define MMEA2_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L
+#define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL
+#define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L
+#define MMEA2_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L
+#define MMEA2_MISC2__RRET_SWAP_MODE_MASK 0x00002000L
+#define MMEA2_MISC2__BLOCK_REQUESTS_MASK 0x00004000L
+#define MMEA2_MISC2__REQUESTS_BLOCKED_MASK 0x00008000L
+//MMEA2_ADDRDEC_SELECT
+#define MMEA2_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0
+#define MMEA2_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5
+#define MMEA2_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa
+#define MMEA2_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf
+#define MMEA2_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL
+#define MMEA2_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L
+#define MMEA2_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L
+#define MMEA2_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L
+//MMEA2_EDC_CNT3
+#define MMEA2_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0
+#define MMEA2_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2
+#define MMEA2_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4
+#define MMEA2_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6
+#define MMEA2_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0x8
+#define MMEA2_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xa
+#define MMEA2_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L
+#define MMEA2_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL
+#define MMEA2_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L
+#define MMEA2_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
+#define MMEA2_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000300L
+#define MMEA2_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00000C00L
+//MMEA2_MISC_AON
+#define MMEA2_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0
+#define MMEA2_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2
+#define MMEA2_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L
+#define MMEA2_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L
+
+
+// addressBlock: mmhub_ea_mmeadec3
+//MMEA3_DRAM_RD_CLI2GRP_MAP0
+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA3_DRAM_RD_CLI2GRP_MAP1
+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA3_DRAM_WR_CLI2GRP_MAP0
+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA3_DRAM_WR_CLI2GRP_MAP1
+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA3_DRAM_RD_GRP2VC_MAP
+#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
+#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
+#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
+#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
+#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
+#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
+#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
+#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
+//MMEA3_DRAM_WR_GRP2VC_MAP
+#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
+#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
+#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
+#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
+#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
+#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
+#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
+#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
+//MMEA3_DRAM_RD_LAZY
+#define MMEA3_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0
+#define MMEA3_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3
+#define MMEA3_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6
+#define MMEA3_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9
+#define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
+#define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
+#define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b
+#define MMEA3_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L
+#define MMEA3_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L
+#define MMEA3_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L
+#define MMEA3_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L
+#define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
+#define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
+#define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L
+//MMEA3_DRAM_WR_LAZY
+#define MMEA3_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0
+#define MMEA3_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3
+#define MMEA3_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6
+#define MMEA3_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9
+#define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
+#define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
+#define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b
+#define MMEA3_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L
+#define MMEA3_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L
+#define MMEA3_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L
+#define MMEA3_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L
+#define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
+#define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
+#define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L
+//MMEA3_DRAM_RD_CAM_CNTL
+#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
+#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
+#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
+#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
+#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
+#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
+#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
+#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
+#define MMEA3_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c
+#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
+#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
+#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
+#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
+#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
+#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
+#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
+#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
+#define MMEA3_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L
+//MMEA3_DRAM_WR_CAM_CNTL
+#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
+#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
+#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
+#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
+#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
+#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
+#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
+#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
+#define MMEA3_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c
+#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
+#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
+#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
+#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
+#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
+#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
+#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
+#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
+#define MMEA3_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L
+//MMEA3_DRAM_PAGE_BURST
+#define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0
+#define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8
+#define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10
+#define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18
+#define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL
+#define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
+#define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
+#define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L
+//MMEA3_DRAM_RD_PRI_AGE
+#define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA3_DRAM_WR_PRI_AGE
+#define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA3_DRAM_RD_PRI_QUEUING
+#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA3_DRAM_WR_PRI_QUEUING
+#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA3_DRAM_RD_PRI_FIXED
+#define MMEA3_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA3_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA3_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA3_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA3_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA3_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA3_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA3_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA3_DRAM_WR_PRI_FIXED
+#define MMEA3_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA3_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA3_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA3_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA3_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA3_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA3_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA3_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA3_DRAM_RD_PRI_URGENCY
+#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA3_DRAM_WR_PRI_URGENCY
+#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA3_DRAM_RD_PRI_QUANT_PRI1
+#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA3_DRAM_RD_PRI_QUANT_PRI2
+#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA3_DRAM_RD_PRI_QUANT_PRI3
+#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA3_DRAM_WR_PRI_QUANT_PRI1
+#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA3_DRAM_WR_PRI_QUANT_PRI2
+#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA3_DRAM_WR_PRI_QUANT_PRI3
+#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA3_GMI_RD_CLI2GRP_MAP0
+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA3_GMI_RD_CLI2GRP_MAP1
+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA3_GMI_WR_CLI2GRP_MAP0
+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA3_GMI_WR_CLI2GRP_MAP1
+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA3_GMI_RD_GRP2VC_MAP
+#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
+#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
+#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
+#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
+#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
+#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
+#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
+#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
+//MMEA3_GMI_WR_GRP2VC_MAP
+#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
+#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
+#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
+#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
+#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
+#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
+#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
+#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
+//MMEA3_GMI_RD_LAZY
+#define MMEA3_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0
+#define MMEA3_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3
+#define MMEA3_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6
+#define MMEA3_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9
+#define MMEA3_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
+#define MMEA3_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
+#define MMEA3_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b
+#define MMEA3_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L
+#define MMEA3_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L
+#define MMEA3_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L
+#define MMEA3_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L
+#define MMEA3_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
+#define MMEA3_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
+#define MMEA3_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L
+//MMEA3_GMI_WR_LAZY
+#define MMEA3_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0
+#define MMEA3_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3
+#define MMEA3_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6
+#define MMEA3_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9
+#define MMEA3_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
+#define MMEA3_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
+#define MMEA3_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b
+#define MMEA3_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L
+#define MMEA3_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L
+#define MMEA3_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L
+#define MMEA3_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L
+#define MMEA3_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
+#define MMEA3_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
+#define MMEA3_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L
+//MMEA3_GMI_RD_CAM_CNTL
+#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
+#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
+#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
+#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
+#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
+#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
+#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
+#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
+#define MMEA3_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c
+#define MMEA3_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d
+#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
+#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
+#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
+#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
+#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
+#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
+#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
+#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
+#define MMEA3_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L
+#define MMEA3_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L
+//MMEA3_GMI_WR_CAM_CNTL
+#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
+#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
+#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
+#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
+#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
+#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
+#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
+#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
+#define MMEA3_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c
+#define MMEA3_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d
+#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
+#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
+#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
+#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
+#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
+#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
+#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
+#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
+#define MMEA3_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L
+#define MMEA3_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L
+//MMEA3_GMI_PAGE_BURST
+#define MMEA3_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0
+#define MMEA3_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8
+#define MMEA3_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10
+#define MMEA3_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18
+#define MMEA3_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL
+#define MMEA3_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
+#define MMEA3_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
+#define MMEA3_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L
+//MMEA3_GMI_RD_PRI_AGE
+#define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA3_GMI_WR_PRI_AGE
+#define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA3_GMI_RD_PRI_QUEUING
+#define MMEA3_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA3_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA3_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA3_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA3_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA3_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA3_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA3_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA3_GMI_WR_PRI_QUEUING
+#define MMEA3_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA3_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA3_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA3_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA3_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA3_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA3_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA3_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA3_GMI_RD_PRI_FIXED
+#define MMEA3_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA3_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA3_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA3_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA3_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA3_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA3_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA3_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA3_GMI_WR_PRI_FIXED
+#define MMEA3_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA3_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA3_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA3_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA3_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA3_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA3_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA3_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA3_GMI_RD_PRI_URGENCY
+#define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA3_GMI_WR_PRI_URGENCY
+#define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA3_GMI_RD_PRI_URGENCY_MASKING
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L
+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L
+//MMEA3_GMI_WR_PRI_URGENCY_MASKING
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L
+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L
+//MMEA3_GMI_RD_PRI_QUANT_PRI1
+#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA3_GMI_RD_PRI_QUANT_PRI2
+#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA3_GMI_RD_PRI_QUANT_PRI3
+#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA3_GMI_WR_PRI_QUANT_PRI1
+#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA3_GMI_WR_PRI_QUANT_PRI2
+#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA3_GMI_WR_PRI_QUANT_PRI3
+#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA3_ADDRNORM_BASE_ADDR0
+#define MMEA3_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA3_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA3_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc
+#define MMEA3_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA3_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA3_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA3_ADDRNORM_LIMIT_ADDR0
+#define MMEA3_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA3_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc
+#define MMEA3_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA3_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA3_ADDRNORM_BASE_ADDR1
+#define MMEA3_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA3_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA3_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc
+#define MMEA3_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA3_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA3_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA3_ADDRNORM_LIMIT_ADDR1
+#define MMEA3_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA3_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc
+#define MMEA3_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA3_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA3_ADDRNORM_OFFSET_ADDR1
+#define MMEA3_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0
+#define MMEA3_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0xc
+#define MMEA3_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L
+#define MMEA3_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0x00FFF000L
+//MMEA3_ADDRNORM_BASE_ADDR2
+#define MMEA3_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA3_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA3_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc
+#define MMEA3_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA3_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA3_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA3_ADDRNORM_LIMIT_ADDR2
+#define MMEA3_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA3_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc
+#define MMEA3_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA3_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA3_ADDRNORM_BASE_ADDR3
+#define MMEA3_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA3_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA3_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc
+#define MMEA3_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA3_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA3_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA3_ADDRNORM_LIMIT_ADDR3
+#define MMEA3_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA3_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc
+#define MMEA3_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA3_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA3_ADDRNORM_OFFSET_ADDR3
+#define MMEA3_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0
+#define MMEA3_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0xc
+#define MMEA3_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L
+#define MMEA3_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0x00FFF000L
+//MMEA3_ADDRNORM_MEGABASE_ADDR0
+#define MMEA3_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA3_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA3_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA3_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA3_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA3_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA3_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR__SHIFT 0xc
+#define MMEA3_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA3_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA3_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA3_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA3_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA3_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA3_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA3_ADDRNORM_MEGALIMIT_ADDR0
+#define MMEA3_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA3_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc
+#define MMEA3_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA3_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA3_ADDRNORM_MEGABASE_ADDR1
+#define MMEA3_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA3_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA3_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA3_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA3_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA3_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA3_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR__SHIFT 0xc
+#define MMEA3_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA3_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA3_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA3_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA3_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA3_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA3_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA3_ADDRNORM_MEGALIMIT_ADDR1
+#define MMEA3_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA3_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc
+#define MMEA3_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA3_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA3_ADDRNORMDRAM_HOLE_CNTL
+#define MMEA3_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0
+#define MMEA3_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7
+#define MMEA3_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L
+#define MMEA3_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L
+//MMEA3_ADDRNORMGMI_HOLE_CNTL
+#define MMEA3_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0
+#define MMEA3_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7
+#define MMEA3_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L
+#define MMEA3_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L
+//MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG
+#define MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0
+#define MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6
+#define MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL
+#define MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L
+//MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG
+#define MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0
+#define MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6
+#define MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL
+#define MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L
+//MMEA3_ADDRDEC_BANK_CFG
+#define MMEA3_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0
+#define MMEA3_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6
+#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc
+#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf
+#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12
+#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13
+#define MMEA3_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL
+#define MMEA3_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L
+#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L
+#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L
+#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L
+#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L
+//MMEA3_ADDRDEC_MISC_CFG
+#define MMEA3_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0
+#define MMEA3_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1
+#define MMEA3_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2
+#define MMEA3_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8
+#define MMEA3_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9
+#define MMEA3_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc
+#define MMEA3_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11
+#define MMEA3_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16
+#define MMEA3_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18
+#define MMEA3_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a
+#define MMEA3_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d
+#define MMEA3_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L
+#define MMEA3_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L
+#define MMEA3_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L
+#define MMEA3_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L
+#define MMEA3_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L
+#define MMEA3_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L
+#define MMEA3_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L
+#define MMEA3_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L
+#define MMEA3_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L
+#define MMEA3_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L
+#define MMEA3_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L
+//MMEA3_ADDRDECDRAM_HARVEST_ENABLE
+#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0
+#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1
+#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2
+#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3
+#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4
+#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5
+#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L
+#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L
+#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L
+#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L
+#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L
+#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L
+//MMEA3_ADDRDECGMI_HARVEST_ENABLE
+#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0
+#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1
+#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2
+#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3
+#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4
+#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5
+#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L
+#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L
+#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L
+#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L
+#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L
+#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L
+//MMEA3_ADDRDEC0_BASE_ADDR_CS0
+#define MMEA3_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0
+#define MMEA3_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
+#define MMEA3_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L
+#define MMEA3_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC0_BASE_ADDR_CS1
+#define MMEA3_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0
+#define MMEA3_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
+#define MMEA3_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L
+#define MMEA3_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC0_BASE_ADDR_CS2
+#define MMEA3_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0
+#define MMEA3_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
+#define MMEA3_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L
+#define MMEA3_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC0_BASE_ADDR_CS3
+#define MMEA3_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0
+#define MMEA3_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
+#define MMEA3_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L
+#define MMEA3_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC0_BASE_ADDR_SECCS0
+#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0
+#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
+#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L
+#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC0_BASE_ADDR_SECCS1
+#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0
+#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
+#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L
+#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC0_BASE_ADDR_SECCS2
+#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0
+#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
+#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L
+#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC0_BASE_ADDR_SECCS3
+#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0
+#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
+#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L
+#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC0_ADDR_MASK_CS01
+#define MMEA3_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
+#define MMEA3_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC0_ADDR_MASK_CS23
+#define MMEA3_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
+#define MMEA3_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC0_ADDR_MASK_SECCS01
+#define MMEA3_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
+#define MMEA3_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC0_ADDR_MASK_SECCS23
+#define MMEA3_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
+#define MMEA3_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC0_ADDR_CFG_CS01
+#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
+#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
+#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
+#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
+#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
+#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f
+#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
+#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
+#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
+#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L
+//MMEA3_ADDRDEC0_ADDR_CFG_CS23
+#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
+#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
+#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
+#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
+#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
+#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f
+#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
+#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
+#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
+#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L
+//MMEA3_ADDRDEC0_ADDR_SEL_CS01
+#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0
+#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4
+#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8
+#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc
+#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10
+#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
+#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
+#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
+#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
+#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
+#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
+#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L
+#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
+#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
+//MMEA3_ADDRDEC0_ADDR_SEL_CS23
+#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0
+#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4
+#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8
+#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc
+#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10
+#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
+#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
+#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
+#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
+#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
+#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
+#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L
+#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
+#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
+//MMEA3_ADDRDEC0_ADDR_SEL2_CS01
+#define MMEA3_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0
+#define MMEA3_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA3_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL
+#define MMEA3_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L
+//MMEA3_ADDRDEC0_ADDR_SEL2_CS23
+#define MMEA3_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0
+#define MMEA3_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA3_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL
+#define MMEA3_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L
+//MMEA3_ADDRDEC0_COL_SEL_LO_CS01
+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0
+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4
+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8
+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc
+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10
+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14
+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18
+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
+//MMEA3_ADDRDEC0_COL_SEL_LO_CS23
+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0
+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4
+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8
+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc
+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10
+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14
+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18
+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
+//MMEA3_ADDRDEC0_COL_SEL_HI_CS01
+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0
+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4
+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8
+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc
+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10
+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14
+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18
+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
+//MMEA3_ADDRDEC0_COL_SEL_HI_CS23
+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0
+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4
+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8
+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc
+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10
+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14
+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18
+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
+//MMEA3_ADDRDEC0_RM_SEL_CS01
+#define MMEA3_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0
+#define MMEA3_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4
+#define MMEA3_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8
+#define MMEA3_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA3_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA3_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA3_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL
+#define MMEA3_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L
+#define MMEA3_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L
+#define MMEA3_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA3_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA3_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA3_ADDRDEC0_RM_SEL_CS23
+#define MMEA3_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0
+#define MMEA3_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4
+#define MMEA3_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8
+#define MMEA3_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA3_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA3_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA3_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL
+#define MMEA3_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L
+#define MMEA3_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L
+#define MMEA3_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA3_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA3_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA3_ADDRDEC0_RM_SEL_SECCS01
+#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0
+#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4
+#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8
+#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
+#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
+#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
+#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
+#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA3_ADDRDEC0_RM_SEL_SECCS23
+#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0
+#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4
+#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8
+#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
+#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
+#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
+#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
+#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA3_ADDRDEC1_BASE_ADDR_CS0
+#define MMEA3_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0
+#define MMEA3_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
+#define MMEA3_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L
+#define MMEA3_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC1_BASE_ADDR_CS1
+#define MMEA3_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0
+#define MMEA3_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
+#define MMEA3_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L
+#define MMEA3_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC1_BASE_ADDR_CS2
+#define MMEA3_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0
+#define MMEA3_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
+#define MMEA3_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L
+#define MMEA3_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC1_BASE_ADDR_CS3
+#define MMEA3_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0
+#define MMEA3_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
+#define MMEA3_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L
+#define MMEA3_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC1_BASE_ADDR_SECCS0
+#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0
+#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
+#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L
+#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC1_BASE_ADDR_SECCS1
+#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0
+#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
+#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L
+#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC1_BASE_ADDR_SECCS2
+#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0
+#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
+#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L
+#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC1_BASE_ADDR_SECCS3
+#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0
+#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
+#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L
+#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC1_ADDR_MASK_CS01
+#define MMEA3_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
+#define MMEA3_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC1_ADDR_MASK_CS23
+#define MMEA3_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
+#define MMEA3_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC1_ADDR_MASK_SECCS01
+#define MMEA3_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
+#define MMEA3_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC1_ADDR_MASK_SECCS23
+#define MMEA3_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
+#define MMEA3_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC1_ADDR_CFG_CS01
+#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
+#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
+#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
+#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
+#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
+#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f
+#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
+#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
+#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
+#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L
+//MMEA3_ADDRDEC1_ADDR_CFG_CS23
+#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
+#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
+#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
+#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
+#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
+#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f
+#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
+#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
+#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
+#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L
+//MMEA3_ADDRDEC1_ADDR_SEL_CS01
+#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0
+#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4
+#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8
+#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc
+#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10
+#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
+#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
+#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
+#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
+#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
+#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
+#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L
+#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
+#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
+//MMEA3_ADDRDEC1_ADDR_SEL_CS23
+#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0
+#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4
+#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8
+#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc
+#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10
+#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
+#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
+#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
+#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
+#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
+#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
+#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L
+#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
+#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
+//MMEA3_ADDRDEC1_ADDR_SEL2_CS01
+#define MMEA3_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0
+#define MMEA3_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA3_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL
+#define MMEA3_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L
+//MMEA3_ADDRDEC1_ADDR_SEL2_CS23
+#define MMEA3_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0
+#define MMEA3_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA3_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL
+#define MMEA3_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L
+//MMEA3_ADDRDEC1_COL_SEL_LO_CS01
+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0
+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4
+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8
+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc
+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10
+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14
+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18
+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
+//MMEA3_ADDRDEC1_COL_SEL_LO_CS23
+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0
+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4
+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8
+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc
+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10
+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14
+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18
+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
+//MMEA3_ADDRDEC1_COL_SEL_HI_CS01
+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0
+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4
+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8
+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc
+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10
+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14
+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18
+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
+//MMEA3_ADDRDEC1_COL_SEL_HI_CS23
+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0
+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4
+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8
+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc
+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10
+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14
+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18
+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
+//MMEA3_ADDRDEC1_RM_SEL_CS01
+#define MMEA3_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0
+#define MMEA3_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4
+#define MMEA3_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8
+#define MMEA3_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA3_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA3_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA3_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL
+#define MMEA3_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L
+#define MMEA3_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L
+#define MMEA3_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA3_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA3_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA3_ADDRDEC1_RM_SEL_CS23
+#define MMEA3_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0
+#define MMEA3_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4
+#define MMEA3_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8
+#define MMEA3_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA3_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA3_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA3_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL
+#define MMEA3_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L
+#define MMEA3_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L
+#define MMEA3_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA3_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA3_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA3_ADDRDEC1_RM_SEL_SECCS01
+#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0
+#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4
+#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8
+#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
+#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
+#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
+#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
+#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA3_ADDRDEC1_RM_SEL_SECCS23
+#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0
+#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4
+#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8
+#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
+#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
+#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
+#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
+#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA3_ADDRDEC2_BASE_ADDR_CS0
+#define MMEA3_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0
+#define MMEA3_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
+#define MMEA3_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L
+#define MMEA3_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC2_BASE_ADDR_CS1
+#define MMEA3_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0
+#define MMEA3_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
+#define MMEA3_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L
+#define MMEA3_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC2_BASE_ADDR_CS2
+#define MMEA3_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0
+#define MMEA3_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
+#define MMEA3_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L
+#define MMEA3_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC2_BASE_ADDR_CS3
+#define MMEA3_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0
+#define MMEA3_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
+#define MMEA3_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L
+#define MMEA3_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC2_BASE_ADDR_SECCS0
+#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0
+#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
+#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L
+#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC2_BASE_ADDR_SECCS1
+#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0
+#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
+#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L
+#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC2_BASE_ADDR_SECCS2
+#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0
+#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
+#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L
+#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC2_BASE_ADDR_SECCS3
+#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0
+#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
+#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L
+#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC2_ADDR_MASK_CS01
+#define MMEA3_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
+#define MMEA3_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC2_ADDR_MASK_CS23
+#define MMEA3_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
+#define MMEA3_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC2_ADDR_MASK_SECCS01
+#define MMEA3_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
+#define MMEA3_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC2_ADDR_MASK_SECCS23
+#define MMEA3_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
+#define MMEA3_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA3_ADDRDEC2_ADDR_CFG_CS01
+#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
+#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
+#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
+#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
+#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
+#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f
+#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
+#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
+#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
+#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L
+//MMEA3_ADDRDEC2_ADDR_CFG_CS23
+#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
+#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
+#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
+#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
+#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
+#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f
+#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
+#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
+#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
+#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L
+//MMEA3_ADDRDEC2_ADDR_SEL_CS01
+#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0
+#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4
+#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8
+#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc
+#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10
+#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
+#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
+#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
+#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
+#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
+#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
+#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L
+#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
+#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
+//MMEA3_ADDRDEC2_ADDR_SEL_CS23
+#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0
+#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4
+#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8
+#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc
+#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10
+#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
+#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
+#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
+#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
+#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
+#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
+#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L
+#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
+#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
+//MMEA3_ADDRDEC2_ADDR_SEL2_CS01
+#define MMEA3_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0
+#define MMEA3_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA3_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL
+#define MMEA3_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L
+//MMEA3_ADDRDEC2_ADDR_SEL2_CS23
+#define MMEA3_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0
+#define MMEA3_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA3_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL
+#define MMEA3_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L
+//MMEA3_ADDRDEC2_COL_SEL_LO_CS01
+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0
+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4
+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8
+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc
+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10
+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14
+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18
+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
+//MMEA3_ADDRDEC2_COL_SEL_LO_CS23
+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0
+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4
+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8
+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc
+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10
+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14
+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18
+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
+//MMEA3_ADDRDEC2_COL_SEL_HI_CS01
+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0
+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4
+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8
+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc
+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10
+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14
+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18
+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
+//MMEA3_ADDRDEC2_COL_SEL_HI_CS23
+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0
+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4
+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8
+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc
+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10
+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14
+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18
+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
+//MMEA3_ADDRDEC2_RM_SEL_CS01
+#define MMEA3_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0
+#define MMEA3_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4
+#define MMEA3_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8
+#define MMEA3_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA3_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA3_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA3_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL
+#define MMEA3_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L
+#define MMEA3_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L
+#define MMEA3_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA3_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA3_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA3_ADDRDEC2_RM_SEL_CS23
+#define MMEA3_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0
+#define MMEA3_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4
+#define MMEA3_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8
+#define MMEA3_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA3_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA3_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA3_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL
+#define MMEA3_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L
+#define MMEA3_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L
+#define MMEA3_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA3_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA3_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA3_ADDRDEC2_RM_SEL_SECCS01
+#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0
+#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4
+#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8
+#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
+#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
+#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
+#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
+#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA3_ADDRDEC2_RM_SEL_SECCS23
+#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0
+#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4
+#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8
+#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
+#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
+#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
+#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
+#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA3_ADDRNORMDRAM_GLOBAL_CNTL
+//MMEA3_ADDRNORMGMI_GLOBAL_CNTL
+//MMEA3_ADDRNORM_MEGACONTROL_ADDR0
+#define MMEA3_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0
+#define MMEA3_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL
+//MMEA3_ADDRNORM_MEGACONTROL_ADDR1
+#define MMEA3_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0
+#define MMEA3_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL
+//MMEA3_ADDRNORMDRAM_MASKING
+#define MMEA3_ADDRNORMDRAM_MASKING__ADDRHI_MASK__SHIFT 0x0
+#define MMEA3_ADDRNORMDRAM_MASKING__ADDRHI_MASK_MASK 0x00000FFFL
+//MMEA3_ADDRNORMGMI_MASKING
+#define MMEA3_ADDRNORMGMI_MASKING__ADDRHI_MASK__SHIFT 0x0
+#define MMEA3_ADDRNORMGMI_MASKING__ADDRHI_MASK_MASK 0x00000FFFL
+//MMEA3_IO_RD_CLI2GRP_MAP0
+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA3_IO_RD_CLI2GRP_MAP1
+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA3_IO_WR_CLI2GRP_MAP0
+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA3_IO_WR_CLI2GRP_MAP1
+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA3_IO_RD_COMBINE_FLUSH
+#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0
+#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4
+#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8
+#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc
+#define MMEA3_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10
+#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL
+#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L
+#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L
+#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L
+#define MMEA3_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L
+//MMEA3_IO_WR_COMBINE_FLUSH
+#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0
+#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4
+#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8
+#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc
+#define MMEA3_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10
+#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL
+#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L
+#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L
+#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L
+#define MMEA3_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L
+//MMEA3_IO_GROUP_BURST
+#define MMEA3_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0
+#define MMEA3_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8
+#define MMEA3_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10
+#define MMEA3_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18
+#define MMEA3_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL
+#define MMEA3_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
+#define MMEA3_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
+#define MMEA3_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L
+//MMEA3_IO_RD_PRI_AGE
+#define MMEA3_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA3_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA3_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA3_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA3_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA3_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA3_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA3_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA3_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA3_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA3_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA3_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA3_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA3_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA3_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA3_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA3_IO_WR_PRI_AGE
+#define MMEA3_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA3_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA3_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA3_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA3_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA3_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA3_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA3_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA3_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA3_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA3_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA3_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA3_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA3_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA3_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA3_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA3_IO_RD_PRI_QUEUING
+#define MMEA3_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA3_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA3_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA3_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA3_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA3_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA3_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA3_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA3_IO_WR_PRI_QUEUING
+#define MMEA3_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA3_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA3_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA3_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA3_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA3_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA3_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA3_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA3_IO_RD_PRI_FIXED
+#define MMEA3_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA3_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA3_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA3_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA3_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA3_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA3_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA3_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA3_IO_WR_PRI_FIXED
+#define MMEA3_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA3_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA3_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA3_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA3_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA3_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA3_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA3_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA3_IO_RD_PRI_URGENCY
+#define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA3_IO_WR_PRI_URGENCY
+#define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA3_IO_RD_PRI_URGENCY_MASKING
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L
+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L
+//MMEA3_IO_WR_PRI_URGENCY_MASKING
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L
+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L
+//MMEA3_IO_RD_PRI_QUANT_PRI1
+#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA3_IO_RD_PRI_QUANT_PRI2
+#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA3_IO_RD_PRI_QUANT_PRI3
+#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA3_IO_WR_PRI_QUANT_PRI1
+#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA3_IO_WR_PRI_QUANT_PRI2
+#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA3_IO_WR_PRI_QUANT_PRI3
+#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA3_SDP_ARB_DRAM
+#define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0
+#define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8
+#define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10
+#define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11
+#define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12
+#define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13
+#define MMEA3_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14
+#define MMEA3_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15
+#define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL
+#define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L
+#define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L
+#define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L
+#define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L
+#define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L
+#define MMEA3_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L
+#define MMEA3_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L
+//MMEA3_SDP_ARB_GMI
+#define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0
+#define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8
+#define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10
+#define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11
+#define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12
+#define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13
+#define MMEA3_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14
+#define MMEA3_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15
+#define MMEA3_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16
+#define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL
+#define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L
+#define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L
+#define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L
+#define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L
+#define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L
+#define MMEA3_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L
+#define MMEA3_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L
+#define MMEA3_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L
+//MMEA3_SDP_ARB_FINAL
+#define MMEA3_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0
+#define MMEA3_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5
+#define MMEA3_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa
+#define MMEA3_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf
+#define MMEA3_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11
+#define MMEA3_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12
+#define MMEA3_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13
+#define MMEA3_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14
+#define MMEA3_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15
+#define MMEA3_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16
+#define MMEA3_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17
+#define MMEA3_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18
+#define MMEA3_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19
+#define MMEA3_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a
+#define MMEA3_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b
+#define MMEA3_SDP_ARB_FINAL__DRAM_RD_THROTTLE__SHIFT 0x1c
+#define MMEA3_SDP_ARB_FINAL__DRAM_WR_THROTTLE__SHIFT 0x1d
+#define MMEA3_SDP_ARB_FINAL__GMI_RD_THROTTLE__SHIFT 0x1e
+#define MMEA3_SDP_ARB_FINAL__GMI_WR_THROTTLE__SHIFT 0x1f
+#define MMEA3_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL
+#define MMEA3_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L
+#define MMEA3_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L
+#define MMEA3_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L
+#define MMEA3_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L
+#define MMEA3_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L
+#define MMEA3_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L
+#define MMEA3_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L
+#define MMEA3_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L
+#define MMEA3_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L
+#define MMEA3_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L
+#define MMEA3_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L
+#define MMEA3_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L
+#define MMEA3_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L
+#define MMEA3_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L
+#define MMEA3_SDP_ARB_FINAL__DRAM_RD_THROTTLE_MASK 0x10000000L
+#define MMEA3_SDP_ARB_FINAL__DRAM_WR_THROTTLE_MASK 0x20000000L
+#define MMEA3_SDP_ARB_FINAL__GMI_RD_THROTTLE_MASK 0x40000000L
+#define MMEA3_SDP_ARB_FINAL__GMI_WR_THROTTLE_MASK 0x80000000L
+//MMEA3_SDP_DRAM_PRIORITY
+#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
+#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
+#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
+#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
+#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
+#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
+#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
+#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
+#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
+#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
+#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
+#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
+#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
+#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
+#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
+#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
+//MMEA3_SDP_GMI_PRIORITY
+#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
+#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
+#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
+#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
+#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
+#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
+#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
+#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
+#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
+#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
+#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
+#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
+#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
+#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
+#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
+#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
+//MMEA3_SDP_IO_PRIORITY
+#define MMEA3_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
+#define MMEA3_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
+#define MMEA3_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
+#define MMEA3_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
+#define MMEA3_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
+#define MMEA3_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
+#define MMEA3_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
+#define MMEA3_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
+#define MMEA3_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
+#define MMEA3_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
+#define MMEA3_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
+#define MMEA3_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
+#define MMEA3_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
+#define MMEA3_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
+#define MMEA3_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
+#define MMEA3_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
+//MMEA3_SDP_CREDITS
+#define MMEA3_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0
+#define MMEA3_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8
+#define MMEA3_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10
+#define MMEA3_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL
+#define MMEA3_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L
+#define MMEA3_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L
+//MMEA3_SDP_TAG_RESERVE0
+#define MMEA3_SDP_TAG_RESERVE0__VC0__SHIFT 0x0
+#define MMEA3_SDP_TAG_RESERVE0__VC1__SHIFT 0x8
+#define MMEA3_SDP_TAG_RESERVE0__VC2__SHIFT 0x10
+#define MMEA3_SDP_TAG_RESERVE0__VC3__SHIFT 0x18
+#define MMEA3_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL
+#define MMEA3_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L
+#define MMEA3_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L
+#define MMEA3_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L
+//MMEA3_SDP_TAG_RESERVE1
+#define MMEA3_SDP_TAG_RESERVE1__VC4__SHIFT 0x0
+#define MMEA3_SDP_TAG_RESERVE1__VC5__SHIFT 0x8
+#define MMEA3_SDP_TAG_RESERVE1__VC6__SHIFT 0x10
+#define MMEA3_SDP_TAG_RESERVE1__VC7__SHIFT 0x18
+#define MMEA3_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL
+#define MMEA3_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L
+#define MMEA3_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L
+#define MMEA3_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L
+//MMEA3_SDP_VCC_RESERVE0
+#define MMEA3_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0
+#define MMEA3_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6
+#define MMEA3_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc
+#define MMEA3_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12
+#define MMEA3_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18
+#define MMEA3_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL
+#define MMEA3_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L
+#define MMEA3_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L
+#define MMEA3_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L
+#define MMEA3_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L
+//MMEA3_SDP_VCC_RESERVE1
+#define MMEA3_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0
+#define MMEA3_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6
+#define MMEA3_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc
+#define MMEA3_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f
+#define MMEA3_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL
+#define MMEA3_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L
+#define MMEA3_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L
+#define MMEA3_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L
+//MMEA3_SDP_VCD_RESERVE0
+#define MMEA3_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0
+#define MMEA3_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6
+#define MMEA3_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc
+#define MMEA3_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12
+#define MMEA3_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18
+#define MMEA3_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL
+#define MMEA3_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L
+#define MMEA3_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L
+#define MMEA3_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L
+#define MMEA3_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L
+//MMEA3_SDP_VCD_RESERVE1
+#define MMEA3_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0
+#define MMEA3_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6
+#define MMEA3_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc
+#define MMEA3_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f
+#define MMEA3_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL
+#define MMEA3_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L
+#define MMEA3_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L
+#define MMEA3_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L
+//MMEA3_SDP_REQ_CNTL
+#define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0
+#define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1
+#define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2
+#define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3
+#define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4
+#define MMEA3_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5
+#define MMEA3_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6
+#define MMEA3_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8
+#define MMEA3_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa
+#define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L
+#define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L
+#define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L
+#define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L
+#define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L
+#define MMEA3_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L
+#define MMEA3_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L
+#define MMEA3_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L
+#define MMEA3_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L
+//MMEA3_MISC
+#define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0
+#define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1
+#define MMEA3_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2
+#define MMEA3_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3
+#define MMEA3_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4
+#define MMEA3_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5
+#define MMEA3_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6
+#define MMEA3_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7
+#define MMEA3_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8
+#define MMEA3_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9
+#define MMEA3_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa
+#define MMEA3_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb
+#define MMEA3_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc
+#define MMEA3_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd
+#define MMEA3_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe
+#define MMEA3_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf
+#define MMEA3_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11
+#define MMEA3_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13
+#define MMEA3_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15
+#define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a
+#define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b
+#define MMEA3_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c
+#define MMEA3_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d
+#define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e
+#define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f
+#define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L
+#define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L
+#define MMEA3_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L
+#define MMEA3_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L
+#define MMEA3_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L
+#define MMEA3_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L
+#define MMEA3_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L
+#define MMEA3_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L
+#define MMEA3_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L
+#define MMEA3_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L
+#define MMEA3_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L
+#define MMEA3_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L
+#define MMEA3_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L
+#define MMEA3_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L
+#define MMEA3_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L
+#define MMEA3_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L
+#define MMEA3_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L
+#define MMEA3_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L
+#define MMEA3_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L
+#define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L
+#define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L
+#define MMEA3_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L
+#define MMEA3_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L
+#define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L
+#define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L
+//MMEA3_LATENCY_SAMPLING
+#define MMEA3_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0
+#define MMEA3_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1
+#define MMEA3_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2
+#define MMEA3_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3
+#define MMEA3_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4
+#define MMEA3_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5
+#define MMEA3_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6
+#define MMEA3_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7
+#define MMEA3_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8
+#define MMEA3_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9
+#define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa
+#define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb
+#define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc
+#define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd
+#define MMEA3_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe
+#define MMEA3_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16
+#define MMEA3_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L
+#define MMEA3_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L
+#define MMEA3_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L
+#define MMEA3_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L
+#define MMEA3_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L
+#define MMEA3_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L
+#define MMEA3_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L
+#define MMEA3_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L
+#define MMEA3_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L
+#define MMEA3_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L
+#define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L
+#define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L
+#define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L
+#define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L
+#define MMEA3_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L
+#define MMEA3_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L
+//MMEA3_PERFCOUNTER_LO
+#define MMEA3_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MMEA3_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//MMEA3_PERFCOUNTER_HI
+#define MMEA3_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MMEA3_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MMEA3_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define MMEA3_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//MMEA3_PERFCOUNTER0_CFG
+#define MMEA3_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MMEA3_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMEA3_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MMEA3_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MMEA3_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MMEA3_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMEA3_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMEA3_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMEA3_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define MMEA3_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//MMEA3_PERFCOUNTER1_CFG
+#define MMEA3_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MMEA3_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMEA3_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MMEA3_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MMEA3_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MMEA3_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMEA3_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMEA3_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMEA3_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define MMEA3_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//MMEA3_PERFCOUNTER_RSLT_CNTL
+#define MMEA3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MMEA3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MMEA3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MMEA3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MMEA3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define MMEA3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define MMEA3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define MMEA3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+//MMEA3_EDC_CNT
+#define MMEA3_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0
+#define MMEA3_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2
+#define MMEA3_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4
+#define MMEA3_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6
+#define MMEA3_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8
+#define MMEA3_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa
+#define MMEA3_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc
+#define MMEA3_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe
+#define MMEA3_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10
+#define MMEA3_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12
+#define MMEA3_EDC_CNT__IOWR_DATAMEM_SEC_COUNT__SHIFT 0x14
+#define MMEA3_EDC_CNT__IOWR_DATAMEM_DED_COUNT__SHIFT 0x16
+#define MMEA3_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x18
+#define MMEA3_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x1a
+#define MMEA3_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x1c
+#define MMEA3_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1e
+#define MMEA3_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
+#define MMEA3_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
+#define MMEA3_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
+#define MMEA3_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
+#define MMEA3_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
+#define MMEA3_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
+#define MMEA3_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L
+#define MMEA3_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L
+#define MMEA3_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L
+#define MMEA3_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L
+#define MMEA3_EDC_CNT__IOWR_DATAMEM_SEC_COUNT_MASK 0x00300000L
+#define MMEA3_EDC_CNT__IOWR_DATAMEM_DED_COUNT_MASK 0x00C00000L
+#define MMEA3_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x03000000L
+#define MMEA3_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x0C000000L
+#define MMEA3_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x30000000L
+#define MMEA3_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0xC0000000L
+//MMEA3_EDC_CNT2
+#define MMEA3_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0
+#define MMEA3_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2
+#define MMEA3_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4
+#define MMEA3_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6
+#define MMEA3_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8
+#define MMEA3_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa
+#define MMEA3_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc
+#define MMEA3_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe
+#define MMEA3_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10
+#define MMEA3_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12
+#define MMEA3_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14
+#define MMEA3_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16
+#define MMEA3_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT 0x18
+#define MMEA3_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT 0x1a
+#define MMEA3_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT 0x1c
+#define MMEA3_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT 0x1e
+#define MMEA3_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
+#define MMEA3_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
+#define MMEA3_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
+#define MMEA3_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
+#define MMEA3_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
+#define MMEA3_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
+#define MMEA3_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L
+#define MMEA3_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L
+#define MMEA3_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L
+#define MMEA3_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L
+#define MMEA3_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L
+#define MMEA3_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L
+#define MMEA3_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK 0x03000000L
+#define MMEA3_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK 0x0C000000L
+#define MMEA3_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK 0x30000000L
+#define MMEA3_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK 0xC0000000L
+//MMEA3_DSM_CNTL
+#define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3
+#define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define MMEA3_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9
+#define MMEA3_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb
+#define MMEA3_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc
+#define MMEA3_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
+#define MMEA3_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf
+#define MMEA3_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11
+#define MMEA3_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12
+#define MMEA3_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14
+#define MMEA3_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15
+#define MMEA3_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17
+#define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
+#define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define MMEA3_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L
+#define MMEA3_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
+#define MMEA3_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L
+#define MMEA3_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
+#define MMEA3_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L
+#define MMEA3_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L
+#define MMEA3_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L
+#define MMEA3_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L
+#define MMEA3_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L
+#define MMEA3_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L
+//MMEA3_DSM_CNTLA
+#define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3
+#define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define MMEA3_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define MMEA3_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define MMEA3_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9
+#define MMEA3_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb
+#define MMEA3_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc
+#define MMEA3_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
+#define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf
+#define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11
+#define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12
+#define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14
+#define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
+#define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define MMEA3_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define MMEA3_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define MMEA3_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L
+#define MMEA3_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
+#define MMEA3_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L
+#define MMEA3_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
+#define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L
+#define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L
+#define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L
+#define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L
+//MMEA3_DSM_CNTLB
+//MMEA3_DSM_CNTL2
+#define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5
+#define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8
+#define MMEA3_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define MMEA3_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb
+#define MMEA3_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define MMEA3_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe
+#define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11
+#define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14
+#define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15
+#define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17
+#define MMEA3_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
+#define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define MMEA3_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define MMEA3_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define MMEA3_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define MMEA3_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L
+#define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L
+#define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L
+#define MMEA3_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
+//MMEA3_DSM_CNTL2A
+#define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5
+#define MMEA3_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define MMEA3_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8
+#define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb
+#define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe
+#define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11
+#define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14
+#define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define MMEA3_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define MMEA3_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L
+//MMEA3_DSM_CNTL2B
+//MMEA3_CGTT_CLK_CTRL
+#define MMEA3_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define MMEA3_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define MMEA3_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc
+#define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14
+#define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15
+#define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16
+#define MMEA3_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17
+#define MMEA3_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c
+#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d
+#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e
+#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f
+#define MMEA3_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define MMEA3_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define MMEA3_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L
+#define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L
+#define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L
+#define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L
+#define MMEA3_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L
+#define MMEA3_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L
+#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L
+#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L
+#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L
+//MMEA3_EDC_MODE
+#define MMEA3_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10
+#define MMEA3_EDC_MODE__GATE_FUE__SHIFT 0x11
+#define MMEA3_EDC_MODE__DED_MODE__SHIFT 0x14
+#define MMEA3_EDC_MODE__PROP_FED__SHIFT 0x1d
+#define MMEA3_EDC_MODE__BYPASS__SHIFT 0x1f
+#define MMEA3_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L
+#define MMEA3_EDC_MODE__GATE_FUE_MASK 0x00020000L
+#define MMEA3_EDC_MODE__DED_MODE_MASK 0x00300000L
+#define MMEA3_EDC_MODE__PROP_FED_MASK 0x20000000L
+#define MMEA3_EDC_MODE__BYPASS_MASK 0x80000000L
+//MMEA3_ERR_STATUS
+#define MMEA3_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0
+#define MMEA3_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4
+#define MMEA3_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8
+#define MMEA3_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa
+#define MMEA3_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb
+#define MMEA3_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc
+#define MMEA3_ERR_STATUS__FUE_FLAG__SHIFT 0xd
+#define MMEA3_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe
+#define MMEA3_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf
+#define MMEA3_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10
+#define MMEA3_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11
+#define MMEA3_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12
+#define MMEA3_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL
+#define MMEA3_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L
+#define MMEA3_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L
+#define MMEA3_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L
+#define MMEA3_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L
+#define MMEA3_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L
+#define MMEA3_ERR_STATUS__FUE_FLAG_MASK 0x00002000L
+#define MMEA3_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L
+#define MMEA3_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L
+#define MMEA3_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L
+#define MMEA3_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L
+#define MMEA3_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L
+//MMEA3_MISC2
+#define MMEA3_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0
+#define MMEA3_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1
+#define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2
+#define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7
+#define MMEA3_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc
+#define MMEA3_MISC2__RRET_SWAP_MODE__SHIFT 0xd
+#define MMEA3_MISC2__BLOCK_REQUESTS__SHIFT 0xe
+#define MMEA3_MISC2__REQUESTS_BLOCKED__SHIFT 0xf
+#define MMEA3_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L
+#define MMEA3_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L
+#define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL
+#define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L
+#define MMEA3_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L
+#define MMEA3_MISC2__RRET_SWAP_MODE_MASK 0x00002000L
+#define MMEA3_MISC2__BLOCK_REQUESTS_MASK 0x00004000L
+#define MMEA3_MISC2__REQUESTS_BLOCKED_MASK 0x00008000L
+//MMEA3_ADDRDEC_SELECT
+#define MMEA3_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0
+#define MMEA3_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5
+#define MMEA3_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa
+#define MMEA3_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf
+#define MMEA3_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL
+#define MMEA3_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L
+#define MMEA3_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L
+#define MMEA3_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L
+//MMEA3_EDC_CNT3
+#define MMEA3_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0
+#define MMEA3_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2
+#define MMEA3_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4
+#define MMEA3_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6
+#define MMEA3_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0x8
+#define MMEA3_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xa
+#define MMEA3_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L
+#define MMEA3_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL
+#define MMEA3_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L
+#define MMEA3_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
+#define MMEA3_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000300L
+#define MMEA3_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00000C00L
+//MMEA3_MISC_AON
+#define MMEA3_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0
+#define MMEA3_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2
+#define MMEA3_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L
+#define MMEA3_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L
+
+
+// addressBlock: mmhub_ea_mmeadec4
+//MMEA4_DRAM_RD_CLI2GRP_MAP0
+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA4_DRAM_RD_CLI2GRP_MAP1
+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA4_DRAM_WR_CLI2GRP_MAP0
+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA4_DRAM_WR_CLI2GRP_MAP1
+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA4_DRAM_RD_GRP2VC_MAP
+#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
+#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
+#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
+#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
+#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
+#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
+#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
+#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
+//MMEA4_DRAM_WR_GRP2VC_MAP
+#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
+#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
+#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
+#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
+#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
+#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
+#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
+#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
+//MMEA4_DRAM_RD_LAZY
+#define MMEA4_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0
+#define MMEA4_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3
+#define MMEA4_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6
+#define MMEA4_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9
+#define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
+#define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
+#define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b
+#define MMEA4_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L
+#define MMEA4_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L
+#define MMEA4_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L
+#define MMEA4_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L
+#define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
+#define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
+#define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L
+//MMEA4_DRAM_WR_LAZY
+#define MMEA4_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0
+#define MMEA4_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3
+#define MMEA4_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6
+#define MMEA4_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9
+#define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
+#define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
+#define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b
+#define MMEA4_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L
+#define MMEA4_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L
+#define MMEA4_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L
+#define MMEA4_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L
+#define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
+#define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
+#define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L
+//MMEA4_DRAM_RD_CAM_CNTL
+#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
+#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
+#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
+#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
+#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
+#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
+#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
+#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
+#define MMEA4_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c
+#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
+#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
+#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
+#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
+#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
+#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
+#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
+#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
+#define MMEA4_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L
+//MMEA4_DRAM_WR_CAM_CNTL
+#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
+#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
+#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
+#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
+#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
+#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
+#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
+#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
+#define MMEA4_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c
+#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
+#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
+#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
+#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
+#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
+#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
+#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
+#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
+#define MMEA4_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L
+//MMEA4_DRAM_PAGE_BURST
+#define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0
+#define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8
+#define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10
+#define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18
+#define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL
+#define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
+#define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
+#define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L
+//MMEA4_DRAM_RD_PRI_AGE
+#define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA4_DRAM_WR_PRI_AGE
+#define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA4_DRAM_RD_PRI_QUEUING
+#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA4_DRAM_WR_PRI_QUEUING
+#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA4_DRAM_RD_PRI_FIXED
+#define MMEA4_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA4_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA4_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA4_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA4_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA4_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA4_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA4_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA4_DRAM_WR_PRI_FIXED
+#define MMEA4_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA4_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA4_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA4_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA4_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA4_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA4_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA4_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA4_DRAM_RD_PRI_URGENCY
+#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA4_DRAM_WR_PRI_URGENCY
+#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA4_DRAM_RD_PRI_QUANT_PRI1
+#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA4_DRAM_RD_PRI_QUANT_PRI2
+#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA4_DRAM_RD_PRI_QUANT_PRI3
+#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA4_DRAM_WR_PRI_QUANT_PRI1
+#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA4_DRAM_WR_PRI_QUANT_PRI2
+#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA4_DRAM_WR_PRI_QUANT_PRI3
+#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA4_GMI_RD_CLI2GRP_MAP0
+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA4_GMI_RD_CLI2GRP_MAP1
+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA4_GMI_WR_CLI2GRP_MAP0
+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA4_GMI_WR_CLI2GRP_MAP1
+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA4_GMI_RD_GRP2VC_MAP
+#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
+#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
+#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
+#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
+#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
+#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
+#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
+#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
+//MMEA4_GMI_WR_GRP2VC_MAP
+#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
+#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
+#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
+#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
+#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
+#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
+#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
+#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
+//MMEA4_GMI_RD_LAZY
+#define MMEA4_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0
+#define MMEA4_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3
+#define MMEA4_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6
+#define MMEA4_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9
+#define MMEA4_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
+#define MMEA4_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
+#define MMEA4_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b
+#define MMEA4_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L
+#define MMEA4_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L
+#define MMEA4_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L
+#define MMEA4_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L
+#define MMEA4_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
+#define MMEA4_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
+#define MMEA4_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L
+//MMEA4_GMI_WR_LAZY
+#define MMEA4_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0
+#define MMEA4_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3
+#define MMEA4_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6
+#define MMEA4_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9
+#define MMEA4_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
+#define MMEA4_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
+#define MMEA4_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b
+#define MMEA4_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L
+#define MMEA4_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L
+#define MMEA4_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L
+#define MMEA4_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L
+#define MMEA4_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
+#define MMEA4_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
+#define MMEA4_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L
+//MMEA4_GMI_RD_CAM_CNTL
+#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
+#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
+#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
+#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
+#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
+#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
+#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
+#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
+#define MMEA4_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c
+#define MMEA4_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d
+#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
+#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
+#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
+#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
+#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
+#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
+#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
+#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
+#define MMEA4_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L
+#define MMEA4_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L
+//MMEA4_GMI_WR_CAM_CNTL
+#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
+#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
+#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
+#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
+#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
+#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
+#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
+#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
+#define MMEA4_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c
+#define MMEA4_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d
+#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
+#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
+#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
+#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
+#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
+#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
+#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
+#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
+#define MMEA4_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L
+#define MMEA4_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L
+//MMEA4_GMI_PAGE_BURST
+#define MMEA4_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0
+#define MMEA4_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8
+#define MMEA4_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10
+#define MMEA4_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18
+#define MMEA4_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL
+#define MMEA4_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
+#define MMEA4_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
+#define MMEA4_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L
+//MMEA4_GMI_RD_PRI_AGE
+#define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA4_GMI_WR_PRI_AGE
+#define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA4_GMI_RD_PRI_QUEUING
+#define MMEA4_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA4_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA4_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA4_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA4_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA4_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA4_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA4_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA4_GMI_WR_PRI_QUEUING
+#define MMEA4_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA4_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA4_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA4_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA4_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA4_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA4_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA4_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA4_GMI_RD_PRI_FIXED
+#define MMEA4_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA4_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA4_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA4_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA4_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA4_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA4_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA4_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA4_GMI_WR_PRI_FIXED
+#define MMEA4_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA4_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA4_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA4_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA4_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA4_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA4_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA4_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA4_GMI_RD_PRI_URGENCY
+#define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA4_GMI_WR_PRI_URGENCY
+#define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA4_GMI_RD_PRI_URGENCY_MASKING
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L
+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L
+//MMEA4_GMI_WR_PRI_URGENCY_MASKING
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L
+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L
+//MMEA4_GMI_RD_PRI_QUANT_PRI1
+#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA4_GMI_RD_PRI_QUANT_PRI2
+#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA4_GMI_RD_PRI_QUANT_PRI3
+#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA4_GMI_WR_PRI_QUANT_PRI1
+#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA4_GMI_WR_PRI_QUANT_PRI2
+#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA4_GMI_WR_PRI_QUANT_PRI3
+#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA4_ADDRNORM_BASE_ADDR0
+#define MMEA4_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA4_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA4_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc
+#define MMEA4_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA4_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA4_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA4_ADDRNORM_LIMIT_ADDR0
+#define MMEA4_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA4_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc
+#define MMEA4_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA4_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA4_ADDRNORM_BASE_ADDR1
+#define MMEA4_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA4_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA4_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc
+#define MMEA4_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA4_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA4_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA4_ADDRNORM_LIMIT_ADDR1
+#define MMEA4_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA4_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc
+#define MMEA4_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA4_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA4_ADDRNORM_OFFSET_ADDR1
+#define MMEA4_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0
+#define MMEA4_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0xc
+#define MMEA4_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L
+#define MMEA4_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0x00FFF000L
+//MMEA4_ADDRNORM_BASE_ADDR2
+#define MMEA4_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA4_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA4_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc
+#define MMEA4_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA4_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA4_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA4_ADDRNORM_LIMIT_ADDR2
+#define MMEA4_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA4_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc
+#define MMEA4_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA4_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA4_ADDRNORM_BASE_ADDR3
+#define MMEA4_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA4_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA4_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc
+#define MMEA4_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA4_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA4_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA4_ADDRNORM_LIMIT_ADDR3
+#define MMEA4_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA4_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc
+#define MMEA4_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA4_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA4_ADDRNORM_OFFSET_ADDR3
+#define MMEA4_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0
+#define MMEA4_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0xc
+#define MMEA4_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L
+#define MMEA4_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0x00FFF000L
+//MMEA4_ADDRNORM_MEGABASE_ADDR0
+#define MMEA4_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA4_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA4_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA4_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA4_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA4_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA4_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR__SHIFT 0xc
+#define MMEA4_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA4_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA4_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA4_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA4_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA4_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA4_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA4_ADDRNORM_MEGALIMIT_ADDR0
+#define MMEA4_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA4_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc
+#define MMEA4_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA4_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA4_ADDRNORM_MEGABASE_ADDR1
+#define MMEA4_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA4_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA4_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA4_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA4_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA4_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA4_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR__SHIFT 0xc
+#define MMEA4_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA4_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA4_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA4_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA4_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA4_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA4_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA4_ADDRNORM_MEGALIMIT_ADDR1
+#define MMEA4_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA4_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc
+#define MMEA4_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA4_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA4_ADDRNORMDRAM_HOLE_CNTL
+#define MMEA4_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0
+#define MMEA4_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7
+#define MMEA4_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L
+#define MMEA4_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L
+//MMEA4_ADDRNORMGMI_HOLE_CNTL
+#define MMEA4_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0
+#define MMEA4_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7
+#define MMEA4_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L
+#define MMEA4_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L
+//MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG
+#define MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0
+#define MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6
+#define MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL
+#define MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L
+//MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG
+#define MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0
+#define MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6
+#define MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL
+#define MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L
+//MMEA4_ADDRDEC_BANK_CFG
+#define MMEA4_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0
+#define MMEA4_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6
+#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc
+#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf
+#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12
+#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13
+#define MMEA4_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL
+#define MMEA4_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L
+#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L
+#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L
+#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L
+#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L
+//MMEA4_ADDRDEC_MISC_CFG
+#define MMEA4_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0
+#define MMEA4_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1
+#define MMEA4_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2
+#define MMEA4_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8
+#define MMEA4_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9
+#define MMEA4_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc
+#define MMEA4_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11
+#define MMEA4_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16
+#define MMEA4_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18
+#define MMEA4_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a
+#define MMEA4_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d
+#define MMEA4_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L
+#define MMEA4_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L
+#define MMEA4_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L
+#define MMEA4_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L
+#define MMEA4_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L
+#define MMEA4_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L
+#define MMEA4_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L
+#define MMEA4_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L
+#define MMEA4_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L
+#define MMEA4_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L
+#define MMEA4_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L
+//MMEA4_ADDRDECDRAM_HARVEST_ENABLE
+#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0
+#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1
+#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2
+#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3
+#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4
+#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5
+#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L
+#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L
+#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L
+#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L
+#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L
+#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L
+//MMEA4_ADDRDECGMI_HARVEST_ENABLE
+#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0
+#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1
+#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2
+#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3
+#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4
+#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5
+#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L
+#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L
+#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L
+#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L
+#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L
+#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L
+//MMEA4_ADDRDEC0_BASE_ADDR_CS0
+#define MMEA4_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0
+#define MMEA4_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
+#define MMEA4_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L
+#define MMEA4_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC0_BASE_ADDR_CS1
+#define MMEA4_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0
+#define MMEA4_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
+#define MMEA4_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L
+#define MMEA4_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC0_BASE_ADDR_CS2
+#define MMEA4_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0
+#define MMEA4_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
+#define MMEA4_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L
+#define MMEA4_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC0_BASE_ADDR_CS3
+#define MMEA4_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0
+#define MMEA4_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
+#define MMEA4_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L
+#define MMEA4_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC0_BASE_ADDR_SECCS0
+#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0
+#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
+#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L
+#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC0_BASE_ADDR_SECCS1
+#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0
+#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
+#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L
+#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC0_BASE_ADDR_SECCS2
+#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0
+#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
+#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L
+#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC0_BASE_ADDR_SECCS3
+#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0
+#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
+#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L
+#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC0_ADDR_MASK_CS01
+#define MMEA4_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
+#define MMEA4_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC0_ADDR_MASK_CS23
+#define MMEA4_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
+#define MMEA4_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC0_ADDR_MASK_SECCS01
+#define MMEA4_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
+#define MMEA4_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC0_ADDR_MASK_SECCS23
+#define MMEA4_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
+#define MMEA4_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC0_ADDR_CFG_CS01
+#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
+#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
+#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
+#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
+#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
+#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f
+#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
+#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
+#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
+#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L
+//MMEA4_ADDRDEC0_ADDR_CFG_CS23
+#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
+#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
+#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
+#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
+#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
+#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f
+#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
+#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
+#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
+#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L
+//MMEA4_ADDRDEC0_ADDR_SEL_CS01
+#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0
+#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4
+#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8
+#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc
+#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10
+#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
+#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
+#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
+#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
+#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
+#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
+#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L
+#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
+#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
+//MMEA4_ADDRDEC0_ADDR_SEL_CS23
+#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0
+#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4
+#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8
+#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc
+#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10
+#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
+#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
+#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
+#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
+#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
+#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
+#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L
+#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
+#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
+//MMEA4_ADDRDEC0_ADDR_SEL2_CS01
+#define MMEA4_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0
+#define MMEA4_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA4_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL
+#define MMEA4_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L
+//MMEA4_ADDRDEC0_ADDR_SEL2_CS23
+#define MMEA4_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0
+#define MMEA4_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA4_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL
+#define MMEA4_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L
+//MMEA4_ADDRDEC0_COL_SEL_LO_CS01
+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0
+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4
+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8
+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc
+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10
+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14
+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18
+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
+//MMEA4_ADDRDEC0_COL_SEL_LO_CS23
+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0
+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4
+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8
+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc
+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10
+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14
+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18
+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
+//MMEA4_ADDRDEC0_COL_SEL_HI_CS01
+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0
+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4
+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8
+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc
+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10
+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14
+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18
+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
+//MMEA4_ADDRDEC0_COL_SEL_HI_CS23
+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0
+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4
+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8
+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc
+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10
+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14
+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18
+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
+//MMEA4_ADDRDEC0_RM_SEL_CS01
+#define MMEA4_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0
+#define MMEA4_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4
+#define MMEA4_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8
+#define MMEA4_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA4_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA4_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA4_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL
+#define MMEA4_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L
+#define MMEA4_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L
+#define MMEA4_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA4_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA4_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA4_ADDRDEC0_RM_SEL_CS23
+#define MMEA4_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0
+#define MMEA4_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4
+#define MMEA4_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8
+#define MMEA4_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA4_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA4_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA4_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL
+#define MMEA4_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L
+#define MMEA4_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L
+#define MMEA4_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA4_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA4_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA4_ADDRDEC0_RM_SEL_SECCS01
+#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0
+#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4
+#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8
+#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
+#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
+#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
+#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
+#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA4_ADDRDEC0_RM_SEL_SECCS23
+#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0
+#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4
+#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8
+#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
+#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
+#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
+#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
+#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA4_ADDRDEC1_BASE_ADDR_CS0
+#define MMEA4_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0
+#define MMEA4_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
+#define MMEA4_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L
+#define MMEA4_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC1_BASE_ADDR_CS1
+#define MMEA4_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0
+#define MMEA4_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
+#define MMEA4_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L
+#define MMEA4_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC1_BASE_ADDR_CS2
+#define MMEA4_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0
+#define MMEA4_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
+#define MMEA4_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L
+#define MMEA4_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC1_BASE_ADDR_CS3
+#define MMEA4_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0
+#define MMEA4_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
+#define MMEA4_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L
+#define MMEA4_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC1_BASE_ADDR_SECCS0
+#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0
+#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
+#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L
+#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC1_BASE_ADDR_SECCS1
+#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0
+#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
+#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L
+#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC1_BASE_ADDR_SECCS2
+#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0
+#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
+#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L
+#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC1_BASE_ADDR_SECCS3
+#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0
+#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
+#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L
+#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC1_ADDR_MASK_CS01
+#define MMEA4_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
+#define MMEA4_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC1_ADDR_MASK_CS23
+#define MMEA4_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
+#define MMEA4_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC1_ADDR_MASK_SECCS01
+#define MMEA4_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
+#define MMEA4_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC1_ADDR_MASK_SECCS23
+#define MMEA4_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
+#define MMEA4_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC1_ADDR_CFG_CS01
+#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
+#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
+#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
+#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
+#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
+#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f
+#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
+#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
+#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
+#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L
+//MMEA4_ADDRDEC1_ADDR_CFG_CS23
+#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
+#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
+#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
+#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
+#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
+#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f
+#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
+#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
+#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
+#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L
+//MMEA4_ADDRDEC1_ADDR_SEL_CS01
+#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0
+#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4
+#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8
+#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc
+#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10
+#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
+#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
+#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
+#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
+#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
+#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
+#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L
+#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
+#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
+//MMEA4_ADDRDEC1_ADDR_SEL_CS23
+#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0
+#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4
+#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8
+#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc
+#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10
+#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
+#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
+#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
+#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
+#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
+#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
+#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L
+#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
+#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
+//MMEA4_ADDRDEC1_ADDR_SEL2_CS01
+#define MMEA4_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0
+#define MMEA4_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA4_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL
+#define MMEA4_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L
+//MMEA4_ADDRDEC1_ADDR_SEL2_CS23
+#define MMEA4_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0
+#define MMEA4_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA4_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL
+#define MMEA4_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L
+//MMEA4_ADDRDEC1_COL_SEL_LO_CS01
+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0
+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4
+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8
+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc
+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10
+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14
+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18
+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
+//MMEA4_ADDRDEC1_COL_SEL_LO_CS23
+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0
+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4
+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8
+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc
+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10
+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14
+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18
+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
+//MMEA4_ADDRDEC1_COL_SEL_HI_CS01
+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0
+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4
+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8
+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc
+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10
+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14
+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18
+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
+//MMEA4_ADDRDEC1_COL_SEL_HI_CS23
+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0
+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4
+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8
+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc
+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10
+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14
+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18
+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
+//MMEA4_ADDRDEC1_RM_SEL_CS01
+#define MMEA4_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0
+#define MMEA4_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4
+#define MMEA4_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8
+#define MMEA4_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA4_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA4_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA4_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL
+#define MMEA4_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L
+#define MMEA4_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L
+#define MMEA4_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA4_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA4_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA4_ADDRDEC1_RM_SEL_CS23
+#define MMEA4_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0
+#define MMEA4_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4
+#define MMEA4_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8
+#define MMEA4_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA4_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA4_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA4_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL
+#define MMEA4_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L
+#define MMEA4_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L
+#define MMEA4_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA4_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA4_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA4_ADDRDEC1_RM_SEL_SECCS01
+#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0
+#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4
+#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8
+#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
+#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
+#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
+#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
+#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA4_ADDRDEC1_RM_SEL_SECCS23
+#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0
+#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4
+#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8
+#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
+#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
+#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
+#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
+#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA4_ADDRDEC2_BASE_ADDR_CS0
+#define MMEA4_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0
+#define MMEA4_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
+#define MMEA4_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L
+#define MMEA4_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC2_BASE_ADDR_CS1
+#define MMEA4_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0
+#define MMEA4_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
+#define MMEA4_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L
+#define MMEA4_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC2_BASE_ADDR_CS2
+#define MMEA4_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0
+#define MMEA4_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
+#define MMEA4_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L
+#define MMEA4_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC2_BASE_ADDR_CS3
+#define MMEA4_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0
+#define MMEA4_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
+#define MMEA4_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L
+#define MMEA4_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC2_BASE_ADDR_SECCS0
+#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0
+#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
+#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L
+#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC2_BASE_ADDR_SECCS1
+#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0
+#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
+#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L
+#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC2_BASE_ADDR_SECCS2
+#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0
+#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
+#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L
+#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC2_BASE_ADDR_SECCS3
+#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0
+#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
+#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L
+#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC2_ADDR_MASK_CS01
+#define MMEA4_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
+#define MMEA4_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC2_ADDR_MASK_CS23
+#define MMEA4_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
+#define MMEA4_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC2_ADDR_MASK_SECCS01
+#define MMEA4_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
+#define MMEA4_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC2_ADDR_MASK_SECCS23
+#define MMEA4_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
+#define MMEA4_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA4_ADDRDEC2_ADDR_CFG_CS01
+#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
+#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
+#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
+#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
+#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
+#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f
+#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
+#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
+#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
+#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L
+//MMEA4_ADDRDEC2_ADDR_CFG_CS23
+#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
+#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
+#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
+#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
+#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
+#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f
+#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
+#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
+#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
+#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L
+//MMEA4_ADDRDEC2_ADDR_SEL_CS01
+#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0
+#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4
+#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8
+#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc
+#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10
+#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
+#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
+#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
+#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
+#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
+#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
+#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L
+#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
+#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
+//MMEA4_ADDRDEC2_ADDR_SEL_CS23
+#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0
+#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4
+#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8
+#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc
+#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10
+#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
+#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
+#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
+#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
+#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
+#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
+#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L
+#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
+#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
+//MMEA4_ADDRDEC2_ADDR_SEL2_CS01
+#define MMEA4_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0
+#define MMEA4_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA4_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL
+#define MMEA4_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L
+//MMEA4_ADDRDEC2_ADDR_SEL2_CS23
+#define MMEA4_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0
+#define MMEA4_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA4_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL
+#define MMEA4_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L
+//MMEA4_ADDRDEC2_COL_SEL_LO_CS01
+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0
+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4
+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8
+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc
+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10
+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14
+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18
+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
+//MMEA4_ADDRDEC2_COL_SEL_LO_CS23
+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0
+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4
+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8
+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc
+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10
+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14
+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18
+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
+//MMEA4_ADDRDEC2_COL_SEL_HI_CS01
+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0
+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4
+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8
+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc
+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10
+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14
+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18
+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
+//MMEA4_ADDRDEC2_COL_SEL_HI_CS23
+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0
+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4
+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8
+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc
+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10
+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14
+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18
+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
+//MMEA4_ADDRDEC2_RM_SEL_CS01
+#define MMEA4_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0
+#define MMEA4_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4
+#define MMEA4_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8
+#define MMEA4_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA4_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA4_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA4_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL
+#define MMEA4_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L
+#define MMEA4_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L
+#define MMEA4_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA4_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA4_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA4_ADDRDEC2_RM_SEL_CS23
+#define MMEA4_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0
+#define MMEA4_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4
+#define MMEA4_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8
+#define MMEA4_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA4_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA4_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA4_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL
+#define MMEA4_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L
+#define MMEA4_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L
+#define MMEA4_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA4_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA4_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA4_ADDRDEC2_RM_SEL_SECCS01
+#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0
+#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4
+#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8
+#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
+#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
+#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
+#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
+#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA4_ADDRDEC2_RM_SEL_SECCS23
+#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0
+#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4
+#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8
+#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
+#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
+#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
+#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
+#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA4_ADDRNORMDRAM_GLOBAL_CNTL
+//MMEA4_ADDRNORMGMI_GLOBAL_CNTL
+//MMEA4_ADDRNORM_MEGACONTROL_ADDR0
+#define MMEA4_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0
+#define MMEA4_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL
+//MMEA4_ADDRNORM_MEGACONTROL_ADDR1
+#define MMEA4_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0
+#define MMEA4_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL
+//MMEA4_ADDRNORMDRAM_MASKING
+#define MMEA4_ADDRNORMDRAM_MASKING__ADDRHI_MASK__SHIFT 0x0
+#define MMEA4_ADDRNORMDRAM_MASKING__ADDRHI_MASK_MASK 0x00000FFFL
+//MMEA4_ADDRNORMGMI_MASKING
+#define MMEA4_ADDRNORMGMI_MASKING__ADDRHI_MASK__SHIFT 0x0
+#define MMEA4_ADDRNORMGMI_MASKING__ADDRHI_MASK_MASK 0x00000FFFL
+//MMEA4_IO_RD_CLI2GRP_MAP0
+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA4_IO_RD_CLI2GRP_MAP1
+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA4_IO_WR_CLI2GRP_MAP0
+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA4_IO_WR_CLI2GRP_MAP1
+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA4_IO_RD_COMBINE_FLUSH
+#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0
+#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4
+#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8
+#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc
+#define MMEA4_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10
+#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL
+#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L
+#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L
+#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L
+#define MMEA4_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L
+//MMEA4_IO_WR_COMBINE_FLUSH
+#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0
+#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4
+#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8
+#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc
+#define MMEA4_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10
+#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL
+#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L
+#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L
+#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L
+#define MMEA4_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L
+//MMEA4_IO_GROUP_BURST
+#define MMEA4_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0
+#define MMEA4_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8
+#define MMEA4_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10
+#define MMEA4_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18
+#define MMEA4_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL
+#define MMEA4_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
+#define MMEA4_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
+#define MMEA4_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L
+//MMEA4_IO_RD_PRI_AGE
+#define MMEA4_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA4_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA4_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA4_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA4_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA4_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA4_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA4_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA4_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA4_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA4_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA4_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA4_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA4_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA4_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA4_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA4_IO_WR_PRI_AGE
+#define MMEA4_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA4_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA4_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA4_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA4_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA4_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA4_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA4_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA4_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA4_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA4_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA4_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA4_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA4_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA4_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA4_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA4_IO_RD_PRI_QUEUING
+#define MMEA4_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA4_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA4_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA4_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA4_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA4_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA4_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA4_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA4_IO_WR_PRI_QUEUING
+#define MMEA4_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA4_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA4_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA4_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA4_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA4_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA4_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA4_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA4_IO_RD_PRI_FIXED
+#define MMEA4_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA4_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA4_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA4_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA4_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA4_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA4_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA4_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA4_IO_WR_PRI_FIXED
+#define MMEA4_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA4_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA4_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA4_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA4_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA4_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA4_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA4_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA4_IO_RD_PRI_URGENCY
+#define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA4_IO_WR_PRI_URGENCY
+#define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA4_IO_RD_PRI_URGENCY_MASKING
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L
+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L
+//MMEA4_IO_WR_PRI_URGENCY_MASKING
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L
+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L
+//MMEA4_IO_RD_PRI_QUANT_PRI1
+#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA4_IO_RD_PRI_QUANT_PRI2
+#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA4_IO_RD_PRI_QUANT_PRI3
+#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA4_IO_WR_PRI_QUANT_PRI1
+#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA4_IO_WR_PRI_QUANT_PRI2
+#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA4_IO_WR_PRI_QUANT_PRI3
+#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA4_SDP_ARB_DRAM
+#define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0
+#define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8
+#define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10
+#define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11
+#define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12
+#define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13
+#define MMEA4_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14
+#define MMEA4_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15
+#define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL
+#define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L
+#define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L
+#define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L
+#define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L
+#define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L
+#define MMEA4_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L
+#define MMEA4_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L
+//MMEA4_SDP_ARB_GMI
+#define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0
+#define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8
+#define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10
+#define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11
+#define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12
+#define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13
+#define MMEA4_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14
+#define MMEA4_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15
+#define MMEA4_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16
+#define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL
+#define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L
+#define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L
+#define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L
+#define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L
+#define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L
+#define MMEA4_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L
+#define MMEA4_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L
+#define MMEA4_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L
+//MMEA4_SDP_ARB_FINAL
+#define MMEA4_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0
+#define MMEA4_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5
+#define MMEA4_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa
+#define MMEA4_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf
+#define MMEA4_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11
+#define MMEA4_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12
+#define MMEA4_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13
+#define MMEA4_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14
+#define MMEA4_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15
+#define MMEA4_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16
+#define MMEA4_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17
+#define MMEA4_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18
+#define MMEA4_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19
+#define MMEA4_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a
+#define MMEA4_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b
+#define MMEA4_SDP_ARB_FINAL__DRAM_RD_THROTTLE__SHIFT 0x1c
+#define MMEA4_SDP_ARB_FINAL__DRAM_WR_THROTTLE__SHIFT 0x1d
+#define MMEA4_SDP_ARB_FINAL__GMI_RD_THROTTLE__SHIFT 0x1e
+#define MMEA4_SDP_ARB_FINAL__GMI_WR_THROTTLE__SHIFT 0x1f
+#define MMEA4_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL
+#define MMEA4_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L
+#define MMEA4_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L
+#define MMEA4_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L
+#define MMEA4_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L
+#define MMEA4_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L
+#define MMEA4_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L
+#define MMEA4_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L
+#define MMEA4_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L
+#define MMEA4_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L
+#define MMEA4_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L
+#define MMEA4_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L
+#define MMEA4_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L
+#define MMEA4_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L
+#define MMEA4_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L
+#define MMEA4_SDP_ARB_FINAL__DRAM_RD_THROTTLE_MASK 0x10000000L
+#define MMEA4_SDP_ARB_FINAL__DRAM_WR_THROTTLE_MASK 0x20000000L
+#define MMEA4_SDP_ARB_FINAL__GMI_RD_THROTTLE_MASK 0x40000000L
+#define MMEA4_SDP_ARB_FINAL__GMI_WR_THROTTLE_MASK 0x80000000L
+//MMEA4_SDP_DRAM_PRIORITY
+#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
+#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
+#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
+#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
+#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
+#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
+#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
+#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
+#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
+#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
+#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
+#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
+#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
+#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
+#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
+#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
+//MMEA4_SDP_GMI_PRIORITY
+#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
+#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
+#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
+#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
+#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
+#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
+#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
+#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
+#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
+#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
+#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
+#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
+#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
+#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
+#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
+#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
+//MMEA4_SDP_IO_PRIORITY
+#define MMEA4_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
+#define MMEA4_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
+#define MMEA4_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
+#define MMEA4_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
+#define MMEA4_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
+#define MMEA4_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
+#define MMEA4_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
+#define MMEA4_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
+#define MMEA4_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
+#define MMEA4_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
+#define MMEA4_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
+#define MMEA4_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
+#define MMEA4_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
+#define MMEA4_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
+#define MMEA4_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
+#define MMEA4_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
+//MMEA4_SDP_CREDITS
+#define MMEA4_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0
+#define MMEA4_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8
+#define MMEA4_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10
+#define MMEA4_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL
+#define MMEA4_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L
+#define MMEA4_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L
+//MMEA4_SDP_TAG_RESERVE0
+#define MMEA4_SDP_TAG_RESERVE0__VC0__SHIFT 0x0
+#define MMEA4_SDP_TAG_RESERVE0__VC1__SHIFT 0x8
+#define MMEA4_SDP_TAG_RESERVE0__VC2__SHIFT 0x10
+#define MMEA4_SDP_TAG_RESERVE0__VC3__SHIFT 0x18
+#define MMEA4_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL
+#define MMEA4_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L
+#define MMEA4_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L
+#define MMEA4_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L
+//MMEA4_SDP_TAG_RESERVE1
+#define MMEA4_SDP_TAG_RESERVE1__VC4__SHIFT 0x0
+#define MMEA4_SDP_TAG_RESERVE1__VC5__SHIFT 0x8
+#define MMEA4_SDP_TAG_RESERVE1__VC6__SHIFT 0x10
+#define MMEA4_SDP_TAG_RESERVE1__VC7__SHIFT 0x18
+#define MMEA4_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL
+#define MMEA4_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L
+#define MMEA4_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L
+#define MMEA4_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L
+//MMEA4_SDP_VCC_RESERVE0
+#define MMEA4_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0
+#define MMEA4_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6
+#define MMEA4_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc
+#define MMEA4_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12
+#define MMEA4_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18
+#define MMEA4_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL
+#define MMEA4_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L
+#define MMEA4_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L
+#define MMEA4_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L
+#define MMEA4_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L
+//MMEA4_SDP_VCC_RESERVE1
+#define MMEA4_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0
+#define MMEA4_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6
+#define MMEA4_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc
+#define MMEA4_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f
+#define MMEA4_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL
+#define MMEA4_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L
+#define MMEA4_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L
+#define MMEA4_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L
+//MMEA4_SDP_VCD_RESERVE0
+#define MMEA4_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0
+#define MMEA4_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6
+#define MMEA4_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc
+#define MMEA4_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12
+#define MMEA4_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18
+#define MMEA4_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL
+#define MMEA4_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L
+#define MMEA4_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L
+#define MMEA4_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L
+#define MMEA4_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L
+//MMEA4_SDP_VCD_RESERVE1
+#define MMEA4_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0
+#define MMEA4_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6
+#define MMEA4_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc
+#define MMEA4_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f
+#define MMEA4_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL
+#define MMEA4_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L
+#define MMEA4_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L
+#define MMEA4_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L
+//MMEA4_SDP_REQ_CNTL
+#define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0
+#define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1
+#define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2
+#define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3
+#define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4
+#define MMEA4_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5
+#define MMEA4_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6
+#define MMEA4_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8
+#define MMEA4_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa
+#define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L
+#define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L
+#define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L
+#define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L
+#define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L
+#define MMEA4_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L
+#define MMEA4_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L
+#define MMEA4_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L
+#define MMEA4_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L
+//MMEA4_MISC
+#define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0
+#define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1
+#define MMEA4_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2
+#define MMEA4_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3
+#define MMEA4_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4
+#define MMEA4_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5
+#define MMEA4_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6
+#define MMEA4_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7
+#define MMEA4_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8
+#define MMEA4_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9
+#define MMEA4_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa
+#define MMEA4_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb
+#define MMEA4_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc
+#define MMEA4_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd
+#define MMEA4_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe
+#define MMEA4_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf
+#define MMEA4_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11
+#define MMEA4_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13
+#define MMEA4_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15
+#define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a
+#define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b
+#define MMEA4_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c
+#define MMEA4_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d
+#define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e
+#define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f
+#define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L
+#define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L
+#define MMEA4_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L
+#define MMEA4_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L
+#define MMEA4_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L
+#define MMEA4_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L
+#define MMEA4_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L
+#define MMEA4_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L
+#define MMEA4_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L
+#define MMEA4_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L
+#define MMEA4_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L
+#define MMEA4_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L
+#define MMEA4_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L
+#define MMEA4_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L
+#define MMEA4_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L
+#define MMEA4_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L
+#define MMEA4_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L
+#define MMEA4_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L
+#define MMEA4_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L
+#define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L
+#define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L
+#define MMEA4_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L
+#define MMEA4_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L
+#define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L
+#define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L
+//MMEA4_LATENCY_SAMPLING
+#define MMEA4_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0
+#define MMEA4_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1
+#define MMEA4_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2
+#define MMEA4_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3
+#define MMEA4_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4
+#define MMEA4_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5
+#define MMEA4_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6
+#define MMEA4_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7
+#define MMEA4_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8
+#define MMEA4_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9
+#define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa
+#define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb
+#define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc
+#define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd
+#define MMEA4_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe
+#define MMEA4_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16
+#define MMEA4_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L
+#define MMEA4_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L
+#define MMEA4_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L
+#define MMEA4_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L
+#define MMEA4_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L
+#define MMEA4_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L
+#define MMEA4_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L
+#define MMEA4_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L
+#define MMEA4_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L
+#define MMEA4_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L
+#define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L
+#define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L
+#define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L
+#define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L
+#define MMEA4_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L
+#define MMEA4_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L
+//MMEA4_PERFCOUNTER_LO
+#define MMEA4_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MMEA4_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//MMEA4_PERFCOUNTER_HI
+#define MMEA4_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MMEA4_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MMEA4_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define MMEA4_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//MMEA4_PERFCOUNTER0_CFG
+#define MMEA4_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MMEA4_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMEA4_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MMEA4_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MMEA4_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MMEA4_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMEA4_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMEA4_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMEA4_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define MMEA4_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//MMEA4_PERFCOUNTER1_CFG
+#define MMEA4_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MMEA4_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMEA4_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MMEA4_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MMEA4_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MMEA4_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMEA4_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMEA4_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMEA4_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define MMEA4_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//MMEA4_PERFCOUNTER_RSLT_CNTL
+#define MMEA4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MMEA4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MMEA4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MMEA4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MMEA4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define MMEA4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define MMEA4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define MMEA4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+//MMEA4_EDC_CNT
+#define MMEA4_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0
+#define MMEA4_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2
+#define MMEA4_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4
+#define MMEA4_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6
+#define MMEA4_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8
+#define MMEA4_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa
+#define MMEA4_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc
+#define MMEA4_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe
+#define MMEA4_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10
+#define MMEA4_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12
+#define MMEA4_EDC_CNT__IOWR_DATAMEM_SEC_COUNT__SHIFT 0x14
+#define MMEA4_EDC_CNT__IOWR_DATAMEM_DED_COUNT__SHIFT 0x16
+#define MMEA4_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x18
+#define MMEA4_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x1a
+#define MMEA4_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x1c
+#define MMEA4_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1e
+#define MMEA4_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
+#define MMEA4_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
+#define MMEA4_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
+#define MMEA4_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
+#define MMEA4_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
+#define MMEA4_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
+#define MMEA4_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L
+#define MMEA4_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L
+#define MMEA4_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L
+#define MMEA4_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L
+#define MMEA4_EDC_CNT__IOWR_DATAMEM_SEC_COUNT_MASK 0x00300000L
+#define MMEA4_EDC_CNT__IOWR_DATAMEM_DED_COUNT_MASK 0x00C00000L
+#define MMEA4_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x03000000L
+#define MMEA4_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x0C000000L
+#define MMEA4_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x30000000L
+#define MMEA4_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0xC0000000L
+//MMEA4_EDC_CNT2
+#define MMEA4_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0
+#define MMEA4_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2
+#define MMEA4_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4
+#define MMEA4_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6
+#define MMEA4_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8
+#define MMEA4_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa
+#define MMEA4_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc
+#define MMEA4_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe
+#define MMEA4_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10
+#define MMEA4_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12
+#define MMEA4_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14
+#define MMEA4_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16
+#define MMEA4_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT 0x18
+#define MMEA4_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT 0x1a
+#define MMEA4_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT 0x1c
+#define MMEA4_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT 0x1e
+#define MMEA4_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
+#define MMEA4_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
+#define MMEA4_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
+#define MMEA4_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
+#define MMEA4_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
+#define MMEA4_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
+#define MMEA4_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L
+#define MMEA4_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L
+#define MMEA4_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L
+#define MMEA4_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L
+#define MMEA4_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L
+#define MMEA4_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L
+#define MMEA4_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK 0x03000000L
+#define MMEA4_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK 0x0C000000L
+#define MMEA4_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK 0x30000000L
+#define MMEA4_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK 0xC0000000L
+//MMEA4_DSM_CNTL
+#define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3
+#define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define MMEA4_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9
+#define MMEA4_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb
+#define MMEA4_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc
+#define MMEA4_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
+#define MMEA4_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf
+#define MMEA4_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11
+#define MMEA4_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12
+#define MMEA4_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14
+#define MMEA4_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15
+#define MMEA4_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17
+#define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
+#define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define MMEA4_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L
+#define MMEA4_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
+#define MMEA4_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L
+#define MMEA4_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
+#define MMEA4_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L
+#define MMEA4_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L
+#define MMEA4_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L
+#define MMEA4_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L
+#define MMEA4_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L
+#define MMEA4_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L
+//MMEA4_DSM_CNTLA
+#define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3
+#define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define MMEA4_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define MMEA4_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define MMEA4_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9
+#define MMEA4_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb
+#define MMEA4_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc
+#define MMEA4_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
+#define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf
+#define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11
+#define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12
+#define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14
+#define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
+#define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define MMEA4_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define MMEA4_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define MMEA4_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L
+#define MMEA4_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
+#define MMEA4_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L
+#define MMEA4_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
+#define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L
+#define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L
+#define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L
+#define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L
+//MMEA4_DSM_CNTLB
+//MMEA4_DSM_CNTL2
+#define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5
+#define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8
+#define MMEA4_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define MMEA4_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb
+#define MMEA4_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define MMEA4_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe
+#define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11
+#define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14
+#define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15
+#define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17
+#define MMEA4_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
+#define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define MMEA4_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define MMEA4_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define MMEA4_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define MMEA4_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L
+#define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L
+#define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L
+#define MMEA4_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
+//MMEA4_DSM_CNTL2A
+#define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5
+#define MMEA4_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define MMEA4_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8
+#define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb
+#define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe
+#define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11
+#define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14
+#define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define MMEA4_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define MMEA4_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L
+//MMEA4_DSM_CNTL2B
+//MMEA4_CGTT_CLK_CTRL
+#define MMEA4_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define MMEA4_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define MMEA4_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc
+#define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14
+#define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15
+#define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16
+#define MMEA4_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17
+#define MMEA4_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c
+#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d
+#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e
+#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f
+#define MMEA4_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define MMEA4_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define MMEA4_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L
+#define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L
+#define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L
+#define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L
+#define MMEA4_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L
+#define MMEA4_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L
+#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L
+#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L
+#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L
+//MMEA4_EDC_MODE
+#define MMEA4_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10
+#define MMEA4_EDC_MODE__GATE_FUE__SHIFT 0x11
+#define MMEA4_EDC_MODE__DED_MODE__SHIFT 0x14
+#define MMEA4_EDC_MODE__PROP_FED__SHIFT 0x1d
+#define MMEA4_EDC_MODE__BYPASS__SHIFT 0x1f
+#define MMEA4_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L
+#define MMEA4_EDC_MODE__GATE_FUE_MASK 0x00020000L
+#define MMEA4_EDC_MODE__DED_MODE_MASK 0x00300000L
+#define MMEA4_EDC_MODE__PROP_FED_MASK 0x20000000L
+#define MMEA4_EDC_MODE__BYPASS_MASK 0x80000000L
+//MMEA4_ERR_STATUS
+#define MMEA4_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0
+#define MMEA4_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4
+#define MMEA4_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8
+#define MMEA4_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa
+#define MMEA4_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb
+#define MMEA4_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc
+#define MMEA4_ERR_STATUS__FUE_FLAG__SHIFT 0xd
+#define MMEA4_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe
+#define MMEA4_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf
+#define MMEA4_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10
+#define MMEA4_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11
+#define MMEA4_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12
+#define MMEA4_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL
+#define MMEA4_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L
+#define MMEA4_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L
+#define MMEA4_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L
+#define MMEA4_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L
+#define MMEA4_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L
+#define MMEA4_ERR_STATUS__FUE_FLAG_MASK 0x00002000L
+#define MMEA4_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L
+#define MMEA4_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L
+#define MMEA4_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L
+#define MMEA4_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L
+#define MMEA4_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L
+//MMEA4_MISC2
+#define MMEA4_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0
+#define MMEA4_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1
+#define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2
+#define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7
+#define MMEA4_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc
+#define MMEA4_MISC2__RRET_SWAP_MODE__SHIFT 0xd
+#define MMEA4_MISC2__BLOCK_REQUESTS__SHIFT 0xe
+#define MMEA4_MISC2__REQUESTS_BLOCKED__SHIFT 0xf
+#define MMEA4_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L
+#define MMEA4_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L
+#define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL
+#define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L
+#define MMEA4_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L
+#define MMEA4_MISC2__RRET_SWAP_MODE_MASK 0x00002000L
+#define MMEA4_MISC2__BLOCK_REQUESTS_MASK 0x00004000L
+#define MMEA4_MISC2__REQUESTS_BLOCKED_MASK 0x00008000L
+//MMEA4_ADDRDEC_SELECT
+#define MMEA4_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0
+#define MMEA4_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5
+#define MMEA4_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa
+#define MMEA4_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf
+#define MMEA4_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL
+#define MMEA4_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L
+#define MMEA4_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L
+#define MMEA4_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L
+//MMEA4_EDC_CNT3
+#define MMEA4_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0
+#define MMEA4_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2
+#define MMEA4_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4
+#define MMEA4_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6
+#define MMEA4_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0x8
+#define MMEA4_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xa
+#define MMEA4_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L
+#define MMEA4_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL
+#define MMEA4_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L
+#define MMEA4_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
+#define MMEA4_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000300L
+#define MMEA4_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00000C00L
+//MMEA4_MISC_AON
+#define MMEA4_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0
+#define MMEA4_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2
+#define MMEA4_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L
+#define MMEA4_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L
+
+
+// addressBlock: mmhub_ea_mmeadec5
+//MMEA5_DRAM_RD_CLI2GRP_MAP0
+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA5_DRAM_RD_CLI2GRP_MAP1
+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA5_DRAM_WR_CLI2GRP_MAP0
+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA5_DRAM_WR_CLI2GRP_MAP1
+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA5_DRAM_RD_GRP2VC_MAP
+#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
+#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
+#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
+#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
+#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
+#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
+#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
+#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
+//MMEA5_DRAM_WR_GRP2VC_MAP
+#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
+#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
+#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
+#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
+#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
+#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
+#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
+#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
+//MMEA5_DRAM_RD_LAZY
+#define MMEA5_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0
+#define MMEA5_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3
+#define MMEA5_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6
+#define MMEA5_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9
+#define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
+#define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
+#define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b
+#define MMEA5_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L
+#define MMEA5_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L
+#define MMEA5_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L
+#define MMEA5_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L
+#define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
+#define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
+#define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L
+//MMEA5_DRAM_WR_LAZY
+#define MMEA5_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0
+#define MMEA5_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3
+#define MMEA5_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6
+#define MMEA5_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9
+#define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
+#define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
+#define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b
+#define MMEA5_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L
+#define MMEA5_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L
+#define MMEA5_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L
+#define MMEA5_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L
+#define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
+#define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
+#define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L
+//MMEA5_DRAM_RD_CAM_CNTL
+#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
+#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
+#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
+#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
+#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
+#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
+#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
+#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
+#define MMEA5_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c
+#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
+#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
+#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
+#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
+#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
+#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
+#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
+#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
+#define MMEA5_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L
+//MMEA5_DRAM_WR_CAM_CNTL
+#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
+#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
+#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
+#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
+#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
+#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
+#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
+#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
+#define MMEA5_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c
+#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
+#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
+#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
+#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
+#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
+#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
+#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
+#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
+#define MMEA5_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L
+//MMEA5_DRAM_PAGE_BURST
+#define MMEA5_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0
+#define MMEA5_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8
+#define MMEA5_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10
+#define MMEA5_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18
+#define MMEA5_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL
+#define MMEA5_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
+#define MMEA5_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
+#define MMEA5_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L
+//MMEA5_DRAM_RD_PRI_AGE
+#define MMEA5_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA5_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA5_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA5_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA5_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA5_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA5_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA5_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA5_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA5_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA5_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA5_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA5_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA5_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA5_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA5_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA5_DRAM_WR_PRI_AGE
+#define MMEA5_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA5_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA5_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA5_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA5_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA5_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA5_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA5_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA5_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA5_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA5_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA5_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA5_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA5_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA5_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA5_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA5_DRAM_RD_PRI_QUEUING
+#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA5_DRAM_WR_PRI_QUEUING
+#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA5_DRAM_RD_PRI_FIXED
+#define MMEA5_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA5_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA5_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA5_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA5_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA5_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA5_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA5_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA5_DRAM_WR_PRI_FIXED
+#define MMEA5_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA5_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA5_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA5_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA5_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA5_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA5_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA5_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA5_DRAM_RD_PRI_URGENCY
+#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA5_DRAM_WR_PRI_URGENCY
+#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA5_DRAM_RD_PRI_QUANT_PRI1
+#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA5_DRAM_RD_PRI_QUANT_PRI2
+#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA5_DRAM_RD_PRI_QUANT_PRI3
+#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA5_DRAM_WR_PRI_QUANT_PRI1
+#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA5_DRAM_WR_PRI_QUANT_PRI2
+#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA5_DRAM_WR_PRI_QUANT_PRI3
+#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA5_GMI_RD_CLI2GRP_MAP0
+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA5_GMI_RD_CLI2GRP_MAP1
+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA5_GMI_WR_CLI2GRP_MAP0
+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA5_GMI_WR_CLI2GRP_MAP1
+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA5_GMI_RD_GRP2VC_MAP
+#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
+#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
+#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
+#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
+#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
+#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
+#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
+#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
+//MMEA5_GMI_WR_GRP2VC_MAP
+#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
+#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
+#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
+#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
+#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
+#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
+#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
+#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
+//MMEA5_GMI_RD_LAZY
+#define MMEA5_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0
+#define MMEA5_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3
+#define MMEA5_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6
+#define MMEA5_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9
+#define MMEA5_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
+#define MMEA5_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
+#define MMEA5_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b
+#define MMEA5_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L
+#define MMEA5_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L
+#define MMEA5_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L
+#define MMEA5_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L
+#define MMEA5_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
+#define MMEA5_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
+#define MMEA5_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L
+//MMEA5_GMI_WR_LAZY
+#define MMEA5_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0
+#define MMEA5_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3
+#define MMEA5_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6
+#define MMEA5_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9
+#define MMEA5_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
+#define MMEA5_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
+#define MMEA5_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b
+#define MMEA5_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L
+#define MMEA5_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L
+#define MMEA5_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L
+#define MMEA5_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L
+#define MMEA5_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
+#define MMEA5_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
+#define MMEA5_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L
+//MMEA5_GMI_RD_CAM_CNTL
+#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
+#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
+#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
+#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
+#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
+#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
+#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
+#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
+#define MMEA5_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c
+#define MMEA5_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d
+#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
+#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
+#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
+#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
+#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
+#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
+#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
+#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
+#define MMEA5_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L
+#define MMEA5_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L
+//MMEA5_GMI_WR_CAM_CNTL
+#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
+#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
+#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
+#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
+#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
+#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
+#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
+#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
+#define MMEA5_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c
+#define MMEA5_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d
+#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
+#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
+#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
+#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
+#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
+#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
+#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
+#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
+#define MMEA5_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L
+#define MMEA5_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L
+//MMEA5_GMI_PAGE_BURST
+#define MMEA5_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0
+#define MMEA5_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8
+#define MMEA5_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10
+#define MMEA5_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18
+#define MMEA5_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL
+#define MMEA5_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
+#define MMEA5_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
+#define MMEA5_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L
+//MMEA5_GMI_RD_PRI_AGE
+#define MMEA5_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA5_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA5_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA5_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA5_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA5_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA5_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA5_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA5_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA5_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA5_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA5_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA5_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA5_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA5_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA5_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA5_GMI_WR_PRI_AGE
+#define MMEA5_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA5_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA5_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA5_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA5_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA5_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA5_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA5_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA5_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA5_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA5_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA5_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA5_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA5_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA5_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA5_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA5_GMI_RD_PRI_QUEUING
+#define MMEA5_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA5_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA5_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA5_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA5_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA5_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA5_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA5_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA5_GMI_WR_PRI_QUEUING
+#define MMEA5_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA5_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA5_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA5_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA5_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA5_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA5_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA5_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA5_GMI_RD_PRI_FIXED
+#define MMEA5_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA5_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA5_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA5_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA5_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA5_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA5_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA5_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA5_GMI_WR_PRI_FIXED
+#define MMEA5_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA5_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA5_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA5_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA5_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA5_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA5_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA5_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA5_GMI_RD_PRI_URGENCY
+#define MMEA5_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA5_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA5_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA5_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA5_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA5_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA5_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA5_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA5_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA5_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA5_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA5_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA5_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA5_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA5_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA5_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA5_GMI_WR_PRI_URGENCY
+#define MMEA5_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA5_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA5_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA5_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA5_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA5_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA5_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA5_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA5_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA5_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA5_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA5_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA5_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA5_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA5_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA5_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA5_GMI_RD_PRI_URGENCY_MASKING
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L
+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L
+//MMEA5_GMI_WR_PRI_URGENCY_MASKING
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L
+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L
+//MMEA5_GMI_RD_PRI_QUANT_PRI1
+#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA5_GMI_RD_PRI_QUANT_PRI2
+#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA5_GMI_RD_PRI_QUANT_PRI3
+#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA5_GMI_WR_PRI_QUANT_PRI1
+#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA5_GMI_WR_PRI_QUANT_PRI2
+#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA5_GMI_WR_PRI_QUANT_PRI3
+#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA5_ADDRNORM_BASE_ADDR0
+#define MMEA5_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA5_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA5_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc
+#define MMEA5_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA5_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA5_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA5_ADDRNORM_LIMIT_ADDR0
+#define MMEA5_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA5_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc
+#define MMEA5_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA5_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA5_ADDRNORM_BASE_ADDR1
+#define MMEA5_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA5_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA5_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc
+#define MMEA5_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA5_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA5_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA5_ADDRNORM_LIMIT_ADDR1
+#define MMEA5_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA5_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc
+#define MMEA5_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA5_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA5_ADDRNORM_OFFSET_ADDR1
+#define MMEA5_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0
+#define MMEA5_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0xc
+#define MMEA5_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L
+#define MMEA5_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0x00FFF000L
+//MMEA5_ADDRNORM_BASE_ADDR2
+#define MMEA5_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA5_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA5_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc
+#define MMEA5_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA5_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA5_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA5_ADDRNORM_LIMIT_ADDR2
+#define MMEA5_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA5_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc
+#define MMEA5_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA5_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA5_ADDRNORM_BASE_ADDR3
+#define MMEA5_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA5_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA5_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc
+#define MMEA5_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA5_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA5_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA5_ADDRNORM_LIMIT_ADDR3
+#define MMEA5_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA5_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc
+#define MMEA5_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA5_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA5_ADDRNORM_OFFSET_ADDR3
+#define MMEA5_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0
+#define MMEA5_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0xc
+#define MMEA5_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L
+#define MMEA5_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0x00FFF000L
+//MMEA5_ADDRNORM_MEGABASE_ADDR0
+#define MMEA5_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA5_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA5_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA5_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA5_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA5_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA5_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR__SHIFT 0xc
+#define MMEA5_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA5_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA5_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA5_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA5_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA5_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA5_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA5_ADDRNORM_MEGALIMIT_ADDR0
+#define MMEA5_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA5_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc
+#define MMEA5_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA5_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA5_ADDRNORM_MEGABASE_ADDR1
+#define MMEA5_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA5_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA5_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA5_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7
+#define MMEA5_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA5_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA5_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR__SHIFT 0xc
+#define MMEA5_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA5_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA5_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL
+#define MMEA5_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L
+#define MMEA5_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA5_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA5_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA5_ADDRNORM_MEGALIMIT_ADDR1
+#define MMEA5_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA5_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc
+#define MMEA5_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA5_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA5_ADDRNORMDRAM_HOLE_CNTL
+#define MMEA5_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0
+#define MMEA5_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7
+#define MMEA5_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L
+#define MMEA5_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L
+//MMEA5_ADDRNORMGMI_HOLE_CNTL
+#define MMEA5_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0
+#define MMEA5_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7
+#define MMEA5_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L
+#define MMEA5_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L
+//MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG
+#define MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0
+#define MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6
+#define MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL
+#define MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L
+//MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG
+#define MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0
+#define MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6
+#define MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL
+#define MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L
+//MMEA5_ADDRDEC_BANK_CFG
+#define MMEA5_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0
+#define MMEA5_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6
+#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc
+#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf
+#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12
+#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13
+#define MMEA5_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL
+#define MMEA5_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L
+#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L
+#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L
+#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L
+#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L
+//MMEA5_ADDRDEC_MISC_CFG
+#define MMEA5_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0
+#define MMEA5_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1
+#define MMEA5_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2
+#define MMEA5_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8
+#define MMEA5_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9
+#define MMEA5_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc
+#define MMEA5_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11
+#define MMEA5_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16
+#define MMEA5_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18
+#define MMEA5_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a
+#define MMEA5_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d
+#define MMEA5_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L
+#define MMEA5_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L
+#define MMEA5_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L
+#define MMEA5_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L
+#define MMEA5_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L
+#define MMEA5_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L
+#define MMEA5_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L
+#define MMEA5_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L
+#define MMEA5_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L
+#define MMEA5_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L
+#define MMEA5_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L
+//MMEA5_ADDRDECDRAM_HARVEST_ENABLE
+#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0
+#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1
+#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2
+#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3
+#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4
+#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5
+#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L
+#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L
+#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L
+#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L
+#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L
+#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L
+//MMEA5_ADDRDECGMI_HARVEST_ENABLE
+#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0
+#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1
+#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2
+#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3
+#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4
+#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5
+#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L
+#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L
+#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L
+#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L
+#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L
+#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L
+//MMEA5_ADDRDEC0_BASE_ADDR_CS0
+#define MMEA5_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0
+#define MMEA5_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
+#define MMEA5_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L
+#define MMEA5_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC0_BASE_ADDR_CS1
+#define MMEA5_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0
+#define MMEA5_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
+#define MMEA5_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L
+#define MMEA5_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC0_BASE_ADDR_CS2
+#define MMEA5_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0
+#define MMEA5_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
+#define MMEA5_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L
+#define MMEA5_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC0_BASE_ADDR_CS3
+#define MMEA5_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0
+#define MMEA5_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
+#define MMEA5_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L
+#define MMEA5_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC0_BASE_ADDR_SECCS0
+#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0
+#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
+#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L
+#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC0_BASE_ADDR_SECCS1
+#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0
+#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
+#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L
+#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC0_BASE_ADDR_SECCS2
+#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0
+#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
+#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L
+#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC0_BASE_ADDR_SECCS3
+#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0
+#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
+#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L
+#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC0_ADDR_MASK_CS01
+#define MMEA5_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
+#define MMEA5_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC0_ADDR_MASK_CS23
+#define MMEA5_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
+#define MMEA5_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC0_ADDR_MASK_SECCS01
+#define MMEA5_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
+#define MMEA5_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC0_ADDR_MASK_SECCS23
+#define MMEA5_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
+#define MMEA5_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC0_ADDR_CFG_CS01
+#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
+#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
+#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
+#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
+#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
+#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f
+#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
+#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
+#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
+#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L
+//MMEA5_ADDRDEC0_ADDR_CFG_CS23
+#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
+#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
+#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
+#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
+#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
+#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f
+#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
+#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
+#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
+#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L
+//MMEA5_ADDRDEC0_ADDR_SEL_CS01
+#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0
+#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4
+#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8
+#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc
+#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10
+#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
+#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
+#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
+#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
+#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
+#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
+#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L
+#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
+#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
+//MMEA5_ADDRDEC0_ADDR_SEL_CS23
+#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0
+#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4
+#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8
+#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc
+#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10
+#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
+#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
+#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
+#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
+#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
+#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
+#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L
+#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
+#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
+//MMEA5_ADDRDEC0_ADDR_SEL2_CS01
+#define MMEA5_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0
+#define MMEA5_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA5_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL
+#define MMEA5_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L
+//MMEA5_ADDRDEC0_ADDR_SEL2_CS23
+#define MMEA5_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0
+#define MMEA5_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA5_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL
+#define MMEA5_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L
+//MMEA5_ADDRDEC0_COL_SEL_LO_CS01
+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0
+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4
+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8
+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc
+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10
+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14
+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18
+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
+//MMEA5_ADDRDEC0_COL_SEL_LO_CS23
+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0
+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4
+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8
+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc
+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10
+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14
+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18
+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
+//MMEA5_ADDRDEC0_COL_SEL_HI_CS01
+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0
+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4
+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8
+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc
+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10
+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14
+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18
+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
+//MMEA5_ADDRDEC0_COL_SEL_HI_CS23
+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0
+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4
+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8
+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc
+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10
+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14
+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18
+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
+//MMEA5_ADDRDEC0_RM_SEL_CS01
+#define MMEA5_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0
+#define MMEA5_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4
+#define MMEA5_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8
+#define MMEA5_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA5_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA5_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA5_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL
+#define MMEA5_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L
+#define MMEA5_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L
+#define MMEA5_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA5_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA5_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA5_ADDRDEC0_RM_SEL_CS23
+#define MMEA5_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0
+#define MMEA5_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4
+#define MMEA5_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8
+#define MMEA5_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA5_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA5_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA5_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL
+#define MMEA5_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L
+#define MMEA5_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L
+#define MMEA5_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA5_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA5_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA5_ADDRDEC0_RM_SEL_SECCS01
+#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0
+#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4
+#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8
+#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
+#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
+#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
+#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
+#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA5_ADDRDEC0_RM_SEL_SECCS23
+#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0
+#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4
+#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8
+#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
+#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
+#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
+#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
+#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA5_ADDRDEC1_BASE_ADDR_CS0
+#define MMEA5_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0
+#define MMEA5_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
+#define MMEA5_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L
+#define MMEA5_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC1_BASE_ADDR_CS1
+#define MMEA5_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0
+#define MMEA5_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
+#define MMEA5_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L
+#define MMEA5_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC1_BASE_ADDR_CS2
+#define MMEA5_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0
+#define MMEA5_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
+#define MMEA5_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L
+#define MMEA5_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC1_BASE_ADDR_CS3
+#define MMEA5_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0
+#define MMEA5_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
+#define MMEA5_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L
+#define MMEA5_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC1_BASE_ADDR_SECCS0
+#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0
+#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
+#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L
+#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC1_BASE_ADDR_SECCS1
+#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0
+#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
+#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L
+#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC1_BASE_ADDR_SECCS2
+#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0
+#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
+#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L
+#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC1_BASE_ADDR_SECCS3
+#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0
+#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
+#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L
+#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC1_ADDR_MASK_CS01
+#define MMEA5_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
+#define MMEA5_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC1_ADDR_MASK_CS23
+#define MMEA5_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
+#define MMEA5_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC1_ADDR_MASK_SECCS01
+#define MMEA5_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
+#define MMEA5_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC1_ADDR_MASK_SECCS23
+#define MMEA5_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
+#define MMEA5_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC1_ADDR_CFG_CS01
+#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
+#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
+#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
+#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
+#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
+#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f
+#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
+#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
+#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
+#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L
+//MMEA5_ADDRDEC1_ADDR_CFG_CS23
+#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
+#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
+#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
+#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
+#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
+#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f
+#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
+#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
+#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
+#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L
+//MMEA5_ADDRDEC1_ADDR_SEL_CS01
+#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0
+#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4
+#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8
+#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc
+#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10
+#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
+#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
+#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
+#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
+#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
+#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
+#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L
+#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
+#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
+//MMEA5_ADDRDEC1_ADDR_SEL_CS23
+#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0
+#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4
+#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8
+#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc
+#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10
+#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
+#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
+#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
+#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
+#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
+#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
+#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L
+#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
+#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
+//MMEA5_ADDRDEC1_ADDR_SEL2_CS01
+#define MMEA5_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0
+#define MMEA5_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA5_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL
+#define MMEA5_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L
+//MMEA5_ADDRDEC1_ADDR_SEL2_CS23
+#define MMEA5_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0
+#define MMEA5_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA5_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL
+#define MMEA5_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L
+//MMEA5_ADDRDEC1_COL_SEL_LO_CS01
+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0
+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4
+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8
+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc
+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10
+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14
+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18
+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
+//MMEA5_ADDRDEC1_COL_SEL_LO_CS23
+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0
+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4
+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8
+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc
+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10
+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14
+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18
+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
+//MMEA5_ADDRDEC1_COL_SEL_HI_CS01
+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0
+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4
+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8
+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc
+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10
+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14
+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18
+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
+//MMEA5_ADDRDEC1_COL_SEL_HI_CS23
+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0
+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4
+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8
+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc
+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10
+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14
+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18
+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
+//MMEA5_ADDRDEC1_RM_SEL_CS01
+#define MMEA5_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0
+#define MMEA5_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4
+#define MMEA5_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8
+#define MMEA5_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA5_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA5_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA5_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL
+#define MMEA5_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L
+#define MMEA5_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L
+#define MMEA5_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA5_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA5_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA5_ADDRDEC1_RM_SEL_CS23
+#define MMEA5_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0
+#define MMEA5_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4
+#define MMEA5_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8
+#define MMEA5_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA5_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA5_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA5_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL
+#define MMEA5_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L
+#define MMEA5_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L
+#define MMEA5_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA5_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA5_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA5_ADDRDEC1_RM_SEL_SECCS01
+#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0
+#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4
+#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8
+#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
+#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
+#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
+#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
+#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA5_ADDRDEC1_RM_SEL_SECCS23
+#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0
+#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4
+#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8
+#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
+#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
+#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
+#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
+#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA5_ADDRDEC2_BASE_ADDR_CS0
+#define MMEA5_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0
+#define MMEA5_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
+#define MMEA5_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L
+#define MMEA5_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC2_BASE_ADDR_CS1
+#define MMEA5_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0
+#define MMEA5_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
+#define MMEA5_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L
+#define MMEA5_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC2_BASE_ADDR_CS2
+#define MMEA5_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0
+#define MMEA5_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
+#define MMEA5_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L
+#define MMEA5_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC2_BASE_ADDR_CS3
+#define MMEA5_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0
+#define MMEA5_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
+#define MMEA5_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L
+#define MMEA5_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC2_BASE_ADDR_SECCS0
+#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0
+#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
+#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L
+#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC2_BASE_ADDR_SECCS1
+#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0
+#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
+#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L
+#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC2_BASE_ADDR_SECCS2
+#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0
+#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
+#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L
+#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC2_BASE_ADDR_SECCS3
+#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0
+#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
+#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L
+#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC2_ADDR_MASK_CS01
+#define MMEA5_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
+#define MMEA5_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC2_ADDR_MASK_CS23
+#define MMEA5_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
+#define MMEA5_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC2_ADDR_MASK_SECCS01
+#define MMEA5_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
+#define MMEA5_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC2_ADDR_MASK_SECCS23
+#define MMEA5_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
+#define MMEA5_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA5_ADDRDEC2_ADDR_CFG_CS01
+#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
+#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
+#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
+#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
+#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
+#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f
+#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
+#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
+#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
+#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L
+//MMEA5_ADDRDEC2_ADDR_CFG_CS23
+#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1
+#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
+#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
+#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
+#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
+#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
+#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f
+#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL
+#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
+#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
+#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
+#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L
+//MMEA5_ADDRDEC2_ADDR_SEL_CS01
+#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0
+#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4
+#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8
+#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc
+#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10
+#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
+#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
+#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
+#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
+#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
+#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
+#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L
+#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
+#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
+//MMEA5_ADDRDEC2_ADDR_SEL_CS23
+#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0
+#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4
+#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8
+#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc
+#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10
+#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
+#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
+#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
+#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
+#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
+#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
+#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L
+#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
+#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
+//MMEA5_ADDRDEC2_ADDR_SEL2_CS01
+#define MMEA5_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0
+#define MMEA5_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA5_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL
+#define MMEA5_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L
+//MMEA5_ADDRDEC2_ADDR_SEL2_CS23
+#define MMEA5_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0
+#define MMEA5_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA5_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL
+#define MMEA5_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L
+//MMEA5_ADDRDEC2_COL_SEL_LO_CS01
+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0
+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4
+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8
+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc
+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10
+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14
+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18
+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
+//MMEA5_ADDRDEC2_COL_SEL_LO_CS23
+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0
+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4
+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8
+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc
+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10
+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14
+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18
+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
+//MMEA5_ADDRDEC2_COL_SEL_HI_CS01
+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0
+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4
+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8
+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc
+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10
+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14
+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18
+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
+//MMEA5_ADDRDEC2_COL_SEL_HI_CS23
+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0
+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4
+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8
+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc
+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10
+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14
+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18
+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
+//MMEA5_ADDRDEC2_RM_SEL_CS01
+#define MMEA5_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0
+#define MMEA5_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4
+#define MMEA5_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8
+#define MMEA5_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA5_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA5_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA5_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL
+#define MMEA5_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L
+#define MMEA5_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L
+#define MMEA5_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA5_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA5_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA5_ADDRDEC2_RM_SEL_CS23
+#define MMEA5_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0
+#define MMEA5_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4
+#define MMEA5_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8
+#define MMEA5_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA5_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA5_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA5_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL
+#define MMEA5_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L
+#define MMEA5_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L
+#define MMEA5_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA5_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA5_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA5_ADDRDEC2_RM_SEL_SECCS01
+#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0
+#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4
+#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8
+#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
+#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
+#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
+#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
+#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA5_ADDRDEC2_RM_SEL_SECCS23
+#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0
+#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4
+#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8
+#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
+#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
+#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
+#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
+#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA5_ADDRNORMDRAM_GLOBAL_CNTL
+//MMEA5_ADDRNORMGMI_GLOBAL_CNTL
+//MMEA5_ADDRNORM_MEGACONTROL_ADDR0
+#define MMEA5_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0
+#define MMEA5_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL
+//MMEA5_ADDRNORM_MEGACONTROL_ADDR1
+#define MMEA5_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0
+#define MMEA5_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL
+//MMEA5_ADDRNORMDRAM_MASKING
+#define MMEA5_ADDRNORMDRAM_MASKING__ADDRHI_MASK__SHIFT 0x0
+#define MMEA5_ADDRNORMDRAM_MASKING__ADDRHI_MASK_MASK 0x00000FFFL
+//MMEA5_ADDRNORMGMI_MASKING
+#define MMEA5_ADDRNORMGMI_MASKING__ADDRHI_MASK__SHIFT 0x0
+#define MMEA5_ADDRNORMGMI_MASKING__ADDRHI_MASK_MASK 0x00000FFFL
+//MMEA5_IO_RD_CLI2GRP_MAP0
+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA5_IO_RD_CLI2GRP_MAP1
+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA5_IO_WR_CLI2GRP_MAP0
+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA5_IO_WR_CLI2GRP_MAP1
+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA5_IO_RD_COMBINE_FLUSH
+#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0
+#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4
+#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8
+#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc
+#define MMEA5_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10
+#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL
+#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L
+#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L
+#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L
+#define MMEA5_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L
+//MMEA5_IO_WR_COMBINE_FLUSH
+#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0
+#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4
+#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8
+#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc
+#define MMEA5_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10
+#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL
+#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L
+#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L
+#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L
+#define MMEA5_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L
+//MMEA5_IO_GROUP_BURST
+#define MMEA5_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0
+#define MMEA5_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8
+#define MMEA5_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10
+#define MMEA5_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18
+#define MMEA5_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL
+#define MMEA5_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
+#define MMEA5_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
+#define MMEA5_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L
+//MMEA5_IO_RD_PRI_AGE
+#define MMEA5_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA5_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA5_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA5_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA5_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA5_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA5_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA5_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA5_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA5_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA5_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA5_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA5_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA5_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA5_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA5_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA5_IO_WR_PRI_AGE
+#define MMEA5_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA5_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA5_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA5_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA5_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA5_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA5_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA5_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA5_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA5_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA5_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA5_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA5_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA5_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA5_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA5_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA5_IO_RD_PRI_QUEUING
+#define MMEA5_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA5_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA5_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA5_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA5_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA5_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA5_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA5_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA5_IO_WR_PRI_QUEUING
+#define MMEA5_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA5_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA5_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA5_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA5_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA5_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA5_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA5_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA5_IO_RD_PRI_FIXED
+#define MMEA5_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA5_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA5_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA5_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA5_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA5_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA5_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA5_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA5_IO_WR_PRI_FIXED
+#define MMEA5_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA5_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA5_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA5_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA5_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA5_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA5_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA5_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA5_IO_RD_PRI_URGENCY
+#define MMEA5_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA5_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA5_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA5_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA5_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA5_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA5_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA5_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA5_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA5_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA5_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA5_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA5_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA5_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA5_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA5_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA5_IO_WR_PRI_URGENCY
+#define MMEA5_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA5_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA5_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA5_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA5_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA5_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA5_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA5_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA5_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA5_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA5_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA5_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA5_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA5_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA5_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA5_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA5_IO_RD_PRI_URGENCY_MASKING
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L
+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L
+//MMEA5_IO_WR_PRI_URGENCY_MASKING
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L
+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L
+//MMEA5_IO_RD_PRI_QUANT_PRI1
+#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA5_IO_RD_PRI_QUANT_PRI2
+#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA5_IO_RD_PRI_QUANT_PRI3
+#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA5_IO_WR_PRI_QUANT_PRI1
+#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA5_IO_WR_PRI_QUANT_PRI2
+#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA5_IO_WR_PRI_QUANT_PRI3
+#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA5_SDP_ARB_DRAM
+#define MMEA5_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0
+#define MMEA5_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8
+#define MMEA5_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10
+#define MMEA5_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11
+#define MMEA5_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12
+#define MMEA5_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13
+#define MMEA5_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14
+#define MMEA5_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15
+#define MMEA5_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL
+#define MMEA5_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L
+#define MMEA5_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L
+#define MMEA5_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L
+#define MMEA5_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L
+#define MMEA5_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L
+#define MMEA5_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L
+#define MMEA5_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L
+//MMEA5_SDP_ARB_GMI
+#define MMEA5_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0
+#define MMEA5_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8
+#define MMEA5_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10
+#define MMEA5_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11
+#define MMEA5_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12
+#define MMEA5_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13
+#define MMEA5_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14
+#define MMEA5_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15
+#define MMEA5_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16
+#define MMEA5_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL
+#define MMEA5_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L
+#define MMEA5_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L
+#define MMEA5_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L
+#define MMEA5_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L
+#define MMEA5_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L
+#define MMEA5_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L
+#define MMEA5_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L
+#define MMEA5_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L
+//MMEA5_SDP_ARB_FINAL
+#define MMEA5_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0
+#define MMEA5_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5
+#define MMEA5_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa
+#define MMEA5_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf
+#define MMEA5_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11
+#define MMEA5_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12
+#define MMEA5_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13
+#define MMEA5_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14
+#define MMEA5_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15
+#define MMEA5_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16
+#define MMEA5_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17
+#define MMEA5_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18
+#define MMEA5_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19
+#define MMEA5_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a
+#define MMEA5_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b
+#define MMEA5_SDP_ARB_FINAL__DRAM_RD_THROTTLE__SHIFT 0x1c
+#define MMEA5_SDP_ARB_FINAL__DRAM_WR_THROTTLE__SHIFT 0x1d
+#define MMEA5_SDP_ARB_FINAL__GMI_RD_THROTTLE__SHIFT 0x1e
+#define MMEA5_SDP_ARB_FINAL__GMI_WR_THROTTLE__SHIFT 0x1f
+#define MMEA5_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL
+#define MMEA5_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L
+#define MMEA5_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L
+#define MMEA5_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L
+#define MMEA5_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L
+#define MMEA5_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L
+#define MMEA5_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L
+#define MMEA5_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L
+#define MMEA5_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L
+#define MMEA5_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L
+#define MMEA5_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L
+#define MMEA5_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L
+#define MMEA5_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L
+#define MMEA5_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L
+#define MMEA5_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L
+#define MMEA5_SDP_ARB_FINAL__DRAM_RD_THROTTLE_MASK 0x10000000L
+#define MMEA5_SDP_ARB_FINAL__DRAM_WR_THROTTLE_MASK 0x20000000L
+#define MMEA5_SDP_ARB_FINAL__GMI_RD_THROTTLE_MASK 0x40000000L
+#define MMEA5_SDP_ARB_FINAL__GMI_WR_THROTTLE_MASK 0x80000000L
+//MMEA5_SDP_DRAM_PRIORITY
+#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
+#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
+#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
+#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
+#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
+#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
+#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
+#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
+#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
+#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
+#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
+#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
+#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
+#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
+#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
+#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
+//MMEA5_SDP_GMI_PRIORITY
+#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
+#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
+#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
+#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
+#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
+#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
+#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
+#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
+#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
+#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
+#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
+#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
+#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
+#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
+#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
+#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
+//MMEA5_SDP_IO_PRIORITY
+#define MMEA5_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
+#define MMEA5_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
+#define MMEA5_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
+#define MMEA5_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
+#define MMEA5_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
+#define MMEA5_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
+#define MMEA5_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
+#define MMEA5_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
+#define MMEA5_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
+#define MMEA5_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
+#define MMEA5_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
+#define MMEA5_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
+#define MMEA5_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
+#define MMEA5_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
+#define MMEA5_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
+#define MMEA5_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
+//MMEA5_SDP_CREDITS
+#define MMEA5_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0
+#define MMEA5_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8
+#define MMEA5_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10
+#define MMEA5_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL
+#define MMEA5_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L
+#define MMEA5_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L
+//MMEA5_SDP_TAG_RESERVE0
+#define MMEA5_SDP_TAG_RESERVE0__VC0__SHIFT 0x0
+#define MMEA5_SDP_TAG_RESERVE0__VC1__SHIFT 0x8
+#define MMEA5_SDP_TAG_RESERVE0__VC2__SHIFT 0x10
+#define MMEA5_SDP_TAG_RESERVE0__VC3__SHIFT 0x18
+#define MMEA5_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL
+#define MMEA5_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L
+#define MMEA5_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L
+#define MMEA5_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L
+//MMEA5_SDP_TAG_RESERVE1
+#define MMEA5_SDP_TAG_RESERVE1__VC4__SHIFT 0x0
+#define MMEA5_SDP_TAG_RESERVE1__VC5__SHIFT 0x8
+#define MMEA5_SDP_TAG_RESERVE1__VC6__SHIFT 0x10
+#define MMEA5_SDP_TAG_RESERVE1__VC7__SHIFT 0x18
+#define MMEA5_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL
+#define MMEA5_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L
+#define MMEA5_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L
+#define MMEA5_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L
+//MMEA5_SDP_VCC_RESERVE0
+#define MMEA5_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0
+#define MMEA5_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6
+#define MMEA5_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc
+#define MMEA5_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12
+#define MMEA5_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18
+#define MMEA5_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL
+#define MMEA5_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L
+#define MMEA5_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L
+#define MMEA5_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L
+#define MMEA5_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L
+//MMEA5_SDP_VCC_RESERVE1
+#define MMEA5_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0
+#define MMEA5_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6
+#define MMEA5_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc
+#define MMEA5_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f
+#define MMEA5_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL
+#define MMEA5_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L
+#define MMEA5_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L
+#define MMEA5_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L
+//MMEA5_SDP_VCD_RESERVE0
+#define MMEA5_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0
+#define MMEA5_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6
+#define MMEA5_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc
+#define MMEA5_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12
+#define MMEA5_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18
+#define MMEA5_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL
+#define MMEA5_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L
+#define MMEA5_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L
+#define MMEA5_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L
+#define MMEA5_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L
+//MMEA5_SDP_VCD_RESERVE1
+#define MMEA5_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0
+#define MMEA5_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6
+#define MMEA5_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc
+#define MMEA5_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f
+#define MMEA5_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL
+#define MMEA5_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L
+#define MMEA5_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L
+#define MMEA5_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L
+//MMEA5_SDP_REQ_CNTL
+#define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0
+#define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1
+#define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2
+#define MMEA5_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3
+#define MMEA5_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4
+#define MMEA5_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5
+#define MMEA5_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6
+#define MMEA5_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8
+#define MMEA5_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa
+#define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L
+#define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L
+#define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L
+#define MMEA5_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L
+#define MMEA5_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L
+#define MMEA5_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L
+#define MMEA5_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L
+#define MMEA5_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L
+#define MMEA5_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L
+//MMEA5_MISC
+#define MMEA5_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0
+#define MMEA5_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1
+#define MMEA5_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2
+#define MMEA5_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3
+#define MMEA5_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4
+#define MMEA5_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5
+#define MMEA5_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6
+#define MMEA5_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7
+#define MMEA5_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8
+#define MMEA5_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9
+#define MMEA5_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa
+#define MMEA5_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb
+#define MMEA5_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc
+#define MMEA5_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd
+#define MMEA5_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe
+#define MMEA5_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf
+#define MMEA5_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11
+#define MMEA5_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13
+#define MMEA5_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15
+#define MMEA5_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a
+#define MMEA5_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b
+#define MMEA5_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c
+#define MMEA5_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d
+#define MMEA5_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e
+#define MMEA5_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f
+#define MMEA5_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L
+#define MMEA5_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L
+#define MMEA5_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L
+#define MMEA5_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L
+#define MMEA5_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L
+#define MMEA5_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L
+#define MMEA5_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L
+#define MMEA5_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L
+#define MMEA5_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L
+#define MMEA5_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L
+#define MMEA5_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L
+#define MMEA5_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L
+#define MMEA5_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L
+#define MMEA5_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L
+#define MMEA5_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L
+#define MMEA5_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L
+#define MMEA5_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L
+#define MMEA5_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L
+#define MMEA5_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L
+#define MMEA5_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L
+#define MMEA5_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L
+#define MMEA5_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L
+#define MMEA5_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L
+#define MMEA5_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L
+#define MMEA5_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L
+//MMEA5_LATENCY_SAMPLING
+#define MMEA5_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0
+#define MMEA5_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1
+#define MMEA5_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2
+#define MMEA5_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3
+#define MMEA5_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4
+#define MMEA5_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5
+#define MMEA5_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6
+#define MMEA5_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7
+#define MMEA5_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8
+#define MMEA5_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9
+#define MMEA5_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa
+#define MMEA5_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb
+#define MMEA5_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc
+#define MMEA5_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd
+#define MMEA5_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe
+#define MMEA5_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16
+#define MMEA5_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L
+#define MMEA5_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L
+#define MMEA5_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L
+#define MMEA5_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L
+#define MMEA5_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L
+#define MMEA5_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L
+#define MMEA5_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L
+#define MMEA5_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L
+#define MMEA5_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L
+#define MMEA5_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L
+#define MMEA5_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L
+#define MMEA5_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L
+#define MMEA5_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L
+#define MMEA5_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L
+#define MMEA5_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L
+#define MMEA5_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L
+//MMEA5_PERFCOUNTER_LO
+#define MMEA5_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MMEA5_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//MMEA5_PERFCOUNTER_HI
+#define MMEA5_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MMEA5_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MMEA5_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define MMEA5_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//MMEA5_PERFCOUNTER0_CFG
+#define MMEA5_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MMEA5_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMEA5_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MMEA5_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MMEA5_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MMEA5_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMEA5_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMEA5_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMEA5_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define MMEA5_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//MMEA5_PERFCOUNTER1_CFG
+#define MMEA5_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MMEA5_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMEA5_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MMEA5_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MMEA5_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MMEA5_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMEA5_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMEA5_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMEA5_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define MMEA5_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//MMEA5_PERFCOUNTER_RSLT_CNTL
+#define MMEA5_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MMEA5_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MMEA5_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MMEA5_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MMEA5_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MMEA5_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MMEA5_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define MMEA5_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define MMEA5_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define MMEA5_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define MMEA5_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define MMEA5_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+//MMEA5_EDC_CNT
+#define MMEA5_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0
+#define MMEA5_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2
+#define MMEA5_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4
+#define MMEA5_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6
+#define MMEA5_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8
+#define MMEA5_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa
+#define MMEA5_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc
+#define MMEA5_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe
+#define MMEA5_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10
+#define MMEA5_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12
+#define MMEA5_EDC_CNT__IOWR_DATAMEM_SEC_COUNT__SHIFT 0x14
+#define MMEA5_EDC_CNT__IOWR_DATAMEM_DED_COUNT__SHIFT 0x16
+#define MMEA5_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x18
+#define MMEA5_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x1a
+#define MMEA5_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x1c
+#define MMEA5_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1e
+#define MMEA5_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
+#define MMEA5_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
+#define MMEA5_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
+#define MMEA5_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
+#define MMEA5_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
+#define MMEA5_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
+#define MMEA5_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L
+#define MMEA5_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L
+#define MMEA5_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L
+#define MMEA5_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L
+#define MMEA5_EDC_CNT__IOWR_DATAMEM_SEC_COUNT_MASK 0x00300000L
+#define MMEA5_EDC_CNT__IOWR_DATAMEM_DED_COUNT_MASK 0x00C00000L
+#define MMEA5_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x03000000L
+#define MMEA5_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x0C000000L
+#define MMEA5_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x30000000L
+#define MMEA5_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0xC0000000L
+//MMEA5_EDC_CNT2
+#define MMEA5_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0
+#define MMEA5_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2
+#define MMEA5_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4
+#define MMEA5_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6
+#define MMEA5_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8
+#define MMEA5_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa
+#define MMEA5_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc
+#define MMEA5_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe
+#define MMEA5_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10
+#define MMEA5_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12
+#define MMEA5_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14
+#define MMEA5_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16
+#define MMEA5_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT 0x18
+#define MMEA5_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT 0x1a
+#define MMEA5_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT 0x1c
+#define MMEA5_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT 0x1e
+#define MMEA5_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
+#define MMEA5_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
+#define MMEA5_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
+#define MMEA5_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
+#define MMEA5_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
+#define MMEA5_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
+#define MMEA5_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L
+#define MMEA5_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L
+#define MMEA5_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L
+#define MMEA5_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L
+#define MMEA5_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L
+#define MMEA5_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L
+#define MMEA5_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK 0x03000000L
+#define MMEA5_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK 0x0C000000L
+#define MMEA5_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK 0x30000000L
+#define MMEA5_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK 0xC0000000L
+//MMEA5_DSM_CNTL
+#define MMEA5_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define MMEA5_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define MMEA5_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3
+#define MMEA5_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define MMEA5_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define MMEA5_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define MMEA5_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9
+#define MMEA5_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb
+#define MMEA5_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc
+#define MMEA5_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
+#define MMEA5_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf
+#define MMEA5_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11
+#define MMEA5_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12
+#define MMEA5_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14
+#define MMEA5_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15
+#define MMEA5_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17
+#define MMEA5_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define MMEA5_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define MMEA5_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
+#define MMEA5_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define MMEA5_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define MMEA5_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define MMEA5_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L
+#define MMEA5_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
+#define MMEA5_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L
+#define MMEA5_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
+#define MMEA5_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L
+#define MMEA5_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L
+#define MMEA5_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L
+#define MMEA5_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L
+#define MMEA5_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L
+#define MMEA5_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L
+//MMEA5_DSM_CNTLA
+#define MMEA5_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define MMEA5_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define MMEA5_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3
+#define MMEA5_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define MMEA5_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define MMEA5_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define MMEA5_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9
+#define MMEA5_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb
+#define MMEA5_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc
+#define MMEA5_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
+#define MMEA5_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf
+#define MMEA5_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11
+#define MMEA5_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12
+#define MMEA5_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14
+#define MMEA5_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define MMEA5_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define MMEA5_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
+#define MMEA5_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define MMEA5_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define MMEA5_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define MMEA5_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L
+#define MMEA5_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
+#define MMEA5_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L
+#define MMEA5_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
+#define MMEA5_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L
+#define MMEA5_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L
+#define MMEA5_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L
+#define MMEA5_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L
+//MMEA5_DSM_CNTLB
+//MMEA5_DSM_CNTL2
+#define MMEA5_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define MMEA5_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define MMEA5_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define MMEA5_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5
+#define MMEA5_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define MMEA5_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8
+#define MMEA5_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define MMEA5_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb
+#define MMEA5_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define MMEA5_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe
+#define MMEA5_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define MMEA5_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11
+#define MMEA5_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define MMEA5_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14
+#define MMEA5_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15
+#define MMEA5_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17
+#define MMEA5_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
+#define MMEA5_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define MMEA5_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define MMEA5_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define MMEA5_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define MMEA5_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define MMEA5_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define MMEA5_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define MMEA5_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define MMEA5_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define MMEA5_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define MMEA5_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define MMEA5_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define MMEA5_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define MMEA5_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L
+#define MMEA5_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L
+#define MMEA5_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L
+#define MMEA5_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
+//MMEA5_DSM_CNTL2A
+#define MMEA5_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define MMEA5_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define MMEA5_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define MMEA5_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5
+#define MMEA5_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define MMEA5_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8
+#define MMEA5_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define MMEA5_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb
+#define MMEA5_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define MMEA5_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe
+#define MMEA5_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define MMEA5_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11
+#define MMEA5_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define MMEA5_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14
+#define MMEA5_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define MMEA5_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define MMEA5_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define MMEA5_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define MMEA5_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define MMEA5_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define MMEA5_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define MMEA5_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define MMEA5_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define MMEA5_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define MMEA5_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define MMEA5_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define MMEA5_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define MMEA5_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L
+//MMEA5_DSM_CNTL2B
+//MMEA5_CGTT_CLK_CTRL
+#define MMEA5_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define MMEA5_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define MMEA5_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc
+#define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14
+#define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15
+#define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16
+#define MMEA5_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17
+#define MMEA5_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c
+#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d
+#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e
+#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f
+#define MMEA5_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define MMEA5_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define MMEA5_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L
+#define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L
+#define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L
+#define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L
+#define MMEA5_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L
+#define MMEA5_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L
+#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L
+#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L
+#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L
+//MMEA5_EDC_MODE
+#define MMEA5_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10
+#define MMEA5_EDC_MODE__GATE_FUE__SHIFT 0x11
+#define MMEA5_EDC_MODE__DED_MODE__SHIFT 0x14
+#define MMEA5_EDC_MODE__PROP_FED__SHIFT 0x1d
+#define MMEA5_EDC_MODE__BYPASS__SHIFT 0x1f
+#define MMEA5_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L
+#define MMEA5_EDC_MODE__GATE_FUE_MASK 0x00020000L
+#define MMEA5_EDC_MODE__DED_MODE_MASK 0x00300000L
+#define MMEA5_EDC_MODE__PROP_FED_MASK 0x20000000L
+#define MMEA5_EDC_MODE__BYPASS_MASK 0x80000000L
+//MMEA5_ERR_STATUS
+#define MMEA5_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0
+#define MMEA5_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4
+#define MMEA5_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8
+#define MMEA5_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa
+#define MMEA5_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb
+#define MMEA5_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc
+#define MMEA5_ERR_STATUS__FUE_FLAG__SHIFT 0xd
+#define MMEA5_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe
+#define MMEA5_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf
+#define MMEA5_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10
+#define MMEA5_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11
+#define MMEA5_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12
+#define MMEA5_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL
+#define MMEA5_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L
+#define MMEA5_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L
+#define MMEA5_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L
+#define MMEA5_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L
+#define MMEA5_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L
+#define MMEA5_ERR_STATUS__FUE_FLAG_MASK 0x00002000L
+#define MMEA5_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L
+#define MMEA5_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L
+#define MMEA5_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L
+#define MMEA5_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L
+#define MMEA5_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L
+//MMEA5_MISC2
+#define MMEA5_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0
+#define MMEA5_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1
+#define MMEA5_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2
+#define MMEA5_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7
+#define MMEA5_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc
+#define MMEA5_MISC2__RRET_SWAP_MODE__SHIFT 0xd
+#define MMEA5_MISC2__BLOCK_REQUESTS__SHIFT 0xe
+#define MMEA5_MISC2__REQUESTS_BLOCKED__SHIFT 0xf
+#define MMEA5_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L
+#define MMEA5_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L
+#define MMEA5_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL
+#define MMEA5_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L
+#define MMEA5_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L
+#define MMEA5_MISC2__RRET_SWAP_MODE_MASK 0x00002000L
+#define MMEA5_MISC2__BLOCK_REQUESTS_MASK 0x00004000L
+#define MMEA5_MISC2__REQUESTS_BLOCKED_MASK 0x00008000L
+//MMEA5_ADDRDEC_SELECT
+#define MMEA5_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0
+#define MMEA5_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5
+#define MMEA5_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa
+#define MMEA5_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf
+#define MMEA5_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL
+#define MMEA5_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L
+#define MMEA5_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L
+#define MMEA5_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L
+//MMEA5_EDC_CNT3
+#define MMEA5_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0
+#define MMEA5_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2
+#define MMEA5_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4
+#define MMEA5_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6
+#define MMEA5_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0x8
+#define MMEA5_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xa
+#define MMEA5_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L
+#define MMEA5_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL
+#define MMEA5_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L
+#define MMEA5_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
+#define MMEA5_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000300L
+#define MMEA5_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00000C00L
+//MMEA5_MISC_AON
+#define MMEA5_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0
+#define MMEA5_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2
+#define MMEA5_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L
+#define MMEA5_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L
+
+
+// addressBlock: mmhub_l1tlb_vml1dec
+//MC_VM_MX_L1_TLB0_STATUS
+#define MC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
+#define MC_VM_MX_L1_TLB0_STATUS__BUSY_MASK 0x00000001L
+#define MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
+//MC_VM_MX_L1_TLB1_STATUS
+#define MC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
+#define MC_VM_MX_L1_TLB1_STATUS__BUSY_MASK 0x00000001L
+#define MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
+//MC_VM_MX_L1_TLB2_STATUS
+#define MC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
+#define MC_VM_MX_L1_TLB2_STATUS__BUSY_MASK 0x00000001L
+#define MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
+//MC_VM_MX_L1_TLB3_STATUS
+#define MC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
+#define MC_VM_MX_L1_TLB3_STATUS__BUSY_MASK 0x00000001L
+#define MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
+//MC_VM_MX_L1_TLB4_STATUS
+#define MC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
+#define MC_VM_MX_L1_TLB4_STATUS__BUSY_MASK 0x00000001L
+#define MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
+//MC_VM_MX_L1_TLB5_STATUS
+#define MC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
+#define MC_VM_MX_L1_TLB5_STATUS__BUSY_MASK 0x00000001L
+#define MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
+//MC_VM_MX_L1_TLB6_STATUS
+#define MC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
+#define MC_VM_MX_L1_TLB6_STATUS__BUSY_MASK 0x00000001L
+#define MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
+//MC_VM_MX_L1_TLB7_STATUS
+#define MC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
+#define MC_VM_MX_L1_TLB7_STATUS__BUSY_MASK 0x00000001L
+#define MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
+
+
+// addressBlock: mmhub_l1tlb_vml1pldec
+//MC_VM_MX_L1_PERFCOUNTER0_CFG
+#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_MX_L1_PERFCOUNTER1_CFG
+#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_MX_L1_PERFCOUNTER2_CFG
+#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_MX_L1_PERFCOUNTER3_CFG
+#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL
+#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+
+
+// addressBlock: mmhub_l1tlb_vml1prdec
+//MC_VM_MX_L1_PERFCOUNTER_LO
+#define MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//MC_VM_MX_L1_PERFCOUNTER_HI
+#define MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+
+
+// addressBlock: mmhub_pctldec0
+//PCTL0_CTRL
+#define PCTL0_CTRL__PG_ENABLE__SHIFT 0x0
+#define PCTL0_CTRL__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1
+#define PCTL0_CTRL__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT 0xb
+#define PCTL0_CTRL__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x10
+#define PCTL0_CTRL__OVR_EA0_SDP_PARTACK__SHIFT 0x11
+#define PCTL0_CTRL__OVR_EA1_SDP_PARTACK__SHIFT 0x12
+#define PCTL0_CTRL__OVR_EA2_SDP_PARTACK__SHIFT 0x13
+#define PCTL0_CTRL__OVR_EA3_SDP_PARTACK__SHIFT 0x14
+#define PCTL0_CTRL__OVR_EA4_SDP_PARTACK__SHIFT 0x15
+#define PCTL0_CTRL__OVR_EA5_SDP_PARTACK__SHIFT 0x16
+#define PCTL0_CTRL__OVR_EA0_SDP_FULLACK__SHIFT 0x17
+#define PCTL0_CTRL__OVR_EA1_SDP_FULLACK__SHIFT 0x18
+#define PCTL0_CTRL__OVR_EA2_SDP_FULLACK__SHIFT 0x19
+#define PCTL0_CTRL__OVR_EA3_SDP_FULLACK__SHIFT 0x1a
+#define PCTL0_CTRL__OVR_EA4_SDP_FULLACK__SHIFT 0x1b
+#define PCTL0_CTRL__OVR_EA5_SDP_FULLACK__SHIFT 0x1c
+#define PCTL0_CTRL__PG_ENABLE_MASK 0x00000001L
+#define PCTL0_CTRL__ALLOW_DEEP_SLEEP_MODE_MASK 0x0000000EL
+#define PCTL0_CTRL__STCTRL_DAGB_IDLE_THRESHOLD_MASK 0x0000F800L
+#define PCTL0_CTRL__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x00010000L
+#define PCTL0_CTRL__OVR_EA0_SDP_PARTACK_MASK 0x00020000L
+#define PCTL0_CTRL__OVR_EA1_SDP_PARTACK_MASK 0x00040000L
+#define PCTL0_CTRL__OVR_EA2_SDP_PARTACK_MASK 0x00080000L
+#define PCTL0_CTRL__OVR_EA3_SDP_PARTACK_MASK 0x00100000L
+#define PCTL0_CTRL__OVR_EA4_SDP_PARTACK_MASK 0x00200000L
+#define PCTL0_CTRL__OVR_EA5_SDP_PARTACK_MASK 0x00400000L
+#define PCTL0_CTRL__OVR_EA0_SDP_FULLACK_MASK 0x00800000L
+#define PCTL0_CTRL__OVR_EA1_SDP_FULLACK_MASK 0x01000000L
+#define PCTL0_CTRL__OVR_EA2_SDP_FULLACK_MASK 0x02000000L
+#define PCTL0_CTRL__OVR_EA3_SDP_FULLACK_MASK 0x04000000L
+#define PCTL0_CTRL__OVR_EA4_SDP_FULLACK_MASK 0x08000000L
+#define PCTL0_CTRL__OVR_EA5_SDP_FULLACK_MASK 0x10000000L
+//PCTL0_MMHUB_DEEPSLEEP_IB
+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS0__SHIFT 0x0
+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS1__SHIFT 0x1
+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS2__SHIFT 0x2
+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS3__SHIFT 0x3
+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS4__SHIFT 0x4
+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS5__SHIFT 0x5
+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS6__SHIFT 0x6
+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS7__SHIFT 0x7
+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS8__SHIFT 0x8
+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS9__SHIFT 0x9
+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS10__SHIFT 0xa
+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS11__SHIFT 0xb
+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS12__SHIFT 0xc
+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS13__SHIFT 0xd
+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS14__SHIFT 0xe
+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS15__SHIFT 0xf
+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS16__SHIFT 0x10
+#define PCTL0_MMHUB_DEEPSLEEP_IB__SETCLEAR__SHIFT 0x1f
+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS0_MASK 0x00000001L
+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS1_MASK 0x00000002L
+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS2_MASK 0x00000004L
+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS3_MASK 0x00000008L
+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS4_MASK 0x00000010L
+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS5_MASK 0x00000020L
+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS6_MASK 0x00000040L
+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS7_MASK 0x00000080L
+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS8_MASK 0x00000100L
+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS9_MASK 0x00000200L
+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS10_MASK 0x00000400L
+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS11_MASK 0x00000800L
+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS12_MASK 0x00001000L
+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS13_MASK 0x00002000L
+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS14_MASK 0x00004000L
+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS15_MASK 0x00008000L
+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS16_MASK 0x00010000L
+#define PCTL0_MMHUB_DEEPSLEEP_IB__SETCLEAR_MASK 0x80000000L
+//PCTL0_MMHUB_DEEPSLEEP_OVERRIDE
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT 0x0
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT 0x1
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT 0x2
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT 0x3
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT 0x4
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT 0x5
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT 0x6
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT 0x7
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT 0x8
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT 0x9
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT 0xa
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT 0xb
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT 0xc
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT 0xd
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT 0xe
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT 0xf
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT 0x10
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB__SHIFT 0x11
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK 0x00000001L
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK 0x00000002L
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK 0x00000004L
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK 0x00000008L
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK 0x00000010L
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK 0x00000020L
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK 0x00000040L
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK 0x00000080L
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK 0x00000100L
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK 0x00000200L
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK 0x00000400L
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK 0x00000800L
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK 0x00001000L
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK 0x00002000L
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK 0x00004000L
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK 0x00008000L
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK 0x00010000L
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB_MASK 0x00020000L
+//PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0__SHIFT 0x0
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1__SHIFT 0x1
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2__SHIFT 0x2
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3__SHIFT 0x3
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4__SHIFT 0x4
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5__SHIFT 0x5
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6__SHIFT 0x6
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7__SHIFT 0x7
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8__SHIFT 0x8
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9__SHIFT 0x9
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10__SHIFT 0xa
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11__SHIFT 0xb
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12__SHIFT 0xc
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13__SHIFT 0xd
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14__SHIFT 0xe
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15__SHIFT 0xf
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16__SHIFT 0x10
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0_MASK 0x00000001L
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1_MASK 0x00000002L
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2_MASK 0x00000004L
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3_MASK 0x00000008L
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4_MASK 0x00000010L
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5_MASK 0x00000020L
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6_MASK 0x00000040L
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7_MASK 0x00000080L
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8_MASK 0x00000100L
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9_MASK 0x00000200L
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10_MASK 0x00000400L
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11_MASK 0x00000800L
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12_MASK 0x00001000L
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13_MASK 0x00002000L
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14_MASK 0x00004000L
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15_MASK 0x00008000L
+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16_MASK 0x00010000L
+//PCTL0_PG_IGNORE_DEEPSLEEP
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS0__SHIFT 0x0
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS1__SHIFT 0x1
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS2__SHIFT 0x2
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS3__SHIFT 0x3
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS4__SHIFT 0x4
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS5__SHIFT 0x5
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS6__SHIFT 0x6
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS7__SHIFT 0x7
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS8__SHIFT 0x8
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS9__SHIFT 0x9
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS10__SHIFT 0xa
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS11__SHIFT 0xb
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS12__SHIFT 0xc
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS13__SHIFT 0xd
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS14__SHIFT 0xe
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS15__SHIFT 0xf
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS16__SHIFT 0x10
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS_ATHUB__SHIFT 0x11
+#define PCTL0_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT 0x12
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS0_MASK 0x00000001L
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS1_MASK 0x00000002L
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS2_MASK 0x00000004L
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS3_MASK 0x00000008L
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS4_MASK 0x00000010L
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS5_MASK 0x00000020L
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS6_MASK 0x00000040L
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS7_MASK 0x00000080L
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS8_MASK 0x00000100L
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS9_MASK 0x00000200L
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS10_MASK 0x00000400L
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS11_MASK 0x00000800L
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS12_MASK 0x00001000L
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS13_MASK 0x00002000L
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS14_MASK 0x00004000L
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS15_MASK 0x00008000L
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS16_MASK 0x00010000L
+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS_ATHUB_MASK 0x00020000L
+#define PCTL0_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK 0x00040000L
+//PCTL0_PG_IGNORE_DEEPSLEEP_IB
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS0__SHIFT 0x0
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS1__SHIFT 0x1
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS2__SHIFT 0x2
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS3__SHIFT 0x3
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS4__SHIFT 0x4
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS5__SHIFT 0x5
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS6__SHIFT 0x6
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS7__SHIFT 0x7
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS8__SHIFT 0x8
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS9__SHIFT 0x9
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS10__SHIFT 0xa
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS11__SHIFT 0xb
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS12__SHIFT 0xc
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS13__SHIFT 0xd
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS14__SHIFT 0xe
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS15__SHIFT 0xf
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS16__SHIFT 0x10
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__ALLIPS__SHIFT 0x11
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS0_MASK 0x00000001L
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS1_MASK 0x00000002L
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS2_MASK 0x00000004L
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS3_MASK 0x00000008L
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS4_MASK 0x00000010L
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS5_MASK 0x00000020L
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS6_MASK 0x00000040L
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS7_MASK 0x00000080L
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS8_MASK 0x00000100L
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS9_MASK 0x00000200L
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS10_MASK 0x00000400L
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS11_MASK 0x00000800L
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS12_MASK 0x00001000L
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS13_MASK 0x00002000L
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS14_MASK 0x00004000L
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS15_MASK 0x00008000L
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS16_MASK 0x00010000L
+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__ALLIPS_MASK 0x00020000L
+//PCTL0_SLICE0_CFG_DAGB_BUSY
+#define PCTL0_SLICE0_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0
+#define PCTL0_SLICE0_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL
+//PCTL0_SLICE0_CFG_DS_ALLOW
+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS0__SHIFT 0x0
+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS1__SHIFT 0x1
+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS2__SHIFT 0x2
+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS3__SHIFT 0x3
+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS4__SHIFT 0x4
+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS5__SHIFT 0x5
+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS6__SHIFT 0x6
+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS7__SHIFT 0x7
+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS8__SHIFT 0x8
+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS9__SHIFT 0x9
+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS10__SHIFT 0xa
+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS11__SHIFT 0xb
+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS12__SHIFT 0xc
+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS13__SHIFT 0xd
+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS14__SHIFT 0xe
+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS15__SHIFT 0xf
+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS16__SHIFT 0x10
+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS0_MASK 0x00000001L
+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS1_MASK 0x00000002L
+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS2_MASK 0x00000004L
+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS3_MASK 0x00000008L
+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS4_MASK 0x00000010L
+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS5_MASK 0x00000020L
+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS6_MASK 0x00000040L
+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS7_MASK 0x00000080L
+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS8_MASK 0x00000100L
+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS9_MASK 0x00000200L
+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS10_MASK 0x00000400L
+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS11_MASK 0x00000800L
+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS12_MASK 0x00001000L
+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS13_MASK 0x00002000L
+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS14_MASK 0x00004000L
+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS15_MASK 0x00008000L
+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS16_MASK 0x00010000L
+//PCTL0_SLICE0_CFG_DS_ALLOW_IB
+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0
+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1
+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2
+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3
+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4
+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5
+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6
+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7
+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8
+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9
+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa
+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb
+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc
+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd
+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe
+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf
+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10
+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L
+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L
+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L
+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L
+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L
+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L
+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L
+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L
+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L
+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L
+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L
+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L
+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L
+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L
+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L
+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L
+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L
+//PCTL0_SLICE1_CFG_DAGB_BUSY
+#define PCTL0_SLICE1_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0
+#define PCTL0_SLICE1_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL
+//PCTL0_SLICE1_CFG_DS_ALLOW
+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS0__SHIFT 0x0
+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS1__SHIFT 0x1
+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS2__SHIFT 0x2
+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS3__SHIFT 0x3
+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS4__SHIFT 0x4
+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS5__SHIFT 0x5
+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS6__SHIFT 0x6
+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS7__SHIFT 0x7
+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS8__SHIFT 0x8
+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS9__SHIFT 0x9
+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS10__SHIFT 0xa
+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS11__SHIFT 0xb
+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS12__SHIFT 0xc
+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS13__SHIFT 0xd
+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS14__SHIFT 0xe
+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS15__SHIFT 0xf
+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS16__SHIFT 0x10
+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS0_MASK 0x00000001L
+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS1_MASK 0x00000002L
+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS2_MASK 0x00000004L
+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS3_MASK 0x00000008L
+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS4_MASK 0x00000010L
+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS5_MASK 0x00000020L
+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS6_MASK 0x00000040L
+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS7_MASK 0x00000080L
+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS8_MASK 0x00000100L
+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS9_MASK 0x00000200L
+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS10_MASK 0x00000400L
+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS11_MASK 0x00000800L
+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS12_MASK 0x00001000L
+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS13_MASK 0x00002000L
+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS14_MASK 0x00004000L
+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS15_MASK 0x00008000L
+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS16_MASK 0x00010000L
+//PCTL0_SLICE1_CFG_DS_ALLOW_IB
+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0
+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1
+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2
+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3
+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4
+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5
+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6
+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7
+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8
+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9
+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa
+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb
+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc
+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd
+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe
+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf
+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10
+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L
+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L
+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L
+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L
+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L
+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L
+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L
+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L
+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L
+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L
+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L
+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L
+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L
+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L
+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L
+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L
+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L
+//PCTL0_SLICE2_CFG_DAGB_BUSY
+#define PCTL0_SLICE2_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0
+#define PCTL0_SLICE2_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL
+//PCTL0_SLICE2_CFG_DS_ALLOW
+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS0__SHIFT 0x0
+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS1__SHIFT 0x1
+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS2__SHIFT 0x2
+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS3__SHIFT 0x3
+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS4__SHIFT 0x4
+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS5__SHIFT 0x5
+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS6__SHIFT 0x6
+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS7__SHIFT 0x7
+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS8__SHIFT 0x8
+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS9__SHIFT 0x9
+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS10__SHIFT 0xa
+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS11__SHIFT 0xb
+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS12__SHIFT 0xc
+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS13__SHIFT 0xd
+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS14__SHIFT 0xe
+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS15__SHIFT 0xf
+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS16__SHIFT 0x10
+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS0_MASK 0x00000001L
+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS1_MASK 0x00000002L
+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS2_MASK 0x00000004L
+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS3_MASK 0x00000008L
+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS4_MASK 0x00000010L
+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS5_MASK 0x00000020L
+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS6_MASK 0x00000040L
+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS7_MASK 0x00000080L
+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS8_MASK 0x00000100L
+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS9_MASK 0x00000200L
+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS10_MASK 0x00000400L
+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS11_MASK 0x00000800L
+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS12_MASK 0x00001000L
+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS13_MASK 0x00002000L
+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS14_MASK 0x00004000L
+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS15_MASK 0x00008000L
+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS16_MASK 0x00010000L
+//PCTL0_SLICE2_CFG_DS_ALLOW_IB
+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0
+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1
+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2
+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3
+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4
+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5
+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6
+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7
+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8
+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9
+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa
+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb
+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc
+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd
+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe
+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf
+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10
+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L
+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L
+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L
+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L
+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L
+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L
+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L
+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L
+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L
+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L
+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L
+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L
+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L
+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L
+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L
+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L
+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L
+//PCTL0_SLICE3_CFG_DAGB_BUSY
+#define PCTL0_SLICE3_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0
+#define PCTL0_SLICE3_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL
+//PCTL0_SLICE3_CFG_DS_ALLOW
+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS0__SHIFT 0x0
+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS1__SHIFT 0x1
+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS2__SHIFT 0x2
+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS3__SHIFT 0x3
+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS4__SHIFT 0x4
+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS5__SHIFT 0x5
+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS6__SHIFT 0x6
+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS7__SHIFT 0x7
+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS8__SHIFT 0x8
+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS9__SHIFT 0x9
+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS10__SHIFT 0xa
+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS11__SHIFT 0xb
+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS12__SHIFT 0xc
+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS13__SHIFT 0xd
+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS14__SHIFT 0xe
+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS15__SHIFT 0xf
+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS16__SHIFT 0x10
+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS0_MASK 0x00000001L
+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS1_MASK 0x00000002L
+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS2_MASK 0x00000004L
+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS3_MASK 0x00000008L
+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS4_MASK 0x00000010L
+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS5_MASK 0x00000020L
+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS6_MASK 0x00000040L
+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS7_MASK 0x00000080L
+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS8_MASK 0x00000100L
+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS9_MASK 0x00000200L
+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS10_MASK 0x00000400L
+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS11_MASK 0x00000800L
+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS12_MASK 0x00001000L
+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS13_MASK 0x00002000L
+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS14_MASK 0x00004000L
+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS15_MASK 0x00008000L
+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS16_MASK 0x00010000L
+//PCTL0_SLICE3_CFG_DS_ALLOW_IB
+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0
+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1
+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2
+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3
+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4
+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5
+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6
+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7
+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8
+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9
+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa
+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb
+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc
+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd
+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe
+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf
+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10
+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L
+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L
+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L
+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L
+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L
+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L
+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L
+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L
+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L
+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L
+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L
+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L
+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L
+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L
+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L
+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L
+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L
+//PCTL0_SLICE4_CFG_DAGB_BUSY
+#define PCTL0_SLICE4_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0
+#define PCTL0_SLICE4_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL
+//PCTL0_SLICE4_CFG_DS_ALLOW
+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS0__SHIFT 0x0
+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS1__SHIFT 0x1
+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS2__SHIFT 0x2
+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS3__SHIFT 0x3
+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS4__SHIFT 0x4
+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS5__SHIFT 0x5
+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS6__SHIFT 0x6
+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS7__SHIFT 0x7
+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS8__SHIFT 0x8
+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS9__SHIFT 0x9
+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS10__SHIFT 0xa
+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS11__SHIFT 0xb
+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS12__SHIFT 0xc
+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS13__SHIFT 0xd
+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS14__SHIFT 0xe
+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS15__SHIFT 0xf
+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS16__SHIFT 0x10
+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS0_MASK 0x00000001L
+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS1_MASK 0x00000002L
+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS2_MASK 0x00000004L
+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS3_MASK 0x00000008L
+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS4_MASK 0x00000010L
+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS5_MASK 0x00000020L
+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS6_MASK 0x00000040L
+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS7_MASK 0x00000080L
+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS8_MASK 0x00000100L
+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS9_MASK 0x00000200L
+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS10_MASK 0x00000400L
+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS11_MASK 0x00000800L
+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS12_MASK 0x00001000L
+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS13_MASK 0x00002000L
+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS14_MASK 0x00004000L
+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS15_MASK 0x00008000L
+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS16_MASK 0x00010000L
+//PCTL0_SLICE4_CFG_DS_ALLOW_IB
+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0
+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1
+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2
+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3
+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4
+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5
+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6
+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7
+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8
+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9
+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa
+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb
+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc
+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd
+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe
+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf
+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10
+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L
+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L
+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L
+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L
+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L
+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L
+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L
+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L
+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L
+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L
+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L
+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L
+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L
+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L
+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L
+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L
+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L
+//PCTL0_SLICE5_CFG_DAGB_BUSY
+#define PCTL0_SLICE5_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0
+#define PCTL0_SLICE5_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL
+//PCTL0_SLICE5_CFG_DS_ALLOW
+#define PCTL0_SLICE5_CFG_DS_ALLOW__DS0__SHIFT 0x0
+#define PCTL0_SLICE5_CFG_DS_ALLOW__DS1__SHIFT 0x1
+#define PCTL0_SLICE5_CFG_DS_ALLOW__DS2__SHIFT 0x2
+#define PCTL0_SLICE5_CFG_DS_ALLOW__DS3__SHIFT 0x3
+#define PCTL0_SLICE5_CFG_DS_ALLOW__DS4__SHIFT 0x4
+#define PCTL0_SLICE5_CFG_DS_ALLOW__DS5__SHIFT 0x5
+#define PCTL0_SLICE5_CFG_DS_ALLOW__DS6__SHIFT 0x6
+#define PCTL0_SLICE5_CFG_DS_ALLOW__DS7__SHIFT 0x7
+#define PCTL0_SLICE5_CFG_DS_ALLOW__DS8__SHIFT 0x8
+#define PCTL0_SLICE5_CFG_DS_ALLOW__DS9__SHIFT 0x9
+#define PCTL0_SLICE5_CFG_DS_ALLOW__DS10__SHIFT 0xa
+#define PCTL0_SLICE5_CFG_DS_ALLOW__DS11__SHIFT 0xb
+#define PCTL0_SLICE5_CFG_DS_ALLOW__DS12__SHIFT 0xc
+#define PCTL0_SLICE5_CFG_DS_ALLOW__DS13__SHIFT 0xd
+#define PCTL0_SLICE5_CFG_DS_ALLOW__DS14__SHIFT 0xe
+#define PCTL0_SLICE5_CFG_DS_ALLOW__DS15__SHIFT 0xf
+#define PCTL0_SLICE5_CFG_DS_ALLOW__DS16__SHIFT 0x10
+#define PCTL0_SLICE5_CFG_DS_ALLOW__DS0_MASK 0x00000001L
+#define PCTL0_SLICE5_CFG_DS_ALLOW__DS1_MASK 0x00000002L
+#define PCTL0_SLICE5_CFG_DS_ALLOW__DS2_MASK 0x00000004L
+#define PCTL0_SLICE5_CFG_DS_ALLOW__DS3_MASK 0x00000008L
+#define PCTL0_SLICE5_CFG_DS_ALLOW__DS4_MASK 0x00000010L
+#define PCTL0_SLICE5_CFG_DS_ALLOW__DS5_MASK 0x00000020L
+#define PCTL0_SLICE5_CFG_DS_ALLOW__DS6_MASK 0x00000040L
+#define PCTL0_SLICE5_CFG_DS_ALLOW__DS7_MASK 0x00000080L
+#define PCTL0_SLICE5_CFG_DS_ALLOW__DS8_MASK 0x00000100L
+#define PCTL0_SLICE5_CFG_DS_ALLOW__DS9_MASK 0x00000200L
+#define PCTL0_SLICE5_CFG_DS_ALLOW__DS10_MASK 0x00000400L
+#define PCTL0_SLICE5_CFG_DS_ALLOW__DS11_MASK 0x00000800L
+#define PCTL0_SLICE5_CFG_DS_ALLOW__DS12_MASK 0x00001000L
+#define PCTL0_SLICE5_CFG_DS_ALLOW__DS13_MASK 0x00002000L
+#define PCTL0_SLICE5_CFG_DS_ALLOW__DS14_MASK 0x00004000L
+#define PCTL0_SLICE5_CFG_DS_ALLOW__DS15_MASK 0x00008000L
+#define PCTL0_SLICE5_CFG_DS_ALLOW__DS16_MASK 0x00010000L
+//PCTL0_SLICE5_CFG_DS_ALLOW_IB
+#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0
+#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1
+#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2
+#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3
+#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4
+#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5
+#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6
+#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7
+#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8
+#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9
+#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa
+#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb
+#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc
+#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd
+#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe
+#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf
+#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10
+#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L
+#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L
+#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L
+#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L
+#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L
+#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L
+#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L
+#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L
+#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L
+#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L
+#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L
+#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L
+#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L
+#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L
+#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L
+#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L
+#define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L
+//PCTL0_UTCL2_MISC
+#define PCTL0_UTCL2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xb
+#define PCTL0_UTCL2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xc
+#define PCTL0_UTCL2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xf
+#define PCTL0_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10
+#define PCTL0_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11
+#define PCTL0_UTCL2_MISC__RD_TIMER_ENABLE__SHIFT 0x12
+#define PCTL0_UTCL2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000800L
+#define PCTL0_UTCL2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00007000L
+#define PCTL0_UTCL2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00008000L
+#define PCTL0_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00010000L
+#define PCTL0_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L
+#define PCTL0_UTCL2_MISC__RD_TIMER_ENABLE_MASK 0x00040000L
+//PCTL0_SLICE0_MISC
+#define PCTL0_SLICE0_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa
+#define PCTL0_SLICE0_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb
+#define PCTL0_SLICE0_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe
+#define PCTL0_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf
+#define PCTL0_SLICE0_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10
+#define PCTL0_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11
+#define PCTL0_SLICE0_MISC__RD_TIMER_ENABLE__SHIFT 0x12
+#define PCTL0_SLICE0_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L
+#define PCTL0_SLICE0_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L
+#define PCTL0_SLICE0_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L
+#define PCTL0_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L
+#define PCTL0_SLICE0_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L
+#define PCTL0_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L
+#define PCTL0_SLICE0_MISC__RD_TIMER_ENABLE_MASK 0x00040000L
+//PCTL0_SLICE1_MISC
+#define PCTL0_SLICE1_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa
+#define PCTL0_SLICE1_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb
+#define PCTL0_SLICE1_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe
+#define PCTL0_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf
+#define PCTL0_SLICE1_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10
+#define PCTL0_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11
+#define PCTL0_SLICE1_MISC__RD_TIMER_ENABLE__SHIFT 0x12
+#define PCTL0_SLICE1_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L
+#define PCTL0_SLICE1_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L
+#define PCTL0_SLICE1_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L
+#define PCTL0_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L
+#define PCTL0_SLICE1_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L
+#define PCTL0_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L
+#define PCTL0_SLICE1_MISC__RD_TIMER_ENABLE_MASK 0x00040000L
+//PCTL0_SLICE2_MISC
+#define PCTL0_SLICE2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa
+#define PCTL0_SLICE2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb
+#define PCTL0_SLICE2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe
+#define PCTL0_SLICE2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf
+#define PCTL0_SLICE2_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10
+#define PCTL0_SLICE2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11
+#define PCTL0_SLICE2_MISC__RD_TIMER_ENABLE__SHIFT 0x12
+#define PCTL0_SLICE2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L
+#define PCTL0_SLICE2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L
+#define PCTL0_SLICE2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L
+#define PCTL0_SLICE2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L
+#define PCTL0_SLICE2_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L
+#define PCTL0_SLICE2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L
+#define PCTL0_SLICE2_MISC__RD_TIMER_ENABLE_MASK 0x00040000L
+//PCTL0_SLICE3_MISC
+#define PCTL0_SLICE3_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa
+#define PCTL0_SLICE3_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb
+#define PCTL0_SLICE3_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe
+#define PCTL0_SLICE3_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf
+#define PCTL0_SLICE3_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10
+#define PCTL0_SLICE3_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11
+#define PCTL0_SLICE3_MISC__RD_TIMER_ENABLE__SHIFT 0x12
+#define PCTL0_SLICE3_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L
+#define PCTL0_SLICE3_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L
+#define PCTL0_SLICE3_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L
+#define PCTL0_SLICE3_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L
+#define PCTL0_SLICE3_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L
+#define PCTL0_SLICE3_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L
+#define PCTL0_SLICE3_MISC__RD_TIMER_ENABLE_MASK 0x00040000L
+//PCTL0_SLICE4_MISC
+#define PCTL0_SLICE4_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa
+#define PCTL0_SLICE4_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb
+#define PCTL0_SLICE4_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe
+#define PCTL0_SLICE4_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf
+#define PCTL0_SLICE4_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10
+#define PCTL0_SLICE4_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11
+#define PCTL0_SLICE4_MISC__RD_TIMER_ENABLE__SHIFT 0x12
+#define PCTL0_SLICE4_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L
+#define PCTL0_SLICE4_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L
+#define PCTL0_SLICE4_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L
+#define PCTL0_SLICE4_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L
+#define PCTL0_SLICE4_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L
+#define PCTL0_SLICE4_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L
+#define PCTL0_SLICE4_MISC__RD_TIMER_ENABLE_MASK 0x00040000L
+//PCTL0_SLICE5_MISC
+#define PCTL0_SLICE5_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa
+#define PCTL0_SLICE5_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb
+#define PCTL0_SLICE5_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe
+#define PCTL0_SLICE5_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf
+#define PCTL0_SLICE5_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10
+#define PCTL0_SLICE5_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11
+#define PCTL0_SLICE5_MISC__RD_TIMER_ENABLE__SHIFT 0x12
+#define PCTL0_SLICE5_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L
+#define PCTL0_SLICE5_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L
+#define PCTL0_SLICE5_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L
+#define PCTL0_SLICE5_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L
+#define PCTL0_SLICE5_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L
+#define PCTL0_SLICE5_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L
+#define PCTL0_SLICE5_MISC__RD_TIMER_ENABLE_MASK 0x00040000L
+
+
+// addressBlock: mmhub_utcl2_atcl2dec
+//ATC_L2_CNTL
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7
+#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT 0x8
+#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT 0xb
+#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0xe
+#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0xf
+#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x10
+#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0x13
+#define ATC_L2_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0x14
+#define ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE__SHIFT 0x16
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L
+#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK 0x00000300L
+#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK 0x00001800L
+#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00004000L
+#define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00008000L
+#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00070000L
+#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00080000L
+#define ATC_L2_CNTL__FRAG_APT_INTXN_MODE_MASK 0x00300000L
+#define ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE_MASK 0x0FC00000L
+//ATC_L2_CNTL2
+#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0
+#define ATC_L2_CNTL2__NUM_BANKS_LOG2__SHIFT 0x6
+#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x9
+#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xb
+#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0xc
+#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xf
+#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x12
+#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL
+#define ATC_L2_CNTL2__NUM_BANKS_LOG2_MASK 0x000001C0L
+#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x00000600L
+#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000800L
+#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00007000L
+#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00038000L
+#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00FC0000L
+//ATC_L2_CACHE_DATA0
+#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0
+#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1
+#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2
+#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x17
+#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L
+#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L
+#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x007FFFFCL
+#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x07800000L
+//ATC_L2_CACHE_DATA1
+#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0
+#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL
+//ATC_L2_CACHE_DATA2
+#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0
+#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL
+//ATC_L2_CACHE_DATA3
+#define ATC_L2_CACHE_DATA3__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0
+#define ATC_L2_CACHE_DATA3__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL
+//ATC_L2_CNTL3
+#define ATC_L2_CNTL3__L2_SMALLK_FRAGMENT_SIZE__SHIFT 0x0
+#define ATC_L2_CNTL3__L2_MIDK_FRAGMENT_SIZE__SHIFT 0x6
+#define ATC_L2_CNTL3__L2_BIGK_FRAGMENT_SIZE__SHIFT 0xc
+#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x12
+#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x15
+#define ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x1b
+#define ATC_L2_CNTL3__REPEATER_FGCG_OFF__SHIFT 0x1e
+#define ATC_L2_CNTL3__L2_SMALLK_FRAGMENT_SIZE_MASK 0x0000003FL
+#define ATC_L2_CNTL3__L2_MIDK_FRAGMENT_SIZE_MASK 0x00000FC0L
+#define ATC_L2_CNTL3__L2_BIGK_FRAGMENT_SIZE_MASK 0x0003F000L
+#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x001C0000L
+#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x07E00000L
+#define ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x38000000L
+#define ATC_L2_CNTL3__REPEATER_FGCG_OFF_MASK 0x40000000L
+//ATC_L2_STATUS
+#define ATC_L2_STATUS__BUSY__SHIFT 0x0
+#define ATC_L2_STATUS__BUSY_MASK 0x00000001L
+//ATC_L2_STATUS2
+#define ATC_L2_STATUS2__UCE_MEM_ADDR__SHIFT 0x0
+#define ATC_L2_STATUS2__UCE_MEM_INST__SHIFT 0xc
+#define ATC_L2_STATUS2__UCE_SRT_CACHE__SHIFT 0x12
+#define ATC_L2_STATUS2__UCE__SHIFT 0x13
+#define ATC_L2_STATUS2__UCE_MEM_ADDR_MASK 0x00000FFFL
+#define ATC_L2_STATUS2__UCE_MEM_INST_MASK 0x0003F000L
+#define ATC_L2_STATUS2__UCE_SRT_CACHE_MASK 0x00040000L
+#define ATC_L2_STATUS2__UCE_MASK 0x00080000L
+//ATC_L2_MISC_CG
+#define ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6
+#define ATC_L2_MISC_CG__ENABLE__SHIFT 0x12
+#define ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L
+#define ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L
+#define ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L
+//ATC_L2_MEM_POWER_LS
+#define ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
+#define ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
+#define ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL
+#define ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L
+//ATC_L2_CGTT_CLK_CTRL
+#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
+#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
+#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
+#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
+#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
+#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
+//ATC_L2_CACHE_4K_DSM_INDEX
+#define ATC_L2_CACHE_4K_DSM_INDEX__INDEX__SHIFT 0x0
+#define ATC_L2_CACHE_4K_DSM_INDEX__INDEX_MASK 0x000000FFL
+//ATC_L2_CACHE_32K_DSM_INDEX
+#define ATC_L2_CACHE_32K_DSM_INDEX__INDEX__SHIFT 0x0
+#define ATC_L2_CACHE_32K_DSM_INDEX__INDEX_MASK 0x000000FFL
+//ATC_L2_CACHE_2M_DSM_INDEX
+#define ATC_L2_CACHE_2M_DSM_INDEX__INDEX__SHIFT 0x0
+#define ATC_L2_CACHE_2M_DSM_INDEX__INDEX_MASK 0x000000FFL
+//ATC_L2_CACHE_4K_DSM_CNTL
+#define ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY__SHIFT 0x0
+#define ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6
+#define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9
+#define ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb
+#define ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS__SHIFT 0xc
+#define ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT__SHIFT 0xd
+#define ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT__SHIFT 0xf
+#define ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE__SHIFT 0x11
+#define ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY_MASK 0x0000003FL
+#define ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L
+#define ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS_MASK 0x00001000L
+#define ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT_MASK 0x00006000L
+#define ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT_MASK 0x00018000L
+#define ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE_MASK 0x00020000L
+//ATC_L2_CACHE_32K_DSM_CNTL
+#define ATC_L2_CACHE_32K_DSM_CNTL__INJECT_DELAY__SHIFT 0x0
+#define ATC_L2_CACHE_32K_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6
+#define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9
+#define ATC_L2_CACHE_32K_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb
+#define ATC_L2_CACHE_32K_DSM_CNTL__WRITE_COUNTERS__SHIFT 0xc
+#define ATC_L2_CACHE_32K_DSM_CNTL__SEC_COUNT__SHIFT 0xd
+#define ATC_L2_CACHE_32K_DSM_CNTL__DED_COUNT__SHIFT 0xf
+#define ATC_L2_CACHE_32K_DSM_CNTL__TEST_FUE__SHIFT 0x11
+#define ATC_L2_CACHE_32K_DSM_CNTL__INJECT_DELAY_MASK 0x0000003FL
+#define ATC_L2_CACHE_32K_DSM_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define ATC_L2_CACHE_32K_DSM_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L
+#define ATC_L2_CACHE_32K_DSM_CNTL__WRITE_COUNTERS_MASK 0x00001000L
+#define ATC_L2_CACHE_32K_DSM_CNTL__SEC_COUNT_MASK 0x00006000L
+#define ATC_L2_CACHE_32K_DSM_CNTL__DED_COUNT_MASK 0x00018000L
+#define ATC_L2_CACHE_32K_DSM_CNTL__TEST_FUE_MASK 0x00020000L
+//ATC_L2_CACHE_2M_DSM_CNTL
+#define ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY__SHIFT 0x0
+#define ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6
+#define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9
+#define ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb
+#define ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS__SHIFT 0xc
+#define ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT__SHIFT 0xd
+#define ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT__SHIFT 0xf
+#define ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE__SHIFT 0x11
+#define ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY_MASK 0x0000003FL
+#define ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L
+#define ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS_MASK 0x00001000L
+#define ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT_MASK 0x00006000L
+#define ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT_MASK 0x00018000L
+#define ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE_MASK 0x00020000L
+//ATC_L2_CNTL4
+#define ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x0
+#define ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0xa
+#define ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000003FFL
+#define ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000FFC00L
+//ATC_L2_MM_GROUP_RT_CLASSES
+#define ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT 0x0
+#define ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK 0xFFFFFFFFL
+
+
+// addressBlock: mmhub_utcl2_atcl2pfcntldec
+//ATC_L2_PERFCOUNTER0_CFG
+#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//ATC_L2_PERFCOUNTER1_CFG
+#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//ATC_L2_PERFCOUNTER_RSLT_CNTL
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+
+
+// addressBlock: mmhub_utcl2_atcl2pfcntrdec
+//ATC_L2_PERFCOUNTER_LO
+#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//ATC_L2_PERFCOUNTER_HI
+#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+
+
+// addressBlock: mmhub_utcl2_l2tlbdec
+//L2TLB_TLB0_STATUS
+#define L2TLB_TLB0_STATUS__BUSY__SHIFT 0x0
+#define L2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
+#define L2TLB_TLB0_STATUS__BUSY_MASK 0x00000001L
+#define L2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
+//UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR__SHIFT 0x0
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR_MASK 0xFFFFFFFFL
+//UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR__SHIFT 0x0
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID__SHIFT 0x4
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID__SHIFT 0x9
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF__SHIFT 0xd
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA__SHIFT 0xe
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM__SHIFT 0x10
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM__SHIFT 0x11
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM__SHIFT 0x12
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID__SHIFT 0x13
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ__SHIFT 0x1f
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR_MASK 0x0000000FL
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID_MASK 0x000000F0L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID_MASK 0x00001E00L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF_MASK 0x00002000L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA_MASK 0x0000C000L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM_MASK 0x00010000L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM_MASK 0x00020000L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM_MASK 0x00040000L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID_MASK 0x0FF80000L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ_MASK 0x80000000L
+//UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR__SHIFT 0x0
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR_MASK 0xFFFFFFFFL
+//UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR__SHIFT 0x0
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS__SHIFT 0x4
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE__SHIFT 0x7
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP__SHIFT 0xd
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA__SHIFT 0xe
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO__SHIFT 0xf
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ__SHIFT 0x10
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE__SHIFT 0x11
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE__SHIFT 0x12
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG__SHIFT 0x14
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK__SHIFT 0x15
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK__SHIFT 0x1e
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR_MASK 0x0000000FL
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS_MASK 0x00000070L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE_MASK 0x00001F80L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP_MASK 0x00002000L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA_MASK 0x00004000L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO_MASK 0x00008000L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ_MASK 0x00010000L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE_MASK 0x00020000L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE_MASK 0x000C0000L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG_MASK 0x00100000L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK_MASK 0x00600000L
+#define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK_MASK 0x40000000L
+
+
+// addressBlock: mmhub_utcl2_l2tlbpldec
+//L2TLB_PERFCOUNTER0_CFG
+#define L2TLB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define L2TLB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define L2TLB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define L2TLB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define L2TLB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define L2TLB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define L2TLB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define L2TLB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define L2TLB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define L2TLB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//L2TLB_PERFCOUNTER1_CFG
+#define L2TLB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define L2TLB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define L2TLB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define L2TLB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define L2TLB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define L2TLB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define L2TLB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define L2TLB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define L2TLB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define L2TLB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//L2TLB_PERFCOUNTER2_CFG
+#define L2TLB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define L2TLB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define L2TLB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define L2TLB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define L2TLB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define L2TLB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
+#define L2TLB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define L2TLB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
+#define L2TLB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
+#define L2TLB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
+//L2TLB_PERFCOUNTER3_CFG
+#define L2TLB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define L2TLB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define L2TLB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define L2TLB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define L2TLB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define L2TLB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL
+#define L2TLB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define L2TLB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L
+#define L2TLB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L
+#define L2TLB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L
+//L2TLB_PERFCOUNTER_RSLT_CNTL
+#define L2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define L2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define L2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define L2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define L2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define L2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define L2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define L2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+
+
+// addressBlock: mmhub_utcl2_l2tlbprdec
+//L2TLB_PERFCOUNTER_LO
+#define L2TLB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define L2TLB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//L2TLB_PERFCOUNTER_HI
+#define L2TLB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define L2TLB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define L2TLB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define L2TLB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+
+
+// addressBlock: mmhub_utcl2_vml2pfdec
+//VM_L2_CNTL
+#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0
+#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1
+#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2
+#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4
+#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8
+#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9
+#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa
+#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
+#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc
+#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf
+#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12
+#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13
+#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15
+#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a
+#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L
+#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L
+#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL
+#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L
+#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L
+#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L
+#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L
+#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L
+#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L
+#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L
+#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L
+#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L
+#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L
+#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L
+//VM_L2_CNTL2
+#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0
+#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1
+#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15
+#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16
+#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17
+#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a
+#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c
+#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L
+#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L
+#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L
+#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L
+#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L
+#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L
+#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L
+//VM_L2_CNTL3
+#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0
+#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6
+#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8
+#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf
+#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14
+#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15
+#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18
+#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c
+#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d
+#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e
+#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f
+#define VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL
+#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L
+#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L
+#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L
+#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L
+#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L
+#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L
+#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L
+#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L
+#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L
+#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L
+//VM_L2_STATUS
+#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0
+#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1
+#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11
+#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12
+#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13
+#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14
+#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15
+#define VM_L2_STATUS__L2_BUSY_MASK 0x00000001L
+#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL
+#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L
+#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L
+#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L
+#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L
+#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L
+//VM_DUMMY_PAGE_FAULT_CNTL
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL
+//VM_DUMMY_PAGE_FAULT_ADDR_LO32
+#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0
+#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
+//VM_DUMMY_PAGE_FAULT_ADDR_HI32
+#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0
+#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL
+//VM_L2_PROTECTION_FAULT_CNTL
+#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1
+#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2
+#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3
+#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
+#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5
+#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6
+#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
+#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8
+#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9
+#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb
+#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd
+#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d
+#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e
+#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f
+#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L
+#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L
+#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L
+#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L
+#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L
+#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L
+#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L
+#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L
+#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L
+#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L
+#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L
+#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L
+#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L
+#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L
+#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L
+//VM_L2_PROTECTION_FAULT_CNTL2
+#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10
+#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11
+#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12
+#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13
+#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL
+#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L
+#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L
+#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L
+#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L
+//VM_L2_PROTECTION_FAULT_MM_CNTL3
+#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL
+//VM_L2_PROTECTION_FAULT_MM_CNTL4
+#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL
+//VM_L2_PROTECTION_FAULT_STATUS
+#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1
+#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4
+#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8
+#define VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9
+#define VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12
+#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13
+#define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14
+#define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18
+#define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19
+#define VM_L2_PROTECTION_FAULT_STATUS__UCE__SHIFT 0x1d
+#define VM_L2_PROTECTION_FAULT_STATUS__FED__SHIFT 0x1e
+#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L
+#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL
+#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L
+#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L
+#define VM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L
+#define VM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L
+#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L
+#define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L
+#define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L
+#define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L
+#define VM_L2_PROTECTION_FAULT_STATUS__UCE_MASK 0x20000000L
+#define VM_L2_PROTECTION_FAULT_STATUS__FED_MASK 0x40000000L
+//VM_L2_PROTECTION_FAULT_ADDR_LO32
+#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
+//VM_L2_PROTECTION_FAULT_ADDR_HI32
+#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL
+//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32
+#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
+//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32
+#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0
+#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL
+//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32
+#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0
+#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL
+//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32
+#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0
+#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL
+//VM_L2_CNTL4
+#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0
+#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6
+#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7
+#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8
+#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12
+#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c
+#define VM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT 0x1d
+#define VM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT 0x1e
+#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL
+#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L
+#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L
+#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L
+#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L
+#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L
+#define VM_L2_CNTL4__GC_CH_FGCG_OFF_MASK 0x20000000L
+#define VM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK 0x40000000L
+//VM_L2_MM_GROUP_RT_CLASSES
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L
+#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L
+//VM_L2_BANK_SELECT_RESERVED_CID
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
+#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L
+#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L
+//VM_L2_BANK_SELECT_RESERVED_CID2
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
+#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L
+#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L
+//VM_L2_CACHE_PARITY_CNTL
+#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0
+#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1
+#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc
+#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L
+#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L
+#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L
+#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L
+//VM_L2_CGTT_CLK_CTRL
+#define VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
+#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
+#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
+#define VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
+#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
+#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
+//VM_L2_CGTT_BUSY_CTRL
+#define VM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0
+#define VM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x4
+#define VM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000000FL
+#define VM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000010L
+//VML2_MEM_ECC_INDEX
+#define VML2_MEM_ECC_INDEX__INDEX__SHIFT 0x0
+#define VML2_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL
+//VML2_WALKER_MEM_ECC_INDEX
+#define VML2_WALKER_MEM_ECC_INDEX__INDEX__SHIFT 0x0
+#define VML2_WALKER_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL
+//UTCL2_MEM_ECC_INDEX
+#define UTCL2_MEM_ECC_INDEX__INDEX__SHIFT 0x0
+#define UTCL2_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL
+//VML2_MEM_ECC_CNTL
+#define VML2_MEM_ECC_CNTL__INJECT_DELAY__SHIFT 0x0
+#define VML2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6
+#define VML2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define VML2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9
+#define VML2_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb
+#define VML2_MEM_ECC_CNTL__SEC_COUNT__SHIFT 0xc
+#define VML2_MEM_ECC_CNTL__DED_COUNT__SHIFT 0xe
+#define VML2_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT 0x10
+#define VML2_MEM_ECC_CNTL__TEST_FUE__SHIFT 0x11
+#define VML2_MEM_ECC_CNTL__INJECT_DELAY_MASK 0x0000003FL
+#define VML2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define VML2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define VML2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define VML2_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L
+#define VML2_MEM_ECC_CNTL__SEC_COUNT_MASK 0x00003000L
+#define VML2_MEM_ECC_CNTL__DED_COUNT_MASK 0x0000C000L
+#define VML2_MEM_ECC_CNTL__WRITE_COUNTERS_MASK 0x00010000L
+#define VML2_MEM_ECC_CNTL__TEST_FUE_MASK 0x00020000L
+//VML2_WALKER_MEM_ECC_CNTL
+#define VML2_WALKER_MEM_ECC_CNTL__INJECT_DELAY__SHIFT 0x0
+#define VML2_WALKER_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6
+#define VML2_WALKER_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define VML2_WALKER_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9
+#define VML2_WALKER_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb
+#define VML2_WALKER_MEM_ECC_CNTL__SEC_COUNT__SHIFT 0xc
+#define VML2_WALKER_MEM_ECC_CNTL__DED_COUNT__SHIFT 0xe
+#define VML2_WALKER_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT 0x10
+#define VML2_WALKER_MEM_ECC_CNTL__TEST_FUE__SHIFT 0x11
+#define VML2_WALKER_MEM_ECC_CNTL__INJECT_DELAY_MASK 0x0000003FL
+#define VML2_WALKER_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define VML2_WALKER_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define VML2_WALKER_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define VML2_WALKER_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L
+#define VML2_WALKER_MEM_ECC_CNTL__SEC_COUNT_MASK 0x00003000L
+#define VML2_WALKER_MEM_ECC_CNTL__DED_COUNT_MASK 0x0000C000L
+#define VML2_WALKER_MEM_ECC_CNTL__WRITE_COUNTERS_MASK 0x00010000L
+#define VML2_WALKER_MEM_ECC_CNTL__TEST_FUE_MASK 0x00020000L
+//UTCL2_MEM_ECC_CNTL
+#define UTCL2_MEM_ECC_CNTL__INJECT_DELAY__SHIFT 0x0
+#define UTCL2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6
+#define UTCL2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define UTCL2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9
+#define UTCL2_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb
+#define UTCL2_MEM_ECC_CNTL__SEC_COUNT__SHIFT 0xc
+#define UTCL2_MEM_ECC_CNTL__DED_COUNT__SHIFT 0xe
+#define UTCL2_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT 0x10
+#define UTCL2_MEM_ECC_CNTL__TEST_FUE__SHIFT 0x11
+#define UTCL2_MEM_ECC_CNTL__INJECT_DELAY_MASK 0x0000003FL
+#define UTCL2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define UTCL2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define UTCL2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define UTCL2_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L
+#define UTCL2_MEM_ECC_CNTL__SEC_COUNT_MASK 0x00003000L
+#define UTCL2_MEM_ECC_CNTL__DED_COUNT_MASK 0x0000C000L
+#define UTCL2_MEM_ECC_CNTL__WRITE_COUNTERS_MASK 0x00010000L
+#define UTCL2_MEM_ECC_CNTL__TEST_FUE_MASK 0x00020000L
+//VML2_MEM_ECC_STATUS
+#define VML2_MEM_ECC_STATUS__UCE__SHIFT 0x0
+#define VML2_MEM_ECC_STATUS__FED__SHIFT 0x1
+#define VML2_MEM_ECC_STATUS__UCE_MASK 0x00000001L
+#define VML2_MEM_ECC_STATUS__FED_MASK 0x00000002L
+//VML2_WALKER_MEM_ECC_STATUS
+#define VML2_WALKER_MEM_ECC_STATUS__UCE__SHIFT 0x0
+#define VML2_WALKER_MEM_ECC_STATUS__FED__SHIFT 0x1
+#define VML2_WALKER_MEM_ECC_STATUS__UCE_MASK 0x00000001L
+#define VML2_WALKER_MEM_ECC_STATUS__FED_MASK 0x00000002L
+//UTCL2_MEM_ECC_STATUS
+#define UTCL2_MEM_ECC_STATUS__UCE__SHIFT 0x0
+#define UTCL2_MEM_ECC_STATUS__FED__SHIFT 0x1
+#define UTCL2_MEM_ECC_STATUS__UCE_MASK 0x00000001L
+#define UTCL2_MEM_ECC_STATUS__FED_MASK 0x00000002L
+//UTCL2_EDC_MODE
+#define UTCL2_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0xf
+#define UTCL2_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10
+#define UTCL2_EDC_MODE__GATE_FUE__SHIFT 0x11
+#define UTCL2_EDC_MODE__DED_MODE__SHIFT 0x14
+#define UTCL2_EDC_MODE__PROP_FED__SHIFT 0x1d
+#define UTCL2_EDC_MODE__BYPASS__SHIFT 0x1f
+#define UTCL2_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x00008000L
+#define UTCL2_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L
+#define UTCL2_EDC_MODE__GATE_FUE_MASK 0x00020000L
+#define UTCL2_EDC_MODE__DED_MODE_MASK 0x00300000L
+#define UTCL2_EDC_MODE__PROP_FED_MASK 0x20000000L
+#define UTCL2_EDC_MODE__BYPASS_MASK 0x80000000L
+//UTCL2_EDC_CONFIG
+#define UTCL2_EDC_CONFIG__DIS_EDC__SHIFT 0x1
+#define UTCL2_EDC_CONFIG__DIS_EDC_MASK 0x00000002L
+
+
+// addressBlock: mmhub_utcl2_vml2pldec
+//MC_VM_L2_PERFCOUNTER0_CFG
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_L2_PERFCOUNTER1_CFG
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_L2_PERFCOUNTER2_CFG
+#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_L2_PERFCOUNTER3_CFG
+#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_L2_PERFCOUNTER4_CFG
+#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_L2_PERFCOUNTER5_CFG
+#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_L2_PERFCOUNTER6_CFG
+#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_L2_PERFCOUNTER7_CFG
+#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL
+#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L
+#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L
+#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L
+//MC_VM_L2_PERFCOUNTER_RSLT_CNTL
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+
+
+// addressBlock: mmhub_utcl2_vml2prdec
+//MC_VM_L2_PERFCOUNTER_LO
+#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//MC_VM_L2_PERFCOUNTER_HI
+#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+
+
+// addressBlock: mmhub_utcl2_vml2vcdec
+//VM_CONTEXT0_CNTL
+#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT1_CNTL
+#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT2_CNTL
+#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT3_CNTL
+#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT4_CNTL
+#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT5_CNTL
+#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT6_CNTL
+#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT7_CNTL
+#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT8_CNTL
+#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT9_CNTL
+#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT10_CNTL
+#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT11_CNTL
+#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT12_CNTL
+#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT13_CNTL
+#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT14_CNTL
+#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXT15_CNTL
+#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//VM_CONTEXTS_DISABLE
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L
+//VM_INVALIDATE_ENG0_SEM
+#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG1_SEM
+#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG2_SEM
+#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG3_SEM
+#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG4_SEM
+#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG5_SEM
+#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG6_SEM
+#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG7_SEM
+#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG8_SEM
+#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG9_SEM
+#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG10_SEM
+#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG11_SEM
+#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG12_SEM
+#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG13_SEM
+#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG14_SEM
+#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG15_SEM
+#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG16_SEM
+#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG17_SEM
+#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0
+#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L
+//VM_INVALIDATE_ENG0_REQ
+#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG1_REQ
+#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG2_REQ
+#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG3_REQ
+#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG4_REQ
+#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG5_REQ
+#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG6_REQ
+#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG7_REQ
+#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG8_REQ
+#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG9_REQ
+#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG10_REQ
+#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG11_REQ
+#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG12_REQ
+#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG13_REQ
+#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG14_REQ
+#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG15_REQ
+#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG16_REQ
+#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG17_REQ
+#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
+#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
+#define VM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT 0x18
+#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00030000L
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
+#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
+#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
+#define VM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK 0x01000000L
+//VM_INVALIDATE_ENG0_ACK
+#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG1_ACK
+#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG2_ACK
+#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG3_ACK
+#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG4_ACK
+#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG5_ACK
+#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG6_ACK
+#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG7_ACK
+#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG8_ACK
+#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG9_ACK
+#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG10_ACK
+#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG11_ACK
+#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG12_ACK
+#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG13_ACK
+#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG14_ACK
+#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG15_ACK
+#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG16_ACK
+#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG17_ACK
+#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10
+#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L
+//VM_INVALIDATE_ENG0_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG0_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG1_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG1_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG2_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG2_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG3_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG3_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG4_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG4_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG5_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG5_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG6_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG6_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG7_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG7_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG8_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG8_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG9_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG9_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG10_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG10_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG11_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG11_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG12_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG12_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG13_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG13_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG14_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG14_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG15_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG15_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG16_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG16_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_INVALIDATE_ENG17_ADDR_RANGE_LO32
+#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//VM_INVALIDATE_ENG17_ADDR_RANGE_HI32
+#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
+#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
+#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
+#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
+#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
+#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
+#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+
+
+// addressBlock: mmhub_utcl2_vmsharedhvdec
+//MC_VM_FB_SIZE_OFFSET_VF0
+#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF1
+#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF2
+#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF3
+#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF4
+#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF5
+#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF6
+#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF7
+#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF8
+#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF9
+#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF10
+#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF11
+#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF12
+#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF13
+#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF14
+#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_FB_SIZE_OFFSET_VF15
+#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MC_VM_MARC_BASE_LO_0
+#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc
+#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L
+//MC_VM_MARC_BASE_LO_1
+#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc
+#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L
+//MC_VM_MARC_BASE_LO_2
+#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc
+#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L
+//MC_VM_MARC_BASE_LO_3
+#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc
+#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L
+//MC_VM_MARC_BASE_HI_0
+#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0
+#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL
+//MC_VM_MARC_BASE_HI_1
+#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0
+#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL
+//MC_VM_MARC_BASE_HI_2
+#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0
+#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL
+//MC_VM_MARC_BASE_HI_3
+#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0
+#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL
+//MC_VM_MARC_RELOC_LO_0
+#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0
+#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1
+#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc
+#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L
+#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L
+#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L
+//MC_VM_MARC_RELOC_LO_1
+#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0
+#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1
+#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc
+#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L
+#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L
+#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L
+//MC_VM_MARC_RELOC_LO_2
+#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0
+#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1
+#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc
+#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L
+#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L
+#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L
+//MC_VM_MARC_RELOC_LO_3
+#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0
+#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1
+#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc
+#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L
+#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L
+#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L
+//MC_VM_MARC_RELOC_HI_0
+#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0
+#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL
+//MC_VM_MARC_RELOC_HI_1
+#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0
+#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL
+//MC_VM_MARC_RELOC_HI_2
+#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0
+#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL
+//MC_VM_MARC_RELOC_HI_3
+#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0
+#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL
+//MC_VM_MARC_LEN_LO_0
+#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc
+#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L
+//MC_VM_MARC_LEN_LO_1
+#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc
+#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L
+//MC_VM_MARC_LEN_LO_2
+#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc
+#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L
+//MC_VM_MARC_LEN_LO_3
+#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc
+#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L
+//MC_VM_MARC_LEN_HI_0
+#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0
+#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL
+//MC_VM_MARC_LEN_HI_1
+#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0
+#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL
+//MC_VM_MARC_LEN_HI_2
+#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0
+#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL
+//MC_VM_MARC_LEN_HI_3
+#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0
+#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL
+//VM_PCIE_ATS_CNTL
+#define VM_PCIE_ATS_CNTL__STU__SHIFT 0x10
+#define VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L
+#define VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_0
+#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_1
+#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_2
+#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_3
+#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_4
+#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_5
+#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_6
+#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_7
+#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_8
+#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_9
+#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_10
+#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_11
+#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_12
+#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_13
+#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_14
+#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L
+//VM_PCIE_ATS_CNTL_VF_15
+#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f
+#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L
+//MC_SHARED_ACTIVE_FCN_ID
+#define MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0
+#define MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f
+#define MC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
+#define MC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L
+//MC_VM_XGMI_GPUIOV_ENABLE
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0__SHIFT 0x0
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1__SHIFT 0x1
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2__SHIFT 0x2
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3__SHIFT 0x3
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4__SHIFT 0x4
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5__SHIFT 0x5
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6__SHIFT 0x6
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7__SHIFT 0x7
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8__SHIFT 0x8
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9__SHIFT 0x9
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10__SHIFT 0xa
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11__SHIFT 0xb
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12__SHIFT 0xc
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13__SHIFT 0xd
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14__SHIFT 0xe
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15__SHIFT 0xf
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF__SHIFT 0x1f
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0_MASK 0x00000001L
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1_MASK 0x00000002L
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2_MASK 0x00000004L
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3_MASK 0x00000008L
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4_MASK 0x00000010L
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5_MASK 0x00000020L
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6_MASK 0x00000040L
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7_MASK 0x00000080L
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8_MASK 0x00000100L
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9_MASK 0x00000200L
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10_MASK 0x00000400L
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11_MASK 0x00000800L
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12_MASK 0x00001000L
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13_MASK 0x00002000L
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14_MASK 0x00004000L
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15_MASK 0x00008000L
+#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF_MASK 0x80000000L
+
+
+// addressBlock: mmhub_utcl2_vmsharedpfdec
+//MC_VM_FB_OFFSET
+#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0
+#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL
+//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
+#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0
+#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL
+//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
+#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0
+#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL
+//MC_VM_STEERING
+#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0
+#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L
+//MC_SHARED_VIRT_RESET_REQ
+#define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0
+#define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f
+#define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL
+#define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L
+//MC_MEM_POWER_LS
+#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
+#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
+#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL
+#define MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L
+//MC_VM_CACHEABLE_DRAM_ADDRESS_START
+#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0
+#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x00FFFFFFL
+//MC_VM_CACHEABLE_DRAM_ADDRESS_END
+#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0
+#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x00FFFFFFL
+//MC_VM_APT_CNTL
+#define MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0
+#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1
+#define MC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT 0x2
+#define MC_VM_APT_CNTL__PERMS_GRANTED__SHIFT 0x3
+#define MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L
+#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L
+#define MC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK 0x00000004L
+#define MC_VM_APT_CNTL__PERMS_GRANTED_MASK 0x00000008L
+//MC_VM_LOCAL_HBM_ADDRESS_START
+#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0
+#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x00FFFFFFL
+//MC_VM_LOCAL_HBM_ADDRESS_END
+#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0
+#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x00FFFFFFL
+//MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL
+#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0
+#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L
+//UTCL2_CGTT_CLK_CTRL
+#define UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0xc
+#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
+#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
+#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
+#define UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L
+#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
+#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
+#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
+//MC_VM_XGMI_LFB_CNTL
+#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT 0x0
+#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT 0x4
+#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK 0x0000000FL
+#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK 0x000000F0L
+//MC_VM_XGMI_LFB_SIZE
+#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT 0x0
+#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK 0x0001FFFFL
+//MC_VM_CACHEABLE_DRAM_CNTL
+#define MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE__SHIFT 0x0
+#define MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE_MASK 0x00000001L
+//MC_VM_HOST_MAPPING
+#define MC_VM_HOST_MAPPING__MODE__SHIFT 0x0
+#define MC_VM_HOST_MAPPING__MODE_MASK 0x00000001L
+
+
+// addressBlock: mmhub_utcl2_vmsharedvcdec
+//MC_VM_FB_LOCATION_BASE
+#define MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0
+#define MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL
+//MC_VM_FB_LOCATION_TOP
+#define MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0
+#define MC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL
+//MC_VM_AGP_TOP
+#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0
+#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL
+//MC_VM_AGP_BOT
+#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0
+#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL
+//MC_VM_AGP_BASE
+#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0
+#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL
+//MC_VM_SYSTEM_APERTURE_LOW_ADDR
+#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0
+#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL
+//MC_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0
+#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL
+//MC_VM_MX_L1_TLB_CNTL
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0
+#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3
+#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6
+#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7
+#define MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb
+#define MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT 0xd
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L
+#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L
+#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L
+#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L
+#define MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L
+#define MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK 0x00002000L
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_2_offset.h
new file mode 100644
index 000000000000..0b1e781fed7e
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_2_offset.h
@@ -0,0 +1,361 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ *
+ */
+#ifndef _mp_13_0_2_OFFSET_HEADER
+#define _mp_13_0_2_OFFSET_HEADER
+
+
+
+// addressBlock: mp_SmuMp0_SmnDec
+// base address: 0x0
+#define regMP0_SMN_C2PMSG_32 0x0060
+#define regMP0_SMN_C2PMSG_32_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_33 0x0061
+#define regMP0_SMN_C2PMSG_33_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_34 0x0062
+#define regMP0_SMN_C2PMSG_34_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_35 0x0063
+#define regMP0_SMN_C2PMSG_35_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_36 0x0064
+#define regMP0_SMN_C2PMSG_36_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_37 0x0065
+#define regMP0_SMN_C2PMSG_37_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_38 0x0066
+#define regMP0_SMN_C2PMSG_38_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_39 0x0067
+#define regMP0_SMN_C2PMSG_39_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_40 0x0068
+#define regMP0_SMN_C2PMSG_40_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_41 0x0069
+#define regMP0_SMN_C2PMSG_41_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_42 0x006a
+#define regMP0_SMN_C2PMSG_42_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_43 0x006b
+#define regMP0_SMN_C2PMSG_43_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_44 0x006c
+#define regMP0_SMN_C2PMSG_44_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_45 0x006d
+#define regMP0_SMN_C2PMSG_45_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_46 0x006e
+#define regMP0_SMN_C2PMSG_46_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_47 0x006f
+#define regMP0_SMN_C2PMSG_47_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_48 0x0070
+#define regMP0_SMN_C2PMSG_48_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_49 0x0071
+#define regMP0_SMN_C2PMSG_49_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_50 0x0072
+#define regMP0_SMN_C2PMSG_50_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_51 0x0073
+#define regMP0_SMN_C2PMSG_51_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_52 0x0074
+#define regMP0_SMN_C2PMSG_52_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_53 0x0075
+#define regMP0_SMN_C2PMSG_53_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_54 0x0076
+#define regMP0_SMN_C2PMSG_54_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_55 0x0077
+#define regMP0_SMN_C2PMSG_55_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_56 0x0078
+#define regMP0_SMN_C2PMSG_56_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_57 0x0079
+#define regMP0_SMN_C2PMSG_57_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_58 0x007a
+#define regMP0_SMN_C2PMSG_58_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_59 0x007b
+#define regMP0_SMN_C2PMSG_59_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_60 0x007c
+#define regMP0_SMN_C2PMSG_60_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_61 0x007d
+#define regMP0_SMN_C2PMSG_61_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_62 0x007e
+#define regMP0_SMN_C2PMSG_62_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_63 0x007f
+#define regMP0_SMN_C2PMSG_63_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_64 0x0080
+#define regMP0_SMN_C2PMSG_64_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_65 0x0081
+#define regMP0_SMN_C2PMSG_65_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_66 0x0082
+#define regMP0_SMN_C2PMSG_66_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_67 0x0083
+#define regMP0_SMN_C2PMSG_67_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_68 0x0084
+#define regMP0_SMN_C2PMSG_68_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_69 0x0085
+#define regMP0_SMN_C2PMSG_69_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_70 0x0086
+#define regMP0_SMN_C2PMSG_70_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_71 0x0087
+#define regMP0_SMN_C2PMSG_71_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_72 0x0088
+#define regMP0_SMN_C2PMSG_72_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_73 0x0089
+#define regMP0_SMN_C2PMSG_73_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_74 0x008a
+#define regMP0_SMN_C2PMSG_74_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_75 0x008b
+#define regMP0_SMN_C2PMSG_75_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_76 0x008c
+#define regMP0_SMN_C2PMSG_76_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_77 0x008d
+#define regMP0_SMN_C2PMSG_77_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_78 0x008e
+#define regMP0_SMN_C2PMSG_78_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_79 0x008f
+#define regMP0_SMN_C2PMSG_79_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_80 0x0090
+#define regMP0_SMN_C2PMSG_80_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_81 0x0091
+#define regMP0_SMN_C2PMSG_81_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_82 0x0092
+#define regMP0_SMN_C2PMSG_82_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_83 0x0093
+#define regMP0_SMN_C2PMSG_83_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_84 0x0094
+#define regMP0_SMN_C2PMSG_84_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_85 0x0095
+#define regMP0_SMN_C2PMSG_85_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_86 0x0096
+#define regMP0_SMN_C2PMSG_86_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_87 0x0097
+#define regMP0_SMN_C2PMSG_87_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_88 0x0098
+#define regMP0_SMN_C2PMSG_88_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_89 0x0099
+#define regMP0_SMN_C2PMSG_89_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_90 0x009a
+#define regMP0_SMN_C2PMSG_90_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_91 0x009b
+#define regMP0_SMN_C2PMSG_91_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_92 0x009c
+#define regMP0_SMN_C2PMSG_92_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_93 0x009d
+#define regMP0_SMN_C2PMSG_93_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_94 0x009e
+#define regMP0_SMN_C2PMSG_94_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_95 0x009f
+#define regMP0_SMN_C2PMSG_95_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_96 0x00a0
+#define regMP0_SMN_C2PMSG_96_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_97 0x00a1
+#define regMP0_SMN_C2PMSG_97_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_98 0x00a2
+#define regMP0_SMN_C2PMSG_98_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_99 0x00a3
+#define regMP0_SMN_C2PMSG_99_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_100 0x00a4
+#define regMP0_SMN_C2PMSG_100_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_101 0x00a5
+#define regMP0_SMN_C2PMSG_101_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_102 0x00a6
+#define regMP0_SMN_C2PMSG_102_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_103 0x00a7
+#define regMP0_SMN_C2PMSG_103_BASE_IDX 0
+#define regMP0_SMN_IH_CREDIT 0x00c1
+#define regMP0_SMN_IH_CREDIT_BASE_IDX 0
+#define regMP0_SMN_IH_SW_INT 0x00c2
+#define regMP0_SMN_IH_SW_INT_BASE_IDX 0
+#define regMP0_SMN_IH_SW_INT_CTRL 0x00c3
+#define regMP0_SMN_IH_SW_INT_CTRL_BASE_IDX 0
+
+
+// addressBlock: mp_SmuMp1Pub_CruDec
+// base address: 0x0
+#define regMP1_FIRMWARE_FLAGS 0xbee009
+#define regMP1_FIRMWARE_FLAGS_BASE_IDX 0
+
+
+// addressBlock: mp_SmuMp1_SmnDec
+// base address: 0x0
+#define regMP1_SMN_C2PMSG_32 0x0260
+#define regMP1_SMN_C2PMSG_32_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_33 0x0261
+#define regMP1_SMN_C2PMSG_33_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_34 0x0262
+#define regMP1_SMN_C2PMSG_34_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_35 0x0263
+#define regMP1_SMN_C2PMSG_35_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_36 0x0264
+#define regMP1_SMN_C2PMSG_36_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_37 0x0265
+#define regMP1_SMN_C2PMSG_37_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_38 0x0266
+#define regMP1_SMN_C2PMSG_38_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_39 0x0267
+#define regMP1_SMN_C2PMSG_39_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_40 0x0268
+#define regMP1_SMN_C2PMSG_40_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_41 0x0269
+#define regMP1_SMN_C2PMSG_41_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_42 0x026a
+#define regMP1_SMN_C2PMSG_42_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_43 0x026b
+#define regMP1_SMN_C2PMSG_43_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_44 0x026c
+#define regMP1_SMN_C2PMSG_44_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_45 0x026d
+#define regMP1_SMN_C2PMSG_45_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_46 0x026e
+#define regMP1_SMN_C2PMSG_46_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_47 0x026f
+#define regMP1_SMN_C2PMSG_47_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_48 0x0270
+#define regMP1_SMN_C2PMSG_48_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_49 0x0271
+#define regMP1_SMN_C2PMSG_49_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_50 0x0272
+#define regMP1_SMN_C2PMSG_50_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_51 0x0273
+#define regMP1_SMN_C2PMSG_51_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_52 0x0274
+#define regMP1_SMN_C2PMSG_52_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_53 0x0275
+#define regMP1_SMN_C2PMSG_53_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_54 0x0276
+#define regMP1_SMN_C2PMSG_54_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_55 0x0277
+#define regMP1_SMN_C2PMSG_55_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_56 0x0278
+#define regMP1_SMN_C2PMSG_56_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_57 0x0279
+#define regMP1_SMN_C2PMSG_57_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_58 0x027a
+#define regMP1_SMN_C2PMSG_58_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_59 0x027b
+#define regMP1_SMN_C2PMSG_59_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_60 0x027c
+#define regMP1_SMN_C2PMSG_60_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_61 0x027d
+#define regMP1_SMN_C2PMSG_61_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_62 0x027e
+#define regMP1_SMN_C2PMSG_62_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_63 0x027f
+#define regMP1_SMN_C2PMSG_63_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_64 0x0280
+#define regMP1_SMN_C2PMSG_64_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_65 0x0281
+#define regMP1_SMN_C2PMSG_65_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_66 0x0282
+#define regMP1_SMN_C2PMSG_66_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_67 0x0283
+#define regMP1_SMN_C2PMSG_67_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_68 0x0284
+#define regMP1_SMN_C2PMSG_68_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_69 0x0285
+#define regMP1_SMN_C2PMSG_69_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_70 0x0286
+#define regMP1_SMN_C2PMSG_70_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_71 0x0287
+#define regMP1_SMN_C2PMSG_71_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_72 0x0288
+#define regMP1_SMN_C2PMSG_72_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_73 0x0289
+#define regMP1_SMN_C2PMSG_73_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_74 0x028a
+#define regMP1_SMN_C2PMSG_74_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_75 0x028b
+#define regMP1_SMN_C2PMSG_75_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_76 0x028c
+#define regMP1_SMN_C2PMSG_76_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_77 0x028d
+#define regMP1_SMN_C2PMSG_77_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_78 0x028e
+#define regMP1_SMN_C2PMSG_78_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_79 0x028f
+#define regMP1_SMN_C2PMSG_79_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_80 0x0290
+#define regMP1_SMN_C2PMSG_80_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_81 0x0291
+#define regMP1_SMN_C2PMSG_81_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_82 0x0292
+#define regMP1_SMN_C2PMSG_82_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_83 0x0293
+#define regMP1_SMN_C2PMSG_83_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_84 0x0294
+#define regMP1_SMN_C2PMSG_84_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_85 0x0295
+#define regMP1_SMN_C2PMSG_85_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_86 0x0296
+#define regMP1_SMN_C2PMSG_86_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_87 0x0297
+#define regMP1_SMN_C2PMSG_87_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_88 0x0298
+#define regMP1_SMN_C2PMSG_88_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_89 0x0299
+#define regMP1_SMN_C2PMSG_89_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_90 0x029a
+#define regMP1_SMN_C2PMSG_90_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_91 0x029b
+#define regMP1_SMN_C2PMSG_91_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_92 0x029c
+#define regMP1_SMN_C2PMSG_92_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_93 0x029d
+#define regMP1_SMN_C2PMSG_93_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_94 0x029e
+#define regMP1_SMN_C2PMSG_94_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_95 0x029f
+#define regMP1_SMN_C2PMSG_95_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_96 0x02a0
+#define regMP1_SMN_C2PMSG_96_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_97 0x02a1
+#define regMP1_SMN_C2PMSG_97_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_98 0x02a2
+#define regMP1_SMN_C2PMSG_98_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_99 0x02a3
+#define regMP1_SMN_C2PMSG_99_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_100 0x02a4
+#define regMP1_SMN_C2PMSG_100_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_101 0x02a5
+#define regMP1_SMN_C2PMSG_101_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_102 0x02a6
+#define regMP1_SMN_C2PMSG_102_BASE_IDX 0
+#define regMP1_SMN_C2PMSG_103 0x02a7
+#define regMP1_SMN_C2PMSG_103_BASE_IDX 0
+#define regMP1_SMN_IH_CREDIT 0x02c1
+#define regMP1_SMN_IH_CREDIT_BASE_IDX 0
+#define regMP1_SMN_IH_SW_INT 0x02c2
+#define regMP1_SMN_IH_SW_INT_BASE_IDX 0
+#define regMP1_SMN_IH_SW_INT_CTRL 0x02c3
+#define regMP1_SMN_IH_SW_INT_CTRL_BASE_IDX 0
+#define regMP1_SMN_FPS_CNT 0x02c4
+#define regMP1_SMN_FPS_CNT_BASE_IDX 0
+#define regMP1_SMN_EXT_SCRATCH0 0x0340
+#define regMP1_SMN_EXT_SCRATCH0_BASE_IDX 0
+#define regMP1_SMN_EXT_SCRATCH1 0x0341
+#define regMP1_SMN_EXT_SCRATCH1_BASE_IDX 0
+#define regMP1_SMN_EXT_SCRATCH2 0x0342
+#define regMP1_SMN_EXT_SCRATCH2_BASE_IDX 0
+#define regMP1_SMN_EXT_SCRATCH3 0x0343
+#define regMP1_SMN_EXT_SCRATCH3_BASE_IDX 0
+#define regMP1_SMN_EXT_SCRATCH4 0x0344
+#define regMP1_SMN_EXT_SCRATCH4_BASE_IDX 0
+#define regMP1_SMN_EXT_SCRATCH5 0x0345
+#define regMP1_SMN_EXT_SCRATCH5_BASE_IDX 0
+#define regMP1_SMN_EXT_SCRATCH6 0x0346
+#define regMP1_SMN_EXT_SCRATCH6_BASE_IDX 0
+#define regMP1_SMN_EXT_SCRATCH7 0x0347
+#define regMP1_SMN_EXT_SCRATCH7_BASE_IDX 0
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_2_sh_mask.h
new file mode 100644
index 000000000000..0af8e95dadab
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_2_sh_mask.h
@@ -0,0 +1,531 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ *
+ */
+#ifndef _mp_13_0_2_SH_MASK_HEADER
+#define _mp_13_0_2_SH_MASK_HEADER
+
+
+// addressBlock: mp_SmuMp0_SmnDec
+//MP0_SMN_C2PMSG_32
+#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_33
+#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_34
+#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_35
+#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_36
+#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_37
+#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_38
+#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_39
+#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_40
+#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_41
+#define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_42
+#define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_43
+#define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_44
+#define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_45
+#define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_46
+#define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_47
+#define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_48
+#define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_49
+#define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_50
+#define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_51
+#define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_52
+#define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_53
+#define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_54
+#define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_55
+#define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_56
+#define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_57
+#define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_58
+#define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_59
+#define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_60
+#define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_61
+#define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_62
+#define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_63
+#define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_64
+#define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_65
+#define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_66
+#define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_67
+#define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_68
+#define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_69
+#define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_70
+#define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_71
+#define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_72
+#define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_73
+#define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_74
+#define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_75
+#define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_76
+#define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_77
+#define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_78
+#define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_79
+#define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_80
+#define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_81
+#define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_82
+#define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_83
+#define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_84
+#define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_85
+#define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_86
+#define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_87
+#define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_88
+#define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_89
+#define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_90
+#define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_91
+#define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_92
+#define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_93
+#define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_94
+#define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_95
+#define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_96
+#define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_97
+#define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_98
+#define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_99
+#define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_100
+#define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_101
+#define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_102
+#define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_C2PMSG_103
+#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
+#define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
+//MP0_SMN_IH_CREDIT
+#define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
+#define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10
+#define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
+#define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
+//MP0_SMN_IH_SW_INT
+#define MP0_SMN_IH_SW_INT__ID__SHIFT 0x0
+#define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x8
+#define MP0_SMN_IH_SW_INT__ID_MASK 0x000000FFL
+#define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000100L
+//MP0_SMN_IH_SW_INT_CTRL
+#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0
+#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8
+#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L
+#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L
+
+
+// addressBlock: mp_SmuMp1Pub_CruDec
+//MP1_FIRMWARE_FLAGS
+#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0
+#define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1
+#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L
+#define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL
+
+
+// addressBlock: mp_SmuMp1_SmnDec
+//MP1_SMN_C2PMSG_32
+#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_33
+#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_34
+#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_35
+#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_36
+#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_37
+#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_38
+#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_39
+#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_40
+#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_41
+#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_42
+#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_43
+#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_44
+#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_45
+#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_46
+#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_47
+#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_48
+#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_49
+#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_50
+#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_51
+#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_52
+#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_53
+#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_54
+#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_55
+#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_56
+#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_57
+#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_58
+#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_59
+#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_60
+#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_61
+#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_62
+#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_63
+#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_64
+#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_65
+#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_66
+#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_67
+#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_68
+#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_69
+#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_70
+#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_71
+#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_72
+#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_73
+#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_74
+#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_75
+#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_76
+#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_77
+#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_78
+#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_79
+#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_80
+#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_81
+#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_82
+#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_83
+#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_84
+#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_85
+#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_86
+#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_87
+#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_88
+#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_89
+#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_90
+#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_91
+#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_92
+#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_93
+#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_94
+#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_95
+#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_96
+#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_97
+#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_98
+#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_99
+#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_100
+#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_101
+#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_102
+#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_103
+#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_IH_CREDIT
+#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
+#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10
+#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
+#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
+//MP1_SMN_IH_SW_INT
+#define MP1_SMN_IH_SW_INT__ID__SHIFT 0x0
+#define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x8
+#define MP1_SMN_IH_SW_INT__ID_MASK 0x000000FFL
+#define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000100L
+//MP1_SMN_IH_SW_INT_CTRL
+#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0
+#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8
+#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L
+#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L
+//MP1_SMN_FPS_CNT
+#define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0
+#define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH0
+#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0
+#define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH1
+#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0
+#define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH2
+#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0
+#define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH3
+#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0
+#define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH4
+#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0
+#define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH5
+#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0
+#define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH6
+#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0
+#define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH7
+#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0
+#define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_0_offset.h
new file mode 100644
index 000000000000..9f156633fdb6
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_0_offset.h
@@ -0,0 +1,5224 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef _sdma_4_4_0_OFFSET_HEADER
+#define _sdma_4_4_0_OFFSET_HEADER
+
+
+// addressBlock: sdma0_sdma0dec
+// base address: 0x4980
+#define regSDMA0_UCODE_ADDR 0x0000
+#define regSDMA0_UCODE_ADDR_BASE_IDX 0
+#define regSDMA0_UCODE_DATA 0x0001
+#define regSDMA0_UCODE_DATA_BASE_IDX 0
+#define regSDMA0_VF_ENABLE 0x000a
+#define regSDMA0_VF_ENABLE_BASE_IDX 0
+#define regSDMA0_CONTEXT_GROUP_BOUNDARY 0x0019
+#define regSDMA0_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0
+#define regSDMA0_POWER_CNTL 0x001a
+#define regSDMA0_POWER_CNTL_BASE_IDX 0
+#define regSDMA0_CLK_CTRL 0x001b
+#define regSDMA0_CLK_CTRL_BASE_IDX 0
+#define regSDMA0_CNTL 0x001c
+#define regSDMA0_CNTL_BASE_IDX 0
+#define regSDMA0_CHICKEN_BITS 0x001d
+#define regSDMA0_CHICKEN_BITS_BASE_IDX 0
+#define regSDMA0_GB_ADDR_CONFIG 0x001e
+#define regSDMA0_GB_ADDR_CONFIG_BASE_IDX 0
+#define regSDMA0_GB_ADDR_CONFIG_READ 0x001f
+#define regSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX 0
+#define regSDMA0_RB_RPTR_FETCH_HI 0x0020
+#define regSDMA0_RB_RPTR_FETCH_HI_BASE_IDX 0
+#define regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0021
+#define regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0
+#define regSDMA0_RB_RPTR_FETCH 0x0022
+#define regSDMA0_RB_RPTR_FETCH_BASE_IDX 0
+#define regSDMA0_IB_OFFSET_FETCH 0x0023
+#define regSDMA0_IB_OFFSET_FETCH_BASE_IDX 0
+#define regSDMA0_PROGRAM 0x0024
+#define regSDMA0_PROGRAM_BASE_IDX 0
+#define regSDMA0_STATUS_REG 0x0025
+#define regSDMA0_STATUS_REG_BASE_IDX 0
+#define regSDMA0_STATUS1_REG 0x0026
+#define regSDMA0_STATUS1_REG_BASE_IDX 0
+#define regSDMA0_RD_BURST_CNTL 0x0027
+#define regSDMA0_RD_BURST_CNTL_BASE_IDX 0
+#define regSDMA0_HBM_PAGE_CONFIG 0x0028
+#define regSDMA0_HBM_PAGE_CONFIG_BASE_IDX 0
+#define regSDMA0_UCODE_CHECKSUM 0x0029
+#define regSDMA0_UCODE_CHECKSUM_BASE_IDX 0
+#define regSDMA0_F32_CNTL 0x002a
+#define regSDMA0_F32_CNTL_BASE_IDX 0
+#define regSDMA0_FREEZE 0x002b
+#define regSDMA0_FREEZE_BASE_IDX 0
+#define regSDMA0_PHASE0_QUANTUM 0x002c
+#define regSDMA0_PHASE0_QUANTUM_BASE_IDX 0
+#define regSDMA0_PHASE1_QUANTUM 0x002d
+#define regSDMA0_PHASE1_QUANTUM_BASE_IDX 0
+#define regSDMA_POWER_GATING 0x002e
+#define regSDMA_POWER_GATING_BASE_IDX 0
+#define regSDMA_PGFSM_CONFIG 0x002f
+#define regSDMA_PGFSM_CONFIG_BASE_IDX 0
+#define regSDMA_PGFSM_WRITE 0x0030
+#define regSDMA_PGFSM_WRITE_BASE_IDX 0
+#define regSDMA_PGFSM_READ 0x0031
+#define regSDMA_PGFSM_READ_BASE_IDX 0
+#define regCC_SDMA0_EDC_CONFIG 0x0032
+#define regCC_SDMA0_EDC_CONFIG_BASE_IDX 0
+#define regSDMA0_BA_THRESHOLD 0x0033
+#define regSDMA0_BA_THRESHOLD_BASE_IDX 0
+#define regSDMA0_ID 0x0034
+#define regSDMA0_ID_BASE_IDX 0
+#define regSDMA0_VERSION 0x0035
+#define regSDMA0_VERSION_BASE_IDX 0
+#define regSDMA0_EDC_COUNTER 0x0036
+#define regSDMA0_EDC_COUNTER_BASE_IDX 0
+#define regSDMA0_EDC_COUNTER2 0x0037
+#define regSDMA0_EDC_COUNTER2_BASE_IDX 0
+#define regSDMA0_STATUS2_REG 0x0038
+#define regSDMA0_STATUS2_REG_BASE_IDX 0
+#define regSDMA0_ATOMIC_CNTL 0x0039
+#define regSDMA0_ATOMIC_CNTL_BASE_IDX 0
+#define regSDMA0_ATOMIC_PREOP_LO 0x003a
+#define regSDMA0_ATOMIC_PREOP_LO_BASE_IDX 0
+#define regSDMA0_ATOMIC_PREOP_HI 0x003b
+#define regSDMA0_ATOMIC_PREOP_HI_BASE_IDX 0
+#define regSDMA0_UTCL1_CNTL 0x003c
+#define regSDMA0_UTCL1_CNTL_BASE_IDX 0
+#define regSDMA0_UTCL1_WATERMK 0x003d
+#define regSDMA0_UTCL1_WATERMK_BASE_IDX 0
+#define regSDMA0_UTCL1_RD_STATUS 0x003e
+#define regSDMA0_UTCL1_RD_STATUS_BASE_IDX 0
+#define regSDMA0_UTCL1_WR_STATUS 0x003f
+#define regSDMA0_UTCL1_WR_STATUS_BASE_IDX 0
+#define regSDMA0_UTCL1_INV0 0x0040
+#define regSDMA0_UTCL1_INV0_BASE_IDX 0
+#define regSDMA0_UTCL1_INV1 0x0041
+#define regSDMA0_UTCL1_INV1_BASE_IDX 0
+#define regSDMA0_UTCL1_INV2 0x0042
+#define regSDMA0_UTCL1_INV2_BASE_IDX 0
+#define regSDMA0_UTCL1_RD_XNACK0 0x0043
+#define regSDMA0_UTCL1_RD_XNACK0_BASE_IDX 0
+#define regSDMA0_UTCL1_RD_XNACK1 0x0044
+#define regSDMA0_UTCL1_RD_XNACK1_BASE_IDX 0
+#define regSDMA0_UTCL1_WR_XNACK0 0x0045
+#define regSDMA0_UTCL1_WR_XNACK0_BASE_IDX 0
+#define regSDMA0_UTCL1_WR_XNACK1 0x0046
+#define regSDMA0_UTCL1_WR_XNACK1_BASE_IDX 0
+#define regSDMA0_UTCL1_TIMEOUT 0x0047
+#define regSDMA0_UTCL1_TIMEOUT_BASE_IDX 0
+#define regSDMA0_UTCL1_PAGE 0x0048
+#define regSDMA0_UTCL1_PAGE_BASE_IDX 0
+#define regSDMA0_POWER_CNTL_IDLE 0x0049
+#define regSDMA0_POWER_CNTL_IDLE_BASE_IDX 0
+#define regSDMA0_RELAX_ORDERING_LUT 0x004a
+#define regSDMA0_RELAX_ORDERING_LUT_BASE_IDX 0
+#define regSDMA0_CHICKEN_BITS_2 0x004b
+#define regSDMA0_CHICKEN_BITS_2_BASE_IDX 0
+#define regSDMA0_STATUS3_REG 0x004c
+#define regSDMA0_STATUS3_REG_BASE_IDX 0
+#define regSDMA0_PHYSICAL_ADDR_LO 0x004d
+#define regSDMA0_PHYSICAL_ADDR_LO_BASE_IDX 0
+#define regSDMA0_PHYSICAL_ADDR_HI 0x004e
+#define regSDMA0_PHYSICAL_ADDR_HI_BASE_IDX 0
+#define regSDMA0_PHASE2_QUANTUM 0x004f
+#define regSDMA0_PHASE2_QUANTUM_BASE_IDX 0
+#define regSDMA0_ERROR_LOG 0x0050
+#define regSDMA0_ERROR_LOG_BASE_IDX 0
+#define regSDMA0_PUB_DUMMY_REG0 0x0051
+#define regSDMA0_PUB_DUMMY_REG0_BASE_IDX 0
+#define regSDMA0_PUB_DUMMY_REG1 0x0052
+#define regSDMA0_PUB_DUMMY_REG1_BASE_IDX 0
+#define regSDMA0_PUB_DUMMY_REG2 0x0053
+#define regSDMA0_PUB_DUMMY_REG2_BASE_IDX 0
+#define regSDMA0_PUB_DUMMY_REG3 0x0054
+#define regSDMA0_PUB_DUMMY_REG3_BASE_IDX 0
+#define regSDMA0_F32_COUNTER 0x0055
+#define regSDMA0_F32_COUNTER_BASE_IDX 0
+#define regSDMA0_PERFCNT_PERFCOUNTER0_CFG 0x0057
+#define regSDMA0_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX 0
+#define regSDMA0_PERFCNT_PERFCOUNTER1_CFG 0x0058
+#define regSDMA0_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX 0
+#define regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x0059
+#define regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+#define regSDMA0_PERFCNT_MISC_CNTL 0x005a
+#define regSDMA0_PERFCNT_MISC_CNTL_BASE_IDX 0
+#define regSDMA0_PERFCNT_PERFCOUNTER_LO 0x005b
+#define regSDMA0_PERFCNT_PERFCOUNTER_LO_BASE_IDX 0
+#define regSDMA0_PERFCNT_PERFCOUNTER_HI 0x005c
+#define regSDMA0_PERFCNT_PERFCOUNTER_HI_BASE_IDX 0
+#define regSDMA0_CRD_CNTL 0x005d
+#define regSDMA0_CRD_CNTL_BASE_IDX 0
+#define regSDMA0_ULV_CNTL 0x005f
+#define regSDMA0_ULV_CNTL_BASE_IDX 0
+#define regSDMA0_EA_DBIT_ADDR_DATA 0x0060
+#define regSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX 0
+#define regSDMA0_EA_DBIT_ADDR_INDEX 0x0061
+#define regSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX 0
+#define regSDMA0_STATUS4_REG 0x0063
+#define regSDMA0_STATUS4_REG_BASE_IDX 0
+#define regSDMA0_SCRATCH_RAM_DATA 0x0064
+#define regSDMA0_SCRATCH_RAM_DATA_BASE_IDX 0
+#define regSDMA0_SCRATCH_RAM_ADDR 0x0065
+#define regSDMA0_SCRATCH_RAM_ADDR_BASE_IDX 0
+#define regSDMA0_CE_CTRL 0x0066
+#define regSDMA0_CE_CTRL_BASE_IDX 0
+#define regSDMA0_RAS_STATUS 0x0067
+#define regSDMA0_RAS_STATUS_BASE_IDX 0
+#define regSDMA0_CLK_STATUS 0x0068
+#define regSDMA0_CLK_STATUS_BASE_IDX 0
+#define regSDMA0_GFX_RB_CNTL 0x0080
+#define regSDMA0_GFX_RB_CNTL_BASE_IDX 0
+#define regSDMA0_GFX_RB_BASE 0x0081
+#define regSDMA0_GFX_RB_BASE_BASE_IDX 0
+#define regSDMA0_GFX_RB_BASE_HI 0x0082
+#define regSDMA0_GFX_RB_BASE_HI_BASE_IDX 0
+#define regSDMA0_GFX_RB_RPTR 0x0083
+#define regSDMA0_GFX_RB_RPTR_BASE_IDX 0
+#define regSDMA0_GFX_RB_RPTR_HI 0x0084
+#define regSDMA0_GFX_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA0_GFX_RB_WPTR 0x0085
+#define regSDMA0_GFX_RB_WPTR_BASE_IDX 0
+#define regSDMA0_GFX_RB_WPTR_HI 0x0086
+#define regSDMA0_GFX_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA0_GFX_RB_WPTR_POLL_CNTL 0x0087
+#define regSDMA0_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA0_GFX_RB_RPTR_ADDR_HI 0x0088
+#define regSDMA0_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA0_GFX_RB_RPTR_ADDR_LO 0x0089
+#define regSDMA0_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA0_GFX_IB_CNTL 0x008a
+#define regSDMA0_GFX_IB_CNTL_BASE_IDX 0
+#define regSDMA0_GFX_IB_RPTR 0x008b
+#define regSDMA0_GFX_IB_RPTR_BASE_IDX 0
+#define regSDMA0_GFX_IB_OFFSET 0x008c
+#define regSDMA0_GFX_IB_OFFSET_BASE_IDX 0
+#define regSDMA0_GFX_IB_BASE_LO 0x008d
+#define regSDMA0_GFX_IB_BASE_LO_BASE_IDX 0
+#define regSDMA0_GFX_IB_BASE_HI 0x008e
+#define regSDMA0_GFX_IB_BASE_HI_BASE_IDX 0
+#define regSDMA0_GFX_IB_SIZE 0x008f
+#define regSDMA0_GFX_IB_SIZE_BASE_IDX 0
+#define regSDMA0_GFX_SKIP_CNTL 0x0090
+#define regSDMA0_GFX_SKIP_CNTL_BASE_IDX 0
+#define regSDMA0_GFX_CONTEXT_STATUS 0x0091
+#define regSDMA0_GFX_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA0_GFX_DOORBELL 0x0092
+#define regSDMA0_GFX_DOORBELL_BASE_IDX 0
+#define regSDMA0_GFX_CONTEXT_CNTL 0x0093
+#define regSDMA0_GFX_CONTEXT_CNTL_BASE_IDX 0
+#define regSDMA0_GFX_STATUS 0x00a8
+#define regSDMA0_GFX_STATUS_BASE_IDX 0
+#define regSDMA0_GFX_DOORBELL_LOG 0x00a9
+#define regSDMA0_GFX_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA0_GFX_WATERMARK 0x00aa
+#define regSDMA0_GFX_WATERMARK_BASE_IDX 0
+#define regSDMA0_GFX_DOORBELL_OFFSET 0x00ab
+#define regSDMA0_GFX_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA0_GFX_CSA_ADDR_LO 0x00ac
+#define regSDMA0_GFX_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA0_GFX_CSA_ADDR_HI 0x00ad
+#define regSDMA0_GFX_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA0_GFX_IB_SUB_REMAIN 0x00af
+#define regSDMA0_GFX_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA0_GFX_PREEMPT 0x00b0
+#define regSDMA0_GFX_PREEMPT_BASE_IDX 0
+#define regSDMA0_GFX_DUMMY_REG 0x00b1
+#define regSDMA0_GFX_DUMMY_REG_BASE_IDX 0
+#define regSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2
+#define regSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3
+#define regSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA0_GFX_RB_AQL_CNTL 0x00b4
+#define regSDMA0_GFX_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA0_GFX_MINOR_PTR_UPDATE 0x00b5
+#define regSDMA0_GFX_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA0_GFX_MIDCMD_DATA0 0x00c0
+#define regSDMA0_GFX_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA0_GFX_MIDCMD_DATA1 0x00c1
+#define regSDMA0_GFX_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA0_GFX_MIDCMD_DATA2 0x00c2
+#define regSDMA0_GFX_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA0_GFX_MIDCMD_DATA3 0x00c3
+#define regSDMA0_GFX_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA0_GFX_MIDCMD_DATA4 0x00c4
+#define regSDMA0_GFX_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA0_GFX_MIDCMD_DATA5 0x00c5
+#define regSDMA0_GFX_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA0_GFX_MIDCMD_DATA6 0x00c6
+#define regSDMA0_GFX_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA0_GFX_MIDCMD_DATA7 0x00c7
+#define regSDMA0_GFX_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA0_GFX_MIDCMD_DATA8 0x00c8
+#define regSDMA0_GFX_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA0_GFX_MIDCMD_DATA9 0x00c9
+#define regSDMA0_GFX_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA0_GFX_MIDCMD_DATA10 0x00ca
+#define regSDMA0_GFX_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA0_GFX_MIDCMD_CNTL 0x00cb
+#define regSDMA0_GFX_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA0_PAGE_RB_CNTL 0x00d8
+#define regSDMA0_PAGE_RB_CNTL_BASE_IDX 0
+#define regSDMA0_PAGE_RB_BASE 0x00d9
+#define regSDMA0_PAGE_RB_BASE_BASE_IDX 0
+#define regSDMA0_PAGE_RB_BASE_HI 0x00da
+#define regSDMA0_PAGE_RB_BASE_HI_BASE_IDX 0
+#define regSDMA0_PAGE_RB_RPTR 0x00db
+#define regSDMA0_PAGE_RB_RPTR_BASE_IDX 0
+#define regSDMA0_PAGE_RB_RPTR_HI 0x00dc
+#define regSDMA0_PAGE_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA0_PAGE_RB_WPTR 0x00dd
+#define regSDMA0_PAGE_RB_WPTR_BASE_IDX 0
+#define regSDMA0_PAGE_RB_WPTR_HI 0x00de
+#define regSDMA0_PAGE_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA0_PAGE_RB_WPTR_POLL_CNTL 0x00df
+#define regSDMA0_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA0_PAGE_RB_RPTR_ADDR_HI 0x00e0
+#define regSDMA0_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA0_PAGE_RB_RPTR_ADDR_LO 0x00e1
+#define regSDMA0_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA0_PAGE_IB_CNTL 0x00e2
+#define regSDMA0_PAGE_IB_CNTL_BASE_IDX 0
+#define regSDMA0_PAGE_IB_RPTR 0x00e3
+#define regSDMA0_PAGE_IB_RPTR_BASE_IDX 0
+#define regSDMA0_PAGE_IB_OFFSET 0x00e4
+#define regSDMA0_PAGE_IB_OFFSET_BASE_IDX 0
+#define regSDMA0_PAGE_IB_BASE_LO 0x00e5
+#define regSDMA0_PAGE_IB_BASE_LO_BASE_IDX 0
+#define regSDMA0_PAGE_IB_BASE_HI 0x00e6
+#define regSDMA0_PAGE_IB_BASE_HI_BASE_IDX 0
+#define regSDMA0_PAGE_IB_SIZE 0x00e7
+#define regSDMA0_PAGE_IB_SIZE_BASE_IDX 0
+#define regSDMA0_PAGE_SKIP_CNTL 0x00e8
+#define regSDMA0_PAGE_SKIP_CNTL_BASE_IDX 0
+#define regSDMA0_PAGE_CONTEXT_STATUS 0x00e9
+#define regSDMA0_PAGE_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA0_PAGE_DOORBELL 0x00ea
+#define regSDMA0_PAGE_DOORBELL_BASE_IDX 0
+#define regSDMA0_PAGE_STATUS 0x0100
+#define regSDMA0_PAGE_STATUS_BASE_IDX 0
+#define regSDMA0_PAGE_DOORBELL_LOG 0x0101
+#define regSDMA0_PAGE_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA0_PAGE_WATERMARK 0x0102
+#define regSDMA0_PAGE_WATERMARK_BASE_IDX 0
+#define regSDMA0_PAGE_DOORBELL_OFFSET 0x0103
+#define regSDMA0_PAGE_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA0_PAGE_CSA_ADDR_LO 0x0104
+#define regSDMA0_PAGE_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA0_PAGE_CSA_ADDR_HI 0x0105
+#define regSDMA0_PAGE_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA0_PAGE_IB_SUB_REMAIN 0x0107
+#define regSDMA0_PAGE_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA0_PAGE_PREEMPT 0x0108
+#define regSDMA0_PAGE_PREEMPT_BASE_IDX 0
+#define regSDMA0_PAGE_DUMMY_REG 0x0109
+#define regSDMA0_PAGE_DUMMY_REG_BASE_IDX 0
+#define regSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 0x010a
+#define regSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 0x010b
+#define regSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA0_PAGE_RB_AQL_CNTL 0x010c
+#define regSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA0_PAGE_MINOR_PTR_UPDATE 0x010d
+#define regSDMA0_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA0_PAGE_MIDCMD_DATA0 0x0118
+#define regSDMA0_PAGE_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA0_PAGE_MIDCMD_DATA1 0x0119
+#define regSDMA0_PAGE_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA0_PAGE_MIDCMD_DATA2 0x011a
+#define regSDMA0_PAGE_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA0_PAGE_MIDCMD_DATA3 0x011b
+#define regSDMA0_PAGE_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA0_PAGE_MIDCMD_DATA4 0x011c
+#define regSDMA0_PAGE_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA0_PAGE_MIDCMD_DATA5 0x011d
+#define regSDMA0_PAGE_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA0_PAGE_MIDCMD_DATA6 0x011e
+#define regSDMA0_PAGE_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA0_PAGE_MIDCMD_DATA7 0x011f
+#define regSDMA0_PAGE_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA0_PAGE_MIDCMD_DATA8 0x0120
+#define regSDMA0_PAGE_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA0_PAGE_MIDCMD_DATA9 0x0121
+#define regSDMA0_PAGE_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA0_PAGE_MIDCMD_DATA10 0x0122
+#define regSDMA0_PAGE_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA0_PAGE_MIDCMD_CNTL 0x0123
+#define regSDMA0_PAGE_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA0_RLC0_RB_CNTL 0x0130
+#define regSDMA0_RLC0_RB_CNTL_BASE_IDX 0
+#define regSDMA0_RLC0_RB_BASE 0x0131
+#define regSDMA0_RLC0_RB_BASE_BASE_IDX 0
+#define regSDMA0_RLC0_RB_BASE_HI 0x0132
+#define regSDMA0_RLC0_RB_BASE_HI_BASE_IDX 0
+#define regSDMA0_RLC0_RB_RPTR 0x0133
+#define regSDMA0_RLC0_RB_RPTR_BASE_IDX 0
+#define regSDMA0_RLC0_RB_RPTR_HI 0x0134
+#define regSDMA0_RLC0_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA0_RLC0_RB_WPTR 0x0135
+#define regSDMA0_RLC0_RB_WPTR_BASE_IDX 0
+#define regSDMA0_RLC0_RB_WPTR_HI 0x0136
+#define regSDMA0_RLC0_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x0137
+#define regSDMA0_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA0_RLC0_RB_RPTR_ADDR_HI 0x0138
+#define regSDMA0_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA0_RLC0_RB_RPTR_ADDR_LO 0x0139
+#define regSDMA0_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA0_RLC0_IB_CNTL 0x013a
+#define regSDMA0_RLC0_IB_CNTL_BASE_IDX 0
+#define regSDMA0_RLC0_IB_RPTR 0x013b
+#define regSDMA0_RLC0_IB_RPTR_BASE_IDX 0
+#define regSDMA0_RLC0_IB_OFFSET 0x013c
+#define regSDMA0_RLC0_IB_OFFSET_BASE_IDX 0
+#define regSDMA0_RLC0_IB_BASE_LO 0x013d
+#define regSDMA0_RLC0_IB_BASE_LO_BASE_IDX 0
+#define regSDMA0_RLC0_IB_BASE_HI 0x013e
+#define regSDMA0_RLC0_IB_BASE_HI_BASE_IDX 0
+#define regSDMA0_RLC0_IB_SIZE 0x013f
+#define regSDMA0_RLC0_IB_SIZE_BASE_IDX 0
+#define regSDMA0_RLC0_SKIP_CNTL 0x0140
+#define regSDMA0_RLC0_SKIP_CNTL_BASE_IDX 0
+#define regSDMA0_RLC0_CONTEXT_STATUS 0x0141
+#define regSDMA0_RLC0_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA0_RLC0_DOORBELL 0x0142
+#define regSDMA0_RLC0_DOORBELL_BASE_IDX 0
+#define regSDMA0_RLC0_STATUS 0x0158
+#define regSDMA0_RLC0_STATUS_BASE_IDX 0
+#define regSDMA0_RLC0_DOORBELL_LOG 0x0159
+#define regSDMA0_RLC0_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA0_RLC0_WATERMARK 0x015a
+#define regSDMA0_RLC0_WATERMARK_BASE_IDX 0
+#define regSDMA0_RLC0_DOORBELL_OFFSET 0x015b
+#define regSDMA0_RLC0_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA0_RLC0_CSA_ADDR_LO 0x015c
+#define regSDMA0_RLC0_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA0_RLC0_CSA_ADDR_HI 0x015d
+#define regSDMA0_RLC0_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA0_RLC0_IB_SUB_REMAIN 0x015f
+#define regSDMA0_RLC0_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA0_RLC0_PREEMPT 0x0160
+#define regSDMA0_RLC0_PREEMPT_BASE_IDX 0
+#define regSDMA0_RLC0_DUMMY_REG 0x0161
+#define regSDMA0_RLC0_DUMMY_REG_BASE_IDX 0
+#define regSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x0162
+#define regSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x0163
+#define regSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA0_RLC0_RB_AQL_CNTL 0x0164
+#define regSDMA0_RLC0_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA0_RLC0_MINOR_PTR_UPDATE 0x0165
+#define regSDMA0_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA0_RLC0_MIDCMD_DATA0 0x0170
+#define regSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA0_RLC0_MIDCMD_DATA1 0x0171
+#define regSDMA0_RLC0_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA0_RLC0_MIDCMD_DATA2 0x0172
+#define regSDMA0_RLC0_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA0_RLC0_MIDCMD_DATA3 0x0173
+#define regSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA0_RLC0_MIDCMD_DATA4 0x0174
+#define regSDMA0_RLC0_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA0_RLC0_MIDCMD_DATA5 0x0175
+#define regSDMA0_RLC0_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA0_RLC0_MIDCMD_DATA6 0x0176
+#define regSDMA0_RLC0_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA0_RLC0_MIDCMD_DATA7 0x0177
+#define regSDMA0_RLC0_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA0_RLC0_MIDCMD_DATA8 0x0178
+#define regSDMA0_RLC0_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA0_RLC0_MIDCMD_DATA9 0x0179
+#define regSDMA0_RLC0_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA0_RLC0_MIDCMD_DATA10 0x017a
+#define regSDMA0_RLC0_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA0_RLC0_MIDCMD_CNTL 0x017b
+#define regSDMA0_RLC0_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA0_RLC1_RB_CNTL 0x0188
+#define regSDMA0_RLC1_RB_CNTL_BASE_IDX 0
+#define regSDMA0_RLC1_RB_BASE 0x0189
+#define regSDMA0_RLC1_RB_BASE_BASE_IDX 0
+#define regSDMA0_RLC1_RB_BASE_HI 0x018a
+#define regSDMA0_RLC1_RB_BASE_HI_BASE_IDX 0
+#define regSDMA0_RLC1_RB_RPTR 0x018b
+#define regSDMA0_RLC1_RB_RPTR_BASE_IDX 0
+#define regSDMA0_RLC1_RB_RPTR_HI 0x018c
+#define regSDMA0_RLC1_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA0_RLC1_RB_WPTR 0x018d
+#define regSDMA0_RLC1_RB_WPTR_BASE_IDX 0
+#define regSDMA0_RLC1_RB_WPTR_HI 0x018e
+#define regSDMA0_RLC1_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x018f
+#define regSDMA0_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA0_RLC1_RB_RPTR_ADDR_HI 0x0190
+#define regSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA0_RLC1_RB_RPTR_ADDR_LO 0x0191
+#define regSDMA0_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA0_RLC1_IB_CNTL 0x0192
+#define regSDMA0_RLC1_IB_CNTL_BASE_IDX 0
+#define regSDMA0_RLC1_IB_RPTR 0x0193
+#define regSDMA0_RLC1_IB_RPTR_BASE_IDX 0
+#define regSDMA0_RLC1_IB_OFFSET 0x0194
+#define regSDMA0_RLC1_IB_OFFSET_BASE_IDX 0
+#define regSDMA0_RLC1_IB_BASE_LO 0x0195
+#define regSDMA0_RLC1_IB_BASE_LO_BASE_IDX 0
+#define regSDMA0_RLC1_IB_BASE_HI 0x0196
+#define regSDMA0_RLC1_IB_BASE_HI_BASE_IDX 0
+#define regSDMA0_RLC1_IB_SIZE 0x0197
+#define regSDMA0_RLC1_IB_SIZE_BASE_IDX 0
+#define regSDMA0_RLC1_SKIP_CNTL 0x0198
+#define regSDMA0_RLC1_SKIP_CNTL_BASE_IDX 0
+#define regSDMA0_RLC1_CONTEXT_STATUS 0x0199
+#define regSDMA0_RLC1_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA0_RLC1_DOORBELL 0x019a
+#define regSDMA0_RLC1_DOORBELL_BASE_IDX 0
+#define regSDMA0_RLC1_STATUS 0x01b0
+#define regSDMA0_RLC1_STATUS_BASE_IDX 0
+#define regSDMA0_RLC1_DOORBELL_LOG 0x01b1
+#define regSDMA0_RLC1_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA0_RLC1_WATERMARK 0x01b2
+#define regSDMA0_RLC1_WATERMARK_BASE_IDX 0
+#define regSDMA0_RLC1_DOORBELL_OFFSET 0x01b3
+#define regSDMA0_RLC1_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA0_RLC1_CSA_ADDR_LO 0x01b4
+#define regSDMA0_RLC1_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA0_RLC1_CSA_ADDR_HI 0x01b5
+#define regSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA0_RLC1_IB_SUB_REMAIN 0x01b7
+#define regSDMA0_RLC1_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA0_RLC1_PREEMPT 0x01b8
+#define regSDMA0_RLC1_PREEMPT_BASE_IDX 0
+#define regSDMA0_RLC1_DUMMY_REG 0x01b9
+#define regSDMA0_RLC1_DUMMY_REG_BASE_IDX 0
+#define regSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x01ba
+#define regSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x01bb
+#define regSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA0_RLC1_RB_AQL_CNTL 0x01bc
+#define regSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA0_RLC1_MINOR_PTR_UPDATE 0x01bd
+#define regSDMA0_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA0_RLC1_MIDCMD_DATA0 0x01c8
+#define regSDMA0_RLC1_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA0_RLC1_MIDCMD_DATA1 0x01c9
+#define regSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA0_RLC1_MIDCMD_DATA2 0x01ca
+#define regSDMA0_RLC1_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA0_RLC1_MIDCMD_DATA3 0x01cb
+#define regSDMA0_RLC1_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA0_RLC1_MIDCMD_DATA4 0x01cc
+#define regSDMA0_RLC1_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA0_RLC1_MIDCMD_DATA5 0x01cd
+#define regSDMA0_RLC1_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA0_RLC1_MIDCMD_DATA6 0x01ce
+#define regSDMA0_RLC1_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA0_RLC1_MIDCMD_DATA7 0x01cf
+#define regSDMA0_RLC1_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA0_RLC1_MIDCMD_DATA8 0x01d0
+#define regSDMA0_RLC1_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA0_RLC1_MIDCMD_DATA9 0x01d1
+#define regSDMA0_RLC1_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA0_RLC1_MIDCMD_DATA10 0x01d2
+#define regSDMA0_RLC1_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA0_RLC1_MIDCMD_CNTL 0x01d3
+#define regSDMA0_RLC1_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA0_RLC2_RB_CNTL 0x01e0
+#define regSDMA0_RLC2_RB_CNTL_BASE_IDX 0
+#define regSDMA0_RLC2_RB_BASE 0x01e1
+#define regSDMA0_RLC2_RB_BASE_BASE_IDX 0
+#define regSDMA0_RLC2_RB_BASE_HI 0x01e2
+#define regSDMA0_RLC2_RB_BASE_HI_BASE_IDX 0
+#define regSDMA0_RLC2_RB_RPTR 0x01e3
+#define regSDMA0_RLC2_RB_RPTR_BASE_IDX 0
+#define regSDMA0_RLC2_RB_RPTR_HI 0x01e4
+#define regSDMA0_RLC2_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA0_RLC2_RB_WPTR 0x01e5
+#define regSDMA0_RLC2_RB_WPTR_BASE_IDX 0
+#define regSDMA0_RLC2_RB_WPTR_HI 0x01e6
+#define regSDMA0_RLC2_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA0_RLC2_RB_WPTR_POLL_CNTL 0x01e7
+#define regSDMA0_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA0_RLC2_RB_RPTR_ADDR_HI 0x01e8
+#define regSDMA0_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA0_RLC2_RB_RPTR_ADDR_LO 0x01e9
+#define regSDMA0_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA0_RLC2_IB_CNTL 0x01ea
+#define regSDMA0_RLC2_IB_CNTL_BASE_IDX 0
+#define regSDMA0_RLC2_IB_RPTR 0x01eb
+#define regSDMA0_RLC2_IB_RPTR_BASE_IDX 0
+#define regSDMA0_RLC2_IB_OFFSET 0x01ec
+#define regSDMA0_RLC2_IB_OFFSET_BASE_IDX 0
+#define regSDMA0_RLC2_IB_BASE_LO 0x01ed
+#define regSDMA0_RLC2_IB_BASE_LO_BASE_IDX 0
+#define regSDMA0_RLC2_IB_BASE_HI 0x01ee
+#define regSDMA0_RLC2_IB_BASE_HI_BASE_IDX 0
+#define regSDMA0_RLC2_IB_SIZE 0x01ef
+#define regSDMA0_RLC2_IB_SIZE_BASE_IDX 0
+#define regSDMA0_RLC2_SKIP_CNTL 0x01f0
+#define regSDMA0_RLC2_SKIP_CNTL_BASE_IDX 0
+#define regSDMA0_RLC2_CONTEXT_STATUS 0x01f1
+#define regSDMA0_RLC2_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA0_RLC2_DOORBELL 0x01f2
+#define regSDMA0_RLC2_DOORBELL_BASE_IDX 0
+#define regSDMA0_RLC2_STATUS 0x0208
+#define regSDMA0_RLC2_STATUS_BASE_IDX 0
+#define regSDMA0_RLC2_DOORBELL_LOG 0x0209
+#define regSDMA0_RLC2_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA0_RLC2_WATERMARK 0x020a
+#define regSDMA0_RLC2_WATERMARK_BASE_IDX 0
+#define regSDMA0_RLC2_DOORBELL_OFFSET 0x020b
+#define regSDMA0_RLC2_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA0_RLC2_CSA_ADDR_LO 0x020c
+#define regSDMA0_RLC2_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA0_RLC2_CSA_ADDR_HI 0x020d
+#define regSDMA0_RLC2_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA0_RLC2_IB_SUB_REMAIN 0x020f
+#define regSDMA0_RLC2_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA0_RLC2_PREEMPT 0x0210
+#define regSDMA0_RLC2_PREEMPT_BASE_IDX 0
+#define regSDMA0_RLC2_DUMMY_REG 0x0211
+#define regSDMA0_RLC2_DUMMY_REG_BASE_IDX 0
+#define regSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI 0x0212
+#define regSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO 0x0213
+#define regSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA0_RLC2_RB_AQL_CNTL 0x0214
+#define regSDMA0_RLC2_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA0_RLC2_MINOR_PTR_UPDATE 0x0215
+#define regSDMA0_RLC2_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA0_RLC2_MIDCMD_DATA0 0x0220
+#define regSDMA0_RLC2_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA0_RLC2_MIDCMD_DATA1 0x0221
+#define regSDMA0_RLC2_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA0_RLC2_MIDCMD_DATA2 0x0222
+#define regSDMA0_RLC2_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA0_RLC2_MIDCMD_DATA3 0x0223
+#define regSDMA0_RLC2_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA0_RLC2_MIDCMD_DATA4 0x0224
+#define regSDMA0_RLC2_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA0_RLC2_MIDCMD_DATA5 0x0225
+#define regSDMA0_RLC2_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA0_RLC2_MIDCMD_DATA6 0x0226
+#define regSDMA0_RLC2_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA0_RLC2_MIDCMD_DATA7 0x0227
+#define regSDMA0_RLC2_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA0_RLC2_MIDCMD_DATA8 0x0228
+#define regSDMA0_RLC2_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA0_RLC2_MIDCMD_DATA9 0x0229
+#define regSDMA0_RLC2_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA0_RLC2_MIDCMD_DATA10 0x022a
+#define regSDMA0_RLC2_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA0_RLC2_MIDCMD_CNTL 0x022b
+#define regSDMA0_RLC2_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA0_RLC3_RB_CNTL 0x0238
+#define regSDMA0_RLC3_RB_CNTL_BASE_IDX 0
+#define regSDMA0_RLC3_RB_BASE 0x0239
+#define regSDMA0_RLC3_RB_BASE_BASE_IDX 0
+#define regSDMA0_RLC3_RB_BASE_HI 0x023a
+#define regSDMA0_RLC3_RB_BASE_HI_BASE_IDX 0
+#define regSDMA0_RLC3_RB_RPTR 0x023b
+#define regSDMA0_RLC3_RB_RPTR_BASE_IDX 0
+#define regSDMA0_RLC3_RB_RPTR_HI 0x023c
+#define regSDMA0_RLC3_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA0_RLC3_RB_WPTR 0x023d
+#define regSDMA0_RLC3_RB_WPTR_BASE_IDX 0
+#define regSDMA0_RLC3_RB_WPTR_HI 0x023e
+#define regSDMA0_RLC3_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA0_RLC3_RB_WPTR_POLL_CNTL 0x023f
+#define regSDMA0_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA0_RLC3_RB_RPTR_ADDR_HI 0x0240
+#define regSDMA0_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA0_RLC3_RB_RPTR_ADDR_LO 0x0241
+#define regSDMA0_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA0_RLC3_IB_CNTL 0x0242
+#define regSDMA0_RLC3_IB_CNTL_BASE_IDX 0
+#define regSDMA0_RLC3_IB_RPTR 0x0243
+#define regSDMA0_RLC3_IB_RPTR_BASE_IDX 0
+#define regSDMA0_RLC3_IB_OFFSET 0x0244
+#define regSDMA0_RLC3_IB_OFFSET_BASE_IDX 0
+#define regSDMA0_RLC3_IB_BASE_LO 0x0245
+#define regSDMA0_RLC3_IB_BASE_LO_BASE_IDX 0
+#define regSDMA0_RLC3_IB_BASE_HI 0x0246
+#define regSDMA0_RLC3_IB_BASE_HI_BASE_IDX 0
+#define regSDMA0_RLC3_IB_SIZE 0x0247
+#define regSDMA0_RLC3_IB_SIZE_BASE_IDX 0
+#define regSDMA0_RLC3_SKIP_CNTL 0x0248
+#define regSDMA0_RLC3_SKIP_CNTL_BASE_IDX 0
+#define regSDMA0_RLC3_CONTEXT_STATUS 0x0249
+#define regSDMA0_RLC3_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA0_RLC3_DOORBELL 0x024a
+#define regSDMA0_RLC3_DOORBELL_BASE_IDX 0
+#define regSDMA0_RLC3_STATUS 0x0260
+#define regSDMA0_RLC3_STATUS_BASE_IDX 0
+#define regSDMA0_RLC3_DOORBELL_LOG 0x0261
+#define regSDMA0_RLC3_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA0_RLC3_WATERMARK 0x0262
+#define regSDMA0_RLC3_WATERMARK_BASE_IDX 0
+#define regSDMA0_RLC3_DOORBELL_OFFSET 0x0263
+#define regSDMA0_RLC3_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA0_RLC3_CSA_ADDR_LO 0x0264
+#define regSDMA0_RLC3_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA0_RLC3_CSA_ADDR_HI 0x0265
+#define regSDMA0_RLC3_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA0_RLC3_IB_SUB_REMAIN 0x0267
+#define regSDMA0_RLC3_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA0_RLC3_PREEMPT 0x0268
+#define regSDMA0_RLC3_PREEMPT_BASE_IDX 0
+#define regSDMA0_RLC3_DUMMY_REG 0x0269
+#define regSDMA0_RLC3_DUMMY_REG_BASE_IDX 0
+#define regSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI 0x026a
+#define regSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO 0x026b
+#define regSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA0_RLC3_RB_AQL_CNTL 0x026c
+#define regSDMA0_RLC3_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA0_RLC3_MINOR_PTR_UPDATE 0x026d
+#define regSDMA0_RLC3_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA0_RLC3_MIDCMD_DATA0 0x0278
+#define regSDMA0_RLC3_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA0_RLC3_MIDCMD_DATA1 0x0279
+#define regSDMA0_RLC3_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA0_RLC3_MIDCMD_DATA2 0x027a
+#define regSDMA0_RLC3_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA0_RLC3_MIDCMD_DATA3 0x027b
+#define regSDMA0_RLC3_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA0_RLC3_MIDCMD_DATA4 0x027c
+#define regSDMA0_RLC3_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA0_RLC3_MIDCMD_DATA5 0x027d
+#define regSDMA0_RLC3_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA0_RLC3_MIDCMD_DATA6 0x027e
+#define regSDMA0_RLC3_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA0_RLC3_MIDCMD_DATA7 0x027f
+#define regSDMA0_RLC3_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA0_RLC3_MIDCMD_DATA8 0x0280
+#define regSDMA0_RLC3_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA0_RLC3_MIDCMD_DATA9 0x0281
+#define regSDMA0_RLC3_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA0_RLC3_MIDCMD_DATA10 0x0282
+#define regSDMA0_RLC3_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA0_RLC3_MIDCMD_CNTL 0x0283
+#define regSDMA0_RLC3_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA0_RLC4_RB_CNTL 0x0290
+#define regSDMA0_RLC4_RB_CNTL_BASE_IDX 0
+#define regSDMA0_RLC4_RB_BASE 0x0291
+#define regSDMA0_RLC4_RB_BASE_BASE_IDX 0
+#define regSDMA0_RLC4_RB_BASE_HI 0x0292
+#define regSDMA0_RLC4_RB_BASE_HI_BASE_IDX 0
+#define regSDMA0_RLC4_RB_RPTR 0x0293
+#define regSDMA0_RLC4_RB_RPTR_BASE_IDX 0
+#define regSDMA0_RLC4_RB_RPTR_HI 0x0294
+#define regSDMA0_RLC4_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA0_RLC4_RB_WPTR 0x0295
+#define regSDMA0_RLC4_RB_WPTR_BASE_IDX 0
+#define regSDMA0_RLC4_RB_WPTR_HI 0x0296
+#define regSDMA0_RLC4_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA0_RLC4_RB_WPTR_POLL_CNTL 0x0297
+#define regSDMA0_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA0_RLC4_RB_RPTR_ADDR_HI 0x0298
+#define regSDMA0_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA0_RLC4_RB_RPTR_ADDR_LO 0x0299
+#define regSDMA0_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA0_RLC4_IB_CNTL 0x029a
+#define regSDMA0_RLC4_IB_CNTL_BASE_IDX 0
+#define regSDMA0_RLC4_IB_RPTR 0x029b
+#define regSDMA0_RLC4_IB_RPTR_BASE_IDX 0
+#define regSDMA0_RLC4_IB_OFFSET 0x029c
+#define regSDMA0_RLC4_IB_OFFSET_BASE_IDX 0
+#define regSDMA0_RLC4_IB_BASE_LO 0x029d
+#define regSDMA0_RLC4_IB_BASE_LO_BASE_IDX 0
+#define regSDMA0_RLC4_IB_BASE_HI 0x029e
+#define regSDMA0_RLC4_IB_BASE_HI_BASE_IDX 0
+#define regSDMA0_RLC4_IB_SIZE 0x029f
+#define regSDMA0_RLC4_IB_SIZE_BASE_IDX 0
+#define regSDMA0_RLC4_SKIP_CNTL 0x02a0
+#define regSDMA0_RLC4_SKIP_CNTL_BASE_IDX 0
+#define regSDMA0_RLC4_CONTEXT_STATUS 0x02a1
+#define regSDMA0_RLC4_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA0_RLC4_DOORBELL 0x02a2
+#define regSDMA0_RLC4_DOORBELL_BASE_IDX 0
+#define regSDMA0_RLC4_STATUS 0x02b8
+#define regSDMA0_RLC4_STATUS_BASE_IDX 0
+#define regSDMA0_RLC4_DOORBELL_LOG 0x02b9
+#define regSDMA0_RLC4_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA0_RLC4_WATERMARK 0x02ba
+#define regSDMA0_RLC4_WATERMARK_BASE_IDX 0
+#define regSDMA0_RLC4_DOORBELL_OFFSET 0x02bb
+#define regSDMA0_RLC4_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA0_RLC4_CSA_ADDR_LO 0x02bc
+#define regSDMA0_RLC4_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA0_RLC4_CSA_ADDR_HI 0x02bd
+#define regSDMA0_RLC4_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA0_RLC4_IB_SUB_REMAIN 0x02bf
+#define regSDMA0_RLC4_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA0_RLC4_PREEMPT 0x02c0
+#define regSDMA0_RLC4_PREEMPT_BASE_IDX 0
+#define regSDMA0_RLC4_DUMMY_REG 0x02c1
+#define regSDMA0_RLC4_DUMMY_REG_BASE_IDX 0
+#define regSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI 0x02c2
+#define regSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO 0x02c3
+#define regSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA0_RLC4_RB_AQL_CNTL 0x02c4
+#define regSDMA0_RLC4_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA0_RLC4_MINOR_PTR_UPDATE 0x02c5
+#define regSDMA0_RLC4_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA0_RLC4_MIDCMD_DATA0 0x02d0
+#define regSDMA0_RLC4_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA0_RLC4_MIDCMD_DATA1 0x02d1
+#define regSDMA0_RLC4_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA0_RLC4_MIDCMD_DATA2 0x02d2
+#define regSDMA0_RLC4_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA0_RLC4_MIDCMD_DATA3 0x02d3
+#define regSDMA0_RLC4_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA0_RLC4_MIDCMD_DATA4 0x02d4
+#define regSDMA0_RLC4_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA0_RLC4_MIDCMD_DATA5 0x02d5
+#define regSDMA0_RLC4_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA0_RLC4_MIDCMD_DATA6 0x02d6
+#define regSDMA0_RLC4_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA0_RLC4_MIDCMD_DATA7 0x02d7
+#define regSDMA0_RLC4_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA0_RLC4_MIDCMD_DATA8 0x02d8
+#define regSDMA0_RLC4_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA0_RLC4_MIDCMD_DATA9 0x02d9
+#define regSDMA0_RLC4_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA0_RLC4_MIDCMD_DATA10 0x02da
+#define regSDMA0_RLC4_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA0_RLC4_MIDCMD_CNTL 0x02db
+#define regSDMA0_RLC4_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA0_RLC5_RB_CNTL 0x02e8
+#define regSDMA0_RLC5_RB_CNTL_BASE_IDX 0
+#define regSDMA0_RLC5_RB_BASE 0x02e9
+#define regSDMA0_RLC5_RB_BASE_BASE_IDX 0
+#define regSDMA0_RLC5_RB_BASE_HI 0x02ea
+#define regSDMA0_RLC5_RB_BASE_HI_BASE_IDX 0
+#define regSDMA0_RLC5_RB_RPTR 0x02eb
+#define regSDMA0_RLC5_RB_RPTR_BASE_IDX 0
+#define regSDMA0_RLC5_RB_RPTR_HI 0x02ec
+#define regSDMA0_RLC5_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA0_RLC5_RB_WPTR 0x02ed
+#define regSDMA0_RLC5_RB_WPTR_BASE_IDX 0
+#define regSDMA0_RLC5_RB_WPTR_HI 0x02ee
+#define regSDMA0_RLC5_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA0_RLC5_RB_WPTR_POLL_CNTL 0x02ef
+#define regSDMA0_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA0_RLC5_RB_RPTR_ADDR_HI 0x02f0
+#define regSDMA0_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA0_RLC5_RB_RPTR_ADDR_LO 0x02f1
+#define regSDMA0_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA0_RLC5_IB_CNTL 0x02f2
+#define regSDMA0_RLC5_IB_CNTL_BASE_IDX 0
+#define regSDMA0_RLC5_IB_RPTR 0x02f3
+#define regSDMA0_RLC5_IB_RPTR_BASE_IDX 0
+#define regSDMA0_RLC5_IB_OFFSET 0x02f4
+#define regSDMA0_RLC5_IB_OFFSET_BASE_IDX 0
+#define regSDMA0_RLC5_IB_BASE_LO 0x02f5
+#define regSDMA0_RLC5_IB_BASE_LO_BASE_IDX 0
+#define regSDMA0_RLC5_IB_BASE_HI 0x02f6
+#define regSDMA0_RLC5_IB_BASE_HI_BASE_IDX 0
+#define regSDMA0_RLC5_IB_SIZE 0x02f7
+#define regSDMA0_RLC5_IB_SIZE_BASE_IDX 0
+#define regSDMA0_RLC5_SKIP_CNTL 0x02f8
+#define regSDMA0_RLC5_SKIP_CNTL_BASE_IDX 0
+#define regSDMA0_RLC5_CONTEXT_STATUS 0x02f9
+#define regSDMA0_RLC5_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA0_RLC5_DOORBELL 0x02fa
+#define regSDMA0_RLC5_DOORBELL_BASE_IDX 0
+#define regSDMA0_RLC5_STATUS 0x0310
+#define regSDMA0_RLC5_STATUS_BASE_IDX 0
+#define regSDMA0_RLC5_DOORBELL_LOG 0x0311
+#define regSDMA0_RLC5_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA0_RLC5_WATERMARK 0x0312
+#define regSDMA0_RLC5_WATERMARK_BASE_IDX 0
+#define regSDMA0_RLC5_DOORBELL_OFFSET 0x0313
+#define regSDMA0_RLC5_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA0_RLC5_CSA_ADDR_LO 0x0314
+#define regSDMA0_RLC5_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA0_RLC5_CSA_ADDR_HI 0x0315
+#define regSDMA0_RLC5_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA0_RLC5_IB_SUB_REMAIN 0x0317
+#define regSDMA0_RLC5_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA0_RLC5_PREEMPT 0x0318
+#define regSDMA0_RLC5_PREEMPT_BASE_IDX 0
+#define regSDMA0_RLC5_DUMMY_REG 0x0319
+#define regSDMA0_RLC5_DUMMY_REG_BASE_IDX 0
+#define regSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI 0x031a
+#define regSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO 0x031b
+#define regSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA0_RLC5_RB_AQL_CNTL 0x031c
+#define regSDMA0_RLC5_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA0_RLC5_MINOR_PTR_UPDATE 0x031d
+#define regSDMA0_RLC5_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA0_RLC5_MIDCMD_DATA0 0x0328
+#define regSDMA0_RLC5_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA0_RLC5_MIDCMD_DATA1 0x0329
+#define regSDMA0_RLC5_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA0_RLC5_MIDCMD_DATA2 0x032a
+#define regSDMA0_RLC5_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA0_RLC5_MIDCMD_DATA3 0x032b
+#define regSDMA0_RLC5_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA0_RLC5_MIDCMD_DATA4 0x032c
+#define regSDMA0_RLC5_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA0_RLC5_MIDCMD_DATA5 0x032d
+#define regSDMA0_RLC5_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA0_RLC5_MIDCMD_DATA6 0x032e
+#define regSDMA0_RLC5_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA0_RLC5_MIDCMD_DATA7 0x032f
+#define regSDMA0_RLC5_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA0_RLC5_MIDCMD_DATA8 0x0330
+#define regSDMA0_RLC5_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA0_RLC5_MIDCMD_DATA9 0x0331
+#define regSDMA0_RLC5_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA0_RLC5_MIDCMD_DATA10 0x0332
+#define regSDMA0_RLC5_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA0_RLC5_MIDCMD_CNTL 0x0333
+#define regSDMA0_RLC5_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA0_RLC6_RB_CNTL 0x0340
+#define regSDMA0_RLC6_RB_CNTL_BASE_IDX 0
+#define regSDMA0_RLC6_RB_BASE 0x0341
+#define regSDMA0_RLC6_RB_BASE_BASE_IDX 0
+#define regSDMA0_RLC6_RB_BASE_HI 0x0342
+#define regSDMA0_RLC6_RB_BASE_HI_BASE_IDX 0
+#define regSDMA0_RLC6_RB_RPTR 0x0343
+#define regSDMA0_RLC6_RB_RPTR_BASE_IDX 0
+#define regSDMA0_RLC6_RB_RPTR_HI 0x0344
+#define regSDMA0_RLC6_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA0_RLC6_RB_WPTR 0x0345
+#define regSDMA0_RLC6_RB_WPTR_BASE_IDX 0
+#define regSDMA0_RLC6_RB_WPTR_HI 0x0346
+#define regSDMA0_RLC6_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA0_RLC6_RB_WPTR_POLL_CNTL 0x0347
+#define regSDMA0_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA0_RLC6_RB_RPTR_ADDR_HI 0x0348
+#define regSDMA0_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA0_RLC6_RB_RPTR_ADDR_LO 0x0349
+#define regSDMA0_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA0_RLC6_IB_CNTL 0x034a
+#define regSDMA0_RLC6_IB_CNTL_BASE_IDX 0
+#define regSDMA0_RLC6_IB_RPTR 0x034b
+#define regSDMA0_RLC6_IB_RPTR_BASE_IDX 0
+#define regSDMA0_RLC6_IB_OFFSET 0x034c
+#define regSDMA0_RLC6_IB_OFFSET_BASE_IDX 0
+#define regSDMA0_RLC6_IB_BASE_LO 0x034d
+#define regSDMA0_RLC6_IB_BASE_LO_BASE_IDX 0
+#define regSDMA0_RLC6_IB_BASE_HI 0x034e
+#define regSDMA0_RLC6_IB_BASE_HI_BASE_IDX 0
+#define regSDMA0_RLC6_IB_SIZE 0x034f
+#define regSDMA0_RLC6_IB_SIZE_BASE_IDX 0
+#define regSDMA0_RLC6_SKIP_CNTL 0x0350
+#define regSDMA0_RLC6_SKIP_CNTL_BASE_IDX 0
+#define regSDMA0_RLC6_CONTEXT_STATUS 0x0351
+#define regSDMA0_RLC6_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA0_RLC6_DOORBELL 0x0352
+#define regSDMA0_RLC6_DOORBELL_BASE_IDX 0
+#define regSDMA0_RLC6_STATUS 0x0368
+#define regSDMA0_RLC6_STATUS_BASE_IDX 0
+#define regSDMA0_RLC6_DOORBELL_LOG 0x0369
+#define regSDMA0_RLC6_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA0_RLC6_WATERMARK 0x036a
+#define regSDMA0_RLC6_WATERMARK_BASE_IDX 0
+#define regSDMA0_RLC6_DOORBELL_OFFSET 0x036b
+#define regSDMA0_RLC6_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA0_RLC6_CSA_ADDR_LO 0x036c
+#define regSDMA0_RLC6_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA0_RLC6_CSA_ADDR_HI 0x036d
+#define regSDMA0_RLC6_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA0_RLC6_IB_SUB_REMAIN 0x036f
+#define regSDMA0_RLC6_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA0_RLC6_PREEMPT 0x0370
+#define regSDMA0_RLC6_PREEMPT_BASE_IDX 0
+#define regSDMA0_RLC6_DUMMY_REG 0x0371
+#define regSDMA0_RLC6_DUMMY_REG_BASE_IDX 0
+#define regSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI 0x0372
+#define regSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO 0x0373
+#define regSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA0_RLC6_RB_AQL_CNTL 0x0374
+#define regSDMA0_RLC6_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA0_RLC6_MINOR_PTR_UPDATE 0x0375
+#define regSDMA0_RLC6_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA0_RLC6_MIDCMD_DATA0 0x0380
+#define regSDMA0_RLC6_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA0_RLC6_MIDCMD_DATA1 0x0381
+#define regSDMA0_RLC6_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA0_RLC6_MIDCMD_DATA2 0x0382
+#define regSDMA0_RLC6_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA0_RLC6_MIDCMD_DATA3 0x0383
+#define regSDMA0_RLC6_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA0_RLC6_MIDCMD_DATA4 0x0384
+#define regSDMA0_RLC6_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA0_RLC6_MIDCMD_DATA5 0x0385
+#define regSDMA0_RLC6_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA0_RLC6_MIDCMD_DATA6 0x0386
+#define regSDMA0_RLC6_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA0_RLC6_MIDCMD_DATA7 0x0387
+#define regSDMA0_RLC6_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA0_RLC6_MIDCMD_DATA8 0x0388
+#define regSDMA0_RLC6_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA0_RLC6_MIDCMD_DATA9 0x0389
+#define regSDMA0_RLC6_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA0_RLC6_MIDCMD_DATA10 0x038a
+#define regSDMA0_RLC6_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA0_RLC6_MIDCMD_CNTL 0x038b
+#define regSDMA0_RLC6_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA0_RLC7_RB_CNTL 0x0398
+#define regSDMA0_RLC7_RB_CNTL_BASE_IDX 0
+#define regSDMA0_RLC7_RB_BASE 0x0399
+#define regSDMA0_RLC7_RB_BASE_BASE_IDX 0
+#define regSDMA0_RLC7_RB_BASE_HI 0x039a
+#define regSDMA0_RLC7_RB_BASE_HI_BASE_IDX 0
+#define regSDMA0_RLC7_RB_RPTR 0x039b
+#define regSDMA0_RLC7_RB_RPTR_BASE_IDX 0
+#define regSDMA0_RLC7_RB_RPTR_HI 0x039c
+#define regSDMA0_RLC7_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA0_RLC7_RB_WPTR 0x039d
+#define regSDMA0_RLC7_RB_WPTR_BASE_IDX 0
+#define regSDMA0_RLC7_RB_WPTR_HI 0x039e
+#define regSDMA0_RLC7_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA0_RLC7_RB_WPTR_POLL_CNTL 0x039f
+#define regSDMA0_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA0_RLC7_RB_RPTR_ADDR_HI 0x03a0
+#define regSDMA0_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA0_RLC7_RB_RPTR_ADDR_LO 0x03a1
+#define regSDMA0_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA0_RLC7_IB_CNTL 0x03a2
+#define regSDMA0_RLC7_IB_CNTL_BASE_IDX 0
+#define regSDMA0_RLC7_IB_RPTR 0x03a3
+#define regSDMA0_RLC7_IB_RPTR_BASE_IDX 0
+#define regSDMA0_RLC7_IB_OFFSET 0x03a4
+#define regSDMA0_RLC7_IB_OFFSET_BASE_IDX 0
+#define regSDMA0_RLC7_IB_BASE_LO 0x03a5
+#define regSDMA0_RLC7_IB_BASE_LO_BASE_IDX 0
+#define regSDMA0_RLC7_IB_BASE_HI 0x03a6
+#define regSDMA0_RLC7_IB_BASE_HI_BASE_IDX 0
+#define regSDMA0_RLC7_IB_SIZE 0x03a7
+#define regSDMA0_RLC7_IB_SIZE_BASE_IDX 0
+#define regSDMA0_RLC7_SKIP_CNTL 0x03a8
+#define regSDMA0_RLC7_SKIP_CNTL_BASE_IDX 0
+#define regSDMA0_RLC7_CONTEXT_STATUS 0x03a9
+#define regSDMA0_RLC7_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA0_RLC7_DOORBELL 0x03aa
+#define regSDMA0_RLC7_DOORBELL_BASE_IDX 0
+#define regSDMA0_RLC7_STATUS 0x03c0
+#define regSDMA0_RLC7_STATUS_BASE_IDX 0
+#define regSDMA0_RLC7_DOORBELL_LOG 0x03c1
+#define regSDMA0_RLC7_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA0_RLC7_WATERMARK 0x03c2
+#define regSDMA0_RLC7_WATERMARK_BASE_IDX 0
+#define regSDMA0_RLC7_DOORBELL_OFFSET 0x03c3
+#define regSDMA0_RLC7_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA0_RLC7_CSA_ADDR_LO 0x03c4
+#define regSDMA0_RLC7_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA0_RLC7_CSA_ADDR_HI 0x03c5
+#define regSDMA0_RLC7_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA0_RLC7_IB_SUB_REMAIN 0x03c7
+#define regSDMA0_RLC7_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA0_RLC7_PREEMPT 0x03c8
+#define regSDMA0_RLC7_PREEMPT_BASE_IDX 0
+#define regSDMA0_RLC7_DUMMY_REG 0x03c9
+#define regSDMA0_RLC7_DUMMY_REG_BASE_IDX 0
+#define regSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI 0x03ca
+#define regSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO 0x03cb
+#define regSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA0_RLC7_RB_AQL_CNTL 0x03cc
+#define regSDMA0_RLC7_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA0_RLC7_MINOR_PTR_UPDATE 0x03cd
+#define regSDMA0_RLC7_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA0_RLC7_MIDCMD_DATA0 0x03d8
+#define regSDMA0_RLC7_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA0_RLC7_MIDCMD_DATA1 0x03d9
+#define regSDMA0_RLC7_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA0_RLC7_MIDCMD_DATA2 0x03da
+#define regSDMA0_RLC7_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA0_RLC7_MIDCMD_DATA3 0x03db
+#define regSDMA0_RLC7_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA0_RLC7_MIDCMD_DATA4 0x03dc
+#define regSDMA0_RLC7_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA0_RLC7_MIDCMD_DATA5 0x03dd
+#define regSDMA0_RLC7_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA0_RLC7_MIDCMD_DATA6 0x03de
+#define regSDMA0_RLC7_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA0_RLC7_MIDCMD_DATA7 0x03df
+#define regSDMA0_RLC7_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA0_RLC7_MIDCMD_DATA8 0x03e0
+#define regSDMA0_RLC7_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA0_RLC7_MIDCMD_DATA9 0x03e1
+#define regSDMA0_RLC7_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA0_RLC7_MIDCMD_DATA10 0x03e2
+#define regSDMA0_RLC7_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA0_RLC7_MIDCMD_CNTL 0x03e3
+#define regSDMA0_RLC7_MIDCMD_CNTL_BASE_IDX 0
+
+
+// addressBlock: sdma0_sdma1dec
+// base address: 0x6180
+#define regSDMA1_UCODE_ADDR 0x0600
+#define regSDMA1_UCODE_ADDR_BASE_IDX 0
+#define regSDMA1_UCODE_DATA 0x0601
+#define regSDMA1_UCODE_DATA_BASE_IDX 0
+#define regSDMA1_VF_ENABLE 0x060a
+#define regSDMA1_VF_ENABLE_BASE_IDX 0
+#define regSDMA1_CONTEXT_GROUP_BOUNDARY 0x0619
+#define regSDMA1_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0
+#define regSDMA1_POWER_CNTL 0x061a
+#define regSDMA1_POWER_CNTL_BASE_IDX 0
+#define regSDMA1_CLK_CTRL 0x061b
+#define regSDMA1_CLK_CTRL_BASE_IDX 0
+#define regSDMA1_CNTL 0x061c
+#define regSDMA1_CNTL_BASE_IDX 0
+#define regSDMA1_CHICKEN_BITS 0x061d
+#define regSDMA1_CHICKEN_BITS_BASE_IDX 0
+#define regSDMA1_GB_ADDR_CONFIG 0x061e
+#define regSDMA1_GB_ADDR_CONFIG_BASE_IDX 0
+#define regSDMA1_GB_ADDR_CONFIG_READ 0x061f
+#define regSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX 0
+#define regSDMA1_RB_RPTR_FETCH_HI 0x0620
+#define regSDMA1_RB_RPTR_FETCH_HI_BASE_IDX 0
+#define regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x0621
+#define regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0
+#define regSDMA1_RB_RPTR_FETCH 0x0622
+#define regSDMA1_RB_RPTR_FETCH_BASE_IDX 0
+#define regSDMA1_IB_OFFSET_FETCH 0x0623
+#define regSDMA1_IB_OFFSET_FETCH_BASE_IDX 0
+#define regSDMA1_PROGRAM 0x0624
+#define regSDMA1_PROGRAM_BASE_IDX 0
+#define regSDMA1_STATUS_REG 0x0625
+#define regSDMA1_STATUS_REG_BASE_IDX 0
+#define regSDMA1_STATUS1_REG 0x0626
+#define regSDMA1_STATUS1_REG_BASE_IDX 0
+#define regSDMA1_RD_BURST_CNTL 0x0627
+#define regSDMA1_RD_BURST_CNTL_BASE_IDX 0
+#define regSDMA1_HBM_PAGE_CONFIG 0x0628
+#define regSDMA1_HBM_PAGE_CONFIG_BASE_IDX 0
+#define regSDMA1_UCODE_CHECKSUM 0x0629
+#define regSDMA1_UCODE_CHECKSUM_BASE_IDX 0
+#define regSDMA1_F32_CNTL 0x062a
+#define regSDMA1_F32_CNTL_BASE_IDX 0
+#define regSDMA1_FREEZE 0x062b
+#define regSDMA1_FREEZE_BASE_IDX 0
+#define regSDMA1_PHASE0_QUANTUM 0x062c
+#define regSDMA1_PHASE0_QUANTUM_BASE_IDX 0
+#define regSDMA1_PHASE1_QUANTUM 0x062d
+#define regSDMA1_PHASE1_QUANTUM_BASE_IDX 0
+#define regCC_SDMA1_EDC_CONFIG 0x0632
+#define regCC_SDMA1_EDC_CONFIG_BASE_IDX 0
+#define regSDMA1_BA_THRESHOLD 0x0633
+#define regSDMA1_BA_THRESHOLD_BASE_IDX 0
+#define regSDMA1_ID 0x0634
+#define regSDMA1_ID_BASE_IDX 0
+#define regSDMA1_VERSION 0x0635
+#define regSDMA1_VERSION_BASE_IDX 0
+#define regSDMA1_EDC_COUNTER 0x0636
+#define regSDMA1_EDC_COUNTER_BASE_IDX 0
+#define regSDMA1_EDC_COUNTER2 0x0637
+#define regSDMA1_EDC_COUNTER2_BASE_IDX 0
+#define regSDMA1_STATUS2_REG 0x0638
+#define regSDMA1_STATUS2_REG_BASE_IDX 0
+#define regSDMA1_ATOMIC_CNTL 0x0639
+#define regSDMA1_ATOMIC_CNTL_BASE_IDX 0
+#define regSDMA1_ATOMIC_PREOP_LO 0x063a
+#define regSDMA1_ATOMIC_PREOP_LO_BASE_IDX 0
+#define regSDMA1_ATOMIC_PREOP_HI 0x063b
+#define regSDMA1_ATOMIC_PREOP_HI_BASE_IDX 0
+#define regSDMA1_UTCL1_CNTL 0x063c
+#define regSDMA1_UTCL1_CNTL_BASE_IDX 0
+#define regSDMA1_UTCL1_WATERMK 0x063d
+#define regSDMA1_UTCL1_WATERMK_BASE_IDX 0
+#define regSDMA1_UTCL1_RD_STATUS 0x063e
+#define regSDMA1_UTCL1_RD_STATUS_BASE_IDX 0
+#define regSDMA1_UTCL1_WR_STATUS 0x063f
+#define regSDMA1_UTCL1_WR_STATUS_BASE_IDX 0
+#define regSDMA1_UTCL1_INV0 0x0640
+#define regSDMA1_UTCL1_INV0_BASE_IDX 0
+#define regSDMA1_UTCL1_INV1 0x0641
+#define regSDMA1_UTCL1_INV1_BASE_IDX 0
+#define regSDMA1_UTCL1_INV2 0x0642
+#define regSDMA1_UTCL1_INV2_BASE_IDX 0
+#define regSDMA1_UTCL1_RD_XNACK0 0x0643
+#define regSDMA1_UTCL1_RD_XNACK0_BASE_IDX 0
+#define regSDMA1_UTCL1_RD_XNACK1 0x0644
+#define regSDMA1_UTCL1_RD_XNACK1_BASE_IDX 0
+#define regSDMA1_UTCL1_WR_XNACK0 0x0645
+#define regSDMA1_UTCL1_WR_XNACK0_BASE_IDX 0
+#define regSDMA1_UTCL1_WR_XNACK1 0x0646
+#define regSDMA1_UTCL1_WR_XNACK1_BASE_IDX 0
+#define regSDMA1_UTCL1_TIMEOUT 0x0647
+#define regSDMA1_UTCL1_TIMEOUT_BASE_IDX 0
+#define regSDMA1_UTCL1_PAGE 0x0648
+#define regSDMA1_UTCL1_PAGE_BASE_IDX 0
+#define regSDMA1_POWER_CNTL_IDLE 0x0649
+#define regSDMA1_POWER_CNTL_IDLE_BASE_IDX 0
+#define regSDMA1_RELAX_ORDERING_LUT 0x064a
+#define regSDMA1_RELAX_ORDERING_LUT_BASE_IDX 0
+#define regSDMA1_CHICKEN_BITS_2 0x064b
+#define regSDMA1_CHICKEN_BITS_2_BASE_IDX 0
+#define regSDMA1_STATUS3_REG 0x064c
+#define regSDMA1_STATUS3_REG_BASE_IDX 0
+#define regSDMA1_PHYSICAL_ADDR_LO 0x064d
+#define regSDMA1_PHYSICAL_ADDR_LO_BASE_IDX 0
+#define regSDMA1_PHYSICAL_ADDR_HI 0x064e
+#define regSDMA1_PHYSICAL_ADDR_HI_BASE_IDX 0
+#define regSDMA1_PHASE2_QUANTUM 0x064f
+#define regSDMA1_PHASE2_QUANTUM_BASE_IDX 0
+#define regSDMA1_ERROR_LOG 0x0650
+#define regSDMA1_ERROR_LOG_BASE_IDX 0
+#define regSDMA1_PUB_DUMMY_REG0 0x0651
+#define regSDMA1_PUB_DUMMY_REG0_BASE_IDX 0
+#define regSDMA1_PUB_DUMMY_REG1 0x0652
+#define regSDMA1_PUB_DUMMY_REG1_BASE_IDX 0
+#define regSDMA1_PUB_DUMMY_REG2 0x0653
+#define regSDMA1_PUB_DUMMY_REG2_BASE_IDX 0
+#define regSDMA1_PUB_DUMMY_REG3 0x0654
+#define regSDMA1_PUB_DUMMY_REG3_BASE_IDX 0
+#define regSDMA1_F32_COUNTER 0x0655
+#define regSDMA1_F32_COUNTER_BASE_IDX 0
+#define regSDMA1_PERFCNT_PERFCOUNTER0_CFG 0x0657
+#define regSDMA1_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX 0
+#define regSDMA1_PERFCNT_PERFCOUNTER1_CFG 0x0658
+#define regSDMA1_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX 0
+#define regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x0659
+#define regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+#define regSDMA1_PERFCNT_MISC_CNTL 0x065a
+#define regSDMA1_PERFCNT_MISC_CNTL_BASE_IDX 0
+#define regSDMA1_PERFCNT_PERFCOUNTER_LO 0x065b
+#define regSDMA1_PERFCNT_PERFCOUNTER_LO_BASE_IDX 0
+#define regSDMA1_PERFCNT_PERFCOUNTER_HI 0x065c
+#define regSDMA1_PERFCNT_PERFCOUNTER_HI_BASE_IDX 0
+#define regSDMA1_CRD_CNTL 0x065d
+#define regSDMA1_CRD_CNTL_BASE_IDX 0
+#define regSDMA1_ULV_CNTL 0x065f
+#define regSDMA1_ULV_CNTL_BASE_IDX 0
+#define regSDMA1_EA_DBIT_ADDR_DATA 0x0660
+#define regSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX 0
+#define regSDMA1_EA_DBIT_ADDR_INDEX 0x0661
+#define regSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX 0
+#define regSDMA1_STATUS4_REG 0x0663
+#define regSDMA1_STATUS4_REG_BASE_IDX 0
+#define regSDMA1_SCRATCH_RAM_DATA 0x0664
+#define regSDMA1_SCRATCH_RAM_DATA_BASE_IDX 0
+#define regSDMA1_SCRATCH_RAM_ADDR 0x0665
+#define regSDMA1_SCRATCH_RAM_ADDR_BASE_IDX 0
+#define regSDMA1_CE_CTRL 0x0666
+#define regSDMA1_CE_CTRL_BASE_IDX 0
+#define regSDMA1_RAS_STATUS 0x0667
+#define regSDMA1_RAS_STATUS_BASE_IDX 0
+#define regSDMA1_CLK_STATUS 0x0668
+#define regSDMA1_CLK_STATUS_BASE_IDX 0
+#define regSDMA1_GFX_RB_CNTL 0x0680
+#define regSDMA1_GFX_RB_CNTL_BASE_IDX 0
+#define regSDMA1_GFX_RB_BASE 0x0681
+#define regSDMA1_GFX_RB_BASE_BASE_IDX 0
+#define regSDMA1_GFX_RB_BASE_HI 0x0682
+#define regSDMA1_GFX_RB_BASE_HI_BASE_IDX 0
+#define regSDMA1_GFX_RB_RPTR 0x0683
+#define regSDMA1_GFX_RB_RPTR_BASE_IDX 0
+#define regSDMA1_GFX_RB_RPTR_HI 0x0684
+#define regSDMA1_GFX_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA1_GFX_RB_WPTR 0x0685
+#define regSDMA1_GFX_RB_WPTR_BASE_IDX 0
+#define regSDMA1_GFX_RB_WPTR_HI 0x0686
+#define regSDMA1_GFX_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA1_GFX_RB_WPTR_POLL_CNTL 0x0687
+#define regSDMA1_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA1_GFX_RB_RPTR_ADDR_HI 0x0688
+#define regSDMA1_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA1_GFX_RB_RPTR_ADDR_LO 0x0689
+#define regSDMA1_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA1_GFX_IB_CNTL 0x068a
+#define regSDMA1_GFX_IB_CNTL_BASE_IDX 0
+#define regSDMA1_GFX_IB_RPTR 0x068b
+#define regSDMA1_GFX_IB_RPTR_BASE_IDX 0
+#define regSDMA1_GFX_IB_OFFSET 0x068c
+#define regSDMA1_GFX_IB_OFFSET_BASE_IDX 0
+#define regSDMA1_GFX_IB_BASE_LO 0x068d
+#define regSDMA1_GFX_IB_BASE_LO_BASE_IDX 0
+#define regSDMA1_GFX_IB_BASE_HI 0x068e
+#define regSDMA1_GFX_IB_BASE_HI_BASE_IDX 0
+#define regSDMA1_GFX_IB_SIZE 0x068f
+#define regSDMA1_GFX_IB_SIZE_BASE_IDX 0
+#define regSDMA1_GFX_SKIP_CNTL 0x0690
+#define regSDMA1_GFX_SKIP_CNTL_BASE_IDX 0
+#define regSDMA1_GFX_CONTEXT_STATUS 0x0691
+#define regSDMA1_GFX_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA1_GFX_DOORBELL 0x0692
+#define regSDMA1_GFX_DOORBELL_BASE_IDX 0
+#define regSDMA1_GFX_CONTEXT_CNTL 0x0693
+#define regSDMA1_GFX_CONTEXT_CNTL_BASE_IDX 0
+#define regSDMA1_GFX_STATUS 0x06a8
+#define regSDMA1_GFX_STATUS_BASE_IDX 0
+#define regSDMA1_GFX_DOORBELL_LOG 0x06a9
+#define regSDMA1_GFX_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA1_GFX_WATERMARK 0x06aa
+#define regSDMA1_GFX_WATERMARK_BASE_IDX 0
+#define regSDMA1_GFX_DOORBELL_OFFSET 0x06ab
+#define regSDMA1_GFX_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA1_GFX_CSA_ADDR_LO 0x06ac
+#define regSDMA1_GFX_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA1_GFX_CSA_ADDR_HI 0x06ad
+#define regSDMA1_GFX_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA1_GFX_IB_SUB_REMAIN 0x06af
+#define regSDMA1_GFX_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA1_GFX_PREEMPT 0x06b0
+#define regSDMA1_GFX_PREEMPT_BASE_IDX 0
+#define regSDMA1_GFX_DUMMY_REG 0x06b1
+#define regSDMA1_GFX_DUMMY_REG_BASE_IDX 0
+#define regSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x06b2
+#define regSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x06b3
+#define regSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA1_GFX_RB_AQL_CNTL 0x06b4
+#define regSDMA1_GFX_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA1_GFX_MINOR_PTR_UPDATE 0x06b5
+#define regSDMA1_GFX_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA1_GFX_MIDCMD_DATA0 0x06c0
+#define regSDMA1_GFX_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA1_GFX_MIDCMD_DATA1 0x06c1
+#define regSDMA1_GFX_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA1_GFX_MIDCMD_DATA2 0x06c2
+#define regSDMA1_GFX_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA1_GFX_MIDCMD_DATA3 0x06c3
+#define regSDMA1_GFX_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA1_GFX_MIDCMD_DATA4 0x06c4
+#define regSDMA1_GFX_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA1_GFX_MIDCMD_DATA5 0x06c5
+#define regSDMA1_GFX_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA1_GFX_MIDCMD_DATA6 0x06c6
+#define regSDMA1_GFX_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA1_GFX_MIDCMD_DATA7 0x06c7
+#define regSDMA1_GFX_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA1_GFX_MIDCMD_DATA8 0x06c8
+#define regSDMA1_GFX_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA1_GFX_MIDCMD_DATA9 0x06c9
+#define regSDMA1_GFX_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA1_GFX_MIDCMD_DATA10 0x06ca
+#define regSDMA1_GFX_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA1_GFX_MIDCMD_CNTL 0x06cb
+#define regSDMA1_GFX_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA1_PAGE_RB_CNTL 0x06d8
+#define regSDMA1_PAGE_RB_CNTL_BASE_IDX 0
+#define regSDMA1_PAGE_RB_BASE 0x06d9
+#define regSDMA1_PAGE_RB_BASE_BASE_IDX 0
+#define regSDMA1_PAGE_RB_BASE_HI 0x06da
+#define regSDMA1_PAGE_RB_BASE_HI_BASE_IDX 0
+#define regSDMA1_PAGE_RB_RPTR 0x06db
+#define regSDMA1_PAGE_RB_RPTR_BASE_IDX 0
+#define regSDMA1_PAGE_RB_RPTR_HI 0x06dc
+#define regSDMA1_PAGE_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA1_PAGE_RB_WPTR 0x06dd
+#define regSDMA1_PAGE_RB_WPTR_BASE_IDX 0
+#define regSDMA1_PAGE_RB_WPTR_HI 0x06de
+#define regSDMA1_PAGE_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA1_PAGE_RB_WPTR_POLL_CNTL 0x06df
+#define regSDMA1_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA1_PAGE_RB_RPTR_ADDR_HI 0x06e0
+#define regSDMA1_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA1_PAGE_RB_RPTR_ADDR_LO 0x06e1
+#define regSDMA1_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA1_PAGE_IB_CNTL 0x06e2
+#define regSDMA1_PAGE_IB_CNTL_BASE_IDX 0
+#define regSDMA1_PAGE_IB_RPTR 0x06e3
+#define regSDMA1_PAGE_IB_RPTR_BASE_IDX 0
+#define regSDMA1_PAGE_IB_OFFSET 0x06e4
+#define regSDMA1_PAGE_IB_OFFSET_BASE_IDX 0
+#define regSDMA1_PAGE_IB_BASE_LO 0x06e5
+#define regSDMA1_PAGE_IB_BASE_LO_BASE_IDX 0
+#define regSDMA1_PAGE_IB_BASE_HI 0x06e6
+#define regSDMA1_PAGE_IB_BASE_HI_BASE_IDX 0
+#define regSDMA1_PAGE_IB_SIZE 0x06e7
+#define regSDMA1_PAGE_IB_SIZE_BASE_IDX 0
+#define regSDMA1_PAGE_SKIP_CNTL 0x06e8
+#define regSDMA1_PAGE_SKIP_CNTL_BASE_IDX 0
+#define regSDMA1_PAGE_CONTEXT_STATUS 0x06e9
+#define regSDMA1_PAGE_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA1_PAGE_DOORBELL 0x06ea
+#define regSDMA1_PAGE_DOORBELL_BASE_IDX 0
+#define regSDMA1_PAGE_STATUS 0x0700
+#define regSDMA1_PAGE_STATUS_BASE_IDX 0
+#define regSDMA1_PAGE_DOORBELL_LOG 0x0701
+#define regSDMA1_PAGE_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA1_PAGE_WATERMARK 0x0702
+#define regSDMA1_PAGE_WATERMARK_BASE_IDX 0
+#define regSDMA1_PAGE_DOORBELL_OFFSET 0x0703
+#define regSDMA1_PAGE_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA1_PAGE_CSA_ADDR_LO 0x0704
+#define regSDMA1_PAGE_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA1_PAGE_CSA_ADDR_HI 0x0705
+#define regSDMA1_PAGE_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA1_PAGE_IB_SUB_REMAIN 0x0707
+#define regSDMA1_PAGE_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA1_PAGE_PREEMPT 0x0708
+#define regSDMA1_PAGE_PREEMPT_BASE_IDX 0
+#define regSDMA1_PAGE_DUMMY_REG 0x0709
+#define regSDMA1_PAGE_DUMMY_REG_BASE_IDX 0
+#define regSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI 0x070a
+#define regSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO 0x070b
+#define regSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA1_PAGE_RB_AQL_CNTL 0x070c
+#define regSDMA1_PAGE_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA1_PAGE_MINOR_PTR_UPDATE 0x070d
+#define regSDMA1_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA1_PAGE_MIDCMD_DATA0 0x0718
+#define regSDMA1_PAGE_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA1_PAGE_MIDCMD_DATA1 0x0719
+#define regSDMA1_PAGE_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA1_PAGE_MIDCMD_DATA2 0x071a
+#define regSDMA1_PAGE_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA1_PAGE_MIDCMD_DATA3 0x071b
+#define regSDMA1_PAGE_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA1_PAGE_MIDCMD_DATA4 0x071c
+#define regSDMA1_PAGE_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA1_PAGE_MIDCMD_DATA5 0x071d
+#define regSDMA1_PAGE_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA1_PAGE_MIDCMD_DATA6 0x071e
+#define regSDMA1_PAGE_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA1_PAGE_MIDCMD_DATA7 0x071f
+#define regSDMA1_PAGE_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA1_PAGE_MIDCMD_DATA8 0x0720
+#define regSDMA1_PAGE_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA1_PAGE_MIDCMD_DATA9 0x0721
+#define regSDMA1_PAGE_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA1_PAGE_MIDCMD_DATA10 0x0722
+#define regSDMA1_PAGE_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA1_PAGE_MIDCMD_CNTL 0x0723
+#define regSDMA1_PAGE_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA1_RLC0_RB_CNTL 0x0730
+#define regSDMA1_RLC0_RB_CNTL_BASE_IDX 0
+#define regSDMA1_RLC0_RB_BASE 0x0731
+#define regSDMA1_RLC0_RB_BASE_BASE_IDX 0
+#define regSDMA1_RLC0_RB_BASE_HI 0x0732
+#define regSDMA1_RLC0_RB_BASE_HI_BASE_IDX 0
+#define regSDMA1_RLC0_RB_RPTR 0x0733
+#define regSDMA1_RLC0_RB_RPTR_BASE_IDX 0
+#define regSDMA1_RLC0_RB_RPTR_HI 0x0734
+#define regSDMA1_RLC0_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA1_RLC0_RB_WPTR 0x0735
+#define regSDMA1_RLC0_RB_WPTR_BASE_IDX 0
+#define regSDMA1_RLC0_RB_WPTR_HI 0x0736
+#define regSDMA1_RLC0_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x0737
+#define regSDMA1_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA1_RLC0_RB_RPTR_ADDR_HI 0x0738
+#define regSDMA1_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA1_RLC0_RB_RPTR_ADDR_LO 0x0739
+#define regSDMA1_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA1_RLC0_IB_CNTL 0x073a
+#define regSDMA1_RLC0_IB_CNTL_BASE_IDX 0
+#define regSDMA1_RLC0_IB_RPTR 0x073b
+#define regSDMA1_RLC0_IB_RPTR_BASE_IDX 0
+#define regSDMA1_RLC0_IB_OFFSET 0x073c
+#define regSDMA1_RLC0_IB_OFFSET_BASE_IDX 0
+#define regSDMA1_RLC0_IB_BASE_LO 0x073d
+#define regSDMA1_RLC0_IB_BASE_LO_BASE_IDX 0
+#define regSDMA1_RLC0_IB_BASE_HI 0x073e
+#define regSDMA1_RLC0_IB_BASE_HI_BASE_IDX 0
+#define regSDMA1_RLC0_IB_SIZE 0x073f
+#define regSDMA1_RLC0_IB_SIZE_BASE_IDX 0
+#define regSDMA1_RLC0_SKIP_CNTL 0x0740
+#define regSDMA1_RLC0_SKIP_CNTL_BASE_IDX 0
+#define regSDMA1_RLC0_CONTEXT_STATUS 0x0741
+#define regSDMA1_RLC0_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA1_RLC0_DOORBELL 0x0742
+#define regSDMA1_RLC0_DOORBELL_BASE_IDX 0
+#define regSDMA1_RLC0_STATUS 0x0758
+#define regSDMA1_RLC0_STATUS_BASE_IDX 0
+#define regSDMA1_RLC0_DOORBELL_LOG 0x0759
+#define regSDMA1_RLC0_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA1_RLC0_WATERMARK 0x075a
+#define regSDMA1_RLC0_WATERMARK_BASE_IDX 0
+#define regSDMA1_RLC0_DOORBELL_OFFSET 0x075b
+#define regSDMA1_RLC0_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA1_RLC0_CSA_ADDR_LO 0x075c
+#define regSDMA1_RLC0_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA1_RLC0_CSA_ADDR_HI 0x075d
+#define regSDMA1_RLC0_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA1_RLC0_IB_SUB_REMAIN 0x075f
+#define regSDMA1_RLC0_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA1_RLC0_PREEMPT 0x0760
+#define regSDMA1_RLC0_PREEMPT_BASE_IDX 0
+#define regSDMA1_RLC0_DUMMY_REG 0x0761
+#define regSDMA1_RLC0_DUMMY_REG_BASE_IDX 0
+#define regSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x0762
+#define regSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x0763
+#define regSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA1_RLC0_RB_AQL_CNTL 0x0764
+#define regSDMA1_RLC0_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA1_RLC0_MINOR_PTR_UPDATE 0x0765
+#define regSDMA1_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA1_RLC0_MIDCMD_DATA0 0x0770
+#define regSDMA1_RLC0_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA1_RLC0_MIDCMD_DATA1 0x0771
+#define regSDMA1_RLC0_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA1_RLC0_MIDCMD_DATA2 0x0772
+#define regSDMA1_RLC0_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA1_RLC0_MIDCMD_DATA3 0x0773
+#define regSDMA1_RLC0_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA1_RLC0_MIDCMD_DATA4 0x0774
+#define regSDMA1_RLC0_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA1_RLC0_MIDCMD_DATA5 0x0775
+#define regSDMA1_RLC0_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA1_RLC0_MIDCMD_DATA6 0x0776
+#define regSDMA1_RLC0_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA1_RLC0_MIDCMD_DATA7 0x0777
+#define regSDMA1_RLC0_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA1_RLC0_MIDCMD_DATA8 0x0778
+#define regSDMA1_RLC0_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA1_RLC0_MIDCMD_DATA9 0x0779
+#define regSDMA1_RLC0_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA1_RLC0_MIDCMD_DATA10 0x077a
+#define regSDMA1_RLC0_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA1_RLC0_MIDCMD_CNTL 0x077b
+#define regSDMA1_RLC0_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA1_RLC1_RB_CNTL 0x0788
+#define regSDMA1_RLC1_RB_CNTL_BASE_IDX 0
+#define regSDMA1_RLC1_RB_BASE 0x0789
+#define regSDMA1_RLC1_RB_BASE_BASE_IDX 0
+#define regSDMA1_RLC1_RB_BASE_HI 0x078a
+#define regSDMA1_RLC1_RB_BASE_HI_BASE_IDX 0
+#define regSDMA1_RLC1_RB_RPTR 0x078b
+#define regSDMA1_RLC1_RB_RPTR_BASE_IDX 0
+#define regSDMA1_RLC1_RB_RPTR_HI 0x078c
+#define regSDMA1_RLC1_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA1_RLC1_RB_WPTR 0x078d
+#define regSDMA1_RLC1_RB_WPTR_BASE_IDX 0
+#define regSDMA1_RLC1_RB_WPTR_HI 0x078e
+#define regSDMA1_RLC1_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x078f
+#define regSDMA1_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA1_RLC1_RB_RPTR_ADDR_HI 0x0790
+#define regSDMA1_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA1_RLC1_RB_RPTR_ADDR_LO 0x0791
+#define regSDMA1_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA1_RLC1_IB_CNTL 0x0792
+#define regSDMA1_RLC1_IB_CNTL_BASE_IDX 0
+#define regSDMA1_RLC1_IB_RPTR 0x0793
+#define regSDMA1_RLC1_IB_RPTR_BASE_IDX 0
+#define regSDMA1_RLC1_IB_OFFSET 0x0794
+#define regSDMA1_RLC1_IB_OFFSET_BASE_IDX 0
+#define regSDMA1_RLC1_IB_BASE_LO 0x0795
+#define regSDMA1_RLC1_IB_BASE_LO_BASE_IDX 0
+#define regSDMA1_RLC1_IB_BASE_HI 0x0796
+#define regSDMA1_RLC1_IB_BASE_HI_BASE_IDX 0
+#define regSDMA1_RLC1_IB_SIZE 0x0797
+#define regSDMA1_RLC1_IB_SIZE_BASE_IDX 0
+#define regSDMA1_RLC1_SKIP_CNTL 0x0798
+#define regSDMA1_RLC1_SKIP_CNTL_BASE_IDX 0
+#define regSDMA1_RLC1_CONTEXT_STATUS 0x0799
+#define regSDMA1_RLC1_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA1_RLC1_DOORBELL 0x079a
+#define regSDMA1_RLC1_DOORBELL_BASE_IDX 0
+#define regSDMA1_RLC1_STATUS 0x07b0
+#define regSDMA1_RLC1_STATUS_BASE_IDX 0
+#define regSDMA1_RLC1_DOORBELL_LOG 0x07b1
+#define regSDMA1_RLC1_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA1_RLC1_WATERMARK 0x07b2
+#define regSDMA1_RLC1_WATERMARK_BASE_IDX 0
+#define regSDMA1_RLC1_DOORBELL_OFFSET 0x07b3
+#define regSDMA1_RLC1_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA1_RLC1_CSA_ADDR_LO 0x07b4
+#define regSDMA1_RLC1_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA1_RLC1_CSA_ADDR_HI 0x07b5
+#define regSDMA1_RLC1_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA1_RLC1_IB_SUB_REMAIN 0x07b7
+#define regSDMA1_RLC1_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA1_RLC1_PREEMPT 0x07b8
+#define regSDMA1_RLC1_PREEMPT_BASE_IDX 0
+#define regSDMA1_RLC1_DUMMY_REG 0x07b9
+#define regSDMA1_RLC1_DUMMY_REG_BASE_IDX 0
+#define regSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x07ba
+#define regSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x07bb
+#define regSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA1_RLC1_RB_AQL_CNTL 0x07bc
+#define regSDMA1_RLC1_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA1_RLC1_MINOR_PTR_UPDATE 0x07bd
+#define regSDMA1_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA1_RLC1_MIDCMD_DATA0 0x07c8
+#define regSDMA1_RLC1_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA1_RLC1_MIDCMD_DATA1 0x07c9
+#define regSDMA1_RLC1_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA1_RLC1_MIDCMD_DATA2 0x07ca
+#define regSDMA1_RLC1_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA1_RLC1_MIDCMD_DATA3 0x07cb
+#define regSDMA1_RLC1_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA1_RLC1_MIDCMD_DATA4 0x07cc
+#define regSDMA1_RLC1_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA1_RLC1_MIDCMD_DATA5 0x07cd
+#define regSDMA1_RLC1_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA1_RLC1_MIDCMD_DATA6 0x07ce
+#define regSDMA1_RLC1_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA1_RLC1_MIDCMD_DATA7 0x07cf
+#define regSDMA1_RLC1_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA1_RLC1_MIDCMD_DATA8 0x07d0
+#define regSDMA1_RLC1_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA1_RLC1_MIDCMD_DATA9 0x07d1
+#define regSDMA1_RLC1_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA1_RLC1_MIDCMD_DATA10 0x07d2
+#define regSDMA1_RLC1_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA1_RLC1_MIDCMD_CNTL 0x07d3
+#define regSDMA1_RLC1_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA1_RLC2_RB_CNTL 0x07e0
+#define regSDMA1_RLC2_RB_CNTL_BASE_IDX 0
+#define regSDMA1_RLC2_RB_BASE 0x07e1
+#define regSDMA1_RLC2_RB_BASE_BASE_IDX 0
+#define regSDMA1_RLC2_RB_BASE_HI 0x07e2
+#define regSDMA1_RLC2_RB_BASE_HI_BASE_IDX 0
+#define regSDMA1_RLC2_RB_RPTR 0x07e3
+#define regSDMA1_RLC2_RB_RPTR_BASE_IDX 0
+#define regSDMA1_RLC2_RB_RPTR_HI 0x07e4
+#define regSDMA1_RLC2_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA1_RLC2_RB_WPTR 0x07e5
+#define regSDMA1_RLC2_RB_WPTR_BASE_IDX 0
+#define regSDMA1_RLC2_RB_WPTR_HI 0x07e6
+#define regSDMA1_RLC2_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA1_RLC2_RB_WPTR_POLL_CNTL 0x07e7
+#define regSDMA1_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA1_RLC2_RB_RPTR_ADDR_HI 0x07e8
+#define regSDMA1_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA1_RLC2_RB_RPTR_ADDR_LO 0x07e9
+#define regSDMA1_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA1_RLC2_IB_CNTL 0x07ea
+#define regSDMA1_RLC2_IB_CNTL_BASE_IDX 0
+#define regSDMA1_RLC2_IB_RPTR 0x07eb
+#define regSDMA1_RLC2_IB_RPTR_BASE_IDX 0
+#define regSDMA1_RLC2_IB_OFFSET 0x07ec
+#define regSDMA1_RLC2_IB_OFFSET_BASE_IDX 0
+#define regSDMA1_RLC2_IB_BASE_LO 0x07ed
+#define regSDMA1_RLC2_IB_BASE_LO_BASE_IDX 0
+#define regSDMA1_RLC2_IB_BASE_HI 0x07ee
+#define regSDMA1_RLC2_IB_BASE_HI_BASE_IDX 0
+#define regSDMA1_RLC2_IB_SIZE 0x07ef
+#define regSDMA1_RLC2_IB_SIZE_BASE_IDX 0
+#define regSDMA1_RLC2_SKIP_CNTL 0x07f0
+#define regSDMA1_RLC2_SKIP_CNTL_BASE_IDX 0
+#define regSDMA1_RLC2_CONTEXT_STATUS 0x07f1
+#define regSDMA1_RLC2_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA1_RLC2_DOORBELL 0x07f2
+#define regSDMA1_RLC2_DOORBELL_BASE_IDX 0
+#define regSDMA1_RLC2_STATUS 0x0808
+#define regSDMA1_RLC2_STATUS_BASE_IDX 0
+#define regSDMA1_RLC2_DOORBELL_LOG 0x0809
+#define regSDMA1_RLC2_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA1_RLC2_WATERMARK 0x080a
+#define regSDMA1_RLC2_WATERMARK_BASE_IDX 0
+#define regSDMA1_RLC2_DOORBELL_OFFSET 0x080b
+#define regSDMA1_RLC2_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA1_RLC2_CSA_ADDR_LO 0x080c
+#define regSDMA1_RLC2_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA1_RLC2_CSA_ADDR_HI 0x080d
+#define regSDMA1_RLC2_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA1_RLC2_IB_SUB_REMAIN 0x080f
+#define regSDMA1_RLC2_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA1_RLC2_PREEMPT 0x0810
+#define regSDMA1_RLC2_PREEMPT_BASE_IDX 0
+#define regSDMA1_RLC2_DUMMY_REG 0x0811
+#define regSDMA1_RLC2_DUMMY_REG_BASE_IDX 0
+#define regSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI 0x0812
+#define regSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO 0x0813
+#define regSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA1_RLC2_RB_AQL_CNTL 0x0814
+#define regSDMA1_RLC2_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA1_RLC2_MINOR_PTR_UPDATE 0x0815
+#define regSDMA1_RLC2_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA1_RLC2_MIDCMD_DATA0 0x0820
+#define regSDMA1_RLC2_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA1_RLC2_MIDCMD_DATA1 0x0821
+#define regSDMA1_RLC2_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA1_RLC2_MIDCMD_DATA2 0x0822
+#define regSDMA1_RLC2_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA1_RLC2_MIDCMD_DATA3 0x0823
+#define regSDMA1_RLC2_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA1_RLC2_MIDCMD_DATA4 0x0824
+#define regSDMA1_RLC2_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA1_RLC2_MIDCMD_DATA5 0x0825
+#define regSDMA1_RLC2_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA1_RLC2_MIDCMD_DATA6 0x0826
+#define regSDMA1_RLC2_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA1_RLC2_MIDCMD_DATA7 0x0827
+#define regSDMA1_RLC2_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA1_RLC2_MIDCMD_DATA8 0x0828
+#define regSDMA1_RLC2_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA1_RLC2_MIDCMD_DATA9 0x0829
+#define regSDMA1_RLC2_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA1_RLC2_MIDCMD_DATA10 0x082a
+#define regSDMA1_RLC2_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA1_RLC2_MIDCMD_CNTL 0x082b
+#define regSDMA1_RLC2_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA1_RLC3_RB_CNTL 0x0838
+#define regSDMA1_RLC3_RB_CNTL_BASE_IDX 0
+#define regSDMA1_RLC3_RB_BASE 0x0839
+#define regSDMA1_RLC3_RB_BASE_BASE_IDX 0
+#define regSDMA1_RLC3_RB_BASE_HI 0x083a
+#define regSDMA1_RLC3_RB_BASE_HI_BASE_IDX 0
+#define regSDMA1_RLC3_RB_RPTR 0x083b
+#define regSDMA1_RLC3_RB_RPTR_BASE_IDX 0
+#define regSDMA1_RLC3_RB_RPTR_HI 0x083c
+#define regSDMA1_RLC3_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA1_RLC3_RB_WPTR 0x083d
+#define regSDMA1_RLC3_RB_WPTR_BASE_IDX 0
+#define regSDMA1_RLC3_RB_WPTR_HI 0x083e
+#define regSDMA1_RLC3_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA1_RLC3_RB_WPTR_POLL_CNTL 0x083f
+#define regSDMA1_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA1_RLC3_RB_RPTR_ADDR_HI 0x0840
+#define regSDMA1_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA1_RLC3_RB_RPTR_ADDR_LO 0x0841
+#define regSDMA1_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA1_RLC3_IB_CNTL 0x0842
+#define regSDMA1_RLC3_IB_CNTL_BASE_IDX 0
+#define regSDMA1_RLC3_IB_RPTR 0x0843
+#define regSDMA1_RLC3_IB_RPTR_BASE_IDX 0
+#define regSDMA1_RLC3_IB_OFFSET 0x0844
+#define regSDMA1_RLC3_IB_OFFSET_BASE_IDX 0
+#define regSDMA1_RLC3_IB_BASE_LO 0x0845
+#define regSDMA1_RLC3_IB_BASE_LO_BASE_IDX 0
+#define regSDMA1_RLC3_IB_BASE_HI 0x0846
+#define regSDMA1_RLC3_IB_BASE_HI_BASE_IDX 0
+#define regSDMA1_RLC3_IB_SIZE 0x0847
+#define regSDMA1_RLC3_IB_SIZE_BASE_IDX 0
+#define regSDMA1_RLC3_SKIP_CNTL 0x0848
+#define regSDMA1_RLC3_SKIP_CNTL_BASE_IDX 0
+#define regSDMA1_RLC3_CONTEXT_STATUS 0x0849
+#define regSDMA1_RLC3_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA1_RLC3_DOORBELL 0x084a
+#define regSDMA1_RLC3_DOORBELL_BASE_IDX 0
+#define regSDMA1_RLC3_STATUS 0x0860
+#define regSDMA1_RLC3_STATUS_BASE_IDX 0
+#define regSDMA1_RLC3_DOORBELL_LOG 0x0861
+#define regSDMA1_RLC3_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA1_RLC3_WATERMARK 0x0862
+#define regSDMA1_RLC3_WATERMARK_BASE_IDX 0
+#define regSDMA1_RLC3_DOORBELL_OFFSET 0x0863
+#define regSDMA1_RLC3_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA1_RLC3_CSA_ADDR_LO 0x0864
+#define regSDMA1_RLC3_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA1_RLC3_CSA_ADDR_HI 0x0865
+#define regSDMA1_RLC3_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA1_RLC3_IB_SUB_REMAIN 0x0867
+#define regSDMA1_RLC3_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA1_RLC3_PREEMPT 0x0868
+#define regSDMA1_RLC3_PREEMPT_BASE_IDX 0
+#define regSDMA1_RLC3_DUMMY_REG 0x0869
+#define regSDMA1_RLC3_DUMMY_REG_BASE_IDX 0
+#define regSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI 0x086a
+#define regSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO 0x086b
+#define regSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA1_RLC3_RB_AQL_CNTL 0x086c
+#define regSDMA1_RLC3_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA1_RLC3_MINOR_PTR_UPDATE 0x086d
+#define regSDMA1_RLC3_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA1_RLC3_MIDCMD_DATA0 0x0878
+#define regSDMA1_RLC3_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA1_RLC3_MIDCMD_DATA1 0x0879
+#define regSDMA1_RLC3_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA1_RLC3_MIDCMD_DATA2 0x087a
+#define regSDMA1_RLC3_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA1_RLC3_MIDCMD_DATA3 0x087b
+#define regSDMA1_RLC3_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA1_RLC3_MIDCMD_DATA4 0x087c
+#define regSDMA1_RLC3_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA1_RLC3_MIDCMD_DATA5 0x087d
+#define regSDMA1_RLC3_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA1_RLC3_MIDCMD_DATA6 0x087e
+#define regSDMA1_RLC3_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA1_RLC3_MIDCMD_DATA7 0x087f
+#define regSDMA1_RLC3_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA1_RLC3_MIDCMD_DATA8 0x0880
+#define regSDMA1_RLC3_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA1_RLC3_MIDCMD_DATA9 0x0881
+#define regSDMA1_RLC3_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA1_RLC3_MIDCMD_DATA10 0x0882
+#define regSDMA1_RLC3_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA1_RLC3_MIDCMD_CNTL 0x0883
+#define regSDMA1_RLC3_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA1_RLC4_RB_CNTL 0x0890
+#define regSDMA1_RLC4_RB_CNTL_BASE_IDX 0
+#define regSDMA1_RLC4_RB_BASE 0x0891
+#define regSDMA1_RLC4_RB_BASE_BASE_IDX 0
+#define regSDMA1_RLC4_RB_BASE_HI 0x0892
+#define regSDMA1_RLC4_RB_BASE_HI_BASE_IDX 0
+#define regSDMA1_RLC4_RB_RPTR 0x0893
+#define regSDMA1_RLC4_RB_RPTR_BASE_IDX 0
+#define regSDMA1_RLC4_RB_RPTR_HI 0x0894
+#define regSDMA1_RLC4_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA1_RLC4_RB_WPTR 0x0895
+#define regSDMA1_RLC4_RB_WPTR_BASE_IDX 0
+#define regSDMA1_RLC4_RB_WPTR_HI 0x0896
+#define regSDMA1_RLC4_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA1_RLC4_RB_WPTR_POLL_CNTL 0x0897
+#define regSDMA1_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA1_RLC4_RB_RPTR_ADDR_HI 0x0898
+#define regSDMA1_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA1_RLC4_RB_RPTR_ADDR_LO 0x0899
+#define regSDMA1_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA1_RLC4_IB_CNTL 0x089a
+#define regSDMA1_RLC4_IB_CNTL_BASE_IDX 0
+#define regSDMA1_RLC4_IB_RPTR 0x089b
+#define regSDMA1_RLC4_IB_RPTR_BASE_IDX 0
+#define regSDMA1_RLC4_IB_OFFSET 0x089c
+#define regSDMA1_RLC4_IB_OFFSET_BASE_IDX 0
+#define regSDMA1_RLC4_IB_BASE_LO 0x089d
+#define regSDMA1_RLC4_IB_BASE_LO_BASE_IDX 0
+#define regSDMA1_RLC4_IB_BASE_HI 0x089e
+#define regSDMA1_RLC4_IB_BASE_HI_BASE_IDX 0
+#define regSDMA1_RLC4_IB_SIZE 0x089f
+#define regSDMA1_RLC4_IB_SIZE_BASE_IDX 0
+#define regSDMA1_RLC4_SKIP_CNTL 0x08a0
+#define regSDMA1_RLC4_SKIP_CNTL_BASE_IDX 0
+#define regSDMA1_RLC4_CONTEXT_STATUS 0x08a1
+#define regSDMA1_RLC4_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA1_RLC4_DOORBELL 0x08a2
+#define regSDMA1_RLC4_DOORBELL_BASE_IDX 0
+#define regSDMA1_RLC4_STATUS 0x08b8
+#define regSDMA1_RLC4_STATUS_BASE_IDX 0
+#define regSDMA1_RLC4_DOORBELL_LOG 0x08b9
+#define regSDMA1_RLC4_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA1_RLC4_WATERMARK 0x08ba
+#define regSDMA1_RLC4_WATERMARK_BASE_IDX 0
+#define regSDMA1_RLC4_DOORBELL_OFFSET 0x08bb
+#define regSDMA1_RLC4_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA1_RLC4_CSA_ADDR_LO 0x08bc
+#define regSDMA1_RLC4_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA1_RLC4_CSA_ADDR_HI 0x08bd
+#define regSDMA1_RLC4_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA1_RLC4_IB_SUB_REMAIN 0x08bf
+#define regSDMA1_RLC4_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA1_RLC4_PREEMPT 0x08c0
+#define regSDMA1_RLC4_PREEMPT_BASE_IDX 0
+#define regSDMA1_RLC4_DUMMY_REG 0x08c1
+#define regSDMA1_RLC4_DUMMY_REG_BASE_IDX 0
+#define regSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI 0x08c2
+#define regSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO 0x08c3
+#define regSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA1_RLC4_RB_AQL_CNTL 0x08c4
+#define regSDMA1_RLC4_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA1_RLC4_MINOR_PTR_UPDATE 0x08c5
+#define regSDMA1_RLC4_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA1_RLC4_MIDCMD_DATA0 0x08d0
+#define regSDMA1_RLC4_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA1_RLC4_MIDCMD_DATA1 0x08d1
+#define regSDMA1_RLC4_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA1_RLC4_MIDCMD_DATA2 0x08d2
+#define regSDMA1_RLC4_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA1_RLC4_MIDCMD_DATA3 0x08d3
+#define regSDMA1_RLC4_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA1_RLC4_MIDCMD_DATA4 0x08d4
+#define regSDMA1_RLC4_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA1_RLC4_MIDCMD_DATA5 0x08d5
+#define regSDMA1_RLC4_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA1_RLC4_MIDCMD_DATA6 0x08d6
+#define regSDMA1_RLC4_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA1_RLC4_MIDCMD_DATA7 0x08d7
+#define regSDMA1_RLC4_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA1_RLC4_MIDCMD_DATA8 0x08d8
+#define regSDMA1_RLC4_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA1_RLC4_MIDCMD_DATA9 0x08d9
+#define regSDMA1_RLC4_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA1_RLC4_MIDCMD_DATA10 0x08da
+#define regSDMA1_RLC4_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA1_RLC4_MIDCMD_CNTL 0x08db
+#define regSDMA1_RLC4_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA1_RLC5_RB_CNTL 0x08e8
+#define regSDMA1_RLC5_RB_CNTL_BASE_IDX 0
+#define regSDMA1_RLC5_RB_BASE 0x08e9
+#define regSDMA1_RLC5_RB_BASE_BASE_IDX 0
+#define regSDMA1_RLC5_RB_BASE_HI 0x08ea
+#define regSDMA1_RLC5_RB_BASE_HI_BASE_IDX 0
+#define regSDMA1_RLC5_RB_RPTR 0x08eb
+#define regSDMA1_RLC5_RB_RPTR_BASE_IDX 0
+#define regSDMA1_RLC5_RB_RPTR_HI 0x08ec
+#define regSDMA1_RLC5_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA1_RLC5_RB_WPTR 0x08ed
+#define regSDMA1_RLC5_RB_WPTR_BASE_IDX 0
+#define regSDMA1_RLC5_RB_WPTR_HI 0x08ee
+#define regSDMA1_RLC5_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA1_RLC5_RB_WPTR_POLL_CNTL 0x08ef
+#define regSDMA1_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA1_RLC5_RB_RPTR_ADDR_HI 0x08f0
+#define regSDMA1_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA1_RLC5_RB_RPTR_ADDR_LO 0x08f1
+#define regSDMA1_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA1_RLC5_IB_CNTL 0x08f2
+#define regSDMA1_RLC5_IB_CNTL_BASE_IDX 0
+#define regSDMA1_RLC5_IB_RPTR 0x08f3
+#define regSDMA1_RLC5_IB_RPTR_BASE_IDX 0
+#define regSDMA1_RLC5_IB_OFFSET 0x08f4
+#define regSDMA1_RLC5_IB_OFFSET_BASE_IDX 0
+#define regSDMA1_RLC5_IB_BASE_LO 0x08f5
+#define regSDMA1_RLC5_IB_BASE_LO_BASE_IDX 0
+#define regSDMA1_RLC5_IB_BASE_HI 0x08f6
+#define regSDMA1_RLC5_IB_BASE_HI_BASE_IDX 0
+#define regSDMA1_RLC5_IB_SIZE 0x08f7
+#define regSDMA1_RLC5_IB_SIZE_BASE_IDX 0
+#define regSDMA1_RLC5_SKIP_CNTL 0x08f8
+#define regSDMA1_RLC5_SKIP_CNTL_BASE_IDX 0
+#define regSDMA1_RLC5_CONTEXT_STATUS 0x08f9
+#define regSDMA1_RLC5_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA1_RLC5_DOORBELL 0x08fa
+#define regSDMA1_RLC5_DOORBELL_BASE_IDX 0
+#define regSDMA1_RLC5_STATUS 0x0910
+#define regSDMA1_RLC5_STATUS_BASE_IDX 0
+#define regSDMA1_RLC5_DOORBELL_LOG 0x0911
+#define regSDMA1_RLC5_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA1_RLC5_WATERMARK 0x0912
+#define regSDMA1_RLC5_WATERMARK_BASE_IDX 0
+#define regSDMA1_RLC5_DOORBELL_OFFSET 0x0913
+#define regSDMA1_RLC5_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA1_RLC5_CSA_ADDR_LO 0x0914
+#define regSDMA1_RLC5_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA1_RLC5_CSA_ADDR_HI 0x0915
+#define regSDMA1_RLC5_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA1_RLC5_IB_SUB_REMAIN 0x0917
+#define regSDMA1_RLC5_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA1_RLC5_PREEMPT 0x0918
+#define regSDMA1_RLC5_PREEMPT_BASE_IDX 0
+#define regSDMA1_RLC5_DUMMY_REG 0x0919
+#define regSDMA1_RLC5_DUMMY_REG_BASE_IDX 0
+#define regSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI 0x091a
+#define regSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO 0x091b
+#define regSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA1_RLC5_RB_AQL_CNTL 0x091c
+#define regSDMA1_RLC5_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA1_RLC5_MINOR_PTR_UPDATE 0x091d
+#define regSDMA1_RLC5_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA1_RLC5_MIDCMD_DATA0 0x0928
+#define regSDMA1_RLC5_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA1_RLC5_MIDCMD_DATA1 0x0929
+#define regSDMA1_RLC5_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA1_RLC5_MIDCMD_DATA2 0x092a
+#define regSDMA1_RLC5_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA1_RLC5_MIDCMD_DATA3 0x092b
+#define regSDMA1_RLC5_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA1_RLC5_MIDCMD_DATA4 0x092c
+#define regSDMA1_RLC5_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA1_RLC5_MIDCMD_DATA5 0x092d
+#define regSDMA1_RLC5_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA1_RLC5_MIDCMD_DATA6 0x092e
+#define regSDMA1_RLC5_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA1_RLC5_MIDCMD_DATA7 0x092f
+#define regSDMA1_RLC5_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA1_RLC5_MIDCMD_DATA8 0x0930
+#define regSDMA1_RLC5_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA1_RLC5_MIDCMD_DATA9 0x0931
+#define regSDMA1_RLC5_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA1_RLC5_MIDCMD_DATA10 0x0932
+#define regSDMA1_RLC5_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA1_RLC5_MIDCMD_CNTL 0x0933
+#define regSDMA1_RLC5_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA1_RLC6_RB_CNTL 0x0940
+#define regSDMA1_RLC6_RB_CNTL_BASE_IDX 0
+#define regSDMA1_RLC6_RB_BASE 0x0941
+#define regSDMA1_RLC6_RB_BASE_BASE_IDX 0
+#define regSDMA1_RLC6_RB_BASE_HI 0x0942
+#define regSDMA1_RLC6_RB_BASE_HI_BASE_IDX 0
+#define regSDMA1_RLC6_RB_RPTR 0x0943
+#define regSDMA1_RLC6_RB_RPTR_BASE_IDX 0
+#define regSDMA1_RLC6_RB_RPTR_HI 0x0944
+#define regSDMA1_RLC6_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA1_RLC6_RB_WPTR 0x0945
+#define regSDMA1_RLC6_RB_WPTR_BASE_IDX 0
+#define regSDMA1_RLC6_RB_WPTR_HI 0x0946
+#define regSDMA1_RLC6_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA1_RLC6_RB_WPTR_POLL_CNTL 0x0947
+#define regSDMA1_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA1_RLC6_RB_RPTR_ADDR_HI 0x0948
+#define regSDMA1_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA1_RLC6_RB_RPTR_ADDR_LO 0x0949
+#define regSDMA1_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA1_RLC6_IB_CNTL 0x094a
+#define regSDMA1_RLC6_IB_CNTL_BASE_IDX 0
+#define regSDMA1_RLC6_IB_RPTR 0x094b
+#define regSDMA1_RLC6_IB_RPTR_BASE_IDX 0
+#define regSDMA1_RLC6_IB_OFFSET 0x094c
+#define regSDMA1_RLC6_IB_OFFSET_BASE_IDX 0
+#define regSDMA1_RLC6_IB_BASE_LO 0x094d
+#define regSDMA1_RLC6_IB_BASE_LO_BASE_IDX 0
+#define regSDMA1_RLC6_IB_BASE_HI 0x094e
+#define regSDMA1_RLC6_IB_BASE_HI_BASE_IDX 0
+#define regSDMA1_RLC6_IB_SIZE 0x094f
+#define regSDMA1_RLC6_IB_SIZE_BASE_IDX 0
+#define regSDMA1_RLC6_SKIP_CNTL 0x0950
+#define regSDMA1_RLC6_SKIP_CNTL_BASE_IDX 0
+#define regSDMA1_RLC6_CONTEXT_STATUS 0x0951
+#define regSDMA1_RLC6_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA1_RLC6_DOORBELL 0x0952
+#define regSDMA1_RLC6_DOORBELL_BASE_IDX 0
+#define regSDMA1_RLC6_STATUS 0x0968
+#define regSDMA1_RLC6_STATUS_BASE_IDX 0
+#define regSDMA1_RLC6_DOORBELL_LOG 0x0969
+#define regSDMA1_RLC6_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA1_RLC6_WATERMARK 0x096a
+#define regSDMA1_RLC6_WATERMARK_BASE_IDX 0
+#define regSDMA1_RLC6_DOORBELL_OFFSET 0x096b
+#define regSDMA1_RLC6_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA1_RLC6_CSA_ADDR_LO 0x096c
+#define regSDMA1_RLC6_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA1_RLC6_CSA_ADDR_HI 0x096d
+#define regSDMA1_RLC6_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA1_RLC6_IB_SUB_REMAIN 0x096f
+#define regSDMA1_RLC6_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA1_RLC6_PREEMPT 0x0970
+#define regSDMA1_RLC6_PREEMPT_BASE_IDX 0
+#define regSDMA1_RLC6_DUMMY_REG 0x0971
+#define regSDMA1_RLC6_DUMMY_REG_BASE_IDX 0
+#define regSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI 0x0972
+#define regSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO 0x0973
+#define regSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA1_RLC6_RB_AQL_CNTL 0x0974
+#define regSDMA1_RLC6_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA1_RLC6_MINOR_PTR_UPDATE 0x0975
+#define regSDMA1_RLC6_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA1_RLC6_MIDCMD_DATA0 0x0980
+#define regSDMA1_RLC6_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA1_RLC6_MIDCMD_DATA1 0x0981
+#define regSDMA1_RLC6_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA1_RLC6_MIDCMD_DATA2 0x0982
+#define regSDMA1_RLC6_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA1_RLC6_MIDCMD_DATA3 0x0983
+#define regSDMA1_RLC6_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA1_RLC6_MIDCMD_DATA4 0x0984
+#define regSDMA1_RLC6_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA1_RLC6_MIDCMD_DATA5 0x0985
+#define regSDMA1_RLC6_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA1_RLC6_MIDCMD_DATA6 0x0986
+#define regSDMA1_RLC6_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA1_RLC6_MIDCMD_DATA7 0x0987
+#define regSDMA1_RLC6_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA1_RLC6_MIDCMD_DATA8 0x0988
+#define regSDMA1_RLC6_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA1_RLC6_MIDCMD_DATA9 0x0989
+#define regSDMA1_RLC6_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA1_RLC6_MIDCMD_DATA10 0x098a
+#define regSDMA1_RLC6_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA1_RLC6_MIDCMD_CNTL 0x098b
+#define regSDMA1_RLC6_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA1_RLC7_RB_CNTL 0x0998
+#define regSDMA1_RLC7_RB_CNTL_BASE_IDX 0
+#define regSDMA1_RLC7_RB_BASE 0x0999
+#define regSDMA1_RLC7_RB_BASE_BASE_IDX 0
+#define regSDMA1_RLC7_RB_BASE_HI 0x099a
+#define regSDMA1_RLC7_RB_BASE_HI_BASE_IDX 0
+#define regSDMA1_RLC7_RB_RPTR 0x099b
+#define regSDMA1_RLC7_RB_RPTR_BASE_IDX 0
+#define regSDMA1_RLC7_RB_RPTR_HI 0x099c
+#define regSDMA1_RLC7_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA1_RLC7_RB_WPTR 0x099d
+#define regSDMA1_RLC7_RB_WPTR_BASE_IDX 0
+#define regSDMA1_RLC7_RB_WPTR_HI 0x099e
+#define regSDMA1_RLC7_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA1_RLC7_RB_WPTR_POLL_CNTL 0x099f
+#define regSDMA1_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA1_RLC7_RB_RPTR_ADDR_HI 0x09a0
+#define regSDMA1_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA1_RLC7_RB_RPTR_ADDR_LO 0x09a1
+#define regSDMA1_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA1_RLC7_IB_CNTL 0x09a2
+#define regSDMA1_RLC7_IB_CNTL_BASE_IDX 0
+#define regSDMA1_RLC7_IB_RPTR 0x09a3
+#define regSDMA1_RLC7_IB_RPTR_BASE_IDX 0
+#define regSDMA1_RLC7_IB_OFFSET 0x09a4
+#define regSDMA1_RLC7_IB_OFFSET_BASE_IDX 0
+#define regSDMA1_RLC7_IB_BASE_LO 0x09a5
+#define regSDMA1_RLC7_IB_BASE_LO_BASE_IDX 0
+#define regSDMA1_RLC7_IB_BASE_HI 0x09a6
+#define regSDMA1_RLC7_IB_BASE_HI_BASE_IDX 0
+#define regSDMA1_RLC7_IB_SIZE 0x09a7
+#define regSDMA1_RLC7_IB_SIZE_BASE_IDX 0
+#define regSDMA1_RLC7_SKIP_CNTL 0x09a8
+#define regSDMA1_RLC7_SKIP_CNTL_BASE_IDX 0
+#define regSDMA1_RLC7_CONTEXT_STATUS 0x09a9
+#define regSDMA1_RLC7_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA1_RLC7_DOORBELL 0x09aa
+#define regSDMA1_RLC7_DOORBELL_BASE_IDX 0
+#define regSDMA1_RLC7_STATUS 0x09c0
+#define regSDMA1_RLC7_STATUS_BASE_IDX 0
+#define regSDMA1_RLC7_DOORBELL_LOG 0x09c1
+#define regSDMA1_RLC7_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA1_RLC7_WATERMARK 0x09c2
+#define regSDMA1_RLC7_WATERMARK_BASE_IDX 0
+#define regSDMA1_RLC7_DOORBELL_OFFSET 0x09c3
+#define regSDMA1_RLC7_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA1_RLC7_CSA_ADDR_LO 0x09c4
+#define regSDMA1_RLC7_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA1_RLC7_CSA_ADDR_HI 0x09c5
+#define regSDMA1_RLC7_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA1_RLC7_IB_SUB_REMAIN 0x09c7
+#define regSDMA1_RLC7_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA1_RLC7_PREEMPT 0x09c8
+#define regSDMA1_RLC7_PREEMPT_BASE_IDX 0
+#define regSDMA1_RLC7_DUMMY_REG 0x09c9
+#define regSDMA1_RLC7_DUMMY_REG_BASE_IDX 0
+#define regSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI 0x09ca
+#define regSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO 0x09cb
+#define regSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA1_RLC7_RB_AQL_CNTL 0x09cc
+#define regSDMA1_RLC7_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA1_RLC7_MINOR_PTR_UPDATE 0x09cd
+#define regSDMA1_RLC7_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA1_RLC7_MIDCMD_DATA0 0x09d8
+#define regSDMA1_RLC7_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA1_RLC7_MIDCMD_DATA1 0x09d9
+#define regSDMA1_RLC7_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA1_RLC7_MIDCMD_DATA2 0x09da
+#define regSDMA1_RLC7_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA1_RLC7_MIDCMD_DATA3 0x09db
+#define regSDMA1_RLC7_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA1_RLC7_MIDCMD_DATA4 0x09dc
+#define regSDMA1_RLC7_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA1_RLC7_MIDCMD_DATA5 0x09dd
+#define regSDMA1_RLC7_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA1_RLC7_MIDCMD_DATA6 0x09de
+#define regSDMA1_RLC7_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA1_RLC7_MIDCMD_DATA7 0x09df
+#define regSDMA1_RLC7_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA1_RLC7_MIDCMD_DATA8 0x09e0
+#define regSDMA1_RLC7_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA1_RLC7_MIDCMD_DATA9 0x09e1
+#define regSDMA1_RLC7_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA1_RLC7_MIDCMD_DATA10 0x09e2
+#define regSDMA1_RLC7_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA1_RLC7_MIDCMD_CNTL 0x09e3
+#define regSDMA1_RLC7_MIDCMD_CNTL_BASE_IDX 0
+
+
+// addressBlock: sdma0_sdma2dec
+// base address: 0x78000
+#define regSDMA2_UCODE_ADDR 0x1cda0
+#define regSDMA2_UCODE_ADDR_BASE_IDX 0
+#define regSDMA2_UCODE_DATA 0x1cda1
+#define regSDMA2_UCODE_DATA_BASE_IDX 0
+#define regSDMA2_VF_ENABLE 0x1cdaa
+#define regSDMA2_VF_ENABLE_BASE_IDX 0
+#define regSDMA2_CONTEXT_GROUP_BOUNDARY 0x1cdb9
+#define regSDMA2_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0
+#define regSDMA2_POWER_CNTL 0x1cdba
+#define regSDMA2_POWER_CNTL_BASE_IDX 0
+#define regSDMA2_CLK_CTRL 0x1cdbb
+#define regSDMA2_CLK_CTRL_BASE_IDX 0
+#define regSDMA2_CNTL 0x1cdbc
+#define regSDMA2_CNTL_BASE_IDX 0
+#define regSDMA2_CHICKEN_BITS 0x1cdbd
+#define regSDMA2_CHICKEN_BITS_BASE_IDX 0
+#define regSDMA2_GB_ADDR_CONFIG 0x1cdbe
+#define regSDMA2_GB_ADDR_CONFIG_BASE_IDX 0
+#define regSDMA2_GB_ADDR_CONFIG_READ 0x1cdbf
+#define regSDMA2_GB_ADDR_CONFIG_READ_BASE_IDX 0
+#define regSDMA2_RB_RPTR_FETCH_HI 0x1cdc0
+#define regSDMA2_RB_RPTR_FETCH_HI_BASE_IDX 0
+#define regSDMA2_SEM_WAIT_FAIL_TIMER_CNTL 0x1cdc1
+#define regSDMA2_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0
+#define regSDMA2_RB_RPTR_FETCH 0x1cdc2
+#define regSDMA2_RB_RPTR_FETCH_BASE_IDX 0
+#define regSDMA2_IB_OFFSET_FETCH 0x1cdc3
+#define regSDMA2_IB_OFFSET_FETCH_BASE_IDX 0
+#define regSDMA2_PROGRAM 0x1cdc4
+#define regSDMA2_PROGRAM_BASE_IDX 0
+#define regSDMA2_STATUS_REG 0x1cdc5
+#define regSDMA2_STATUS_REG_BASE_IDX 0
+#define regSDMA2_STATUS1_REG 0x1cdc6
+#define regSDMA2_STATUS1_REG_BASE_IDX 0
+#define regSDMA2_RD_BURST_CNTL 0x1cdc7
+#define regSDMA2_RD_BURST_CNTL_BASE_IDX 0
+#define regSDMA2_HBM_PAGE_CONFIG 0x1cdc8
+#define regSDMA2_HBM_PAGE_CONFIG_BASE_IDX 0
+#define regSDMA2_UCODE_CHECKSUM 0x1cdc9
+#define regSDMA2_UCODE_CHECKSUM_BASE_IDX 0
+#define regSDMA2_F32_CNTL 0x1cdca
+#define regSDMA2_F32_CNTL_BASE_IDX 0
+#define regSDMA2_FREEZE 0x1cdcb
+#define regSDMA2_FREEZE_BASE_IDX 0
+#define regSDMA2_PHASE0_QUANTUM 0x1cdcc
+#define regSDMA2_PHASE0_QUANTUM_BASE_IDX 0
+#define regSDMA2_PHASE1_QUANTUM 0x1cdcd
+#define regSDMA2_PHASE1_QUANTUM_BASE_IDX 0
+#define regCC_SDMA2_EDC_CONFIG 0x1cdd2
+#define regCC_SDMA2_EDC_CONFIG_BASE_IDX 0
+#define regSDMA2_BA_THRESHOLD 0x1cdd3
+#define regSDMA2_BA_THRESHOLD_BASE_IDX 0
+#define regSDMA2_ID 0x1cdd4
+#define regSDMA2_ID_BASE_IDX 0
+#define regSDMA2_VERSION 0x1cdd5
+#define regSDMA2_VERSION_BASE_IDX 0
+#define regSDMA2_EDC_COUNTER 0x1cdd6
+#define regSDMA2_EDC_COUNTER_BASE_IDX 0
+#define regSDMA2_EDC_COUNTER2 0x1cdd7
+#define regSDMA2_EDC_COUNTER2_BASE_IDX 0
+#define regSDMA2_STATUS2_REG 0x1cdd8
+#define regSDMA2_STATUS2_REG_BASE_IDX 0
+#define regSDMA2_ATOMIC_CNTL 0x1cdd9
+#define regSDMA2_ATOMIC_CNTL_BASE_IDX 0
+#define regSDMA2_ATOMIC_PREOP_LO 0x1cdda
+#define regSDMA2_ATOMIC_PREOP_LO_BASE_IDX 0
+#define regSDMA2_ATOMIC_PREOP_HI 0x1cddb
+#define regSDMA2_ATOMIC_PREOP_HI_BASE_IDX 0
+#define regSDMA2_UTCL1_CNTL 0x1cddc
+#define regSDMA2_UTCL1_CNTL_BASE_IDX 0
+#define regSDMA2_UTCL1_WATERMK 0x1cddd
+#define regSDMA2_UTCL1_WATERMK_BASE_IDX 0
+#define regSDMA2_UTCL1_RD_STATUS 0x1cdde
+#define regSDMA2_UTCL1_RD_STATUS_BASE_IDX 0
+#define regSDMA2_UTCL1_WR_STATUS 0x1cddf
+#define regSDMA2_UTCL1_WR_STATUS_BASE_IDX 0
+#define regSDMA2_UTCL1_INV0 0x1cde0
+#define regSDMA2_UTCL1_INV0_BASE_IDX 0
+#define regSDMA2_UTCL1_INV1 0x1cde1
+#define regSDMA2_UTCL1_INV1_BASE_IDX 0
+#define regSDMA2_UTCL1_INV2 0x1cde2
+#define regSDMA2_UTCL1_INV2_BASE_IDX 0
+#define regSDMA2_UTCL1_RD_XNACK0 0x1cde3
+#define regSDMA2_UTCL1_RD_XNACK0_BASE_IDX 0
+#define regSDMA2_UTCL1_RD_XNACK1 0x1cde4
+#define regSDMA2_UTCL1_RD_XNACK1_BASE_IDX 0
+#define regSDMA2_UTCL1_WR_XNACK0 0x1cde5
+#define regSDMA2_UTCL1_WR_XNACK0_BASE_IDX 0
+#define regSDMA2_UTCL1_WR_XNACK1 0x1cde6
+#define regSDMA2_UTCL1_WR_XNACK1_BASE_IDX 0
+#define regSDMA2_UTCL1_TIMEOUT 0x1cde7
+#define regSDMA2_UTCL1_TIMEOUT_BASE_IDX 0
+#define regSDMA2_UTCL1_PAGE 0x1cde8
+#define regSDMA2_UTCL1_PAGE_BASE_IDX 0
+#define regSDMA2_POWER_CNTL_IDLE 0x1cde9
+#define regSDMA2_POWER_CNTL_IDLE_BASE_IDX 0
+#define regSDMA2_RELAX_ORDERING_LUT 0x1cdea
+#define regSDMA2_RELAX_ORDERING_LUT_BASE_IDX 0
+#define regSDMA2_CHICKEN_BITS_2 0x1cdeb
+#define regSDMA2_CHICKEN_BITS_2_BASE_IDX 0
+#define regSDMA2_STATUS3_REG 0x1cdec
+#define regSDMA2_STATUS3_REG_BASE_IDX 0
+#define regSDMA2_PHYSICAL_ADDR_LO 0x1cded
+#define regSDMA2_PHYSICAL_ADDR_LO_BASE_IDX 0
+#define regSDMA2_PHYSICAL_ADDR_HI 0x1cdee
+#define regSDMA2_PHYSICAL_ADDR_HI_BASE_IDX 0
+#define regSDMA2_PHASE2_QUANTUM 0x1cdef
+#define regSDMA2_PHASE2_QUANTUM_BASE_IDX 0
+#define regSDMA2_ERROR_LOG 0x1cdf0
+#define regSDMA2_ERROR_LOG_BASE_IDX 0
+#define regSDMA2_PUB_DUMMY_REG0 0x1cdf1
+#define regSDMA2_PUB_DUMMY_REG0_BASE_IDX 0
+#define regSDMA2_PUB_DUMMY_REG1 0x1cdf2
+#define regSDMA2_PUB_DUMMY_REG1_BASE_IDX 0
+#define regSDMA2_PUB_DUMMY_REG2 0x1cdf3
+#define regSDMA2_PUB_DUMMY_REG2_BASE_IDX 0
+#define regSDMA2_PUB_DUMMY_REG3 0x1cdf4
+#define regSDMA2_PUB_DUMMY_REG3_BASE_IDX 0
+#define regSDMA2_F32_COUNTER 0x1cdf5
+#define regSDMA2_F32_COUNTER_BASE_IDX 0
+#define regSDMA2_PERFCNT_PERFCOUNTER0_CFG 0x1cdf7
+#define regSDMA2_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX 0
+#define regSDMA2_PERFCNT_PERFCOUNTER1_CFG 0x1cdf8
+#define regSDMA2_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX 0
+#define regSDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x1cdf9
+#define regSDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+#define regSDMA2_PERFCNT_MISC_CNTL 0x1cdfa
+#define regSDMA2_PERFCNT_MISC_CNTL_BASE_IDX 0
+#define regSDMA2_PERFCNT_PERFCOUNTER_LO 0x1cdfb
+#define regSDMA2_PERFCNT_PERFCOUNTER_LO_BASE_IDX 0
+#define regSDMA2_PERFCNT_PERFCOUNTER_HI 0x1cdfc
+#define regSDMA2_PERFCNT_PERFCOUNTER_HI_BASE_IDX 0
+#define regSDMA2_CRD_CNTL 0x1cdfd
+#define regSDMA2_CRD_CNTL_BASE_IDX 0
+#define regSDMA2_ULV_CNTL 0x1cdff
+#define regSDMA2_ULV_CNTL_BASE_IDX 0
+#define regSDMA2_EA_DBIT_ADDR_DATA 0x1ce00
+#define regSDMA2_EA_DBIT_ADDR_DATA_BASE_IDX 0
+#define regSDMA2_EA_DBIT_ADDR_INDEX 0x1ce01
+#define regSDMA2_EA_DBIT_ADDR_INDEX_BASE_IDX 0
+#define regSDMA2_STATUS4_REG 0x1ce03
+#define regSDMA2_STATUS4_REG_BASE_IDX 0
+#define regSDMA2_SCRATCH_RAM_DATA 0x1ce04
+#define regSDMA2_SCRATCH_RAM_DATA_BASE_IDX 0
+#define regSDMA2_SCRATCH_RAM_ADDR 0x1ce05
+#define regSDMA2_SCRATCH_RAM_ADDR_BASE_IDX 0
+#define regSDMA2_CE_CTRL 0x1ce06
+#define regSDMA2_CE_CTRL_BASE_IDX 0
+#define regSDMA2_RAS_STATUS 0x1ce07
+#define regSDMA2_RAS_STATUS_BASE_IDX 0
+#define regSDMA2_CLK_STATUS 0x1ce08
+#define regSDMA2_CLK_STATUS_BASE_IDX 0
+#define regSDMA2_GFX_RB_CNTL 0x1ce20
+#define regSDMA2_GFX_RB_CNTL_BASE_IDX 0
+#define regSDMA2_GFX_RB_BASE 0x1ce21
+#define regSDMA2_GFX_RB_BASE_BASE_IDX 0
+#define regSDMA2_GFX_RB_BASE_HI 0x1ce22
+#define regSDMA2_GFX_RB_BASE_HI_BASE_IDX 0
+#define regSDMA2_GFX_RB_RPTR 0x1ce23
+#define regSDMA2_GFX_RB_RPTR_BASE_IDX 0
+#define regSDMA2_GFX_RB_RPTR_HI 0x1ce24
+#define regSDMA2_GFX_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA2_GFX_RB_WPTR 0x1ce25
+#define regSDMA2_GFX_RB_WPTR_BASE_IDX 0
+#define regSDMA2_GFX_RB_WPTR_HI 0x1ce26
+#define regSDMA2_GFX_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA2_GFX_RB_WPTR_POLL_CNTL 0x1ce27
+#define regSDMA2_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA2_GFX_RB_RPTR_ADDR_HI 0x1ce28
+#define regSDMA2_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA2_GFX_RB_RPTR_ADDR_LO 0x1ce29
+#define regSDMA2_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA2_GFX_IB_CNTL 0x1ce2a
+#define regSDMA2_GFX_IB_CNTL_BASE_IDX 0
+#define regSDMA2_GFX_IB_RPTR 0x1ce2b
+#define regSDMA2_GFX_IB_RPTR_BASE_IDX 0
+#define regSDMA2_GFX_IB_OFFSET 0x1ce2c
+#define regSDMA2_GFX_IB_OFFSET_BASE_IDX 0
+#define regSDMA2_GFX_IB_BASE_LO 0x1ce2d
+#define regSDMA2_GFX_IB_BASE_LO_BASE_IDX 0
+#define regSDMA2_GFX_IB_BASE_HI 0x1ce2e
+#define regSDMA2_GFX_IB_BASE_HI_BASE_IDX 0
+#define regSDMA2_GFX_IB_SIZE 0x1ce2f
+#define regSDMA2_GFX_IB_SIZE_BASE_IDX 0
+#define regSDMA2_GFX_SKIP_CNTL 0x1ce30
+#define regSDMA2_GFX_SKIP_CNTL_BASE_IDX 0
+#define regSDMA2_GFX_CONTEXT_STATUS 0x1ce31
+#define regSDMA2_GFX_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA2_GFX_DOORBELL 0x1ce32
+#define regSDMA2_GFX_DOORBELL_BASE_IDX 0
+#define regSDMA2_GFX_CONTEXT_CNTL 0x1ce33
+#define regSDMA2_GFX_CONTEXT_CNTL_BASE_IDX 0
+#define regSDMA2_GFX_STATUS 0x1ce48
+#define regSDMA2_GFX_STATUS_BASE_IDX 0
+#define regSDMA2_GFX_DOORBELL_LOG 0x1ce49
+#define regSDMA2_GFX_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA2_GFX_WATERMARK 0x1ce4a
+#define regSDMA2_GFX_WATERMARK_BASE_IDX 0
+#define regSDMA2_GFX_DOORBELL_OFFSET 0x1ce4b
+#define regSDMA2_GFX_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA2_GFX_CSA_ADDR_LO 0x1ce4c
+#define regSDMA2_GFX_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA2_GFX_CSA_ADDR_HI 0x1ce4d
+#define regSDMA2_GFX_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA2_GFX_IB_SUB_REMAIN 0x1ce4f
+#define regSDMA2_GFX_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA2_GFX_PREEMPT 0x1ce50
+#define regSDMA2_GFX_PREEMPT_BASE_IDX 0
+#define regSDMA2_GFX_DUMMY_REG 0x1ce51
+#define regSDMA2_GFX_DUMMY_REG_BASE_IDX 0
+#define regSDMA2_GFX_RB_WPTR_POLL_ADDR_HI 0x1ce52
+#define regSDMA2_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA2_GFX_RB_WPTR_POLL_ADDR_LO 0x1ce53
+#define regSDMA2_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA2_GFX_RB_AQL_CNTL 0x1ce54
+#define regSDMA2_GFX_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA2_GFX_MINOR_PTR_UPDATE 0x1ce55
+#define regSDMA2_GFX_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA2_GFX_MIDCMD_DATA0 0x1ce60
+#define regSDMA2_GFX_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA2_GFX_MIDCMD_DATA1 0x1ce61
+#define regSDMA2_GFX_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA2_GFX_MIDCMD_DATA2 0x1ce62
+#define regSDMA2_GFX_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA2_GFX_MIDCMD_DATA3 0x1ce63
+#define regSDMA2_GFX_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA2_GFX_MIDCMD_DATA4 0x1ce64
+#define regSDMA2_GFX_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA2_GFX_MIDCMD_DATA5 0x1ce65
+#define regSDMA2_GFX_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA2_GFX_MIDCMD_DATA6 0x1ce66
+#define regSDMA2_GFX_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA2_GFX_MIDCMD_DATA7 0x1ce67
+#define regSDMA2_GFX_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA2_GFX_MIDCMD_DATA8 0x1ce68
+#define regSDMA2_GFX_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA2_GFX_MIDCMD_DATA9 0x1ce69
+#define regSDMA2_GFX_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA2_GFX_MIDCMD_DATA10 0x1ce6a
+#define regSDMA2_GFX_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA2_GFX_MIDCMD_CNTL 0x1ce6b
+#define regSDMA2_GFX_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA2_PAGE_RB_CNTL 0x1ce78
+#define regSDMA2_PAGE_RB_CNTL_BASE_IDX 0
+#define regSDMA2_PAGE_RB_BASE 0x1ce79
+#define regSDMA2_PAGE_RB_BASE_BASE_IDX 0
+#define regSDMA2_PAGE_RB_BASE_HI 0x1ce7a
+#define regSDMA2_PAGE_RB_BASE_HI_BASE_IDX 0
+#define regSDMA2_PAGE_RB_RPTR 0x1ce7b
+#define regSDMA2_PAGE_RB_RPTR_BASE_IDX 0
+#define regSDMA2_PAGE_RB_RPTR_HI 0x1ce7c
+#define regSDMA2_PAGE_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA2_PAGE_RB_WPTR 0x1ce7d
+#define regSDMA2_PAGE_RB_WPTR_BASE_IDX 0
+#define regSDMA2_PAGE_RB_WPTR_HI 0x1ce7e
+#define regSDMA2_PAGE_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA2_PAGE_RB_WPTR_POLL_CNTL 0x1ce7f
+#define regSDMA2_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA2_PAGE_RB_RPTR_ADDR_HI 0x1ce80
+#define regSDMA2_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA2_PAGE_RB_RPTR_ADDR_LO 0x1ce81
+#define regSDMA2_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA2_PAGE_IB_CNTL 0x1ce82
+#define regSDMA2_PAGE_IB_CNTL_BASE_IDX 0
+#define regSDMA2_PAGE_IB_RPTR 0x1ce83
+#define regSDMA2_PAGE_IB_RPTR_BASE_IDX 0
+#define regSDMA2_PAGE_IB_OFFSET 0x1ce84
+#define regSDMA2_PAGE_IB_OFFSET_BASE_IDX 0
+#define regSDMA2_PAGE_IB_BASE_LO 0x1ce85
+#define regSDMA2_PAGE_IB_BASE_LO_BASE_IDX 0
+#define regSDMA2_PAGE_IB_BASE_HI 0x1ce86
+#define regSDMA2_PAGE_IB_BASE_HI_BASE_IDX 0
+#define regSDMA2_PAGE_IB_SIZE 0x1ce87
+#define regSDMA2_PAGE_IB_SIZE_BASE_IDX 0
+#define regSDMA2_PAGE_SKIP_CNTL 0x1ce88
+#define regSDMA2_PAGE_SKIP_CNTL_BASE_IDX 0
+#define regSDMA2_PAGE_CONTEXT_STATUS 0x1ce89
+#define regSDMA2_PAGE_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA2_PAGE_DOORBELL 0x1ce8a
+#define regSDMA2_PAGE_DOORBELL_BASE_IDX 0
+#define regSDMA2_PAGE_STATUS 0x1cea0
+#define regSDMA2_PAGE_STATUS_BASE_IDX 0
+#define regSDMA2_PAGE_DOORBELL_LOG 0x1cea1
+#define regSDMA2_PAGE_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA2_PAGE_WATERMARK 0x1cea2
+#define regSDMA2_PAGE_WATERMARK_BASE_IDX 0
+#define regSDMA2_PAGE_DOORBELL_OFFSET 0x1cea3
+#define regSDMA2_PAGE_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA2_PAGE_CSA_ADDR_LO 0x1cea4
+#define regSDMA2_PAGE_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA2_PAGE_CSA_ADDR_HI 0x1cea5
+#define regSDMA2_PAGE_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA2_PAGE_IB_SUB_REMAIN 0x1cea7
+#define regSDMA2_PAGE_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA2_PAGE_PREEMPT 0x1cea8
+#define regSDMA2_PAGE_PREEMPT_BASE_IDX 0
+#define regSDMA2_PAGE_DUMMY_REG 0x1cea9
+#define regSDMA2_PAGE_DUMMY_REG_BASE_IDX 0
+#define regSDMA2_PAGE_RB_WPTR_POLL_ADDR_HI 0x1ceaa
+#define regSDMA2_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA2_PAGE_RB_WPTR_POLL_ADDR_LO 0x1ceab
+#define regSDMA2_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA2_PAGE_RB_AQL_CNTL 0x1ceac
+#define regSDMA2_PAGE_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA2_PAGE_MINOR_PTR_UPDATE 0x1cead
+#define regSDMA2_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA2_PAGE_MIDCMD_DATA0 0x1ceb8
+#define regSDMA2_PAGE_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA2_PAGE_MIDCMD_DATA1 0x1ceb9
+#define regSDMA2_PAGE_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA2_PAGE_MIDCMD_DATA2 0x1ceba
+#define regSDMA2_PAGE_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA2_PAGE_MIDCMD_DATA3 0x1cebb
+#define regSDMA2_PAGE_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA2_PAGE_MIDCMD_DATA4 0x1cebc
+#define regSDMA2_PAGE_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA2_PAGE_MIDCMD_DATA5 0x1cebd
+#define regSDMA2_PAGE_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA2_PAGE_MIDCMD_DATA6 0x1cebe
+#define regSDMA2_PAGE_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA2_PAGE_MIDCMD_DATA7 0x1cebf
+#define regSDMA2_PAGE_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA2_PAGE_MIDCMD_DATA8 0x1cec0
+#define regSDMA2_PAGE_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA2_PAGE_MIDCMD_DATA9 0x1cec1
+#define regSDMA2_PAGE_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA2_PAGE_MIDCMD_DATA10 0x1cec2
+#define regSDMA2_PAGE_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA2_PAGE_MIDCMD_CNTL 0x1cec3
+#define regSDMA2_PAGE_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA2_RLC0_RB_CNTL 0x1ced0
+#define regSDMA2_RLC0_RB_CNTL_BASE_IDX 0
+#define regSDMA2_RLC0_RB_BASE 0x1ced1
+#define regSDMA2_RLC0_RB_BASE_BASE_IDX 0
+#define regSDMA2_RLC0_RB_BASE_HI 0x1ced2
+#define regSDMA2_RLC0_RB_BASE_HI_BASE_IDX 0
+#define regSDMA2_RLC0_RB_RPTR 0x1ced3
+#define regSDMA2_RLC0_RB_RPTR_BASE_IDX 0
+#define regSDMA2_RLC0_RB_RPTR_HI 0x1ced4
+#define regSDMA2_RLC0_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA2_RLC0_RB_WPTR 0x1ced5
+#define regSDMA2_RLC0_RB_WPTR_BASE_IDX 0
+#define regSDMA2_RLC0_RB_WPTR_HI 0x1ced6
+#define regSDMA2_RLC0_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA2_RLC0_RB_WPTR_POLL_CNTL 0x1ced7
+#define regSDMA2_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA2_RLC0_RB_RPTR_ADDR_HI 0x1ced8
+#define regSDMA2_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA2_RLC0_RB_RPTR_ADDR_LO 0x1ced9
+#define regSDMA2_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA2_RLC0_IB_CNTL 0x1ceda
+#define regSDMA2_RLC0_IB_CNTL_BASE_IDX 0
+#define regSDMA2_RLC0_IB_RPTR 0x1cedb
+#define regSDMA2_RLC0_IB_RPTR_BASE_IDX 0
+#define regSDMA2_RLC0_IB_OFFSET 0x1cedc
+#define regSDMA2_RLC0_IB_OFFSET_BASE_IDX 0
+#define regSDMA2_RLC0_IB_BASE_LO 0x1cedd
+#define regSDMA2_RLC0_IB_BASE_LO_BASE_IDX 0
+#define regSDMA2_RLC0_IB_BASE_HI 0x1cede
+#define regSDMA2_RLC0_IB_BASE_HI_BASE_IDX 0
+#define regSDMA2_RLC0_IB_SIZE 0x1cedf
+#define regSDMA2_RLC0_IB_SIZE_BASE_IDX 0
+#define regSDMA2_RLC0_SKIP_CNTL 0x1cee0
+#define regSDMA2_RLC0_SKIP_CNTL_BASE_IDX 0
+#define regSDMA2_RLC0_CONTEXT_STATUS 0x1cee1
+#define regSDMA2_RLC0_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA2_RLC0_DOORBELL 0x1cee2
+#define regSDMA2_RLC0_DOORBELL_BASE_IDX 0
+#define regSDMA2_RLC0_STATUS 0x1cef8
+#define regSDMA2_RLC0_STATUS_BASE_IDX 0
+#define regSDMA2_RLC0_DOORBELL_LOG 0x1cef9
+#define regSDMA2_RLC0_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA2_RLC0_WATERMARK 0x1cefa
+#define regSDMA2_RLC0_WATERMARK_BASE_IDX 0
+#define regSDMA2_RLC0_DOORBELL_OFFSET 0x1cefb
+#define regSDMA2_RLC0_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA2_RLC0_CSA_ADDR_LO 0x1cefc
+#define regSDMA2_RLC0_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA2_RLC0_CSA_ADDR_HI 0x1cefd
+#define regSDMA2_RLC0_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA2_RLC0_IB_SUB_REMAIN 0x1ceff
+#define regSDMA2_RLC0_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA2_RLC0_PREEMPT 0x1cf00
+#define regSDMA2_RLC0_PREEMPT_BASE_IDX 0
+#define regSDMA2_RLC0_DUMMY_REG 0x1cf01
+#define regSDMA2_RLC0_DUMMY_REG_BASE_IDX 0
+#define regSDMA2_RLC0_RB_WPTR_POLL_ADDR_HI 0x1cf02
+#define regSDMA2_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA2_RLC0_RB_WPTR_POLL_ADDR_LO 0x1cf03
+#define regSDMA2_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA2_RLC0_RB_AQL_CNTL 0x1cf04
+#define regSDMA2_RLC0_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA2_RLC0_MINOR_PTR_UPDATE 0x1cf05
+#define regSDMA2_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA2_RLC0_MIDCMD_DATA0 0x1cf10
+#define regSDMA2_RLC0_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA2_RLC0_MIDCMD_DATA1 0x1cf11
+#define regSDMA2_RLC0_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA2_RLC0_MIDCMD_DATA2 0x1cf12
+#define regSDMA2_RLC0_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA2_RLC0_MIDCMD_DATA3 0x1cf13
+#define regSDMA2_RLC0_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA2_RLC0_MIDCMD_DATA4 0x1cf14
+#define regSDMA2_RLC0_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA2_RLC0_MIDCMD_DATA5 0x1cf15
+#define regSDMA2_RLC0_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA2_RLC0_MIDCMD_DATA6 0x1cf16
+#define regSDMA2_RLC0_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA2_RLC0_MIDCMD_DATA7 0x1cf17
+#define regSDMA2_RLC0_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA2_RLC0_MIDCMD_DATA8 0x1cf18
+#define regSDMA2_RLC0_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA2_RLC0_MIDCMD_DATA9 0x1cf19
+#define regSDMA2_RLC0_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA2_RLC0_MIDCMD_DATA10 0x1cf1a
+#define regSDMA2_RLC0_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA2_RLC0_MIDCMD_CNTL 0x1cf1b
+#define regSDMA2_RLC0_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA2_RLC1_RB_CNTL 0x1cf28
+#define regSDMA2_RLC1_RB_CNTL_BASE_IDX 0
+#define regSDMA2_RLC1_RB_BASE 0x1cf29
+#define regSDMA2_RLC1_RB_BASE_BASE_IDX 0
+#define regSDMA2_RLC1_RB_BASE_HI 0x1cf2a
+#define regSDMA2_RLC1_RB_BASE_HI_BASE_IDX 0
+#define regSDMA2_RLC1_RB_RPTR 0x1cf2b
+#define regSDMA2_RLC1_RB_RPTR_BASE_IDX 0
+#define regSDMA2_RLC1_RB_RPTR_HI 0x1cf2c
+#define regSDMA2_RLC1_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA2_RLC1_RB_WPTR 0x1cf2d
+#define regSDMA2_RLC1_RB_WPTR_BASE_IDX 0
+#define regSDMA2_RLC1_RB_WPTR_HI 0x1cf2e
+#define regSDMA2_RLC1_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA2_RLC1_RB_WPTR_POLL_CNTL 0x1cf2f
+#define regSDMA2_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA2_RLC1_RB_RPTR_ADDR_HI 0x1cf30
+#define regSDMA2_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA2_RLC1_RB_RPTR_ADDR_LO 0x1cf31
+#define regSDMA2_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA2_RLC1_IB_CNTL 0x1cf32
+#define regSDMA2_RLC1_IB_CNTL_BASE_IDX 0
+#define regSDMA2_RLC1_IB_RPTR 0x1cf33
+#define regSDMA2_RLC1_IB_RPTR_BASE_IDX 0
+#define regSDMA2_RLC1_IB_OFFSET 0x1cf34
+#define regSDMA2_RLC1_IB_OFFSET_BASE_IDX 0
+#define regSDMA2_RLC1_IB_BASE_LO 0x1cf35
+#define regSDMA2_RLC1_IB_BASE_LO_BASE_IDX 0
+#define regSDMA2_RLC1_IB_BASE_HI 0x1cf36
+#define regSDMA2_RLC1_IB_BASE_HI_BASE_IDX 0
+#define regSDMA2_RLC1_IB_SIZE 0x1cf37
+#define regSDMA2_RLC1_IB_SIZE_BASE_IDX 0
+#define regSDMA2_RLC1_SKIP_CNTL 0x1cf38
+#define regSDMA2_RLC1_SKIP_CNTL_BASE_IDX 0
+#define regSDMA2_RLC1_CONTEXT_STATUS 0x1cf39
+#define regSDMA2_RLC1_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA2_RLC1_DOORBELL 0x1cf3a
+#define regSDMA2_RLC1_DOORBELL_BASE_IDX 0
+#define regSDMA2_RLC1_STATUS 0x1cf50
+#define regSDMA2_RLC1_STATUS_BASE_IDX 0
+#define regSDMA2_RLC1_DOORBELL_LOG 0x1cf51
+#define regSDMA2_RLC1_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA2_RLC1_WATERMARK 0x1cf52
+#define regSDMA2_RLC1_WATERMARK_BASE_IDX 0
+#define regSDMA2_RLC1_DOORBELL_OFFSET 0x1cf53
+#define regSDMA2_RLC1_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA2_RLC1_CSA_ADDR_LO 0x1cf54
+#define regSDMA2_RLC1_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA2_RLC1_CSA_ADDR_HI 0x1cf55
+#define regSDMA2_RLC1_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA2_RLC1_IB_SUB_REMAIN 0x1cf57
+#define regSDMA2_RLC1_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA2_RLC1_PREEMPT 0x1cf58
+#define regSDMA2_RLC1_PREEMPT_BASE_IDX 0
+#define regSDMA2_RLC1_DUMMY_REG 0x1cf59
+#define regSDMA2_RLC1_DUMMY_REG_BASE_IDX 0
+#define regSDMA2_RLC1_RB_WPTR_POLL_ADDR_HI 0x1cf5a
+#define regSDMA2_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA2_RLC1_RB_WPTR_POLL_ADDR_LO 0x1cf5b
+#define regSDMA2_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA2_RLC1_RB_AQL_CNTL 0x1cf5c
+#define regSDMA2_RLC1_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA2_RLC1_MINOR_PTR_UPDATE 0x1cf5d
+#define regSDMA2_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA2_RLC1_MIDCMD_DATA0 0x1cf68
+#define regSDMA2_RLC1_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA2_RLC1_MIDCMD_DATA1 0x1cf69
+#define regSDMA2_RLC1_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA2_RLC1_MIDCMD_DATA2 0x1cf6a
+#define regSDMA2_RLC1_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA2_RLC1_MIDCMD_DATA3 0x1cf6b
+#define regSDMA2_RLC1_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA2_RLC1_MIDCMD_DATA4 0x1cf6c
+#define regSDMA2_RLC1_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA2_RLC1_MIDCMD_DATA5 0x1cf6d
+#define regSDMA2_RLC1_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA2_RLC1_MIDCMD_DATA6 0x1cf6e
+#define regSDMA2_RLC1_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA2_RLC1_MIDCMD_DATA7 0x1cf6f
+#define regSDMA2_RLC1_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA2_RLC1_MIDCMD_DATA8 0x1cf70
+#define regSDMA2_RLC1_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA2_RLC1_MIDCMD_DATA9 0x1cf71
+#define regSDMA2_RLC1_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA2_RLC1_MIDCMD_DATA10 0x1cf72
+#define regSDMA2_RLC1_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA2_RLC1_MIDCMD_CNTL 0x1cf73
+#define regSDMA2_RLC1_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA2_RLC2_RB_CNTL 0x1cf80
+#define regSDMA2_RLC2_RB_CNTL_BASE_IDX 0
+#define regSDMA2_RLC2_RB_BASE 0x1cf81
+#define regSDMA2_RLC2_RB_BASE_BASE_IDX 0
+#define regSDMA2_RLC2_RB_BASE_HI 0x1cf82
+#define regSDMA2_RLC2_RB_BASE_HI_BASE_IDX 0
+#define regSDMA2_RLC2_RB_RPTR 0x1cf83
+#define regSDMA2_RLC2_RB_RPTR_BASE_IDX 0
+#define regSDMA2_RLC2_RB_RPTR_HI 0x1cf84
+#define regSDMA2_RLC2_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA2_RLC2_RB_WPTR 0x1cf85
+#define regSDMA2_RLC2_RB_WPTR_BASE_IDX 0
+#define regSDMA2_RLC2_RB_WPTR_HI 0x1cf86
+#define regSDMA2_RLC2_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA2_RLC2_RB_WPTR_POLL_CNTL 0x1cf87
+#define regSDMA2_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA2_RLC2_RB_RPTR_ADDR_HI 0x1cf88
+#define regSDMA2_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA2_RLC2_RB_RPTR_ADDR_LO 0x1cf89
+#define regSDMA2_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA2_RLC2_IB_CNTL 0x1cf8a
+#define regSDMA2_RLC2_IB_CNTL_BASE_IDX 0
+#define regSDMA2_RLC2_IB_RPTR 0x1cf8b
+#define regSDMA2_RLC2_IB_RPTR_BASE_IDX 0
+#define regSDMA2_RLC2_IB_OFFSET 0x1cf8c
+#define regSDMA2_RLC2_IB_OFFSET_BASE_IDX 0
+#define regSDMA2_RLC2_IB_BASE_LO 0x1cf8d
+#define regSDMA2_RLC2_IB_BASE_LO_BASE_IDX 0
+#define regSDMA2_RLC2_IB_BASE_HI 0x1cf8e
+#define regSDMA2_RLC2_IB_BASE_HI_BASE_IDX 0
+#define regSDMA2_RLC2_IB_SIZE 0x1cf8f
+#define regSDMA2_RLC2_IB_SIZE_BASE_IDX 0
+#define regSDMA2_RLC2_SKIP_CNTL 0x1cf90
+#define regSDMA2_RLC2_SKIP_CNTL_BASE_IDX 0
+#define regSDMA2_RLC2_CONTEXT_STATUS 0x1cf91
+#define regSDMA2_RLC2_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA2_RLC2_DOORBELL 0x1cf92
+#define regSDMA2_RLC2_DOORBELL_BASE_IDX 0
+#define regSDMA2_RLC2_STATUS 0x1cfa8
+#define regSDMA2_RLC2_STATUS_BASE_IDX 0
+#define regSDMA2_RLC2_DOORBELL_LOG 0x1cfa9
+#define regSDMA2_RLC2_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA2_RLC2_WATERMARK 0x1cfaa
+#define regSDMA2_RLC2_WATERMARK_BASE_IDX 0
+#define regSDMA2_RLC2_DOORBELL_OFFSET 0x1cfab
+#define regSDMA2_RLC2_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA2_RLC2_CSA_ADDR_LO 0x1cfac
+#define regSDMA2_RLC2_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA2_RLC2_CSA_ADDR_HI 0x1cfad
+#define regSDMA2_RLC2_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA2_RLC2_IB_SUB_REMAIN 0x1cfaf
+#define regSDMA2_RLC2_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA2_RLC2_PREEMPT 0x1cfb0
+#define regSDMA2_RLC2_PREEMPT_BASE_IDX 0
+#define regSDMA2_RLC2_DUMMY_REG 0x1cfb1
+#define regSDMA2_RLC2_DUMMY_REG_BASE_IDX 0
+#define regSDMA2_RLC2_RB_WPTR_POLL_ADDR_HI 0x1cfb2
+#define regSDMA2_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA2_RLC2_RB_WPTR_POLL_ADDR_LO 0x1cfb3
+#define regSDMA2_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA2_RLC2_RB_AQL_CNTL 0x1cfb4
+#define regSDMA2_RLC2_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA2_RLC2_MINOR_PTR_UPDATE 0x1cfb5
+#define regSDMA2_RLC2_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA2_RLC2_MIDCMD_DATA0 0x1cfc0
+#define regSDMA2_RLC2_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA2_RLC2_MIDCMD_DATA1 0x1cfc1
+#define regSDMA2_RLC2_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA2_RLC2_MIDCMD_DATA2 0x1cfc2
+#define regSDMA2_RLC2_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA2_RLC2_MIDCMD_DATA3 0x1cfc3
+#define regSDMA2_RLC2_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA2_RLC2_MIDCMD_DATA4 0x1cfc4
+#define regSDMA2_RLC2_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA2_RLC2_MIDCMD_DATA5 0x1cfc5
+#define regSDMA2_RLC2_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA2_RLC2_MIDCMD_DATA6 0x1cfc6
+#define regSDMA2_RLC2_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA2_RLC2_MIDCMD_DATA7 0x1cfc7
+#define regSDMA2_RLC2_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA2_RLC2_MIDCMD_DATA8 0x1cfc8
+#define regSDMA2_RLC2_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA2_RLC2_MIDCMD_DATA9 0x1cfc9
+#define regSDMA2_RLC2_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA2_RLC2_MIDCMD_DATA10 0x1cfca
+#define regSDMA2_RLC2_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA2_RLC2_MIDCMD_CNTL 0x1cfcb
+#define regSDMA2_RLC2_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA2_RLC3_RB_CNTL 0x1cfd8
+#define regSDMA2_RLC3_RB_CNTL_BASE_IDX 0
+#define regSDMA2_RLC3_RB_BASE 0x1cfd9
+#define regSDMA2_RLC3_RB_BASE_BASE_IDX 0
+#define regSDMA2_RLC3_RB_BASE_HI 0x1cfda
+#define regSDMA2_RLC3_RB_BASE_HI_BASE_IDX 0
+#define regSDMA2_RLC3_RB_RPTR 0x1cfdb
+#define regSDMA2_RLC3_RB_RPTR_BASE_IDX 0
+#define regSDMA2_RLC3_RB_RPTR_HI 0x1cfdc
+#define regSDMA2_RLC3_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA2_RLC3_RB_WPTR 0x1cfdd
+#define regSDMA2_RLC3_RB_WPTR_BASE_IDX 0
+#define regSDMA2_RLC3_RB_WPTR_HI 0x1cfde
+#define regSDMA2_RLC3_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA2_RLC3_RB_WPTR_POLL_CNTL 0x1cfdf
+#define regSDMA2_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA2_RLC3_RB_RPTR_ADDR_HI 0x1cfe0
+#define regSDMA2_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA2_RLC3_RB_RPTR_ADDR_LO 0x1cfe1
+#define regSDMA2_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA2_RLC3_IB_CNTL 0x1cfe2
+#define regSDMA2_RLC3_IB_CNTL_BASE_IDX 0
+#define regSDMA2_RLC3_IB_RPTR 0x1cfe3
+#define regSDMA2_RLC3_IB_RPTR_BASE_IDX 0
+#define regSDMA2_RLC3_IB_OFFSET 0x1cfe4
+#define regSDMA2_RLC3_IB_OFFSET_BASE_IDX 0
+#define regSDMA2_RLC3_IB_BASE_LO 0x1cfe5
+#define regSDMA2_RLC3_IB_BASE_LO_BASE_IDX 0
+#define regSDMA2_RLC3_IB_BASE_HI 0x1cfe6
+#define regSDMA2_RLC3_IB_BASE_HI_BASE_IDX 0
+#define regSDMA2_RLC3_IB_SIZE 0x1cfe7
+#define regSDMA2_RLC3_IB_SIZE_BASE_IDX 0
+#define regSDMA2_RLC3_SKIP_CNTL 0x1cfe8
+#define regSDMA2_RLC3_SKIP_CNTL_BASE_IDX 0
+#define regSDMA2_RLC3_CONTEXT_STATUS 0x1cfe9
+#define regSDMA2_RLC3_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA2_RLC3_DOORBELL 0x1cfea
+#define regSDMA2_RLC3_DOORBELL_BASE_IDX 0
+#define regSDMA2_RLC3_STATUS 0x1d000
+#define regSDMA2_RLC3_STATUS_BASE_IDX 0
+#define regSDMA2_RLC3_DOORBELL_LOG 0x1d001
+#define regSDMA2_RLC3_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA2_RLC3_WATERMARK 0x1d002
+#define regSDMA2_RLC3_WATERMARK_BASE_IDX 0
+#define regSDMA2_RLC3_DOORBELL_OFFSET 0x1d003
+#define regSDMA2_RLC3_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA2_RLC3_CSA_ADDR_LO 0x1d004
+#define regSDMA2_RLC3_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA2_RLC3_CSA_ADDR_HI 0x1d005
+#define regSDMA2_RLC3_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA2_RLC3_IB_SUB_REMAIN 0x1d007
+#define regSDMA2_RLC3_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA2_RLC3_PREEMPT 0x1d008
+#define regSDMA2_RLC3_PREEMPT_BASE_IDX 0
+#define regSDMA2_RLC3_DUMMY_REG 0x1d009
+#define regSDMA2_RLC3_DUMMY_REG_BASE_IDX 0
+#define regSDMA2_RLC3_RB_WPTR_POLL_ADDR_HI 0x1d00a
+#define regSDMA2_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA2_RLC3_RB_WPTR_POLL_ADDR_LO 0x1d00b
+#define regSDMA2_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA2_RLC3_RB_AQL_CNTL 0x1d00c
+#define regSDMA2_RLC3_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA2_RLC3_MINOR_PTR_UPDATE 0x1d00d
+#define regSDMA2_RLC3_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA2_RLC3_MIDCMD_DATA0 0x1d018
+#define regSDMA2_RLC3_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA2_RLC3_MIDCMD_DATA1 0x1d019
+#define regSDMA2_RLC3_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA2_RLC3_MIDCMD_DATA2 0x1d01a
+#define regSDMA2_RLC3_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA2_RLC3_MIDCMD_DATA3 0x1d01b
+#define regSDMA2_RLC3_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA2_RLC3_MIDCMD_DATA4 0x1d01c
+#define regSDMA2_RLC3_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA2_RLC3_MIDCMD_DATA5 0x1d01d
+#define regSDMA2_RLC3_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA2_RLC3_MIDCMD_DATA6 0x1d01e
+#define regSDMA2_RLC3_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA2_RLC3_MIDCMD_DATA7 0x1d01f
+#define regSDMA2_RLC3_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA2_RLC3_MIDCMD_DATA8 0x1d020
+#define regSDMA2_RLC3_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA2_RLC3_MIDCMD_DATA9 0x1d021
+#define regSDMA2_RLC3_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA2_RLC3_MIDCMD_DATA10 0x1d022
+#define regSDMA2_RLC3_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA2_RLC3_MIDCMD_CNTL 0x1d023
+#define regSDMA2_RLC3_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA2_RLC4_RB_CNTL 0x1d030
+#define regSDMA2_RLC4_RB_CNTL_BASE_IDX 0
+#define regSDMA2_RLC4_RB_BASE 0x1d031
+#define regSDMA2_RLC4_RB_BASE_BASE_IDX 0
+#define regSDMA2_RLC4_RB_BASE_HI 0x1d032
+#define regSDMA2_RLC4_RB_BASE_HI_BASE_IDX 0
+#define regSDMA2_RLC4_RB_RPTR 0x1d033
+#define regSDMA2_RLC4_RB_RPTR_BASE_IDX 0
+#define regSDMA2_RLC4_RB_RPTR_HI 0x1d034
+#define regSDMA2_RLC4_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA2_RLC4_RB_WPTR 0x1d035
+#define regSDMA2_RLC4_RB_WPTR_BASE_IDX 0
+#define regSDMA2_RLC4_RB_WPTR_HI 0x1d036
+#define regSDMA2_RLC4_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA2_RLC4_RB_WPTR_POLL_CNTL 0x1d037
+#define regSDMA2_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA2_RLC4_RB_RPTR_ADDR_HI 0x1d038
+#define regSDMA2_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA2_RLC4_RB_RPTR_ADDR_LO 0x1d039
+#define regSDMA2_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA2_RLC4_IB_CNTL 0x1d03a
+#define regSDMA2_RLC4_IB_CNTL_BASE_IDX 0
+#define regSDMA2_RLC4_IB_RPTR 0x1d03b
+#define regSDMA2_RLC4_IB_RPTR_BASE_IDX 0
+#define regSDMA2_RLC4_IB_OFFSET 0x1d03c
+#define regSDMA2_RLC4_IB_OFFSET_BASE_IDX 0
+#define regSDMA2_RLC4_IB_BASE_LO 0x1d03d
+#define regSDMA2_RLC4_IB_BASE_LO_BASE_IDX 0
+#define regSDMA2_RLC4_IB_BASE_HI 0x1d03e
+#define regSDMA2_RLC4_IB_BASE_HI_BASE_IDX 0
+#define regSDMA2_RLC4_IB_SIZE 0x1d03f
+#define regSDMA2_RLC4_IB_SIZE_BASE_IDX 0
+#define regSDMA2_RLC4_SKIP_CNTL 0x1d040
+#define regSDMA2_RLC4_SKIP_CNTL_BASE_IDX 0
+#define regSDMA2_RLC4_CONTEXT_STATUS 0x1d041
+#define regSDMA2_RLC4_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA2_RLC4_DOORBELL 0x1d042
+#define regSDMA2_RLC4_DOORBELL_BASE_IDX 0
+#define regSDMA2_RLC4_STATUS 0x1d058
+#define regSDMA2_RLC4_STATUS_BASE_IDX 0
+#define regSDMA2_RLC4_DOORBELL_LOG 0x1d059
+#define regSDMA2_RLC4_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA2_RLC4_WATERMARK 0x1d05a
+#define regSDMA2_RLC4_WATERMARK_BASE_IDX 0
+#define regSDMA2_RLC4_DOORBELL_OFFSET 0x1d05b
+#define regSDMA2_RLC4_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA2_RLC4_CSA_ADDR_LO 0x1d05c
+#define regSDMA2_RLC4_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA2_RLC4_CSA_ADDR_HI 0x1d05d
+#define regSDMA2_RLC4_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA2_RLC4_IB_SUB_REMAIN 0x1d05f
+#define regSDMA2_RLC4_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA2_RLC4_PREEMPT 0x1d060
+#define regSDMA2_RLC4_PREEMPT_BASE_IDX 0
+#define regSDMA2_RLC4_DUMMY_REG 0x1d061
+#define regSDMA2_RLC4_DUMMY_REG_BASE_IDX 0
+#define regSDMA2_RLC4_RB_WPTR_POLL_ADDR_HI 0x1d062
+#define regSDMA2_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA2_RLC4_RB_WPTR_POLL_ADDR_LO 0x1d063
+#define regSDMA2_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA2_RLC4_RB_AQL_CNTL 0x1d064
+#define regSDMA2_RLC4_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA2_RLC4_MINOR_PTR_UPDATE 0x1d065
+#define regSDMA2_RLC4_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA2_RLC4_MIDCMD_DATA0 0x1d070
+#define regSDMA2_RLC4_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA2_RLC4_MIDCMD_DATA1 0x1d071
+#define regSDMA2_RLC4_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA2_RLC4_MIDCMD_DATA2 0x1d072
+#define regSDMA2_RLC4_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA2_RLC4_MIDCMD_DATA3 0x1d073
+#define regSDMA2_RLC4_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA2_RLC4_MIDCMD_DATA4 0x1d074
+#define regSDMA2_RLC4_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA2_RLC4_MIDCMD_DATA5 0x1d075
+#define regSDMA2_RLC4_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA2_RLC4_MIDCMD_DATA6 0x1d076
+#define regSDMA2_RLC4_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA2_RLC4_MIDCMD_DATA7 0x1d077
+#define regSDMA2_RLC4_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA2_RLC4_MIDCMD_DATA8 0x1d078
+#define regSDMA2_RLC4_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA2_RLC4_MIDCMD_DATA9 0x1d079
+#define regSDMA2_RLC4_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA2_RLC4_MIDCMD_DATA10 0x1d07a
+#define regSDMA2_RLC4_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA2_RLC4_MIDCMD_CNTL 0x1d07b
+#define regSDMA2_RLC4_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA2_RLC5_RB_CNTL 0x1d088
+#define regSDMA2_RLC5_RB_CNTL_BASE_IDX 0
+#define regSDMA2_RLC5_RB_BASE 0x1d089
+#define regSDMA2_RLC5_RB_BASE_BASE_IDX 0
+#define regSDMA2_RLC5_RB_BASE_HI 0x1d08a
+#define regSDMA2_RLC5_RB_BASE_HI_BASE_IDX 0
+#define regSDMA2_RLC5_RB_RPTR 0x1d08b
+#define regSDMA2_RLC5_RB_RPTR_BASE_IDX 0
+#define regSDMA2_RLC5_RB_RPTR_HI 0x1d08c
+#define regSDMA2_RLC5_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA2_RLC5_RB_WPTR 0x1d08d
+#define regSDMA2_RLC5_RB_WPTR_BASE_IDX 0
+#define regSDMA2_RLC5_RB_WPTR_HI 0x1d08e
+#define regSDMA2_RLC5_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA2_RLC5_RB_WPTR_POLL_CNTL 0x1d08f
+#define regSDMA2_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA2_RLC5_RB_RPTR_ADDR_HI 0x1d090
+#define regSDMA2_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA2_RLC5_RB_RPTR_ADDR_LO 0x1d091
+#define regSDMA2_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA2_RLC5_IB_CNTL 0x1d092
+#define regSDMA2_RLC5_IB_CNTL_BASE_IDX 0
+#define regSDMA2_RLC5_IB_RPTR 0x1d093
+#define regSDMA2_RLC5_IB_RPTR_BASE_IDX 0
+#define regSDMA2_RLC5_IB_OFFSET 0x1d094
+#define regSDMA2_RLC5_IB_OFFSET_BASE_IDX 0
+#define regSDMA2_RLC5_IB_BASE_LO 0x1d095
+#define regSDMA2_RLC5_IB_BASE_LO_BASE_IDX 0
+#define regSDMA2_RLC5_IB_BASE_HI 0x1d096
+#define regSDMA2_RLC5_IB_BASE_HI_BASE_IDX 0
+#define regSDMA2_RLC5_IB_SIZE 0x1d097
+#define regSDMA2_RLC5_IB_SIZE_BASE_IDX 0
+#define regSDMA2_RLC5_SKIP_CNTL 0x1d098
+#define regSDMA2_RLC5_SKIP_CNTL_BASE_IDX 0
+#define regSDMA2_RLC5_CONTEXT_STATUS 0x1d099
+#define regSDMA2_RLC5_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA2_RLC5_DOORBELL 0x1d09a
+#define regSDMA2_RLC5_DOORBELL_BASE_IDX 0
+#define regSDMA2_RLC5_STATUS 0x1d0b0
+#define regSDMA2_RLC5_STATUS_BASE_IDX 0
+#define regSDMA2_RLC5_DOORBELL_LOG 0x1d0b1
+#define regSDMA2_RLC5_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA2_RLC5_WATERMARK 0x1d0b2
+#define regSDMA2_RLC5_WATERMARK_BASE_IDX 0
+#define regSDMA2_RLC5_DOORBELL_OFFSET 0x1d0b3
+#define regSDMA2_RLC5_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA2_RLC5_CSA_ADDR_LO 0x1d0b4
+#define regSDMA2_RLC5_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA2_RLC5_CSA_ADDR_HI 0x1d0b5
+#define regSDMA2_RLC5_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA2_RLC5_IB_SUB_REMAIN 0x1d0b7
+#define regSDMA2_RLC5_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA2_RLC5_PREEMPT 0x1d0b8
+#define regSDMA2_RLC5_PREEMPT_BASE_IDX 0
+#define regSDMA2_RLC5_DUMMY_REG 0x1d0b9
+#define regSDMA2_RLC5_DUMMY_REG_BASE_IDX 0
+#define regSDMA2_RLC5_RB_WPTR_POLL_ADDR_HI 0x1d0ba
+#define regSDMA2_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA2_RLC5_RB_WPTR_POLL_ADDR_LO 0x1d0bb
+#define regSDMA2_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA2_RLC5_RB_AQL_CNTL 0x1d0bc
+#define regSDMA2_RLC5_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA2_RLC5_MINOR_PTR_UPDATE 0x1d0bd
+#define regSDMA2_RLC5_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA2_RLC5_MIDCMD_DATA0 0x1d0c8
+#define regSDMA2_RLC5_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA2_RLC5_MIDCMD_DATA1 0x1d0c9
+#define regSDMA2_RLC5_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA2_RLC5_MIDCMD_DATA2 0x1d0ca
+#define regSDMA2_RLC5_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA2_RLC5_MIDCMD_DATA3 0x1d0cb
+#define regSDMA2_RLC5_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA2_RLC5_MIDCMD_DATA4 0x1d0cc
+#define regSDMA2_RLC5_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA2_RLC5_MIDCMD_DATA5 0x1d0cd
+#define regSDMA2_RLC5_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA2_RLC5_MIDCMD_DATA6 0x1d0ce
+#define regSDMA2_RLC5_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA2_RLC5_MIDCMD_DATA7 0x1d0cf
+#define regSDMA2_RLC5_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA2_RLC5_MIDCMD_DATA8 0x1d0d0
+#define regSDMA2_RLC5_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA2_RLC5_MIDCMD_DATA9 0x1d0d1
+#define regSDMA2_RLC5_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA2_RLC5_MIDCMD_DATA10 0x1d0d2
+#define regSDMA2_RLC5_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA2_RLC5_MIDCMD_CNTL 0x1d0d3
+#define regSDMA2_RLC5_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA2_RLC6_RB_CNTL 0x1d0e0
+#define regSDMA2_RLC6_RB_CNTL_BASE_IDX 0
+#define regSDMA2_RLC6_RB_BASE 0x1d0e1
+#define regSDMA2_RLC6_RB_BASE_BASE_IDX 0
+#define regSDMA2_RLC6_RB_BASE_HI 0x1d0e2
+#define regSDMA2_RLC6_RB_BASE_HI_BASE_IDX 0
+#define regSDMA2_RLC6_RB_RPTR 0x1d0e3
+#define regSDMA2_RLC6_RB_RPTR_BASE_IDX 0
+#define regSDMA2_RLC6_RB_RPTR_HI 0x1d0e4
+#define regSDMA2_RLC6_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA2_RLC6_RB_WPTR 0x1d0e5
+#define regSDMA2_RLC6_RB_WPTR_BASE_IDX 0
+#define regSDMA2_RLC6_RB_WPTR_HI 0x1d0e6
+#define regSDMA2_RLC6_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA2_RLC6_RB_WPTR_POLL_CNTL 0x1d0e7
+#define regSDMA2_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA2_RLC6_RB_RPTR_ADDR_HI 0x1d0e8
+#define regSDMA2_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA2_RLC6_RB_RPTR_ADDR_LO 0x1d0e9
+#define regSDMA2_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA2_RLC6_IB_CNTL 0x1d0ea
+#define regSDMA2_RLC6_IB_CNTL_BASE_IDX 0
+#define regSDMA2_RLC6_IB_RPTR 0x1d0eb
+#define regSDMA2_RLC6_IB_RPTR_BASE_IDX 0
+#define regSDMA2_RLC6_IB_OFFSET 0x1d0ec
+#define regSDMA2_RLC6_IB_OFFSET_BASE_IDX 0
+#define regSDMA2_RLC6_IB_BASE_LO 0x1d0ed
+#define regSDMA2_RLC6_IB_BASE_LO_BASE_IDX 0
+#define regSDMA2_RLC6_IB_BASE_HI 0x1d0ee
+#define regSDMA2_RLC6_IB_BASE_HI_BASE_IDX 0
+#define regSDMA2_RLC6_IB_SIZE 0x1d0ef
+#define regSDMA2_RLC6_IB_SIZE_BASE_IDX 0
+#define regSDMA2_RLC6_SKIP_CNTL 0x1d0f0
+#define regSDMA2_RLC6_SKIP_CNTL_BASE_IDX 0
+#define regSDMA2_RLC6_CONTEXT_STATUS 0x1d0f1
+#define regSDMA2_RLC6_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA2_RLC6_DOORBELL 0x1d0f2
+#define regSDMA2_RLC6_DOORBELL_BASE_IDX 0
+#define regSDMA2_RLC6_STATUS 0x1d108
+#define regSDMA2_RLC6_STATUS_BASE_IDX 0
+#define regSDMA2_RLC6_DOORBELL_LOG 0x1d109
+#define regSDMA2_RLC6_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA2_RLC6_WATERMARK 0x1d10a
+#define regSDMA2_RLC6_WATERMARK_BASE_IDX 0
+#define regSDMA2_RLC6_DOORBELL_OFFSET 0x1d10b
+#define regSDMA2_RLC6_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA2_RLC6_CSA_ADDR_LO 0x1d10c
+#define regSDMA2_RLC6_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA2_RLC6_CSA_ADDR_HI 0x1d10d
+#define regSDMA2_RLC6_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA2_RLC6_IB_SUB_REMAIN 0x1d10f
+#define regSDMA2_RLC6_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA2_RLC6_PREEMPT 0x1d110
+#define regSDMA2_RLC6_PREEMPT_BASE_IDX 0
+#define regSDMA2_RLC6_DUMMY_REG 0x1d111
+#define regSDMA2_RLC6_DUMMY_REG_BASE_IDX 0
+#define regSDMA2_RLC6_RB_WPTR_POLL_ADDR_HI 0x1d112
+#define regSDMA2_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA2_RLC6_RB_WPTR_POLL_ADDR_LO 0x1d113
+#define regSDMA2_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA2_RLC6_RB_AQL_CNTL 0x1d114
+#define regSDMA2_RLC6_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA2_RLC6_MINOR_PTR_UPDATE 0x1d115
+#define regSDMA2_RLC6_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA2_RLC6_MIDCMD_DATA0 0x1d120
+#define regSDMA2_RLC6_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA2_RLC6_MIDCMD_DATA1 0x1d121
+#define regSDMA2_RLC6_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA2_RLC6_MIDCMD_DATA2 0x1d122
+#define regSDMA2_RLC6_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA2_RLC6_MIDCMD_DATA3 0x1d123
+#define regSDMA2_RLC6_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA2_RLC6_MIDCMD_DATA4 0x1d124
+#define regSDMA2_RLC6_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA2_RLC6_MIDCMD_DATA5 0x1d125
+#define regSDMA2_RLC6_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA2_RLC6_MIDCMD_DATA6 0x1d126
+#define regSDMA2_RLC6_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA2_RLC6_MIDCMD_DATA7 0x1d127
+#define regSDMA2_RLC6_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA2_RLC6_MIDCMD_DATA8 0x1d128
+#define regSDMA2_RLC6_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA2_RLC6_MIDCMD_DATA9 0x1d129
+#define regSDMA2_RLC6_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA2_RLC6_MIDCMD_DATA10 0x1d12a
+#define regSDMA2_RLC6_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA2_RLC6_MIDCMD_CNTL 0x1d12b
+#define regSDMA2_RLC6_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA2_RLC7_RB_CNTL 0x1d138
+#define regSDMA2_RLC7_RB_CNTL_BASE_IDX 0
+#define regSDMA2_RLC7_RB_BASE 0x1d139
+#define regSDMA2_RLC7_RB_BASE_BASE_IDX 0
+#define regSDMA2_RLC7_RB_BASE_HI 0x1d13a
+#define regSDMA2_RLC7_RB_BASE_HI_BASE_IDX 0
+#define regSDMA2_RLC7_RB_RPTR 0x1d13b
+#define regSDMA2_RLC7_RB_RPTR_BASE_IDX 0
+#define regSDMA2_RLC7_RB_RPTR_HI 0x1d13c
+#define regSDMA2_RLC7_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA2_RLC7_RB_WPTR 0x1d13d
+#define regSDMA2_RLC7_RB_WPTR_BASE_IDX 0
+#define regSDMA2_RLC7_RB_WPTR_HI 0x1d13e
+#define regSDMA2_RLC7_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA2_RLC7_RB_WPTR_POLL_CNTL 0x1d13f
+#define regSDMA2_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA2_RLC7_RB_RPTR_ADDR_HI 0x1d140
+#define regSDMA2_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA2_RLC7_RB_RPTR_ADDR_LO 0x1d141
+#define regSDMA2_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA2_RLC7_IB_CNTL 0x1d142
+#define regSDMA2_RLC7_IB_CNTL_BASE_IDX 0
+#define regSDMA2_RLC7_IB_RPTR 0x1d143
+#define regSDMA2_RLC7_IB_RPTR_BASE_IDX 0
+#define regSDMA2_RLC7_IB_OFFSET 0x1d144
+#define regSDMA2_RLC7_IB_OFFSET_BASE_IDX 0
+#define regSDMA2_RLC7_IB_BASE_LO 0x1d145
+#define regSDMA2_RLC7_IB_BASE_LO_BASE_IDX 0
+#define regSDMA2_RLC7_IB_BASE_HI 0x1d146
+#define regSDMA2_RLC7_IB_BASE_HI_BASE_IDX 0
+#define regSDMA2_RLC7_IB_SIZE 0x1d147
+#define regSDMA2_RLC7_IB_SIZE_BASE_IDX 0
+#define regSDMA2_RLC7_SKIP_CNTL 0x1d148
+#define regSDMA2_RLC7_SKIP_CNTL_BASE_IDX 0
+#define regSDMA2_RLC7_CONTEXT_STATUS 0x1d149
+#define regSDMA2_RLC7_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA2_RLC7_DOORBELL 0x1d14a
+#define regSDMA2_RLC7_DOORBELL_BASE_IDX 0
+#define regSDMA2_RLC7_STATUS 0x1d160
+#define regSDMA2_RLC7_STATUS_BASE_IDX 0
+#define regSDMA2_RLC7_DOORBELL_LOG 0x1d161
+#define regSDMA2_RLC7_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA2_RLC7_WATERMARK 0x1d162
+#define regSDMA2_RLC7_WATERMARK_BASE_IDX 0
+#define regSDMA2_RLC7_DOORBELL_OFFSET 0x1d163
+#define regSDMA2_RLC7_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA2_RLC7_CSA_ADDR_LO 0x1d164
+#define regSDMA2_RLC7_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA2_RLC7_CSA_ADDR_HI 0x1d165
+#define regSDMA2_RLC7_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA2_RLC7_IB_SUB_REMAIN 0x1d167
+#define regSDMA2_RLC7_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA2_RLC7_PREEMPT 0x1d168
+#define regSDMA2_RLC7_PREEMPT_BASE_IDX 0
+#define regSDMA2_RLC7_DUMMY_REG 0x1d169
+#define regSDMA2_RLC7_DUMMY_REG_BASE_IDX 0
+#define regSDMA2_RLC7_RB_WPTR_POLL_ADDR_HI 0x1d16a
+#define regSDMA2_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA2_RLC7_RB_WPTR_POLL_ADDR_LO 0x1d16b
+#define regSDMA2_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA2_RLC7_RB_AQL_CNTL 0x1d16c
+#define regSDMA2_RLC7_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA2_RLC7_MINOR_PTR_UPDATE 0x1d16d
+#define regSDMA2_RLC7_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA2_RLC7_MIDCMD_DATA0 0x1d178
+#define regSDMA2_RLC7_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA2_RLC7_MIDCMD_DATA1 0x1d179
+#define regSDMA2_RLC7_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA2_RLC7_MIDCMD_DATA2 0x1d17a
+#define regSDMA2_RLC7_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA2_RLC7_MIDCMD_DATA3 0x1d17b
+#define regSDMA2_RLC7_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA2_RLC7_MIDCMD_DATA4 0x1d17c
+#define regSDMA2_RLC7_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA2_RLC7_MIDCMD_DATA5 0x1d17d
+#define regSDMA2_RLC7_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA2_RLC7_MIDCMD_DATA6 0x1d17e
+#define regSDMA2_RLC7_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA2_RLC7_MIDCMD_DATA7 0x1d17f
+#define regSDMA2_RLC7_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA2_RLC7_MIDCMD_DATA8 0x1d180
+#define regSDMA2_RLC7_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA2_RLC7_MIDCMD_DATA9 0x1d181
+#define regSDMA2_RLC7_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA2_RLC7_MIDCMD_DATA10 0x1d182
+#define regSDMA2_RLC7_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA2_RLC7_MIDCMD_CNTL 0x1d183
+#define regSDMA2_RLC7_MIDCMD_CNTL_BASE_IDX 0
+
+
+// addressBlock: sdma0_sdma3dec
+// base address: 0x79000
+#define regSDMA3_UCODE_ADDR 0x1d1a0
+#define regSDMA3_UCODE_ADDR_BASE_IDX 0
+#define regSDMA3_UCODE_DATA 0x1d1a1
+#define regSDMA3_UCODE_DATA_BASE_IDX 0
+#define regSDMA3_VF_ENABLE 0x1d1aa
+#define regSDMA3_VF_ENABLE_BASE_IDX 0
+#define regSDMA3_CONTEXT_GROUP_BOUNDARY 0x1d1b9
+#define regSDMA3_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0
+#define regSDMA3_POWER_CNTL 0x1d1ba
+#define regSDMA3_POWER_CNTL_BASE_IDX 0
+#define regSDMA3_CLK_CTRL 0x1d1bb
+#define regSDMA3_CLK_CTRL_BASE_IDX 0
+#define regSDMA3_CNTL 0x1d1bc
+#define regSDMA3_CNTL_BASE_IDX 0
+#define regSDMA3_CHICKEN_BITS 0x1d1bd
+#define regSDMA3_CHICKEN_BITS_BASE_IDX 0
+#define regSDMA3_GB_ADDR_CONFIG 0x1d1be
+#define regSDMA3_GB_ADDR_CONFIG_BASE_IDX 0
+#define regSDMA3_GB_ADDR_CONFIG_READ 0x1d1bf
+#define regSDMA3_GB_ADDR_CONFIG_READ_BASE_IDX 0
+#define regSDMA3_RB_RPTR_FETCH_HI 0x1d1c0
+#define regSDMA3_RB_RPTR_FETCH_HI_BASE_IDX 0
+#define regSDMA3_SEM_WAIT_FAIL_TIMER_CNTL 0x1d1c1
+#define regSDMA3_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0
+#define regSDMA3_RB_RPTR_FETCH 0x1d1c2
+#define regSDMA3_RB_RPTR_FETCH_BASE_IDX 0
+#define regSDMA3_IB_OFFSET_FETCH 0x1d1c3
+#define regSDMA3_IB_OFFSET_FETCH_BASE_IDX 0
+#define regSDMA3_PROGRAM 0x1d1c4
+#define regSDMA3_PROGRAM_BASE_IDX 0
+#define regSDMA3_STATUS_REG 0x1d1c5
+#define regSDMA3_STATUS_REG_BASE_IDX 0
+#define regSDMA3_STATUS1_REG 0x1d1c6
+#define regSDMA3_STATUS1_REG_BASE_IDX 0
+#define regSDMA3_RD_BURST_CNTL 0x1d1c7
+#define regSDMA3_RD_BURST_CNTL_BASE_IDX 0
+#define regSDMA3_HBM_PAGE_CONFIG 0x1d1c8
+#define regSDMA3_HBM_PAGE_CONFIG_BASE_IDX 0
+#define regSDMA3_UCODE_CHECKSUM 0x1d1c9
+#define regSDMA3_UCODE_CHECKSUM_BASE_IDX 0
+#define regSDMA3_F32_CNTL 0x1d1ca
+#define regSDMA3_F32_CNTL_BASE_IDX 0
+#define regSDMA3_FREEZE 0x1d1cb
+#define regSDMA3_FREEZE_BASE_IDX 0
+#define regSDMA3_PHASE0_QUANTUM 0x1d1cc
+#define regSDMA3_PHASE0_QUANTUM_BASE_IDX 0
+#define regSDMA3_PHASE1_QUANTUM 0x1d1cd
+#define regSDMA3_PHASE1_QUANTUM_BASE_IDX 0
+#define regCC_SDMA3_EDC_CONFIG 0x1d1d2
+#define regCC_SDMA3_EDC_CONFIG_BASE_IDX 0
+#define regSDMA3_BA_THRESHOLD 0x1d1d3
+#define regSDMA3_BA_THRESHOLD_BASE_IDX 0
+#define regSDMA3_ID 0x1d1d4
+#define regSDMA3_ID_BASE_IDX 0
+#define regSDMA3_VERSION 0x1d1d5
+#define regSDMA3_VERSION_BASE_IDX 0
+#define regSDMA3_EDC_COUNTER 0x1d1d6
+#define regSDMA3_EDC_COUNTER_BASE_IDX 0
+#define regSDMA3_EDC_COUNTER2 0x1d1d7
+#define regSDMA3_EDC_COUNTER2_BASE_IDX 0
+#define regSDMA3_STATUS2_REG 0x1d1d8
+#define regSDMA3_STATUS2_REG_BASE_IDX 0
+#define regSDMA3_ATOMIC_CNTL 0x1d1d9
+#define regSDMA3_ATOMIC_CNTL_BASE_IDX 0
+#define regSDMA3_ATOMIC_PREOP_LO 0x1d1da
+#define regSDMA3_ATOMIC_PREOP_LO_BASE_IDX 0
+#define regSDMA3_ATOMIC_PREOP_HI 0x1d1db
+#define regSDMA3_ATOMIC_PREOP_HI_BASE_IDX 0
+#define regSDMA3_UTCL1_CNTL 0x1d1dc
+#define regSDMA3_UTCL1_CNTL_BASE_IDX 0
+#define regSDMA3_UTCL1_WATERMK 0x1d1dd
+#define regSDMA3_UTCL1_WATERMK_BASE_IDX 0
+#define regSDMA3_UTCL1_RD_STATUS 0x1d1de
+#define regSDMA3_UTCL1_RD_STATUS_BASE_IDX 0
+#define regSDMA3_UTCL1_WR_STATUS 0x1d1df
+#define regSDMA3_UTCL1_WR_STATUS_BASE_IDX 0
+#define regSDMA3_UTCL1_INV0 0x1d1e0
+#define regSDMA3_UTCL1_INV0_BASE_IDX 0
+#define regSDMA3_UTCL1_INV1 0x1d1e1
+#define regSDMA3_UTCL1_INV1_BASE_IDX 0
+#define regSDMA3_UTCL1_INV2 0x1d1e2
+#define regSDMA3_UTCL1_INV2_BASE_IDX 0
+#define regSDMA3_UTCL1_RD_XNACK0 0x1d1e3
+#define regSDMA3_UTCL1_RD_XNACK0_BASE_IDX 0
+#define regSDMA3_UTCL1_RD_XNACK1 0x1d1e4
+#define regSDMA3_UTCL1_RD_XNACK1_BASE_IDX 0
+#define regSDMA3_UTCL1_WR_XNACK0 0x1d1e5
+#define regSDMA3_UTCL1_WR_XNACK0_BASE_IDX 0
+#define regSDMA3_UTCL1_WR_XNACK1 0x1d1e6
+#define regSDMA3_UTCL1_WR_XNACK1_BASE_IDX 0
+#define regSDMA3_UTCL1_TIMEOUT 0x1d1e7
+#define regSDMA3_UTCL1_TIMEOUT_BASE_IDX 0
+#define regSDMA3_UTCL1_PAGE 0x1d1e8
+#define regSDMA3_UTCL1_PAGE_BASE_IDX 0
+#define regSDMA3_POWER_CNTL_IDLE 0x1d1e9
+#define regSDMA3_POWER_CNTL_IDLE_BASE_IDX 0
+#define regSDMA3_RELAX_ORDERING_LUT 0x1d1ea
+#define regSDMA3_RELAX_ORDERING_LUT_BASE_IDX 0
+#define regSDMA3_CHICKEN_BITS_2 0x1d1eb
+#define regSDMA3_CHICKEN_BITS_2_BASE_IDX 0
+#define regSDMA3_STATUS3_REG 0x1d1ec
+#define regSDMA3_STATUS3_REG_BASE_IDX 0
+#define regSDMA3_PHYSICAL_ADDR_LO 0x1d1ed
+#define regSDMA3_PHYSICAL_ADDR_LO_BASE_IDX 0
+#define regSDMA3_PHYSICAL_ADDR_HI 0x1d1ee
+#define regSDMA3_PHYSICAL_ADDR_HI_BASE_IDX 0
+#define regSDMA3_PHASE2_QUANTUM 0x1d1ef
+#define regSDMA3_PHASE2_QUANTUM_BASE_IDX 0
+#define regSDMA3_ERROR_LOG 0x1d1f0
+#define regSDMA3_ERROR_LOG_BASE_IDX 0
+#define regSDMA3_PUB_DUMMY_REG0 0x1d1f1
+#define regSDMA3_PUB_DUMMY_REG0_BASE_IDX 0
+#define regSDMA3_PUB_DUMMY_REG1 0x1d1f2
+#define regSDMA3_PUB_DUMMY_REG1_BASE_IDX 0
+#define regSDMA3_PUB_DUMMY_REG2 0x1d1f3
+#define regSDMA3_PUB_DUMMY_REG2_BASE_IDX 0
+#define regSDMA3_PUB_DUMMY_REG3 0x1d1f4
+#define regSDMA3_PUB_DUMMY_REG3_BASE_IDX 0
+#define regSDMA3_F32_COUNTER 0x1d1f5
+#define regSDMA3_F32_COUNTER_BASE_IDX 0
+#define regSDMA3_PERFCNT_PERFCOUNTER0_CFG 0x1d1f7
+#define regSDMA3_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX 0
+#define regSDMA3_PERFCNT_PERFCOUNTER1_CFG 0x1d1f8
+#define regSDMA3_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX 0
+#define regSDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x1d1f9
+#define regSDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+#define regSDMA3_PERFCNT_MISC_CNTL 0x1d1fa
+#define regSDMA3_PERFCNT_MISC_CNTL_BASE_IDX 0
+#define regSDMA3_PERFCNT_PERFCOUNTER_LO 0x1d1fb
+#define regSDMA3_PERFCNT_PERFCOUNTER_LO_BASE_IDX 0
+#define regSDMA3_PERFCNT_PERFCOUNTER_HI 0x1d1fc
+#define regSDMA3_PERFCNT_PERFCOUNTER_HI_BASE_IDX 0
+#define regSDMA3_CRD_CNTL 0x1d1fd
+#define regSDMA3_CRD_CNTL_BASE_IDX 0
+#define regSDMA3_ULV_CNTL 0x1d1ff
+#define regSDMA3_ULV_CNTL_BASE_IDX 0
+#define regSDMA3_EA_DBIT_ADDR_DATA 0x1d200
+#define regSDMA3_EA_DBIT_ADDR_DATA_BASE_IDX 0
+#define regSDMA3_EA_DBIT_ADDR_INDEX 0x1d201
+#define regSDMA3_EA_DBIT_ADDR_INDEX_BASE_IDX 0
+#define regSDMA3_STATUS4_REG 0x1d203
+#define regSDMA3_STATUS4_REG_BASE_IDX 0
+#define regSDMA3_SCRATCH_RAM_DATA 0x1d204
+#define regSDMA3_SCRATCH_RAM_DATA_BASE_IDX 0
+#define regSDMA3_SCRATCH_RAM_ADDR 0x1d205
+#define regSDMA3_SCRATCH_RAM_ADDR_BASE_IDX 0
+#define regSDMA3_CE_CTRL 0x1d206
+#define regSDMA3_CE_CTRL_BASE_IDX 0
+#define regSDMA3_RAS_STATUS 0x1d207
+#define regSDMA3_RAS_STATUS_BASE_IDX 0
+#define regSDMA3_CLK_STATUS 0x1d208
+#define regSDMA3_CLK_STATUS_BASE_IDX 0
+#define regSDMA3_GFX_RB_CNTL 0x1d220
+#define regSDMA3_GFX_RB_CNTL_BASE_IDX 0
+#define regSDMA3_GFX_RB_BASE 0x1d221
+#define regSDMA3_GFX_RB_BASE_BASE_IDX 0
+#define regSDMA3_GFX_RB_BASE_HI 0x1d222
+#define regSDMA3_GFX_RB_BASE_HI_BASE_IDX 0
+#define regSDMA3_GFX_RB_RPTR 0x1d223
+#define regSDMA3_GFX_RB_RPTR_BASE_IDX 0
+#define regSDMA3_GFX_RB_RPTR_HI 0x1d224
+#define regSDMA3_GFX_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA3_GFX_RB_WPTR 0x1d225
+#define regSDMA3_GFX_RB_WPTR_BASE_IDX 0
+#define regSDMA3_GFX_RB_WPTR_HI 0x1d226
+#define regSDMA3_GFX_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA3_GFX_RB_WPTR_POLL_CNTL 0x1d227
+#define regSDMA3_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA3_GFX_RB_RPTR_ADDR_HI 0x1d228
+#define regSDMA3_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA3_GFX_RB_RPTR_ADDR_LO 0x1d229
+#define regSDMA3_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA3_GFX_IB_CNTL 0x1d22a
+#define regSDMA3_GFX_IB_CNTL_BASE_IDX 0
+#define regSDMA3_GFX_IB_RPTR 0x1d22b
+#define regSDMA3_GFX_IB_RPTR_BASE_IDX 0
+#define regSDMA3_GFX_IB_OFFSET 0x1d22c
+#define regSDMA3_GFX_IB_OFFSET_BASE_IDX 0
+#define regSDMA3_GFX_IB_BASE_LO 0x1d22d
+#define regSDMA3_GFX_IB_BASE_LO_BASE_IDX 0
+#define regSDMA3_GFX_IB_BASE_HI 0x1d22e
+#define regSDMA3_GFX_IB_BASE_HI_BASE_IDX 0
+#define regSDMA3_GFX_IB_SIZE 0x1d22f
+#define regSDMA3_GFX_IB_SIZE_BASE_IDX 0
+#define regSDMA3_GFX_SKIP_CNTL 0x1d230
+#define regSDMA3_GFX_SKIP_CNTL_BASE_IDX 0
+#define regSDMA3_GFX_CONTEXT_STATUS 0x1d231
+#define regSDMA3_GFX_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA3_GFX_DOORBELL 0x1d232
+#define regSDMA3_GFX_DOORBELL_BASE_IDX 0
+#define regSDMA3_GFX_CONTEXT_CNTL 0x1d233
+#define regSDMA3_GFX_CONTEXT_CNTL_BASE_IDX 0
+#define regSDMA3_GFX_STATUS 0x1d248
+#define regSDMA3_GFX_STATUS_BASE_IDX 0
+#define regSDMA3_GFX_DOORBELL_LOG 0x1d249
+#define regSDMA3_GFX_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA3_GFX_WATERMARK 0x1d24a
+#define regSDMA3_GFX_WATERMARK_BASE_IDX 0
+#define regSDMA3_GFX_DOORBELL_OFFSET 0x1d24b
+#define regSDMA3_GFX_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA3_GFX_CSA_ADDR_LO 0x1d24c
+#define regSDMA3_GFX_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA3_GFX_CSA_ADDR_HI 0x1d24d
+#define regSDMA3_GFX_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA3_GFX_IB_SUB_REMAIN 0x1d24f
+#define regSDMA3_GFX_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA3_GFX_PREEMPT 0x1d250
+#define regSDMA3_GFX_PREEMPT_BASE_IDX 0
+#define regSDMA3_GFX_DUMMY_REG 0x1d251
+#define regSDMA3_GFX_DUMMY_REG_BASE_IDX 0
+#define regSDMA3_GFX_RB_WPTR_POLL_ADDR_HI 0x1d252
+#define regSDMA3_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA3_GFX_RB_WPTR_POLL_ADDR_LO 0x1d253
+#define regSDMA3_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA3_GFX_RB_AQL_CNTL 0x1d254
+#define regSDMA3_GFX_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA3_GFX_MINOR_PTR_UPDATE 0x1d255
+#define regSDMA3_GFX_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA3_GFX_MIDCMD_DATA0 0x1d260
+#define regSDMA3_GFX_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA3_GFX_MIDCMD_DATA1 0x1d261
+#define regSDMA3_GFX_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA3_GFX_MIDCMD_DATA2 0x1d262
+#define regSDMA3_GFX_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA3_GFX_MIDCMD_DATA3 0x1d263
+#define regSDMA3_GFX_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA3_GFX_MIDCMD_DATA4 0x1d264
+#define regSDMA3_GFX_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA3_GFX_MIDCMD_DATA5 0x1d265
+#define regSDMA3_GFX_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA3_GFX_MIDCMD_DATA6 0x1d266
+#define regSDMA3_GFX_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA3_GFX_MIDCMD_DATA7 0x1d267
+#define regSDMA3_GFX_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA3_GFX_MIDCMD_DATA8 0x1d268
+#define regSDMA3_GFX_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA3_GFX_MIDCMD_DATA9 0x1d269
+#define regSDMA3_GFX_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA3_GFX_MIDCMD_DATA10 0x1d26a
+#define regSDMA3_GFX_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA3_GFX_MIDCMD_CNTL 0x1d26b
+#define regSDMA3_GFX_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA3_PAGE_RB_CNTL 0x1d278
+#define regSDMA3_PAGE_RB_CNTL_BASE_IDX 0
+#define regSDMA3_PAGE_RB_BASE 0x1d279
+#define regSDMA3_PAGE_RB_BASE_BASE_IDX 0
+#define regSDMA3_PAGE_RB_BASE_HI 0x1d27a
+#define regSDMA3_PAGE_RB_BASE_HI_BASE_IDX 0
+#define regSDMA3_PAGE_RB_RPTR 0x1d27b
+#define regSDMA3_PAGE_RB_RPTR_BASE_IDX 0
+#define regSDMA3_PAGE_RB_RPTR_HI 0x1d27c
+#define regSDMA3_PAGE_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA3_PAGE_RB_WPTR 0x1d27d
+#define regSDMA3_PAGE_RB_WPTR_BASE_IDX 0
+#define regSDMA3_PAGE_RB_WPTR_HI 0x1d27e
+#define regSDMA3_PAGE_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA3_PAGE_RB_WPTR_POLL_CNTL 0x1d27f
+#define regSDMA3_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA3_PAGE_RB_RPTR_ADDR_HI 0x1d280
+#define regSDMA3_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA3_PAGE_RB_RPTR_ADDR_LO 0x1d281
+#define regSDMA3_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA3_PAGE_IB_CNTL 0x1d282
+#define regSDMA3_PAGE_IB_CNTL_BASE_IDX 0
+#define regSDMA3_PAGE_IB_RPTR 0x1d283
+#define regSDMA3_PAGE_IB_RPTR_BASE_IDX 0
+#define regSDMA3_PAGE_IB_OFFSET 0x1d284
+#define regSDMA3_PAGE_IB_OFFSET_BASE_IDX 0
+#define regSDMA3_PAGE_IB_BASE_LO 0x1d285
+#define regSDMA3_PAGE_IB_BASE_LO_BASE_IDX 0
+#define regSDMA3_PAGE_IB_BASE_HI 0x1d286
+#define regSDMA3_PAGE_IB_BASE_HI_BASE_IDX 0
+#define regSDMA3_PAGE_IB_SIZE 0x1d287
+#define regSDMA3_PAGE_IB_SIZE_BASE_IDX 0
+#define regSDMA3_PAGE_SKIP_CNTL 0x1d288
+#define regSDMA3_PAGE_SKIP_CNTL_BASE_IDX 0
+#define regSDMA3_PAGE_CONTEXT_STATUS 0x1d289
+#define regSDMA3_PAGE_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA3_PAGE_DOORBELL 0x1d28a
+#define regSDMA3_PAGE_DOORBELL_BASE_IDX 0
+#define regSDMA3_PAGE_STATUS 0x1d2a0
+#define regSDMA3_PAGE_STATUS_BASE_IDX 0
+#define regSDMA3_PAGE_DOORBELL_LOG 0x1d2a1
+#define regSDMA3_PAGE_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA3_PAGE_WATERMARK 0x1d2a2
+#define regSDMA3_PAGE_WATERMARK_BASE_IDX 0
+#define regSDMA3_PAGE_DOORBELL_OFFSET 0x1d2a3
+#define regSDMA3_PAGE_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA3_PAGE_CSA_ADDR_LO 0x1d2a4
+#define regSDMA3_PAGE_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA3_PAGE_CSA_ADDR_HI 0x1d2a5
+#define regSDMA3_PAGE_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA3_PAGE_IB_SUB_REMAIN 0x1d2a7
+#define regSDMA3_PAGE_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA3_PAGE_PREEMPT 0x1d2a8
+#define regSDMA3_PAGE_PREEMPT_BASE_IDX 0
+#define regSDMA3_PAGE_DUMMY_REG 0x1d2a9
+#define regSDMA3_PAGE_DUMMY_REG_BASE_IDX 0
+#define regSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI 0x1d2aa
+#define regSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO 0x1d2ab
+#define regSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA3_PAGE_RB_AQL_CNTL 0x1d2ac
+#define regSDMA3_PAGE_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA3_PAGE_MINOR_PTR_UPDATE 0x1d2ad
+#define regSDMA3_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA3_PAGE_MIDCMD_DATA0 0x1d2b8
+#define regSDMA3_PAGE_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA3_PAGE_MIDCMD_DATA1 0x1d2b9
+#define regSDMA3_PAGE_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA3_PAGE_MIDCMD_DATA2 0x1d2ba
+#define regSDMA3_PAGE_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA3_PAGE_MIDCMD_DATA3 0x1d2bb
+#define regSDMA3_PAGE_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA3_PAGE_MIDCMD_DATA4 0x1d2bc
+#define regSDMA3_PAGE_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA3_PAGE_MIDCMD_DATA5 0x1d2bd
+#define regSDMA3_PAGE_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA3_PAGE_MIDCMD_DATA6 0x1d2be
+#define regSDMA3_PAGE_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA3_PAGE_MIDCMD_DATA7 0x1d2bf
+#define regSDMA3_PAGE_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA3_PAGE_MIDCMD_DATA8 0x1d2c0
+#define regSDMA3_PAGE_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA3_PAGE_MIDCMD_DATA9 0x1d2c1
+#define regSDMA3_PAGE_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA3_PAGE_MIDCMD_DATA10 0x1d2c2
+#define regSDMA3_PAGE_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA3_PAGE_MIDCMD_CNTL 0x1d2c3
+#define regSDMA3_PAGE_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA3_RLC0_RB_CNTL 0x1d2d0
+#define regSDMA3_RLC0_RB_CNTL_BASE_IDX 0
+#define regSDMA3_RLC0_RB_BASE 0x1d2d1
+#define regSDMA3_RLC0_RB_BASE_BASE_IDX 0
+#define regSDMA3_RLC0_RB_BASE_HI 0x1d2d2
+#define regSDMA3_RLC0_RB_BASE_HI_BASE_IDX 0
+#define regSDMA3_RLC0_RB_RPTR 0x1d2d3
+#define regSDMA3_RLC0_RB_RPTR_BASE_IDX 0
+#define regSDMA3_RLC0_RB_RPTR_HI 0x1d2d4
+#define regSDMA3_RLC0_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA3_RLC0_RB_WPTR 0x1d2d5
+#define regSDMA3_RLC0_RB_WPTR_BASE_IDX 0
+#define regSDMA3_RLC0_RB_WPTR_HI 0x1d2d6
+#define regSDMA3_RLC0_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA3_RLC0_RB_WPTR_POLL_CNTL 0x1d2d7
+#define regSDMA3_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA3_RLC0_RB_RPTR_ADDR_HI 0x1d2d8
+#define regSDMA3_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA3_RLC0_RB_RPTR_ADDR_LO 0x1d2d9
+#define regSDMA3_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA3_RLC0_IB_CNTL 0x1d2da
+#define regSDMA3_RLC0_IB_CNTL_BASE_IDX 0
+#define regSDMA3_RLC0_IB_RPTR 0x1d2db
+#define regSDMA3_RLC0_IB_RPTR_BASE_IDX 0
+#define regSDMA3_RLC0_IB_OFFSET 0x1d2dc
+#define regSDMA3_RLC0_IB_OFFSET_BASE_IDX 0
+#define regSDMA3_RLC0_IB_BASE_LO 0x1d2dd
+#define regSDMA3_RLC0_IB_BASE_LO_BASE_IDX 0
+#define regSDMA3_RLC0_IB_BASE_HI 0x1d2de
+#define regSDMA3_RLC0_IB_BASE_HI_BASE_IDX 0
+#define regSDMA3_RLC0_IB_SIZE 0x1d2df
+#define regSDMA3_RLC0_IB_SIZE_BASE_IDX 0
+#define regSDMA3_RLC0_SKIP_CNTL 0x1d2e0
+#define regSDMA3_RLC0_SKIP_CNTL_BASE_IDX 0
+#define regSDMA3_RLC0_CONTEXT_STATUS 0x1d2e1
+#define regSDMA3_RLC0_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA3_RLC0_DOORBELL 0x1d2e2
+#define regSDMA3_RLC0_DOORBELL_BASE_IDX 0
+#define regSDMA3_RLC0_STATUS 0x1d2f8
+#define regSDMA3_RLC0_STATUS_BASE_IDX 0
+#define regSDMA3_RLC0_DOORBELL_LOG 0x1d2f9
+#define regSDMA3_RLC0_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA3_RLC0_WATERMARK 0x1d2fa
+#define regSDMA3_RLC0_WATERMARK_BASE_IDX 0
+#define regSDMA3_RLC0_DOORBELL_OFFSET 0x1d2fb
+#define regSDMA3_RLC0_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA3_RLC0_CSA_ADDR_LO 0x1d2fc
+#define regSDMA3_RLC0_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA3_RLC0_CSA_ADDR_HI 0x1d2fd
+#define regSDMA3_RLC0_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA3_RLC0_IB_SUB_REMAIN 0x1d2ff
+#define regSDMA3_RLC0_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA3_RLC0_PREEMPT 0x1d300
+#define regSDMA3_RLC0_PREEMPT_BASE_IDX 0
+#define regSDMA3_RLC0_DUMMY_REG 0x1d301
+#define regSDMA3_RLC0_DUMMY_REG_BASE_IDX 0
+#define regSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI 0x1d302
+#define regSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO 0x1d303
+#define regSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA3_RLC0_RB_AQL_CNTL 0x1d304
+#define regSDMA3_RLC0_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA3_RLC0_MINOR_PTR_UPDATE 0x1d305
+#define regSDMA3_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA3_RLC0_MIDCMD_DATA0 0x1d310
+#define regSDMA3_RLC0_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA3_RLC0_MIDCMD_DATA1 0x1d311
+#define regSDMA3_RLC0_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA3_RLC0_MIDCMD_DATA2 0x1d312
+#define regSDMA3_RLC0_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA3_RLC0_MIDCMD_DATA3 0x1d313
+#define regSDMA3_RLC0_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA3_RLC0_MIDCMD_DATA4 0x1d314
+#define regSDMA3_RLC0_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA3_RLC0_MIDCMD_DATA5 0x1d315
+#define regSDMA3_RLC0_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA3_RLC0_MIDCMD_DATA6 0x1d316
+#define regSDMA3_RLC0_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA3_RLC0_MIDCMD_DATA7 0x1d317
+#define regSDMA3_RLC0_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA3_RLC0_MIDCMD_DATA8 0x1d318
+#define regSDMA3_RLC0_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA3_RLC0_MIDCMD_DATA9 0x1d319
+#define regSDMA3_RLC0_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA3_RLC0_MIDCMD_DATA10 0x1d31a
+#define regSDMA3_RLC0_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA3_RLC0_MIDCMD_CNTL 0x1d31b
+#define regSDMA3_RLC0_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA3_RLC1_RB_CNTL 0x1d328
+#define regSDMA3_RLC1_RB_CNTL_BASE_IDX 0
+#define regSDMA3_RLC1_RB_BASE 0x1d329
+#define regSDMA3_RLC1_RB_BASE_BASE_IDX 0
+#define regSDMA3_RLC1_RB_BASE_HI 0x1d32a
+#define regSDMA3_RLC1_RB_BASE_HI_BASE_IDX 0
+#define regSDMA3_RLC1_RB_RPTR 0x1d32b
+#define regSDMA3_RLC1_RB_RPTR_BASE_IDX 0
+#define regSDMA3_RLC1_RB_RPTR_HI 0x1d32c
+#define regSDMA3_RLC1_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA3_RLC1_RB_WPTR 0x1d32d
+#define regSDMA3_RLC1_RB_WPTR_BASE_IDX 0
+#define regSDMA3_RLC1_RB_WPTR_HI 0x1d32e
+#define regSDMA3_RLC1_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA3_RLC1_RB_WPTR_POLL_CNTL 0x1d32f
+#define regSDMA3_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA3_RLC1_RB_RPTR_ADDR_HI 0x1d330
+#define regSDMA3_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA3_RLC1_RB_RPTR_ADDR_LO 0x1d331
+#define regSDMA3_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA3_RLC1_IB_CNTL 0x1d332
+#define regSDMA3_RLC1_IB_CNTL_BASE_IDX 0
+#define regSDMA3_RLC1_IB_RPTR 0x1d333
+#define regSDMA3_RLC1_IB_RPTR_BASE_IDX 0
+#define regSDMA3_RLC1_IB_OFFSET 0x1d334
+#define regSDMA3_RLC1_IB_OFFSET_BASE_IDX 0
+#define regSDMA3_RLC1_IB_BASE_LO 0x1d335
+#define regSDMA3_RLC1_IB_BASE_LO_BASE_IDX 0
+#define regSDMA3_RLC1_IB_BASE_HI 0x1d336
+#define regSDMA3_RLC1_IB_BASE_HI_BASE_IDX 0
+#define regSDMA3_RLC1_IB_SIZE 0x1d337
+#define regSDMA3_RLC1_IB_SIZE_BASE_IDX 0
+#define regSDMA3_RLC1_SKIP_CNTL 0x1d338
+#define regSDMA3_RLC1_SKIP_CNTL_BASE_IDX 0
+#define regSDMA3_RLC1_CONTEXT_STATUS 0x1d339
+#define regSDMA3_RLC1_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA3_RLC1_DOORBELL 0x1d33a
+#define regSDMA3_RLC1_DOORBELL_BASE_IDX 0
+#define regSDMA3_RLC1_STATUS 0x1d350
+#define regSDMA3_RLC1_STATUS_BASE_IDX 0
+#define regSDMA3_RLC1_DOORBELL_LOG 0x1d351
+#define regSDMA3_RLC1_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA3_RLC1_WATERMARK 0x1d352
+#define regSDMA3_RLC1_WATERMARK_BASE_IDX 0
+#define regSDMA3_RLC1_DOORBELL_OFFSET 0x1d353
+#define regSDMA3_RLC1_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA3_RLC1_CSA_ADDR_LO 0x1d354
+#define regSDMA3_RLC1_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA3_RLC1_CSA_ADDR_HI 0x1d355
+#define regSDMA3_RLC1_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA3_RLC1_IB_SUB_REMAIN 0x1d357
+#define regSDMA3_RLC1_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA3_RLC1_PREEMPT 0x1d358
+#define regSDMA3_RLC1_PREEMPT_BASE_IDX 0
+#define regSDMA3_RLC1_DUMMY_REG 0x1d359
+#define regSDMA3_RLC1_DUMMY_REG_BASE_IDX 0
+#define regSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI 0x1d35a
+#define regSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO 0x1d35b
+#define regSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA3_RLC1_RB_AQL_CNTL 0x1d35c
+#define regSDMA3_RLC1_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA3_RLC1_MINOR_PTR_UPDATE 0x1d35d
+#define regSDMA3_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA3_RLC1_MIDCMD_DATA0 0x1d368
+#define regSDMA3_RLC1_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA3_RLC1_MIDCMD_DATA1 0x1d369
+#define regSDMA3_RLC1_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA3_RLC1_MIDCMD_DATA2 0x1d36a
+#define regSDMA3_RLC1_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA3_RLC1_MIDCMD_DATA3 0x1d36b
+#define regSDMA3_RLC1_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA3_RLC1_MIDCMD_DATA4 0x1d36c
+#define regSDMA3_RLC1_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA3_RLC1_MIDCMD_DATA5 0x1d36d
+#define regSDMA3_RLC1_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA3_RLC1_MIDCMD_DATA6 0x1d36e
+#define regSDMA3_RLC1_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA3_RLC1_MIDCMD_DATA7 0x1d36f
+#define regSDMA3_RLC1_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA3_RLC1_MIDCMD_DATA8 0x1d370
+#define regSDMA3_RLC1_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA3_RLC1_MIDCMD_DATA9 0x1d371
+#define regSDMA3_RLC1_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA3_RLC1_MIDCMD_DATA10 0x1d372
+#define regSDMA3_RLC1_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA3_RLC1_MIDCMD_CNTL 0x1d373
+#define regSDMA3_RLC1_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA3_RLC2_RB_CNTL 0x1d380
+#define regSDMA3_RLC2_RB_CNTL_BASE_IDX 0
+#define regSDMA3_RLC2_RB_BASE 0x1d381
+#define regSDMA3_RLC2_RB_BASE_BASE_IDX 0
+#define regSDMA3_RLC2_RB_BASE_HI 0x1d382
+#define regSDMA3_RLC2_RB_BASE_HI_BASE_IDX 0
+#define regSDMA3_RLC2_RB_RPTR 0x1d383
+#define regSDMA3_RLC2_RB_RPTR_BASE_IDX 0
+#define regSDMA3_RLC2_RB_RPTR_HI 0x1d384
+#define regSDMA3_RLC2_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA3_RLC2_RB_WPTR 0x1d385
+#define regSDMA3_RLC2_RB_WPTR_BASE_IDX 0
+#define regSDMA3_RLC2_RB_WPTR_HI 0x1d386
+#define regSDMA3_RLC2_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA3_RLC2_RB_WPTR_POLL_CNTL 0x1d387
+#define regSDMA3_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA3_RLC2_RB_RPTR_ADDR_HI 0x1d388
+#define regSDMA3_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA3_RLC2_RB_RPTR_ADDR_LO 0x1d389
+#define regSDMA3_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA3_RLC2_IB_CNTL 0x1d38a
+#define regSDMA3_RLC2_IB_CNTL_BASE_IDX 0
+#define regSDMA3_RLC2_IB_RPTR 0x1d38b
+#define regSDMA3_RLC2_IB_RPTR_BASE_IDX 0
+#define regSDMA3_RLC2_IB_OFFSET 0x1d38c
+#define regSDMA3_RLC2_IB_OFFSET_BASE_IDX 0
+#define regSDMA3_RLC2_IB_BASE_LO 0x1d38d
+#define regSDMA3_RLC2_IB_BASE_LO_BASE_IDX 0
+#define regSDMA3_RLC2_IB_BASE_HI 0x1d38e
+#define regSDMA3_RLC2_IB_BASE_HI_BASE_IDX 0
+#define regSDMA3_RLC2_IB_SIZE 0x1d38f
+#define regSDMA3_RLC2_IB_SIZE_BASE_IDX 0
+#define regSDMA3_RLC2_SKIP_CNTL 0x1d390
+#define regSDMA3_RLC2_SKIP_CNTL_BASE_IDX 0
+#define regSDMA3_RLC2_CONTEXT_STATUS 0x1d391
+#define regSDMA3_RLC2_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA3_RLC2_DOORBELL 0x1d392
+#define regSDMA3_RLC2_DOORBELL_BASE_IDX 0
+#define regSDMA3_RLC2_STATUS 0x1d3a8
+#define regSDMA3_RLC2_STATUS_BASE_IDX 0
+#define regSDMA3_RLC2_DOORBELL_LOG 0x1d3a9
+#define regSDMA3_RLC2_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA3_RLC2_WATERMARK 0x1d3aa
+#define regSDMA3_RLC2_WATERMARK_BASE_IDX 0
+#define regSDMA3_RLC2_DOORBELL_OFFSET 0x1d3ab
+#define regSDMA3_RLC2_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA3_RLC2_CSA_ADDR_LO 0x1d3ac
+#define regSDMA3_RLC2_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA3_RLC2_CSA_ADDR_HI 0x1d3ad
+#define regSDMA3_RLC2_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA3_RLC2_IB_SUB_REMAIN 0x1d3af
+#define regSDMA3_RLC2_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA3_RLC2_PREEMPT 0x1d3b0
+#define regSDMA3_RLC2_PREEMPT_BASE_IDX 0
+#define regSDMA3_RLC2_DUMMY_REG 0x1d3b1
+#define regSDMA3_RLC2_DUMMY_REG_BASE_IDX 0
+#define regSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI 0x1d3b2
+#define regSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO 0x1d3b3
+#define regSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA3_RLC2_RB_AQL_CNTL 0x1d3b4
+#define regSDMA3_RLC2_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA3_RLC2_MINOR_PTR_UPDATE 0x1d3b5
+#define regSDMA3_RLC2_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA3_RLC2_MIDCMD_DATA0 0x1d3c0
+#define regSDMA3_RLC2_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA3_RLC2_MIDCMD_DATA1 0x1d3c1
+#define regSDMA3_RLC2_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA3_RLC2_MIDCMD_DATA2 0x1d3c2
+#define regSDMA3_RLC2_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA3_RLC2_MIDCMD_DATA3 0x1d3c3
+#define regSDMA3_RLC2_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA3_RLC2_MIDCMD_DATA4 0x1d3c4
+#define regSDMA3_RLC2_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA3_RLC2_MIDCMD_DATA5 0x1d3c5
+#define regSDMA3_RLC2_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA3_RLC2_MIDCMD_DATA6 0x1d3c6
+#define regSDMA3_RLC2_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA3_RLC2_MIDCMD_DATA7 0x1d3c7
+#define regSDMA3_RLC2_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA3_RLC2_MIDCMD_DATA8 0x1d3c8
+#define regSDMA3_RLC2_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA3_RLC2_MIDCMD_DATA9 0x1d3c9
+#define regSDMA3_RLC2_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA3_RLC2_MIDCMD_DATA10 0x1d3ca
+#define regSDMA3_RLC2_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA3_RLC2_MIDCMD_CNTL 0x1d3cb
+#define regSDMA3_RLC2_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA3_RLC3_RB_CNTL 0x1d3d8
+#define regSDMA3_RLC3_RB_CNTL_BASE_IDX 0
+#define regSDMA3_RLC3_RB_BASE 0x1d3d9
+#define regSDMA3_RLC3_RB_BASE_BASE_IDX 0
+#define regSDMA3_RLC3_RB_BASE_HI 0x1d3da
+#define regSDMA3_RLC3_RB_BASE_HI_BASE_IDX 0
+#define regSDMA3_RLC3_RB_RPTR 0x1d3db
+#define regSDMA3_RLC3_RB_RPTR_BASE_IDX 0
+#define regSDMA3_RLC3_RB_RPTR_HI 0x1d3dc
+#define regSDMA3_RLC3_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA3_RLC3_RB_WPTR 0x1d3dd
+#define regSDMA3_RLC3_RB_WPTR_BASE_IDX 0
+#define regSDMA3_RLC3_RB_WPTR_HI 0x1d3de
+#define regSDMA3_RLC3_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA3_RLC3_RB_WPTR_POLL_CNTL 0x1d3df
+#define regSDMA3_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA3_RLC3_RB_RPTR_ADDR_HI 0x1d3e0
+#define regSDMA3_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA3_RLC3_RB_RPTR_ADDR_LO 0x1d3e1
+#define regSDMA3_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA3_RLC3_IB_CNTL 0x1d3e2
+#define regSDMA3_RLC3_IB_CNTL_BASE_IDX 0
+#define regSDMA3_RLC3_IB_RPTR 0x1d3e3
+#define regSDMA3_RLC3_IB_RPTR_BASE_IDX 0
+#define regSDMA3_RLC3_IB_OFFSET 0x1d3e4
+#define regSDMA3_RLC3_IB_OFFSET_BASE_IDX 0
+#define regSDMA3_RLC3_IB_BASE_LO 0x1d3e5
+#define regSDMA3_RLC3_IB_BASE_LO_BASE_IDX 0
+#define regSDMA3_RLC3_IB_BASE_HI 0x1d3e6
+#define regSDMA3_RLC3_IB_BASE_HI_BASE_IDX 0
+#define regSDMA3_RLC3_IB_SIZE 0x1d3e7
+#define regSDMA3_RLC3_IB_SIZE_BASE_IDX 0
+#define regSDMA3_RLC3_SKIP_CNTL 0x1d3e8
+#define regSDMA3_RLC3_SKIP_CNTL_BASE_IDX 0
+#define regSDMA3_RLC3_CONTEXT_STATUS 0x1d3e9
+#define regSDMA3_RLC3_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA3_RLC3_DOORBELL 0x1d3ea
+#define regSDMA3_RLC3_DOORBELL_BASE_IDX 0
+#define regSDMA3_RLC3_STATUS 0x1d400
+#define regSDMA3_RLC3_STATUS_BASE_IDX 0
+#define regSDMA3_RLC3_DOORBELL_LOG 0x1d401
+#define regSDMA3_RLC3_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA3_RLC3_WATERMARK 0x1d402
+#define regSDMA3_RLC3_WATERMARK_BASE_IDX 0
+#define regSDMA3_RLC3_DOORBELL_OFFSET 0x1d403
+#define regSDMA3_RLC3_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA3_RLC3_CSA_ADDR_LO 0x1d404
+#define regSDMA3_RLC3_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA3_RLC3_CSA_ADDR_HI 0x1d405
+#define regSDMA3_RLC3_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA3_RLC3_IB_SUB_REMAIN 0x1d407
+#define regSDMA3_RLC3_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA3_RLC3_PREEMPT 0x1d408
+#define regSDMA3_RLC3_PREEMPT_BASE_IDX 0
+#define regSDMA3_RLC3_DUMMY_REG 0x1d409
+#define regSDMA3_RLC3_DUMMY_REG_BASE_IDX 0
+#define regSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI 0x1d40a
+#define regSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO 0x1d40b
+#define regSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA3_RLC3_RB_AQL_CNTL 0x1d40c
+#define regSDMA3_RLC3_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA3_RLC3_MINOR_PTR_UPDATE 0x1d40d
+#define regSDMA3_RLC3_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA3_RLC3_MIDCMD_DATA0 0x1d418
+#define regSDMA3_RLC3_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA3_RLC3_MIDCMD_DATA1 0x1d419
+#define regSDMA3_RLC3_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA3_RLC3_MIDCMD_DATA2 0x1d41a
+#define regSDMA3_RLC3_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA3_RLC3_MIDCMD_DATA3 0x1d41b
+#define regSDMA3_RLC3_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA3_RLC3_MIDCMD_DATA4 0x1d41c
+#define regSDMA3_RLC3_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA3_RLC3_MIDCMD_DATA5 0x1d41d
+#define regSDMA3_RLC3_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA3_RLC3_MIDCMD_DATA6 0x1d41e
+#define regSDMA3_RLC3_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA3_RLC3_MIDCMD_DATA7 0x1d41f
+#define regSDMA3_RLC3_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA3_RLC3_MIDCMD_DATA8 0x1d420
+#define regSDMA3_RLC3_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA3_RLC3_MIDCMD_DATA9 0x1d421
+#define regSDMA3_RLC3_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA3_RLC3_MIDCMD_DATA10 0x1d422
+#define regSDMA3_RLC3_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA3_RLC3_MIDCMD_CNTL 0x1d423
+#define regSDMA3_RLC3_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA3_RLC4_RB_CNTL 0x1d430
+#define regSDMA3_RLC4_RB_CNTL_BASE_IDX 0
+#define regSDMA3_RLC4_RB_BASE 0x1d431
+#define regSDMA3_RLC4_RB_BASE_BASE_IDX 0
+#define regSDMA3_RLC4_RB_BASE_HI 0x1d432
+#define regSDMA3_RLC4_RB_BASE_HI_BASE_IDX 0
+#define regSDMA3_RLC4_RB_RPTR 0x1d433
+#define regSDMA3_RLC4_RB_RPTR_BASE_IDX 0
+#define regSDMA3_RLC4_RB_RPTR_HI 0x1d434
+#define regSDMA3_RLC4_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA3_RLC4_RB_WPTR 0x1d435
+#define regSDMA3_RLC4_RB_WPTR_BASE_IDX 0
+#define regSDMA3_RLC4_RB_WPTR_HI 0x1d436
+#define regSDMA3_RLC4_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA3_RLC4_RB_WPTR_POLL_CNTL 0x1d437
+#define regSDMA3_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA3_RLC4_RB_RPTR_ADDR_HI 0x1d438
+#define regSDMA3_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA3_RLC4_RB_RPTR_ADDR_LO 0x1d439
+#define regSDMA3_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA3_RLC4_IB_CNTL 0x1d43a
+#define regSDMA3_RLC4_IB_CNTL_BASE_IDX 0
+#define regSDMA3_RLC4_IB_RPTR 0x1d43b
+#define regSDMA3_RLC4_IB_RPTR_BASE_IDX 0
+#define regSDMA3_RLC4_IB_OFFSET 0x1d43c
+#define regSDMA3_RLC4_IB_OFFSET_BASE_IDX 0
+#define regSDMA3_RLC4_IB_BASE_LO 0x1d43d
+#define regSDMA3_RLC4_IB_BASE_LO_BASE_IDX 0
+#define regSDMA3_RLC4_IB_BASE_HI 0x1d43e
+#define regSDMA3_RLC4_IB_BASE_HI_BASE_IDX 0
+#define regSDMA3_RLC4_IB_SIZE 0x1d43f
+#define regSDMA3_RLC4_IB_SIZE_BASE_IDX 0
+#define regSDMA3_RLC4_SKIP_CNTL 0x1d440
+#define regSDMA3_RLC4_SKIP_CNTL_BASE_IDX 0
+#define regSDMA3_RLC4_CONTEXT_STATUS 0x1d441
+#define regSDMA3_RLC4_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA3_RLC4_DOORBELL 0x1d442
+#define regSDMA3_RLC4_DOORBELL_BASE_IDX 0
+#define regSDMA3_RLC4_STATUS 0x1d458
+#define regSDMA3_RLC4_STATUS_BASE_IDX 0
+#define regSDMA3_RLC4_DOORBELL_LOG 0x1d459
+#define regSDMA3_RLC4_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA3_RLC4_WATERMARK 0x1d45a
+#define regSDMA3_RLC4_WATERMARK_BASE_IDX 0
+#define regSDMA3_RLC4_DOORBELL_OFFSET 0x1d45b
+#define regSDMA3_RLC4_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA3_RLC4_CSA_ADDR_LO 0x1d45c
+#define regSDMA3_RLC4_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA3_RLC4_CSA_ADDR_HI 0x1d45d
+#define regSDMA3_RLC4_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA3_RLC4_IB_SUB_REMAIN 0x1d45f
+#define regSDMA3_RLC4_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA3_RLC4_PREEMPT 0x1d460
+#define regSDMA3_RLC4_PREEMPT_BASE_IDX 0
+#define regSDMA3_RLC4_DUMMY_REG 0x1d461
+#define regSDMA3_RLC4_DUMMY_REG_BASE_IDX 0
+#define regSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI 0x1d462
+#define regSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO 0x1d463
+#define regSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA3_RLC4_RB_AQL_CNTL 0x1d464
+#define regSDMA3_RLC4_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA3_RLC4_MINOR_PTR_UPDATE 0x1d465
+#define regSDMA3_RLC4_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA3_RLC4_MIDCMD_DATA0 0x1d470
+#define regSDMA3_RLC4_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA3_RLC4_MIDCMD_DATA1 0x1d471
+#define regSDMA3_RLC4_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA3_RLC4_MIDCMD_DATA2 0x1d472
+#define regSDMA3_RLC4_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA3_RLC4_MIDCMD_DATA3 0x1d473
+#define regSDMA3_RLC4_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA3_RLC4_MIDCMD_DATA4 0x1d474
+#define regSDMA3_RLC4_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA3_RLC4_MIDCMD_DATA5 0x1d475
+#define regSDMA3_RLC4_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA3_RLC4_MIDCMD_DATA6 0x1d476
+#define regSDMA3_RLC4_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA3_RLC4_MIDCMD_DATA7 0x1d477
+#define regSDMA3_RLC4_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA3_RLC4_MIDCMD_DATA8 0x1d478
+#define regSDMA3_RLC4_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA3_RLC4_MIDCMD_DATA9 0x1d479
+#define regSDMA3_RLC4_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA3_RLC4_MIDCMD_DATA10 0x1d47a
+#define regSDMA3_RLC4_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA3_RLC4_MIDCMD_CNTL 0x1d47b
+#define regSDMA3_RLC4_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA3_RLC5_RB_CNTL 0x1d488
+#define regSDMA3_RLC5_RB_CNTL_BASE_IDX 0
+#define regSDMA3_RLC5_RB_BASE 0x1d489
+#define regSDMA3_RLC5_RB_BASE_BASE_IDX 0
+#define regSDMA3_RLC5_RB_BASE_HI 0x1d48a
+#define regSDMA3_RLC5_RB_BASE_HI_BASE_IDX 0
+#define regSDMA3_RLC5_RB_RPTR 0x1d48b
+#define regSDMA3_RLC5_RB_RPTR_BASE_IDX 0
+#define regSDMA3_RLC5_RB_RPTR_HI 0x1d48c
+#define regSDMA3_RLC5_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA3_RLC5_RB_WPTR 0x1d48d
+#define regSDMA3_RLC5_RB_WPTR_BASE_IDX 0
+#define regSDMA3_RLC5_RB_WPTR_HI 0x1d48e
+#define regSDMA3_RLC5_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA3_RLC5_RB_WPTR_POLL_CNTL 0x1d48f
+#define regSDMA3_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA3_RLC5_RB_RPTR_ADDR_HI 0x1d490
+#define regSDMA3_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA3_RLC5_RB_RPTR_ADDR_LO 0x1d491
+#define regSDMA3_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA3_RLC5_IB_CNTL 0x1d492
+#define regSDMA3_RLC5_IB_CNTL_BASE_IDX 0
+#define regSDMA3_RLC5_IB_RPTR 0x1d493
+#define regSDMA3_RLC5_IB_RPTR_BASE_IDX 0
+#define regSDMA3_RLC5_IB_OFFSET 0x1d494
+#define regSDMA3_RLC5_IB_OFFSET_BASE_IDX 0
+#define regSDMA3_RLC5_IB_BASE_LO 0x1d495
+#define regSDMA3_RLC5_IB_BASE_LO_BASE_IDX 0
+#define regSDMA3_RLC5_IB_BASE_HI 0x1d496
+#define regSDMA3_RLC5_IB_BASE_HI_BASE_IDX 0
+#define regSDMA3_RLC5_IB_SIZE 0x1d497
+#define regSDMA3_RLC5_IB_SIZE_BASE_IDX 0
+#define regSDMA3_RLC5_SKIP_CNTL 0x1d498
+#define regSDMA3_RLC5_SKIP_CNTL_BASE_IDX 0
+#define regSDMA3_RLC5_CONTEXT_STATUS 0x1d499
+#define regSDMA3_RLC5_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA3_RLC5_DOORBELL 0x1d49a
+#define regSDMA3_RLC5_DOORBELL_BASE_IDX 0
+#define regSDMA3_RLC5_STATUS 0x1d4b0
+#define regSDMA3_RLC5_STATUS_BASE_IDX 0
+#define regSDMA3_RLC5_DOORBELL_LOG 0x1d4b1
+#define regSDMA3_RLC5_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA3_RLC5_WATERMARK 0x1d4b2
+#define regSDMA3_RLC5_WATERMARK_BASE_IDX 0
+#define regSDMA3_RLC5_DOORBELL_OFFSET 0x1d4b3
+#define regSDMA3_RLC5_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA3_RLC5_CSA_ADDR_LO 0x1d4b4
+#define regSDMA3_RLC5_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA3_RLC5_CSA_ADDR_HI 0x1d4b5
+#define regSDMA3_RLC5_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA3_RLC5_IB_SUB_REMAIN 0x1d4b7
+#define regSDMA3_RLC5_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA3_RLC5_PREEMPT 0x1d4b8
+#define regSDMA3_RLC5_PREEMPT_BASE_IDX 0
+#define regSDMA3_RLC5_DUMMY_REG 0x1d4b9
+#define regSDMA3_RLC5_DUMMY_REG_BASE_IDX 0
+#define regSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI 0x1d4ba
+#define regSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO 0x1d4bb
+#define regSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA3_RLC5_RB_AQL_CNTL 0x1d4bc
+#define regSDMA3_RLC5_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA3_RLC5_MINOR_PTR_UPDATE 0x1d4bd
+#define regSDMA3_RLC5_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA3_RLC5_MIDCMD_DATA0 0x1d4c8
+#define regSDMA3_RLC5_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA3_RLC5_MIDCMD_DATA1 0x1d4c9
+#define regSDMA3_RLC5_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA3_RLC5_MIDCMD_DATA2 0x1d4ca
+#define regSDMA3_RLC5_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA3_RLC5_MIDCMD_DATA3 0x1d4cb
+#define regSDMA3_RLC5_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA3_RLC5_MIDCMD_DATA4 0x1d4cc
+#define regSDMA3_RLC5_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA3_RLC5_MIDCMD_DATA5 0x1d4cd
+#define regSDMA3_RLC5_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA3_RLC5_MIDCMD_DATA6 0x1d4ce
+#define regSDMA3_RLC5_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA3_RLC5_MIDCMD_DATA7 0x1d4cf
+#define regSDMA3_RLC5_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA3_RLC5_MIDCMD_DATA8 0x1d4d0
+#define regSDMA3_RLC5_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA3_RLC5_MIDCMD_DATA9 0x1d4d1
+#define regSDMA3_RLC5_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA3_RLC5_MIDCMD_DATA10 0x1d4d2
+#define regSDMA3_RLC5_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA3_RLC5_MIDCMD_CNTL 0x1d4d3
+#define regSDMA3_RLC5_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA3_RLC6_RB_CNTL 0x1d4e0
+#define regSDMA3_RLC6_RB_CNTL_BASE_IDX 0
+#define regSDMA3_RLC6_RB_BASE 0x1d4e1
+#define regSDMA3_RLC6_RB_BASE_BASE_IDX 0
+#define regSDMA3_RLC6_RB_BASE_HI 0x1d4e2
+#define regSDMA3_RLC6_RB_BASE_HI_BASE_IDX 0
+#define regSDMA3_RLC6_RB_RPTR 0x1d4e3
+#define regSDMA3_RLC6_RB_RPTR_BASE_IDX 0
+#define regSDMA3_RLC6_RB_RPTR_HI 0x1d4e4
+#define regSDMA3_RLC6_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA3_RLC6_RB_WPTR 0x1d4e5
+#define regSDMA3_RLC6_RB_WPTR_BASE_IDX 0
+#define regSDMA3_RLC6_RB_WPTR_HI 0x1d4e6
+#define regSDMA3_RLC6_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA3_RLC6_RB_WPTR_POLL_CNTL 0x1d4e7
+#define regSDMA3_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA3_RLC6_RB_RPTR_ADDR_HI 0x1d4e8
+#define regSDMA3_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA3_RLC6_RB_RPTR_ADDR_LO 0x1d4e9
+#define regSDMA3_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA3_RLC6_IB_CNTL 0x1d4ea
+#define regSDMA3_RLC6_IB_CNTL_BASE_IDX 0
+#define regSDMA3_RLC6_IB_RPTR 0x1d4eb
+#define regSDMA3_RLC6_IB_RPTR_BASE_IDX 0
+#define regSDMA3_RLC6_IB_OFFSET 0x1d4ec
+#define regSDMA3_RLC6_IB_OFFSET_BASE_IDX 0
+#define regSDMA3_RLC6_IB_BASE_LO 0x1d4ed
+#define regSDMA3_RLC6_IB_BASE_LO_BASE_IDX 0
+#define regSDMA3_RLC6_IB_BASE_HI 0x1d4ee
+#define regSDMA3_RLC6_IB_BASE_HI_BASE_IDX 0
+#define regSDMA3_RLC6_IB_SIZE 0x1d4ef
+#define regSDMA3_RLC6_IB_SIZE_BASE_IDX 0
+#define regSDMA3_RLC6_SKIP_CNTL 0x1d4f0
+#define regSDMA3_RLC6_SKIP_CNTL_BASE_IDX 0
+#define regSDMA3_RLC6_CONTEXT_STATUS 0x1d4f1
+#define regSDMA3_RLC6_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA3_RLC6_DOORBELL 0x1d4f2
+#define regSDMA3_RLC6_DOORBELL_BASE_IDX 0
+#define regSDMA3_RLC6_STATUS 0x1d508
+#define regSDMA3_RLC6_STATUS_BASE_IDX 0
+#define regSDMA3_RLC6_DOORBELL_LOG 0x1d509
+#define regSDMA3_RLC6_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA3_RLC6_WATERMARK 0x1d50a
+#define regSDMA3_RLC6_WATERMARK_BASE_IDX 0
+#define regSDMA3_RLC6_DOORBELL_OFFSET 0x1d50b
+#define regSDMA3_RLC6_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA3_RLC6_CSA_ADDR_LO 0x1d50c
+#define regSDMA3_RLC6_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA3_RLC6_CSA_ADDR_HI 0x1d50d
+#define regSDMA3_RLC6_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA3_RLC6_IB_SUB_REMAIN 0x1d50f
+#define regSDMA3_RLC6_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA3_RLC6_PREEMPT 0x1d510
+#define regSDMA3_RLC6_PREEMPT_BASE_IDX 0
+#define regSDMA3_RLC6_DUMMY_REG 0x1d511
+#define regSDMA3_RLC6_DUMMY_REG_BASE_IDX 0
+#define regSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI 0x1d512
+#define regSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO 0x1d513
+#define regSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA3_RLC6_RB_AQL_CNTL 0x1d514
+#define regSDMA3_RLC6_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA3_RLC6_MINOR_PTR_UPDATE 0x1d515
+#define regSDMA3_RLC6_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA3_RLC6_MIDCMD_DATA0 0x1d520
+#define regSDMA3_RLC6_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA3_RLC6_MIDCMD_DATA1 0x1d521
+#define regSDMA3_RLC6_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA3_RLC6_MIDCMD_DATA2 0x1d522
+#define regSDMA3_RLC6_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA3_RLC6_MIDCMD_DATA3 0x1d523
+#define regSDMA3_RLC6_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA3_RLC6_MIDCMD_DATA4 0x1d524
+#define regSDMA3_RLC6_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA3_RLC6_MIDCMD_DATA5 0x1d525
+#define regSDMA3_RLC6_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA3_RLC6_MIDCMD_DATA6 0x1d526
+#define regSDMA3_RLC6_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA3_RLC6_MIDCMD_DATA7 0x1d527
+#define regSDMA3_RLC6_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA3_RLC6_MIDCMD_DATA8 0x1d528
+#define regSDMA3_RLC6_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA3_RLC6_MIDCMD_DATA9 0x1d529
+#define regSDMA3_RLC6_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA3_RLC6_MIDCMD_DATA10 0x1d52a
+#define regSDMA3_RLC6_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA3_RLC6_MIDCMD_CNTL 0x1d52b
+#define regSDMA3_RLC6_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA3_RLC7_RB_CNTL 0x1d538
+#define regSDMA3_RLC7_RB_CNTL_BASE_IDX 0
+#define regSDMA3_RLC7_RB_BASE 0x1d539
+#define regSDMA3_RLC7_RB_BASE_BASE_IDX 0
+#define regSDMA3_RLC7_RB_BASE_HI 0x1d53a
+#define regSDMA3_RLC7_RB_BASE_HI_BASE_IDX 0
+#define regSDMA3_RLC7_RB_RPTR 0x1d53b
+#define regSDMA3_RLC7_RB_RPTR_BASE_IDX 0
+#define regSDMA3_RLC7_RB_RPTR_HI 0x1d53c
+#define regSDMA3_RLC7_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA3_RLC7_RB_WPTR 0x1d53d
+#define regSDMA3_RLC7_RB_WPTR_BASE_IDX 0
+#define regSDMA3_RLC7_RB_WPTR_HI 0x1d53e
+#define regSDMA3_RLC7_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA3_RLC7_RB_WPTR_POLL_CNTL 0x1d53f
+#define regSDMA3_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA3_RLC7_RB_RPTR_ADDR_HI 0x1d540
+#define regSDMA3_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA3_RLC7_RB_RPTR_ADDR_LO 0x1d541
+#define regSDMA3_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA3_RLC7_IB_CNTL 0x1d542
+#define regSDMA3_RLC7_IB_CNTL_BASE_IDX 0
+#define regSDMA3_RLC7_IB_RPTR 0x1d543
+#define regSDMA3_RLC7_IB_RPTR_BASE_IDX 0
+#define regSDMA3_RLC7_IB_OFFSET 0x1d544
+#define regSDMA3_RLC7_IB_OFFSET_BASE_IDX 0
+#define regSDMA3_RLC7_IB_BASE_LO 0x1d545
+#define regSDMA3_RLC7_IB_BASE_LO_BASE_IDX 0
+#define regSDMA3_RLC7_IB_BASE_HI 0x1d546
+#define regSDMA3_RLC7_IB_BASE_HI_BASE_IDX 0
+#define regSDMA3_RLC7_IB_SIZE 0x1d547
+#define regSDMA3_RLC7_IB_SIZE_BASE_IDX 0
+#define regSDMA3_RLC7_SKIP_CNTL 0x1d548
+#define regSDMA3_RLC7_SKIP_CNTL_BASE_IDX 0
+#define regSDMA3_RLC7_CONTEXT_STATUS 0x1d549
+#define regSDMA3_RLC7_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA3_RLC7_DOORBELL 0x1d54a
+#define regSDMA3_RLC7_DOORBELL_BASE_IDX 0
+#define regSDMA3_RLC7_STATUS 0x1d560
+#define regSDMA3_RLC7_STATUS_BASE_IDX 0
+#define regSDMA3_RLC7_DOORBELL_LOG 0x1d561
+#define regSDMA3_RLC7_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA3_RLC7_WATERMARK 0x1d562
+#define regSDMA3_RLC7_WATERMARK_BASE_IDX 0
+#define regSDMA3_RLC7_DOORBELL_OFFSET 0x1d563
+#define regSDMA3_RLC7_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA3_RLC7_CSA_ADDR_LO 0x1d564
+#define regSDMA3_RLC7_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA3_RLC7_CSA_ADDR_HI 0x1d565
+#define regSDMA3_RLC7_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA3_RLC7_IB_SUB_REMAIN 0x1d567
+#define regSDMA3_RLC7_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA3_RLC7_PREEMPT 0x1d568
+#define regSDMA3_RLC7_PREEMPT_BASE_IDX 0
+#define regSDMA3_RLC7_DUMMY_REG 0x1d569
+#define regSDMA3_RLC7_DUMMY_REG_BASE_IDX 0
+#define regSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI 0x1d56a
+#define regSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO 0x1d56b
+#define regSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA3_RLC7_RB_AQL_CNTL 0x1d56c
+#define regSDMA3_RLC7_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA3_RLC7_MINOR_PTR_UPDATE 0x1d56d
+#define regSDMA3_RLC7_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA3_RLC7_MIDCMD_DATA0 0x1d578
+#define regSDMA3_RLC7_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA3_RLC7_MIDCMD_DATA1 0x1d579
+#define regSDMA3_RLC7_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA3_RLC7_MIDCMD_DATA2 0x1d57a
+#define regSDMA3_RLC7_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA3_RLC7_MIDCMD_DATA3 0x1d57b
+#define regSDMA3_RLC7_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA3_RLC7_MIDCMD_DATA4 0x1d57c
+#define regSDMA3_RLC7_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA3_RLC7_MIDCMD_DATA5 0x1d57d
+#define regSDMA3_RLC7_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA3_RLC7_MIDCMD_DATA6 0x1d57e
+#define regSDMA3_RLC7_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA3_RLC7_MIDCMD_DATA7 0x1d57f
+#define regSDMA3_RLC7_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA3_RLC7_MIDCMD_DATA8 0x1d580
+#define regSDMA3_RLC7_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA3_RLC7_MIDCMD_DATA9 0x1d581
+#define regSDMA3_RLC7_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA3_RLC7_MIDCMD_DATA10 0x1d582
+#define regSDMA3_RLC7_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA3_RLC7_MIDCMD_CNTL 0x1d583
+#define regSDMA3_RLC7_MIDCMD_CNTL_BASE_IDX 0
+
+
+// addressBlock: sdma0_sdma4dec
+// base address: 0x7a000
+#define regSDMA4_UCODE_ADDR 0x1d5a0
+#define regSDMA4_UCODE_ADDR_BASE_IDX 0
+#define regSDMA4_UCODE_DATA 0x1d5a1
+#define regSDMA4_UCODE_DATA_BASE_IDX 0
+#define regSDMA4_VF_ENABLE 0x1d5aa
+#define regSDMA4_VF_ENABLE_BASE_IDX 0
+#define regSDMA4_CONTEXT_GROUP_BOUNDARY 0x1d5b9
+#define regSDMA4_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0
+#define regSDMA4_POWER_CNTL 0x1d5ba
+#define regSDMA4_POWER_CNTL_BASE_IDX 0
+#define regSDMA4_CLK_CTRL 0x1d5bb
+#define regSDMA4_CLK_CTRL_BASE_IDX 0
+#define regSDMA4_CNTL 0x1d5bc
+#define regSDMA4_CNTL_BASE_IDX 0
+#define regSDMA4_CHICKEN_BITS 0x1d5bd
+#define regSDMA4_CHICKEN_BITS_BASE_IDX 0
+#define regSDMA4_GB_ADDR_CONFIG 0x1d5be
+#define regSDMA4_GB_ADDR_CONFIG_BASE_IDX 0
+#define regSDMA4_GB_ADDR_CONFIG_READ 0x1d5bf
+#define regSDMA4_GB_ADDR_CONFIG_READ_BASE_IDX 0
+#define regSDMA4_RB_RPTR_FETCH_HI 0x1d5c0
+#define regSDMA4_RB_RPTR_FETCH_HI_BASE_IDX 0
+#define regSDMA4_SEM_WAIT_FAIL_TIMER_CNTL 0x1d5c1
+#define regSDMA4_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0
+#define regSDMA4_RB_RPTR_FETCH 0x1d5c2
+#define regSDMA4_RB_RPTR_FETCH_BASE_IDX 0
+#define regSDMA4_IB_OFFSET_FETCH 0x1d5c3
+#define regSDMA4_IB_OFFSET_FETCH_BASE_IDX 0
+#define regSDMA4_PROGRAM 0x1d5c4
+#define regSDMA4_PROGRAM_BASE_IDX 0
+#define regSDMA4_STATUS_REG 0x1d5c5
+#define regSDMA4_STATUS_REG_BASE_IDX 0
+#define regSDMA4_STATUS1_REG 0x1d5c6
+#define regSDMA4_STATUS1_REG_BASE_IDX 0
+#define regSDMA4_RD_BURST_CNTL 0x1d5c7
+#define regSDMA4_RD_BURST_CNTL_BASE_IDX 0
+#define regSDMA4_HBM_PAGE_CONFIG 0x1d5c8
+#define regSDMA4_HBM_PAGE_CONFIG_BASE_IDX 0
+#define regSDMA4_UCODE_CHECKSUM 0x1d5c9
+#define regSDMA4_UCODE_CHECKSUM_BASE_IDX 0
+#define regSDMA4_F32_CNTL 0x1d5ca
+#define regSDMA4_F32_CNTL_BASE_IDX 0
+#define regSDMA4_FREEZE 0x1d5cb
+#define regSDMA4_FREEZE_BASE_IDX 0
+#define regSDMA4_PHASE0_QUANTUM 0x1d5cc
+#define regSDMA4_PHASE0_QUANTUM_BASE_IDX 0
+#define regSDMA4_PHASE1_QUANTUM 0x1d5cd
+#define regSDMA4_PHASE1_QUANTUM_BASE_IDX 0
+#define regCC_SDMA4_EDC_CONFIG 0x1d5d2
+#define regCC_SDMA4_EDC_CONFIG_BASE_IDX 0
+#define regSDMA4_BA_THRESHOLD 0x1d5d3
+#define regSDMA4_BA_THRESHOLD_BASE_IDX 0
+#define regSDMA4_ID 0x1d5d4
+#define regSDMA4_ID_BASE_IDX 0
+#define regSDMA4_VERSION 0x1d5d5
+#define regSDMA4_VERSION_BASE_IDX 0
+#define regSDMA4_EDC_COUNTER 0x1d5d6
+#define regSDMA4_EDC_COUNTER_BASE_IDX 0
+#define regSDMA4_EDC_COUNTER2 0x1d5d7
+#define regSDMA4_EDC_COUNTER2_BASE_IDX 0
+#define regSDMA4_STATUS2_REG 0x1d5d8
+#define regSDMA4_STATUS2_REG_BASE_IDX 0
+#define regSDMA4_ATOMIC_CNTL 0x1d5d9
+#define regSDMA4_ATOMIC_CNTL_BASE_IDX 0
+#define regSDMA4_ATOMIC_PREOP_LO 0x1d5da
+#define regSDMA4_ATOMIC_PREOP_LO_BASE_IDX 0
+#define regSDMA4_ATOMIC_PREOP_HI 0x1d5db
+#define regSDMA4_ATOMIC_PREOP_HI_BASE_IDX 0
+#define regSDMA4_UTCL1_CNTL 0x1d5dc
+#define regSDMA4_UTCL1_CNTL_BASE_IDX 0
+#define regSDMA4_UTCL1_WATERMK 0x1d5dd
+#define regSDMA4_UTCL1_WATERMK_BASE_IDX 0
+#define regSDMA4_UTCL1_RD_STATUS 0x1d5de
+#define regSDMA4_UTCL1_RD_STATUS_BASE_IDX 0
+#define regSDMA4_UTCL1_WR_STATUS 0x1d5df
+#define regSDMA4_UTCL1_WR_STATUS_BASE_IDX 0
+#define regSDMA4_UTCL1_INV0 0x1d5e0
+#define regSDMA4_UTCL1_INV0_BASE_IDX 0
+#define regSDMA4_UTCL1_INV1 0x1d5e1
+#define regSDMA4_UTCL1_INV1_BASE_IDX 0
+#define regSDMA4_UTCL1_INV2 0x1d5e2
+#define regSDMA4_UTCL1_INV2_BASE_IDX 0
+#define regSDMA4_UTCL1_RD_XNACK0 0x1d5e3
+#define regSDMA4_UTCL1_RD_XNACK0_BASE_IDX 0
+#define regSDMA4_UTCL1_RD_XNACK1 0x1d5e4
+#define regSDMA4_UTCL1_RD_XNACK1_BASE_IDX 0
+#define regSDMA4_UTCL1_WR_XNACK0 0x1d5e5
+#define regSDMA4_UTCL1_WR_XNACK0_BASE_IDX 0
+#define regSDMA4_UTCL1_WR_XNACK1 0x1d5e6
+#define regSDMA4_UTCL1_WR_XNACK1_BASE_IDX 0
+#define regSDMA4_UTCL1_TIMEOUT 0x1d5e7
+#define regSDMA4_UTCL1_TIMEOUT_BASE_IDX 0
+#define regSDMA4_UTCL1_PAGE 0x1d5e8
+#define regSDMA4_UTCL1_PAGE_BASE_IDX 0
+#define regSDMA4_POWER_CNTL_IDLE 0x1d5e9
+#define regSDMA4_POWER_CNTL_IDLE_BASE_IDX 0
+#define regSDMA4_RELAX_ORDERING_LUT 0x1d5ea
+#define regSDMA4_RELAX_ORDERING_LUT_BASE_IDX 0
+#define regSDMA4_CHICKEN_BITS_2 0x1d5eb
+#define regSDMA4_CHICKEN_BITS_2_BASE_IDX 0
+#define regSDMA4_STATUS3_REG 0x1d5ec
+#define regSDMA4_STATUS3_REG_BASE_IDX 0
+#define regSDMA4_PHYSICAL_ADDR_LO 0x1d5ed
+#define regSDMA4_PHYSICAL_ADDR_LO_BASE_IDX 0
+#define regSDMA4_PHYSICAL_ADDR_HI 0x1d5ee
+#define regSDMA4_PHYSICAL_ADDR_HI_BASE_IDX 0
+#define regSDMA4_PHASE2_QUANTUM 0x1d5ef
+#define regSDMA4_PHASE2_QUANTUM_BASE_IDX 0
+#define regSDMA4_ERROR_LOG 0x1d5f0
+#define regSDMA4_ERROR_LOG_BASE_IDX 0
+#define regSDMA4_PUB_DUMMY_REG0 0x1d5f1
+#define regSDMA4_PUB_DUMMY_REG0_BASE_IDX 0
+#define regSDMA4_PUB_DUMMY_REG1 0x1d5f2
+#define regSDMA4_PUB_DUMMY_REG1_BASE_IDX 0
+#define regSDMA4_PUB_DUMMY_REG2 0x1d5f3
+#define regSDMA4_PUB_DUMMY_REG2_BASE_IDX 0
+#define regSDMA4_PUB_DUMMY_REG3 0x1d5f4
+#define regSDMA4_PUB_DUMMY_REG3_BASE_IDX 0
+#define regSDMA4_F32_COUNTER 0x1d5f5
+#define regSDMA4_F32_COUNTER_BASE_IDX 0
+#define regSDMA4_PERFCNT_PERFCOUNTER0_CFG 0x1d5f7
+#define regSDMA4_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX 0
+#define regSDMA4_PERFCNT_PERFCOUNTER1_CFG 0x1d5f8
+#define regSDMA4_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX 0
+#define regSDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x1d5f9
+#define regSDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+#define regSDMA4_PERFCNT_MISC_CNTL 0x1d5fa
+#define regSDMA4_PERFCNT_MISC_CNTL_BASE_IDX 0
+#define regSDMA4_PERFCNT_PERFCOUNTER_LO 0x1d5fb
+#define regSDMA4_PERFCNT_PERFCOUNTER_LO_BASE_IDX 0
+#define regSDMA4_PERFCNT_PERFCOUNTER_HI 0x1d5fc
+#define regSDMA4_PERFCNT_PERFCOUNTER_HI_BASE_IDX 0
+#define regSDMA4_CRD_CNTL 0x1d5fd
+#define regSDMA4_CRD_CNTL_BASE_IDX 0
+#define regSDMA4_ULV_CNTL 0x1d5ff
+#define regSDMA4_ULV_CNTL_BASE_IDX 0
+#define regSDMA4_EA_DBIT_ADDR_DATA 0x1d600
+#define regSDMA4_EA_DBIT_ADDR_DATA_BASE_IDX 0
+#define regSDMA4_EA_DBIT_ADDR_INDEX 0x1d601
+#define regSDMA4_EA_DBIT_ADDR_INDEX_BASE_IDX 0
+#define regSDMA4_STATUS4_REG 0x1d603
+#define regSDMA4_STATUS4_REG_BASE_IDX 0
+#define regSDMA4_SCRATCH_RAM_DATA 0x1d604
+#define regSDMA4_SCRATCH_RAM_DATA_BASE_IDX 0
+#define regSDMA4_SCRATCH_RAM_ADDR 0x1d605
+#define regSDMA4_SCRATCH_RAM_ADDR_BASE_IDX 0
+#define regSDMA4_CE_CTRL 0x1d606
+#define regSDMA4_CE_CTRL_BASE_IDX 0
+#define regSDMA4_RAS_STATUS 0x1d607
+#define regSDMA4_RAS_STATUS_BASE_IDX 0
+#define regSDMA4_CLK_STATUS 0x1d608
+#define regSDMA4_CLK_STATUS_BASE_IDX 0
+#define regSDMA4_GFX_RB_CNTL 0x1d620
+#define regSDMA4_GFX_RB_CNTL_BASE_IDX 0
+#define regSDMA4_GFX_RB_BASE 0x1d621
+#define regSDMA4_GFX_RB_BASE_BASE_IDX 0
+#define regSDMA4_GFX_RB_BASE_HI 0x1d622
+#define regSDMA4_GFX_RB_BASE_HI_BASE_IDX 0
+#define regSDMA4_GFX_RB_RPTR 0x1d623
+#define regSDMA4_GFX_RB_RPTR_BASE_IDX 0
+#define regSDMA4_GFX_RB_RPTR_HI 0x1d624
+#define regSDMA4_GFX_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA4_GFX_RB_WPTR 0x1d625
+#define regSDMA4_GFX_RB_WPTR_BASE_IDX 0
+#define regSDMA4_GFX_RB_WPTR_HI 0x1d626
+#define regSDMA4_GFX_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA4_GFX_RB_WPTR_POLL_CNTL 0x1d627
+#define regSDMA4_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA4_GFX_RB_RPTR_ADDR_HI 0x1d628
+#define regSDMA4_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA4_GFX_RB_RPTR_ADDR_LO 0x1d629
+#define regSDMA4_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA4_GFX_IB_CNTL 0x1d62a
+#define regSDMA4_GFX_IB_CNTL_BASE_IDX 0
+#define regSDMA4_GFX_IB_RPTR 0x1d62b
+#define regSDMA4_GFX_IB_RPTR_BASE_IDX 0
+#define regSDMA4_GFX_IB_OFFSET 0x1d62c
+#define regSDMA4_GFX_IB_OFFSET_BASE_IDX 0
+#define regSDMA4_GFX_IB_BASE_LO 0x1d62d
+#define regSDMA4_GFX_IB_BASE_LO_BASE_IDX 0
+#define regSDMA4_GFX_IB_BASE_HI 0x1d62e
+#define regSDMA4_GFX_IB_BASE_HI_BASE_IDX 0
+#define regSDMA4_GFX_IB_SIZE 0x1d62f
+#define regSDMA4_GFX_IB_SIZE_BASE_IDX 0
+#define regSDMA4_GFX_SKIP_CNTL 0x1d630
+#define regSDMA4_GFX_SKIP_CNTL_BASE_IDX 0
+#define regSDMA4_GFX_CONTEXT_STATUS 0x1d631
+#define regSDMA4_GFX_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA4_GFX_DOORBELL 0x1d632
+#define regSDMA4_GFX_DOORBELL_BASE_IDX 0
+#define regSDMA4_GFX_CONTEXT_CNTL 0x1d633
+#define regSDMA4_GFX_CONTEXT_CNTL_BASE_IDX 0
+#define regSDMA4_GFX_STATUS 0x1d648
+#define regSDMA4_GFX_STATUS_BASE_IDX 0
+#define regSDMA4_GFX_DOORBELL_LOG 0x1d649
+#define regSDMA4_GFX_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA4_GFX_WATERMARK 0x1d64a
+#define regSDMA4_GFX_WATERMARK_BASE_IDX 0
+#define regSDMA4_GFX_DOORBELL_OFFSET 0x1d64b
+#define regSDMA4_GFX_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA4_GFX_CSA_ADDR_LO 0x1d64c
+#define regSDMA4_GFX_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA4_GFX_CSA_ADDR_HI 0x1d64d
+#define regSDMA4_GFX_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA4_GFX_IB_SUB_REMAIN 0x1d64f
+#define regSDMA4_GFX_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA4_GFX_PREEMPT 0x1d650
+#define regSDMA4_GFX_PREEMPT_BASE_IDX 0
+#define regSDMA4_GFX_DUMMY_REG 0x1d651
+#define regSDMA4_GFX_DUMMY_REG_BASE_IDX 0
+#define regSDMA4_GFX_RB_WPTR_POLL_ADDR_HI 0x1d652
+#define regSDMA4_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA4_GFX_RB_WPTR_POLL_ADDR_LO 0x1d653
+#define regSDMA4_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA4_GFX_RB_AQL_CNTL 0x1d654
+#define regSDMA4_GFX_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA4_GFX_MINOR_PTR_UPDATE 0x1d655
+#define regSDMA4_GFX_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA4_GFX_MIDCMD_DATA0 0x1d660
+#define regSDMA4_GFX_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA4_GFX_MIDCMD_DATA1 0x1d661
+#define regSDMA4_GFX_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA4_GFX_MIDCMD_DATA2 0x1d662
+#define regSDMA4_GFX_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA4_GFX_MIDCMD_DATA3 0x1d663
+#define regSDMA4_GFX_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA4_GFX_MIDCMD_DATA4 0x1d664
+#define regSDMA4_GFX_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA4_GFX_MIDCMD_DATA5 0x1d665
+#define regSDMA4_GFX_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA4_GFX_MIDCMD_DATA6 0x1d666
+#define regSDMA4_GFX_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA4_GFX_MIDCMD_DATA7 0x1d667
+#define regSDMA4_GFX_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA4_GFX_MIDCMD_DATA8 0x1d668
+#define regSDMA4_GFX_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA4_GFX_MIDCMD_DATA9 0x1d669
+#define regSDMA4_GFX_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA4_GFX_MIDCMD_DATA10 0x1d66a
+#define regSDMA4_GFX_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA4_GFX_MIDCMD_CNTL 0x1d66b
+#define regSDMA4_GFX_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA4_PAGE_RB_CNTL 0x1d678
+#define regSDMA4_PAGE_RB_CNTL_BASE_IDX 0
+#define regSDMA4_PAGE_RB_BASE 0x1d679
+#define regSDMA4_PAGE_RB_BASE_BASE_IDX 0
+#define regSDMA4_PAGE_RB_BASE_HI 0x1d67a
+#define regSDMA4_PAGE_RB_BASE_HI_BASE_IDX 0
+#define regSDMA4_PAGE_RB_RPTR 0x1d67b
+#define regSDMA4_PAGE_RB_RPTR_BASE_IDX 0
+#define regSDMA4_PAGE_RB_RPTR_HI 0x1d67c
+#define regSDMA4_PAGE_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA4_PAGE_RB_WPTR 0x1d67d
+#define regSDMA4_PAGE_RB_WPTR_BASE_IDX 0
+#define regSDMA4_PAGE_RB_WPTR_HI 0x1d67e
+#define regSDMA4_PAGE_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA4_PAGE_RB_WPTR_POLL_CNTL 0x1d67f
+#define regSDMA4_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA4_PAGE_RB_RPTR_ADDR_HI 0x1d680
+#define regSDMA4_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA4_PAGE_RB_RPTR_ADDR_LO 0x1d681
+#define regSDMA4_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA4_PAGE_IB_CNTL 0x1d682
+#define regSDMA4_PAGE_IB_CNTL_BASE_IDX 0
+#define regSDMA4_PAGE_IB_RPTR 0x1d683
+#define regSDMA4_PAGE_IB_RPTR_BASE_IDX 0
+#define regSDMA4_PAGE_IB_OFFSET 0x1d684
+#define regSDMA4_PAGE_IB_OFFSET_BASE_IDX 0
+#define regSDMA4_PAGE_IB_BASE_LO 0x1d685
+#define regSDMA4_PAGE_IB_BASE_LO_BASE_IDX 0
+#define regSDMA4_PAGE_IB_BASE_HI 0x1d686
+#define regSDMA4_PAGE_IB_BASE_HI_BASE_IDX 0
+#define regSDMA4_PAGE_IB_SIZE 0x1d687
+#define regSDMA4_PAGE_IB_SIZE_BASE_IDX 0
+#define regSDMA4_PAGE_SKIP_CNTL 0x1d688
+#define regSDMA4_PAGE_SKIP_CNTL_BASE_IDX 0
+#define regSDMA4_PAGE_CONTEXT_STATUS 0x1d689
+#define regSDMA4_PAGE_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA4_PAGE_DOORBELL 0x1d68a
+#define regSDMA4_PAGE_DOORBELL_BASE_IDX 0
+#define regSDMA4_PAGE_STATUS 0x1d6a0
+#define regSDMA4_PAGE_STATUS_BASE_IDX 0
+#define regSDMA4_PAGE_DOORBELL_LOG 0x1d6a1
+#define regSDMA4_PAGE_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA4_PAGE_WATERMARK 0x1d6a2
+#define regSDMA4_PAGE_WATERMARK_BASE_IDX 0
+#define regSDMA4_PAGE_DOORBELL_OFFSET 0x1d6a3
+#define regSDMA4_PAGE_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA4_PAGE_CSA_ADDR_LO 0x1d6a4
+#define regSDMA4_PAGE_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA4_PAGE_CSA_ADDR_HI 0x1d6a5
+#define regSDMA4_PAGE_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA4_PAGE_IB_SUB_REMAIN 0x1d6a7
+#define regSDMA4_PAGE_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA4_PAGE_PREEMPT 0x1d6a8
+#define regSDMA4_PAGE_PREEMPT_BASE_IDX 0
+#define regSDMA4_PAGE_DUMMY_REG 0x1d6a9
+#define regSDMA4_PAGE_DUMMY_REG_BASE_IDX 0
+#define regSDMA4_PAGE_RB_WPTR_POLL_ADDR_HI 0x1d6aa
+#define regSDMA4_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA4_PAGE_RB_WPTR_POLL_ADDR_LO 0x1d6ab
+#define regSDMA4_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA4_PAGE_RB_AQL_CNTL 0x1d6ac
+#define regSDMA4_PAGE_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA4_PAGE_MINOR_PTR_UPDATE 0x1d6ad
+#define regSDMA4_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA4_PAGE_MIDCMD_DATA0 0x1d6b8
+#define regSDMA4_PAGE_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA4_PAGE_MIDCMD_DATA1 0x1d6b9
+#define regSDMA4_PAGE_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA4_PAGE_MIDCMD_DATA2 0x1d6ba
+#define regSDMA4_PAGE_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA4_PAGE_MIDCMD_DATA3 0x1d6bb
+#define regSDMA4_PAGE_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA4_PAGE_MIDCMD_DATA4 0x1d6bc
+#define regSDMA4_PAGE_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA4_PAGE_MIDCMD_DATA5 0x1d6bd
+#define regSDMA4_PAGE_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA4_PAGE_MIDCMD_DATA6 0x1d6be
+#define regSDMA4_PAGE_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA4_PAGE_MIDCMD_DATA7 0x1d6bf
+#define regSDMA4_PAGE_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA4_PAGE_MIDCMD_DATA8 0x1d6c0
+#define regSDMA4_PAGE_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA4_PAGE_MIDCMD_DATA9 0x1d6c1
+#define regSDMA4_PAGE_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA4_PAGE_MIDCMD_DATA10 0x1d6c2
+#define regSDMA4_PAGE_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA4_PAGE_MIDCMD_CNTL 0x1d6c3
+#define regSDMA4_PAGE_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA4_RLC0_RB_CNTL 0x1d6d0
+#define regSDMA4_RLC0_RB_CNTL_BASE_IDX 0
+#define regSDMA4_RLC0_RB_BASE 0x1d6d1
+#define regSDMA4_RLC0_RB_BASE_BASE_IDX 0
+#define regSDMA4_RLC0_RB_BASE_HI 0x1d6d2
+#define regSDMA4_RLC0_RB_BASE_HI_BASE_IDX 0
+#define regSDMA4_RLC0_RB_RPTR 0x1d6d3
+#define regSDMA4_RLC0_RB_RPTR_BASE_IDX 0
+#define regSDMA4_RLC0_RB_RPTR_HI 0x1d6d4
+#define regSDMA4_RLC0_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA4_RLC0_RB_WPTR 0x1d6d5
+#define regSDMA4_RLC0_RB_WPTR_BASE_IDX 0
+#define regSDMA4_RLC0_RB_WPTR_HI 0x1d6d6
+#define regSDMA4_RLC0_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA4_RLC0_RB_WPTR_POLL_CNTL 0x1d6d7
+#define regSDMA4_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA4_RLC0_RB_RPTR_ADDR_HI 0x1d6d8
+#define regSDMA4_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA4_RLC0_RB_RPTR_ADDR_LO 0x1d6d9
+#define regSDMA4_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA4_RLC0_IB_CNTL 0x1d6da
+#define regSDMA4_RLC0_IB_CNTL_BASE_IDX 0
+#define regSDMA4_RLC0_IB_RPTR 0x1d6db
+#define regSDMA4_RLC0_IB_RPTR_BASE_IDX 0
+#define regSDMA4_RLC0_IB_OFFSET 0x1d6dc
+#define regSDMA4_RLC0_IB_OFFSET_BASE_IDX 0
+#define regSDMA4_RLC0_IB_BASE_LO 0x1d6dd
+#define regSDMA4_RLC0_IB_BASE_LO_BASE_IDX 0
+#define regSDMA4_RLC0_IB_BASE_HI 0x1d6de
+#define regSDMA4_RLC0_IB_BASE_HI_BASE_IDX 0
+#define regSDMA4_RLC0_IB_SIZE 0x1d6df
+#define regSDMA4_RLC0_IB_SIZE_BASE_IDX 0
+#define regSDMA4_RLC0_SKIP_CNTL 0x1d6e0
+#define regSDMA4_RLC0_SKIP_CNTL_BASE_IDX 0
+#define regSDMA4_RLC0_CONTEXT_STATUS 0x1d6e1
+#define regSDMA4_RLC0_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA4_RLC0_DOORBELL 0x1d6e2
+#define regSDMA4_RLC0_DOORBELL_BASE_IDX 0
+#define regSDMA4_RLC0_STATUS 0x1d6f8
+#define regSDMA4_RLC0_STATUS_BASE_IDX 0
+#define regSDMA4_RLC0_DOORBELL_LOG 0x1d6f9
+#define regSDMA4_RLC0_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA4_RLC0_WATERMARK 0x1d6fa
+#define regSDMA4_RLC0_WATERMARK_BASE_IDX 0
+#define regSDMA4_RLC0_DOORBELL_OFFSET 0x1d6fb
+#define regSDMA4_RLC0_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA4_RLC0_CSA_ADDR_LO 0x1d6fc
+#define regSDMA4_RLC0_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA4_RLC0_CSA_ADDR_HI 0x1d6fd
+#define regSDMA4_RLC0_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA4_RLC0_IB_SUB_REMAIN 0x1d6ff
+#define regSDMA4_RLC0_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA4_RLC0_PREEMPT 0x1d700
+#define regSDMA4_RLC0_PREEMPT_BASE_IDX 0
+#define regSDMA4_RLC0_DUMMY_REG 0x1d701
+#define regSDMA4_RLC0_DUMMY_REG_BASE_IDX 0
+#define regSDMA4_RLC0_RB_WPTR_POLL_ADDR_HI 0x1d702
+#define regSDMA4_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA4_RLC0_RB_WPTR_POLL_ADDR_LO 0x1d703
+#define regSDMA4_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA4_RLC0_RB_AQL_CNTL 0x1d704
+#define regSDMA4_RLC0_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA4_RLC0_MINOR_PTR_UPDATE 0x1d705
+#define regSDMA4_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA4_RLC0_MIDCMD_DATA0 0x1d710
+#define regSDMA4_RLC0_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA4_RLC0_MIDCMD_DATA1 0x1d711
+#define regSDMA4_RLC0_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA4_RLC0_MIDCMD_DATA2 0x1d712
+#define regSDMA4_RLC0_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA4_RLC0_MIDCMD_DATA3 0x1d713
+#define regSDMA4_RLC0_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA4_RLC0_MIDCMD_DATA4 0x1d714
+#define regSDMA4_RLC0_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA4_RLC0_MIDCMD_DATA5 0x1d715
+#define regSDMA4_RLC0_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA4_RLC0_MIDCMD_DATA6 0x1d716
+#define regSDMA4_RLC0_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA4_RLC0_MIDCMD_DATA7 0x1d717
+#define regSDMA4_RLC0_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA4_RLC0_MIDCMD_DATA8 0x1d718
+#define regSDMA4_RLC0_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA4_RLC0_MIDCMD_DATA9 0x1d719
+#define regSDMA4_RLC0_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA4_RLC0_MIDCMD_DATA10 0x1d71a
+#define regSDMA4_RLC0_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA4_RLC0_MIDCMD_CNTL 0x1d71b
+#define regSDMA4_RLC0_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA4_RLC1_RB_CNTL 0x1d728
+#define regSDMA4_RLC1_RB_CNTL_BASE_IDX 0
+#define regSDMA4_RLC1_RB_BASE 0x1d729
+#define regSDMA4_RLC1_RB_BASE_BASE_IDX 0
+#define regSDMA4_RLC1_RB_BASE_HI 0x1d72a
+#define regSDMA4_RLC1_RB_BASE_HI_BASE_IDX 0
+#define regSDMA4_RLC1_RB_RPTR 0x1d72b
+#define regSDMA4_RLC1_RB_RPTR_BASE_IDX 0
+#define regSDMA4_RLC1_RB_RPTR_HI 0x1d72c
+#define regSDMA4_RLC1_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA4_RLC1_RB_WPTR 0x1d72d
+#define regSDMA4_RLC1_RB_WPTR_BASE_IDX 0
+#define regSDMA4_RLC1_RB_WPTR_HI 0x1d72e
+#define regSDMA4_RLC1_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA4_RLC1_RB_WPTR_POLL_CNTL 0x1d72f
+#define regSDMA4_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA4_RLC1_RB_RPTR_ADDR_HI 0x1d730
+#define regSDMA4_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA4_RLC1_RB_RPTR_ADDR_LO 0x1d731
+#define regSDMA4_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA4_RLC1_IB_CNTL 0x1d732
+#define regSDMA4_RLC1_IB_CNTL_BASE_IDX 0
+#define regSDMA4_RLC1_IB_RPTR 0x1d733
+#define regSDMA4_RLC1_IB_RPTR_BASE_IDX 0
+#define regSDMA4_RLC1_IB_OFFSET 0x1d734
+#define regSDMA4_RLC1_IB_OFFSET_BASE_IDX 0
+#define regSDMA4_RLC1_IB_BASE_LO 0x1d735
+#define regSDMA4_RLC1_IB_BASE_LO_BASE_IDX 0
+#define regSDMA4_RLC1_IB_BASE_HI 0x1d736
+#define regSDMA4_RLC1_IB_BASE_HI_BASE_IDX 0
+#define regSDMA4_RLC1_IB_SIZE 0x1d737
+#define regSDMA4_RLC1_IB_SIZE_BASE_IDX 0
+#define regSDMA4_RLC1_SKIP_CNTL 0x1d738
+#define regSDMA4_RLC1_SKIP_CNTL_BASE_IDX 0
+#define regSDMA4_RLC1_CONTEXT_STATUS 0x1d739
+#define regSDMA4_RLC1_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA4_RLC1_DOORBELL 0x1d73a
+#define regSDMA4_RLC1_DOORBELL_BASE_IDX 0
+#define regSDMA4_RLC1_STATUS 0x1d750
+#define regSDMA4_RLC1_STATUS_BASE_IDX 0
+#define regSDMA4_RLC1_DOORBELL_LOG 0x1d751
+#define regSDMA4_RLC1_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA4_RLC1_WATERMARK 0x1d752
+#define regSDMA4_RLC1_WATERMARK_BASE_IDX 0
+#define regSDMA4_RLC1_DOORBELL_OFFSET 0x1d753
+#define regSDMA4_RLC1_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA4_RLC1_CSA_ADDR_LO 0x1d754
+#define regSDMA4_RLC1_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA4_RLC1_CSA_ADDR_HI 0x1d755
+#define regSDMA4_RLC1_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA4_RLC1_IB_SUB_REMAIN 0x1d757
+#define regSDMA4_RLC1_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA4_RLC1_PREEMPT 0x1d758
+#define regSDMA4_RLC1_PREEMPT_BASE_IDX 0
+#define regSDMA4_RLC1_DUMMY_REG 0x1d759
+#define regSDMA4_RLC1_DUMMY_REG_BASE_IDX 0
+#define regSDMA4_RLC1_RB_WPTR_POLL_ADDR_HI 0x1d75a
+#define regSDMA4_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA4_RLC1_RB_WPTR_POLL_ADDR_LO 0x1d75b
+#define regSDMA4_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA4_RLC1_RB_AQL_CNTL 0x1d75c
+#define regSDMA4_RLC1_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA4_RLC1_MINOR_PTR_UPDATE 0x1d75d
+#define regSDMA4_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA4_RLC1_MIDCMD_DATA0 0x1d768
+#define regSDMA4_RLC1_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA4_RLC1_MIDCMD_DATA1 0x1d769
+#define regSDMA4_RLC1_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA4_RLC1_MIDCMD_DATA2 0x1d76a
+#define regSDMA4_RLC1_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA4_RLC1_MIDCMD_DATA3 0x1d76b
+#define regSDMA4_RLC1_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA4_RLC1_MIDCMD_DATA4 0x1d76c
+#define regSDMA4_RLC1_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA4_RLC1_MIDCMD_DATA5 0x1d76d
+#define regSDMA4_RLC1_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA4_RLC1_MIDCMD_DATA6 0x1d76e
+#define regSDMA4_RLC1_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA4_RLC1_MIDCMD_DATA7 0x1d76f
+#define regSDMA4_RLC1_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA4_RLC1_MIDCMD_DATA8 0x1d770
+#define regSDMA4_RLC1_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA4_RLC1_MIDCMD_DATA9 0x1d771
+#define regSDMA4_RLC1_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA4_RLC1_MIDCMD_DATA10 0x1d772
+#define regSDMA4_RLC1_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA4_RLC1_MIDCMD_CNTL 0x1d773
+#define regSDMA4_RLC1_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA4_RLC2_RB_CNTL 0x1d780
+#define regSDMA4_RLC2_RB_CNTL_BASE_IDX 0
+#define regSDMA4_RLC2_RB_BASE 0x1d781
+#define regSDMA4_RLC2_RB_BASE_BASE_IDX 0
+#define regSDMA4_RLC2_RB_BASE_HI 0x1d782
+#define regSDMA4_RLC2_RB_BASE_HI_BASE_IDX 0
+#define regSDMA4_RLC2_RB_RPTR 0x1d783
+#define regSDMA4_RLC2_RB_RPTR_BASE_IDX 0
+#define regSDMA4_RLC2_RB_RPTR_HI 0x1d784
+#define regSDMA4_RLC2_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA4_RLC2_RB_WPTR 0x1d785
+#define regSDMA4_RLC2_RB_WPTR_BASE_IDX 0
+#define regSDMA4_RLC2_RB_WPTR_HI 0x1d786
+#define regSDMA4_RLC2_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA4_RLC2_RB_WPTR_POLL_CNTL 0x1d787
+#define regSDMA4_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA4_RLC2_RB_RPTR_ADDR_HI 0x1d788
+#define regSDMA4_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA4_RLC2_RB_RPTR_ADDR_LO 0x1d789
+#define regSDMA4_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA4_RLC2_IB_CNTL 0x1d78a
+#define regSDMA4_RLC2_IB_CNTL_BASE_IDX 0
+#define regSDMA4_RLC2_IB_RPTR 0x1d78b
+#define regSDMA4_RLC2_IB_RPTR_BASE_IDX 0
+#define regSDMA4_RLC2_IB_OFFSET 0x1d78c
+#define regSDMA4_RLC2_IB_OFFSET_BASE_IDX 0
+#define regSDMA4_RLC2_IB_BASE_LO 0x1d78d
+#define regSDMA4_RLC2_IB_BASE_LO_BASE_IDX 0
+#define regSDMA4_RLC2_IB_BASE_HI 0x1d78e
+#define regSDMA4_RLC2_IB_BASE_HI_BASE_IDX 0
+#define regSDMA4_RLC2_IB_SIZE 0x1d78f
+#define regSDMA4_RLC2_IB_SIZE_BASE_IDX 0
+#define regSDMA4_RLC2_SKIP_CNTL 0x1d790
+#define regSDMA4_RLC2_SKIP_CNTL_BASE_IDX 0
+#define regSDMA4_RLC2_CONTEXT_STATUS 0x1d791
+#define regSDMA4_RLC2_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA4_RLC2_DOORBELL 0x1d792
+#define regSDMA4_RLC2_DOORBELL_BASE_IDX 0
+#define regSDMA4_RLC2_STATUS 0x1d7a8
+#define regSDMA4_RLC2_STATUS_BASE_IDX 0
+#define regSDMA4_RLC2_DOORBELL_LOG 0x1d7a9
+#define regSDMA4_RLC2_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA4_RLC2_WATERMARK 0x1d7aa
+#define regSDMA4_RLC2_WATERMARK_BASE_IDX 0
+#define regSDMA4_RLC2_DOORBELL_OFFSET 0x1d7ab
+#define regSDMA4_RLC2_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA4_RLC2_CSA_ADDR_LO 0x1d7ac
+#define regSDMA4_RLC2_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA4_RLC2_CSA_ADDR_HI 0x1d7ad
+#define regSDMA4_RLC2_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA4_RLC2_IB_SUB_REMAIN 0x1d7af
+#define regSDMA4_RLC2_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA4_RLC2_PREEMPT 0x1d7b0
+#define regSDMA4_RLC2_PREEMPT_BASE_IDX 0
+#define regSDMA4_RLC2_DUMMY_REG 0x1d7b1
+#define regSDMA4_RLC2_DUMMY_REG_BASE_IDX 0
+#define regSDMA4_RLC2_RB_WPTR_POLL_ADDR_HI 0x1d7b2
+#define regSDMA4_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA4_RLC2_RB_WPTR_POLL_ADDR_LO 0x1d7b3
+#define regSDMA4_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA4_RLC2_RB_AQL_CNTL 0x1d7b4
+#define regSDMA4_RLC2_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA4_RLC2_MINOR_PTR_UPDATE 0x1d7b5
+#define regSDMA4_RLC2_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA4_RLC2_MIDCMD_DATA0 0x1d7c0
+#define regSDMA4_RLC2_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA4_RLC2_MIDCMD_DATA1 0x1d7c1
+#define regSDMA4_RLC2_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA4_RLC2_MIDCMD_DATA2 0x1d7c2
+#define regSDMA4_RLC2_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA4_RLC2_MIDCMD_DATA3 0x1d7c3
+#define regSDMA4_RLC2_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA4_RLC2_MIDCMD_DATA4 0x1d7c4
+#define regSDMA4_RLC2_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA4_RLC2_MIDCMD_DATA5 0x1d7c5
+#define regSDMA4_RLC2_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA4_RLC2_MIDCMD_DATA6 0x1d7c6
+#define regSDMA4_RLC2_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA4_RLC2_MIDCMD_DATA7 0x1d7c7
+#define regSDMA4_RLC2_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA4_RLC2_MIDCMD_DATA8 0x1d7c8
+#define regSDMA4_RLC2_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA4_RLC2_MIDCMD_DATA9 0x1d7c9
+#define regSDMA4_RLC2_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA4_RLC2_MIDCMD_DATA10 0x1d7ca
+#define regSDMA4_RLC2_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA4_RLC2_MIDCMD_CNTL 0x1d7cb
+#define regSDMA4_RLC2_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA4_RLC3_RB_CNTL 0x1d7d8
+#define regSDMA4_RLC3_RB_CNTL_BASE_IDX 0
+#define regSDMA4_RLC3_RB_BASE 0x1d7d9
+#define regSDMA4_RLC3_RB_BASE_BASE_IDX 0
+#define regSDMA4_RLC3_RB_BASE_HI 0x1d7da
+#define regSDMA4_RLC3_RB_BASE_HI_BASE_IDX 0
+#define regSDMA4_RLC3_RB_RPTR 0x1d7db
+#define regSDMA4_RLC3_RB_RPTR_BASE_IDX 0
+#define regSDMA4_RLC3_RB_RPTR_HI 0x1d7dc
+#define regSDMA4_RLC3_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA4_RLC3_RB_WPTR 0x1d7dd
+#define regSDMA4_RLC3_RB_WPTR_BASE_IDX 0
+#define regSDMA4_RLC3_RB_WPTR_HI 0x1d7de
+#define regSDMA4_RLC3_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA4_RLC3_RB_WPTR_POLL_CNTL 0x1d7df
+#define regSDMA4_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA4_RLC3_RB_RPTR_ADDR_HI 0x1d7e0
+#define regSDMA4_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA4_RLC3_RB_RPTR_ADDR_LO 0x1d7e1
+#define regSDMA4_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA4_RLC3_IB_CNTL 0x1d7e2
+#define regSDMA4_RLC3_IB_CNTL_BASE_IDX 0
+#define regSDMA4_RLC3_IB_RPTR 0x1d7e3
+#define regSDMA4_RLC3_IB_RPTR_BASE_IDX 0
+#define regSDMA4_RLC3_IB_OFFSET 0x1d7e4
+#define regSDMA4_RLC3_IB_OFFSET_BASE_IDX 0
+#define regSDMA4_RLC3_IB_BASE_LO 0x1d7e5
+#define regSDMA4_RLC3_IB_BASE_LO_BASE_IDX 0
+#define regSDMA4_RLC3_IB_BASE_HI 0x1d7e6
+#define regSDMA4_RLC3_IB_BASE_HI_BASE_IDX 0
+#define regSDMA4_RLC3_IB_SIZE 0x1d7e7
+#define regSDMA4_RLC3_IB_SIZE_BASE_IDX 0
+#define regSDMA4_RLC3_SKIP_CNTL 0x1d7e8
+#define regSDMA4_RLC3_SKIP_CNTL_BASE_IDX 0
+#define regSDMA4_RLC3_CONTEXT_STATUS 0x1d7e9
+#define regSDMA4_RLC3_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA4_RLC3_DOORBELL 0x1d7ea
+#define regSDMA4_RLC3_DOORBELL_BASE_IDX 0
+#define regSDMA4_RLC3_STATUS 0x1d800
+#define regSDMA4_RLC3_STATUS_BASE_IDX 0
+#define regSDMA4_RLC3_DOORBELL_LOG 0x1d801
+#define regSDMA4_RLC3_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA4_RLC3_WATERMARK 0x1d802
+#define regSDMA4_RLC3_WATERMARK_BASE_IDX 0
+#define regSDMA4_RLC3_DOORBELL_OFFSET 0x1d803
+#define regSDMA4_RLC3_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA4_RLC3_CSA_ADDR_LO 0x1d804
+#define regSDMA4_RLC3_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA4_RLC3_CSA_ADDR_HI 0x1d805
+#define regSDMA4_RLC3_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA4_RLC3_IB_SUB_REMAIN 0x1d807
+#define regSDMA4_RLC3_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA4_RLC3_PREEMPT 0x1d808
+#define regSDMA4_RLC3_PREEMPT_BASE_IDX 0
+#define regSDMA4_RLC3_DUMMY_REG 0x1d809
+#define regSDMA4_RLC3_DUMMY_REG_BASE_IDX 0
+#define regSDMA4_RLC3_RB_WPTR_POLL_ADDR_HI 0x1d80a
+#define regSDMA4_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA4_RLC3_RB_WPTR_POLL_ADDR_LO 0x1d80b
+#define regSDMA4_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA4_RLC3_RB_AQL_CNTL 0x1d80c
+#define regSDMA4_RLC3_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA4_RLC3_MINOR_PTR_UPDATE 0x1d80d
+#define regSDMA4_RLC3_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA4_RLC3_MIDCMD_DATA0 0x1d818
+#define regSDMA4_RLC3_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA4_RLC3_MIDCMD_DATA1 0x1d819
+#define regSDMA4_RLC3_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA4_RLC3_MIDCMD_DATA2 0x1d81a
+#define regSDMA4_RLC3_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA4_RLC3_MIDCMD_DATA3 0x1d81b
+#define regSDMA4_RLC3_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA4_RLC3_MIDCMD_DATA4 0x1d81c
+#define regSDMA4_RLC3_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA4_RLC3_MIDCMD_DATA5 0x1d81d
+#define regSDMA4_RLC3_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA4_RLC3_MIDCMD_DATA6 0x1d81e
+#define regSDMA4_RLC3_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA4_RLC3_MIDCMD_DATA7 0x1d81f
+#define regSDMA4_RLC3_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA4_RLC3_MIDCMD_DATA8 0x1d820
+#define regSDMA4_RLC3_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA4_RLC3_MIDCMD_DATA9 0x1d821
+#define regSDMA4_RLC3_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA4_RLC3_MIDCMD_DATA10 0x1d822
+#define regSDMA4_RLC3_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA4_RLC3_MIDCMD_CNTL 0x1d823
+#define regSDMA4_RLC3_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA4_RLC4_RB_CNTL 0x1d830
+#define regSDMA4_RLC4_RB_CNTL_BASE_IDX 0
+#define regSDMA4_RLC4_RB_BASE 0x1d831
+#define regSDMA4_RLC4_RB_BASE_BASE_IDX 0
+#define regSDMA4_RLC4_RB_BASE_HI 0x1d832
+#define regSDMA4_RLC4_RB_BASE_HI_BASE_IDX 0
+#define regSDMA4_RLC4_RB_RPTR 0x1d833
+#define regSDMA4_RLC4_RB_RPTR_BASE_IDX 0
+#define regSDMA4_RLC4_RB_RPTR_HI 0x1d834
+#define regSDMA4_RLC4_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA4_RLC4_RB_WPTR 0x1d835
+#define regSDMA4_RLC4_RB_WPTR_BASE_IDX 0
+#define regSDMA4_RLC4_RB_WPTR_HI 0x1d836
+#define regSDMA4_RLC4_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA4_RLC4_RB_WPTR_POLL_CNTL 0x1d837
+#define regSDMA4_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA4_RLC4_RB_RPTR_ADDR_HI 0x1d838
+#define regSDMA4_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA4_RLC4_RB_RPTR_ADDR_LO 0x1d839
+#define regSDMA4_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA4_RLC4_IB_CNTL 0x1d83a
+#define regSDMA4_RLC4_IB_CNTL_BASE_IDX 0
+#define regSDMA4_RLC4_IB_RPTR 0x1d83b
+#define regSDMA4_RLC4_IB_RPTR_BASE_IDX 0
+#define regSDMA4_RLC4_IB_OFFSET 0x1d83c
+#define regSDMA4_RLC4_IB_OFFSET_BASE_IDX 0
+#define regSDMA4_RLC4_IB_BASE_LO 0x1d83d
+#define regSDMA4_RLC4_IB_BASE_LO_BASE_IDX 0
+#define regSDMA4_RLC4_IB_BASE_HI 0x1d83e
+#define regSDMA4_RLC4_IB_BASE_HI_BASE_IDX 0
+#define regSDMA4_RLC4_IB_SIZE 0x1d83f
+#define regSDMA4_RLC4_IB_SIZE_BASE_IDX 0
+#define regSDMA4_RLC4_SKIP_CNTL 0x1d840
+#define regSDMA4_RLC4_SKIP_CNTL_BASE_IDX 0
+#define regSDMA4_RLC4_CONTEXT_STATUS 0x1d841
+#define regSDMA4_RLC4_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA4_RLC4_DOORBELL 0x1d842
+#define regSDMA4_RLC4_DOORBELL_BASE_IDX 0
+#define regSDMA4_RLC4_STATUS 0x1d858
+#define regSDMA4_RLC4_STATUS_BASE_IDX 0
+#define regSDMA4_RLC4_DOORBELL_LOG 0x1d859
+#define regSDMA4_RLC4_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA4_RLC4_WATERMARK 0x1d85a
+#define regSDMA4_RLC4_WATERMARK_BASE_IDX 0
+#define regSDMA4_RLC4_DOORBELL_OFFSET 0x1d85b
+#define regSDMA4_RLC4_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA4_RLC4_CSA_ADDR_LO 0x1d85c
+#define regSDMA4_RLC4_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA4_RLC4_CSA_ADDR_HI 0x1d85d
+#define regSDMA4_RLC4_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA4_RLC4_IB_SUB_REMAIN 0x1d85f
+#define regSDMA4_RLC4_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA4_RLC4_PREEMPT 0x1d860
+#define regSDMA4_RLC4_PREEMPT_BASE_IDX 0
+#define regSDMA4_RLC4_DUMMY_REG 0x1d861
+#define regSDMA4_RLC4_DUMMY_REG_BASE_IDX 0
+#define regSDMA4_RLC4_RB_WPTR_POLL_ADDR_HI 0x1d862
+#define regSDMA4_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA4_RLC4_RB_WPTR_POLL_ADDR_LO 0x1d863
+#define regSDMA4_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA4_RLC4_RB_AQL_CNTL 0x1d864
+#define regSDMA4_RLC4_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA4_RLC4_MINOR_PTR_UPDATE 0x1d865
+#define regSDMA4_RLC4_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA4_RLC4_MIDCMD_DATA0 0x1d870
+#define regSDMA4_RLC4_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA4_RLC4_MIDCMD_DATA1 0x1d871
+#define regSDMA4_RLC4_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA4_RLC4_MIDCMD_DATA2 0x1d872
+#define regSDMA4_RLC4_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA4_RLC4_MIDCMD_DATA3 0x1d873
+#define regSDMA4_RLC4_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA4_RLC4_MIDCMD_DATA4 0x1d874
+#define regSDMA4_RLC4_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA4_RLC4_MIDCMD_DATA5 0x1d875
+#define regSDMA4_RLC4_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA4_RLC4_MIDCMD_DATA6 0x1d876
+#define regSDMA4_RLC4_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA4_RLC4_MIDCMD_DATA7 0x1d877
+#define regSDMA4_RLC4_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA4_RLC4_MIDCMD_DATA8 0x1d878
+#define regSDMA4_RLC4_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA4_RLC4_MIDCMD_DATA9 0x1d879
+#define regSDMA4_RLC4_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA4_RLC4_MIDCMD_DATA10 0x1d87a
+#define regSDMA4_RLC4_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA4_RLC4_MIDCMD_CNTL 0x1d87b
+#define regSDMA4_RLC4_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA4_RLC5_RB_CNTL 0x1d888
+#define regSDMA4_RLC5_RB_CNTL_BASE_IDX 0
+#define regSDMA4_RLC5_RB_BASE 0x1d889
+#define regSDMA4_RLC5_RB_BASE_BASE_IDX 0
+#define regSDMA4_RLC5_RB_BASE_HI 0x1d88a
+#define regSDMA4_RLC5_RB_BASE_HI_BASE_IDX 0
+#define regSDMA4_RLC5_RB_RPTR 0x1d88b
+#define regSDMA4_RLC5_RB_RPTR_BASE_IDX 0
+#define regSDMA4_RLC5_RB_RPTR_HI 0x1d88c
+#define regSDMA4_RLC5_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA4_RLC5_RB_WPTR 0x1d88d
+#define regSDMA4_RLC5_RB_WPTR_BASE_IDX 0
+#define regSDMA4_RLC5_RB_WPTR_HI 0x1d88e
+#define regSDMA4_RLC5_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA4_RLC5_RB_WPTR_POLL_CNTL 0x1d88f
+#define regSDMA4_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA4_RLC5_RB_RPTR_ADDR_HI 0x1d890
+#define regSDMA4_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA4_RLC5_RB_RPTR_ADDR_LO 0x1d891
+#define regSDMA4_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA4_RLC5_IB_CNTL 0x1d892
+#define regSDMA4_RLC5_IB_CNTL_BASE_IDX 0
+#define regSDMA4_RLC5_IB_RPTR 0x1d893
+#define regSDMA4_RLC5_IB_RPTR_BASE_IDX 0
+#define regSDMA4_RLC5_IB_OFFSET 0x1d894
+#define regSDMA4_RLC5_IB_OFFSET_BASE_IDX 0
+#define regSDMA4_RLC5_IB_BASE_LO 0x1d895
+#define regSDMA4_RLC5_IB_BASE_LO_BASE_IDX 0
+#define regSDMA4_RLC5_IB_BASE_HI 0x1d896
+#define regSDMA4_RLC5_IB_BASE_HI_BASE_IDX 0
+#define regSDMA4_RLC5_IB_SIZE 0x1d897
+#define regSDMA4_RLC5_IB_SIZE_BASE_IDX 0
+#define regSDMA4_RLC5_SKIP_CNTL 0x1d898
+#define regSDMA4_RLC5_SKIP_CNTL_BASE_IDX 0
+#define regSDMA4_RLC5_CONTEXT_STATUS 0x1d899
+#define regSDMA4_RLC5_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA4_RLC5_DOORBELL 0x1d89a
+#define regSDMA4_RLC5_DOORBELL_BASE_IDX 0
+#define regSDMA4_RLC5_STATUS 0x1d8b0
+#define regSDMA4_RLC5_STATUS_BASE_IDX 0
+#define regSDMA4_RLC5_DOORBELL_LOG 0x1d8b1
+#define regSDMA4_RLC5_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA4_RLC5_WATERMARK 0x1d8b2
+#define regSDMA4_RLC5_WATERMARK_BASE_IDX 0
+#define regSDMA4_RLC5_DOORBELL_OFFSET 0x1d8b3
+#define regSDMA4_RLC5_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA4_RLC5_CSA_ADDR_LO 0x1d8b4
+#define regSDMA4_RLC5_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA4_RLC5_CSA_ADDR_HI 0x1d8b5
+#define regSDMA4_RLC5_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA4_RLC5_IB_SUB_REMAIN 0x1d8b7
+#define regSDMA4_RLC5_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA4_RLC5_PREEMPT 0x1d8b8
+#define regSDMA4_RLC5_PREEMPT_BASE_IDX 0
+#define regSDMA4_RLC5_DUMMY_REG 0x1d8b9
+#define regSDMA4_RLC5_DUMMY_REG_BASE_IDX 0
+#define regSDMA4_RLC5_RB_WPTR_POLL_ADDR_HI 0x1d8ba
+#define regSDMA4_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA4_RLC5_RB_WPTR_POLL_ADDR_LO 0x1d8bb
+#define regSDMA4_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA4_RLC5_RB_AQL_CNTL 0x1d8bc
+#define regSDMA4_RLC5_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA4_RLC5_MINOR_PTR_UPDATE 0x1d8bd
+#define regSDMA4_RLC5_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA4_RLC5_MIDCMD_DATA0 0x1d8c8
+#define regSDMA4_RLC5_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA4_RLC5_MIDCMD_DATA1 0x1d8c9
+#define regSDMA4_RLC5_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA4_RLC5_MIDCMD_DATA2 0x1d8ca
+#define regSDMA4_RLC5_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA4_RLC5_MIDCMD_DATA3 0x1d8cb
+#define regSDMA4_RLC5_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA4_RLC5_MIDCMD_DATA4 0x1d8cc
+#define regSDMA4_RLC5_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA4_RLC5_MIDCMD_DATA5 0x1d8cd
+#define regSDMA4_RLC5_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA4_RLC5_MIDCMD_DATA6 0x1d8ce
+#define regSDMA4_RLC5_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA4_RLC5_MIDCMD_DATA7 0x1d8cf
+#define regSDMA4_RLC5_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA4_RLC5_MIDCMD_DATA8 0x1d8d0
+#define regSDMA4_RLC5_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA4_RLC5_MIDCMD_DATA9 0x1d8d1
+#define regSDMA4_RLC5_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA4_RLC5_MIDCMD_DATA10 0x1d8d2
+#define regSDMA4_RLC5_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA4_RLC5_MIDCMD_CNTL 0x1d8d3
+#define regSDMA4_RLC5_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA4_RLC6_RB_CNTL 0x1d8e0
+#define regSDMA4_RLC6_RB_CNTL_BASE_IDX 0
+#define regSDMA4_RLC6_RB_BASE 0x1d8e1
+#define regSDMA4_RLC6_RB_BASE_BASE_IDX 0
+#define regSDMA4_RLC6_RB_BASE_HI 0x1d8e2
+#define regSDMA4_RLC6_RB_BASE_HI_BASE_IDX 0
+#define regSDMA4_RLC6_RB_RPTR 0x1d8e3
+#define regSDMA4_RLC6_RB_RPTR_BASE_IDX 0
+#define regSDMA4_RLC6_RB_RPTR_HI 0x1d8e4
+#define regSDMA4_RLC6_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA4_RLC6_RB_WPTR 0x1d8e5
+#define regSDMA4_RLC6_RB_WPTR_BASE_IDX 0
+#define regSDMA4_RLC6_RB_WPTR_HI 0x1d8e6
+#define regSDMA4_RLC6_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA4_RLC6_RB_WPTR_POLL_CNTL 0x1d8e7
+#define regSDMA4_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA4_RLC6_RB_RPTR_ADDR_HI 0x1d8e8
+#define regSDMA4_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA4_RLC6_RB_RPTR_ADDR_LO 0x1d8e9
+#define regSDMA4_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA4_RLC6_IB_CNTL 0x1d8ea
+#define regSDMA4_RLC6_IB_CNTL_BASE_IDX 0
+#define regSDMA4_RLC6_IB_RPTR 0x1d8eb
+#define regSDMA4_RLC6_IB_RPTR_BASE_IDX 0
+#define regSDMA4_RLC6_IB_OFFSET 0x1d8ec
+#define regSDMA4_RLC6_IB_OFFSET_BASE_IDX 0
+#define regSDMA4_RLC6_IB_BASE_LO 0x1d8ed
+#define regSDMA4_RLC6_IB_BASE_LO_BASE_IDX 0
+#define regSDMA4_RLC6_IB_BASE_HI 0x1d8ee
+#define regSDMA4_RLC6_IB_BASE_HI_BASE_IDX 0
+#define regSDMA4_RLC6_IB_SIZE 0x1d8ef
+#define regSDMA4_RLC6_IB_SIZE_BASE_IDX 0
+#define regSDMA4_RLC6_SKIP_CNTL 0x1d8f0
+#define regSDMA4_RLC6_SKIP_CNTL_BASE_IDX 0
+#define regSDMA4_RLC6_CONTEXT_STATUS 0x1d8f1
+#define regSDMA4_RLC6_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA4_RLC6_DOORBELL 0x1d8f2
+#define regSDMA4_RLC6_DOORBELL_BASE_IDX 0
+#define regSDMA4_RLC6_STATUS 0x1d908
+#define regSDMA4_RLC6_STATUS_BASE_IDX 0
+#define regSDMA4_RLC6_DOORBELL_LOG 0x1d909
+#define regSDMA4_RLC6_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA4_RLC6_WATERMARK 0x1d90a
+#define regSDMA4_RLC6_WATERMARK_BASE_IDX 0
+#define regSDMA4_RLC6_DOORBELL_OFFSET 0x1d90b
+#define regSDMA4_RLC6_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA4_RLC6_CSA_ADDR_LO 0x1d90c
+#define regSDMA4_RLC6_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA4_RLC6_CSA_ADDR_HI 0x1d90d
+#define regSDMA4_RLC6_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA4_RLC6_IB_SUB_REMAIN 0x1d90f
+#define regSDMA4_RLC6_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA4_RLC6_PREEMPT 0x1d910
+#define regSDMA4_RLC6_PREEMPT_BASE_IDX 0
+#define regSDMA4_RLC6_DUMMY_REG 0x1d911
+#define regSDMA4_RLC6_DUMMY_REG_BASE_IDX 0
+#define regSDMA4_RLC6_RB_WPTR_POLL_ADDR_HI 0x1d912
+#define regSDMA4_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA4_RLC6_RB_WPTR_POLL_ADDR_LO 0x1d913
+#define regSDMA4_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA4_RLC6_RB_AQL_CNTL 0x1d914
+#define regSDMA4_RLC6_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA4_RLC6_MINOR_PTR_UPDATE 0x1d915
+#define regSDMA4_RLC6_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA4_RLC6_MIDCMD_DATA0 0x1d920
+#define regSDMA4_RLC6_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA4_RLC6_MIDCMD_DATA1 0x1d921
+#define regSDMA4_RLC6_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA4_RLC6_MIDCMD_DATA2 0x1d922
+#define regSDMA4_RLC6_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA4_RLC6_MIDCMD_DATA3 0x1d923
+#define regSDMA4_RLC6_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA4_RLC6_MIDCMD_DATA4 0x1d924
+#define regSDMA4_RLC6_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA4_RLC6_MIDCMD_DATA5 0x1d925
+#define regSDMA4_RLC6_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA4_RLC6_MIDCMD_DATA6 0x1d926
+#define regSDMA4_RLC6_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA4_RLC6_MIDCMD_DATA7 0x1d927
+#define regSDMA4_RLC6_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA4_RLC6_MIDCMD_DATA8 0x1d928
+#define regSDMA4_RLC6_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA4_RLC6_MIDCMD_DATA9 0x1d929
+#define regSDMA4_RLC6_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA4_RLC6_MIDCMD_DATA10 0x1d92a
+#define regSDMA4_RLC6_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA4_RLC6_MIDCMD_CNTL 0x1d92b
+#define regSDMA4_RLC6_MIDCMD_CNTL_BASE_IDX 0
+#define regSDMA4_RLC7_RB_CNTL 0x1d938
+#define regSDMA4_RLC7_RB_CNTL_BASE_IDX 0
+#define regSDMA4_RLC7_RB_BASE 0x1d939
+#define regSDMA4_RLC7_RB_BASE_BASE_IDX 0
+#define regSDMA4_RLC7_RB_BASE_HI 0x1d93a
+#define regSDMA4_RLC7_RB_BASE_HI_BASE_IDX 0
+#define regSDMA4_RLC7_RB_RPTR 0x1d93b
+#define regSDMA4_RLC7_RB_RPTR_BASE_IDX 0
+#define regSDMA4_RLC7_RB_RPTR_HI 0x1d93c
+#define regSDMA4_RLC7_RB_RPTR_HI_BASE_IDX 0
+#define regSDMA4_RLC7_RB_WPTR 0x1d93d
+#define regSDMA4_RLC7_RB_WPTR_BASE_IDX 0
+#define regSDMA4_RLC7_RB_WPTR_HI 0x1d93e
+#define regSDMA4_RLC7_RB_WPTR_HI_BASE_IDX 0
+#define regSDMA4_RLC7_RB_WPTR_POLL_CNTL 0x1d93f
+#define regSDMA4_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define regSDMA4_RLC7_RB_RPTR_ADDR_HI 0x1d940
+#define regSDMA4_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define regSDMA4_RLC7_RB_RPTR_ADDR_LO 0x1d941
+#define regSDMA4_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define regSDMA4_RLC7_IB_CNTL 0x1d942
+#define regSDMA4_RLC7_IB_CNTL_BASE_IDX 0
+#define regSDMA4_RLC7_IB_RPTR 0x1d943
+#define regSDMA4_RLC7_IB_RPTR_BASE_IDX 0
+#define regSDMA4_RLC7_IB_OFFSET 0x1d944
+#define regSDMA4_RLC7_IB_OFFSET_BASE_IDX 0
+#define regSDMA4_RLC7_IB_BASE_LO 0x1d945
+#define regSDMA4_RLC7_IB_BASE_LO_BASE_IDX 0
+#define regSDMA4_RLC7_IB_BASE_HI 0x1d946
+#define regSDMA4_RLC7_IB_BASE_HI_BASE_IDX 0
+#define regSDMA4_RLC7_IB_SIZE 0x1d947
+#define regSDMA4_RLC7_IB_SIZE_BASE_IDX 0
+#define regSDMA4_RLC7_SKIP_CNTL 0x1d948
+#define regSDMA4_RLC7_SKIP_CNTL_BASE_IDX 0
+#define regSDMA4_RLC7_CONTEXT_STATUS 0x1d949
+#define regSDMA4_RLC7_CONTEXT_STATUS_BASE_IDX 0
+#define regSDMA4_RLC7_DOORBELL 0x1d94a
+#define regSDMA4_RLC7_DOORBELL_BASE_IDX 0
+#define regSDMA4_RLC7_STATUS 0x1d960
+#define regSDMA4_RLC7_STATUS_BASE_IDX 0
+#define regSDMA4_RLC7_DOORBELL_LOG 0x1d961
+#define regSDMA4_RLC7_DOORBELL_LOG_BASE_IDX 0
+#define regSDMA4_RLC7_WATERMARK 0x1d962
+#define regSDMA4_RLC7_WATERMARK_BASE_IDX 0
+#define regSDMA4_RLC7_DOORBELL_OFFSET 0x1d963
+#define regSDMA4_RLC7_DOORBELL_OFFSET_BASE_IDX 0
+#define regSDMA4_RLC7_CSA_ADDR_LO 0x1d964
+#define regSDMA4_RLC7_CSA_ADDR_LO_BASE_IDX 0
+#define regSDMA4_RLC7_CSA_ADDR_HI 0x1d965
+#define regSDMA4_RLC7_CSA_ADDR_HI_BASE_IDX 0
+#define regSDMA4_RLC7_IB_SUB_REMAIN 0x1d967
+#define regSDMA4_RLC7_IB_SUB_REMAIN_BASE_IDX 0
+#define regSDMA4_RLC7_PREEMPT 0x1d968
+#define regSDMA4_RLC7_PREEMPT_BASE_IDX 0
+#define regSDMA4_RLC7_DUMMY_REG 0x1d969
+#define regSDMA4_RLC7_DUMMY_REG_BASE_IDX 0
+#define regSDMA4_RLC7_RB_WPTR_POLL_ADDR_HI 0x1d96a
+#define regSDMA4_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define regSDMA4_RLC7_RB_WPTR_POLL_ADDR_LO 0x1d96b
+#define regSDMA4_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define regSDMA4_RLC7_RB_AQL_CNTL 0x1d96c
+#define regSDMA4_RLC7_RB_AQL_CNTL_BASE_IDX 0
+#define regSDMA4_RLC7_MINOR_PTR_UPDATE 0x1d96d
+#define regSDMA4_RLC7_MINOR_PTR_UPDATE_BASE_IDX 0
+#define regSDMA4_RLC7_MIDCMD_DATA0 0x1d978
+#define regSDMA4_RLC7_MIDCMD_DATA0_BASE_IDX 0
+#define regSDMA4_RLC7_MIDCMD_DATA1 0x1d979
+#define regSDMA4_RLC7_MIDCMD_DATA1_BASE_IDX 0
+#define regSDMA4_RLC7_MIDCMD_DATA2 0x1d97a
+#define regSDMA4_RLC7_MIDCMD_DATA2_BASE_IDX 0
+#define regSDMA4_RLC7_MIDCMD_DATA3 0x1d97b
+#define regSDMA4_RLC7_MIDCMD_DATA3_BASE_IDX 0
+#define regSDMA4_RLC7_MIDCMD_DATA4 0x1d97c
+#define regSDMA4_RLC7_MIDCMD_DATA4_BASE_IDX 0
+#define regSDMA4_RLC7_MIDCMD_DATA5 0x1d97d
+#define regSDMA4_RLC7_MIDCMD_DATA5_BASE_IDX 0
+#define regSDMA4_RLC7_MIDCMD_DATA6 0x1d97e
+#define regSDMA4_RLC7_MIDCMD_DATA6_BASE_IDX 0
+#define regSDMA4_RLC7_MIDCMD_DATA7 0x1d97f
+#define regSDMA4_RLC7_MIDCMD_DATA7_BASE_IDX 0
+#define regSDMA4_RLC7_MIDCMD_DATA8 0x1d980
+#define regSDMA4_RLC7_MIDCMD_DATA8_BASE_IDX 0
+#define regSDMA4_RLC7_MIDCMD_DATA9 0x1d981
+#define regSDMA4_RLC7_MIDCMD_DATA9_BASE_IDX 0
+#define regSDMA4_RLC7_MIDCMD_DATA10 0x1d982
+#define regSDMA4_RLC7_MIDCMD_DATA10_BASE_IDX 0
+#define regSDMA4_RLC7_MIDCMD_CNTL 0x1d983
+#define regSDMA4_RLC7_MIDCMD_CNTL_BASE_IDX 0
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_0_sh_mask.h
new file mode 100644
index 000000000000..4464af3be22d
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_0_sh_mask.h
@@ -0,0 +1,13922 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef _sdma_4_4_0_SH_MASK_HEADER
+#define _sdma_4_4_0_SH_MASK_HEADER
+
+
+// addressBlock: sdma0_sdma0dec
+//SDMA0_UCODE_ADDR
+#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0
+#define SDMA0_UCODE_ADDR__VALUE_MASK 0x00003FFFL
+//SDMA0_UCODE_DATA
+#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0
+#define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL
+//SDMA0_VF_ENABLE
+#define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0
+#define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x00000001L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0
+#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1
+#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x00000001L
+#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x00000002L
+//SDMA0_CONTEXT_GROUP_BOUNDARY
+#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0
+#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL
+//SDMA0_POWER_CNTL
+#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0
+#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1
+#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2
+#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3
+#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
+#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9
+#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
+#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb
+#define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc
+#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a
+#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L
+#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L
+#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L
+#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L
+#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L
+#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L
+#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L
+#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L
+#define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L
+#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
+//SDMA0_CLK_CTRL
+#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define SDMA0_CLK_CTRL__RESERVED_MASK 0x00FFF000L
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//SDMA0_CNTL
+#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0
+#define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1
+#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
+#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
+#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5
+#define SDMA0_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x6
+#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11
+#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
+#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
+#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
+#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e
+#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L
+#define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L
+#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L
+#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L
+#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L
+#define SDMA0_CNTL__MIDCMD_EXPIRE_ENABLE_MASK 0x00000040L
+#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L
+#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L
+#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L
+#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L
+#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L
+//SDMA0_CHICKEN_BITS
+#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
+#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
+#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
+#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8
+#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
+#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
+#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11
+#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
+#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
+#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19
+#define SDMA0_CHICKEN_BITS__SRAM_FGCG_ENABLE__SHIFT 0x1a
+#define SDMA0_CHICKEN_BITS__RESERVED__SHIFT 0x1b
+#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L
+#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L
+#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L
+#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L
+#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L
+#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L
+#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L
+#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L
+#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L
+#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L
+#define SDMA0_CHICKEN_BITS__SRAM_FGCG_ENABLE_MASK 0x04000000L
+#define SDMA0_CHICKEN_BITS__RESERVED_MASK 0xF8000000L
+//SDMA0_GB_ADDR_CONFIG
+#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
+#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
+#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
+#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
+#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
+#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
+//SDMA0_GB_ADDR_CONFIG_READ
+#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0
+#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc
+#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13
+#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L
+#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
+#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L
+#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L
+//SDMA0_RB_RPTR_FETCH_HI
+#define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_SEM_WAIT_FAIL_TIMER_CNTL
+#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
+#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL
+//SDMA0_RB_RPTR_FETCH
+#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
+#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL
+//SDMA0_IB_OFFSET_FETCH
+#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
+#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL
+//SDMA0_PROGRAM
+#define SDMA0_PROGRAM__STREAM__SHIFT 0x0
+#define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL
+//SDMA0_STATUS_REG
+#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0
+#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1
+#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2
+#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3
+#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
+#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
+#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
+#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
+#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
+#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9
+#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa
+#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
+#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc
+#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
+#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe
+#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
+#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10
+#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
+#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
+#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
+#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14
+#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
+#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
+#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
+#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a
+#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
+#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
+#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e
+#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
+#define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L
+#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L
+#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L
+#define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L
+#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L
+#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L
+#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L
+#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L
+#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L
+#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L
+#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L
+#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L
+#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L
+#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L
+#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L
+#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L
+#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L
+#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L
+#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L
+#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L
+#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L
+#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L
+#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L
+#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L
+#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L
+#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L
+#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L
+#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L
+#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L
+//SDMA0_STATUS1_REG
+#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
+#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
+#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
+#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
+#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
+#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
+#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
+#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9
+#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
+#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
+#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
+#define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf
+#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
+#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
+#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L
+#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L
+#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L
+#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L
+#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L
+#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L
+#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L
+#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L
+#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L
+#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L
+#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L
+#define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L
+#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L
+#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L
+//SDMA0_RD_BURST_CNTL
+#define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0
+#define SDMA0_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2
+#define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L
+#define SDMA0_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL
+//SDMA0_HBM_PAGE_CONFIG
+#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0
+#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L
+//SDMA0_UCODE_CHECKSUM
+#define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0
+#define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL
+//SDMA0_F32_CNTL
+#define SDMA0_F32_CNTL__HALT__SHIFT 0x0
+#define SDMA0_F32_CNTL__STEP__SHIFT 0x1
+#define SDMA0_F32_CNTL__RESET__SHIFT 0x8
+#define SDMA0_F32_CNTL__HALT_MASK 0x00000001L
+#define SDMA0_F32_CNTL__STEP_MASK 0x00000002L
+#define SDMA0_F32_CNTL__RESET_MASK 0x00000100L
+//SDMA0_FREEZE
+#define SDMA0_FREEZE__PREEMPT__SHIFT 0x0
+#define SDMA0_FREEZE__FREEZE__SHIFT 0x4
+#define SDMA0_FREEZE__FROZEN__SHIFT 0x5
+#define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6
+#define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L
+#define SDMA0_FREEZE__FREEZE_MASK 0x00000010L
+#define SDMA0_FREEZE__FROZEN_MASK 0x00000020L
+#define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L
+//SDMA0_PHASE0_QUANTUM
+#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL
+#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L
+#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L
+//SDMA0_PHASE1_QUANTUM
+#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL
+#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L
+#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L
+//SDMA_POWER_GATING
+#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x0
+#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x1
+#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x2
+#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x3
+#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4
+#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L
+#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L
+#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L
+#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L
+#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L
+//SDMA_PGFSM_CONFIG
+#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0
+#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8
+#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9
+#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
+#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb
+#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc
+#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd
+#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b
+#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c
+#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL
+#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L
+#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L
+#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L
+#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L
+#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L
+#define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L
+#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L
+#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L
+//SDMA_PGFSM_WRITE
+#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0
+#define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL
+//SDMA_PGFSM_READ
+#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0
+#define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL
+//CC_SDMA0_EDC_CONFIG
+#define CC_SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1
+#define CC_SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L
+//SDMA0_BA_THRESHOLD
+#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0
+#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10
+#define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL
+#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L
+//SDMA0_ID
+#define SDMA0_ID__DEVICE_ID__SHIFT 0x0
+#define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL
+//SDMA0_VERSION
+#define SDMA0_VERSION__MINVER__SHIFT 0x0
+#define SDMA0_VERSION__MAJVER__SHIFT 0x8
+#define SDMA0_VERSION__REV__SHIFT 0x10
+#define SDMA0_VERSION__MINVER_MASK 0x0000007FL
+#define SDMA0_VERSION__MAJVER_MASK 0x00007F00L
+#define SDMA0_VERSION__REV_MASK 0x003F0000L
+//SDMA0_EDC_COUNTER
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x0
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x2
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x4
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0x6
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0x8
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xa
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xc
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0x10
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x12
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x14
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x16
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x18
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x1a
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x1c
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x1e
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000003L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x0000000CL
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000030L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x000000C0L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000300L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00000C00L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00003000L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x0000C000L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00030000L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x000C0000L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00300000L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00C00000L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x03000000L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x0C000000L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x30000000L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0xC0000000L
+//SDMA0_EDC_COUNTER2
+#define SDMA0_EDC_COUNTER2__SDMA_UCODE_BUF_SED__SHIFT 0x0
+#define SDMA0_EDC_COUNTER2__SDMA_RB_CMD_BUF_SED__SHIFT 0x2
+#define SDMA0_EDC_COUNTER2__SDMA_IB_CMD_BUF_SED__SHIFT 0x4
+#define SDMA0_EDC_COUNTER2__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x6
+#define SDMA0_EDC_COUNTER2__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x8
+#define SDMA0_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED__SHIFT 0xa
+#define SDMA0_EDC_COUNTER2__SDMA_DATA_LUT_FIFO_SED__SHIFT 0xc
+#define SDMA0_EDC_COUNTER2__SDMA_SPLIT_DATA_BUF_SED__SHIFT 0xe
+#define SDMA0_EDC_COUNTER2__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10
+#define SDMA0_EDC_COUNTER2__SDMA_MC_RDRET_BUF_SED__SHIFT 0x12
+#define SDMA0_EDC_COUNTER2__SDMA_UCODE_BUF_SED_MASK 0x00000003L
+#define SDMA0_EDC_COUNTER2__SDMA_RB_CMD_BUF_SED_MASK 0x0000000CL
+#define SDMA0_EDC_COUNTER2__SDMA_IB_CMD_BUF_SED_MASK 0x00000030L
+#define SDMA0_EDC_COUNTER2__SDMA_UTCL1_RD_FIFO_SED_MASK 0x000000C0L
+#define SDMA0_EDC_COUNTER2__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000300L
+#define SDMA0_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED_MASK 0x00000C00L
+#define SDMA0_EDC_COUNTER2__SDMA_DATA_LUT_FIFO_SED_MASK 0x00003000L
+#define SDMA0_EDC_COUNTER2__SDMA_SPLIT_DATA_BUF_SED_MASK 0x0000C000L
+#define SDMA0_EDC_COUNTER2__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00030000L
+#define SDMA0_EDC_COUNTER2__SDMA_MC_RDRET_BUF_SED_MASK 0x000C0000L
+//SDMA0_STATUS2_REG
+#define SDMA0_STATUS2_REG__ID__SHIFT 0x0
+#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3
+#define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10
+#define SDMA0_STATUS2_REG__ID_MASK 0x00000007L
+#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L
+#define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L
+//SDMA0_ATOMIC_CNTL
+#define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0
+#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f
+#define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL
+#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L
+//SDMA0_ATOMIC_PREOP_LO
+#define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0
+#define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL
+//SDMA0_ATOMIC_PREOP_HI
+#define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0
+#define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL
+//SDMA0_UTCL1_CNTL
+#define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0
+#define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1
+#define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb
+#define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe
+#define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18
+#define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
+#define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L
+#define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL
+#define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L
+#define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L
+#define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L
+#define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L
+//SDMA0_UTCL1_WATERMK
+#define SDMA0_UTCL1_WATERMK__REQ_WATERMK__SHIFT 0x0
+#define SDMA0_UTCL1_WATERMK__REQ_DEPTH__SHIFT 0x3
+#define SDMA0_UTCL1_WATERMK__PAGE_WATERMK__SHIFT 0x5
+#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x8
+#define SDMA0_UTCL1_WATERMK__RESERVED__SHIFT 0x10
+#define SDMA0_UTCL1_WATERMK__REQ_WATERMK_MASK 0x00000007L
+#define SDMA0_UTCL1_WATERMK__REQ_DEPTH_MASK 0x00000018L
+#define SDMA0_UTCL1_WATERMK__PAGE_WATERMK_MASK 0x000000E0L
+#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x0000FF00L
+#define SDMA0_UTCL1_WATERMK__RESERVED_MASK 0xFFFF0000L
+//SDMA0_UTCL1_RD_STATUS
+#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
+#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
+#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
+#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
+#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
+#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
+#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
+#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
+#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
+#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
+#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
+#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
+#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
+#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
+#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
+#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
+#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
+#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
+#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12
+#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13
+#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14
+#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15
+#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16
+#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a
+#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
+#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e
+#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f
+#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
+#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L
+#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L
+#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L
+#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L
+#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L
+#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L
+#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L
+#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L
+#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L
+#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L
+#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L
+#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L
+#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L
+#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L
+#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L
+#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L
+#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L
+#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L
+#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L
+#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L
+#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L
+#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L
+#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L
+#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L
+#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L
+#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L
+//SDMA0_UTCL1_WR_STATUS
+#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
+#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
+#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
+#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
+#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
+#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
+#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
+#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
+#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
+#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
+#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
+#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
+#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
+#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
+#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
+#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
+#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
+#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
+#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12
+#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13
+#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14
+#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15
+#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16
+#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19
+#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c
+#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
+#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e
+#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f
+#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
+#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L
+#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L
+#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L
+#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L
+#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L
+#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L
+#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L
+#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L
+#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L
+#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L
+#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L
+#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L
+#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L
+#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L
+#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L
+#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L
+#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L
+#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L
+#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L
+#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L
+#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L
+#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L
+#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L
+#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L
+#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L
+#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L
+#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L
+//SDMA0_UTCL1_INV0
+#define SDMA0_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0
+#define SDMA0_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1
+#define SDMA0_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2
+#define SDMA0_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3
+#define SDMA0_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4
+#define SDMA0_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5
+#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6
+#define SDMA0_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7
+#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8
+#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9
+#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa
+#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb
+#define SDMA0_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc
+#define SDMA0_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c
+#define SDMA0_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L
+#define SDMA0_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L
+#define SDMA0_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L
+#define SDMA0_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L
+#define SDMA0_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L
+#define SDMA0_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L
+#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L
+#define SDMA0_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L
+#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L
+#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L
+#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L
+#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L
+#define SDMA0_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L
+#define SDMA0_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L
+//SDMA0_UTCL1_INV1
+#define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0
+#define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL
+//SDMA0_UTCL1_INV2
+#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0
+#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL
+//SDMA0_UTCL1_RD_XNACK0
+#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
+#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
+//SDMA0_UTCL1_RD_XNACK1
+#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
+#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4
+#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8
+#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a
+#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
+#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L
+#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
+#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L
+//SDMA0_UTCL1_WR_XNACK0
+#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
+#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
+//SDMA0_UTCL1_WR_XNACK1
+#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
+#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4
+#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8
+#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a
+#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
+#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L
+#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
+#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L
+//SDMA0_UTCL1_TIMEOUT
+#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0
+#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10
+#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL
+#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L
+//SDMA0_UTCL1_PAGE
+#define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0
+#define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1
+#define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6
+#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9
+#define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L
+#define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL
+#define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L
+#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L
+//SDMA0_POWER_CNTL_IDLE
+#define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0
+#define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10
+#define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18
+#define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL
+#define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L
+#define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L
+//SDMA0_RELAX_ORDERING_LUT
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0
+#define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1
+#define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4
+#define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6
+#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8
+#define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9
+#define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa
+#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb
+#define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc
+#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe
+#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b
+#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c
+#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
+#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e
+#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L
+#define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L
+#define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L
+#define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L
+#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L
+#define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L
+#define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L
+#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L
+#define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L
+#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L
+#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L
+#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L
+#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L
+#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L
+#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L
+//SDMA0_CHICKEN_BITS_2
+#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0
+#define SDMA0_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT 0x4
+#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL
+#define SDMA0_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK 0x00000010L
+//SDMA0_STATUS3_REG
+#define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0
+#define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10
+#define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14
+#define SDMA0_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15
+#define SDMA0_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16
+#define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL
+#define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L
+#define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L
+#define SDMA0_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L
+#define SDMA0_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L
+//SDMA0_PHYSICAL_ADDR_LO
+#define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0
+#define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1
+#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2
+#define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc
+#define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L
+#define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L
+#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L
+#define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L
+//SDMA0_PHYSICAL_ADDR_HI
+#define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL
+//SDMA0_PHASE2_QUANTUM
+#define SDMA0_PHASE2_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA0_PHASE2_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA0_PHASE2_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA0_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL
+#define SDMA0_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L
+#define SDMA0_PHASE2_QUANTUM__PREFER_MASK 0x40000000L
+//SDMA0_ERROR_LOG
+#define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x0
+#define SDMA0_ERROR_LOG__STATUS__SHIFT 0x10
+#define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL
+#define SDMA0_ERROR_LOG__STATUS_MASK 0xFFFF0000L
+//SDMA0_PUB_DUMMY_REG0
+#define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x0
+#define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL
+//SDMA0_PUB_DUMMY_REG1
+#define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x0
+#define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL
+//SDMA0_PUB_DUMMY_REG2
+#define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x0
+#define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL
+//SDMA0_PUB_DUMMY_REG3
+#define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x0
+#define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL
+//SDMA0_F32_COUNTER
+#define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0
+#define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL
+//SDMA0_PERFCNT_PERFCOUNTER0_CFG
+#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define SDMA0_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//SDMA0_PERFCNT_PERFCOUNTER1_CFG
+#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define SDMA0_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL
+#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+//SDMA0_PERFCNT_MISC_CNTL
+#define SDMA0_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x0
+#define SDMA0_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000FFFFL
+//SDMA0_PERFCNT_PERFCOUNTER_LO
+#define SDMA0_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define SDMA0_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//SDMA0_PERFCNT_PERFCOUNTER_HI
+#define SDMA0_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define SDMA0_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define SDMA0_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define SDMA0_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//SDMA0_CRD_CNTL
+#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7
+#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd
+#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L
+#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L
+//SDMA0_ULV_CNTL
+#define SDMA0_ULV_CNTL__HYSTERESIS__SHIFT 0x0
+#define SDMA0_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b
+#define SDMA0_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c
+#define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
+#define SDMA0_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e
+#define SDMA0_ULV_CNTL__ULV_STATUS__SHIFT 0x1f
+#define SDMA0_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL
+#define SDMA0_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L
+#define SDMA0_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L
+#define SDMA0_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L
+#define SDMA0_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L
+#define SDMA0_ULV_CNTL__ULV_STATUS_MASK 0x80000000L
+//SDMA0_EA_DBIT_ADDR_DATA
+#define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0
+#define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL
+//SDMA0_EA_DBIT_ADDR_INDEX
+#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0
+#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L
+//SDMA0_STATUS4_REG
+#define SDMA0_STATUS4_REG__IDLE__SHIFT 0x0
+#define SDMA0_STATUS4_REG__IH_OUTSTANDING__SHIFT 0x2
+#define SDMA0_STATUS4_REG__SEM_OUTSTANDING__SHIFT 0x3
+#define SDMA0_STATUS4_REG__MMHUB_RD_OUTSTANDING__SHIFT 0x4
+#define SDMA0_STATUS4_REG__MMHUB_WR_OUTSTANDING__SHIFT 0x5
+#define SDMA0_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT 0x6
+#define SDMA0_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT 0x7
+#define SDMA0_STATUS4_REG__REG_POLLING__SHIFT 0x8
+#define SDMA0_STATUS4_REG__MEM_POLLING__SHIFT 0x9
+#define SDMA0_STATUS4_REG__UTCL2_RD_XNACK__SHIFT 0xa
+#define SDMA0_STATUS4_REG__UTCL2_WR_XNACK__SHIFT 0xc
+#define SDMA0_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT 0xe
+#define SDMA0_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT 0x12
+#define SDMA0_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT 0x13
+#define SDMA0_STATUS4_REG__IDLE_MASK 0x00000001L
+#define SDMA0_STATUS4_REG__IH_OUTSTANDING_MASK 0x00000004L
+#define SDMA0_STATUS4_REG__SEM_OUTSTANDING_MASK 0x00000008L
+#define SDMA0_STATUS4_REG__MMHUB_RD_OUTSTANDING_MASK 0x00000010L
+#define SDMA0_STATUS4_REG__MMHUB_WR_OUTSTANDING_MASK 0x00000020L
+#define SDMA0_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK 0x00000040L
+#define SDMA0_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK 0x00000080L
+#define SDMA0_STATUS4_REG__REG_POLLING_MASK 0x00000100L
+#define SDMA0_STATUS4_REG__MEM_POLLING_MASK 0x00000200L
+#define SDMA0_STATUS4_REG__UTCL2_RD_XNACK_MASK 0x00000C00L
+#define SDMA0_STATUS4_REG__UTCL2_WR_XNACK_MASK 0x00003000L
+#define SDMA0_STATUS4_REG__ACTIVE_QUEUE_ID_MASK 0x0003C000L
+#define SDMA0_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK 0x00040000L
+#define SDMA0_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK 0x00080000L
+//SDMA0_SCRATCH_RAM_DATA
+#define SDMA0_SCRATCH_RAM_DATA__DATA__SHIFT 0x0
+#define SDMA0_SCRATCH_RAM_DATA__DATA_MASK 0xFFFFFFFFL
+//SDMA0_SCRATCH_RAM_ADDR
+#define SDMA0_SCRATCH_RAM_ADDR__ADDR__SHIFT 0x0
+#define SDMA0_SCRATCH_RAM_ADDR__ADDR_MASK 0x0000007FL
+//SDMA0_CE_CTRL
+#define SDMA0_CE_CTRL__RD_LUT_WATERMARK__SHIFT 0x0
+#define SDMA0_CE_CTRL__RD_LUT_DEPTH__SHIFT 0x3
+#define SDMA0_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT 0x5
+#define SDMA0_CE_CTRL__RESERVED__SHIFT 0x8
+#define SDMA0_CE_CTRL__RD_LUT_WATERMARK_MASK 0x00000007L
+#define SDMA0_CE_CTRL__RD_LUT_DEPTH_MASK 0x00000018L
+#define SDMA0_CE_CTRL__WR_AFIFO_WATERMARK_MASK 0x000000E0L
+#define SDMA0_CE_CTRL__RESERVED_MASK 0xFFFFFF00L
+//SDMA0_RAS_STATUS
+#define SDMA0_RAS_STATUS__RB_FETCH_ECC__SHIFT 0x0
+#define SDMA0_RAS_STATUS__IB_FETCH_ECC__SHIFT 0x1
+#define SDMA0_RAS_STATUS__F32_DATA_ECC__SHIFT 0x2
+#define SDMA0_RAS_STATUS__SEM_WPTR_ATOMIC_ECC__SHIFT 0x3
+#define SDMA0_RAS_STATUS__COPY_DATA_ECC__SHIFT 0x4
+#define SDMA0_RAS_STATUS__SRAM_ECC__SHIFT 0x5
+#define SDMA0_RAS_STATUS__RB_FETCH_NACK_GEN_ERR__SHIFT 0x8
+#define SDMA0_RAS_STATUS__IB_FETCH_NACK_GEN_ERR__SHIFT 0x9
+#define SDMA0_RAS_STATUS__F32_DATA_NACK_GEN_ERR__SHIFT 0xa
+#define SDMA0_RAS_STATUS__COPY_DATA_NACK_GEN_ERR__SHIFT 0xb
+#define SDMA0_RAS_STATUS__WRRET_DATA_NACK_GEN_ERR__SHIFT 0xc
+#define SDMA0_RAS_STATUS__WPTR_RPTR_ATOMIC_NACK_GEN_ERR__SHIFT 0xd
+#define SDMA0_RAS_STATUS__RB_FETCH_ECC_MASK 0x00000001L
+#define SDMA0_RAS_STATUS__IB_FETCH_ECC_MASK 0x00000002L
+#define SDMA0_RAS_STATUS__F32_DATA_ECC_MASK 0x00000004L
+#define SDMA0_RAS_STATUS__SEM_WPTR_ATOMIC_ECC_MASK 0x00000008L
+#define SDMA0_RAS_STATUS__COPY_DATA_ECC_MASK 0x00000010L
+#define SDMA0_RAS_STATUS__SRAM_ECC_MASK 0x00000020L
+#define SDMA0_RAS_STATUS__RB_FETCH_NACK_GEN_ERR_MASK 0x00000100L
+#define SDMA0_RAS_STATUS__IB_FETCH_NACK_GEN_ERR_MASK 0x00000200L
+#define SDMA0_RAS_STATUS__F32_DATA_NACK_GEN_ERR_MASK 0x00000400L
+#define SDMA0_RAS_STATUS__COPY_DATA_NACK_GEN_ERR_MASK 0x00000800L
+#define SDMA0_RAS_STATUS__WRRET_DATA_NACK_GEN_ERR_MASK 0x00001000L
+#define SDMA0_RAS_STATUS__WPTR_RPTR_ATOMIC_NACK_GEN_ERR_MASK 0x00002000L
+//SDMA0_CLK_STATUS
+#define SDMA0_CLK_STATUS__DYN_CLK__SHIFT 0x0
+#define SDMA0_CLK_STATUS__PTR_CLK__SHIFT 0x1
+#define SDMA0_CLK_STATUS__REG_CLK__SHIFT 0x2
+#define SDMA0_CLK_STATUS__F32_CLK__SHIFT 0x3
+#define SDMA0_CLK_STATUS__DYN_CLK_MASK 0x00000001L
+#define SDMA0_CLK_STATUS__PTR_CLK_MASK 0x00000002L
+#define SDMA0_CLK_STATUS__REG_CLK_MASK 0x00000004L
+#define SDMA0_CLK_STATUS__F32_CLK_MASK 0x00000008L
+//SDMA0_GFX_RB_CNTL
+#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA0_GFX_RB_BASE
+#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_GFX_RB_BASE_HI
+#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA0_GFX_RB_RPTR
+#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_GFX_RB_RPTR_HI
+#define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_GFX_RB_WPTR
+#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_GFX_RB_WPTR_HI
+#define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_GFX_RB_WPTR_POLL_CNTL
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA0_GFX_RB_RPTR_ADDR_HI
+#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_GFX_RB_RPTR_ADDR_LO
+#define SDMA0_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_GFX_IB_CNTL
+#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA0_GFX_IB_RPTR
+#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA0_GFX_IB_OFFSET
+#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA0_GFX_IB_BASE_LO
+#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA0_GFX_IB_BASE_HI
+#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_GFX_IB_SIZE
+#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA0_GFX_SKIP_CNTL
+#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA0_GFX_CONTEXT_STATUS
+#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA0_GFX_DOORBELL
+#define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA0_GFX_CONTEXT_CNTL
+#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
+#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18
+#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L
+#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0x0F000000L
+//SDMA0_GFX_STATUS
+#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA0_GFX_DOORBELL_LOG
+#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA0_GFX_WATERMARK
+#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA0_GFX_DOORBELL_OFFSET
+#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA0_GFX_CSA_ADDR_LO
+#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_GFX_CSA_ADDR_HI
+#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_GFX_IB_SUB_REMAIN
+#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA0_GFX_PREEMPT
+#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA0_GFX_DUMMY_REG
+#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA0_GFX_RB_WPTR_POLL_ADDR_HI
+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_GFX_RB_WPTR_POLL_ADDR_LO
+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_GFX_RB_AQL_CNTL
+#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA0_GFX_MINOR_PTR_UPDATE
+#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA0_GFX_MIDCMD_DATA0
+#define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_DATA1
+#define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_DATA2
+#define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_DATA3
+#define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_DATA4
+#define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_DATA5
+#define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_DATA6
+#define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_DATA7
+#define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_DATA8
+#define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_DATA9
+#define SDMA0_GFX_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_DATA10
+#define SDMA0_GFX_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_CNTL
+#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA0_PAGE_RB_CNTL
+#define SDMA0_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA0_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA0_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA0_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA0_PAGE_RB_BASE
+#define SDMA0_PAGE_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_RB_BASE_HI
+#define SDMA0_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA0_PAGE_RB_RPTR
+#define SDMA0_PAGE_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA0_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_RB_RPTR_HI
+#define SDMA0_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_RB_WPTR
+#define SDMA0_PAGE_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA0_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_RB_WPTR_HI
+#define SDMA0_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_RB_WPTR_POLL_CNTL
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA0_PAGE_RB_RPTR_ADDR_HI
+#define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_RB_RPTR_ADDR_LO
+#define SDMA0_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_PAGE_IB_CNTL
+#define SDMA0_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA0_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA0_PAGE_IB_RPTR
+#define SDMA0_PAGE_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA0_PAGE_IB_OFFSET
+#define SDMA0_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA0_PAGE_IB_BASE_LO
+#define SDMA0_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA0_PAGE_IB_BASE_HI
+#define SDMA0_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_IB_SIZE
+#define SDMA0_PAGE_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA0_PAGE_SKIP_CNTL
+#define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA0_PAGE_CONTEXT_STATUS
+#define SDMA0_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA0_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA0_PAGE_DOORBELL
+#define SDMA0_PAGE_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_PAGE_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA0_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA0_PAGE_STATUS
+#define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA0_PAGE_DOORBELL_LOG
+#define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA0_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA0_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA0_PAGE_WATERMARK
+#define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA0_PAGE_DOORBELL_OFFSET
+#define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA0_PAGE_CSA_ADDR_LO
+#define SDMA0_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_PAGE_CSA_ADDR_HI
+#define SDMA0_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_IB_SUB_REMAIN
+#define SDMA0_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA0_PAGE_PREEMPT
+#define SDMA0_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA0_PAGE_DUMMY_REG
+#define SDMA0_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI
+#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO
+#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_PAGE_RB_AQL_CNTL
+#define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA0_PAGE_MINOR_PTR_UPDATE
+#define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA0_PAGE_MIDCMD_DATA0
+#define SDMA0_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_DATA1
+#define SDMA0_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_DATA2
+#define SDMA0_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_DATA3
+#define SDMA0_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_DATA4
+#define SDMA0_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_DATA5
+#define SDMA0_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_DATA6
+#define SDMA0_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_DATA7
+#define SDMA0_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_DATA8
+#define SDMA0_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_DATA9
+#define SDMA0_PAGE_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_DATA10
+#define SDMA0_PAGE_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_CNTL
+#define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA0_RLC0_RB_CNTL
+#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA0_RLC0_RB_BASE
+#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_RB_BASE_HI
+#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA0_RLC0_RB_RPTR
+#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_RB_RPTR_HI
+#define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_RB_WPTR
+#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_RB_WPTR_HI
+#define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_RB_WPTR_POLL_CNTL
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA0_RLC0_RB_RPTR_ADDR_HI
+#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_RB_RPTR_ADDR_LO
+#define SDMA0_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC0_IB_CNTL
+#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA0_RLC0_IB_RPTR
+#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC0_IB_OFFSET
+#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC0_IB_BASE_LO
+#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA0_RLC0_IB_BASE_HI
+#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_IB_SIZE
+#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA0_RLC0_SKIP_CNTL
+#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA0_RLC0_CONTEXT_STATUS
+#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA0_RLC0_DOORBELL
+#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA0_RLC0_STATUS
+#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA0_RLC0_DOORBELL_LOG
+#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA0_RLC0_WATERMARK
+#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA0_RLC0_DOORBELL_OFFSET
+#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA0_RLC0_CSA_ADDR_LO
+#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC0_CSA_ADDR_HI
+#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_IB_SUB_REMAIN
+#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA0_RLC0_PREEMPT
+#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA0_RLC0_DUMMY_REG
+#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI
+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO
+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC0_RB_AQL_CNTL
+#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA0_RLC0_MINOR_PTR_UPDATE
+#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA0_RLC0_MIDCMD_DATA0
+#define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_DATA1
+#define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_DATA2
+#define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_DATA3
+#define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_DATA4
+#define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_DATA5
+#define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_DATA6
+#define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_DATA7
+#define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_DATA8
+#define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_DATA9
+#define SDMA0_RLC0_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_DATA10
+#define SDMA0_RLC0_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_CNTL
+#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA0_RLC1_RB_CNTL
+#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA0_RLC1_RB_BASE
+#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_RB_BASE_HI
+#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA0_RLC1_RB_RPTR
+#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_RB_RPTR_HI
+#define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_RB_WPTR
+#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_RB_WPTR_HI
+#define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_RB_WPTR_POLL_CNTL
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA0_RLC1_RB_RPTR_ADDR_HI
+#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_RB_RPTR_ADDR_LO
+#define SDMA0_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC1_IB_CNTL
+#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA0_RLC1_IB_RPTR
+#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC1_IB_OFFSET
+#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC1_IB_BASE_LO
+#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA0_RLC1_IB_BASE_HI
+#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_IB_SIZE
+#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA0_RLC1_SKIP_CNTL
+#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA0_RLC1_CONTEXT_STATUS
+#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA0_RLC1_DOORBELL
+#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA0_RLC1_STATUS
+#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA0_RLC1_DOORBELL_LOG
+#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA0_RLC1_WATERMARK
+#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA0_RLC1_DOORBELL_OFFSET
+#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA0_RLC1_CSA_ADDR_LO
+#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC1_CSA_ADDR_HI
+#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_IB_SUB_REMAIN
+#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA0_RLC1_PREEMPT
+#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA0_RLC1_DUMMY_REG
+#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI
+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO
+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC1_RB_AQL_CNTL
+#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA0_RLC1_MINOR_PTR_UPDATE
+#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA0_RLC1_MIDCMD_DATA0
+#define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_DATA1
+#define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_DATA2
+#define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_DATA3
+#define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_DATA4
+#define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_DATA5
+#define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_DATA6
+#define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_DATA7
+#define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_DATA8
+#define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_DATA9
+#define SDMA0_RLC1_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_DATA10
+#define SDMA0_RLC1_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_CNTL
+#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA0_RLC2_RB_CNTL
+#define SDMA0_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA0_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA0_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA0_RLC2_RB_BASE
+#define SDMA0_RLC2_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_RB_BASE_HI
+#define SDMA0_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA0_RLC2_RB_RPTR
+#define SDMA0_RLC2_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_RB_RPTR_HI
+#define SDMA0_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_RB_WPTR
+#define SDMA0_RLC2_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_RB_WPTR_HI
+#define SDMA0_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_RB_WPTR_POLL_CNTL
+#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA0_RLC2_RB_RPTR_ADDR_HI
+#define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_RB_RPTR_ADDR_LO
+#define SDMA0_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC2_IB_CNTL
+#define SDMA0_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA0_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA0_RLC2_IB_RPTR
+#define SDMA0_RLC2_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC2_IB_OFFSET
+#define SDMA0_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC2_IB_BASE_LO
+#define SDMA0_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA0_RLC2_IB_BASE_HI
+#define SDMA0_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_IB_SIZE
+#define SDMA0_RLC2_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA0_RLC2_SKIP_CNTL
+#define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA0_RLC2_CONTEXT_STATUS
+#define SDMA0_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA0_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA0_RLC2_DOORBELL
+#define SDMA0_RLC2_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_RLC2_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA0_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA0_RLC2_STATUS
+#define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA0_RLC2_DOORBELL_LOG
+#define SDMA0_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA0_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA0_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA0_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA0_RLC2_WATERMARK
+#define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA0_RLC2_DOORBELL_OFFSET
+#define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA0_RLC2_CSA_ADDR_LO
+#define SDMA0_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC2_CSA_ADDR_HI
+#define SDMA0_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_IB_SUB_REMAIN
+#define SDMA0_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA0_RLC2_PREEMPT
+#define SDMA0_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA0_RLC2_DUMMY_REG
+#define SDMA0_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI
+#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO
+#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC2_RB_AQL_CNTL
+#define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA0_RLC2_MINOR_PTR_UPDATE
+#define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA0_RLC2_MIDCMD_DATA0
+#define SDMA0_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA0_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_MIDCMD_DATA1
+#define SDMA0_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA0_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_MIDCMD_DATA2
+#define SDMA0_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA0_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_MIDCMD_DATA3
+#define SDMA0_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA0_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_MIDCMD_DATA4
+#define SDMA0_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA0_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_MIDCMD_DATA5
+#define SDMA0_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA0_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_MIDCMD_DATA6
+#define SDMA0_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA0_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_MIDCMD_DATA7
+#define SDMA0_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA0_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_MIDCMD_DATA8
+#define SDMA0_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA0_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_MIDCMD_DATA9
+#define SDMA0_RLC2_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA0_RLC2_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_MIDCMD_DATA10
+#define SDMA0_RLC2_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA0_RLC2_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_MIDCMD_CNTL
+#define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA0_RLC3_RB_CNTL
+#define SDMA0_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA0_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA0_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA0_RLC3_RB_BASE
+#define SDMA0_RLC3_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_RB_BASE_HI
+#define SDMA0_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA0_RLC3_RB_RPTR
+#define SDMA0_RLC3_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_RB_RPTR_HI
+#define SDMA0_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_RB_WPTR
+#define SDMA0_RLC3_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_RB_WPTR_HI
+#define SDMA0_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_RB_WPTR_POLL_CNTL
+#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA0_RLC3_RB_RPTR_ADDR_HI
+#define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_RB_RPTR_ADDR_LO
+#define SDMA0_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC3_IB_CNTL
+#define SDMA0_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA0_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA0_RLC3_IB_RPTR
+#define SDMA0_RLC3_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC3_IB_OFFSET
+#define SDMA0_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC3_IB_BASE_LO
+#define SDMA0_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA0_RLC3_IB_BASE_HI
+#define SDMA0_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_IB_SIZE
+#define SDMA0_RLC3_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA0_RLC3_SKIP_CNTL
+#define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA0_RLC3_CONTEXT_STATUS
+#define SDMA0_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA0_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA0_RLC3_DOORBELL
+#define SDMA0_RLC3_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_RLC3_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA0_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA0_RLC3_STATUS
+#define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA0_RLC3_DOORBELL_LOG
+#define SDMA0_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA0_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA0_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA0_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA0_RLC3_WATERMARK
+#define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA0_RLC3_DOORBELL_OFFSET
+#define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA0_RLC3_CSA_ADDR_LO
+#define SDMA0_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC3_CSA_ADDR_HI
+#define SDMA0_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_IB_SUB_REMAIN
+#define SDMA0_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA0_RLC3_PREEMPT
+#define SDMA0_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA0_RLC3_DUMMY_REG
+#define SDMA0_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI
+#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO
+#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC3_RB_AQL_CNTL
+#define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA0_RLC3_MINOR_PTR_UPDATE
+#define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA0_RLC3_MIDCMD_DATA0
+#define SDMA0_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA0_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_MIDCMD_DATA1
+#define SDMA0_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA0_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_MIDCMD_DATA2
+#define SDMA0_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA0_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_MIDCMD_DATA3
+#define SDMA0_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA0_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_MIDCMD_DATA4
+#define SDMA0_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA0_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_MIDCMD_DATA5
+#define SDMA0_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA0_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_MIDCMD_DATA6
+#define SDMA0_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA0_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_MIDCMD_DATA7
+#define SDMA0_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA0_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_MIDCMD_DATA8
+#define SDMA0_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA0_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_MIDCMD_DATA9
+#define SDMA0_RLC3_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA0_RLC3_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_MIDCMD_DATA10
+#define SDMA0_RLC3_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA0_RLC3_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_MIDCMD_CNTL
+#define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA0_RLC4_RB_CNTL
+#define SDMA0_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA0_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA0_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA0_RLC4_RB_BASE
+#define SDMA0_RLC4_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_RB_BASE_HI
+#define SDMA0_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA0_RLC4_RB_RPTR
+#define SDMA0_RLC4_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_RB_RPTR_HI
+#define SDMA0_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_RB_WPTR
+#define SDMA0_RLC4_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_RB_WPTR_HI
+#define SDMA0_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_RB_WPTR_POLL_CNTL
+#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA0_RLC4_RB_RPTR_ADDR_HI
+#define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_RB_RPTR_ADDR_LO
+#define SDMA0_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC4_IB_CNTL
+#define SDMA0_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA0_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA0_RLC4_IB_RPTR
+#define SDMA0_RLC4_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC4_IB_OFFSET
+#define SDMA0_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC4_IB_BASE_LO
+#define SDMA0_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA0_RLC4_IB_BASE_HI
+#define SDMA0_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_IB_SIZE
+#define SDMA0_RLC4_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA0_RLC4_SKIP_CNTL
+#define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA0_RLC4_CONTEXT_STATUS
+#define SDMA0_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA0_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA0_RLC4_DOORBELL
+#define SDMA0_RLC4_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_RLC4_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA0_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA0_RLC4_STATUS
+#define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA0_RLC4_DOORBELL_LOG
+#define SDMA0_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA0_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA0_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA0_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA0_RLC4_WATERMARK
+#define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA0_RLC4_DOORBELL_OFFSET
+#define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA0_RLC4_CSA_ADDR_LO
+#define SDMA0_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC4_CSA_ADDR_HI
+#define SDMA0_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_IB_SUB_REMAIN
+#define SDMA0_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA0_RLC4_PREEMPT
+#define SDMA0_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA0_RLC4_DUMMY_REG
+#define SDMA0_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI
+#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO
+#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC4_RB_AQL_CNTL
+#define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA0_RLC4_MINOR_PTR_UPDATE
+#define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA0_RLC4_MIDCMD_DATA0
+#define SDMA0_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA0_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_MIDCMD_DATA1
+#define SDMA0_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA0_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_MIDCMD_DATA2
+#define SDMA0_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA0_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_MIDCMD_DATA3
+#define SDMA0_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA0_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_MIDCMD_DATA4
+#define SDMA0_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA0_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_MIDCMD_DATA5
+#define SDMA0_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA0_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_MIDCMD_DATA6
+#define SDMA0_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA0_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_MIDCMD_DATA7
+#define SDMA0_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA0_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_MIDCMD_DATA8
+#define SDMA0_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA0_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_MIDCMD_DATA9
+#define SDMA0_RLC4_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA0_RLC4_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_MIDCMD_DATA10
+#define SDMA0_RLC4_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA0_RLC4_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_MIDCMD_CNTL
+#define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA0_RLC5_RB_CNTL
+#define SDMA0_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA0_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA0_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA0_RLC5_RB_BASE
+#define SDMA0_RLC5_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_RB_BASE_HI
+#define SDMA0_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA0_RLC5_RB_RPTR
+#define SDMA0_RLC5_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_RB_RPTR_HI
+#define SDMA0_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_RB_WPTR
+#define SDMA0_RLC5_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_RB_WPTR_HI
+#define SDMA0_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_RB_WPTR_POLL_CNTL
+#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA0_RLC5_RB_RPTR_ADDR_HI
+#define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_RB_RPTR_ADDR_LO
+#define SDMA0_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC5_IB_CNTL
+#define SDMA0_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA0_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA0_RLC5_IB_RPTR
+#define SDMA0_RLC5_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC5_IB_OFFSET
+#define SDMA0_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC5_IB_BASE_LO
+#define SDMA0_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA0_RLC5_IB_BASE_HI
+#define SDMA0_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_IB_SIZE
+#define SDMA0_RLC5_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA0_RLC5_SKIP_CNTL
+#define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA0_RLC5_CONTEXT_STATUS
+#define SDMA0_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA0_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA0_RLC5_DOORBELL
+#define SDMA0_RLC5_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_RLC5_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA0_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA0_RLC5_STATUS
+#define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA0_RLC5_DOORBELL_LOG
+#define SDMA0_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA0_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA0_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA0_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA0_RLC5_WATERMARK
+#define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA0_RLC5_DOORBELL_OFFSET
+#define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA0_RLC5_CSA_ADDR_LO
+#define SDMA0_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC5_CSA_ADDR_HI
+#define SDMA0_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_IB_SUB_REMAIN
+#define SDMA0_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA0_RLC5_PREEMPT
+#define SDMA0_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA0_RLC5_DUMMY_REG
+#define SDMA0_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI
+#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO
+#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC5_RB_AQL_CNTL
+#define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA0_RLC5_MINOR_PTR_UPDATE
+#define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA0_RLC5_MIDCMD_DATA0
+#define SDMA0_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA0_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_MIDCMD_DATA1
+#define SDMA0_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA0_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_MIDCMD_DATA2
+#define SDMA0_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA0_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_MIDCMD_DATA3
+#define SDMA0_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA0_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_MIDCMD_DATA4
+#define SDMA0_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA0_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_MIDCMD_DATA5
+#define SDMA0_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA0_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_MIDCMD_DATA6
+#define SDMA0_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA0_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_MIDCMD_DATA7
+#define SDMA0_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA0_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_MIDCMD_DATA8
+#define SDMA0_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA0_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_MIDCMD_DATA9
+#define SDMA0_RLC5_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA0_RLC5_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_MIDCMD_DATA10
+#define SDMA0_RLC5_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA0_RLC5_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_MIDCMD_CNTL
+#define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA0_RLC6_RB_CNTL
+#define SDMA0_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA0_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA0_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA0_RLC6_RB_BASE
+#define SDMA0_RLC6_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_RB_BASE_HI
+#define SDMA0_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA0_RLC6_RB_RPTR
+#define SDMA0_RLC6_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_RB_RPTR_HI
+#define SDMA0_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_RB_WPTR
+#define SDMA0_RLC6_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_RB_WPTR_HI
+#define SDMA0_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_RB_WPTR_POLL_CNTL
+#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA0_RLC6_RB_RPTR_ADDR_HI
+#define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_RB_RPTR_ADDR_LO
+#define SDMA0_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC6_IB_CNTL
+#define SDMA0_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA0_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA0_RLC6_IB_RPTR
+#define SDMA0_RLC6_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC6_IB_OFFSET
+#define SDMA0_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC6_IB_BASE_LO
+#define SDMA0_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA0_RLC6_IB_BASE_HI
+#define SDMA0_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_IB_SIZE
+#define SDMA0_RLC6_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA0_RLC6_SKIP_CNTL
+#define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA0_RLC6_CONTEXT_STATUS
+#define SDMA0_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA0_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA0_RLC6_DOORBELL
+#define SDMA0_RLC6_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_RLC6_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA0_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA0_RLC6_STATUS
+#define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA0_RLC6_DOORBELL_LOG
+#define SDMA0_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA0_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA0_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA0_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA0_RLC6_WATERMARK
+#define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA0_RLC6_DOORBELL_OFFSET
+#define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA0_RLC6_CSA_ADDR_LO
+#define SDMA0_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC6_CSA_ADDR_HI
+#define SDMA0_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_IB_SUB_REMAIN
+#define SDMA0_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA0_RLC6_PREEMPT
+#define SDMA0_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA0_RLC6_DUMMY_REG
+#define SDMA0_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI
+#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO
+#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC6_RB_AQL_CNTL
+#define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA0_RLC6_MINOR_PTR_UPDATE
+#define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA0_RLC6_MIDCMD_DATA0
+#define SDMA0_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA0_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_MIDCMD_DATA1
+#define SDMA0_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA0_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_MIDCMD_DATA2
+#define SDMA0_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA0_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_MIDCMD_DATA3
+#define SDMA0_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA0_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_MIDCMD_DATA4
+#define SDMA0_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA0_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_MIDCMD_DATA5
+#define SDMA0_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA0_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_MIDCMD_DATA6
+#define SDMA0_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA0_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_MIDCMD_DATA7
+#define SDMA0_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA0_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_MIDCMD_DATA8
+#define SDMA0_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA0_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_MIDCMD_DATA9
+#define SDMA0_RLC6_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA0_RLC6_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_MIDCMD_DATA10
+#define SDMA0_RLC6_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA0_RLC6_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_MIDCMD_CNTL
+#define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA0_RLC7_RB_CNTL
+#define SDMA0_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA0_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA0_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA0_RLC7_RB_BASE
+#define SDMA0_RLC7_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_RB_BASE_HI
+#define SDMA0_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA0_RLC7_RB_RPTR
+#define SDMA0_RLC7_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_RB_RPTR_HI
+#define SDMA0_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_RB_WPTR
+#define SDMA0_RLC7_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_RB_WPTR_HI
+#define SDMA0_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_RB_WPTR_POLL_CNTL
+#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA0_RLC7_RB_RPTR_ADDR_HI
+#define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_RB_RPTR_ADDR_LO
+#define SDMA0_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC7_IB_CNTL
+#define SDMA0_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA0_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA0_RLC7_IB_RPTR
+#define SDMA0_RLC7_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC7_IB_OFFSET
+#define SDMA0_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC7_IB_BASE_LO
+#define SDMA0_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA0_RLC7_IB_BASE_HI
+#define SDMA0_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_IB_SIZE
+#define SDMA0_RLC7_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA0_RLC7_SKIP_CNTL
+#define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA0_RLC7_CONTEXT_STATUS
+#define SDMA0_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA0_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA0_RLC7_DOORBELL
+#define SDMA0_RLC7_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_RLC7_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA0_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA0_RLC7_STATUS
+#define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA0_RLC7_DOORBELL_LOG
+#define SDMA0_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA0_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA0_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA0_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA0_RLC7_WATERMARK
+#define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA0_RLC7_DOORBELL_OFFSET
+#define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA0_RLC7_CSA_ADDR_LO
+#define SDMA0_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC7_CSA_ADDR_HI
+#define SDMA0_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_IB_SUB_REMAIN
+#define SDMA0_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA0_RLC7_PREEMPT
+#define SDMA0_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA0_RLC7_DUMMY_REG
+#define SDMA0_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI
+#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO
+#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC7_RB_AQL_CNTL
+#define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA0_RLC7_MINOR_PTR_UPDATE
+#define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA0_RLC7_MIDCMD_DATA0
+#define SDMA0_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA0_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_MIDCMD_DATA1
+#define SDMA0_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA0_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_MIDCMD_DATA2
+#define SDMA0_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA0_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_MIDCMD_DATA3
+#define SDMA0_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA0_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_MIDCMD_DATA4
+#define SDMA0_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA0_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_MIDCMD_DATA5
+#define SDMA0_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA0_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_MIDCMD_DATA6
+#define SDMA0_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA0_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_MIDCMD_DATA7
+#define SDMA0_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA0_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_MIDCMD_DATA8
+#define SDMA0_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA0_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_MIDCMD_DATA9
+#define SDMA0_RLC7_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA0_RLC7_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_MIDCMD_DATA10
+#define SDMA0_RLC7_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA0_RLC7_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_MIDCMD_CNTL
+#define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+
+
+// addressBlock: sdma0_sdma1dec
+//SDMA1_UCODE_ADDR
+#define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0
+#define SDMA1_UCODE_ADDR__VALUE_MASK 0x00003FFFL
+//SDMA1_UCODE_DATA
+#define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0
+#define SDMA1_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL
+//SDMA1_VF_ENABLE
+#define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT 0x0
+#define SDMA1_VF_ENABLE__VF_ENABLE_MASK 0x00000001L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR__SHIFT 0x0
+#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT 0x1
+#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK 0x00000001L
+#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK 0x00000002L
+//SDMA1_CONTEXT_GROUP_BOUNDARY
+#define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0
+#define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL
+//SDMA1_POWER_CNTL
+#define SDMA1_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0
+#define SDMA1_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1
+#define SDMA1_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2
+#define SDMA1_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3
+#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
+#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9
+#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
+#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb
+#define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc
+#define SDMA1_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a
+#define SDMA1_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L
+#define SDMA1_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L
+#define SDMA1_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L
+#define SDMA1_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L
+#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L
+#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L
+#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L
+#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L
+#define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L
+#define SDMA1_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
+//SDMA1_CLK_CTRL
+#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define SDMA1_CLK_CTRL__RESERVED__SHIFT 0xc
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define SDMA1_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define SDMA1_CLK_CTRL__RESERVED_MASK 0x00FFF000L
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//SDMA1_CNTL
+#define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0
+#define SDMA1_CNTL__UTC_L1_ENABLE__SHIFT 0x1
+#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
+#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
+#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5
+#define SDMA1_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x6
+#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11
+#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
+#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
+#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
+#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e
+#define SDMA1_CNTL__TRAP_ENABLE_MASK 0x00000001L
+#define SDMA1_CNTL__UTC_L1_ENABLE_MASK 0x00000002L
+#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L
+#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L
+#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L
+#define SDMA1_CNTL__MIDCMD_EXPIRE_ENABLE_MASK 0x00000040L
+#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L
+#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L
+#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L
+#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L
+#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L
+//SDMA1_CHICKEN_BITS
+#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
+#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
+#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
+#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8
+#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
+#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
+#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11
+#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
+#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
+#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19
+#define SDMA1_CHICKEN_BITS__SRAM_FGCG_ENABLE__SHIFT 0x1a
+#define SDMA1_CHICKEN_BITS__RESERVED__SHIFT 0x1b
+#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L
+#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L
+#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L
+#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L
+#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L
+#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L
+#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L
+#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L
+#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L
+#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L
+#define SDMA1_CHICKEN_BITS__SRAM_FGCG_ENABLE_MASK 0x04000000L
+#define SDMA1_CHICKEN_BITS__RESERVED_MASK 0xF8000000L
+//SDMA1_GB_ADDR_CONFIG
+#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define SDMA1_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
+#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
+#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
+#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
+#define SDMA1_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
+#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
+//SDMA1_GB_ADDR_CONFIG_READ
+#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0
+#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc
+#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13
+#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L
+#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
+#define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L
+#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L
+//SDMA1_RB_RPTR_FETCH_HI
+#define SDMA1_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_SEM_WAIT_FAIL_TIMER_CNTL
+#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
+#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL
+//SDMA1_RB_RPTR_FETCH
+#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
+#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL
+//SDMA1_IB_OFFSET_FETCH
+#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
+#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL
+//SDMA1_PROGRAM
+#define SDMA1_PROGRAM__STREAM__SHIFT 0x0
+#define SDMA1_PROGRAM__STREAM_MASK 0xFFFFFFFFL
+//SDMA1_STATUS_REG
+#define SDMA1_STATUS_REG__IDLE__SHIFT 0x0
+#define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1
+#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2
+#define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3
+#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
+#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
+#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
+#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
+#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
+#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9
+#define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa
+#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
+#define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc
+#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
+#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe
+#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
+#define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10
+#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
+#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
+#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
+#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14
+#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
+#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
+#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
+#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a
+#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
+#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
+#define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e
+#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
+#define SDMA1_STATUS_REG__IDLE_MASK 0x00000001L
+#define SDMA1_STATUS_REG__REG_IDLE_MASK 0x00000002L
+#define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x00000004L
+#define SDMA1_STATUS_REG__RB_FULL_MASK 0x00000008L
+#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L
+#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L
+#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L
+#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L
+#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L
+#define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x00000200L
+#define SDMA1_STATUS_REG__EX_IDLE_MASK 0x00000400L
+#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L
+#define SDMA1_STATUS_REG__PACKET_READY_MASK 0x00001000L
+#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L
+#define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x00004000L
+#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L
+#define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L
+#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L
+#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L
+#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L
+#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L
+#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L
+#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L
+#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L
+#define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x04000000L
+#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L
+#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L
+#define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000L
+#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L
+//SDMA1_STATUS1_REG
+#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
+#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
+#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
+#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
+#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
+#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
+#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
+#define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9
+#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
+#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
+#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
+#define SDMA1_STATUS1_REG__EX_START__SHIFT 0xf
+#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
+#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
+#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L
+#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L
+#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L
+#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L
+#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L
+#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L
+#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L
+#define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L
+#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L
+#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L
+#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L
+#define SDMA1_STATUS1_REG__EX_START_MASK 0x00008000L
+#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L
+#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L
+//SDMA1_RD_BURST_CNTL
+#define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT 0x0
+#define SDMA1_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2
+#define SDMA1_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L
+#define SDMA1_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL
+//SDMA1_HBM_PAGE_CONFIG
+#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0
+#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L
+//SDMA1_UCODE_CHECKSUM
+#define SDMA1_UCODE_CHECKSUM__DATA__SHIFT 0x0
+#define SDMA1_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL
+//SDMA1_F32_CNTL
+#define SDMA1_F32_CNTL__HALT__SHIFT 0x0
+#define SDMA1_F32_CNTL__STEP__SHIFT 0x1
+#define SDMA1_F32_CNTL__RESET__SHIFT 0x8
+#define SDMA1_F32_CNTL__HALT_MASK 0x00000001L
+#define SDMA1_F32_CNTL__STEP_MASK 0x00000002L
+#define SDMA1_F32_CNTL__RESET_MASK 0x00000100L
+//SDMA1_FREEZE
+#define SDMA1_FREEZE__PREEMPT__SHIFT 0x0
+#define SDMA1_FREEZE__FREEZE__SHIFT 0x4
+#define SDMA1_FREEZE__FROZEN__SHIFT 0x5
+#define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6
+#define SDMA1_FREEZE__PREEMPT_MASK 0x00000001L
+#define SDMA1_FREEZE__FREEZE_MASK 0x00000010L
+#define SDMA1_FREEZE__FROZEN_MASK 0x00000020L
+#define SDMA1_FREEZE__F32_FREEZE_MASK 0x00000040L
+//SDMA1_PHASE0_QUANTUM
+#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL
+#define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L
+#define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000L
+//SDMA1_PHASE1_QUANTUM
+#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL
+#define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L
+#define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000L
+//CC_SDMA1_EDC_CONFIG
+#define CC_SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1
+#define CC_SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x00000002L
+//SDMA1_BA_THRESHOLD
+#define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0
+#define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10
+#define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL
+#define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L
+//SDMA1_ID
+#define SDMA1_ID__DEVICE_ID__SHIFT 0x0
+#define SDMA1_ID__DEVICE_ID_MASK 0x000000FFL
+//SDMA1_VERSION
+#define SDMA1_VERSION__MINVER__SHIFT 0x0
+#define SDMA1_VERSION__MAJVER__SHIFT 0x8
+#define SDMA1_VERSION__REV__SHIFT 0x10
+#define SDMA1_VERSION__MINVER_MASK 0x0000007FL
+#define SDMA1_VERSION__MAJVER_MASK 0x00007F00L
+#define SDMA1_VERSION__REV_MASK 0x003F0000L
+//SDMA1_EDC_COUNTER
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x0
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x2
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x4
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0x6
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0x8
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xa
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xc
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0x10
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x12
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x14
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x16
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x18
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x1a
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x1c
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x1e
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000003L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x0000000CL
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000030L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x000000C0L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000300L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00000C00L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00003000L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x0000C000L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00030000L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x000C0000L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00300000L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00C00000L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x03000000L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x0C000000L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x30000000L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0xC0000000L
+//SDMA1_EDC_COUNTER2
+#define SDMA1_EDC_COUNTER2__SDMA_UCODE_BUF_SED__SHIFT 0x0
+#define SDMA1_EDC_COUNTER2__SDMA_RB_CMD_BUF_SED__SHIFT 0x2
+#define SDMA1_EDC_COUNTER2__SDMA_IB_CMD_BUF_SED__SHIFT 0x4
+#define SDMA1_EDC_COUNTER2__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x6
+#define SDMA1_EDC_COUNTER2__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x8
+#define SDMA1_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED__SHIFT 0xa
+#define SDMA1_EDC_COUNTER2__SDMA_DATA_LUT_FIFO_SED__SHIFT 0xc
+#define SDMA1_EDC_COUNTER2__SDMA_SPLIT_DATA_BUF_SED__SHIFT 0xe
+#define SDMA1_EDC_COUNTER2__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10
+#define SDMA1_EDC_COUNTER2__SDMA_MC_RDRET_BUF_SED__SHIFT 0x12
+#define SDMA1_EDC_COUNTER2__SDMA_UCODE_BUF_SED_MASK 0x00000003L
+#define SDMA1_EDC_COUNTER2__SDMA_RB_CMD_BUF_SED_MASK 0x0000000CL
+#define SDMA1_EDC_COUNTER2__SDMA_IB_CMD_BUF_SED_MASK 0x00000030L
+#define SDMA1_EDC_COUNTER2__SDMA_UTCL1_RD_FIFO_SED_MASK 0x000000C0L
+#define SDMA1_EDC_COUNTER2__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000300L
+#define SDMA1_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED_MASK 0x00000C00L
+#define SDMA1_EDC_COUNTER2__SDMA_DATA_LUT_FIFO_SED_MASK 0x00003000L
+#define SDMA1_EDC_COUNTER2__SDMA_SPLIT_DATA_BUF_SED_MASK 0x0000C000L
+#define SDMA1_EDC_COUNTER2__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00030000L
+#define SDMA1_EDC_COUNTER2__SDMA_MC_RDRET_BUF_SED_MASK 0x000C0000L
+//SDMA1_STATUS2_REG
+#define SDMA1_STATUS2_REG__ID__SHIFT 0x0
+#define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3
+#define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10
+#define SDMA1_STATUS2_REG__ID_MASK 0x00000007L
+#define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L
+#define SDMA1_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L
+//SDMA1_ATOMIC_CNTL
+#define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0
+#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f
+#define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL
+#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L
+//SDMA1_ATOMIC_PREOP_LO
+#define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0
+#define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL
+//SDMA1_ATOMIC_PREOP_HI
+#define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0
+#define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL
+//SDMA1_UTCL1_CNTL
+#define SDMA1_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0
+#define SDMA1_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1
+#define SDMA1_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb
+#define SDMA1_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe
+#define SDMA1_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18
+#define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
+#define SDMA1_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L
+#define SDMA1_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL
+#define SDMA1_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L
+#define SDMA1_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L
+#define SDMA1_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L
+#define SDMA1_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L
+//SDMA1_UTCL1_WATERMK
+#define SDMA1_UTCL1_WATERMK__REQ_WATERMK__SHIFT 0x0
+#define SDMA1_UTCL1_WATERMK__REQ_DEPTH__SHIFT 0x3
+#define SDMA1_UTCL1_WATERMK__PAGE_WATERMK__SHIFT 0x5
+#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x8
+#define SDMA1_UTCL1_WATERMK__RESERVED__SHIFT 0x10
+#define SDMA1_UTCL1_WATERMK__REQ_WATERMK_MASK 0x00000007L
+#define SDMA1_UTCL1_WATERMK__REQ_DEPTH_MASK 0x00000018L
+#define SDMA1_UTCL1_WATERMK__PAGE_WATERMK_MASK 0x000000E0L
+#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x0000FF00L
+#define SDMA1_UTCL1_WATERMK__RESERVED_MASK 0xFFFF0000L
+//SDMA1_UTCL1_RD_STATUS
+#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
+#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
+#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
+#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
+#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
+#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
+#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
+#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
+#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
+#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
+#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
+#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
+#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
+#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
+#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
+#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
+#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
+#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
+#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12
+#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13
+#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14
+#define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15
+#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16
+#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a
+#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
+#define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e
+#define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f
+#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
+#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L
+#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L
+#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L
+#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L
+#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L
+#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L
+#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L
+#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L
+#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L
+#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L
+#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L
+#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L
+#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L
+#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L
+#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L
+#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L
+#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L
+#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L
+#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L
+#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L
+#define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L
+#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L
+#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L
+#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L
+#define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L
+#define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L
+//SDMA1_UTCL1_WR_STATUS
+#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
+#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
+#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
+#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
+#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
+#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
+#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
+#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
+#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
+#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
+#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
+#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
+#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
+#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
+#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
+#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
+#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
+#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
+#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12
+#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13
+#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14
+#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15
+#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16
+#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19
+#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c
+#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
+#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e
+#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f
+#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
+#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L
+#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L
+#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L
+#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L
+#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L
+#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L
+#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L
+#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L
+#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L
+#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L
+#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L
+#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L
+#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L
+#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L
+#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L
+#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L
+#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L
+#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L
+#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L
+#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L
+#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L
+#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L
+#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L
+#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L
+#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L
+#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L
+#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L
+//SDMA1_UTCL1_INV0
+#define SDMA1_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0
+#define SDMA1_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1
+#define SDMA1_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2
+#define SDMA1_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3
+#define SDMA1_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4
+#define SDMA1_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5
+#define SDMA1_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6
+#define SDMA1_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7
+#define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8
+#define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9
+#define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa
+#define SDMA1_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb
+#define SDMA1_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc
+#define SDMA1_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c
+#define SDMA1_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L
+#define SDMA1_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L
+#define SDMA1_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L
+#define SDMA1_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L
+#define SDMA1_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L
+#define SDMA1_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L
+#define SDMA1_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L
+#define SDMA1_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L
+#define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L
+#define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L
+#define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L
+#define SDMA1_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L
+#define SDMA1_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L
+#define SDMA1_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L
+//SDMA1_UTCL1_INV1
+#define SDMA1_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0
+#define SDMA1_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL
+//SDMA1_UTCL1_INV2
+#define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0
+#define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL
+//SDMA1_UTCL1_RD_XNACK0
+#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
+#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
+//SDMA1_UTCL1_RD_XNACK1
+#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
+#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4
+#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8
+#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a
+#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
+#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L
+#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
+#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L
+//SDMA1_UTCL1_WR_XNACK0
+#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
+#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
+//SDMA1_UTCL1_WR_XNACK1
+#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
+#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4
+#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8
+#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a
+#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
+#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L
+#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
+#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L
+//SDMA1_UTCL1_TIMEOUT
+#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0
+#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10
+#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL
+#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L
+//SDMA1_UTCL1_PAGE
+#define SDMA1_UTCL1_PAGE__VM_HOLE__SHIFT 0x0
+#define SDMA1_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1
+#define SDMA1_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6
+#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9
+#define SDMA1_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L
+#define SDMA1_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL
+#define SDMA1_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L
+#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L
+//SDMA1_POWER_CNTL_IDLE
+#define SDMA1_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0
+#define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10
+#define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18
+#define SDMA1_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL
+#define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L
+#define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L
+//SDMA1_RELAX_ORDERING_LUT
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0
+#define SDMA1_RELAX_ORDERING_LUT__COPY__SHIFT 0x1
+#define SDMA1_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4
+#define SDMA1_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6
+#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8
+#define SDMA1_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9
+#define SDMA1_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa
+#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb
+#define SDMA1_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc
+#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe
+#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b
+#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c
+#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
+#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e
+#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L
+#define SDMA1_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L
+#define SDMA1_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L
+#define SDMA1_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L
+#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L
+#define SDMA1_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L
+#define SDMA1_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L
+#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L
+#define SDMA1_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L
+#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L
+#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L
+#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L
+#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L
+#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L
+#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L
+//SDMA1_CHICKEN_BITS_2
+#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0
+#define SDMA1_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT 0x4
+#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL
+#define SDMA1_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK 0x00000010L
+//SDMA1_STATUS3_REG
+#define SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0
+#define SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10
+#define SDMA1_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14
+#define SDMA1_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15
+#define SDMA1_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16
+#define SDMA1_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL
+#define SDMA1_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L
+#define SDMA1_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L
+#define SDMA1_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L
+#define SDMA1_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L
+//SDMA1_PHYSICAL_ADDR_LO
+#define SDMA1_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0
+#define SDMA1_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1
+#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2
+#define SDMA1_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc
+#define SDMA1_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L
+#define SDMA1_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L
+#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L
+#define SDMA1_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L
+//SDMA1_PHYSICAL_ADDR_HI
+#define SDMA1_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL
+//SDMA1_PHASE2_QUANTUM
+#define SDMA1_PHASE2_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA1_PHASE2_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA1_PHASE2_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA1_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL
+#define SDMA1_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L
+#define SDMA1_PHASE2_QUANTUM__PREFER_MASK 0x40000000L
+//SDMA1_ERROR_LOG
+#define SDMA1_ERROR_LOG__OVERRIDE__SHIFT 0x0
+#define SDMA1_ERROR_LOG__STATUS__SHIFT 0x10
+#define SDMA1_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL
+#define SDMA1_ERROR_LOG__STATUS_MASK 0xFFFF0000L
+//SDMA1_PUB_DUMMY_REG0
+#define SDMA1_PUB_DUMMY_REG0__VALUE__SHIFT 0x0
+#define SDMA1_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL
+//SDMA1_PUB_DUMMY_REG1
+#define SDMA1_PUB_DUMMY_REG1__VALUE__SHIFT 0x0
+#define SDMA1_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL
+//SDMA1_PUB_DUMMY_REG2
+#define SDMA1_PUB_DUMMY_REG2__VALUE__SHIFT 0x0
+#define SDMA1_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL
+//SDMA1_PUB_DUMMY_REG3
+#define SDMA1_PUB_DUMMY_REG3__VALUE__SHIFT 0x0
+#define SDMA1_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL
+//SDMA1_F32_COUNTER
+#define SDMA1_F32_COUNTER__VALUE__SHIFT 0x0
+#define SDMA1_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL
+//SDMA1_PERFCNT_PERFCOUNTER0_CFG
+#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define SDMA1_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//SDMA1_PERFCNT_PERFCOUNTER1_CFG
+#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define SDMA1_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL
+#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+//SDMA1_PERFCNT_MISC_CNTL
+#define SDMA1_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x0
+#define SDMA1_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000FFFFL
+//SDMA1_PERFCNT_PERFCOUNTER_LO
+#define SDMA1_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define SDMA1_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//SDMA1_PERFCNT_PERFCOUNTER_HI
+#define SDMA1_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define SDMA1_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define SDMA1_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define SDMA1_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//SDMA1_CRD_CNTL
+#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7
+#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd
+#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L
+#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L
+//SDMA1_ULV_CNTL
+#define SDMA1_ULV_CNTL__HYSTERESIS__SHIFT 0x0
+#define SDMA1_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b
+#define SDMA1_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c
+#define SDMA1_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
+#define SDMA1_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e
+#define SDMA1_ULV_CNTL__ULV_STATUS__SHIFT 0x1f
+#define SDMA1_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL
+#define SDMA1_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L
+#define SDMA1_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L
+#define SDMA1_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L
+#define SDMA1_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L
+#define SDMA1_ULV_CNTL__ULV_STATUS_MASK 0x80000000L
+//SDMA1_EA_DBIT_ADDR_DATA
+#define SDMA1_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0
+#define SDMA1_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL
+//SDMA1_EA_DBIT_ADDR_INDEX
+#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0
+#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L
+//SDMA1_STATUS4_REG
+#define SDMA1_STATUS4_REG__IDLE__SHIFT 0x0
+#define SDMA1_STATUS4_REG__IH_OUTSTANDING__SHIFT 0x2
+#define SDMA1_STATUS4_REG__SEM_OUTSTANDING__SHIFT 0x3
+#define SDMA1_STATUS4_REG__MMHUB_RD_OUTSTANDING__SHIFT 0x4
+#define SDMA1_STATUS4_REG__MMHUB_WR_OUTSTANDING__SHIFT 0x5
+#define SDMA1_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT 0x6
+#define SDMA1_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT 0x7
+#define SDMA1_STATUS4_REG__REG_POLLING__SHIFT 0x8
+#define SDMA1_STATUS4_REG__MEM_POLLING__SHIFT 0x9
+#define SDMA1_STATUS4_REG__UTCL2_RD_XNACK__SHIFT 0xa
+#define SDMA1_STATUS4_REG__UTCL2_WR_XNACK__SHIFT 0xc
+#define SDMA1_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT 0xe
+#define SDMA1_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT 0x12
+#define SDMA1_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT 0x13
+#define SDMA1_STATUS4_REG__IDLE_MASK 0x00000001L
+#define SDMA1_STATUS4_REG__IH_OUTSTANDING_MASK 0x00000004L
+#define SDMA1_STATUS4_REG__SEM_OUTSTANDING_MASK 0x00000008L
+#define SDMA1_STATUS4_REG__MMHUB_RD_OUTSTANDING_MASK 0x00000010L
+#define SDMA1_STATUS4_REG__MMHUB_WR_OUTSTANDING_MASK 0x00000020L
+#define SDMA1_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK 0x00000040L
+#define SDMA1_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK 0x00000080L
+#define SDMA1_STATUS4_REG__REG_POLLING_MASK 0x00000100L
+#define SDMA1_STATUS4_REG__MEM_POLLING_MASK 0x00000200L
+#define SDMA1_STATUS4_REG__UTCL2_RD_XNACK_MASK 0x00000C00L
+#define SDMA1_STATUS4_REG__UTCL2_WR_XNACK_MASK 0x00003000L
+#define SDMA1_STATUS4_REG__ACTIVE_QUEUE_ID_MASK 0x0003C000L
+#define SDMA1_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK 0x00040000L
+#define SDMA1_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK 0x00080000L
+//SDMA1_SCRATCH_RAM_DATA
+#define SDMA1_SCRATCH_RAM_DATA__DATA__SHIFT 0x0
+#define SDMA1_SCRATCH_RAM_DATA__DATA_MASK 0xFFFFFFFFL
+//SDMA1_SCRATCH_RAM_ADDR
+#define SDMA1_SCRATCH_RAM_ADDR__ADDR__SHIFT 0x0
+#define SDMA1_SCRATCH_RAM_ADDR__ADDR_MASK 0x0000007FL
+//SDMA1_CE_CTRL
+#define SDMA1_CE_CTRL__RD_LUT_WATERMARK__SHIFT 0x0
+#define SDMA1_CE_CTRL__RD_LUT_DEPTH__SHIFT 0x3
+#define SDMA1_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT 0x5
+#define SDMA1_CE_CTRL__RESERVED__SHIFT 0x8
+#define SDMA1_CE_CTRL__RD_LUT_WATERMARK_MASK 0x00000007L
+#define SDMA1_CE_CTRL__RD_LUT_DEPTH_MASK 0x00000018L
+#define SDMA1_CE_CTRL__WR_AFIFO_WATERMARK_MASK 0x000000E0L
+#define SDMA1_CE_CTRL__RESERVED_MASK 0xFFFFFF00L
+//SDMA1_RAS_STATUS
+#define SDMA1_RAS_STATUS__RB_FETCH_ECC__SHIFT 0x0
+#define SDMA1_RAS_STATUS__IB_FETCH_ECC__SHIFT 0x1
+#define SDMA1_RAS_STATUS__F32_DATA_ECC__SHIFT 0x2
+#define SDMA1_RAS_STATUS__SEM_WPTR_ATOMIC_ECC__SHIFT 0x3
+#define SDMA1_RAS_STATUS__COPY_DATA_ECC__SHIFT 0x4
+#define SDMA1_RAS_STATUS__SRAM_ECC__SHIFT 0x5
+#define SDMA1_RAS_STATUS__RB_FETCH_NACK_GEN_ERR__SHIFT 0x8
+#define SDMA1_RAS_STATUS__IB_FETCH_NACK_GEN_ERR__SHIFT 0x9
+#define SDMA1_RAS_STATUS__F32_DATA_NACK_GEN_ERR__SHIFT 0xa
+#define SDMA1_RAS_STATUS__COPY_DATA_NACK_GEN_ERR__SHIFT 0xb
+#define SDMA1_RAS_STATUS__WRRET_DATA_NACK_GEN_ERR__SHIFT 0xc
+#define SDMA1_RAS_STATUS__WPTR_RPTR_ATOMIC_NACK_GEN_ERR__SHIFT 0xd
+#define SDMA1_RAS_STATUS__RB_FETCH_ECC_MASK 0x00000001L
+#define SDMA1_RAS_STATUS__IB_FETCH_ECC_MASK 0x00000002L
+#define SDMA1_RAS_STATUS__F32_DATA_ECC_MASK 0x00000004L
+#define SDMA1_RAS_STATUS__SEM_WPTR_ATOMIC_ECC_MASK 0x00000008L
+#define SDMA1_RAS_STATUS__COPY_DATA_ECC_MASK 0x00000010L
+#define SDMA1_RAS_STATUS__SRAM_ECC_MASK 0x00000020L
+#define SDMA1_RAS_STATUS__RB_FETCH_NACK_GEN_ERR_MASK 0x00000100L
+#define SDMA1_RAS_STATUS__IB_FETCH_NACK_GEN_ERR_MASK 0x00000200L
+#define SDMA1_RAS_STATUS__F32_DATA_NACK_GEN_ERR_MASK 0x00000400L
+#define SDMA1_RAS_STATUS__COPY_DATA_NACK_GEN_ERR_MASK 0x00000800L
+#define SDMA1_RAS_STATUS__WRRET_DATA_NACK_GEN_ERR_MASK 0x00001000L
+#define SDMA1_RAS_STATUS__WPTR_RPTR_ATOMIC_NACK_GEN_ERR_MASK 0x00002000L
+//SDMA1_CLK_STATUS
+#define SDMA1_CLK_STATUS__DYN_CLK__SHIFT 0x0
+#define SDMA1_CLK_STATUS__PTR_CLK__SHIFT 0x1
+#define SDMA1_CLK_STATUS__REG_CLK__SHIFT 0x2
+#define SDMA1_CLK_STATUS__F32_CLK__SHIFT 0x3
+#define SDMA1_CLK_STATUS__DYN_CLK_MASK 0x00000001L
+#define SDMA1_CLK_STATUS__PTR_CLK_MASK 0x00000002L
+#define SDMA1_CLK_STATUS__REG_CLK_MASK 0x00000004L
+#define SDMA1_CLK_STATUS__F32_CLK_MASK 0x00000008L
+//SDMA1_GFX_RB_CNTL
+#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA1_GFX_RB_BASE
+#define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_GFX_RB_BASE_HI
+#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA1_GFX_RB_RPTR
+#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_GFX_RB_RPTR_HI
+#define SDMA1_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_GFX_RB_WPTR
+#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_GFX_RB_WPTR_HI
+#define SDMA1_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_GFX_RB_WPTR_POLL_CNTL
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA1_GFX_RB_RPTR_ADDR_HI
+#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_GFX_RB_RPTR_ADDR_LO
+#define SDMA1_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_GFX_IB_CNTL
+#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA1_GFX_IB_RPTR
+#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA1_GFX_IB_OFFSET
+#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA1_GFX_IB_BASE_LO
+#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA1_GFX_IB_BASE_HI
+#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_GFX_IB_SIZE
+#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA1_GFX_SKIP_CNTL
+#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA1_GFX_CONTEXT_STATUS
+#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA1_GFX_DOORBELL
+#define SDMA1_GFX_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_GFX_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA1_GFX_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA1_GFX_CONTEXT_CNTL
+#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
+#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18
+#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L
+#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0x0F000000L
+//SDMA1_GFX_STATUS
+#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA1_GFX_DOORBELL_LOG
+#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA1_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA1_GFX_WATERMARK
+#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA1_GFX_DOORBELL_OFFSET
+#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA1_GFX_CSA_ADDR_LO
+#define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_GFX_CSA_ADDR_HI
+#define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_GFX_IB_SUB_REMAIN
+#define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA1_GFX_PREEMPT
+#define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA1_GFX_DUMMY_REG
+#define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA1_GFX_RB_WPTR_POLL_ADDR_HI
+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_GFX_RB_WPTR_POLL_ADDR_LO
+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_GFX_RB_AQL_CNTL
+#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA1_GFX_MINOR_PTR_UPDATE
+#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA1_GFX_MIDCMD_DATA0
+#define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_DATA1
+#define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_DATA2
+#define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_DATA3
+#define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_DATA4
+#define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_DATA5
+#define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_DATA6
+#define SDMA1_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_DATA7
+#define SDMA1_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_DATA8
+#define SDMA1_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_DATA9
+#define SDMA1_GFX_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_DATA10
+#define SDMA1_GFX_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_CNTL
+#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA1_PAGE_RB_CNTL
+#define SDMA1_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA1_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA1_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA1_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA1_PAGE_RB_BASE
+#define SDMA1_PAGE_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_RB_BASE_HI
+#define SDMA1_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA1_PAGE_RB_RPTR
+#define SDMA1_PAGE_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA1_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_RB_RPTR_HI
+#define SDMA1_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_RB_WPTR
+#define SDMA1_PAGE_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA1_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_RB_WPTR_HI
+#define SDMA1_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_RB_WPTR_POLL_CNTL
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA1_PAGE_RB_RPTR_ADDR_HI
+#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_RB_RPTR_ADDR_LO
+#define SDMA1_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_PAGE_IB_CNTL
+#define SDMA1_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA1_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA1_PAGE_IB_RPTR
+#define SDMA1_PAGE_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA1_PAGE_IB_OFFSET
+#define SDMA1_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA1_PAGE_IB_BASE_LO
+#define SDMA1_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA1_PAGE_IB_BASE_HI
+#define SDMA1_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_IB_SIZE
+#define SDMA1_PAGE_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA1_PAGE_SKIP_CNTL
+#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA1_PAGE_CONTEXT_STATUS
+#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA1_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA1_PAGE_DOORBELL
+#define SDMA1_PAGE_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_PAGE_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA1_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA1_PAGE_STATUS
+#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA1_PAGE_DOORBELL_LOG
+#define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA1_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA1_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA1_PAGE_WATERMARK
+#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA1_PAGE_DOORBELL_OFFSET
+#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA1_PAGE_CSA_ADDR_LO
+#define SDMA1_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_PAGE_CSA_ADDR_HI
+#define SDMA1_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_IB_SUB_REMAIN
+#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA1_PAGE_PREEMPT
+#define SDMA1_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA1_PAGE_DUMMY_REG
+#define SDMA1_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI
+#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO
+#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_PAGE_RB_AQL_CNTL
+#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA1_PAGE_MINOR_PTR_UPDATE
+#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA1_PAGE_MIDCMD_DATA0
+#define SDMA1_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_DATA1
+#define SDMA1_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_DATA2
+#define SDMA1_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_DATA3
+#define SDMA1_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_DATA4
+#define SDMA1_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_DATA5
+#define SDMA1_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_DATA6
+#define SDMA1_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_DATA7
+#define SDMA1_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_DATA8
+#define SDMA1_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_DATA9
+#define SDMA1_PAGE_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_DATA10
+#define SDMA1_PAGE_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_CNTL
+#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA1_RLC0_RB_CNTL
+#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA1_RLC0_RB_BASE
+#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_RB_BASE_HI
+#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA1_RLC0_RB_RPTR
+#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_RB_RPTR_HI
+#define SDMA1_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_RB_WPTR
+#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_RB_WPTR_HI
+#define SDMA1_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_RB_WPTR_POLL_CNTL
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA1_RLC0_RB_RPTR_ADDR_HI
+#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_RB_RPTR_ADDR_LO
+#define SDMA1_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC0_IB_CNTL
+#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA1_RLC0_IB_RPTR
+#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC0_IB_OFFSET
+#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC0_IB_BASE_LO
+#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA1_RLC0_IB_BASE_HI
+#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_IB_SIZE
+#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA1_RLC0_SKIP_CNTL
+#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA1_RLC0_CONTEXT_STATUS
+#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA1_RLC0_DOORBELL
+#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA1_RLC0_STATUS
+#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA1_RLC0_DOORBELL_LOG
+#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA1_RLC0_WATERMARK
+#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA1_RLC0_DOORBELL_OFFSET
+#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA1_RLC0_CSA_ADDR_LO
+#define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC0_CSA_ADDR_HI
+#define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_IB_SUB_REMAIN
+#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA1_RLC0_PREEMPT
+#define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA1_RLC0_DUMMY_REG
+#define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI
+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO
+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC0_RB_AQL_CNTL
+#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA1_RLC0_MINOR_PTR_UPDATE
+#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA1_RLC0_MIDCMD_DATA0
+#define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_DATA1
+#define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_DATA2
+#define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_DATA3
+#define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_DATA4
+#define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_DATA5
+#define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_DATA6
+#define SDMA1_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_DATA7
+#define SDMA1_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_DATA8
+#define SDMA1_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_DATA9
+#define SDMA1_RLC0_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_DATA10
+#define SDMA1_RLC0_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_CNTL
+#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA1_RLC1_RB_CNTL
+#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA1_RLC1_RB_BASE
+#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_RB_BASE_HI
+#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA1_RLC1_RB_RPTR
+#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_RB_RPTR_HI
+#define SDMA1_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_RB_WPTR
+#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_RB_WPTR_HI
+#define SDMA1_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_RB_WPTR_POLL_CNTL
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA1_RLC1_RB_RPTR_ADDR_HI
+#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_RB_RPTR_ADDR_LO
+#define SDMA1_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC1_IB_CNTL
+#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA1_RLC1_IB_RPTR
+#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC1_IB_OFFSET
+#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC1_IB_BASE_LO
+#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA1_RLC1_IB_BASE_HI
+#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_IB_SIZE
+#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA1_RLC1_SKIP_CNTL
+#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA1_RLC1_CONTEXT_STATUS
+#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA1_RLC1_DOORBELL
+#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA1_RLC1_STATUS
+#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA1_RLC1_DOORBELL_LOG
+#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA1_RLC1_WATERMARK
+#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA1_RLC1_DOORBELL_OFFSET
+#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA1_RLC1_CSA_ADDR_LO
+#define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC1_CSA_ADDR_HI
+#define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_IB_SUB_REMAIN
+#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA1_RLC1_PREEMPT
+#define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA1_RLC1_DUMMY_REG
+#define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI
+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO
+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC1_RB_AQL_CNTL
+#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA1_RLC1_MINOR_PTR_UPDATE
+#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA1_RLC1_MIDCMD_DATA0
+#define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_DATA1
+#define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_DATA2
+#define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_DATA3
+#define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_DATA4
+#define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_DATA5
+#define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_DATA6
+#define SDMA1_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_DATA7
+#define SDMA1_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_DATA8
+#define SDMA1_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_DATA9
+#define SDMA1_RLC1_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_DATA10
+#define SDMA1_RLC1_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_CNTL
+#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA1_RLC2_RB_CNTL
+#define SDMA1_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA1_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA1_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA1_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA1_RLC2_RB_BASE
+#define SDMA1_RLC2_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_RB_BASE_HI
+#define SDMA1_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA1_RLC2_RB_RPTR
+#define SDMA1_RLC2_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_RB_RPTR_HI
+#define SDMA1_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_RB_WPTR
+#define SDMA1_RLC2_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_RB_WPTR_HI
+#define SDMA1_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_RB_WPTR_POLL_CNTL
+#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA1_RLC2_RB_RPTR_ADDR_HI
+#define SDMA1_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_RB_RPTR_ADDR_LO
+#define SDMA1_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA1_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA1_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC2_IB_CNTL
+#define SDMA1_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA1_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA1_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA1_RLC2_IB_RPTR
+#define SDMA1_RLC2_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC2_IB_OFFSET
+#define SDMA1_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC2_IB_BASE_LO
+#define SDMA1_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA1_RLC2_IB_BASE_HI
+#define SDMA1_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_IB_SIZE
+#define SDMA1_RLC2_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA1_RLC2_SKIP_CNTL
+#define SDMA1_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA1_RLC2_CONTEXT_STATUS
+#define SDMA1_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA1_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA1_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA1_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA1_RLC2_DOORBELL
+#define SDMA1_RLC2_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_RLC2_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA1_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA1_RLC2_STATUS
+#define SDMA1_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA1_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA1_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA1_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA1_RLC2_DOORBELL_LOG
+#define SDMA1_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA1_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA1_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA1_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA1_RLC2_WATERMARK
+#define SDMA1_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA1_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA1_RLC2_DOORBELL_OFFSET
+#define SDMA1_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA1_RLC2_CSA_ADDR_LO
+#define SDMA1_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC2_CSA_ADDR_HI
+#define SDMA1_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_IB_SUB_REMAIN
+#define SDMA1_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA1_RLC2_PREEMPT
+#define SDMA1_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA1_RLC2_DUMMY_REG
+#define SDMA1_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI
+#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO
+#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC2_RB_AQL_CNTL
+#define SDMA1_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA1_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA1_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA1_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA1_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA1_RLC2_MINOR_PTR_UPDATE
+#define SDMA1_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA1_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA1_RLC2_MIDCMD_DATA0
+#define SDMA1_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA1_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_MIDCMD_DATA1
+#define SDMA1_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA1_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_MIDCMD_DATA2
+#define SDMA1_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA1_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_MIDCMD_DATA3
+#define SDMA1_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA1_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_MIDCMD_DATA4
+#define SDMA1_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA1_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_MIDCMD_DATA5
+#define SDMA1_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA1_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_MIDCMD_DATA6
+#define SDMA1_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA1_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_MIDCMD_DATA7
+#define SDMA1_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA1_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_MIDCMD_DATA8
+#define SDMA1_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA1_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_MIDCMD_DATA9
+#define SDMA1_RLC2_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA1_RLC2_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_MIDCMD_DATA10
+#define SDMA1_RLC2_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA1_RLC2_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_MIDCMD_CNTL
+#define SDMA1_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA1_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA1_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA1_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA1_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA1_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA1_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA1_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA1_RLC3_RB_CNTL
+#define SDMA1_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA1_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA1_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA1_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA1_RLC3_RB_BASE
+#define SDMA1_RLC3_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_RB_BASE_HI
+#define SDMA1_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA1_RLC3_RB_RPTR
+#define SDMA1_RLC3_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_RB_RPTR_HI
+#define SDMA1_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_RB_WPTR
+#define SDMA1_RLC3_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_RB_WPTR_HI
+#define SDMA1_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_RB_WPTR_POLL_CNTL
+#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA1_RLC3_RB_RPTR_ADDR_HI
+#define SDMA1_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_RB_RPTR_ADDR_LO
+#define SDMA1_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA1_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA1_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC3_IB_CNTL
+#define SDMA1_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA1_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA1_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA1_RLC3_IB_RPTR
+#define SDMA1_RLC3_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC3_IB_OFFSET
+#define SDMA1_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC3_IB_BASE_LO
+#define SDMA1_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA1_RLC3_IB_BASE_HI
+#define SDMA1_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_IB_SIZE
+#define SDMA1_RLC3_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA1_RLC3_SKIP_CNTL
+#define SDMA1_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA1_RLC3_CONTEXT_STATUS
+#define SDMA1_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA1_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA1_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA1_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA1_RLC3_DOORBELL
+#define SDMA1_RLC3_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_RLC3_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA1_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA1_RLC3_STATUS
+#define SDMA1_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA1_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA1_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA1_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA1_RLC3_DOORBELL_LOG
+#define SDMA1_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA1_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA1_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA1_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA1_RLC3_WATERMARK
+#define SDMA1_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA1_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA1_RLC3_DOORBELL_OFFSET
+#define SDMA1_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA1_RLC3_CSA_ADDR_LO
+#define SDMA1_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC3_CSA_ADDR_HI
+#define SDMA1_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_IB_SUB_REMAIN
+#define SDMA1_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA1_RLC3_PREEMPT
+#define SDMA1_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA1_RLC3_DUMMY_REG
+#define SDMA1_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI
+#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO
+#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC3_RB_AQL_CNTL
+#define SDMA1_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA1_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA1_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA1_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA1_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA1_RLC3_MINOR_PTR_UPDATE
+#define SDMA1_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA1_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA1_RLC3_MIDCMD_DATA0
+#define SDMA1_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA1_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_MIDCMD_DATA1
+#define SDMA1_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA1_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_MIDCMD_DATA2
+#define SDMA1_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA1_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_MIDCMD_DATA3
+#define SDMA1_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA1_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_MIDCMD_DATA4
+#define SDMA1_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA1_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_MIDCMD_DATA5
+#define SDMA1_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA1_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_MIDCMD_DATA6
+#define SDMA1_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA1_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_MIDCMD_DATA7
+#define SDMA1_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA1_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_MIDCMD_DATA8
+#define SDMA1_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA1_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_MIDCMD_DATA9
+#define SDMA1_RLC3_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA1_RLC3_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_MIDCMD_DATA10
+#define SDMA1_RLC3_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA1_RLC3_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_MIDCMD_CNTL
+#define SDMA1_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA1_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA1_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA1_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA1_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA1_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA1_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA1_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA1_RLC4_RB_CNTL
+#define SDMA1_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA1_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA1_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA1_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA1_RLC4_RB_BASE
+#define SDMA1_RLC4_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_RB_BASE_HI
+#define SDMA1_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA1_RLC4_RB_RPTR
+#define SDMA1_RLC4_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_RB_RPTR_HI
+#define SDMA1_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_RB_WPTR
+#define SDMA1_RLC4_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_RB_WPTR_HI
+#define SDMA1_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_RB_WPTR_POLL_CNTL
+#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA1_RLC4_RB_RPTR_ADDR_HI
+#define SDMA1_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_RB_RPTR_ADDR_LO
+#define SDMA1_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA1_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA1_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC4_IB_CNTL
+#define SDMA1_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA1_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA1_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA1_RLC4_IB_RPTR
+#define SDMA1_RLC4_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC4_IB_OFFSET
+#define SDMA1_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC4_IB_BASE_LO
+#define SDMA1_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA1_RLC4_IB_BASE_HI
+#define SDMA1_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_IB_SIZE
+#define SDMA1_RLC4_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA1_RLC4_SKIP_CNTL
+#define SDMA1_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA1_RLC4_CONTEXT_STATUS
+#define SDMA1_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA1_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA1_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA1_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA1_RLC4_DOORBELL
+#define SDMA1_RLC4_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_RLC4_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA1_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA1_RLC4_STATUS
+#define SDMA1_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA1_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA1_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA1_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA1_RLC4_DOORBELL_LOG
+#define SDMA1_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA1_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA1_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA1_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA1_RLC4_WATERMARK
+#define SDMA1_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA1_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA1_RLC4_DOORBELL_OFFSET
+#define SDMA1_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA1_RLC4_CSA_ADDR_LO
+#define SDMA1_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC4_CSA_ADDR_HI
+#define SDMA1_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_IB_SUB_REMAIN
+#define SDMA1_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA1_RLC4_PREEMPT
+#define SDMA1_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA1_RLC4_DUMMY_REG
+#define SDMA1_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI
+#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO
+#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC4_RB_AQL_CNTL
+#define SDMA1_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA1_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA1_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA1_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA1_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA1_RLC4_MINOR_PTR_UPDATE
+#define SDMA1_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA1_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA1_RLC4_MIDCMD_DATA0
+#define SDMA1_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA1_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_MIDCMD_DATA1
+#define SDMA1_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA1_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_MIDCMD_DATA2
+#define SDMA1_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA1_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_MIDCMD_DATA3
+#define SDMA1_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA1_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_MIDCMD_DATA4
+#define SDMA1_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA1_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_MIDCMD_DATA5
+#define SDMA1_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA1_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_MIDCMD_DATA6
+#define SDMA1_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA1_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_MIDCMD_DATA7
+#define SDMA1_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA1_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_MIDCMD_DATA8
+#define SDMA1_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA1_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_MIDCMD_DATA9
+#define SDMA1_RLC4_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA1_RLC4_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_MIDCMD_DATA10
+#define SDMA1_RLC4_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA1_RLC4_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_MIDCMD_CNTL
+#define SDMA1_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA1_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA1_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA1_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA1_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA1_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA1_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA1_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA1_RLC5_RB_CNTL
+#define SDMA1_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA1_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA1_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA1_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA1_RLC5_RB_BASE
+#define SDMA1_RLC5_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_RB_BASE_HI
+#define SDMA1_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA1_RLC5_RB_RPTR
+#define SDMA1_RLC5_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_RB_RPTR_HI
+#define SDMA1_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_RB_WPTR
+#define SDMA1_RLC5_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_RB_WPTR_HI
+#define SDMA1_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_RB_WPTR_POLL_CNTL
+#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA1_RLC5_RB_RPTR_ADDR_HI
+#define SDMA1_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_RB_RPTR_ADDR_LO
+#define SDMA1_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA1_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA1_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC5_IB_CNTL
+#define SDMA1_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA1_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA1_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA1_RLC5_IB_RPTR
+#define SDMA1_RLC5_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC5_IB_OFFSET
+#define SDMA1_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC5_IB_BASE_LO
+#define SDMA1_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA1_RLC5_IB_BASE_HI
+#define SDMA1_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_IB_SIZE
+#define SDMA1_RLC5_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA1_RLC5_SKIP_CNTL
+#define SDMA1_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA1_RLC5_CONTEXT_STATUS
+#define SDMA1_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA1_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA1_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA1_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA1_RLC5_DOORBELL
+#define SDMA1_RLC5_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_RLC5_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA1_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA1_RLC5_STATUS
+#define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA1_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA1_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA1_RLC5_DOORBELL_LOG
+#define SDMA1_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA1_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA1_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA1_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA1_RLC5_WATERMARK
+#define SDMA1_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA1_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA1_RLC5_DOORBELL_OFFSET
+#define SDMA1_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA1_RLC5_CSA_ADDR_LO
+#define SDMA1_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC5_CSA_ADDR_HI
+#define SDMA1_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_IB_SUB_REMAIN
+#define SDMA1_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA1_RLC5_PREEMPT
+#define SDMA1_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA1_RLC5_DUMMY_REG
+#define SDMA1_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI
+#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO
+#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC5_RB_AQL_CNTL
+#define SDMA1_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA1_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA1_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA1_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA1_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA1_RLC5_MINOR_PTR_UPDATE
+#define SDMA1_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA1_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA1_RLC5_MIDCMD_DATA0
+#define SDMA1_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA1_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_MIDCMD_DATA1
+#define SDMA1_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA1_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_MIDCMD_DATA2
+#define SDMA1_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA1_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_MIDCMD_DATA3
+#define SDMA1_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA1_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_MIDCMD_DATA4
+#define SDMA1_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA1_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_MIDCMD_DATA5
+#define SDMA1_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA1_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_MIDCMD_DATA6
+#define SDMA1_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA1_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_MIDCMD_DATA7
+#define SDMA1_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA1_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_MIDCMD_DATA8
+#define SDMA1_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA1_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_MIDCMD_DATA9
+#define SDMA1_RLC5_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA1_RLC5_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_MIDCMD_DATA10
+#define SDMA1_RLC5_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA1_RLC5_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_MIDCMD_CNTL
+#define SDMA1_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA1_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA1_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA1_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA1_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA1_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA1_RLC6_RB_CNTL
+#define SDMA1_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA1_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA1_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA1_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA1_RLC6_RB_BASE
+#define SDMA1_RLC6_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_RB_BASE_HI
+#define SDMA1_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA1_RLC6_RB_RPTR
+#define SDMA1_RLC6_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_RB_RPTR_HI
+#define SDMA1_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_RB_WPTR
+#define SDMA1_RLC6_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_RB_WPTR_HI
+#define SDMA1_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_RB_WPTR_POLL_CNTL
+#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA1_RLC6_RB_RPTR_ADDR_HI
+#define SDMA1_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_RB_RPTR_ADDR_LO
+#define SDMA1_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA1_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA1_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC6_IB_CNTL
+#define SDMA1_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA1_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA1_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA1_RLC6_IB_RPTR
+#define SDMA1_RLC6_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC6_IB_OFFSET
+#define SDMA1_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC6_IB_BASE_LO
+#define SDMA1_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA1_RLC6_IB_BASE_HI
+#define SDMA1_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_IB_SIZE
+#define SDMA1_RLC6_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA1_RLC6_SKIP_CNTL
+#define SDMA1_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA1_RLC6_CONTEXT_STATUS
+#define SDMA1_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA1_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA1_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA1_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA1_RLC6_DOORBELL
+#define SDMA1_RLC6_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_RLC6_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA1_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA1_RLC6_STATUS
+#define SDMA1_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA1_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA1_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA1_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA1_RLC6_DOORBELL_LOG
+#define SDMA1_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA1_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA1_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA1_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA1_RLC6_WATERMARK
+#define SDMA1_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA1_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA1_RLC6_DOORBELL_OFFSET
+#define SDMA1_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA1_RLC6_CSA_ADDR_LO
+#define SDMA1_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC6_CSA_ADDR_HI
+#define SDMA1_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_IB_SUB_REMAIN
+#define SDMA1_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA1_RLC6_PREEMPT
+#define SDMA1_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA1_RLC6_DUMMY_REG
+#define SDMA1_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI
+#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO
+#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC6_RB_AQL_CNTL
+#define SDMA1_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA1_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA1_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA1_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA1_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA1_RLC6_MINOR_PTR_UPDATE
+#define SDMA1_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA1_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA1_RLC6_MIDCMD_DATA0
+#define SDMA1_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA1_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_MIDCMD_DATA1
+#define SDMA1_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA1_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_MIDCMD_DATA2
+#define SDMA1_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA1_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_MIDCMD_DATA3
+#define SDMA1_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA1_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_MIDCMD_DATA4
+#define SDMA1_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA1_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_MIDCMD_DATA5
+#define SDMA1_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA1_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_MIDCMD_DATA6
+#define SDMA1_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA1_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_MIDCMD_DATA7
+#define SDMA1_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA1_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_MIDCMD_DATA8
+#define SDMA1_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA1_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_MIDCMD_DATA9
+#define SDMA1_RLC6_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA1_RLC6_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_MIDCMD_DATA10
+#define SDMA1_RLC6_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA1_RLC6_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_MIDCMD_CNTL
+#define SDMA1_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA1_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA1_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA1_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA1_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA1_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA1_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA1_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA1_RLC7_RB_CNTL
+#define SDMA1_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA1_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA1_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA1_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA1_RLC7_RB_BASE
+#define SDMA1_RLC7_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_RB_BASE_HI
+#define SDMA1_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA1_RLC7_RB_RPTR
+#define SDMA1_RLC7_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_RB_RPTR_HI
+#define SDMA1_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_RB_WPTR
+#define SDMA1_RLC7_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_RB_WPTR_HI
+#define SDMA1_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_RB_WPTR_POLL_CNTL
+#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA1_RLC7_RB_RPTR_ADDR_HI
+#define SDMA1_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_RB_RPTR_ADDR_LO
+#define SDMA1_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA1_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA1_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC7_IB_CNTL
+#define SDMA1_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA1_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA1_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA1_RLC7_IB_RPTR
+#define SDMA1_RLC7_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC7_IB_OFFSET
+#define SDMA1_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC7_IB_BASE_LO
+#define SDMA1_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA1_RLC7_IB_BASE_HI
+#define SDMA1_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_IB_SIZE
+#define SDMA1_RLC7_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA1_RLC7_SKIP_CNTL
+#define SDMA1_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA1_RLC7_CONTEXT_STATUS
+#define SDMA1_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA1_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA1_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA1_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA1_RLC7_DOORBELL
+#define SDMA1_RLC7_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_RLC7_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA1_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA1_RLC7_STATUS
+#define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA1_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA1_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA1_RLC7_DOORBELL_LOG
+#define SDMA1_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA1_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA1_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA1_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA1_RLC7_WATERMARK
+#define SDMA1_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA1_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA1_RLC7_DOORBELL_OFFSET
+#define SDMA1_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA1_RLC7_CSA_ADDR_LO
+#define SDMA1_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC7_CSA_ADDR_HI
+#define SDMA1_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_IB_SUB_REMAIN
+#define SDMA1_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA1_RLC7_PREEMPT
+#define SDMA1_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA1_RLC7_DUMMY_REG
+#define SDMA1_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI
+#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO
+#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC7_RB_AQL_CNTL
+#define SDMA1_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA1_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA1_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA1_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA1_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA1_RLC7_MINOR_PTR_UPDATE
+#define SDMA1_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA1_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA1_RLC7_MIDCMD_DATA0
+#define SDMA1_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA1_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_MIDCMD_DATA1
+#define SDMA1_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA1_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_MIDCMD_DATA2
+#define SDMA1_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA1_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_MIDCMD_DATA3
+#define SDMA1_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA1_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_MIDCMD_DATA4
+#define SDMA1_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA1_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_MIDCMD_DATA5
+#define SDMA1_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA1_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_MIDCMD_DATA6
+#define SDMA1_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA1_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_MIDCMD_DATA7
+#define SDMA1_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA1_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_MIDCMD_DATA8
+#define SDMA1_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA1_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_MIDCMD_DATA9
+#define SDMA1_RLC7_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA1_RLC7_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_MIDCMD_DATA10
+#define SDMA1_RLC7_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA1_RLC7_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_MIDCMD_CNTL
+#define SDMA1_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA1_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA1_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA1_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA1_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA1_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA1_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA1_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+
+
+// addressBlock: sdma0_sdma2dec
+//SDMA2_UCODE_ADDR
+#define SDMA2_UCODE_ADDR__VALUE__SHIFT 0x0
+#define SDMA2_UCODE_ADDR__VALUE_MASK 0x00003FFFL
+//SDMA2_UCODE_DATA
+#define SDMA2_UCODE_DATA__VALUE__SHIFT 0x0
+#define SDMA2_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL
+//SDMA2_VF_ENABLE
+#define SDMA2_VF_ENABLE__VF_ENABLE__SHIFT 0x0
+#define SDMA2_VF_ENABLE__VF_ENABLE_MASK 0x00000001L
+#define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_ADDR__SHIFT 0x0
+#define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_DATA__SHIFT 0x1
+#define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_ADDR_MASK 0x00000001L
+#define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_DATA_MASK 0x00000002L
+//SDMA2_CONTEXT_GROUP_BOUNDARY
+#define SDMA2_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0
+#define SDMA2_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL
+//SDMA2_POWER_CNTL
+#define SDMA2_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0
+#define SDMA2_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1
+#define SDMA2_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2
+#define SDMA2_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3
+#define SDMA2_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
+#define SDMA2_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9
+#define SDMA2_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
+#define SDMA2_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb
+#define SDMA2_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc
+#define SDMA2_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a
+#define SDMA2_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L
+#define SDMA2_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L
+#define SDMA2_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L
+#define SDMA2_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L
+#define SDMA2_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L
+#define SDMA2_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L
+#define SDMA2_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L
+#define SDMA2_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L
+#define SDMA2_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L
+#define SDMA2_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
+//SDMA2_CLK_CTRL
+#define SDMA2_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define SDMA2_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define SDMA2_CLK_CTRL__RESERVED__SHIFT 0xc
+#define SDMA2_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define SDMA2_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define SDMA2_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define SDMA2_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define SDMA2_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define SDMA2_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define SDMA2_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define SDMA2_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define SDMA2_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define SDMA2_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define SDMA2_CLK_CTRL__RESERVED_MASK 0x00FFF000L
+#define SDMA2_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define SDMA2_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define SDMA2_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define SDMA2_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define SDMA2_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define SDMA2_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define SDMA2_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define SDMA2_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//SDMA2_CNTL
+#define SDMA2_CNTL__TRAP_ENABLE__SHIFT 0x0
+#define SDMA2_CNTL__UTC_L1_ENABLE__SHIFT 0x1
+#define SDMA2_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
+#define SDMA2_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
+#define SDMA2_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
+#define SDMA2_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5
+#define SDMA2_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x6
+#define SDMA2_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11
+#define SDMA2_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
+#define SDMA2_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
+#define SDMA2_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
+#define SDMA2_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e
+#define SDMA2_CNTL__TRAP_ENABLE_MASK 0x00000001L
+#define SDMA2_CNTL__UTC_L1_ENABLE_MASK 0x00000002L
+#define SDMA2_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L
+#define SDMA2_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L
+#define SDMA2_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA2_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L
+#define SDMA2_CNTL__MIDCMD_EXPIRE_ENABLE_MASK 0x00000040L
+#define SDMA2_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L
+#define SDMA2_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L
+#define SDMA2_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L
+#define SDMA2_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L
+#define SDMA2_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L
+//SDMA2_CHICKEN_BITS
+#define SDMA2_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
+#define SDMA2_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
+#define SDMA2_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
+#define SDMA2_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8
+#define SDMA2_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
+#define SDMA2_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
+#define SDMA2_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11
+#define SDMA2_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
+#define SDMA2_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
+#define SDMA2_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19
+#define SDMA2_CHICKEN_BITS__SRAM_FGCG_ENABLE__SHIFT 0x1a
+#define SDMA2_CHICKEN_BITS__RESERVED__SHIFT 0x1b
+#define SDMA2_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L
+#define SDMA2_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L
+#define SDMA2_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L
+#define SDMA2_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L
+#define SDMA2_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L
+#define SDMA2_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L
+#define SDMA2_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L
+#define SDMA2_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L
+#define SDMA2_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L
+#define SDMA2_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L
+#define SDMA2_CHICKEN_BITS__SRAM_FGCG_ENABLE_MASK 0x04000000L
+#define SDMA2_CHICKEN_BITS__RESERVED_MASK 0xF8000000L
+//SDMA2_GB_ADDR_CONFIG
+#define SDMA2_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define SDMA2_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define SDMA2_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define SDMA2_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
+#define SDMA2_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
+#define SDMA2_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
+#define SDMA2_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define SDMA2_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
+#define SDMA2_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
+#define SDMA2_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
+//SDMA2_GB_ADDR_CONFIG_READ
+#define SDMA2_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0
+#define SDMA2_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define SDMA2_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define SDMA2_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc
+#define SDMA2_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13
+#define SDMA2_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L
+#define SDMA2_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define SDMA2_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
+#define SDMA2_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L
+#define SDMA2_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L
+//SDMA2_RB_RPTR_FETCH_HI
+#define SDMA2_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0
+#define SDMA2_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_SEM_WAIT_FAIL_TIMER_CNTL
+#define SDMA2_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
+#define SDMA2_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL
+//SDMA2_RB_RPTR_FETCH
+#define SDMA2_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
+#define SDMA2_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL
+//SDMA2_IB_OFFSET_FETCH
+#define SDMA2_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
+#define SDMA2_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL
+//SDMA2_PROGRAM
+#define SDMA2_PROGRAM__STREAM__SHIFT 0x0
+#define SDMA2_PROGRAM__STREAM_MASK 0xFFFFFFFFL
+//SDMA2_STATUS_REG
+#define SDMA2_STATUS_REG__IDLE__SHIFT 0x0
+#define SDMA2_STATUS_REG__REG_IDLE__SHIFT 0x1
+#define SDMA2_STATUS_REG__RB_EMPTY__SHIFT 0x2
+#define SDMA2_STATUS_REG__RB_FULL__SHIFT 0x3
+#define SDMA2_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
+#define SDMA2_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
+#define SDMA2_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
+#define SDMA2_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
+#define SDMA2_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
+#define SDMA2_STATUS_REG__INSIDE_IB__SHIFT 0x9
+#define SDMA2_STATUS_REG__EX_IDLE__SHIFT 0xa
+#define SDMA2_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
+#define SDMA2_STATUS_REG__PACKET_READY__SHIFT 0xc
+#define SDMA2_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
+#define SDMA2_STATUS_REG__SRBM_IDLE__SHIFT 0xe
+#define SDMA2_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
+#define SDMA2_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10
+#define SDMA2_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
+#define SDMA2_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
+#define SDMA2_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
+#define SDMA2_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14
+#define SDMA2_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
+#define SDMA2_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
+#define SDMA2_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
+#define SDMA2_STATUS_REG__SEM_IDLE__SHIFT 0x1a
+#define SDMA2_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
+#define SDMA2_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
+#define SDMA2_STATUS_REG__INT_IDLE__SHIFT 0x1e
+#define SDMA2_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
+#define SDMA2_STATUS_REG__IDLE_MASK 0x00000001L
+#define SDMA2_STATUS_REG__REG_IDLE_MASK 0x00000002L
+#define SDMA2_STATUS_REG__RB_EMPTY_MASK 0x00000004L
+#define SDMA2_STATUS_REG__RB_FULL_MASK 0x00000008L
+#define SDMA2_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L
+#define SDMA2_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L
+#define SDMA2_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L
+#define SDMA2_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L
+#define SDMA2_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L
+#define SDMA2_STATUS_REG__INSIDE_IB_MASK 0x00000200L
+#define SDMA2_STATUS_REG__EX_IDLE_MASK 0x00000400L
+#define SDMA2_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L
+#define SDMA2_STATUS_REG__PACKET_READY_MASK 0x00001000L
+#define SDMA2_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L
+#define SDMA2_STATUS_REG__SRBM_IDLE_MASK 0x00004000L
+#define SDMA2_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L
+#define SDMA2_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L
+#define SDMA2_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L
+#define SDMA2_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L
+#define SDMA2_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L
+#define SDMA2_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L
+#define SDMA2_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L
+#define SDMA2_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L
+#define SDMA2_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L
+#define SDMA2_STATUS_REG__SEM_IDLE_MASK 0x04000000L
+#define SDMA2_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L
+#define SDMA2_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L
+#define SDMA2_STATUS_REG__INT_IDLE_MASK 0x40000000L
+#define SDMA2_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L
+//SDMA2_STATUS1_REG
+#define SDMA2_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
+#define SDMA2_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
+#define SDMA2_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
+#define SDMA2_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
+#define SDMA2_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
+#define SDMA2_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
+#define SDMA2_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
+#define SDMA2_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9
+#define SDMA2_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
+#define SDMA2_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
+#define SDMA2_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
+#define SDMA2_STATUS1_REG__EX_START__SHIFT 0xf
+#define SDMA2_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
+#define SDMA2_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
+#define SDMA2_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L
+#define SDMA2_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L
+#define SDMA2_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L
+#define SDMA2_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L
+#define SDMA2_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L
+#define SDMA2_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L
+#define SDMA2_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L
+#define SDMA2_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L
+#define SDMA2_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L
+#define SDMA2_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L
+#define SDMA2_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L
+#define SDMA2_STATUS1_REG__EX_START_MASK 0x00008000L
+#define SDMA2_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L
+#define SDMA2_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L
+//SDMA2_RD_BURST_CNTL
+#define SDMA2_RD_BURST_CNTL__RD_BURST__SHIFT 0x0
+#define SDMA2_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2
+#define SDMA2_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L
+#define SDMA2_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL
+//SDMA2_HBM_PAGE_CONFIG
+#define SDMA2_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0
+#define SDMA2_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L
+//SDMA2_UCODE_CHECKSUM
+#define SDMA2_UCODE_CHECKSUM__DATA__SHIFT 0x0
+#define SDMA2_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL
+//SDMA2_F32_CNTL
+#define SDMA2_F32_CNTL__HALT__SHIFT 0x0
+#define SDMA2_F32_CNTL__STEP__SHIFT 0x1
+#define SDMA2_F32_CNTL__RESET__SHIFT 0x8
+#define SDMA2_F32_CNTL__HALT_MASK 0x00000001L
+#define SDMA2_F32_CNTL__STEP_MASK 0x00000002L
+#define SDMA2_F32_CNTL__RESET_MASK 0x00000100L
+//SDMA2_FREEZE
+#define SDMA2_FREEZE__PREEMPT__SHIFT 0x0
+#define SDMA2_FREEZE__FREEZE__SHIFT 0x4
+#define SDMA2_FREEZE__FROZEN__SHIFT 0x5
+#define SDMA2_FREEZE__F32_FREEZE__SHIFT 0x6
+#define SDMA2_FREEZE__PREEMPT_MASK 0x00000001L
+#define SDMA2_FREEZE__FREEZE_MASK 0x00000010L
+#define SDMA2_FREEZE__FROZEN_MASK 0x00000020L
+#define SDMA2_FREEZE__F32_FREEZE_MASK 0x00000040L
+//SDMA2_PHASE0_QUANTUM
+#define SDMA2_PHASE0_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA2_PHASE0_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA2_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA2_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL
+#define SDMA2_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L
+#define SDMA2_PHASE0_QUANTUM__PREFER_MASK 0x40000000L
+//SDMA2_PHASE1_QUANTUM
+#define SDMA2_PHASE1_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA2_PHASE1_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA2_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA2_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL
+#define SDMA2_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L
+#define SDMA2_PHASE1_QUANTUM__PREFER_MASK 0x40000000L
+//CC_SDMA2_EDC_CONFIG
+#define CC_SDMA2_EDC_CONFIG__DIS_EDC__SHIFT 0x1
+#define CC_SDMA2_EDC_CONFIG__DIS_EDC_MASK 0x00000002L
+//SDMA2_BA_THRESHOLD
+#define SDMA2_BA_THRESHOLD__READ_THRES__SHIFT 0x0
+#define SDMA2_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10
+#define SDMA2_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL
+#define SDMA2_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L
+//SDMA2_ID
+#define SDMA2_ID__DEVICE_ID__SHIFT 0x0
+#define SDMA2_ID__DEVICE_ID_MASK 0x000000FFL
+//SDMA2_VERSION
+#define SDMA2_VERSION__MINVER__SHIFT 0x0
+#define SDMA2_VERSION__MAJVER__SHIFT 0x8
+#define SDMA2_VERSION__REV__SHIFT 0x10
+#define SDMA2_VERSION__MINVER_MASK 0x0000007FL
+#define SDMA2_VERSION__MAJVER_MASK 0x00007F00L
+#define SDMA2_VERSION__REV_MASK 0x003F0000L
+//SDMA2_EDC_COUNTER
+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x0
+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x2
+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x4
+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0x6
+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0x8
+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xa
+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xc
+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe
+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0x10
+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x12
+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x14
+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x16
+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x18
+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x1a
+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x1c
+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x1e
+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000003L
+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x0000000CL
+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000030L
+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x000000C0L
+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000300L
+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00000C00L
+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00003000L
+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x0000C000L
+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00030000L
+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x000C0000L
+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00300000L
+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00C00000L
+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x03000000L
+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x0C000000L
+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x30000000L
+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0xC0000000L
+//SDMA2_EDC_COUNTER2
+#define SDMA2_EDC_COUNTER2__SDMA_UCODE_BUF_SED__SHIFT 0x0
+#define SDMA2_EDC_COUNTER2__SDMA_RB_CMD_BUF_SED__SHIFT 0x2
+#define SDMA2_EDC_COUNTER2__SDMA_IB_CMD_BUF_SED__SHIFT 0x4
+#define SDMA2_EDC_COUNTER2__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x6
+#define SDMA2_EDC_COUNTER2__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x8
+#define SDMA2_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED__SHIFT 0xa
+#define SDMA2_EDC_COUNTER2__SDMA_DATA_LUT_FIFO_SED__SHIFT 0xc
+#define SDMA2_EDC_COUNTER2__SDMA_SPLIT_DATA_BUF_SED__SHIFT 0xe
+#define SDMA2_EDC_COUNTER2__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10
+#define SDMA2_EDC_COUNTER2__SDMA_MC_RDRET_BUF_SED__SHIFT 0x12
+#define SDMA2_EDC_COUNTER2__SDMA_UCODE_BUF_SED_MASK 0x00000003L
+#define SDMA2_EDC_COUNTER2__SDMA_RB_CMD_BUF_SED_MASK 0x0000000CL
+#define SDMA2_EDC_COUNTER2__SDMA_IB_CMD_BUF_SED_MASK 0x00000030L
+#define SDMA2_EDC_COUNTER2__SDMA_UTCL1_RD_FIFO_SED_MASK 0x000000C0L
+#define SDMA2_EDC_COUNTER2__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000300L
+#define SDMA2_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED_MASK 0x00000C00L
+#define SDMA2_EDC_COUNTER2__SDMA_DATA_LUT_FIFO_SED_MASK 0x00003000L
+#define SDMA2_EDC_COUNTER2__SDMA_SPLIT_DATA_BUF_SED_MASK 0x0000C000L
+#define SDMA2_EDC_COUNTER2__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00030000L
+#define SDMA2_EDC_COUNTER2__SDMA_MC_RDRET_BUF_SED_MASK 0x000C0000L
+//SDMA2_STATUS2_REG
+#define SDMA2_STATUS2_REG__ID__SHIFT 0x0
+#define SDMA2_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3
+#define SDMA2_STATUS2_REG__CMD_OP__SHIFT 0x10
+#define SDMA2_STATUS2_REG__ID_MASK 0x00000007L
+#define SDMA2_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L
+#define SDMA2_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L
+//SDMA2_ATOMIC_CNTL
+#define SDMA2_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0
+#define SDMA2_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f
+#define SDMA2_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL
+#define SDMA2_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L
+//SDMA2_ATOMIC_PREOP_LO
+#define SDMA2_ATOMIC_PREOP_LO__DATA__SHIFT 0x0
+#define SDMA2_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL
+//SDMA2_ATOMIC_PREOP_HI
+#define SDMA2_ATOMIC_PREOP_HI__DATA__SHIFT 0x0
+#define SDMA2_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL
+//SDMA2_UTCL1_CNTL
+#define SDMA2_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0
+#define SDMA2_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1
+#define SDMA2_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb
+#define SDMA2_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe
+#define SDMA2_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18
+#define SDMA2_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
+#define SDMA2_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L
+#define SDMA2_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL
+#define SDMA2_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L
+#define SDMA2_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L
+#define SDMA2_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L
+#define SDMA2_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L
+//SDMA2_UTCL1_WATERMK
+#define SDMA2_UTCL1_WATERMK__REQ_WATERMK__SHIFT 0x0
+#define SDMA2_UTCL1_WATERMK__REQ_DEPTH__SHIFT 0x3
+#define SDMA2_UTCL1_WATERMK__PAGE_WATERMK__SHIFT 0x5
+#define SDMA2_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x8
+#define SDMA2_UTCL1_WATERMK__RESERVED__SHIFT 0x10
+#define SDMA2_UTCL1_WATERMK__REQ_WATERMK_MASK 0x00000007L
+#define SDMA2_UTCL1_WATERMK__REQ_DEPTH_MASK 0x00000018L
+#define SDMA2_UTCL1_WATERMK__PAGE_WATERMK_MASK 0x000000E0L
+#define SDMA2_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x0000FF00L
+#define SDMA2_UTCL1_WATERMK__RESERVED_MASK 0xFFFF0000L
+//SDMA2_UTCL1_RD_STATUS
+#define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
+#define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
+#define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
+#define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
+#define SDMA2_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
+#define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
+#define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
+#define SDMA2_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
+#define SDMA2_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
+#define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
+#define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
+#define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
+#define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
+#define SDMA2_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
+#define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
+#define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
+#define SDMA2_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
+#define SDMA2_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
+#define SDMA2_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12
+#define SDMA2_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13
+#define SDMA2_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14
+#define SDMA2_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15
+#define SDMA2_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16
+#define SDMA2_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a
+#define SDMA2_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
+#define SDMA2_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e
+#define SDMA2_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f
+#define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
+#define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L
+#define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L
+#define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L
+#define SDMA2_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L
+#define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L
+#define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L
+#define SDMA2_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L
+#define SDMA2_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L
+#define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L
+#define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L
+#define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L
+#define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L
+#define SDMA2_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L
+#define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L
+#define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L
+#define SDMA2_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L
+#define SDMA2_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L
+#define SDMA2_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L
+#define SDMA2_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L
+#define SDMA2_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L
+#define SDMA2_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L
+#define SDMA2_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L
+#define SDMA2_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L
+#define SDMA2_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L
+#define SDMA2_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L
+#define SDMA2_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L
+//SDMA2_UTCL1_WR_STATUS
+#define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
+#define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
+#define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
+#define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
+#define SDMA2_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
+#define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
+#define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
+#define SDMA2_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
+#define SDMA2_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
+#define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
+#define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
+#define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
+#define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
+#define SDMA2_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
+#define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
+#define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
+#define SDMA2_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
+#define SDMA2_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
+#define SDMA2_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12
+#define SDMA2_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13
+#define SDMA2_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14
+#define SDMA2_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15
+#define SDMA2_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16
+#define SDMA2_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19
+#define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c
+#define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
+#define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e
+#define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f
+#define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
+#define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L
+#define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L
+#define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L
+#define SDMA2_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L
+#define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L
+#define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L
+#define SDMA2_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L
+#define SDMA2_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L
+#define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L
+#define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L
+#define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L
+#define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L
+#define SDMA2_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L
+#define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L
+#define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L
+#define SDMA2_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L
+#define SDMA2_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L
+#define SDMA2_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L
+#define SDMA2_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L
+#define SDMA2_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L
+#define SDMA2_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L
+#define SDMA2_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L
+#define SDMA2_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L
+#define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L
+#define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L
+#define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L
+#define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L
+//SDMA2_UTCL1_INV0
+#define SDMA2_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0
+#define SDMA2_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1
+#define SDMA2_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2
+#define SDMA2_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3
+#define SDMA2_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4
+#define SDMA2_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5
+#define SDMA2_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6
+#define SDMA2_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7
+#define SDMA2_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8
+#define SDMA2_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9
+#define SDMA2_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa
+#define SDMA2_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb
+#define SDMA2_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc
+#define SDMA2_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c
+#define SDMA2_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L
+#define SDMA2_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L
+#define SDMA2_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L
+#define SDMA2_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L
+#define SDMA2_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L
+#define SDMA2_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L
+#define SDMA2_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L
+#define SDMA2_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L
+#define SDMA2_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L
+#define SDMA2_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L
+#define SDMA2_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L
+#define SDMA2_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L
+#define SDMA2_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L
+#define SDMA2_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L
+//SDMA2_UTCL1_INV1
+#define SDMA2_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0
+#define SDMA2_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL
+//SDMA2_UTCL1_INV2
+#define SDMA2_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0
+#define SDMA2_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL
+//SDMA2_UTCL1_RD_XNACK0
+#define SDMA2_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
+#define SDMA2_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
+//SDMA2_UTCL1_RD_XNACK1
+#define SDMA2_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
+#define SDMA2_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4
+#define SDMA2_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8
+#define SDMA2_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a
+#define SDMA2_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
+#define SDMA2_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L
+#define SDMA2_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
+#define SDMA2_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L
+//SDMA2_UTCL1_WR_XNACK0
+#define SDMA2_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
+#define SDMA2_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
+//SDMA2_UTCL1_WR_XNACK1
+#define SDMA2_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
+#define SDMA2_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4
+#define SDMA2_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8
+#define SDMA2_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a
+#define SDMA2_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
+#define SDMA2_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L
+#define SDMA2_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
+#define SDMA2_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L
+//SDMA2_UTCL1_TIMEOUT
+#define SDMA2_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0
+#define SDMA2_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10
+#define SDMA2_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL
+#define SDMA2_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L
+//SDMA2_UTCL1_PAGE
+#define SDMA2_UTCL1_PAGE__VM_HOLE__SHIFT 0x0
+#define SDMA2_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1
+#define SDMA2_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6
+#define SDMA2_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9
+#define SDMA2_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L
+#define SDMA2_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL
+#define SDMA2_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L
+#define SDMA2_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L
+//SDMA2_POWER_CNTL_IDLE
+#define SDMA2_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0
+#define SDMA2_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10
+#define SDMA2_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18
+#define SDMA2_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL
+#define SDMA2_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L
+#define SDMA2_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L
+//SDMA2_RELAX_ORDERING_LUT
+#define SDMA2_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0
+#define SDMA2_RELAX_ORDERING_LUT__COPY__SHIFT 0x1
+#define SDMA2_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2
+#define SDMA2_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3
+#define SDMA2_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4
+#define SDMA2_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5
+#define SDMA2_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6
+#define SDMA2_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8
+#define SDMA2_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9
+#define SDMA2_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa
+#define SDMA2_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb
+#define SDMA2_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc
+#define SDMA2_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd
+#define SDMA2_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe
+#define SDMA2_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b
+#define SDMA2_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c
+#define SDMA2_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
+#define SDMA2_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e
+#define SDMA2_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f
+#define SDMA2_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L
+#define SDMA2_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L
+#define SDMA2_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L
+#define SDMA2_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L
+#define SDMA2_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L
+#define SDMA2_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L
+#define SDMA2_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L
+#define SDMA2_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L
+#define SDMA2_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L
+#define SDMA2_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L
+#define SDMA2_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L
+#define SDMA2_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L
+#define SDMA2_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L
+#define SDMA2_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L
+#define SDMA2_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L
+#define SDMA2_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L
+#define SDMA2_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L
+#define SDMA2_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L
+#define SDMA2_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L
+//SDMA2_CHICKEN_BITS_2
+#define SDMA2_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0
+#define SDMA2_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT 0x4
+#define SDMA2_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL
+#define SDMA2_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK 0x00000010L
+//SDMA2_STATUS3_REG
+#define SDMA2_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0
+#define SDMA2_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10
+#define SDMA2_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14
+#define SDMA2_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15
+#define SDMA2_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16
+#define SDMA2_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL
+#define SDMA2_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L
+#define SDMA2_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L
+#define SDMA2_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L
+#define SDMA2_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L
+//SDMA2_PHYSICAL_ADDR_LO
+#define SDMA2_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0
+#define SDMA2_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1
+#define SDMA2_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2
+#define SDMA2_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc
+#define SDMA2_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L
+#define SDMA2_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L
+#define SDMA2_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L
+#define SDMA2_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L
+//SDMA2_PHYSICAL_ADDR_HI
+#define SDMA2_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA2_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL
+//SDMA2_PHASE2_QUANTUM
+#define SDMA2_PHASE2_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA2_PHASE2_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA2_PHASE2_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA2_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL
+#define SDMA2_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L
+#define SDMA2_PHASE2_QUANTUM__PREFER_MASK 0x40000000L
+//SDMA2_ERROR_LOG
+#define SDMA2_ERROR_LOG__OVERRIDE__SHIFT 0x0
+#define SDMA2_ERROR_LOG__STATUS__SHIFT 0x10
+#define SDMA2_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL
+#define SDMA2_ERROR_LOG__STATUS_MASK 0xFFFF0000L
+//SDMA2_PUB_DUMMY_REG0
+#define SDMA2_PUB_DUMMY_REG0__VALUE__SHIFT 0x0
+#define SDMA2_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL
+//SDMA2_PUB_DUMMY_REG1
+#define SDMA2_PUB_DUMMY_REG1__VALUE__SHIFT 0x0
+#define SDMA2_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL
+//SDMA2_PUB_DUMMY_REG2
+#define SDMA2_PUB_DUMMY_REG2__VALUE__SHIFT 0x0
+#define SDMA2_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL
+//SDMA2_PUB_DUMMY_REG3
+#define SDMA2_PUB_DUMMY_REG3__VALUE__SHIFT 0x0
+#define SDMA2_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL
+//SDMA2_F32_COUNTER
+#define SDMA2_F32_COUNTER__VALUE__SHIFT 0x0
+#define SDMA2_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL
+//SDMA2_PERFCNT_PERFCOUNTER0_CFG
+#define SDMA2_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define SDMA2_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define SDMA2_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define SDMA2_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define SDMA2_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define SDMA2_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define SDMA2_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define SDMA2_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define SDMA2_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define SDMA2_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//SDMA2_PERFCNT_PERFCOUNTER1_CFG
+#define SDMA2_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define SDMA2_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define SDMA2_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define SDMA2_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define SDMA2_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define SDMA2_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define SDMA2_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define SDMA2_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define SDMA2_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define SDMA2_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL
+#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+//SDMA2_PERFCNT_MISC_CNTL
+#define SDMA2_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x0
+#define SDMA2_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000FFFFL
+//SDMA2_PERFCNT_PERFCOUNTER_LO
+#define SDMA2_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define SDMA2_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//SDMA2_PERFCNT_PERFCOUNTER_HI
+#define SDMA2_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define SDMA2_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define SDMA2_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define SDMA2_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//SDMA2_CRD_CNTL
+#define SDMA2_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7
+#define SDMA2_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd
+#define SDMA2_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L
+#define SDMA2_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L
+//SDMA2_ULV_CNTL
+#define SDMA2_ULV_CNTL__HYSTERESIS__SHIFT 0x0
+#define SDMA2_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b
+#define SDMA2_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c
+#define SDMA2_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
+#define SDMA2_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e
+#define SDMA2_ULV_CNTL__ULV_STATUS__SHIFT 0x1f
+#define SDMA2_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL
+#define SDMA2_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L
+#define SDMA2_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L
+#define SDMA2_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L
+#define SDMA2_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L
+#define SDMA2_ULV_CNTL__ULV_STATUS_MASK 0x80000000L
+//SDMA2_EA_DBIT_ADDR_DATA
+#define SDMA2_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0
+#define SDMA2_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL
+//SDMA2_EA_DBIT_ADDR_INDEX
+#define SDMA2_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0
+#define SDMA2_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L
+//SDMA2_STATUS4_REG
+#define SDMA2_STATUS4_REG__IDLE__SHIFT 0x0
+#define SDMA2_STATUS4_REG__IH_OUTSTANDING__SHIFT 0x2
+#define SDMA2_STATUS4_REG__SEM_OUTSTANDING__SHIFT 0x3
+#define SDMA2_STATUS4_REG__MMHUB_RD_OUTSTANDING__SHIFT 0x4
+#define SDMA2_STATUS4_REG__MMHUB_WR_OUTSTANDING__SHIFT 0x5
+#define SDMA2_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT 0x6
+#define SDMA2_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT 0x7
+#define SDMA2_STATUS4_REG__REG_POLLING__SHIFT 0x8
+#define SDMA2_STATUS4_REG__MEM_POLLING__SHIFT 0x9
+#define SDMA2_STATUS4_REG__UTCL2_RD_XNACK__SHIFT 0xa
+#define SDMA2_STATUS4_REG__UTCL2_WR_XNACK__SHIFT 0xc
+#define SDMA2_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT 0xe
+#define SDMA2_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT 0x12
+#define SDMA2_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT 0x13
+#define SDMA2_STATUS4_REG__IDLE_MASK 0x00000001L
+#define SDMA2_STATUS4_REG__IH_OUTSTANDING_MASK 0x00000004L
+#define SDMA2_STATUS4_REG__SEM_OUTSTANDING_MASK 0x00000008L
+#define SDMA2_STATUS4_REG__MMHUB_RD_OUTSTANDING_MASK 0x00000010L
+#define SDMA2_STATUS4_REG__MMHUB_WR_OUTSTANDING_MASK 0x00000020L
+#define SDMA2_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK 0x00000040L
+#define SDMA2_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK 0x00000080L
+#define SDMA2_STATUS4_REG__REG_POLLING_MASK 0x00000100L
+#define SDMA2_STATUS4_REG__MEM_POLLING_MASK 0x00000200L
+#define SDMA2_STATUS4_REG__UTCL2_RD_XNACK_MASK 0x00000C00L
+#define SDMA2_STATUS4_REG__UTCL2_WR_XNACK_MASK 0x00003000L
+#define SDMA2_STATUS4_REG__ACTIVE_QUEUE_ID_MASK 0x0003C000L
+#define SDMA2_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK 0x00040000L
+#define SDMA2_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK 0x00080000L
+//SDMA2_SCRATCH_RAM_DATA
+#define SDMA2_SCRATCH_RAM_DATA__DATA__SHIFT 0x0
+#define SDMA2_SCRATCH_RAM_DATA__DATA_MASK 0xFFFFFFFFL
+//SDMA2_SCRATCH_RAM_ADDR
+#define SDMA2_SCRATCH_RAM_ADDR__ADDR__SHIFT 0x0
+#define SDMA2_SCRATCH_RAM_ADDR__ADDR_MASK 0x0000007FL
+//SDMA2_CE_CTRL
+#define SDMA2_CE_CTRL__RD_LUT_WATERMARK__SHIFT 0x0
+#define SDMA2_CE_CTRL__RD_LUT_DEPTH__SHIFT 0x3
+#define SDMA2_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT 0x5
+#define SDMA2_CE_CTRL__RESERVED__SHIFT 0x8
+#define SDMA2_CE_CTRL__RD_LUT_WATERMARK_MASK 0x00000007L
+#define SDMA2_CE_CTRL__RD_LUT_DEPTH_MASK 0x00000018L
+#define SDMA2_CE_CTRL__WR_AFIFO_WATERMARK_MASK 0x000000E0L
+#define SDMA2_CE_CTRL__RESERVED_MASK 0xFFFFFF00L
+//SDMA2_RAS_STATUS
+#define SDMA2_RAS_STATUS__RB_FETCH_ECC__SHIFT 0x0
+#define SDMA2_RAS_STATUS__IB_FETCH_ECC__SHIFT 0x1
+#define SDMA2_RAS_STATUS__F32_DATA_ECC__SHIFT 0x2
+#define SDMA2_RAS_STATUS__SEM_WPTR_ATOMIC_ECC__SHIFT 0x3
+#define SDMA2_RAS_STATUS__COPY_DATA_ECC__SHIFT 0x4
+#define SDMA2_RAS_STATUS__SRAM_ECC__SHIFT 0x5
+#define SDMA2_RAS_STATUS__RB_FETCH_NACK_GEN_ERR__SHIFT 0x8
+#define SDMA2_RAS_STATUS__IB_FETCH_NACK_GEN_ERR__SHIFT 0x9
+#define SDMA2_RAS_STATUS__F32_DATA_NACK_GEN_ERR__SHIFT 0xa
+#define SDMA2_RAS_STATUS__COPY_DATA_NACK_GEN_ERR__SHIFT 0xb
+#define SDMA2_RAS_STATUS__WRRET_DATA_NACK_GEN_ERR__SHIFT 0xc
+#define SDMA2_RAS_STATUS__WPTR_RPTR_ATOMIC_NACK_GEN_ERR__SHIFT 0xd
+#define SDMA2_RAS_STATUS__RB_FETCH_ECC_MASK 0x00000001L
+#define SDMA2_RAS_STATUS__IB_FETCH_ECC_MASK 0x00000002L
+#define SDMA2_RAS_STATUS__F32_DATA_ECC_MASK 0x00000004L
+#define SDMA2_RAS_STATUS__SEM_WPTR_ATOMIC_ECC_MASK 0x00000008L
+#define SDMA2_RAS_STATUS__COPY_DATA_ECC_MASK 0x00000010L
+#define SDMA2_RAS_STATUS__SRAM_ECC_MASK 0x00000020L
+#define SDMA2_RAS_STATUS__RB_FETCH_NACK_GEN_ERR_MASK 0x00000100L
+#define SDMA2_RAS_STATUS__IB_FETCH_NACK_GEN_ERR_MASK 0x00000200L
+#define SDMA2_RAS_STATUS__F32_DATA_NACK_GEN_ERR_MASK 0x00000400L
+#define SDMA2_RAS_STATUS__COPY_DATA_NACK_GEN_ERR_MASK 0x00000800L
+#define SDMA2_RAS_STATUS__WRRET_DATA_NACK_GEN_ERR_MASK 0x00001000L
+#define SDMA2_RAS_STATUS__WPTR_RPTR_ATOMIC_NACK_GEN_ERR_MASK 0x00002000L
+//SDMA2_CLK_STATUS
+#define SDMA2_CLK_STATUS__DYN_CLK__SHIFT 0x0
+#define SDMA2_CLK_STATUS__PTR_CLK__SHIFT 0x1
+#define SDMA2_CLK_STATUS__REG_CLK__SHIFT 0x2
+#define SDMA2_CLK_STATUS__F32_CLK__SHIFT 0x3
+#define SDMA2_CLK_STATUS__DYN_CLK_MASK 0x00000001L
+#define SDMA2_CLK_STATUS__PTR_CLK_MASK 0x00000002L
+#define SDMA2_CLK_STATUS__REG_CLK_MASK 0x00000004L
+#define SDMA2_CLK_STATUS__F32_CLK_MASK 0x00000008L
+//SDMA2_GFX_RB_CNTL
+#define SDMA2_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA2_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA2_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA2_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA2_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA2_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA2_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA2_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA2_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA2_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA2_GFX_RB_BASE
+#define SDMA2_GFX_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA2_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_GFX_RB_BASE_HI
+#define SDMA2_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA2_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA2_GFX_RB_RPTR
+#define SDMA2_GFX_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA2_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_GFX_RB_RPTR_HI
+#define SDMA2_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA2_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_GFX_RB_WPTR
+#define SDMA2_GFX_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA2_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_GFX_RB_WPTR_HI
+#define SDMA2_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA2_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_GFX_RB_WPTR_POLL_CNTL
+#define SDMA2_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA2_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA2_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA2_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA2_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA2_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA2_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA2_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA2_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA2_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA2_GFX_RB_RPTR_ADDR_HI
+#define SDMA2_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA2_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_GFX_RB_RPTR_ADDR_LO
+#define SDMA2_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA2_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA2_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA2_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA2_GFX_IB_CNTL
+#define SDMA2_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA2_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA2_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA2_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA2_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA2_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA2_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA2_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA2_GFX_IB_RPTR
+#define SDMA2_GFX_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA2_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA2_GFX_IB_OFFSET
+#define SDMA2_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA2_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA2_GFX_IB_BASE_LO
+#define SDMA2_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA2_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA2_GFX_IB_BASE_HI
+#define SDMA2_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA2_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_GFX_IB_SIZE
+#define SDMA2_GFX_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA2_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA2_GFX_SKIP_CNTL
+#define SDMA2_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA2_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA2_GFX_CONTEXT_STATUS
+#define SDMA2_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA2_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA2_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA2_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA2_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA2_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA2_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA2_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA2_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA2_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA2_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA2_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA2_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA2_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA2_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA2_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA2_GFX_DOORBELL
+#define SDMA2_GFX_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA2_GFX_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA2_GFX_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA2_GFX_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA2_GFX_CONTEXT_CNTL
+#define SDMA2_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
+#define SDMA2_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18
+#define SDMA2_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L
+#define SDMA2_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0x0F000000L
+//SDMA2_GFX_STATUS
+#define SDMA2_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA2_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA2_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA2_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA2_GFX_DOORBELL_LOG
+#define SDMA2_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA2_GFX_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA2_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA2_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA2_GFX_WATERMARK
+#define SDMA2_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA2_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA2_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA2_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA2_GFX_DOORBELL_OFFSET
+#define SDMA2_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA2_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA2_GFX_CSA_ADDR_LO
+#define SDMA2_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA2_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA2_GFX_CSA_ADDR_HI
+#define SDMA2_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA2_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_GFX_IB_SUB_REMAIN
+#define SDMA2_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA2_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA2_GFX_PREEMPT
+#define SDMA2_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA2_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA2_GFX_DUMMY_REG
+#define SDMA2_GFX_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA2_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA2_GFX_RB_WPTR_POLL_ADDR_HI
+#define SDMA2_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA2_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_GFX_RB_WPTR_POLL_ADDR_LO
+#define SDMA2_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA2_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA2_GFX_RB_AQL_CNTL
+#define SDMA2_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA2_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA2_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA2_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA2_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA2_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA2_GFX_MINOR_PTR_UPDATE
+#define SDMA2_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA2_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA2_GFX_MIDCMD_DATA0
+#define SDMA2_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA2_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA2_GFX_MIDCMD_DATA1
+#define SDMA2_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA2_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA2_GFX_MIDCMD_DATA2
+#define SDMA2_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA2_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA2_GFX_MIDCMD_DATA3
+#define SDMA2_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA2_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA2_GFX_MIDCMD_DATA4
+#define SDMA2_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA2_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA2_GFX_MIDCMD_DATA5
+#define SDMA2_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA2_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA2_GFX_MIDCMD_DATA6
+#define SDMA2_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA2_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA2_GFX_MIDCMD_DATA7
+#define SDMA2_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA2_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA2_GFX_MIDCMD_DATA8
+#define SDMA2_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA2_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA2_GFX_MIDCMD_DATA9
+#define SDMA2_GFX_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA2_GFX_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA2_GFX_MIDCMD_DATA10
+#define SDMA2_GFX_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA2_GFX_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA2_GFX_MIDCMD_CNTL
+#define SDMA2_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA2_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA2_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA2_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA2_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA2_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA2_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA2_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA2_PAGE_RB_CNTL
+#define SDMA2_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA2_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA2_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA2_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA2_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA2_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA2_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA2_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA2_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA2_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA2_PAGE_RB_BASE
+#define SDMA2_PAGE_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA2_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_PAGE_RB_BASE_HI
+#define SDMA2_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA2_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA2_PAGE_RB_RPTR
+#define SDMA2_PAGE_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA2_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_PAGE_RB_RPTR_HI
+#define SDMA2_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA2_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_PAGE_RB_WPTR
+#define SDMA2_PAGE_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA2_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_PAGE_RB_WPTR_HI
+#define SDMA2_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA2_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_PAGE_RB_WPTR_POLL_CNTL
+#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA2_PAGE_RB_RPTR_ADDR_HI
+#define SDMA2_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA2_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_PAGE_RB_RPTR_ADDR_LO
+#define SDMA2_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA2_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA2_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA2_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA2_PAGE_IB_CNTL
+#define SDMA2_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA2_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA2_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA2_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA2_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA2_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA2_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA2_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA2_PAGE_IB_RPTR
+#define SDMA2_PAGE_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA2_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA2_PAGE_IB_OFFSET
+#define SDMA2_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA2_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA2_PAGE_IB_BASE_LO
+#define SDMA2_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA2_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA2_PAGE_IB_BASE_HI
+#define SDMA2_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA2_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_PAGE_IB_SIZE
+#define SDMA2_PAGE_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA2_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA2_PAGE_SKIP_CNTL
+#define SDMA2_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA2_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA2_PAGE_CONTEXT_STATUS
+#define SDMA2_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA2_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA2_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA2_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA2_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA2_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA2_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA2_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA2_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA2_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA2_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA2_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA2_PAGE_DOORBELL
+#define SDMA2_PAGE_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA2_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA2_PAGE_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA2_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA2_PAGE_STATUS
+#define SDMA2_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA2_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA2_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA2_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA2_PAGE_DOORBELL_LOG
+#define SDMA2_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA2_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA2_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA2_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA2_PAGE_WATERMARK
+#define SDMA2_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA2_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA2_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA2_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA2_PAGE_DOORBELL_OFFSET
+#define SDMA2_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA2_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA2_PAGE_CSA_ADDR_LO
+#define SDMA2_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA2_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA2_PAGE_CSA_ADDR_HI
+#define SDMA2_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA2_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_PAGE_IB_SUB_REMAIN
+#define SDMA2_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA2_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA2_PAGE_PREEMPT
+#define SDMA2_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA2_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA2_PAGE_DUMMY_REG
+#define SDMA2_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA2_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA2_PAGE_RB_WPTR_POLL_ADDR_HI
+#define SDMA2_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA2_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_PAGE_RB_WPTR_POLL_ADDR_LO
+#define SDMA2_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA2_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA2_PAGE_RB_AQL_CNTL
+#define SDMA2_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA2_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA2_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA2_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA2_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA2_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA2_PAGE_MINOR_PTR_UPDATE
+#define SDMA2_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA2_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA2_PAGE_MIDCMD_DATA0
+#define SDMA2_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA2_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA2_PAGE_MIDCMD_DATA1
+#define SDMA2_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA2_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA2_PAGE_MIDCMD_DATA2
+#define SDMA2_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA2_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA2_PAGE_MIDCMD_DATA3
+#define SDMA2_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA2_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA2_PAGE_MIDCMD_DATA4
+#define SDMA2_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA2_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA2_PAGE_MIDCMD_DATA5
+#define SDMA2_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA2_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA2_PAGE_MIDCMD_DATA6
+#define SDMA2_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA2_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA2_PAGE_MIDCMD_DATA7
+#define SDMA2_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA2_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA2_PAGE_MIDCMD_DATA8
+#define SDMA2_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA2_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA2_PAGE_MIDCMD_DATA9
+#define SDMA2_PAGE_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA2_PAGE_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA2_PAGE_MIDCMD_DATA10
+#define SDMA2_PAGE_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA2_PAGE_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA2_PAGE_MIDCMD_CNTL
+#define SDMA2_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA2_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA2_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA2_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA2_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA2_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA2_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA2_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA2_RLC0_RB_CNTL
+#define SDMA2_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA2_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA2_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA2_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA2_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA2_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA2_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA2_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA2_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA2_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA2_RLC0_RB_BASE
+#define SDMA2_RLC0_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA2_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC0_RB_BASE_HI
+#define SDMA2_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA2_RLC0_RB_RPTR
+#define SDMA2_RLC0_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA2_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_RLC0_RB_RPTR_HI
+#define SDMA2_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA2_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_RLC0_RB_WPTR
+#define SDMA2_RLC0_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA2_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_RLC0_RB_WPTR_HI
+#define SDMA2_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA2_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_RLC0_RB_WPTR_POLL_CNTL
+#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA2_RLC0_RB_RPTR_ADDR_HI
+#define SDMA2_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC0_RB_RPTR_ADDR_LO
+#define SDMA2_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA2_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA2_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA2_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA2_RLC0_IB_CNTL
+#define SDMA2_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA2_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA2_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA2_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA2_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA2_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA2_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA2_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA2_RLC0_IB_RPTR
+#define SDMA2_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA2_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA2_RLC0_IB_OFFSET
+#define SDMA2_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA2_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA2_RLC0_IB_BASE_LO
+#define SDMA2_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA2_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA2_RLC0_IB_BASE_HI
+#define SDMA2_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC0_IB_SIZE
+#define SDMA2_RLC0_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA2_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA2_RLC0_SKIP_CNTL
+#define SDMA2_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA2_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA2_RLC0_CONTEXT_STATUS
+#define SDMA2_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA2_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA2_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA2_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA2_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA2_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA2_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA2_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA2_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA2_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA2_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA2_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA2_RLC0_DOORBELL
+#define SDMA2_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA2_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA2_RLC0_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA2_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA2_RLC0_STATUS
+#define SDMA2_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA2_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA2_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA2_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA2_RLC0_DOORBELL_LOG
+#define SDMA2_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA2_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA2_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA2_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA2_RLC0_WATERMARK
+#define SDMA2_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA2_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA2_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA2_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA2_RLC0_DOORBELL_OFFSET
+#define SDMA2_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA2_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA2_RLC0_CSA_ADDR_LO
+#define SDMA2_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA2_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA2_RLC0_CSA_ADDR_HI
+#define SDMA2_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC0_IB_SUB_REMAIN
+#define SDMA2_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA2_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA2_RLC0_PREEMPT
+#define SDMA2_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA2_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA2_RLC0_DUMMY_REG
+#define SDMA2_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA2_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA2_RLC0_RB_WPTR_POLL_ADDR_HI
+#define SDMA2_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC0_RB_WPTR_POLL_ADDR_LO
+#define SDMA2_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA2_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA2_RLC0_RB_AQL_CNTL
+#define SDMA2_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA2_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA2_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA2_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA2_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA2_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA2_RLC0_MINOR_PTR_UPDATE
+#define SDMA2_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA2_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA2_RLC0_MIDCMD_DATA0
+#define SDMA2_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA2_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA2_RLC0_MIDCMD_DATA1
+#define SDMA2_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA2_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA2_RLC0_MIDCMD_DATA2
+#define SDMA2_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA2_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA2_RLC0_MIDCMD_DATA3
+#define SDMA2_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA2_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA2_RLC0_MIDCMD_DATA4
+#define SDMA2_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA2_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA2_RLC0_MIDCMD_DATA5
+#define SDMA2_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA2_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA2_RLC0_MIDCMD_DATA6
+#define SDMA2_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA2_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA2_RLC0_MIDCMD_DATA7
+#define SDMA2_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA2_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA2_RLC0_MIDCMD_DATA8
+#define SDMA2_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA2_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA2_RLC0_MIDCMD_DATA9
+#define SDMA2_RLC0_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA2_RLC0_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA2_RLC0_MIDCMD_DATA10
+#define SDMA2_RLC0_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA2_RLC0_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA2_RLC0_MIDCMD_CNTL
+#define SDMA2_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA2_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA2_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA2_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA2_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA2_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA2_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA2_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA2_RLC1_RB_CNTL
+#define SDMA2_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA2_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA2_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA2_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA2_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA2_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA2_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA2_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA2_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA2_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA2_RLC1_RB_BASE
+#define SDMA2_RLC1_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA2_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC1_RB_BASE_HI
+#define SDMA2_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA2_RLC1_RB_RPTR
+#define SDMA2_RLC1_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA2_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_RLC1_RB_RPTR_HI
+#define SDMA2_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA2_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_RLC1_RB_WPTR
+#define SDMA2_RLC1_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA2_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_RLC1_RB_WPTR_HI
+#define SDMA2_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA2_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_RLC1_RB_WPTR_POLL_CNTL
+#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA2_RLC1_RB_RPTR_ADDR_HI
+#define SDMA2_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC1_RB_RPTR_ADDR_LO
+#define SDMA2_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA2_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA2_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA2_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA2_RLC1_IB_CNTL
+#define SDMA2_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA2_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA2_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA2_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA2_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA2_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA2_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA2_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA2_RLC1_IB_RPTR
+#define SDMA2_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA2_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA2_RLC1_IB_OFFSET
+#define SDMA2_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA2_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA2_RLC1_IB_BASE_LO
+#define SDMA2_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA2_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA2_RLC1_IB_BASE_HI
+#define SDMA2_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC1_IB_SIZE
+#define SDMA2_RLC1_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA2_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA2_RLC1_SKIP_CNTL
+#define SDMA2_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA2_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA2_RLC1_CONTEXT_STATUS
+#define SDMA2_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA2_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA2_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA2_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA2_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA2_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA2_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA2_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA2_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA2_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA2_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA2_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA2_RLC1_DOORBELL
+#define SDMA2_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA2_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA2_RLC1_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA2_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA2_RLC1_STATUS
+#define SDMA2_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA2_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA2_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA2_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA2_RLC1_DOORBELL_LOG
+#define SDMA2_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA2_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA2_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA2_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA2_RLC1_WATERMARK
+#define SDMA2_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA2_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA2_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA2_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA2_RLC1_DOORBELL_OFFSET
+#define SDMA2_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA2_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA2_RLC1_CSA_ADDR_LO
+#define SDMA2_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA2_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA2_RLC1_CSA_ADDR_HI
+#define SDMA2_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC1_IB_SUB_REMAIN
+#define SDMA2_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA2_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA2_RLC1_PREEMPT
+#define SDMA2_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA2_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA2_RLC1_DUMMY_REG
+#define SDMA2_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA2_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA2_RLC1_RB_WPTR_POLL_ADDR_HI
+#define SDMA2_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC1_RB_WPTR_POLL_ADDR_LO
+#define SDMA2_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA2_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA2_RLC1_RB_AQL_CNTL
+#define SDMA2_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA2_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA2_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA2_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA2_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA2_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA2_RLC1_MINOR_PTR_UPDATE
+#define SDMA2_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA2_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA2_RLC1_MIDCMD_DATA0
+#define SDMA2_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA2_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA2_RLC1_MIDCMD_DATA1
+#define SDMA2_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA2_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA2_RLC1_MIDCMD_DATA2
+#define SDMA2_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA2_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA2_RLC1_MIDCMD_DATA3
+#define SDMA2_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA2_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA2_RLC1_MIDCMD_DATA4
+#define SDMA2_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA2_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA2_RLC1_MIDCMD_DATA5
+#define SDMA2_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA2_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA2_RLC1_MIDCMD_DATA6
+#define SDMA2_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA2_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA2_RLC1_MIDCMD_DATA7
+#define SDMA2_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA2_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA2_RLC1_MIDCMD_DATA8
+#define SDMA2_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA2_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA2_RLC1_MIDCMD_DATA9
+#define SDMA2_RLC1_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA2_RLC1_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA2_RLC1_MIDCMD_DATA10
+#define SDMA2_RLC1_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA2_RLC1_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA2_RLC1_MIDCMD_CNTL
+#define SDMA2_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA2_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA2_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA2_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA2_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA2_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA2_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA2_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA2_RLC2_RB_CNTL
+#define SDMA2_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA2_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA2_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA2_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA2_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA2_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA2_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA2_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA2_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA2_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA2_RLC2_RB_BASE
+#define SDMA2_RLC2_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA2_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC2_RB_BASE_HI
+#define SDMA2_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA2_RLC2_RB_RPTR
+#define SDMA2_RLC2_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA2_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_RLC2_RB_RPTR_HI
+#define SDMA2_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA2_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_RLC2_RB_WPTR
+#define SDMA2_RLC2_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA2_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_RLC2_RB_WPTR_HI
+#define SDMA2_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA2_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_RLC2_RB_WPTR_POLL_CNTL
+#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA2_RLC2_RB_RPTR_ADDR_HI
+#define SDMA2_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC2_RB_RPTR_ADDR_LO
+#define SDMA2_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA2_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA2_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA2_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA2_RLC2_IB_CNTL
+#define SDMA2_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA2_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA2_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA2_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA2_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA2_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA2_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA2_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA2_RLC2_IB_RPTR
+#define SDMA2_RLC2_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA2_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA2_RLC2_IB_OFFSET
+#define SDMA2_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA2_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA2_RLC2_IB_BASE_LO
+#define SDMA2_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA2_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA2_RLC2_IB_BASE_HI
+#define SDMA2_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC2_IB_SIZE
+#define SDMA2_RLC2_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA2_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA2_RLC2_SKIP_CNTL
+#define SDMA2_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA2_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA2_RLC2_CONTEXT_STATUS
+#define SDMA2_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA2_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA2_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA2_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA2_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA2_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA2_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA2_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA2_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA2_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA2_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA2_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA2_RLC2_DOORBELL
+#define SDMA2_RLC2_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA2_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA2_RLC2_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA2_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA2_RLC2_STATUS
+#define SDMA2_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA2_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA2_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA2_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA2_RLC2_DOORBELL_LOG
+#define SDMA2_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA2_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA2_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA2_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA2_RLC2_WATERMARK
+#define SDMA2_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA2_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA2_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA2_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA2_RLC2_DOORBELL_OFFSET
+#define SDMA2_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA2_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA2_RLC2_CSA_ADDR_LO
+#define SDMA2_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA2_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA2_RLC2_CSA_ADDR_HI
+#define SDMA2_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC2_IB_SUB_REMAIN
+#define SDMA2_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA2_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA2_RLC2_PREEMPT
+#define SDMA2_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA2_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA2_RLC2_DUMMY_REG
+#define SDMA2_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA2_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA2_RLC2_RB_WPTR_POLL_ADDR_HI
+#define SDMA2_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC2_RB_WPTR_POLL_ADDR_LO
+#define SDMA2_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA2_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA2_RLC2_RB_AQL_CNTL
+#define SDMA2_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA2_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA2_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA2_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA2_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA2_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA2_RLC2_MINOR_PTR_UPDATE
+#define SDMA2_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA2_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA2_RLC2_MIDCMD_DATA0
+#define SDMA2_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA2_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA2_RLC2_MIDCMD_DATA1
+#define SDMA2_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA2_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA2_RLC2_MIDCMD_DATA2
+#define SDMA2_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA2_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA2_RLC2_MIDCMD_DATA3
+#define SDMA2_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA2_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA2_RLC2_MIDCMD_DATA4
+#define SDMA2_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA2_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA2_RLC2_MIDCMD_DATA5
+#define SDMA2_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA2_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA2_RLC2_MIDCMD_DATA6
+#define SDMA2_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA2_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA2_RLC2_MIDCMD_DATA7
+#define SDMA2_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA2_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA2_RLC2_MIDCMD_DATA8
+#define SDMA2_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA2_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA2_RLC2_MIDCMD_DATA9
+#define SDMA2_RLC2_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA2_RLC2_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA2_RLC2_MIDCMD_DATA10
+#define SDMA2_RLC2_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA2_RLC2_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA2_RLC2_MIDCMD_CNTL
+#define SDMA2_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA2_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA2_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA2_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA2_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA2_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA2_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA2_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA2_RLC3_RB_CNTL
+#define SDMA2_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA2_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA2_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA2_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA2_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA2_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA2_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA2_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA2_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA2_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA2_RLC3_RB_BASE
+#define SDMA2_RLC3_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA2_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC3_RB_BASE_HI
+#define SDMA2_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA2_RLC3_RB_RPTR
+#define SDMA2_RLC3_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA2_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_RLC3_RB_RPTR_HI
+#define SDMA2_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA2_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_RLC3_RB_WPTR
+#define SDMA2_RLC3_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA2_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_RLC3_RB_WPTR_HI
+#define SDMA2_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA2_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_RLC3_RB_WPTR_POLL_CNTL
+#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA2_RLC3_RB_RPTR_ADDR_HI
+#define SDMA2_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC3_RB_RPTR_ADDR_LO
+#define SDMA2_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA2_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA2_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA2_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA2_RLC3_IB_CNTL
+#define SDMA2_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA2_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA2_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA2_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA2_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA2_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA2_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA2_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA2_RLC3_IB_RPTR
+#define SDMA2_RLC3_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA2_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA2_RLC3_IB_OFFSET
+#define SDMA2_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA2_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA2_RLC3_IB_BASE_LO
+#define SDMA2_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA2_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA2_RLC3_IB_BASE_HI
+#define SDMA2_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC3_IB_SIZE
+#define SDMA2_RLC3_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA2_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA2_RLC3_SKIP_CNTL
+#define SDMA2_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA2_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA2_RLC3_CONTEXT_STATUS
+#define SDMA2_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA2_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA2_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA2_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA2_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA2_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA2_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA2_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA2_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA2_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA2_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA2_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA2_RLC3_DOORBELL
+#define SDMA2_RLC3_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA2_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA2_RLC3_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA2_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA2_RLC3_STATUS
+#define SDMA2_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA2_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA2_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA2_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA2_RLC3_DOORBELL_LOG
+#define SDMA2_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA2_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA2_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA2_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA2_RLC3_WATERMARK
+#define SDMA2_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA2_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA2_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA2_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA2_RLC3_DOORBELL_OFFSET
+#define SDMA2_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA2_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA2_RLC3_CSA_ADDR_LO
+#define SDMA2_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA2_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA2_RLC3_CSA_ADDR_HI
+#define SDMA2_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC3_IB_SUB_REMAIN
+#define SDMA2_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA2_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA2_RLC3_PREEMPT
+#define SDMA2_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA2_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA2_RLC3_DUMMY_REG
+#define SDMA2_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA2_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA2_RLC3_RB_WPTR_POLL_ADDR_HI
+#define SDMA2_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC3_RB_WPTR_POLL_ADDR_LO
+#define SDMA2_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA2_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA2_RLC3_RB_AQL_CNTL
+#define SDMA2_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA2_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA2_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA2_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA2_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA2_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA2_RLC3_MINOR_PTR_UPDATE
+#define SDMA2_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA2_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA2_RLC3_MIDCMD_DATA0
+#define SDMA2_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA2_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA2_RLC3_MIDCMD_DATA1
+#define SDMA2_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA2_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA2_RLC3_MIDCMD_DATA2
+#define SDMA2_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA2_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA2_RLC3_MIDCMD_DATA3
+#define SDMA2_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA2_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA2_RLC3_MIDCMD_DATA4
+#define SDMA2_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA2_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA2_RLC3_MIDCMD_DATA5
+#define SDMA2_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA2_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA2_RLC3_MIDCMD_DATA6
+#define SDMA2_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA2_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA2_RLC3_MIDCMD_DATA7
+#define SDMA2_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA2_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA2_RLC3_MIDCMD_DATA8
+#define SDMA2_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA2_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA2_RLC3_MIDCMD_DATA9
+#define SDMA2_RLC3_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA2_RLC3_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA2_RLC3_MIDCMD_DATA10
+#define SDMA2_RLC3_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA2_RLC3_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA2_RLC3_MIDCMD_CNTL
+#define SDMA2_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA2_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA2_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA2_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA2_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA2_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA2_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA2_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA2_RLC4_RB_CNTL
+#define SDMA2_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA2_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA2_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA2_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA2_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA2_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA2_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA2_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA2_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA2_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA2_RLC4_RB_BASE
+#define SDMA2_RLC4_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA2_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC4_RB_BASE_HI
+#define SDMA2_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA2_RLC4_RB_RPTR
+#define SDMA2_RLC4_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA2_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_RLC4_RB_RPTR_HI
+#define SDMA2_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA2_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_RLC4_RB_WPTR
+#define SDMA2_RLC4_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA2_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_RLC4_RB_WPTR_HI
+#define SDMA2_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA2_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_RLC4_RB_WPTR_POLL_CNTL
+#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA2_RLC4_RB_RPTR_ADDR_HI
+#define SDMA2_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC4_RB_RPTR_ADDR_LO
+#define SDMA2_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA2_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA2_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA2_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA2_RLC4_IB_CNTL
+#define SDMA2_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA2_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA2_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA2_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA2_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA2_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA2_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA2_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA2_RLC4_IB_RPTR
+#define SDMA2_RLC4_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA2_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA2_RLC4_IB_OFFSET
+#define SDMA2_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA2_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA2_RLC4_IB_BASE_LO
+#define SDMA2_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA2_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA2_RLC4_IB_BASE_HI
+#define SDMA2_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC4_IB_SIZE
+#define SDMA2_RLC4_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA2_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA2_RLC4_SKIP_CNTL
+#define SDMA2_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA2_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA2_RLC4_CONTEXT_STATUS
+#define SDMA2_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA2_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA2_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA2_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA2_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA2_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA2_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA2_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA2_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA2_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA2_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA2_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA2_RLC4_DOORBELL
+#define SDMA2_RLC4_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA2_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA2_RLC4_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA2_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA2_RLC4_STATUS
+#define SDMA2_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA2_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA2_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA2_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA2_RLC4_DOORBELL_LOG
+#define SDMA2_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA2_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA2_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA2_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA2_RLC4_WATERMARK
+#define SDMA2_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA2_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA2_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA2_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA2_RLC4_DOORBELL_OFFSET
+#define SDMA2_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA2_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA2_RLC4_CSA_ADDR_LO
+#define SDMA2_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA2_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA2_RLC4_CSA_ADDR_HI
+#define SDMA2_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC4_IB_SUB_REMAIN
+#define SDMA2_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA2_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA2_RLC4_PREEMPT
+#define SDMA2_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA2_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA2_RLC4_DUMMY_REG
+#define SDMA2_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA2_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA2_RLC4_RB_WPTR_POLL_ADDR_HI
+#define SDMA2_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC4_RB_WPTR_POLL_ADDR_LO
+#define SDMA2_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA2_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA2_RLC4_RB_AQL_CNTL
+#define SDMA2_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA2_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA2_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA2_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA2_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA2_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA2_RLC4_MINOR_PTR_UPDATE
+#define SDMA2_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA2_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA2_RLC4_MIDCMD_DATA0
+#define SDMA2_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA2_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA2_RLC4_MIDCMD_DATA1
+#define SDMA2_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA2_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA2_RLC4_MIDCMD_DATA2
+#define SDMA2_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA2_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA2_RLC4_MIDCMD_DATA3
+#define SDMA2_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA2_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA2_RLC4_MIDCMD_DATA4
+#define SDMA2_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA2_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA2_RLC4_MIDCMD_DATA5
+#define SDMA2_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA2_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA2_RLC4_MIDCMD_DATA6
+#define SDMA2_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA2_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA2_RLC4_MIDCMD_DATA7
+#define SDMA2_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA2_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA2_RLC4_MIDCMD_DATA8
+#define SDMA2_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA2_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA2_RLC4_MIDCMD_DATA9
+#define SDMA2_RLC4_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA2_RLC4_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA2_RLC4_MIDCMD_DATA10
+#define SDMA2_RLC4_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA2_RLC4_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA2_RLC4_MIDCMD_CNTL
+#define SDMA2_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA2_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA2_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA2_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA2_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA2_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA2_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA2_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA2_RLC5_RB_CNTL
+#define SDMA2_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA2_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA2_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA2_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA2_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA2_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA2_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA2_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA2_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA2_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA2_RLC5_RB_BASE
+#define SDMA2_RLC5_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA2_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC5_RB_BASE_HI
+#define SDMA2_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA2_RLC5_RB_RPTR
+#define SDMA2_RLC5_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA2_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_RLC5_RB_RPTR_HI
+#define SDMA2_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA2_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_RLC5_RB_WPTR
+#define SDMA2_RLC5_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA2_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_RLC5_RB_WPTR_HI
+#define SDMA2_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA2_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_RLC5_RB_WPTR_POLL_CNTL
+#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA2_RLC5_RB_RPTR_ADDR_HI
+#define SDMA2_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC5_RB_RPTR_ADDR_LO
+#define SDMA2_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA2_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA2_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA2_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA2_RLC5_IB_CNTL
+#define SDMA2_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA2_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA2_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA2_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA2_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA2_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA2_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA2_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA2_RLC5_IB_RPTR
+#define SDMA2_RLC5_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA2_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA2_RLC5_IB_OFFSET
+#define SDMA2_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA2_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA2_RLC5_IB_BASE_LO
+#define SDMA2_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA2_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA2_RLC5_IB_BASE_HI
+#define SDMA2_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC5_IB_SIZE
+#define SDMA2_RLC5_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA2_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA2_RLC5_SKIP_CNTL
+#define SDMA2_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA2_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA2_RLC5_CONTEXT_STATUS
+#define SDMA2_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA2_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA2_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA2_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA2_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA2_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA2_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA2_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA2_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA2_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA2_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA2_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA2_RLC5_DOORBELL
+#define SDMA2_RLC5_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA2_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA2_RLC5_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA2_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA2_RLC5_STATUS
+#define SDMA2_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA2_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA2_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA2_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA2_RLC5_DOORBELL_LOG
+#define SDMA2_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA2_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA2_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA2_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA2_RLC5_WATERMARK
+#define SDMA2_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA2_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA2_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA2_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA2_RLC5_DOORBELL_OFFSET
+#define SDMA2_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA2_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA2_RLC5_CSA_ADDR_LO
+#define SDMA2_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA2_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA2_RLC5_CSA_ADDR_HI
+#define SDMA2_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC5_IB_SUB_REMAIN
+#define SDMA2_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA2_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA2_RLC5_PREEMPT
+#define SDMA2_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA2_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA2_RLC5_DUMMY_REG
+#define SDMA2_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA2_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA2_RLC5_RB_WPTR_POLL_ADDR_HI
+#define SDMA2_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC5_RB_WPTR_POLL_ADDR_LO
+#define SDMA2_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA2_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA2_RLC5_RB_AQL_CNTL
+#define SDMA2_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA2_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA2_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA2_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA2_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA2_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA2_RLC5_MINOR_PTR_UPDATE
+#define SDMA2_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA2_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA2_RLC5_MIDCMD_DATA0
+#define SDMA2_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA2_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA2_RLC5_MIDCMD_DATA1
+#define SDMA2_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA2_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA2_RLC5_MIDCMD_DATA2
+#define SDMA2_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA2_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA2_RLC5_MIDCMD_DATA3
+#define SDMA2_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA2_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA2_RLC5_MIDCMD_DATA4
+#define SDMA2_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA2_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA2_RLC5_MIDCMD_DATA5
+#define SDMA2_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA2_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA2_RLC5_MIDCMD_DATA6
+#define SDMA2_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA2_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA2_RLC5_MIDCMD_DATA7
+#define SDMA2_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA2_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA2_RLC5_MIDCMD_DATA8
+#define SDMA2_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA2_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA2_RLC5_MIDCMD_DATA9
+#define SDMA2_RLC5_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA2_RLC5_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA2_RLC5_MIDCMD_DATA10
+#define SDMA2_RLC5_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA2_RLC5_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA2_RLC5_MIDCMD_CNTL
+#define SDMA2_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA2_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA2_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA2_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA2_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA2_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA2_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA2_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA2_RLC6_RB_CNTL
+#define SDMA2_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA2_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA2_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA2_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA2_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA2_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA2_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA2_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA2_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA2_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA2_RLC6_RB_BASE
+#define SDMA2_RLC6_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA2_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC6_RB_BASE_HI
+#define SDMA2_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA2_RLC6_RB_RPTR
+#define SDMA2_RLC6_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA2_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_RLC6_RB_RPTR_HI
+#define SDMA2_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA2_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_RLC6_RB_WPTR
+#define SDMA2_RLC6_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA2_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_RLC6_RB_WPTR_HI
+#define SDMA2_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA2_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_RLC6_RB_WPTR_POLL_CNTL
+#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA2_RLC6_RB_RPTR_ADDR_HI
+#define SDMA2_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC6_RB_RPTR_ADDR_LO
+#define SDMA2_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA2_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA2_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA2_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA2_RLC6_IB_CNTL
+#define SDMA2_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA2_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA2_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA2_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA2_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA2_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA2_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA2_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA2_RLC6_IB_RPTR
+#define SDMA2_RLC6_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA2_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA2_RLC6_IB_OFFSET
+#define SDMA2_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA2_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA2_RLC6_IB_BASE_LO
+#define SDMA2_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA2_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA2_RLC6_IB_BASE_HI
+#define SDMA2_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC6_IB_SIZE
+#define SDMA2_RLC6_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA2_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA2_RLC6_SKIP_CNTL
+#define SDMA2_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA2_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA2_RLC6_CONTEXT_STATUS
+#define SDMA2_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA2_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA2_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA2_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA2_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA2_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA2_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA2_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA2_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA2_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA2_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA2_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA2_RLC6_DOORBELL
+#define SDMA2_RLC6_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA2_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA2_RLC6_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA2_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA2_RLC6_STATUS
+#define SDMA2_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA2_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA2_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA2_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA2_RLC6_DOORBELL_LOG
+#define SDMA2_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA2_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA2_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA2_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA2_RLC6_WATERMARK
+#define SDMA2_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA2_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA2_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA2_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA2_RLC6_DOORBELL_OFFSET
+#define SDMA2_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA2_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA2_RLC6_CSA_ADDR_LO
+#define SDMA2_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA2_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA2_RLC6_CSA_ADDR_HI
+#define SDMA2_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC6_IB_SUB_REMAIN
+#define SDMA2_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA2_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA2_RLC6_PREEMPT
+#define SDMA2_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA2_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA2_RLC6_DUMMY_REG
+#define SDMA2_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA2_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA2_RLC6_RB_WPTR_POLL_ADDR_HI
+#define SDMA2_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC6_RB_WPTR_POLL_ADDR_LO
+#define SDMA2_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA2_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA2_RLC6_RB_AQL_CNTL
+#define SDMA2_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA2_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA2_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA2_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA2_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA2_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA2_RLC6_MINOR_PTR_UPDATE
+#define SDMA2_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA2_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA2_RLC6_MIDCMD_DATA0
+#define SDMA2_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA2_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA2_RLC6_MIDCMD_DATA1
+#define SDMA2_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA2_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA2_RLC6_MIDCMD_DATA2
+#define SDMA2_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA2_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA2_RLC6_MIDCMD_DATA3
+#define SDMA2_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA2_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA2_RLC6_MIDCMD_DATA4
+#define SDMA2_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA2_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA2_RLC6_MIDCMD_DATA5
+#define SDMA2_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA2_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA2_RLC6_MIDCMD_DATA6
+#define SDMA2_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA2_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA2_RLC6_MIDCMD_DATA7
+#define SDMA2_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA2_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA2_RLC6_MIDCMD_DATA8
+#define SDMA2_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA2_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA2_RLC6_MIDCMD_DATA9
+#define SDMA2_RLC6_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA2_RLC6_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA2_RLC6_MIDCMD_DATA10
+#define SDMA2_RLC6_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA2_RLC6_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA2_RLC6_MIDCMD_CNTL
+#define SDMA2_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA2_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA2_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA2_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA2_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA2_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA2_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA2_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA2_RLC7_RB_CNTL
+#define SDMA2_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA2_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA2_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA2_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA2_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA2_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA2_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA2_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA2_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA2_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA2_RLC7_RB_BASE
+#define SDMA2_RLC7_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA2_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC7_RB_BASE_HI
+#define SDMA2_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA2_RLC7_RB_RPTR
+#define SDMA2_RLC7_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA2_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_RLC7_RB_RPTR_HI
+#define SDMA2_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA2_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_RLC7_RB_WPTR
+#define SDMA2_RLC7_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA2_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_RLC7_RB_WPTR_HI
+#define SDMA2_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA2_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA2_RLC7_RB_WPTR_POLL_CNTL
+#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA2_RLC7_RB_RPTR_ADDR_HI
+#define SDMA2_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC7_RB_RPTR_ADDR_LO
+#define SDMA2_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA2_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA2_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA2_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA2_RLC7_IB_CNTL
+#define SDMA2_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA2_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA2_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA2_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA2_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA2_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA2_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA2_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA2_RLC7_IB_RPTR
+#define SDMA2_RLC7_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA2_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA2_RLC7_IB_OFFSET
+#define SDMA2_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA2_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA2_RLC7_IB_BASE_LO
+#define SDMA2_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA2_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA2_RLC7_IB_BASE_HI
+#define SDMA2_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC7_IB_SIZE
+#define SDMA2_RLC7_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA2_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA2_RLC7_SKIP_CNTL
+#define SDMA2_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA2_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA2_RLC7_CONTEXT_STATUS
+#define SDMA2_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA2_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA2_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA2_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA2_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA2_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA2_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA2_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA2_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA2_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA2_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA2_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA2_RLC7_DOORBELL
+#define SDMA2_RLC7_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA2_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA2_RLC7_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA2_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA2_RLC7_STATUS
+#define SDMA2_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA2_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA2_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA2_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA2_RLC7_DOORBELL_LOG
+#define SDMA2_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA2_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA2_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA2_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA2_RLC7_WATERMARK
+#define SDMA2_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA2_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA2_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA2_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA2_RLC7_DOORBELL_OFFSET
+#define SDMA2_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA2_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA2_RLC7_CSA_ADDR_LO
+#define SDMA2_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA2_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA2_RLC7_CSA_ADDR_HI
+#define SDMA2_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC7_IB_SUB_REMAIN
+#define SDMA2_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA2_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA2_RLC7_PREEMPT
+#define SDMA2_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA2_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA2_RLC7_DUMMY_REG
+#define SDMA2_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA2_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA2_RLC7_RB_WPTR_POLL_ADDR_HI
+#define SDMA2_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA2_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA2_RLC7_RB_WPTR_POLL_ADDR_LO
+#define SDMA2_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA2_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA2_RLC7_RB_AQL_CNTL
+#define SDMA2_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA2_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA2_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA2_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA2_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA2_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA2_RLC7_MINOR_PTR_UPDATE
+#define SDMA2_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA2_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA2_RLC7_MIDCMD_DATA0
+#define SDMA2_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA2_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA2_RLC7_MIDCMD_DATA1
+#define SDMA2_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA2_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA2_RLC7_MIDCMD_DATA2
+#define SDMA2_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA2_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA2_RLC7_MIDCMD_DATA3
+#define SDMA2_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA2_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA2_RLC7_MIDCMD_DATA4
+#define SDMA2_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA2_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA2_RLC7_MIDCMD_DATA5
+#define SDMA2_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA2_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA2_RLC7_MIDCMD_DATA6
+#define SDMA2_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA2_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA2_RLC7_MIDCMD_DATA7
+#define SDMA2_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA2_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA2_RLC7_MIDCMD_DATA8
+#define SDMA2_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA2_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA2_RLC7_MIDCMD_DATA9
+#define SDMA2_RLC7_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA2_RLC7_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA2_RLC7_MIDCMD_DATA10
+#define SDMA2_RLC7_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA2_RLC7_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA2_RLC7_MIDCMD_CNTL
+#define SDMA2_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA2_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA2_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA2_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA2_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA2_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA2_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA2_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+
+
+// addressBlock: sdma0_sdma3dec
+//SDMA3_UCODE_ADDR
+#define SDMA3_UCODE_ADDR__VALUE__SHIFT 0x0
+#define SDMA3_UCODE_ADDR__VALUE_MASK 0x00003FFFL
+//SDMA3_UCODE_DATA
+#define SDMA3_UCODE_DATA__VALUE__SHIFT 0x0
+#define SDMA3_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL
+//SDMA3_VF_ENABLE
+#define SDMA3_VF_ENABLE__VF_ENABLE__SHIFT 0x0
+#define SDMA3_VF_ENABLE__VF_ENABLE_MASK 0x00000001L
+#define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_ADDR__SHIFT 0x0
+#define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_DATA__SHIFT 0x1
+#define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_ADDR_MASK 0x00000001L
+#define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_DATA_MASK 0x00000002L
+//SDMA3_CONTEXT_GROUP_BOUNDARY
+#define SDMA3_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0
+#define SDMA3_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL
+//SDMA3_POWER_CNTL
+#define SDMA3_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0
+#define SDMA3_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1
+#define SDMA3_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2
+#define SDMA3_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3
+#define SDMA3_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
+#define SDMA3_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9
+#define SDMA3_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
+#define SDMA3_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb
+#define SDMA3_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc
+#define SDMA3_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a
+#define SDMA3_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L
+#define SDMA3_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L
+#define SDMA3_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L
+#define SDMA3_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L
+#define SDMA3_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L
+#define SDMA3_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L
+#define SDMA3_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L
+#define SDMA3_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L
+#define SDMA3_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L
+#define SDMA3_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
+//SDMA3_CLK_CTRL
+#define SDMA3_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define SDMA3_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define SDMA3_CLK_CTRL__RESERVED__SHIFT 0xc
+#define SDMA3_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define SDMA3_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define SDMA3_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define SDMA3_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define SDMA3_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define SDMA3_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define SDMA3_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define SDMA3_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define SDMA3_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define SDMA3_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define SDMA3_CLK_CTRL__RESERVED_MASK 0x00FFF000L
+#define SDMA3_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define SDMA3_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define SDMA3_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define SDMA3_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define SDMA3_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define SDMA3_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define SDMA3_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define SDMA3_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//SDMA3_CNTL
+#define SDMA3_CNTL__TRAP_ENABLE__SHIFT 0x0
+#define SDMA3_CNTL__UTC_L1_ENABLE__SHIFT 0x1
+#define SDMA3_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
+#define SDMA3_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
+#define SDMA3_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
+#define SDMA3_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5
+#define SDMA3_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x6
+#define SDMA3_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11
+#define SDMA3_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
+#define SDMA3_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
+#define SDMA3_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
+#define SDMA3_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e
+#define SDMA3_CNTL__TRAP_ENABLE_MASK 0x00000001L
+#define SDMA3_CNTL__UTC_L1_ENABLE_MASK 0x00000002L
+#define SDMA3_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L
+#define SDMA3_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L
+#define SDMA3_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA3_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L
+#define SDMA3_CNTL__MIDCMD_EXPIRE_ENABLE_MASK 0x00000040L
+#define SDMA3_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L
+#define SDMA3_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L
+#define SDMA3_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L
+#define SDMA3_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L
+#define SDMA3_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L
+//SDMA3_CHICKEN_BITS
+#define SDMA3_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
+#define SDMA3_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
+#define SDMA3_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
+#define SDMA3_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8
+#define SDMA3_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
+#define SDMA3_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
+#define SDMA3_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11
+#define SDMA3_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
+#define SDMA3_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
+#define SDMA3_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19
+#define SDMA3_CHICKEN_BITS__SRAM_FGCG_ENABLE__SHIFT 0x1a
+#define SDMA3_CHICKEN_BITS__RESERVED__SHIFT 0x1b
+#define SDMA3_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L
+#define SDMA3_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L
+#define SDMA3_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L
+#define SDMA3_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L
+#define SDMA3_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L
+#define SDMA3_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L
+#define SDMA3_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L
+#define SDMA3_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L
+#define SDMA3_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L
+#define SDMA3_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L
+#define SDMA3_CHICKEN_BITS__SRAM_FGCG_ENABLE_MASK 0x04000000L
+#define SDMA3_CHICKEN_BITS__RESERVED_MASK 0xF8000000L
+//SDMA3_GB_ADDR_CONFIG
+#define SDMA3_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define SDMA3_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define SDMA3_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define SDMA3_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
+#define SDMA3_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
+#define SDMA3_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
+#define SDMA3_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define SDMA3_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
+#define SDMA3_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
+#define SDMA3_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
+//SDMA3_GB_ADDR_CONFIG_READ
+#define SDMA3_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0
+#define SDMA3_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define SDMA3_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define SDMA3_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc
+#define SDMA3_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13
+#define SDMA3_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L
+#define SDMA3_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define SDMA3_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
+#define SDMA3_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L
+#define SDMA3_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L
+//SDMA3_RB_RPTR_FETCH_HI
+#define SDMA3_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0
+#define SDMA3_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_SEM_WAIT_FAIL_TIMER_CNTL
+#define SDMA3_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
+#define SDMA3_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL
+//SDMA3_RB_RPTR_FETCH
+#define SDMA3_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
+#define SDMA3_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL
+//SDMA3_IB_OFFSET_FETCH
+#define SDMA3_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
+#define SDMA3_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL
+//SDMA3_PROGRAM
+#define SDMA3_PROGRAM__STREAM__SHIFT 0x0
+#define SDMA3_PROGRAM__STREAM_MASK 0xFFFFFFFFL
+//SDMA3_STATUS_REG
+#define SDMA3_STATUS_REG__IDLE__SHIFT 0x0
+#define SDMA3_STATUS_REG__REG_IDLE__SHIFT 0x1
+#define SDMA3_STATUS_REG__RB_EMPTY__SHIFT 0x2
+#define SDMA3_STATUS_REG__RB_FULL__SHIFT 0x3
+#define SDMA3_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
+#define SDMA3_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
+#define SDMA3_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
+#define SDMA3_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
+#define SDMA3_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
+#define SDMA3_STATUS_REG__INSIDE_IB__SHIFT 0x9
+#define SDMA3_STATUS_REG__EX_IDLE__SHIFT 0xa
+#define SDMA3_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
+#define SDMA3_STATUS_REG__PACKET_READY__SHIFT 0xc
+#define SDMA3_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
+#define SDMA3_STATUS_REG__SRBM_IDLE__SHIFT 0xe
+#define SDMA3_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
+#define SDMA3_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10
+#define SDMA3_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
+#define SDMA3_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
+#define SDMA3_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
+#define SDMA3_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14
+#define SDMA3_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
+#define SDMA3_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
+#define SDMA3_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
+#define SDMA3_STATUS_REG__SEM_IDLE__SHIFT 0x1a
+#define SDMA3_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
+#define SDMA3_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
+#define SDMA3_STATUS_REG__INT_IDLE__SHIFT 0x1e
+#define SDMA3_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
+#define SDMA3_STATUS_REG__IDLE_MASK 0x00000001L
+#define SDMA3_STATUS_REG__REG_IDLE_MASK 0x00000002L
+#define SDMA3_STATUS_REG__RB_EMPTY_MASK 0x00000004L
+#define SDMA3_STATUS_REG__RB_FULL_MASK 0x00000008L
+#define SDMA3_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L
+#define SDMA3_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L
+#define SDMA3_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L
+#define SDMA3_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L
+#define SDMA3_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L
+#define SDMA3_STATUS_REG__INSIDE_IB_MASK 0x00000200L
+#define SDMA3_STATUS_REG__EX_IDLE_MASK 0x00000400L
+#define SDMA3_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L
+#define SDMA3_STATUS_REG__PACKET_READY_MASK 0x00001000L
+#define SDMA3_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L
+#define SDMA3_STATUS_REG__SRBM_IDLE_MASK 0x00004000L
+#define SDMA3_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L
+#define SDMA3_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L
+#define SDMA3_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L
+#define SDMA3_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L
+#define SDMA3_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L
+#define SDMA3_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L
+#define SDMA3_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L
+#define SDMA3_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L
+#define SDMA3_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L
+#define SDMA3_STATUS_REG__SEM_IDLE_MASK 0x04000000L
+#define SDMA3_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L
+#define SDMA3_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L
+#define SDMA3_STATUS_REG__INT_IDLE_MASK 0x40000000L
+#define SDMA3_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L
+//SDMA3_STATUS1_REG
+#define SDMA3_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
+#define SDMA3_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
+#define SDMA3_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
+#define SDMA3_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
+#define SDMA3_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
+#define SDMA3_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
+#define SDMA3_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
+#define SDMA3_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9
+#define SDMA3_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
+#define SDMA3_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
+#define SDMA3_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
+#define SDMA3_STATUS1_REG__EX_START__SHIFT 0xf
+#define SDMA3_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
+#define SDMA3_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
+#define SDMA3_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L
+#define SDMA3_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L
+#define SDMA3_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L
+#define SDMA3_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L
+#define SDMA3_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L
+#define SDMA3_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L
+#define SDMA3_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L
+#define SDMA3_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L
+#define SDMA3_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L
+#define SDMA3_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L
+#define SDMA3_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L
+#define SDMA3_STATUS1_REG__EX_START_MASK 0x00008000L
+#define SDMA3_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L
+#define SDMA3_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L
+//SDMA3_RD_BURST_CNTL
+#define SDMA3_RD_BURST_CNTL__RD_BURST__SHIFT 0x0
+#define SDMA3_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2
+#define SDMA3_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L
+#define SDMA3_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL
+//SDMA3_HBM_PAGE_CONFIG
+#define SDMA3_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0
+#define SDMA3_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L
+//SDMA3_UCODE_CHECKSUM
+#define SDMA3_UCODE_CHECKSUM__DATA__SHIFT 0x0
+#define SDMA3_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL
+//SDMA3_F32_CNTL
+#define SDMA3_F32_CNTL__HALT__SHIFT 0x0
+#define SDMA3_F32_CNTL__STEP__SHIFT 0x1
+#define SDMA3_F32_CNTL__RESET__SHIFT 0x8
+#define SDMA3_F32_CNTL__HALT_MASK 0x00000001L
+#define SDMA3_F32_CNTL__STEP_MASK 0x00000002L
+#define SDMA3_F32_CNTL__RESET_MASK 0x00000100L
+//SDMA3_FREEZE
+#define SDMA3_FREEZE__PREEMPT__SHIFT 0x0
+#define SDMA3_FREEZE__FREEZE__SHIFT 0x4
+#define SDMA3_FREEZE__FROZEN__SHIFT 0x5
+#define SDMA3_FREEZE__F32_FREEZE__SHIFT 0x6
+#define SDMA3_FREEZE__PREEMPT_MASK 0x00000001L
+#define SDMA3_FREEZE__FREEZE_MASK 0x00000010L
+#define SDMA3_FREEZE__FROZEN_MASK 0x00000020L
+#define SDMA3_FREEZE__F32_FREEZE_MASK 0x00000040L
+//SDMA3_PHASE0_QUANTUM
+#define SDMA3_PHASE0_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA3_PHASE0_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA3_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA3_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL
+#define SDMA3_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L
+#define SDMA3_PHASE0_QUANTUM__PREFER_MASK 0x40000000L
+//SDMA3_PHASE1_QUANTUM
+#define SDMA3_PHASE1_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA3_PHASE1_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA3_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA3_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL
+#define SDMA3_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L
+#define SDMA3_PHASE1_QUANTUM__PREFER_MASK 0x40000000L
+//CC_SDMA3_EDC_CONFIG
+#define CC_SDMA3_EDC_CONFIG__DIS_EDC__SHIFT 0x1
+#define CC_SDMA3_EDC_CONFIG__DIS_EDC_MASK 0x00000002L
+//SDMA3_BA_THRESHOLD
+#define SDMA3_BA_THRESHOLD__READ_THRES__SHIFT 0x0
+#define SDMA3_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10
+#define SDMA3_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL
+#define SDMA3_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L
+//SDMA3_ID
+#define SDMA3_ID__DEVICE_ID__SHIFT 0x0
+#define SDMA3_ID__DEVICE_ID_MASK 0x000000FFL
+//SDMA3_VERSION
+#define SDMA3_VERSION__MINVER__SHIFT 0x0
+#define SDMA3_VERSION__MAJVER__SHIFT 0x8
+#define SDMA3_VERSION__REV__SHIFT 0x10
+#define SDMA3_VERSION__MINVER_MASK 0x0000007FL
+#define SDMA3_VERSION__MAJVER_MASK 0x00007F00L
+#define SDMA3_VERSION__REV_MASK 0x003F0000L
+//SDMA3_EDC_COUNTER
+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x0
+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x2
+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x4
+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0x6
+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0x8
+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xa
+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xc
+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe
+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0x10
+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x12
+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x14
+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x16
+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x18
+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x1a
+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x1c
+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x1e
+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000003L
+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x0000000CL
+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000030L
+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x000000C0L
+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000300L
+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00000C00L
+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00003000L
+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x0000C000L
+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00030000L
+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x000C0000L
+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00300000L
+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00C00000L
+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x03000000L
+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x0C000000L
+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x30000000L
+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0xC0000000L
+//SDMA3_EDC_COUNTER2
+#define SDMA3_EDC_COUNTER2__SDMA_UCODE_BUF_SED__SHIFT 0x0
+#define SDMA3_EDC_COUNTER2__SDMA_RB_CMD_BUF_SED__SHIFT 0x2
+#define SDMA3_EDC_COUNTER2__SDMA_IB_CMD_BUF_SED__SHIFT 0x4
+#define SDMA3_EDC_COUNTER2__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x6
+#define SDMA3_EDC_COUNTER2__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x8
+#define SDMA3_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED__SHIFT 0xa
+#define SDMA3_EDC_COUNTER2__SDMA_DATA_LUT_FIFO_SED__SHIFT 0xc
+#define SDMA3_EDC_COUNTER2__SDMA_SPLIT_DATA_BUF_SED__SHIFT 0xe
+#define SDMA3_EDC_COUNTER2__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10
+#define SDMA3_EDC_COUNTER2__SDMA_MC_RDRET_BUF_SED__SHIFT 0x12
+#define SDMA3_EDC_COUNTER2__SDMA_UCODE_BUF_SED_MASK 0x00000003L
+#define SDMA3_EDC_COUNTER2__SDMA_RB_CMD_BUF_SED_MASK 0x0000000CL
+#define SDMA3_EDC_COUNTER2__SDMA_IB_CMD_BUF_SED_MASK 0x00000030L
+#define SDMA3_EDC_COUNTER2__SDMA_UTCL1_RD_FIFO_SED_MASK 0x000000C0L
+#define SDMA3_EDC_COUNTER2__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000300L
+#define SDMA3_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED_MASK 0x00000C00L
+#define SDMA3_EDC_COUNTER2__SDMA_DATA_LUT_FIFO_SED_MASK 0x00003000L
+#define SDMA3_EDC_COUNTER2__SDMA_SPLIT_DATA_BUF_SED_MASK 0x0000C000L
+#define SDMA3_EDC_COUNTER2__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00030000L
+#define SDMA3_EDC_COUNTER2__SDMA_MC_RDRET_BUF_SED_MASK 0x000C0000L
+//SDMA3_STATUS2_REG
+#define SDMA3_STATUS2_REG__ID__SHIFT 0x0
+#define SDMA3_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3
+#define SDMA3_STATUS2_REG__CMD_OP__SHIFT 0x10
+#define SDMA3_STATUS2_REG__ID_MASK 0x00000007L
+#define SDMA3_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L
+#define SDMA3_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L
+//SDMA3_ATOMIC_CNTL
+#define SDMA3_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0
+#define SDMA3_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f
+#define SDMA3_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL
+#define SDMA3_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L
+//SDMA3_ATOMIC_PREOP_LO
+#define SDMA3_ATOMIC_PREOP_LO__DATA__SHIFT 0x0
+#define SDMA3_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL
+//SDMA3_ATOMIC_PREOP_HI
+#define SDMA3_ATOMIC_PREOP_HI__DATA__SHIFT 0x0
+#define SDMA3_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL
+//SDMA3_UTCL1_CNTL
+#define SDMA3_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0
+#define SDMA3_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1
+#define SDMA3_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb
+#define SDMA3_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe
+#define SDMA3_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18
+#define SDMA3_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
+#define SDMA3_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L
+#define SDMA3_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL
+#define SDMA3_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L
+#define SDMA3_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L
+#define SDMA3_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L
+#define SDMA3_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L
+//SDMA3_UTCL1_WATERMK
+#define SDMA3_UTCL1_WATERMK__REQ_WATERMK__SHIFT 0x0
+#define SDMA3_UTCL1_WATERMK__REQ_DEPTH__SHIFT 0x3
+#define SDMA3_UTCL1_WATERMK__PAGE_WATERMK__SHIFT 0x5
+#define SDMA3_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x8
+#define SDMA3_UTCL1_WATERMK__RESERVED__SHIFT 0x10
+#define SDMA3_UTCL1_WATERMK__REQ_WATERMK_MASK 0x00000007L
+#define SDMA3_UTCL1_WATERMK__REQ_DEPTH_MASK 0x00000018L
+#define SDMA3_UTCL1_WATERMK__PAGE_WATERMK_MASK 0x000000E0L
+#define SDMA3_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x0000FF00L
+#define SDMA3_UTCL1_WATERMK__RESERVED_MASK 0xFFFF0000L
+//SDMA3_UTCL1_RD_STATUS
+#define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
+#define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
+#define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
+#define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
+#define SDMA3_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
+#define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
+#define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
+#define SDMA3_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
+#define SDMA3_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
+#define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
+#define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
+#define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
+#define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
+#define SDMA3_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
+#define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
+#define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
+#define SDMA3_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
+#define SDMA3_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
+#define SDMA3_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12
+#define SDMA3_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13
+#define SDMA3_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14
+#define SDMA3_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15
+#define SDMA3_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16
+#define SDMA3_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a
+#define SDMA3_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
+#define SDMA3_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e
+#define SDMA3_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f
+#define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
+#define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L
+#define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L
+#define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L
+#define SDMA3_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L
+#define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L
+#define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L
+#define SDMA3_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L
+#define SDMA3_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L
+#define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L
+#define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L
+#define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L
+#define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L
+#define SDMA3_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L
+#define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L
+#define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L
+#define SDMA3_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L
+#define SDMA3_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L
+#define SDMA3_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L
+#define SDMA3_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L
+#define SDMA3_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L
+#define SDMA3_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L
+#define SDMA3_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L
+#define SDMA3_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L
+#define SDMA3_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L
+#define SDMA3_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L
+#define SDMA3_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L
+//SDMA3_UTCL1_WR_STATUS
+#define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
+#define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
+#define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
+#define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
+#define SDMA3_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
+#define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
+#define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
+#define SDMA3_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
+#define SDMA3_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
+#define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
+#define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
+#define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
+#define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
+#define SDMA3_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
+#define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
+#define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
+#define SDMA3_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
+#define SDMA3_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
+#define SDMA3_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12
+#define SDMA3_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13
+#define SDMA3_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14
+#define SDMA3_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15
+#define SDMA3_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16
+#define SDMA3_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19
+#define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c
+#define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
+#define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e
+#define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f
+#define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
+#define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L
+#define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L
+#define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L
+#define SDMA3_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L
+#define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L
+#define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L
+#define SDMA3_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L
+#define SDMA3_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L
+#define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L
+#define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L
+#define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L
+#define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L
+#define SDMA3_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L
+#define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L
+#define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L
+#define SDMA3_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L
+#define SDMA3_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L
+#define SDMA3_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L
+#define SDMA3_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L
+#define SDMA3_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L
+#define SDMA3_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L
+#define SDMA3_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L
+#define SDMA3_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L
+#define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L
+#define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L
+#define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L
+#define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L
+//SDMA3_UTCL1_INV0
+#define SDMA3_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0
+#define SDMA3_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1
+#define SDMA3_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2
+#define SDMA3_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3
+#define SDMA3_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4
+#define SDMA3_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5
+#define SDMA3_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6
+#define SDMA3_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7
+#define SDMA3_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8
+#define SDMA3_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9
+#define SDMA3_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa
+#define SDMA3_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb
+#define SDMA3_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc
+#define SDMA3_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c
+#define SDMA3_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L
+#define SDMA3_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L
+#define SDMA3_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L
+#define SDMA3_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L
+#define SDMA3_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L
+#define SDMA3_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L
+#define SDMA3_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L
+#define SDMA3_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L
+#define SDMA3_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L
+#define SDMA3_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L
+#define SDMA3_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L
+#define SDMA3_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L
+#define SDMA3_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L
+#define SDMA3_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L
+//SDMA3_UTCL1_INV1
+#define SDMA3_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0
+#define SDMA3_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL
+//SDMA3_UTCL1_INV2
+#define SDMA3_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0
+#define SDMA3_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL
+//SDMA3_UTCL1_RD_XNACK0
+#define SDMA3_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
+#define SDMA3_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
+//SDMA3_UTCL1_RD_XNACK1
+#define SDMA3_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
+#define SDMA3_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4
+#define SDMA3_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8
+#define SDMA3_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a
+#define SDMA3_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
+#define SDMA3_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L
+#define SDMA3_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
+#define SDMA3_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L
+//SDMA3_UTCL1_WR_XNACK0
+#define SDMA3_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
+#define SDMA3_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
+//SDMA3_UTCL1_WR_XNACK1
+#define SDMA3_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
+#define SDMA3_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4
+#define SDMA3_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8
+#define SDMA3_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a
+#define SDMA3_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
+#define SDMA3_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L
+#define SDMA3_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
+#define SDMA3_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L
+//SDMA3_UTCL1_TIMEOUT
+#define SDMA3_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0
+#define SDMA3_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10
+#define SDMA3_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL
+#define SDMA3_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L
+//SDMA3_UTCL1_PAGE
+#define SDMA3_UTCL1_PAGE__VM_HOLE__SHIFT 0x0
+#define SDMA3_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1
+#define SDMA3_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6
+#define SDMA3_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9
+#define SDMA3_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L
+#define SDMA3_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL
+#define SDMA3_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L
+#define SDMA3_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L
+//SDMA3_POWER_CNTL_IDLE
+#define SDMA3_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0
+#define SDMA3_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10
+#define SDMA3_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18
+#define SDMA3_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL
+#define SDMA3_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L
+#define SDMA3_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L
+//SDMA3_RELAX_ORDERING_LUT
+#define SDMA3_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0
+#define SDMA3_RELAX_ORDERING_LUT__COPY__SHIFT 0x1
+#define SDMA3_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2
+#define SDMA3_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3
+#define SDMA3_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4
+#define SDMA3_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5
+#define SDMA3_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6
+#define SDMA3_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8
+#define SDMA3_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9
+#define SDMA3_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa
+#define SDMA3_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb
+#define SDMA3_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc
+#define SDMA3_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd
+#define SDMA3_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe
+#define SDMA3_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b
+#define SDMA3_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c
+#define SDMA3_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
+#define SDMA3_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e
+#define SDMA3_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f
+#define SDMA3_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L
+#define SDMA3_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L
+#define SDMA3_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L
+#define SDMA3_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L
+#define SDMA3_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L
+#define SDMA3_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L
+#define SDMA3_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L
+#define SDMA3_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L
+#define SDMA3_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L
+#define SDMA3_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L
+#define SDMA3_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L
+#define SDMA3_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L
+#define SDMA3_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L
+#define SDMA3_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L
+#define SDMA3_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L
+#define SDMA3_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L
+#define SDMA3_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L
+#define SDMA3_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L
+#define SDMA3_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L
+//SDMA3_CHICKEN_BITS_2
+#define SDMA3_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0
+#define SDMA3_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT 0x4
+#define SDMA3_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL
+#define SDMA3_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK 0x00000010L
+//SDMA3_STATUS3_REG
+#define SDMA3_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0
+#define SDMA3_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10
+#define SDMA3_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14
+#define SDMA3_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15
+#define SDMA3_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16
+#define SDMA3_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL
+#define SDMA3_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L
+#define SDMA3_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L
+#define SDMA3_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L
+#define SDMA3_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L
+//SDMA3_PHYSICAL_ADDR_LO
+#define SDMA3_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0
+#define SDMA3_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1
+#define SDMA3_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2
+#define SDMA3_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc
+#define SDMA3_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L
+#define SDMA3_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L
+#define SDMA3_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L
+#define SDMA3_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L
+//SDMA3_PHYSICAL_ADDR_HI
+#define SDMA3_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA3_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL
+//SDMA3_PHASE2_QUANTUM
+#define SDMA3_PHASE2_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA3_PHASE2_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA3_PHASE2_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA3_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL
+#define SDMA3_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L
+#define SDMA3_PHASE2_QUANTUM__PREFER_MASK 0x40000000L
+//SDMA3_ERROR_LOG
+#define SDMA3_ERROR_LOG__OVERRIDE__SHIFT 0x0
+#define SDMA3_ERROR_LOG__STATUS__SHIFT 0x10
+#define SDMA3_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL
+#define SDMA3_ERROR_LOG__STATUS_MASK 0xFFFF0000L
+//SDMA3_PUB_DUMMY_REG0
+#define SDMA3_PUB_DUMMY_REG0__VALUE__SHIFT 0x0
+#define SDMA3_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL
+//SDMA3_PUB_DUMMY_REG1
+#define SDMA3_PUB_DUMMY_REG1__VALUE__SHIFT 0x0
+#define SDMA3_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL
+//SDMA3_PUB_DUMMY_REG2
+#define SDMA3_PUB_DUMMY_REG2__VALUE__SHIFT 0x0
+#define SDMA3_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL
+//SDMA3_PUB_DUMMY_REG3
+#define SDMA3_PUB_DUMMY_REG3__VALUE__SHIFT 0x0
+#define SDMA3_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL
+//SDMA3_F32_COUNTER
+#define SDMA3_F32_COUNTER__VALUE__SHIFT 0x0
+#define SDMA3_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL
+//SDMA3_PERFCNT_PERFCOUNTER0_CFG
+#define SDMA3_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define SDMA3_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define SDMA3_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define SDMA3_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define SDMA3_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define SDMA3_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define SDMA3_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define SDMA3_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define SDMA3_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define SDMA3_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//SDMA3_PERFCNT_PERFCOUNTER1_CFG
+#define SDMA3_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define SDMA3_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define SDMA3_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define SDMA3_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define SDMA3_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define SDMA3_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define SDMA3_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define SDMA3_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define SDMA3_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define SDMA3_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL
+#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+//SDMA3_PERFCNT_MISC_CNTL
+#define SDMA3_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x0
+#define SDMA3_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000FFFFL
+//SDMA3_PERFCNT_PERFCOUNTER_LO
+#define SDMA3_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define SDMA3_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//SDMA3_PERFCNT_PERFCOUNTER_HI
+#define SDMA3_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define SDMA3_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define SDMA3_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define SDMA3_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//SDMA3_CRD_CNTL
+#define SDMA3_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7
+#define SDMA3_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd
+#define SDMA3_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L
+#define SDMA3_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L
+//SDMA3_ULV_CNTL
+#define SDMA3_ULV_CNTL__HYSTERESIS__SHIFT 0x0
+#define SDMA3_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b
+#define SDMA3_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c
+#define SDMA3_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
+#define SDMA3_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e
+#define SDMA3_ULV_CNTL__ULV_STATUS__SHIFT 0x1f
+#define SDMA3_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL
+#define SDMA3_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L
+#define SDMA3_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L
+#define SDMA3_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L
+#define SDMA3_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L
+#define SDMA3_ULV_CNTL__ULV_STATUS_MASK 0x80000000L
+//SDMA3_EA_DBIT_ADDR_DATA
+#define SDMA3_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0
+#define SDMA3_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL
+//SDMA3_EA_DBIT_ADDR_INDEX
+#define SDMA3_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0
+#define SDMA3_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L
+//SDMA3_STATUS4_REG
+#define SDMA3_STATUS4_REG__IDLE__SHIFT 0x0
+#define SDMA3_STATUS4_REG__IH_OUTSTANDING__SHIFT 0x2
+#define SDMA3_STATUS4_REG__SEM_OUTSTANDING__SHIFT 0x3
+#define SDMA3_STATUS4_REG__MMHUB_RD_OUTSTANDING__SHIFT 0x4
+#define SDMA3_STATUS4_REG__MMHUB_WR_OUTSTANDING__SHIFT 0x5
+#define SDMA3_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT 0x6
+#define SDMA3_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT 0x7
+#define SDMA3_STATUS4_REG__REG_POLLING__SHIFT 0x8
+#define SDMA3_STATUS4_REG__MEM_POLLING__SHIFT 0x9
+#define SDMA3_STATUS4_REG__UTCL2_RD_XNACK__SHIFT 0xa
+#define SDMA3_STATUS4_REG__UTCL2_WR_XNACK__SHIFT 0xc
+#define SDMA3_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT 0xe
+#define SDMA3_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT 0x12
+#define SDMA3_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT 0x13
+#define SDMA3_STATUS4_REG__IDLE_MASK 0x00000001L
+#define SDMA3_STATUS4_REG__IH_OUTSTANDING_MASK 0x00000004L
+#define SDMA3_STATUS4_REG__SEM_OUTSTANDING_MASK 0x00000008L
+#define SDMA3_STATUS4_REG__MMHUB_RD_OUTSTANDING_MASK 0x00000010L
+#define SDMA3_STATUS4_REG__MMHUB_WR_OUTSTANDING_MASK 0x00000020L
+#define SDMA3_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK 0x00000040L
+#define SDMA3_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK 0x00000080L
+#define SDMA3_STATUS4_REG__REG_POLLING_MASK 0x00000100L
+#define SDMA3_STATUS4_REG__MEM_POLLING_MASK 0x00000200L
+#define SDMA3_STATUS4_REG__UTCL2_RD_XNACK_MASK 0x00000C00L
+#define SDMA3_STATUS4_REG__UTCL2_WR_XNACK_MASK 0x00003000L
+#define SDMA3_STATUS4_REG__ACTIVE_QUEUE_ID_MASK 0x0003C000L
+#define SDMA3_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK 0x00040000L
+#define SDMA3_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK 0x00080000L
+//SDMA3_SCRATCH_RAM_DATA
+#define SDMA3_SCRATCH_RAM_DATA__DATA__SHIFT 0x0
+#define SDMA3_SCRATCH_RAM_DATA__DATA_MASK 0xFFFFFFFFL
+//SDMA3_SCRATCH_RAM_ADDR
+#define SDMA3_SCRATCH_RAM_ADDR__ADDR__SHIFT 0x0
+#define SDMA3_SCRATCH_RAM_ADDR__ADDR_MASK 0x0000007FL
+//SDMA3_CE_CTRL
+#define SDMA3_CE_CTRL__RD_LUT_WATERMARK__SHIFT 0x0
+#define SDMA3_CE_CTRL__RD_LUT_DEPTH__SHIFT 0x3
+#define SDMA3_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT 0x5
+#define SDMA3_CE_CTRL__RESERVED__SHIFT 0x8
+#define SDMA3_CE_CTRL__RD_LUT_WATERMARK_MASK 0x00000007L
+#define SDMA3_CE_CTRL__RD_LUT_DEPTH_MASK 0x00000018L
+#define SDMA3_CE_CTRL__WR_AFIFO_WATERMARK_MASK 0x000000E0L
+#define SDMA3_CE_CTRL__RESERVED_MASK 0xFFFFFF00L
+//SDMA3_RAS_STATUS
+#define SDMA3_RAS_STATUS__RB_FETCH_ECC__SHIFT 0x0
+#define SDMA3_RAS_STATUS__IB_FETCH_ECC__SHIFT 0x1
+#define SDMA3_RAS_STATUS__F32_DATA_ECC__SHIFT 0x2
+#define SDMA3_RAS_STATUS__SEM_WPTR_ATOMIC_ECC__SHIFT 0x3
+#define SDMA3_RAS_STATUS__COPY_DATA_ECC__SHIFT 0x4
+#define SDMA3_RAS_STATUS__SRAM_ECC__SHIFT 0x5
+#define SDMA3_RAS_STATUS__RB_FETCH_NACK_GEN_ERR__SHIFT 0x8
+#define SDMA3_RAS_STATUS__IB_FETCH_NACK_GEN_ERR__SHIFT 0x9
+#define SDMA3_RAS_STATUS__F32_DATA_NACK_GEN_ERR__SHIFT 0xa
+#define SDMA3_RAS_STATUS__COPY_DATA_NACK_GEN_ERR__SHIFT 0xb
+#define SDMA3_RAS_STATUS__WRRET_DATA_NACK_GEN_ERR__SHIFT 0xc
+#define SDMA3_RAS_STATUS__WPTR_RPTR_ATOMIC_NACK_GEN_ERR__SHIFT 0xd
+#define SDMA3_RAS_STATUS__RB_FETCH_ECC_MASK 0x00000001L
+#define SDMA3_RAS_STATUS__IB_FETCH_ECC_MASK 0x00000002L
+#define SDMA3_RAS_STATUS__F32_DATA_ECC_MASK 0x00000004L
+#define SDMA3_RAS_STATUS__SEM_WPTR_ATOMIC_ECC_MASK 0x00000008L
+#define SDMA3_RAS_STATUS__COPY_DATA_ECC_MASK 0x00000010L
+#define SDMA3_RAS_STATUS__SRAM_ECC_MASK 0x00000020L
+#define SDMA3_RAS_STATUS__RB_FETCH_NACK_GEN_ERR_MASK 0x00000100L
+#define SDMA3_RAS_STATUS__IB_FETCH_NACK_GEN_ERR_MASK 0x00000200L
+#define SDMA3_RAS_STATUS__F32_DATA_NACK_GEN_ERR_MASK 0x00000400L
+#define SDMA3_RAS_STATUS__COPY_DATA_NACK_GEN_ERR_MASK 0x00000800L
+#define SDMA3_RAS_STATUS__WRRET_DATA_NACK_GEN_ERR_MASK 0x00001000L
+#define SDMA3_RAS_STATUS__WPTR_RPTR_ATOMIC_NACK_GEN_ERR_MASK 0x00002000L
+//SDMA3_CLK_STATUS
+#define SDMA3_CLK_STATUS__DYN_CLK__SHIFT 0x0
+#define SDMA3_CLK_STATUS__PTR_CLK__SHIFT 0x1
+#define SDMA3_CLK_STATUS__REG_CLK__SHIFT 0x2
+#define SDMA3_CLK_STATUS__F32_CLK__SHIFT 0x3
+#define SDMA3_CLK_STATUS__DYN_CLK_MASK 0x00000001L
+#define SDMA3_CLK_STATUS__PTR_CLK_MASK 0x00000002L
+#define SDMA3_CLK_STATUS__REG_CLK_MASK 0x00000004L
+#define SDMA3_CLK_STATUS__F32_CLK_MASK 0x00000008L
+//SDMA3_GFX_RB_CNTL
+#define SDMA3_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA3_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA3_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA3_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA3_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA3_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA3_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA3_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA3_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA3_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA3_GFX_RB_BASE
+#define SDMA3_GFX_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA3_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_GFX_RB_BASE_HI
+#define SDMA3_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA3_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA3_GFX_RB_RPTR
+#define SDMA3_GFX_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA3_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_GFX_RB_RPTR_HI
+#define SDMA3_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA3_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_GFX_RB_WPTR
+#define SDMA3_GFX_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA3_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_GFX_RB_WPTR_HI
+#define SDMA3_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA3_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_GFX_RB_WPTR_POLL_CNTL
+#define SDMA3_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA3_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA3_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA3_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA3_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA3_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA3_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA3_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA3_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA3_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA3_GFX_RB_RPTR_ADDR_HI
+#define SDMA3_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA3_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_GFX_RB_RPTR_ADDR_LO
+#define SDMA3_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA3_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA3_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA3_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA3_GFX_IB_CNTL
+#define SDMA3_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA3_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA3_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA3_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA3_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA3_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA3_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA3_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA3_GFX_IB_RPTR
+#define SDMA3_GFX_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA3_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA3_GFX_IB_OFFSET
+#define SDMA3_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA3_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA3_GFX_IB_BASE_LO
+#define SDMA3_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA3_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA3_GFX_IB_BASE_HI
+#define SDMA3_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA3_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_GFX_IB_SIZE
+#define SDMA3_GFX_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA3_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA3_GFX_SKIP_CNTL
+#define SDMA3_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA3_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA3_GFX_CONTEXT_STATUS
+#define SDMA3_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA3_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA3_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA3_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA3_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA3_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA3_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA3_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA3_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA3_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA3_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA3_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA3_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA3_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA3_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA3_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA3_GFX_DOORBELL
+#define SDMA3_GFX_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA3_GFX_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA3_GFX_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA3_GFX_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA3_GFX_CONTEXT_CNTL
+#define SDMA3_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
+#define SDMA3_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18
+#define SDMA3_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L
+#define SDMA3_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0x0F000000L
+//SDMA3_GFX_STATUS
+#define SDMA3_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA3_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA3_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA3_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA3_GFX_DOORBELL_LOG
+#define SDMA3_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA3_GFX_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA3_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA3_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA3_GFX_WATERMARK
+#define SDMA3_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA3_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA3_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA3_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA3_GFX_DOORBELL_OFFSET
+#define SDMA3_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA3_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA3_GFX_CSA_ADDR_LO
+#define SDMA3_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA3_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA3_GFX_CSA_ADDR_HI
+#define SDMA3_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA3_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_GFX_IB_SUB_REMAIN
+#define SDMA3_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA3_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA3_GFX_PREEMPT
+#define SDMA3_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA3_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA3_GFX_DUMMY_REG
+#define SDMA3_GFX_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA3_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA3_GFX_RB_WPTR_POLL_ADDR_HI
+#define SDMA3_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA3_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_GFX_RB_WPTR_POLL_ADDR_LO
+#define SDMA3_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA3_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA3_GFX_RB_AQL_CNTL
+#define SDMA3_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA3_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA3_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA3_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA3_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA3_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA3_GFX_MINOR_PTR_UPDATE
+#define SDMA3_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA3_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA3_GFX_MIDCMD_DATA0
+#define SDMA3_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA3_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA3_GFX_MIDCMD_DATA1
+#define SDMA3_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA3_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA3_GFX_MIDCMD_DATA2
+#define SDMA3_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA3_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA3_GFX_MIDCMD_DATA3
+#define SDMA3_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA3_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA3_GFX_MIDCMD_DATA4
+#define SDMA3_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA3_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA3_GFX_MIDCMD_DATA5
+#define SDMA3_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA3_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA3_GFX_MIDCMD_DATA6
+#define SDMA3_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA3_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA3_GFX_MIDCMD_DATA7
+#define SDMA3_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA3_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA3_GFX_MIDCMD_DATA8
+#define SDMA3_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA3_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA3_GFX_MIDCMD_DATA9
+#define SDMA3_GFX_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA3_GFX_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA3_GFX_MIDCMD_DATA10
+#define SDMA3_GFX_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA3_GFX_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA3_GFX_MIDCMD_CNTL
+#define SDMA3_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA3_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA3_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA3_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA3_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA3_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA3_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA3_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA3_PAGE_RB_CNTL
+#define SDMA3_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA3_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA3_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA3_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA3_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA3_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA3_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA3_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA3_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA3_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA3_PAGE_RB_BASE
+#define SDMA3_PAGE_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA3_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_PAGE_RB_BASE_HI
+#define SDMA3_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA3_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA3_PAGE_RB_RPTR
+#define SDMA3_PAGE_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA3_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_PAGE_RB_RPTR_HI
+#define SDMA3_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA3_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_PAGE_RB_WPTR
+#define SDMA3_PAGE_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA3_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_PAGE_RB_WPTR_HI
+#define SDMA3_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA3_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_PAGE_RB_WPTR_POLL_CNTL
+#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA3_PAGE_RB_RPTR_ADDR_HI
+#define SDMA3_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA3_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_PAGE_RB_RPTR_ADDR_LO
+#define SDMA3_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA3_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA3_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA3_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA3_PAGE_IB_CNTL
+#define SDMA3_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA3_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA3_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA3_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA3_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA3_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA3_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA3_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA3_PAGE_IB_RPTR
+#define SDMA3_PAGE_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA3_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA3_PAGE_IB_OFFSET
+#define SDMA3_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA3_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA3_PAGE_IB_BASE_LO
+#define SDMA3_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA3_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA3_PAGE_IB_BASE_HI
+#define SDMA3_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA3_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_PAGE_IB_SIZE
+#define SDMA3_PAGE_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA3_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA3_PAGE_SKIP_CNTL
+#define SDMA3_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA3_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA3_PAGE_CONTEXT_STATUS
+#define SDMA3_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA3_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA3_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA3_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA3_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA3_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA3_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA3_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA3_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA3_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA3_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA3_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA3_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA3_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA3_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA3_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA3_PAGE_DOORBELL
+#define SDMA3_PAGE_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA3_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA3_PAGE_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA3_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA3_PAGE_STATUS
+#define SDMA3_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA3_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA3_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA3_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA3_PAGE_DOORBELL_LOG
+#define SDMA3_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA3_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA3_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA3_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA3_PAGE_WATERMARK
+#define SDMA3_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA3_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA3_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA3_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA3_PAGE_DOORBELL_OFFSET
+#define SDMA3_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA3_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA3_PAGE_CSA_ADDR_LO
+#define SDMA3_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA3_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA3_PAGE_CSA_ADDR_HI
+#define SDMA3_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA3_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_PAGE_IB_SUB_REMAIN
+#define SDMA3_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA3_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA3_PAGE_PREEMPT
+#define SDMA3_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA3_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA3_PAGE_DUMMY_REG
+#define SDMA3_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA3_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA3_PAGE_RB_WPTR_POLL_ADDR_HI
+#define SDMA3_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA3_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_PAGE_RB_WPTR_POLL_ADDR_LO
+#define SDMA3_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA3_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA3_PAGE_RB_AQL_CNTL
+#define SDMA3_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA3_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA3_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA3_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA3_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA3_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA3_PAGE_MINOR_PTR_UPDATE
+#define SDMA3_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA3_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA3_PAGE_MIDCMD_DATA0
+#define SDMA3_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA3_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA3_PAGE_MIDCMD_DATA1
+#define SDMA3_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA3_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA3_PAGE_MIDCMD_DATA2
+#define SDMA3_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA3_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA3_PAGE_MIDCMD_DATA3
+#define SDMA3_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA3_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA3_PAGE_MIDCMD_DATA4
+#define SDMA3_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA3_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA3_PAGE_MIDCMD_DATA5
+#define SDMA3_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA3_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA3_PAGE_MIDCMD_DATA6
+#define SDMA3_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA3_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA3_PAGE_MIDCMD_DATA7
+#define SDMA3_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA3_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA3_PAGE_MIDCMD_DATA8
+#define SDMA3_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA3_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA3_PAGE_MIDCMD_DATA9
+#define SDMA3_PAGE_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA3_PAGE_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA3_PAGE_MIDCMD_DATA10
+#define SDMA3_PAGE_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA3_PAGE_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA3_PAGE_MIDCMD_CNTL
+#define SDMA3_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA3_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA3_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA3_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA3_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA3_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA3_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA3_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA3_RLC0_RB_CNTL
+#define SDMA3_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA3_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA3_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA3_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA3_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA3_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA3_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA3_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA3_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA3_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA3_RLC0_RB_BASE
+#define SDMA3_RLC0_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA3_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC0_RB_BASE_HI
+#define SDMA3_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA3_RLC0_RB_RPTR
+#define SDMA3_RLC0_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA3_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_RLC0_RB_RPTR_HI
+#define SDMA3_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA3_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_RLC0_RB_WPTR
+#define SDMA3_RLC0_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA3_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_RLC0_RB_WPTR_HI
+#define SDMA3_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA3_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_RLC0_RB_WPTR_POLL_CNTL
+#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA3_RLC0_RB_RPTR_ADDR_HI
+#define SDMA3_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC0_RB_RPTR_ADDR_LO
+#define SDMA3_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA3_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA3_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA3_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA3_RLC0_IB_CNTL
+#define SDMA3_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA3_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA3_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA3_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA3_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA3_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA3_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA3_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA3_RLC0_IB_RPTR
+#define SDMA3_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA3_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA3_RLC0_IB_OFFSET
+#define SDMA3_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA3_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA3_RLC0_IB_BASE_LO
+#define SDMA3_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA3_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA3_RLC0_IB_BASE_HI
+#define SDMA3_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC0_IB_SIZE
+#define SDMA3_RLC0_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA3_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA3_RLC0_SKIP_CNTL
+#define SDMA3_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA3_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA3_RLC0_CONTEXT_STATUS
+#define SDMA3_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA3_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA3_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA3_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA3_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA3_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA3_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA3_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA3_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA3_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA3_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA3_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA3_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA3_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA3_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA3_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA3_RLC0_DOORBELL
+#define SDMA3_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA3_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA3_RLC0_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA3_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA3_RLC0_STATUS
+#define SDMA3_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA3_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA3_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA3_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA3_RLC0_DOORBELL_LOG
+#define SDMA3_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA3_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA3_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA3_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA3_RLC0_WATERMARK
+#define SDMA3_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA3_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA3_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA3_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA3_RLC0_DOORBELL_OFFSET
+#define SDMA3_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA3_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA3_RLC0_CSA_ADDR_LO
+#define SDMA3_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA3_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA3_RLC0_CSA_ADDR_HI
+#define SDMA3_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC0_IB_SUB_REMAIN
+#define SDMA3_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA3_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA3_RLC0_PREEMPT
+#define SDMA3_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA3_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA3_RLC0_DUMMY_REG
+#define SDMA3_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA3_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA3_RLC0_RB_WPTR_POLL_ADDR_HI
+#define SDMA3_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC0_RB_WPTR_POLL_ADDR_LO
+#define SDMA3_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA3_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA3_RLC0_RB_AQL_CNTL
+#define SDMA3_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA3_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA3_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA3_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA3_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA3_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA3_RLC0_MINOR_PTR_UPDATE
+#define SDMA3_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA3_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA3_RLC0_MIDCMD_DATA0
+#define SDMA3_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA3_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA3_RLC0_MIDCMD_DATA1
+#define SDMA3_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA3_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA3_RLC0_MIDCMD_DATA2
+#define SDMA3_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA3_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA3_RLC0_MIDCMD_DATA3
+#define SDMA3_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA3_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA3_RLC0_MIDCMD_DATA4
+#define SDMA3_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA3_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA3_RLC0_MIDCMD_DATA5
+#define SDMA3_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA3_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA3_RLC0_MIDCMD_DATA6
+#define SDMA3_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA3_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA3_RLC0_MIDCMD_DATA7
+#define SDMA3_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA3_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA3_RLC0_MIDCMD_DATA8
+#define SDMA3_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA3_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA3_RLC0_MIDCMD_DATA9
+#define SDMA3_RLC0_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA3_RLC0_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA3_RLC0_MIDCMD_DATA10
+#define SDMA3_RLC0_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA3_RLC0_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA3_RLC0_MIDCMD_CNTL
+#define SDMA3_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA3_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA3_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA3_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA3_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA3_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA3_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA3_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA3_RLC1_RB_CNTL
+#define SDMA3_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA3_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA3_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA3_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA3_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA3_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA3_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA3_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA3_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA3_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA3_RLC1_RB_BASE
+#define SDMA3_RLC1_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA3_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC1_RB_BASE_HI
+#define SDMA3_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA3_RLC1_RB_RPTR
+#define SDMA3_RLC1_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA3_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_RLC1_RB_RPTR_HI
+#define SDMA3_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA3_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_RLC1_RB_WPTR
+#define SDMA3_RLC1_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA3_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_RLC1_RB_WPTR_HI
+#define SDMA3_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA3_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_RLC1_RB_WPTR_POLL_CNTL
+#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA3_RLC1_RB_RPTR_ADDR_HI
+#define SDMA3_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC1_RB_RPTR_ADDR_LO
+#define SDMA3_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA3_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA3_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA3_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA3_RLC1_IB_CNTL
+#define SDMA3_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA3_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA3_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA3_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA3_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA3_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA3_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA3_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA3_RLC1_IB_RPTR
+#define SDMA3_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA3_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA3_RLC1_IB_OFFSET
+#define SDMA3_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA3_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA3_RLC1_IB_BASE_LO
+#define SDMA3_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA3_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA3_RLC1_IB_BASE_HI
+#define SDMA3_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC1_IB_SIZE
+#define SDMA3_RLC1_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA3_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA3_RLC1_SKIP_CNTL
+#define SDMA3_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA3_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA3_RLC1_CONTEXT_STATUS
+#define SDMA3_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA3_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA3_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA3_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA3_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA3_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA3_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA3_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA3_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA3_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA3_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA3_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA3_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA3_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA3_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA3_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA3_RLC1_DOORBELL
+#define SDMA3_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA3_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA3_RLC1_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA3_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA3_RLC1_STATUS
+#define SDMA3_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA3_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA3_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA3_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA3_RLC1_DOORBELL_LOG
+#define SDMA3_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA3_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA3_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA3_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA3_RLC1_WATERMARK
+#define SDMA3_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA3_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA3_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA3_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA3_RLC1_DOORBELL_OFFSET
+#define SDMA3_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA3_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA3_RLC1_CSA_ADDR_LO
+#define SDMA3_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA3_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA3_RLC1_CSA_ADDR_HI
+#define SDMA3_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC1_IB_SUB_REMAIN
+#define SDMA3_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA3_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA3_RLC1_PREEMPT
+#define SDMA3_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA3_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA3_RLC1_DUMMY_REG
+#define SDMA3_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA3_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA3_RLC1_RB_WPTR_POLL_ADDR_HI
+#define SDMA3_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC1_RB_WPTR_POLL_ADDR_LO
+#define SDMA3_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA3_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA3_RLC1_RB_AQL_CNTL
+#define SDMA3_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA3_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA3_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA3_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA3_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA3_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA3_RLC1_MINOR_PTR_UPDATE
+#define SDMA3_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA3_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA3_RLC1_MIDCMD_DATA0
+#define SDMA3_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA3_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA3_RLC1_MIDCMD_DATA1
+#define SDMA3_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA3_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA3_RLC1_MIDCMD_DATA2
+#define SDMA3_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA3_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA3_RLC1_MIDCMD_DATA3
+#define SDMA3_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA3_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA3_RLC1_MIDCMD_DATA4
+#define SDMA3_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA3_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA3_RLC1_MIDCMD_DATA5
+#define SDMA3_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA3_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA3_RLC1_MIDCMD_DATA6
+#define SDMA3_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA3_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA3_RLC1_MIDCMD_DATA7
+#define SDMA3_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA3_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA3_RLC1_MIDCMD_DATA8
+#define SDMA3_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA3_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA3_RLC1_MIDCMD_DATA9
+#define SDMA3_RLC1_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA3_RLC1_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA3_RLC1_MIDCMD_DATA10
+#define SDMA3_RLC1_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA3_RLC1_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA3_RLC1_MIDCMD_CNTL
+#define SDMA3_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA3_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA3_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA3_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA3_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA3_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA3_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA3_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA3_RLC2_RB_CNTL
+#define SDMA3_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA3_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA3_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA3_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA3_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA3_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA3_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA3_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA3_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA3_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA3_RLC2_RB_BASE
+#define SDMA3_RLC2_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA3_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC2_RB_BASE_HI
+#define SDMA3_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA3_RLC2_RB_RPTR
+#define SDMA3_RLC2_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA3_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_RLC2_RB_RPTR_HI
+#define SDMA3_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA3_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_RLC2_RB_WPTR
+#define SDMA3_RLC2_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA3_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_RLC2_RB_WPTR_HI
+#define SDMA3_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA3_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_RLC2_RB_WPTR_POLL_CNTL
+#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA3_RLC2_RB_RPTR_ADDR_HI
+#define SDMA3_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC2_RB_RPTR_ADDR_LO
+#define SDMA3_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA3_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA3_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA3_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA3_RLC2_IB_CNTL
+#define SDMA3_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA3_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA3_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA3_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA3_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA3_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA3_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA3_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA3_RLC2_IB_RPTR
+#define SDMA3_RLC2_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA3_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA3_RLC2_IB_OFFSET
+#define SDMA3_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA3_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA3_RLC2_IB_BASE_LO
+#define SDMA3_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA3_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA3_RLC2_IB_BASE_HI
+#define SDMA3_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC2_IB_SIZE
+#define SDMA3_RLC2_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA3_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA3_RLC2_SKIP_CNTL
+#define SDMA3_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA3_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA3_RLC2_CONTEXT_STATUS
+#define SDMA3_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA3_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA3_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA3_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA3_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA3_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA3_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA3_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA3_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA3_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA3_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA3_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA3_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA3_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA3_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA3_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA3_RLC2_DOORBELL
+#define SDMA3_RLC2_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA3_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA3_RLC2_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA3_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA3_RLC2_STATUS
+#define SDMA3_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA3_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA3_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA3_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA3_RLC2_DOORBELL_LOG
+#define SDMA3_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA3_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA3_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA3_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA3_RLC2_WATERMARK
+#define SDMA3_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA3_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA3_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA3_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA3_RLC2_DOORBELL_OFFSET
+#define SDMA3_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA3_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA3_RLC2_CSA_ADDR_LO
+#define SDMA3_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA3_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA3_RLC2_CSA_ADDR_HI
+#define SDMA3_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC2_IB_SUB_REMAIN
+#define SDMA3_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA3_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA3_RLC2_PREEMPT
+#define SDMA3_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA3_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA3_RLC2_DUMMY_REG
+#define SDMA3_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA3_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA3_RLC2_RB_WPTR_POLL_ADDR_HI
+#define SDMA3_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC2_RB_WPTR_POLL_ADDR_LO
+#define SDMA3_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA3_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA3_RLC2_RB_AQL_CNTL
+#define SDMA3_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA3_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA3_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA3_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA3_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA3_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA3_RLC2_MINOR_PTR_UPDATE
+#define SDMA3_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA3_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA3_RLC2_MIDCMD_DATA0
+#define SDMA3_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA3_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA3_RLC2_MIDCMD_DATA1
+#define SDMA3_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA3_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA3_RLC2_MIDCMD_DATA2
+#define SDMA3_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA3_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA3_RLC2_MIDCMD_DATA3
+#define SDMA3_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA3_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA3_RLC2_MIDCMD_DATA4
+#define SDMA3_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA3_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA3_RLC2_MIDCMD_DATA5
+#define SDMA3_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA3_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA3_RLC2_MIDCMD_DATA6
+#define SDMA3_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA3_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA3_RLC2_MIDCMD_DATA7
+#define SDMA3_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA3_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA3_RLC2_MIDCMD_DATA8
+#define SDMA3_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA3_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA3_RLC2_MIDCMD_DATA9
+#define SDMA3_RLC2_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA3_RLC2_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA3_RLC2_MIDCMD_DATA10
+#define SDMA3_RLC2_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA3_RLC2_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA3_RLC2_MIDCMD_CNTL
+#define SDMA3_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA3_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA3_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA3_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA3_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA3_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA3_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA3_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA3_RLC3_RB_CNTL
+#define SDMA3_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA3_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA3_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA3_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA3_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA3_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA3_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA3_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA3_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA3_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA3_RLC3_RB_BASE
+#define SDMA3_RLC3_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA3_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC3_RB_BASE_HI
+#define SDMA3_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA3_RLC3_RB_RPTR
+#define SDMA3_RLC3_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA3_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_RLC3_RB_RPTR_HI
+#define SDMA3_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA3_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_RLC3_RB_WPTR
+#define SDMA3_RLC3_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA3_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_RLC3_RB_WPTR_HI
+#define SDMA3_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA3_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_RLC3_RB_WPTR_POLL_CNTL
+#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA3_RLC3_RB_RPTR_ADDR_HI
+#define SDMA3_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC3_RB_RPTR_ADDR_LO
+#define SDMA3_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA3_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA3_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA3_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA3_RLC3_IB_CNTL
+#define SDMA3_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA3_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA3_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA3_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA3_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA3_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA3_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA3_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA3_RLC3_IB_RPTR
+#define SDMA3_RLC3_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA3_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA3_RLC3_IB_OFFSET
+#define SDMA3_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA3_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA3_RLC3_IB_BASE_LO
+#define SDMA3_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA3_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA3_RLC3_IB_BASE_HI
+#define SDMA3_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC3_IB_SIZE
+#define SDMA3_RLC3_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA3_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA3_RLC3_SKIP_CNTL
+#define SDMA3_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA3_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA3_RLC3_CONTEXT_STATUS
+#define SDMA3_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA3_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA3_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA3_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA3_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA3_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA3_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA3_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA3_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA3_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA3_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA3_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA3_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA3_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA3_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA3_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA3_RLC3_DOORBELL
+#define SDMA3_RLC3_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA3_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA3_RLC3_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA3_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA3_RLC3_STATUS
+#define SDMA3_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA3_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA3_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA3_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA3_RLC3_DOORBELL_LOG
+#define SDMA3_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA3_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA3_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA3_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA3_RLC3_WATERMARK
+#define SDMA3_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA3_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA3_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA3_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA3_RLC3_DOORBELL_OFFSET
+#define SDMA3_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA3_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA3_RLC3_CSA_ADDR_LO
+#define SDMA3_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA3_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA3_RLC3_CSA_ADDR_HI
+#define SDMA3_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC3_IB_SUB_REMAIN
+#define SDMA3_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA3_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA3_RLC3_PREEMPT
+#define SDMA3_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA3_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA3_RLC3_DUMMY_REG
+#define SDMA3_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA3_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA3_RLC3_RB_WPTR_POLL_ADDR_HI
+#define SDMA3_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC3_RB_WPTR_POLL_ADDR_LO
+#define SDMA3_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA3_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA3_RLC3_RB_AQL_CNTL
+#define SDMA3_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA3_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA3_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA3_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA3_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA3_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA3_RLC3_MINOR_PTR_UPDATE
+#define SDMA3_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA3_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA3_RLC3_MIDCMD_DATA0
+#define SDMA3_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA3_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA3_RLC3_MIDCMD_DATA1
+#define SDMA3_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA3_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA3_RLC3_MIDCMD_DATA2
+#define SDMA3_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA3_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA3_RLC3_MIDCMD_DATA3
+#define SDMA3_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA3_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA3_RLC3_MIDCMD_DATA4
+#define SDMA3_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA3_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA3_RLC3_MIDCMD_DATA5
+#define SDMA3_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA3_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA3_RLC3_MIDCMD_DATA6
+#define SDMA3_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA3_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA3_RLC3_MIDCMD_DATA7
+#define SDMA3_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA3_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA3_RLC3_MIDCMD_DATA8
+#define SDMA3_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA3_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA3_RLC3_MIDCMD_DATA9
+#define SDMA3_RLC3_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA3_RLC3_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA3_RLC3_MIDCMD_DATA10
+#define SDMA3_RLC3_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA3_RLC3_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA3_RLC3_MIDCMD_CNTL
+#define SDMA3_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA3_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA3_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA3_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA3_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA3_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA3_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA3_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA3_RLC4_RB_CNTL
+#define SDMA3_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA3_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA3_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA3_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA3_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA3_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA3_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA3_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA3_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA3_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA3_RLC4_RB_BASE
+#define SDMA3_RLC4_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA3_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC4_RB_BASE_HI
+#define SDMA3_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA3_RLC4_RB_RPTR
+#define SDMA3_RLC4_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA3_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_RLC4_RB_RPTR_HI
+#define SDMA3_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA3_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_RLC4_RB_WPTR
+#define SDMA3_RLC4_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA3_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_RLC4_RB_WPTR_HI
+#define SDMA3_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA3_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_RLC4_RB_WPTR_POLL_CNTL
+#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA3_RLC4_RB_RPTR_ADDR_HI
+#define SDMA3_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC4_RB_RPTR_ADDR_LO
+#define SDMA3_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA3_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA3_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA3_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA3_RLC4_IB_CNTL
+#define SDMA3_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA3_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA3_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA3_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA3_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA3_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA3_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA3_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA3_RLC4_IB_RPTR
+#define SDMA3_RLC4_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA3_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA3_RLC4_IB_OFFSET
+#define SDMA3_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA3_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA3_RLC4_IB_BASE_LO
+#define SDMA3_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA3_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA3_RLC4_IB_BASE_HI
+#define SDMA3_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC4_IB_SIZE
+#define SDMA3_RLC4_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA3_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA3_RLC4_SKIP_CNTL
+#define SDMA3_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA3_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA3_RLC4_CONTEXT_STATUS
+#define SDMA3_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA3_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA3_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA3_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA3_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA3_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA3_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA3_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA3_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA3_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA3_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA3_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA3_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA3_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA3_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA3_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA3_RLC4_DOORBELL
+#define SDMA3_RLC4_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA3_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA3_RLC4_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA3_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA3_RLC4_STATUS
+#define SDMA3_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA3_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA3_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA3_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA3_RLC4_DOORBELL_LOG
+#define SDMA3_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA3_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA3_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA3_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA3_RLC4_WATERMARK
+#define SDMA3_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA3_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA3_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA3_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA3_RLC4_DOORBELL_OFFSET
+#define SDMA3_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA3_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA3_RLC4_CSA_ADDR_LO
+#define SDMA3_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA3_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA3_RLC4_CSA_ADDR_HI
+#define SDMA3_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC4_IB_SUB_REMAIN
+#define SDMA3_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA3_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA3_RLC4_PREEMPT
+#define SDMA3_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA3_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA3_RLC4_DUMMY_REG
+#define SDMA3_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA3_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA3_RLC4_RB_WPTR_POLL_ADDR_HI
+#define SDMA3_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC4_RB_WPTR_POLL_ADDR_LO
+#define SDMA3_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA3_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA3_RLC4_RB_AQL_CNTL
+#define SDMA3_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA3_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA3_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA3_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA3_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA3_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA3_RLC4_MINOR_PTR_UPDATE
+#define SDMA3_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA3_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA3_RLC4_MIDCMD_DATA0
+#define SDMA3_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA3_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA3_RLC4_MIDCMD_DATA1
+#define SDMA3_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA3_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA3_RLC4_MIDCMD_DATA2
+#define SDMA3_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA3_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA3_RLC4_MIDCMD_DATA3
+#define SDMA3_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA3_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA3_RLC4_MIDCMD_DATA4
+#define SDMA3_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA3_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA3_RLC4_MIDCMD_DATA5
+#define SDMA3_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA3_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA3_RLC4_MIDCMD_DATA6
+#define SDMA3_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA3_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA3_RLC4_MIDCMD_DATA7
+#define SDMA3_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA3_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA3_RLC4_MIDCMD_DATA8
+#define SDMA3_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA3_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA3_RLC4_MIDCMD_DATA9
+#define SDMA3_RLC4_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA3_RLC4_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA3_RLC4_MIDCMD_DATA10
+#define SDMA3_RLC4_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA3_RLC4_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA3_RLC4_MIDCMD_CNTL
+#define SDMA3_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA3_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA3_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA3_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA3_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA3_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA3_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA3_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA3_RLC5_RB_CNTL
+#define SDMA3_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA3_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA3_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA3_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA3_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA3_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA3_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA3_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA3_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA3_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA3_RLC5_RB_BASE
+#define SDMA3_RLC5_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA3_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC5_RB_BASE_HI
+#define SDMA3_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA3_RLC5_RB_RPTR
+#define SDMA3_RLC5_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA3_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_RLC5_RB_RPTR_HI
+#define SDMA3_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA3_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_RLC5_RB_WPTR
+#define SDMA3_RLC5_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA3_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_RLC5_RB_WPTR_HI
+#define SDMA3_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA3_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_RLC5_RB_WPTR_POLL_CNTL
+#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA3_RLC5_RB_RPTR_ADDR_HI
+#define SDMA3_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC5_RB_RPTR_ADDR_LO
+#define SDMA3_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA3_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA3_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA3_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA3_RLC5_IB_CNTL
+#define SDMA3_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA3_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA3_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA3_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA3_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA3_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA3_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA3_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA3_RLC5_IB_RPTR
+#define SDMA3_RLC5_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA3_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA3_RLC5_IB_OFFSET
+#define SDMA3_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA3_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA3_RLC5_IB_BASE_LO
+#define SDMA3_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA3_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA3_RLC5_IB_BASE_HI
+#define SDMA3_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC5_IB_SIZE
+#define SDMA3_RLC5_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA3_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA3_RLC5_SKIP_CNTL
+#define SDMA3_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA3_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA3_RLC5_CONTEXT_STATUS
+#define SDMA3_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA3_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA3_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA3_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA3_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA3_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA3_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA3_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA3_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA3_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA3_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA3_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA3_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA3_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA3_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA3_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA3_RLC5_DOORBELL
+#define SDMA3_RLC5_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA3_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA3_RLC5_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA3_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA3_RLC5_STATUS
+#define SDMA3_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA3_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA3_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA3_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA3_RLC5_DOORBELL_LOG
+#define SDMA3_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA3_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA3_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA3_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA3_RLC5_WATERMARK
+#define SDMA3_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA3_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA3_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA3_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA3_RLC5_DOORBELL_OFFSET
+#define SDMA3_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA3_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA3_RLC5_CSA_ADDR_LO
+#define SDMA3_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA3_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA3_RLC5_CSA_ADDR_HI
+#define SDMA3_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC5_IB_SUB_REMAIN
+#define SDMA3_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA3_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA3_RLC5_PREEMPT
+#define SDMA3_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA3_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA3_RLC5_DUMMY_REG
+#define SDMA3_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA3_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA3_RLC5_RB_WPTR_POLL_ADDR_HI
+#define SDMA3_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC5_RB_WPTR_POLL_ADDR_LO
+#define SDMA3_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA3_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA3_RLC5_RB_AQL_CNTL
+#define SDMA3_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA3_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA3_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA3_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA3_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA3_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA3_RLC5_MINOR_PTR_UPDATE
+#define SDMA3_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA3_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA3_RLC5_MIDCMD_DATA0
+#define SDMA3_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA3_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA3_RLC5_MIDCMD_DATA1
+#define SDMA3_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA3_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA3_RLC5_MIDCMD_DATA2
+#define SDMA3_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA3_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA3_RLC5_MIDCMD_DATA3
+#define SDMA3_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA3_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA3_RLC5_MIDCMD_DATA4
+#define SDMA3_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA3_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA3_RLC5_MIDCMD_DATA5
+#define SDMA3_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA3_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA3_RLC5_MIDCMD_DATA6
+#define SDMA3_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA3_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA3_RLC5_MIDCMD_DATA7
+#define SDMA3_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA3_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA3_RLC5_MIDCMD_DATA8
+#define SDMA3_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA3_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA3_RLC5_MIDCMD_DATA9
+#define SDMA3_RLC5_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA3_RLC5_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA3_RLC5_MIDCMD_DATA10
+#define SDMA3_RLC5_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA3_RLC5_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA3_RLC5_MIDCMD_CNTL
+#define SDMA3_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA3_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA3_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA3_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA3_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA3_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA3_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA3_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA3_RLC6_RB_CNTL
+#define SDMA3_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA3_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA3_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA3_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA3_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA3_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA3_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA3_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA3_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA3_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA3_RLC6_RB_BASE
+#define SDMA3_RLC6_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA3_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC6_RB_BASE_HI
+#define SDMA3_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA3_RLC6_RB_RPTR
+#define SDMA3_RLC6_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA3_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_RLC6_RB_RPTR_HI
+#define SDMA3_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA3_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_RLC6_RB_WPTR
+#define SDMA3_RLC6_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA3_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_RLC6_RB_WPTR_HI
+#define SDMA3_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA3_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_RLC6_RB_WPTR_POLL_CNTL
+#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA3_RLC6_RB_RPTR_ADDR_HI
+#define SDMA3_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC6_RB_RPTR_ADDR_LO
+#define SDMA3_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA3_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA3_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA3_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA3_RLC6_IB_CNTL
+#define SDMA3_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA3_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA3_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA3_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA3_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA3_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA3_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA3_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA3_RLC6_IB_RPTR
+#define SDMA3_RLC6_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA3_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA3_RLC6_IB_OFFSET
+#define SDMA3_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA3_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA3_RLC6_IB_BASE_LO
+#define SDMA3_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA3_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA3_RLC6_IB_BASE_HI
+#define SDMA3_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC6_IB_SIZE
+#define SDMA3_RLC6_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA3_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA3_RLC6_SKIP_CNTL
+#define SDMA3_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA3_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA3_RLC6_CONTEXT_STATUS
+#define SDMA3_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA3_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA3_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA3_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA3_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA3_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA3_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA3_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA3_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA3_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA3_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA3_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA3_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA3_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA3_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA3_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA3_RLC6_DOORBELL
+#define SDMA3_RLC6_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA3_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA3_RLC6_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA3_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA3_RLC6_STATUS
+#define SDMA3_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA3_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA3_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA3_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA3_RLC6_DOORBELL_LOG
+#define SDMA3_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA3_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA3_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA3_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA3_RLC6_WATERMARK
+#define SDMA3_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA3_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA3_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA3_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA3_RLC6_DOORBELL_OFFSET
+#define SDMA3_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA3_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA3_RLC6_CSA_ADDR_LO
+#define SDMA3_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA3_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA3_RLC6_CSA_ADDR_HI
+#define SDMA3_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC6_IB_SUB_REMAIN
+#define SDMA3_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA3_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA3_RLC6_PREEMPT
+#define SDMA3_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA3_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA3_RLC6_DUMMY_REG
+#define SDMA3_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA3_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA3_RLC6_RB_WPTR_POLL_ADDR_HI
+#define SDMA3_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC6_RB_WPTR_POLL_ADDR_LO
+#define SDMA3_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA3_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA3_RLC6_RB_AQL_CNTL
+#define SDMA3_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA3_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA3_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA3_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA3_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA3_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA3_RLC6_MINOR_PTR_UPDATE
+#define SDMA3_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA3_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA3_RLC6_MIDCMD_DATA0
+#define SDMA3_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA3_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA3_RLC6_MIDCMD_DATA1
+#define SDMA3_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA3_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA3_RLC6_MIDCMD_DATA2
+#define SDMA3_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA3_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA3_RLC6_MIDCMD_DATA3
+#define SDMA3_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA3_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA3_RLC6_MIDCMD_DATA4
+#define SDMA3_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA3_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA3_RLC6_MIDCMD_DATA5
+#define SDMA3_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA3_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA3_RLC6_MIDCMD_DATA6
+#define SDMA3_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA3_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA3_RLC6_MIDCMD_DATA7
+#define SDMA3_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA3_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA3_RLC6_MIDCMD_DATA8
+#define SDMA3_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA3_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA3_RLC6_MIDCMD_DATA9
+#define SDMA3_RLC6_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA3_RLC6_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA3_RLC6_MIDCMD_DATA10
+#define SDMA3_RLC6_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA3_RLC6_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA3_RLC6_MIDCMD_CNTL
+#define SDMA3_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA3_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA3_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA3_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA3_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA3_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA3_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA3_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA3_RLC7_RB_CNTL
+#define SDMA3_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA3_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA3_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA3_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA3_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA3_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA3_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA3_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA3_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA3_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA3_RLC7_RB_BASE
+#define SDMA3_RLC7_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA3_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC7_RB_BASE_HI
+#define SDMA3_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA3_RLC7_RB_RPTR
+#define SDMA3_RLC7_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA3_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_RLC7_RB_RPTR_HI
+#define SDMA3_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA3_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_RLC7_RB_WPTR
+#define SDMA3_RLC7_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA3_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_RLC7_RB_WPTR_HI
+#define SDMA3_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA3_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA3_RLC7_RB_WPTR_POLL_CNTL
+#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA3_RLC7_RB_RPTR_ADDR_HI
+#define SDMA3_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC7_RB_RPTR_ADDR_LO
+#define SDMA3_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA3_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA3_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA3_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA3_RLC7_IB_CNTL
+#define SDMA3_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA3_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA3_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA3_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA3_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA3_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA3_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA3_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA3_RLC7_IB_RPTR
+#define SDMA3_RLC7_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA3_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA3_RLC7_IB_OFFSET
+#define SDMA3_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA3_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA3_RLC7_IB_BASE_LO
+#define SDMA3_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA3_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA3_RLC7_IB_BASE_HI
+#define SDMA3_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC7_IB_SIZE
+#define SDMA3_RLC7_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA3_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA3_RLC7_SKIP_CNTL
+#define SDMA3_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA3_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA3_RLC7_CONTEXT_STATUS
+#define SDMA3_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA3_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA3_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA3_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA3_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA3_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA3_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA3_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA3_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA3_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA3_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA3_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA3_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA3_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA3_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA3_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA3_RLC7_DOORBELL
+#define SDMA3_RLC7_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA3_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA3_RLC7_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA3_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA3_RLC7_STATUS
+#define SDMA3_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA3_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA3_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA3_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA3_RLC7_DOORBELL_LOG
+#define SDMA3_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA3_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA3_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA3_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA3_RLC7_WATERMARK
+#define SDMA3_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA3_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA3_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA3_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA3_RLC7_DOORBELL_OFFSET
+#define SDMA3_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA3_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA3_RLC7_CSA_ADDR_LO
+#define SDMA3_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA3_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA3_RLC7_CSA_ADDR_HI
+#define SDMA3_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC7_IB_SUB_REMAIN
+#define SDMA3_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA3_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA3_RLC7_PREEMPT
+#define SDMA3_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA3_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA3_RLC7_DUMMY_REG
+#define SDMA3_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA3_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA3_RLC7_RB_WPTR_POLL_ADDR_HI
+#define SDMA3_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA3_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA3_RLC7_RB_WPTR_POLL_ADDR_LO
+#define SDMA3_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA3_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA3_RLC7_RB_AQL_CNTL
+#define SDMA3_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA3_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA3_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA3_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA3_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA3_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA3_RLC7_MINOR_PTR_UPDATE
+#define SDMA3_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA3_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA3_RLC7_MIDCMD_DATA0
+#define SDMA3_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA3_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA3_RLC7_MIDCMD_DATA1
+#define SDMA3_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA3_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA3_RLC7_MIDCMD_DATA2
+#define SDMA3_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA3_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA3_RLC7_MIDCMD_DATA3
+#define SDMA3_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA3_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA3_RLC7_MIDCMD_DATA4
+#define SDMA3_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA3_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA3_RLC7_MIDCMD_DATA5
+#define SDMA3_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA3_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA3_RLC7_MIDCMD_DATA6
+#define SDMA3_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA3_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA3_RLC7_MIDCMD_DATA7
+#define SDMA3_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA3_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA3_RLC7_MIDCMD_DATA8
+#define SDMA3_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA3_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA3_RLC7_MIDCMD_DATA9
+#define SDMA3_RLC7_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA3_RLC7_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA3_RLC7_MIDCMD_DATA10
+#define SDMA3_RLC7_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA3_RLC7_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA3_RLC7_MIDCMD_CNTL
+#define SDMA3_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA3_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA3_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA3_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA3_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA3_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA3_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA3_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+
+
+// addressBlock: sdma0_sdma4dec
+//SDMA4_UCODE_ADDR
+#define SDMA4_UCODE_ADDR__VALUE__SHIFT 0x0
+#define SDMA4_UCODE_ADDR__VALUE_MASK 0x00003FFFL
+//SDMA4_UCODE_DATA
+#define SDMA4_UCODE_DATA__VALUE__SHIFT 0x0
+#define SDMA4_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL
+//SDMA4_VF_ENABLE
+#define SDMA4_VF_ENABLE__VF_ENABLE__SHIFT 0x0
+#define SDMA4_VF_ENABLE__VF_ENABLE_MASK 0x00000001L
+#define SDMA4_PUB_REG_TYPE0__SDMA4_UCODE_ADDR__SHIFT 0x0
+#define SDMA4_PUB_REG_TYPE0__SDMA4_UCODE_DATA__SHIFT 0x1
+#define SDMA4_PUB_REG_TYPE0__SDMA4_UCODE_ADDR_MASK 0x00000001L
+#define SDMA4_PUB_REG_TYPE0__SDMA4_UCODE_DATA_MASK 0x00000002L
+//SDMA4_CONTEXT_GROUP_BOUNDARY
+#define SDMA4_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0
+#define SDMA4_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL
+//SDMA4_POWER_CNTL
+#define SDMA4_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0
+#define SDMA4_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1
+#define SDMA4_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2
+#define SDMA4_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3
+#define SDMA4_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
+#define SDMA4_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9
+#define SDMA4_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
+#define SDMA4_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb
+#define SDMA4_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc
+#define SDMA4_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a
+#define SDMA4_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L
+#define SDMA4_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L
+#define SDMA4_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L
+#define SDMA4_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L
+#define SDMA4_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L
+#define SDMA4_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L
+#define SDMA4_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L
+#define SDMA4_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L
+#define SDMA4_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L
+#define SDMA4_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
+//SDMA4_CLK_CTRL
+#define SDMA4_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define SDMA4_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define SDMA4_CLK_CTRL__RESERVED__SHIFT 0xc
+#define SDMA4_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define SDMA4_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define SDMA4_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define SDMA4_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define SDMA4_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define SDMA4_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define SDMA4_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define SDMA4_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define SDMA4_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define SDMA4_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define SDMA4_CLK_CTRL__RESERVED_MASK 0x00FFF000L
+#define SDMA4_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define SDMA4_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define SDMA4_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define SDMA4_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define SDMA4_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define SDMA4_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define SDMA4_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define SDMA4_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//SDMA4_CNTL
+#define SDMA4_CNTL__TRAP_ENABLE__SHIFT 0x0
+#define SDMA4_CNTL__UTC_L1_ENABLE__SHIFT 0x1
+#define SDMA4_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
+#define SDMA4_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
+#define SDMA4_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
+#define SDMA4_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5
+#define SDMA4_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x6
+#define SDMA4_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11
+#define SDMA4_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
+#define SDMA4_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
+#define SDMA4_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
+#define SDMA4_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e
+#define SDMA4_CNTL__TRAP_ENABLE_MASK 0x00000001L
+#define SDMA4_CNTL__UTC_L1_ENABLE_MASK 0x00000002L
+#define SDMA4_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L
+#define SDMA4_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L
+#define SDMA4_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA4_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L
+#define SDMA4_CNTL__MIDCMD_EXPIRE_ENABLE_MASK 0x00000040L
+#define SDMA4_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L
+#define SDMA4_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L
+#define SDMA4_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L
+#define SDMA4_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L
+#define SDMA4_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L
+//SDMA4_CHICKEN_BITS
+#define SDMA4_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
+#define SDMA4_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
+#define SDMA4_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
+#define SDMA4_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8
+#define SDMA4_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
+#define SDMA4_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
+#define SDMA4_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11
+#define SDMA4_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
+#define SDMA4_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
+#define SDMA4_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19
+#define SDMA4_CHICKEN_BITS__SRAM_FGCG_ENABLE__SHIFT 0x1a
+#define SDMA4_CHICKEN_BITS__RESERVED__SHIFT 0x1b
+#define SDMA4_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L
+#define SDMA4_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L
+#define SDMA4_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L
+#define SDMA4_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L
+#define SDMA4_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L
+#define SDMA4_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L
+#define SDMA4_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L
+#define SDMA4_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L
+#define SDMA4_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L
+#define SDMA4_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L
+#define SDMA4_CHICKEN_BITS__SRAM_FGCG_ENABLE_MASK 0x04000000L
+#define SDMA4_CHICKEN_BITS__RESERVED_MASK 0xF8000000L
+//SDMA4_GB_ADDR_CONFIG
+#define SDMA4_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define SDMA4_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define SDMA4_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define SDMA4_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
+#define SDMA4_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
+#define SDMA4_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
+#define SDMA4_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define SDMA4_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
+#define SDMA4_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
+#define SDMA4_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
+//SDMA4_GB_ADDR_CONFIG_READ
+#define SDMA4_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0
+#define SDMA4_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define SDMA4_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define SDMA4_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc
+#define SDMA4_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13
+#define SDMA4_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L
+#define SDMA4_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define SDMA4_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
+#define SDMA4_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L
+#define SDMA4_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L
+//SDMA4_RB_RPTR_FETCH_HI
+#define SDMA4_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0
+#define SDMA4_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_SEM_WAIT_FAIL_TIMER_CNTL
+#define SDMA4_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
+#define SDMA4_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL
+//SDMA4_RB_RPTR_FETCH
+#define SDMA4_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
+#define SDMA4_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL
+//SDMA4_IB_OFFSET_FETCH
+#define SDMA4_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
+#define SDMA4_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL
+//SDMA4_PROGRAM
+#define SDMA4_PROGRAM__STREAM__SHIFT 0x0
+#define SDMA4_PROGRAM__STREAM_MASK 0xFFFFFFFFL
+//SDMA4_STATUS_REG
+#define SDMA4_STATUS_REG__IDLE__SHIFT 0x0
+#define SDMA4_STATUS_REG__REG_IDLE__SHIFT 0x1
+#define SDMA4_STATUS_REG__RB_EMPTY__SHIFT 0x2
+#define SDMA4_STATUS_REG__RB_FULL__SHIFT 0x3
+#define SDMA4_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
+#define SDMA4_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
+#define SDMA4_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
+#define SDMA4_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
+#define SDMA4_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
+#define SDMA4_STATUS_REG__INSIDE_IB__SHIFT 0x9
+#define SDMA4_STATUS_REG__EX_IDLE__SHIFT 0xa
+#define SDMA4_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
+#define SDMA4_STATUS_REG__PACKET_READY__SHIFT 0xc
+#define SDMA4_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
+#define SDMA4_STATUS_REG__SRBM_IDLE__SHIFT 0xe
+#define SDMA4_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
+#define SDMA4_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10
+#define SDMA4_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
+#define SDMA4_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
+#define SDMA4_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
+#define SDMA4_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14
+#define SDMA4_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
+#define SDMA4_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
+#define SDMA4_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
+#define SDMA4_STATUS_REG__SEM_IDLE__SHIFT 0x1a
+#define SDMA4_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
+#define SDMA4_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
+#define SDMA4_STATUS_REG__INT_IDLE__SHIFT 0x1e
+#define SDMA4_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
+#define SDMA4_STATUS_REG__IDLE_MASK 0x00000001L
+#define SDMA4_STATUS_REG__REG_IDLE_MASK 0x00000002L
+#define SDMA4_STATUS_REG__RB_EMPTY_MASK 0x00000004L
+#define SDMA4_STATUS_REG__RB_FULL_MASK 0x00000008L
+#define SDMA4_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L
+#define SDMA4_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L
+#define SDMA4_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L
+#define SDMA4_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L
+#define SDMA4_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L
+#define SDMA4_STATUS_REG__INSIDE_IB_MASK 0x00000200L
+#define SDMA4_STATUS_REG__EX_IDLE_MASK 0x00000400L
+#define SDMA4_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L
+#define SDMA4_STATUS_REG__PACKET_READY_MASK 0x00001000L
+#define SDMA4_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L
+#define SDMA4_STATUS_REG__SRBM_IDLE_MASK 0x00004000L
+#define SDMA4_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L
+#define SDMA4_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L
+#define SDMA4_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L
+#define SDMA4_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L
+#define SDMA4_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L
+#define SDMA4_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L
+#define SDMA4_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L
+#define SDMA4_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L
+#define SDMA4_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L
+#define SDMA4_STATUS_REG__SEM_IDLE_MASK 0x04000000L
+#define SDMA4_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L
+#define SDMA4_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L
+#define SDMA4_STATUS_REG__INT_IDLE_MASK 0x40000000L
+#define SDMA4_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L
+//SDMA4_STATUS1_REG
+#define SDMA4_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
+#define SDMA4_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
+#define SDMA4_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
+#define SDMA4_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
+#define SDMA4_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
+#define SDMA4_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
+#define SDMA4_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
+#define SDMA4_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9
+#define SDMA4_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
+#define SDMA4_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
+#define SDMA4_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
+#define SDMA4_STATUS1_REG__EX_START__SHIFT 0xf
+#define SDMA4_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
+#define SDMA4_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
+#define SDMA4_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L
+#define SDMA4_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L
+#define SDMA4_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L
+#define SDMA4_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L
+#define SDMA4_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L
+#define SDMA4_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L
+#define SDMA4_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L
+#define SDMA4_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L
+#define SDMA4_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L
+#define SDMA4_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L
+#define SDMA4_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L
+#define SDMA4_STATUS1_REG__EX_START_MASK 0x00008000L
+#define SDMA4_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L
+#define SDMA4_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L
+//SDMA4_RD_BURST_CNTL
+#define SDMA4_RD_BURST_CNTL__RD_BURST__SHIFT 0x0
+#define SDMA4_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2
+#define SDMA4_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L
+#define SDMA4_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL
+//SDMA4_HBM_PAGE_CONFIG
+#define SDMA4_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0
+#define SDMA4_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L
+//SDMA4_UCODE_CHECKSUM
+#define SDMA4_UCODE_CHECKSUM__DATA__SHIFT 0x0
+#define SDMA4_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL
+//SDMA4_F32_CNTL
+#define SDMA4_F32_CNTL__HALT__SHIFT 0x0
+#define SDMA4_F32_CNTL__STEP__SHIFT 0x1
+#define SDMA4_F32_CNTL__RESET__SHIFT 0x8
+#define SDMA4_F32_CNTL__HALT_MASK 0x00000001L
+#define SDMA4_F32_CNTL__STEP_MASK 0x00000002L
+#define SDMA4_F32_CNTL__RESET_MASK 0x00000100L
+//SDMA4_FREEZE
+#define SDMA4_FREEZE__PREEMPT__SHIFT 0x0
+#define SDMA4_FREEZE__FREEZE__SHIFT 0x4
+#define SDMA4_FREEZE__FROZEN__SHIFT 0x5
+#define SDMA4_FREEZE__F32_FREEZE__SHIFT 0x6
+#define SDMA4_FREEZE__PREEMPT_MASK 0x00000001L
+#define SDMA4_FREEZE__FREEZE_MASK 0x00000010L
+#define SDMA4_FREEZE__FROZEN_MASK 0x00000020L
+#define SDMA4_FREEZE__F32_FREEZE_MASK 0x00000040L
+//SDMA4_PHASE0_QUANTUM
+#define SDMA4_PHASE0_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA4_PHASE0_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA4_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA4_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL
+#define SDMA4_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L
+#define SDMA4_PHASE0_QUANTUM__PREFER_MASK 0x40000000L
+//SDMA4_PHASE1_QUANTUM
+#define SDMA4_PHASE1_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA4_PHASE1_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA4_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA4_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL
+#define SDMA4_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L
+#define SDMA4_PHASE1_QUANTUM__PREFER_MASK 0x40000000L
+//CC_SDMA4_EDC_CONFIG
+#define CC_SDMA4_EDC_CONFIG__DIS_EDC__SHIFT 0x1
+#define CC_SDMA4_EDC_CONFIG__DIS_EDC_MASK 0x00000002L
+//SDMA4_BA_THRESHOLD
+#define SDMA4_BA_THRESHOLD__READ_THRES__SHIFT 0x0
+#define SDMA4_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10
+#define SDMA4_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL
+#define SDMA4_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L
+//SDMA4_ID
+#define SDMA4_ID__DEVICE_ID__SHIFT 0x0
+#define SDMA4_ID__DEVICE_ID_MASK 0x000000FFL
+//SDMA4_VERSION
+#define SDMA4_VERSION__MINVER__SHIFT 0x0
+#define SDMA4_VERSION__MAJVER__SHIFT 0x8
+#define SDMA4_VERSION__REV__SHIFT 0x10
+#define SDMA4_VERSION__MINVER_MASK 0x0000007FL
+#define SDMA4_VERSION__MAJVER_MASK 0x00007F00L
+#define SDMA4_VERSION__REV_MASK 0x003F0000L
+//SDMA4_EDC_COUNTER
+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x0
+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x2
+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x4
+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0x6
+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0x8
+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xa
+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xc
+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe
+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0x10
+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x12
+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x14
+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x16
+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x18
+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x1a
+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x1c
+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x1e
+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000003L
+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x0000000CL
+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000030L
+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x000000C0L
+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000300L
+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00000C00L
+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00003000L
+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x0000C000L
+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00030000L
+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x000C0000L
+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00300000L
+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00C00000L
+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x03000000L
+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x0C000000L
+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x30000000L
+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0xC0000000L
+//SDMA4_EDC_COUNTER2
+#define SDMA4_EDC_COUNTER2__SDMA_UCODE_BUF_SED__SHIFT 0x0
+#define SDMA4_EDC_COUNTER2__SDMA_RB_CMD_BUF_SED__SHIFT 0x2
+#define SDMA4_EDC_COUNTER2__SDMA_IB_CMD_BUF_SED__SHIFT 0x4
+#define SDMA4_EDC_COUNTER2__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x6
+#define SDMA4_EDC_COUNTER2__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x8
+#define SDMA4_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED__SHIFT 0xa
+#define SDMA4_EDC_COUNTER2__SDMA_DATA_LUT_FIFO_SED__SHIFT 0xc
+#define SDMA4_EDC_COUNTER2__SDMA_SPLIT_DATA_BUF_SED__SHIFT 0xe
+#define SDMA4_EDC_COUNTER2__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10
+#define SDMA4_EDC_COUNTER2__SDMA_MC_RDRET_BUF_SED__SHIFT 0x12
+#define SDMA4_EDC_COUNTER2__SDMA_UCODE_BUF_SED_MASK 0x00000003L
+#define SDMA4_EDC_COUNTER2__SDMA_RB_CMD_BUF_SED_MASK 0x0000000CL
+#define SDMA4_EDC_COUNTER2__SDMA_IB_CMD_BUF_SED_MASK 0x00000030L
+#define SDMA4_EDC_COUNTER2__SDMA_UTCL1_RD_FIFO_SED_MASK 0x000000C0L
+#define SDMA4_EDC_COUNTER2__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000300L
+#define SDMA4_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED_MASK 0x00000C00L
+#define SDMA4_EDC_COUNTER2__SDMA_DATA_LUT_FIFO_SED_MASK 0x00003000L
+#define SDMA4_EDC_COUNTER2__SDMA_SPLIT_DATA_BUF_SED_MASK 0x0000C000L
+#define SDMA4_EDC_COUNTER2__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00030000L
+#define SDMA4_EDC_COUNTER2__SDMA_MC_RDRET_BUF_SED_MASK 0x000C0000L
+//SDMA4_STATUS2_REG
+#define SDMA4_STATUS2_REG__ID__SHIFT 0x0
+#define SDMA4_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3
+#define SDMA4_STATUS2_REG__CMD_OP__SHIFT 0x10
+#define SDMA4_STATUS2_REG__ID_MASK 0x00000007L
+#define SDMA4_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L
+#define SDMA4_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L
+//SDMA4_ATOMIC_CNTL
+#define SDMA4_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0
+#define SDMA4_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f
+#define SDMA4_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL
+#define SDMA4_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L
+//SDMA4_ATOMIC_PREOP_LO
+#define SDMA4_ATOMIC_PREOP_LO__DATA__SHIFT 0x0
+#define SDMA4_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL
+//SDMA4_ATOMIC_PREOP_HI
+#define SDMA4_ATOMIC_PREOP_HI__DATA__SHIFT 0x0
+#define SDMA4_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL
+//SDMA4_UTCL1_CNTL
+#define SDMA4_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0
+#define SDMA4_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1
+#define SDMA4_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb
+#define SDMA4_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe
+#define SDMA4_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18
+#define SDMA4_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
+#define SDMA4_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L
+#define SDMA4_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL
+#define SDMA4_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L
+#define SDMA4_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L
+#define SDMA4_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L
+#define SDMA4_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L
+//SDMA4_UTCL1_WATERMK
+#define SDMA4_UTCL1_WATERMK__REQ_WATERMK__SHIFT 0x0
+#define SDMA4_UTCL1_WATERMK__REQ_DEPTH__SHIFT 0x3
+#define SDMA4_UTCL1_WATERMK__PAGE_WATERMK__SHIFT 0x5
+#define SDMA4_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x8
+#define SDMA4_UTCL1_WATERMK__RESERVED__SHIFT 0x10
+#define SDMA4_UTCL1_WATERMK__REQ_WATERMK_MASK 0x00000007L
+#define SDMA4_UTCL1_WATERMK__REQ_DEPTH_MASK 0x00000018L
+#define SDMA4_UTCL1_WATERMK__PAGE_WATERMK_MASK 0x000000E0L
+#define SDMA4_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x0000FF00L
+#define SDMA4_UTCL1_WATERMK__RESERVED_MASK 0xFFFF0000L
+//SDMA4_UTCL1_RD_STATUS
+#define SDMA4_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
+#define SDMA4_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
+#define SDMA4_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
+#define SDMA4_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
+#define SDMA4_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
+#define SDMA4_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
+#define SDMA4_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
+#define SDMA4_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
+#define SDMA4_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
+#define SDMA4_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
+#define SDMA4_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
+#define SDMA4_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
+#define SDMA4_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
+#define SDMA4_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
+#define SDMA4_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
+#define SDMA4_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
+#define SDMA4_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
+#define SDMA4_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
+#define SDMA4_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12
+#define SDMA4_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13
+#define SDMA4_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14
+#define SDMA4_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15
+#define SDMA4_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16
+#define SDMA4_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a
+#define SDMA4_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
+#define SDMA4_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e
+#define SDMA4_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f
+#define SDMA4_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
+#define SDMA4_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L
+#define SDMA4_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L
+#define SDMA4_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L
+#define SDMA4_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L
+#define SDMA4_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L
+#define SDMA4_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L
+#define SDMA4_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L
+#define SDMA4_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L
+#define SDMA4_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L
+#define SDMA4_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L
+#define SDMA4_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L
+#define SDMA4_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L
+#define SDMA4_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L
+#define SDMA4_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L
+#define SDMA4_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L
+#define SDMA4_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L
+#define SDMA4_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L
+#define SDMA4_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L
+#define SDMA4_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L
+#define SDMA4_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L
+#define SDMA4_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L
+#define SDMA4_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L
+#define SDMA4_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L
+#define SDMA4_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L
+#define SDMA4_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L
+#define SDMA4_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L
+//SDMA4_UTCL1_WR_STATUS
+#define SDMA4_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
+#define SDMA4_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
+#define SDMA4_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
+#define SDMA4_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
+#define SDMA4_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
+#define SDMA4_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
+#define SDMA4_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
+#define SDMA4_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
+#define SDMA4_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
+#define SDMA4_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
+#define SDMA4_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
+#define SDMA4_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
+#define SDMA4_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
+#define SDMA4_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
+#define SDMA4_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
+#define SDMA4_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
+#define SDMA4_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
+#define SDMA4_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
+#define SDMA4_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12
+#define SDMA4_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13
+#define SDMA4_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14
+#define SDMA4_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15
+#define SDMA4_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16
+#define SDMA4_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19
+#define SDMA4_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c
+#define SDMA4_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
+#define SDMA4_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e
+#define SDMA4_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f
+#define SDMA4_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
+#define SDMA4_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L
+#define SDMA4_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L
+#define SDMA4_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L
+#define SDMA4_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L
+#define SDMA4_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L
+#define SDMA4_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L
+#define SDMA4_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L
+#define SDMA4_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L
+#define SDMA4_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L
+#define SDMA4_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L
+#define SDMA4_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L
+#define SDMA4_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L
+#define SDMA4_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L
+#define SDMA4_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L
+#define SDMA4_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L
+#define SDMA4_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L
+#define SDMA4_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L
+#define SDMA4_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L
+#define SDMA4_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L
+#define SDMA4_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L
+#define SDMA4_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L
+#define SDMA4_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L
+#define SDMA4_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L
+#define SDMA4_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L
+#define SDMA4_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L
+#define SDMA4_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L
+#define SDMA4_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L
+//SDMA4_UTCL1_INV0
+#define SDMA4_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0
+#define SDMA4_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1
+#define SDMA4_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2
+#define SDMA4_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3
+#define SDMA4_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4
+#define SDMA4_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5
+#define SDMA4_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6
+#define SDMA4_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7
+#define SDMA4_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8
+#define SDMA4_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9
+#define SDMA4_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa
+#define SDMA4_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb
+#define SDMA4_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc
+#define SDMA4_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c
+#define SDMA4_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L
+#define SDMA4_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L
+#define SDMA4_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L
+#define SDMA4_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L
+#define SDMA4_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L
+#define SDMA4_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L
+#define SDMA4_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L
+#define SDMA4_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L
+#define SDMA4_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L
+#define SDMA4_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L
+#define SDMA4_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L
+#define SDMA4_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L
+#define SDMA4_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L
+#define SDMA4_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L
+//SDMA4_UTCL1_INV1
+#define SDMA4_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0
+#define SDMA4_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL
+//SDMA4_UTCL1_INV2
+#define SDMA4_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0
+#define SDMA4_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL
+//SDMA4_UTCL1_RD_XNACK0
+#define SDMA4_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
+#define SDMA4_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
+//SDMA4_UTCL1_RD_XNACK1
+#define SDMA4_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
+#define SDMA4_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4
+#define SDMA4_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8
+#define SDMA4_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a
+#define SDMA4_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
+#define SDMA4_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L
+#define SDMA4_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
+#define SDMA4_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L
+//SDMA4_UTCL1_WR_XNACK0
+#define SDMA4_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
+#define SDMA4_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
+//SDMA4_UTCL1_WR_XNACK1
+#define SDMA4_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
+#define SDMA4_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4
+#define SDMA4_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8
+#define SDMA4_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a
+#define SDMA4_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
+#define SDMA4_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L
+#define SDMA4_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
+#define SDMA4_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L
+//SDMA4_UTCL1_TIMEOUT
+#define SDMA4_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0
+#define SDMA4_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10
+#define SDMA4_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL
+#define SDMA4_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L
+//SDMA4_UTCL1_PAGE
+#define SDMA4_UTCL1_PAGE__VM_HOLE__SHIFT 0x0
+#define SDMA4_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1
+#define SDMA4_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6
+#define SDMA4_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9
+#define SDMA4_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L
+#define SDMA4_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL
+#define SDMA4_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L
+#define SDMA4_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L
+//SDMA4_POWER_CNTL_IDLE
+#define SDMA4_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0
+#define SDMA4_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10
+#define SDMA4_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18
+#define SDMA4_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL
+#define SDMA4_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L
+#define SDMA4_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L
+//SDMA4_RELAX_ORDERING_LUT
+#define SDMA4_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0
+#define SDMA4_RELAX_ORDERING_LUT__COPY__SHIFT 0x1
+#define SDMA4_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2
+#define SDMA4_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3
+#define SDMA4_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4
+#define SDMA4_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5
+#define SDMA4_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6
+#define SDMA4_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8
+#define SDMA4_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9
+#define SDMA4_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa
+#define SDMA4_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb
+#define SDMA4_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc
+#define SDMA4_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd
+#define SDMA4_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe
+#define SDMA4_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b
+#define SDMA4_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c
+#define SDMA4_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
+#define SDMA4_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e
+#define SDMA4_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f
+#define SDMA4_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L
+#define SDMA4_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L
+#define SDMA4_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L
+#define SDMA4_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L
+#define SDMA4_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L
+#define SDMA4_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L
+#define SDMA4_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L
+#define SDMA4_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L
+#define SDMA4_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L
+#define SDMA4_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L
+#define SDMA4_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L
+#define SDMA4_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L
+#define SDMA4_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L
+#define SDMA4_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L
+#define SDMA4_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L
+#define SDMA4_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L
+#define SDMA4_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L
+#define SDMA4_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L
+#define SDMA4_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L
+//SDMA4_CHICKEN_BITS_2
+#define SDMA4_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0
+#define SDMA4_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT 0x4
+#define SDMA4_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL
+#define SDMA4_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK 0x00000010L
+//SDMA4_STATUS3_REG
+#define SDMA4_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0
+#define SDMA4_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10
+#define SDMA4_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14
+#define SDMA4_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15
+#define SDMA4_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16
+#define SDMA4_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL
+#define SDMA4_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L
+#define SDMA4_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L
+#define SDMA4_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L
+#define SDMA4_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L
+//SDMA4_PHYSICAL_ADDR_LO
+#define SDMA4_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0
+#define SDMA4_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1
+#define SDMA4_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2
+#define SDMA4_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc
+#define SDMA4_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L
+#define SDMA4_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L
+#define SDMA4_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L
+#define SDMA4_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L
+//SDMA4_PHYSICAL_ADDR_HI
+#define SDMA4_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA4_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL
+//SDMA4_PHASE2_QUANTUM
+#define SDMA4_PHASE2_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA4_PHASE2_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA4_PHASE2_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA4_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL
+#define SDMA4_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L
+#define SDMA4_PHASE2_QUANTUM__PREFER_MASK 0x40000000L
+//SDMA4_ERROR_LOG
+#define SDMA4_ERROR_LOG__OVERRIDE__SHIFT 0x0
+#define SDMA4_ERROR_LOG__STATUS__SHIFT 0x10
+#define SDMA4_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL
+#define SDMA4_ERROR_LOG__STATUS_MASK 0xFFFF0000L
+//SDMA4_PUB_DUMMY_REG0
+#define SDMA4_PUB_DUMMY_REG0__VALUE__SHIFT 0x0
+#define SDMA4_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL
+//SDMA4_PUB_DUMMY_REG1
+#define SDMA4_PUB_DUMMY_REG1__VALUE__SHIFT 0x0
+#define SDMA4_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL
+//SDMA4_PUB_DUMMY_REG2
+#define SDMA4_PUB_DUMMY_REG2__VALUE__SHIFT 0x0
+#define SDMA4_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL
+//SDMA4_PUB_DUMMY_REG3
+#define SDMA4_PUB_DUMMY_REG3__VALUE__SHIFT 0x0
+#define SDMA4_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL
+//SDMA4_F32_COUNTER
+#define SDMA4_F32_COUNTER__VALUE__SHIFT 0x0
+#define SDMA4_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL
+//SDMA4_PERFCNT_PERFCOUNTER0_CFG
+#define SDMA4_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define SDMA4_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define SDMA4_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define SDMA4_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define SDMA4_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define SDMA4_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define SDMA4_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define SDMA4_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define SDMA4_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define SDMA4_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//SDMA4_PERFCNT_PERFCOUNTER1_CFG
+#define SDMA4_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define SDMA4_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define SDMA4_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define SDMA4_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define SDMA4_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define SDMA4_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define SDMA4_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define SDMA4_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define SDMA4_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define SDMA4_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL
+#define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+//SDMA4_PERFCNT_MISC_CNTL
+#define SDMA4_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x0
+#define SDMA4_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000FFFFL
+//SDMA4_PERFCNT_PERFCOUNTER_LO
+#define SDMA4_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define SDMA4_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//SDMA4_PERFCNT_PERFCOUNTER_HI
+#define SDMA4_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define SDMA4_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define SDMA4_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define SDMA4_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//SDMA4_CRD_CNTL
+#define SDMA4_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7
+#define SDMA4_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd
+#define SDMA4_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L
+#define SDMA4_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L
+//SDMA4_ULV_CNTL
+#define SDMA4_ULV_CNTL__HYSTERESIS__SHIFT 0x0
+#define SDMA4_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b
+#define SDMA4_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c
+#define SDMA4_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
+#define SDMA4_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e
+#define SDMA4_ULV_CNTL__ULV_STATUS__SHIFT 0x1f
+#define SDMA4_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL
+#define SDMA4_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L
+#define SDMA4_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L
+#define SDMA4_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L
+#define SDMA4_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L
+#define SDMA4_ULV_CNTL__ULV_STATUS_MASK 0x80000000L
+//SDMA4_EA_DBIT_ADDR_DATA
+#define SDMA4_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0
+#define SDMA4_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL
+//SDMA4_EA_DBIT_ADDR_INDEX
+#define SDMA4_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0
+#define SDMA4_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L
+//SDMA4_STATUS4_REG
+#define SDMA4_STATUS4_REG__IDLE__SHIFT 0x0
+#define SDMA4_STATUS4_REG__IH_OUTSTANDING__SHIFT 0x2
+#define SDMA4_STATUS4_REG__SEM_OUTSTANDING__SHIFT 0x3
+#define SDMA4_STATUS4_REG__MMHUB_RD_OUTSTANDING__SHIFT 0x4
+#define SDMA4_STATUS4_REG__MMHUB_WR_OUTSTANDING__SHIFT 0x5
+#define SDMA4_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT 0x6
+#define SDMA4_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT 0x7
+#define SDMA4_STATUS4_REG__REG_POLLING__SHIFT 0x8
+#define SDMA4_STATUS4_REG__MEM_POLLING__SHIFT 0x9
+#define SDMA4_STATUS4_REG__UTCL2_RD_XNACK__SHIFT 0xa
+#define SDMA4_STATUS4_REG__UTCL2_WR_XNACK__SHIFT 0xc
+#define SDMA4_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT 0xe
+#define SDMA4_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT 0x12
+#define SDMA4_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT 0x13
+#define SDMA4_STATUS4_REG__IDLE_MASK 0x00000001L
+#define SDMA4_STATUS4_REG__IH_OUTSTANDING_MASK 0x00000004L
+#define SDMA4_STATUS4_REG__SEM_OUTSTANDING_MASK 0x00000008L
+#define SDMA4_STATUS4_REG__MMHUB_RD_OUTSTANDING_MASK 0x00000010L
+#define SDMA4_STATUS4_REG__MMHUB_WR_OUTSTANDING_MASK 0x00000020L
+#define SDMA4_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK 0x00000040L
+#define SDMA4_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK 0x00000080L
+#define SDMA4_STATUS4_REG__REG_POLLING_MASK 0x00000100L
+#define SDMA4_STATUS4_REG__MEM_POLLING_MASK 0x00000200L
+#define SDMA4_STATUS4_REG__UTCL2_RD_XNACK_MASK 0x00000C00L
+#define SDMA4_STATUS4_REG__UTCL2_WR_XNACK_MASK 0x00003000L
+#define SDMA4_STATUS4_REG__ACTIVE_QUEUE_ID_MASK 0x0003C000L
+#define SDMA4_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK 0x00040000L
+#define SDMA4_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK 0x00080000L
+//SDMA4_SCRATCH_RAM_DATA
+#define SDMA4_SCRATCH_RAM_DATA__DATA__SHIFT 0x0
+#define SDMA4_SCRATCH_RAM_DATA__DATA_MASK 0xFFFFFFFFL
+//SDMA4_SCRATCH_RAM_ADDR
+#define SDMA4_SCRATCH_RAM_ADDR__ADDR__SHIFT 0x0
+#define SDMA4_SCRATCH_RAM_ADDR__ADDR_MASK 0x0000007FL
+//SDMA4_CE_CTRL
+#define SDMA4_CE_CTRL__RD_LUT_WATERMARK__SHIFT 0x0
+#define SDMA4_CE_CTRL__RD_LUT_DEPTH__SHIFT 0x3
+#define SDMA4_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT 0x5
+#define SDMA4_CE_CTRL__RESERVED__SHIFT 0x8
+#define SDMA4_CE_CTRL__RD_LUT_WATERMARK_MASK 0x00000007L
+#define SDMA4_CE_CTRL__RD_LUT_DEPTH_MASK 0x00000018L
+#define SDMA4_CE_CTRL__WR_AFIFO_WATERMARK_MASK 0x000000E0L
+#define SDMA4_CE_CTRL__RESERVED_MASK 0xFFFFFF00L
+//SDMA4_RAS_STATUS
+#define SDMA4_RAS_STATUS__RB_FETCH_ECC__SHIFT 0x0
+#define SDMA4_RAS_STATUS__IB_FETCH_ECC__SHIFT 0x1
+#define SDMA4_RAS_STATUS__F32_DATA_ECC__SHIFT 0x2
+#define SDMA4_RAS_STATUS__SEM_WPTR_ATOMIC_ECC__SHIFT 0x3
+#define SDMA4_RAS_STATUS__COPY_DATA_ECC__SHIFT 0x4
+#define SDMA4_RAS_STATUS__SRAM_ECC__SHIFT 0x5
+#define SDMA4_RAS_STATUS__RB_FETCH_NACK_GEN_ERR__SHIFT 0x8
+#define SDMA4_RAS_STATUS__IB_FETCH_NACK_GEN_ERR__SHIFT 0x9
+#define SDMA4_RAS_STATUS__F32_DATA_NACK_GEN_ERR__SHIFT 0xa
+#define SDMA4_RAS_STATUS__COPY_DATA_NACK_GEN_ERR__SHIFT 0xb
+#define SDMA4_RAS_STATUS__WRRET_DATA_NACK_GEN_ERR__SHIFT 0xc
+#define SDMA4_RAS_STATUS__WPTR_RPTR_ATOMIC_NACK_GEN_ERR__SHIFT 0xd
+#define SDMA4_RAS_STATUS__RB_FETCH_ECC_MASK 0x00000001L
+#define SDMA4_RAS_STATUS__IB_FETCH_ECC_MASK 0x00000002L
+#define SDMA4_RAS_STATUS__F32_DATA_ECC_MASK 0x00000004L
+#define SDMA4_RAS_STATUS__SEM_WPTR_ATOMIC_ECC_MASK 0x00000008L
+#define SDMA4_RAS_STATUS__COPY_DATA_ECC_MASK 0x00000010L
+#define SDMA4_RAS_STATUS__SRAM_ECC_MASK 0x00000020L
+#define SDMA4_RAS_STATUS__RB_FETCH_NACK_GEN_ERR_MASK 0x00000100L
+#define SDMA4_RAS_STATUS__IB_FETCH_NACK_GEN_ERR_MASK 0x00000200L
+#define SDMA4_RAS_STATUS__F32_DATA_NACK_GEN_ERR_MASK 0x00000400L
+#define SDMA4_RAS_STATUS__COPY_DATA_NACK_GEN_ERR_MASK 0x00000800L
+#define SDMA4_RAS_STATUS__WRRET_DATA_NACK_GEN_ERR_MASK 0x00001000L
+#define SDMA4_RAS_STATUS__WPTR_RPTR_ATOMIC_NACK_GEN_ERR_MASK 0x00002000L
+//SDMA4_CLK_STATUS
+#define SDMA4_CLK_STATUS__DYN_CLK__SHIFT 0x0
+#define SDMA4_CLK_STATUS__PTR_CLK__SHIFT 0x1
+#define SDMA4_CLK_STATUS__REG_CLK__SHIFT 0x2
+#define SDMA4_CLK_STATUS__F32_CLK__SHIFT 0x3
+#define SDMA4_CLK_STATUS__DYN_CLK_MASK 0x00000001L
+#define SDMA4_CLK_STATUS__PTR_CLK_MASK 0x00000002L
+#define SDMA4_CLK_STATUS__REG_CLK_MASK 0x00000004L
+#define SDMA4_CLK_STATUS__F32_CLK_MASK 0x00000008L
+//SDMA4_GFX_RB_CNTL
+#define SDMA4_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA4_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA4_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA4_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA4_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA4_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA4_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA4_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA4_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA4_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA4_GFX_RB_BASE
+#define SDMA4_GFX_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA4_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_GFX_RB_BASE_HI
+#define SDMA4_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA4_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA4_GFX_RB_RPTR
+#define SDMA4_GFX_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA4_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_GFX_RB_RPTR_HI
+#define SDMA4_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA4_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_GFX_RB_WPTR
+#define SDMA4_GFX_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA4_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_GFX_RB_WPTR_HI
+#define SDMA4_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA4_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_GFX_RB_WPTR_POLL_CNTL
+#define SDMA4_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA4_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA4_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA4_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA4_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA4_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA4_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA4_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA4_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA4_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA4_GFX_RB_RPTR_ADDR_HI
+#define SDMA4_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA4_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_GFX_RB_RPTR_ADDR_LO
+#define SDMA4_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA4_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA4_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA4_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA4_GFX_IB_CNTL
+#define SDMA4_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA4_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA4_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA4_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA4_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA4_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA4_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA4_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA4_GFX_IB_RPTR
+#define SDMA4_GFX_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA4_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA4_GFX_IB_OFFSET
+#define SDMA4_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA4_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA4_GFX_IB_BASE_LO
+#define SDMA4_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA4_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA4_GFX_IB_BASE_HI
+#define SDMA4_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA4_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_GFX_IB_SIZE
+#define SDMA4_GFX_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA4_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA4_GFX_SKIP_CNTL
+#define SDMA4_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA4_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA4_GFX_CONTEXT_STATUS
+#define SDMA4_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA4_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA4_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA4_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA4_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA4_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA4_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA4_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA4_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA4_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA4_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA4_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA4_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA4_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA4_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA4_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA4_GFX_DOORBELL
+#define SDMA4_GFX_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA4_GFX_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA4_GFX_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA4_GFX_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA4_GFX_CONTEXT_CNTL
+#define SDMA4_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
+#define SDMA4_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18
+#define SDMA4_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L
+#define SDMA4_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0x0F000000L
+//SDMA4_GFX_STATUS
+#define SDMA4_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA4_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA4_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA4_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA4_GFX_DOORBELL_LOG
+#define SDMA4_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA4_GFX_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA4_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA4_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA4_GFX_WATERMARK
+#define SDMA4_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA4_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA4_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA4_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA4_GFX_DOORBELL_OFFSET
+#define SDMA4_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA4_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA4_GFX_CSA_ADDR_LO
+#define SDMA4_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA4_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA4_GFX_CSA_ADDR_HI
+#define SDMA4_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA4_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_GFX_IB_SUB_REMAIN
+#define SDMA4_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA4_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA4_GFX_PREEMPT
+#define SDMA4_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA4_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA4_GFX_DUMMY_REG
+#define SDMA4_GFX_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA4_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA4_GFX_RB_WPTR_POLL_ADDR_HI
+#define SDMA4_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA4_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_GFX_RB_WPTR_POLL_ADDR_LO
+#define SDMA4_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA4_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA4_GFX_RB_AQL_CNTL
+#define SDMA4_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA4_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA4_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA4_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA4_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA4_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA4_GFX_MINOR_PTR_UPDATE
+#define SDMA4_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA4_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA4_GFX_MIDCMD_DATA0
+#define SDMA4_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA4_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA4_GFX_MIDCMD_DATA1
+#define SDMA4_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA4_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA4_GFX_MIDCMD_DATA2
+#define SDMA4_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA4_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA4_GFX_MIDCMD_DATA3
+#define SDMA4_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA4_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA4_GFX_MIDCMD_DATA4
+#define SDMA4_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA4_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA4_GFX_MIDCMD_DATA5
+#define SDMA4_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA4_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA4_GFX_MIDCMD_DATA6
+#define SDMA4_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA4_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA4_GFX_MIDCMD_DATA7
+#define SDMA4_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA4_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA4_GFX_MIDCMD_DATA8
+#define SDMA4_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA4_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA4_GFX_MIDCMD_DATA9
+#define SDMA4_GFX_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA4_GFX_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA4_GFX_MIDCMD_DATA10
+#define SDMA4_GFX_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA4_GFX_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA4_GFX_MIDCMD_CNTL
+#define SDMA4_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA4_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA4_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA4_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA4_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA4_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA4_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA4_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA4_PAGE_RB_CNTL
+#define SDMA4_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA4_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA4_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA4_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA4_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA4_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA4_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA4_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA4_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA4_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA4_PAGE_RB_BASE
+#define SDMA4_PAGE_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA4_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_PAGE_RB_BASE_HI
+#define SDMA4_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA4_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA4_PAGE_RB_RPTR
+#define SDMA4_PAGE_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA4_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_PAGE_RB_RPTR_HI
+#define SDMA4_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA4_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_PAGE_RB_WPTR
+#define SDMA4_PAGE_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA4_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_PAGE_RB_WPTR_HI
+#define SDMA4_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA4_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_PAGE_RB_WPTR_POLL_CNTL
+#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA4_PAGE_RB_RPTR_ADDR_HI
+#define SDMA4_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA4_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_PAGE_RB_RPTR_ADDR_LO
+#define SDMA4_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA4_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA4_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA4_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA4_PAGE_IB_CNTL
+#define SDMA4_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA4_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA4_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA4_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA4_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA4_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA4_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA4_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA4_PAGE_IB_RPTR
+#define SDMA4_PAGE_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA4_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA4_PAGE_IB_OFFSET
+#define SDMA4_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA4_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA4_PAGE_IB_BASE_LO
+#define SDMA4_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA4_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA4_PAGE_IB_BASE_HI
+#define SDMA4_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA4_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_PAGE_IB_SIZE
+#define SDMA4_PAGE_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA4_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA4_PAGE_SKIP_CNTL
+#define SDMA4_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA4_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA4_PAGE_CONTEXT_STATUS
+#define SDMA4_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA4_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA4_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA4_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA4_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA4_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA4_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA4_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA4_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA4_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA4_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA4_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA4_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA4_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA4_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA4_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA4_PAGE_DOORBELL
+#define SDMA4_PAGE_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA4_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA4_PAGE_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA4_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA4_PAGE_STATUS
+#define SDMA4_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA4_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA4_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA4_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA4_PAGE_DOORBELL_LOG
+#define SDMA4_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA4_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA4_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA4_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA4_PAGE_WATERMARK
+#define SDMA4_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA4_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA4_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA4_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA4_PAGE_DOORBELL_OFFSET
+#define SDMA4_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA4_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA4_PAGE_CSA_ADDR_LO
+#define SDMA4_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA4_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA4_PAGE_CSA_ADDR_HI
+#define SDMA4_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA4_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_PAGE_IB_SUB_REMAIN
+#define SDMA4_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA4_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA4_PAGE_PREEMPT
+#define SDMA4_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA4_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA4_PAGE_DUMMY_REG
+#define SDMA4_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA4_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA4_PAGE_RB_WPTR_POLL_ADDR_HI
+#define SDMA4_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA4_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_PAGE_RB_WPTR_POLL_ADDR_LO
+#define SDMA4_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA4_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA4_PAGE_RB_AQL_CNTL
+#define SDMA4_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA4_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA4_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA4_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA4_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA4_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA4_PAGE_MINOR_PTR_UPDATE
+#define SDMA4_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA4_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA4_PAGE_MIDCMD_DATA0
+#define SDMA4_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA4_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA4_PAGE_MIDCMD_DATA1
+#define SDMA4_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA4_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA4_PAGE_MIDCMD_DATA2
+#define SDMA4_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA4_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA4_PAGE_MIDCMD_DATA3
+#define SDMA4_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA4_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA4_PAGE_MIDCMD_DATA4
+#define SDMA4_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA4_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA4_PAGE_MIDCMD_DATA5
+#define SDMA4_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA4_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA4_PAGE_MIDCMD_DATA6
+#define SDMA4_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA4_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA4_PAGE_MIDCMD_DATA7
+#define SDMA4_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA4_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA4_PAGE_MIDCMD_DATA8
+#define SDMA4_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA4_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA4_PAGE_MIDCMD_DATA9
+#define SDMA4_PAGE_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA4_PAGE_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA4_PAGE_MIDCMD_DATA10
+#define SDMA4_PAGE_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA4_PAGE_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA4_PAGE_MIDCMD_CNTL
+#define SDMA4_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA4_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA4_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA4_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA4_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA4_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA4_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA4_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA4_RLC0_RB_CNTL
+#define SDMA4_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA4_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA4_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA4_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA4_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA4_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA4_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA4_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA4_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA4_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA4_RLC0_RB_BASE
+#define SDMA4_RLC0_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA4_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC0_RB_BASE_HI
+#define SDMA4_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA4_RLC0_RB_RPTR
+#define SDMA4_RLC0_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA4_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_RLC0_RB_RPTR_HI
+#define SDMA4_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA4_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_RLC0_RB_WPTR
+#define SDMA4_RLC0_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA4_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_RLC0_RB_WPTR_HI
+#define SDMA4_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA4_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_RLC0_RB_WPTR_POLL_CNTL
+#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA4_RLC0_RB_RPTR_ADDR_HI
+#define SDMA4_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC0_RB_RPTR_ADDR_LO
+#define SDMA4_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA4_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA4_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA4_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA4_RLC0_IB_CNTL
+#define SDMA4_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA4_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA4_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA4_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA4_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA4_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA4_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA4_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA4_RLC0_IB_RPTR
+#define SDMA4_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA4_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA4_RLC0_IB_OFFSET
+#define SDMA4_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA4_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA4_RLC0_IB_BASE_LO
+#define SDMA4_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA4_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA4_RLC0_IB_BASE_HI
+#define SDMA4_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC0_IB_SIZE
+#define SDMA4_RLC0_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA4_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA4_RLC0_SKIP_CNTL
+#define SDMA4_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA4_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA4_RLC0_CONTEXT_STATUS
+#define SDMA4_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA4_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA4_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA4_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA4_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA4_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA4_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA4_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA4_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA4_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA4_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA4_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA4_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA4_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA4_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA4_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA4_RLC0_DOORBELL
+#define SDMA4_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA4_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA4_RLC0_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA4_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA4_RLC0_STATUS
+#define SDMA4_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA4_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA4_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA4_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA4_RLC0_DOORBELL_LOG
+#define SDMA4_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA4_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA4_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA4_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA4_RLC0_WATERMARK
+#define SDMA4_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA4_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA4_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA4_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA4_RLC0_DOORBELL_OFFSET
+#define SDMA4_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA4_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA4_RLC0_CSA_ADDR_LO
+#define SDMA4_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA4_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA4_RLC0_CSA_ADDR_HI
+#define SDMA4_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC0_IB_SUB_REMAIN
+#define SDMA4_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA4_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA4_RLC0_PREEMPT
+#define SDMA4_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA4_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA4_RLC0_DUMMY_REG
+#define SDMA4_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA4_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA4_RLC0_RB_WPTR_POLL_ADDR_HI
+#define SDMA4_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC0_RB_WPTR_POLL_ADDR_LO
+#define SDMA4_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA4_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA4_RLC0_RB_AQL_CNTL
+#define SDMA4_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA4_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA4_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA4_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA4_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA4_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA4_RLC0_MINOR_PTR_UPDATE
+#define SDMA4_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA4_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA4_RLC0_MIDCMD_DATA0
+#define SDMA4_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA4_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA4_RLC0_MIDCMD_DATA1
+#define SDMA4_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA4_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA4_RLC0_MIDCMD_DATA2
+#define SDMA4_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA4_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA4_RLC0_MIDCMD_DATA3
+#define SDMA4_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA4_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA4_RLC0_MIDCMD_DATA4
+#define SDMA4_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA4_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA4_RLC0_MIDCMD_DATA5
+#define SDMA4_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA4_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA4_RLC0_MIDCMD_DATA6
+#define SDMA4_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA4_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA4_RLC0_MIDCMD_DATA7
+#define SDMA4_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA4_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA4_RLC0_MIDCMD_DATA8
+#define SDMA4_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA4_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA4_RLC0_MIDCMD_DATA9
+#define SDMA4_RLC0_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA4_RLC0_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA4_RLC0_MIDCMD_DATA10
+#define SDMA4_RLC0_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA4_RLC0_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA4_RLC0_MIDCMD_CNTL
+#define SDMA4_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA4_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA4_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA4_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA4_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA4_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA4_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA4_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA4_RLC1_RB_CNTL
+#define SDMA4_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA4_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA4_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA4_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA4_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA4_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA4_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA4_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA4_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA4_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA4_RLC1_RB_BASE
+#define SDMA4_RLC1_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA4_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC1_RB_BASE_HI
+#define SDMA4_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA4_RLC1_RB_RPTR
+#define SDMA4_RLC1_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA4_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_RLC1_RB_RPTR_HI
+#define SDMA4_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA4_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_RLC1_RB_WPTR
+#define SDMA4_RLC1_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA4_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_RLC1_RB_WPTR_HI
+#define SDMA4_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA4_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_RLC1_RB_WPTR_POLL_CNTL
+#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA4_RLC1_RB_RPTR_ADDR_HI
+#define SDMA4_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC1_RB_RPTR_ADDR_LO
+#define SDMA4_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA4_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA4_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA4_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA4_RLC1_IB_CNTL
+#define SDMA4_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA4_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA4_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA4_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA4_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA4_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA4_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA4_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA4_RLC1_IB_RPTR
+#define SDMA4_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA4_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA4_RLC1_IB_OFFSET
+#define SDMA4_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA4_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA4_RLC1_IB_BASE_LO
+#define SDMA4_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA4_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA4_RLC1_IB_BASE_HI
+#define SDMA4_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC1_IB_SIZE
+#define SDMA4_RLC1_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA4_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA4_RLC1_SKIP_CNTL
+#define SDMA4_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA4_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA4_RLC1_CONTEXT_STATUS
+#define SDMA4_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA4_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA4_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA4_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA4_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA4_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA4_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA4_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA4_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA4_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA4_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA4_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA4_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA4_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA4_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA4_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA4_RLC1_DOORBELL
+#define SDMA4_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA4_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA4_RLC1_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA4_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA4_RLC1_STATUS
+#define SDMA4_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA4_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA4_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA4_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA4_RLC1_DOORBELL_LOG
+#define SDMA4_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA4_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA4_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA4_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA4_RLC1_WATERMARK
+#define SDMA4_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA4_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA4_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA4_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA4_RLC1_DOORBELL_OFFSET
+#define SDMA4_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA4_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA4_RLC1_CSA_ADDR_LO
+#define SDMA4_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA4_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA4_RLC1_CSA_ADDR_HI
+#define SDMA4_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC1_IB_SUB_REMAIN
+#define SDMA4_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA4_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA4_RLC1_PREEMPT
+#define SDMA4_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA4_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA4_RLC1_DUMMY_REG
+#define SDMA4_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA4_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA4_RLC1_RB_WPTR_POLL_ADDR_HI
+#define SDMA4_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC1_RB_WPTR_POLL_ADDR_LO
+#define SDMA4_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA4_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA4_RLC1_RB_AQL_CNTL
+#define SDMA4_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA4_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA4_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA4_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA4_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA4_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA4_RLC1_MINOR_PTR_UPDATE
+#define SDMA4_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA4_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA4_RLC1_MIDCMD_DATA0
+#define SDMA4_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA4_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA4_RLC1_MIDCMD_DATA1
+#define SDMA4_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA4_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA4_RLC1_MIDCMD_DATA2
+#define SDMA4_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA4_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA4_RLC1_MIDCMD_DATA3
+#define SDMA4_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA4_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA4_RLC1_MIDCMD_DATA4
+#define SDMA4_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA4_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA4_RLC1_MIDCMD_DATA5
+#define SDMA4_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA4_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA4_RLC1_MIDCMD_DATA6
+#define SDMA4_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA4_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA4_RLC1_MIDCMD_DATA7
+#define SDMA4_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA4_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA4_RLC1_MIDCMD_DATA8
+#define SDMA4_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA4_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA4_RLC1_MIDCMD_DATA9
+#define SDMA4_RLC1_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA4_RLC1_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA4_RLC1_MIDCMD_DATA10
+#define SDMA4_RLC1_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA4_RLC1_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA4_RLC1_MIDCMD_CNTL
+#define SDMA4_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA4_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA4_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA4_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA4_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA4_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA4_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA4_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA4_RLC2_RB_CNTL
+#define SDMA4_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA4_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA4_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA4_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA4_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA4_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA4_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA4_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA4_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA4_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA4_RLC2_RB_BASE
+#define SDMA4_RLC2_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA4_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC2_RB_BASE_HI
+#define SDMA4_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA4_RLC2_RB_RPTR
+#define SDMA4_RLC2_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA4_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_RLC2_RB_RPTR_HI
+#define SDMA4_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA4_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_RLC2_RB_WPTR
+#define SDMA4_RLC2_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA4_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_RLC2_RB_WPTR_HI
+#define SDMA4_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA4_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_RLC2_RB_WPTR_POLL_CNTL
+#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA4_RLC2_RB_RPTR_ADDR_HI
+#define SDMA4_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC2_RB_RPTR_ADDR_LO
+#define SDMA4_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA4_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA4_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA4_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA4_RLC2_IB_CNTL
+#define SDMA4_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA4_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA4_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA4_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA4_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA4_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA4_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA4_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA4_RLC2_IB_RPTR
+#define SDMA4_RLC2_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA4_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA4_RLC2_IB_OFFSET
+#define SDMA4_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA4_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA4_RLC2_IB_BASE_LO
+#define SDMA4_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA4_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA4_RLC2_IB_BASE_HI
+#define SDMA4_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC2_IB_SIZE
+#define SDMA4_RLC2_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA4_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA4_RLC2_SKIP_CNTL
+#define SDMA4_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA4_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA4_RLC2_CONTEXT_STATUS
+#define SDMA4_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA4_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA4_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA4_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA4_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA4_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA4_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA4_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA4_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA4_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA4_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA4_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA4_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA4_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA4_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA4_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA4_RLC2_DOORBELL
+#define SDMA4_RLC2_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA4_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA4_RLC2_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA4_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA4_RLC2_STATUS
+#define SDMA4_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA4_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA4_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA4_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA4_RLC2_DOORBELL_LOG
+#define SDMA4_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA4_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA4_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA4_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA4_RLC2_WATERMARK
+#define SDMA4_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA4_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA4_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA4_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA4_RLC2_DOORBELL_OFFSET
+#define SDMA4_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA4_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA4_RLC2_CSA_ADDR_LO
+#define SDMA4_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA4_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA4_RLC2_CSA_ADDR_HI
+#define SDMA4_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC2_IB_SUB_REMAIN
+#define SDMA4_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA4_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA4_RLC2_PREEMPT
+#define SDMA4_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA4_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA4_RLC2_DUMMY_REG
+#define SDMA4_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA4_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA4_RLC2_RB_WPTR_POLL_ADDR_HI
+#define SDMA4_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC2_RB_WPTR_POLL_ADDR_LO
+#define SDMA4_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA4_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA4_RLC2_RB_AQL_CNTL
+#define SDMA4_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA4_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA4_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA4_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA4_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA4_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA4_RLC2_MINOR_PTR_UPDATE
+#define SDMA4_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA4_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA4_RLC2_MIDCMD_DATA0
+#define SDMA4_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA4_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA4_RLC2_MIDCMD_DATA1
+#define SDMA4_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA4_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA4_RLC2_MIDCMD_DATA2
+#define SDMA4_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA4_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA4_RLC2_MIDCMD_DATA3
+#define SDMA4_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA4_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA4_RLC2_MIDCMD_DATA4
+#define SDMA4_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA4_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA4_RLC2_MIDCMD_DATA5
+#define SDMA4_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA4_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA4_RLC2_MIDCMD_DATA6
+#define SDMA4_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA4_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA4_RLC2_MIDCMD_DATA7
+#define SDMA4_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA4_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA4_RLC2_MIDCMD_DATA8
+#define SDMA4_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA4_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA4_RLC2_MIDCMD_DATA9
+#define SDMA4_RLC2_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA4_RLC2_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA4_RLC2_MIDCMD_DATA10
+#define SDMA4_RLC2_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA4_RLC2_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA4_RLC2_MIDCMD_CNTL
+#define SDMA4_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA4_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA4_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA4_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA4_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA4_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA4_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA4_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA4_RLC3_RB_CNTL
+#define SDMA4_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA4_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA4_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA4_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA4_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA4_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA4_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA4_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA4_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA4_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA4_RLC3_RB_BASE
+#define SDMA4_RLC3_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA4_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC3_RB_BASE_HI
+#define SDMA4_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA4_RLC3_RB_RPTR
+#define SDMA4_RLC3_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA4_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_RLC3_RB_RPTR_HI
+#define SDMA4_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA4_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_RLC3_RB_WPTR
+#define SDMA4_RLC3_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA4_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_RLC3_RB_WPTR_HI
+#define SDMA4_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA4_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_RLC3_RB_WPTR_POLL_CNTL
+#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA4_RLC3_RB_RPTR_ADDR_HI
+#define SDMA4_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC3_RB_RPTR_ADDR_LO
+#define SDMA4_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA4_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA4_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA4_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA4_RLC3_IB_CNTL
+#define SDMA4_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA4_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA4_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA4_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA4_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA4_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA4_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA4_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA4_RLC3_IB_RPTR
+#define SDMA4_RLC3_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA4_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA4_RLC3_IB_OFFSET
+#define SDMA4_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA4_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA4_RLC3_IB_BASE_LO
+#define SDMA4_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA4_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA4_RLC3_IB_BASE_HI
+#define SDMA4_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC3_IB_SIZE
+#define SDMA4_RLC3_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA4_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA4_RLC3_SKIP_CNTL
+#define SDMA4_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA4_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA4_RLC3_CONTEXT_STATUS
+#define SDMA4_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA4_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA4_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA4_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA4_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA4_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA4_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA4_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA4_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA4_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA4_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA4_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA4_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA4_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA4_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA4_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA4_RLC3_DOORBELL
+#define SDMA4_RLC3_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA4_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA4_RLC3_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA4_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA4_RLC3_STATUS
+#define SDMA4_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA4_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA4_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA4_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA4_RLC3_DOORBELL_LOG
+#define SDMA4_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA4_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA4_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA4_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA4_RLC3_WATERMARK
+#define SDMA4_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA4_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA4_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA4_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA4_RLC3_DOORBELL_OFFSET
+#define SDMA4_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA4_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA4_RLC3_CSA_ADDR_LO
+#define SDMA4_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA4_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA4_RLC3_CSA_ADDR_HI
+#define SDMA4_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC3_IB_SUB_REMAIN
+#define SDMA4_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA4_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA4_RLC3_PREEMPT
+#define SDMA4_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA4_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA4_RLC3_DUMMY_REG
+#define SDMA4_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA4_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA4_RLC3_RB_WPTR_POLL_ADDR_HI
+#define SDMA4_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC3_RB_WPTR_POLL_ADDR_LO
+#define SDMA4_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA4_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA4_RLC3_RB_AQL_CNTL
+#define SDMA4_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA4_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA4_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA4_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA4_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA4_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA4_RLC3_MINOR_PTR_UPDATE
+#define SDMA4_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA4_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA4_RLC3_MIDCMD_DATA0
+#define SDMA4_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA4_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA4_RLC3_MIDCMD_DATA1
+#define SDMA4_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA4_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA4_RLC3_MIDCMD_DATA2
+#define SDMA4_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA4_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA4_RLC3_MIDCMD_DATA3
+#define SDMA4_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA4_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA4_RLC3_MIDCMD_DATA4
+#define SDMA4_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA4_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA4_RLC3_MIDCMD_DATA5
+#define SDMA4_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA4_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA4_RLC3_MIDCMD_DATA6
+#define SDMA4_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA4_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA4_RLC3_MIDCMD_DATA7
+#define SDMA4_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA4_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA4_RLC3_MIDCMD_DATA8
+#define SDMA4_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA4_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA4_RLC3_MIDCMD_DATA9
+#define SDMA4_RLC3_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA4_RLC3_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA4_RLC3_MIDCMD_DATA10
+#define SDMA4_RLC3_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA4_RLC3_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA4_RLC3_MIDCMD_CNTL
+#define SDMA4_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA4_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA4_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA4_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA4_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA4_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA4_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA4_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA4_RLC4_RB_CNTL
+#define SDMA4_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA4_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA4_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA4_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA4_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA4_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA4_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA4_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA4_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA4_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA4_RLC4_RB_BASE
+#define SDMA4_RLC4_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA4_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC4_RB_BASE_HI
+#define SDMA4_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA4_RLC4_RB_RPTR
+#define SDMA4_RLC4_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA4_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_RLC4_RB_RPTR_HI
+#define SDMA4_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA4_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_RLC4_RB_WPTR
+#define SDMA4_RLC4_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA4_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_RLC4_RB_WPTR_HI
+#define SDMA4_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA4_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_RLC4_RB_WPTR_POLL_CNTL
+#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA4_RLC4_RB_RPTR_ADDR_HI
+#define SDMA4_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC4_RB_RPTR_ADDR_LO
+#define SDMA4_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA4_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA4_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA4_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA4_RLC4_IB_CNTL
+#define SDMA4_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA4_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA4_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA4_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA4_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA4_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA4_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA4_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA4_RLC4_IB_RPTR
+#define SDMA4_RLC4_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA4_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA4_RLC4_IB_OFFSET
+#define SDMA4_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA4_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA4_RLC4_IB_BASE_LO
+#define SDMA4_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA4_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA4_RLC4_IB_BASE_HI
+#define SDMA4_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC4_IB_SIZE
+#define SDMA4_RLC4_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA4_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA4_RLC4_SKIP_CNTL
+#define SDMA4_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA4_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA4_RLC4_CONTEXT_STATUS
+#define SDMA4_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA4_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA4_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA4_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA4_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA4_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA4_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA4_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA4_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA4_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA4_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA4_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA4_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA4_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA4_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA4_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA4_RLC4_DOORBELL
+#define SDMA4_RLC4_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA4_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA4_RLC4_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA4_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA4_RLC4_STATUS
+#define SDMA4_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA4_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA4_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA4_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA4_RLC4_DOORBELL_LOG
+#define SDMA4_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA4_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA4_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA4_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA4_RLC4_WATERMARK
+#define SDMA4_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA4_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA4_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA4_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA4_RLC4_DOORBELL_OFFSET
+#define SDMA4_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA4_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA4_RLC4_CSA_ADDR_LO
+#define SDMA4_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA4_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA4_RLC4_CSA_ADDR_HI
+#define SDMA4_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC4_IB_SUB_REMAIN
+#define SDMA4_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA4_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA4_RLC4_PREEMPT
+#define SDMA4_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA4_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA4_RLC4_DUMMY_REG
+#define SDMA4_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA4_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA4_RLC4_RB_WPTR_POLL_ADDR_HI
+#define SDMA4_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC4_RB_WPTR_POLL_ADDR_LO
+#define SDMA4_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA4_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA4_RLC4_RB_AQL_CNTL
+#define SDMA4_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA4_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA4_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA4_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA4_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA4_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA4_RLC4_MINOR_PTR_UPDATE
+#define SDMA4_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA4_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA4_RLC4_MIDCMD_DATA0
+#define SDMA4_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA4_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA4_RLC4_MIDCMD_DATA1
+#define SDMA4_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA4_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA4_RLC4_MIDCMD_DATA2
+#define SDMA4_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA4_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA4_RLC4_MIDCMD_DATA3
+#define SDMA4_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA4_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA4_RLC4_MIDCMD_DATA4
+#define SDMA4_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA4_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA4_RLC4_MIDCMD_DATA5
+#define SDMA4_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA4_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA4_RLC4_MIDCMD_DATA6
+#define SDMA4_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA4_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA4_RLC4_MIDCMD_DATA7
+#define SDMA4_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA4_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA4_RLC4_MIDCMD_DATA8
+#define SDMA4_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA4_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA4_RLC4_MIDCMD_DATA9
+#define SDMA4_RLC4_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA4_RLC4_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA4_RLC4_MIDCMD_DATA10
+#define SDMA4_RLC4_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA4_RLC4_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA4_RLC4_MIDCMD_CNTL
+#define SDMA4_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA4_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA4_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA4_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA4_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA4_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA4_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA4_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA4_RLC5_RB_CNTL
+#define SDMA4_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA4_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA4_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA4_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA4_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA4_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA4_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA4_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA4_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA4_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA4_RLC5_RB_BASE
+#define SDMA4_RLC5_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA4_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC5_RB_BASE_HI
+#define SDMA4_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA4_RLC5_RB_RPTR
+#define SDMA4_RLC5_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA4_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_RLC5_RB_RPTR_HI
+#define SDMA4_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA4_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_RLC5_RB_WPTR
+#define SDMA4_RLC5_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA4_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_RLC5_RB_WPTR_HI
+#define SDMA4_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA4_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_RLC5_RB_WPTR_POLL_CNTL
+#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA4_RLC5_RB_RPTR_ADDR_HI
+#define SDMA4_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC5_RB_RPTR_ADDR_LO
+#define SDMA4_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA4_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA4_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA4_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA4_RLC5_IB_CNTL
+#define SDMA4_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA4_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA4_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA4_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA4_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA4_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA4_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA4_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA4_RLC5_IB_RPTR
+#define SDMA4_RLC5_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA4_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA4_RLC5_IB_OFFSET
+#define SDMA4_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA4_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA4_RLC5_IB_BASE_LO
+#define SDMA4_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA4_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA4_RLC5_IB_BASE_HI
+#define SDMA4_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC5_IB_SIZE
+#define SDMA4_RLC5_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA4_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA4_RLC5_SKIP_CNTL
+#define SDMA4_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA4_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA4_RLC5_CONTEXT_STATUS
+#define SDMA4_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA4_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA4_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA4_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA4_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA4_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA4_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA4_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA4_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA4_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA4_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA4_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA4_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA4_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA4_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA4_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA4_RLC5_DOORBELL
+#define SDMA4_RLC5_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA4_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA4_RLC5_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA4_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA4_RLC5_STATUS
+#define SDMA4_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA4_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA4_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA4_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA4_RLC5_DOORBELL_LOG
+#define SDMA4_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA4_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA4_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA4_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA4_RLC5_WATERMARK
+#define SDMA4_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA4_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA4_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA4_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA4_RLC5_DOORBELL_OFFSET
+#define SDMA4_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA4_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA4_RLC5_CSA_ADDR_LO
+#define SDMA4_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA4_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA4_RLC5_CSA_ADDR_HI
+#define SDMA4_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC5_IB_SUB_REMAIN
+#define SDMA4_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA4_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA4_RLC5_PREEMPT
+#define SDMA4_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA4_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA4_RLC5_DUMMY_REG
+#define SDMA4_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA4_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA4_RLC5_RB_WPTR_POLL_ADDR_HI
+#define SDMA4_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC5_RB_WPTR_POLL_ADDR_LO
+#define SDMA4_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA4_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA4_RLC5_RB_AQL_CNTL
+#define SDMA4_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA4_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA4_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA4_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA4_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA4_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA4_RLC5_MINOR_PTR_UPDATE
+#define SDMA4_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA4_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA4_RLC5_MIDCMD_DATA0
+#define SDMA4_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA4_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA4_RLC5_MIDCMD_DATA1
+#define SDMA4_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA4_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA4_RLC5_MIDCMD_DATA2
+#define SDMA4_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA4_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA4_RLC5_MIDCMD_DATA3
+#define SDMA4_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA4_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA4_RLC5_MIDCMD_DATA4
+#define SDMA4_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA4_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA4_RLC5_MIDCMD_DATA5
+#define SDMA4_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA4_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA4_RLC5_MIDCMD_DATA6
+#define SDMA4_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA4_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA4_RLC5_MIDCMD_DATA7
+#define SDMA4_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA4_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA4_RLC5_MIDCMD_DATA8
+#define SDMA4_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA4_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA4_RLC5_MIDCMD_DATA9
+#define SDMA4_RLC5_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA4_RLC5_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA4_RLC5_MIDCMD_DATA10
+#define SDMA4_RLC5_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA4_RLC5_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA4_RLC5_MIDCMD_CNTL
+#define SDMA4_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA4_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA4_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA4_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA4_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA4_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA4_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA4_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA4_RLC6_RB_CNTL
+#define SDMA4_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA4_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA4_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA4_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA4_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA4_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA4_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA4_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA4_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA4_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA4_RLC6_RB_BASE
+#define SDMA4_RLC6_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA4_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC6_RB_BASE_HI
+#define SDMA4_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA4_RLC6_RB_RPTR
+#define SDMA4_RLC6_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA4_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_RLC6_RB_RPTR_HI
+#define SDMA4_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA4_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_RLC6_RB_WPTR
+#define SDMA4_RLC6_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA4_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_RLC6_RB_WPTR_HI
+#define SDMA4_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA4_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_RLC6_RB_WPTR_POLL_CNTL
+#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA4_RLC6_RB_RPTR_ADDR_HI
+#define SDMA4_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC6_RB_RPTR_ADDR_LO
+#define SDMA4_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA4_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA4_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA4_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA4_RLC6_IB_CNTL
+#define SDMA4_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA4_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA4_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA4_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA4_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA4_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA4_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA4_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA4_RLC6_IB_RPTR
+#define SDMA4_RLC6_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA4_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA4_RLC6_IB_OFFSET
+#define SDMA4_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA4_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA4_RLC6_IB_BASE_LO
+#define SDMA4_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA4_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA4_RLC6_IB_BASE_HI
+#define SDMA4_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC6_IB_SIZE
+#define SDMA4_RLC6_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA4_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA4_RLC6_SKIP_CNTL
+#define SDMA4_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA4_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA4_RLC6_CONTEXT_STATUS
+#define SDMA4_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA4_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA4_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA4_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA4_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA4_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA4_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA4_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA4_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA4_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA4_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA4_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA4_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA4_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA4_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA4_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA4_RLC6_DOORBELL
+#define SDMA4_RLC6_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA4_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA4_RLC6_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA4_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA4_RLC6_STATUS
+#define SDMA4_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA4_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA4_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA4_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA4_RLC6_DOORBELL_LOG
+#define SDMA4_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA4_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA4_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA4_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA4_RLC6_WATERMARK
+#define SDMA4_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA4_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA4_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA4_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA4_RLC6_DOORBELL_OFFSET
+#define SDMA4_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA4_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA4_RLC6_CSA_ADDR_LO
+#define SDMA4_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA4_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA4_RLC6_CSA_ADDR_HI
+#define SDMA4_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC6_IB_SUB_REMAIN
+#define SDMA4_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA4_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA4_RLC6_PREEMPT
+#define SDMA4_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA4_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA4_RLC6_DUMMY_REG
+#define SDMA4_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA4_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA4_RLC6_RB_WPTR_POLL_ADDR_HI
+#define SDMA4_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC6_RB_WPTR_POLL_ADDR_LO
+#define SDMA4_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA4_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA4_RLC6_RB_AQL_CNTL
+#define SDMA4_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA4_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA4_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA4_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA4_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA4_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA4_RLC6_MINOR_PTR_UPDATE
+#define SDMA4_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA4_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA4_RLC6_MIDCMD_DATA0
+#define SDMA4_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA4_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA4_RLC6_MIDCMD_DATA1
+#define SDMA4_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA4_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA4_RLC6_MIDCMD_DATA2
+#define SDMA4_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA4_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA4_RLC6_MIDCMD_DATA3
+#define SDMA4_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA4_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA4_RLC6_MIDCMD_DATA4
+#define SDMA4_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA4_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA4_RLC6_MIDCMD_DATA5
+#define SDMA4_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA4_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA4_RLC6_MIDCMD_DATA6
+#define SDMA4_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA4_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA4_RLC6_MIDCMD_DATA7
+#define SDMA4_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA4_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA4_RLC6_MIDCMD_DATA8
+#define SDMA4_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA4_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA4_RLC6_MIDCMD_DATA9
+#define SDMA4_RLC6_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA4_RLC6_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA4_RLC6_MIDCMD_DATA10
+#define SDMA4_RLC6_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA4_RLC6_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA4_RLC6_MIDCMD_CNTL
+#define SDMA4_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA4_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA4_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA4_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA4_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA4_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA4_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA4_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA4_RLC7_RB_CNTL
+#define SDMA4_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA4_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA4_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA4_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA4_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA4_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA4_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA4_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA4_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA4_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L
+//SDMA4_RLC7_RB_BASE
+#define SDMA4_RLC7_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA4_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC7_RB_BASE_HI
+#define SDMA4_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA4_RLC7_RB_RPTR
+#define SDMA4_RLC7_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA4_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_RLC7_RB_RPTR_HI
+#define SDMA4_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA4_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_RLC7_RB_WPTR
+#define SDMA4_RLC7_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA4_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_RLC7_RB_WPTR_HI
+#define SDMA4_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA4_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA4_RLC7_RB_WPTR_POLL_CNTL
+#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA4_RLC7_RB_RPTR_ADDR_HI
+#define SDMA4_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC7_RB_RPTR_ADDR_LO
+#define SDMA4_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
+#define SDMA4_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA4_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
+#define SDMA4_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA4_RLC7_IB_CNTL
+#define SDMA4_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA4_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA4_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA4_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA4_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA4_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA4_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA4_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA4_RLC7_IB_RPTR
+#define SDMA4_RLC7_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA4_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA4_RLC7_IB_OFFSET
+#define SDMA4_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA4_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA4_RLC7_IB_BASE_LO
+#define SDMA4_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA4_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA4_RLC7_IB_BASE_HI
+#define SDMA4_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC7_IB_SIZE
+#define SDMA4_RLC7_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA4_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA4_RLC7_SKIP_CNTL
+#define SDMA4_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA4_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA4_RLC7_CONTEXT_STATUS
+#define SDMA4_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA4_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA4_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA4_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA4_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA4_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA4_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA4_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA4_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA4_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA4_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA4_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA4_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA4_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA4_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA4_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA4_RLC7_DOORBELL
+#define SDMA4_RLC7_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA4_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA4_RLC7_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA4_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA4_RLC7_STATUS
+#define SDMA4_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA4_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA4_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA4_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA4_RLC7_DOORBELL_LOG
+#define SDMA4_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA4_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA4_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
+#define SDMA4_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
+//SDMA4_RLC7_WATERMARK
+#define SDMA4_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA4_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA4_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA4_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA4_RLC7_DOORBELL_OFFSET
+#define SDMA4_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA4_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA4_RLC7_CSA_ADDR_LO
+#define SDMA4_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA4_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA4_RLC7_CSA_ADDR_HI
+#define SDMA4_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC7_IB_SUB_REMAIN
+#define SDMA4_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA4_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
+//SDMA4_RLC7_PREEMPT
+#define SDMA4_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA4_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA4_RLC7_DUMMY_REG
+#define SDMA4_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA4_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA4_RLC7_RB_WPTR_POLL_ADDR_HI
+#define SDMA4_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA4_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA4_RLC7_RB_WPTR_POLL_ADDR_LO
+#define SDMA4_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA4_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA4_RLC7_RB_AQL_CNTL
+#define SDMA4_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA4_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA4_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA4_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA4_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA4_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+//SDMA4_RLC7_MINOR_PTR_UPDATE
+#define SDMA4_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA4_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA4_RLC7_MIDCMD_DATA0
+#define SDMA4_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA4_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA4_RLC7_MIDCMD_DATA1
+#define SDMA4_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA4_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA4_RLC7_MIDCMD_DATA2
+#define SDMA4_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA4_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA4_RLC7_MIDCMD_DATA3
+#define SDMA4_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA4_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA4_RLC7_MIDCMD_DATA4
+#define SDMA4_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA4_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA4_RLC7_MIDCMD_DATA5
+#define SDMA4_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA4_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA4_RLC7_MIDCMD_DATA6
+#define SDMA4_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA4_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA4_RLC7_MIDCMD_DATA7
+#define SDMA4_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA4_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA4_RLC7_MIDCMD_DATA8
+#define SDMA4_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA4_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA4_RLC7_MIDCMD_DATA9
+#define SDMA4_RLC7_MIDCMD_DATA9__DATA9__SHIFT 0x0
+#define SDMA4_RLC7_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
+//SDMA4_RLC7_MIDCMD_DATA10
+#define SDMA4_RLC7_MIDCMD_DATA10__DATA10__SHIFT 0x0
+#define SDMA4_RLC7_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
+//SDMA4_RLC7_MIDCMD_CNTL
+#define SDMA4_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA4_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA4_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA4_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA4_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA4_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA4_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA4_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_13_0_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_13_0_2_offset.h
new file mode 100644
index 000000000000..f542268bdb2b
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_13_0_2_offset.h
@@ -0,0 +1,516 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ *
+ */
+#ifndef _smuio_13_0_2_OFFSET_HEADER
+#define _smuio_13_0_2_OFFSET_HEADER
+
+
+
+// addressBlock: smuio_smuio_SmuSmuioDec
+// base address: 0x5a000
+#define regSMUSVI0_TEL_PLANE0 0x0004
+#define regSMUSVI0_TEL_PLANE0_BASE_IDX 0
+#define regSMUSVI0_PLANE0_CURRENTVID 0x0014
+#define regSMUSVI0_PLANE0_CURRENTVID_BASE_IDX 0
+#define regSMUIO_MCM_CONFIG 0x0024
+#define regSMUIO_MCM_CONFIG_BASE_IDX 0
+#define regCKSVII2C_IC_CON 0x0040
+#define regCKSVII2C_IC_CON_BASE_IDX 0
+#define regCKSVII2C_IC_TAR 0x0041
+#define regCKSVII2C_IC_TAR_BASE_IDX 0
+#define regCKSVII2C_IC_SAR 0x0042
+#define regCKSVII2C_IC_SAR_BASE_IDX 0
+#define regCKSVII2C_IC_HS_MADDR 0x0043
+#define regCKSVII2C_IC_HS_MADDR_BASE_IDX 0
+#define regCKSVII2C_IC_DATA_CMD 0x0044
+#define regCKSVII2C_IC_DATA_CMD_BASE_IDX 0
+#define regCKSVII2C_IC_SS_SCL_HCNT 0x0045
+#define regCKSVII2C_IC_SS_SCL_HCNT_BASE_IDX 0
+#define regCKSVII2C_IC_SS_SCL_LCNT 0x0046
+#define regCKSVII2C_IC_SS_SCL_LCNT_BASE_IDX 0
+#define regCKSVII2C_IC_FS_SCL_HCNT 0x0047
+#define regCKSVII2C_IC_FS_SCL_HCNT_BASE_IDX 0
+#define regCKSVII2C_IC_FS_SCL_LCNT 0x0048
+#define regCKSVII2C_IC_FS_SCL_LCNT_BASE_IDX 0
+#define regCKSVII2C_IC_HS_SCL_HCNT 0x0049
+#define regCKSVII2C_IC_HS_SCL_HCNT_BASE_IDX 0
+#define regCKSVII2C_IC_HS_SCL_LCNT 0x004a
+#define regCKSVII2C_IC_HS_SCL_LCNT_BASE_IDX 0
+#define regCKSVII2C_IC_INTR_STAT 0x004b
+#define regCKSVII2C_IC_INTR_STAT_BASE_IDX 0
+#define regCKSVII2C_IC_INTR_MASK 0x004c
+#define regCKSVII2C_IC_INTR_MASK_BASE_IDX 0
+#define regCKSVII2C_IC_RAW_INTR_STAT 0x004d
+#define regCKSVII2C_IC_RAW_INTR_STAT_BASE_IDX 0
+#define regCKSVII2C_IC_RX_TL 0x004e
+#define regCKSVII2C_IC_RX_TL_BASE_IDX 0
+#define regCKSVII2C_IC_TX_TL 0x004f
+#define regCKSVII2C_IC_TX_TL_BASE_IDX 0
+#define regCKSVII2C_IC_CLR_INTR 0x0050
+#define regCKSVII2C_IC_CLR_INTR_BASE_IDX 0
+#define regCKSVII2C_IC_CLR_RX_UNDER 0x0051
+#define regCKSVII2C_IC_CLR_RX_UNDER_BASE_IDX 0
+#define regCKSVII2C_IC_CLR_RX_OVER 0x0052
+#define regCKSVII2C_IC_CLR_RX_OVER_BASE_IDX 0
+#define regCKSVII2C_IC_CLR_TX_OVER 0x0053
+#define regCKSVII2C_IC_CLR_TX_OVER_BASE_IDX 0
+#define regCKSVII2C_IC_CLR_RD_REQ 0x0054
+#define regCKSVII2C_IC_CLR_RD_REQ_BASE_IDX 0
+#define regCKSVII2C_IC_CLR_TX_ABRT 0x0055
+#define regCKSVII2C_IC_CLR_TX_ABRT_BASE_IDX 0
+#define regCKSVII2C_IC_CLR_RX_DONE 0x0056
+#define regCKSVII2C_IC_CLR_RX_DONE_BASE_IDX 0
+#define regCKSVII2C_IC_CLR_ACTIVITY 0x0057
+#define regCKSVII2C_IC_CLR_ACTIVITY_BASE_IDX 0
+#define regCKSVII2C_IC_CLR_STOP_DET 0x0058
+#define regCKSVII2C_IC_CLR_STOP_DET_BASE_IDX 0
+#define regCKSVII2C_IC_CLR_START_DET 0x0059
+#define regCKSVII2C_IC_CLR_START_DET_BASE_IDX 0
+#define regCKSVII2C_IC_CLR_GEN_CALL 0x005a
+#define regCKSVII2C_IC_CLR_GEN_CALL_BASE_IDX 0
+#define regCKSVII2C_IC_ENABLE 0x005b
+#define regCKSVII2C_IC_ENABLE_BASE_IDX 0
+#define regCKSVII2C_IC_STATUS 0x005c
+#define regCKSVII2C_IC_STATUS_BASE_IDX 0
+#define regCKSVII2C_IC_TXFLR 0x005d
+#define regCKSVII2C_IC_TXFLR_BASE_IDX 0
+#define regCKSVII2C_IC_RXFLR 0x005e
+#define regCKSVII2C_IC_RXFLR_BASE_IDX 0
+#define regCKSVII2C_IC_SDA_HOLD 0x005f
+#define regCKSVII2C_IC_SDA_HOLD_BASE_IDX 0
+#define regCKSVII2C_IC_TX_ABRT_SOURCE 0x0060
+#define regCKSVII2C_IC_TX_ABRT_SOURCE_BASE_IDX 0
+#define regCKSVII2C_IC_SLV_DATA_NACK_ONLY 0x0061
+#define regCKSVII2C_IC_SLV_DATA_NACK_ONLY_BASE_IDX 0
+#define regCKSVII2C_IC_DMA_CR 0x0062
+#define regCKSVII2C_IC_DMA_CR_BASE_IDX 0
+#define regCKSVII2C_IC_DMA_TDLR 0x0063
+#define regCKSVII2C_IC_DMA_TDLR_BASE_IDX 0
+#define regCKSVII2C_IC_DMA_RDLR 0x0064
+#define regCKSVII2C_IC_DMA_RDLR_BASE_IDX 0
+#define regCKSVII2C_IC_SDA_SETUP 0x0065
+#define regCKSVII2C_IC_SDA_SETUP_BASE_IDX 0
+#define regCKSVII2C_IC_ACK_GENERAL_CALL 0x0066
+#define regCKSVII2C_IC_ACK_GENERAL_CALL_BASE_IDX 0
+#define regCKSVII2C_IC_ENABLE_STATUS 0x0067
+#define regCKSVII2C_IC_ENABLE_STATUS_BASE_IDX 0
+#define regCKSVII2C_IC_FS_SPKLEN 0x0068
+#define regCKSVII2C_IC_FS_SPKLEN_BASE_IDX 0
+#define regCKSVII2C_IC_HS_SPKLEN 0x0069
+#define regCKSVII2C_IC_HS_SPKLEN_BASE_IDX 0
+#define regCKSVII2C_IC_CLR_RESTART_DET 0x006a
+#define regCKSVII2C_IC_CLR_RESTART_DET_BASE_IDX 0
+#define regCKSVII2C_IC_COMP_PARAM_1 0x006b
+#define regCKSVII2C_IC_COMP_PARAM_1_BASE_IDX 0
+#define regCKSVII2C_IC_COMP_VERSION 0x006c
+#define regCKSVII2C_IC_COMP_VERSION_BASE_IDX 0
+#define regCKSVII2C_IC_COMP_TYPE 0x006d
+#define regCKSVII2C_IC_COMP_TYPE_BASE_IDX 0
+#define regCKSVII2C1_IC_CON 0x0080
+#define regCKSVII2C1_IC_CON_BASE_IDX 0
+#define regCKSVII2C1_IC_TAR 0x0081
+#define regCKSVII2C1_IC_TAR_BASE_IDX 0
+#define regCKSVII2C1_IC_SAR 0x0082
+#define regCKSVII2C1_IC_SAR_BASE_IDX 0
+#define regCKSVII2C1_IC_HS_MADDR 0x0083
+#define regCKSVII2C1_IC_HS_MADDR_BASE_IDX 0
+#define regCKSVII2C1_IC_DATA_CMD 0x0084
+#define regCKSVII2C1_IC_DATA_CMD_BASE_IDX 0
+#define regCKSVII2C1_IC_SS_SCL_HCNT 0x0085
+#define regCKSVII2C1_IC_SS_SCL_HCNT_BASE_IDX 0
+#define regCKSVII2C1_IC_SS_SCL_LCNT 0x0086
+#define regCKSVII2C1_IC_SS_SCL_LCNT_BASE_IDX 0
+#define regCKSVII2C1_IC_FS_SCL_HCNT 0x0087
+#define regCKSVII2C1_IC_FS_SCL_HCNT_BASE_IDX 0
+#define regCKSVII2C1_IC_FS_SCL_LCNT 0x0088
+#define regCKSVII2C1_IC_FS_SCL_LCNT_BASE_IDX 0
+#define regCKSVII2C1_IC_HS_SCL_HCNT 0x0089
+#define regCKSVII2C1_IC_HS_SCL_HCNT_BASE_IDX 0
+#define regCKSVII2C1_IC_HS_SCL_LCNT 0x008a
+#define regCKSVII2C1_IC_HS_SCL_LCNT_BASE_IDX 0
+#define regCKSVII2C1_IC_INTR_STAT 0x008b
+#define regCKSVII2C1_IC_INTR_STAT_BASE_IDX 0
+#define regCKSVII2C1_IC_INTR_MASK 0x008c
+#define regCKSVII2C1_IC_INTR_MASK_BASE_IDX 0
+#define regCKSVII2C1_IC_RAW_INTR_STAT 0x008d
+#define regCKSVII2C1_IC_RAW_INTR_STAT_BASE_IDX 0
+#define regCKSVII2C1_IC_RX_TL 0x008e
+#define regCKSVII2C1_IC_RX_TL_BASE_IDX 0
+#define regCKSVII2C1_IC_TX_TL 0x008f
+#define regCKSVII2C1_IC_TX_TL_BASE_IDX 0
+#define regCKSVII2C1_IC_CLR_INTR 0x0090
+#define regCKSVII2C1_IC_CLR_INTR_BASE_IDX 0
+#define regCKSVII2C1_IC_CLR_RX_UNDER 0x0091
+#define regCKSVII2C1_IC_CLR_RX_UNDER_BASE_IDX 0
+#define regCKSVII2C1_IC_CLR_RX_OVER 0x0092
+#define regCKSVII2C1_IC_CLR_RX_OVER_BASE_IDX 0
+#define regCKSVII2C1_IC_CLR_TX_OVER 0x0093
+#define regCKSVII2C1_IC_CLR_TX_OVER_BASE_IDX 0
+#define regCKSVII2C1_IC_CLR_RD_REQ 0x0094
+#define regCKSVII2C1_IC_CLR_RD_REQ_BASE_IDX 0
+#define regCKSVII2C1_IC_CLR_TX_ABRT 0x0095
+#define regCKSVII2C1_IC_CLR_TX_ABRT_BASE_IDX 0
+#define regCKSVII2C1_IC_CLR_RX_DONE 0x0096
+#define regCKSVII2C1_IC_CLR_RX_DONE_BASE_IDX 0
+#define regCKSVII2C1_IC_CLR_ACTIVITY 0x0097
+#define regCKSVII2C1_IC_CLR_ACTIVITY_BASE_IDX 0
+#define regCKSVII2C1_IC_CLR_STOP_DET 0x0098
+#define regCKSVII2C1_IC_CLR_STOP_DET_BASE_IDX 0
+#define regCKSVII2C1_IC_CLR_START_DET 0x0099
+#define regCKSVII2C1_IC_CLR_START_DET_BASE_IDX 0
+#define regCKSVII2C1_IC_CLR_GEN_CALL 0x009a
+#define regCKSVII2C1_IC_CLR_GEN_CALL_BASE_IDX 0
+#define regCKSVII2C1_IC_ENABLE 0x009b
+#define regCKSVII2C1_IC_ENABLE_BASE_IDX 0
+#define regCKSVII2C1_IC_STATUS 0x009c
+#define regCKSVII2C1_IC_STATUS_BASE_IDX 0
+#define regCKSVII2C1_IC_TXFLR 0x009d
+#define regCKSVII2C1_IC_TXFLR_BASE_IDX 0
+#define regCKSVII2C1_IC_RXFLR 0x009e
+#define regCKSVII2C1_IC_RXFLR_BASE_IDX 0
+#define regCKSVII2C1_IC_SDA_HOLD 0x009f
+#define regCKSVII2C1_IC_SDA_HOLD_BASE_IDX 0
+#define regCKSVII2C1_IC_TX_ABRT_SOURCE 0x00a0
+#define regCKSVII2C1_IC_TX_ABRT_SOURCE_BASE_IDX 0
+#define regCKSVII2C1_IC_SLV_DATA_NACK_ONLY 0x00a1
+#define regCKSVII2C1_IC_SLV_DATA_NACK_ONLY_BASE_IDX 0
+#define regCKSVII2C1_IC_DMA_CR 0x00a2
+#define regCKSVII2C1_IC_DMA_CR_BASE_IDX 0
+#define regCKSVII2C1_IC_DMA_TDLR 0x00a3
+#define regCKSVII2C1_IC_DMA_TDLR_BASE_IDX 0
+#define regCKSVII2C1_IC_DMA_RDLR 0x00a4
+#define regCKSVII2C1_IC_DMA_RDLR_BASE_IDX 0
+#define regCKSVII2C1_IC_SDA_SETUP 0x00a5
+#define regCKSVII2C1_IC_SDA_SETUP_BASE_IDX 0
+#define regCKSVII2C1_IC_ACK_GENERAL_CALL 0x00a6
+#define regCKSVII2C1_IC_ACK_GENERAL_CALL_BASE_IDX 0
+#define regCKSVII2C1_IC_ENABLE_STATUS 0x00a7
+#define regCKSVII2C1_IC_ENABLE_STATUS_BASE_IDX 0
+#define regCKSVII2C1_IC_FS_SPKLEN 0x00a8
+#define regCKSVII2C1_IC_FS_SPKLEN_BASE_IDX 0
+#define regCKSVII2C1_IC_HS_SPKLEN 0x00a9
+#define regCKSVII2C1_IC_HS_SPKLEN_BASE_IDX 0
+#define regCKSVII2C1_IC_CLR_RESTART_DET 0x00aa
+#define regCKSVII2C1_IC_CLR_RESTART_DET_BASE_IDX 0
+#define regCKSVII2C1_IC_COMP_PARAM_1 0x00ab
+#define regCKSVII2C1_IC_COMP_PARAM_1_BASE_IDX 0
+#define regCKSVII2C1_IC_COMP_VERSION 0x00ac
+#define regCKSVII2C1_IC_COMP_VERSION_BASE_IDX 0
+#define regCKSVII2C1_IC_COMP_TYPE 0x00ad
+#define regCKSVII2C1_IC_COMP_TYPE_BASE_IDX 0
+#define regSMUIO_MP_RESET_INTR 0x00c1
+#define regSMUIO_MP_RESET_INTR_BASE_IDX 0
+#define regSMUIO_SOC_HALT 0x00c2
+#define regSMUIO_SOC_HALT_BASE_IDX 0
+#define regSMUIO_PWRMGT 0x00cd
+#define regSMUIO_PWRMGT_BASE_IDX 0
+#define regSMUIO_GFX_MISC_CNTL 0x00d1
+#define regSMUIO_GFX_MISC_CNTL_BASE_IDX 0
+#define regROM_CNTL 0x00e1
+#define regROM_CNTL_BASE_IDX 0
+#define regPAGE_MIRROR_CNTL 0x00e2
+#define regPAGE_MIRROR_CNTL_BASE_IDX 0
+#define regROM_STATUS 0x00e3
+#define regROM_STATUS_BASE_IDX 0
+#define regCGTT_ROM_CLK_CTRL0 0x00e4
+#define regCGTT_ROM_CLK_CTRL0_BASE_IDX 0
+#define regROM_INDEX 0x00e5
+#define regROM_INDEX_BASE_IDX 0
+#define regROM_DATA 0x00e6
+#define regROM_DATA_BASE_IDX 0
+#define regROM_START 0x00e7
+#define regROM_START_BASE_IDX 0
+#define regROM_SW_CNTL 0x00e9
+#define regROM_SW_CNTL_BASE_IDX 0
+#define regROM_SW_STATUS 0x00ea
+#define regROM_SW_STATUS_BASE_IDX 0
+#define regROM_SW_COMMAND 0x00eb
+#define regROM_SW_COMMAND_BASE_IDX 0
+#define regROM_SW_DATA_1 0x00ed
+#define regROM_SW_DATA_1_BASE_IDX 0
+#define regROM_SW_DATA_2 0x00ee
+#define regROM_SW_DATA_2_BASE_IDX 0
+#define regROM_SW_DATA_3 0x00ef
+#define regROM_SW_DATA_3_BASE_IDX 0
+#define regROM_SW_DATA_4 0x00f0
+#define regROM_SW_DATA_4_BASE_IDX 0
+#define regROM_SW_DATA_5 0x00f1
+#define regROM_SW_DATA_5_BASE_IDX 0
+#define regROM_SW_DATA_6 0x00f2
+#define regROM_SW_DATA_6_BASE_IDX 0
+#define regROM_SW_DATA_7 0x00f3
+#define regROM_SW_DATA_7_BASE_IDX 0
+#define regROM_SW_DATA_8 0x00f4
+#define regROM_SW_DATA_8_BASE_IDX 0
+#define regROM_SW_DATA_9 0x00f5
+#define regROM_SW_DATA_9_BASE_IDX 0
+#define regROM_SW_DATA_10 0x00f6
+#define regROM_SW_DATA_10_BASE_IDX 0
+#define regROM_SW_DATA_11 0x00f7
+#define regROM_SW_DATA_11_BASE_IDX 0
+#define regROM_SW_DATA_12 0x00f8
+#define regROM_SW_DATA_12_BASE_IDX 0
+#define regROM_SW_DATA_13 0x00f9
+#define regROM_SW_DATA_13_BASE_IDX 0
+#define regROM_SW_DATA_14 0x00fa
+#define regROM_SW_DATA_14_BASE_IDX 0
+#define regROM_SW_DATA_15 0x00fb
+#define regROM_SW_DATA_15_BASE_IDX 0
+#define regROM_SW_DATA_16 0x00fc
+#define regROM_SW_DATA_16_BASE_IDX 0
+#define regROM_SW_DATA_17 0x00fd
+#define regROM_SW_DATA_17_BASE_IDX 0
+#define regROM_SW_DATA_18 0x00fe
+#define regROM_SW_DATA_18_BASE_IDX 0
+#define regROM_SW_DATA_19 0x00ff
+#define regROM_SW_DATA_19_BASE_IDX 0
+#define regROM_SW_DATA_20 0x0100
+#define regROM_SW_DATA_20_BASE_IDX 0
+#define regROM_SW_DATA_21 0x0101
+#define regROM_SW_DATA_21_BASE_IDX 0
+#define regROM_SW_DATA_22 0x0102
+#define regROM_SW_DATA_22_BASE_IDX 0
+#define regROM_SW_DATA_23 0x0103
+#define regROM_SW_DATA_23_BASE_IDX 0
+#define regROM_SW_DATA_24 0x0104
+#define regROM_SW_DATA_24_BASE_IDX 0
+#define regROM_SW_DATA_25 0x0105
+#define regROM_SW_DATA_25_BASE_IDX 0
+#define regROM_SW_DATA_26 0x0106
+#define regROM_SW_DATA_26_BASE_IDX 0
+#define regROM_SW_DATA_27 0x0107
+#define regROM_SW_DATA_27_BASE_IDX 0
+#define regROM_SW_DATA_28 0x0108
+#define regROM_SW_DATA_28_BASE_IDX 0
+#define regROM_SW_DATA_29 0x0109
+#define regROM_SW_DATA_29_BASE_IDX 0
+#define regROM_SW_DATA_30 0x010a
+#define regROM_SW_DATA_30_BASE_IDX 0
+#define regROM_SW_DATA_31 0x010b
+#define regROM_SW_DATA_31_BASE_IDX 0
+#define regROM_SW_DATA_32 0x010c
+#define regROM_SW_DATA_32_BASE_IDX 0
+#define regROM_SW_DATA_33 0x010d
+#define regROM_SW_DATA_33_BASE_IDX 0
+#define regROM_SW_DATA_34 0x010e
+#define regROM_SW_DATA_34_BASE_IDX 0
+#define regROM_SW_DATA_35 0x010f
+#define regROM_SW_DATA_35_BASE_IDX 0
+#define regROM_SW_DATA_36 0x0110
+#define regROM_SW_DATA_36_BASE_IDX 0
+#define regROM_SW_DATA_37 0x0111
+#define regROM_SW_DATA_37_BASE_IDX 0
+#define regROM_SW_DATA_38 0x0112
+#define regROM_SW_DATA_38_BASE_IDX 0
+#define regROM_SW_DATA_39 0x0113
+#define regROM_SW_DATA_39_BASE_IDX 0
+#define regROM_SW_DATA_40 0x0114
+#define regROM_SW_DATA_40_BASE_IDX 0
+#define regROM_SW_DATA_41 0x0115
+#define regROM_SW_DATA_41_BASE_IDX 0
+#define regROM_SW_DATA_42 0x0116
+#define regROM_SW_DATA_42_BASE_IDX 0
+#define regROM_SW_DATA_43 0x0117
+#define regROM_SW_DATA_43_BASE_IDX 0
+#define regROM_SW_DATA_44 0x0118
+#define regROM_SW_DATA_44_BASE_IDX 0
+#define regROM_SW_DATA_45 0x0119
+#define regROM_SW_DATA_45_BASE_IDX 0
+#define regROM_SW_DATA_46 0x011a
+#define regROM_SW_DATA_46_BASE_IDX 0
+#define regROM_SW_DATA_47 0x011b
+#define regROM_SW_DATA_47_BASE_IDX 0
+#define regROM_SW_DATA_48 0x011c
+#define regROM_SW_DATA_48_BASE_IDX 0
+#define regROM_SW_DATA_49 0x011d
+#define regROM_SW_DATA_49_BASE_IDX 0
+#define regROM_SW_DATA_50 0x011e
+#define regROM_SW_DATA_50_BASE_IDX 0
+#define regROM_SW_DATA_51 0x011f
+#define regROM_SW_DATA_51_BASE_IDX 0
+#define regROM_SW_DATA_52 0x0120
+#define regROM_SW_DATA_52_BASE_IDX 0
+#define regROM_SW_DATA_53 0x0121
+#define regROM_SW_DATA_53_BASE_IDX 0
+#define regROM_SW_DATA_54 0x0122
+#define regROM_SW_DATA_54_BASE_IDX 0
+#define regROM_SW_DATA_55 0x0123
+#define regROM_SW_DATA_55_BASE_IDX 0
+#define regROM_SW_DATA_56 0x0124
+#define regROM_SW_DATA_56_BASE_IDX 0
+#define regROM_SW_DATA_57 0x0125
+#define regROM_SW_DATA_57_BASE_IDX 0
+#define regROM_SW_DATA_58 0x0126
+#define regROM_SW_DATA_58_BASE_IDX 0
+#define regROM_SW_DATA_59 0x0127
+#define regROM_SW_DATA_59_BASE_IDX 0
+#define regROM_SW_DATA_60 0x0128
+#define regROM_SW_DATA_60_BASE_IDX 0
+#define regROM_SW_DATA_61 0x0129
+#define regROM_SW_DATA_61_BASE_IDX 0
+#define regROM_SW_DATA_62 0x012a
+#define regROM_SW_DATA_62_BASE_IDX 0
+#define regROM_SW_DATA_63 0x012b
+#define regROM_SW_DATA_63_BASE_IDX 0
+#define regROM_SW_DATA_64 0x012c
+#define regROM_SW_DATA_64_BASE_IDX 0
+#define regSMU_GPIOPAD_SW_INT_STAT 0x0140
+#define regSMU_GPIOPAD_SW_INT_STAT_BASE_IDX 0
+#define regSMU_GPIOPAD_MASK 0x0141
+#define regSMU_GPIOPAD_MASK_BASE_IDX 0
+#define regSMU_GPIOPAD_A 0x0142
+#define regSMU_GPIOPAD_A_BASE_IDX 0
+#define regSMU_GPIOPAD_TXIMPSEL 0x0143
+#define regSMU_GPIOPAD_TXIMPSEL_BASE_IDX 0
+#define regSMU_GPIOPAD_EN 0x0144
+#define regSMU_GPIOPAD_EN_BASE_IDX 0
+#define regSMU_GPIOPAD_Y 0x0145
+#define regSMU_GPIOPAD_Y_BASE_IDX 0
+#define regSMU_GPIOPAD_RXEN 0x0146
+#define regSMU_GPIOPAD_RXEN_BASE_IDX 0
+#define regSMU_GPIOPAD_RCVR_SEL0 0x0147
+#define regSMU_GPIOPAD_RCVR_SEL0_BASE_IDX 0
+#define regSMU_GPIOPAD_RCVR_SEL1 0x0148
+#define regSMU_GPIOPAD_RCVR_SEL1_BASE_IDX 0
+#define regSMU_GPIOPAD_PU_EN 0x0149
+#define regSMU_GPIOPAD_PU_EN_BASE_IDX 0
+#define regSMU_GPIOPAD_PD_EN 0x014a
+#define regSMU_GPIOPAD_PD_EN_BASE_IDX 0
+#define regSMU_GPIOPAD_PINSTRAPS 0x014b
+#define regSMU_GPIOPAD_PINSTRAPS_BASE_IDX 0
+#define regDFT_PINSTRAPS 0x014c
+#define regDFT_PINSTRAPS_BASE_IDX 0
+#define regSMU_GPIOPAD_INT_STAT_EN 0x014d
+#define regSMU_GPIOPAD_INT_STAT_EN_BASE_IDX 0
+#define regSMU_GPIOPAD_INT_STAT 0x014e
+#define regSMU_GPIOPAD_INT_STAT_BASE_IDX 0
+#define regSMU_GPIOPAD_INT_STAT_AK 0x014f
+#define regSMU_GPIOPAD_INT_STAT_AK_BASE_IDX 0
+#define regSMU_GPIOPAD_INT_EN 0x0150
+#define regSMU_GPIOPAD_INT_EN_BASE_IDX 0
+#define regSMU_GPIOPAD_INT_TYPE 0x0151
+#define regSMU_GPIOPAD_INT_TYPE_BASE_IDX 0
+#define regSMU_GPIOPAD_INT_POLARITY 0x0152
+#define regSMU_GPIOPAD_INT_POLARITY_BASE_IDX 0
+#define regROM_CC_BIF_PINSTRAP 0x0153
+#define regROM_CC_BIF_PINSTRAP_BASE_IDX 0
+#define regIO_SMUIO_PINSTRAP 0x0154
+#define regIO_SMUIO_PINSTRAP_BASE_IDX 0
+#define regSMUIO_PCC_CONTROL 0x0155
+#define regSMUIO_PCC_CONTROL_BASE_IDX 0
+#define regSMUIO_PCC_GPIO_SELECT 0x0156
+#define regSMUIO_PCC_GPIO_SELECT_BASE_IDX 0
+#define regSMUIO_GPIO_INT0_SELECT 0x0157
+#define regSMUIO_GPIO_INT0_SELECT_BASE_IDX 0
+#define regSMUIO_GPIO_INT1_SELECT 0x0158
+#define regSMUIO_GPIO_INT1_SELECT_BASE_IDX 0
+#define regSMUIO_GPIO_INT2_SELECT 0x0159
+#define regSMUIO_GPIO_INT2_SELECT_BASE_IDX 0
+#define regSMUIO_GPIO_INT3_SELECT 0x015a
+#define regSMUIO_GPIO_INT3_SELECT_BASE_IDX 0
+#define regSMU_GPIOPAD_MP_INT0_STAT 0x015b
+#define regSMU_GPIOPAD_MP_INT0_STAT_BASE_IDX 0
+#define regSMU_GPIOPAD_MP_INT1_STAT 0x015c
+#define regSMU_GPIOPAD_MP_INT1_STAT_BASE_IDX 0
+#define regSMU_GPIOPAD_MP_INT2_STAT 0x015d
+#define regSMU_GPIOPAD_MP_INT2_STAT_BASE_IDX 0
+#define regSMU_GPIOPAD_MP_INT3_STAT 0x015e
+#define regSMU_GPIOPAD_MP_INT3_STAT_BASE_IDX 0
+#define regSMIO_INDEX 0x015f
+#define regSMIO_INDEX_BASE_IDX 0
+#define regS0_VID_SMIO_CNTL 0x0160
+#define regS0_VID_SMIO_CNTL_BASE_IDX 0
+#define regS1_VID_SMIO_CNTL 0x0161
+#define regS1_VID_SMIO_CNTL_BASE_IDX 0
+#define regOPEN_DRAIN_SELECT 0x0162
+#define regOPEN_DRAIN_SELECT_BASE_IDX 0
+#define regSMIO_ENABLE 0x0163
+#define regSMIO_ENABLE_BASE_IDX 0
+#define regSMU_GPIOPAD_S0 0x0164
+#define regSMU_GPIOPAD_S0_BASE_IDX 0
+#define regSMU_GPIOPAD_S1 0x0165
+#define regSMU_GPIOPAD_S1_BASE_IDX 0
+#define regSMU_GPIOPAD_SCL_EN 0x0166
+#define regSMU_GPIOPAD_SCL_EN_BASE_IDX 0
+#define regSMU_GPIOPAD_SDA_EN 0x0167
+#define regSMU_GPIOPAD_SDA_EN_BASE_IDX 0
+#define regSMU_GPIOPAD_SCHMEN 0x0168
+#define regSMU_GPIOPAD_SCHMEN_BASE_IDX 0
+
+
+// addressBlock: smuio_smuio_pwr_SmuSmuioDec
+// base address: 0x5a800
+#define regIP_DISCOVERY_VERSION 0x0000
+#define regIP_DISCOVERY_VERSION_BASE_IDX 1
+#define regSOC_GAP_PWROK 0x00fc
+#define regSOC_GAP_PWROK_BASE_IDX 1
+#define regGFX_GAP_PWROK 0x00fd
+#define regGFX_GAP_PWROK_BASE_IDX 1
+#define regPWROK_REFCLK_GAP_CYCLES 0x00fe
+#define regPWROK_REFCLK_GAP_CYCLES_BASE_IDX 1
+#define regGOLDEN_TSC_INCREMENT_UPPER 0x0104
+#define regGOLDEN_TSC_INCREMENT_UPPER_BASE_IDX 1
+#define regGOLDEN_TSC_INCREMENT_LOWER 0x0105
+#define regGOLDEN_TSC_INCREMENT_LOWER_BASE_IDX 1
+#define regGOLDEN_TSC_COUNT_UPPER 0x0106
+#define regGOLDEN_TSC_COUNT_UPPER_BASE_IDX 1
+#define regGOLDEN_TSC_COUNT_LOWER 0x0107
+#define regGOLDEN_TSC_COUNT_LOWER_BASE_IDX 1
+#define regSOC_GOLDEN_TSC_SHADOW_UPPER 0x0108
+#define regSOC_GOLDEN_TSC_SHADOW_UPPER_BASE_IDX 1
+#define regSOC_GOLDEN_TSC_SHADOW_LOWER 0x0109
+#define regSOC_GOLDEN_TSC_SHADOW_LOWER_BASE_IDX 1
+#define regGFX_GOLDEN_TSC_SHADOW_UPPER 0x010a
+#define regGFX_GOLDEN_TSC_SHADOW_UPPER_BASE_IDX 1
+#define regGFX_GOLDEN_TSC_SHADOW_LOWER 0x010b
+#define regGFX_GOLDEN_TSC_SHADOW_LOWER_BASE_IDX 1
+#define regSCRATCH_REGISTER0 0x0114
+#define regSCRATCH_REGISTER0_BASE_IDX 1
+#define regSCRATCH_REGISTER1 0x0115
+#define regSCRATCH_REGISTER1_BASE_IDX 1
+#define regSCRATCH_REGISTER2 0x0116
+#define regSCRATCH_REGISTER2_BASE_IDX 1
+#define regSCRATCH_REGISTER3 0x0117
+#define regSCRATCH_REGISTER3_BASE_IDX 1
+#define regSCRATCH_REGISTER4 0x0118
+#define regSCRATCH_REGISTER4_BASE_IDX 1
+#define regSCRATCH_REGISTER5 0x0119
+#define regSCRATCH_REGISTER5_BASE_IDX 1
+#define regSCRATCH_REGISTER6 0x011a
+#define regSCRATCH_REGISTER6_BASE_IDX 1
+#define regSCRATCH_REGISTER7 0x011b
+#define regSCRATCH_REGISTER7_BASE_IDX 1
+#define regPWR_DISP_TIMER_CONTROL 0x0134
+#define regPWR_DISP_TIMER_CONTROL_BASE_IDX 1
+#define regPWR_DISP_TIMER_DEBUG 0x0135
+#define regPWR_DISP_TIMER_DEBUG_BASE_IDX 1
+#define regPWR_DISP_TIMER2_CONTROL 0x0136
+#define regPWR_DISP_TIMER2_CONTROL_BASE_IDX 1
+#define regPWR_DISP_TIMER2_DEBUG 0x0137
+#define regPWR_DISP_TIMER2_DEBUG_BASE_IDX 1
+#define regPWR_DISP_TIMER_GLOBAL_CONTROL 0x0138
+#define regPWR_DISP_TIMER_GLOBAL_CONTROL_BASE_IDX 1
+#define regPWR_IH_CONTROL 0x0139
+#define regPWR_IH_CONTROL_BASE_IDX 1
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_13_0_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_13_0_2_sh_mask.h
new file mode 100644
index 000000000000..7040b99b5224
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_13_0_2_sh_mask.h
@@ -0,0 +1,1163 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ *
+ */
+#ifndef _smuio_13_0_2_SH_MASK_HEADER
+#define _smuio_13_0_2_SH_MASK_HEADER
+
+
+// addressBlock: smuio_smuio_SmuSmuioDec
+//SMUSVI0_TEL_PLANE0
+#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_IDDCOR__SHIFT 0x0
+#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT 0x10
+#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_IDDCOR_MASK 0x000000FFL
+#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK 0x01FF0000L
+//SMUSVI0_PLANE0_CURRENTVID
+#define SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT 0x18
+#define SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID_MASK 0xFF000000L
+//SMUIO_MCM_CONFIG
+#define SMUIO_MCM_CONFIG__DIE_ID__SHIFT 0x0
+#define SMUIO_MCM_CONFIG__PKG_TYPE__SHIFT 0x1
+#define SMUIO_MCM_CONFIG__SOCKET_ID__SHIFT 0x4
+#define SMUIO_MCM_CONFIG__PKG_SUBTYPE__SHIFT 0x8
+#define SMUIO_MCM_CONFIG__TOPOLOGY_ID__SHIFT 0xa
+#define SMUIO_MCM_CONFIG__DIE_ID_MASK 0x00000001L
+#define SMUIO_MCM_CONFIG__PKG_TYPE_MASK 0x0000000EL
+#define SMUIO_MCM_CONFIG__SOCKET_ID_MASK 0x000000F0L
+#define SMUIO_MCM_CONFIG__PKG_SUBTYPE_MASK 0x00000300L
+#define SMUIO_MCM_CONFIG__TOPOLOGY_ID_MASK 0x00007C00L
+//CKSVII2C_IC_CON
+#define CKSVII2C_IC_CON__IC_MASTER_MODE__SHIFT 0x0
+#define CKSVII2C_IC_CON__IC_MAX_SPEED_MODE__SHIFT 0x1
+#define CKSVII2C_IC_CON__IC_10BITADDR_SLAVE__SHIFT 0x3
+#define CKSVII2C_IC_CON__IC_10BITADDR_MASTER__SHIFT 0x4
+#define CKSVII2C_IC_CON__IC_RESTART_EN__SHIFT 0x5
+#define CKSVII2C_IC_CON__IC_SLAVE_DISABLE__SHIFT 0x6
+#define CKSVII2C_IC_CON__STOP_DET_IFADDRESSED__SHIFT 0x7
+#define CKSVII2C_IC_CON__TX_EMPTY_CTRL__SHIFT 0x8
+#define CKSVII2C_IC_CON__RX_FIFO_FULL_HLD_CTRL__SHIFT 0x9
+#define CKSVII2C_IC_CON__IC_MASTER_MODE_MASK 0x00000001L
+#define CKSVII2C_IC_CON__IC_MAX_SPEED_MODE_MASK 0x00000006L
+#define CKSVII2C_IC_CON__IC_10BITADDR_SLAVE_MASK 0x00000008L
+#define CKSVII2C_IC_CON__IC_10BITADDR_MASTER_MASK 0x00000010L
+#define CKSVII2C_IC_CON__IC_RESTART_EN_MASK 0x00000020L
+#define CKSVII2C_IC_CON__IC_SLAVE_DISABLE_MASK 0x00000040L
+#define CKSVII2C_IC_CON__STOP_DET_IFADDRESSED_MASK 0x00000080L
+#define CKSVII2C_IC_CON__TX_EMPTY_CTRL_MASK 0x00000100L
+#define CKSVII2C_IC_CON__RX_FIFO_FULL_HLD_CTRL_MASK 0x00000200L
+//CKSVII2C_IC_TAR
+#define CKSVII2C_IC_TAR__IC_TAR__SHIFT 0x0
+#define CKSVII2C_IC_TAR__GC_OR_START__SHIFT 0xa
+#define CKSVII2C_IC_TAR__SPECIAL__SHIFT 0xb
+#define CKSVII2C_IC_TAR__IC_10BITADDR_MASTER__SHIFT 0xc
+#define CKSVII2C_IC_TAR__IC_TAR_MASK 0x000003FFL
+#define CKSVII2C_IC_TAR__GC_OR_START_MASK 0x00000400L
+#define CKSVII2C_IC_TAR__SPECIAL_MASK 0x00000800L
+#define CKSVII2C_IC_TAR__IC_10BITADDR_MASTER_MASK 0x00001000L
+//CKSVII2C_IC_SAR
+#define CKSVII2C_IC_SAR__IC_SAR__SHIFT 0x0
+#define CKSVII2C_IC_SAR__IC_SAR_MASK 0x000003FFL
+//CKSVII2C_IC_HS_MADDR
+#define CKSVII2C_IC_HS_MADDR__IC_HS_MADDR__SHIFT 0x0
+#define CKSVII2C_IC_HS_MADDR__IC_HS_MADDR_MASK 0x00000007L
+//CKSVII2C_IC_DATA_CMD
+#define CKSVII2C_IC_DATA_CMD__DAT__SHIFT 0x0
+#define CKSVII2C_IC_DATA_CMD__CMD__SHIFT 0x8
+#define CKSVII2C_IC_DATA_CMD__STOP__SHIFT 0x9
+#define CKSVII2C_IC_DATA_CMD__RESTART__SHIFT 0xa
+#define CKSVII2C_IC_DATA_CMD__DAT_MASK 0x000000FFL
+#define CKSVII2C_IC_DATA_CMD__CMD_MASK 0x00000100L
+#define CKSVII2C_IC_DATA_CMD__STOP_MASK 0x00000200L
+#define CKSVII2C_IC_DATA_CMD__RESTART_MASK 0x00000400L
+//CKSVII2C_IC_SS_SCL_HCNT
+#define CKSVII2C_IC_SS_SCL_HCNT__IC_SS_SCL_HCNT__SHIFT 0x0
+#define CKSVII2C_IC_SS_SCL_HCNT__IC_SS_SCL_HCNT_MASK 0x0000FFFFL
+//CKSVII2C_IC_SS_SCL_LCNT
+#define CKSVII2C_IC_SS_SCL_LCNT__IC_SS_SCL_LCNT__SHIFT 0x0
+#define CKSVII2C_IC_SS_SCL_LCNT__IC_SS_SCL_LCNT_MASK 0x0000FFFFL
+//CKSVII2C_IC_FS_SCL_HCNT
+#define CKSVII2C_IC_FS_SCL_HCNT__IC_FS_SCL_HCNT__SHIFT 0x0
+#define CKSVII2C_IC_FS_SCL_HCNT__IC_FS_SCL_HCNT_MASK 0x0000FFFFL
+//CKSVII2C_IC_FS_SCL_LCNT
+#define CKSVII2C_IC_FS_SCL_LCNT__IC_FS_SCL_LCNT__SHIFT 0x0
+#define CKSVII2C_IC_FS_SCL_LCNT__IC_FS_SCL_LCNT_MASK 0x0000FFFFL
+//CKSVII2C_IC_HS_SCL_HCNT
+#define CKSVII2C_IC_HS_SCL_HCNT__IC_HS_SCL_HCNT__SHIFT 0x0
+#define CKSVII2C_IC_HS_SCL_HCNT__IC_HS_SCL_HCNT_MASK 0x0000FFFFL
+//CKSVII2C_IC_HS_SCL_LCNT
+#define CKSVII2C_IC_HS_SCL_LCNT__IC_HS_SCL_LCNT__SHIFT 0x0
+#define CKSVII2C_IC_HS_SCL_LCNT__IC_HS_SCL_LCNT_MASK 0x0000FFFFL
+//CKSVII2C_IC_INTR_STAT
+#define CKSVII2C_IC_INTR_STAT__R_RX_UNDER__SHIFT 0x0
+#define CKSVII2C_IC_INTR_STAT__R_RX_OVER__SHIFT 0x1
+#define CKSVII2C_IC_INTR_STAT__R_RX_FULL__SHIFT 0x2
+#define CKSVII2C_IC_INTR_STAT__R_TX_OVER__SHIFT 0x3
+#define CKSVII2C_IC_INTR_STAT__R_TX_EMPTY__SHIFT 0x4
+#define CKSVII2C_IC_INTR_STAT__R_RD_REQ__SHIFT 0x5
+#define CKSVII2C_IC_INTR_STAT__R_TX_ABRT__SHIFT 0x6
+#define CKSVII2C_IC_INTR_STAT__R_RX_DONE__SHIFT 0x7
+#define CKSVII2C_IC_INTR_STAT__R_ACTIVITY__SHIFT 0x8
+#define CKSVII2C_IC_INTR_STAT__R_STOP_DET__SHIFT 0x9
+#define CKSVII2C_IC_INTR_STAT__R_START_DET__SHIFT 0xa
+#define CKSVII2C_IC_INTR_STAT__R_GEN_CALL__SHIFT 0xb
+#define CKSVII2C_IC_INTR_STAT__R_RESTART_DET__SHIFT 0xc
+#define CKSVII2C_IC_INTR_STAT__R_MST_ON_HOLD__SHIFT 0xd
+#define CKSVII2C_IC_INTR_STAT__R_RX_UNDER_MASK 0x00000001L
+#define CKSVII2C_IC_INTR_STAT__R_RX_OVER_MASK 0x00000002L
+#define CKSVII2C_IC_INTR_STAT__R_RX_FULL_MASK 0x00000004L
+#define CKSVII2C_IC_INTR_STAT__R_TX_OVER_MASK 0x00000008L
+#define CKSVII2C_IC_INTR_STAT__R_TX_EMPTY_MASK 0x00000010L
+#define CKSVII2C_IC_INTR_STAT__R_RD_REQ_MASK 0x00000020L
+#define CKSVII2C_IC_INTR_STAT__R_TX_ABRT_MASK 0x00000040L
+#define CKSVII2C_IC_INTR_STAT__R_RX_DONE_MASK 0x00000080L
+#define CKSVII2C_IC_INTR_STAT__R_ACTIVITY_MASK 0x00000100L
+#define CKSVII2C_IC_INTR_STAT__R_STOP_DET_MASK 0x00000200L
+#define CKSVII2C_IC_INTR_STAT__R_START_DET_MASK 0x00000400L
+#define CKSVII2C_IC_INTR_STAT__R_GEN_CALL_MASK 0x00000800L
+#define CKSVII2C_IC_INTR_STAT__R_RESTART_DET_MASK 0x00001000L
+#define CKSVII2C_IC_INTR_STAT__R_MST_ON_HOLD_MASK 0x00002000L
+//CKSVII2C_IC_INTR_MASK
+#define CKSVII2C_IC_INTR_MASK__M_RX_UNDER__SHIFT 0x0
+#define CKSVII2C_IC_INTR_MASK__M_RX_OVER__SHIFT 0x1
+#define CKSVII2C_IC_INTR_MASK__M_RX_FULL__SHIFT 0x2
+#define CKSVII2C_IC_INTR_MASK__M_TX_OVER__SHIFT 0x3
+#define CKSVII2C_IC_INTR_MASK__M_TX_EMPTY__SHIFT 0x4
+#define CKSVII2C_IC_INTR_MASK__M_RD_REQ__SHIFT 0x5
+#define CKSVII2C_IC_INTR_MASK__M_TX_ABRT__SHIFT 0x6
+#define CKSVII2C_IC_INTR_MASK__M_RX_DONE__SHIFT 0x7
+#define CKSVII2C_IC_INTR_MASK__M_ACTIVITY__SHIFT 0x8
+#define CKSVII2C_IC_INTR_MASK__M_STOP_DET__SHIFT 0x9
+#define CKSVII2C_IC_INTR_MASK__M_START_DET__SHIFT 0xa
+#define CKSVII2C_IC_INTR_MASK__M_GEN_CALL__SHIFT 0xb
+#define CKSVII2C_IC_INTR_MASK__M_RESTART_DET__SHIFT 0xc
+#define CKSVII2C_IC_INTR_MASK__M_MST_ON_HOLD__SHIFT 0xd
+#define CKSVII2C_IC_INTR_MASK__M_RX_UNDER_MASK 0x00000001L
+#define CKSVII2C_IC_INTR_MASK__M_RX_OVER_MASK 0x00000002L
+#define CKSVII2C_IC_INTR_MASK__M_RX_FULL_MASK 0x00000004L
+#define CKSVII2C_IC_INTR_MASK__M_TX_OVER_MASK 0x00000008L
+#define CKSVII2C_IC_INTR_MASK__M_TX_EMPTY_MASK 0x00000010L
+#define CKSVII2C_IC_INTR_MASK__M_RD_REQ_MASK 0x00000020L
+#define CKSVII2C_IC_INTR_MASK__M_TX_ABRT_MASK 0x00000040L
+#define CKSVII2C_IC_INTR_MASK__M_RX_DONE_MASK 0x00000080L
+#define CKSVII2C_IC_INTR_MASK__M_ACTIVITY_MASK 0x00000100L
+#define CKSVII2C_IC_INTR_MASK__M_STOP_DET_MASK 0x00000200L
+#define CKSVII2C_IC_INTR_MASK__M_START_DET_MASK 0x00000400L
+#define CKSVII2C_IC_INTR_MASK__M_GEN_CALL_MASK 0x00000800L
+#define CKSVII2C_IC_INTR_MASK__M_RESTART_DET_MASK 0x00001000L
+#define CKSVII2C_IC_INTR_MASK__M_MST_ON_HOLD_MASK 0x00002000L
+//CKSVII2C_IC_RAW_INTR_STAT
+//CKSVII2C_IC_RX_TL
+#define CKSVII2C_IC_RX_TL__RX_TL__SHIFT 0x0
+#define CKSVII2C_IC_RX_TL__RX_TL_MASK 0x000000FFL
+//CKSVII2C_IC_TX_TL
+#define CKSVII2C_IC_TX_TL__TX_TL__SHIFT 0x0
+#define CKSVII2C_IC_TX_TL__TX_TL_MASK 0x000000FFL
+//CKSVII2C_IC_CLR_INTR
+//CKSVII2C_IC_CLR_RX_UNDER
+//CKSVII2C_IC_CLR_RX_OVER
+//CKSVII2C_IC_CLR_TX_OVER
+//CKSVII2C_IC_CLR_RD_REQ
+//CKSVII2C_IC_CLR_TX_ABRT
+//CKSVII2C_IC_CLR_RX_DONE
+//CKSVII2C_IC_CLR_ACTIVITY
+//CKSVII2C_IC_CLR_STOP_DET
+//CKSVII2C_IC_CLR_START_DET
+//CKSVII2C_IC_CLR_GEN_CALL
+//CKSVII2C_IC_ENABLE
+#define CKSVII2C_IC_ENABLE__ENABLE__SHIFT 0x0
+#define CKSVII2C_IC_ENABLE__ABORT__SHIFT 0x1
+#define CKSVII2C_IC_ENABLE__TX_CMD_BLOCK__SHIFT 0x2
+#define CKSVII2C_IC_ENABLE__ENABLE_MASK 0x00000001L
+#define CKSVII2C_IC_ENABLE__ABORT_MASK 0x00000002L
+#define CKSVII2C_IC_ENABLE__TX_CMD_BLOCK_MASK 0x00000004L
+//CKSVII2C_IC_STATUS
+#define CKSVII2C_IC_STATUS__ACTIVITY__SHIFT 0x0
+#define CKSVII2C_IC_STATUS__TFNF__SHIFT 0x1
+#define CKSVII2C_IC_STATUS__TFE__SHIFT 0x2
+#define CKSVII2C_IC_STATUS__RFNE__SHIFT 0x3
+#define CKSVII2C_IC_STATUS__RFF__SHIFT 0x4
+#define CKSVII2C_IC_STATUS__MST_ACTIVITY__SHIFT 0x5
+#define CKSVII2C_IC_STATUS__SLV_ACTIVITY__SHIFT 0x6
+#define CKSVII2C_IC_STATUS__ACTIVITY_MASK 0x00000001L
+#define CKSVII2C_IC_STATUS__TFNF_MASK 0x00000002L
+#define CKSVII2C_IC_STATUS__TFE_MASK 0x00000004L
+#define CKSVII2C_IC_STATUS__RFNE_MASK 0x00000008L
+#define CKSVII2C_IC_STATUS__RFF_MASK 0x00000010L
+#define CKSVII2C_IC_STATUS__MST_ACTIVITY_MASK 0x00000020L
+#define CKSVII2C_IC_STATUS__SLV_ACTIVITY_MASK 0x00000040L
+//CKSVII2C_IC_TXFLR
+#define CKSVII2C_IC_TXFLR__TXFLR__SHIFT 0x0
+#define CKSVII2C_IC_TXFLR__TXFLR_MASK 0x0000003FL
+//CKSVII2C_IC_RXFLR
+#define CKSVII2C_IC_RXFLR__RXFLR__SHIFT 0x0
+#define CKSVII2C_IC_RXFLR__RXFLR_MASK 0x0000003FL
+//CKSVII2C_IC_SDA_HOLD
+#define CKSVII2C_IC_SDA_HOLD__IC_SDA_TX_HOLD__SHIFT 0x0
+#define CKSVII2C_IC_SDA_HOLD__IC_SDA_RX_HOLD__SHIFT 0x10
+#define CKSVII2C_IC_SDA_HOLD__IC_SDA_TX_HOLD_MASK 0x0000FFFFL
+#define CKSVII2C_IC_SDA_HOLD__IC_SDA_RX_HOLD_MASK 0x00FF0000L
+//CKSVII2C_IC_TX_ABRT_SOURCE
+//CKSVII2C_IC_SLV_DATA_NACK_ONLY
+//CKSVII2C_IC_DMA_CR
+//CKSVII2C_IC_DMA_TDLR
+//CKSVII2C_IC_DMA_RDLR
+//CKSVII2C_IC_SDA_SETUP
+#define CKSVII2C_IC_SDA_SETUP__SDA_SETUP__SHIFT 0x0
+#define CKSVII2C_IC_SDA_SETUP__SDA_SETUP_MASK 0x000000FFL
+//CKSVII2C_IC_ACK_GENERAL_CALL
+#define CKSVII2C_IC_ACK_GENERAL_CALL__ACK_GEN_CALL__SHIFT 0x0
+#define CKSVII2C_IC_ACK_GENERAL_CALL__ACK_GEN_CALL_MASK 0x00000001L
+//CKSVII2C_IC_ENABLE_STATUS
+#define CKSVII2C_IC_ENABLE_STATUS__IC_EN__SHIFT 0x0
+#define CKSVII2C_IC_ENABLE_STATUS__SLV_DISABLED_WHILE_BUSY__SHIFT 0x1
+#define CKSVII2C_IC_ENABLE_STATUS__SLV_RX_DATA_LOST__SHIFT 0x2
+#define CKSVII2C_IC_ENABLE_STATUS__IC_EN_MASK 0x00000001L
+#define CKSVII2C_IC_ENABLE_STATUS__SLV_DISABLED_WHILE_BUSY_MASK 0x00000002L
+#define CKSVII2C_IC_ENABLE_STATUS__SLV_RX_DATA_LOST_MASK 0x00000004L
+//CKSVII2C_IC_FS_SPKLEN
+#define CKSVII2C_IC_FS_SPKLEN__IC_FS_SPKLEN__SHIFT 0x0
+#define CKSVII2C_IC_FS_SPKLEN__IC_FS_SPKLEN_MASK 0x000000FFL
+//CKSVII2C_IC_HS_SPKLEN
+#define CKSVII2C_IC_HS_SPKLEN__IC_HS_SPKLEN__SHIFT 0x0
+#define CKSVII2C_IC_HS_SPKLEN__IC_HS_SPKLEN_MASK 0x000000FFL
+//CKSVII2C_IC_CLR_RESTART_DET
+//CKSVII2C_IC_COMP_PARAM_1
+#define CKSVII2C_IC_COMP_PARAM_1__APB_DATA_WIDTH__SHIFT 0x0
+#define CKSVII2C_IC_COMP_PARAM_1__MAX_SPEED_MODE__SHIFT 0x2
+#define CKSVII2C_IC_COMP_PARAM_1__HC_COUNT_VALUES__SHIFT 0x4
+#define CKSVII2C_IC_COMP_PARAM_1__INTR_IO__SHIFT 0x5
+#define CKSVII2C_IC_COMP_PARAM_1__HAS_DMA__SHIFT 0x6
+#define CKSVII2C_IC_COMP_PARAM_1__ADD_ENCODED_PARAMS__SHIFT 0x7
+#define CKSVII2C_IC_COMP_PARAM_1__RX_BUFFER_DEPTH__SHIFT 0x8
+#define CKSVII2C_IC_COMP_PARAM_1__TX_BUFFER_DEPTH__SHIFT 0x10
+#define CKSVII2C_IC_COMP_PARAM_1__APB_DATA_WIDTH_MASK 0x00000003L
+#define CKSVII2C_IC_COMP_PARAM_1__MAX_SPEED_MODE_MASK 0x0000000CL
+#define CKSVII2C_IC_COMP_PARAM_1__HC_COUNT_VALUES_MASK 0x00000010L
+#define CKSVII2C_IC_COMP_PARAM_1__INTR_IO_MASK 0x00000020L
+#define CKSVII2C_IC_COMP_PARAM_1__HAS_DMA_MASK 0x00000040L
+#define CKSVII2C_IC_COMP_PARAM_1__ADD_ENCODED_PARAMS_MASK 0x00000080L
+#define CKSVII2C_IC_COMP_PARAM_1__RX_BUFFER_DEPTH_MASK 0x0000FF00L
+#define CKSVII2C_IC_COMP_PARAM_1__TX_BUFFER_DEPTH_MASK 0x00FF0000L
+//CKSVII2C_IC_COMP_VERSION
+#define CKSVII2C_IC_COMP_VERSION__IC_COMP_VERSION__SHIFT 0x0
+#define CKSVII2C_IC_COMP_VERSION__IC_COMP_VERSION_MASK 0xFFFFFFFFL
+//CKSVII2C_IC_COMP_TYPE
+#define CKSVII2C_IC_COMP_TYPE__IC_COMP_TYPE__SHIFT 0x0
+#define CKSVII2C_IC_COMP_TYPE__IC_COMP_TYPE_MASK 0xFFFFFFFFL
+//CKSVII2C1_IC_CON
+#define CKSVII2C1_IC_CON__IC1_MASTER_MODE__SHIFT 0x0
+#define CKSVII2C1_IC_CON__IC1_MAX_SPEED_MODE__SHIFT 0x1
+#define CKSVII2C1_IC_CON__IC1_10BITADDR_SLAVE__SHIFT 0x3
+#define CKSVII2C1_IC_CON__IC1_10BITADDR_MASTER__SHIFT 0x4
+#define CKSVII2C1_IC_CON__IC1_RESTART_EN__SHIFT 0x5
+#define CKSVII2C1_IC_CON__IC1_SLAVE_DISABLE__SHIFT 0x6
+#define CKSVII2C1_IC_CON__STOP1_DET_IFADDRESSED__SHIFT 0x7
+#define CKSVII2C1_IC_CON__TX1_EMPTY_CTRL__SHIFT 0x8
+#define CKSVII2C1_IC_CON__RX1_FIFO_FULL_HLD_CTRL__SHIFT 0x9
+#define CKSVII2C1_IC_CON__IC1_MASTER_MODE_MASK 0x00000001L
+#define CKSVII2C1_IC_CON__IC1_MAX_SPEED_MODE_MASK 0x00000006L
+#define CKSVII2C1_IC_CON__IC1_10BITADDR_SLAVE_MASK 0x00000008L
+#define CKSVII2C1_IC_CON__IC1_10BITADDR_MASTER_MASK 0x00000010L
+#define CKSVII2C1_IC_CON__IC1_RESTART_EN_MASK 0x00000020L
+#define CKSVII2C1_IC_CON__IC1_SLAVE_DISABLE_MASK 0x00000040L
+#define CKSVII2C1_IC_CON__STOP1_DET_IFADDRESSED_MASK 0x00000080L
+#define CKSVII2C1_IC_CON__TX1_EMPTY_CTRL_MASK 0x00000100L
+#define CKSVII2C1_IC_CON__RX1_FIFO_FULL_HLD_CTRL_MASK 0x00000200L
+//CKSVII2C1_IC_TAR
+#define CKSVII2C1_IC_TAR__IC1_TAR__SHIFT 0x0
+#define CKSVII2C1_IC_TAR__GC1_OR_START__SHIFT 0xa
+#define CKSVII2C1_IC_TAR__SPECIAL1__SHIFT 0xb
+#define CKSVII2C1_IC_TAR__IC1_10BITADDR_MASTER__SHIFT 0xc
+#define CKSVII2C1_IC_TAR__IC1_TAR_MASK 0x000003FFL
+#define CKSVII2C1_IC_TAR__GC1_OR_START_MASK 0x00000400L
+#define CKSVII2C1_IC_TAR__SPECIAL1_MASK 0x00000800L
+#define CKSVII2C1_IC_TAR__IC1_10BITADDR_MASTER_MASK 0x00001000L
+//CKSVII2C1_IC_SAR
+#define CKSVII2C1_IC_SAR__IC1_SAR__SHIFT 0x0
+#define CKSVII2C1_IC_SAR__IC1_SAR_MASK 0x000003FFL
+//CKSVII2C1_IC_HS_MADDR
+#define CKSVII2C1_IC_HS_MADDR__IC1_HS_MADDR__SHIFT 0x0
+#define CKSVII2C1_IC_HS_MADDR__IC1_HS_MADDR_MASK 0x00000007L
+//CKSVII2C1_IC_DATA_CMD
+#define CKSVII2C1_IC_DATA_CMD__DAT1__SHIFT 0x0
+#define CKSVII2C1_IC_DATA_CMD__CMD1__SHIFT 0x8
+#define CKSVII2C1_IC_DATA_CMD__STOP1__SHIFT 0x9
+#define CKSVII2C1_IC_DATA_CMD__RESTART1__SHIFT 0xa
+#define CKSVII2C1_IC_DATA_CMD__DAT1_MASK 0x000000FFL
+#define CKSVII2C1_IC_DATA_CMD__CMD1_MASK 0x00000100L
+#define CKSVII2C1_IC_DATA_CMD__STOP1_MASK 0x00000200L
+#define CKSVII2C1_IC_DATA_CMD__RESTART1_MASK 0x00000400L
+//CKSVII2C1_IC_SS_SCL_HCNT
+#define CKSVII2C1_IC_SS_SCL_HCNT__IC1_SS_SCL_HCNT__SHIFT 0x0
+#define CKSVII2C1_IC_SS_SCL_HCNT__IC1_SS_SCL_HCNT_MASK 0x0000FFFFL
+//CKSVII2C1_IC_SS_SCL_LCNT
+#define CKSVII2C1_IC_SS_SCL_LCNT__IC1_SS_SCL_LCNT__SHIFT 0x0
+#define CKSVII2C1_IC_SS_SCL_LCNT__IC1_SS_SCL_LCNT_MASK 0x0000FFFFL
+//CKSVII2C1_IC_FS_SCL_HCNT
+#define CKSVII2C1_IC_FS_SCL_HCNT__IC1_FS_SCL_HCNT__SHIFT 0x0
+#define CKSVII2C1_IC_FS_SCL_HCNT__IC1_FS_SCL_HCNT_MASK 0x0000FFFFL
+//CKSVII2C1_IC_FS_SCL_LCNT
+#define CKSVII2C1_IC_FS_SCL_LCNT__IC1_FS_SCL_LCNT__SHIFT 0x0
+#define CKSVII2C1_IC_FS_SCL_LCNT__IC1_FS_SCL_LCNT_MASK 0x0000FFFFL
+//CKSVII2C1_IC_HS_SCL_HCNT
+#define CKSVII2C1_IC_HS_SCL_HCNT__IC1_HS_SCL_HCNT__SHIFT 0x0
+#define CKSVII2C1_IC_HS_SCL_HCNT__IC1_HS_SCL_HCNT_MASK 0x0000FFFFL
+//CKSVII2C1_IC_HS_SCL_LCNT
+#define CKSVII2C1_IC_HS_SCL_LCNT__IC1_HS_SCL_LCNT__SHIFT 0x0
+#define CKSVII2C1_IC_HS_SCL_LCNT__IC1_HS_SCL_LCNT_MASK 0x0000FFFFL
+//CKSVII2C1_IC_INTR_STAT
+#define CKSVII2C1_IC_INTR_STAT__R1_RX_UNDER__SHIFT 0x0
+#define CKSVII2C1_IC_INTR_STAT__R1_RX_OVER__SHIFT 0x1
+#define CKSVII2C1_IC_INTR_STAT__R1_RX_FULL__SHIFT 0x2
+#define CKSVII2C1_IC_INTR_STAT__R1_TX_OVER__SHIFT 0x3
+#define CKSVII2C1_IC_INTR_STAT__R1_TX_EMPTY__SHIFT 0x4
+#define CKSVII2C1_IC_INTR_STAT__R1_RD_REQ__SHIFT 0x5
+#define CKSVII2C1_IC_INTR_STAT__R1_TX_ABRT__SHIFT 0x6
+#define CKSVII2C1_IC_INTR_STAT__R1_RX_DONE__SHIFT 0x7
+#define CKSVII2C1_IC_INTR_STAT__R1_ACTIVITY__SHIFT 0x8
+#define CKSVII2C1_IC_INTR_STAT__R1_STOP_DET__SHIFT 0x9
+#define CKSVII2C1_IC_INTR_STAT__R1_START_DET__SHIFT 0xa
+#define CKSVII2C1_IC_INTR_STAT__R1_GEN_CALL__SHIFT 0xb
+#define CKSVII2C1_IC_INTR_STAT__R1_RESTART_DET__SHIFT 0xc
+#define CKSVII2C1_IC_INTR_STAT__R1_MST_ON_HOLD__SHIFT 0xd
+#define CKSVII2C1_IC_INTR_STAT__R1_RX_UNDER_MASK 0x00000001L
+#define CKSVII2C1_IC_INTR_STAT__R1_RX_OVER_MASK 0x00000002L
+#define CKSVII2C1_IC_INTR_STAT__R1_RX_FULL_MASK 0x00000004L
+#define CKSVII2C1_IC_INTR_STAT__R1_TX_OVER_MASK 0x00000008L
+#define CKSVII2C1_IC_INTR_STAT__R1_TX_EMPTY_MASK 0x00000010L
+#define CKSVII2C1_IC_INTR_STAT__R1_RD_REQ_MASK 0x00000020L
+#define CKSVII2C1_IC_INTR_STAT__R1_TX_ABRT_MASK 0x00000040L
+#define CKSVII2C1_IC_INTR_STAT__R1_RX_DONE_MASK 0x00000080L
+#define CKSVII2C1_IC_INTR_STAT__R1_ACTIVITY_MASK 0x00000100L
+#define CKSVII2C1_IC_INTR_STAT__R1_STOP_DET_MASK 0x00000200L
+#define CKSVII2C1_IC_INTR_STAT__R1_START_DET_MASK 0x00000400L
+#define CKSVII2C1_IC_INTR_STAT__R1_GEN_CALL_MASK 0x00000800L
+#define CKSVII2C1_IC_INTR_STAT__R1_RESTART_DET_MASK 0x00001000L
+#define CKSVII2C1_IC_INTR_STAT__R1_MST_ON_HOLD_MASK 0x00002000L
+//CKSVII2C1_IC_INTR_MASK
+#define CKSVII2C1_IC_INTR_MASK__M1_RX_UNDER__SHIFT 0x0
+#define CKSVII2C1_IC_INTR_MASK__M1_RX_OVER__SHIFT 0x1
+#define CKSVII2C1_IC_INTR_MASK__M1_RX_FULL__SHIFT 0x2
+#define CKSVII2C1_IC_INTR_MASK__M1_TX_OVER__SHIFT 0x3
+#define CKSVII2C1_IC_INTR_MASK__M1_TX_EMPTY__SHIFT 0x4
+#define CKSVII2C1_IC_INTR_MASK__M1_RD_REQ__SHIFT 0x5
+#define CKSVII2C1_IC_INTR_MASK__M1_TX_ABRT__SHIFT 0x6
+#define CKSVII2C1_IC_INTR_MASK__M1_RX_DONE__SHIFT 0x7
+#define CKSVII2C1_IC_INTR_MASK__M1_ACTIVITY__SHIFT 0x8
+#define CKSVII2C1_IC_INTR_MASK__M1_STOP_DET__SHIFT 0x9
+#define CKSVII2C1_IC_INTR_MASK__M1_START_DET__SHIFT 0xa
+#define CKSVII2C1_IC_INTR_MASK__M1_GEN_CALL__SHIFT 0xb
+#define CKSVII2C1_IC_INTR_MASK__M1_RESTART_DET__SHIFT 0xc
+#define CKSVII2C1_IC_INTR_MASK__M1_MST_ON_HOLD__SHIFT 0xd
+#define CKSVII2C1_IC_INTR_MASK__M1_RX_UNDER_MASK 0x00000001L
+#define CKSVII2C1_IC_INTR_MASK__M1_RX_OVER_MASK 0x00000002L
+#define CKSVII2C1_IC_INTR_MASK__M1_RX_FULL_MASK 0x00000004L
+#define CKSVII2C1_IC_INTR_MASK__M1_TX_OVER_MASK 0x00000008L
+#define CKSVII2C1_IC_INTR_MASK__M1_TX_EMPTY_MASK 0x00000010L
+#define CKSVII2C1_IC_INTR_MASK__M1_RD_REQ_MASK 0x00000020L
+#define CKSVII2C1_IC_INTR_MASK__M1_TX_ABRT_MASK 0x00000040L
+#define CKSVII2C1_IC_INTR_MASK__M1_RX_DONE_MASK 0x00000080L
+#define CKSVII2C1_IC_INTR_MASK__M1_ACTIVITY_MASK 0x00000100L
+#define CKSVII2C1_IC_INTR_MASK__M1_STOP_DET_MASK 0x00000200L
+#define CKSVII2C1_IC_INTR_MASK__M1_START_DET_MASK 0x00000400L
+#define CKSVII2C1_IC_INTR_MASK__M1_GEN_CALL_MASK 0x00000800L
+#define CKSVII2C1_IC_INTR_MASK__M1_RESTART_DET_MASK 0x00001000L
+#define CKSVII2C1_IC_INTR_MASK__M1_MST_ON_HOLD_MASK 0x00002000L
+//CKSVII2C1_IC_RAW_INTR_STAT
+//CKSVII2C1_IC_RX_TL
+#define CKSVII2C1_IC_RX_TL__RX1_TL__SHIFT 0x0
+#define CKSVII2C1_IC_RX_TL__RX1_TL_MASK 0x000000FFL
+//CKSVII2C1_IC_TX_TL
+#define CKSVII2C1_IC_TX_TL__TX1_TL__SHIFT 0x0
+#define CKSVII2C1_IC_TX_TL__TX1_TL_MASK 0x000000FFL
+//CKSVII2C1_IC_CLR_INTR
+//CKSVII2C1_IC_CLR_RX_UNDER
+//CKSVII2C1_IC_CLR_RX_OVER
+//CKSVII2C1_IC_CLR_TX_OVER
+//CKSVII2C1_IC_CLR_RD_REQ
+//CKSVII2C1_IC_CLR_TX_ABRT
+//CKSVII2C1_IC_CLR_RX_DONE
+//CKSVII2C1_IC_CLR_ACTIVITY
+//CKSVII2C1_IC_CLR_STOP_DET
+//CKSVII2C1_IC_CLR_START_DET
+//CKSVII2C1_IC_CLR_GEN_CALL
+//CKSVII2C1_IC_ENABLE
+#define CKSVII2C1_IC_ENABLE__ENABLE1__SHIFT 0x0
+#define CKSVII2C1_IC_ENABLE__ABORT1__SHIFT 0x1
+#define CKSVII2C1_IC_ENABLE__TX1_CMD_BLOCK__SHIFT 0x2
+#define CKSVII2C1_IC_ENABLE__ENABLE1_MASK 0x00000001L
+#define CKSVII2C1_IC_ENABLE__ABORT1_MASK 0x00000002L
+#define CKSVII2C1_IC_ENABLE__TX1_CMD_BLOCK_MASK 0x00000004L
+//CKSVII2C1_IC_STATUS
+#define CKSVII2C1_IC_STATUS__ACTIVITY1__SHIFT 0x0
+#define CKSVII2C1_IC_STATUS__TFNF1__SHIFT 0x1
+#define CKSVII2C1_IC_STATUS__TFE1__SHIFT 0x2
+#define CKSVII2C1_IC_STATUS__RFNE1__SHIFT 0x3
+#define CKSVII2C1_IC_STATUS__RFF1__SHIFT 0x4
+#define CKSVII2C1_IC_STATUS__MST1_ACTIVITY__SHIFT 0x5
+#define CKSVII2C1_IC_STATUS__SLV1_ACTIVITY__SHIFT 0x6
+#define CKSVII2C1_IC_STATUS__ACTIVITY1_MASK 0x00000001L
+#define CKSVII2C1_IC_STATUS__TFNF1_MASK 0x00000002L
+#define CKSVII2C1_IC_STATUS__TFE1_MASK 0x00000004L
+#define CKSVII2C1_IC_STATUS__RFNE1_MASK 0x00000008L
+#define CKSVII2C1_IC_STATUS__RFF1_MASK 0x00000010L
+#define CKSVII2C1_IC_STATUS__MST1_ACTIVITY_MASK 0x00000020L
+#define CKSVII2C1_IC_STATUS__SLV1_ACTIVITY_MASK 0x00000040L
+//CKSVII2C1_IC_TXFLR
+#define CKSVII2C1_IC_TXFLR__TXFLR1__SHIFT 0x0
+#define CKSVII2C1_IC_TXFLR__TXFLR1_MASK 0x0000003FL
+//CKSVII2C1_IC_RXFLR
+#define CKSVII2C1_IC_RXFLR__RXFLR1__SHIFT 0x0
+#define CKSVII2C1_IC_RXFLR__RXFLR1_MASK 0x0000003FL
+//CKSVII2C1_IC_SDA_HOLD
+#define CKSVII2C1_IC_SDA_HOLD__IC1_SDA_TX_HOLD__SHIFT 0x0
+#define CKSVII2C1_IC_SDA_HOLD__IC1_SDA_RX_HOLD__SHIFT 0x10
+#define CKSVII2C1_IC_SDA_HOLD__IC1_SDA_TX_HOLD_MASK 0x0000FFFFL
+#define CKSVII2C1_IC_SDA_HOLD__IC1_SDA_RX_HOLD_MASK 0x00FF0000L
+//CKSVII2C1_IC_TX_ABRT_SOURCE
+//CKSVII2C1_IC_SLV_DATA_NACK_ONLY
+//CKSVII2C1_IC_DMA_CR
+//CKSVII2C1_IC_DMA_TDLR
+//CKSVII2C1_IC_DMA_RDLR
+//CKSVII2C1_IC_SDA_SETUP
+#define CKSVII2C1_IC_SDA_SETUP__SDA1_SETUP__SHIFT 0x0
+#define CKSVII2C1_IC_SDA_SETUP__SDA1_SETUP_MASK 0x000000FFL
+//CKSVII2C1_IC_ACK_GENERAL_CALL
+#define CKSVII2C1_IC_ACK_GENERAL_CALL__ACK1_GEN_CALL__SHIFT 0x0
+#define CKSVII2C1_IC_ACK_GENERAL_CALL__ACK1_GEN_CALL_MASK 0x00000001L
+//CKSVII2C1_IC_ENABLE_STATUS
+#define CKSVII2C1_IC_ENABLE_STATUS__IC1_EN__SHIFT 0x0
+#define CKSVII2C1_IC_ENABLE_STATUS__SLV1_DISABLED_WHILE_BUSY__SHIFT 0x1
+#define CKSVII2C1_IC_ENABLE_STATUS__SLV1_RX_DATA_LOST__SHIFT 0x2
+#define CKSVII2C1_IC_ENABLE_STATUS__IC1_EN_MASK 0x00000001L
+#define CKSVII2C1_IC_ENABLE_STATUS__SLV1_DISABLED_WHILE_BUSY_MASK 0x00000002L
+#define CKSVII2C1_IC_ENABLE_STATUS__SLV1_RX_DATA_LOST_MASK 0x00000004L
+//CKSVII2C1_IC_FS_SPKLEN
+#define CKSVII2C1_IC_FS_SPKLEN__IC1_FS_SPKLEN__SHIFT 0x0
+#define CKSVII2C1_IC_FS_SPKLEN__IC1_FS_SPKLEN_MASK 0x000000FFL
+//CKSVII2C1_IC_HS_SPKLEN
+#define CKSVII2C1_IC_HS_SPKLEN__IC1_HS_SPKLEN__SHIFT 0x0
+#define CKSVII2C1_IC_HS_SPKLEN__IC1_HS_SPKLEN_MASK 0x000000FFL
+//CKSVII2C1_IC_CLR_RESTART_DET
+//CKSVII2C1_IC_COMP_PARAM_1
+#define CKSVII2C1_IC_COMP_PARAM_1__APB1_DATA_WIDTH__SHIFT 0x0
+#define CKSVII2C1_IC_COMP_PARAM_1__MAX1_SPEED_MODE__SHIFT 0x2
+#define CKSVII2C1_IC_COMP_PARAM_1__HC1_COUNT_VALUES__SHIFT 0x4
+#define CKSVII2C1_IC_COMP_PARAM_1__INTR1_IO__SHIFT 0x5
+#define CKSVII2C1_IC_COMP_PARAM_1__HAS1_DMA__SHIFT 0x6
+#define CKSVII2C1_IC_COMP_PARAM_1__ADD1_ENCODED_PARAMS__SHIFT 0x7
+#define CKSVII2C1_IC_COMP_PARAM_1__RX1_BUFFER_DEPTH__SHIFT 0x8
+#define CKSVII2C1_IC_COMP_PARAM_1__TX1_BUFFER_DEPTH__SHIFT 0x10
+#define CKSVII2C1_IC_COMP_PARAM_1__APB1_DATA_WIDTH_MASK 0x00000003L
+#define CKSVII2C1_IC_COMP_PARAM_1__MAX1_SPEED_MODE_MASK 0x0000000CL
+#define CKSVII2C1_IC_COMP_PARAM_1__HC1_COUNT_VALUES_MASK 0x00000010L
+#define CKSVII2C1_IC_COMP_PARAM_1__INTR1_IO_MASK 0x00000020L
+#define CKSVII2C1_IC_COMP_PARAM_1__HAS1_DMA_MASK 0x00000040L
+#define CKSVII2C1_IC_COMP_PARAM_1__ADD1_ENCODED_PARAMS_MASK 0x00000080L
+#define CKSVII2C1_IC_COMP_PARAM_1__RX1_BUFFER_DEPTH_MASK 0x0000FF00L
+#define CKSVII2C1_IC_COMP_PARAM_1__TX1_BUFFER_DEPTH_MASK 0x00FF0000L
+//CKSVII2C1_IC_COMP_VERSION
+#define CKSVII2C1_IC_COMP_VERSION__IC1_COMP_VERSION__SHIFT 0x0
+#define CKSVII2C1_IC_COMP_VERSION__IC1_COMP_VERSION_MASK 0xFFFFFFFFL
+//CKSVII2C1_IC_COMP_TYPE
+#define CKSVII2C1_IC_COMP_TYPE__IC1_COMP_TYPE__SHIFT 0x0
+#define CKSVII2C1_IC_COMP_TYPE__IC1_COMP_TYPE_MASK 0xFFFFFFFFL
+//SMUIO_MP_RESET_INTR
+#define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR__SHIFT 0x0
+#define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR_MASK 0x00000001L
+//SMUIO_SOC_HALT
+#define SMUIO_SOC_HALT__WDT_FORCE_PWROK_EN__SHIFT 0x2
+#define SMUIO_SOC_HALT__WDT_FORCE_RESETn_EN__SHIFT 0x3
+#define SMUIO_SOC_HALT__WDT_FORCE_PWROK_EN_MASK 0x00000004L
+#define SMUIO_SOC_HALT__WDT_FORCE_RESETn_EN_MASK 0x00000008L
+//SMUIO_PWRMGT
+#define SMUIO_PWRMGT__i2c_clk_gate_en__SHIFT 0x0
+#define SMUIO_PWRMGT__i2c1_clk_gate_en__SHIFT 0x4
+#define SMUIO_PWRMGT__i2c_clk_gate_en_MASK 0x00000001L
+#define SMUIO_PWRMGT__i2c1_clk_gate_en_MASK 0x00000010L
+//SMUIO_GFX_MISC_CNTL
+#define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff__SHIFT 0x0
+#define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff_MASK 0x00000001L
+//ROM_CNTL
+#define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x0
+#define ROM_CNTL__READ_MODE__SHIFT 0x1
+#define ROM_CNTL__READ_MODE_OVERRIDE__SHIFT 0x3
+#define ROM_CNTL__SPI_TIMING_RELAX_SCK__SHIFT 0x4
+#define ROM_CNTL__SPI_TIMING_RELAX_SCK_OVERRIDE__SHIFT 0x5
+#define ROM_CNTL__FOUR_BYTE_ADDRESS_MODE__SHIFT 0x6
+#define ROM_CNTL__DUMMY_CYCLE_NUM__SHIFT 0x8
+#define ROM_CNTL__SPI_TIMING_RELAX__SHIFT 0x14
+#define ROM_CNTL__SPI_TIMING_RELAX_OVERRIDE__SHIFT 0x15
+#define ROM_CNTL__SPI_FAST_MODE__SHIFT 0x16
+#define ROM_CNTL__SPI_FAST_MODE_OVERRIDE__SHIFT 0x17
+#define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT 0x18
+#define ROM_CNTL__SCK_PRESCALE_REFCLK_OVERRIDE__SHIFT 0x1c
+#define ROM_CNTL__ROM_INDEX_ADDRESS_AUTO_INCREASE__SHIFT 0x1d
+#define ROM_CNTL__CLOCK_GATING_EN_MASK 0x00000001L
+#define ROM_CNTL__READ_MODE_MASK 0x00000006L
+#define ROM_CNTL__READ_MODE_OVERRIDE_MASK 0x00000008L
+#define ROM_CNTL__SPI_TIMING_RELAX_SCK_MASK 0x00000010L
+#define ROM_CNTL__SPI_TIMING_RELAX_SCK_OVERRIDE_MASK 0x00000020L
+#define ROM_CNTL__FOUR_BYTE_ADDRESS_MODE_MASK 0x00000040L
+#define ROM_CNTL__DUMMY_CYCLE_NUM_MASK 0x00000F00L
+#define ROM_CNTL__SPI_TIMING_RELAX_MASK 0x00100000L
+#define ROM_CNTL__SPI_TIMING_RELAX_OVERRIDE_MASK 0x00200000L
+#define ROM_CNTL__SPI_FAST_MODE_MASK 0x00400000L
+#define ROM_CNTL__SPI_FAST_MODE_OVERRIDE_MASK 0x00800000L
+#define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK 0x0F000000L
+#define ROM_CNTL__SCK_PRESCALE_REFCLK_OVERRIDE_MASK 0x10000000L
+#define ROM_CNTL__ROM_INDEX_ADDRESS_AUTO_INCREASE_MASK 0x20000000L
+//PAGE_MIRROR_CNTL
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x0
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x19
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x1a
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x1c
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0x01FFFFFFL
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x02000000L
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0x0C000000L
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x10000000L
+//ROM_STATUS
+#define ROM_STATUS__ROM_BUSY__SHIFT 0x0
+#define ROM_STATUS__ROM_BUSY_MASK 0x00000001L
+//CGTT_ROM_CLK_CTRL0
+#define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0
+#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL
+#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L
+//ROM_INDEX
+#define ROM_INDEX__ROM_INDEX__SHIFT 0x0
+#define ROM_INDEX__ROM_INDEX_MASK 0x01FFFFFFL
+//ROM_DATA
+#define ROM_DATA__ROM_DATA__SHIFT 0x0
+#define ROM_DATA__ROM_DATA_MASK 0xFFFFFFFFL
+//ROM_START
+#define ROM_START__ROM_START__SHIFT 0x0
+#define ROM_START__ROM_START_MASK 0x01FFFFFFL
+//ROM_SW_CNTL
+#define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0
+#define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10
+#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x13
+#define ROM_SW_CNTL__DATA_SIZE_MASK 0x0000FFFFL
+#define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x00070000L
+#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x00080000L
+//ROM_SW_STATUS
+#define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0
+#define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x00000001L
+//ROM_SW_COMMAND
+#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0
+#define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8
+#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0x000000FFL
+#define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xFFFFFF00L
+//ROM_SW_DATA_1
+#define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_2
+#define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_3
+#define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_4
+#define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_5
+#define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_6
+#define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_7
+#define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_8
+#define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_9
+#define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_10
+#define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_11
+#define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_12
+#define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_13
+#define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_14
+#define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_15
+#define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_16
+#define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_17
+#define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_18
+#define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_19
+#define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_20
+#define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_21
+#define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_22
+#define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_23
+#define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_24
+#define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_25
+#define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_26
+#define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_27
+#define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_28
+#define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_29
+#define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_30
+#define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_31
+#define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_32
+#define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_33
+#define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_34
+#define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_35
+#define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_36
+#define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_37
+#define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_38
+#define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_39
+#define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_40
+#define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_41
+#define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_42
+#define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_43
+#define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_44
+#define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_45
+#define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_46
+#define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_47
+#define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_48
+#define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_49
+#define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_50
+#define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_51
+#define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_52
+#define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_53
+#define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_54
+#define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_55
+#define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_56
+#define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_57
+#define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_58
+#define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_59
+#define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_60
+#define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_61
+#define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_62
+#define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_63
+#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_64
+#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//SMU_GPIOPAD_SW_INT_STAT
+#define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0
+#define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x00000001L
+//SMU_GPIOPAD_MASK
+#define SMU_GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0
+#define SMU_GPIOPAD_MASK__GPIO_MASK_MASK 0x7FFFFFFFL
+//SMU_GPIOPAD_A
+#define SMU_GPIOPAD_A__GPIO_A__SHIFT 0x0
+#define SMU_GPIOPAD_A__GPIO_A_MASK 0x7FFFFFFFL
+//SMU_GPIOPAD_TXIMPSEL
+#define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL__SHIFT 0x0
+#define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL_MASK 0x7FFFFFFFL
+//SMU_GPIOPAD_EN
+#define SMU_GPIOPAD_EN__GPIO_EN__SHIFT 0x0
+#define SMU_GPIOPAD_EN__GPIO_EN_MASK 0x7FFFFFFFL
+//SMU_GPIOPAD_Y
+#define SMU_GPIOPAD_Y__GPIO_Y__SHIFT 0x0
+#define SMU_GPIOPAD_Y__GPIO_Y_MASK 0x7FFFFFFFL
+//SMU_GPIOPAD_RXEN
+#define SMU_GPIOPAD_RXEN__GPIO_RXEN__SHIFT 0x0
+#define SMU_GPIOPAD_RXEN__GPIO_RXEN_MASK 0x7FFFFFFFL
+//SMU_GPIOPAD_RCVR_SEL0
+#define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0__SHIFT 0x0
+#define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0_MASK 0x7FFFFFFFL
+//SMU_GPIOPAD_RCVR_SEL1
+#define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1__SHIFT 0x0
+#define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1_MASK 0x7FFFFFFFL
+//SMU_GPIOPAD_PU_EN
+#define SMU_GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0
+#define SMU_GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7FFFFFFFL
+//SMU_GPIOPAD_PD_EN
+#define SMU_GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0
+#define SMU_GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7FFFFFFFL
+//SMU_GPIOPAD_PINSTRAPS
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x00000001L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x00000002L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x00000004L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x00000008L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x00000010L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x00000020L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x00000040L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x00000080L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x00000100L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x00000200L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x00000400L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x00000800L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x00001000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x00002000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x00004000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x00008000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x00010000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x00020000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x00040000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x00080000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x00100000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x00200000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x00400000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x00800000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x01000000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x02000000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x04000000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x08000000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000L
+//DFT_PINSTRAPS
+#define DFT_PINSTRAPS__DFT_PINSTRAPS__SHIFT 0x0
+#define DFT_PINSTRAPS__DFT_PINSTRAPS_MASK 0x000003FFL
+//SMU_GPIOPAD_INT_STAT_EN
+#define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0
+#define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f
+#define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1FFFFFFFL
+#define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000L
+//SMU_GPIOPAD_INT_STAT
+#define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0
+#define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f
+#define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1FFFFFFFL
+#define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000L
+//SMU_GPIOPAD_INT_STAT_AK
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c
+#define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x00000001L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x00000002L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x00000004L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x00000008L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x00000010L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x00000020L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x00000040L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x00000080L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x00000100L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x00000200L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x00000400L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x00000800L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x00001000L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x00002000L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x00004000L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x00008000L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x00010000L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x00020000L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x00040000L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x00080000L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x00100000L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x00200000L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x00400000L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x00800000L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x01000000L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x02000000L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x04000000L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x08000000L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000L
+#define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000L
+//SMU_GPIOPAD_INT_EN
+#define SMU_GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0
+#define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f
+#define SMU_GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1FFFFFFFL
+#define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000L
+//SMU_GPIOPAD_INT_TYPE
+#define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0
+#define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f
+#define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1FFFFFFFL
+#define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000L
+//SMU_GPIOPAD_INT_POLARITY
+#define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0
+#define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f
+#define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1FFFFFFFL
+#define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000L
+//ROM_CC_BIF_PINSTRAP
+#define ROM_CC_BIF_PINSTRAP__BIOS_ROM_EN__SHIFT 0x0
+#define ROM_CC_BIF_PINSTRAP__BIF_MEM_AP_SIZE__SHIFT 0x1
+#define ROM_CC_BIF_PINSTRAP__ROM_CONFIG__SHIFT 0x4
+#define ROM_CC_BIF_PINSTRAP__BIF_GEN3_DIS_A__SHIFT 0x7
+#define ROM_CC_BIF_PINSTRAP__BIF_CLK_PM_EN__SHIFT 0x8
+#define ROM_CC_BIF_PINSTRAP__BIF_VGA_DIS__SHIFT 0x9
+#define ROM_CC_BIF_PINSTRAP__BIF_LC_TX_SWING__SHIFT 0xa
+#define ROM_CC_BIF_PINSTRAP__BIOS_ROM_EN_MASK 0x00000001L
+#define ROM_CC_BIF_PINSTRAP__BIF_MEM_AP_SIZE_MASK 0x0000000EL
+#define ROM_CC_BIF_PINSTRAP__ROM_CONFIG_MASK 0x00000070L
+#define ROM_CC_BIF_PINSTRAP__BIF_GEN3_DIS_A_MASK 0x00000080L
+#define ROM_CC_BIF_PINSTRAP__BIF_CLK_PM_EN_MASK 0x00000100L
+#define ROM_CC_BIF_PINSTRAP__BIF_VGA_DIS_MASK 0x00000200L
+#define ROM_CC_BIF_PINSTRAP__BIF_LC_TX_SWING_MASK 0x00000400L
+//IO_SMUIO_PINSTRAP
+#define IO_SMUIO_PINSTRAP__AUD_PORT_CONN__SHIFT 0x0
+#define IO_SMUIO_PINSTRAP__AUD__SHIFT 0x3
+#define IO_SMUIO_PINSTRAP__BOARD_CONFIG__SHIFT 0x5
+#define IO_SMUIO_PINSTRAP__SMBUS_ADDR__SHIFT 0x8
+#define IO_SMUIO_PINSTRAP__AUD_PORT_CONN_MASK 0x00000007L
+#define IO_SMUIO_PINSTRAP__AUD_MASK 0x00000018L
+#define IO_SMUIO_PINSTRAP__BOARD_CONFIG_MASK 0x000000E0L
+#define IO_SMUIO_PINSTRAP__SMBUS_ADDR_MASK 0x00000100L
+//SMUIO_PCC_CONTROL
+#define SMUIO_PCC_CONTROL__PCC_POLARITY__SHIFT 0x0
+#define SMUIO_PCC_CONTROL__PCC_POLARITY_MASK 0x00000001L
+//SMUIO_PCC_GPIO_SELECT
+#define SMUIO_PCC_GPIO_SELECT__GPIO__SHIFT 0x0
+#define SMUIO_PCC_GPIO_SELECT__GPIO_MASK 0xFFFFFFFFL
+//SMUIO_GPIO_INT0_SELECT
+#define SMUIO_GPIO_INT0_SELECT__GPIO_INT0_SELECT__SHIFT 0x0
+#define SMUIO_GPIO_INT0_SELECT__GPIO_INT0_SELECT_MASK 0xFFFFFFFFL
+//SMUIO_GPIO_INT1_SELECT
+#define SMUIO_GPIO_INT1_SELECT__GPIO_INT1_SELECT__SHIFT 0x0
+#define SMUIO_GPIO_INT1_SELECT__GPIO_INT1_SELECT_MASK 0xFFFFFFFFL
+//SMUIO_GPIO_INT2_SELECT
+#define SMUIO_GPIO_INT2_SELECT__GPIO_INT2_SELECT__SHIFT 0x0
+#define SMUIO_GPIO_INT2_SELECT__GPIO_INT2_SELECT_MASK 0xFFFFFFFFL
+//SMUIO_GPIO_INT3_SELECT
+#define SMUIO_GPIO_INT3_SELECT__GPIO_INT3_SELECT__SHIFT 0x0
+#define SMUIO_GPIO_INT3_SELECT__GPIO_INT3_SELECT_MASK 0xFFFFFFFFL
+//SMU_GPIOPAD_MP_INT0_STAT
+#define SMU_GPIOPAD_MP_INT0_STAT__GPIO_MP_INT0_STAT__SHIFT 0x0
+#define SMU_GPIOPAD_MP_INT0_STAT__GPIO_MP_INT0_STAT_MASK 0x1FFFFFFFL
+//SMU_GPIOPAD_MP_INT1_STAT
+#define SMU_GPIOPAD_MP_INT1_STAT__GPIO_MP_INT1_STAT__SHIFT 0x0
+#define SMU_GPIOPAD_MP_INT1_STAT__GPIO_MP_INT1_STAT_MASK 0x1FFFFFFFL
+//SMU_GPIOPAD_MP_INT2_STAT
+#define SMU_GPIOPAD_MP_INT2_STAT__GPIO_MP_INT2_STAT__SHIFT 0x0
+#define SMU_GPIOPAD_MP_INT2_STAT__GPIO_MP_INT2_STAT_MASK 0x1FFFFFFFL
+//SMU_GPIOPAD_MP_INT3_STAT
+#define SMU_GPIOPAD_MP_INT3_STAT__GPIO_MP_INT3_STAT__SHIFT 0x0
+#define SMU_GPIOPAD_MP_INT3_STAT__GPIO_MP_INT3_STAT_MASK 0x1FFFFFFFL
+//SMIO_INDEX
+#define SMIO_INDEX__SW_SMIO_INDEX__SHIFT 0x0
+#define SMIO_INDEX__SW_SMIO_INDEX_MASK 0x00000001L
+//S0_VID_SMIO_CNTL
+#define S0_VID_SMIO_CNTL__S0_SMIO_VALUES__SHIFT 0x0
+#define S0_VID_SMIO_CNTL__S0_SMIO_VALUES_MASK 0xFFFFFFFFL
+//S1_VID_SMIO_CNTL
+#define S1_VID_SMIO_CNTL__S1_SMIO_VALUES__SHIFT 0x0
+#define S1_VID_SMIO_CNTL__S1_SMIO_VALUES_MASK 0xFFFFFFFFL
+//OPEN_DRAIN_SELECT
+#define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT__SHIFT 0x0
+#define OPEN_DRAIN_SELECT__RESERVED__SHIFT 0x1f
+#define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT_MASK 0x7FFFFFFFL
+#define OPEN_DRAIN_SELECT__RESERVED_MASK 0x80000000L
+//SMIO_ENABLE
+#define SMIO_ENABLE__SMIO_ENABLE__SHIFT 0x0
+#define SMIO_ENABLE__SMIO_ENABLE_MASK 0xFFFFFFFFL
+//SMU_GPIOPAD_S0
+#define SMU_GPIOPAD_S0__GPIO_S0__SHIFT 0x0
+#define SMU_GPIOPAD_S0__GPIO_S0_MASK 0x7FFFFFFFL
+//SMU_GPIOPAD_S1
+#define SMU_GPIOPAD_S1__GPIO_S1__SHIFT 0x0
+#define SMU_GPIOPAD_S1__GPIO_S1_MASK 0x7FFFFFFFL
+//SMU_GPIOPAD_SCL_EN
+#define SMU_GPIOPAD_SCL_EN__GPIO_SCL_EN__SHIFT 0x0
+#define SMU_GPIOPAD_SCL_EN__GPIO_SCL_EN_MASK 0x7FFFFFFFL
+//SMU_GPIOPAD_SDA_EN
+#define SMU_GPIOPAD_SDA_EN__GPIO_SDA_EN__SHIFT 0x0
+#define SMU_GPIOPAD_SDA_EN__GPIO_SDA_EN_MASK 0x7FFFFFFFL
+//SMU_GPIOPAD_SCHMEN
+#define SMU_GPIOPAD_SCHMEN__GPIO_SCHMEN__SHIFT 0x0
+#define SMU_GPIOPAD_SCHMEN__GPIO_SCHMEN_MASK 0x7FFFFFFFL
+
+
+// addressBlock: smuio_smuio_pwr_SmuSmuioDec
+//IP_DISCOVERY_VERSION
+#define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION__SHIFT 0x0
+#define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION_MASK 0xFFFFFFFFL
+//SOC_GAP_PWROK
+#define SOC_GAP_PWROK__soc_gap_pwrok__SHIFT 0x0
+#define SOC_GAP_PWROK__soc_gap_pwrok_MASK 0x00000001L
+//GFX_GAP_PWROK
+#define GFX_GAP_PWROK__gfx_gap_pwrok__SHIFT 0x0
+#define GFX_GAP_PWROK__gfx_gap_pwrok_MASK 0x00000001L
+//PWROK_REFCLK_GAP_CYCLES
+#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles__SHIFT 0x0
+#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles__SHIFT 0x8
+#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles_MASK 0x000000FFL
+#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles_MASK 0x0000FF00L
+//GOLDEN_TSC_INCREMENT_UPPER
+#define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper__SHIFT 0x0
+#define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper_MASK 0x00FFFFFFL
+//GOLDEN_TSC_INCREMENT_LOWER
+#define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower__SHIFT 0x0
+#define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower_MASK 0xFFFFFFFFL
+//GOLDEN_TSC_COUNT_UPPER
+#define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper__SHIFT 0x0
+#define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper_MASK 0x00FFFFFFL
+//GOLDEN_TSC_COUNT_LOWER
+#define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower__SHIFT 0x0
+#define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower_MASK 0xFFFFFFFFL
+//SOC_GOLDEN_TSC_SHADOW_UPPER
+#define SOC_GOLDEN_TSC_SHADOW_UPPER__SOCGoldenTscShadowUpper__SHIFT 0x0
+#define SOC_GOLDEN_TSC_SHADOW_UPPER__SOCGoldenTscShadowUpper_MASK 0x00FFFFFFL
+//SOC_GOLDEN_TSC_SHADOW_LOWER
+#define SOC_GOLDEN_TSC_SHADOW_LOWER__SOCGoldenTscShadowLower__SHIFT 0x0
+#define SOC_GOLDEN_TSC_SHADOW_LOWER__SOCGoldenTscShadowLower_MASK 0xFFFFFFFFL
+//GFX_GOLDEN_TSC_SHADOW_UPPER
+#define GFX_GOLDEN_TSC_SHADOW_UPPER__GFXGoldenTscShadowUpper__SHIFT 0x0
+#define GFX_GOLDEN_TSC_SHADOW_UPPER__GFXGoldenTscShadowUpper_MASK 0x00FFFFFFL
+//GFX_GOLDEN_TSC_SHADOW_LOWER
+#define GFX_GOLDEN_TSC_SHADOW_LOWER__GFXGoldenTscShadowLower__SHIFT 0x0
+#define GFX_GOLDEN_TSC_SHADOW_LOWER__GFXGoldenTscShadowLower_MASK 0xFFFFFFFFL
+//SCRATCH_REGISTER0
+#define SCRATCH_REGISTER0__ScratchPad0__SHIFT 0x0
+#define SCRATCH_REGISTER0__ScratchPad0_MASK 0xFFFFFFFFL
+//SCRATCH_REGISTER1
+#define SCRATCH_REGISTER1__ScratchPad1__SHIFT 0x0
+#define SCRATCH_REGISTER1__ScratchPad1_MASK 0xFFFFFFFFL
+//SCRATCH_REGISTER2
+#define SCRATCH_REGISTER2__ScratchPad2__SHIFT 0x0
+#define SCRATCH_REGISTER2__ScratchPad2_MASK 0xFFFFFFFFL
+//SCRATCH_REGISTER3
+#define SCRATCH_REGISTER3__ScratchPad3__SHIFT 0x0
+#define SCRATCH_REGISTER3__ScratchPad3_MASK 0xFFFFFFFFL
+//SCRATCH_REGISTER4
+#define SCRATCH_REGISTER4__ScratchPad4__SHIFT 0x0
+#define SCRATCH_REGISTER4__ScratchPad4_MASK 0xFFFFFFFFL
+//SCRATCH_REGISTER5
+#define SCRATCH_REGISTER5__ScratchPad5__SHIFT 0x0
+#define SCRATCH_REGISTER5__ScratchPad5_MASK 0xFFFFFFFFL
+//SCRATCH_REGISTER6
+#define SCRATCH_REGISTER6__ScratchPad6__SHIFT 0x0
+#define SCRATCH_REGISTER6__ScratchPad6_MASK 0xFFFFFFFFL
+//SCRATCH_REGISTER7
+#define SCRATCH_REGISTER7__ScratchPad7__SHIFT 0x0
+#define SCRATCH_REGISTER7__ScratchPad7_MASK 0xFFFFFFFFL
+//PWR_DISP_TIMER_CONTROL
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L
+//PWR_DISP_TIMER_DEBUG
+#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT 0x0
+#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT__SHIFT 0x1
+#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT__SHIFT 0x2
+#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL__SHIFT 0x7
+#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING_MASK 0x00000001L
+#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT_MASK 0x00000002L
+#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_MASK 0x00000004L
+#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL_MASK 0xFFFFFF80L
+//PWR_DISP_TIMER2_CONTROL
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L
+//PWR_DISP_TIMER2_DEBUG
+#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT 0x0
+#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT__SHIFT 0x1
+#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT__SHIFT 0x2
+#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL__SHIFT 0x7
+#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING_MASK 0x00000001L
+#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT_MASK 0x00000002L
+#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_MASK 0x00000004L
+#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL_MASK 0xFFFFFF80L
+//PWR_DISP_TIMER_GLOBAL_CONTROL
+#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH__SHIFT 0x0
+#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN__SHIFT 0xa
+#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH_MASK 0x000003FFL
+#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN_MASK 0x00000400L
+//PWR_IH_CONTROL
+#define PWR_IH_CONTROL__MAX_CREDIT__SHIFT 0x0
+#define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK__SHIFT 0x5
+#define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK__SHIFT 0x6
+#define PWR_IH_CONTROL__MAX_CREDIT_MASK 0x0000001FL
+#define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK_MASK 0x00000020L
+#define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK_MASK 0x00000040L
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_13_0_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_13_0_2_offset.h
new file mode 100644
index 000000000000..ea03c9d135e9
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_13_0_2_offset.h
@@ -0,0 +1,346 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ *
+ */
+#ifndef _thm_13_0_2_OFFSET_HEADER
+#define _thm_13_0_2_OFFSET_HEADER
+
+
+
+// addressBlock: thm_thm_SmuThmDec
+// base address: 0x59800
+#define regTHM_TCON_CUR_TMP 0x0000
+#define regTHM_TCON_CUR_TMP_BASE_IDX 0
+#define regTHM_TCON_HTC 0x0001
+#define regTHM_TCON_HTC_BASE_IDX 0
+#define regTHM_TCON_THERM_TRIP 0x0002
+#define regTHM_TCON_THERM_TRIP_BASE_IDX 0
+#define regTHM_CTF_DELAY 0x0003
+#define regTHM_CTF_DELAY_BASE_IDX 0
+#define regTHM_GPIO_PROCHOT_CTRL 0x0004
+#define regTHM_GPIO_PROCHOT_CTRL_BASE_IDX 0
+#define regTHM_GPIO_THERMTRIP_CTRL 0x0005
+#define regTHM_GPIO_THERMTRIP_CTRL_BASE_IDX 0
+#define regTHM_GPIO_PWM_CTRL 0x0006
+#define regTHM_GPIO_PWM_CTRL_BASE_IDX 0
+#define regTHM_GPIO_TACHIN_CTRL 0x0007
+#define regTHM_GPIO_TACHIN_CTRL_BASE_IDX 0
+#define regTHM_GPIO_PUMPOUT_CTRL 0x0008
+#define regTHM_GPIO_PUMPOUT_CTRL_BASE_IDX 0
+#define regTHM_GPIO_PUMPIN_CTRL 0x0009
+#define regTHM_GPIO_PUMPIN_CTRL_BASE_IDX 0
+#define regTHM_THERMAL_INT_ENA 0x000a
+#define regTHM_THERMAL_INT_ENA_BASE_IDX 0
+#define regTHM_THERMAL_INT_CTRL 0x000b
+#define regTHM_THERMAL_INT_CTRL_BASE_IDX 0
+#define regTHM_THERMAL_INT_STATUS 0x000c
+#define regTHM_THERMAL_INT_STATUS_BASE_IDX 0
+#define regTHM_TMON0_RDIL0_DATA 0x000d
+#define regTHM_TMON0_RDIL0_DATA_BASE_IDX 0
+#define regTHM_TMON0_RDIL1_DATA 0x000e
+#define regTHM_TMON0_RDIL1_DATA_BASE_IDX 0
+#define regTHM_TMON0_RDIL2_DATA 0x000f
+#define regTHM_TMON0_RDIL2_DATA_BASE_IDX 0
+#define regTHM_TMON0_RDIL3_DATA 0x0010
+#define regTHM_TMON0_RDIL3_DATA_BASE_IDX 0
+#define regTHM_TMON0_RDIL4_DATA 0x0011
+#define regTHM_TMON0_RDIL4_DATA_BASE_IDX 0
+#define regTHM_TMON0_RDIL5_DATA 0x0012
+#define regTHM_TMON0_RDIL5_DATA_BASE_IDX 0
+#define regTHM_TMON0_RDIL6_DATA 0x0013
+#define regTHM_TMON0_RDIL6_DATA_BASE_IDX 0
+#define regTHM_TMON0_RDIL7_DATA 0x0014
+#define regTHM_TMON0_RDIL7_DATA_BASE_IDX 0
+#define regTHM_TMON0_RDIL8_DATA 0x0015
+#define regTHM_TMON0_RDIL8_DATA_BASE_IDX 0
+#define regTHM_TMON0_RDIL9_DATA 0x0016
+#define regTHM_TMON0_RDIL9_DATA_BASE_IDX 0
+#define regTHM_TMON0_RDIL10_DATA 0x0017
+#define regTHM_TMON0_RDIL10_DATA_BASE_IDX 0
+#define regTHM_TMON0_RDIL11_DATA 0x0018
+#define regTHM_TMON0_RDIL11_DATA_BASE_IDX 0
+#define regTHM_TMON0_RDIL12_DATA 0x0019
+#define regTHM_TMON0_RDIL12_DATA_BASE_IDX 0
+#define regTHM_TMON0_RDIL13_DATA 0x001a
+#define regTHM_TMON0_RDIL13_DATA_BASE_IDX 0
+#define regTHM_TMON0_RDIL14_DATA 0x001b
+#define regTHM_TMON0_RDIL14_DATA_BASE_IDX 0
+#define regTHM_TMON0_RDIL15_DATA 0x001c
+#define regTHM_TMON0_RDIL15_DATA_BASE_IDX 0
+#define regTHM_TMON0_RDIR0_DATA 0x001d
+#define regTHM_TMON0_RDIR0_DATA_BASE_IDX 0
+#define regTHM_TMON0_RDIR1_DATA 0x001e
+#define regTHM_TMON0_RDIR1_DATA_BASE_IDX 0
+#define regTHM_TMON0_RDIR2_DATA 0x001f
+#define regTHM_TMON0_RDIR2_DATA_BASE_IDX 0
+#define regTHM_TMON0_RDIR3_DATA 0x0020
+#define regTHM_TMON0_RDIR3_DATA_BASE_IDX 0
+#define regTHM_TMON0_RDIR4_DATA 0x0021
+#define regTHM_TMON0_RDIR4_DATA_BASE_IDX 0
+#define regTHM_TMON0_RDIR5_DATA 0x0022
+#define regTHM_TMON0_RDIR5_DATA_BASE_IDX 0
+#define regTHM_TMON0_RDIR6_DATA 0x0023
+#define regTHM_TMON0_RDIR6_DATA_BASE_IDX 0
+#define regTHM_TMON0_RDIR7_DATA 0x0024
+#define regTHM_TMON0_RDIR7_DATA_BASE_IDX 0
+#define regTHM_TMON0_RDIR8_DATA 0x0025
+#define regTHM_TMON0_RDIR8_DATA_BASE_IDX 0
+#define regTHM_TMON0_RDIR9_DATA 0x0026
+#define regTHM_TMON0_RDIR9_DATA_BASE_IDX 0
+#define regTHM_TMON0_RDIR10_DATA 0x0027
+#define regTHM_TMON0_RDIR10_DATA_BASE_IDX 0
+#define regTHM_TMON0_RDIR11_DATA 0x0028
+#define regTHM_TMON0_RDIR11_DATA_BASE_IDX 0
+#define regTHM_TMON0_RDIR12_DATA 0x0029
+#define regTHM_TMON0_RDIR12_DATA_BASE_IDX 0
+#define regTHM_TMON0_RDIR13_DATA 0x002a
+#define regTHM_TMON0_RDIR13_DATA_BASE_IDX 0
+#define regTHM_TMON0_RDIR14_DATA 0x002b
+#define regTHM_TMON0_RDIR14_DATA_BASE_IDX 0
+#define regTHM_TMON0_RDIR15_DATA 0x002c
+#define regTHM_TMON0_RDIR15_DATA_BASE_IDX 0
+#define regTHM_TMON0_INT_DATA 0x002d
+#define regTHM_TMON0_INT_DATA_BASE_IDX 0
+#define regTHM_TMON0_CTRL 0x002e
+#define regTHM_TMON0_CTRL_BASE_IDX 0
+#define regTHM_TMON0_CTRL2 0x002f
+#define regTHM_TMON0_CTRL2_BASE_IDX 0
+#define regTHM_TMON1_RDIL0_DATA 0x0031
+#define regTHM_TMON1_RDIL0_DATA_BASE_IDX 0
+#define regTHM_TMON1_RDIL1_DATA 0x0032
+#define regTHM_TMON1_RDIL1_DATA_BASE_IDX 0
+#define regTHM_TMON1_RDIL2_DATA 0x0033
+#define regTHM_TMON1_RDIL2_DATA_BASE_IDX 0
+#define regTHM_TMON1_RDIL3_DATA 0x0034
+#define regTHM_TMON1_RDIL3_DATA_BASE_IDX 0
+#define regTHM_TMON1_RDIL4_DATA 0x0035
+#define regTHM_TMON1_RDIL4_DATA_BASE_IDX 0
+#define regTHM_TMON1_RDIL5_DATA 0x0036
+#define regTHM_TMON1_RDIL5_DATA_BASE_IDX 0
+#define regTHM_TMON1_RDIL6_DATA 0x0037
+#define regTHM_TMON1_RDIL6_DATA_BASE_IDX 0
+#define regTHM_TMON1_RDIL7_DATA 0x0038
+#define regTHM_TMON1_RDIL7_DATA_BASE_IDX 0
+#define regTHM_TMON1_RDIL8_DATA 0x0039
+#define regTHM_TMON1_RDIL8_DATA_BASE_IDX 0
+#define regTHM_TMON1_RDIL9_DATA 0x003a
+#define regTHM_TMON1_RDIL9_DATA_BASE_IDX 0
+#define regTHM_TMON1_RDIL10_DATA 0x003b
+#define regTHM_TMON1_RDIL10_DATA_BASE_IDX 0
+#define regTHM_TMON1_RDIL11_DATA 0x003c
+#define regTHM_TMON1_RDIL11_DATA_BASE_IDX 0
+#define regTHM_TMON1_RDIL12_DATA 0x003d
+#define regTHM_TMON1_RDIL12_DATA_BASE_IDX 0
+#define regTHM_TMON1_RDIL13_DATA 0x003e
+#define regTHM_TMON1_RDIL13_DATA_BASE_IDX 0
+#define regTHM_TMON1_RDIL14_DATA 0x003f
+#define regTHM_TMON1_RDIL14_DATA_BASE_IDX 0
+#define regTHM_TMON1_RDIL15_DATA 0x0040
+#define regTHM_TMON1_RDIL15_DATA_BASE_IDX 0
+#define regTHM_TMON1_RDIR0_DATA 0x0041
+#define regTHM_TMON1_RDIR0_DATA_BASE_IDX 0
+#define regTHM_TMON1_RDIR1_DATA 0x0042
+#define regTHM_TMON1_RDIR1_DATA_BASE_IDX 0
+#define regTHM_TMON1_RDIR2_DATA 0x0043
+#define regTHM_TMON1_RDIR2_DATA_BASE_IDX 0
+#define regTHM_TMON1_RDIR3_DATA 0x0044
+#define regTHM_TMON1_RDIR3_DATA_BASE_IDX 0
+#define regTHM_TMON1_RDIR4_DATA 0x0045
+#define regTHM_TMON1_RDIR4_DATA_BASE_IDX 0
+#define regTHM_TMON1_RDIR5_DATA 0x0046
+#define regTHM_TMON1_RDIR5_DATA_BASE_IDX 0
+#define regTHM_TMON1_RDIR6_DATA 0x0047
+#define regTHM_TMON1_RDIR6_DATA_BASE_IDX 0
+#define regTHM_TMON1_RDIR7_DATA 0x0048
+#define regTHM_TMON1_RDIR7_DATA_BASE_IDX 0
+#define regTHM_TMON1_RDIR8_DATA 0x0049
+#define regTHM_TMON1_RDIR8_DATA_BASE_IDX 0
+#define regTHM_TMON1_RDIR9_DATA 0x004a
+#define regTHM_TMON1_RDIR9_DATA_BASE_IDX 0
+#define regTHM_TMON1_RDIR10_DATA 0x004b
+#define regTHM_TMON1_RDIR10_DATA_BASE_IDX 0
+#define regTHM_TMON1_RDIR11_DATA 0x004c
+#define regTHM_TMON1_RDIR11_DATA_BASE_IDX 0
+#define regTHM_TMON1_RDIR12_DATA 0x004d
+#define regTHM_TMON1_RDIR12_DATA_BASE_IDX 0
+#define regTHM_TMON1_RDIR13_DATA 0x004e
+#define regTHM_TMON1_RDIR13_DATA_BASE_IDX 0
+#define regTHM_TMON1_RDIR14_DATA 0x004f
+#define regTHM_TMON1_RDIR14_DATA_BASE_IDX 0
+#define regTHM_TMON1_RDIR15_DATA 0x0050
+#define regTHM_TMON1_RDIR15_DATA_BASE_IDX 0
+#define regTHM_TMON1_INT_DATA 0x0051
+#define regTHM_TMON1_INT_DATA_BASE_IDX 0
+#define regTHM_DIE1_TEMP 0x0079
+#define regTHM_DIE1_TEMP_BASE_IDX 0
+#define regTHM_DIE2_TEMP 0x007a
+#define regTHM_DIE2_TEMP_BASE_IDX 0
+#define regTHM_DIE3_TEMP 0x007b
+#define regTHM_DIE3_TEMP_BASE_IDX 0
+#define regTHM_SW_TEMP 0x0081
+#define regTHM_SW_TEMP_BASE_IDX 0
+#define regCG_MULT_THERMAL_CTRL 0x0082
+#define regCG_MULT_THERMAL_CTRL_BASE_IDX 0
+#define regCG_MULT_THERMAL_STATUS 0x0083
+#define regCG_MULT_THERMAL_STATUS_BASE_IDX 0
+#define regCG_THERMAL_RANGE 0x0084
+#define regCG_THERMAL_RANGE_BASE_IDX 0
+#define regTHM_TMON_CONFIG 0x0085
+#define regTHM_TMON_CONFIG_BASE_IDX 0
+#define regTHM_TMON_CONFIG2 0x0086
+#define regTHM_TMON_CONFIG2_BASE_IDX 0
+#define regTHM_TMON0_COEFF 0x0087
+#define regTHM_TMON0_COEFF_BASE_IDX 0
+#define regTHM_TMON1_COEFF 0x0088
+#define regTHM_TMON1_COEFF_BASE_IDX 0
+#define regCG_FDO_CTRL0 0x008b
+#define regCG_FDO_CTRL0_BASE_IDX 0
+#define regCG_FDO_CTRL1 0x008c
+#define regCG_FDO_CTRL1_BASE_IDX 0
+#define regCG_FDO_CTRL2 0x008d
+#define regCG_FDO_CTRL2_BASE_IDX 0
+#define regCG_TACH_CTRL 0x008e
+#define regCG_TACH_CTRL_BASE_IDX 0
+#define regCG_TACH_STATUS 0x008f
+#define regCG_TACH_STATUS_BASE_IDX 0
+#define regCG_THERMAL_STATUS 0x0090
+#define regCG_THERMAL_STATUS_BASE_IDX 0
+#define regCG_PUMP_CTRL0 0x0091
+#define regCG_PUMP_CTRL0_BASE_IDX 0
+#define regCG_PUMP_CTRL1 0x0092
+#define regCG_PUMP_CTRL1_BASE_IDX 0
+#define regCG_PUMP_CTRL2 0x0093
+#define regCG_PUMP_CTRL2_BASE_IDX 0
+#define regCG_PUMP_TACH_CTRL 0x0094
+#define regCG_PUMP_TACH_CTRL_BASE_IDX 0
+#define regCG_PUMP_TACH_STATUS 0x0095
+#define regCG_PUMP_TACH_STATUS_BASE_IDX 0
+#define regCG_PUMP_STATUS 0x0096
+#define regCG_PUMP_STATUS_BASE_IDX 0
+#define regTHM_TCON_LOCAL0 0x0097
+#define regTHM_TCON_LOCAL0_BASE_IDX 0
+#define regTHM_TCON_LOCAL1 0x0098
+#define regTHM_TCON_LOCAL1_BASE_IDX 0
+#define regTHM_TCON_LOCAL2 0x0099
+#define regTHM_TCON_LOCAL2_BASE_IDX 0
+#define regTHM_TCON_LOCAL3 0x009a
+#define regTHM_TCON_LOCAL3_BASE_IDX 0
+#define regTHM_TCON_LOCAL4 0x009b
+#define regTHM_TCON_LOCAL4_BASE_IDX 0
+#define regTHM_TCON_LOCAL5 0x009c
+#define regTHM_TCON_LOCAL5_BASE_IDX 0
+#define regTHM_TCON_LOCAL6 0x009d
+#define regTHM_TCON_LOCAL6_BASE_IDX 0
+#define regTHM_TCON_LOCAL7 0x009e
+#define regTHM_TCON_LOCAL7_BASE_IDX 0
+#define regTHM_TCON_LOCAL8 0x009f
+#define regTHM_TCON_LOCAL8_BASE_IDX 0
+#define regTHM_TCON_LOCAL9 0x00a0
+#define regTHM_TCON_LOCAL9_BASE_IDX 0
+#define regTHM_TCON_LOCAL10 0x00a1
+#define regTHM_TCON_LOCAL10_BASE_IDX 0
+#define regTHM_TCON_LOCAL11 0x00a2
+#define regTHM_TCON_LOCAL11_BASE_IDX 0
+#define regTHM_TCON_LOCAL12 0x00a3
+#define regTHM_TCON_LOCAL12_BASE_IDX 0
+#define regTHM_TCON_LOCAL14 0x00a4
+#define regTHM_TCON_LOCAL14_BASE_IDX 0
+#define regTHM_TCON_LOCAL15 0x00a5
+#define regTHM_TCON_LOCAL15_BASE_IDX 0
+#define regTHM_TCON_LOCAL13 0x00a6
+#define regTHM_TCON_LOCAL13_BASE_IDX 0
+#define regXTAL_CNTL 0x00ac
+#define regXTAL_CNTL_BASE_IDX 0
+#define regTHM_PWRMGT 0x00ad
+#define regTHM_PWRMGT_BASE_IDX 0
+#define regTHM_GPIO_MACO_EN_CTRL 0x00ae
+#define regTHM_GPIO_MACO_EN_CTRL_BASE_IDX 0
+#define regSBTSI_REMOTE_TEMP 0x00ca
+#define regSBTSI_REMOTE_TEMP_BASE_IDX 0
+#define regSBRMI_CONTROL 0x00cb
+#define regSBRMI_CONTROL_BASE_IDX 0
+#define regSBRMI_COMMAND 0x00cc
+#define regSBRMI_COMMAND_BASE_IDX 0
+#define regSBRMI_WRITE_DATA0 0x00cd
+#define regSBRMI_WRITE_DATA0_BASE_IDX 0
+#define regSBRMI_WRITE_DATA1 0x00ce
+#define regSBRMI_WRITE_DATA1_BASE_IDX 0
+#define regSBRMI_WRITE_DATA2 0x00cf
+#define regSBRMI_WRITE_DATA2_BASE_IDX 0
+#define regSBRMI_READ_DATA0 0x00d0
+#define regSBRMI_READ_DATA0_BASE_IDX 0
+#define regSBRMI_READ_DATA1 0x00d1
+#define regSBRMI_READ_DATA1_BASE_IDX 0
+#define regSBRMI_CORE_EN_NUMBER 0x00d2
+#define regSBRMI_CORE_EN_NUMBER_BASE_IDX 0
+#define regSBRMI_CORE_EN_STATUS0 0x00d3
+#define regSBRMI_CORE_EN_STATUS0_BASE_IDX 0
+#define regSBRMI_CORE_EN_STATUS1 0x00d4
+#define regSBRMI_CORE_EN_STATUS1_BASE_IDX 0
+#define regSBRMI_APIC_STATUS0 0x00d5
+#define regSBRMI_APIC_STATUS0_BASE_IDX 0
+#define regSBRMI_APIC_STATUS1 0x00d6
+#define regSBRMI_APIC_STATUS1_BASE_IDX 0
+#define regSBRMI_MCE_STATUS0 0x00db
+#define regSBRMI_MCE_STATUS0_BASE_IDX 0
+#define regSBRMI_MCE_STATUS1 0x00dc
+#define regSBRMI_MCE_STATUS1_BASE_IDX 0
+#define regSMBUS_CNTL0 0x00df
+#define regSMBUS_CNTL0_BASE_IDX 0
+#define regSMBUS_CNTL1 0x00e0
+#define regSMBUS_CNTL1_BASE_IDX 0
+#define regSMBUS_BLKWR_CMD_CTRL0 0x00e1
+#define regSMBUS_BLKWR_CMD_CTRL0_BASE_IDX 0
+#define regSMBUS_BLKWR_CMD_CTRL1 0x00e2
+#define regSMBUS_BLKWR_CMD_CTRL1_BASE_IDX 0
+#define regSMBUS_BLKRD_CMD_CTRL0 0x00e3
+#define regSMBUS_BLKRD_CMD_CTRL0_BASE_IDX 0
+#define regSMBUS_BLKRD_CMD_CTRL1 0x00e4
+#define regSMBUS_BLKRD_CMD_CTRL1_BASE_IDX 0
+#define regSMBUS_TIMING_CNTL0 0x00e5
+#define regSMBUS_TIMING_CNTL0_BASE_IDX 0
+#define regSMBUS_TIMING_CNTL1 0x00e6
+#define regSMBUS_TIMING_CNTL1_BASE_IDX 0
+#define regSMBUS_TIMING_CNTL2 0x00e7
+#define regSMBUS_TIMING_CNTL2_BASE_IDX 0
+#define regSMBUS_TRIGGER_CNTL 0x00e8
+#define regSMBUS_TRIGGER_CNTL_BASE_IDX 0
+#define regSMBUS_UDID_CNTL0 0x00e9
+#define regSMBUS_UDID_CNTL0_BASE_IDX 0
+#define regSMBUS_UDID_CNTL1 0x00ea
+#define regSMBUS_UDID_CNTL1_BASE_IDX 0
+#define regSMBUS_UDID_CNTL2 0x00eb
+#define regSMBUS_UDID_CNTL2_BASE_IDX 0
+#define regTHM_TMON0_REMOTE_START 0x0100
+#define regTHM_TMON0_REMOTE_START_BASE_IDX 0
+#define regTHM_TMON0_REMOTE_END 0x013f
+#define regTHM_TMON0_REMOTE_END_BASE_IDX 0
+#define regTHM_TMON1_REMOTE_START 0x0140
+#define regTHM_TMON1_REMOTE_START_BASE_IDX 0
+#define regTHM_TMON1_REMOTE_END 0x017f
+#define regTHM_TMON1_REMOTE_END_BASE_IDX 0
+#define regTHM_TMON2_REMOTE_START 0x0180
+#define regTHM_TMON2_REMOTE_START_BASE_IDX 0
+#define regTHM_TMON2_REMOTE_END 0x01bf
+#define regTHM_TMON2_REMOTE_END_BASE_IDX 0
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_13_0_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_13_0_2_sh_mask.h
new file mode 100644
index 000000000000..3d81ae154901
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_13_0_2_sh_mask.h
@@ -0,0 +1,1297 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ *
+ */
+#ifndef _thm_13_0_2_SH_MASK_HEADER
+#define _thm_13_0_2_SH_MASK_HEADER
+
+
+// addressBlock: thm_thm_SmuThmDec
+//THM_TCON_CUR_TMP
+#define THM_TCON_CUR_TMP__PER_STEP_TIME_UP__SHIFT 0x0
+#define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT 0x5
+#define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT 0x7
+#define THM_TCON_CUR_TMP__PER_STEP_TIME_DN__SHIFT 0x8
+#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT 0x10
+#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT 0x12
+#define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT 0x13
+#define THM_TCON_CUR_TMP__MCM_EN__SHIFT 0x14
+#define THM_TCON_CUR_TMP__CUR_TEMP__SHIFT 0x15
+#define THM_TCON_CUR_TMP__PER_STEP_TIME_UP_MASK 0x0000001FL
+#define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP_MASK 0x00000060L
+#define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN_MASK 0x00000080L
+#define THM_TCON_CUR_TMP__PER_STEP_TIME_DN_MASK 0x00001F00L
+#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL_MASK 0x00030000L
+#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL_MASK 0x00040000L
+#define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK 0x00080000L
+#define THM_TCON_CUR_TMP__MCM_EN_MASK 0x00100000L
+#define THM_TCON_CUR_TMP__CUR_TEMP_MASK 0xFFE00000L
+//THM_TCON_HTC
+#define THM_TCON_HTC__HTC_EN__SHIFT 0x0
+#define THM_TCON_HTC__EXTERNAL_PROCHOT__SHIFT 0x2
+#define THM_TCON_HTC__INTERNAL_PROCHOT__SHIFT 0x3
+#define THM_TCON_HTC__HTC_ACTIVE__SHIFT 0x4
+#define THM_TCON_HTC__HTC_ACTIVE_LOG__SHIFT 0x5
+#define THM_TCON_HTC__HTC_DIAG__SHIFT 0x8
+#define THM_TCON_HTC__DIS_PROCHOT_PIN_OUT__SHIFT 0x9
+#define THM_TCON_HTC__HTC_TO_IH_EN__SHIFT 0xa
+#define THM_TCON_HTC__PROCHOT_TO_IH_EN__SHIFT 0xb
+#define THM_TCON_HTC__PROCHOT_EVENT_SRC__SHIFT 0xc
+#define THM_TCON_HTC__DIS_PROCHOT_PIN_IN__SHIFT 0xf
+#define THM_TCON_HTC__HTC_TMP_LMT__SHIFT 0x10
+#define THM_TCON_HTC__HTC_HYST_LMT__SHIFT 0x17
+#define THM_TCON_HTC__HTC_SLEW_SEL__SHIFT 0x1b
+#define THM_TCON_HTC__HTC_EN_MASK 0x00000001L
+#define THM_TCON_HTC__EXTERNAL_PROCHOT_MASK 0x00000004L
+#define THM_TCON_HTC__INTERNAL_PROCHOT_MASK 0x00000008L
+#define THM_TCON_HTC__HTC_ACTIVE_MASK 0x00000010L
+#define THM_TCON_HTC__HTC_ACTIVE_LOG_MASK 0x00000020L
+#define THM_TCON_HTC__HTC_DIAG_MASK 0x00000100L
+#define THM_TCON_HTC__DIS_PROCHOT_PIN_OUT_MASK 0x00000200L
+#define THM_TCON_HTC__HTC_TO_IH_EN_MASK 0x00000400L
+#define THM_TCON_HTC__PROCHOT_TO_IH_EN_MASK 0x00000800L
+#define THM_TCON_HTC__PROCHOT_EVENT_SRC_MASK 0x00007000L
+#define THM_TCON_HTC__DIS_PROCHOT_PIN_IN_MASK 0x00008000L
+#define THM_TCON_HTC__HTC_TMP_LMT_MASK 0x007F0000L
+#define THM_TCON_HTC__HTC_HYST_LMT_MASK 0x07800000L
+#define THM_TCON_HTC__HTC_SLEW_SEL_MASK 0x18000000L
+//THM_TCON_THERM_TRIP
+#define THM_TCON_THERM_TRIP__CTF_PAD_POLARITY__SHIFT 0x0
+#define THM_TCON_THERM_TRIP__THERM_TP__SHIFT 0x1
+#define THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED__SHIFT 0x2
+#define THM_TCON_THERM_TRIP__THERM_TP_SENSE__SHIFT 0x3
+#define THM_TCON_THERM_TRIP__RSVD2__SHIFT 0x4
+#define THM_TCON_THERM_TRIP__THERM_TP_EN__SHIFT 0x5
+#define THM_TCON_THERM_TRIP__THERM_TP_LMT__SHIFT 0x6
+#define THM_TCON_THERM_TRIP__RSVD3__SHIFT 0xe
+#define THM_TCON_THERM_TRIP__SW_THERM_TP__SHIFT 0x1f
+#define THM_TCON_THERM_TRIP__CTF_PAD_POLARITY_MASK 0x00000001L
+#define THM_TCON_THERM_TRIP__THERM_TP_MASK 0x00000002L
+#define THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED_MASK 0x00000004L
+#define THM_TCON_THERM_TRIP__THERM_TP_SENSE_MASK 0x00000008L
+#define THM_TCON_THERM_TRIP__RSVD2_MASK 0x00000010L
+#define THM_TCON_THERM_TRIP__THERM_TP_EN_MASK 0x00000020L
+#define THM_TCON_THERM_TRIP__THERM_TP_LMT_MASK 0x00003FC0L
+#define THM_TCON_THERM_TRIP__RSVD3_MASK 0x7FFFC000L
+#define THM_TCON_THERM_TRIP__SW_THERM_TP_MASK 0x80000000L
+//THM_CTF_DELAY
+#define THM_CTF_DELAY__CTF_DELAY_CNT__SHIFT 0x0
+#define THM_CTF_DELAY__CTF_DELAY_CNT_MASK 0x000FFFFFL
+//THM_GPIO_PROCHOT_CTRL
+#define THM_GPIO_PROCHOT_CTRL__TXIMPSEL__SHIFT 0x0
+#define THM_GPIO_PROCHOT_CTRL__PD__SHIFT 0x1
+#define THM_GPIO_PROCHOT_CTRL__PU__SHIFT 0x2
+#define THM_GPIO_PROCHOT_CTRL__SCHMEN__SHIFT 0x3
+#define THM_GPIO_PROCHOT_CTRL__S0__SHIFT 0x4
+#define THM_GPIO_PROCHOT_CTRL__S1__SHIFT 0x5
+#define THM_GPIO_PROCHOT_CTRL__RXEN__SHIFT 0x6
+#define THM_GPIO_PROCHOT_CTRL__RXSEL0__SHIFT 0x7
+#define THM_GPIO_PROCHOT_CTRL__RXSEL1__SHIFT 0x8
+#define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE__SHIFT 0x10
+#define THM_GPIO_PROCHOT_CTRL__OE__SHIFT 0x11
+#define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE__SHIFT 0x12
+#define THM_GPIO_PROCHOT_CTRL__A__SHIFT 0x13
+#define THM_GPIO_PROCHOT_CTRL__Y__SHIFT 0x1f
+#define THM_GPIO_PROCHOT_CTRL__TXIMPSEL_MASK 0x00000001L
+#define THM_GPIO_PROCHOT_CTRL__PD_MASK 0x00000002L
+#define THM_GPIO_PROCHOT_CTRL__PU_MASK 0x00000004L
+#define THM_GPIO_PROCHOT_CTRL__SCHMEN_MASK 0x00000008L
+#define THM_GPIO_PROCHOT_CTRL__S0_MASK 0x00000010L
+#define THM_GPIO_PROCHOT_CTRL__S1_MASK 0x00000020L
+#define THM_GPIO_PROCHOT_CTRL__RXEN_MASK 0x00000040L
+#define THM_GPIO_PROCHOT_CTRL__RXSEL0_MASK 0x00000080L
+#define THM_GPIO_PROCHOT_CTRL__RXSEL1_MASK 0x00000100L
+#define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE_MASK 0x00010000L
+#define THM_GPIO_PROCHOT_CTRL__OE_MASK 0x00020000L
+#define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE_MASK 0x00040000L
+#define THM_GPIO_PROCHOT_CTRL__A_MASK 0x00080000L
+#define THM_GPIO_PROCHOT_CTRL__Y_MASK 0x80000000L
+//THM_GPIO_THERMTRIP_CTRL
+#define THM_GPIO_THERMTRIP_CTRL__TXIMPSEL__SHIFT 0x0
+#define THM_GPIO_THERMTRIP_CTRL__PD__SHIFT 0x1
+#define THM_GPIO_THERMTRIP_CTRL__PU__SHIFT 0x2
+#define THM_GPIO_THERMTRIP_CTRL__SCHMEN__SHIFT 0x3
+#define THM_GPIO_THERMTRIP_CTRL__S0__SHIFT 0x4
+#define THM_GPIO_THERMTRIP_CTRL__S1__SHIFT 0x5
+#define THM_GPIO_THERMTRIP_CTRL__RXEN__SHIFT 0x6
+#define THM_GPIO_THERMTRIP_CTRL__RXSEL0__SHIFT 0x7
+#define THM_GPIO_THERMTRIP_CTRL__RXSEL1__SHIFT 0x8
+#define THM_GPIO_THERMTRIP_CTRL__OE_OVERRIDE__SHIFT 0x10
+#define THM_GPIO_THERMTRIP_CTRL__OE__SHIFT 0x11
+#define THM_GPIO_THERMTRIP_CTRL__A_OVERRIDE__SHIFT 0x12
+#define THM_GPIO_THERMTRIP_CTRL__A__SHIFT 0x13
+#define THM_GPIO_THERMTRIP_CTRL__CTFEN__SHIFT 0x14
+#define THM_GPIO_THERMTRIP_CTRL__Y__SHIFT 0x1f
+#define THM_GPIO_THERMTRIP_CTRL__TXIMPSEL_MASK 0x00000001L
+#define THM_GPIO_THERMTRIP_CTRL__PD_MASK 0x00000002L
+#define THM_GPIO_THERMTRIP_CTRL__PU_MASK 0x00000004L
+#define THM_GPIO_THERMTRIP_CTRL__SCHMEN_MASK 0x00000008L
+#define THM_GPIO_THERMTRIP_CTRL__S0_MASK 0x00000010L
+#define THM_GPIO_THERMTRIP_CTRL__S1_MASK 0x00000020L
+#define THM_GPIO_THERMTRIP_CTRL__RXEN_MASK 0x00000040L
+#define THM_GPIO_THERMTRIP_CTRL__RXSEL0_MASK 0x00000080L
+#define THM_GPIO_THERMTRIP_CTRL__RXSEL1_MASK 0x00000100L
+#define THM_GPIO_THERMTRIP_CTRL__OE_OVERRIDE_MASK 0x00010000L
+#define THM_GPIO_THERMTRIP_CTRL__OE_MASK 0x00020000L
+#define THM_GPIO_THERMTRIP_CTRL__A_OVERRIDE_MASK 0x00040000L
+#define THM_GPIO_THERMTRIP_CTRL__A_MASK 0x00080000L
+#define THM_GPIO_THERMTRIP_CTRL__CTFEN_MASK 0x00100000L
+#define THM_GPIO_THERMTRIP_CTRL__Y_MASK 0x80000000L
+//THM_GPIO_PWM_CTRL
+#define THM_GPIO_PWM_CTRL__TXIMPSEL__SHIFT 0x0
+#define THM_GPIO_PWM_CTRL__PD__SHIFT 0x1
+#define THM_GPIO_PWM_CTRL__PU__SHIFT 0x2
+#define THM_GPIO_PWM_CTRL__SCHMEN__SHIFT 0x3
+#define THM_GPIO_PWM_CTRL__S0__SHIFT 0x4
+#define THM_GPIO_PWM_CTRL__S1__SHIFT 0x5
+#define THM_GPIO_PWM_CTRL__RXEN__SHIFT 0x6
+#define THM_GPIO_PWM_CTRL__RXSEL0__SHIFT 0x7
+#define THM_GPIO_PWM_CTRL__RXSEL1__SHIFT 0x8
+#define THM_GPIO_PWM_CTRL__OE_OVERRIDE__SHIFT 0x10
+#define THM_GPIO_PWM_CTRL__OE__SHIFT 0x11
+#define THM_GPIO_PWM_CTRL__A_OVERRIDE__SHIFT 0x12
+#define THM_GPIO_PWM_CTRL__A__SHIFT 0x13
+#define THM_GPIO_PWM_CTRL__Y__SHIFT 0x1f
+#define THM_GPIO_PWM_CTRL__TXIMPSEL_MASK 0x00000001L
+#define THM_GPIO_PWM_CTRL__PD_MASK 0x00000002L
+#define THM_GPIO_PWM_CTRL__PU_MASK 0x00000004L
+#define THM_GPIO_PWM_CTRL__SCHMEN_MASK 0x00000008L
+#define THM_GPIO_PWM_CTRL__S0_MASK 0x00000010L
+#define THM_GPIO_PWM_CTRL__S1_MASK 0x00000020L
+#define THM_GPIO_PWM_CTRL__RXEN_MASK 0x00000040L
+#define THM_GPIO_PWM_CTRL__RXSEL0_MASK 0x00000080L
+#define THM_GPIO_PWM_CTRL__RXSEL1_MASK 0x00000100L
+#define THM_GPIO_PWM_CTRL__OE_OVERRIDE_MASK 0x00010000L
+#define THM_GPIO_PWM_CTRL__OE_MASK 0x00020000L
+#define THM_GPIO_PWM_CTRL__A_OVERRIDE_MASK 0x00040000L
+#define THM_GPIO_PWM_CTRL__A_MASK 0x00080000L
+#define THM_GPIO_PWM_CTRL__Y_MASK 0x80000000L
+//THM_GPIO_TACHIN_CTRL
+#define THM_GPIO_TACHIN_CTRL__TXIMPSEL__SHIFT 0x0
+#define THM_GPIO_TACHIN_CTRL__PD__SHIFT 0x1
+#define THM_GPIO_TACHIN_CTRL__PU__SHIFT 0x2
+#define THM_GPIO_TACHIN_CTRL__SCHMEN__SHIFT 0x3
+#define THM_GPIO_TACHIN_CTRL__S0__SHIFT 0x4
+#define THM_GPIO_TACHIN_CTRL__S1__SHIFT 0x5
+#define THM_GPIO_TACHIN_CTRL__RXEN__SHIFT 0x6
+#define THM_GPIO_TACHIN_CTRL__RXSEL0__SHIFT 0x7
+#define THM_GPIO_TACHIN_CTRL__RXSEL1__SHIFT 0x8
+#define THM_GPIO_TACHIN_CTRL__OE_OVERRIDE__SHIFT 0x10
+#define THM_GPIO_TACHIN_CTRL__OE__SHIFT 0x11
+#define THM_GPIO_TACHIN_CTRL__A_OVERRIDE__SHIFT 0x12
+#define THM_GPIO_TACHIN_CTRL__A__SHIFT 0x13
+#define THM_GPIO_TACHIN_CTRL__Y__SHIFT 0x1f
+#define THM_GPIO_TACHIN_CTRL__TXIMPSEL_MASK 0x00000001L
+#define THM_GPIO_TACHIN_CTRL__PD_MASK 0x00000002L
+#define THM_GPIO_TACHIN_CTRL__PU_MASK 0x00000004L
+#define THM_GPIO_TACHIN_CTRL__SCHMEN_MASK 0x00000008L
+#define THM_GPIO_TACHIN_CTRL__S0_MASK 0x00000010L
+#define THM_GPIO_TACHIN_CTRL__S1_MASK 0x00000020L
+#define THM_GPIO_TACHIN_CTRL__RXEN_MASK 0x00000040L
+#define THM_GPIO_TACHIN_CTRL__RXSEL0_MASK 0x00000080L
+#define THM_GPIO_TACHIN_CTRL__RXSEL1_MASK 0x00000100L
+#define THM_GPIO_TACHIN_CTRL__OE_OVERRIDE_MASK 0x00010000L
+#define THM_GPIO_TACHIN_CTRL__OE_MASK 0x00020000L
+#define THM_GPIO_TACHIN_CTRL__A_OVERRIDE_MASK 0x00040000L
+#define THM_GPIO_TACHIN_CTRL__A_MASK 0x00080000L
+#define THM_GPIO_TACHIN_CTRL__Y_MASK 0x80000000L
+//THM_GPIO_PUMPOUT_CTRL
+#define THM_GPIO_PUMPOUT_CTRL__TXIMPSEL__SHIFT 0x0
+#define THM_GPIO_PUMPOUT_CTRL__PD__SHIFT 0x1
+#define THM_GPIO_PUMPOUT_CTRL__PU__SHIFT 0x2
+#define THM_GPIO_PUMPOUT_CTRL__SCHMEN__SHIFT 0x3
+#define THM_GPIO_PUMPOUT_CTRL__S0__SHIFT 0x4
+#define THM_GPIO_PUMPOUT_CTRL__S1__SHIFT 0x5
+#define THM_GPIO_PUMPOUT_CTRL__RXEN__SHIFT 0x6
+#define THM_GPIO_PUMPOUT_CTRL__RXSEL0__SHIFT 0x7
+#define THM_GPIO_PUMPOUT_CTRL__RXSEL1__SHIFT 0x8
+#define THM_GPIO_PUMPOUT_CTRL__OE_OVERRIDE__SHIFT 0x10
+#define THM_GPIO_PUMPOUT_CTRL__OE__SHIFT 0x11
+#define THM_GPIO_PUMPOUT_CTRL__A_OVERRIDE__SHIFT 0x12
+#define THM_GPIO_PUMPOUT_CTRL__A__SHIFT 0x13
+#define THM_GPIO_PUMPOUT_CTRL__Y__SHIFT 0x1f
+#define THM_GPIO_PUMPOUT_CTRL__TXIMPSEL_MASK 0x00000001L
+#define THM_GPIO_PUMPOUT_CTRL__PD_MASK 0x00000002L
+#define THM_GPIO_PUMPOUT_CTRL__PU_MASK 0x00000004L
+#define THM_GPIO_PUMPOUT_CTRL__SCHMEN_MASK 0x00000008L
+#define THM_GPIO_PUMPOUT_CTRL__S0_MASK 0x00000010L
+#define THM_GPIO_PUMPOUT_CTRL__S1_MASK 0x00000020L
+#define THM_GPIO_PUMPOUT_CTRL__RXEN_MASK 0x00000040L
+#define THM_GPIO_PUMPOUT_CTRL__RXSEL0_MASK 0x00000080L
+#define THM_GPIO_PUMPOUT_CTRL__RXSEL1_MASK 0x00000100L
+#define THM_GPIO_PUMPOUT_CTRL__OE_OVERRIDE_MASK 0x00010000L
+#define THM_GPIO_PUMPOUT_CTRL__OE_MASK 0x00020000L
+#define THM_GPIO_PUMPOUT_CTRL__A_OVERRIDE_MASK 0x00040000L
+#define THM_GPIO_PUMPOUT_CTRL__A_MASK 0x00080000L
+#define THM_GPIO_PUMPOUT_CTRL__Y_MASK 0x80000000L
+//THM_GPIO_PUMPIN_CTRL
+#define THM_GPIO_PUMPIN_CTRL__TXIMPSEL__SHIFT 0x0
+#define THM_GPIO_PUMPIN_CTRL__PD__SHIFT 0x1
+#define THM_GPIO_PUMPIN_CTRL__PU__SHIFT 0x2
+#define THM_GPIO_PUMPIN_CTRL__SCHMEN__SHIFT 0x3
+#define THM_GPIO_PUMPIN_CTRL__S0__SHIFT 0x4
+#define THM_GPIO_PUMPIN_CTRL__S1__SHIFT 0x5
+#define THM_GPIO_PUMPIN_CTRL__RXEN__SHIFT 0x6
+#define THM_GPIO_PUMPIN_CTRL__RXSEL0__SHIFT 0x7
+#define THM_GPIO_PUMPIN_CTRL__RXSEL1__SHIFT 0x8
+#define THM_GPIO_PUMPIN_CTRL__OE_OVERRIDE__SHIFT 0x10
+#define THM_GPIO_PUMPIN_CTRL__OE__SHIFT 0x11
+#define THM_GPIO_PUMPIN_CTRL__A_OVERRIDE__SHIFT 0x12
+#define THM_GPIO_PUMPIN_CTRL__A__SHIFT 0x13
+#define THM_GPIO_PUMPIN_CTRL__Y__SHIFT 0x1f
+#define THM_GPIO_PUMPIN_CTRL__TXIMPSEL_MASK 0x00000001L
+#define THM_GPIO_PUMPIN_CTRL__PD_MASK 0x00000002L
+#define THM_GPIO_PUMPIN_CTRL__PU_MASK 0x00000004L
+#define THM_GPIO_PUMPIN_CTRL__SCHMEN_MASK 0x00000008L
+#define THM_GPIO_PUMPIN_CTRL__S0_MASK 0x00000010L
+#define THM_GPIO_PUMPIN_CTRL__S1_MASK 0x00000020L
+#define THM_GPIO_PUMPIN_CTRL__RXEN_MASK 0x00000040L
+#define THM_GPIO_PUMPIN_CTRL__RXSEL0_MASK 0x00000080L
+#define THM_GPIO_PUMPIN_CTRL__RXSEL1_MASK 0x00000100L
+#define THM_GPIO_PUMPIN_CTRL__OE_OVERRIDE_MASK 0x00010000L
+#define THM_GPIO_PUMPIN_CTRL__OE_MASK 0x00020000L
+#define THM_GPIO_PUMPIN_CTRL__A_OVERRIDE_MASK 0x00040000L
+#define THM_GPIO_PUMPIN_CTRL__A_MASK 0x00080000L
+#define THM_GPIO_PUMPIN_CTRL__Y_MASK 0x80000000L
+//THM_THERMAL_INT_ENA
+#define THM_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0
+#define THM_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1
+#define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2
+#define THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3
+#define THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4
+#define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5
+#define THM_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x00000001L
+#define THM_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x00000002L
+#define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x00000004L
+#define THM_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x00000008L
+#define THM_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x00000010L
+#define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x00000020L
+//THM_THERMAL_INT_CTRL
+#define THM_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0
+#define THM_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8
+#define THM_THERMAL_INT_CTRL__TEMP_THRESHOLD__SHIFT 0x10
+#define THM_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18
+#define THM_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19
+#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a
+#define THM_THERMAL_INT_CTRL__THERM_PROCHOT_MASK__SHIFT 0x1b
+#define THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA__SHIFT 0x1c
+#define THM_THERMAL_INT_CTRL__MAX_IH_CREDIT__SHIFT 0x1d
+#define THM_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0x000000FFL
+#define THM_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0x0000FF00L
+#define THM_THERMAL_INT_CTRL__TEMP_THRESHOLD_MASK 0x00FF0000L
+#define THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x01000000L
+#define THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x02000000L
+#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x04000000L
+#define THM_THERMAL_INT_CTRL__THERM_PROCHOT_MASK_MASK 0x08000000L
+#define THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA_MASK 0x10000000L
+#define THM_THERMAL_INT_CTRL__MAX_IH_CREDIT_MASK 0xE0000000L
+//THM_THERMAL_INT_STATUS
+#define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0
+#define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1
+#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2
+#define THM_THERMAL_INT_STATUS__THERM_PROCHOT_DETECT__SHIFT 0x3
+#define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x00000001L
+#define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x00000002L
+#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x00000004L
+#define THM_THERMAL_INT_STATUS__THERM_PROCHOT_DETECT_MASK 0x00000008L
+//THM_TMON0_RDIL0_DATA
+#define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL0_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIL0_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIL0_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIL1_DATA
+#define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL1_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIL1_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIL1_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIL2_DATA
+#define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL2_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIL2_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIL2_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIL3_DATA
+#define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL3_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIL3_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIL3_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIL4_DATA
+#define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL4_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIL4_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIL4_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIL5_DATA
+#define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL5_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIL5_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIL5_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIL6_DATA
+#define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL6_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIL6_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIL6_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIL7_DATA
+#define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL7_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIL7_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIL7_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIL8_DATA
+#define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL8_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIL8_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIL8_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIL9_DATA
+#define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL9_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIL9_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIL9_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIL10_DATA
+#define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL10_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIL10_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIL10_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIL11_DATA
+#define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL11_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIL11_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIL11_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIL12_DATA
+#define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL12_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIL12_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIL12_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIL13_DATA
+#define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL13_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIL13_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIL13_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIL14_DATA
+#define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL14_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIL14_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIL14_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIL15_DATA
+#define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL15_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIL15_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIL15_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIR0_DATA
+#define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR0_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIR0_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIR0_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIR1_DATA
+#define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR1_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIR1_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIR1_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIR2_DATA
+#define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR2_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIR2_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIR2_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIR3_DATA
+#define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR3_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIR3_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIR3_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIR4_DATA
+#define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR4_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIR4_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIR4_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIR5_DATA
+#define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR5_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIR5_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIR5_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIR6_DATA
+#define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR6_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIR6_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIR6_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIR7_DATA
+#define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR7_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIR7_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIR7_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIR8_DATA
+#define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR8_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIR8_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIR8_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIR9_DATA
+#define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR9_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIR9_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIR9_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIR10_DATA
+#define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR10_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIR10_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIR10_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIR11_DATA
+#define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR11_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIR11_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIR11_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIR12_DATA
+#define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR12_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIR12_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIR12_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIR13_DATA
+#define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR13_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIR13_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIR13_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIR14_DATA
+#define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR14_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIR14_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIR14_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_RDIR15_DATA
+#define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR15_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_RDIR15_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_RDIR15_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_INT_DATA
+#define THM_TMON0_INT_DATA__Z__SHIFT 0x0
+#define THM_TMON0_INT_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_INT_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_INT_DATA__Z_MASK 0x000007FFL
+#define THM_TMON0_INT_DATA__VALID_MASK 0x00000800L
+#define THM_TMON0_INT_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON0_CTRL
+#define THM_TMON0_CTRL__POWER_DOWN__SHIFT 0x0
+#define THM_TMON0_CTRL__BGADJ__SHIFT 0x1
+#define THM_TMON0_CTRL__BGADJ_MODE__SHIFT 0x9
+#define THM_TMON0_CTRL__TMON_PAUSE__SHIFT 0xa
+#define THM_TMON0_CTRL__INT_MEAS_EN__SHIFT 0xb
+#define THM_TMON0_CTRL__EN_CFG_SERDES__SHIFT 0xd
+#define THM_TMON0_CTRL__POWER_DOWN_MASK 0x00000001L
+#define THM_TMON0_CTRL__BGADJ_MASK 0x000001FEL
+#define THM_TMON0_CTRL__BGADJ_MODE_MASK 0x00000200L
+#define THM_TMON0_CTRL__TMON_PAUSE_MASK 0x00000400L
+#define THM_TMON0_CTRL__INT_MEAS_EN_MASK 0x00000800L
+#define THM_TMON0_CTRL__EN_CFG_SERDES_MASK 0x00002000L
+//THM_TMON0_CTRL2
+#define THM_TMON0_CTRL2__RDIL_PRESENT__SHIFT 0x0
+#define THM_TMON0_CTRL2__RDIR_PRESENT__SHIFT 0x10
+#define THM_TMON0_CTRL2__RDIL_PRESENT_MASK 0x0000FFFFL
+#define THM_TMON0_CTRL2__RDIR_PRESENT_MASK 0xFFFF0000L
+//THM_TMON1_RDIL0_DATA
+#define THM_TMON1_RDIL0_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL0_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL0_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL0_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIL0_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIL0_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIL1_DATA
+#define THM_TMON1_RDIL1_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL1_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL1_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL1_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIL1_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIL1_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIL2_DATA
+#define THM_TMON1_RDIL2_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL2_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL2_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL2_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIL2_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIL2_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIL3_DATA
+#define THM_TMON1_RDIL3_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL3_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL3_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL3_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIL3_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIL3_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIL4_DATA
+#define THM_TMON1_RDIL4_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL4_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL4_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL4_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIL4_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIL4_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIL5_DATA
+#define THM_TMON1_RDIL5_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL5_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL5_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL5_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIL5_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIL5_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIL6_DATA
+#define THM_TMON1_RDIL6_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL6_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL6_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL6_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIL6_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIL6_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIL7_DATA
+#define THM_TMON1_RDIL7_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL7_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL7_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL7_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIL7_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIL7_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIL8_DATA
+#define THM_TMON1_RDIL8_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL8_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL8_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL8_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIL8_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIL8_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIL9_DATA
+#define THM_TMON1_RDIL9_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL9_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL9_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL9_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIL9_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIL9_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIL10_DATA
+#define THM_TMON1_RDIL10_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL10_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL10_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL10_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIL10_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIL10_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIL11_DATA
+#define THM_TMON1_RDIL11_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL11_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL11_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL11_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIL11_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIL11_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIL12_DATA
+#define THM_TMON1_RDIL12_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL12_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL12_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL12_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIL12_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIL12_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIL13_DATA
+#define THM_TMON1_RDIL13_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL13_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL13_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL13_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIL13_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIL13_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIL14_DATA
+#define THM_TMON1_RDIL14_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL14_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL14_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL14_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIL14_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIL14_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIL15_DATA
+#define THM_TMON1_RDIL15_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL15_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL15_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL15_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIL15_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIL15_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIR0_DATA
+#define THM_TMON1_RDIR0_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR0_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR0_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR0_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIR0_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIR0_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIR1_DATA
+#define THM_TMON1_RDIR1_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR1_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR1_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR1_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIR1_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIR1_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIR2_DATA
+#define THM_TMON1_RDIR2_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR2_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR2_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR2_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIR2_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIR2_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIR3_DATA
+#define THM_TMON1_RDIR3_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR3_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR3_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR3_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIR3_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIR3_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIR4_DATA
+#define THM_TMON1_RDIR4_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR4_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR4_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR4_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIR4_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIR4_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIR5_DATA
+#define THM_TMON1_RDIR5_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR5_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR5_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR5_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIR5_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIR5_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIR6_DATA
+#define THM_TMON1_RDIR6_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR6_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR6_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR6_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIR6_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIR6_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIR7_DATA
+#define THM_TMON1_RDIR7_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR7_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR7_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR7_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIR7_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIR7_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIR8_DATA
+#define THM_TMON1_RDIR8_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR8_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR8_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR8_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIR8_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIR8_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIR9_DATA
+#define THM_TMON1_RDIR9_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR9_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR9_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR9_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIR9_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIR9_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIR10_DATA
+#define THM_TMON1_RDIR10_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR10_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR10_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR10_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIR10_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIR10_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIR11_DATA
+#define THM_TMON1_RDIR11_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR11_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR11_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR11_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIR11_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIR11_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIR12_DATA
+#define THM_TMON1_RDIR12_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR12_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR12_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR12_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIR12_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIR12_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIR13_DATA
+#define THM_TMON1_RDIR13_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR13_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR13_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR13_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIR13_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIR13_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIR14_DATA
+#define THM_TMON1_RDIR14_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR14_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR14_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR14_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIR14_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIR14_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_RDIR15_DATA
+#define THM_TMON1_RDIR15_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR15_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR15_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR15_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_RDIR15_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_RDIR15_DATA__TEMP_MASK 0x00FFF000L
+//THM_TMON1_INT_DATA
+#define THM_TMON1_INT_DATA__Z__SHIFT 0x0
+#define THM_TMON1_INT_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_INT_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_INT_DATA__Z_MASK 0x000007FFL
+#define THM_TMON1_INT_DATA__VALID_MASK 0x00000800L
+#define THM_TMON1_INT_DATA__TEMP_MASK 0x00FFF000L
+//THM_DIE1_TEMP
+#define THM_DIE1_TEMP__TEMP__SHIFT 0x0
+#define THM_DIE1_TEMP__VALID__SHIFT 0xb
+#define THM_DIE1_TEMP__TEMP_MASK 0x000007FFL
+#define THM_DIE1_TEMP__VALID_MASK 0x00000800L
+//THM_DIE2_TEMP
+#define THM_DIE2_TEMP__TEMP__SHIFT 0x0
+#define THM_DIE2_TEMP__VALID__SHIFT 0xb
+#define THM_DIE2_TEMP__TEMP_MASK 0x000007FFL
+#define THM_DIE2_TEMP__VALID_MASK 0x00000800L
+//THM_DIE3_TEMP
+#define THM_DIE3_TEMP__TEMP__SHIFT 0x0
+#define THM_DIE3_TEMP__VALID__SHIFT 0xb
+#define THM_DIE3_TEMP__TEMP_MASK 0x000007FFL
+#define THM_DIE3_TEMP__VALID_MASK 0x00000800L
+//THM_SW_TEMP
+#define THM_SW_TEMP__SW_TEMP__SHIFT 0x0
+#define THM_SW_TEMP__SW_TEMP_MASK 0x000001FFL
+//CG_MULT_THERMAL_CTRL
+#define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT 0x0
+#define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT 0x4
+#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT 0x9
+#define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x14
+#define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK 0x0000000FL
+#define CG_MULT_THERMAL_CTRL__UNUSED_MASK 0x000001F0L
+#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK 0x00000200L
+#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0x0FF00000L
+//CG_MULT_THERMAL_STATUS
+#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0
+#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9
+#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x000001FFL
+#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x0003FE00L
+//CG_THERMAL_RANGE
+#define CG_THERMAL_RANGE__ASIC_T_MAX__SHIFT 0x0
+#define CG_THERMAL_RANGE__ASIC_T_MIN__SHIFT 0x10
+#define CG_THERMAL_RANGE__ASIC_T_MAX_MASK 0x000001FFL
+#define CG_THERMAL_RANGE__ASIC_T_MIN_MASK 0x01FF0000L
+//THM_TMON_CONFIG
+#define THM_TMON_CONFIG__NUM_ACQ__SHIFT 0x0
+#define THM_TMON_CONFIG__FORCE_MAX_ACQ__SHIFT 0x3
+#define THM_TMON_CONFIG__TSEN_TMON_MODE__SHIFT 0x4
+#define THM_TMON_CONFIG__CONFIG_SOURCE__SHIFT 0x5
+#define THM_TMON_CONFIG__RE_CALIB_EN__SHIFT 0x6
+#define THM_TMON_CONFIG__Z__SHIFT 0x15
+#define THM_TMON_CONFIG__NUM_ACQ_MASK 0x00000007L
+#define THM_TMON_CONFIG__FORCE_MAX_ACQ_MASK 0x00000008L
+#define THM_TMON_CONFIG__TSEN_TMON_MODE_MASK 0x00000010L
+#define THM_TMON_CONFIG__CONFIG_SOURCE_MASK 0x00000020L
+#define THM_TMON_CONFIG__RE_CALIB_EN_MASK 0x00000040L
+#define THM_TMON_CONFIG__Z_MASK 0xFFE00000L
+//THM_TMON_CONFIG2
+#define THM_TMON_CONFIG2__A__SHIFT 0x0
+#define THM_TMON_CONFIG2__B__SHIFT 0xc
+#define THM_TMON_CONFIG2__C__SHIFT 0x12
+#define THM_TMON_CONFIG2__K__SHIFT 0x1d
+#define THM_TMON_CONFIG2__A_MASK 0x00000FFFL
+#define THM_TMON_CONFIG2__B_MASK 0x0003F000L
+#define THM_TMON_CONFIG2__C_MASK 0x1FFC0000L
+#define THM_TMON_CONFIG2__K_MASK 0x20000000L
+//THM_TMON0_COEFF
+#define THM_TMON0_COEFF__C_OFFSET__SHIFT 0x0
+#define THM_TMON0_COEFF__D__SHIFT 0xb
+#define THM_TMON0_COEFF__C_OFFSET_MASK 0x000007FFL
+#define THM_TMON0_COEFF__D_MASK 0x0003F800L
+//THM_TMON1_COEFF
+#define THM_TMON1_COEFF__C_OFFSET__SHIFT 0x0
+#define THM_TMON1_COEFF__D__SHIFT 0xb
+#define THM_TMON1_COEFF__C_OFFSET_MASK 0x000007FFL
+#define THM_TMON1_COEFF__D_MASK 0x0003F800L
+//CG_FDO_CTRL0
+#define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT 0x0
+#define CG_FDO_CTRL0__FAN_SPINUP_DUTY__SHIFT 0x8
+#define CG_FDO_CTRL0__FDO_PWM_MANUAL__SHIFT 0x10
+#define CG_FDO_CTRL0__FDO_PWM_HYSTER__SHIFT 0x11
+#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN__SHIFT 0x17
+#define CG_FDO_CTRL0__FDO_PWM_RAMP__SHIFT 0x18
+#define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 0x000000FFL
+#define CG_FDO_CTRL0__FAN_SPINUP_DUTY_MASK 0x0000FF00L
+#define CG_FDO_CTRL0__FDO_PWM_MANUAL_MASK 0x00010000L
+#define CG_FDO_CTRL0__FDO_PWM_HYSTER_MASK 0x007E0000L
+#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN_MASK 0x00800000L
+#define CG_FDO_CTRL0__FDO_PWM_RAMP_MASK 0xFF000000L
+//CG_FDO_CTRL1
+#define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT 0x0
+#define CG_FDO_CTRL1__FMIN_DUTY__SHIFT 0x8
+#define CG_FDO_CTRL1__M__SHIFT 0x10
+#define CG_FDO_CTRL1__TACH_IN_MAX__SHIFT 0x18
+#define CG_FDO_CTRL1__FMAX_DUTY100_MASK 0x000000FFL
+#define CG_FDO_CTRL1__FMIN_DUTY_MASK 0x0000FF00L
+#define CG_FDO_CTRL1__M_MASK 0x00FF0000L
+#define CG_FDO_CTRL1__TACH_IN_MAX_MASK 0xFF000000L
+//CG_FDO_CTRL2
+#define CG_FDO_CTRL2__TMIN__SHIFT 0x0
+#define CG_FDO_CTRL2__FAN_SPINUP_TIME__SHIFT 0x8
+#define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT 0xb
+#define CG_FDO_CTRL2__TMIN_HYSTER__SHIFT 0xe
+#define CG_FDO_CTRL2__TMAX__SHIFT 0x11
+#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19
+#define CG_FDO_CTRL2__TMIN_MASK 0x000000FFL
+#define CG_FDO_CTRL2__FAN_SPINUP_TIME_MASK 0x00000700L
+#define CG_FDO_CTRL2__FDO_PWM_MODE_MASK 0x00003800L
+#define CG_FDO_CTRL2__TMIN_HYSTER_MASK 0x0001C000L
+#define CG_FDO_CTRL2__TMAX_MASK 0x01FE0000L
+#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK 0xFE000000L
+//CG_TACH_CTRL
+#define CG_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0
+#define CG_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3
+#define CG_TACH_CTRL__EDGE_PER_REV_MASK 0x00000007L
+#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xFFFFFFF8L
+//CG_TACH_STATUS
+#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0
+#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xFFFFFFFFL
+//CG_THERMAL_STATUS
+#define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x9
+#define CG_THERMAL_STATUS__TACH_IN_H_DEGLITCH_CNT__SHIFT 0x11
+#define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x0001FE00L
+#define CG_THERMAL_STATUS__TACH_IN_H_DEGLITCH_CNT_MASK 0xFFFE0000L
+//CG_PUMP_CTRL0
+#define CG_PUMP_CTRL0__PUMP_STATIC_DUTY__SHIFT 0x0
+#define CG_PUMP_CTRL0__PUMP_SPINUP_DUTY__SHIFT 0x8
+#define CG_PUMP_CTRL0__PUMP_PWM_MANUAL__SHIFT 0x10
+#define CG_PUMP_CTRL0__PUMP_PWM_HYSTER__SHIFT 0x11
+#define CG_PUMP_CTRL0__PUMP_PWM_RAMP_EN__SHIFT 0x17
+#define CG_PUMP_CTRL0__PUMP_PWM_RAMP__SHIFT 0x18
+#define CG_PUMP_CTRL0__PUMP_STATIC_DUTY_MASK 0x000000FFL
+#define CG_PUMP_CTRL0__PUMP_SPINUP_DUTY_MASK 0x0000FF00L
+#define CG_PUMP_CTRL0__PUMP_PWM_MANUAL_MASK 0x00010000L
+#define CG_PUMP_CTRL0__PUMP_PWM_HYSTER_MASK 0x007E0000L
+#define CG_PUMP_CTRL0__PUMP_PWM_RAMP_EN_MASK 0x00800000L
+#define CG_PUMP_CTRL0__PUMP_PWM_RAMP_MASK 0xFF000000L
+//CG_PUMP_CTRL1
+#define CG_PUMP_CTRL1__PMAX_DUTY100__SHIFT 0x0
+#define CG_PUMP_CTRL1__PMIN_DUTY__SHIFT 0x8
+#define CG_PUMP_CTRL1__M__SHIFT 0x10
+#define CG_PUMP_CTRL1__TACH_IN_MAX__SHIFT 0x18
+#define CG_PUMP_CTRL1__PMAX_DUTY100_MASK 0x000000FFL
+#define CG_PUMP_CTRL1__PMIN_DUTY_MASK 0x0000FF00L
+#define CG_PUMP_CTRL1__M_MASK 0x00FF0000L
+#define CG_PUMP_CTRL1__TACH_IN_MAX_MASK 0xFF000000L
+//CG_PUMP_CTRL2
+#define CG_PUMP_CTRL2__TMIN__SHIFT 0x0
+#define CG_PUMP_CTRL2__PUMP_SPINUP_TIME__SHIFT 0x8
+#define CG_PUMP_CTRL2__PUMP_PWM_MODE__SHIFT 0xb
+#define CG_PUMP_CTRL2__TMIN_HYSTER__SHIFT 0xe
+#define CG_PUMP_CTRL2__TMAX__SHIFT 0x11
+#define CG_PUMP_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19
+#define CG_PUMP_CTRL2__TMIN_MASK 0x000000FFL
+#define CG_PUMP_CTRL2__PUMP_SPINUP_TIME_MASK 0x00000700L
+#define CG_PUMP_CTRL2__PUMP_PWM_MODE_MASK 0x00003800L
+#define CG_PUMP_CTRL2__TMIN_HYSTER_MASK 0x0001C000L
+#define CG_PUMP_CTRL2__TMAX_MASK 0x01FE0000L
+#define CG_PUMP_CTRL2__TACH_PWM_RESP_RATE_MASK 0xFE000000L
+//CG_PUMP_TACH_CTRL
+#define CG_PUMP_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0
+#define CG_PUMP_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3
+#define CG_PUMP_TACH_CTRL__EDGE_PER_REV_MASK 0x00000007L
+#define CG_PUMP_TACH_CTRL__TARGET_PERIOD_MASK 0xFFFFFFF8L
+//CG_PUMP_TACH_STATUS
+#define CG_PUMP_TACH_STATUS__TACH_PERIOD__SHIFT 0x0
+#define CG_PUMP_TACH_STATUS__TACH_PERIOD_MASK 0xFFFFFFFFL
+//CG_PUMP_STATUS
+#define CG_PUMP_STATUS__PUMP_PWM_DUTY__SHIFT 0x9
+#define CG_PUMP_STATUS__PUMP_IN_H_DEGLITCH_CNT__SHIFT 0x11
+#define CG_PUMP_STATUS__PUMP_PWM_DUTY_MASK 0x0001FE00L
+#define CG_PUMP_STATUS__PUMP_IN_H_DEGLITCH_CNT_MASK 0xFFFE0000L
+//THM_TCON_LOCAL0
+#define THM_TCON_LOCAL0__TMON0_PwrDn_Dis__SHIFT 0x1
+#define THM_TCON_LOCAL0__TMON1_PwrDn_Dis__SHIFT 0x2
+#define THM_TCON_LOCAL0__TMON2_PwrDn_Dis__SHIFT 0x3
+#define THM_TCON_LOCAL0__TMON0_PwrDn_Dis_MASK 0x00000002L
+#define THM_TCON_LOCAL0__TMON1_PwrDn_Dis_MASK 0x00000004L
+#define THM_TCON_LOCAL0__TMON2_PwrDn_Dis_MASK 0x00000008L
+//THM_TCON_LOCAL1
+#define THM_TCON_LOCAL1__Turn_Off_TMON0__SHIFT 0x0
+#define THM_TCON_LOCAL1__Turn_Off_TMON1__SHIFT 0x1
+#define THM_TCON_LOCAL1__Turn_Off_TMON2__SHIFT 0x2
+#define THM_TCON_LOCAL1__PowerDownTmon0__SHIFT 0x4
+#define THM_TCON_LOCAL1__PowerDownTmon1__SHIFT 0x5
+#define THM_TCON_LOCAL1__PowerDownTmon2__SHIFT 0x6
+#define THM_TCON_LOCAL1__Turn_Off_TMON0_MASK 0x00000001L
+#define THM_TCON_LOCAL1__Turn_Off_TMON1_MASK 0x00000002L
+#define THM_TCON_LOCAL1__Turn_Off_TMON2_MASK 0x00000004L
+#define THM_TCON_LOCAL1__PowerDownTmon0_MASK 0x00000010L
+#define THM_TCON_LOCAL1__PowerDownTmon1_MASK 0x00000020L
+#define THM_TCON_LOCAL1__PowerDownTmon2_MASK 0x00000040L
+//THM_TCON_LOCAL2
+#define THM_TCON_LOCAL2__TMON_init_delay__SHIFT 0x0
+#define THM_TCON_LOCAL2__TMON_pwrup_stagger_time__SHIFT 0x2
+#define THM_TCON_LOCAL2__short_stagger_count__SHIFT 0x5
+#define THM_TCON_LOCAL2__sbtsi_use_corrected__SHIFT 0x6
+#define THM_TCON_LOCAL2__temp_read_skip_scale__SHIFT 0xa
+#define THM_TCON_LOCAL2__skip_scale_correction__SHIFT 0xb
+#define THM_TCON_LOCAL2__TMON_init_delay_MASK 0x00000003L
+#define THM_TCON_LOCAL2__TMON_pwrup_stagger_time_MASK 0x0000000CL
+#define THM_TCON_LOCAL2__short_stagger_count_MASK 0x00000020L
+#define THM_TCON_LOCAL2__sbtsi_use_corrected_MASK 0x00000040L
+#define THM_TCON_LOCAL2__temp_read_skip_scale_MASK 0x00000400L
+#define THM_TCON_LOCAL2__skip_scale_correction_MASK 0x00000800L
+//THM_TCON_LOCAL3
+#define THM_TCON_LOCAL3__Global_TMAX__SHIFT 0x0
+#define THM_TCON_LOCAL3__Global_TMAX_MASK 0x000007FFL
+//THM_TCON_LOCAL4
+#define THM_TCON_LOCAL4__Global_TMAX_ID__SHIFT 0x0
+#define THM_TCON_LOCAL4__Global_TMAX_ID_MASK 0x000000FFL
+//THM_TCON_LOCAL5
+#define THM_TCON_LOCAL5__Global_TMIN__SHIFT 0x0
+#define THM_TCON_LOCAL5__Global_TMIN_MASK 0x000007FFL
+//THM_TCON_LOCAL6
+#define THM_TCON_LOCAL6__Global_TMIN_ID__SHIFT 0x0
+#define THM_TCON_LOCAL6__Global_TMIN_ID_MASK 0x000000FFL
+//THM_TCON_LOCAL7
+#define THM_TCON_LOCAL7__THERMID__SHIFT 0x0
+#define THM_TCON_LOCAL7__THERMID_MASK 0x000000FFL
+//THM_TCON_LOCAL8
+#define THM_TCON_LOCAL8__THERMMAX__SHIFT 0x0
+#define THM_TCON_LOCAL8__THERMMAX_MASK 0x000007FFL
+//THM_TCON_LOCAL9
+#define THM_TCON_LOCAL9__Tj_Max_TMON0__SHIFT 0x0
+#define THM_TCON_LOCAL9__Tj_Max_TMON0_MASK 0x000007FFL
+//THM_TCON_LOCAL10
+#define THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID__SHIFT 0x0
+#define THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID_MASK 0x000000FFL
+//THM_TCON_LOCAL11
+#define THM_TCON_LOCAL11__Tj_Max_TMON1__SHIFT 0x0
+#define THM_TCON_LOCAL11__Tj_Max_TMON1_MASK 0x000007FFL
+//THM_TCON_LOCAL12
+#define THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID__SHIFT 0x0
+#define THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID_MASK 0x000000FFL
+//THM_TCON_LOCAL14
+#define THM_TCON_LOCAL14__Tj_Max_TMON2__SHIFT 0x0
+#define THM_TCON_LOCAL14__Tj_Max_TMON2_MASK 0x000007FFL
+//THM_TCON_LOCAL15
+#define THM_TCON_LOCAL15__TMON2_Tj_Max_RS_ID__SHIFT 0x0
+#define THM_TCON_LOCAL15__TMON2_Tj_Max_RS_ID_MASK 0x000000FFL
+//THM_TCON_LOCAL13
+#define THM_TCON_LOCAL13__boot_done__SHIFT 0x0
+#define THM_TCON_LOCAL13__boot_done_MASK 0x00000001L
+//XTAL_CNTL
+#define XTAL_CNTL__PCIE_REFCLK_SWITCH__SHIFT 0x0
+#define XTAL_CNTL__CORE_XTAL_CLKGEN_CLKEN__SHIFT 0x4
+#define XTAL_CNTL__CORE_XTAL_PWDN__SHIFT 0x8
+#define XTAL_CNTL__OSC_GAIN_EN__SHIFT 0xc
+#define XTAL_CNTL__PCIE_REFCLK_SWITCH_MASK 0x00000001L
+#define XTAL_CNTL__CORE_XTAL_CLKGEN_CLKEN_MASK 0x00000010L
+#define XTAL_CNTL__CORE_XTAL_PWDN_MASK 0x00000100L
+#define XTAL_CNTL__OSC_GAIN_EN_MASK 0x00007000L
+//THM_PWRMGT
+#define THM_PWRMGT__CLK_GATE_EN__SHIFT 0x0
+#define THM_PWRMGT__CLK_GATE_ST__SHIFT 0x1
+#define THM_PWRMGT__PUMP_CTL_GATE_EN__SHIFT 0x6
+#define THM_PWRMGT__FAN_CTL_GATE_EN__SHIFT 0x7
+#define THM_PWRMGT__CLK_GATE_MAX_CNT__SHIFT 0x8
+#define THM_PWRMGT__PROTOTYPE_TSEN_CLK_TOGGLE_EN__SHIFT 0x18
+#define THM_PWRMGT__CLK_GATE_EN_MASK 0x00000001L
+#define THM_PWRMGT__CLK_GATE_ST_MASK 0x00000002L
+#define THM_PWRMGT__PUMP_CTL_GATE_EN_MASK 0x00000040L
+#define THM_PWRMGT__FAN_CTL_GATE_EN_MASK 0x00000080L
+#define THM_PWRMGT__CLK_GATE_MAX_CNT_MASK 0x00FFFF00L
+#define THM_PWRMGT__PROTOTYPE_TSEN_CLK_TOGGLE_EN_MASK 0x01000000L
+//THM_GPIO_MACO_EN_CTRL
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_TXIMPSEL__SHIFT 0x0
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_PD__SHIFT 0x1
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_PU__SHIFT 0x2
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_SCHMEN__SHIFT 0x3
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_S0__SHIFT 0x4
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_S1__SHIFT 0x5
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXEN__SHIFT 0x6
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL0__SHIFT 0x7
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL1__SHIFT 0x8
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_OE_OVERRIDE__SHIFT 0x10
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_OE__SHIFT 0x11
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_A_OVERRIDE__SHIFT 0x12
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_A__SHIFT 0x13
+#define THM_GPIO_MACO_EN_CTRL__Y__SHIFT 0x1f
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_TXIMPSEL_MASK 0x00000001L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_PD_MASK 0x00000002L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_PU_MASK 0x00000004L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_SCHMEN_MASK 0x00000008L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_S0_MASK 0x00000010L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_S1_MASK 0x00000020L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXEN_MASK 0x00000040L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL0_MASK 0x00000080L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL1_MASK 0x00000100L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_OE_OVERRIDE_MASK 0x00010000L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_OE_MASK 0x00020000L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_A_OVERRIDE_MASK 0x00040000L
+#define THM_GPIO_MACO_EN_CTRL__MACO_EN_A_MASK 0x00080000L
+#define THM_GPIO_MACO_EN_CTRL__Y_MASK 0x80000000L
+//SBTSI_REMOTE_TEMP
+#define SBTSI_REMOTE_TEMP__RemoteTcenSensor__SHIFT 0x0
+#define SBTSI_REMOTE_TEMP__RemoteTcenSensorId__SHIFT 0xb
+#define SBTSI_REMOTE_TEMP__RemoteTcenSensorValid__SHIFT 0x13
+#define SBTSI_REMOTE_TEMP__RemoteTcenSensor_MASK 0x000007FFL
+#define SBTSI_REMOTE_TEMP__RemoteTcenSensorId_MASK 0x0007F800L
+#define SBTSI_REMOTE_TEMP__RemoteTcenSensorValid_MASK 0x00080000L
+//SBRMI_CONTROL
+#define SBRMI_CONTROL__READ_CMD_INT_DIS__SHIFT 0x0
+#define SBRMI_CONTROL__DPD__SHIFT 0x1
+#define SBRMI_CONTROL__DbrdySts__SHIFT 0x2
+#define SBRMI_CONTROL__READ_CMD_INT_DIS_MASK 0x00000001L
+#define SBRMI_CONTROL__DPD_MASK 0x00000002L
+#define SBRMI_CONTROL__DbrdySts_MASK 0x00000004L
+//SBRMI_COMMAND
+#define SBRMI_COMMAND__Command__SHIFT 0x0
+#define SBRMI_COMMAND__WrDataLen__SHIFT 0x8
+#define SBRMI_COMMAND__RdDataLen__SHIFT 0x10
+#define SBRMI_COMMAND__CommandSent__SHIFT 0x18
+#define SBRMI_COMMAND__CommandNotSupported__SHIFT 0x19
+#define SBRMI_COMMAND__CommandAborted__SHIFT 0x1a
+#define SBRMI_COMMAND__Status__SHIFT 0x1c
+#define SBRMI_COMMAND__Command_MASK 0x000000FFL
+#define SBRMI_COMMAND__WrDataLen_MASK 0x0000FF00L
+#define SBRMI_COMMAND__RdDataLen_MASK 0x00FF0000L
+#define SBRMI_COMMAND__CommandSent_MASK 0x01000000L
+#define SBRMI_COMMAND__CommandNotSupported_MASK 0x02000000L
+#define SBRMI_COMMAND__CommandAborted_MASK 0x04000000L
+#define SBRMI_COMMAND__Status_MASK 0xF0000000L
+//SBRMI_WRITE_DATA0
+#define SBRMI_WRITE_DATA0__WrByte0__SHIFT 0x0
+#define SBRMI_WRITE_DATA0__WrByte1__SHIFT 0x8
+#define SBRMI_WRITE_DATA0__WrByte2__SHIFT 0x10
+#define SBRMI_WRITE_DATA0__WrByte3__SHIFT 0x18
+#define SBRMI_WRITE_DATA0__WrByte0_MASK 0x000000FFL
+#define SBRMI_WRITE_DATA0__WrByte1_MASK 0x0000FF00L
+#define SBRMI_WRITE_DATA0__WrByte2_MASK 0x00FF0000L
+#define SBRMI_WRITE_DATA0__WrByte3_MASK 0xFF000000L
+//SBRMI_WRITE_DATA1
+#define SBRMI_WRITE_DATA1__WrByte4__SHIFT 0x0
+#define SBRMI_WRITE_DATA1__WrByte5__SHIFT 0x8
+#define SBRMI_WRITE_DATA1__WrByte6__SHIFT 0x10
+#define SBRMI_WRITE_DATA1__WrByte7__SHIFT 0x18
+#define SBRMI_WRITE_DATA1__WrByte4_MASK 0x000000FFL
+#define SBRMI_WRITE_DATA1__WrByte5_MASK 0x0000FF00L
+#define SBRMI_WRITE_DATA1__WrByte6_MASK 0x00FF0000L
+#define SBRMI_WRITE_DATA1__WrByte7_MASK 0xFF000000L
+//SBRMI_WRITE_DATA2
+#define SBRMI_WRITE_DATA2__WrByte8__SHIFT 0x0
+#define SBRMI_WRITE_DATA2__WrByte9__SHIFT 0x8
+#define SBRMI_WRITE_DATA2__WrByte10__SHIFT 0x10
+#define SBRMI_WRITE_DATA2__WrByte11__SHIFT 0x18
+#define SBRMI_WRITE_DATA2__WrByte8_MASK 0x000000FFL
+#define SBRMI_WRITE_DATA2__WrByte9_MASK 0x0000FF00L
+#define SBRMI_WRITE_DATA2__WrByte10_MASK 0x00FF0000L
+#define SBRMI_WRITE_DATA2__WrByte11_MASK 0xFF000000L
+//SBRMI_READ_DATA0
+#define SBRMI_READ_DATA0__RdByte0__SHIFT 0x0
+#define SBRMI_READ_DATA0__RdByte1__SHIFT 0x8
+#define SBRMI_READ_DATA0__RdByte2__SHIFT 0x10
+#define SBRMI_READ_DATA0__RdByte3__SHIFT 0x18
+#define SBRMI_READ_DATA0__RdByte0_MASK 0x000000FFL
+#define SBRMI_READ_DATA0__RdByte1_MASK 0x0000FF00L
+#define SBRMI_READ_DATA0__RdByte2_MASK 0x00FF0000L
+#define SBRMI_READ_DATA0__RdByte3_MASK 0xFF000000L
+//SBRMI_READ_DATA1
+#define SBRMI_READ_DATA1__RdByte4__SHIFT 0x0
+#define SBRMI_READ_DATA1__RdByte5__SHIFT 0x8
+#define SBRMI_READ_DATA1__RdByte6__SHIFT 0x10
+#define SBRMI_READ_DATA1__RdByte7__SHIFT 0x18
+#define SBRMI_READ_DATA1__RdByte4_MASK 0x000000FFL
+#define SBRMI_READ_DATA1__RdByte5_MASK 0x0000FF00L
+#define SBRMI_READ_DATA1__RdByte6_MASK 0x00FF0000L
+#define SBRMI_READ_DATA1__RdByte7_MASK 0xFF000000L
+//SBRMI_CORE_EN_NUMBER
+#define SBRMI_CORE_EN_NUMBER__EnabledCoreNum__SHIFT 0x0
+#define SBRMI_CORE_EN_NUMBER__EnabledCoreNum_MASK 0x0000007FL
+//SBRMI_CORE_EN_STATUS0
+#define SBRMI_CORE_EN_STATUS0__CoreEnStat0__SHIFT 0x0
+#define SBRMI_CORE_EN_STATUS0__CoreEnStat0_MASK 0xFFFFFFFFL
+//SBRMI_CORE_EN_STATUS1
+#define SBRMI_CORE_EN_STATUS1__CoreEnStat1__SHIFT 0x0
+#define SBRMI_CORE_EN_STATUS1__CoreEnStat1_MASK 0xFFFFFFFFL
+//SBRMI_APIC_STATUS0
+#define SBRMI_APIC_STATUS0__APICStat0__SHIFT 0x0
+#define SBRMI_APIC_STATUS0__APICStat0_MASK 0xFFFFFFFFL
+//SBRMI_APIC_STATUS1
+#define SBRMI_APIC_STATUS1__APICStat1__SHIFT 0x0
+#define SBRMI_APIC_STATUS1__APICStat1_MASK 0xFFFFFFFFL
+//SBRMI_MCE_STATUS0
+#define SBRMI_MCE_STATUS0__MceStat0__SHIFT 0x0
+#define SBRMI_MCE_STATUS0__MceStat0_MASK 0xFFFFFFFFL
+//SBRMI_MCE_STATUS1
+#define SBRMI_MCE_STATUS1__MceStat1__SHIFT 0x0
+#define SBRMI_MCE_STATUS1__MceStat1_MASK 0xFFFFFFFFL
+//SMBUS_CNTL0
+#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_OVERRIDE__SHIFT 0x0
+#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR__SHIFT 0x1
+#define SMBUS_CNTL0__SMB_CPL_DUMMY_BYTE__SHIFT 0x8
+#define SMBUS_CNTL0__SMB_NOTIFY_ARP_MAX_TIMES__SHIFT 0x10
+#define SMBUS_CNTL0__THM_READY__SHIFT 0x14
+#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_OVERRIDE_MASK 0x00000001L
+#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_MASK 0x000000FEL
+#define SMBUS_CNTL0__SMB_CPL_DUMMY_BYTE_MASK 0x0000FF00L
+#define SMBUS_CNTL0__SMB_NOTIFY_ARP_MAX_TIMES_MASK 0x00070000L
+#define SMBUS_CNTL0__THM_READY_MASK 0x00100000L
+//SMBUS_CNTL1
+#define SMBUS_CNTL1__SMB_TIMEOUT_EN__SHIFT 0x0
+#define SMBUS_CNTL1__SMB_BLK_WR_CMD_EN__SHIFT 0x1
+#define SMBUS_CNTL1__SMB_BLK_RD_CMD_EN__SHIFT 0x9
+#define SMBUS_CNTL1__SMB_TIMEOUT_EN_MASK 0x00000001L
+#define SMBUS_CNTL1__SMB_BLK_WR_CMD_EN_MASK 0x000001FEL
+#define SMBUS_CNTL1__SMB_BLK_RD_CMD_EN_MASK 0x0001FE00L
+//SMBUS_BLKWR_CMD_CTRL0
+#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD0__SHIFT 0x0
+#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD1__SHIFT 0x8
+#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD2__SHIFT 0x10
+#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD3__SHIFT 0x18
+#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD0_MASK 0x000000FFL
+#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD1_MASK 0x0000FF00L
+#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD2_MASK 0x00FF0000L
+#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD3_MASK 0xFF000000L
+//SMBUS_BLKWR_CMD_CTRL1
+#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD4__SHIFT 0x0
+#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD5__SHIFT 0x8
+#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD6__SHIFT 0x10
+#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD7__SHIFT 0x18
+#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD4_MASK 0x000000FFL
+#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD5_MASK 0x0000FF00L
+#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD6_MASK 0x00FF0000L
+#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD7_MASK 0xFF000000L
+//SMBUS_BLKRD_CMD_CTRL0
+#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD0__SHIFT 0x0
+#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD1__SHIFT 0x8
+#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD2__SHIFT 0x10
+#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD3__SHIFT 0x18
+#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD0_MASK 0x000000FFL
+#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD1_MASK 0x0000FF00L
+#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD2_MASK 0x00FF0000L
+#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD3_MASK 0xFF000000L
+//SMBUS_BLKRD_CMD_CTRL1
+#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD4__SHIFT 0x0
+#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD5__SHIFT 0x8
+#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD6__SHIFT 0x10
+#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD7__SHIFT 0x18
+#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD4_MASK 0x000000FFL
+#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD5_MASK 0x0000FF00L
+#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD6_MASK 0x00FF0000L
+#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD7_MASK 0xFF000000L
+//SMBUS_TIMING_CNTL0
+#define SMBUS_TIMING_CNTL0__SMB_TIMEOUT_MARGIN__SHIFT 0x0
+#define SMBUS_TIMING_CNTL0__SMB_FILTER_LEVEL_CONVERT_MARGIN__SHIFT 0x16
+#define SMBUS_TIMING_CNTL0__SMB_TIMEOUT_MARGIN_MASK 0x003FFFFFL
+#define SMBUS_TIMING_CNTL0__SMB_FILTER_LEVEL_CONVERT_MARGIN_MASK 0x3FC00000L
+//SMBUS_TIMING_CNTL1
+#define SMBUS_TIMING_CNTL1__SMB_DAT_SETUP_TIME_MARGIN__SHIFT 0x0
+#define SMBUS_TIMING_CNTL1__SMB_DAT_HOLD_TIME_MARGIN__SHIFT 0x5
+#define SMBUS_TIMING_CNTL1__SMB_START_AND_STOP_TIMING_MARGIN__SHIFT 0xb
+#define SMBUS_TIMING_CNTL1__SMB_BUS_FREE_MARGIN__SHIFT 0x14
+#define SMBUS_TIMING_CNTL1__SMB_DAT_SETUP_TIME_MARGIN_MASK 0x0000001FL
+#define SMBUS_TIMING_CNTL1__SMB_DAT_HOLD_TIME_MARGIN_MASK 0x000007E0L
+#define SMBUS_TIMING_CNTL1__SMB_START_AND_STOP_TIMING_MARGIN_MASK 0x000FF800L
+#define SMBUS_TIMING_CNTL1__SMB_BUS_FREE_MARGIN_MASK 0x3FF00000L
+//SMBUS_TIMING_CNTL2
+#define SMBUS_TIMING_CNTL2__SMB_SMBCLK_HIGHMAX_MARGIN__SHIFT 0x0
+#define SMBUS_TIMING_CNTL2__SMBCLK_LEVEL_CTRL_MARGIN__SHIFT 0xd
+#define SMBUS_TIMING_CNTL2__SMB_SMBCLK_HIGHMAX_MARGIN_MASK 0x00001FFFL
+#define SMBUS_TIMING_CNTL2__SMBCLK_LEVEL_CTRL_MARGIN_MASK 0x07FFE000L
+//SMBUS_TRIGGER_CNTL
+#define SMBUS_TRIGGER_CNTL__SMB_SOFT_RESET_TRIGGER__SHIFT 0x0
+#define SMBUS_TRIGGER_CNTL__SMB_NOTIFY_ARP_TRIGGER__SHIFT 0x8
+#define SMBUS_TRIGGER_CNTL__SMB_SOFT_RESET_TRIGGER_MASK 0x00000001L
+#define SMBUS_TRIGGER_CNTL__SMB_NOTIFY_ARP_TRIGGER_MASK 0x00000100L
+//SMBUS_UDID_CNTL0
+#define SMBUS_UDID_CNTL0__SMB_PRBS_INI_SEED__SHIFT 0x0
+#define SMBUS_UDID_CNTL0__SMB_SRST_REGEN_UDID_EN__SHIFT 0x1f
+#define SMBUS_UDID_CNTL0__SMB_PRBS_INI_SEED_MASK 0x7FFFFFFFL
+#define SMBUS_UDID_CNTL0__SMB_SRST_REGEN_UDID_EN_MASK 0x80000000L
+//SMBUS_UDID_CNTL1
+#define SMBUS_UDID_CNTL1__SMB_UDID_31_0__SHIFT 0x0
+#define SMBUS_UDID_CNTL1__SMB_UDID_31_0_MASK 0xFFFFFFFFL
+//SMBUS_UDID_CNTL2
+#define SMBUS_UDID_CNTL2__PEC_SUPPORTED__SHIFT 0x0
+#define SMBUS_UDID_CNTL2__UDID_VERSION__SHIFT 0x1
+#define SMBUS_UDID_CNTL2__SMBUS_VERSION__SHIFT 0x4
+#define SMBUS_UDID_CNTL2__OEM__SHIFT 0x8
+#define SMBUS_UDID_CNTL2__ASF__SHIFT 0x9
+#define SMBUS_UDID_CNTL2__IPMI__SHIFT 0xa
+#define SMBUS_UDID_CNTL2__PEC_SUPPORTED_MASK 0x00000001L
+#define SMBUS_UDID_CNTL2__UDID_VERSION_MASK 0x0000000EL
+#define SMBUS_UDID_CNTL2__SMBUS_VERSION_MASK 0x000000F0L
+#define SMBUS_UDID_CNTL2__OEM_MASK 0x00000100L
+#define SMBUS_UDID_CNTL2__ASF_MASK 0x00000200L
+#define SMBUS_UDID_CNTL2__IPMI_MASK 0x00000400L
+//THM_TMON0_REMOTE_START
+#define THM_TMON0_REMOTE_START__DATA__SHIFT 0x0
+#define THM_TMON0_REMOTE_START__DATA_MASK 0xFFFFFFFFL
+//THM_TMON0_REMOTE_END
+#define THM_TMON0_REMOTE_END__DATA__SHIFT 0x0
+#define THM_TMON0_REMOTE_END__DATA_MASK 0xFFFFFFFFL
+//THM_TMON1_REMOTE_START
+#define THM_TMON1_REMOTE_START__DATA__SHIFT 0x0
+#define THM_TMON1_REMOTE_START__DATA_MASK 0xFFFFFFFFL
+//THM_TMON1_REMOTE_END
+#define THM_TMON1_REMOTE_END__DATA__SHIFT 0x0
+#define THM_TMON1_REMOTE_END__DATA_MASK 0xFFFFFFFFL
+//THM_TMON2_REMOTE_START
+#define THM_TMON2_REMOTE_START__DATA__SHIFT 0x0
+#define THM_TMON2_REMOTE_START__DATA_MASK 0xFFFFFFFFL
+//THM_TMON2_REMOTE_END
+#define THM_TMON2_REMOTE_END__DATA__SHIFT 0x0
+#define THM_TMON2_REMOTE_END__DATA_MASK 0xFFFFFFFFL
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_7_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_7_0_offset.h
new file mode 100644
index 000000000000..912955f75b14
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_7_0_offset.h
@@ -0,0 +1,2620 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef _umc_6_7_0_OFFSET_HEADER
+#define _umc_6_7_0_OFFSET_HEADER
+
+
+
+// addressBlock: umc_w_phy_umc0_mca_ip_umc0_mca_map
+// base address: 0x50f00
+#define regMCA_UMC_UMC0_MCUMC_STATUST0 0x03c2
+#define regMCA_UMC_UMC0_MCUMC_STATUST0_BASE_IDX 0
+#define regMCA_UMC_UMC0_MCUMC_ADDRT0 0x03c4
+#define regMCA_UMC_UMC0_MCUMC_ADDRT0_BASE_IDX 0
+
+
+// addressBlock: umc_w_phy_umc0_umcch0_umcchdec
+// base address: 0x50000
+#define regUMCCH0_0_BaseAddrCS0 0x0000
+#define regUMCCH0_0_BaseAddrCS0_BASE_IDX 0
+#define regUMCCH0_0_AddrMaskCS01 0x0008
+#define regUMCCH0_0_AddrMaskCS01_BASE_IDX 0
+#define regUMCCH0_0_AddrSelCS01 0x0010
+#define regUMCCH0_0_AddrSelCS01_BASE_IDX 0
+#define regUMCCH0_0_AddrHashBank0 0x0032
+#define regUMCCH0_0_AddrHashBank0_BASE_IDX 0
+#define regUMCCH0_0_AddrHashBank1 0x0033
+#define regUMCCH0_0_AddrHashBank1_BASE_IDX 0
+#define regUMCCH0_0_AddrHashBank2 0x0034
+#define regUMCCH0_0_AddrHashBank2_BASE_IDX 0
+#define regUMCCH0_0_AddrHashBank3 0x0035
+#define regUMCCH0_0_AddrHashBank3_BASE_IDX 0
+#define regUMCCH0_0_AddrHashBank4 0x0036
+#define regUMCCH0_0_AddrHashBank4_BASE_IDX 0
+#define regUMCCH0_0_AddrHashBank5 0x0037
+#define regUMCCH0_0_AddrHashBank5_BASE_IDX 0
+#define regUMCCH0_0_UMC_CONFIG 0x0040
+#define regUMCCH0_0_UMC_CONFIG_BASE_IDX 0
+#define regUMCCH0_0_EccCtrl 0x0053
+#define regUMCCH0_0_EccCtrl_BASE_IDX 0
+#define regUMCCH0_0_UmcLocalCap 0x0306
+#define regUMCCH0_0_UmcLocalCap_BASE_IDX 0
+#define regUMCCH0_0_EccErrCntSel 0x0328
+#define regUMCCH0_0_EccErrCntSel_BASE_IDX 0
+#define regUMCCH0_0_EccErrCnt 0x0329
+#define regUMCCH0_0_EccErrCnt_BASE_IDX 0
+#define regUMCCH0_0_PerfMonCtlClk 0x0340
+#define regUMCCH0_0_PerfMonCtlClk_BASE_IDX 0
+#define regUMCCH0_0_PerfMonCtrClk_Lo 0x0341
+#define regUMCCH0_0_PerfMonCtrClk_Lo_BASE_IDX 0
+#define regUMCCH0_0_PerfMonCtrClk_Hi 0x0342
+#define regUMCCH0_0_PerfMonCtrClk_Hi_BASE_IDX 0
+#define regUMCCH0_0_PerfMonCtl1 0x0344
+#define regUMCCH0_0_PerfMonCtl1_BASE_IDX 0
+#define regUMCCH0_0_PerfMonCtr1_Lo 0x0345
+#define regUMCCH0_0_PerfMonCtr1_Lo_BASE_IDX 0
+#define regUMCCH0_0_PerfMonCtr1_Hi 0x0346
+#define regUMCCH0_0_PerfMonCtr1_Hi_BASE_IDX 0
+#define regUMCCH0_0_PerfMonCtl2 0x0347
+#define regUMCCH0_0_PerfMonCtl2_BASE_IDX 0
+#define regUMCCH0_0_PerfMonCtr2_Lo 0x0348
+#define regUMCCH0_0_PerfMonCtr2_Lo_BASE_IDX 0
+#define regUMCCH0_0_PerfMonCtr2_Hi 0x0349
+#define regUMCCH0_0_PerfMonCtr2_Hi_BASE_IDX 0
+#define regUMCCH0_0_PerfMonCtl3 0x034a
+#define regUMCCH0_0_PerfMonCtl3_BASE_IDX 0
+#define regUMCCH0_0_PerfMonCtr3_Lo 0x034b
+#define regUMCCH0_0_PerfMonCtr3_Lo_BASE_IDX 0
+#define regUMCCH0_0_PerfMonCtr3_Hi 0x034c
+#define regUMCCH0_0_PerfMonCtr3_Hi_BASE_IDX 0
+#define regUMCCH0_0_PerfMonCtl4 0x034d
+#define regUMCCH0_0_PerfMonCtl4_BASE_IDX 0
+#define regUMCCH0_0_PerfMonCtr4_Lo 0x034e
+#define regUMCCH0_0_PerfMonCtr4_Lo_BASE_IDX 0
+#define regUMCCH0_0_PerfMonCtr4_Hi 0x034f
+#define regUMCCH0_0_PerfMonCtr4_Hi_BASE_IDX 0
+#define regUMCCH0_0_PerfMonCtl5 0x0350
+#define regUMCCH0_0_PerfMonCtl5_BASE_IDX 0
+#define regUMCCH0_0_PerfMonCtr5_Lo 0x0351
+#define regUMCCH0_0_PerfMonCtr5_Lo_BASE_IDX 0
+#define regUMCCH0_0_PerfMonCtr5_Hi 0x0352
+#define regUMCCH0_0_PerfMonCtr5_Hi_BASE_IDX 0
+#define regUMCCH0_0_PerfMonCtl6 0x0353
+#define regUMCCH0_0_PerfMonCtl6_BASE_IDX 0
+#define regUMCCH0_0_PerfMonCtr6_Lo 0x0354
+#define regUMCCH0_0_PerfMonCtr6_Lo_BASE_IDX 0
+#define regUMCCH0_0_PerfMonCtr6_Hi 0x0355
+#define regUMCCH0_0_PerfMonCtr6_Hi_BASE_IDX 0
+#define regUMCCH0_0_PerfMonCtl7 0x0356
+#define regUMCCH0_0_PerfMonCtl7_BASE_IDX 0
+#define regUMCCH0_0_PerfMonCtr7_Lo 0x0357
+#define regUMCCH0_0_PerfMonCtr7_Lo_BASE_IDX 0
+#define regUMCCH0_0_PerfMonCtr7_Hi 0x0358
+#define regUMCCH0_0_PerfMonCtr7_Hi_BASE_IDX 0
+#define regUMCCH0_0_PerfMonCtl8 0x0359
+#define regUMCCH0_0_PerfMonCtl8_BASE_IDX 0
+#define regUMCCH0_0_PerfMonCtr8_Lo 0x035a
+#define regUMCCH0_0_PerfMonCtr8_Lo_BASE_IDX 0
+#define regUMCCH0_0_PerfMonCtr8_Hi 0x035b
+#define regUMCCH0_0_PerfMonCtr8_Hi_BASE_IDX 0
+
+
+// addressBlock: umc_w_phy_umc0_umcch1_umcchdec
+// base address: 0x51000
+#define regUMCCH1_0_BaseAddrCS0 0x0400
+#define regUMCCH1_0_BaseAddrCS0_BASE_IDX 0
+#define regUMCCH1_0_AddrMaskCS01 0x0408
+#define regUMCCH1_0_AddrMaskCS01_BASE_IDX 0
+#define regUMCCH1_0_AddrSelCS01 0x0410
+#define regUMCCH1_0_AddrSelCS01_BASE_IDX 0
+#define regUMCCH1_0_AddrHashBank0 0x0432
+#define regUMCCH1_0_AddrHashBank0_BASE_IDX 0
+#define regUMCCH1_0_AddrHashBank1 0x0433
+#define regUMCCH1_0_AddrHashBank1_BASE_IDX 0
+#define regUMCCH1_0_AddrHashBank2 0x0434
+#define regUMCCH1_0_AddrHashBank2_BASE_IDX 0
+#define regUMCCH1_0_AddrHashBank3 0x0435
+#define regUMCCH1_0_AddrHashBank3_BASE_IDX 0
+#define regUMCCH1_0_AddrHashBank4 0x0436
+#define regUMCCH1_0_AddrHashBank4_BASE_IDX 0
+#define regUMCCH1_0_AddrHashBank5 0x0437
+#define regUMCCH1_0_AddrHashBank5_BASE_IDX 0
+#define regUMCCH1_0_UMC_CONFIG 0x0440
+#define regUMCCH1_0_UMC_CONFIG_BASE_IDX 0
+#define regUMCCH1_0_EccCtrl 0x0453
+#define regUMCCH1_0_EccCtrl_BASE_IDX 0
+#define regUMCCH1_0_UmcLocalCap 0x0706
+#define regUMCCH1_0_UmcLocalCap_BASE_IDX 0
+#define regUMCCH1_0_EccErrCntSel 0x0728
+#define regUMCCH1_0_EccErrCntSel_BASE_IDX 0
+#define regUMCCH1_0_EccErrCnt 0x0729
+#define regUMCCH1_0_EccErrCnt_BASE_IDX 0
+#define regUMCCH1_0_PerfMonCtlClk 0x0740
+#define regUMCCH1_0_PerfMonCtlClk_BASE_IDX 0
+#define regUMCCH1_0_PerfMonCtrClk_Lo 0x0741
+#define regUMCCH1_0_PerfMonCtrClk_Lo_BASE_IDX 0
+#define regUMCCH1_0_PerfMonCtrClk_Hi 0x0742
+#define regUMCCH1_0_PerfMonCtrClk_Hi_BASE_IDX 0
+#define regUMCCH1_0_PerfMonCtl1 0x0744
+#define regUMCCH1_0_PerfMonCtl1_BASE_IDX 0
+#define regUMCCH1_0_PerfMonCtr1_Lo 0x0745
+#define regUMCCH1_0_PerfMonCtr1_Lo_BASE_IDX 0
+#define regUMCCH1_0_PerfMonCtr1_Hi 0x0746
+#define regUMCCH1_0_PerfMonCtr1_Hi_BASE_IDX 0
+#define regUMCCH1_0_PerfMonCtl2 0x0747
+#define regUMCCH1_0_PerfMonCtl2_BASE_IDX 0
+#define regUMCCH1_0_PerfMonCtr2_Lo 0x0748
+#define regUMCCH1_0_PerfMonCtr2_Lo_BASE_IDX 0
+#define regUMCCH1_0_PerfMonCtr2_Hi 0x0749
+#define regUMCCH1_0_PerfMonCtr2_Hi_BASE_IDX 0
+#define regUMCCH1_0_PerfMonCtl3 0x074a
+#define regUMCCH1_0_PerfMonCtl3_BASE_IDX 0
+#define regUMCCH1_0_PerfMonCtr3_Lo 0x074b
+#define regUMCCH1_0_PerfMonCtr3_Lo_BASE_IDX 0
+#define regUMCCH1_0_PerfMonCtr3_Hi 0x074c
+#define regUMCCH1_0_PerfMonCtr3_Hi_BASE_IDX 0
+#define regUMCCH1_0_PerfMonCtl4 0x074d
+#define regUMCCH1_0_PerfMonCtl4_BASE_IDX 0
+#define regUMCCH1_0_PerfMonCtr4_Lo 0x074e
+#define regUMCCH1_0_PerfMonCtr4_Lo_BASE_IDX 0
+#define regUMCCH1_0_PerfMonCtr4_Hi 0x074f
+#define regUMCCH1_0_PerfMonCtr4_Hi_BASE_IDX 0
+#define regUMCCH1_0_PerfMonCtl5 0x0750
+#define regUMCCH1_0_PerfMonCtl5_BASE_IDX 0
+#define regUMCCH1_0_PerfMonCtr5_Lo 0x0751
+#define regUMCCH1_0_PerfMonCtr5_Lo_BASE_IDX 0
+#define regUMCCH1_0_PerfMonCtr5_Hi 0x0752
+#define regUMCCH1_0_PerfMonCtr5_Hi_BASE_IDX 0
+#define regUMCCH1_0_PerfMonCtl6 0x0753
+#define regUMCCH1_0_PerfMonCtl6_BASE_IDX 0
+#define regUMCCH1_0_PerfMonCtr6_Lo 0x0754
+#define regUMCCH1_0_PerfMonCtr6_Lo_BASE_IDX 0
+#define regUMCCH1_0_PerfMonCtr6_Hi 0x0755
+#define regUMCCH1_0_PerfMonCtr6_Hi_BASE_IDX 0
+#define regUMCCH1_0_PerfMonCtl7 0x0756
+#define regUMCCH1_0_PerfMonCtl7_BASE_IDX 0
+#define regUMCCH1_0_PerfMonCtr7_Lo 0x0757
+#define regUMCCH1_0_PerfMonCtr7_Lo_BASE_IDX 0
+#define regUMCCH1_0_PerfMonCtr7_Hi 0x0758
+#define regUMCCH1_0_PerfMonCtr7_Hi_BASE_IDX 0
+#define regUMCCH1_0_PerfMonCtl8 0x0759
+#define regUMCCH1_0_PerfMonCtl8_BASE_IDX 0
+#define regUMCCH1_0_PerfMonCtr8_Lo 0x075a
+#define regUMCCH1_0_PerfMonCtr8_Lo_BASE_IDX 0
+#define regUMCCH1_0_PerfMonCtr8_Hi 0x075b
+#define regUMCCH1_0_PerfMonCtr8_Hi_BASE_IDX 0
+
+
+// addressBlock: umc_w_phy_umc0_umcch2_umcchdec
+// base address: 0x52000
+#define regUMCCH2_0_BaseAddrCS0 0x0800
+#define regUMCCH2_0_BaseAddrCS0_BASE_IDX 0
+#define regUMCCH2_0_AddrMaskCS01 0x0808
+#define regUMCCH2_0_AddrMaskCS01_BASE_IDX 0
+#define regUMCCH2_0_AddrSelCS01 0x0810
+#define regUMCCH2_0_AddrSelCS01_BASE_IDX 0
+#define regUMCCH2_0_AddrHashBank0 0x0832
+#define regUMCCH2_0_AddrHashBank0_BASE_IDX 0
+#define regUMCCH2_0_AddrHashBank1 0x0833
+#define regUMCCH2_0_AddrHashBank1_BASE_IDX 0
+#define regUMCCH2_0_AddrHashBank2 0x0834
+#define regUMCCH2_0_AddrHashBank2_BASE_IDX 0
+#define regUMCCH2_0_AddrHashBank3 0x0835
+#define regUMCCH2_0_AddrHashBank3_BASE_IDX 0
+#define regUMCCH2_0_AddrHashBank4 0x0836
+#define regUMCCH2_0_AddrHashBank4_BASE_IDX 0
+#define regUMCCH2_0_AddrHashBank5 0x0837
+#define regUMCCH2_0_AddrHashBank5_BASE_IDX 0
+#define regUMCCH2_0_UMC_CONFIG 0x0840
+#define regUMCCH2_0_UMC_CONFIG_BASE_IDX 0
+#define regUMCCH2_0_EccCtrl 0x0853
+#define regUMCCH2_0_EccCtrl_BASE_IDX 0
+#define regUMCCH2_0_UmcLocalCap 0x0b06
+#define regUMCCH2_0_UmcLocalCap_BASE_IDX 0
+#define regUMCCH2_0_EccErrCntSel 0x0b28
+#define regUMCCH2_0_EccErrCntSel_BASE_IDX 0
+#define regUMCCH2_0_EccErrCnt 0x0b29
+#define regUMCCH2_0_EccErrCnt_BASE_IDX 0
+#define regUMCCH2_0_PerfMonCtlClk 0x0b40
+#define regUMCCH2_0_PerfMonCtlClk_BASE_IDX 0
+#define regUMCCH2_0_PerfMonCtrClk_Lo 0x0b41
+#define regUMCCH2_0_PerfMonCtrClk_Lo_BASE_IDX 0
+#define regUMCCH2_0_PerfMonCtrClk_Hi 0x0b42
+#define regUMCCH2_0_PerfMonCtrClk_Hi_BASE_IDX 0
+#define regUMCCH2_0_PerfMonCtl1 0x0b44
+#define regUMCCH2_0_PerfMonCtl1_BASE_IDX 0
+#define regUMCCH2_0_PerfMonCtr1_Lo 0x0b45
+#define regUMCCH2_0_PerfMonCtr1_Lo_BASE_IDX 0
+#define regUMCCH2_0_PerfMonCtr1_Hi 0x0b46
+#define regUMCCH2_0_PerfMonCtr1_Hi_BASE_IDX 0
+#define regUMCCH2_0_PerfMonCtl2 0x0b47
+#define regUMCCH2_0_PerfMonCtl2_BASE_IDX 0
+#define regUMCCH2_0_PerfMonCtr2_Lo 0x0b48
+#define regUMCCH2_0_PerfMonCtr2_Lo_BASE_IDX 0
+#define regUMCCH2_0_PerfMonCtr2_Hi 0x0b49
+#define regUMCCH2_0_PerfMonCtr2_Hi_BASE_IDX 0
+#define regUMCCH2_0_PerfMonCtl3 0x0b4a
+#define regUMCCH2_0_PerfMonCtl3_BASE_IDX 0
+#define regUMCCH2_0_PerfMonCtr3_Lo 0x0b4b
+#define regUMCCH2_0_PerfMonCtr3_Lo_BASE_IDX 0
+#define regUMCCH2_0_PerfMonCtr3_Hi 0x0b4c
+#define regUMCCH2_0_PerfMonCtr3_Hi_BASE_IDX 0
+#define regUMCCH2_0_PerfMonCtl4 0x0b4d
+#define regUMCCH2_0_PerfMonCtl4_BASE_IDX 0
+#define regUMCCH2_0_PerfMonCtr4_Lo 0x0b4e
+#define regUMCCH2_0_PerfMonCtr4_Lo_BASE_IDX 0
+#define regUMCCH2_0_PerfMonCtr4_Hi 0x0b4f
+#define regUMCCH2_0_PerfMonCtr4_Hi_BASE_IDX 0
+#define regUMCCH2_0_PerfMonCtl5 0x0b50
+#define regUMCCH2_0_PerfMonCtl5_BASE_IDX 0
+#define regUMCCH2_0_PerfMonCtr5_Lo 0x0b51
+#define regUMCCH2_0_PerfMonCtr5_Lo_BASE_IDX 0
+#define regUMCCH2_0_PerfMonCtr5_Hi 0x0b52
+#define regUMCCH2_0_PerfMonCtr5_Hi_BASE_IDX 0
+#define regUMCCH2_0_PerfMonCtl6 0x0b53
+#define regUMCCH2_0_PerfMonCtl6_BASE_IDX 0
+#define regUMCCH2_0_PerfMonCtr6_Lo 0x0b54
+#define regUMCCH2_0_PerfMonCtr6_Lo_BASE_IDX 0
+#define regUMCCH2_0_PerfMonCtr6_Hi 0x0b55
+#define regUMCCH2_0_PerfMonCtr6_Hi_BASE_IDX 0
+#define regUMCCH2_0_PerfMonCtl7 0x0b56
+#define regUMCCH2_0_PerfMonCtl7_BASE_IDX 0
+#define regUMCCH2_0_PerfMonCtr7_Lo 0x0b57
+#define regUMCCH2_0_PerfMonCtr7_Lo_BASE_IDX 0
+#define regUMCCH2_0_PerfMonCtr7_Hi 0x0b58
+#define regUMCCH2_0_PerfMonCtr7_Hi_BASE_IDX 0
+#define regUMCCH2_0_PerfMonCtl8 0x0b59
+#define regUMCCH2_0_PerfMonCtl8_BASE_IDX 0
+#define regUMCCH2_0_PerfMonCtr8_Lo 0x0b5a
+#define regUMCCH2_0_PerfMonCtr8_Lo_BASE_IDX 0
+#define regUMCCH2_0_PerfMonCtr8_Hi 0x0b5b
+#define regUMCCH2_0_PerfMonCtr8_Hi_BASE_IDX 0
+
+
+// addressBlock: umc_w_phy_umc0_umcch3_umcchdec
+// base address: 0x53000
+#define regUMCCH3_0_BaseAddrCS0 0x0c00
+#define regUMCCH3_0_BaseAddrCS0_BASE_IDX 0
+#define regUMCCH3_0_AddrMaskCS01 0x0c08
+#define regUMCCH3_0_AddrMaskCS01_BASE_IDX 0
+#define regUMCCH3_0_AddrSelCS01 0x0c10
+#define regUMCCH3_0_AddrSelCS01_BASE_IDX 0
+#define regUMCCH3_0_AddrHashBank0 0x0c32
+#define regUMCCH3_0_AddrHashBank0_BASE_IDX 0
+#define regUMCCH3_0_AddrHashBank1 0x0c33
+#define regUMCCH3_0_AddrHashBank1_BASE_IDX 0
+#define regUMCCH3_0_AddrHashBank2 0x0c34
+#define regUMCCH3_0_AddrHashBank2_BASE_IDX 0
+#define regUMCCH3_0_AddrHashBank3 0x0c35
+#define regUMCCH3_0_AddrHashBank3_BASE_IDX 0
+#define regUMCCH3_0_AddrHashBank4 0x0c36
+#define regUMCCH3_0_AddrHashBank4_BASE_IDX 0
+#define regUMCCH3_0_AddrHashBank5 0x0c37
+#define regUMCCH3_0_AddrHashBank5_BASE_IDX 0
+#define regUMCCH3_0_UMC_CONFIG 0x0c40
+#define regUMCCH3_0_UMC_CONFIG_BASE_IDX 0
+#define regUMCCH3_0_EccCtrl 0x0c53
+#define regUMCCH3_0_EccCtrl_BASE_IDX 0
+#define regUMCCH3_0_UmcLocalCap 0x0f06
+#define regUMCCH3_0_UmcLocalCap_BASE_IDX 0
+#define regUMCCH3_0_EccErrCntSel 0x0f28
+#define regUMCCH3_0_EccErrCntSel_BASE_IDX 0
+#define regUMCCH3_0_EccErrCnt 0x0f29
+#define regUMCCH3_0_EccErrCnt_BASE_IDX 0
+#define regUMCCH3_0_PerfMonCtlClk 0x0f40
+#define regUMCCH3_0_PerfMonCtlClk_BASE_IDX 0
+#define regUMCCH3_0_PerfMonCtrClk_Lo 0x0f41
+#define regUMCCH3_0_PerfMonCtrClk_Lo_BASE_IDX 0
+#define regUMCCH3_0_PerfMonCtrClk_Hi 0x0f42
+#define regUMCCH3_0_PerfMonCtrClk_Hi_BASE_IDX 0
+#define regUMCCH3_0_PerfMonCtl1 0x0f44
+#define regUMCCH3_0_PerfMonCtl1_BASE_IDX 0
+#define regUMCCH3_0_PerfMonCtr1_Lo 0x0f45
+#define regUMCCH3_0_PerfMonCtr1_Lo_BASE_IDX 0
+#define regUMCCH3_0_PerfMonCtr1_Hi 0x0f46
+#define regUMCCH3_0_PerfMonCtr1_Hi_BASE_IDX 0
+#define regUMCCH3_0_PerfMonCtl2 0x0f47
+#define regUMCCH3_0_PerfMonCtl2_BASE_IDX 0
+#define regUMCCH3_0_PerfMonCtr2_Lo 0x0f48
+#define regUMCCH3_0_PerfMonCtr2_Lo_BASE_IDX 0
+#define regUMCCH3_0_PerfMonCtr2_Hi 0x0f49
+#define regUMCCH3_0_PerfMonCtr2_Hi_BASE_IDX 0
+#define regUMCCH3_0_PerfMonCtl3 0x0f4a
+#define regUMCCH3_0_PerfMonCtl3_BASE_IDX 0
+#define regUMCCH3_0_PerfMonCtr3_Lo 0x0f4b
+#define regUMCCH3_0_PerfMonCtr3_Lo_BASE_IDX 0
+#define regUMCCH3_0_PerfMonCtr3_Hi 0x0f4c
+#define regUMCCH3_0_PerfMonCtr3_Hi_BASE_IDX 0
+#define regUMCCH3_0_PerfMonCtl4 0x0f4d
+#define regUMCCH3_0_PerfMonCtl4_BASE_IDX 0
+#define regUMCCH3_0_PerfMonCtr4_Lo 0x0f4e
+#define regUMCCH3_0_PerfMonCtr4_Lo_BASE_IDX 0
+#define regUMCCH3_0_PerfMonCtr4_Hi 0x0f4f
+#define regUMCCH3_0_PerfMonCtr4_Hi_BASE_IDX 0
+#define regUMCCH3_0_PerfMonCtl5 0x0f50
+#define regUMCCH3_0_PerfMonCtl5_BASE_IDX 0
+#define regUMCCH3_0_PerfMonCtr5_Lo 0x0f51
+#define regUMCCH3_0_PerfMonCtr5_Lo_BASE_IDX 0
+#define regUMCCH3_0_PerfMonCtr5_Hi 0x0f52
+#define regUMCCH3_0_PerfMonCtr5_Hi_BASE_IDX 0
+#define regUMCCH3_0_PerfMonCtl6 0x0f53
+#define regUMCCH3_0_PerfMonCtl6_BASE_IDX 0
+#define regUMCCH3_0_PerfMonCtr6_Lo 0x0f54
+#define regUMCCH3_0_PerfMonCtr6_Lo_BASE_IDX 0
+#define regUMCCH3_0_PerfMonCtr6_Hi 0x0f55
+#define regUMCCH3_0_PerfMonCtr6_Hi_BASE_IDX 0
+#define regUMCCH3_0_PerfMonCtl7 0x0f56
+#define regUMCCH3_0_PerfMonCtl7_BASE_IDX 0
+#define regUMCCH3_0_PerfMonCtr7_Lo 0x0f57
+#define regUMCCH3_0_PerfMonCtr7_Lo_BASE_IDX 0
+#define regUMCCH3_0_PerfMonCtr7_Hi 0x0f58
+#define regUMCCH3_0_PerfMonCtr7_Hi_BASE_IDX 0
+#define regUMCCH3_0_PerfMonCtl8 0x0f59
+#define regUMCCH3_0_PerfMonCtl8_BASE_IDX 0
+#define regUMCCH3_0_PerfMonCtr8_Lo 0x0f5a
+#define regUMCCH3_0_PerfMonCtr8_Lo_BASE_IDX 0
+#define regUMCCH3_0_PerfMonCtr8_Hi 0x0f5b
+#define regUMCCH3_0_PerfMonCtr8_Hi_BASE_IDX 0
+
+
+// addressBlock: umc_w_phy_umc0_umcch4_umcchdec
+// base address: 0x150000
+#define regUMCCH4_0_BaseAddrCS0 0x0000
+#define regUMCCH4_0_BaseAddrCS0_BASE_IDX 1
+#define regUMCCH4_0_AddrMaskCS01 0x0008
+#define regUMCCH4_0_AddrMaskCS01_BASE_IDX 1
+#define regUMCCH4_0_AddrSelCS01 0x0010
+#define regUMCCH4_0_AddrSelCS01_BASE_IDX 1
+#define regUMCCH4_0_AddrHashBank0 0x0032
+#define regUMCCH4_0_AddrHashBank0_BASE_IDX 1
+#define regUMCCH4_0_AddrHashBank1 0x0033
+#define regUMCCH4_0_AddrHashBank1_BASE_IDX 1
+#define regUMCCH4_0_AddrHashBank2 0x0034
+#define regUMCCH4_0_AddrHashBank2_BASE_IDX 1
+#define regUMCCH4_0_AddrHashBank3 0x0035
+#define regUMCCH4_0_AddrHashBank3_BASE_IDX 1
+#define regUMCCH4_0_AddrHashBank4 0x0036
+#define regUMCCH4_0_AddrHashBank4_BASE_IDX 1
+#define regUMCCH4_0_AddrHashBank5 0x0037
+#define regUMCCH4_0_AddrHashBank5_BASE_IDX 1
+#define regUMCCH4_0_EccErrCntSel 0x0328
+#define regUMCCH4_0_EccErrCntSel_BASE_IDX 1
+#define regUMCCH4_0_EccErrCnt 0x0329
+#define regUMCCH4_0_EccErrCnt_BASE_IDX 1
+#define regUMCCH4_0_PerfMonCtlClk 0x0340
+#define regUMCCH4_0_PerfMonCtlClk_BASE_IDX 1
+#define regUMCCH4_0_PerfMonCtrClk_Lo 0x0341
+#define regUMCCH4_0_PerfMonCtrClk_Lo_BASE_IDX 1
+#define regUMCCH4_0_PerfMonCtrClk_Hi 0x0342
+#define regUMCCH4_0_PerfMonCtrClk_Hi_BASE_IDX 1
+#define regUMCCH4_0_PerfMonCtl1 0x0344
+#define regUMCCH4_0_PerfMonCtl1_BASE_IDX 1
+#define regUMCCH4_0_PerfMonCtr1_Lo 0x0345
+#define regUMCCH4_0_PerfMonCtr1_Lo_BASE_IDX 1
+#define regUMCCH4_0_PerfMonCtr1_Hi 0x0346
+#define regUMCCH4_0_PerfMonCtr1_Hi_BASE_IDX 1
+#define regUMCCH4_0_PerfMonCtl2 0x0347
+#define regUMCCH4_0_PerfMonCtl2_BASE_IDX 1
+#define regUMCCH4_0_PerfMonCtr2_Lo 0x0348
+#define regUMCCH4_0_PerfMonCtr2_Lo_BASE_IDX 1
+#define regUMCCH4_0_PerfMonCtr2_Hi 0x0349
+#define regUMCCH4_0_PerfMonCtr2_Hi_BASE_IDX 1
+#define regUMCCH4_0_PerfMonCtl3 0x034a
+#define regUMCCH4_0_PerfMonCtl3_BASE_IDX 1
+#define regUMCCH4_0_PerfMonCtr3_Lo 0x034b
+#define regUMCCH4_0_PerfMonCtr3_Lo_BASE_IDX 1
+#define regUMCCH4_0_PerfMonCtr3_Hi 0x034c
+#define regUMCCH4_0_PerfMonCtr3_Hi_BASE_IDX 1
+#define regUMCCH4_0_PerfMonCtl4 0x034d
+#define regUMCCH4_0_PerfMonCtl4_BASE_IDX 1
+#define regUMCCH4_0_PerfMonCtr4_Lo 0x034e
+#define regUMCCH4_0_PerfMonCtr4_Lo_BASE_IDX 1
+#define regUMCCH4_0_PerfMonCtr4_Hi 0x034f
+#define regUMCCH4_0_PerfMonCtr4_Hi_BASE_IDX 1
+#define regUMCCH4_0_PerfMonCtl5 0x0350
+#define regUMCCH4_0_PerfMonCtl5_BASE_IDX 1
+#define regUMCCH4_0_PerfMonCtr5_Lo 0x0351
+#define regUMCCH4_0_PerfMonCtr5_Lo_BASE_IDX 1
+#define regUMCCH4_0_PerfMonCtr5_Hi 0x0352
+#define regUMCCH4_0_PerfMonCtr5_Hi_BASE_IDX 1
+#define regUMCCH4_0_PerfMonCtl6 0x0353
+#define regUMCCH4_0_PerfMonCtl6_BASE_IDX 1
+#define regUMCCH4_0_PerfMonCtr6_Lo 0x0354
+#define regUMCCH4_0_PerfMonCtr6_Lo_BASE_IDX 1
+#define regUMCCH4_0_PerfMonCtr6_Hi 0x0355
+#define regUMCCH4_0_PerfMonCtr6_Hi_BASE_IDX 1
+#define regUMCCH4_0_PerfMonCtl7 0x0356
+#define regUMCCH4_0_PerfMonCtl7_BASE_IDX 1
+#define regUMCCH4_0_PerfMonCtr7_Lo 0x0357
+#define regUMCCH4_0_PerfMonCtr7_Lo_BASE_IDX 1
+#define regUMCCH4_0_PerfMonCtr7_Hi 0x0358
+#define regUMCCH4_0_PerfMonCtr7_Hi_BASE_IDX 1
+#define regUMCCH4_0_PerfMonCtl8 0x0359
+#define regUMCCH4_0_PerfMonCtl8_BASE_IDX 1
+#define regUMCCH4_0_PerfMonCtr8_Lo 0x035a
+#define regUMCCH4_0_PerfMonCtr8_Lo_BASE_IDX 1
+#define regUMCCH4_0_PerfMonCtr8_Hi 0x035b
+#define regUMCCH4_0_PerfMonCtr8_Hi_BASE_IDX 1
+
+
+// addressBlock: umc_w_phy_umc0_umcch5_umcchdec
+// base address: 0x151000
+#define regUMCCH5_0_BaseAddrCS0 0x0400
+#define regUMCCH5_0_BaseAddrCS0_BASE_IDX 1
+#define regUMCCH5_0_AddrMaskCS01 0x0408
+#define regUMCCH5_0_AddrMaskCS01_BASE_IDX 1
+#define regUMCCH5_0_AddrSelCS01 0x0410
+#define regUMCCH5_0_AddrSelCS01_BASE_IDX 1
+#define regUMCCH5_0_AddrHashBank0 0x0432
+#define regUMCCH5_0_AddrHashBank0_BASE_IDX 1
+#define regUMCCH5_0_AddrHashBank1 0x0433
+#define regUMCCH5_0_AddrHashBank1_BASE_IDX 1
+#define regUMCCH5_0_AddrHashBank2 0x0434
+#define regUMCCH5_0_AddrHashBank2_BASE_IDX 1
+#define regUMCCH5_0_AddrHashBank3 0x0435
+#define regUMCCH5_0_AddrHashBank3_BASE_IDX 1
+#define regUMCCH5_0_AddrHashBank4 0x0436
+#define regUMCCH5_0_AddrHashBank4_BASE_IDX 1
+#define regUMCCH5_0_AddrHashBank5 0x0437
+#define regUMCCH5_0_AddrHashBank5_BASE_IDX 1
+#define regUMCCH5_0_EccErrCntSel 0x0728
+#define regUMCCH5_0_EccErrCntSel_BASE_IDX 1
+#define regUMCCH5_0_EccErrCnt 0x0729
+#define regUMCCH5_0_EccErrCnt_BASE_IDX 1
+#define regUMCCH5_0_PerfMonCtlClk 0x0740
+#define regUMCCH5_0_PerfMonCtlClk_BASE_IDX 1
+#define regUMCCH5_0_PerfMonCtrClk_Lo 0x0741
+#define regUMCCH5_0_PerfMonCtrClk_Lo_BASE_IDX 1
+#define regUMCCH5_0_PerfMonCtrClk_Hi 0x0742
+#define regUMCCH5_0_PerfMonCtrClk_Hi_BASE_IDX 1
+#define regUMCCH5_0_PerfMonCtl1 0x0744
+#define regUMCCH5_0_PerfMonCtl1_BASE_IDX 1
+#define regUMCCH5_0_PerfMonCtr1_Lo 0x0745
+#define regUMCCH5_0_PerfMonCtr1_Lo_BASE_IDX 1
+#define regUMCCH5_0_PerfMonCtr1_Hi 0x0746
+#define regUMCCH5_0_PerfMonCtr1_Hi_BASE_IDX 1
+#define regUMCCH5_0_PerfMonCtl2 0x0747
+#define regUMCCH5_0_PerfMonCtl2_BASE_IDX 1
+#define regUMCCH5_0_PerfMonCtr2_Lo 0x0748
+#define regUMCCH5_0_PerfMonCtr2_Lo_BASE_IDX 1
+#define regUMCCH5_0_PerfMonCtr2_Hi 0x0749
+#define regUMCCH5_0_PerfMonCtr2_Hi_BASE_IDX 1
+#define regUMCCH5_0_PerfMonCtl3 0x074a
+#define regUMCCH5_0_PerfMonCtl3_BASE_IDX 1
+#define regUMCCH5_0_PerfMonCtr3_Lo 0x074b
+#define regUMCCH5_0_PerfMonCtr3_Lo_BASE_IDX 1
+#define regUMCCH5_0_PerfMonCtr3_Hi 0x074c
+#define regUMCCH5_0_PerfMonCtr3_Hi_BASE_IDX 1
+#define regUMCCH5_0_PerfMonCtl4 0x074d
+#define regUMCCH5_0_PerfMonCtl4_BASE_IDX 1
+#define regUMCCH5_0_PerfMonCtr4_Lo 0x074e
+#define regUMCCH5_0_PerfMonCtr4_Lo_BASE_IDX 1
+#define regUMCCH5_0_PerfMonCtr4_Hi 0x074f
+#define regUMCCH5_0_PerfMonCtr4_Hi_BASE_IDX 1
+#define regUMCCH5_0_PerfMonCtl5 0x0750
+#define regUMCCH5_0_PerfMonCtl5_BASE_IDX 1
+#define regUMCCH5_0_PerfMonCtr5_Lo 0x0751
+#define regUMCCH5_0_PerfMonCtr5_Lo_BASE_IDX 1
+#define regUMCCH5_0_PerfMonCtr5_Hi 0x0752
+#define regUMCCH5_0_PerfMonCtr5_Hi_BASE_IDX 1
+#define regUMCCH5_0_PerfMonCtl6 0x0753
+#define regUMCCH5_0_PerfMonCtl6_BASE_IDX 1
+#define regUMCCH5_0_PerfMonCtr6_Lo 0x0754
+#define regUMCCH5_0_PerfMonCtr6_Lo_BASE_IDX 1
+#define regUMCCH5_0_PerfMonCtr6_Hi 0x0755
+#define regUMCCH5_0_PerfMonCtr6_Hi_BASE_IDX 1
+#define regUMCCH5_0_PerfMonCtl7 0x0756
+#define regUMCCH5_0_PerfMonCtl7_BASE_IDX 1
+#define regUMCCH5_0_PerfMonCtr7_Lo 0x0757
+#define regUMCCH5_0_PerfMonCtr7_Lo_BASE_IDX 1
+#define regUMCCH5_0_PerfMonCtr7_Hi 0x0758
+#define regUMCCH5_0_PerfMonCtr7_Hi_BASE_IDX 1
+#define regUMCCH5_0_PerfMonCtl8 0x0759
+#define regUMCCH5_0_PerfMonCtl8_BASE_IDX 1
+#define regUMCCH5_0_PerfMonCtr8_Lo 0x075a
+#define regUMCCH5_0_PerfMonCtr8_Lo_BASE_IDX 1
+#define regUMCCH5_0_PerfMonCtr8_Hi 0x075b
+#define regUMCCH5_0_PerfMonCtr8_Hi_BASE_IDX 1
+
+
+// addressBlock: umc_w_phy_umc0_umcch6_umcchdec
+// base address: 0x152000
+#define regUMCCH6_0_BaseAddrCS0 0x0800
+#define regUMCCH6_0_BaseAddrCS0_BASE_IDX 1
+#define regUMCCH6_0_AddrMaskCS01 0x0808
+#define regUMCCH6_0_AddrMaskCS01_BASE_IDX 1
+#define regUMCCH6_0_AddrSelCS01 0x0810
+#define regUMCCH6_0_AddrSelCS01_BASE_IDX 1
+#define regUMCCH6_0_AddrHashBank0 0x0832
+#define regUMCCH6_0_AddrHashBank0_BASE_IDX 1
+#define regUMCCH6_0_AddrHashBank1 0x0833
+#define regUMCCH6_0_AddrHashBank1_BASE_IDX 1
+#define regUMCCH6_0_AddrHashBank2 0x0834
+#define regUMCCH6_0_AddrHashBank2_BASE_IDX 1
+#define regUMCCH6_0_AddrHashBank3 0x0835
+#define regUMCCH6_0_AddrHashBank3_BASE_IDX 1
+#define regUMCCH6_0_AddrHashBank4 0x0836
+#define regUMCCH6_0_AddrHashBank4_BASE_IDX 1
+#define regUMCCH6_0_AddrHashBank5 0x0837
+#define regUMCCH6_0_AddrHashBank5_BASE_IDX 1
+#define regUMCCH6_0_EccErrCntSel 0x0b28
+#define regUMCCH6_0_EccErrCntSel_BASE_IDX 1
+#define regUMCCH6_0_EccErrCnt 0x0b29
+#define regUMCCH6_0_EccErrCnt_BASE_IDX 1
+#define regUMCCH6_0_PerfMonCtlClk 0x0b40
+#define regUMCCH6_0_PerfMonCtlClk_BASE_IDX 1
+#define regUMCCH6_0_PerfMonCtrClk_Lo 0x0b41
+#define regUMCCH6_0_PerfMonCtrClk_Lo_BASE_IDX 1
+#define regUMCCH6_0_PerfMonCtrClk_Hi 0x0b42
+#define regUMCCH6_0_PerfMonCtrClk_Hi_BASE_IDX 1
+#define regUMCCH6_0_PerfMonCtl1 0x0b44
+#define regUMCCH6_0_PerfMonCtl1_BASE_IDX 1
+#define regUMCCH6_0_PerfMonCtr1_Lo 0x0b45
+#define regUMCCH6_0_PerfMonCtr1_Lo_BASE_IDX 1
+#define regUMCCH6_0_PerfMonCtr1_Hi 0x0b46
+#define regUMCCH6_0_PerfMonCtr1_Hi_BASE_IDX 1
+#define regUMCCH6_0_PerfMonCtl2 0x0b47
+#define regUMCCH6_0_PerfMonCtl2_BASE_IDX 1
+#define regUMCCH6_0_PerfMonCtr2_Lo 0x0b48
+#define regUMCCH6_0_PerfMonCtr2_Lo_BASE_IDX 1
+#define regUMCCH6_0_PerfMonCtr2_Hi 0x0b49
+#define regUMCCH6_0_PerfMonCtr2_Hi_BASE_IDX 1
+#define regUMCCH6_0_PerfMonCtl3 0x0b4a
+#define regUMCCH6_0_PerfMonCtl3_BASE_IDX 1
+#define regUMCCH6_0_PerfMonCtr3_Lo 0x0b4b
+#define regUMCCH6_0_PerfMonCtr3_Lo_BASE_IDX 1
+#define regUMCCH6_0_PerfMonCtr3_Hi 0x0b4c
+#define regUMCCH6_0_PerfMonCtr3_Hi_BASE_IDX 1
+#define regUMCCH6_0_PerfMonCtl4 0x0b4d
+#define regUMCCH6_0_PerfMonCtl4_BASE_IDX 1
+#define regUMCCH6_0_PerfMonCtr4_Lo 0x0b4e
+#define regUMCCH6_0_PerfMonCtr4_Lo_BASE_IDX 1
+#define regUMCCH6_0_PerfMonCtr4_Hi 0x0b4f
+#define regUMCCH6_0_PerfMonCtr4_Hi_BASE_IDX 1
+#define regUMCCH6_0_PerfMonCtl5 0x0b50
+#define regUMCCH6_0_PerfMonCtl5_BASE_IDX 1
+#define regUMCCH6_0_PerfMonCtr5_Lo 0x0b51
+#define regUMCCH6_0_PerfMonCtr5_Lo_BASE_IDX 1
+#define regUMCCH6_0_PerfMonCtr5_Hi 0x0b52
+#define regUMCCH6_0_PerfMonCtr5_Hi_BASE_IDX 1
+#define regUMCCH6_0_PerfMonCtl6 0x0b53
+#define regUMCCH6_0_PerfMonCtl6_BASE_IDX 1
+#define regUMCCH6_0_PerfMonCtr6_Lo 0x0b54
+#define regUMCCH6_0_PerfMonCtr6_Lo_BASE_IDX 1
+#define regUMCCH6_0_PerfMonCtr6_Hi 0x0b55
+#define regUMCCH6_0_PerfMonCtr6_Hi_BASE_IDX 1
+#define regUMCCH6_0_PerfMonCtl7 0x0b56
+#define regUMCCH6_0_PerfMonCtl7_BASE_IDX 1
+#define regUMCCH6_0_PerfMonCtr7_Lo 0x0b57
+#define regUMCCH6_0_PerfMonCtr7_Lo_BASE_IDX 1
+#define regUMCCH6_0_PerfMonCtr7_Hi 0x0b58
+#define regUMCCH6_0_PerfMonCtr7_Hi_BASE_IDX 1
+#define regUMCCH6_0_PerfMonCtl8 0x0b59
+#define regUMCCH6_0_PerfMonCtl8_BASE_IDX 1
+#define regUMCCH6_0_PerfMonCtr8_Lo 0x0b5a
+#define regUMCCH6_0_PerfMonCtr8_Lo_BASE_IDX 1
+#define regUMCCH6_0_PerfMonCtr8_Hi 0x0b5b
+#define regUMCCH6_0_PerfMonCtr8_Hi_BASE_IDX 1
+
+
+// addressBlock: umc_w_phy_umc0_umcch7_umcchdec
+// base address: 0x153000
+#define regUMCCH7_0_BaseAddrCS0 0x0c00
+#define regUMCCH7_0_BaseAddrCS0_BASE_IDX 1
+#define regUMCCH7_0_AddrMaskCS01 0x0c08
+#define regUMCCH7_0_AddrMaskCS01_BASE_IDX 1
+#define regUMCCH7_0_AddrSelCS01 0x0c10
+#define regUMCCH7_0_AddrSelCS01_BASE_IDX 1
+#define regUMCCH7_0_AddrHashBank0 0x0c32
+#define regUMCCH7_0_AddrHashBank0_BASE_IDX 1
+#define regUMCCH7_0_AddrHashBank1 0x0c33
+#define regUMCCH7_0_AddrHashBank1_BASE_IDX 1
+#define regUMCCH7_0_AddrHashBank2 0x0c34
+#define regUMCCH7_0_AddrHashBank2_BASE_IDX 1
+#define regUMCCH7_0_AddrHashBank3 0x0c35
+#define regUMCCH7_0_AddrHashBank3_BASE_IDX 1
+#define regUMCCH7_0_AddrHashBank4 0x0c36
+#define regUMCCH7_0_AddrHashBank4_BASE_IDX 1
+#define regUMCCH7_0_AddrHashBank5 0x0c37
+#define regUMCCH7_0_AddrHashBank5_BASE_IDX 1
+#define regUMCCH7_0_EccErrCntSel 0x0f28
+#define regUMCCH7_0_EccErrCntSel_BASE_IDX 1
+#define regUMCCH7_0_EccErrCnt 0x0f29
+#define regUMCCH7_0_EccErrCnt_BASE_IDX 1
+#define regUMCCH7_0_PerfMonCtlClk 0x0f40
+#define regUMCCH7_0_PerfMonCtlClk_BASE_IDX 1
+#define regUMCCH7_0_PerfMonCtrClk_Lo 0x0f41
+#define regUMCCH7_0_PerfMonCtrClk_Lo_BASE_IDX 1
+#define regUMCCH7_0_PerfMonCtrClk_Hi 0x0f42
+#define regUMCCH7_0_PerfMonCtrClk_Hi_BASE_IDX 1
+#define regUMCCH7_0_PerfMonCtl1 0x0f44
+#define regUMCCH7_0_PerfMonCtl1_BASE_IDX 1
+#define regUMCCH7_0_PerfMonCtr1_Lo 0x0f45
+#define regUMCCH7_0_PerfMonCtr1_Lo_BASE_IDX 1
+#define regUMCCH7_0_PerfMonCtr1_Hi 0x0f46
+#define regUMCCH7_0_PerfMonCtr1_Hi_BASE_IDX 1
+#define regUMCCH7_0_PerfMonCtl2 0x0f47
+#define regUMCCH7_0_PerfMonCtl2_BASE_IDX 1
+#define regUMCCH7_0_PerfMonCtr2_Lo 0x0f48
+#define regUMCCH7_0_PerfMonCtr2_Lo_BASE_IDX 1
+#define regUMCCH7_0_PerfMonCtr2_Hi 0x0f49
+#define regUMCCH7_0_PerfMonCtr2_Hi_BASE_IDX 1
+#define regUMCCH7_0_PerfMonCtl3 0x0f4a
+#define regUMCCH7_0_PerfMonCtl3_BASE_IDX 1
+#define regUMCCH7_0_PerfMonCtr3_Lo 0x0f4b
+#define regUMCCH7_0_PerfMonCtr3_Lo_BASE_IDX 1
+#define regUMCCH7_0_PerfMonCtr3_Hi 0x0f4c
+#define regUMCCH7_0_PerfMonCtr3_Hi_BASE_IDX 1
+#define regUMCCH7_0_PerfMonCtl4 0x0f4d
+#define regUMCCH7_0_PerfMonCtl4_BASE_IDX 1
+#define regUMCCH7_0_PerfMonCtr4_Lo 0x0f4e
+#define regUMCCH7_0_PerfMonCtr4_Lo_BASE_IDX 1
+#define regUMCCH7_0_PerfMonCtr4_Hi 0x0f4f
+#define regUMCCH7_0_PerfMonCtr4_Hi_BASE_IDX 1
+#define regUMCCH7_0_PerfMonCtl5 0x0f50
+#define regUMCCH7_0_PerfMonCtl5_BASE_IDX 1
+#define regUMCCH7_0_PerfMonCtr5_Lo 0x0f51
+#define regUMCCH7_0_PerfMonCtr5_Lo_BASE_IDX 1
+#define regUMCCH7_0_PerfMonCtr5_Hi 0x0f52
+#define regUMCCH7_0_PerfMonCtr5_Hi_BASE_IDX 1
+#define regUMCCH7_0_PerfMonCtl6 0x0f53
+#define regUMCCH7_0_PerfMonCtl6_BASE_IDX 1
+#define regUMCCH7_0_PerfMonCtr6_Lo 0x0f54
+#define regUMCCH7_0_PerfMonCtr6_Lo_BASE_IDX 1
+#define regUMCCH7_0_PerfMonCtr6_Hi 0x0f55
+#define regUMCCH7_0_PerfMonCtr6_Hi_BASE_IDX 1
+#define regUMCCH7_0_PerfMonCtl7 0x0f56
+#define regUMCCH7_0_PerfMonCtl7_BASE_IDX 1
+#define regUMCCH7_0_PerfMonCtr7_Lo 0x0f57
+#define regUMCCH7_0_PerfMonCtr7_Lo_BASE_IDX 1
+#define regUMCCH7_0_PerfMonCtr7_Hi 0x0f58
+#define regUMCCH7_0_PerfMonCtr7_Hi_BASE_IDX 1
+#define regUMCCH7_0_PerfMonCtl8 0x0f59
+#define regUMCCH7_0_PerfMonCtl8_BASE_IDX 1
+#define regUMCCH7_0_PerfMonCtr8_Lo 0x0f5a
+#define regUMCCH7_0_PerfMonCtr8_Lo_BASE_IDX 1
+#define regUMCCH7_0_PerfMonCtr8_Hi 0x0f5b
+#define regUMCCH7_0_PerfMonCtr8_Hi_BASE_IDX 1
+
+
+// addressBlock: umc_w_phy_umc1_umcch0_umcchdec
+// base address: 0x250000
+#define regUMCCH0_1_BaseAddrCS0 0x40000
+#define regUMCCH0_1_BaseAddrCS0_BASE_IDX 1
+#define regUMCCH0_1_AddrMaskCS01 0x40008
+#define regUMCCH0_1_AddrMaskCS01_BASE_IDX 1
+#define regUMCCH0_1_AddrSelCS01 0x40010
+#define regUMCCH0_1_AddrSelCS01_BASE_IDX 1
+#define regUMCCH0_1_AddrHashBank0 0x40032
+#define regUMCCH0_1_AddrHashBank0_BASE_IDX 1
+#define regUMCCH0_1_AddrHashBank1 0x40033
+#define regUMCCH0_1_AddrHashBank1_BASE_IDX 1
+#define regUMCCH0_1_AddrHashBank2 0x40034
+#define regUMCCH0_1_AddrHashBank2_BASE_IDX 1
+#define regUMCCH0_1_AddrHashBank3 0x40035
+#define regUMCCH0_1_AddrHashBank3_BASE_IDX 1
+#define regUMCCH0_1_AddrHashBank4 0x40036
+#define regUMCCH0_1_AddrHashBank4_BASE_IDX 1
+#define regUMCCH0_1_AddrHashBank5 0x40037
+#define regUMCCH0_1_AddrHashBank5_BASE_IDX 1
+#define regUMCCH0_1_EccErrCntSel 0x40328
+#define regUMCCH0_1_EccErrCntSel_BASE_IDX 1
+#define regUMCCH0_1_EccErrCnt 0x40329
+#define regUMCCH0_1_EccErrCnt_BASE_IDX 1
+#define regUMCCH0_1_PerfMonCtlClk 0x40340
+#define regUMCCH0_1_PerfMonCtlClk_BASE_IDX 1
+#define regUMCCH0_1_PerfMonCtrClk_Lo 0x40341
+#define regUMCCH0_1_PerfMonCtrClk_Lo_BASE_IDX 1
+#define regUMCCH0_1_PerfMonCtrClk_Hi 0x40342
+#define regUMCCH0_1_PerfMonCtrClk_Hi_BASE_IDX 1
+#define regUMCCH0_1_PerfMonCtl1 0x40344
+#define regUMCCH0_1_PerfMonCtl1_BASE_IDX 1
+#define regUMCCH0_1_PerfMonCtr1_Lo 0x40345
+#define regUMCCH0_1_PerfMonCtr1_Lo_BASE_IDX 1
+#define regUMCCH0_1_PerfMonCtr1_Hi 0x40346
+#define regUMCCH0_1_PerfMonCtr1_Hi_BASE_IDX 1
+#define regUMCCH0_1_PerfMonCtl2 0x40347
+#define regUMCCH0_1_PerfMonCtl2_BASE_IDX 1
+#define regUMCCH0_1_PerfMonCtr2_Lo 0x40348
+#define regUMCCH0_1_PerfMonCtr2_Lo_BASE_IDX 1
+#define regUMCCH0_1_PerfMonCtr2_Hi 0x40349
+#define regUMCCH0_1_PerfMonCtr2_Hi_BASE_IDX 1
+#define regUMCCH0_1_PerfMonCtl3 0x4034a
+#define regUMCCH0_1_PerfMonCtl3_BASE_IDX 1
+#define regUMCCH0_1_PerfMonCtr3_Lo 0x4034b
+#define regUMCCH0_1_PerfMonCtr3_Lo_BASE_IDX 1
+#define regUMCCH0_1_PerfMonCtr3_Hi 0x4034c
+#define regUMCCH0_1_PerfMonCtr3_Hi_BASE_IDX 1
+#define regUMCCH0_1_PerfMonCtl4 0x4034d
+#define regUMCCH0_1_PerfMonCtl4_BASE_IDX 1
+#define regUMCCH0_1_PerfMonCtr4_Lo 0x4034e
+#define regUMCCH0_1_PerfMonCtr4_Lo_BASE_IDX 1
+#define regUMCCH0_1_PerfMonCtr4_Hi 0x4034f
+#define regUMCCH0_1_PerfMonCtr4_Hi_BASE_IDX 1
+#define regUMCCH0_1_PerfMonCtl5 0x40350
+#define regUMCCH0_1_PerfMonCtl5_BASE_IDX 1
+#define regUMCCH0_1_PerfMonCtr5_Lo 0x40351
+#define regUMCCH0_1_PerfMonCtr5_Lo_BASE_IDX 1
+#define regUMCCH0_1_PerfMonCtr5_Hi 0x40352
+#define regUMCCH0_1_PerfMonCtr5_Hi_BASE_IDX 1
+#define regUMCCH0_1_PerfMonCtl6 0x40353
+#define regUMCCH0_1_PerfMonCtl6_BASE_IDX 1
+#define regUMCCH0_1_PerfMonCtr6_Lo 0x40354
+#define regUMCCH0_1_PerfMonCtr6_Lo_BASE_IDX 1
+#define regUMCCH0_1_PerfMonCtr6_Hi 0x40355
+#define regUMCCH0_1_PerfMonCtr6_Hi_BASE_IDX 1
+#define regUMCCH0_1_PerfMonCtl7 0x40356
+#define regUMCCH0_1_PerfMonCtl7_BASE_IDX 1
+#define regUMCCH0_1_PerfMonCtr7_Lo 0x40357
+#define regUMCCH0_1_PerfMonCtr7_Lo_BASE_IDX 1
+#define regUMCCH0_1_PerfMonCtr7_Hi 0x40358
+#define regUMCCH0_1_PerfMonCtr7_Hi_BASE_IDX 1
+#define regUMCCH0_1_PerfMonCtl8 0x40359
+#define regUMCCH0_1_PerfMonCtl8_BASE_IDX 1
+#define regUMCCH0_1_PerfMonCtr8_Lo 0x4035a
+#define regUMCCH0_1_PerfMonCtr8_Lo_BASE_IDX 1
+#define regUMCCH0_1_PerfMonCtr8_Hi 0x4035b
+#define regUMCCH0_1_PerfMonCtr8_Hi_BASE_IDX 1
+
+
+// addressBlock: umc_w_phy_umc1_umcch1_umcchdec
+// base address: 0x251000
+#define regUMCCH1_1_BaseAddrCS0 0x40400
+#define regUMCCH1_1_BaseAddrCS0_BASE_IDX 1
+#define regUMCCH1_1_AddrMaskCS01 0x40408
+#define regUMCCH1_1_AddrMaskCS01_BASE_IDX 1
+#define regUMCCH1_1_AddrSelCS01 0x40410
+#define regUMCCH1_1_AddrSelCS01_BASE_IDX 1
+#define regUMCCH1_1_AddrHashBank0 0x40432
+#define regUMCCH1_1_AddrHashBank0_BASE_IDX 1
+#define regUMCCH1_1_AddrHashBank1 0x40433
+#define regUMCCH1_1_AddrHashBank1_BASE_IDX 1
+#define regUMCCH1_1_AddrHashBank2 0x40434
+#define regUMCCH1_1_AddrHashBank2_BASE_IDX 1
+#define regUMCCH1_1_AddrHashBank3 0x40435
+#define regUMCCH1_1_AddrHashBank3_BASE_IDX 1
+#define regUMCCH1_1_AddrHashBank4 0x40436
+#define regUMCCH1_1_AddrHashBank4_BASE_IDX 1
+#define regUMCCH1_1_AddrHashBank5 0x40437
+#define regUMCCH1_1_AddrHashBank5_BASE_IDX 1
+#define regUMCCH1_1_EccErrCntSel 0x40728
+#define regUMCCH1_1_EccErrCntSel_BASE_IDX 1
+#define regUMCCH1_1_EccErrCnt 0x40729
+#define regUMCCH1_1_EccErrCnt_BASE_IDX 1
+#define regUMCCH1_1_PerfMonCtlClk 0x40740
+#define regUMCCH1_1_PerfMonCtlClk_BASE_IDX 1
+#define regUMCCH1_1_PerfMonCtrClk_Lo 0x40741
+#define regUMCCH1_1_PerfMonCtrClk_Lo_BASE_IDX 1
+#define regUMCCH1_1_PerfMonCtrClk_Hi 0x40742
+#define regUMCCH1_1_PerfMonCtrClk_Hi_BASE_IDX 1
+#define regUMCCH1_1_PerfMonCtl1 0x40744
+#define regUMCCH1_1_PerfMonCtl1_BASE_IDX 1
+#define regUMCCH1_1_PerfMonCtr1_Lo 0x40745
+#define regUMCCH1_1_PerfMonCtr1_Lo_BASE_IDX 1
+#define regUMCCH1_1_PerfMonCtr1_Hi 0x40746
+#define regUMCCH1_1_PerfMonCtr1_Hi_BASE_IDX 1
+#define regUMCCH1_1_PerfMonCtl2 0x40747
+#define regUMCCH1_1_PerfMonCtl2_BASE_IDX 1
+#define regUMCCH1_1_PerfMonCtr2_Lo 0x40748
+#define regUMCCH1_1_PerfMonCtr2_Lo_BASE_IDX 1
+#define regUMCCH1_1_PerfMonCtr2_Hi 0x40749
+#define regUMCCH1_1_PerfMonCtr2_Hi_BASE_IDX 1
+#define regUMCCH1_1_PerfMonCtl3 0x4074a
+#define regUMCCH1_1_PerfMonCtl3_BASE_IDX 1
+#define regUMCCH1_1_PerfMonCtr3_Lo 0x4074b
+#define regUMCCH1_1_PerfMonCtr3_Lo_BASE_IDX 1
+#define regUMCCH1_1_PerfMonCtr3_Hi 0x4074c
+#define regUMCCH1_1_PerfMonCtr3_Hi_BASE_IDX 1
+#define regUMCCH1_1_PerfMonCtl4 0x4074d
+#define regUMCCH1_1_PerfMonCtl4_BASE_IDX 1
+#define regUMCCH1_1_PerfMonCtr4_Lo 0x4074e
+#define regUMCCH1_1_PerfMonCtr4_Lo_BASE_IDX 1
+#define regUMCCH1_1_PerfMonCtr4_Hi 0x4074f
+#define regUMCCH1_1_PerfMonCtr4_Hi_BASE_IDX 1
+#define regUMCCH1_1_PerfMonCtl5 0x40750
+#define regUMCCH1_1_PerfMonCtl5_BASE_IDX 1
+#define regUMCCH1_1_PerfMonCtr5_Lo 0x40751
+#define regUMCCH1_1_PerfMonCtr5_Lo_BASE_IDX 1
+#define regUMCCH1_1_PerfMonCtr5_Hi 0x40752
+#define regUMCCH1_1_PerfMonCtr5_Hi_BASE_IDX 1
+#define regUMCCH1_1_PerfMonCtl6 0x40753
+#define regUMCCH1_1_PerfMonCtl6_BASE_IDX 1
+#define regUMCCH1_1_PerfMonCtr6_Lo 0x40754
+#define regUMCCH1_1_PerfMonCtr6_Lo_BASE_IDX 1
+#define regUMCCH1_1_PerfMonCtr6_Hi 0x40755
+#define regUMCCH1_1_PerfMonCtr6_Hi_BASE_IDX 1
+#define regUMCCH1_1_PerfMonCtl7 0x40756
+#define regUMCCH1_1_PerfMonCtl7_BASE_IDX 1
+#define regUMCCH1_1_PerfMonCtr7_Lo 0x40757
+#define regUMCCH1_1_PerfMonCtr7_Lo_BASE_IDX 1
+#define regUMCCH1_1_PerfMonCtr7_Hi 0x40758
+#define regUMCCH1_1_PerfMonCtr7_Hi_BASE_IDX 1
+#define regUMCCH1_1_PerfMonCtl8 0x40759
+#define regUMCCH1_1_PerfMonCtl8_BASE_IDX 1
+#define regUMCCH1_1_PerfMonCtr8_Lo 0x4075a
+#define regUMCCH1_1_PerfMonCtr8_Lo_BASE_IDX 1
+#define regUMCCH1_1_PerfMonCtr8_Hi 0x4075b
+#define regUMCCH1_1_PerfMonCtr8_Hi_BASE_IDX 1
+
+
+// addressBlock: umc_w_phy_umc1_umcch2_umcchdec
+// base address: 0x252000
+#define regUMCCH2_1_BaseAddrCS0 0x40800
+#define regUMCCH2_1_BaseAddrCS0_BASE_IDX 1
+#define regUMCCH2_1_AddrMaskCS01 0x40808
+#define regUMCCH2_1_AddrMaskCS01_BASE_IDX 1
+#define regUMCCH2_1_AddrSelCS01 0x40810
+#define regUMCCH2_1_AddrSelCS01_BASE_IDX 1
+#define regUMCCH2_1_AddrHashBank0 0x40832
+#define regUMCCH2_1_AddrHashBank0_BASE_IDX 1
+#define regUMCCH2_1_AddrHashBank1 0x40833
+#define regUMCCH2_1_AddrHashBank1_BASE_IDX 1
+#define regUMCCH2_1_AddrHashBank2 0x40834
+#define regUMCCH2_1_AddrHashBank2_BASE_IDX 1
+#define regUMCCH2_1_AddrHashBank3 0x40835
+#define regUMCCH2_1_AddrHashBank3_BASE_IDX 1
+#define regUMCCH2_1_AddrHashBank4 0x40836
+#define regUMCCH2_1_AddrHashBank4_BASE_IDX 1
+#define regUMCCH2_1_AddrHashBank5 0x40837
+#define regUMCCH2_1_AddrHashBank5_BASE_IDX 1
+#define regUMCCH2_1_EccErrCntSel 0x40b28
+#define regUMCCH2_1_EccErrCntSel_BASE_IDX 1
+#define regUMCCH2_1_EccErrCnt 0x40b29
+#define regUMCCH2_1_EccErrCnt_BASE_IDX 1
+#define regUMCCH2_1_PerfMonCtlClk 0x40b40
+#define regUMCCH2_1_PerfMonCtlClk_BASE_IDX 1
+#define regUMCCH2_1_PerfMonCtrClk_Lo 0x40b41
+#define regUMCCH2_1_PerfMonCtrClk_Lo_BASE_IDX 1
+#define regUMCCH2_1_PerfMonCtrClk_Hi 0x40b42
+#define regUMCCH2_1_PerfMonCtrClk_Hi_BASE_IDX 1
+#define regUMCCH2_1_PerfMonCtl1 0x40b44
+#define regUMCCH2_1_PerfMonCtl1_BASE_IDX 1
+#define regUMCCH2_1_PerfMonCtr1_Lo 0x40b45
+#define regUMCCH2_1_PerfMonCtr1_Lo_BASE_IDX 1
+#define regUMCCH2_1_PerfMonCtr1_Hi 0x40b46
+#define regUMCCH2_1_PerfMonCtr1_Hi_BASE_IDX 1
+#define regUMCCH2_1_PerfMonCtl2 0x40b47
+#define regUMCCH2_1_PerfMonCtl2_BASE_IDX 1
+#define regUMCCH2_1_PerfMonCtr2_Lo 0x40b48
+#define regUMCCH2_1_PerfMonCtr2_Lo_BASE_IDX 1
+#define regUMCCH2_1_PerfMonCtr2_Hi 0x40b49
+#define regUMCCH2_1_PerfMonCtr2_Hi_BASE_IDX 1
+#define regUMCCH2_1_PerfMonCtl3 0x40b4a
+#define regUMCCH2_1_PerfMonCtl3_BASE_IDX 1
+#define regUMCCH2_1_PerfMonCtr3_Lo 0x40b4b
+#define regUMCCH2_1_PerfMonCtr3_Lo_BASE_IDX 1
+#define regUMCCH2_1_PerfMonCtr3_Hi 0x40b4c
+#define regUMCCH2_1_PerfMonCtr3_Hi_BASE_IDX 1
+#define regUMCCH2_1_PerfMonCtl4 0x40b4d
+#define regUMCCH2_1_PerfMonCtl4_BASE_IDX 1
+#define regUMCCH2_1_PerfMonCtr4_Lo 0x40b4e
+#define regUMCCH2_1_PerfMonCtr4_Lo_BASE_IDX 1
+#define regUMCCH2_1_PerfMonCtr4_Hi 0x40b4f
+#define regUMCCH2_1_PerfMonCtr4_Hi_BASE_IDX 1
+#define regUMCCH2_1_PerfMonCtl5 0x40b50
+#define regUMCCH2_1_PerfMonCtl5_BASE_IDX 1
+#define regUMCCH2_1_PerfMonCtr5_Lo 0x40b51
+#define regUMCCH2_1_PerfMonCtr5_Lo_BASE_IDX 1
+#define regUMCCH2_1_PerfMonCtr5_Hi 0x40b52
+#define regUMCCH2_1_PerfMonCtr5_Hi_BASE_IDX 1
+#define regUMCCH2_1_PerfMonCtl6 0x40b53
+#define regUMCCH2_1_PerfMonCtl6_BASE_IDX 1
+#define regUMCCH2_1_PerfMonCtr6_Lo 0x40b54
+#define regUMCCH2_1_PerfMonCtr6_Lo_BASE_IDX 1
+#define regUMCCH2_1_PerfMonCtr6_Hi 0x40b55
+#define regUMCCH2_1_PerfMonCtr6_Hi_BASE_IDX 1
+#define regUMCCH2_1_PerfMonCtl7 0x40b56
+#define regUMCCH2_1_PerfMonCtl7_BASE_IDX 1
+#define regUMCCH2_1_PerfMonCtr7_Lo 0x40b57
+#define regUMCCH2_1_PerfMonCtr7_Lo_BASE_IDX 1
+#define regUMCCH2_1_PerfMonCtr7_Hi 0x40b58
+#define regUMCCH2_1_PerfMonCtr7_Hi_BASE_IDX 1
+#define regUMCCH2_1_PerfMonCtl8 0x40b59
+#define regUMCCH2_1_PerfMonCtl8_BASE_IDX 1
+#define regUMCCH2_1_PerfMonCtr8_Lo 0x40b5a
+#define regUMCCH2_1_PerfMonCtr8_Lo_BASE_IDX 1
+#define regUMCCH2_1_PerfMonCtr8_Hi 0x40b5b
+#define regUMCCH2_1_PerfMonCtr8_Hi_BASE_IDX 1
+
+
+// addressBlock: umc_w_phy_umc1_umcch3_umcchdec
+// base address: 0x253000
+#define regUMCCH3_1_BaseAddrCS0 0x40c00
+#define regUMCCH3_1_BaseAddrCS0_BASE_IDX 1
+#define regUMCCH3_1_AddrMaskCS01 0x40c08
+#define regUMCCH3_1_AddrMaskCS01_BASE_IDX 1
+#define regUMCCH3_1_AddrSelCS01 0x40c10
+#define regUMCCH3_1_AddrSelCS01_BASE_IDX 1
+#define regUMCCH3_1_AddrHashBank0 0x40c32
+#define regUMCCH3_1_AddrHashBank0_BASE_IDX 1
+#define regUMCCH3_1_AddrHashBank1 0x40c33
+#define regUMCCH3_1_AddrHashBank1_BASE_IDX 1
+#define regUMCCH3_1_AddrHashBank2 0x40c34
+#define regUMCCH3_1_AddrHashBank2_BASE_IDX 1
+#define regUMCCH3_1_AddrHashBank3 0x40c35
+#define regUMCCH3_1_AddrHashBank3_BASE_IDX 1
+#define regUMCCH3_1_AddrHashBank4 0x40c36
+#define regUMCCH3_1_AddrHashBank4_BASE_IDX 1
+#define regUMCCH3_1_AddrHashBank5 0x40c37
+#define regUMCCH3_1_AddrHashBank5_BASE_IDX 1
+#define regUMCCH3_1_EccErrCntSel 0x40f28
+#define regUMCCH3_1_EccErrCntSel_BASE_IDX 1
+#define regUMCCH3_1_EccErrCnt 0x40f29
+#define regUMCCH3_1_EccErrCnt_BASE_IDX 1
+#define regUMCCH3_1_PerfMonCtlClk 0x40f40
+#define regUMCCH3_1_PerfMonCtlClk_BASE_IDX 1
+#define regUMCCH3_1_PerfMonCtrClk_Lo 0x40f41
+#define regUMCCH3_1_PerfMonCtrClk_Lo_BASE_IDX 1
+#define regUMCCH3_1_PerfMonCtrClk_Hi 0x40f42
+#define regUMCCH3_1_PerfMonCtrClk_Hi_BASE_IDX 1
+#define regUMCCH3_1_PerfMonCtl1 0x40f44
+#define regUMCCH3_1_PerfMonCtl1_BASE_IDX 1
+#define regUMCCH3_1_PerfMonCtr1_Lo 0x40f45
+#define regUMCCH3_1_PerfMonCtr1_Lo_BASE_IDX 1
+#define regUMCCH3_1_PerfMonCtr1_Hi 0x40f46
+#define regUMCCH3_1_PerfMonCtr1_Hi_BASE_IDX 1
+#define regUMCCH3_1_PerfMonCtl2 0x40f47
+#define regUMCCH3_1_PerfMonCtl2_BASE_IDX 1
+#define regUMCCH3_1_PerfMonCtr2_Lo 0x40f48
+#define regUMCCH3_1_PerfMonCtr2_Lo_BASE_IDX 1
+#define regUMCCH3_1_PerfMonCtr2_Hi 0x40f49
+#define regUMCCH3_1_PerfMonCtr2_Hi_BASE_IDX 1
+#define regUMCCH3_1_PerfMonCtl3 0x40f4a
+#define regUMCCH3_1_PerfMonCtl3_BASE_IDX 1
+#define regUMCCH3_1_PerfMonCtr3_Lo 0x40f4b
+#define regUMCCH3_1_PerfMonCtr3_Lo_BASE_IDX 1
+#define regUMCCH3_1_PerfMonCtr3_Hi 0x40f4c
+#define regUMCCH3_1_PerfMonCtr3_Hi_BASE_IDX 1
+#define regUMCCH3_1_PerfMonCtl4 0x40f4d
+#define regUMCCH3_1_PerfMonCtl4_BASE_IDX 1
+#define regUMCCH3_1_PerfMonCtr4_Lo 0x40f4e
+#define regUMCCH3_1_PerfMonCtr4_Lo_BASE_IDX 1
+#define regUMCCH3_1_PerfMonCtr4_Hi 0x40f4f
+#define regUMCCH3_1_PerfMonCtr4_Hi_BASE_IDX 1
+#define regUMCCH3_1_PerfMonCtl5 0x40f50
+#define regUMCCH3_1_PerfMonCtl5_BASE_IDX 1
+#define regUMCCH3_1_PerfMonCtr5_Lo 0x40f51
+#define regUMCCH3_1_PerfMonCtr5_Lo_BASE_IDX 1
+#define regUMCCH3_1_PerfMonCtr5_Hi 0x40f52
+#define regUMCCH3_1_PerfMonCtr5_Hi_BASE_IDX 1
+#define regUMCCH3_1_PerfMonCtl6 0x40f53
+#define regUMCCH3_1_PerfMonCtl6_BASE_IDX 1
+#define regUMCCH3_1_PerfMonCtr6_Lo 0x40f54
+#define regUMCCH3_1_PerfMonCtr6_Lo_BASE_IDX 1
+#define regUMCCH3_1_PerfMonCtr6_Hi 0x40f55
+#define regUMCCH3_1_PerfMonCtr6_Hi_BASE_IDX 1
+#define regUMCCH3_1_PerfMonCtl7 0x40f56
+#define regUMCCH3_1_PerfMonCtl7_BASE_IDX 1
+#define regUMCCH3_1_PerfMonCtr7_Lo 0x40f57
+#define regUMCCH3_1_PerfMonCtr7_Lo_BASE_IDX 1
+#define regUMCCH3_1_PerfMonCtr7_Hi 0x40f58
+#define regUMCCH3_1_PerfMonCtr7_Hi_BASE_IDX 1
+#define regUMCCH3_1_PerfMonCtl8 0x40f59
+#define regUMCCH3_1_PerfMonCtl8_BASE_IDX 1
+#define regUMCCH3_1_PerfMonCtr8_Lo 0x40f5a
+#define regUMCCH3_1_PerfMonCtr8_Lo_BASE_IDX 1
+#define regUMCCH3_1_PerfMonCtr8_Hi 0x40f5b
+#define regUMCCH3_1_PerfMonCtr8_Hi_BASE_IDX 1
+
+
+// addressBlock: umc_w_phy_umc1_umcch4_umcchdec
+// base address: 0x350000
+#define regUMCCH4_1_BaseAddrCS0 0x80000
+#define regUMCCH4_1_BaseAddrCS0_BASE_IDX 1
+#define regUMCCH4_1_AddrMaskCS01 0x80008
+#define regUMCCH4_1_AddrMaskCS01_BASE_IDX 1
+#define regUMCCH4_1_AddrSelCS01 0x80010
+#define regUMCCH4_1_AddrSelCS01_BASE_IDX 1
+#define regUMCCH4_1_AddrHashBank0 0x80032
+#define regUMCCH4_1_AddrHashBank0_BASE_IDX 1
+#define regUMCCH4_1_AddrHashBank1 0x80033
+#define regUMCCH4_1_AddrHashBank1_BASE_IDX 1
+#define regUMCCH4_1_AddrHashBank2 0x80034
+#define regUMCCH4_1_AddrHashBank2_BASE_IDX 1
+#define regUMCCH4_1_AddrHashBank3 0x80035
+#define regUMCCH4_1_AddrHashBank3_BASE_IDX 1
+#define regUMCCH4_1_AddrHashBank4 0x80036
+#define regUMCCH4_1_AddrHashBank4_BASE_IDX 1
+#define regUMCCH4_1_AddrHashBank5 0x80037
+#define regUMCCH4_1_AddrHashBank5_BASE_IDX 1
+#define regUMCCH4_1_EccErrCntSel 0x80328
+#define regUMCCH4_1_EccErrCntSel_BASE_IDX 1
+#define regUMCCH4_1_EccErrCnt 0x80329
+#define regUMCCH4_1_EccErrCnt_BASE_IDX 1
+#define regUMCCH4_1_PerfMonCtlClk 0x80340
+#define regUMCCH4_1_PerfMonCtlClk_BASE_IDX 1
+#define regUMCCH4_1_PerfMonCtrClk_Lo 0x80341
+#define regUMCCH4_1_PerfMonCtrClk_Lo_BASE_IDX 1
+#define regUMCCH4_1_PerfMonCtrClk_Hi 0x80342
+#define regUMCCH4_1_PerfMonCtrClk_Hi_BASE_IDX 1
+#define regUMCCH4_1_PerfMonCtl1 0x80344
+#define regUMCCH4_1_PerfMonCtl1_BASE_IDX 1
+#define regUMCCH4_1_PerfMonCtr1_Lo 0x80345
+#define regUMCCH4_1_PerfMonCtr1_Lo_BASE_IDX 1
+#define regUMCCH4_1_PerfMonCtr1_Hi 0x80346
+#define regUMCCH4_1_PerfMonCtr1_Hi_BASE_IDX 1
+#define regUMCCH4_1_PerfMonCtl2 0x80347
+#define regUMCCH4_1_PerfMonCtl2_BASE_IDX 1
+#define regUMCCH4_1_PerfMonCtr2_Lo 0x80348
+#define regUMCCH4_1_PerfMonCtr2_Lo_BASE_IDX 1
+#define regUMCCH4_1_PerfMonCtr2_Hi 0x80349
+#define regUMCCH4_1_PerfMonCtr2_Hi_BASE_IDX 1
+#define regUMCCH4_1_PerfMonCtl3 0x8034a
+#define regUMCCH4_1_PerfMonCtl3_BASE_IDX 1
+#define regUMCCH4_1_PerfMonCtr3_Lo 0x8034b
+#define regUMCCH4_1_PerfMonCtr3_Lo_BASE_IDX 1
+#define regUMCCH4_1_PerfMonCtr3_Hi 0x8034c
+#define regUMCCH4_1_PerfMonCtr3_Hi_BASE_IDX 1
+#define regUMCCH4_1_PerfMonCtl4 0x8034d
+#define regUMCCH4_1_PerfMonCtl4_BASE_IDX 1
+#define regUMCCH4_1_PerfMonCtr4_Lo 0x8034e
+#define regUMCCH4_1_PerfMonCtr4_Lo_BASE_IDX 1
+#define regUMCCH4_1_PerfMonCtr4_Hi 0x8034f
+#define regUMCCH4_1_PerfMonCtr4_Hi_BASE_IDX 1
+#define regUMCCH4_1_PerfMonCtl5 0x80350
+#define regUMCCH4_1_PerfMonCtl5_BASE_IDX 1
+#define regUMCCH4_1_PerfMonCtr5_Lo 0x80351
+#define regUMCCH4_1_PerfMonCtr5_Lo_BASE_IDX 1
+#define regUMCCH4_1_PerfMonCtr5_Hi 0x80352
+#define regUMCCH4_1_PerfMonCtr5_Hi_BASE_IDX 1
+#define regUMCCH4_1_PerfMonCtl6 0x80353
+#define regUMCCH4_1_PerfMonCtl6_BASE_IDX 1
+#define regUMCCH4_1_PerfMonCtr6_Lo 0x80354
+#define regUMCCH4_1_PerfMonCtr6_Lo_BASE_IDX 1
+#define regUMCCH4_1_PerfMonCtr6_Hi 0x80355
+#define regUMCCH4_1_PerfMonCtr6_Hi_BASE_IDX 1
+#define regUMCCH4_1_PerfMonCtl7 0x80356
+#define regUMCCH4_1_PerfMonCtl7_BASE_IDX 1
+#define regUMCCH4_1_PerfMonCtr7_Lo 0x80357
+#define regUMCCH4_1_PerfMonCtr7_Lo_BASE_IDX 1
+#define regUMCCH4_1_PerfMonCtr7_Hi 0x80358
+#define regUMCCH4_1_PerfMonCtr7_Hi_BASE_IDX 1
+#define regUMCCH4_1_PerfMonCtl8 0x80359
+#define regUMCCH4_1_PerfMonCtl8_BASE_IDX 1
+#define regUMCCH4_1_PerfMonCtr8_Lo 0x8035a
+#define regUMCCH4_1_PerfMonCtr8_Lo_BASE_IDX 1
+#define regUMCCH4_1_PerfMonCtr8_Hi 0x8035b
+#define regUMCCH4_1_PerfMonCtr8_Hi_BASE_IDX 1
+
+
+// addressBlock: umc_w_phy_umc1_umcch5_umcchdec
+// base address: 0x351000
+#define regUMCCH5_1_BaseAddrCS0 0x80400
+#define regUMCCH5_1_BaseAddrCS0_BASE_IDX 1
+#define regUMCCH5_1_AddrMaskCS01 0x80408
+#define regUMCCH5_1_AddrMaskCS01_BASE_IDX 1
+#define regUMCCH5_1_AddrSelCS01 0x80410
+#define regUMCCH5_1_AddrSelCS01_BASE_IDX 1
+#define regUMCCH5_1_AddrHashBank0 0x80432
+#define regUMCCH5_1_AddrHashBank0_BASE_IDX 1
+#define regUMCCH5_1_AddrHashBank1 0x80433
+#define regUMCCH5_1_AddrHashBank1_BASE_IDX 1
+#define regUMCCH5_1_AddrHashBank2 0x80434
+#define regUMCCH5_1_AddrHashBank2_BASE_IDX 1
+#define regUMCCH5_1_AddrHashBank3 0x80435
+#define regUMCCH5_1_AddrHashBank3_BASE_IDX 1
+#define regUMCCH5_1_AddrHashBank4 0x80436
+#define regUMCCH5_1_AddrHashBank4_BASE_IDX 1
+#define regUMCCH5_1_AddrHashBank5 0x80437
+#define regUMCCH5_1_AddrHashBank5_BASE_IDX 1
+#define regUMCCH5_1_EccErrCntSel 0x80728
+#define regUMCCH5_1_EccErrCntSel_BASE_IDX 1
+#define regUMCCH5_1_EccErrCnt 0x80729
+#define regUMCCH5_1_EccErrCnt_BASE_IDX 1
+#define regUMCCH5_1_PerfMonCtlClk 0x80740
+#define regUMCCH5_1_PerfMonCtlClk_BASE_IDX 1
+#define regUMCCH5_1_PerfMonCtrClk_Lo 0x80741
+#define regUMCCH5_1_PerfMonCtrClk_Lo_BASE_IDX 1
+#define regUMCCH5_1_PerfMonCtrClk_Hi 0x80742
+#define regUMCCH5_1_PerfMonCtrClk_Hi_BASE_IDX 1
+#define regUMCCH5_1_PerfMonCtl1 0x80744
+#define regUMCCH5_1_PerfMonCtl1_BASE_IDX 1
+#define regUMCCH5_1_PerfMonCtr1_Lo 0x80745
+#define regUMCCH5_1_PerfMonCtr1_Lo_BASE_IDX 1
+#define regUMCCH5_1_PerfMonCtr1_Hi 0x80746
+#define regUMCCH5_1_PerfMonCtr1_Hi_BASE_IDX 1
+#define regUMCCH5_1_PerfMonCtl2 0x80747
+#define regUMCCH5_1_PerfMonCtl2_BASE_IDX 1
+#define regUMCCH5_1_PerfMonCtr2_Lo 0x80748
+#define regUMCCH5_1_PerfMonCtr2_Lo_BASE_IDX 1
+#define regUMCCH5_1_PerfMonCtr2_Hi 0x80749
+#define regUMCCH5_1_PerfMonCtr2_Hi_BASE_IDX 1
+#define regUMCCH5_1_PerfMonCtl3 0x8074a
+#define regUMCCH5_1_PerfMonCtl3_BASE_IDX 1
+#define regUMCCH5_1_PerfMonCtr3_Lo 0x8074b
+#define regUMCCH5_1_PerfMonCtr3_Lo_BASE_IDX 1
+#define regUMCCH5_1_PerfMonCtr3_Hi 0x8074c
+#define regUMCCH5_1_PerfMonCtr3_Hi_BASE_IDX 1
+#define regUMCCH5_1_PerfMonCtl4 0x8074d
+#define regUMCCH5_1_PerfMonCtl4_BASE_IDX 1
+#define regUMCCH5_1_PerfMonCtr4_Lo 0x8074e
+#define regUMCCH5_1_PerfMonCtr4_Lo_BASE_IDX 1
+#define regUMCCH5_1_PerfMonCtr4_Hi 0x8074f
+#define regUMCCH5_1_PerfMonCtr4_Hi_BASE_IDX 1
+#define regUMCCH5_1_PerfMonCtl5 0x80750
+#define regUMCCH5_1_PerfMonCtl5_BASE_IDX 1
+#define regUMCCH5_1_PerfMonCtr5_Lo 0x80751
+#define regUMCCH5_1_PerfMonCtr5_Lo_BASE_IDX 1
+#define regUMCCH5_1_PerfMonCtr5_Hi 0x80752
+#define regUMCCH5_1_PerfMonCtr5_Hi_BASE_IDX 1
+#define regUMCCH5_1_PerfMonCtl6 0x80753
+#define regUMCCH5_1_PerfMonCtl6_BASE_IDX 1
+#define regUMCCH5_1_PerfMonCtr6_Lo 0x80754
+#define regUMCCH5_1_PerfMonCtr6_Lo_BASE_IDX 1
+#define regUMCCH5_1_PerfMonCtr6_Hi 0x80755
+#define regUMCCH5_1_PerfMonCtr6_Hi_BASE_IDX 1
+#define regUMCCH5_1_PerfMonCtl7 0x80756
+#define regUMCCH5_1_PerfMonCtl7_BASE_IDX 1
+#define regUMCCH5_1_PerfMonCtr7_Lo 0x80757
+#define regUMCCH5_1_PerfMonCtr7_Lo_BASE_IDX 1
+#define regUMCCH5_1_PerfMonCtr7_Hi 0x80758
+#define regUMCCH5_1_PerfMonCtr7_Hi_BASE_IDX 1
+#define regUMCCH5_1_PerfMonCtl8 0x80759
+#define regUMCCH5_1_PerfMonCtl8_BASE_IDX 1
+#define regUMCCH5_1_PerfMonCtr8_Lo 0x8075a
+#define regUMCCH5_1_PerfMonCtr8_Lo_BASE_IDX 1
+#define regUMCCH5_1_PerfMonCtr8_Hi 0x8075b
+#define regUMCCH5_1_PerfMonCtr8_Hi_BASE_IDX 1
+
+
+// addressBlock: umc_w_phy_umc1_umcch6_umcchdec
+// base address: 0x352000
+#define regUMCCH6_1_BaseAddrCS0 0x80800
+#define regUMCCH6_1_BaseAddrCS0_BASE_IDX 1
+#define regUMCCH6_1_AddrMaskCS01 0x80808
+#define regUMCCH6_1_AddrMaskCS01_BASE_IDX 1
+#define regUMCCH6_1_AddrSelCS01 0x80810
+#define regUMCCH6_1_AddrSelCS01_BASE_IDX 1
+#define regUMCCH6_1_AddrHashBank0 0x80832
+#define regUMCCH6_1_AddrHashBank0_BASE_IDX 1
+#define regUMCCH6_1_AddrHashBank1 0x80833
+#define regUMCCH6_1_AddrHashBank1_BASE_IDX 1
+#define regUMCCH6_1_AddrHashBank2 0x80834
+#define regUMCCH6_1_AddrHashBank2_BASE_IDX 1
+#define regUMCCH6_1_AddrHashBank3 0x80835
+#define regUMCCH6_1_AddrHashBank3_BASE_IDX 1
+#define regUMCCH6_1_AddrHashBank4 0x80836
+#define regUMCCH6_1_AddrHashBank4_BASE_IDX 1
+#define regUMCCH6_1_AddrHashBank5 0x80837
+#define regUMCCH6_1_AddrHashBank5_BASE_IDX 1
+#define regUMCCH6_1_EccErrCntSel 0x80b28
+#define regUMCCH6_1_EccErrCntSel_BASE_IDX 1
+#define regUMCCH6_1_EccErrCnt 0x80b29
+#define regUMCCH6_1_EccErrCnt_BASE_IDX 1
+#define regUMCCH6_1_PerfMonCtlClk 0x80b40
+#define regUMCCH6_1_PerfMonCtlClk_BASE_IDX 1
+#define regUMCCH6_1_PerfMonCtrClk_Lo 0x80b41
+#define regUMCCH6_1_PerfMonCtrClk_Lo_BASE_IDX 1
+#define regUMCCH6_1_PerfMonCtrClk_Hi 0x80b42
+#define regUMCCH6_1_PerfMonCtrClk_Hi_BASE_IDX 1
+#define regUMCCH6_1_PerfMonCtl1 0x80b44
+#define regUMCCH6_1_PerfMonCtl1_BASE_IDX 1
+#define regUMCCH6_1_PerfMonCtr1_Lo 0x80b45
+#define regUMCCH6_1_PerfMonCtr1_Lo_BASE_IDX 1
+#define regUMCCH6_1_PerfMonCtr1_Hi 0x80b46
+#define regUMCCH6_1_PerfMonCtr1_Hi_BASE_IDX 1
+#define regUMCCH6_1_PerfMonCtl2 0x80b47
+#define regUMCCH6_1_PerfMonCtl2_BASE_IDX 1
+#define regUMCCH6_1_PerfMonCtr2_Lo 0x80b48
+#define regUMCCH6_1_PerfMonCtr2_Lo_BASE_IDX 1
+#define regUMCCH6_1_PerfMonCtr2_Hi 0x80b49
+#define regUMCCH6_1_PerfMonCtr2_Hi_BASE_IDX 1
+#define regUMCCH6_1_PerfMonCtl3 0x80b4a
+#define regUMCCH6_1_PerfMonCtl3_BASE_IDX 1
+#define regUMCCH6_1_PerfMonCtr3_Lo 0x80b4b
+#define regUMCCH6_1_PerfMonCtr3_Lo_BASE_IDX 1
+#define regUMCCH6_1_PerfMonCtr3_Hi 0x80b4c
+#define regUMCCH6_1_PerfMonCtr3_Hi_BASE_IDX 1
+#define regUMCCH6_1_PerfMonCtl4 0x80b4d
+#define regUMCCH6_1_PerfMonCtl4_BASE_IDX 1
+#define regUMCCH6_1_PerfMonCtr4_Lo 0x80b4e
+#define regUMCCH6_1_PerfMonCtr4_Lo_BASE_IDX 1
+#define regUMCCH6_1_PerfMonCtr4_Hi 0x80b4f
+#define regUMCCH6_1_PerfMonCtr4_Hi_BASE_IDX 1
+#define regUMCCH6_1_PerfMonCtl5 0x80b50
+#define regUMCCH6_1_PerfMonCtl5_BASE_IDX 1
+#define regUMCCH6_1_PerfMonCtr5_Lo 0x80b51
+#define regUMCCH6_1_PerfMonCtr5_Lo_BASE_IDX 1
+#define regUMCCH6_1_PerfMonCtr5_Hi 0x80b52
+#define regUMCCH6_1_PerfMonCtr5_Hi_BASE_IDX 1
+#define regUMCCH6_1_PerfMonCtl6 0x80b53
+#define regUMCCH6_1_PerfMonCtl6_BASE_IDX 1
+#define regUMCCH6_1_PerfMonCtr6_Lo 0x80b54
+#define regUMCCH6_1_PerfMonCtr6_Lo_BASE_IDX 1
+#define regUMCCH6_1_PerfMonCtr6_Hi 0x80b55
+#define regUMCCH6_1_PerfMonCtr6_Hi_BASE_IDX 1
+#define regUMCCH6_1_PerfMonCtl7 0x80b56
+#define regUMCCH6_1_PerfMonCtl7_BASE_IDX 1
+#define regUMCCH6_1_PerfMonCtr7_Lo 0x80b57
+#define regUMCCH6_1_PerfMonCtr7_Lo_BASE_IDX 1
+#define regUMCCH6_1_PerfMonCtr7_Hi 0x80b58
+#define regUMCCH6_1_PerfMonCtr7_Hi_BASE_IDX 1
+#define regUMCCH6_1_PerfMonCtl8 0x80b59
+#define regUMCCH6_1_PerfMonCtl8_BASE_IDX 1
+#define regUMCCH6_1_PerfMonCtr8_Lo 0x80b5a
+#define regUMCCH6_1_PerfMonCtr8_Lo_BASE_IDX 1
+#define regUMCCH6_1_PerfMonCtr8_Hi 0x80b5b
+#define regUMCCH6_1_PerfMonCtr8_Hi_BASE_IDX 1
+
+
+// addressBlock: umc_w_phy_umc1_umcch7_umcchdec
+// base address: 0x353000
+#define regUMCCH7_1_BaseAddrCS0 0x80c00
+#define regUMCCH7_1_BaseAddrCS0_BASE_IDX 1
+#define regUMCCH7_1_AddrMaskCS01 0x80c08
+#define regUMCCH7_1_AddrMaskCS01_BASE_IDX 1
+#define regUMCCH7_1_AddrSelCS01 0x80c10
+#define regUMCCH7_1_AddrSelCS01_BASE_IDX 1
+#define regUMCCH7_1_AddrHashBank0 0x80c32
+#define regUMCCH7_1_AddrHashBank0_BASE_IDX 1
+#define regUMCCH7_1_AddrHashBank1 0x80c33
+#define regUMCCH7_1_AddrHashBank1_BASE_IDX 1
+#define regUMCCH7_1_AddrHashBank2 0x80c34
+#define regUMCCH7_1_AddrHashBank2_BASE_IDX 1
+#define regUMCCH7_1_AddrHashBank3 0x80c35
+#define regUMCCH7_1_AddrHashBank3_BASE_IDX 1
+#define regUMCCH7_1_AddrHashBank4 0x80c36
+#define regUMCCH7_1_AddrHashBank4_BASE_IDX 1
+#define regUMCCH7_1_AddrHashBank5 0x80c37
+#define regUMCCH7_1_AddrHashBank5_BASE_IDX 1
+#define regUMCCH7_1_EccErrCntSel 0x80f28
+#define regUMCCH7_1_EccErrCntSel_BASE_IDX 1
+#define regUMCCH7_1_EccErrCnt 0x80f29
+#define regUMCCH7_1_EccErrCnt_BASE_IDX 1
+#define regUMCCH7_1_PerfMonCtlClk 0x80f40
+#define regUMCCH7_1_PerfMonCtlClk_BASE_IDX 1
+#define regUMCCH7_1_PerfMonCtrClk_Lo 0x80f41
+#define regUMCCH7_1_PerfMonCtrClk_Lo_BASE_IDX 1
+#define regUMCCH7_1_PerfMonCtrClk_Hi 0x80f42
+#define regUMCCH7_1_PerfMonCtrClk_Hi_BASE_IDX 1
+#define regUMCCH7_1_PerfMonCtl1 0x80f44
+#define regUMCCH7_1_PerfMonCtl1_BASE_IDX 1
+#define regUMCCH7_1_PerfMonCtr1_Lo 0x80f45
+#define regUMCCH7_1_PerfMonCtr1_Lo_BASE_IDX 1
+#define regUMCCH7_1_PerfMonCtr1_Hi 0x80f46
+#define regUMCCH7_1_PerfMonCtr1_Hi_BASE_IDX 1
+#define regUMCCH7_1_PerfMonCtl2 0x80f47
+#define regUMCCH7_1_PerfMonCtl2_BASE_IDX 1
+#define regUMCCH7_1_PerfMonCtr2_Lo 0x80f48
+#define regUMCCH7_1_PerfMonCtr2_Lo_BASE_IDX 1
+#define regUMCCH7_1_PerfMonCtr2_Hi 0x80f49
+#define regUMCCH7_1_PerfMonCtr2_Hi_BASE_IDX 1
+#define regUMCCH7_1_PerfMonCtl3 0x80f4a
+#define regUMCCH7_1_PerfMonCtl3_BASE_IDX 1
+#define regUMCCH7_1_PerfMonCtr3_Lo 0x80f4b
+#define regUMCCH7_1_PerfMonCtr3_Lo_BASE_IDX 1
+#define regUMCCH7_1_PerfMonCtr3_Hi 0x80f4c
+#define regUMCCH7_1_PerfMonCtr3_Hi_BASE_IDX 1
+#define regUMCCH7_1_PerfMonCtl4 0x80f4d
+#define regUMCCH7_1_PerfMonCtl4_BASE_IDX 1
+#define regUMCCH7_1_PerfMonCtr4_Lo 0x80f4e
+#define regUMCCH7_1_PerfMonCtr4_Lo_BASE_IDX 1
+#define regUMCCH7_1_PerfMonCtr4_Hi 0x80f4f
+#define regUMCCH7_1_PerfMonCtr4_Hi_BASE_IDX 1
+#define regUMCCH7_1_PerfMonCtl5 0x80f50
+#define regUMCCH7_1_PerfMonCtl5_BASE_IDX 1
+#define regUMCCH7_1_PerfMonCtr5_Lo 0x80f51
+#define regUMCCH7_1_PerfMonCtr5_Lo_BASE_IDX 1
+#define regUMCCH7_1_PerfMonCtr5_Hi 0x80f52
+#define regUMCCH7_1_PerfMonCtr5_Hi_BASE_IDX 1
+#define regUMCCH7_1_PerfMonCtl6 0x80f53
+#define regUMCCH7_1_PerfMonCtl6_BASE_IDX 1
+#define regUMCCH7_1_PerfMonCtr6_Lo 0x80f54
+#define regUMCCH7_1_PerfMonCtr6_Lo_BASE_IDX 1
+#define regUMCCH7_1_PerfMonCtr6_Hi 0x80f55
+#define regUMCCH7_1_PerfMonCtr6_Hi_BASE_IDX 1
+#define regUMCCH7_1_PerfMonCtl7 0x80f56
+#define regUMCCH7_1_PerfMonCtl7_BASE_IDX 1
+#define regUMCCH7_1_PerfMonCtr7_Lo 0x80f57
+#define regUMCCH7_1_PerfMonCtr7_Lo_BASE_IDX 1
+#define regUMCCH7_1_PerfMonCtr7_Hi 0x80f58
+#define regUMCCH7_1_PerfMonCtr7_Hi_BASE_IDX 1
+#define regUMCCH7_1_PerfMonCtl8 0x80f59
+#define regUMCCH7_1_PerfMonCtl8_BASE_IDX 1
+#define regUMCCH7_1_PerfMonCtr8_Lo 0x80f5a
+#define regUMCCH7_1_PerfMonCtr8_Lo_BASE_IDX 1
+#define regUMCCH7_1_PerfMonCtr8_Hi 0x80f5b
+#define regUMCCH7_1_PerfMonCtr8_Hi_BASE_IDX 1
+
+
+// addressBlock: umc_w_phy_umc2_umcch0_umcchdec
+// base address: 0x450000
+#define regUMCCH0_2_BaseAddrCS0 0xc0000
+#define regUMCCH0_2_BaseAddrCS0_BASE_IDX 1
+#define regUMCCH0_2_AddrMaskCS01 0xc0008
+#define regUMCCH0_2_AddrMaskCS01_BASE_IDX 1
+#define regUMCCH0_2_AddrSelCS01 0xc0010
+#define regUMCCH0_2_AddrSelCS01_BASE_IDX 1
+#define regUMCCH0_2_AddrHashBank0 0xc0032
+#define regUMCCH0_2_AddrHashBank0_BASE_IDX 1
+#define regUMCCH0_2_AddrHashBank1 0xc0033
+#define regUMCCH0_2_AddrHashBank1_BASE_IDX 1
+#define regUMCCH0_2_AddrHashBank2 0xc0034
+#define regUMCCH0_2_AddrHashBank2_BASE_IDX 1
+#define regUMCCH0_2_AddrHashBank3 0xc0035
+#define regUMCCH0_2_AddrHashBank3_BASE_IDX 1
+#define regUMCCH0_2_AddrHashBank4 0xc0036
+#define regUMCCH0_2_AddrHashBank4_BASE_IDX 1
+#define regUMCCH0_2_AddrHashBank5 0xc0037
+#define regUMCCH0_2_AddrHashBank5_BASE_IDX 1
+#define regUMCCH0_2_EccErrCntSel 0xc0328
+#define regUMCCH0_2_EccErrCntSel_BASE_IDX 1
+#define regUMCCH0_2_EccErrCnt 0xc0329
+#define regUMCCH0_2_EccErrCnt_BASE_IDX 1
+#define regUMCCH0_2_PerfMonCtlClk 0xc0340
+#define regUMCCH0_2_PerfMonCtlClk_BASE_IDX 1
+#define regUMCCH0_2_PerfMonCtrClk_Lo 0xc0341
+#define regUMCCH0_2_PerfMonCtrClk_Lo_BASE_IDX 1
+#define regUMCCH0_2_PerfMonCtrClk_Hi 0xc0342
+#define regUMCCH0_2_PerfMonCtrClk_Hi_BASE_IDX 1
+#define regUMCCH0_2_PerfMonCtl1 0xc0344
+#define regUMCCH0_2_PerfMonCtl1_BASE_IDX 1
+#define regUMCCH0_2_PerfMonCtr1_Lo 0xc0345
+#define regUMCCH0_2_PerfMonCtr1_Lo_BASE_IDX 1
+#define regUMCCH0_2_PerfMonCtr1_Hi 0xc0346
+#define regUMCCH0_2_PerfMonCtr1_Hi_BASE_IDX 1
+#define regUMCCH0_2_PerfMonCtl2 0xc0347
+#define regUMCCH0_2_PerfMonCtl2_BASE_IDX 1
+#define regUMCCH0_2_PerfMonCtr2_Lo 0xc0348
+#define regUMCCH0_2_PerfMonCtr2_Lo_BASE_IDX 1
+#define regUMCCH0_2_PerfMonCtr2_Hi 0xc0349
+#define regUMCCH0_2_PerfMonCtr2_Hi_BASE_IDX 1
+#define regUMCCH0_2_PerfMonCtl3 0xc034a
+#define regUMCCH0_2_PerfMonCtl3_BASE_IDX 1
+#define regUMCCH0_2_PerfMonCtr3_Lo 0xc034b
+#define regUMCCH0_2_PerfMonCtr3_Lo_BASE_IDX 1
+#define regUMCCH0_2_PerfMonCtr3_Hi 0xc034c
+#define regUMCCH0_2_PerfMonCtr3_Hi_BASE_IDX 1
+#define regUMCCH0_2_PerfMonCtl4 0xc034d
+#define regUMCCH0_2_PerfMonCtl4_BASE_IDX 1
+#define regUMCCH0_2_PerfMonCtr4_Lo 0xc034e
+#define regUMCCH0_2_PerfMonCtr4_Lo_BASE_IDX 1
+#define regUMCCH0_2_PerfMonCtr4_Hi 0xc034f
+#define regUMCCH0_2_PerfMonCtr4_Hi_BASE_IDX 1
+#define regUMCCH0_2_PerfMonCtl5 0xc0350
+#define regUMCCH0_2_PerfMonCtl5_BASE_IDX 1
+#define regUMCCH0_2_PerfMonCtr5_Lo 0xc0351
+#define regUMCCH0_2_PerfMonCtr5_Lo_BASE_IDX 1
+#define regUMCCH0_2_PerfMonCtr5_Hi 0xc0352
+#define regUMCCH0_2_PerfMonCtr5_Hi_BASE_IDX 1
+#define regUMCCH0_2_PerfMonCtl6 0xc0353
+#define regUMCCH0_2_PerfMonCtl6_BASE_IDX 1
+#define regUMCCH0_2_PerfMonCtr6_Lo 0xc0354
+#define regUMCCH0_2_PerfMonCtr6_Lo_BASE_IDX 1
+#define regUMCCH0_2_PerfMonCtr6_Hi 0xc0355
+#define regUMCCH0_2_PerfMonCtr6_Hi_BASE_IDX 1
+#define regUMCCH0_2_PerfMonCtl7 0xc0356
+#define regUMCCH0_2_PerfMonCtl7_BASE_IDX 1
+#define regUMCCH0_2_PerfMonCtr7_Lo 0xc0357
+#define regUMCCH0_2_PerfMonCtr7_Lo_BASE_IDX 1
+#define regUMCCH0_2_PerfMonCtr7_Hi 0xc0358
+#define regUMCCH0_2_PerfMonCtr7_Hi_BASE_IDX 1
+#define regUMCCH0_2_PerfMonCtl8 0xc0359
+#define regUMCCH0_2_PerfMonCtl8_BASE_IDX 1
+#define regUMCCH0_2_PerfMonCtr8_Lo 0xc035a
+#define regUMCCH0_2_PerfMonCtr8_Lo_BASE_IDX 1
+#define regUMCCH0_2_PerfMonCtr8_Hi 0xc035b
+#define regUMCCH0_2_PerfMonCtr8_Hi_BASE_IDX 1
+
+
+// addressBlock: umc_w_phy_umc2_umcch1_umcchdec
+// base address: 0x451000
+#define regUMCCH1_2_BaseAddrCS0 0xc0400
+#define regUMCCH1_2_BaseAddrCS0_BASE_IDX 1
+#define regUMCCH1_2_AddrMaskCS01 0xc0408
+#define regUMCCH1_2_AddrMaskCS01_BASE_IDX 1
+#define regUMCCH1_2_AddrSelCS01 0xc0410
+#define regUMCCH1_2_AddrSelCS01_BASE_IDX 1
+#define regUMCCH1_2_AddrHashBank0 0xc0432
+#define regUMCCH1_2_AddrHashBank0_BASE_IDX 1
+#define regUMCCH1_2_AddrHashBank1 0xc0433
+#define regUMCCH1_2_AddrHashBank1_BASE_IDX 1
+#define regUMCCH1_2_AddrHashBank2 0xc0434
+#define regUMCCH1_2_AddrHashBank2_BASE_IDX 1
+#define regUMCCH1_2_AddrHashBank3 0xc0435
+#define regUMCCH1_2_AddrHashBank3_BASE_IDX 1
+#define regUMCCH1_2_AddrHashBank4 0xc0436
+#define regUMCCH1_2_AddrHashBank4_BASE_IDX 1
+#define regUMCCH1_2_AddrHashBank5 0xc0437
+#define regUMCCH1_2_AddrHashBank5_BASE_IDX 1
+#define regUMCCH1_2_EccErrCntSel 0xc0728
+#define regUMCCH1_2_EccErrCntSel_BASE_IDX 1
+#define regUMCCH1_2_EccErrCnt 0xc0729
+#define regUMCCH1_2_EccErrCnt_BASE_IDX 1
+#define regUMCCH1_2_PerfMonCtlClk 0xc0740
+#define regUMCCH1_2_PerfMonCtlClk_BASE_IDX 1
+#define regUMCCH1_2_PerfMonCtrClk_Lo 0xc0741
+#define regUMCCH1_2_PerfMonCtrClk_Lo_BASE_IDX 1
+#define regUMCCH1_2_PerfMonCtrClk_Hi 0xc0742
+#define regUMCCH1_2_PerfMonCtrClk_Hi_BASE_IDX 1
+#define regUMCCH1_2_PerfMonCtl1 0xc0744
+#define regUMCCH1_2_PerfMonCtl1_BASE_IDX 1
+#define regUMCCH1_2_PerfMonCtr1_Lo 0xc0745
+#define regUMCCH1_2_PerfMonCtr1_Lo_BASE_IDX 1
+#define regUMCCH1_2_PerfMonCtr1_Hi 0xc0746
+#define regUMCCH1_2_PerfMonCtr1_Hi_BASE_IDX 1
+#define regUMCCH1_2_PerfMonCtl2 0xc0747
+#define regUMCCH1_2_PerfMonCtl2_BASE_IDX 1
+#define regUMCCH1_2_PerfMonCtr2_Lo 0xc0748
+#define regUMCCH1_2_PerfMonCtr2_Lo_BASE_IDX 1
+#define regUMCCH1_2_PerfMonCtr2_Hi 0xc0749
+#define regUMCCH1_2_PerfMonCtr2_Hi_BASE_IDX 1
+#define regUMCCH1_2_PerfMonCtl3 0xc074a
+#define regUMCCH1_2_PerfMonCtl3_BASE_IDX 1
+#define regUMCCH1_2_PerfMonCtr3_Lo 0xc074b
+#define regUMCCH1_2_PerfMonCtr3_Lo_BASE_IDX 1
+#define regUMCCH1_2_PerfMonCtr3_Hi 0xc074c
+#define regUMCCH1_2_PerfMonCtr3_Hi_BASE_IDX 1
+#define regUMCCH1_2_PerfMonCtl4 0xc074d
+#define regUMCCH1_2_PerfMonCtl4_BASE_IDX 1
+#define regUMCCH1_2_PerfMonCtr4_Lo 0xc074e
+#define regUMCCH1_2_PerfMonCtr4_Lo_BASE_IDX 1
+#define regUMCCH1_2_PerfMonCtr4_Hi 0xc074f
+#define regUMCCH1_2_PerfMonCtr4_Hi_BASE_IDX 1
+#define regUMCCH1_2_PerfMonCtl5 0xc0750
+#define regUMCCH1_2_PerfMonCtl5_BASE_IDX 1
+#define regUMCCH1_2_PerfMonCtr5_Lo 0xc0751
+#define regUMCCH1_2_PerfMonCtr5_Lo_BASE_IDX 1
+#define regUMCCH1_2_PerfMonCtr5_Hi 0xc0752
+#define regUMCCH1_2_PerfMonCtr5_Hi_BASE_IDX 1
+#define regUMCCH1_2_PerfMonCtl6 0xc0753
+#define regUMCCH1_2_PerfMonCtl6_BASE_IDX 1
+#define regUMCCH1_2_PerfMonCtr6_Lo 0xc0754
+#define regUMCCH1_2_PerfMonCtr6_Lo_BASE_IDX 1
+#define regUMCCH1_2_PerfMonCtr6_Hi 0xc0755
+#define regUMCCH1_2_PerfMonCtr6_Hi_BASE_IDX 1
+#define regUMCCH1_2_PerfMonCtl7 0xc0756
+#define regUMCCH1_2_PerfMonCtl7_BASE_IDX 1
+#define regUMCCH1_2_PerfMonCtr7_Lo 0xc0757
+#define regUMCCH1_2_PerfMonCtr7_Lo_BASE_IDX 1
+#define regUMCCH1_2_PerfMonCtr7_Hi 0xc0758
+#define regUMCCH1_2_PerfMonCtr7_Hi_BASE_IDX 1
+#define regUMCCH1_2_PerfMonCtl8 0xc0759
+#define regUMCCH1_2_PerfMonCtl8_BASE_IDX 1
+#define regUMCCH1_2_PerfMonCtr8_Lo 0xc075a
+#define regUMCCH1_2_PerfMonCtr8_Lo_BASE_IDX 1
+#define regUMCCH1_2_PerfMonCtr8_Hi 0xc075b
+#define regUMCCH1_2_PerfMonCtr8_Hi_BASE_IDX 1
+
+
+// addressBlock: umc_w_phy_umc2_umcch2_umcchdec
+// base address: 0x452000
+#define regUMCCH2_2_BaseAddrCS0 0xc0800
+#define regUMCCH2_2_BaseAddrCS0_BASE_IDX 1
+#define regUMCCH2_2_AddrMaskCS01 0xc0808
+#define regUMCCH2_2_AddrMaskCS01_BASE_IDX 1
+#define regUMCCH2_2_AddrSelCS01 0xc0810
+#define regUMCCH2_2_AddrSelCS01_BASE_IDX 1
+#define regUMCCH2_2_AddrHashBank0 0xc0832
+#define regUMCCH2_2_AddrHashBank0_BASE_IDX 1
+#define regUMCCH2_2_AddrHashBank1 0xc0833
+#define regUMCCH2_2_AddrHashBank1_BASE_IDX 1
+#define regUMCCH2_2_AddrHashBank2 0xc0834
+#define regUMCCH2_2_AddrHashBank2_BASE_IDX 1
+#define regUMCCH2_2_AddrHashBank3 0xc0835
+#define regUMCCH2_2_AddrHashBank3_BASE_IDX 1
+#define regUMCCH2_2_AddrHashBank4 0xc0836
+#define regUMCCH2_2_AddrHashBank4_BASE_IDX 1
+#define regUMCCH2_2_AddrHashBank5 0xc0837
+#define regUMCCH2_2_AddrHashBank5_BASE_IDX 1
+#define regUMCCH2_2_EccErrCntSel 0xc0b28
+#define regUMCCH2_2_EccErrCntSel_BASE_IDX 1
+#define regUMCCH2_2_EccErrCnt 0xc0b29
+#define regUMCCH2_2_EccErrCnt_BASE_IDX 1
+#define regUMCCH2_2_PerfMonCtlClk 0xc0b40
+#define regUMCCH2_2_PerfMonCtlClk_BASE_IDX 1
+#define regUMCCH2_2_PerfMonCtrClk_Lo 0xc0b41
+#define regUMCCH2_2_PerfMonCtrClk_Lo_BASE_IDX 1
+#define regUMCCH2_2_PerfMonCtrClk_Hi 0xc0b42
+#define regUMCCH2_2_PerfMonCtrClk_Hi_BASE_IDX 1
+#define regUMCCH2_2_PerfMonCtl1 0xc0b44
+#define regUMCCH2_2_PerfMonCtl1_BASE_IDX 1
+#define regUMCCH2_2_PerfMonCtr1_Lo 0xc0b45
+#define regUMCCH2_2_PerfMonCtr1_Lo_BASE_IDX 1
+#define regUMCCH2_2_PerfMonCtr1_Hi 0xc0b46
+#define regUMCCH2_2_PerfMonCtr1_Hi_BASE_IDX 1
+#define regUMCCH2_2_PerfMonCtl2 0xc0b47
+#define regUMCCH2_2_PerfMonCtl2_BASE_IDX 1
+#define regUMCCH2_2_PerfMonCtr2_Lo 0xc0b48
+#define regUMCCH2_2_PerfMonCtr2_Lo_BASE_IDX 1
+#define regUMCCH2_2_PerfMonCtr2_Hi 0xc0b49
+#define regUMCCH2_2_PerfMonCtr2_Hi_BASE_IDX 1
+#define regUMCCH2_2_PerfMonCtl3 0xc0b4a
+#define regUMCCH2_2_PerfMonCtl3_BASE_IDX 1
+#define regUMCCH2_2_PerfMonCtr3_Lo 0xc0b4b
+#define regUMCCH2_2_PerfMonCtr3_Lo_BASE_IDX 1
+#define regUMCCH2_2_PerfMonCtr3_Hi 0xc0b4c
+#define regUMCCH2_2_PerfMonCtr3_Hi_BASE_IDX 1
+#define regUMCCH2_2_PerfMonCtl4 0xc0b4d
+#define regUMCCH2_2_PerfMonCtl4_BASE_IDX 1
+#define regUMCCH2_2_PerfMonCtr4_Lo 0xc0b4e
+#define regUMCCH2_2_PerfMonCtr4_Lo_BASE_IDX 1
+#define regUMCCH2_2_PerfMonCtr4_Hi 0xc0b4f
+#define regUMCCH2_2_PerfMonCtr4_Hi_BASE_IDX 1
+#define regUMCCH2_2_PerfMonCtl5 0xc0b50
+#define regUMCCH2_2_PerfMonCtl5_BASE_IDX 1
+#define regUMCCH2_2_PerfMonCtr5_Lo 0xc0b51
+#define regUMCCH2_2_PerfMonCtr5_Lo_BASE_IDX 1
+#define regUMCCH2_2_PerfMonCtr5_Hi 0xc0b52
+#define regUMCCH2_2_PerfMonCtr5_Hi_BASE_IDX 1
+#define regUMCCH2_2_PerfMonCtl6 0xc0b53
+#define regUMCCH2_2_PerfMonCtl6_BASE_IDX 1
+#define regUMCCH2_2_PerfMonCtr6_Lo 0xc0b54
+#define regUMCCH2_2_PerfMonCtr6_Lo_BASE_IDX 1
+#define regUMCCH2_2_PerfMonCtr6_Hi 0xc0b55
+#define regUMCCH2_2_PerfMonCtr6_Hi_BASE_IDX 1
+#define regUMCCH2_2_PerfMonCtl7 0xc0b56
+#define regUMCCH2_2_PerfMonCtl7_BASE_IDX 1
+#define regUMCCH2_2_PerfMonCtr7_Lo 0xc0b57
+#define regUMCCH2_2_PerfMonCtr7_Lo_BASE_IDX 1
+#define regUMCCH2_2_PerfMonCtr7_Hi 0xc0b58
+#define regUMCCH2_2_PerfMonCtr7_Hi_BASE_IDX 1
+#define regUMCCH2_2_PerfMonCtl8 0xc0b59
+#define regUMCCH2_2_PerfMonCtl8_BASE_IDX 1
+#define regUMCCH2_2_PerfMonCtr8_Lo 0xc0b5a
+#define regUMCCH2_2_PerfMonCtr8_Lo_BASE_IDX 1
+#define regUMCCH2_2_PerfMonCtr8_Hi 0xc0b5b
+#define regUMCCH2_2_PerfMonCtr8_Hi_BASE_IDX 1
+
+
+// addressBlock: umc_w_phy_umc2_umcch3_umcchdec
+// base address: 0x453000
+#define regUMCCH3_2_BaseAddrCS0 0xc0c00
+#define regUMCCH3_2_BaseAddrCS0_BASE_IDX 1
+#define regUMCCH3_2_AddrMaskCS01 0xc0c08
+#define regUMCCH3_2_AddrMaskCS01_BASE_IDX 1
+#define regUMCCH3_2_AddrSelCS01 0xc0c10
+#define regUMCCH3_2_AddrSelCS01_BASE_IDX 1
+#define regUMCCH3_2_AddrHashBank0 0xc0c32
+#define regUMCCH3_2_AddrHashBank0_BASE_IDX 1
+#define regUMCCH3_2_AddrHashBank1 0xc0c33
+#define regUMCCH3_2_AddrHashBank1_BASE_IDX 1
+#define regUMCCH3_2_AddrHashBank2 0xc0c34
+#define regUMCCH3_2_AddrHashBank2_BASE_IDX 1
+#define regUMCCH3_2_AddrHashBank3 0xc0c35
+#define regUMCCH3_2_AddrHashBank3_BASE_IDX 1
+#define regUMCCH3_2_AddrHashBank4 0xc0c36
+#define regUMCCH3_2_AddrHashBank4_BASE_IDX 1
+#define regUMCCH3_2_AddrHashBank5 0xc0c37
+#define regUMCCH3_2_AddrHashBank5_BASE_IDX 1
+#define regUMCCH3_2_EccErrCntSel 0xc0f28
+#define regUMCCH3_2_EccErrCntSel_BASE_IDX 1
+#define regUMCCH3_2_EccErrCnt 0xc0f29
+#define regUMCCH3_2_EccErrCnt_BASE_IDX 1
+#define regUMCCH3_2_PerfMonCtlClk 0xc0f40
+#define regUMCCH3_2_PerfMonCtlClk_BASE_IDX 1
+#define regUMCCH3_2_PerfMonCtrClk_Lo 0xc0f41
+#define regUMCCH3_2_PerfMonCtrClk_Lo_BASE_IDX 1
+#define regUMCCH3_2_PerfMonCtrClk_Hi 0xc0f42
+#define regUMCCH3_2_PerfMonCtrClk_Hi_BASE_IDX 1
+#define regUMCCH3_2_PerfMonCtl1 0xc0f44
+#define regUMCCH3_2_PerfMonCtl1_BASE_IDX 1
+#define regUMCCH3_2_PerfMonCtr1_Lo 0xc0f45
+#define regUMCCH3_2_PerfMonCtr1_Lo_BASE_IDX 1
+#define regUMCCH3_2_PerfMonCtr1_Hi 0xc0f46
+#define regUMCCH3_2_PerfMonCtr1_Hi_BASE_IDX 1
+#define regUMCCH3_2_PerfMonCtl2 0xc0f47
+#define regUMCCH3_2_PerfMonCtl2_BASE_IDX 1
+#define regUMCCH3_2_PerfMonCtr2_Lo 0xc0f48
+#define regUMCCH3_2_PerfMonCtr2_Lo_BASE_IDX 1
+#define regUMCCH3_2_PerfMonCtr2_Hi 0xc0f49
+#define regUMCCH3_2_PerfMonCtr2_Hi_BASE_IDX 1
+#define regUMCCH3_2_PerfMonCtl3 0xc0f4a
+#define regUMCCH3_2_PerfMonCtl3_BASE_IDX 1
+#define regUMCCH3_2_PerfMonCtr3_Lo 0xc0f4b
+#define regUMCCH3_2_PerfMonCtr3_Lo_BASE_IDX 1
+#define regUMCCH3_2_PerfMonCtr3_Hi 0xc0f4c
+#define regUMCCH3_2_PerfMonCtr3_Hi_BASE_IDX 1
+#define regUMCCH3_2_PerfMonCtl4 0xc0f4d
+#define regUMCCH3_2_PerfMonCtl4_BASE_IDX 1
+#define regUMCCH3_2_PerfMonCtr4_Lo 0xc0f4e
+#define regUMCCH3_2_PerfMonCtr4_Lo_BASE_IDX 1
+#define regUMCCH3_2_PerfMonCtr4_Hi 0xc0f4f
+#define regUMCCH3_2_PerfMonCtr4_Hi_BASE_IDX 1
+#define regUMCCH3_2_PerfMonCtl5 0xc0f50
+#define regUMCCH3_2_PerfMonCtl5_BASE_IDX 1
+#define regUMCCH3_2_PerfMonCtr5_Lo 0xc0f51
+#define regUMCCH3_2_PerfMonCtr5_Lo_BASE_IDX 1
+#define regUMCCH3_2_PerfMonCtr5_Hi 0xc0f52
+#define regUMCCH3_2_PerfMonCtr5_Hi_BASE_IDX 1
+#define regUMCCH3_2_PerfMonCtl6 0xc0f53
+#define regUMCCH3_2_PerfMonCtl6_BASE_IDX 1
+#define regUMCCH3_2_PerfMonCtr6_Lo 0xc0f54
+#define regUMCCH3_2_PerfMonCtr6_Lo_BASE_IDX 1
+#define regUMCCH3_2_PerfMonCtr6_Hi 0xc0f55
+#define regUMCCH3_2_PerfMonCtr6_Hi_BASE_IDX 1
+#define regUMCCH3_2_PerfMonCtl7 0xc0f56
+#define regUMCCH3_2_PerfMonCtl7_BASE_IDX 1
+#define regUMCCH3_2_PerfMonCtr7_Lo 0xc0f57
+#define regUMCCH3_2_PerfMonCtr7_Lo_BASE_IDX 1
+#define regUMCCH3_2_PerfMonCtr7_Hi 0xc0f58
+#define regUMCCH3_2_PerfMonCtr7_Hi_BASE_IDX 1
+#define regUMCCH3_2_PerfMonCtl8 0xc0f59
+#define regUMCCH3_2_PerfMonCtl8_BASE_IDX 1
+#define regUMCCH3_2_PerfMonCtr8_Lo 0xc0f5a
+#define regUMCCH3_2_PerfMonCtr8_Lo_BASE_IDX 1
+#define regUMCCH3_2_PerfMonCtr8_Hi 0xc0f5b
+#define regUMCCH3_2_PerfMonCtr8_Hi_BASE_IDX 1
+
+
+// addressBlock: umc_w_phy_umc2_umcch4_umcchdec
+// base address: 0x550000
+#define regUMCCH4_2_BaseAddrCS0 0x100000
+#define regUMCCH4_2_BaseAddrCS0_BASE_IDX 1
+#define regUMCCH4_2_AddrMaskCS01 0x100008
+#define regUMCCH4_2_AddrMaskCS01_BASE_IDX 1
+#define regUMCCH4_2_AddrSelCS01 0x100010
+#define regUMCCH4_2_AddrSelCS01_BASE_IDX 1
+#define regUMCCH4_2_AddrHashBank0 0x100032
+#define regUMCCH4_2_AddrHashBank0_BASE_IDX 1
+#define regUMCCH4_2_AddrHashBank1 0x100033
+#define regUMCCH4_2_AddrHashBank1_BASE_IDX 1
+#define regUMCCH4_2_AddrHashBank2 0x100034
+#define regUMCCH4_2_AddrHashBank2_BASE_IDX 1
+#define regUMCCH4_2_AddrHashBank3 0x100035
+#define regUMCCH4_2_AddrHashBank3_BASE_IDX 1
+#define regUMCCH4_2_AddrHashBank4 0x100036
+#define regUMCCH4_2_AddrHashBank4_BASE_IDX 1
+#define regUMCCH4_2_AddrHashBank5 0x100037
+#define regUMCCH4_2_AddrHashBank5_BASE_IDX 1
+#define regUMCCH4_2_EccErrCntSel 0x100328
+#define regUMCCH4_2_EccErrCntSel_BASE_IDX 1
+#define regUMCCH4_2_EccErrCnt 0x100329
+#define regUMCCH4_2_EccErrCnt_BASE_IDX 1
+#define regUMCCH4_2_PerfMonCtlClk 0x100340
+#define regUMCCH4_2_PerfMonCtlClk_BASE_IDX 1
+#define regUMCCH4_2_PerfMonCtrClk_Lo 0x100341
+#define regUMCCH4_2_PerfMonCtrClk_Lo_BASE_IDX 1
+#define regUMCCH4_2_PerfMonCtrClk_Hi 0x100342
+#define regUMCCH4_2_PerfMonCtrClk_Hi_BASE_IDX 1
+#define regUMCCH4_2_PerfMonCtl1 0x100344
+#define regUMCCH4_2_PerfMonCtl1_BASE_IDX 1
+#define regUMCCH4_2_PerfMonCtr1_Lo 0x100345
+#define regUMCCH4_2_PerfMonCtr1_Lo_BASE_IDX 1
+#define regUMCCH4_2_PerfMonCtr1_Hi 0x100346
+#define regUMCCH4_2_PerfMonCtr1_Hi_BASE_IDX 1
+#define regUMCCH4_2_PerfMonCtl2 0x100347
+#define regUMCCH4_2_PerfMonCtl2_BASE_IDX 1
+#define regUMCCH4_2_PerfMonCtr2_Lo 0x100348
+#define regUMCCH4_2_PerfMonCtr2_Lo_BASE_IDX 1
+#define regUMCCH4_2_PerfMonCtr2_Hi 0x100349
+#define regUMCCH4_2_PerfMonCtr2_Hi_BASE_IDX 1
+#define regUMCCH4_2_PerfMonCtl3 0x10034a
+#define regUMCCH4_2_PerfMonCtl3_BASE_IDX 1
+#define regUMCCH4_2_PerfMonCtr3_Lo 0x10034b
+#define regUMCCH4_2_PerfMonCtr3_Lo_BASE_IDX 1
+#define regUMCCH4_2_PerfMonCtr3_Hi 0x10034c
+#define regUMCCH4_2_PerfMonCtr3_Hi_BASE_IDX 1
+#define regUMCCH4_2_PerfMonCtl4 0x10034d
+#define regUMCCH4_2_PerfMonCtl4_BASE_IDX 1
+#define regUMCCH4_2_PerfMonCtr4_Lo 0x10034e
+#define regUMCCH4_2_PerfMonCtr4_Lo_BASE_IDX 1
+#define regUMCCH4_2_PerfMonCtr4_Hi 0x10034f
+#define regUMCCH4_2_PerfMonCtr4_Hi_BASE_IDX 1
+#define regUMCCH4_2_PerfMonCtl5 0x100350
+#define regUMCCH4_2_PerfMonCtl5_BASE_IDX 1
+#define regUMCCH4_2_PerfMonCtr5_Lo 0x100351
+#define regUMCCH4_2_PerfMonCtr5_Lo_BASE_IDX 1
+#define regUMCCH4_2_PerfMonCtr5_Hi 0x100352
+#define regUMCCH4_2_PerfMonCtr5_Hi_BASE_IDX 1
+#define regUMCCH4_2_PerfMonCtl6 0x100353
+#define regUMCCH4_2_PerfMonCtl6_BASE_IDX 1
+#define regUMCCH4_2_PerfMonCtr6_Lo 0x100354
+#define regUMCCH4_2_PerfMonCtr6_Lo_BASE_IDX 1
+#define regUMCCH4_2_PerfMonCtr6_Hi 0x100355
+#define regUMCCH4_2_PerfMonCtr6_Hi_BASE_IDX 1
+#define regUMCCH4_2_PerfMonCtl7 0x100356
+#define regUMCCH4_2_PerfMonCtl7_BASE_IDX 1
+#define regUMCCH4_2_PerfMonCtr7_Lo 0x100357
+#define regUMCCH4_2_PerfMonCtr7_Lo_BASE_IDX 1
+#define regUMCCH4_2_PerfMonCtr7_Hi 0x100358
+#define regUMCCH4_2_PerfMonCtr7_Hi_BASE_IDX 1
+#define regUMCCH4_2_PerfMonCtl8 0x100359
+#define regUMCCH4_2_PerfMonCtl8_BASE_IDX 1
+#define regUMCCH4_2_PerfMonCtr8_Lo 0x10035a
+#define regUMCCH4_2_PerfMonCtr8_Lo_BASE_IDX 1
+#define regUMCCH4_2_PerfMonCtr8_Hi 0x10035b
+#define regUMCCH4_2_PerfMonCtr8_Hi_BASE_IDX 1
+
+
+// addressBlock: umc_w_phy_umc2_umcch5_umcchdec
+// base address: 0x551000
+#define regUMCCH5_2_BaseAddrCS0 0x100400
+#define regUMCCH5_2_BaseAddrCS0_BASE_IDX 1
+#define regUMCCH5_2_AddrMaskCS01 0x100408
+#define regUMCCH5_2_AddrMaskCS01_BASE_IDX 1
+#define regUMCCH5_2_AddrSelCS01 0x100410
+#define regUMCCH5_2_AddrSelCS01_BASE_IDX 1
+#define regUMCCH5_2_AddrHashBank0 0x100432
+#define regUMCCH5_2_AddrHashBank0_BASE_IDX 1
+#define regUMCCH5_2_AddrHashBank1 0x100433
+#define regUMCCH5_2_AddrHashBank1_BASE_IDX 1
+#define regUMCCH5_2_AddrHashBank2 0x100434
+#define regUMCCH5_2_AddrHashBank2_BASE_IDX 1
+#define regUMCCH5_2_AddrHashBank3 0x100435
+#define regUMCCH5_2_AddrHashBank3_BASE_IDX 1
+#define regUMCCH5_2_AddrHashBank4 0x100436
+#define regUMCCH5_2_AddrHashBank4_BASE_IDX 1
+#define regUMCCH5_2_AddrHashBank5 0x100437
+#define regUMCCH5_2_AddrHashBank5_BASE_IDX 1
+#define regUMCCH5_2_EccErrCntSel 0x100728
+#define regUMCCH5_2_EccErrCntSel_BASE_IDX 1
+#define regUMCCH5_2_EccErrCnt 0x100729
+#define regUMCCH5_2_EccErrCnt_BASE_IDX 1
+#define regUMCCH5_2_PerfMonCtlClk 0x100740
+#define regUMCCH5_2_PerfMonCtlClk_BASE_IDX 1
+#define regUMCCH5_2_PerfMonCtrClk_Lo 0x100741
+#define regUMCCH5_2_PerfMonCtrClk_Lo_BASE_IDX 1
+#define regUMCCH5_2_PerfMonCtrClk_Hi 0x100742
+#define regUMCCH5_2_PerfMonCtrClk_Hi_BASE_IDX 1
+#define regUMCCH5_2_PerfMonCtl1 0x100744
+#define regUMCCH5_2_PerfMonCtl1_BASE_IDX 1
+#define regUMCCH5_2_PerfMonCtr1_Lo 0x100745
+#define regUMCCH5_2_PerfMonCtr1_Lo_BASE_IDX 1
+#define regUMCCH5_2_PerfMonCtr1_Hi 0x100746
+#define regUMCCH5_2_PerfMonCtr1_Hi_BASE_IDX 1
+#define regUMCCH5_2_PerfMonCtl2 0x100747
+#define regUMCCH5_2_PerfMonCtl2_BASE_IDX 1
+#define regUMCCH5_2_PerfMonCtr2_Lo 0x100748
+#define regUMCCH5_2_PerfMonCtr2_Lo_BASE_IDX 1
+#define regUMCCH5_2_PerfMonCtr2_Hi 0x100749
+#define regUMCCH5_2_PerfMonCtr2_Hi_BASE_IDX 1
+#define regUMCCH5_2_PerfMonCtl3 0x10074a
+#define regUMCCH5_2_PerfMonCtl3_BASE_IDX 1
+#define regUMCCH5_2_PerfMonCtr3_Lo 0x10074b
+#define regUMCCH5_2_PerfMonCtr3_Lo_BASE_IDX 1
+#define regUMCCH5_2_PerfMonCtr3_Hi 0x10074c
+#define regUMCCH5_2_PerfMonCtr3_Hi_BASE_IDX 1
+#define regUMCCH5_2_PerfMonCtl4 0x10074d
+#define regUMCCH5_2_PerfMonCtl4_BASE_IDX 1
+#define regUMCCH5_2_PerfMonCtr4_Lo 0x10074e
+#define regUMCCH5_2_PerfMonCtr4_Lo_BASE_IDX 1
+#define regUMCCH5_2_PerfMonCtr4_Hi 0x10074f
+#define regUMCCH5_2_PerfMonCtr4_Hi_BASE_IDX 1
+#define regUMCCH5_2_PerfMonCtl5 0x100750
+#define regUMCCH5_2_PerfMonCtl5_BASE_IDX 1
+#define regUMCCH5_2_PerfMonCtr5_Lo 0x100751
+#define regUMCCH5_2_PerfMonCtr5_Lo_BASE_IDX 1
+#define regUMCCH5_2_PerfMonCtr5_Hi 0x100752
+#define regUMCCH5_2_PerfMonCtr5_Hi_BASE_IDX 1
+#define regUMCCH5_2_PerfMonCtl6 0x100753
+#define regUMCCH5_2_PerfMonCtl6_BASE_IDX 1
+#define regUMCCH5_2_PerfMonCtr6_Lo 0x100754
+#define regUMCCH5_2_PerfMonCtr6_Lo_BASE_IDX 1
+#define regUMCCH5_2_PerfMonCtr6_Hi 0x100755
+#define regUMCCH5_2_PerfMonCtr6_Hi_BASE_IDX 1
+#define regUMCCH5_2_PerfMonCtl7 0x100756
+#define regUMCCH5_2_PerfMonCtl7_BASE_IDX 1
+#define regUMCCH5_2_PerfMonCtr7_Lo 0x100757
+#define regUMCCH5_2_PerfMonCtr7_Lo_BASE_IDX 1
+#define regUMCCH5_2_PerfMonCtr7_Hi 0x100758
+#define regUMCCH5_2_PerfMonCtr7_Hi_BASE_IDX 1
+#define regUMCCH5_2_PerfMonCtl8 0x100759
+#define regUMCCH5_2_PerfMonCtl8_BASE_IDX 1
+#define regUMCCH5_2_PerfMonCtr8_Lo 0x10075a
+#define regUMCCH5_2_PerfMonCtr8_Lo_BASE_IDX 1
+#define regUMCCH5_2_PerfMonCtr8_Hi 0x10075b
+#define regUMCCH5_2_PerfMonCtr8_Hi_BASE_IDX 1
+
+
+// addressBlock: umc_w_phy_umc2_umcch6_umcchdec
+// base address: 0x552000
+#define regUMCCH6_2_BaseAddrCS0 0x100800
+#define regUMCCH6_2_BaseAddrCS0_BASE_IDX 1
+#define regUMCCH6_2_AddrMaskCS01 0x100808
+#define regUMCCH6_2_AddrMaskCS01_BASE_IDX 1
+#define regUMCCH6_2_AddrSelCS01 0x100810
+#define regUMCCH6_2_AddrSelCS01_BASE_IDX 1
+#define regUMCCH6_2_AddrHashBank0 0x100832
+#define regUMCCH6_2_AddrHashBank0_BASE_IDX 1
+#define regUMCCH6_2_AddrHashBank1 0x100833
+#define regUMCCH6_2_AddrHashBank1_BASE_IDX 1
+#define regUMCCH6_2_AddrHashBank2 0x100834
+#define regUMCCH6_2_AddrHashBank2_BASE_IDX 1
+#define regUMCCH6_2_AddrHashBank3 0x100835
+#define regUMCCH6_2_AddrHashBank3_BASE_IDX 1
+#define regUMCCH6_2_AddrHashBank4 0x100836
+#define regUMCCH6_2_AddrHashBank4_BASE_IDX 1
+#define regUMCCH6_2_AddrHashBank5 0x100837
+#define regUMCCH6_2_AddrHashBank5_BASE_IDX 1
+#define regUMCCH6_2_EccErrCntSel 0x100b28
+#define regUMCCH6_2_EccErrCntSel_BASE_IDX 1
+#define regUMCCH6_2_EccErrCnt 0x100b29
+#define regUMCCH6_2_EccErrCnt_BASE_IDX 1
+#define regUMCCH6_2_PerfMonCtlClk 0x100b40
+#define regUMCCH6_2_PerfMonCtlClk_BASE_IDX 1
+#define regUMCCH6_2_PerfMonCtrClk_Lo 0x100b41
+#define regUMCCH6_2_PerfMonCtrClk_Lo_BASE_IDX 1
+#define regUMCCH6_2_PerfMonCtrClk_Hi 0x100b42
+#define regUMCCH6_2_PerfMonCtrClk_Hi_BASE_IDX 1
+#define regUMCCH6_2_PerfMonCtl1 0x100b44
+#define regUMCCH6_2_PerfMonCtl1_BASE_IDX 1
+#define regUMCCH6_2_PerfMonCtr1_Lo 0x100b45
+#define regUMCCH6_2_PerfMonCtr1_Lo_BASE_IDX 1
+#define regUMCCH6_2_PerfMonCtr1_Hi 0x100b46
+#define regUMCCH6_2_PerfMonCtr1_Hi_BASE_IDX 1
+#define regUMCCH6_2_PerfMonCtl2 0x100b47
+#define regUMCCH6_2_PerfMonCtl2_BASE_IDX 1
+#define regUMCCH6_2_PerfMonCtr2_Lo 0x100b48
+#define regUMCCH6_2_PerfMonCtr2_Lo_BASE_IDX 1
+#define regUMCCH6_2_PerfMonCtr2_Hi 0x100b49
+#define regUMCCH6_2_PerfMonCtr2_Hi_BASE_IDX 1
+#define regUMCCH6_2_PerfMonCtl3 0x100b4a
+#define regUMCCH6_2_PerfMonCtl3_BASE_IDX 1
+#define regUMCCH6_2_PerfMonCtr3_Lo 0x100b4b
+#define regUMCCH6_2_PerfMonCtr3_Lo_BASE_IDX 1
+#define regUMCCH6_2_PerfMonCtr3_Hi 0x100b4c
+#define regUMCCH6_2_PerfMonCtr3_Hi_BASE_IDX 1
+#define regUMCCH6_2_PerfMonCtl4 0x100b4d
+#define regUMCCH6_2_PerfMonCtl4_BASE_IDX 1
+#define regUMCCH6_2_PerfMonCtr4_Lo 0x100b4e
+#define regUMCCH6_2_PerfMonCtr4_Lo_BASE_IDX 1
+#define regUMCCH6_2_PerfMonCtr4_Hi 0x100b4f
+#define regUMCCH6_2_PerfMonCtr4_Hi_BASE_IDX 1
+#define regUMCCH6_2_PerfMonCtl5 0x100b50
+#define regUMCCH6_2_PerfMonCtl5_BASE_IDX 1
+#define regUMCCH6_2_PerfMonCtr5_Lo 0x100b51
+#define regUMCCH6_2_PerfMonCtr5_Lo_BASE_IDX 1
+#define regUMCCH6_2_PerfMonCtr5_Hi 0x100b52
+#define regUMCCH6_2_PerfMonCtr5_Hi_BASE_IDX 1
+#define regUMCCH6_2_PerfMonCtl6 0x100b53
+#define regUMCCH6_2_PerfMonCtl6_BASE_IDX 1
+#define regUMCCH6_2_PerfMonCtr6_Lo 0x100b54
+#define regUMCCH6_2_PerfMonCtr6_Lo_BASE_IDX 1
+#define regUMCCH6_2_PerfMonCtr6_Hi 0x100b55
+#define regUMCCH6_2_PerfMonCtr6_Hi_BASE_IDX 1
+#define regUMCCH6_2_PerfMonCtl7 0x100b56
+#define regUMCCH6_2_PerfMonCtl7_BASE_IDX 1
+#define regUMCCH6_2_PerfMonCtr7_Lo 0x100b57
+#define regUMCCH6_2_PerfMonCtr7_Lo_BASE_IDX 1
+#define regUMCCH6_2_PerfMonCtr7_Hi 0x100b58
+#define regUMCCH6_2_PerfMonCtr7_Hi_BASE_IDX 1
+#define regUMCCH6_2_PerfMonCtl8 0x100b59
+#define regUMCCH6_2_PerfMonCtl8_BASE_IDX 1
+#define regUMCCH6_2_PerfMonCtr8_Lo 0x100b5a
+#define regUMCCH6_2_PerfMonCtr8_Lo_BASE_IDX 1
+#define regUMCCH6_2_PerfMonCtr8_Hi 0x100b5b
+#define regUMCCH6_2_PerfMonCtr8_Hi_BASE_IDX 1
+
+
+// addressBlock: umc_w_phy_umc2_umcch7_umcchdec
+// base address: 0x553000
+#define regUMCCH7_2_BaseAddrCS0 0x100c00
+#define regUMCCH7_2_BaseAddrCS0_BASE_IDX 1
+#define regUMCCH7_2_AddrMaskCS01 0x100c08
+#define regUMCCH7_2_AddrMaskCS01_BASE_IDX 1
+#define regUMCCH7_2_AddrSelCS01 0x100c10
+#define regUMCCH7_2_AddrSelCS01_BASE_IDX 1
+#define regUMCCH7_2_AddrHashBank0 0x100c32
+#define regUMCCH7_2_AddrHashBank0_BASE_IDX 1
+#define regUMCCH7_2_AddrHashBank1 0x100c33
+#define regUMCCH7_2_AddrHashBank1_BASE_IDX 1
+#define regUMCCH7_2_AddrHashBank2 0x100c34
+#define regUMCCH7_2_AddrHashBank2_BASE_IDX 1
+#define regUMCCH7_2_AddrHashBank3 0x100c35
+#define regUMCCH7_2_AddrHashBank3_BASE_IDX 1
+#define regUMCCH7_2_AddrHashBank4 0x100c36
+#define regUMCCH7_2_AddrHashBank4_BASE_IDX 1
+#define regUMCCH7_2_AddrHashBank5 0x100c37
+#define regUMCCH7_2_AddrHashBank5_BASE_IDX 1
+#define regUMCCH7_2_EccErrCntSel 0x100f28
+#define regUMCCH7_2_EccErrCntSel_BASE_IDX 1
+#define regUMCCH7_2_EccErrCnt 0x100f29
+#define regUMCCH7_2_EccErrCnt_BASE_IDX 1
+#define regUMCCH7_2_PerfMonCtlClk 0x100f40
+#define regUMCCH7_2_PerfMonCtlClk_BASE_IDX 1
+#define regUMCCH7_2_PerfMonCtrClk_Lo 0x100f41
+#define regUMCCH7_2_PerfMonCtrClk_Lo_BASE_IDX 1
+#define regUMCCH7_2_PerfMonCtrClk_Hi 0x100f42
+#define regUMCCH7_2_PerfMonCtrClk_Hi_BASE_IDX 1
+#define regUMCCH7_2_PerfMonCtl1 0x100f44
+#define regUMCCH7_2_PerfMonCtl1_BASE_IDX 1
+#define regUMCCH7_2_PerfMonCtr1_Lo 0x100f45
+#define regUMCCH7_2_PerfMonCtr1_Lo_BASE_IDX 1
+#define regUMCCH7_2_PerfMonCtr1_Hi 0x100f46
+#define regUMCCH7_2_PerfMonCtr1_Hi_BASE_IDX 1
+#define regUMCCH7_2_PerfMonCtl2 0x100f47
+#define regUMCCH7_2_PerfMonCtl2_BASE_IDX 1
+#define regUMCCH7_2_PerfMonCtr2_Lo 0x100f48
+#define regUMCCH7_2_PerfMonCtr2_Lo_BASE_IDX 1
+#define regUMCCH7_2_PerfMonCtr2_Hi 0x100f49
+#define regUMCCH7_2_PerfMonCtr2_Hi_BASE_IDX 1
+#define regUMCCH7_2_PerfMonCtl3 0x100f4a
+#define regUMCCH7_2_PerfMonCtl3_BASE_IDX 1
+#define regUMCCH7_2_PerfMonCtr3_Lo 0x100f4b
+#define regUMCCH7_2_PerfMonCtr3_Lo_BASE_IDX 1
+#define regUMCCH7_2_PerfMonCtr3_Hi 0x100f4c
+#define regUMCCH7_2_PerfMonCtr3_Hi_BASE_IDX 1
+#define regUMCCH7_2_PerfMonCtl4 0x100f4d
+#define regUMCCH7_2_PerfMonCtl4_BASE_IDX 1
+#define regUMCCH7_2_PerfMonCtr4_Lo 0x100f4e
+#define regUMCCH7_2_PerfMonCtr4_Lo_BASE_IDX 1
+#define regUMCCH7_2_PerfMonCtr4_Hi 0x100f4f
+#define regUMCCH7_2_PerfMonCtr4_Hi_BASE_IDX 1
+#define regUMCCH7_2_PerfMonCtl5 0x100f50
+#define regUMCCH7_2_PerfMonCtl5_BASE_IDX 1
+#define regUMCCH7_2_PerfMonCtr5_Lo 0x100f51
+#define regUMCCH7_2_PerfMonCtr5_Lo_BASE_IDX 1
+#define regUMCCH7_2_PerfMonCtr5_Hi 0x100f52
+#define regUMCCH7_2_PerfMonCtr5_Hi_BASE_IDX 1
+#define regUMCCH7_2_PerfMonCtl6 0x100f53
+#define regUMCCH7_2_PerfMonCtl6_BASE_IDX 1
+#define regUMCCH7_2_PerfMonCtr6_Lo 0x100f54
+#define regUMCCH7_2_PerfMonCtr6_Lo_BASE_IDX 1
+#define regUMCCH7_2_PerfMonCtr6_Hi 0x100f55
+#define regUMCCH7_2_PerfMonCtr6_Hi_BASE_IDX 1
+#define regUMCCH7_2_PerfMonCtl7 0x100f56
+#define regUMCCH7_2_PerfMonCtl7_BASE_IDX 1
+#define regUMCCH7_2_PerfMonCtr7_Lo 0x100f57
+#define regUMCCH7_2_PerfMonCtr7_Lo_BASE_IDX 1
+#define regUMCCH7_2_PerfMonCtr7_Hi 0x100f58
+#define regUMCCH7_2_PerfMonCtr7_Hi_BASE_IDX 1
+#define regUMCCH7_2_PerfMonCtl8 0x100f59
+#define regUMCCH7_2_PerfMonCtl8_BASE_IDX 1
+#define regUMCCH7_2_PerfMonCtr8_Lo 0x100f5a
+#define regUMCCH7_2_PerfMonCtr8_Lo_BASE_IDX 1
+#define regUMCCH7_2_PerfMonCtr8_Hi 0x100f5b
+#define regUMCCH7_2_PerfMonCtr8_Hi_BASE_IDX 1
+
+
+// addressBlock: umc_w_phy_umc3_umcch0_umcchdec
+// base address: 0x650000
+#define regUMCCH0_3_BaseAddrCS0 0x140000
+#define regUMCCH0_3_BaseAddrCS0_BASE_IDX 1
+#define regUMCCH0_3_AddrMaskCS01 0x140008
+#define regUMCCH0_3_AddrMaskCS01_BASE_IDX 1
+#define regUMCCH0_3_AddrSelCS01 0x140010
+#define regUMCCH0_3_AddrSelCS01_BASE_IDX 1
+#define regUMCCH0_3_AddrHashBank0 0x140032
+#define regUMCCH0_3_AddrHashBank0_BASE_IDX 1
+#define regUMCCH0_3_AddrHashBank1 0x140033
+#define regUMCCH0_3_AddrHashBank1_BASE_IDX 1
+#define regUMCCH0_3_AddrHashBank2 0x140034
+#define regUMCCH0_3_AddrHashBank2_BASE_IDX 1
+#define regUMCCH0_3_AddrHashBank3 0x140035
+#define regUMCCH0_3_AddrHashBank3_BASE_IDX 1
+#define regUMCCH0_3_AddrHashBank4 0x140036
+#define regUMCCH0_3_AddrHashBank4_BASE_IDX 1
+#define regUMCCH0_3_AddrHashBank5 0x140037
+#define regUMCCH0_3_AddrHashBank5_BASE_IDX 1
+#define regUMCCH0_3_EccErrCntSel 0x140328
+#define regUMCCH0_3_EccErrCntSel_BASE_IDX 1
+#define regUMCCH0_3_EccErrCnt 0x140329
+#define regUMCCH0_3_EccErrCnt_BASE_IDX 1
+#define regUMCCH0_3_PerfMonCtlClk 0x140340
+#define regUMCCH0_3_PerfMonCtlClk_BASE_IDX 1
+#define regUMCCH0_3_PerfMonCtrClk_Lo 0x140341
+#define regUMCCH0_3_PerfMonCtrClk_Lo_BASE_IDX 1
+#define regUMCCH0_3_PerfMonCtrClk_Hi 0x140342
+#define regUMCCH0_3_PerfMonCtrClk_Hi_BASE_IDX 1
+#define regUMCCH0_3_PerfMonCtl1 0x140344
+#define regUMCCH0_3_PerfMonCtl1_BASE_IDX 1
+#define regUMCCH0_3_PerfMonCtr1_Lo 0x140345
+#define regUMCCH0_3_PerfMonCtr1_Lo_BASE_IDX 1
+#define regUMCCH0_3_PerfMonCtr1_Hi 0x140346
+#define regUMCCH0_3_PerfMonCtr1_Hi_BASE_IDX 1
+#define regUMCCH0_3_PerfMonCtl2 0x140347
+#define regUMCCH0_3_PerfMonCtl2_BASE_IDX 1
+#define regUMCCH0_3_PerfMonCtr2_Lo 0x140348
+#define regUMCCH0_3_PerfMonCtr2_Lo_BASE_IDX 1
+#define regUMCCH0_3_PerfMonCtr2_Hi 0x140349
+#define regUMCCH0_3_PerfMonCtr2_Hi_BASE_IDX 1
+#define regUMCCH0_3_PerfMonCtl3 0x14034a
+#define regUMCCH0_3_PerfMonCtl3_BASE_IDX 1
+#define regUMCCH0_3_PerfMonCtr3_Lo 0x14034b
+#define regUMCCH0_3_PerfMonCtr3_Lo_BASE_IDX 1
+#define regUMCCH0_3_PerfMonCtr3_Hi 0x14034c
+#define regUMCCH0_3_PerfMonCtr3_Hi_BASE_IDX 1
+#define regUMCCH0_3_PerfMonCtl4 0x14034d
+#define regUMCCH0_3_PerfMonCtl4_BASE_IDX 1
+#define regUMCCH0_3_PerfMonCtr4_Lo 0x14034e
+#define regUMCCH0_3_PerfMonCtr4_Lo_BASE_IDX 1
+#define regUMCCH0_3_PerfMonCtr4_Hi 0x14034f
+#define regUMCCH0_3_PerfMonCtr4_Hi_BASE_IDX 1
+#define regUMCCH0_3_PerfMonCtl5 0x140350
+#define regUMCCH0_3_PerfMonCtl5_BASE_IDX 1
+#define regUMCCH0_3_PerfMonCtr5_Lo 0x140351
+#define regUMCCH0_3_PerfMonCtr5_Lo_BASE_IDX 1
+#define regUMCCH0_3_PerfMonCtr5_Hi 0x140352
+#define regUMCCH0_3_PerfMonCtr5_Hi_BASE_IDX 1
+#define regUMCCH0_3_PerfMonCtl6 0x140353
+#define regUMCCH0_3_PerfMonCtl6_BASE_IDX 1
+#define regUMCCH0_3_PerfMonCtr6_Lo 0x140354
+#define regUMCCH0_3_PerfMonCtr6_Lo_BASE_IDX 1
+#define regUMCCH0_3_PerfMonCtr6_Hi 0x140355
+#define regUMCCH0_3_PerfMonCtr6_Hi_BASE_IDX 1
+#define regUMCCH0_3_PerfMonCtl7 0x140356
+#define regUMCCH0_3_PerfMonCtl7_BASE_IDX 1
+#define regUMCCH0_3_PerfMonCtr7_Lo 0x140357
+#define regUMCCH0_3_PerfMonCtr7_Lo_BASE_IDX 1
+#define regUMCCH0_3_PerfMonCtr7_Hi 0x140358
+#define regUMCCH0_3_PerfMonCtr7_Hi_BASE_IDX 1
+#define regUMCCH0_3_PerfMonCtl8 0x140359
+#define regUMCCH0_3_PerfMonCtl8_BASE_IDX 1
+#define regUMCCH0_3_PerfMonCtr8_Lo 0x14035a
+#define regUMCCH0_3_PerfMonCtr8_Lo_BASE_IDX 1
+#define regUMCCH0_3_PerfMonCtr8_Hi 0x14035b
+#define regUMCCH0_3_PerfMonCtr8_Hi_BASE_IDX 1
+
+
+// addressBlock: umc_w_phy_umc3_umcch1_umcchdec
+// base address: 0x651000
+#define regUMCCH1_3_BaseAddrCS0 0x140400
+#define regUMCCH1_3_BaseAddrCS0_BASE_IDX 1
+#define regUMCCH1_3_AddrMaskCS01 0x140408
+#define regUMCCH1_3_AddrMaskCS01_BASE_IDX 1
+#define regUMCCH1_3_AddrSelCS01 0x140410
+#define regUMCCH1_3_AddrSelCS01_BASE_IDX 1
+#define regUMCCH1_3_AddrHashBank0 0x140432
+#define regUMCCH1_3_AddrHashBank0_BASE_IDX 1
+#define regUMCCH1_3_AddrHashBank1 0x140433
+#define regUMCCH1_3_AddrHashBank1_BASE_IDX 1
+#define regUMCCH1_3_AddrHashBank2 0x140434
+#define regUMCCH1_3_AddrHashBank2_BASE_IDX 1
+#define regUMCCH1_3_AddrHashBank3 0x140435
+#define regUMCCH1_3_AddrHashBank3_BASE_IDX 1
+#define regUMCCH1_3_AddrHashBank4 0x140436
+#define regUMCCH1_3_AddrHashBank4_BASE_IDX 1
+#define regUMCCH1_3_AddrHashBank5 0x140437
+#define regUMCCH1_3_AddrHashBank5_BASE_IDX 1
+#define regUMCCH1_3_EccErrCntSel 0x140728
+#define regUMCCH1_3_EccErrCntSel_BASE_IDX 1
+#define regUMCCH1_3_EccErrCnt 0x140729
+#define regUMCCH1_3_EccErrCnt_BASE_IDX 1
+#define regUMCCH1_3_PerfMonCtlClk 0x140740
+#define regUMCCH1_3_PerfMonCtlClk_BASE_IDX 1
+#define regUMCCH1_3_PerfMonCtrClk_Lo 0x140741
+#define regUMCCH1_3_PerfMonCtrClk_Lo_BASE_IDX 1
+#define regUMCCH1_3_PerfMonCtrClk_Hi 0x140742
+#define regUMCCH1_3_PerfMonCtrClk_Hi_BASE_IDX 1
+#define regUMCCH1_3_PerfMonCtl1 0x140744
+#define regUMCCH1_3_PerfMonCtl1_BASE_IDX 1
+#define regUMCCH1_3_PerfMonCtr1_Lo 0x140745
+#define regUMCCH1_3_PerfMonCtr1_Lo_BASE_IDX 1
+#define regUMCCH1_3_PerfMonCtr1_Hi 0x140746
+#define regUMCCH1_3_PerfMonCtr1_Hi_BASE_IDX 1
+#define regUMCCH1_3_PerfMonCtl2 0x140747
+#define regUMCCH1_3_PerfMonCtl2_BASE_IDX 1
+#define regUMCCH1_3_PerfMonCtr2_Lo 0x140748
+#define regUMCCH1_3_PerfMonCtr2_Lo_BASE_IDX 1
+#define regUMCCH1_3_PerfMonCtr2_Hi 0x140749
+#define regUMCCH1_3_PerfMonCtr2_Hi_BASE_IDX 1
+#define regUMCCH1_3_PerfMonCtl3 0x14074a
+#define regUMCCH1_3_PerfMonCtl3_BASE_IDX 1
+#define regUMCCH1_3_PerfMonCtr3_Lo 0x14074b
+#define regUMCCH1_3_PerfMonCtr3_Lo_BASE_IDX 1
+#define regUMCCH1_3_PerfMonCtr3_Hi 0x14074c
+#define regUMCCH1_3_PerfMonCtr3_Hi_BASE_IDX 1
+#define regUMCCH1_3_PerfMonCtl4 0x14074d
+#define regUMCCH1_3_PerfMonCtl4_BASE_IDX 1
+#define regUMCCH1_3_PerfMonCtr4_Lo 0x14074e
+#define regUMCCH1_3_PerfMonCtr4_Lo_BASE_IDX 1
+#define regUMCCH1_3_PerfMonCtr4_Hi 0x14074f
+#define regUMCCH1_3_PerfMonCtr4_Hi_BASE_IDX 1
+#define regUMCCH1_3_PerfMonCtl5 0x140750
+#define regUMCCH1_3_PerfMonCtl5_BASE_IDX 1
+#define regUMCCH1_3_PerfMonCtr5_Lo 0x140751
+#define regUMCCH1_3_PerfMonCtr5_Lo_BASE_IDX 1
+#define regUMCCH1_3_PerfMonCtr5_Hi 0x140752
+#define regUMCCH1_3_PerfMonCtr5_Hi_BASE_IDX 1
+#define regUMCCH1_3_PerfMonCtl6 0x140753
+#define regUMCCH1_3_PerfMonCtl6_BASE_IDX 1
+#define regUMCCH1_3_PerfMonCtr6_Lo 0x140754
+#define regUMCCH1_3_PerfMonCtr6_Lo_BASE_IDX 1
+#define regUMCCH1_3_PerfMonCtr6_Hi 0x140755
+#define regUMCCH1_3_PerfMonCtr6_Hi_BASE_IDX 1
+#define regUMCCH1_3_PerfMonCtl7 0x140756
+#define regUMCCH1_3_PerfMonCtl7_BASE_IDX 1
+#define regUMCCH1_3_PerfMonCtr7_Lo 0x140757
+#define regUMCCH1_3_PerfMonCtr7_Lo_BASE_IDX 1
+#define regUMCCH1_3_PerfMonCtr7_Hi 0x140758
+#define regUMCCH1_3_PerfMonCtr7_Hi_BASE_IDX 1
+#define regUMCCH1_3_PerfMonCtl8 0x140759
+#define regUMCCH1_3_PerfMonCtl8_BASE_IDX 1
+#define regUMCCH1_3_PerfMonCtr8_Lo 0x14075a
+#define regUMCCH1_3_PerfMonCtr8_Lo_BASE_IDX 1
+#define regUMCCH1_3_PerfMonCtr8_Hi 0x14075b
+#define regUMCCH1_3_PerfMonCtr8_Hi_BASE_IDX 1
+
+
+// addressBlock: umc_w_phy_umc3_umcch2_umcchdec
+// base address: 0x652000
+#define regUMCCH2_3_BaseAddrCS0 0x140800
+#define regUMCCH2_3_BaseAddrCS0_BASE_IDX 1
+#define regUMCCH2_3_AddrMaskCS01 0x140808
+#define regUMCCH2_3_AddrMaskCS01_BASE_IDX 1
+#define regUMCCH2_3_AddrSelCS01 0x140810
+#define regUMCCH2_3_AddrSelCS01_BASE_IDX 1
+#define regUMCCH2_3_AddrHashBank0 0x140832
+#define regUMCCH2_3_AddrHashBank0_BASE_IDX 1
+#define regUMCCH2_3_AddrHashBank1 0x140833
+#define regUMCCH2_3_AddrHashBank1_BASE_IDX 1
+#define regUMCCH2_3_AddrHashBank2 0x140834
+#define regUMCCH2_3_AddrHashBank2_BASE_IDX 1
+#define regUMCCH2_3_AddrHashBank3 0x140835
+#define regUMCCH2_3_AddrHashBank3_BASE_IDX 1
+#define regUMCCH2_3_AddrHashBank4 0x140836
+#define regUMCCH2_3_AddrHashBank4_BASE_IDX 1
+#define regUMCCH2_3_AddrHashBank5 0x140837
+#define regUMCCH2_3_AddrHashBank5_BASE_IDX 1
+#define regUMCCH2_3_EccErrCntSel 0x140b28
+#define regUMCCH2_3_EccErrCntSel_BASE_IDX 1
+#define regUMCCH2_3_EccErrCnt 0x140b29
+#define regUMCCH2_3_EccErrCnt_BASE_IDX 1
+#define regUMCCH2_3_PerfMonCtlClk 0x140b40
+#define regUMCCH2_3_PerfMonCtlClk_BASE_IDX 1
+#define regUMCCH2_3_PerfMonCtrClk_Lo 0x140b41
+#define regUMCCH2_3_PerfMonCtrClk_Lo_BASE_IDX 1
+#define regUMCCH2_3_PerfMonCtrClk_Hi 0x140b42
+#define regUMCCH2_3_PerfMonCtrClk_Hi_BASE_IDX 1
+#define regUMCCH2_3_PerfMonCtl1 0x140b44
+#define regUMCCH2_3_PerfMonCtl1_BASE_IDX 1
+#define regUMCCH2_3_PerfMonCtr1_Lo 0x140b45
+#define regUMCCH2_3_PerfMonCtr1_Lo_BASE_IDX 1
+#define regUMCCH2_3_PerfMonCtr1_Hi 0x140b46
+#define regUMCCH2_3_PerfMonCtr1_Hi_BASE_IDX 1
+#define regUMCCH2_3_PerfMonCtl2 0x140b47
+#define regUMCCH2_3_PerfMonCtl2_BASE_IDX 1
+#define regUMCCH2_3_PerfMonCtr2_Lo 0x140b48
+#define regUMCCH2_3_PerfMonCtr2_Lo_BASE_IDX 1
+#define regUMCCH2_3_PerfMonCtr2_Hi 0x140b49
+#define regUMCCH2_3_PerfMonCtr2_Hi_BASE_IDX 1
+#define regUMCCH2_3_PerfMonCtl3 0x140b4a
+#define regUMCCH2_3_PerfMonCtl3_BASE_IDX 1
+#define regUMCCH2_3_PerfMonCtr3_Lo 0x140b4b
+#define regUMCCH2_3_PerfMonCtr3_Lo_BASE_IDX 1
+#define regUMCCH2_3_PerfMonCtr3_Hi 0x140b4c
+#define regUMCCH2_3_PerfMonCtr3_Hi_BASE_IDX 1
+#define regUMCCH2_3_PerfMonCtl4 0x140b4d
+#define regUMCCH2_3_PerfMonCtl4_BASE_IDX 1
+#define regUMCCH2_3_PerfMonCtr4_Lo 0x140b4e
+#define regUMCCH2_3_PerfMonCtr4_Lo_BASE_IDX 1
+#define regUMCCH2_3_PerfMonCtr4_Hi 0x140b4f
+#define regUMCCH2_3_PerfMonCtr4_Hi_BASE_IDX 1
+#define regUMCCH2_3_PerfMonCtl5 0x140b50
+#define regUMCCH2_3_PerfMonCtl5_BASE_IDX 1
+#define regUMCCH2_3_PerfMonCtr5_Lo 0x140b51
+#define regUMCCH2_3_PerfMonCtr5_Lo_BASE_IDX 1
+#define regUMCCH2_3_PerfMonCtr5_Hi 0x140b52
+#define regUMCCH2_3_PerfMonCtr5_Hi_BASE_IDX 1
+#define regUMCCH2_3_PerfMonCtl6 0x140b53
+#define regUMCCH2_3_PerfMonCtl6_BASE_IDX 1
+#define regUMCCH2_3_PerfMonCtr6_Lo 0x140b54
+#define regUMCCH2_3_PerfMonCtr6_Lo_BASE_IDX 1
+#define regUMCCH2_3_PerfMonCtr6_Hi 0x140b55
+#define regUMCCH2_3_PerfMonCtr6_Hi_BASE_IDX 1
+#define regUMCCH2_3_PerfMonCtl7 0x140b56
+#define regUMCCH2_3_PerfMonCtl7_BASE_IDX 1
+#define regUMCCH2_3_PerfMonCtr7_Lo 0x140b57
+#define regUMCCH2_3_PerfMonCtr7_Lo_BASE_IDX 1
+#define regUMCCH2_3_PerfMonCtr7_Hi 0x140b58
+#define regUMCCH2_3_PerfMonCtr7_Hi_BASE_IDX 1
+#define regUMCCH2_3_PerfMonCtl8 0x140b59
+#define regUMCCH2_3_PerfMonCtl8_BASE_IDX 1
+#define regUMCCH2_3_PerfMonCtr8_Lo 0x140b5a
+#define regUMCCH2_3_PerfMonCtr8_Lo_BASE_IDX 1
+#define regUMCCH2_3_PerfMonCtr8_Hi 0x140b5b
+#define regUMCCH2_3_PerfMonCtr8_Hi_BASE_IDX 1
+
+
+// addressBlock: umc_w_phy_umc3_umcch3_umcchdec
+// base address: 0x653000
+#define regUMCCH3_3_BaseAddrCS0 0x140c00
+#define regUMCCH3_3_BaseAddrCS0_BASE_IDX 1
+#define regUMCCH3_3_AddrMaskCS01 0x140c08
+#define regUMCCH3_3_AddrMaskCS01_BASE_IDX 1
+#define regUMCCH3_3_AddrSelCS01 0x140c10
+#define regUMCCH3_3_AddrSelCS01_BASE_IDX 1
+#define regUMCCH3_3_AddrHashBank0 0x140c32
+#define regUMCCH3_3_AddrHashBank0_BASE_IDX 1
+#define regUMCCH3_3_AddrHashBank1 0x140c33
+#define regUMCCH3_3_AddrHashBank1_BASE_IDX 1
+#define regUMCCH3_3_AddrHashBank2 0x140c34
+#define regUMCCH3_3_AddrHashBank2_BASE_IDX 1
+#define regUMCCH3_3_AddrHashBank3 0x140c35
+#define regUMCCH3_3_AddrHashBank3_BASE_IDX 1
+#define regUMCCH3_3_AddrHashBank4 0x140c36
+#define regUMCCH3_3_AddrHashBank4_BASE_IDX 1
+#define regUMCCH3_3_AddrHashBank5 0x140c37
+#define regUMCCH3_3_AddrHashBank5_BASE_IDX 1
+#define regUMCCH3_3_EccErrCntSel 0x140f28
+#define regUMCCH3_3_EccErrCntSel_BASE_IDX 1
+#define regUMCCH3_3_EccErrCnt 0x140f29
+#define regUMCCH3_3_EccErrCnt_BASE_IDX 1
+#define regUMCCH3_3_PerfMonCtlClk 0x140f40
+#define regUMCCH3_3_PerfMonCtlClk_BASE_IDX 1
+#define regUMCCH3_3_PerfMonCtrClk_Lo 0x140f41
+#define regUMCCH3_3_PerfMonCtrClk_Lo_BASE_IDX 1
+#define regUMCCH3_3_PerfMonCtrClk_Hi 0x140f42
+#define regUMCCH3_3_PerfMonCtrClk_Hi_BASE_IDX 1
+#define regUMCCH3_3_PerfMonCtl1 0x140f44
+#define regUMCCH3_3_PerfMonCtl1_BASE_IDX 1
+#define regUMCCH3_3_PerfMonCtr1_Lo 0x140f45
+#define regUMCCH3_3_PerfMonCtr1_Lo_BASE_IDX 1
+#define regUMCCH3_3_PerfMonCtr1_Hi 0x140f46
+#define regUMCCH3_3_PerfMonCtr1_Hi_BASE_IDX 1
+#define regUMCCH3_3_PerfMonCtl2 0x140f47
+#define regUMCCH3_3_PerfMonCtl2_BASE_IDX 1
+#define regUMCCH3_3_PerfMonCtr2_Lo 0x140f48
+#define regUMCCH3_3_PerfMonCtr2_Lo_BASE_IDX 1
+#define regUMCCH3_3_PerfMonCtr2_Hi 0x140f49
+#define regUMCCH3_3_PerfMonCtr2_Hi_BASE_IDX 1
+#define regUMCCH3_3_PerfMonCtl3 0x140f4a
+#define regUMCCH3_3_PerfMonCtl3_BASE_IDX 1
+#define regUMCCH3_3_PerfMonCtr3_Lo 0x140f4b
+#define regUMCCH3_3_PerfMonCtr3_Lo_BASE_IDX 1
+#define regUMCCH3_3_PerfMonCtr3_Hi 0x140f4c
+#define regUMCCH3_3_PerfMonCtr3_Hi_BASE_IDX 1
+#define regUMCCH3_3_PerfMonCtl4 0x140f4d
+#define regUMCCH3_3_PerfMonCtl4_BASE_IDX 1
+#define regUMCCH3_3_PerfMonCtr4_Lo 0x140f4e
+#define regUMCCH3_3_PerfMonCtr4_Lo_BASE_IDX 1
+#define regUMCCH3_3_PerfMonCtr4_Hi 0x140f4f
+#define regUMCCH3_3_PerfMonCtr4_Hi_BASE_IDX 1
+#define regUMCCH3_3_PerfMonCtl5 0x140f50
+#define regUMCCH3_3_PerfMonCtl5_BASE_IDX 1
+#define regUMCCH3_3_PerfMonCtr5_Lo 0x140f51
+#define regUMCCH3_3_PerfMonCtr5_Lo_BASE_IDX 1
+#define regUMCCH3_3_PerfMonCtr5_Hi 0x140f52
+#define regUMCCH3_3_PerfMonCtr5_Hi_BASE_IDX 1
+#define regUMCCH3_3_PerfMonCtl6 0x140f53
+#define regUMCCH3_3_PerfMonCtl6_BASE_IDX 1
+#define regUMCCH3_3_PerfMonCtr6_Lo 0x140f54
+#define regUMCCH3_3_PerfMonCtr6_Lo_BASE_IDX 1
+#define regUMCCH3_3_PerfMonCtr6_Hi 0x140f55
+#define regUMCCH3_3_PerfMonCtr6_Hi_BASE_IDX 1
+#define regUMCCH3_3_PerfMonCtl7 0x140f56
+#define regUMCCH3_3_PerfMonCtl7_BASE_IDX 1
+#define regUMCCH3_3_PerfMonCtr7_Lo 0x140f57
+#define regUMCCH3_3_PerfMonCtr7_Lo_BASE_IDX 1
+#define regUMCCH3_3_PerfMonCtr7_Hi 0x140f58
+#define regUMCCH3_3_PerfMonCtr7_Hi_BASE_IDX 1
+#define regUMCCH3_3_PerfMonCtl8 0x140f59
+#define regUMCCH3_3_PerfMonCtl8_BASE_IDX 1
+#define regUMCCH3_3_PerfMonCtr8_Lo 0x140f5a
+#define regUMCCH3_3_PerfMonCtr8_Lo_BASE_IDX 1
+#define regUMCCH3_3_PerfMonCtr8_Hi 0x140f5b
+#define regUMCCH3_3_PerfMonCtr8_Hi_BASE_IDX 1
+
+
+// addressBlock: umc_w_phy_umc3_umcch4_umcchdec
+// base address: 0x750000
+#define regUMCCH4_3_BaseAddrCS0 0x180000
+#define regUMCCH4_3_BaseAddrCS0_BASE_IDX 1
+#define regUMCCH4_3_AddrMaskCS01 0x180008
+#define regUMCCH4_3_AddrMaskCS01_BASE_IDX 1
+#define regUMCCH4_3_AddrSelCS01 0x180010
+#define regUMCCH4_3_AddrSelCS01_BASE_IDX 1
+#define regUMCCH4_3_AddrHashBank0 0x180032
+#define regUMCCH4_3_AddrHashBank0_BASE_IDX 1
+#define regUMCCH4_3_AddrHashBank1 0x180033
+#define regUMCCH4_3_AddrHashBank1_BASE_IDX 1
+#define regUMCCH4_3_AddrHashBank2 0x180034
+#define regUMCCH4_3_AddrHashBank2_BASE_IDX 1
+#define regUMCCH4_3_AddrHashBank3 0x180035
+#define regUMCCH4_3_AddrHashBank3_BASE_IDX 1
+#define regUMCCH4_3_AddrHashBank4 0x180036
+#define regUMCCH4_3_AddrHashBank4_BASE_IDX 1
+#define regUMCCH4_3_AddrHashBank5 0x180037
+#define regUMCCH4_3_AddrHashBank5_BASE_IDX 1
+#define regUMCCH4_3_EccErrCntSel 0x180328
+#define regUMCCH4_3_EccErrCntSel_BASE_IDX 1
+#define regUMCCH4_3_EccErrCnt 0x180329
+#define regUMCCH4_3_EccErrCnt_BASE_IDX 1
+#define regUMCCH4_3_PerfMonCtlClk 0x180340
+#define regUMCCH4_3_PerfMonCtlClk_BASE_IDX 1
+#define regUMCCH4_3_PerfMonCtrClk_Lo 0x180341
+#define regUMCCH4_3_PerfMonCtrClk_Lo_BASE_IDX 1
+#define regUMCCH4_3_PerfMonCtrClk_Hi 0x180342
+#define regUMCCH4_3_PerfMonCtrClk_Hi_BASE_IDX 1
+#define regUMCCH4_3_PerfMonCtl1 0x180344
+#define regUMCCH4_3_PerfMonCtl1_BASE_IDX 1
+#define regUMCCH4_3_PerfMonCtr1_Lo 0x180345
+#define regUMCCH4_3_PerfMonCtr1_Lo_BASE_IDX 1
+#define regUMCCH4_3_PerfMonCtr1_Hi 0x180346
+#define regUMCCH4_3_PerfMonCtr1_Hi_BASE_IDX 1
+#define regUMCCH4_3_PerfMonCtl2 0x180347
+#define regUMCCH4_3_PerfMonCtl2_BASE_IDX 1
+#define regUMCCH4_3_PerfMonCtr2_Lo 0x180348
+#define regUMCCH4_3_PerfMonCtr2_Lo_BASE_IDX 1
+#define regUMCCH4_3_PerfMonCtr2_Hi 0x180349
+#define regUMCCH4_3_PerfMonCtr2_Hi_BASE_IDX 1
+#define regUMCCH4_3_PerfMonCtl3 0x18034a
+#define regUMCCH4_3_PerfMonCtl3_BASE_IDX 1
+#define regUMCCH4_3_PerfMonCtr3_Lo 0x18034b
+#define regUMCCH4_3_PerfMonCtr3_Lo_BASE_IDX 1
+#define regUMCCH4_3_PerfMonCtr3_Hi 0x18034c
+#define regUMCCH4_3_PerfMonCtr3_Hi_BASE_IDX 1
+#define regUMCCH4_3_PerfMonCtl4 0x18034d
+#define regUMCCH4_3_PerfMonCtl4_BASE_IDX 1
+#define regUMCCH4_3_PerfMonCtr4_Lo 0x18034e
+#define regUMCCH4_3_PerfMonCtr4_Lo_BASE_IDX 1
+#define regUMCCH4_3_PerfMonCtr4_Hi 0x18034f
+#define regUMCCH4_3_PerfMonCtr4_Hi_BASE_IDX 1
+#define regUMCCH4_3_PerfMonCtl5 0x180350
+#define regUMCCH4_3_PerfMonCtl5_BASE_IDX 1
+#define regUMCCH4_3_PerfMonCtr5_Lo 0x180351
+#define regUMCCH4_3_PerfMonCtr5_Lo_BASE_IDX 1
+#define regUMCCH4_3_PerfMonCtr5_Hi 0x180352
+#define regUMCCH4_3_PerfMonCtr5_Hi_BASE_IDX 1
+#define regUMCCH4_3_PerfMonCtl6 0x180353
+#define regUMCCH4_3_PerfMonCtl6_BASE_IDX 1
+#define regUMCCH4_3_PerfMonCtr6_Lo 0x180354
+#define regUMCCH4_3_PerfMonCtr6_Lo_BASE_IDX 1
+#define regUMCCH4_3_PerfMonCtr6_Hi 0x180355
+#define regUMCCH4_3_PerfMonCtr6_Hi_BASE_IDX 1
+#define regUMCCH4_3_PerfMonCtl7 0x180356
+#define regUMCCH4_3_PerfMonCtl7_BASE_IDX 1
+#define regUMCCH4_3_PerfMonCtr7_Lo 0x180357
+#define regUMCCH4_3_PerfMonCtr7_Lo_BASE_IDX 1
+#define regUMCCH4_3_PerfMonCtr7_Hi 0x180358
+#define regUMCCH4_3_PerfMonCtr7_Hi_BASE_IDX 1
+#define regUMCCH4_3_PerfMonCtl8 0x180359
+#define regUMCCH4_3_PerfMonCtl8_BASE_IDX 1
+#define regUMCCH4_3_PerfMonCtr8_Lo 0x18035a
+#define regUMCCH4_3_PerfMonCtr8_Lo_BASE_IDX 1
+#define regUMCCH4_3_PerfMonCtr8_Hi 0x18035b
+#define regUMCCH4_3_PerfMonCtr8_Hi_BASE_IDX 1
+
+
+// addressBlock: umc_w_phy_umc3_umcch5_umcchdec
+// base address: 0x751000
+#define regUMCCH5_3_BaseAddrCS0 0x180400
+#define regUMCCH5_3_BaseAddrCS0_BASE_IDX 1
+#define regUMCCH5_3_AddrMaskCS01 0x180408
+#define regUMCCH5_3_AddrMaskCS01_BASE_IDX 1
+#define regUMCCH5_3_AddrSelCS01 0x180410
+#define regUMCCH5_3_AddrSelCS01_BASE_IDX 1
+#define regUMCCH5_3_AddrHashBank0 0x180432
+#define regUMCCH5_3_AddrHashBank0_BASE_IDX 1
+#define regUMCCH5_3_AddrHashBank1 0x180433
+#define regUMCCH5_3_AddrHashBank1_BASE_IDX 1
+#define regUMCCH5_3_AddrHashBank2 0x180434
+#define regUMCCH5_3_AddrHashBank2_BASE_IDX 1
+#define regUMCCH5_3_AddrHashBank3 0x180435
+#define regUMCCH5_3_AddrHashBank3_BASE_IDX 1
+#define regUMCCH5_3_AddrHashBank4 0x180436
+#define regUMCCH5_3_AddrHashBank4_BASE_IDX 1
+#define regUMCCH5_3_AddrHashBank5 0x180437
+#define regUMCCH5_3_AddrHashBank5_BASE_IDX 1
+#define regUMCCH5_3_EccErrCntSel 0x180728
+#define regUMCCH5_3_EccErrCntSel_BASE_IDX 1
+#define regUMCCH5_3_EccErrCnt 0x180729
+#define regUMCCH5_3_EccErrCnt_BASE_IDX 1
+#define regUMCCH5_3_PerfMonCtlClk 0x180740
+#define regUMCCH5_3_PerfMonCtlClk_BASE_IDX 1
+#define regUMCCH5_3_PerfMonCtrClk_Lo 0x180741
+#define regUMCCH5_3_PerfMonCtrClk_Lo_BASE_IDX 1
+#define regUMCCH5_3_PerfMonCtrClk_Hi 0x180742
+#define regUMCCH5_3_PerfMonCtrClk_Hi_BASE_IDX 1
+#define regUMCCH5_3_PerfMonCtl1 0x180744
+#define regUMCCH5_3_PerfMonCtl1_BASE_IDX 1
+#define regUMCCH5_3_PerfMonCtr1_Lo 0x180745
+#define regUMCCH5_3_PerfMonCtr1_Lo_BASE_IDX 1
+#define regUMCCH5_3_PerfMonCtr1_Hi 0x180746
+#define regUMCCH5_3_PerfMonCtr1_Hi_BASE_IDX 1
+#define regUMCCH5_3_PerfMonCtl2 0x180747
+#define regUMCCH5_3_PerfMonCtl2_BASE_IDX 1
+#define regUMCCH5_3_PerfMonCtr2_Lo 0x180748
+#define regUMCCH5_3_PerfMonCtr2_Lo_BASE_IDX 1
+#define regUMCCH5_3_PerfMonCtr2_Hi 0x180749
+#define regUMCCH5_3_PerfMonCtr2_Hi_BASE_IDX 1
+#define regUMCCH5_3_PerfMonCtl3 0x18074a
+#define regUMCCH5_3_PerfMonCtl3_BASE_IDX 1
+#define regUMCCH5_3_PerfMonCtr3_Lo 0x18074b
+#define regUMCCH5_3_PerfMonCtr3_Lo_BASE_IDX 1
+#define regUMCCH5_3_PerfMonCtr3_Hi 0x18074c
+#define regUMCCH5_3_PerfMonCtr3_Hi_BASE_IDX 1
+#define regUMCCH5_3_PerfMonCtl4 0x18074d
+#define regUMCCH5_3_PerfMonCtl4_BASE_IDX 1
+#define regUMCCH5_3_PerfMonCtr4_Lo 0x18074e
+#define regUMCCH5_3_PerfMonCtr4_Lo_BASE_IDX 1
+#define regUMCCH5_3_PerfMonCtr4_Hi 0x18074f
+#define regUMCCH5_3_PerfMonCtr4_Hi_BASE_IDX 1
+#define regUMCCH5_3_PerfMonCtl5 0x180750
+#define regUMCCH5_3_PerfMonCtl5_BASE_IDX 1
+#define regUMCCH5_3_PerfMonCtr5_Lo 0x180751
+#define regUMCCH5_3_PerfMonCtr5_Lo_BASE_IDX 1
+#define regUMCCH5_3_PerfMonCtr5_Hi 0x180752
+#define regUMCCH5_3_PerfMonCtr5_Hi_BASE_IDX 1
+#define regUMCCH5_3_PerfMonCtl6 0x180753
+#define regUMCCH5_3_PerfMonCtl6_BASE_IDX 1
+#define regUMCCH5_3_PerfMonCtr6_Lo 0x180754
+#define regUMCCH5_3_PerfMonCtr6_Lo_BASE_IDX 1
+#define regUMCCH5_3_PerfMonCtr6_Hi 0x180755
+#define regUMCCH5_3_PerfMonCtr6_Hi_BASE_IDX 1
+#define regUMCCH5_3_PerfMonCtl7 0x180756
+#define regUMCCH5_3_PerfMonCtl7_BASE_IDX 1
+#define regUMCCH5_3_PerfMonCtr7_Lo 0x180757
+#define regUMCCH5_3_PerfMonCtr7_Lo_BASE_IDX 1
+#define regUMCCH5_3_PerfMonCtr7_Hi 0x180758
+#define regUMCCH5_3_PerfMonCtr7_Hi_BASE_IDX 1
+#define regUMCCH5_3_PerfMonCtl8 0x180759
+#define regUMCCH5_3_PerfMonCtl8_BASE_IDX 1
+#define regUMCCH5_3_PerfMonCtr8_Lo 0x18075a
+#define regUMCCH5_3_PerfMonCtr8_Lo_BASE_IDX 1
+#define regUMCCH5_3_PerfMonCtr8_Hi 0x18075b
+#define regUMCCH5_3_PerfMonCtr8_Hi_BASE_IDX 1
+
+
+// addressBlock: umc_w_phy_umc3_umcch6_umcchdec
+// base address: 0x752000
+#define regUMCCH6_3_BaseAddrCS0 0x180800
+#define regUMCCH6_3_BaseAddrCS0_BASE_IDX 1
+#define regUMCCH6_3_AddrMaskCS01 0x180808
+#define regUMCCH6_3_AddrMaskCS01_BASE_IDX 1
+#define regUMCCH6_3_AddrSelCS01 0x180810
+#define regUMCCH6_3_AddrSelCS01_BASE_IDX 1
+#define regUMCCH6_3_AddrHashBank0 0x180832
+#define regUMCCH6_3_AddrHashBank0_BASE_IDX 1
+#define regUMCCH6_3_AddrHashBank1 0x180833
+#define regUMCCH6_3_AddrHashBank1_BASE_IDX 1
+#define regUMCCH6_3_AddrHashBank2 0x180834
+#define regUMCCH6_3_AddrHashBank2_BASE_IDX 1
+#define regUMCCH6_3_AddrHashBank3 0x180835
+#define regUMCCH6_3_AddrHashBank3_BASE_IDX 1
+#define regUMCCH6_3_AddrHashBank4 0x180836
+#define regUMCCH6_3_AddrHashBank4_BASE_IDX 1
+#define regUMCCH6_3_AddrHashBank5 0x180837
+#define regUMCCH6_3_AddrHashBank5_BASE_IDX 1
+#define regUMCCH6_3_EccErrCntSel 0x180b28
+#define regUMCCH6_3_EccErrCntSel_BASE_IDX 1
+#define regUMCCH6_3_EccErrCnt 0x180b29
+#define regUMCCH6_3_EccErrCnt_BASE_IDX 1
+#define regUMCCH6_3_PerfMonCtlClk 0x180b40
+#define regUMCCH6_3_PerfMonCtlClk_BASE_IDX 1
+#define regUMCCH6_3_PerfMonCtrClk_Lo 0x180b41
+#define regUMCCH6_3_PerfMonCtrClk_Lo_BASE_IDX 1
+#define regUMCCH6_3_PerfMonCtrClk_Hi 0x180b42
+#define regUMCCH6_3_PerfMonCtrClk_Hi_BASE_IDX 1
+#define regUMCCH6_3_PerfMonCtl1 0x180b44
+#define regUMCCH6_3_PerfMonCtl1_BASE_IDX 1
+#define regUMCCH6_3_PerfMonCtr1_Lo 0x180b45
+#define regUMCCH6_3_PerfMonCtr1_Lo_BASE_IDX 1
+#define regUMCCH6_3_PerfMonCtr1_Hi 0x180b46
+#define regUMCCH6_3_PerfMonCtr1_Hi_BASE_IDX 1
+#define regUMCCH6_3_PerfMonCtl2 0x180b47
+#define regUMCCH6_3_PerfMonCtl2_BASE_IDX 1
+#define regUMCCH6_3_PerfMonCtr2_Lo 0x180b48
+#define regUMCCH6_3_PerfMonCtr2_Lo_BASE_IDX 1
+#define regUMCCH6_3_PerfMonCtr2_Hi 0x180b49
+#define regUMCCH6_3_PerfMonCtr2_Hi_BASE_IDX 1
+#define regUMCCH6_3_PerfMonCtl3 0x180b4a
+#define regUMCCH6_3_PerfMonCtl3_BASE_IDX 1
+#define regUMCCH6_3_PerfMonCtr3_Lo 0x180b4b
+#define regUMCCH6_3_PerfMonCtr3_Lo_BASE_IDX 1
+#define regUMCCH6_3_PerfMonCtr3_Hi 0x180b4c
+#define regUMCCH6_3_PerfMonCtr3_Hi_BASE_IDX 1
+#define regUMCCH6_3_PerfMonCtl4 0x180b4d
+#define regUMCCH6_3_PerfMonCtl4_BASE_IDX 1
+#define regUMCCH6_3_PerfMonCtr4_Lo 0x180b4e
+#define regUMCCH6_3_PerfMonCtr4_Lo_BASE_IDX 1
+#define regUMCCH6_3_PerfMonCtr4_Hi 0x180b4f
+#define regUMCCH6_3_PerfMonCtr4_Hi_BASE_IDX 1
+#define regUMCCH6_3_PerfMonCtl5 0x180b50
+#define regUMCCH6_3_PerfMonCtl5_BASE_IDX 1
+#define regUMCCH6_3_PerfMonCtr5_Lo 0x180b51
+#define regUMCCH6_3_PerfMonCtr5_Lo_BASE_IDX 1
+#define regUMCCH6_3_PerfMonCtr5_Hi 0x180b52
+#define regUMCCH6_3_PerfMonCtr5_Hi_BASE_IDX 1
+#define regUMCCH6_3_PerfMonCtl6 0x180b53
+#define regUMCCH6_3_PerfMonCtl6_BASE_IDX 1
+#define regUMCCH6_3_PerfMonCtr6_Lo 0x180b54
+#define regUMCCH6_3_PerfMonCtr6_Lo_BASE_IDX 1
+#define regUMCCH6_3_PerfMonCtr6_Hi 0x180b55
+#define regUMCCH6_3_PerfMonCtr6_Hi_BASE_IDX 1
+#define regUMCCH6_3_PerfMonCtl7 0x180b56
+#define regUMCCH6_3_PerfMonCtl7_BASE_IDX 1
+#define regUMCCH6_3_PerfMonCtr7_Lo 0x180b57
+#define regUMCCH6_3_PerfMonCtr7_Lo_BASE_IDX 1
+#define regUMCCH6_3_PerfMonCtr7_Hi 0x180b58
+#define regUMCCH6_3_PerfMonCtr7_Hi_BASE_IDX 1
+#define regUMCCH6_3_PerfMonCtl8 0x180b59
+#define regUMCCH6_3_PerfMonCtl8_BASE_IDX 1
+#define regUMCCH6_3_PerfMonCtr8_Lo 0x180b5a
+#define regUMCCH6_3_PerfMonCtr8_Lo_BASE_IDX 1
+#define regUMCCH6_3_PerfMonCtr8_Hi 0x180b5b
+#define regUMCCH6_3_PerfMonCtr8_Hi_BASE_IDX 1
+
+
+// addressBlock: umc_w_phy_umc3_umcch7_umcchdec
+// base address: 0x753000
+#define regUMCCH7_3_BaseAddrCS0 0x180c00
+#define regUMCCH7_3_BaseAddrCS0_BASE_IDX 1
+#define regUMCCH7_3_AddrMaskCS01 0x180c08
+#define regUMCCH7_3_AddrMaskCS01_BASE_IDX 1
+#define regUMCCH7_3_AddrSelCS01 0x180c10
+#define regUMCCH7_3_AddrSelCS01_BASE_IDX 1
+#define regUMCCH7_3_AddrHashBank0 0x180c32
+#define regUMCCH7_3_AddrHashBank0_BASE_IDX 1
+#define regUMCCH7_3_AddrHashBank1 0x180c33
+#define regUMCCH7_3_AddrHashBank1_BASE_IDX 1
+#define regUMCCH7_3_AddrHashBank2 0x180c34
+#define regUMCCH7_3_AddrHashBank2_BASE_IDX 1
+#define regUMCCH7_3_AddrHashBank3 0x180c35
+#define regUMCCH7_3_AddrHashBank3_BASE_IDX 1
+#define regUMCCH7_3_AddrHashBank4 0x180c36
+#define regUMCCH7_3_AddrHashBank4_BASE_IDX 1
+#define regUMCCH7_3_AddrHashBank5 0x180c37
+#define regUMCCH7_3_AddrHashBank5_BASE_IDX 1
+#define regUMCCH7_3_EccErrCntSel 0x180f28
+#define regUMCCH7_3_EccErrCntSel_BASE_IDX 1
+#define regUMCCH7_3_EccErrCnt 0x180f29
+#define regUMCCH7_3_EccErrCnt_BASE_IDX 1
+#define regUMCCH7_3_PerfMonCtlClk 0x180f40
+#define regUMCCH7_3_PerfMonCtlClk_BASE_IDX 1
+#define regUMCCH7_3_PerfMonCtrClk_Lo 0x180f41
+#define regUMCCH7_3_PerfMonCtrClk_Lo_BASE_IDX 1
+#define regUMCCH7_3_PerfMonCtrClk_Hi 0x180f42
+#define regUMCCH7_3_PerfMonCtrClk_Hi_BASE_IDX 1
+#define regUMCCH7_3_PerfMonCtl1 0x180f44
+#define regUMCCH7_3_PerfMonCtl1_BASE_IDX 1
+#define regUMCCH7_3_PerfMonCtr1_Lo 0x180f45
+#define regUMCCH7_3_PerfMonCtr1_Lo_BASE_IDX 1
+#define regUMCCH7_3_PerfMonCtr1_Hi 0x180f46
+#define regUMCCH7_3_PerfMonCtr1_Hi_BASE_IDX 1
+#define regUMCCH7_3_PerfMonCtl2 0x180f47
+#define regUMCCH7_3_PerfMonCtl2_BASE_IDX 1
+#define regUMCCH7_3_PerfMonCtr2_Lo 0x180f48
+#define regUMCCH7_3_PerfMonCtr2_Lo_BASE_IDX 1
+#define regUMCCH7_3_PerfMonCtr2_Hi 0x180f49
+#define regUMCCH7_3_PerfMonCtr2_Hi_BASE_IDX 1
+#define regUMCCH7_3_PerfMonCtl3 0x180f4a
+#define regUMCCH7_3_PerfMonCtl3_BASE_IDX 1
+#define regUMCCH7_3_PerfMonCtr3_Lo 0x180f4b
+#define regUMCCH7_3_PerfMonCtr3_Lo_BASE_IDX 1
+#define regUMCCH7_3_PerfMonCtr3_Hi 0x180f4c
+#define regUMCCH7_3_PerfMonCtr3_Hi_BASE_IDX 1
+#define regUMCCH7_3_PerfMonCtl4 0x180f4d
+#define regUMCCH7_3_PerfMonCtl4_BASE_IDX 1
+#define regUMCCH7_3_PerfMonCtr4_Lo 0x180f4e
+#define regUMCCH7_3_PerfMonCtr4_Lo_BASE_IDX 1
+#define regUMCCH7_3_PerfMonCtr4_Hi 0x180f4f
+#define regUMCCH7_3_PerfMonCtr4_Hi_BASE_IDX 1
+#define regUMCCH7_3_PerfMonCtl5 0x180f50
+#define regUMCCH7_3_PerfMonCtl5_BASE_IDX 1
+#define regUMCCH7_3_PerfMonCtr5_Lo 0x180f51
+#define regUMCCH7_3_PerfMonCtr5_Lo_BASE_IDX 1
+#define regUMCCH7_3_PerfMonCtr5_Hi 0x180f52
+#define regUMCCH7_3_PerfMonCtr5_Hi_BASE_IDX 1
+#define regUMCCH7_3_PerfMonCtl6 0x180f53
+#define regUMCCH7_3_PerfMonCtl6_BASE_IDX 1
+#define regUMCCH7_3_PerfMonCtr6_Lo 0x180f54
+#define regUMCCH7_3_PerfMonCtr6_Lo_BASE_IDX 1
+#define regUMCCH7_3_PerfMonCtr6_Hi 0x180f55
+#define regUMCCH7_3_PerfMonCtr6_Hi_BASE_IDX 1
+#define regUMCCH7_3_PerfMonCtl7 0x180f56
+#define regUMCCH7_3_PerfMonCtl7_BASE_IDX 1
+#define regUMCCH7_3_PerfMonCtr7_Lo 0x180f57
+#define regUMCCH7_3_PerfMonCtr7_Lo_BASE_IDX 1
+#define regUMCCH7_3_PerfMonCtr7_Hi 0x180f58
+#define regUMCCH7_3_PerfMonCtr7_Hi_BASE_IDX 1
+#define regUMCCH7_3_PerfMonCtl8 0x180f59
+#define regUMCCH7_3_PerfMonCtl8_BASE_IDX 1
+#define regUMCCH7_3_PerfMonCtr8_Lo 0x180f5a
+#define regUMCCH7_3_PerfMonCtr8_Lo_BASE_IDX 1
+#define regUMCCH7_3_PerfMonCtr8_Hi 0x180f5b
+#define regUMCCH7_3_PerfMonCtr8_Hi_BASE_IDX 1
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_7_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_7_0_sh_mask.h
new file mode 100644
index 000000000000..da5a0968d7cb
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_7_0_sh_mask.h
@@ -0,0 +1,10796 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef _umc_6_7_0_SH_MASK_HEADER
+#define _umc_6_7_0_SH_MASK_HEADER
+
+
+// addressBlock: umc_w_phy_umc0_mca_ip_umc0_mca_map
+//MCA_UMC_UMC0_MCUMC_STATUST0
+#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCode__SHIFT 0x0
+#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCodeExt__SHIFT 0x10
+#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV22__SHIFT 0x16
+#define MCA_UMC_UMC0_MCUMC_STATUST0__AddrLsb__SHIFT 0x18
+#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV30__SHIFT 0x1e
+#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreId__SHIFT 0x20
+#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV38__SHIFT 0x26
+#define MCA_UMC_UMC0_MCUMC_STATUST0__Scrub__SHIFT 0x28
+#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV41__SHIFT 0x29
+#define MCA_UMC_UMC0_MCUMC_STATUST0__Poison__SHIFT 0x2b
+#define MCA_UMC_UMC0_MCUMC_STATUST0__Deferred__SHIFT 0x2c
+#define MCA_UMC_UMC0_MCUMC_STATUST0__UECC__SHIFT 0x2d
+#define MCA_UMC_UMC0_MCUMC_STATUST0__CECC__SHIFT 0x2e
+#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV47__SHIFT 0x2f
+#define MCA_UMC_UMC0_MCUMC_STATUST0__Transparent__SHIFT 0x34
+#define MCA_UMC_UMC0_MCUMC_STATUST0__SyndV__SHIFT 0x35
+#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV54__SHIFT 0x36
+#define MCA_UMC_UMC0_MCUMC_STATUST0__TCC__SHIFT 0x37
+#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreIdVal__SHIFT 0x38
+#define MCA_UMC_UMC0_MCUMC_STATUST0__PCC__SHIFT 0x39
+#define MCA_UMC_UMC0_MCUMC_STATUST0__AddrV__SHIFT 0x3a
+#define MCA_UMC_UMC0_MCUMC_STATUST0__MiscV__SHIFT 0x3b
+#define MCA_UMC_UMC0_MCUMC_STATUST0__En__SHIFT 0x3c
+#define MCA_UMC_UMC0_MCUMC_STATUST0__UC__SHIFT 0x3d
+#define MCA_UMC_UMC0_MCUMC_STATUST0__Overflow__SHIFT 0x3e
+#define MCA_UMC_UMC0_MCUMC_STATUST0__Val__SHIFT 0x3f
+#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCode_MASK 0x000000000000FFFFL
+#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCodeExt_MASK 0x00000000003F0000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV22_MASK 0x0000000000C00000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__AddrLsb_MASK 0x000000003F000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV30_MASK 0x00000000C0000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreId_MASK 0x0000003F00000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV38_MASK 0x000000C000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__Scrub_MASK 0x0000010000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV41_MASK 0x0000060000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__Poison_MASK 0x0000080000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__Deferred_MASK 0x0000100000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__UECC_MASK 0x0000200000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__CECC_MASK 0x0000400000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV47_MASK 0x000F800000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__Transparent_MASK 0x0010000000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__SyndV_MASK 0x0020000000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV54_MASK 0x0040000000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__TCC_MASK 0x0080000000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreIdVal_MASK 0x0100000000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__PCC_MASK 0x0200000000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__AddrV_MASK 0x0400000000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__MiscV_MASK 0x0800000000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__En_MASK 0x1000000000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__UC_MASK 0x2000000000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__Overflow_MASK 0x4000000000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__Val_MASK 0x8000000000000000L
+//MCA_UMC_UMC0_MCUMC_ADDRT0
+#define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr__SHIFT 0x0
+#define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved__SHIFT 0x38
+#define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr_MASK 0x00FFFFFFFFFFFFFFL
+#define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved_MASK 0xFF00000000000000L
+
+
+// addressBlock: umc_w_phy_umc0_umcch0_umcchdec
+//UMCCH0_0_BaseAddrCS0
+#define UMCCH0_0_BaseAddrCS0__CSEnable__SHIFT 0x0
+#define UMCCH0_0_BaseAddrCS0__BaseAddr__SHIFT 0x1
+#define UMCCH0_0_BaseAddrCS0__CSEnable_MASK 0x00000001L
+#define UMCCH0_0_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL
+//UMCCH0_0_AddrMaskCS01
+#define UMCCH0_0_AddrMaskCS01__AddrMask__SHIFT 0x1
+#define UMCCH0_0_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL
+//UMCCH0_0_AddrSelCS01
+#define UMCCH0_0_AddrSelCS01__BankBit0__SHIFT 0x0
+#define UMCCH0_0_AddrSelCS01__BankBit1__SHIFT 0x4
+#define UMCCH0_0_AddrSelCS01__BankBit2__SHIFT 0x8
+#define UMCCH0_0_AddrSelCS01__BankBit3__SHIFT 0xc
+#define UMCCH0_0_AddrSelCS01__BankBit4__SHIFT 0x10
+#define UMCCH0_0_AddrSelCS01__RowLo__SHIFT 0x18
+#define UMCCH0_0_AddrSelCS01__RowHi__SHIFT 0x1c
+#define UMCCH0_0_AddrSelCS01__BankBit0_MASK 0x0000000FL
+#define UMCCH0_0_AddrSelCS01__BankBit1_MASK 0x000000F0L
+#define UMCCH0_0_AddrSelCS01__BankBit2_MASK 0x00000F00L
+#define UMCCH0_0_AddrSelCS01__BankBit3_MASK 0x0000F000L
+#define UMCCH0_0_AddrSelCS01__BankBit4_MASK 0x001F0000L
+#define UMCCH0_0_AddrSelCS01__RowLo_MASK 0x0F000000L
+#define UMCCH0_0_AddrSelCS01__RowHi_MASK 0xF0000000L
+//UMCCH0_0_AddrHashBank0
+#define UMCCH0_0_AddrHashBank0__XorEnable__SHIFT 0x0
+#define UMCCH0_0_AddrHashBank0__ColXor__SHIFT 0x1
+#define UMCCH0_0_AddrHashBank0__RowXor__SHIFT 0xe
+#define UMCCH0_0_AddrHashBank0__XorEnable_MASK 0x00000001L
+#define UMCCH0_0_AddrHashBank0__ColXor_MASK 0x00003FFEL
+#define UMCCH0_0_AddrHashBank0__RowXor_MASK 0xFFFFC000L
+//UMCCH0_0_AddrHashBank1
+#define UMCCH0_0_AddrHashBank1__XorEnable__SHIFT 0x0
+#define UMCCH0_0_AddrHashBank1__ColXor__SHIFT 0x1
+#define UMCCH0_0_AddrHashBank1__RowXor__SHIFT 0xe
+#define UMCCH0_0_AddrHashBank1__XorEnable_MASK 0x00000001L
+#define UMCCH0_0_AddrHashBank1__ColXor_MASK 0x00003FFEL
+#define UMCCH0_0_AddrHashBank1__RowXor_MASK 0xFFFFC000L
+//UMCCH0_0_AddrHashBank2
+#define UMCCH0_0_AddrHashBank2__XorEnable__SHIFT 0x0
+#define UMCCH0_0_AddrHashBank2__ColXor__SHIFT 0x1
+#define UMCCH0_0_AddrHashBank2__RowXor__SHIFT 0xe
+#define UMCCH0_0_AddrHashBank2__XorEnable_MASK 0x00000001L
+#define UMCCH0_0_AddrHashBank2__ColXor_MASK 0x00003FFEL
+#define UMCCH0_0_AddrHashBank2__RowXor_MASK 0xFFFFC000L
+//UMCCH0_0_AddrHashBank3
+#define UMCCH0_0_AddrHashBank3__XorEnable__SHIFT 0x0
+#define UMCCH0_0_AddrHashBank3__ColXor__SHIFT 0x1
+#define UMCCH0_0_AddrHashBank3__RowXor__SHIFT 0xe
+#define UMCCH0_0_AddrHashBank3__XorEnable_MASK 0x00000001L
+#define UMCCH0_0_AddrHashBank3__ColXor_MASK 0x00003FFEL
+#define UMCCH0_0_AddrHashBank3__RowXor_MASK 0xFFFFC000L
+//UMCCH0_0_AddrHashBank4
+#define UMCCH0_0_AddrHashBank4__XorEnable__SHIFT 0x0
+#define UMCCH0_0_AddrHashBank4__ColXor__SHIFT 0x1
+#define UMCCH0_0_AddrHashBank4__RowXor__SHIFT 0xe
+#define UMCCH0_0_AddrHashBank4__XorEnable_MASK 0x00000001L
+#define UMCCH0_0_AddrHashBank4__ColXor_MASK 0x00003FFEL
+#define UMCCH0_0_AddrHashBank4__RowXor_MASK 0xFFFFC000L
+//UMCCH0_0_AddrHashBank5
+#define UMCCH0_0_AddrHashBank5__XorEnable__SHIFT 0x0
+#define UMCCH0_0_AddrHashBank5__ColXor__SHIFT 0x1
+#define UMCCH0_0_AddrHashBank5__RowXor__SHIFT 0xe
+#define UMCCH0_0_AddrHashBank5__XorEnable_MASK 0x00000001L
+#define UMCCH0_0_AddrHashBank5__ColXor_MASK 0x00003FFEL
+#define UMCCH0_0_AddrHashBank5__RowXor_MASK 0xFFFFC000L
+//UMCCH0_0_UMC_CONFIG
+#define UMCCH0_0_UMC_CONFIG__DDR_TYPE__SHIFT 0x0
+#define UMCCH0_0_UMC_CONFIG__BurstLength__SHIFT 0x8
+#define UMCCH0_0_UMC_CONFIG__BurstCtrl__SHIFT 0xa
+#define UMCCH0_0_UMC_CONFIG__DramReady__SHIFT 0x1f
+#define UMCCH0_0_UMC_CONFIG__DDR_TYPE_MASK 0x00000007L
+#define UMCCH0_0_UMC_CONFIG__BurstLength_MASK 0x00000300L
+#define UMCCH0_0_UMC_CONFIG__BurstCtrl_MASK 0x00000C00L
+#define UMCCH0_0_UMC_CONFIG__DramReady_MASK 0x80000000L
+//UMCCH0_0_EccCtrl
+#define UMCCH0_0_EccCtrl__WrEccEn__SHIFT 0x0
+#define UMCCH0_0_EccCtrl__EccReplayEn__SHIFT 0x1
+#define UMCCH0_0_EccCtrl__UCFatalEn__SHIFT 0x8
+#define UMCCH0_0_EccCtrl__RdEccEn__SHIFT 0xa
+#define UMCCH0_0_EccCtrl__PoisonFatalDis__SHIFT 0xc
+#define UMCCH0_0_EccCtrl__PoisonInhibit__SHIFT 0xd
+#define UMCCH0_0_EccCtrl__WrEccEn_MASK 0x00000001L
+#define UMCCH0_0_EccCtrl__EccReplayEn_MASK 0x00000002L
+#define UMCCH0_0_EccCtrl__UCFatalEn_MASK 0x00000100L
+#define UMCCH0_0_EccCtrl__RdEccEn_MASK 0x00000400L
+#define UMCCH0_0_EccCtrl__PoisonFatalDis_MASK 0x00001000L
+#define UMCCH0_0_EccCtrl__PoisonInhibit_MASK 0x00002000L
+//UMCCH0_0_UmcLocalCap
+#define UMCCH0_0_UmcLocalCap__EccDis__SHIFT 0x0
+#define UMCCH0_0_UmcLocalCap__Spare__SHIFT 0x1
+#define UMCCH0_0_UmcLocalCap__WrDis__SHIFT 0x1f
+#define UMCCH0_0_UmcLocalCap__EccDis_MASK 0x00000001L
+#define UMCCH0_0_UmcLocalCap__Spare_MASK 0x0000003EL
+#define UMCCH0_0_UmcLocalCap__WrDis_MASK 0x80000000L
+//UMCCH0_0_EccErrCntSel
+#define UMCCH0_0_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0
+#define UMCCH0_0_EccErrCntSel__EccErrInt__SHIFT 0xc
+#define UMCCH0_0_EccErrCntSel__EccErrCntEn__SHIFT 0xf
+#define UMCCH0_0_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL
+#define UMCCH0_0_EccErrCntSel__EccErrInt_MASK 0x00003000L
+#define UMCCH0_0_EccErrCntSel__EccErrCntEn_MASK 0x00008000L
+//UMCCH0_0_EccErrCnt
+#define UMCCH0_0_EccErrCnt__EccErrCnt__SHIFT 0x0
+#define UMCCH0_0_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL
+//UMCCH0_0_PerfMonCtlClk
+#define UMCCH0_0_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0
+#define UMCCH0_0_PerfMonCtlClk__ClkGate__SHIFT 0x16
+#define UMCCH0_0_PerfMonCtlClk__GlblReset__SHIFT 0x18
+#define UMCCH0_0_PerfMonCtlClk__GlblMonEn__SHIFT 0x19
+#define UMCCH0_0_PerfMonCtlClk__NumCounters__SHIFT 0x1a
+#define UMCCH0_0_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f
+#define UMCCH0_0_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL
+#define UMCCH0_0_PerfMonCtlClk__ClkGate_MASK 0x00400000L
+#define UMCCH0_0_PerfMonCtlClk__GlblReset_MASK 0x01000000L
+#define UMCCH0_0_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L
+#define UMCCH0_0_PerfMonCtlClk__NumCounters_MASK 0x3C000000L
+#define UMCCH0_0_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L
+//UMCCH0_0_PerfMonCtrClk_Lo
+#define UMCCH0_0_PerfMonCtrClk_Lo__Data__SHIFT 0x0
+#define UMCCH0_0_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_0_PerfMonCtrClk_Hi
+#define UMCCH0_0_PerfMonCtrClk_Hi__Data__SHIFT 0x0
+#define UMCCH0_0_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_0_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_0_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L
+//UMCCH0_0_PerfMonCtl1
+#define UMCCH0_0_PerfMonCtl1__EventSelect__SHIFT 0x0
+#define UMCCH0_0_PerfMonCtl1__RdWrMask__SHIFT 0x8
+#define UMCCH0_0_PerfMonCtl1__PriorityMask__SHIFT 0xa
+#define UMCCH0_0_PerfMonCtl1__ReqSizeMask__SHIFT 0xe
+#define UMCCH0_0_PerfMonCtl1__BankSel__SHIFT 0x10
+#define UMCCH0_0_PerfMonCtl1__VCSel__SHIFT 0x18
+#define UMCCH0_0_PerfMonCtl1__SubChanMask__SHIFT 0x1d
+#define UMCCH0_0_PerfMonCtl1__Enable__SHIFT 0x1f
+#define UMCCH0_0_PerfMonCtl1__EventSelect_MASK 0x000000FFL
+#define UMCCH0_0_PerfMonCtl1__RdWrMask_MASK 0x00000300L
+#define UMCCH0_0_PerfMonCtl1__PriorityMask_MASK 0x00003C00L
+#define UMCCH0_0_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH0_0_PerfMonCtl1__BankSel_MASK 0x00FF0000L
+#define UMCCH0_0_PerfMonCtl1__VCSel_MASK 0x1F000000L
+#define UMCCH0_0_PerfMonCtl1__SubChanMask_MASK 0x60000000L
+#define UMCCH0_0_PerfMonCtl1__Enable_MASK 0x80000000L
+//UMCCH0_0_PerfMonCtr1_Lo
+#define UMCCH0_0_PerfMonCtr1_Lo__Data__SHIFT 0x0
+#define UMCCH0_0_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_0_PerfMonCtr1_Hi
+#define UMCCH0_0_PerfMonCtr1_Hi__Data__SHIFT 0x0
+#define UMCCH0_0_PerfMonCtr1_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_0_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH0_0_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH0_0_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_0_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L
+#define UMCCH0_0_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH0_0_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH0_0_PerfMonCtl2
+#define UMCCH0_0_PerfMonCtl2__EventSelect__SHIFT 0x0
+#define UMCCH0_0_PerfMonCtl2__RdWrMask__SHIFT 0x8
+#define UMCCH0_0_PerfMonCtl2__PriorityMask__SHIFT 0xa
+#define UMCCH0_0_PerfMonCtl2__ReqSizeMask__SHIFT 0xe
+#define UMCCH0_0_PerfMonCtl2__BankSel__SHIFT 0x10
+#define UMCCH0_0_PerfMonCtl2__VCSel__SHIFT 0x18
+#define UMCCH0_0_PerfMonCtl2__SubChanMask__SHIFT 0x1d
+#define UMCCH0_0_PerfMonCtl2__Enable__SHIFT 0x1f
+#define UMCCH0_0_PerfMonCtl2__EventSelect_MASK 0x000000FFL
+#define UMCCH0_0_PerfMonCtl2__RdWrMask_MASK 0x00000300L
+#define UMCCH0_0_PerfMonCtl2__PriorityMask_MASK 0x00003C00L
+#define UMCCH0_0_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH0_0_PerfMonCtl2__BankSel_MASK 0x00FF0000L
+#define UMCCH0_0_PerfMonCtl2__VCSel_MASK 0x1F000000L
+#define UMCCH0_0_PerfMonCtl2__SubChanMask_MASK 0x60000000L
+#define UMCCH0_0_PerfMonCtl2__Enable_MASK 0x80000000L
+//UMCCH0_0_PerfMonCtr2_Lo
+#define UMCCH0_0_PerfMonCtr2_Lo__Data__SHIFT 0x0
+#define UMCCH0_0_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_0_PerfMonCtr2_Hi
+#define UMCCH0_0_PerfMonCtr2_Hi__Data__SHIFT 0x0
+#define UMCCH0_0_PerfMonCtr2_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_0_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH0_0_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH0_0_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_0_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L
+#define UMCCH0_0_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH0_0_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH0_0_PerfMonCtl3
+#define UMCCH0_0_PerfMonCtl3__EventSelect__SHIFT 0x0
+#define UMCCH0_0_PerfMonCtl3__RdWrMask__SHIFT 0x8
+#define UMCCH0_0_PerfMonCtl3__PriorityMask__SHIFT 0xa
+#define UMCCH0_0_PerfMonCtl3__ReqSizeMask__SHIFT 0xe
+#define UMCCH0_0_PerfMonCtl3__BankSel__SHIFT 0x10
+#define UMCCH0_0_PerfMonCtl3__VCSel__SHIFT 0x18
+#define UMCCH0_0_PerfMonCtl3__SubChanMask__SHIFT 0x1d
+#define UMCCH0_0_PerfMonCtl3__Enable__SHIFT 0x1f
+#define UMCCH0_0_PerfMonCtl3__EventSelect_MASK 0x000000FFL
+#define UMCCH0_0_PerfMonCtl3__RdWrMask_MASK 0x00000300L
+#define UMCCH0_0_PerfMonCtl3__PriorityMask_MASK 0x00003C00L
+#define UMCCH0_0_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH0_0_PerfMonCtl3__BankSel_MASK 0x00FF0000L
+#define UMCCH0_0_PerfMonCtl3__VCSel_MASK 0x1F000000L
+#define UMCCH0_0_PerfMonCtl3__SubChanMask_MASK 0x60000000L
+#define UMCCH0_0_PerfMonCtl3__Enable_MASK 0x80000000L
+//UMCCH0_0_PerfMonCtr3_Lo
+#define UMCCH0_0_PerfMonCtr3_Lo__Data__SHIFT 0x0
+#define UMCCH0_0_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_0_PerfMonCtr3_Hi
+#define UMCCH0_0_PerfMonCtr3_Hi__Data__SHIFT 0x0
+#define UMCCH0_0_PerfMonCtr3_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_0_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH0_0_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH0_0_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_0_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L
+#define UMCCH0_0_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH0_0_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH0_0_PerfMonCtl4
+#define UMCCH0_0_PerfMonCtl4__EventSelect__SHIFT 0x0
+#define UMCCH0_0_PerfMonCtl4__RdWrMask__SHIFT 0x8
+#define UMCCH0_0_PerfMonCtl4__PriorityMask__SHIFT 0xa
+#define UMCCH0_0_PerfMonCtl4__ReqSizeMask__SHIFT 0xe
+#define UMCCH0_0_PerfMonCtl4__BankSel__SHIFT 0x10
+#define UMCCH0_0_PerfMonCtl4__VCSel__SHIFT 0x18
+#define UMCCH0_0_PerfMonCtl4__SubChanMask__SHIFT 0x1d
+#define UMCCH0_0_PerfMonCtl4__Enable__SHIFT 0x1f
+#define UMCCH0_0_PerfMonCtl4__EventSelect_MASK 0x000000FFL
+#define UMCCH0_0_PerfMonCtl4__RdWrMask_MASK 0x00000300L
+#define UMCCH0_0_PerfMonCtl4__PriorityMask_MASK 0x00003C00L
+#define UMCCH0_0_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH0_0_PerfMonCtl4__BankSel_MASK 0x00FF0000L
+#define UMCCH0_0_PerfMonCtl4__VCSel_MASK 0x1F000000L
+#define UMCCH0_0_PerfMonCtl4__SubChanMask_MASK 0x60000000L
+#define UMCCH0_0_PerfMonCtl4__Enable_MASK 0x80000000L
+//UMCCH0_0_PerfMonCtr4_Lo
+#define UMCCH0_0_PerfMonCtr4_Lo__Data__SHIFT 0x0
+#define UMCCH0_0_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_0_PerfMonCtr4_Hi
+#define UMCCH0_0_PerfMonCtr4_Hi__Data__SHIFT 0x0
+#define UMCCH0_0_PerfMonCtr4_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_0_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH0_0_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH0_0_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_0_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L
+#define UMCCH0_0_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH0_0_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH0_0_PerfMonCtl5
+#define UMCCH0_0_PerfMonCtl5__EventSelect__SHIFT 0x0
+#define UMCCH0_0_PerfMonCtl5__RdWrMask__SHIFT 0x8
+#define UMCCH0_0_PerfMonCtl5__PriorityMask__SHIFT 0xa
+#define UMCCH0_0_PerfMonCtl5__ReqSizeMask__SHIFT 0xe
+#define UMCCH0_0_PerfMonCtl5__BankSel__SHIFT 0x10
+#define UMCCH0_0_PerfMonCtl5__VCSel__SHIFT 0x18
+#define UMCCH0_0_PerfMonCtl5__SubChanMask__SHIFT 0x1d
+#define UMCCH0_0_PerfMonCtl5__Enable__SHIFT 0x1f
+#define UMCCH0_0_PerfMonCtl5__EventSelect_MASK 0x000000FFL
+#define UMCCH0_0_PerfMonCtl5__RdWrMask_MASK 0x00000300L
+#define UMCCH0_0_PerfMonCtl5__PriorityMask_MASK 0x00003C00L
+#define UMCCH0_0_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH0_0_PerfMonCtl5__BankSel_MASK 0x00FF0000L
+#define UMCCH0_0_PerfMonCtl5__VCSel_MASK 0x1F000000L
+#define UMCCH0_0_PerfMonCtl5__SubChanMask_MASK 0x60000000L
+#define UMCCH0_0_PerfMonCtl5__Enable_MASK 0x80000000L
+//UMCCH0_0_PerfMonCtr5_Lo
+#define UMCCH0_0_PerfMonCtr5_Lo__Data__SHIFT 0x0
+#define UMCCH0_0_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_0_PerfMonCtr5_Hi
+#define UMCCH0_0_PerfMonCtr5_Hi__Data__SHIFT 0x0
+#define UMCCH0_0_PerfMonCtr5_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_0_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH0_0_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH0_0_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_0_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L
+#define UMCCH0_0_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH0_0_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH0_0_PerfMonCtl6
+#define UMCCH0_0_PerfMonCtl6__EventSelect__SHIFT 0x0
+#define UMCCH0_0_PerfMonCtl6__RdWrMask__SHIFT 0x8
+#define UMCCH0_0_PerfMonCtl6__PriorityMask__SHIFT 0xa
+#define UMCCH0_0_PerfMonCtl6__ReqSizeMask__SHIFT 0xe
+#define UMCCH0_0_PerfMonCtl6__BankSel__SHIFT 0x10
+#define UMCCH0_0_PerfMonCtl6__VCSel__SHIFT 0x18
+#define UMCCH0_0_PerfMonCtl6__SubChanMask__SHIFT 0x1d
+#define UMCCH0_0_PerfMonCtl6__Enable__SHIFT 0x1f
+#define UMCCH0_0_PerfMonCtl6__EventSelect_MASK 0x000000FFL
+#define UMCCH0_0_PerfMonCtl6__RdWrMask_MASK 0x00000300L
+#define UMCCH0_0_PerfMonCtl6__PriorityMask_MASK 0x00003C00L
+#define UMCCH0_0_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH0_0_PerfMonCtl6__BankSel_MASK 0x00FF0000L
+#define UMCCH0_0_PerfMonCtl6__VCSel_MASK 0x1F000000L
+#define UMCCH0_0_PerfMonCtl6__SubChanMask_MASK 0x60000000L
+#define UMCCH0_0_PerfMonCtl6__Enable_MASK 0x80000000L
+//UMCCH0_0_PerfMonCtr6_Lo
+#define UMCCH0_0_PerfMonCtr6_Lo__Data__SHIFT 0x0
+#define UMCCH0_0_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_0_PerfMonCtr6_Hi
+#define UMCCH0_0_PerfMonCtr6_Hi__Data__SHIFT 0x0
+#define UMCCH0_0_PerfMonCtr6_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_0_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH0_0_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH0_0_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_0_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L
+#define UMCCH0_0_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH0_0_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH0_0_PerfMonCtl7
+#define UMCCH0_0_PerfMonCtl7__EventSelect__SHIFT 0x0
+#define UMCCH0_0_PerfMonCtl7__RdWrMask__SHIFT 0x8
+#define UMCCH0_0_PerfMonCtl7__PriorityMask__SHIFT 0xa
+#define UMCCH0_0_PerfMonCtl7__ReqSizeMask__SHIFT 0xe
+#define UMCCH0_0_PerfMonCtl7__BankSel__SHIFT 0x10
+#define UMCCH0_0_PerfMonCtl7__VCSel__SHIFT 0x18
+#define UMCCH0_0_PerfMonCtl7__SubChanMask__SHIFT 0x1d
+#define UMCCH0_0_PerfMonCtl7__Enable__SHIFT 0x1f
+#define UMCCH0_0_PerfMonCtl7__EventSelect_MASK 0x000000FFL
+#define UMCCH0_0_PerfMonCtl7__RdWrMask_MASK 0x00000300L
+#define UMCCH0_0_PerfMonCtl7__PriorityMask_MASK 0x00003C00L
+#define UMCCH0_0_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH0_0_PerfMonCtl7__BankSel_MASK 0x00FF0000L
+#define UMCCH0_0_PerfMonCtl7__VCSel_MASK 0x1F000000L
+#define UMCCH0_0_PerfMonCtl7__SubChanMask_MASK 0x60000000L
+#define UMCCH0_0_PerfMonCtl7__Enable_MASK 0x80000000L
+//UMCCH0_0_PerfMonCtr7_Lo
+#define UMCCH0_0_PerfMonCtr7_Lo__Data__SHIFT 0x0
+#define UMCCH0_0_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_0_PerfMonCtr7_Hi
+#define UMCCH0_0_PerfMonCtr7_Hi__Data__SHIFT 0x0
+#define UMCCH0_0_PerfMonCtr7_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_0_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH0_0_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH0_0_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_0_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L
+#define UMCCH0_0_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH0_0_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH0_0_PerfMonCtl8
+#define UMCCH0_0_PerfMonCtl8__EventSelect__SHIFT 0x0
+#define UMCCH0_0_PerfMonCtl8__RdWrMask__SHIFT 0x8
+#define UMCCH0_0_PerfMonCtl8__PriorityMask__SHIFT 0xa
+#define UMCCH0_0_PerfMonCtl8__ReqSizeMask__SHIFT 0xe
+#define UMCCH0_0_PerfMonCtl8__BankSel__SHIFT 0x10
+#define UMCCH0_0_PerfMonCtl8__VCSel__SHIFT 0x18
+#define UMCCH0_0_PerfMonCtl8__SubChanMask__SHIFT 0x1d
+#define UMCCH0_0_PerfMonCtl8__Enable__SHIFT 0x1f
+#define UMCCH0_0_PerfMonCtl8__EventSelect_MASK 0x000000FFL
+#define UMCCH0_0_PerfMonCtl8__RdWrMask_MASK 0x00000300L
+#define UMCCH0_0_PerfMonCtl8__PriorityMask_MASK 0x00003C00L
+#define UMCCH0_0_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH0_0_PerfMonCtl8__BankSel_MASK 0x00FF0000L
+#define UMCCH0_0_PerfMonCtl8__VCSel_MASK 0x1F000000L
+#define UMCCH0_0_PerfMonCtl8__SubChanMask_MASK 0x60000000L
+#define UMCCH0_0_PerfMonCtl8__Enable_MASK 0x80000000L
+//UMCCH0_0_PerfMonCtr8_Lo
+#define UMCCH0_0_PerfMonCtr8_Lo__Data__SHIFT 0x0
+#define UMCCH0_0_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_0_PerfMonCtr8_Hi
+#define UMCCH0_0_PerfMonCtr8_Hi__Data__SHIFT 0x0
+#define UMCCH0_0_PerfMonCtr8_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_0_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH0_0_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH0_0_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_0_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L
+#define UMCCH0_0_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH0_0_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L
+
+
+// addressBlock: umc_w_phy_umc0_umcch1_umcchdec
+//UMCCH1_0_BaseAddrCS0
+#define UMCCH1_0_BaseAddrCS0__CSEnable__SHIFT 0x0
+#define UMCCH1_0_BaseAddrCS0__BaseAddr__SHIFT 0x1
+#define UMCCH1_0_BaseAddrCS0__CSEnable_MASK 0x00000001L
+#define UMCCH1_0_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL
+//UMCCH1_0_AddrMaskCS01
+#define UMCCH1_0_AddrMaskCS01__AddrMask__SHIFT 0x1
+#define UMCCH1_0_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL
+//UMCCH1_0_AddrSelCS01
+#define UMCCH1_0_AddrSelCS01__BankBit0__SHIFT 0x0
+#define UMCCH1_0_AddrSelCS01__BankBit1__SHIFT 0x4
+#define UMCCH1_0_AddrSelCS01__BankBit2__SHIFT 0x8
+#define UMCCH1_0_AddrSelCS01__BankBit3__SHIFT 0xc
+#define UMCCH1_0_AddrSelCS01__BankBit4__SHIFT 0x10
+#define UMCCH1_0_AddrSelCS01__RowLo__SHIFT 0x18
+#define UMCCH1_0_AddrSelCS01__RowHi__SHIFT 0x1c
+#define UMCCH1_0_AddrSelCS01__BankBit0_MASK 0x0000000FL
+#define UMCCH1_0_AddrSelCS01__BankBit1_MASK 0x000000F0L
+#define UMCCH1_0_AddrSelCS01__BankBit2_MASK 0x00000F00L
+#define UMCCH1_0_AddrSelCS01__BankBit3_MASK 0x0000F000L
+#define UMCCH1_0_AddrSelCS01__BankBit4_MASK 0x001F0000L
+#define UMCCH1_0_AddrSelCS01__RowLo_MASK 0x0F000000L
+#define UMCCH1_0_AddrSelCS01__RowHi_MASK 0xF0000000L
+//UMCCH1_0_AddrHashBank0
+#define UMCCH1_0_AddrHashBank0__XorEnable__SHIFT 0x0
+#define UMCCH1_0_AddrHashBank0__ColXor__SHIFT 0x1
+#define UMCCH1_0_AddrHashBank0__RowXor__SHIFT 0xe
+#define UMCCH1_0_AddrHashBank0__XorEnable_MASK 0x00000001L
+#define UMCCH1_0_AddrHashBank0__ColXor_MASK 0x00003FFEL
+#define UMCCH1_0_AddrHashBank0__RowXor_MASK 0xFFFFC000L
+//UMCCH1_0_AddrHashBank1
+#define UMCCH1_0_AddrHashBank1__XorEnable__SHIFT 0x0
+#define UMCCH1_0_AddrHashBank1__ColXor__SHIFT 0x1
+#define UMCCH1_0_AddrHashBank1__RowXor__SHIFT 0xe
+#define UMCCH1_0_AddrHashBank1__XorEnable_MASK 0x00000001L
+#define UMCCH1_0_AddrHashBank1__ColXor_MASK 0x00003FFEL
+#define UMCCH1_0_AddrHashBank1__RowXor_MASK 0xFFFFC000L
+//UMCCH1_0_AddrHashBank2
+#define UMCCH1_0_AddrHashBank2__XorEnable__SHIFT 0x0
+#define UMCCH1_0_AddrHashBank2__ColXor__SHIFT 0x1
+#define UMCCH1_0_AddrHashBank2__RowXor__SHIFT 0xe
+#define UMCCH1_0_AddrHashBank2__XorEnable_MASK 0x00000001L
+#define UMCCH1_0_AddrHashBank2__ColXor_MASK 0x00003FFEL
+#define UMCCH1_0_AddrHashBank2__RowXor_MASK 0xFFFFC000L
+//UMCCH1_0_AddrHashBank3
+#define UMCCH1_0_AddrHashBank3__XorEnable__SHIFT 0x0
+#define UMCCH1_0_AddrHashBank3__ColXor__SHIFT 0x1
+#define UMCCH1_0_AddrHashBank3__RowXor__SHIFT 0xe
+#define UMCCH1_0_AddrHashBank3__XorEnable_MASK 0x00000001L
+#define UMCCH1_0_AddrHashBank3__ColXor_MASK 0x00003FFEL
+#define UMCCH1_0_AddrHashBank3__RowXor_MASK 0xFFFFC000L
+//UMCCH1_0_AddrHashBank4
+#define UMCCH1_0_AddrHashBank4__XorEnable__SHIFT 0x0
+#define UMCCH1_0_AddrHashBank4__ColXor__SHIFT 0x1
+#define UMCCH1_0_AddrHashBank4__RowXor__SHIFT 0xe
+#define UMCCH1_0_AddrHashBank4__XorEnable_MASK 0x00000001L
+#define UMCCH1_0_AddrHashBank4__ColXor_MASK 0x00003FFEL
+#define UMCCH1_0_AddrHashBank4__RowXor_MASK 0xFFFFC000L
+//UMCCH1_0_AddrHashBank5
+#define UMCCH1_0_AddrHashBank5__XorEnable__SHIFT 0x0
+#define UMCCH1_0_AddrHashBank5__ColXor__SHIFT 0x1
+#define UMCCH1_0_AddrHashBank5__RowXor__SHIFT 0xe
+#define UMCCH1_0_AddrHashBank5__XorEnable_MASK 0x00000001L
+#define UMCCH1_0_AddrHashBank5__ColXor_MASK 0x00003FFEL
+#define UMCCH1_0_AddrHashBank5__RowXor_MASK 0xFFFFC000L
+//UMCCH1_0_UMC_CONFIG
+#define UMCCH1_0_UMC_CONFIG__DDR_TYPE__SHIFT 0x0
+#define UMCCH1_0_UMC_CONFIG__BurstLength__SHIFT 0x8
+#define UMCCH1_0_UMC_CONFIG__BurstCtrl__SHIFT 0xa
+#define UMCCH1_0_UMC_CONFIG__DramReady__SHIFT 0x1f
+#define UMCCH1_0_UMC_CONFIG__DDR_TYPE_MASK 0x00000007L
+#define UMCCH1_0_UMC_CONFIG__BurstLength_MASK 0x00000300L
+#define UMCCH1_0_UMC_CONFIG__BurstCtrl_MASK 0x00000C00L
+#define UMCCH1_0_UMC_CONFIG__DramReady_MASK 0x80000000L
+//UMCCH1_0_EccCtrl
+#define UMCCH1_0_EccCtrl__WrEccEn__SHIFT 0x0
+#define UMCCH1_0_EccCtrl__EccReplayEn__SHIFT 0x1
+#define UMCCH1_0_EccCtrl__UCFatalEn__SHIFT 0x8
+#define UMCCH1_0_EccCtrl__RdEccEn__SHIFT 0xa
+#define UMCCH1_0_EccCtrl__PoisonFatalDis__SHIFT 0xc
+#define UMCCH1_0_EccCtrl__PoisonInhibit__SHIFT 0xd
+#define UMCCH1_0_EccCtrl__WrEccEn_MASK 0x00000001L
+#define UMCCH1_0_EccCtrl__EccReplayEn_MASK 0x00000002L
+#define UMCCH1_0_EccCtrl__UCFatalEn_MASK 0x00000100L
+#define UMCCH1_0_EccCtrl__RdEccEn_MASK 0x00000400L
+#define UMCCH1_0_EccCtrl__PoisonFatalDis_MASK 0x00001000L
+#define UMCCH1_0_EccCtrl__PoisonInhibit_MASK 0x00002000L
+//UMCCH1_0_UmcLocalCap
+#define UMCCH1_0_UmcLocalCap__EccDis__SHIFT 0x0
+#define UMCCH1_0_UmcLocalCap__Spare__SHIFT 0x1
+#define UMCCH1_0_UmcLocalCap__WrDis__SHIFT 0x1f
+#define UMCCH1_0_UmcLocalCap__EccDis_MASK 0x00000001L
+#define UMCCH1_0_UmcLocalCap__Spare_MASK 0x0000003EL
+#define UMCCH1_0_UmcLocalCap__WrDis_MASK 0x80000000L
+//UMCCH1_0_EccErrCntSel
+#define UMCCH1_0_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0
+#define UMCCH1_0_EccErrCntSel__EccErrInt__SHIFT 0xc
+#define UMCCH1_0_EccErrCntSel__EccErrCntEn__SHIFT 0xf
+#define UMCCH1_0_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL
+#define UMCCH1_0_EccErrCntSel__EccErrInt_MASK 0x00003000L
+#define UMCCH1_0_EccErrCntSel__EccErrCntEn_MASK 0x00008000L
+//UMCCH1_0_EccErrCnt
+#define UMCCH1_0_EccErrCnt__EccErrCnt__SHIFT 0x0
+#define UMCCH1_0_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL
+//UMCCH1_0_PerfMonCtlClk
+#define UMCCH1_0_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0
+#define UMCCH1_0_PerfMonCtlClk__ClkGate__SHIFT 0x16
+#define UMCCH1_0_PerfMonCtlClk__GlblReset__SHIFT 0x18
+#define UMCCH1_0_PerfMonCtlClk__GlblMonEn__SHIFT 0x19
+#define UMCCH1_0_PerfMonCtlClk__NumCounters__SHIFT 0x1a
+#define UMCCH1_0_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f
+#define UMCCH1_0_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL
+#define UMCCH1_0_PerfMonCtlClk__ClkGate_MASK 0x00400000L
+#define UMCCH1_0_PerfMonCtlClk__GlblReset_MASK 0x01000000L
+#define UMCCH1_0_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L
+#define UMCCH1_0_PerfMonCtlClk__NumCounters_MASK 0x3C000000L
+#define UMCCH1_0_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L
+//UMCCH1_0_PerfMonCtrClk_Lo
+#define UMCCH1_0_PerfMonCtrClk_Lo__Data__SHIFT 0x0
+#define UMCCH1_0_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_0_PerfMonCtrClk_Hi
+#define UMCCH1_0_PerfMonCtrClk_Hi__Data__SHIFT 0x0
+#define UMCCH1_0_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_0_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_0_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L
+//UMCCH1_0_PerfMonCtl1
+#define UMCCH1_0_PerfMonCtl1__EventSelect__SHIFT 0x0
+#define UMCCH1_0_PerfMonCtl1__RdWrMask__SHIFT 0x8
+#define UMCCH1_0_PerfMonCtl1__PriorityMask__SHIFT 0xa
+#define UMCCH1_0_PerfMonCtl1__ReqSizeMask__SHIFT 0xe
+#define UMCCH1_0_PerfMonCtl1__BankSel__SHIFT 0x10
+#define UMCCH1_0_PerfMonCtl1__VCSel__SHIFT 0x18
+#define UMCCH1_0_PerfMonCtl1__SubChanMask__SHIFT 0x1d
+#define UMCCH1_0_PerfMonCtl1__Enable__SHIFT 0x1f
+#define UMCCH1_0_PerfMonCtl1__EventSelect_MASK 0x000000FFL
+#define UMCCH1_0_PerfMonCtl1__RdWrMask_MASK 0x00000300L
+#define UMCCH1_0_PerfMonCtl1__PriorityMask_MASK 0x00003C00L
+#define UMCCH1_0_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH1_0_PerfMonCtl1__BankSel_MASK 0x00FF0000L
+#define UMCCH1_0_PerfMonCtl1__VCSel_MASK 0x1F000000L
+#define UMCCH1_0_PerfMonCtl1__SubChanMask_MASK 0x60000000L
+#define UMCCH1_0_PerfMonCtl1__Enable_MASK 0x80000000L
+//UMCCH1_0_PerfMonCtr1_Lo
+#define UMCCH1_0_PerfMonCtr1_Lo__Data__SHIFT 0x0
+#define UMCCH1_0_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_0_PerfMonCtr1_Hi
+#define UMCCH1_0_PerfMonCtr1_Hi__Data__SHIFT 0x0
+#define UMCCH1_0_PerfMonCtr1_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_0_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH1_0_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH1_0_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_0_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L
+#define UMCCH1_0_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH1_0_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH1_0_PerfMonCtl2
+#define UMCCH1_0_PerfMonCtl2__EventSelect__SHIFT 0x0
+#define UMCCH1_0_PerfMonCtl2__RdWrMask__SHIFT 0x8
+#define UMCCH1_0_PerfMonCtl2__PriorityMask__SHIFT 0xa
+#define UMCCH1_0_PerfMonCtl2__ReqSizeMask__SHIFT 0xe
+#define UMCCH1_0_PerfMonCtl2__BankSel__SHIFT 0x10
+#define UMCCH1_0_PerfMonCtl2__VCSel__SHIFT 0x18
+#define UMCCH1_0_PerfMonCtl2__SubChanMask__SHIFT 0x1d
+#define UMCCH1_0_PerfMonCtl2__Enable__SHIFT 0x1f
+#define UMCCH1_0_PerfMonCtl2__EventSelect_MASK 0x000000FFL
+#define UMCCH1_0_PerfMonCtl2__RdWrMask_MASK 0x00000300L
+#define UMCCH1_0_PerfMonCtl2__PriorityMask_MASK 0x00003C00L
+#define UMCCH1_0_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH1_0_PerfMonCtl2__BankSel_MASK 0x00FF0000L
+#define UMCCH1_0_PerfMonCtl2__VCSel_MASK 0x1F000000L
+#define UMCCH1_0_PerfMonCtl2__SubChanMask_MASK 0x60000000L
+#define UMCCH1_0_PerfMonCtl2__Enable_MASK 0x80000000L
+//UMCCH1_0_PerfMonCtr2_Lo
+#define UMCCH1_0_PerfMonCtr2_Lo__Data__SHIFT 0x0
+#define UMCCH1_0_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_0_PerfMonCtr2_Hi
+#define UMCCH1_0_PerfMonCtr2_Hi__Data__SHIFT 0x0
+#define UMCCH1_0_PerfMonCtr2_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_0_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH1_0_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH1_0_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_0_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L
+#define UMCCH1_0_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH1_0_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH1_0_PerfMonCtl3
+#define UMCCH1_0_PerfMonCtl3__EventSelect__SHIFT 0x0
+#define UMCCH1_0_PerfMonCtl3__RdWrMask__SHIFT 0x8
+#define UMCCH1_0_PerfMonCtl3__PriorityMask__SHIFT 0xa
+#define UMCCH1_0_PerfMonCtl3__ReqSizeMask__SHIFT 0xe
+#define UMCCH1_0_PerfMonCtl3__BankSel__SHIFT 0x10
+#define UMCCH1_0_PerfMonCtl3__VCSel__SHIFT 0x18
+#define UMCCH1_0_PerfMonCtl3__SubChanMask__SHIFT 0x1d
+#define UMCCH1_0_PerfMonCtl3__Enable__SHIFT 0x1f
+#define UMCCH1_0_PerfMonCtl3__EventSelect_MASK 0x000000FFL
+#define UMCCH1_0_PerfMonCtl3__RdWrMask_MASK 0x00000300L
+#define UMCCH1_0_PerfMonCtl3__PriorityMask_MASK 0x00003C00L
+#define UMCCH1_0_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH1_0_PerfMonCtl3__BankSel_MASK 0x00FF0000L
+#define UMCCH1_0_PerfMonCtl3__VCSel_MASK 0x1F000000L
+#define UMCCH1_0_PerfMonCtl3__SubChanMask_MASK 0x60000000L
+#define UMCCH1_0_PerfMonCtl3__Enable_MASK 0x80000000L
+//UMCCH1_0_PerfMonCtr3_Lo
+#define UMCCH1_0_PerfMonCtr3_Lo__Data__SHIFT 0x0
+#define UMCCH1_0_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_0_PerfMonCtr3_Hi
+#define UMCCH1_0_PerfMonCtr3_Hi__Data__SHIFT 0x0
+#define UMCCH1_0_PerfMonCtr3_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_0_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH1_0_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH1_0_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_0_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L
+#define UMCCH1_0_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH1_0_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH1_0_PerfMonCtl4
+#define UMCCH1_0_PerfMonCtl4__EventSelect__SHIFT 0x0
+#define UMCCH1_0_PerfMonCtl4__RdWrMask__SHIFT 0x8
+#define UMCCH1_0_PerfMonCtl4__PriorityMask__SHIFT 0xa
+#define UMCCH1_0_PerfMonCtl4__ReqSizeMask__SHIFT 0xe
+#define UMCCH1_0_PerfMonCtl4__BankSel__SHIFT 0x10
+#define UMCCH1_0_PerfMonCtl4__VCSel__SHIFT 0x18
+#define UMCCH1_0_PerfMonCtl4__SubChanMask__SHIFT 0x1d
+#define UMCCH1_0_PerfMonCtl4__Enable__SHIFT 0x1f
+#define UMCCH1_0_PerfMonCtl4__EventSelect_MASK 0x000000FFL
+#define UMCCH1_0_PerfMonCtl4__RdWrMask_MASK 0x00000300L
+#define UMCCH1_0_PerfMonCtl4__PriorityMask_MASK 0x00003C00L
+#define UMCCH1_0_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH1_0_PerfMonCtl4__BankSel_MASK 0x00FF0000L
+#define UMCCH1_0_PerfMonCtl4__VCSel_MASK 0x1F000000L
+#define UMCCH1_0_PerfMonCtl4__SubChanMask_MASK 0x60000000L
+#define UMCCH1_0_PerfMonCtl4__Enable_MASK 0x80000000L
+//UMCCH1_0_PerfMonCtr4_Lo
+#define UMCCH1_0_PerfMonCtr4_Lo__Data__SHIFT 0x0
+#define UMCCH1_0_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_0_PerfMonCtr4_Hi
+#define UMCCH1_0_PerfMonCtr4_Hi__Data__SHIFT 0x0
+#define UMCCH1_0_PerfMonCtr4_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_0_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH1_0_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH1_0_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_0_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L
+#define UMCCH1_0_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH1_0_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH1_0_PerfMonCtl5
+#define UMCCH1_0_PerfMonCtl5__EventSelect__SHIFT 0x0
+#define UMCCH1_0_PerfMonCtl5__RdWrMask__SHIFT 0x8
+#define UMCCH1_0_PerfMonCtl5__PriorityMask__SHIFT 0xa
+#define UMCCH1_0_PerfMonCtl5__ReqSizeMask__SHIFT 0xe
+#define UMCCH1_0_PerfMonCtl5__BankSel__SHIFT 0x10
+#define UMCCH1_0_PerfMonCtl5__VCSel__SHIFT 0x18
+#define UMCCH1_0_PerfMonCtl5__SubChanMask__SHIFT 0x1d
+#define UMCCH1_0_PerfMonCtl5__Enable__SHIFT 0x1f
+#define UMCCH1_0_PerfMonCtl5__EventSelect_MASK 0x000000FFL
+#define UMCCH1_0_PerfMonCtl5__RdWrMask_MASK 0x00000300L
+#define UMCCH1_0_PerfMonCtl5__PriorityMask_MASK 0x00003C00L
+#define UMCCH1_0_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH1_0_PerfMonCtl5__BankSel_MASK 0x00FF0000L
+#define UMCCH1_0_PerfMonCtl5__VCSel_MASK 0x1F000000L
+#define UMCCH1_0_PerfMonCtl5__SubChanMask_MASK 0x60000000L
+#define UMCCH1_0_PerfMonCtl5__Enable_MASK 0x80000000L
+//UMCCH1_0_PerfMonCtr5_Lo
+#define UMCCH1_0_PerfMonCtr5_Lo__Data__SHIFT 0x0
+#define UMCCH1_0_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_0_PerfMonCtr5_Hi
+#define UMCCH1_0_PerfMonCtr5_Hi__Data__SHIFT 0x0
+#define UMCCH1_0_PerfMonCtr5_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_0_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH1_0_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH1_0_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_0_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L
+#define UMCCH1_0_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH1_0_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH1_0_PerfMonCtl6
+#define UMCCH1_0_PerfMonCtl6__EventSelect__SHIFT 0x0
+#define UMCCH1_0_PerfMonCtl6__RdWrMask__SHIFT 0x8
+#define UMCCH1_0_PerfMonCtl6__PriorityMask__SHIFT 0xa
+#define UMCCH1_0_PerfMonCtl6__ReqSizeMask__SHIFT 0xe
+#define UMCCH1_0_PerfMonCtl6__BankSel__SHIFT 0x10
+#define UMCCH1_0_PerfMonCtl6__VCSel__SHIFT 0x18
+#define UMCCH1_0_PerfMonCtl6__SubChanMask__SHIFT 0x1d
+#define UMCCH1_0_PerfMonCtl6__Enable__SHIFT 0x1f
+#define UMCCH1_0_PerfMonCtl6__EventSelect_MASK 0x000000FFL
+#define UMCCH1_0_PerfMonCtl6__RdWrMask_MASK 0x00000300L
+#define UMCCH1_0_PerfMonCtl6__PriorityMask_MASK 0x00003C00L
+#define UMCCH1_0_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH1_0_PerfMonCtl6__BankSel_MASK 0x00FF0000L
+#define UMCCH1_0_PerfMonCtl6__VCSel_MASK 0x1F000000L
+#define UMCCH1_0_PerfMonCtl6__SubChanMask_MASK 0x60000000L
+#define UMCCH1_0_PerfMonCtl6__Enable_MASK 0x80000000L
+//UMCCH1_0_PerfMonCtr6_Lo
+#define UMCCH1_0_PerfMonCtr6_Lo__Data__SHIFT 0x0
+#define UMCCH1_0_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_0_PerfMonCtr6_Hi
+#define UMCCH1_0_PerfMonCtr6_Hi__Data__SHIFT 0x0
+#define UMCCH1_0_PerfMonCtr6_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_0_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH1_0_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH1_0_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_0_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L
+#define UMCCH1_0_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH1_0_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH1_0_PerfMonCtl7
+#define UMCCH1_0_PerfMonCtl7__EventSelect__SHIFT 0x0
+#define UMCCH1_0_PerfMonCtl7__RdWrMask__SHIFT 0x8
+#define UMCCH1_0_PerfMonCtl7__PriorityMask__SHIFT 0xa
+#define UMCCH1_0_PerfMonCtl7__ReqSizeMask__SHIFT 0xe
+#define UMCCH1_0_PerfMonCtl7__BankSel__SHIFT 0x10
+#define UMCCH1_0_PerfMonCtl7__VCSel__SHIFT 0x18
+#define UMCCH1_0_PerfMonCtl7__SubChanMask__SHIFT 0x1d
+#define UMCCH1_0_PerfMonCtl7__Enable__SHIFT 0x1f
+#define UMCCH1_0_PerfMonCtl7__EventSelect_MASK 0x000000FFL
+#define UMCCH1_0_PerfMonCtl7__RdWrMask_MASK 0x00000300L
+#define UMCCH1_0_PerfMonCtl7__PriorityMask_MASK 0x00003C00L
+#define UMCCH1_0_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH1_0_PerfMonCtl7__BankSel_MASK 0x00FF0000L
+#define UMCCH1_0_PerfMonCtl7__VCSel_MASK 0x1F000000L
+#define UMCCH1_0_PerfMonCtl7__SubChanMask_MASK 0x60000000L
+#define UMCCH1_0_PerfMonCtl7__Enable_MASK 0x80000000L
+//UMCCH1_0_PerfMonCtr7_Lo
+#define UMCCH1_0_PerfMonCtr7_Lo__Data__SHIFT 0x0
+#define UMCCH1_0_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_0_PerfMonCtr7_Hi
+#define UMCCH1_0_PerfMonCtr7_Hi__Data__SHIFT 0x0
+#define UMCCH1_0_PerfMonCtr7_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_0_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH1_0_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH1_0_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_0_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L
+#define UMCCH1_0_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH1_0_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH1_0_PerfMonCtl8
+#define UMCCH1_0_PerfMonCtl8__EventSelect__SHIFT 0x0
+#define UMCCH1_0_PerfMonCtl8__RdWrMask__SHIFT 0x8
+#define UMCCH1_0_PerfMonCtl8__PriorityMask__SHIFT 0xa
+#define UMCCH1_0_PerfMonCtl8__ReqSizeMask__SHIFT 0xe
+#define UMCCH1_0_PerfMonCtl8__BankSel__SHIFT 0x10
+#define UMCCH1_0_PerfMonCtl8__VCSel__SHIFT 0x18
+#define UMCCH1_0_PerfMonCtl8__SubChanMask__SHIFT 0x1d
+#define UMCCH1_0_PerfMonCtl8__Enable__SHIFT 0x1f
+#define UMCCH1_0_PerfMonCtl8__EventSelect_MASK 0x000000FFL
+#define UMCCH1_0_PerfMonCtl8__RdWrMask_MASK 0x00000300L
+#define UMCCH1_0_PerfMonCtl8__PriorityMask_MASK 0x00003C00L
+#define UMCCH1_0_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH1_0_PerfMonCtl8__BankSel_MASK 0x00FF0000L
+#define UMCCH1_0_PerfMonCtl8__VCSel_MASK 0x1F000000L
+#define UMCCH1_0_PerfMonCtl8__SubChanMask_MASK 0x60000000L
+#define UMCCH1_0_PerfMonCtl8__Enable_MASK 0x80000000L
+//UMCCH1_0_PerfMonCtr8_Lo
+#define UMCCH1_0_PerfMonCtr8_Lo__Data__SHIFT 0x0
+#define UMCCH1_0_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_0_PerfMonCtr8_Hi
+#define UMCCH1_0_PerfMonCtr8_Hi__Data__SHIFT 0x0
+#define UMCCH1_0_PerfMonCtr8_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_0_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH1_0_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH1_0_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_0_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L
+#define UMCCH1_0_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH1_0_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L
+
+
+// addressBlock: umc_w_phy_umc0_umcch2_umcchdec
+//UMCCH2_0_BaseAddrCS0
+#define UMCCH2_0_BaseAddrCS0__CSEnable__SHIFT 0x0
+#define UMCCH2_0_BaseAddrCS0__BaseAddr__SHIFT 0x1
+#define UMCCH2_0_BaseAddrCS0__CSEnable_MASK 0x00000001L
+#define UMCCH2_0_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL
+//UMCCH2_0_AddrMaskCS01
+#define UMCCH2_0_AddrMaskCS01__AddrMask__SHIFT 0x1
+#define UMCCH2_0_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL
+//UMCCH2_0_AddrSelCS01
+#define UMCCH2_0_AddrSelCS01__BankBit0__SHIFT 0x0
+#define UMCCH2_0_AddrSelCS01__BankBit1__SHIFT 0x4
+#define UMCCH2_0_AddrSelCS01__BankBit2__SHIFT 0x8
+#define UMCCH2_0_AddrSelCS01__BankBit3__SHIFT 0xc
+#define UMCCH2_0_AddrSelCS01__BankBit4__SHIFT 0x10
+#define UMCCH2_0_AddrSelCS01__RowLo__SHIFT 0x18
+#define UMCCH2_0_AddrSelCS01__RowHi__SHIFT 0x1c
+#define UMCCH2_0_AddrSelCS01__BankBit0_MASK 0x0000000FL
+#define UMCCH2_0_AddrSelCS01__BankBit1_MASK 0x000000F0L
+#define UMCCH2_0_AddrSelCS01__BankBit2_MASK 0x00000F00L
+#define UMCCH2_0_AddrSelCS01__BankBit3_MASK 0x0000F000L
+#define UMCCH2_0_AddrSelCS01__BankBit4_MASK 0x001F0000L
+#define UMCCH2_0_AddrSelCS01__RowLo_MASK 0x0F000000L
+#define UMCCH2_0_AddrSelCS01__RowHi_MASK 0xF0000000L
+//UMCCH2_0_AddrHashBank0
+#define UMCCH2_0_AddrHashBank0__XorEnable__SHIFT 0x0
+#define UMCCH2_0_AddrHashBank0__ColXor__SHIFT 0x1
+#define UMCCH2_0_AddrHashBank0__RowXor__SHIFT 0xe
+#define UMCCH2_0_AddrHashBank0__XorEnable_MASK 0x00000001L
+#define UMCCH2_0_AddrHashBank0__ColXor_MASK 0x00003FFEL
+#define UMCCH2_0_AddrHashBank0__RowXor_MASK 0xFFFFC000L
+//UMCCH2_0_AddrHashBank1
+#define UMCCH2_0_AddrHashBank1__XorEnable__SHIFT 0x0
+#define UMCCH2_0_AddrHashBank1__ColXor__SHIFT 0x1
+#define UMCCH2_0_AddrHashBank1__RowXor__SHIFT 0xe
+#define UMCCH2_0_AddrHashBank1__XorEnable_MASK 0x00000001L
+#define UMCCH2_0_AddrHashBank1__ColXor_MASK 0x00003FFEL
+#define UMCCH2_0_AddrHashBank1__RowXor_MASK 0xFFFFC000L
+//UMCCH2_0_AddrHashBank2
+#define UMCCH2_0_AddrHashBank2__XorEnable__SHIFT 0x0
+#define UMCCH2_0_AddrHashBank2__ColXor__SHIFT 0x1
+#define UMCCH2_0_AddrHashBank2__RowXor__SHIFT 0xe
+#define UMCCH2_0_AddrHashBank2__XorEnable_MASK 0x00000001L
+#define UMCCH2_0_AddrHashBank2__ColXor_MASK 0x00003FFEL
+#define UMCCH2_0_AddrHashBank2__RowXor_MASK 0xFFFFC000L
+//UMCCH2_0_AddrHashBank3
+#define UMCCH2_0_AddrHashBank3__XorEnable__SHIFT 0x0
+#define UMCCH2_0_AddrHashBank3__ColXor__SHIFT 0x1
+#define UMCCH2_0_AddrHashBank3__RowXor__SHIFT 0xe
+#define UMCCH2_0_AddrHashBank3__XorEnable_MASK 0x00000001L
+#define UMCCH2_0_AddrHashBank3__ColXor_MASK 0x00003FFEL
+#define UMCCH2_0_AddrHashBank3__RowXor_MASK 0xFFFFC000L
+//UMCCH2_0_AddrHashBank4
+#define UMCCH2_0_AddrHashBank4__XorEnable__SHIFT 0x0
+#define UMCCH2_0_AddrHashBank4__ColXor__SHIFT 0x1
+#define UMCCH2_0_AddrHashBank4__RowXor__SHIFT 0xe
+#define UMCCH2_0_AddrHashBank4__XorEnable_MASK 0x00000001L
+#define UMCCH2_0_AddrHashBank4__ColXor_MASK 0x00003FFEL
+#define UMCCH2_0_AddrHashBank4__RowXor_MASK 0xFFFFC000L
+//UMCCH2_0_AddrHashBank5
+#define UMCCH2_0_AddrHashBank5__XorEnable__SHIFT 0x0
+#define UMCCH2_0_AddrHashBank5__ColXor__SHIFT 0x1
+#define UMCCH2_0_AddrHashBank5__RowXor__SHIFT 0xe
+#define UMCCH2_0_AddrHashBank5__XorEnable_MASK 0x00000001L
+#define UMCCH2_0_AddrHashBank5__ColXor_MASK 0x00003FFEL
+#define UMCCH2_0_AddrHashBank5__RowXor_MASK 0xFFFFC000L
+//UMCCH2_0_UMC_CONFIG
+#define UMCCH2_0_UMC_CONFIG__DDR_TYPE__SHIFT 0x0
+#define UMCCH2_0_UMC_CONFIG__BurstLength__SHIFT 0x8
+#define UMCCH2_0_UMC_CONFIG__BurstCtrl__SHIFT 0xa
+#define UMCCH2_0_UMC_CONFIG__DramReady__SHIFT 0x1f
+#define UMCCH2_0_UMC_CONFIG__DDR_TYPE_MASK 0x00000007L
+#define UMCCH2_0_UMC_CONFIG__BurstLength_MASK 0x00000300L
+#define UMCCH2_0_UMC_CONFIG__BurstCtrl_MASK 0x00000C00L
+#define UMCCH2_0_UMC_CONFIG__DramReady_MASK 0x80000000L
+//UMCCH2_0_EccCtrl
+#define UMCCH2_0_EccCtrl__WrEccEn__SHIFT 0x0
+#define UMCCH2_0_EccCtrl__EccReplayEn__SHIFT 0x1
+#define UMCCH2_0_EccCtrl__UCFatalEn__SHIFT 0x8
+#define UMCCH2_0_EccCtrl__RdEccEn__SHIFT 0xa
+#define UMCCH2_0_EccCtrl__PoisonFatalDis__SHIFT 0xc
+#define UMCCH2_0_EccCtrl__PoisonInhibit__SHIFT 0xd
+#define UMCCH2_0_EccCtrl__WrEccEn_MASK 0x00000001L
+#define UMCCH2_0_EccCtrl__EccReplayEn_MASK 0x00000002L
+#define UMCCH2_0_EccCtrl__UCFatalEn_MASK 0x00000100L
+#define UMCCH2_0_EccCtrl__RdEccEn_MASK 0x00000400L
+#define UMCCH2_0_EccCtrl__PoisonFatalDis_MASK 0x00001000L
+#define UMCCH2_0_EccCtrl__PoisonInhibit_MASK 0x00002000L
+//UMCCH2_0_UmcLocalCap
+#define UMCCH2_0_UmcLocalCap__EccDis__SHIFT 0x0
+#define UMCCH2_0_UmcLocalCap__Spare__SHIFT 0x1
+#define UMCCH2_0_UmcLocalCap__WrDis__SHIFT 0x1f
+#define UMCCH2_0_UmcLocalCap__EccDis_MASK 0x00000001L
+#define UMCCH2_0_UmcLocalCap__Spare_MASK 0x0000003EL
+#define UMCCH2_0_UmcLocalCap__WrDis_MASK 0x80000000L
+//UMCCH2_0_EccErrCntSel
+#define UMCCH2_0_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0
+#define UMCCH2_0_EccErrCntSel__EccErrInt__SHIFT 0xc
+#define UMCCH2_0_EccErrCntSel__EccErrCntEn__SHIFT 0xf
+#define UMCCH2_0_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL
+#define UMCCH2_0_EccErrCntSel__EccErrInt_MASK 0x00003000L
+#define UMCCH2_0_EccErrCntSel__EccErrCntEn_MASK 0x00008000L
+//UMCCH2_0_EccErrCnt
+#define UMCCH2_0_EccErrCnt__EccErrCnt__SHIFT 0x0
+#define UMCCH2_0_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL
+//UMCCH2_0_PerfMonCtlClk
+#define UMCCH2_0_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0
+#define UMCCH2_0_PerfMonCtlClk__ClkGate__SHIFT 0x16
+#define UMCCH2_0_PerfMonCtlClk__GlblReset__SHIFT 0x18
+#define UMCCH2_0_PerfMonCtlClk__GlblMonEn__SHIFT 0x19
+#define UMCCH2_0_PerfMonCtlClk__NumCounters__SHIFT 0x1a
+#define UMCCH2_0_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f
+#define UMCCH2_0_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL
+#define UMCCH2_0_PerfMonCtlClk__ClkGate_MASK 0x00400000L
+#define UMCCH2_0_PerfMonCtlClk__GlblReset_MASK 0x01000000L
+#define UMCCH2_0_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L
+#define UMCCH2_0_PerfMonCtlClk__NumCounters_MASK 0x3C000000L
+#define UMCCH2_0_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L
+//UMCCH2_0_PerfMonCtrClk_Lo
+#define UMCCH2_0_PerfMonCtrClk_Lo__Data__SHIFT 0x0
+#define UMCCH2_0_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_0_PerfMonCtrClk_Hi
+#define UMCCH2_0_PerfMonCtrClk_Hi__Data__SHIFT 0x0
+#define UMCCH2_0_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_0_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_0_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L
+//UMCCH2_0_PerfMonCtl1
+#define UMCCH2_0_PerfMonCtl1__EventSelect__SHIFT 0x0
+#define UMCCH2_0_PerfMonCtl1__RdWrMask__SHIFT 0x8
+#define UMCCH2_0_PerfMonCtl1__PriorityMask__SHIFT 0xa
+#define UMCCH2_0_PerfMonCtl1__ReqSizeMask__SHIFT 0xe
+#define UMCCH2_0_PerfMonCtl1__BankSel__SHIFT 0x10
+#define UMCCH2_0_PerfMonCtl1__VCSel__SHIFT 0x18
+#define UMCCH2_0_PerfMonCtl1__SubChanMask__SHIFT 0x1d
+#define UMCCH2_0_PerfMonCtl1__Enable__SHIFT 0x1f
+#define UMCCH2_0_PerfMonCtl1__EventSelect_MASK 0x000000FFL
+#define UMCCH2_0_PerfMonCtl1__RdWrMask_MASK 0x00000300L
+#define UMCCH2_0_PerfMonCtl1__PriorityMask_MASK 0x00003C00L
+#define UMCCH2_0_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH2_0_PerfMonCtl1__BankSel_MASK 0x00FF0000L
+#define UMCCH2_0_PerfMonCtl1__VCSel_MASK 0x1F000000L
+#define UMCCH2_0_PerfMonCtl1__SubChanMask_MASK 0x60000000L
+#define UMCCH2_0_PerfMonCtl1__Enable_MASK 0x80000000L
+//UMCCH2_0_PerfMonCtr1_Lo
+#define UMCCH2_0_PerfMonCtr1_Lo__Data__SHIFT 0x0
+#define UMCCH2_0_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_0_PerfMonCtr1_Hi
+#define UMCCH2_0_PerfMonCtr1_Hi__Data__SHIFT 0x0
+#define UMCCH2_0_PerfMonCtr1_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_0_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH2_0_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH2_0_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_0_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L
+#define UMCCH2_0_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH2_0_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH2_0_PerfMonCtl2
+#define UMCCH2_0_PerfMonCtl2__EventSelect__SHIFT 0x0
+#define UMCCH2_0_PerfMonCtl2__RdWrMask__SHIFT 0x8
+#define UMCCH2_0_PerfMonCtl2__PriorityMask__SHIFT 0xa
+#define UMCCH2_0_PerfMonCtl2__ReqSizeMask__SHIFT 0xe
+#define UMCCH2_0_PerfMonCtl2__BankSel__SHIFT 0x10
+#define UMCCH2_0_PerfMonCtl2__VCSel__SHIFT 0x18
+#define UMCCH2_0_PerfMonCtl2__SubChanMask__SHIFT 0x1d
+#define UMCCH2_0_PerfMonCtl2__Enable__SHIFT 0x1f
+#define UMCCH2_0_PerfMonCtl2__EventSelect_MASK 0x000000FFL
+#define UMCCH2_0_PerfMonCtl2__RdWrMask_MASK 0x00000300L
+#define UMCCH2_0_PerfMonCtl2__PriorityMask_MASK 0x00003C00L
+#define UMCCH2_0_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH2_0_PerfMonCtl2__BankSel_MASK 0x00FF0000L
+#define UMCCH2_0_PerfMonCtl2__VCSel_MASK 0x1F000000L
+#define UMCCH2_0_PerfMonCtl2__SubChanMask_MASK 0x60000000L
+#define UMCCH2_0_PerfMonCtl2__Enable_MASK 0x80000000L
+//UMCCH2_0_PerfMonCtr2_Lo
+#define UMCCH2_0_PerfMonCtr2_Lo__Data__SHIFT 0x0
+#define UMCCH2_0_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_0_PerfMonCtr2_Hi
+#define UMCCH2_0_PerfMonCtr2_Hi__Data__SHIFT 0x0
+#define UMCCH2_0_PerfMonCtr2_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_0_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH2_0_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH2_0_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_0_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L
+#define UMCCH2_0_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH2_0_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH2_0_PerfMonCtl3
+#define UMCCH2_0_PerfMonCtl3__EventSelect__SHIFT 0x0
+#define UMCCH2_0_PerfMonCtl3__RdWrMask__SHIFT 0x8
+#define UMCCH2_0_PerfMonCtl3__PriorityMask__SHIFT 0xa
+#define UMCCH2_0_PerfMonCtl3__ReqSizeMask__SHIFT 0xe
+#define UMCCH2_0_PerfMonCtl3__BankSel__SHIFT 0x10
+#define UMCCH2_0_PerfMonCtl3__VCSel__SHIFT 0x18
+#define UMCCH2_0_PerfMonCtl3__SubChanMask__SHIFT 0x1d
+#define UMCCH2_0_PerfMonCtl3__Enable__SHIFT 0x1f
+#define UMCCH2_0_PerfMonCtl3__EventSelect_MASK 0x000000FFL
+#define UMCCH2_0_PerfMonCtl3__RdWrMask_MASK 0x00000300L
+#define UMCCH2_0_PerfMonCtl3__PriorityMask_MASK 0x00003C00L
+#define UMCCH2_0_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH2_0_PerfMonCtl3__BankSel_MASK 0x00FF0000L
+#define UMCCH2_0_PerfMonCtl3__VCSel_MASK 0x1F000000L
+#define UMCCH2_0_PerfMonCtl3__SubChanMask_MASK 0x60000000L
+#define UMCCH2_0_PerfMonCtl3__Enable_MASK 0x80000000L
+//UMCCH2_0_PerfMonCtr3_Lo
+#define UMCCH2_0_PerfMonCtr3_Lo__Data__SHIFT 0x0
+#define UMCCH2_0_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_0_PerfMonCtr3_Hi
+#define UMCCH2_0_PerfMonCtr3_Hi__Data__SHIFT 0x0
+#define UMCCH2_0_PerfMonCtr3_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_0_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH2_0_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH2_0_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_0_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L
+#define UMCCH2_0_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH2_0_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH2_0_PerfMonCtl4
+#define UMCCH2_0_PerfMonCtl4__EventSelect__SHIFT 0x0
+#define UMCCH2_0_PerfMonCtl4__RdWrMask__SHIFT 0x8
+#define UMCCH2_0_PerfMonCtl4__PriorityMask__SHIFT 0xa
+#define UMCCH2_0_PerfMonCtl4__ReqSizeMask__SHIFT 0xe
+#define UMCCH2_0_PerfMonCtl4__BankSel__SHIFT 0x10
+#define UMCCH2_0_PerfMonCtl4__VCSel__SHIFT 0x18
+#define UMCCH2_0_PerfMonCtl4__SubChanMask__SHIFT 0x1d
+#define UMCCH2_0_PerfMonCtl4__Enable__SHIFT 0x1f
+#define UMCCH2_0_PerfMonCtl4__EventSelect_MASK 0x000000FFL
+#define UMCCH2_0_PerfMonCtl4__RdWrMask_MASK 0x00000300L
+#define UMCCH2_0_PerfMonCtl4__PriorityMask_MASK 0x00003C00L
+#define UMCCH2_0_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH2_0_PerfMonCtl4__BankSel_MASK 0x00FF0000L
+#define UMCCH2_0_PerfMonCtl4__VCSel_MASK 0x1F000000L
+#define UMCCH2_0_PerfMonCtl4__SubChanMask_MASK 0x60000000L
+#define UMCCH2_0_PerfMonCtl4__Enable_MASK 0x80000000L
+//UMCCH2_0_PerfMonCtr4_Lo
+#define UMCCH2_0_PerfMonCtr4_Lo__Data__SHIFT 0x0
+#define UMCCH2_0_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_0_PerfMonCtr4_Hi
+#define UMCCH2_0_PerfMonCtr4_Hi__Data__SHIFT 0x0
+#define UMCCH2_0_PerfMonCtr4_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_0_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH2_0_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH2_0_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_0_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L
+#define UMCCH2_0_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH2_0_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH2_0_PerfMonCtl5
+#define UMCCH2_0_PerfMonCtl5__EventSelect__SHIFT 0x0
+#define UMCCH2_0_PerfMonCtl5__RdWrMask__SHIFT 0x8
+#define UMCCH2_0_PerfMonCtl5__PriorityMask__SHIFT 0xa
+#define UMCCH2_0_PerfMonCtl5__ReqSizeMask__SHIFT 0xe
+#define UMCCH2_0_PerfMonCtl5__BankSel__SHIFT 0x10
+#define UMCCH2_0_PerfMonCtl5__VCSel__SHIFT 0x18
+#define UMCCH2_0_PerfMonCtl5__SubChanMask__SHIFT 0x1d
+#define UMCCH2_0_PerfMonCtl5__Enable__SHIFT 0x1f
+#define UMCCH2_0_PerfMonCtl5__EventSelect_MASK 0x000000FFL
+#define UMCCH2_0_PerfMonCtl5__RdWrMask_MASK 0x00000300L
+#define UMCCH2_0_PerfMonCtl5__PriorityMask_MASK 0x00003C00L
+#define UMCCH2_0_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH2_0_PerfMonCtl5__BankSel_MASK 0x00FF0000L
+#define UMCCH2_0_PerfMonCtl5__VCSel_MASK 0x1F000000L
+#define UMCCH2_0_PerfMonCtl5__SubChanMask_MASK 0x60000000L
+#define UMCCH2_0_PerfMonCtl5__Enable_MASK 0x80000000L
+//UMCCH2_0_PerfMonCtr5_Lo
+#define UMCCH2_0_PerfMonCtr5_Lo__Data__SHIFT 0x0
+#define UMCCH2_0_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_0_PerfMonCtr5_Hi
+#define UMCCH2_0_PerfMonCtr5_Hi__Data__SHIFT 0x0
+#define UMCCH2_0_PerfMonCtr5_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_0_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH2_0_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH2_0_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_0_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L
+#define UMCCH2_0_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH2_0_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH2_0_PerfMonCtl6
+#define UMCCH2_0_PerfMonCtl6__EventSelect__SHIFT 0x0
+#define UMCCH2_0_PerfMonCtl6__RdWrMask__SHIFT 0x8
+#define UMCCH2_0_PerfMonCtl6__PriorityMask__SHIFT 0xa
+#define UMCCH2_0_PerfMonCtl6__ReqSizeMask__SHIFT 0xe
+#define UMCCH2_0_PerfMonCtl6__BankSel__SHIFT 0x10
+#define UMCCH2_0_PerfMonCtl6__VCSel__SHIFT 0x18
+#define UMCCH2_0_PerfMonCtl6__SubChanMask__SHIFT 0x1d
+#define UMCCH2_0_PerfMonCtl6__Enable__SHIFT 0x1f
+#define UMCCH2_0_PerfMonCtl6__EventSelect_MASK 0x000000FFL
+#define UMCCH2_0_PerfMonCtl6__RdWrMask_MASK 0x00000300L
+#define UMCCH2_0_PerfMonCtl6__PriorityMask_MASK 0x00003C00L
+#define UMCCH2_0_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH2_0_PerfMonCtl6__BankSel_MASK 0x00FF0000L
+#define UMCCH2_0_PerfMonCtl6__VCSel_MASK 0x1F000000L
+#define UMCCH2_0_PerfMonCtl6__SubChanMask_MASK 0x60000000L
+#define UMCCH2_0_PerfMonCtl6__Enable_MASK 0x80000000L
+//UMCCH2_0_PerfMonCtr6_Lo
+#define UMCCH2_0_PerfMonCtr6_Lo__Data__SHIFT 0x0
+#define UMCCH2_0_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_0_PerfMonCtr6_Hi
+#define UMCCH2_0_PerfMonCtr6_Hi__Data__SHIFT 0x0
+#define UMCCH2_0_PerfMonCtr6_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_0_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH2_0_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH2_0_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_0_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L
+#define UMCCH2_0_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH2_0_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH2_0_PerfMonCtl7
+#define UMCCH2_0_PerfMonCtl7__EventSelect__SHIFT 0x0
+#define UMCCH2_0_PerfMonCtl7__RdWrMask__SHIFT 0x8
+#define UMCCH2_0_PerfMonCtl7__PriorityMask__SHIFT 0xa
+#define UMCCH2_0_PerfMonCtl7__ReqSizeMask__SHIFT 0xe
+#define UMCCH2_0_PerfMonCtl7__BankSel__SHIFT 0x10
+#define UMCCH2_0_PerfMonCtl7__VCSel__SHIFT 0x18
+#define UMCCH2_0_PerfMonCtl7__SubChanMask__SHIFT 0x1d
+#define UMCCH2_0_PerfMonCtl7__Enable__SHIFT 0x1f
+#define UMCCH2_0_PerfMonCtl7__EventSelect_MASK 0x000000FFL
+#define UMCCH2_0_PerfMonCtl7__RdWrMask_MASK 0x00000300L
+#define UMCCH2_0_PerfMonCtl7__PriorityMask_MASK 0x00003C00L
+#define UMCCH2_0_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH2_0_PerfMonCtl7__BankSel_MASK 0x00FF0000L
+#define UMCCH2_0_PerfMonCtl7__VCSel_MASK 0x1F000000L
+#define UMCCH2_0_PerfMonCtl7__SubChanMask_MASK 0x60000000L
+#define UMCCH2_0_PerfMonCtl7__Enable_MASK 0x80000000L
+//UMCCH2_0_PerfMonCtr7_Lo
+#define UMCCH2_0_PerfMonCtr7_Lo__Data__SHIFT 0x0
+#define UMCCH2_0_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_0_PerfMonCtr7_Hi
+#define UMCCH2_0_PerfMonCtr7_Hi__Data__SHIFT 0x0
+#define UMCCH2_0_PerfMonCtr7_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_0_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH2_0_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH2_0_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_0_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L
+#define UMCCH2_0_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH2_0_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH2_0_PerfMonCtl8
+#define UMCCH2_0_PerfMonCtl8__EventSelect__SHIFT 0x0
+#define UMCCH2_0_PerfMonCtl8__RdWrMask__SHIFT 0x8
+#define UMCCH2_0_PerfMonCtl8__PriorityMask__SHIFT 0xa
+#define UMCCH2_0_PerfMonCtl8__ReqSizeMask__SHIFT 0xe
+#define UMCCH2_0_PerfMonCtl8__BankSel__SHIFT 0x10
+#define UMCCH2_0_PerfMonCtl8__VCSel__SHIFT 0x18
+#define UMCCH2_0_PerfMonCtl8__SubChanMask__SHIFT 0x1d
+#define UMCCH2_0_PerfMonCtl8__Enable__SHIFT 0x1f
+#define UMCCH2_0_PerfMonCtl8__EventSelect_MASK 0x000000FFL
+#define UMCCH2_0_PerfMonCtl8__RdWrMask_MASK 0x00000300L
+#define UMCCH2_0_PerfMonCtl8__PriorityMask_MASK 0x00003C00L
+#define UMCCH2_0_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH2_0_PerfMonCtl8__BankSel_MASK 0x00FF0000L
+#define UMCCH2_0_PerfMonCtl8__VCSel_MASK 0x1F000000L
+#define UMCCH2_0_PerfMonCtl8__SubChanMask_MASK 0x60000000L
+#define UMCCH2_0_PerfMonCtl8__Enable_MASK 0x80000000L
+//UMCCH2_0_PerfMonCtr8_Lo
+#define UMCCH2_0_PerfMonCtr8_Lo__Data__SHIFT 0x0
+#define UMCCH2_0_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_0_PerfMonCtr8_Hi
+#define UMCCH2_0_PerfMonCtr8_Hi__Data__SHIFT 0x0
+#define UMCCH2_0_PerfMonCtr8_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_0_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH2_0_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH2_0_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_0_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L
+#define UMCCH2_0_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH2_0_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L
+
+
+// addressBlock: umc_w_phy_umc0_umcch3_umcchdec
+//UMCCH3_0_BaseAddrCS0
+#define UMCCH3_0_BaseAddrCS0__CSEnable__SHIFT 0x0
+#define UMCCH3_0_BaseAddrCS0__BaseAddr__SHIFT 0x1
+#define UMCCH3_0_BaseAddrCS0__CSEnable_MASK 0x00000001L
+#define UMCCH3_0_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL
+//UMCCH3_0_AddrMaskCS01
+#define UMCCH3_0_AddrMaskCS01__AddrMask__SHIFT 0x1
+#define UMCCH3_0_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL
+//UMCCH3_0_AddrSelCS01
+#define UMCCH3_0_AddrSelCS01__BankBit0__SHIFT 0x0
+#define UMCCH3_0_AddrSelCS01__BankBit1__SHIFT 0x4
+#define UMCCH3_0_AddrSelCS01__BankBit2__SHIFT 0x8
+#define UMCCH3_0_AddrSelCS01__BankBit3__SHIFT 0xc
+#define UMCCH3_0_AddrSelCS01__BankBit4__SHIFT 0x10
+#define UMCCH3_0_AddrSelCS01__RowLo__SHIFT 0x18
+#define UMCCH3_0_AddrSelCS01__RowHi__SHIFT 0x1c
+#define UMCCH3_0_AddrSelCS01__BankBit0_MASK 0x0000000FL
+#define UMCCH3_0_AddrSelCS01__BankBit1_MASK 0x000000F0L
+#define UMCCH3_0_AddrSelCS01__BankBit2_MASK 0x00000F00L
+#define UMCCH3_0_AddrSelCS01__BankBit3_MASK 0x0000F000L
+#define UMCCH3_0_AddrSelCS01__BankBit4_MASK 0x001F0000L
+#define UMCCH3_0_AddrSelCS01__RowLo_MASK 0x0F000000L
+#define UMCCH3_0_AddrSelCS01__RowHi_MASK 0xF0000000L
+//UMCCH3_0_AddrHashBank0
+#define UMCCH3_0_AddrHashBank0__XorEnable__SHIFT 0x0
+#define UMCCH3_0_AddrHashBank0__ColXor__SHIFT 0x1
+#define UMCCH3_0_AddrHashBank0__RowXor__SHIFT 0xe
+#define UMCCH3_0_AddrHashBank0__XorEnable_MASK 0x00000001L
+#define UMCCH3_0_AddrHashBank0__ColXor_MASK 0x00003FFEL
+#define UMCCH3_0_AddrHashBank0__RowXor_MASK 0xFFFFC000L
+//UMCCH3_0_AddrHashBank1
+#define UMCCH3_0_AddrHashBank1__XorEnable__SHIFT 0x0
+#define UMCCH3_0_AddrHashBank1__ColXor__SHIFT 0x1
+#define UMCCH3_0_AddrHashBank1__RowXor__SHIFT 0xe
+#define UMCCH3_0_AddrHashBank1__XorEnable_MASK 0x00000001L
+#define UMCCH3_0_AddrHashBank1__ColXor_MASK 0x00003FFEL
+#define UMCCH3_0_AddrHashBank1__RowXor_MASK 0xFFFFC000L
+//UMCCH3_0_AddrHashBank2
+#define UMCCH3_0_AddrHashBank2__XorEnable__SHIFT 0x0
+#define UMCCH3_0_AddrHashBank2__ColXor__SHIFT 0x1
+#define UMCCH3_0_AddrHashBank2__RowXor__SHIFT 0xe
+#define UMCCH3_0_AddrHashBank2__XorEnable_MASK 0x00000001L
+#define UMCCH3_0_AddrHashBank2__ColXor_MASK 0x00003FFEL
+#define UMCCH3_0_AddrHashBank2__RowXor_MASK 0xFFFFC000L
+//UMCCH3_0_AddrHashBank3
+#define UMCCH3_0_AddrHashBank3__XorEnable__SHIFT 0x0
+#define UMCCH3_0_AddrHashBank3__ColXor__SHIFT 0x1
+#define UMCCH3_0_AddrHashBank3__RowXor__SHIFT 0xe
+#define UMCCH3_0_AddrHashBank3__XorEnable_MASK 0x00000001L
+#define UMCCH3_0_AddrHashBank3__ColXor_MASK 0x00003FFEL
+#define UMCCH3_0_AddrHashBank3__RowXor_MASK 0xFFFFC000L
+//UMCCH3_0_AddrHashBank4
+#define UMCCH3_0_AddrHashBank4__XorEnable__SHIFT 0x0
+#define UMCCH3_0_AddrHashBank4__ColXor__SHIFT 0x1
+#define UMCCH3_0_AddrHashBank4__RowXor__SHIFT 0xe
+#define UMCCH3_0_AddrHashBank4__XorEnable_MASK 0x00000001L
+#define UMCCH3_0_AddrHashBank4__ColXor_MASK 0x00003FFEL
+#define UMCCH3_0_AddrHashBank4__RowXor_MASK 0xFFFFC000L
+//UMCCH3_0_AddrHashBank5
+#define UMCCH3_0_AddrHashBank5__XorEnable__SHIFT 0x0
+#define UMCCH3_0_AddrHashBank5__ColXor__SHIFT 0x1
+#define UMCCH3_0_AddrHashBank5__RowXor__SHIFT 0xe
+#define UMCCH3_0_AddrHashBank5__XorEnable_MASK 0x00000001L
+#define UMCCH3_0_AddrHashBank5__ColXor_MASK 0x00003FFEL
+#define UMCCH3_0_AddrHashBank5__RowXor_MASK 0xFFFFC000L
+//UMCCH3_0_UMC_CONFIG
+#define UMCCH3_0_UMC_CONFIG__DDR_TYPE__SHIFT 0x0
+#define UMCCH3_0_UMC_CONFIG__BurstLength__SHIFT 0x8
+#define UMCCH3_0_UMC_CONFIG__BurstCtrl__SHIFT 0xa
+#define UMCCH3_0_UMC_CONFIG__DramReady__SHIFT 0x1f
+#define UMCCH3_0_UMC_CONFIG__DDR_TYPE_MASK 0x00000007L
+#define UMCCH3_0_UMC_CONFIG__BurstLength_MASK 0x00000300L
+#define UMCCH3_0_UMC_CONFIG__BurstCtrl_MASK 0x00000C00L
+#define UMCCH3_0_UMC_CONFIG__DramReady_MASK 0x80000000L
+//UMCCH3_0_EccCtrl
+#define UMCCH3_0_EccCtrl__WrEccEn__SHIFT 0x0
+#define UMCCH3_0_EccCtrl__EccReplayEn__SHIFT 0x1
+#define UMCCH3_0_EccCtrl__UCFatalEn__SHIFT 0x8
+#define UMCCH3_0_EccCtrl__RdEccEn__SHIFT 0xa
+#define UMCCH3_0_EccCtrl__PoisonFatalDis__SHIFT 0xc
+#define UMCCH3_0_EccCtrl__PoisonInhibit__SHIFT 0xd
+#define UMCCH3_0_EccCtrl__WrEccEn_MASK 0x00000001L
+#define UMCCH3_0_EccCtrl__EccReplayEn_MASK 0x00000002L
+#define UMCCH3_0_EccCtrl__UCFatalEn_MASK 0x00000100L
+#define UMCCH3_0_EccCtrl__RdEccEn_MASK 0x00000400L
+#define UMCCH3_0_EccCtrl__PoisonFatalDis_MASK 0x00001000L
+#define UMCCH3_0_EccCtrl__PoisonInhibit_MASK 0x00002000L
+//UMCCH3_0_UmcLocalCap
+#define UMCCH3_0_UmcLocalCap__EccDis__SHIFT 0x0
+#define UMCCH3_0_UmcLocalCap__Spare__SHIFT 0x1
+#define UMCCH3_0_UmcLocalCap__WrDis__SHIFT 0x1f
+#define UMCCH3_0_UmcLocalCap__EccDis_MASK 0x00000001L
+#define UMCCH3_0_UmcLocalCap__Spare_MASK 0x0000003EL
+#define UMCCH3_0_UmcLocalCap__WrDis_MASK 0x80000000L
+//UMCCH3_0_EccErrCntSel
+#define UMCCH3_0_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0
+#define UMCCH3_0_EccErrCntSel__EccErrInt__SHIFT 0xc
+#define UMCCH3_0_EccErrCntSel__EccErrCntEn__SHIFT 0xf
+#define UMCCH3_0_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL
+#define UMCCH3_0_EccErrCntSel__EccErrInt_MASK 0x00003000L
+#define UMCCH3_0_EccErrCntSel__EccErrCntEn_MASK 0x00008000L
+//UMCCH3_0_EccErrCnt
+#define UMCCH3_0_EccErrCnt__EccErrCnt__SHIFT 0x0
+#define UMCCH3_0_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL
+//UMCCH3_0_PerfMonCtlClk
+#define UMCCH3_0_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0
+#define UMCCH3_0_PerfMonCtlClk__ClkGate__SHIFT 0x16
+#define UMCCH3_0_PerfMonCtlClk__GlblReset__SHIFT 0x18
+#define UMCCH3_0_PerfMonCtlClk__GlblMonEn__SHIFT 0x19
+#define UMCCH3_0_PerfMonCtlClk__NumCounters__SHIFT 0x1a
+#define UMCCH3_0_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f
+#define UMCCH3_0_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL
+#define UMCCH3_0_PerfMonCtlClk__ClkGate_MASK 0x00400000L
+#define UMCCH3_0_PerfMonCtlClk__GlblReset_MASK 0x01000000L
+#define UMCCH3_0_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L
+#define UMCCH3_0_PerfMonCtlClk__NumCounters_MASK 0x3C000000L
+#define UMCCH3_0_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L
+//UMCCH3_0_PerfMonCtrClk_Lo
+#define UMCCH3_0_PerfMonCtrClk_Lo__Data__SHIFT 0x0
+#define UMCCH3_0_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_0_PerfMonCtrClk_Hi
+#define UMCCH3_0_PerfMonCtrClk_Hi__Data__SHIFT 0x0
+#define UMCCH3_0_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_0_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_0_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L
+//UMCCH3_0_PerfMonCtl1
+#define UMCCH3_0_PerfMonCtl1__EventSelect__SHIFT 0x0
+#define UMCCH3_0_PerfMonCtl1__RdWrMask__SHIFT 0x8
+#define UMCCH3_0_PerfMonCtl1__PriorityMask__SHIFT 0xa
+#define UMCCH3_0_PerfMonCtl1__ReqSizeMask__SHIFT 0xe
+#define UMCCH3_0_PerfMonCtl1__BankSel__SHIFT 0x10
+#define UMCCH3_0_PerfMonCtl1__VCSel__SHIFT 0x18
+#define UMCCH3_0_PerfMonCtl1__SubChanMask__SHIFT 0x1d
+#define UMCCH3_0_PerfMonCtl1__Enable__SHIFT 0x1f
+#define UMCCH3_0_PerfMonCtl1__EventSelect_MASK 0x000000FFL
+#define UMCCH3_0_PerfMonCtl1__RdWrMask_MASK 0x00000300L
+#define UMCCH3_0_PerfMonCtl1__PriorityMask_MASK 0x00003C00L
+#define UMCCH3_0_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH3_0_PerfMonCtl1__BankSel_MASK 0x00FF0000L
+#define UMCCH3_0_PerfMonCtl1__VCSel_MASK 0x1F000000L
+#define UMCCH3_0_PerfMonCtl1__SubChanMask_MASK 0x60000000L
+#define UMCCH3_0_PerfMonCtl1__Enable_MASK 0x80000000L
+//UMCCH3_0_PerfMonCtr1_Lo
+#define UMCCH3_0_PerfMonCtr1_Lo__Data__SHIFT 0x0
+#define UMCCH3_0_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_0_PerfMonCtr1_Hi
+#define UMCCH3_0_PerfMonCtr1_Hi__Data__SHIFT 0x0
+#define UMCCH3_0_PerfMonCtr1_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_0_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH3_0_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH3_0_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_0_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L
+#define UMCCH3_0_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH3_0_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH3_0_PerfMonCtl2
+#define UMCCH3_0_PerfMonCtl2__EventSelect__SHIFT 0x0
+#define UMCCH3_0_PerfMonCtl2__RdWrMask__SHIFT 0x8
+#define UMCCH3_0_PerfMonCtl2__PriorityMask__SHIFT 0xa
+#define UMCCH3_0_PerfMonCtl2__ReqSizeMask__SHIFT 0xe
+#define UMCCH3_0_PerfMonCtl2__BankSel__SHIFT 0x10
+#define UMCCH3_0_PerfMonCtl2__VCSel__SHIFT 0x18
+#define UMCCH3_0_PerfMonCtl2__SubChanMask__SHIFT 0x1d
+#define UMCCH3_0_PerfMonCtl2__Enable__SHIFT 0x1f
+#define UMCCH3_0_PerfMonCtl2__EventSelect_MASK 0x000000FFL
+#define UMCCH3_0_PerfMonCtl2__RdWrMask_MASK 0x00000300L
+#define UMCCH3_0_PerfMonCtl2__PriorityMask_MASK 0x00003C00L
+#define UMCCH3_0_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH3_0_PerfMonCtl2__BankSel_MASK 0x00FF0000L
+#define UMCCH3_0_PerfMonCtl2__VCSel_MASK 0x1F000000L
+#define UMCCH3_0_PerfMonCtl2__SubChanMask_MASK 0x60000000L
+#define UMCCH3_0_PerfMonCtl2__Enable_MASK 0x80000000L
+//UMCCH3_0_PerfMonCtr2_Lo
+#define UMCCH3_0_PerfMonCtr2_Lo__Data__SHIFT 0x0
+#define UMCCH3_0_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_0_PerfMonCtr2_Hi
+#define UMCCH3_0_PerfMonCtr2_Hi__Data__SHIFT 0x0
+#define UMCCH3_0_PerfMonCtr2_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_0_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH3_0_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH3_0_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_0_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L
+#define UMCCH3_0_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH3_0_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH3_0_PerfMonCtl3
+#define UMCCH3_0_PerfMonCtl3__EventSelect__SHIFT 0x0
+#define UMCCH3_0_PerfMonCtl3__RdWrMask__SHIFT 0x8
+#define UMCCH3_0_PerfMonCtl3__PriorityMask__SHIFT 0xa
+#define UMCCH3_0_PerfMonCtl3__ReqSizeMask__SHIFT 0xe
+#define UMCCH3_0_PerfMonCtl3__BankSel__SHIFT 0x10
+#define UMCCH3_0_PerfMonCtl3__VCSel__SHIFT 0x18
+#define UMCCH3_0_PerfMonCtl3__SubChanMask__SHIFT 0x1d
+#define UMCCH3_0_PerfMonCtl3__Enable__SHIFT 0x1f
+#define UMCCH3_0_PerfMonCtl3__EventSelect_MASK 0x000000FFL
+#define UMCCH3_0_PerfMonCtl3__RdWrMask_MASK 0x00000300L
+#define UMCCH3_0_PerfMonCtl3__PriorityMask_MASK 0x00003C00L
+#define UMCCH3_0_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH3_0_PerfMonCtl3__BankSel_MASK 0x00FF0000L
+#define UMCCH3_0_PerfMonCtl3__VCSel_MASK 0x1F000000L
+#define UMCCH3_0_PerfMonCtl3__SubChanMask_MASK 0x60000000L
+#define UMCCH3_0_PerfMonCtl3__Enable_MASK 0x80000000L
+//UMCCH3_0_PerfMonCtr3_Lo
+#define UMCCH3_0_PerfMonCtr3_Lo__Data__SHIFT 0x0
+#define UMCCH3_0_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_0_PerfMonCtr3_Hi
+#define UMCCH3_0_PerfMonCtr3_Hi__Data__SHIFT 0x0
+#define UMCCH3_0_PerfMonCtr3_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_0_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH3_0_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH3_0_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_0_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L
+#define UMCCH3_0_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH3_0_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH3_0_PerfMonCtl4
+#define UMCCH3_0_PerfMonCtl4__EventSelect__SHIFT 0x0
+#define UMCCH3_0_PerfMonCtl4__RdWrMask__SHIFT 0x8
+#define UMCCH3_0_PerfMonCtl4__PriorityMask__SHIFT 0xa
+#define UMCCH3_0_PerfMonCtl4__ReqSizeMask__SHIFT 0xe
+#define UMCCH3_0_PerfMonCtl4__BankSel__SHIFT 0x10
+#define UMCCH3_0_PerfMonCtl4__VCSel__SHIFT 0x18
+#define UMCCH3_0_PerfMonCtl4__SubChanMask__SHIFT 0x1d
+#define UMCCH3_0_PerfMonCtl4__Enable__SHIFT 0x1f
+#define UMCCH3_0_PerfMonCtl4__EventSelect_MASK 0x000000FFL
+#define UMCCH3_0_PerfMonCtl4__RdWrMask_MASK 0x00000300L
+#define UMCCH3_0_PerfMonCtl4__PriorityMask_MASK 0x00003C00L
+#define UMCCH3_0_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH3_0_PerfMonCtl4__BankSel_MASK 0x00FF0000L
+#define UMCCH3_0_PerfMonCtl4__VCSel_MASK 0x1F000000L
+#define UMCCH3_0_PerfMonCtl4__SubChanMask_MASK 0x60000000L
+#define UMCCH3_0_PerfMonCtl4__Enable_MASK 0x80000000L
+//UMCCH3_0_PerfMonCtr4_Lo
+#define UMCCH3_0_PerfMonCtr4_Lo__Data__SHIFT 0x0
+#define UMCCH3_0_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_0_PerfMonCtr4_Hi
+#define UMCCH3_0_PerfMonCtr4_Hi__Data__SHIFT 0x0
+#define UMCCH3_0_PerfMonCtr4_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_0_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH3_0_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH3_0_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_0_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L
+#define UMCCH3_0_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH3_0_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH3_0_PerfMonCtl5
+#define UMCCH3_0_PerfMonCtl5__EventSelect__SHIFT 0x0
+#define UMCCH3_0_PerfMonCtl5__RdWrMask__SHIFT 0x8
+#define UMCCH3_0_PerfMonCtl5__PriorityMask__SHIFT 0xa
+#define UMCCH3_0_PerfMonCtl5__ReqSizeMask__SHIFT 0xe
+#define UMCCH3_0_PerfMonCtl5__BankSel__SHIFT 0x10
+#define UMCCH3_0_PerfMonCtl5__VCSel__SHIFT 0x18
+#define UMCCH3_0_PerfMonCtl5__SubChanMask__SHIFT 0x1d
+#define UMCCH3_0_PerfMonCtl5__Enable__SHIFT 0x1f
+#define UMCCH3_0_PerfMonCtl5__EventSelect_MASK 0x000000FFL
+#define UMCCH3_0_PerfMonCtl5__RdWrMask_MASK 0x00000300L
+#define UMCCH3_0_PerfMonCtl5__PriorityMask_MASK 0x00003C00L
+#define UMCCH3_0_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH3_0_PerfMonCtl5__BankSel_MASK 0x00FF0000L
+#define UMCCH3_0_PerfMonCtl5__VCSel_MASK 0x1F000000L
+#define UMCCH3_0_PerfMonCtl5__SubChanMask_MASK 0x60000000L
+#define UMCCH3_0_PerfMonCtl5__Enable_MASK 0x80000000L
+//UMCCH3_0_PerfMonCtr5_Lo
+#define UMCCH3_0_PerfMonCtr5_Lo__Data__SHIFT 0x0
+#define UMCCH3_0_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_0_PerfMonCtr5_Hi
+#define UMCCH3_0_PerfMonCtr5_Hi__Data__SHIFT 0x0
+#define UMCCH3_0_PerfMonCtr5_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_0_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH3_0_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH3_0_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_0_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L
+#define UMCCH3_0_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH3_0_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH3_0_PerfMonCtl6
+#define UMCCH3_0_PerfMonCtl6__EventSelect__SHIFT 0x0
+#define UMCCH3_0_PerfMonCtl6__RdWrMask__SHIFT 0x8
+#define UMCCH3_0_PerfMonCtl6__PriorityMask__SHIFT 0xa
+#define UMCCH3_0_PerfMonCtl6__ReqSizeMask__SHIFT 0xe
+#define UMCCH3_0_PerfMonCtl6__BankSel__SHIFT 0x10
+#define UMCCH3_0_PerfMonCtl6__VCSel__SHIFT 0x18
+#define UMCCH3_0_PerfMonCtl6__SubChanMask__SHIFT 0x1d
+#define UMCCH3_0_PerfMonCtl6__Enable__SHIFT 0x1f
+#define UMCCH3_0_PerfMonCtl6__EventSelect_MASK 0x000000FFL
+#define UMCCH3_0_PerfMonCtl6__RdWrMask_MASK 0x00000300L
+#define UMCCH3_0_PerfMonCtl6__PriorityMask_MASK 0x00003C00L
+#define UMCCH3_0_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH3_0_PerfMonCtl6__BankSel_MASK 0x00FF0000L
+#define UMCCH3_0_PerfMonCtl6__VCSel_MASK 0x1F000000L
+#define UMCCH3_0_PerfMonCtl6__SubChanMask_MASK 0x60000000L
+#define UMCCH3_0_PerfMonCtl6__Enable_MASK 0x80000000L
+//UMCCH3_0_PerfMonCtr6_Lo
+#define UMCCH3_0_PerfMonCtr6_Lo__Data__SHIFT 0x0
+#define UMCCH3_0_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_0_PerfMonCtr6_Hi
+#define UMCCH3_0_PerfMonCtr6_Hi__Data__SHIFT 0x0
+#define UMCCH3_0_PerfMonCtr6_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_0_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH3_0_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH3_0_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_0_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L
+#define UMCCH3_0_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH3_0_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH3_0_PerfMonCtl7
+#define UMCCH3_0_PerfMonCtl7__EventSelect__SHIFT 0x0
+#define UMCCH3_0_PerfMonCtl7__RdWrMask__SHIFT 0x8
+#define UMCCH3_0_PerfMonCtl7__PriorityMask__SHIFT 0xa
+#define UMCCH3_0_PerfMonCtl7__ReqSizeMask__SHIFT 0xe
+#define UMCCH3_0_PerfMonCtl7__BankSel__SHIFT 0x10
+#define UMCCH3_0_PerfMonCtl7__VCSel__SHIFT 0x18
+#define UMCCH3_0_PerfMonCtl7__SubChanMask__SHIFT 0x1d
+#define UMCCH3_0_PerfMonCtl7__Enable__SHIFT 0x1f
+#define UMCCH3_0_PerfMonCtl7__EventSelect_MASK 0x000000FFL
+#define UMCCH3_0_PerfMonCtl7__RdWrMask_MASK 0x00000300L
+#define UMCCH3_0_PerfMonCtl7__PriorityMask_MASK 0x00003C00L
+#define UMCCH3_0_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH3_0_PerfMonCtl7__BankSel_MASK 0x00FF0000L
+#define UMCCH3_0_PerfMonCtl7__VCSel_MASK 0x1F000000L
+#define UMCCH3_0_PerfMonCtl7__SubChanMask_MASK 0x60000000L
+#define UMCCH3_0_PerfMonCtl7__Enable_MASK 0x80000000L
+//UMCCH3_0_PerfMonCtr7_Lo
+#define UMCCH3_0_PerfMonCtr7_Lo__Data__SHIFT 0x0
+#define UMCCH3_0_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_0_PerfMonCtr7_Hi
+#define UMCCH3_0_PerfMonCtr7_Hi__Data__SHIFT 0x0
+#define UMCCH3_0_PerfMonCtr7_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_0_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH3_0_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH3_0_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_0_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L
+#define UMCCH3_0_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH3_0_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH3_0_PerfMonCtl8
+#define UMCCH3_0_PerfMonCtl8__EventSelect__SHIFT 0x0
+#define UMCCH3_0_PerfMonCtl8__RdWrMask__SHIFT 0x8
+#define UMCCH3_0_PerfMonCtl8__PriorityMask__SHIFT 0xa
+#define UMCCH3_0_PerfMonCtl8__ReqSizeMask__SHIFT 0xe
+#define UMCCH3_0_PerfMonCtl8__BankSel__SHIFT 0x10
+#define UMCCH3_0_PerfMonCtl8__VCSel__SHIFT 0x18
+#define UMCCH3_0_PerfMonCtl8__SubChanMask__SHIFT 0x1d
+#define UMCCH3_0_PerfMonCtl8__Enable__SHIFT 0x1f
+#define UMCCH3_0_PerfMonCtl8__EventSelect_MASK 0x000000FFL
+#define UMCCH3_0_PerfMonCtl8__RdWrMask_MASK 0x00000300L
+#define UMCCH3_0_PerfMonCtl8__PriorityMask_MASK 0x00003C00L
+#define UMCCH3_0_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH3_0_PerfMonCtl8__BankSel_MASK 0x00FF0000L
+#define UMCCH3_0_PerfMonCtl8__VCSel_MASK 0x1F000000L
+#define UMCCH3_0_PerfMonCtl8__SubChanMask_MASK 0x60000000L
+#define UMCCH3_0_PerfMonCtl8__Enable_MASK 0x80000000L
+//UMCCH3_0_PerfMonCtr8_Lo
+#define UMCCH3_0_PerfMonCtr8_Lo__Data__SHIFT 0x0
+#define UMCCH3_0_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_0_PerfMonCtr8_Hi
+#define UMCCH3_0_PerfMonCtr8_Hi__Data__SHIFT 0x0
+#define UMCCH3_0_PerfMonCtr8_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_0_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH3_0_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH3_0_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_0_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L
+#define UMCCH3_0_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH3_0_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L
+
+
+// addressBlock: umc_w_phy_umc0_umcch4_umcchdec
+//UMCCH4_0_BaseAddrCS0
+#define UMCCH4_0_BaseAddrCS0__CSEnable__SHIFT 0x0
+#define UMCCH4_0_BaseAddrCS0__BaseAddr__SHIFT 0x1
+#define UMCCH4_0_BaseAddrCS0__CSEnable_MASK 0x00000001L
+#define UMCCH4_0_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL
+//UMCCH4_0_AddrMaskCS01
+#define UMCCH4_0_AddrMaskCS01__AddrMask__SHIFT 0x1
+#define UMCCH4_0_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL
+//UMCCH4_0_AddrSelCS01
+#define UMCCH4_0_AddrSelCS01__BankBit0__SHIFT 0x0
+#define UMCCH4_0_AddrSelCS01__BankBit1__SHIFT 0x4
+#define UMCCH4_0_AddrSelCS01__BankBit2__SHIFT 0x8
+#define UMCCH4_0_AddrSelCS01__BankBit3__SHIFT 0xc
+#define UMCCH4_0_AddrSelCS01__BankBit4__SHIFT 0x10
+#define UMCCH4_0_AddrSelCS01__RowLo__SHIFT 0x18
+#define UMCCH4_0_AddrSelCS01__RowHi__SHIFT 0x1c
+#define UMCCH4_0_AddrSelCS01__BankBit0_MASK 0x0000000FL
+#define UMCCH4_0_AddrSelCS01__BankBit1_MASK 0x000000F0L
+#define UMCCH4_0_AddrSelCS01__BankBit2_MASK 0x00000F00L
+#define UMCCH4_0_AddrSelCS01__BankBit3_MASK 0x0000F000L
+#define UMCCH4_0_AddrSelCS01__BankBit4_MASK 0x001F0000L
+#define UMCCH4_0_AddrSelCS01__RowLo_MASK 0x0F000000L
+#define UMCCH4_0_AddrSelCS01__RowHi_MASK 0xF0000000L
+//UMCCH4_0_AddrHashBank0
+#define UMCCH4_0_AddrHashBank0__XorEnable__SHIFT 0x0
+#define UMCCH4_0_AddrHashBank0__ColXor__SHIFT 0x1
+#define UMCCH4_0_AddrHashBank0__RowXor__SHIFT 0xe
+#define UMCCH4_0_AddrHashBank0__XorEnable_MASK 0x00000001L
+#define UMCCH4_0_AddrHashBank0__ColXor_MASK 0x00003FFEL
+#define UMCCH4_0_AddrHashBank0__RowXor_MASK 0xFFFFC000L
+//UMCCH4_0_AddrHashBank1
+#define UMCCH4_0_AddrHashBank1__XorEnable__SHIFT 0x0
+#define UMCCH4_0_AddrHashBank1__ColXor__SHIFT 0x1
+#define UMCCH4_0_AddrHashBank1__RowXor__SHIFT 0xe
+#define UMCCH4_0_AddrHashBank1__XorEnable_MASK 0x00000001L
+#define UMCCH4_0_AddrHashBank1__ColXor_MASK 0x00003FFEL
+#define UMCCH4_0_AddrHashBank1__RowXor_MASK 0xFFFFC000L
+//UMCCH4_0_AddrHashBank2
+#define UMCCH4_0_AddrHashBank2__XorEnable__SHIFT 0x0
+#define UMCCH4_0_AddrHashBank2__ColXor__SHIFT 0x1
+#define UMCCH4_0_AddrHashBank2__RowXor__SHIFT 0xe
+#define UMCCH4_0_AddrHashBank2__XorEnable_MASK 0x00000001L
+#define UMCCH4_0_AddrHashBank2__ColXor_MASK 0x00003FFEL
+#define UMCCH4_0_AddrHashBank2__RowXor_MASK 0xFFFFC000L
+//UMCCH4_0_AddrHashBank3
+#define UMCCH4_0_AddrHashBank3__XorEnable__SHIFT 0x0
+#define UMCCH4_0_AddrHashBank3__ColXor__SHIFT 0x1
+#define UMCCH4_0_AddrHashBank3__RowXor__SHIFT 0xe
+#define UMCCH4_0_AddrHashBank3__XorEnable_MASK 0x00000001L
+#define UMCCH4_0_AddrHashBank3__ColXor_MASK 0x00003FFEL
+#define UMCCH4_0_AddrHashBank3__RowXor_MASK 0xFFFFC000L
+//UMCCH4_0_AddrHashBank4
+#define UMCCH4_0_AddrHashBank4__XorEnable__SHIFT 0x0
+#define UMCCH4_0_AddrHashBank4__ColXor__SHIFT 0x1
+#define UMCCH4_0_AddrHashBank4__RowXor__SHIFT 0xe
+#define UMCCH4_0_AddrHashBank4__XorEnable_MASK 0x00000001L
+#define UMCCH4_0_AddrHashBank4__ColXor_MASK 0x00003FFEL
+#define UMCCH4_0_AddrHashBank4__RowXor_MASK 0xFFFFC000L
+//UMCCH4_0_AddrHashBank5
+#define UMCCH4_0_AddrHashBank5__XorEnable__SHIFT 0x0
+#define UMCCH4_0_AddrHashBank5__ColXor__SHIFT 0x1
+#define UMCCH4_0_AddrHashBank5__RowXor__SHIFT 0xe
+#define UMCCH4_0_AddrHashBank5__XorEnable_MASK 0x00000001L
+#define UMCCH4_0_AddrHashBank5__ColXor_MASK 0x00003FFEL
+#define UMCCH4_0_AddrHashBank5__RowXor_MASK 0xFFFFC000L
+//UMCCH4_0_EccErrCntSel
+#define UMCCH4_0_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0
+#define UMCCH4_0_EccErrCntSel__EccErrInt__SHIFT 0xc
+#define UMCCH4_0_EccErrCntSel__EccErrCntEn__SHIFT 0xf
+#define UMCCH4_0_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL
+#define UMCCH4_0_EccErrCntSel__EccErrInt_MASK 0x00003000L
+#define UMCCH4_0_EccErrCntSel__EccErrCntEn_MASK 0x00008000L
+//UMCCH4_0_EccErrCnt
+#define UMCCH4_0_EccErrCnt__EccErrCnt__SHIFT 0x0
+#define UMCCH4_0_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL
+//UMCCH4_0_PerfMonCtlClk
+#define UMCCH4_0_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0
+#define UMCCH4_0_PerfMonCtlClk__ClkGate__SHIFT 0x16
+#define UMCCH4_0_PerfMonCtlClk__GlblReset__SHIFT 0x18
+#define UMCCH4_0_PerfMonCtlClk__GlblMonEn__SHIFT 0x19
+#define UMCCH4_0_PerfMonCtlClk__NumCounters__SHIFT 0x1a
+#define UMCCH4_0_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f
+#define UMCCH4_0_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL
+#define UMCCH4_0_PerfMonCtlClk__ClkGate_MASK 0x00400000L
+#define UMCCH4_0_PerfMonCtlClk__GlblReset_MASK 0x01000000L
+#define UMCCH4_0_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L
+#define UMCCH4_0_PerfMonCtlClk__NumCounters_MASK 0x3C000000L
+#define UMCCH4_0_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L
+//UMCCH4_0_PerfMonCtrClk_Lo
+#define UMCCH4_0_PerfMonCtrClk_Lo__Data__SHIFT 0x0
+#define UMCCH4_0_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_0_PerfMonCtrClk_Hi
+#define UMCCH4_0_PerfMonCtrClk_Hi__Data__SHIFT 0x0
+#define UMCCH4_0_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_0_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_0_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L
+//UMCCH4_0_PerfMonCtl1
+#define UMCCH4_0_PerfMonCtl1__EventSelect__SHIFT 0x0
+#define UMCCH4_0_PerfMonCtl1__RdWrMask__SHIFT 0x8
+#define UMCCH4_0_PerfMonCtl1__PriorityMask__SHIFT 0xa
+#define UMCCH4_0_PerfMonCtl1__ReqSizeMask__SHIFT 0xe
+#define UMCCH4_0_PerfMonCtl1__BankSel__SHIFT 0x10
+#define UMCCH4_0_PerfMonCtl1__VCSel__SHIFT 0x18
+#define UMCCH4_0_PerfMonCtl1__SubChanMask__SHIFT 0x1d
+#define UMCCH4_0_PerfMonCtl1__Enable__SHIFT 0x1f
+#define UMCCH4_0_PerfMonCtl1__EventSelect_MASK 0x000000FFL
+#define UMCCH4_0_PerfMonCtl1__RdWrMask_MASK 0x00000300L
+#define UMCCH4_0_PerfMonCtl1__PriorityMask_MASK 0x00003C00L
+#define UMCCH4_0_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH4_0_PerfMonCtl1__BankSel_MASK 0x00FF0000L
+#define UMCCH4_0_PerfMonCtl1__VCSel_MASK 0x1F000000L
+#define UMCCH4_0_PerfMonCtl1__SubChanMask_MASK 0x60000000L
+#define UMCCH4_0_PerfMonCtl1__Enable_MASK 0x80000000L
+//UMCCH4_0_PerfMonCtr1_Lo
+#define UMCCH4_0_PerfMonCtr1_Lo__Data__SHIFT 0x0
+#define UMCCH4_0_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_0_PerfMonCtr1_Hi
+#define UMCCH4_0_PerfMonCtr1_Hi__Data__SHIFT 0x0
+#define UMCCH4_0_PerfMonCtr1_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_0_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH4_0_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH4_0_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_0_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L
+#define UMCCH4_0_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH4_0_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH4_0_PerfMonCtl2
+#define UMCCH4_0_PerfMonCtl2__EventSelect__SHIFT 0x0
+#define UMCCH4_0_PerfMonCtl2__RdWrMask__SHIFT 0x8
+#define UMCCH4_0_PerfMonCtl2__PriorityMask__SHIFT 0xa
+#define UMCCH4_0_PerfMonCtl2__ReqSizeMask__SHIFT 0xe
+#define UMCCH4_0_PerfMonCtl2__BankSel__SHIFT 0x10
+#define UMCCH4_0_PerfMonCtl2__VCSel__SHIFT 0x18
+#define UMCCH4_0_PerfMonCtl2__SubChanMask__SHIFT 0x1d
+#define UMCCH4_0_PerfMonCtl2__Enable__SHIFT 0x1f
+#define UMCCH4_0_PerfMonCtl2__EventSelect_MASK 0x000000FFL
+#define UMCCH4_0_PerfMonCtl2__RdWrMask_MASK 0x00000300L
+#define UMCCH4_0_PerfMonCtl2__PriorityMask_MASK 0x00003C00L
+#define UMCCH4_0_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH4_0_PerfMonCtl2__BankSel_MASK 0x00FF0000L
+#define UMCCH4_0_PerfMonCtl2__VCSel_MASK 0x1F000000L
+#define UMCCH4_0_PerfMonCtl2__SubChanMask_MASK 0x60000000L
+#define UMCCH4_0_PerfMonCtl2__Enable_MASK 0x80000000L
+//UMCCH4_0_PerfMonCtr2_Lo
+#define UMCCH4_0_PerfMonCtr2_Lo__Data__SHIFT 0x0
+#define UMCCH4_0_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_0_PerfMonCtr2_Hi
+#define UMCCH4_0_PerfMonCtr2_Hi__Data__SHIFT 0x0
+#define UMCCH4_0_PerfMonCtr2_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_0_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH4_0_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH4_0_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_0_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L
+#define UMCCH4_0_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH4_0_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH4_0_PerfMonCtl3
+#define UMCCH4_0_PerfMonCtl3__EventSelect__SHIFT 0x0
+#define UMCCH4_0_PerfMonCtl3__RdWrMask__SHIFT 0x8
+#define UMCCH4_0_PerfMonCtl3__PriorityMask__SHIFT 0xa
+#define UMCCH4_0_PerfMonCtl3__ReqSizeMask__SHIFT 0xe
+#define UMCCH4_0_PerfMonCtl3__BankSel__SHIFT 0x10
+#define UMCCH4_0_PerfMonCtl3__VCSel__SHIFT 0x18
+#define UMCCH4_0_PerfMonCtl3__SubChanMask__SHIFT 0x1d
+#define UMCCH4_0_PerfMonCtl3__Enable__SHIFT 0x1f
+#define UMCCH4_0_PerfMonCtl3__EventSelect_MASK 0x000000FFL
+#define UMCCH4_0_PerfMonCtl3__RdWrMask_MASK 0x00000300L
+#define UMCCH4_0_PerfMonCtl3__PriorityMask_MASK 0x00003C00L
+#define UMCCH4_0_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH4_0_PerfMonCtl3__BankSel_MASK 0x00FF0000L
+#define UMCCH4_0_PerfMonCtl3__VCSel_MASK 0x1F000000L
+#define UMCCH4_0_PerfMonCtl3__SubChanMask_MASK 0x60000000L
+#define UMCCH4_0_PerfMonCtl3__Enable_MASK 0x80000000L
+//UMCCH4_0_PerfMonCtr3_Lo
+#define UMCCH4_0_PerfMonCtr3_Lo__Data__SHIFT 0x0
+#define UMCCH4_0_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_0_PerfMonCtr3_Hi
+#define UMCCH4_0_PerfMonCtr3_Hi__Data__SHIFT 0x0
+#define UMCCH4_0_PerfMonCtr3_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_0_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH4_0_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH4_0_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_0_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L
+#define UMCCH4_0_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH4_0_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH4_0_PerfMonCtl4
+#define UMCCH4_0_PerfMonCtl4__EventSelect__SHIFT 0x0
+#define UMCCH4_0_PerfMonCtl4__RdWrMask__SHIFT 0x8
+#define UMCCH4_0_PerfMonCtl4__PriorityMask__SHIFT 0xa
+#define UMCCH4_0_PerfMonCtl4__ReqSizeMask__SHIFT 0xe
+#define UMCCH4_0_PerfMonCtl4__BankSel__SHIFT 0x10
+#define UMCCH4_0_PerfMonCtl4__VCSel__SHIFT 0x18
+#define UMCCH4_0_PerfMonCtl4__SubChanMask__SHIFT 0x1d
+#define UMCCH4_0_PerfMonCtl4__Enable__SHIFT 0x1f
+#define UMCCH4_0_PerfMonCtl4__EventSelect_MASK 0x000000FFL
+#define UMCCH4_0_PerfMonCtl4__RdWrMask_MASK 0x00000300L
+#define UMCCH4_0_PerfMonCtl4__PriorityMask_MASK 0x00003C00L
+#define UMCCH4_0_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH4_0_PerfMonCtl4__BankSel_MASK 0x00FF0000L
+#define UMCCH4_0_PerfMonCtl4__VCSel_MASK 0x1F000000L
+#define UMCCH4_0_PerfMonCtl4__SubChanMask_MASK 0x60000000L
+#define UMCCH4_0_PerfMonCtl4__Enable_MASK 0x80000000L
+//UMCCH4_0_PerfMonCtr4_Lo
+#define UMCCH4_0_PerfMonCtr4_Lo__Data__SHIFT 0x0
+#define UMCCH4_0_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_0_PerfMonCtr4_Hi
+#define UMCCH4_0_PerfMonCtr4_Hi__Data__SHIFT 0x0
+#define UMCCH4_0_PerfMonCtr4_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_0_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH4_0_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH4_0_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_0_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L
+#define UMCCH4_0_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH4_0_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH4_0_PerfMonCtl5
+#define UMCCH4_0_PerfMonCtl5__EventSelect__SHIFT 0x0
+#define UMCCH4_0_PerfMonCtl5__RdWrMask__SHIFT 0x8
+#define UMCCH4_0_PerfMonCtl5__PriorityMask__SHIFT 0xa
+#define UMCCH4_0_PerfMonCtl5__ReqSizeMask__SHIFT 0xe
+#define UMCCH4_0_PerfMonCtl5__BankSel__SHIFT 0x10
+#define UMCCH4_0_PerfMonCtl5__VCSel__SHIFT 0x18
+#define UMCCH4_0_PerfMonCtl5__SubChanMask__SHIFT 0x1d
+#define UMCCH4_0_PerfMonCtl5__Enable__SHIFT 0x1f
+#define UMCCH4_0_PerfMonCtl5__EventSelect_MASK 0x000000FFL
+#define UMCCH4_0_PerfMonCtl5__RdWrMask_MASK 0x00000300L
+#define UMCCH4_0_PerfMonCtl5__PriorityMask_MASK 0x00003C00L
+#define UMCCH4_0_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH4_0_PerfMonCtl5__BankSel_MASK 0x00FF0000L
+#define UMCCH4_0_PerfMonCtl5__VCSel_MASK 0x1F000000L
+#define UMCCH4_0_PerfMonCtl5__SubChanMask_MASK 0x60000000L
+#define UMCCH4_0_PerfMonCtl5__Enable_MASK 0x80000000L
+//UMCCH4_0_PerfMonCtr5_Lo
+#define UMCCH4_0_PerfMonCtr5_Lo__Data__SHIFT 0x0
+#define UMCCH4_0_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_0_PerfMonCtr5_Hi
+#define UMCCH4_0_PerfMonCtr5_Hi__Data__SHIFT 0x0
+#define UMCCH4_0_PerfMonCtr5_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_0_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH4_0_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH4_0_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_0_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L
+#define UMCCH4_0_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH4_0_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH4_0_PerfMonCtl6
+#define UMCCH4_0_PerfMonCtl6__EventSelect__SHIFT 0x0
+#define UMCCH4_0_PerfMonCtl6__RdWrMask__SHIFT 0x8
+#define UMCCH4_0_PerfMonCtl6__PriorityMask__SHIFT 0xa
+#define UMCCH4_0_PerfMonCtl6__ReqSizeMask__SHIFT 0xe
+#define UMCCH4_0_PerfMonCtl6__BankSel__SHIFT 0x10
+#define UMCCH4_0_PerfMonCtl6__VCSel__SHIFT 0x18
+#define UMCCH4_0_PerfMonCtl6__SubChanMask__SHIFT 0x1d
+#define UMCCH4_0_PerfMonCtl6__Enable__SHIFT 0x1f
+#define UMCCH4_0_PerfMonCtl6__EventSelect_MASK 0x000000FFL
+#define UMCCH4_0_PerfMonCtl6__RdWrMask_MASK 0x00000300L
+#define UMCCH4_0_PerfMonCtl6__PriorityMask_MASK 0x00003C00L
+#define UMCCH4_0_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH4_0_PerfMonCtl6__BankSel_MASK 0x00FF0000L
+#define UMCCH4_0_PerfMonCtl6__VCSel_MASK 0x1F000000L
+#define UMCCH4_0_PerfMonCtl6__SubChanMask_MASK 0x60000000L
+#define UMCCH4_0_PerfMonCtl6__Enable_MASK 0x80000000L
+//UMCCH4_0_PerfMonCtr6_Lo
+#define UMCCH4_0_PerfMonCtr6_Lo__Data__SHIFT 0x0
+#define UMCCH4_0_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_0_PerfMonCtr6_Hi
+#define UMCCH4_0_PerfMonCtr6_Hi__Data__SHIFT 0x0
+#define UMCCH4_0_PerfMonCtr6_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_0_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH4_0_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH4_0_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_0_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L
+#define UMCCH4_0_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH4_0_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH4_0_PerfMonCtl7
+#define UMCCH4_0_PerfMonCtl7__EventSelect__SHIFT 0x0
+#define UMCCH4_0_PerfMonCtl7__RdWrMask__SHIFT 0x8
+#define UMCCH4_0_PerfMonCtl7__PriorityMask__SHIFT 0xa
+#define UMCCH4_0_PerfMonCtl7__ReqSizeMask__SHIFT 0xe
+#define UMCCH4_0_PerfMonCtl7__BankSel__SHIFT 0x10
+#define UMCCH4_0_PerfMonCtl7__VCSel__SHIFT 0x18
+#define UMCCH4_0_PerfMonCtl7__SubChanMask__SHIFT 0x1d
+#define UMCCH4_0_PerfMonCtl7__Enable__SHIFT 0x1f
+#define UMCCH4_0_PerfMonCtl7__EventSelect_MASK 0x000000FFL
+#define UMCCH4_0_PerfMonCtl7__RdWrMask_MASK 0x00000300L
+#define UMCCH4_0_PerfMonCtl7__PriorityMask_MASK 0x00003C00L
+#define UMCCH4_0_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH4_0_PerfMonCtl7__BankSel_MASK 0x00FF0000L
+#define UMCCH4_0_PerfMonCtl7__VCSel_MASK 0x1F000000L
+#define UMCCH4_0_PerfMonCtl7__SubChanMask_MASK 0x60000000L
+#define UMCCH4_0_PerfMonCtl7__Enable_MASK 0x80000000L
+//UMCCH4_0_PerfMonCtr7_Lo
+#define UMCCH4_0_PerfMonCtr7_Lo__Data__SHIFT 0x0
+#define UMCCH4_0_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_0_PerfMonCtr7_Hi
+#define UMCCH4_0_PerfMonCtr7_Hi__Data__SHIFT 0x0
+#define UMCCH4_0_PerfMonCtr7_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_0_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH4_0_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH4_0_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_0_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L
+#define UMCCH4_0_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH4_0_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH4_0_PerfMonCtl8
+#define UMCCH4_0_PerfMonCtl8__EventSelect__SHIFT 0x0
+#define UMCCH4_0_PerfMonCtl8__RdWrMask__SHIFT 0x8
+#define UMCCH4_0_PerfMonCtl8__PriorityMask__SHIFT 0xa
+#define UMCCH4_0_PerfMonCtl8__ReqSizeMask__SHIFT 0xe
+#define UMCCH4_0_PerfMonCtl8__BankSel__SHIFT 0x10
+#define UMCCH4_0_PerfMonCtl8__VCSel__SHIFT 0x18
+#define UMCCH4_0_PerfMonCtl8__SubChanMask__SHIFT 0x1d
+#define UMCCH4_0_PerfMonCtl8__Enable__SHIFT 0x1f
+#define UMCCH4_0_PerfMonCtl8__EventSelect_MASK 0x000000FFL
+#define UMCCH4_0_PerfMonCtl8__RdWrMask_MASK 0x00000300L
+#define UMCCH4_0_PerfMonCtl8__PriorityMask_MASK 0x00003C00L
+#define UMCCH4_0_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH4_0_PerfMonCtl8__BankSel_MASK 0x00FF0000L
+#define UMCCH4_0_PerfMonCtl8__VCSel_MASK 0x1F000000L
+#define UMCCH4_0_PerfMonCtl8__SubChanMask_MASK 0x60000000L
+#define UMCCH4_0_PerfMonCtl8__Enable_MASK 0x80000000L
+//UMCCH4_0_PerfMonCtr8_Lo
+#define UMCCH4_0_PerfMonCtr8_Lo__Data__SHIFT 0x0
+#define UMCCH4_0_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_0_PerfMonCtr8_Hi
+#define UMCCH4_0_PerfMonCtr8_Hi__Data__SHIFT 0x0
+#define UMCCH4_0_PerfMonCtr8_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_0_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH4_0_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH4_0_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_0_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L
+#define UMCCH4_0_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH4_0_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L
+
+
+// addressBlock: umc_w_phy_umc0_umcch5_umcchdec
+//UMCCH5_0_BaseAddrCS0
+#define UMCCH5_0_BaseAddrCS0__CSEnable__SHIFT 0x0
+#define UMCCH5_0_BaseAddrCS0__BaseAddr__SHIFT 0x1
+#define UMCCH5_0_BaseAddrCS0__CSEnable_MASK 0x00000001L
+#define UMCCH5_0_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL
+//UMCCH5_0_AddrMaskCS01
+#define UMCCH5_0_AddrMaskCS01__AddrMask__SHIFT 0x1
+#define UMCCH5_0_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL
+//UMCCH5_0_AddrSelCS01
+#define UMCCH5_0_AddrSelCS01__BankBit0__SHIFT 0x0
+#define UMCCH5_0_AddrSelCS01__BankBit1__SHIFT 0x4
+#define UMCCH5_0_AddrSelCS01__BankBit2__SHIFT 0x8
+#define UMCCH5_0_AddrSelCS01__BankBit3__SHIFT 0xc
+#define UMCCH5_0_AddrSelCS01__BankBit4__SHIFT 0x10
+#define UMCCH5_0_AddrSelCS01__RowLo__SHIFT 0x18
+#define UMCCH5_0_AddrSelCS01__RowHi__SHIFT 0x1c
+#define UMCCH5_0_AddrSelCS01__BankBit0_MASK 0x0000000FL
+#define UMCCH5_0_AddrSelCS01__BankBit1_MASK 0x000000F0L
+#define UMCCH5_0_AddrSelCS01__BankBit2_MASK 0x00000F00L
+#define UMCCH5_0_AddrSelCS01__BankBit3_MASK 0x0000F000L
+#define UMCCH5_0_AddrSelCS01__BankBit4_MASK 0x001F0000L
+#define UMCCH5_0_AddrSelCS01__RowLo_MASK 0x0F000000L
+#define UMCCH5_0_AddrSelCS01__RowHi_MASK 0xF0000000L
+//UMCCH5_0_AddrHashBank0
+#define UMCCH5_0_AddrHashBank0__XorEnable__SHIFT 0x0
+#define UMCCH5_0_AddrHashBank0__ColXor__SHIFT 0x1
+#define UMCCH5_0_AddrHashBank0__RowXor__SHIFT 0xe
+#define UMCCH5_0_AddrHashBank0__XorEnable_MASK 0x00000001L
+#define UMCCH5_0_AddrHashBank0__ColXor_MASK 0x00003FFEL
+#define UMCCH5_0_AddrHashBank0__RowXor_MASK 0xFFFFC000L
+//UMCCH5_0_AddrHashBank1
+#define UMCCH5_0_AddrHashBank1__XorEnable__SHIFT 0x0
+#define UMCCH5_0_AddrHashBank1__ColXor__SHIFT 0x1
+#define UMCCH5_0_AddrHashBank1__RowXor__SHIFT 0xe
+#define UMCCH5_0_AddrHashBank1__XorEnable_MASK 0x00000001L
+#define UMCCH5_0_AddrHashBank1__ColXor_MASK 0x00003FFEL
+#define UMCCH5_0_AddrHashBank1__RowXor_MASK 0xFFFFC000L
+//UMCCH5_0_AddrHashBank2
+#define UMCCH5_0_AddrHashBank2__XorEnable__SHIFT 0x0
+#define UMCCH5_0_AddrHashBank2__ColXor__SHIFT 0x1
+#define UMCCH5_0_AddrHashBank2__RowXor__SHIFT 0xe
+#define UMCCH5_0_AddrHashBank2__XorEnable_MASK 0x00000001L
+#define UMCCH5_0_AddrHashBank2__ColXor_MASK 0x00003FFEL
+#define UMCCH5_0_AddrHashBank2__RowXor_MASK 0xFFFFC000L
+//UMCCH5_0_AddrHashBank3
+#define UMCCH5_0_AddrHashBank3__XorEnable__SHIFT 0x0
+#define UMCCH5_0_AddrHashBank3__ColXor__SHIFT 0x1
+#define UMCCH5_0_AddrHashBank3__RowXor__SHIFT 0xe
+#define UMCCH5_0_AddrHashBank3__XorEnable_MASK 0x00000001L
+#define UMCCH5_0_AddrHashBank3__ColXor_MASK 0x00003FFEL
+#define UMCCH5_0_AddrHashBank3__RowXor_MASK 0xFFFFC000L
+//UMCCH5_0_AddrHashBank4
+#define UMCCH5_0_AddrHashBank4__XorEnable__SHIFT 0x0
+#define UMCCH5_0_AddrHashBank4__ColXor__SHIFT 0x1
+#define UMCCH5_0_AddrHashBank4__RowXor__SHIFT 0xe
+#define UMCCH5_0_AddrHashBank4__XorEnable_MASK 0x00000001L
+#define UMCCH5_0_AddrHashBank4__ColXor_MASK 0x00003FFEL
+#define UMCCH5_0_AddrHashBank4__RowXor_MASK 0xFFFFC000L
+//UMCCH5_0_AddrHashBank5
+#define UMCCH5_0_AddrHashBank5__XorEnable__SHIFT 0x0
+#define UMCCH5_0_AddrHashBank5__ColXor__SHIFT 0x1
+#define UMCCH5_0_AddrHashBank5__RowXor__SHIFT 0xe
+#define UMCCH5_0_AddrHashBank5__XorEnable_MASK 0x00000001L
+#define UMCCH5_0_AddrHashBank5__ColXor_MASK 0x00003FFEL
+#define UMCCH5_0_AddrHashBank5__RowXor_MASK 0xFFFFC000L
+//UMCCH5_0_EccErrCntSel
+#define UMCCH5_0_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0
+#define UMCCH5_0_EccErrCntSel__EccErrInt__SHIFT 0xc
+#define UMCCH5_0_EccErrCntSel__EccErrCntEn__SHIFT 0xf
+#define UMCCH5_0_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL
+#define UMCCH5_0_EccErrCntSel__EccErrInt_MASK 0x00003000L
+#define UMCCH5_0_EccErrCntSel__EccErrCntEn_MASK 0x00008000L
+//UMCCH5_0_EccErrCnt
+#define UMCCH5_0_EccErrCnt__EccErrCnt__SHIFT 0x0
+#define UMCCH5_0_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL
+//UMCCH5_0_PerfMonCtlClk
+#define UMCCH5_0_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0
+#define UMCCH5_0_PerfMonCtlClk__ClkGate__SHIFT 0x16
+#define UMCCH5_0_PerfMonCtlClk__GlblReset__SHIFT 0x18
+#define UMCCH5_0_PerfMonCtlClk__GlblMonEn__SHIFT 0x19
+#define UMCCH5_0_PerfMonCtlClk__NumCounters__SHIFT 0x1a
+#define UMCCH5_0_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f
+#define UMCCH5_0_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL
+#define UMCCH5_0_PerfMonCtlClk__ClkGate_MASK 0x00400000L
+#define UMCCH5_0_PerfMonCtlClk__GlblReset_MASK 0x01000000L
+#define UMCCH5_0_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L
+#define UMCCH5_0_PerfMonCtlClk__NumCounters_MASK 0x3C000000L
+#define UMCCH5_0_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L
+//UMCCH5_0_PerfMonCtrClk_Lo
+#define UMCCH5_0_PerfMonCtrClk_Lo__Data__SHIFT 0x0
+#define UMCCH5_0_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_0_PerfMonCtrClk_Hi
+#define UMCCH5_0_PerfMonCtrClk_Hi__Data__SHIFT 0x0
+#define UMCCH5_0_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_0_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_0_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L
+//UMCCH5_0_PerfMonCtl1
+#define UMCCH5_0_PerfMonCtl1__EventSelect__SHIFT 0x0
+#define UMCCH5_0_PerfMonCtl1__RdWrMask__SHIFT 0x8
+#define UMCCH5_0_PerfMonCtl1__PriorityMask__SHIFT 0xa
+#define UMCCH5_0_PerfMonCtl1__ReqSizeMask__SHIFT 0xe
+#define UMCCH5_0_PerfMonCtl1__BankSel__SHIFT 0x10
+#define UMCCH5_0_PerfMonCtl1__VCSel__SHIFT 0x18
+#define UMCCH5_0_PerfMonCtl1__SubChanMask__SHIFT 0x1d
+#define UMCCH5_0_PerfMonCtl1__Enable__SHIFT 0x1f
+#define UMCCH5_0_PerfMonCtl1__EventSelect_MASK 0x000000FFL
+#define UMCCH5_0_PerfMonCtl1__RdWrMask_MASK 0x00000300L
+#define UMCCH5_0_PerfMonCtl1__PriorityMask_MASK 0x00003C00L
+#define UMCCH5_0_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH5_0_PerfMonCtl1__BankSel_MASK 0x00FF0000L
+#define UMCCH5_0_PerfMonCtl1__VCSel_MASK 0x1F000000L
+#define UMCCH5_0_PerfMonCtl1__SubChanMask_MASK 0x60000000L
+#define UMCCH5_0_PerfMonCtl1__Enable_MASK 0x80000000L
+//UMCCH5_0_PerfMonCtr1_Lo
+#define UMCCH5_0_PerfMonCtr1_Lo__Data__SHIFT 0x0
+#define UMCCH5_0_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_0_PerfMonCtr1_Hi
+#define UMCCH5_0_PerfMonCtr1_Hi__Data__SHIFT 0x0
+#define UMCCH5_0_PerfMonCtr1_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_0_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH5_0_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH5_0_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_0_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L
+#define UMCCH5_0_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH5_0_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH5_0_PerfMonCtl2
+#define UMCCH5_0_PerfMonCtl2__EventSelect__SHIFT 0x0
+#define UMCCH5_0_PerfMonCtl2__RdWrMask__SHIFT 0x8
+#define UMCCH5_0_PerfMonCtl2__PriorityMask__SHIFT 0xa
+#define UMCCH5_0_PerfMonCtl2__ReqSizeMask__SHIFT 0xe
+#define UMCCH5_0_PerfMonCtl2__BankSel__SHIFT 0x10
+#define UMCCH5_0_PerfMonCtl2__VCSel__SHIFT 0x18
+#define UMCCH5_0_PerfMonCtl2__SubChanMask__SHIFT 0x1d
+#define UMCCH5_0_PerfMonCtl2__Enable__SHIFT 0x1f
+#define UMCCH5_0_PerfMonCtl2__EventSelect_MASK 0x000000FFL
+#define UMCCH5_0_PerfMonCtl2__RdWrMask_MASK 0x00000300L
+#define UMCCH5_0_PerfMonCtl2__PriorityMask_MASK 0x00003C00L
+#define UMCCH5_0_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH5_0_PerfMonCtl2__BankSel_MASK 0x00FF0000L
+#define UMCCH5_0_PerfMonCtl2__VCSel_MASK 0x1F000000L
+#define UMCCH5_0_PerfMonCtl2__SubChanMask_MASK 0x60000000L
+#define UMCCH5_0_PerfMonCtl2__Enable_MASK 0x80000000L
+//UMCCH5_0_PerfMonCtr2_Lo
+#define UMCCH5_0_PerfMonCtr2_Lo__Data__SHIFT 0x0
+#define UMCCH5_0_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_0_PerfMonCtr2_Hi
+#define UMCCH5_0_PerfMonCtr2_Hi__Data__SHIFT 0x0
+#define UMCCH5_0_PerfMonCtr2_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_0_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH5_0_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH5_0_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_0_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L
+#define UMCCH5_0_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH5_0_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH5_0_PerfMonCtl3
+#define UMCCH5_0_PerfMonCtl3__EventSelect__SHIFT 0x0
+#define UMCCH5_0_PerfMonCtl3__RdWrMask__SHIFT 0x8
+#define UMCCH5_0_PerfMonCtl3__PriorityMask__SHIFT 0xa
+#define UMCCH5_0_PerfMonCtl3__ReqSizeMask__SHIFT 0xe
+#define UMCCH5_0_PerfMonCtl3__BankSel__SHIFT 0x10
+#define UMCCH5_0_PerfMonCtl3__VCSel__SHIFT 0x18
+#define UMCCH5_0_PerfMonCtl3__SubChanMask__SHIFT 0x1d
+#define UMCCH5_0_PerfMonCtl3__Enable__SHIFT 0x1f
+#define UMCCH5_0_PerfMonCtl3__EventSelect_MASK 0x000000FFL
+#define UMCCH5_0_PerfMonCtl3__RdWrMask_MASK 0x00000300L
+#define UMCCH5_0_PerfMonCtl3__PriorityMask_MASK 0x00003C00L
+#define UMCCH5_0_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH5_0_PerfMonCtl3__BankSel_MASK 0x00FF0000L
+#define UMCCH5_0_PerfMonCtl3__VCSel_MASK 0x1F000000L
+#define UMCCH5_0_PerfMonCtl3__SubChanMask_MASK 0x60000000L
+#define UMCCH5_0_PerfMonCtl3__Enable_MASK 0x80000000L
+//UMCCH5_0_PerfMonCtr3_Lo
+#define UMCCH5_0_PerfMonCtr3_Lo__Data__SHIFT 0x0
+#define UMCCH5_0_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_0_PerfMonCtr3_Hi
+#define UMCCH5_0_PerfMonCtr3_Hi__Data__SHIFT 0x0
+#define UMCCH5_0_PerfMonCtr3_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_0_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH5_0_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH5_0_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_0_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L
+#define UMCCH5_0_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH5_0_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH5_0_PerfMonCtl4
+#define UMCCH5_0_PerfMonCtl4__EventSelect__SHIFT 0x0
+#define UMCCH5_0_PerfMonCtl4__RdWrMask__SHIFT 0x8
+#define UMCCH5_0_PerfMonCtl4__PriorityMask__SHIFT 0xa
+#define UMCCH5_0_PerfMonCtl4__ReqSizeMask__SHIFT 0xe
+#define UMCCH5_0_PerfMonCtl4__BankSel__SHIFT 0x10
+#define UMCCH5_0_PerfMonCtl4__VCSel__SHIFT 0x18
+#define UMCCH5_0_PerfMonCtl4__SubChanMask__SHIFT 0x1d
+#define UMCCH5_0_PerfMonCtl4__Enable__SHIFT 0x1f
+#define UMCCH5_0_PerfMonCtl4__EventSelect_MASK 0x000000FFL
+#define UMCCH5_0_PerfMonCtl4__RdWrMask_MASK 0x00000300L
+#define UMCCH5_0_PerfMonCtl4__PriorityMask_MASK 0x00003C00L
+#define UMCCH5_0_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH5_0_PerfMonCtl4__BankSel_MASK 0x00FF0000L
+#define UMCCH5_0_PerfMonCtl4__VCSel_MASK 0x1F000000L
+#define UMCCH5_0_PerfMonCtl4__SubChanMask_MASK 0x60000000L
+#define UMCCH5_0_PerfMonCtl4__Enable_MASK 0x80000000L
+//UMCCH5_0_PerfMonCtr4_Lo
+#define UMCCH5_0_PerfMonCtr4_Lo__Data__SHIFT 0x0
+#define UMCCH5_0_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_0_PerfMonCtr4_Hi
+#define UMCCH5_0_PerfMonCtr4_Hi__Data__SHIFT 0x0
+#define UMCCH5_0_PerfMonCtr4_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_0_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH5_0_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH5_0_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_0_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L
+#define UMCCH5_0_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH5_0_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH5_0_PerfMonCtl5
+#define UMCCH5_0_PerfMonCtl5__EventSelect__SHIFT 0x0
+#define UMCCH5_0_PerfMonCtl5__RdWrMask__SHIFT 0x8
+#define UMCCH5_0_PerfMonCtl5__PriorityMask__SHIFT 0xa
+#define UMCCH5_0_PerfMonCtl5__ReqSizeMask__SHIFT 0xe
+#define UMCCH5_0_PerfMonCtl5__BankSel__SHIFT 0x10
+#define UMCCH5_0_PerfMonCtl5__VCSel__SHIFT 0x18
+#define UMCCH5_0_PerfMonCtl5__SubChanMask__SHIFT 0x1d
+#define UMCCH5_0_PerfMonCtl5__Enable__SHIFT 0x1f
+#define UMCCH5_0_PerfMonCtl5__EventSelect_MASK 0x000000FFL
+#define UMCCH5_0_PerfMonCtl5__RdWrMask_MASK 0x00000300L
+#define UMCCH5_0_PerfMonCtl5__PriorityMask_MASK 0x00003C00L
+#define UMCCH5_0_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH5_0_PerfMonCtl5__BankSel_MASK 0x00FF0000L
+#define UMCCH5_0_PerfMonCtl5__VCSel_MASK 0x1F000000L
+#define UMCCH5_0_PerfMonCtl5__SubChanMask_MASK 0x60000000L
+#define UMCCH5_0_PerfMonCtl5__Enable_MASK 0x80000000L
+//UMCCH5_0_PerfMonCtr5_Lo
+#define UMCCH5_0_PerfMonCtr5_Lo__Data__SHIFT 0x0
+#define UMCCH5_0_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_0_PerfMonCtr5_Hi
+#define UMCCH5_0_PerfMonCtr5_Hi__Data__SHIFT 0x0
+#define UMCCH5_0_PerfMonCtr5_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_0_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH5_0_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH5_0_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_0_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L
+#define UMCCH5_0_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH5_0_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH5_0_PerfMonCtl6
+#define UMCCH5_0_PerfMonCtl6__EventSelect__SHIFT 0x0
+#define UMCCH5_0_PerfMonCtl6__RdWrMask__SHIFT 0x8
+#define UMCCH5_0_PerfMonCtl6__PriorityMask__SHIFT 0xa
+#define UMCCH5_0_PerfMonCtl6__ReqSizeMask__SHIFT 0xe
+#define UMCCH5_0_PerfMonCtl6__BankSel__SHIFT 0x10
+#define UMCCH5_0_PerfMonCtl6__VCSel__SHIFT 0x18
+#define UMCCH5_0_PerfMonCtl6__SubChanMask__SHIFT 0x1d
+#define UMCCH5_0_PerfMonCtl6__Enable__SHIFT 0x1f
+#define UMCCH5_0_PerfMonCtl6__EventSelect_MASK 0x000000FFL
+#define UMCCH5_0_PerfMonCtl6__RdWrMask_MASK 0x00000300L
+#define UMCCH5_0_PerfMonCtl6__PriorityMask_MASK 0x00003C00L
+#define UMCCH5_0_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH5_0_PerfMonCtl6__BankSel_MASK 0x00FF0000L
+#define UMCCH5_0_PerfMonCtl6__VCSel_MASK 0x1F000000L
+#define UMCCH5_0_PerfMonCtl6__SubChanMask_MASK 0x60000000L
+#define UMCCH5_0_PerfMonCtl6__Enable_MASK 0x80000000L
+//UMCCH5_0_PerfMonCtr6_Lo
+#define UMCCH5_0_PerfMonCtr6_Lo__Data__SHIFT 0x0
+#define UMCCH5_0_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_0_PerfMonCtr6_Hi
+#define UMCCH5_0_PerfMonCtr6_Hi__Data__SHIFT 0x0
+#define UMCCH5_0_PerfMonCtr6_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_0_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH5_0_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH5_0_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_0_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L
+#define UMCCH5_0_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH5_0_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH5_0_PerfMonCtl7
+#define UMCCH5_0_PerfMonCtl7__EventSelect__SHIFT 0x0
+#define UMCCH5_0_PerfMonCtl7__RdWrMask__SHIFT 0x8
+#define UMCCH5_0_PerfMonCtl7__PriorityMask__SHIFT 0xa
+#define UMCCH5_0_PerfMonCtl7__ReqSizeMask__SHIFT 0xe
+#define UMCCH5_0_PerfMonCtl7__BankSel__SHIFT 0x10
+#define UMCCH5_0_PerfMonCtl7__VCSel__SHIFT 0x18
+#define UMCCH5_0_PerfMonCtl7__SubChanMask__SHIFT 0x1d
+#define UMCCH5_0_PerfMonCtl7__Enable__SHIFT 0x1f
+#define UMCCH5_0_PerfMonCtl7__EventSelect_MASK 0x000000FFL
+#define UMCCH5_0_PerfMonCtl7__RdWrMask_MASK 0x00000300L
+#define UMCCH5_0_PerfMonCtl7__PriorityMask_MASK 0x00003C00L
+#define UMCCH5_0_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH5_0_PerfMonCtl7__BankSel_MASK 0x00FF0000L
+#define UMCCH5_0_PerfMonCtl7__VCSel_MASK 0x1F000000L
+#define UMCCH5_0_PerfMonCtl7__SubChanMask_MASK 0x60000000L
+#define UMCCH5_0_PerfMonCtl7__Enable_MASK 0x80000000L
+//UMCCH5_0_PerfMonCtr7_Lo
+#define UMCCH5_0_PerfMonCtr7_Lo__Data__SHIFT 0x0
+#define UMCCH5_0_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_0_PerfMonCtr7_Hi
+#define UMCCH5_0_PerfMonCtr7_Hi__Data__SHIFT 0x0
+#define UMCCH5_0_PerfMonCtr7_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_0_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH5_0_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH5_0_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_0_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L
+#define UMCCH5_0_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH5_0_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH5_0_PerfMonCtl8
+#define UMCCH5_0_PerfMonCtl8__EventSelect__SHIFT 0x0
+#define UMCCH5_0_PerfMonCtl8__RdWrMask__SHIFT 0x8
+#define UMCCH5_0_PerfMonCtl8__PriorityMask__SHIFT 0xa
+#define UMCCH5_0_PerfMonCtl8__ReqSizeMask__SHIFT 0xe
+#define UMCCH5_0_PerfMonCtl8__BankSel__SHIFT 0x10
+#define UMCCH5_0_PerfMonCtl8__VCSel__SHIFT 0x18
+#define UMCCH5_0_PerfMonCtl8__SubChanMask__SHIFT 0x1d
+#define UMCCH5_0_PerfMonCtl8__Enable__SHIFT 0x1f
+#define UMCCH5_0_PerfMonCtl8__EventSelect_MASK 0x000000FFL
+#define UMCCH5_0_PerfMonCtl8__RdWrMask_MASK 0x00000300L
+#define UMCCH5_0_PerfMonCtl8__PriorityMask_MASK 0x00003C00L
+#define UMCCH5_0_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH5_0_PerfMonCtl8__BankSel_MASK 0x00FF0000L
+#define UMCCH5_0_PerfMonCtl8__VCSel_MASK 0x1F000000L
+#define UMCCH5_0_PerfMonCtl8__SubChanMask_MASK 0x60000000L
+#define UMCCH5_0_PerfMonCtl8__Enable_MASK 0x80000000L
+//UMCCH5_0_PerfMonCtr8_Lo
+#define UMCCH5_0_PerfMonCtr8_Lo__Data__SHIFT 0x0
+#define UMCCH5_0_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_0_PerfMonCtr8_Hi
+#define UMCCH5_0_PerfMonCtr8_Hi__Data__SHIFT 0x0
+#define UMCCH5_0_PerfMonCtr8_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_0_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH5_0_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH5_0_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_0_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L
+#define UMCCH5_0_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH5_0_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L
+
+
+// addressBlock: umc_w_phy_umc0_umcch6_umcchdec
+//UMCCH6_0_BaseAddrCS0
+#define UMCCH6_0_BaseAddrCS0__CSEnable__SHIFT 0x0
+#define UMCCH6_0_BaseAddrCS0__BaseAddr__SHIFT 0x1
+#define UMCCH6_0_BaseAddrCS0__CSEnable_MASK 0x00000001L
+#define UMCCH6_0_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL
+//UMCCH6_0_AddrMaskCS01
+#define UMCCH6_0_AddrMaskCS01__AddrMask__SHIFT 0x1
+#define UMCCH6_0_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL
+//UMCCH6_0_AddrSelCS01
+#define UMCCH6_0_AddrSelCS01__BankBit0__SHIFT 0x0
+#define UMCCH6_0_AddrSelCS01__BankBit1__SHIFT 0x4
+#define UMCCH6_0_AddrSelCS01__BankBit2__SHIFT 0x8
+#define UMCCH6_0_AddrSelCS01__BankBit3__SHIFT 0xc
+#define UMCCH6_0_AddrSelCS01__BankBit4__SHIFT 0x10
+#define UMCCH6_0_AddrSelCS01__RowLo__SHIFT 0x18
+#define UMCCH6_0_AddrSelCS01__RowHi__SHIFT 0x1c
+#define UMCCH6_0_AddrSelCS01__BankBit0_MASK 0x0000000FL
+#define UMCCH6_0_AddrSelCS01__BankBit1_MASK 0x000000F0L
+#define UMCCH6_0_AddrSelCS01__BankBit2_MASK 0x00000F00L
+#define UMCCH6_0_AddrSelCS01__BankBit3_MASK 0x0000F000L
+#define UMCCH6_0_AddrSelCS01__BankBit4_MASK 0x001F0000L
+#define UMCCH6_0_AddrSelCS01__RowLo_MASK 0x0F000000L
+#define UMCCH6_0_AddrSelCS01__RowHi_MASK 0xF0000000L
+//UMCCH6_0_AddrHashBank0
+#define UMCCH6_0_AddrHashBank0__XorEnable__SHIFT 0x0
+#define UMCCH6_0_AddrHashBank0__ColXor__SHIFT 0x1
+#define UMCCH6_0_AddrHashBank0__RowXor__SHIFT 0xe
+#define UMCCH6_0_AddrHashBank0__XorEnable_MASK 0x00000001L
+#define UMCCH6_0_AddrHashBank0__ColXor_MASK 0x00003FFEL
+#define UMCCH6_0_AddrHashBank0__RowXor_MASK 0xFFFFC000L
+//UMCCH6_0_AddrHashBank1
+#define UMCCH6_0_AddrHashBank1__XorEnable__SHIFT 0x0
+#define UMCCH6_0_AddrHashBank1__ColXor__SHIFT 0x1
+#define UMCCH6_0_AddrHashBank1__RowXor__SHIFT 0xe
+#define UMCCH6_0_AddrHashBank1__XorEnable_MASK 0x00000001L
+#define UMCCH6_0_AddrHashBank1__ColXor_MASK 0x00003FFEL
+#define UMCCH6_0_AddrHashBank1__RowXor_MASK 0xFFFFC000L
+//UMCCH6_0_AddrHashBank2
+#define UMCCH6_0_AddrHashBank2__XorEnable__SHIFT 0x0
+#define UMCCH6_0_AddrHashBank2__ColXor__SHIFT 0x1
+#define UMCCH6_0_AddrHashBank2__RowXor__SHIFT 0xe
+#define UMCCH6_0_AddrHashBank2__XorEnable_MASK 0x00000001L
+#define UMCCH6_0_AddrHashBank2__ColXor_MASK 0x00003FFEL
+#define UMCCH6_0_AddrHashBank2__RowXor_MASK 0xFFFFC000L
+//UMCCH6_0_AddrHashBank3
+#define UMCCH6_0_AddrHashBank3__XorEnable__SHIFT 0x0
+#define UMCCH6_0_AddrHashBank3__ColXor__SHIFT 0x1
+#define UMCCH6_0_AddrHashBank3__RowXor__SHIFT 0xe
+#define UMCCH6_0_AddrHashBank3__XorEnable_MASK 0x00000001L
+#define UMCCH6_0_AddrHashBank3__ColXor_MASK 0x00003FFEL
+#define UMCCH6_0_AddrHashBank3__RowXor_MASK 0xFFFFC000L
+//UMCCH6_0_AddrHashBank4
+#define UMCCH6_0_AddrHashBank4__XorEnable__SHIFT 0x0
+#define UMCCH6_0_AddrHashBank4__ColXor__SHIFT 0x1
+#define UMCCH6_0_AddrHashBank4__RowXor__SHIFT 0xe
+#define UMCCH6_0_AddrHashBank4__XorEnable_MASK 0x00000001L
+#define UMCCH6_0_AddrHashBank4__ColXor_MASK 0x00003FFEL
+#define UMCCH6_0_AddrHashBank4__RowXor_MASK 0xFFFFC000L
+//UMCCH6_0_AddrHashBank5
+#define UMCCH6_0_AddrHashBank5__XorEnable__SHIFT 0x0
+#define UMCCH6_0_AddrHashBank5__ColXor__SHIFT 0x1
+#define UMCCH6_0_AddrHashBank5__RowXor__SHIFT 0xe
+#define UMCCH6_0_AddrHashBank5__XorEnable_MASK 0x00000001L
+#define UMCCH6_0_AddrHashBank5__ColXor_MASK 0x00003FFEL
+#define UMCCH6_0_AddrHashBank5__RowXor_MASK 0xFFFFC000L
+//UMCCH6_0_EccErrCntSel
+#define UMCCH6_0_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0
+#define UMCCH6_0_EccErrCntSel__EccErrInt__SHIFT 0xc
+#define UMCCH6_0_EccErrCntSel__EccErrCntEn__SHIFT 0xf
+#define UMCCH6_0_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL
+#define UMCCH6_0_EccErrCntSel__EccErrInt_MASK 0x00003000L
+#define UMCCH6_0_EccErrCntSel__EccErrCntEn_MASK 0x00008000L
+//UMCCH6_0_EccErrCnt
+#define UMCCH6_0_EccErrCnt__EccErrCnt__SHIFT 0x0
+#define UMCCH6_0_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL
+//UMCCH6_0_PerfMonCtlClk
+#define UMCCH6_0_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0
+#define UMCCH6_0_PerfMonCtlClk__ClkGate__SHIFT 0x16
+#define UMCCH6_0_PerfMonCtlClk__GlblReset__SHIFT 0x18
+#define UMCCH6_0_PerfMonCtlClk__GlblMonEn__SHIFT 0x19
+#define UMCCH6_0_PerfMonCtlClk__NumCounters__SHIFT 0x1a
+#define UMCCH6_0_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f
+#define UMCCH6_0_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL
+#define UMCCH6_0_PerfMonCtlClk__ClkGate_MASK 0x00400000L
+#define UMCCH6_0_PerfMonCtlClk__GlblReset_MASK 0x01000000L
+#define UMCCH6_0_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L
+#define UMCCH6_0_PerfMonCtlClk__NumCounters_MASK 0x3C000000L
+#define UMCCH6_0_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L
+//UMCCH6_0_PerfMonCtrClk_Lo
+#define UMCCH6_0_PerfMonCtrClk_Lo__Data__SHIFT 0x0
+#define UMCCH6_0_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_0_PerfMonCtrClk_Hi
+#define UMCCH6_0_PerfMonCtrClk_Hi__Data__SHIFT 0x0
+#define UMCCH6_0_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_0_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_0_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L
+//UMCCH6_0_PerfMonCtl1
+#define UMCCH6_0_PerfMonCtl1__EventSelect__SHIFT 0x0
+#define UMCCH6_0_PerfMonCtl1__RdWrMask__SHIFT 0x8
+#define UMCCH6_0_PerfMonCtl1__PriorityMask__SHIFT 0xa
+#define UMCCH6_0_PerfMonCtl1__ReqSizeMask__SHIFT 0xe
+#define UMCCH6_0_PerfMonCtl1__BankSel__SHIFT 0x10
+#define UMCCH6_0_PerfMonCtl1__VCSel__SHIFT 0x18
+#define UMCCH6_0_PerfMonCtl1__SubChanMask__SHIFT 0x1d
+#define UMCCH6_0_PerfMonCtl1__Enable__SHIFT 0x1f
+#define UMCCH6_0_PerfMonCtl1__EventSelect_MASK 0x000000FFL
+#define UMCCH6_0_PerfMonCtl1__RdWrMask_MASK 0x00000300L
+#define UMCCH6_0_PerfMonCtl1__PriorityMask_MASK 0x00003C00L
+#define UMCCH6_0_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH6_0_PerfMonCtl1__BankSel_MASK 0x00FF0000L
+#define UMCCH6_0_PerfMonCtl1__VCSel_MASK 0x1F000000L
+#define UMCCH6_0_PerfMonCtl1__SubChanMask_MASK 0x60000000L
+#define UMCCH6_0_PerfMonCtl1__Enable_MASK 0x80000000L
+//UMCCH6_0_PerfMonCtr1_Lo
+#define UMCCH6_0_PerfMonCtr1_Lo__Data__SHIFT 0x0
+#define UMCCH6_0_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_0_PerfMonCtr1_Hi
+#define UMCCH6_0_PerfMonCtr1_Hi__Data__SHIFT 0x0
+#define UMCCH6_0_PerfMonCtr1_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_0_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH6_0_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH6_0_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_0_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L
+#define UMCCH6_0_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH6_0_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH6_0_PerfMonCtl2
+#define UMCCH6_0_PerfMonCtl2__EventSelect__SHIFT 0x0
+#define UMCCH6_0_PerfMonCtl2__RdWrMask__SHIFT 0x8
+#define UMCCH6_0_PerfMonCtl2__PriorityMask__SHIFT 0xa
+#define UMCCH6_0_PerfMonCtl2__ReqSizeMask__SHIFT 0xe
+#define UMCCH6_0_PerfMonCtl2__BankSel__SHIFT 0x10
+#define UMCCH6_0_PerfMonCtl2__VCSel__SHIFT 0x18
+#define UMCCH6_0_PerfMonCtl2__SubChanMask__SHIFT 0x1d
+#define UMCCH6_0_PerfMonCtl2__Enable__SHIFT 0x1f
+#define UMCCH6_0_PerfMonCtl2__EventSelect_MASK 0x000000FFL
+#define UMCCH6_0_PerfMonCtl2__RdWrMask_MASK 0x00000300L
+#define UMCCH6_0_PerfMonCtl2__PriorityMask_MASK 0x00003C00L
+#define UMCCH6_0_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH6_0_PerfMonCtl2__BankSel_MASK 0x00FF0000L
+#define UMCCH6_0_PerfMonCtl2__VCSel_MASK 0x1F000000L
+#define UMCCH6_0_PerfMonCtl2__SubChanMask_MASK 0x60000000L
+#define UMCCH6_0_PerfMonCtl2__Enable_MASK 0x80000000L
+//UMCCH6_0_PerfMonCtr2_Lo
+#define UMCCH6_0_PerfMonCtr2_Lo__Data__SHIFT 0x0
+#define UMCCH6_0_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_0_PerfMonCtr2_Hi
+#define UMCCH6_0_PerfMonCtr2_Hi__Data__SHIFT 0x0
+#define UMCCH6_0_PerfMonCtr2_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_0_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH6_0_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH6_0_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_0_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L
+#define UMCCH6_0_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH6_0_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH6_0_PerfMonCtl3
+#define UMCCH6_0_PerfMonCtl3__EventSelect__SHIFT 0x0
+#define UMCCH6_0_PerfMonCtl3__RdWrMask__SHIFT 0x8
+#define UMCCH6_0_PerfMonCtl3__PriorityMask__SHIFT 0xa
+#define UMCCH6_0_PerfMonCtl3__ReqSizeMask__SHIFT 0xe
+#define UMCCH6_0_PerfMonCtl3__BankSel__SHIFT 0x10
+#define UMCCH6_0_PerfMonCtl3__VCSel__SHIFT 0x18
+#define UMCCH6_0_PerfMonCtl3__SubChanMask__SHIFT 0x1d
+#define UMCCH6_0_PerfMonCtl3__Enable__SHIFT 0x1f
+#define UMCCH6_0_PerfMonCtl3__EventSelect_MASK 0x000000FFL
+#define UMCCH6_0_PerfMonCtl3__RdWrMask_MASK 0x00000300L
+#define UMCCH6_0_PerfMonCtl3__PriorityMask_MASK 0x00003C00L
+#define UMCCH6_0_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH6_0_PerfMonCtl3__BankSel_MASK 0x00FF0000L
+#define UMCCH6_0_PerfMonCtl3__VCSel_MASK 0x1F000000L
+#define UMCCH6_0_PerfMonCtl3__SubChanMask_MASK 0x60000000L
+#define UMCCH6_0_PerfMonCtl3__Enable_MASK 0x80000000L
+//UMCCH6_0_PerfMonCtr3_Lo
+#define UMCCH6_0_PerfMonCtr3_Lo__Data__SHIFT 0x0
+#define UMCCH6_0_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_0_PerfMonCtr3_Hi
+#define UMCCH6_0_PerfMonCtr3_Hi__Data__SHIFT 0x0
+#define UMCCH6_0_PerfMonCtr3_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_0_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH6_0_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH6_0_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_0_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L
+#define UMCCH6_0_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH6_0_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH6_0_PerfMonCtl4
+#define UMCCH6_0_PerfMonCtl4__EventSelect__SHIFT 0x0
+#define UMCCH6_0_PerfMonCtl4__RdWrMask__SHIFT 0x8
+#define UMCCH6_0_PerfMonCtl4__PriorityMask__SHIFT 0xa
+#define UMCCH6_0_PerfMonCtl4__ReqSizeMask__SHIFT 0xe
+#define UMCCH6_0_PerfMonCtl4__BankSel__SHIFT 0x10
+#define UMCCH6_0_PerfMonCtl4__VCSel__SHIFT 0x18
+#define UMCCH6_0_PerfMonCtl4__SubChanMask__SHIFT 0x1d
+#define UMCCH6_0_PerfMonCtl4__Enable__SHIFT 0x1f
+#define UMCCH6_0_PerfMonCtl4__EventSelect_MASK 0x000000FFL
+#define UMCCH6_0_PerfMonCtl4__RdWrMask_MASK 0x00000300L
+#define UMCCH6_0_PerfMonCtl4__PriorityMask_MASK 0x00003C00L
+#define UMCCH6_0_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH6_0_PerfMonCtl4__BankSel_MASK 0x00FF0000L
+#define UMCCH6_0_PerfMonCtl4__VCSel_MASK 0x1F000000L
+#define UMCCH6_0_PerfMonCtl4__SubChanMask_MASK 0x60000000L
+#define UMCCH6_0_PerfMonCtl4__Enable_MASK 0x80000000L
+//UMCCH6_0_PerfMonCtr4_Lo
+#define UMCCH6_0_PerfMonCtr4_Lo__Data__SHIFT 0x0
+#define UMCCH6_0_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_0_PerfMonCtr4_Hi
+#define UMCCH6_0_PerfMonCtr4_Hi__Data__SHIFT 0x0
+#define UMCCH6_0_PerfMonCtr4_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_0_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH6_0_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH6_0_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_0_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L
+#define UMCCH6_0_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH6_0_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH6_0_PerfMonCtl5
+#define UMCCH6_0_PerfMonCtl5__EventSelect__SHIFT 0x0
+#define UMCCH6_0_PerfMonCtl5__RdWrMask__SHIFT 0x8
+#define UMCCH6_0_PerfMonCtl5__PriorityMask__SHIFT 0xa
+#define UMCCH6_0_PerfMonCtl5__ReqSizeMask__SHIFT 0xe
+#define UMCCH6_0_PerfMonCtl5__BankSel__SHIFT 0x10
+#define UMCCH6_0_PerfMonCtl5__VCSel__SHIFT 0x18
+#define UMCCH6_0_PerfMonCtl5__SubChanMask__SHIFT 0x1d
+#define UMCCH6_0_PerfMonCtl5__Enable__SHIFT 0x1f
+#define UMCCH6_0_PerfMonCtl5__EventSelect_MASK 0x000000FFL
+#define UMCCH6_0_PerfMonCtl5__RdWrMask_MASK 0x00000300L
+#define UMCCH6_0_PerfMonCtl5__PriorityMask_MASK 0x00003C00L
+#define UMCCH6_0_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH6_0_PerfMonCtl5__BankSel_MASK 0x00FF0000L
+#define UMCCH6_0_PerfMonCtl5__VCSel_MASK 0x1F000000L
+#define UMCCH6_0_PerfMonCtl5__SubChanMask_MASK 0x60000000L
+#define UMCCH6_0_PerfMonCtl5__Enable_MASK 0x80000000L
+//UMCCH6_0_PerfMonCtr5_Lo
+#define UMCCH6_0_PerfMonCtr5_Lo__Data__SHIFT 0x0
+#define UMCCH6_0_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_0_PerfMonCtr5_Hi
+#define UMCCH6_0_PerfMonCtr5_Hi__Data__SHIFT 0x0
+#define UMCCH6_0_PerfMonCtr5_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_0_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH6_0_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH6_0_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_0_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L
+#define UMCCH6_0_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH6_0_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH6_0_PerfMonCtl6
+#define UMCCH6_0_PerfMonCtl6__EventSelect__SHIFT 0x0
+#define UMCCH6_0_PerfMonCtl6__RdWrMask__SHIFT 0x8
+#define UMCCH6_0_PerfMonCtl6__PriorityMask__SHIFT 0xa
+#define UMCCH6_0_PerfMonCtl6__ReqSizeMask__SHIFT 0xe
+#define UMCCH6_0_PerfMonCtl6__BankSel__SHIFT 0x10
+#define UMCCH6_0_PerfMonCtl6__VCSel__SHIFT 0x18
+#define UMCCH6_0_PerfMonCtl6__SubChanMask__SHIFT 0x1d
+#define UMCCH6_0_PerfMonCtl6__Enable__SHIFT 0x1f
+#define UMCCH6_0_PerfMonCtl6__EventSelect_MASK 0x000000FFL
+#define UMCCH6_0_PerfMonCtl6__RdWrMask_MASK 0x00000300L
+#define UMCCH6_0_PerfMonCtl6__PriorityMask_MASK 0x00003C00L
+#define UMCCH6_0_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH6_0_PerfMonCtl6__BankSel_MASK 0x00FF0000L
+#define UMCCH6_0_PerfMonCtl6__VCSel_MASK 0x1F000000L
+#define UMCCH6_0_PerfMonCtl6__SubChanMask_MASK 0x60000000L
+#define UMCCH6_0_PerfMonCtl6__Enable_MASK 0x80000000L
+//UMCCH6_0_PerfMonCtr6_Lo
+#define UMCCH6_0_PerfMonCtr6_Lo__Data__SHIFT 0x0
+#define UMCCH6_0_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_0_PerfMonCtr6_Hi
+#define UMCCH6_0_PerfMonCtr6_Hi__Data__SHIFT 0x0
+#define UMCCH6_0_PerfMonCtr6_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_0_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH6_0_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH6_0_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_0_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L
+#define UMCCH6_0_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH6_0_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH6_0_PerfMonCtl7
+#define UMCCH6_0_PerfMonCtl7__EventSelect__SHIFT 0x0
+#define UMCCH6_0_PerfMonCtl7__RdWrMask__SHIFT 0x8
+#define UMCCH6_0_PerfMonCtl7__PriorityMask__SHIFT 0xa
+#define UMCCH6_0_PerfMonCtl7__ReqSizeMask__SHIFT 0xe
+#define UMCCH6_0_PerfMonCtl7__BankSel__SHIFT 0x10
+#define UMCCH6_0_PerfMonCtl7__VCSel__SHIFT 0x18
+#define UMCCH6_0_PerfMonCtl7__SubChanMask__SHIFT 0x1d
+#define UMCCH6_0_PerfMonCtl7__Enable__SHIFT 0x1f
+#define UMCCH6_0_PerfMonCtl7__EventSelect_MASK 0x000000FFL
+#define UMCCH6_0_PerfMonCtl7__RdWrMask_MASK 0x00000300L
+#define UMCCH6_0_PerfMonCtl7__PriorityMask_MASK 0x00003C00L
+#define UMCCH6_0_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH6_0_PerfMonCtl7__BankSel_MASK 0x00FF0000L
+#define UMCCH6_0_PerfMonCtl7__VCSel_MASK 0x1F000000L
+#define UMCCH6_0_PerfMonCtl7__SubChanMask_MASK 0x60000000L
+#define UMCCH6_0_PerfMonCtl7__Enable_MASK 0x80000000L
+//UMCCH6_0_PerfMonCtr7_Lo
+#define UMCCH6_0_PerfMonCtr7_Lo__Data__SHIFT 0x0
+#define UMCCH6_0_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_0_PerfMonCtr7_Hi
+#define UMCCH6_0_PerfMonCtr7_Hi__Data__SHIFT 0x0
+#define UMCCH6_0_PerfMonCtr7_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_0_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH6_0_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH6_0_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_0_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L
+#define UMCCH6_0_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH6_0_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH6_0_PerfMonCtl8
+#define UMCCH6_0_PerfMonCtl8__EventSelect__SHIFT 0x0
+#define UMCCH6_0_PerfMonCtl8__RdWrMask__SHIFT 0x8
+#define UMCCH6_0_PerfMonCtl8__PriorityMask__SHIFT 0xa
+#define UMCCH6_0_PerfMonCtl8__ReqSizeMask__SHIFT 0xe
+#define UMCCH6_0_PerfMonCtl8__BankSel__SHIFT 0x10
+#define UMCCH6_0_PerfMonCtl8__VCSel__SHIFT 0x18
+#define UMCCH6_0_PerfMonCtl8__SubChanMask__SHIFT 0x1d
+#define UMCCH6_0_PerfMonCtl8__Enable__SHIFT 0x1f
+#define UMCCH6_0_PerfMonCtl8__EventSelect_MASK 0x000000FFL
+#define UMCCH6_0_PerfMonCtl8__RdWrMask_MASK 0x00000300L
+#define UMCCH6_0_PerfMonCtl8__PriorityMask_MASK 0x00003C00L
+#define UMCCH6_0_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH6_0_PerfMonCtl8__BankSel_MASK 0x00FF0000L
+#define UMCCH6_0_PerfMonCtl8__VCSel_MASK 0x1F000000L
+#define UMCCH6_0_PerfMonCtl8__SubChanMask_MASK 0x60000000L
+#define UMCCH6_0_PerfMonCtl8__Enable_MASK 0x80000000L
+//UMCCH6_0_PerfMonCtr8_Lo
+#define UMCCH6_0_PerfMonCtr8_Lo__Data__SHIFT 0x0
+#define UMCCH6_0_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_0_PerfMonCtr8_Hi
+#define UMCCH6_0_PerfMonCtr8_Hi__Data__SHIFT 0x0
+#define UMCCH6_0_PerfMonCtr8_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_0_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH6_0_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH6_0_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_0_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L
+#define UMCCH6_0_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH6_0_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L
+
+
+// addressBlock: umc_w_phy_umc0_umcch7_umcchdec
+//UMCCH7_0_BaseAddrCS0
+#define UMCCH7_0_BaseAddrCS0__CSEnable__SHIFT 0x0
+#define UMCCH7_0_BaseAddrCS0__BaseAddr__SHIFT 0x1
+#define UMCCH7_0_BaseAddrCS0__CSEnable_MASK 0x00000001L
+#define UMCCH7_0_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL
+//UMCCH7_0_AddrMaskCS01
+#define UMCCH7_0_AddrMaskCS01__AddrMask__SHIFT 0x1
+#define UMCCH7_0_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL
+//UMCCH7_0_AddrSelCS01
+#define UMCCH7_0_AddrSelCS01__BankBit0__SHIFT 0x0
+#define UMCCH7_0_AddrSelCS01__BankBit1__SHIFT 0x4
+#define UMCCH7_0_AddrSelCS01__BankBit2__SHIFT 0x8
+#define UMCCH7_0_AddrSelCS01__BankBit3__SHIFT 0xc
+#define UMCCH7_0_AddrSelCS01__BankBit4__SHIFT 0x10
+#define UMCCH7_0_AddrSelCS01__RowLo__SHIFT 0x18
+#define UMCCH7_0_AddrSelCS01__RowHi__SHIFT 0x1c
+#define UMCCH7_0_AddrSelCS01__BankBit0_MASK 0x0000000FL
+#define UMCCH7_0_AddrSelCS01__BankBit1_MASK 0x000000F0L
+#define UMCCH7_0_AddrSelCS01__BankBit2_MASK 0x00000F00L
+#define UMCCH7_0_AddrSelCS01__BankBit3_MASK 0x0000F000L
+#define UMCCH7_0_AddrSelCS01__BankBit4_MASK 0x001F0000L
+#define UMCCH7_0_AddrSelCS01__RowLo_MASK 0x0F000000L
+#define UMCCH7_0_AddrSelCS01__RowHi_MASK 0xF0000000L
+//UMCCH7_0_AddrHashBank0
+#define UMCCH7_0_AddrHashBank0__XorEnable__SHIFT 0x0
+#define UMCCH7_0_AddrHashBank0__ColXor__SHIFT 0x1
+#define UMCCH7_0_AddrHashBank0__RowXor__SHIFT 0xe
+#define UMCCH7_0_AddrHashBank0__XorEnable_MASK 0x00000001L
+#define UMCCH7_0_AddrHashBank0__ColXor_MASK 0x00003FFEL
+#define UMCCH7_0_AddrHashBank0__RowXor_MASK 0xFFFFC000L
+//UMCCH7_0_AddrHashBank1
+#define UMCCH7_0_AddrHashBank1__XorEnable__SHIFT 0x0
+#define UMCCH7_0_AddrHashBank1__ColXor__SHIFT 0x1
+#define UMCCH7_0_AddrHashBank1__RowXor__SHIFT 0xe
+#define UMCCH7_0_AddrHashBank1__XorEnable_MASK 0x00000001L
+#define UMCCH7_0_AddrHashBank1__ColXor_MASK 0x00003FFEL
+#define UMCCH7_0_AddrHashBank1__RowXor_MASK 0xFFFFC000L
+//UMCCH7_0_AddrHashBank2
+#define UMCCH7_0_AddrHashBank2__XorEnable__SHIFT 0x0
+#define UMCCH7_0_AddrHashBank2__ColXor__SHIFT 0x1
+#define UMCCH7_0_AddrHashBank2__RowXor__SHIFT 0xe
+#define UMCCH7_0_AddrHashBank2__XorEnable_MASK 0x00000001L
+#define UMCCH7_0_AddrHashBank2__ColXor_MASK 0x00003FFEL
+#define UMCCH7_0_AddrHashBank2__RowXor_MASK 0xFFFFC000L
+//UMCCH7_0_AddrHashBank3
+#define UMCCH7_0_AddrHashBank3__XorEnable__SHIFT 0x0
+#define UMCCH7_0_AddrHashBank3__ColXor__SHIFT 0x1
+#define UMCCH7_0_AddrHashBank3__RowXor__SHIFT 0xe
+#define UMCCH7_0_AddrHashBank3__XorEnable_MASK 0x00000001L
+#define UMCCH7_0_AddrHashBank3__ColXor_MASK 0x00003FFEL
+#define UMCCH7_0_AddrHashBank3__RowXor_MASK 0xFFFFC000L
+//UMCCH7_0_AddrHashBank4
+#define UMCCH7_0_AddrHashBank4__XorEnable__SHIFT 0x0
+#define UMCCH7_0_AddrHashBank4__ColXor__SHIFT 0x1
+#define UMCCH7_0_AddrHashBank4__RowXor__SHIFT 0xe
+#define UMCCH7_0_AddrHashBank4__XorEnable_MASK 0x00000001L
+#define UMCCH7_0_AddrHashBank4__ColXor_MASK 0x00003FFEL
+#define UMCCH7_0_AddrHashBank4__RowXor_MASK 0xFFFFC000L
+//UMCCH7_0_AddrHashBank5
+#define UMCCH7_0_AddrHashBank5__XorEnable__SHIFT 0x0
+#define UMCCH7_0_AddrHashBank5__ColXor__SHIFT 0x1
+#define UMCCH7_0_AddrHashBank5__RowXor__SHIFT 0xe
+#define UMCCH7_0_AddrHashBank5__XorEnable_MASK 0x00000001L
+#define UMCCH7_0_AddrHashBank5__ColXor_MASK 0x00003FFEL
+#define UMCCH7_0_AddrHashBank5__RowXor_MASK 0xFFFFC000L
+//UMCCH7_0_EccErrCntSel
+#define UMCCH7_0_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0
+#define UMCCH7_0_EccErrCntSel__EccErrInt__SHIFT 0xc
+#define UMCCH7_0_EccErrCntSel__EccErrCntEn__SHIFT 0xf
+#define UMCCH7_0_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL
+#define UMCCH7_0_EccErrCntSel__EccErrInt_MASK 0x00003000L
+#define UMCCH7_0_EccErrCntSel__EccErrCntEn_MASK 0x00008000L
+//UMCCH7_0_EccErrCnt
+#define UMCCH7_0_EccErrCnt__EccErrCnt__SHIFT 0x0
+#define UMCCH7_0_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL
+//UMCCH7_0_PerfMonCtlClk
+#define UMCCH7_0_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0
+#define UMCCH7_0_PerfMonCtlClk__ClkGate__SHIFT 0x16
+#define UMCCH7_0_PerfMonCtlClk__GlblReset__SHIFT 0x18
+#define UMCCH7_0_PerfMonCtlClk__GlblMonEn__SHIFT 0x19
+#define UMCCH7_0_PerfMonCtlClk__NumCounters__SHIFT 0x1a
+#define UMCCH7_0_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f
+#define UMCCH7_0_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL
+#define UMCCH7_0_PerfMonCtlClk__ClkGate_MASK 0x00400000L
+#define UMCCH7_0_PerfMonCtlClk__GlblReset_MASK 0x01000000L
+#define UMCCH7_0_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L
+#define UMCCH7_0_PerfMonCtlClk__NumCounters_MASK 0x3C000000L
+#define UMCCH7_0_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L
+//UMCCH7_0_PerfMonCtrClk_Lo
+#define UMCCH7_0_PerfMonCtrClk_Lo__Data__SHIFT 0x0
+#define UMCCH7_0_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_0_PerfMonCtrClk_Hi
+#define UMCCH7_0_PerfMonCtrClk_Hi__Data__SHIFT 0x0
+#define UMCCH7_0_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_0_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_0_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L
+//UMCCH7_0_PerfMonCtl1
+#define UMCCH7_0_PerfMonCtl1__EventSelect__SHIFT 0x0
+#define UMCCH7_0_PerfMonCtl1__RdWrMask__SHIFT 0x8
+#define UMCCH7_0_PerfMonCtl1__PriorityMask__SHIFT 0xa
+#define UMCCH7_0_PerfMonCtl1__ReqSizeMask__SHIFT 0xe
+#define UMCCH7_0_PerfMonCtl1__BankSel__SHIFT 0x10
+#define UMCCH7_0_PerfMonCtl1__VCSel__SHIFT 0x18
+#define UMCCH7_0_PerfMonCtl1__SubChanMask__SHIFT 0x1d
+#define UMCCH7_0_PerfMonCtl1__Enable__SHIFT 0x1f
+#define UMCCH7_0_PerfMonCtl1__EventSelect_MASK 0x000000FFL
+#define UMCCH7_0_PerfMonCtl1__RdWrMask_MASK 0x00000300L
+#define UMCCH7_0_PerfMonCtl1__PriorityMask_MASK 0x00003C00L
+#define UMCCH7_0_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH7_0_PerfMonCtl1__BankSel_MASK 0x00FF0000L
+#define UMCCH7_0_PerfMonCtl1__VCSel_MASK 0x1F000000L
+#define UMCCH7_0_PerfMonCtl1__SubChanMask_MASK 0x60000000L
+#define UMCCH7_0_PerfMonCtl1__Enable_MASK 0x80000000L
+//UMCCH7_0_PerfMonCtr1_Lo
+#define UMCCH7_0_PerfMonCtr1_Lo__Data__SHIFT 0x0
+#define UMCCH7_0_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_0_PerfMonCtr1_Hi
+#define UMCCH7_0_PerfMonCtr1_Hi__Data__SHIFT 0x0
+#define UMCCH7_0_PerfMonCtr1_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_0_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH7_0_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH7_0_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_0_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L
+#define UMCCH7_0_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH7_0_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH7_0_PerfMonCtl2
+#define UMCCH7_0_PerfMonCtl2__EventSelect__SHIFT 0x0
+#define UMCCH7_0_PerfMonCtl2__RdWrMask__SHIFT 0x8
+#define UMCCH7_0_PerfMonCtl2__PriorityMask__SHIFT 0xa
+#define UMCCH7_0_PerfMonCtl2__ReqSizeMask__SHIFT 0xe
+#define UMCCH7_0_PerfMonCtl2__BankSel__SHIFT 0x10
+#define UMCCH7_0_PerfMonCtl2__VCSel__SHIFT 0x18
+#define UMCCH7_0_PerfMonCtl2__SubChanMask__SHIFT 0x1d
+#define UMCCH7_0_PerfMonCtl2__Enable__SHIFT 0x1f
+#define UMCCH7_0_PerfMonCtl2__EventSelect_MASK 0x000000FFL
+#define UMCCH7_0_PerfMonCtl2__RdWrMask_MASK 0x00000300L
+#define UMCCH7_0_PerfMonCtl2__PriorityMask_MASK 0x00003C00L
+#define UMCCH7_0_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH7_0_PerfMonCtl2__BankSel_MASK 0x00FF0000L
+#define UMCCH7_0_PerfMonCtl2__VCSel_MASK 0x1F000000L
+#define UMCCH7_0_PerfMonCtl2__SubChanMask_MASK 0x60000000L
+#define UMCCH7_0_PerfMonCtl2__Enable_MASK 0x80000000L
+//UMCCH7_0_PerfMonCtr2_Lo
+#define UMCCH7_0_PerfMonCtr2_Lo__Data__SHIFT 0x0
+#define UMCCH7_0_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_0_PerfMonCtr2_Hi
+#define UMCCH7_0_PerfMonCtr2_Hi__Data__SHIFT 0x0
+#define UMCCH7_0_PerfMonCtr2_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_0_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH7_0_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH7_0_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_0_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L
+#define UMCCH7_0_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH7_0_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH7_0_PerfMonCtl3
+#define UMCCH7_0_PerfMonCtl3__EventSelect__SHIFT 0x0
+#define UMCCH7_0_PerfMonCtl3__RdWrMask__SHIFT 0x8
+#define UMCCH7_0_PerfMonCtl3__PriorityMask__SHIFT 0xa
+#define UMCCH7_0_PerfMonCtl3__ReqSizeMask__SHIFT 0xe
+#define UMCCH7_0_PerfMonCtl3__BankSel__SHIFT 0x10
+#define UMCCH7_0_PerfMonCtl3__VCSel__SHIFT 0x18
+#define UMCCH7_0_PerfMonCtl3__SubChanMask__SHIFT 0x1d
+#define UMCCH7_0_PerfMonCtl3__Enable__SHIFT 0x1f
+#define UMCCH7_0_PerfMonCtl3__EventSelect_MASK 0x000000FFL
+#define UMCCH7_0_PerfMonCtl3__RdWrMask_MASK 0x00000300L
+#define UMCCH7_0_PerfMonCtl3__PriorityMask_MASK 0x00003C00L
+#define UMCCH7_0_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH7_0_PerfMonCtl3__BankSel_MASK 0x00FF0000L
+#define UMCCH7_0_PerfMonCtl3__VCSel_MASK 0x1F000000L
+#define UMCCH7_0_PerfMonCtl3__SubChanMask_MASK 0x60000000L
+#define UMCCH7_0_PerfMonCtl3__Enable_MASK 0x80000000L
+//UMCCH7_0_PerfMonCtr3_Lo
+#define UMCCH7_0_PerfMonCtr3_Lo__Data__SHIFT 0x0
+#define UMCCH7_0_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_0_PerfMonCtr3_Hi
+#define UMCCH7_0_PerfMonCtr3_Hi__Data__SHIFT 0x0
+#define UMCCH7_0_PerfMonCtr3_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_0_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH7_0_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH7_0_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_0_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L
+#define UMCCH7_0_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH7_0_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH7_0_PerfMonCtl4
+#define UMCCH7_0_PerfMonCtl4__EventSelect__SHIFT 0x0
+#define UMCCH7_0_PerfMonCtl4__RdWrMask__SHIFT 0x8
+#define UMCCH7_0_PerfMonCtl4__PriorityMask__SHIFT 0xa
+#define UMCCH7_0_PerfMonCtl4__ReqSizeMask__SHIFT 0xe
+#define UMCCH7_0_PerfMonCtl4__BankSel__SHIFT 0x10
+#define UMCCH7_0_PerfMonCtl4__VCSel__SHIFT 0x18
+#define UMCCH7_0_PerfMonCtl4__SubChanMask__SHIFT 0x1d
+#define UMCCH7_0_PerfMonCtl4__Enable__SHIFT 0x1f
+#define UMCCH7_0_PerfMonCtl4__EventSelect_MASK 0x000000FFL
+#define UMCCH7_0_PerfMonCtl4__RdWrMask_MASK 0x00000300L
+#define UMCCH7_0_PerfMonCtl4__PriorityMask_MASK 0x00003C00L
+#define UMCCH7_0_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH7_0_PerfMonCtl4__BankSel_MASK 0x00FF0000L
+#define UMCCH7_0_PerfMonCtl4__VCSel_MASK 0x1F000000L
+#define UMCCH7_0_PerfMonCtl4__SubChanMask_MASK 0x60000000L
+#define UMCCH7_0_PerfMonCtl4__Enable_MASK 0x80000000L
+//UMCCH7_0_PerfMonCtr4_Lo
+#define UMCCH7_0_PerfMonCtr4_Lo__Data__SHIFT 0x0
+#define UMCCH7_0_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_0_PerfMonCtr4_Hi
+#define UMCCH7_0_PerfMonCtr4_Hi__Data__SHIFT 0x0
+#define UMCCH7_0_PerfMonCtr4_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_0_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH7_0_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH7_0_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_0_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L
+#define UMCCH7_0_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH7_0_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH7_0_PerfMonCtl5
+#define UMCCH7_0_PerfMonCtl5__EventSelect__SHIFT 0x0
+#define UMCCH7_0_PerfMonCtl5__RdWrMask__SHIFT 0x8
+#define UMCCH7_0_PerfMonCtl5__PriorityMask__SHIFT 0xa
+#define UMCCH7_0_PerfMonCtl5__ReqSizeMask__SHIFT 0xe
+#define UMCCH7_0_PerfMonCtl5__BankSel__SHIFT 0x10
+#define UMCCH7_0_PerfMonCtl5__VCSel__SHIFT 0x18
+#define UMCCH7_0_PerfMonCtl5__SubChanMask__SHIFT 0x1d
+#define UMCCH7_0_PerfMonCtl5__Enable__SHIFT 0x1f
+#define UMCCH7_0_PerfMonCtl5__EventSelect_MASK 0x000000FFL
+#define UMCCH7_0_PerfMonCtl5__RdWrMask_MASK 0x00000300L
+#define UMCCH7_0_PerfMonCtl5__PriorityMask_MASK 0x00003C00L
+#define UMCCH7_0_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH7_0_PerfMonCtl5__BankSel_MASK 0x00FF0000L
+#define UMCCH7_0_PerfMonCtl5__VCSel_MASK 0x1F000000L
+#define UMCCH7_0_PerfMonCtl5__SubChanMask_MASK 0x60000000L
+#define UMCCH7_0_PerfMonCtl5__Enable_MASK 0x80000000L
+//UMCCH7_0_PerfMonCtr5_Lo
+#define UMCCH7_0_PerfMonCtr5_Lo__Data__SHIFT 0x0
+#define UMCCH7_0_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_0_PerfMonCtr5_Hi
+#define UMCCH7_0_PerfMonCtr5_Hi__Data__SHIFT 0x0
+#define UMCCH7_0_PerfMonCtr5_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_0_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH7_0_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH7_0_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_0_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L
+#define UMCCH7_0_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH7_0_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH7_0_PerfMonCtl6
+#define UMCCH7_0_PerfMonCtl6__EventSelect__SHIFT 0x0
+#define UMCCH7_0_PerfMonCtl6__RdWrMask__SHIFT 0x8
+#define UMCCH7_0_PerfMonCtl6__PriorityMask__SHIFT 0xa
+#define UMCCH7_0_PerfMonCtl6__ReqSizeMask__SHIFT 0xe
+#define UMCCH7_0_PerfMonCtl6__BankSel__SHIFT 0x10
+#define UMCCH7_0_PerfMonCtl6__VCSel__SHIFT 0x18
+#define UMCCH7_0_PerfMonCtl6__SubChanMask__SHIFT 0x1d
+#define UMCCH7_0_PerfMonCtl6__Enable__SHIFT 0x1f
+#define UMCCH7_0_PerfMonCtl6__EventSelect_MASK 0x000000FFL
+#define UMCCH7_0_PerfMonCtl6__RdWrMask_MASK 0x00000300L
+#define UMCCH7_0_PerfMonCtl6__PriorityMask_MASK 0x00003C00L
+#define UMCCH7_0_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH7_0_PerfMonCtl6__BankSel_MASK 0x00FF0000L
+#define UMCCH7_0_PerfMonCtl6__VCSel_MASK 0x1F000000L
+#define UMCCH7_0_PerfMonCtl6__SubChanMask_MASK 0x60000000L
+#define UMCCH7_0_PerfMonCtl6__Enable_MASK 0x80000000L
+//UMCCH7_0_PerfMonCtr6_Lo
+#define UMCCH7_0_PerfMonCtr6_Lo__Data__SHIFT 0x0
+#define UMCCH7_0_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_0_PerfMonCtr6_Hi
+#define UMCCH7_0_PerfMonCtr6_Hi__Data__SHIFT 0x0
+#define UMCCH7_0_PerfMonCtr6_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_0_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH7_0_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH7_0_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_0_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L
+#define UMCCH7_0_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH7_0_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH7_0_PerfMonCtl7
+#define UMCCH7_0_PerfMonCtl7__EventSelect__SHIFT 0x0
+#define UMCCH7_0_PerfMonCtl7__RdWrMask__SHIFT 0x8
+#define UMCCH7_0_PerfMonCtl7__PriorityMask__SHIFT 0xa
+#define UMCCH7_0_PerfMonCtl7__ReqSizeMask__SHIFT 0xe
+#define UMCCH7_0_PerfMonCtl7__BankSel__SHIFT 0x10
+#define UMCCH7_0_PerfMonCtl7__VCSel__SHIFT 0x18
+#define UMCCH7_0_PerfMonCtl7__SubChanMask__SHIFT 0x1d
+#define UMCCH7_0_PerfMonCtl7__Enable__SHIFT 0x1f
+#define UMCCH7_0_PerfMonCtl7__EventSelect_MASK 0x000000FFL
+#define UMCCH7_0_PerfMonCtl7__RdWrMask_MASK 0x00000300L
+#define UMCCH7_0_PerfMonCtl7__PriorityMask_MASK 0x00003C00L
+#define UMCCH7_0_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH7_0_PerfMonCtl7__BankSel_MASK 0x00FF0000L
+#define UMCCH7_0_PerfMonCtl7__VCSel_MASK 0x1F000000L
+#define UMCCH7_0_PerfMonCtl7__SubChanMask_MASK 0x60000000L
+#define UMCCH7_0_PerfMonCtl7__Enable_MASK 0x80000000L
+//UMCCH7_0_PerfMonCtr7_Lo
+#define UMCCH7_0_PerfMonCtr7_Lo__Data__SHIFT 0x0
+#define UMCCH7_0_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_0_PerfMonCtr7_Hi
+#define UMCCH7_0_PerfMonCtr7_Hi__Data__SHIFT 0x0
+#define UMCCH7_0_PerfMonCtr7_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_0_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH7_0_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH7_0_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_0_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L
+#define UMCCH7_0_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH7_0_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH7_0_PerfMonCtl8
+#define UMCCH7_0_PerfMonCtl8__EventSelect__SHIFT 0x0
+#define UMCCH7_0_PerfMonCtl8__RdWrMask__SHIFT 0x8
+#define UMCCH7_0_PerfMonCtl8__PriorityMask__SHIFT 0xa
+#define UMCCH7_0_PerfMonCtl8__ReqSizeMask__SHIFT 0xe
+#define UMCCH7_0_PerfMonCtl8__BankSel__SHIFT 0x10
+#define UMCCH7_0_PerfMonCtl8__VCSel__SHIFT 0x18
+#define UMCCH7_0_PerfMonCtl8__SubChanMask__SHIFT 0x1d
+#define UMCCH7_0_PerfMonCtl8__Enable__SHIFT 0x1f
+#define UMCCH7_0_PerfMonCtl8__EventSelect_MASK 0x000000FFL
+#define UMCCH7_0_PerfMonCtl8__RdWrMask_MASK 0x00000300L
+#define UMCCH7_0_PerfMonCtl8__PriorityMask_MASK 0x00003C00L
+#define UMCCH7_0_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH7_0_PerfMonCtl8__BankSel_MASK 0x00FF0000L
+#define UMCCH7_0_PerfMonCtl8__VCSel_MASK 0x1F000000L
+#define UMCCH7_0_PerfMonCtl8__SubChanMask_MASK 0x60000000L
+#define UMCCH7_0_PerfMonCtl8__Enable_MASK 0x80000000L
+//UMCCH7_0_PerfMonCtr8_Lo
+#define UMCCH7_0_PerfMonCtr8_Lo__Data__SHIFT 0x0
+#define UMCCH7_0_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_0_PerfMonCtr8_Hi
+#define UMCCH7_0_PerfMonCtr8_Hi__Data__SHIFT 0x0
+#define UMCCH7_0_PerfMonCtr8_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_0_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH7_0_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH7_0_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_0_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L
+#define UMCCH7_0_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH7_0_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L
+
+
+// addressBlock: umc_w_phy_umc1_umcch0_umcchdec
+//UMCCH0_1_BaseAddrCS0
+#define UMCCH0_1_BaseAddrCS0__CSEnable__SHIFT 0x0
+#define UMCCH0_1_BaseAddrCS0__BaseAddr__SHIFT 0x1
+#define UMCCH0_1_BaseAddrCS0__CSEnable_MASK 0x00000001L
+#define UMCCH0_1_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL
+//UMCCH0_1_AddrMaskCS01
+#define UMCCH0_1_AddrMaskCS01__AddrMask__SHIFT 0x1
+#define UMCCH0_1_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL
+//UMCCH0_1_AddrSelCS01
+#define UMCCH0_1_AddrSelCS01__BankBit0__SHIFT 0x0
+#define UMCCH0_1_AddrSelCS01__BankBit1__SHIFT 0x4
+#define UMCCH0_1_AddrSelCS01__BankBit2__SHIFT 0x8
+#define UMCCH0_1_AddrSelCS01__BankBit3__SHIFT 0xc
+#define UMCCH0_1_AddrSelCS01__BankBit4__SHIFT 0x10
+#define UMCCH0_1_AddrSelCS01__RowLo__SHIFT 0x18
+#define UMCCH0_1_AddrSelCS01__RowHi__SHIFT 0x1c
+#define UMCCH0_1_AddrSelCS01__BankBit0_MASK 0x0000000FL
+#define UMCCH0_1_AddrSelCS01__BankBit1_MASK 0x000000F0L
+#define UMCCH0_1_AddrSelCS01__BankBit2_MASK 0x00000F00L
+#define UMCCH0_1_AddrSelCS01__BankBit3_MASK 0x0000F000L
+#define UMCCH0_1_AddrSelCS01__BankBit4_MASK 0x001F0000L
+#define UMCCH0_1_AddrSelCS01__RowLo_MASK 0x0F000000L
+#define UMCCH0_1_AddrSelCS01__RowHi_MASK 0xF0000000L
+//UMCCH0_1_AddrHashBank0
+#define UMCCH0_1_AddrHashBank0__XorEnable__SHIFT 0x0
+#define UMCCH0_1_AddrHashBank0__ColXor__SHIFT 0x1
+#define UMCCH0_1_AddrHashBank0__RowXor__SHIFT 0xe
+#define UMCCH0_1_AddrHashBank0__XorEnable_MASK 0x00000001L
+#define UMCCH0_1_AddrHashBank0__ColXor_MASK 0x00003FFEL
+#define UMCCH0_1_AddrHashBank0__RowXor_MASK 0xFFFFC000L
+//UMCCH0_1_AddrHashBank1
+#define UMCCH0_1_AddrHashBank1__XorEnable__SHIFT 0x0
+#define UMCCH0_1_AddrHashBank1__ColXor__SHIFT 0x1
+#define UMCCH0_1_AddrHashBank1__RowXor__SHIFT 0xe
+#define UMCCH0_1_AddrHashBank1__XorEnable_MASK 0x00000001L
+#define UMCCH0_1_AddrHashBank1__ColXor_MASK 0x00003FFEL
+#define UMCCH0_1_AddrHashBank1__RowXor_MASK 0xFFFFC000L
+//UMCCH0_1_AddrHashBank2
+#define UMCCH0_1_AddrHashBank2__XorEnable__SHIFT 0x0
+#define UMCCH0_1_AddrHashBank2__ColXor__SHIFT 0x1
+#define UMCCH0_1_AddrHashBank2__RowXor__SHIFT 0xe
+#define UMCCH0_1_AddrHashBank2__XorEnable_MASK 0x00000001L
+#define UMCCH0_1_AddrHashBank2__ColXor_MASK 0x00003FFEL
+#define UMCCH0_1_AddrHashBank2__RowXor_MASK 0xFFFFC000L
+//UMCCH0_1_AddrHashBank3
+#define UMCCH0_1_AddrHashBank3__XorEnable__SHIFT 0x0
+#define UMCCH0_1_AddrHashBank3__ColXor__SHIFT 0x1
+#define UMCCH0_1_AddrHashBank3__RowXor__SHIFT 0xe
+#define UMCCH0_1_AddrHashBank3__XorEnable_MASK 0x00000001L
+#define UMCCH0_1_AddrHashBank3__ColXor_MASK 0x00003FFEL
+#define UMCCH0_1_AddrHashBank3__RowXor_MASK 0xFFFFC000L
+//UMCCH0_1_AddrHashBank4
+#define UMCCH0_1_AddrHashBank4__XorEnable__SHIFT 0x0
+#define UMCCH0_1_AddrHashBank4__ColXor__SHIFT 0x1
+#define UMCCH0_1_AddrHashBank4__RowXor__SHIFT 0xe
+#define UMCCH0_1_AddrHashBank4__XorEnable_MASK 0x00000001L
+#define UMCCH0_1_AddrHashBank4__ColXor_MASK 0x00003FFEL
+#define UMCCH0_1_AddrHashBank4__RowXor_MASK 0xFFFFC000L
+//UMCCH0_1_AddrHashBank5
+#define UMCCH0_1_AddrHashBank5__XorEnable__SHIFT 0x0
+#define UMCCH0_1_AddrHashBank5__ColXor__SHIFT 0x1
+#define UMCCH0_1_AddrHashBank5__RowXor__SHIFT 0xe
+#define UMCCH0_1_AddrHashBank5__XorEnable_MASK 0x00000001L
+#define UMCCH0_1_AddrHashBank5__ColXor_MASK 0x00003FFEL
+#define UMCCH0_1_AddrHashBank5__RowXor_MASK 0xFFFFC000L
+//UMCCH0_1_EccErrCntSel
+#define UMCCH0_1_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0
+#define UMCCH0_1_EccErrCntSel__EccErrInt__SHIFT 0xc
+#define UMCCH0_1_EccErrCntSel__EccErrCntEn__SHIFT 0xf
+#define UMCCH0_1_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL
+#define UMCCH0_1_EccErrCntSel__EccErrInt_MASK 0x00003000L
+#define UMCCH0_1_EccErrCntSel__EccErrCntEn_MASK 0x00008000L
+//UMCCH0_1_EccErrCnt
+#define UMCCH0_1_EccErrCnt__EccErrCnt__SHIFT 0x0
+#define UMCCH0_1_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL
+//UMCCH0_1_PerfMonCtlClk
+#define UMCCH0_1_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0
+#define UMCCH0_1_PerfMonCtlClk__ClkGate__SHIFT 0x16
+#define UMCCH0_1_PerfMonCtlClk__GlblReset__SHIFT 0x18
+#define UMCCH0_1_PerfMonCtlClk__GlblMonEn__SHIFT 0x19
+#define UMCCH0_1_PerfMonCtlClk__NumCounters__SHIFT 0x1a
+#define UMCCH0_1_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f
+#define UMCCH0_1_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL
+#define UMCCH0_1_PerfMonCtlClk__ClkGate_MASK 0x00400000L
+#define UMCCH0_1_PerfMonCtlClk__GlblReset_MASK 0x01000000L
+#define UMCCH0_1_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L
+#define UMCCH0_1_PerfMonCtlClk__NumCounters_MASK 0x3C000000L
+#define UMCCH0_1_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L
+//UMCCH0_1_PerfMonCtrClk_Lo
+#define UMCCH0_1_PerfMonCtrClk_Lo__Data__SHIFT 0x0
+#define UMCCH0_1_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_1_PerfMonCtrClk_Hi
+#define UMCCH0_1_PerfMonCtrClk_Hi__Data__SHIFT 0x0
+#define UMCCH0_1_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_1_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_1_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L
+//UMCCH0_1_PerfMonCtl1
+#define UMCCH0_1_PerfMonCtl1__EventSelect__SHIFT 0x0
+#define UMCCH0_1_PerfMonCtl1__RdWrMask__SHIFT 0x8
+#define UMCCH0_1_PerfMonCtl1__PriorityMask__SHIFT 0xa
+#define UMCCH0_1_PerfMonCtl1__ReqSizeMask__SHIFT 0xe
+#define UMCCH0_1_PerfMonCtl1__BankSel__SHIFT 0x10
+#define UMCCH0_1_PerfMonCtl1__VCSel__SHIFT 0x18
+#define UMCCH0_1_PerfMonCtl1__SubChanMask__SHIFT 0x1d
+#define UMCCH0_1_PerfMonCtl1__Enable__SHIFT 0x1f
+#define UMCCH0_1_PerfMonCtl1__EventSelect_MASK 0x000000FFL
+#define UMCCH0_1_PerfMonCtl1__RdWrMask_MASK 0x00000300L
+#define UMCCH0_1_PerfMonCtl1__PriorityMask_MASK 0x00003C00L
+#define UMCCH0_1_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH0_1_PerfMonCtl1__BankSel_MASK 0x00FF0000L
+#define UMCCH0_1_PerfMonCtl1__VCSel_MASK 0x1F000000L
+#define UMCCH0_1_PerfMonCtl1__SubChanMask_MASK 0x60000000L
+#define UMCCH0_1_PerfMonCtl1__Enable_MASK 0x80000000L
+//UMCCH0_1_PerfMonCtr1_Lo
+#define UMCCH0_1_PerfMonCtr1_Lo__Data__SHIFT 0x0
+#define UMCCH0_1_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_1_PerfMonCtr1_Hi
+#define UMCCH0_1_PerfMonCtr1_Hi__Data__SHIFT 0x0
+#define UMCCH0_1_PerfMonCtr1_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_1_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH0_1_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH0_1_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_1_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L
+#define UMCCH0_1_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH0_1_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH0_1_PerfMonCtl2
+#define UMCCH0_1_PerfMonCtl2__EventSelect__SHIFT 0x0
+#define UMCCH0_1_PerfMonCtl2__RdWrMask__SHIFT 0x8
+#define UMCCH0_1_PerfMonCtl2__PriorityMask__SHIFT 0xa
+#define UMCCH0_1_PerfMonCtl2__ReqSizeMask__SHIFT 0xe
+#define UMCCH0_1_PerfMonCtl2__BankSel__SHIFT 0x10
+#define UMCCH0_1_PerfMonCtl2__VCSel__SHIFT 0x18
+#define UMCCH0_1_PerfMonCtl2__SubChanMask__SHIFT 0x1d
+#define UMCCH0_1_PerfMonCtl2__Enable__SHIFT 0x1f
+#define UMCCH0_1_PerfMonCtl2__EventSelect_MASK 0x000000FFL
+#define UMCCH0_1_PerfMonCtl2__RdWrMask_MASK 0x00000300L
+#define UMCCH0_1_PerfMonCtl2__PriorityMask_MASK 0x00003C00L
+#define UMCCH0_1_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH0_1_PerfMonCtl2__BankSel_MASK 0x00FF0000L
+#define UMCCH0_1_PerfMonCtl2__VCSel_MASK 0x1F000000L
+#define UMCCH0_1_PerfMonCtl2__SubChanMask_MASK 0x60000000L
+#define UMCCH0_1_PerfMonCtl2__Enable_MASK 0x80000000L
+//UMCCH0_1_PerfMonCtr2_Lo
+#define UMCCH0_1_PerfMonCtr2_Lo__Data__SHIFT 0x0
+#define UMCCH0_1_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_1_PerfMonCtr2_Hi
+#define UMCCH0_1_PerfMonCtr2_Hi__Data__SHIFT 0x0
+#define UMCCH0_1_PerfMonCtr2_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_1_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH0_1_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH0_1_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_1_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L
+#define UMCCH0_1_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH0_1_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH0_1_PerfMonCtl3
+#define UMCCH0_1_PerfMonCtl3__EventSelect__SHIFT 0x0
+#define UMCCH0_1_PerfMonCtl3__RdWrMask__SHIFT 0x8
+#define UMCCH0_1_PerfMonCtl3__PriorityMask__SHIFT 0xa
+#define UMCCH0_1_PerfMonCtl3__ReqSizeMask__SHIFT 0xe
+#define UMCCH0_1_PerfMonCtl3__BankSel__SHIFT 0x10
+#define UMCCH0_1_PerfMonCtl3__VCSel__SHIFT 0x18
+#define UMCCH0_1_PerfMonCtl3__SubChanMask__SHIFT 0x1d
+#define UMCCH0_1_PerfMonCtl3__Enable__SHIFT 0x1f
+#define UMCCH0_1_PerfMonCtl3__EventSelect_MASK 0x000000FFL
+#define UMCCH0_1_PerfMonCtl3__RdWrMask_MASK 0x00000300L
+#define UMCCH0_1_PerfMonCtl3__PriorityMask_MASK 0x00003C00L
+#define UMCCH0_1_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH0_1_PerfMonCtl3__BankSel_MASK 0x00FF0000L
+#define UMCCH0_1_PerfMonCtl3__VCSel_MASK 0x1F000000L
+#define UMCCH0_1_PerfMonCtl3__SubChanMask_MASK 0x60000000L
+#define UMCCH0_1_PerfMonCtl3__Enable_MASK 0x80000000L
+//UMCCH0_1_PerfMonCtr3_Lo
+#define UMCCH0_1_PerfMonCtr3_Lo__Data__SHIFT 0x0
+#define UMCCH0_1_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_1_PerfMonCtr3_Hi
+#define UMCCH0_1_PerfMonCtr3_Hi__Data__SHIFT 0x0
+#define UMCCH0_1_PerfMonCtr3_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_1_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH0_1_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH0_1_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_1_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L
+#define UMCCH0_1_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH0_1_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH0_1_PerfMonCtl4
+#define UMCCH0_1_PerfMonCtl4__EventSelect__SHIFT 0x0
+#define UMCCH0_1_PerfMonCtl4__RdWrMask__SHIFT 0x8
+#define UMCCH0_1_PerfMonCtl4__PriorityMask__SHIFT 0xa
+#define UMCCH0_1_PerfMonCtl4__ReqSizeMask__SHIFT 0xe
+#define UMCCH0_1_PerfMonCtl4__BankSel__SHIFT 0x10
+#define UMCCH0_1_PerfMonCtl4__VCSel__SHIFT 0x18
+#define UMCCH0_1_PerfMonCtl4__SubChanMask__SHIFT 0x1d
+#define UMCCH0_1_PerfMonCtl4__Enable__SHIFT 0x1f
+#define UMCCH0_1_PerfMonCtl4__EventSelect_MASK 0x000000FFL
+#define UMCCH0_1_PerfMonCtl4__RdWrMask_MASK 0x00000300L
+#define UMCCH0_1_PerfMonCtl4__PriorityMask_MASK 0x00003C00L
+#define UMCCH0_1_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH0_1_PerfMonCtl4__BankSel_MASK 0x00FF0000L
+#define UMCCH0_1_PerfMonCtl4__VCSel_MASK 0x1F000000L
+#define UMCCH0_1_PerfMonCtl4__SubChanMask_MASK 0x60000000L
+#define UMCCH0_1_PerfMonCtl4__Enable_MASK 0x80000000L
+//UMCCH0_1_PerfMonCtr4_Lo
+#define UMCCH0_1_PerfMonCtr4_Lo__Data__SHIFT 0x0
+#define UMCCH0_1_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_1_PerfMonCtr4_Hi
+#define UMCCH0_1_PerfMonCtr4_Hi__Data__SHIFT 0x0
+#define UMCCH0_1_PerfMonCtr4_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_1_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH0_1_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH0_1_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_1_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L
+#define UMCCH0_1_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH0_1_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH0_1_PerfMonCtl5
+#define UMCCH0_1_PerfMonCtl5__EventSelect__SHIFT 0x0
+#define UMCCH0_1_PerfMonCtl5__RdWrMask__SHIFT 0x8
+#define UMCCH0_1_PerfMonCtl5__PriorityMask__SHIFT 0xa
+#define UMCCH0_1_PerfMonCtl5__ReqSizeMask__SHIFT 0xe
+#define UMCCH0_1_PerfMonCtl5__BankSel__SHIFT 0x10
+#define UMCCH0_1_PerfMonCtl5__VCSel__SHIFT 0x18
+#define UMCCH0_1_PerfMonCtl5__SubChanMask__SHIFT 0x1d
+#define UMCCH0_1_PerfMonCtl5__Enable__SHIFT 0x1f
+#define UMCCH0_1_PerfMonCtl5__EventSelect_MASK 0x000000FFL
+#define UMCCH0_1_PerfMonCtl5__RdWrMask_MASK 0x00000300L
+#define UMCCH0_1_PerfMonCtl5__PriorityMask_MASK 0x00003C00L
+#define UMCCH0_1_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH0_1_PerfMonCtl5__BankSel_MASK 0x00FF0000L
+#define UMCCH0_1_PerfMonCtl5__VCSel_MASK 0x1F000000L
+#define UMCCH0_1_PerfMonCtl5__SubChanMask_MASK 0x60000000L
+#define UMCCH0_1_PerfMonCtl5__Enable_MASK 0x80000000L
+//UMCCH0_1_PerfMonCtr5_Lo
+#define UMCCH0_1_PerfMonCtr5_Lo__Data__SHIFT 0x0
+#define UMCCH0_1_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_1_PerfMonCtr5_Hi
+#define UMCCH0_1_PerfMonCtr5_Hi__Data__SHIFT 0x0
+#define UMCCH0_1_PerfMonCtr5_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_1_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH0_1_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH0_1_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_1_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L
+#define UMCCH0_1_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH0_1_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH0_1_PerfMonCtl6
+#define UMCCH0_1_PerfMonCtl6__EventSelect__SHIFT 0x0
+#define UMCCH0_1_PerfMonCtl6__RdWrMask__SHIFT 0x8
+#define UMCCH0_1_PerfMonCtl6__PriorityMask__SHIFT 0xa
+#define UMCCH0_1_PerfMonCtl6__ReqSizeMask__SHIFT 0xe
+#define UMCCH0_1_PerfMonCtl6__BankSel__SHIFT 0x10
+#define UMCCH0_1_PerfMonCtl6__VCSel__SHIFT 0x18
+#define UMCCH0_1_PerfMonCtl6__SubChanMask__SHIFT 0x1d
+#define UMCCH0_1_PerfMonCtl6__Enable__SHIFT 0x1f
+#define UMCCH0_1_PerfMonCtl6__EventSelect_MASK 0x000000FFL
+#define UMCCH0_1_PerfMonCtl6__RdWrMask_MASK 0x00000300L
+#define UMCCH0_1_PerfMonCtl6__PriorityMask_MASK 0x00003C00L
+#define UMCCH0_1_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH0_1_PerfMonCtl6__BankSel_MASK 0x00FF0000L
+#define UMCCH0_1_PerfMonCtl6__VCSel_MASK 0x1F000000L
+#define UMCCH0_1_PerfMonCtl6__SubChanMask_MASK 0x60000000L
+#define UMCCH0_1_PerfMonCtl6__Enable_MASK 0x80000000L
+//UMCCH0_1_PerfMonCtr6_Lo
+#define UMCCH0_1_PerfMonCtr6_Lo__Data__SHIFT 0x0
+#define UMCCH0_1_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_1_PerfMonCtr6_Hi
+#define UMCCH0_1_PerfMonCtr6_Hi__Data__SHIFT 0x0
+#define UMCCH0_1_PerfMonCtr6_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_1_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH0_1_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH0_1_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_1_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L
+#define UMCCH0_1_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH0_1_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH0_1_PerfMonCtl7
+#define UMCCH0_1_PerfMonCtl7__EventSelect__SHIFT 0x0
+#define UMCCH0_1_PerfMonCtl7__RdWrMask__SHIFT 0x8
+#define UMCCH0_1_PerfMonCtl7__PriorityMask__SHIFT 0xa
+#define UMCCH0_1_PerfMonCtl7__ReqSizeMask__SHIFT 0xe
+#define UMCCH0_1_PerfMonCtl7__BankSel__SHIFT 0x10
+#define UMCCH0_1_PerfMonCtl7__VCSel__SHIFT 0x18
+#define UMCCH0_1_PerfMonCtl7__SubChanMask__SHIFT 0x1d
+#define UMCCH0_1_PerfMonCtl7__Enable__SHIFT 0x1f
+#define UMCCH0_1_PerfMonCtl7__EventSelect_MASK 0x000000FFL
+#define UMCCH0_1_PerfMonCtl7__RdWrMask_MASK 0x00000300L
+#define UMCCH0_1_PerfMonCtl7__PriorityMask_MASK 0x00003C00L
+#define UMCCH0_1_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH0_1_PerfMonCtl7__BankSel_MASK 0x00FF0000L
+#define UMCCH0_1_PerfMonCtl7__VCSel_MASK 0x1F000000L
+#define UMCCH0_1_PerfMonCtl7__SubChanMask_MASK 0x60000000L
+#define UMCCH0_1_PerfMonCtl7__Enable_MASK 0x80000000L
+//UMCCH0_1_PerfMonCtr7_Lo
+#define UMCCH0_1_PerfMonCtr7_Lo__Data__SHIFT 0x0
+#define UMCCH0_1_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_1_PerfMonCtr7_Hi
+#define UMCCH0_1_PerfMonCtr7_Hi__Data__SHIFT 0x0
+#define UMCCH0_1_PerfMonCtr7_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_1_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH0_1_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH0_1_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_1_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L
+#define UMCCH0_1_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH0_1_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH0_1_PerfMonCtl8
+#define UMCCH0_1_PerfMonCtl8__EventSelect__SHIFT 0x0
+#define UMCCH0_1_PerfMonCtl8__RdWrMask__SHIFT 0x8
+#define UMCCH0_1_PerfMonCtl8__PriorityMask__SHIFT 0xa
+#define UMCCH0_1_PerfMonCtl8__ReqSizeMask__SHIFT 0xe
+#define UMCCH0_1_PerfMonCtl8__BankSel__SHIFT 0x10
+#define UMCCH0_1_PerfMonCtl8__VCSel__SHIFT 0x18
+#define UMCCH0_1_PerfMonCtl8__SubChanMask__SHIFT 0x1d
+#define UMCCH0_1_PerfMonCtl8__Enable__SHIFT 0x1f
+#define UMCCH0_1_PerfMonCtl8__EventSelect_MASK 0x000000FFL
+#define UMCCH0_1_PerfMonCtl8__RdWrMask_MASK 0x00000300L
+#define UMCCH0_1_PerfMonCtl8__PriorityMask_MASK 0x00003C00L
+#define UMCCH0_1_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH0_1_PerfMonCtl8__BankSel_MASK 0x00FF0000L
+#define UMCCH0_1_PerfMonCtl8__VCSel_MASK 0x1F000000L
+#define UMCCH0_1_PerfMonCtl8__SubChanMask_MASK 0x60000000L
+#define UMCCH0_1_PerfMonCtl8__Enable_MASK 0x80000000L
+//UMCCH0_1_PerfMonCtr8_Lo
+#define UMCCH0_1_PerfMonCtr8_Lo__Data__SHIFT 0x0
+#define UMCCH0_1_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_1_PerfMonCtr8_Hi
+#define UMCCH0_1_PerfMonCtr8_Hi__Data__SHIFT 0x0
+#define UMCCH0_1_PerfMonCtr8_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_1_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH0_1_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH0_1_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_1_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L
+#define UMCCH0_1_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH0_1_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L
+
+
+// addressBlock: umc_w_phy_umc1_umcch1_umcchdec
+//UMCCH1_1_BaseAddrCS0
+#define UMCCH1_1_BaseAddrCS0__CSEnable__SHIFT 0x0
+#define UMCCH1_1_BaseAddrCS0__BaseAddr__SHIFT 0x1
+#define UMCCH1_1_BaseAddrCS0__CSEnable_MASK 0x00000001L
+#define UMCCH1_1_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL
+//UMCCH1_1_AddrMaskCS01
+#define UMCCH1_1_AddrMaskCS01__AddrMask__SHIFT 0x1
+#define UMCCH1_1_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL
+//UMCCH1_1_AddrSelCS01
+#define UMCCH1_1_AddrSelCS01__BankBit0__SHIFT 0x0
+#define UMCCH1_1_AddrSelCS01__BankBit1__SHIFT 0x4
+#define UMCCH1_1_AddrSelCS01__BankBit2__SHIFT 0x8
+#define UMCCH1_1_AddrSelCS01__BankBit3__SHIFT 0xc
+#define UMCCH1_1_AddrSelCS01__BankBit4__SHIFT 0x10
+#define UMCCH1_1_AddrSelCS01__RowLo__SHIFT 0x18
+#define UMCCH1_1_AddrSelCS01__RowHi__SHIFT 0x1c
+#define UMCCH1_1_AddrSelCS01__BankBit0_MASK 0x0000000FL
+#define UMCCH1_1_AddrSelCS01__BankBit1_MASK 0x000000F0L
+#define UMCCH1_1_AddrSelCS01__BankBit2_MASK 0x00000F00L
+#define UMCCH1_1_AddrSelCS01__BankBit3_MASK 0x0000F000L
+#define UMCCH1_1_AddrSelCS01__BankBit4_MASK 0x001F0000L
+#define UMCCH1_1_AddrSelCS01__RowLo_MASK 0x0F000000L
+#define UMCCH1_1_AddrSelCS01__RowHi_MASK 0xF0000000L
+//UMCCH1_1_AddrHashBank0
+#define UMCCH1_1_AddrHashBank0__XorEnable__SHIFT 0x0
+#define UMCCH1_1_AddrHashBank0__ColXor__SHIFT 0x1
+#define UMCCH1_1_AddrHashBank0__RowXor__SHIFT 0xe
+#define UMCCH1_1_AddrHashBank0__XorEnable_MASK 0x00000001L
+#define UMCCH1_1_AddrHashBank0__ColXor_MASK 0x00003FFEL
+#define UMCCH1_1_AddrHashBank0__RowXor_MASK 0xFFFFC000L
+//UMCCH1_1_AddrHashBank1
+#define UMCCH1_1_AddrHashBank1__XorEnable__SHIFT 0x0
+#define UMCCH1_1_AddrHashBank1__ColXor__SHIFT 0x1
+#define UMCCH1_1_AddrHashBank1__RowXor__SHIFT 0xe
+#define UMCCH1_1_AddrHashBank1__XorEnable_MASK 0x00000001L
+#define UMCCH1_1_AddrHashBank1__ColXor_MASK 0x00003FFEL
+#define UMCCH1_1_AddrHashBank1__RowXor_MASK 0xFFFFC000L
+//UMCCH1_1_AddrHashBank2
+#define UMCCH1_1_AddrHashBank2__XorEnable__SHIFT 0x0
+#define UMCCH1_1_AddrHashBank2__ColXor__SHIFT 0x1
+#define UMCCH1_1_AddrHashBank2__RowXor__SHIFT 0xe
+#define UMCCH1_1_AddrHashBank2__XorEnable_MASK 0x00000001L
+#define UMCCH1_1_AddrHashBank2__ColXor_MASK 0x00003FFEL
+#define UMCCH1_1_AddrHashBank2__RowXor_MASK 0xFFFFC000L
+//UMCCH1_1_AddrHashBank3
+#define UMCCH1_1_AddrHashBank3__XorEnable__SHIFT 0x0
+#define UMCCH1_1_AddrHashBank3__ColXor__SHIFT 0x1
+#define UMCCH1_1_AddrHashBank3__RowXor__SHIFT 0xe
+#define UMCCH1_1_AddrHashBank3__XorEnable_MASK 0x00000001L
+#define UMCCH1_1_AddrHashBank3__ColXor_MASK 0x00003FFEL
+#define UMCCH1_1_AddrHashBank3__RowXor_MASK 0xFFFFC000L
+//UMCCH1_1_AddrHashBank4
+#define UMCCH1_1_AddrHashBank4__XorEnable__SHIFT 0x0
+#define UMCCH1_1_AddrHashBank4__ColXor__SHIFT 0x1
+#define UMCCH1_1_AddrHashBank4__RowXor__SHIFT 0xe
+#define UMCCH1_1_AddrHashBank4__XorEnable_MASK 0x00000001L
+#define UMCCH1_1_AddrHashBank4__ColXor_MASK 0x00003FFEL
+#define UMCCH1_1_AddrHashBank4__RowXor_MASK 0xFFFFC000L
+//UMCCH1_1_AddrHashBank5
+#define UMCCH1_1_AddrHashBank5__XorEnable__SHIFT 0x0
+#define UMCCH1_1_AddrHashBank5__ColXor__SHIFT 0x1
+#define UMCCH1_1_AddrHashBank5__RowXor__SHIFT 0xe
+#define UMCCH1_1_AddrHashBank5__XorEnable_MASK 0x00000001L
+#define UMCCH1_1_AddrHashBank5__ColXor_MASK 0x00003FFEL
+#define UMCCH1_1_AddrHashBank5__RowXor_MASK 0xFFFFC000L
+//UMCCH1_1_EccErrCntSel
+#define UMCCH1_1_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0
+#define UMCCH1_1_EccErrCntSel__EccErrInt__SHIFT 0xc
+#define UMCCH1_1_EccErrCntSel__EccErrCntEn__SHIFT 0xf
+#define UMCCH1_1_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL
+#define UMCCH1_1_EccErrCntSel__EccErrInt_MASK 0x00003000L
+#define UMCCH1_1_EccErrCntSel__EccErrCntEn_MASK 0x00008000L
+//UMCCH1_1_EccErrCnt
+#define UMCCH1_1_EccErrCnt__EccErrCnt__SHIFT 0x0
+#define UMCCH1_1_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL
+//UMCCH1_1_PerfMonCtlClk
+#define UMCCH1_1_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0
+#define UMCCH1_1_PerfMonCtlClk__ClkGate__SHIFT 0x16
+#define UMCCH1_1_PerfMonCtlClk__GlblReset__SHIFT 0x18
+#define UMCCH1_1_PerfMonCtlClk__GlblMonEn__SHIFT 0x19
+#define UMCCH1_1_PerfMonCtlClk__NumCounters__SHIFT 0x1a
+#define UMCCH1_1_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f
+#define UMCCH1_1_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL
+#define UMCCH1_1_PerfMonCtlClk__ClkGate_MASK 0x00400000L
+#define UMCCH1_1_PerfMonCtlClk__GlblReset_MASK 0x01000000L
+#define UMCCH1_1_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L
+#define UMCCH1_1_PerfMonCtlClk__NumCounters_MASK 0x3C000000L
+#define UMCCH1_1_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L
+//UMCCH1_1_PerfMonCtrClk_Lo
+#define UMCCH1_1_PerfMonCtrClk_Lo__Data__SHIFT 0x0
+#define UMCCH1_1_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_1_PerfMonCtrClk_Hi
+#define UMCCH1_1_PerfMonCtrClk_Hi__Data__SHIFT 0x0
+#define UMCCH1_1_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_1_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_1_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L
+//UMCCH1_1_PerfMonCtl1
+#define UMCCH1_1_PerfMonCtl1__EventSelect__SHIFT 0x0
+#define UMCCH1_1_PerfMonCtl1__RdWrMask__SHIFT 0x8
+#define UMCCH1_1_PerfMonCtl1__PriorityMask__SHIFT 0xa
+#define UMCCH1_1_PerfMonCtl1__ReqSizeMask__SHIFT 0xe
+#define UMCCH1_1_PerfMonCtl1__BankSel__SHIFT 0x10
+#define UMCCH1_1_PerfMonCtl1__VCSel__SHIFT 0x18
+#define UMCCH1_1_PerfMonCtl1__SubChanMask__SHIFT 0x1d
+#define UMCCH1_1_PerfMonCtl1__Enable__SHIFT 0x1f
+#define UMCCH1_1_PerfMonCtl1__EventSelect_MASK 0x000000FFL
+#define UMCCH1_1_PerfMonCtl1__RdWrMask_MASK 0x00000300L
+#define UMCCH1_1_PerfMonCtl1__PriorityMask_MASK 0x00003C00L
+#define UMCCH1_1_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH1_1_PerfMonCtl1__BankSel_MASK 0x00FF0000L
+#define UMCCH1_1_PerfMonCtl1__VCSel_MASK 0x1F000000L
+#define UMCCH1_1_PerfMonCtl1__SubChanMask_MASK 0x60000000L
+#define UMCCH1_1_PerfMonCtl1__Enable_MASK 0x80000000L
+//UMCCH1_1_PerfMonCtr1_Lo
+#define UMCCH1_1_PerfMonCtr1_Lo__Data__SHIFT 0x0
+#define UMCCH1_1_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_1_PerfMonCtr1_Hi
+#define UMCCH1_1_PerfMonCtr1_Hi__Data__SHIFT 0x0
+#define UMCCH1_1_PerfMonCtr1_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_1_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH1_1_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH1_1_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_1_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L
+#define UMCCH1_1_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH1_1_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH1_1_PerfMonCtl2
+#define UMCCH1_1_PerfMonCtl2__EventSelect__SHIFT 0x0
+#define UMCCH1_1_PerfMonCtl2__RdWrMask__SHIFT 0x8
+#define UMCCH1_1_PerfMonCtl2__PriorityMask__SHIFT 0xa
+#define UMCCH1_1_PerfMonCtl2__ReqSizeMask__SHIFT 0xe
+#define UMCCH1_1_PerfMonCtl2__BankSel__SHIFT 0x10
+#define UMCCH1_1_PerfMonCtl2__VCSel__SHIFT 0x18
+#define UMCCH1_1_PerfMonCtl2__SubChanMask__SHIFT 0x1d
+#define UMCCH1_1_PerfMonCtl2__Enable__SHIFT 0x1f
+#define UMCCH1_1_PerfMonCtl2__EventSelect_MASK 0x000000FFL
+#define UMCCH1_1_PerfMonCtl2__RdWrMask_MASK 0x00000300L
+#define UMCCH1_1_PerfMonCtl2__PriorityMask_MASK 0x00003C00L
+#define UMCCH1_1_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH1_1_PerfMonCtl2__BankSel_MASK 0x00FF0000L
+#define UMCCH1_1_PerfMonCtl2__VCSel_MASK 0x1F000000L
+#define UMCCH1_1_PerfMonCtl2__SubChanMask_MASK 0x60000000L
+#define UMCCH1_1_PerfMonCtl2__Enable_MASK 0x80000000L
+//UMCCH1_1_PerfMonCtr2_Lo
+#define UMCCH1_1_PerfMonCtr2_Lo__Data__SHIFT 0x0
+#define UMCCH1_1_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_1_PerfMonCtr2_Hi
+#define UMCCH1_1_PerfMonCtr2_Hi__Data__SHIFT 0x0
+#define UMCCH1_1_PerfMonCtr2_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_1_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH1_1_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH1_1_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_1_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L
+#define UMCCH1_1_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH1_1_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH1_1_PerfMonCtl3
+#define UMCCH1_1_PerfMonCtl3__EventSelect__SHIFT 0x0
+#define UMCCH1_1_PerfMonCtl3__RdWrMask__SHIFT 0x8
+#define UMCCH1_1_PerfMonCtl3__PriorityMask__SHIFT 0xa
+#define UMCCH1_1_PerfMonCtl3__ReqSizeMask__SHIFT 0xe
+#define UMCCH1_1_PerfMonCtl3__BankSel__SHIFT 0x10
+#define UMCCH1_1_PerfMonCtl3__VCSel__SHIFT 0x18
+#define UMCCH1_1_PerfMonCtl3__SubChanMask__SHIFT 0x1d
+#define UMCCH1_1_PerfMonCtl3__Enable__SHIFT 0x1f
+#define UMCCH1_1_PerfMonCtl3__EventSelect_MASK 0x000000FFL
+#define UMCCH1_1_PerfMonCtl3__RdWrMask_MASK 0x00000300L
+#define UMCCH1_1_PerfMonCtl3__PriorityMask_MASK 0x00003C00L
+#define UMCCH1_1_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH1_1_PerfMonCtl3__BankSel_MASK 0x00FF0000L
+#define UMCCH1_1_PerfMonCtl3__VCSel_MASK 0x1F000000L
+#define UMCCH1_1_PerfMonCtl3__SubChanMask_MASK 0x60000000L
+#define UMCCH1_1_PerfMonCtl3__Enable_MASK 0x80000000L
+//UMCCH1_1_PerfMonCtr3_Lo
+#define UMCCH1_1_PerfMonCtr3_Lo__Data__SHIFT 0x0
+#define UMCCH1_1_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_1_PerfMonCtr3_Hi
+#define UMCCH1_1_PerfMonCtr3_Hi__Data__SHIFT 0x0
+#define UMCCH1_1_PerfMonCtr3_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_1_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH1_1_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH1_1_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_1_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L
+#define UMCCH1_1_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH1_1_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH1_1_PerfMonCtl4
+#define UMCCH1_1_PerfMonCtl4__EventSelect__SHIFT 0x0
+#define UMCCH1_1_PerfMonCtl4__RdWrMask__SHIFT 0x8
+#define UMCCH1_1_PerfMonCtl4__PriorityMask__SHIFT 0xa
+#define UMCCH1_1_PerfMonCtl4__ReqSizeMask__SHIFT 0xe
+#define UMCCH1_1_PerfMonCtl4__BankSel__SHIFT 0x10
+#define UMCCH1_1_PerfMonCtl4__VCSel__SHIFT 0x18
+#define UMCCH1_1_PerfMonCtl4__SubChanMask__SHIFT 0x1d
+#define UMCCH1_1_PerfMonCtl4__Enable__SHIFT 0x1f
+#define UMCCH1_1_PerfMonCtl4__EventSelect_MASK 0x000000FFL
+#define UMCCH1_1_PerfMonCtl4__RdWrMask_MASK 0x00000300L
+#define UMCCH1_1_PerfMonCtl4__PriorityMask_MASK 0x00003C00L
+#define UMCCH1_1_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH1_1_PerfMonCtl4__BankSel_MASK 0x00FF0000L
+#define UMCCH1_1_PerfMonCtl4__VCSel_MASK 0x1F000000L
+#define UMCCH1_1_PerfMonCtl4__SubChanMask_MASK 0x60000000L
+#define UMCCH1_1_PerfMonCtl4__Enable_MASK 0x80000000L
+//UMCCH1_1_PerfMonCtr4_Lo
+#define UMCCH1_1_PerfMonCtr4_Lo__Data__SHIFT 0x0
+#define UMCCH1_1_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_1_PerfMonCtr4_Hi
+#define UMCCH1_1_PerfMonCtr4_Hi__Data__SHIFT 0x0
+#define UMCCH1_1_PerfMonCtr4_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_1_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH1_1_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH1_1_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_1_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L
+#define UMCCH1_1_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH1_1_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH1_1_PerfMonCtl5
+#define UMCCH1_1_PerfMonCtl5__EventSelect__SHIFT 0x0
+#define UMCCH1_1_PerfMonCtl5__RdWrMask__SHIFT 0x8
+#define UMCCH1_1_PerfMonCtl5__PriorityMask__SHIFT 0xa
+#define UMCCH1_1_PerfMonCtl5__ReqSizeMask__SHIFT 0xe
+#define UMCCH1_1_PerfMonCtl5__BankSel__SHIFT 0x10
+#define UMCCH1_1_PerfMonCtl5__VCSel__SHIFT 0x18
+#define UMCCH1_1_PerfMonCtl5__SubChanMask__SHIFT 0x1d
+#define UMCCH1_1_PerfMonCtl5__Enable__SHIFT 0x1f
+#define UMCCH1_1_PerfMonCtl5__EventSelect_MASK 0x000000FFL
+#define UMCCH1_1_PerfMonCtl5__RdWrMask_MASK 0x00000300L
+#define UMCCH1_1_PerfMonCtl5__PriorityMask_MASK 0x00003C00L
+#define UMCCH1_1_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH1_1_PerfMonCtl5__BankSel_MASK 0x00FF0000L
+#define UMCCH1_1_PerfMonCtl5__VCSel_MASK 0x1F000000L
+#define UMCCH1_1_PerfMonCtl5__SubChanMask_MASK 0x60000000L
+#define UMCCH1_1_PerfMonCtl5__Enable_MASK 0x80000000L
+//UMCCH1_1_PerfMonCtr5_Lo
+#define UMCCH1_1_PerfMonCtr5_Lo__Data__SHIFT 0x0
+#define UMCCH1_1_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_1_PerfMonCtr5_Hi
+#define UMCCH1_1_PerfMonCtr5_Hi__Data__SHIFT 0x0
+#define UMCCH1_1_PerfMonCtr5_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_1_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH1_1_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH1_1_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_1_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L
+#define UMCCH1_1_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH1_1_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH1_1_PerfMonCtl6
+#define UMCCH1_1_PerfMonCtl6__EventSelect__SHIFT 0x0
+#define UMCCH1_1_PerfMonCtl6__RdWrMask__SHIFT 0x8
+#define UMCCH1_1_PerfMonCtl6__PriorityMask__SHIFT 0xa
+#define UMCCH1_1_PerfMonCtl6__ReqSizeMask__SHIFT 0xe
+#define UMCCH1_1_PerfMonCtl6__BankSel__SHIFT 0x10
+#define UMCCH1_1_PerfMonCtl6__VCSel__SHIFT 0x18
+#define UMCCH1_1_PerfMonCtl6__SubChanMask__SHIFT 0x1d
+#define UMCCH1_1_PerfMonCtl6__Enable__SHIFT 0x1f
+#define UMCCH1_1_PerfMonCtl6__EventSelect_MASK 0x000000FFL
+#define UMCCH1_1_PerfMonCtl6__RdWrMask_MASK 0x00000300L
+#define UMCCH1_1_PerfMonCtl6__PriorityMask_MASK 0x00003C00L
+#define UMCCH1_1_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH1_1_PerfMonCtl6__BankSel_MASK 0x00FF0000L
+#define UMCCH1_1_PerfMonCtl6__VCSel_MASK 0x1F000000L
+#define UMCCH1_1_PerfMonCtl6__SubChanMask_MASK 0x60000000L
+#define UMCCH1_1_PerfMonCtl6__Enable_MASK 0x80000000L
+//UMCCH1_1_PerfMonCtr6_Lo
+#define UMCCH1_1_PerfMonCtr6_Lo__Data__SHIFT 0x0
+#define UMCCH1_1_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_1_PerfMonCtr6_Hi
+#define UMCCH1_1_PerfMonCtr6_Hi__Data__SHIFT 0x0
+#define UMCCH1_1_PerfMonCtr6_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_1_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH1_1_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH1_1_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_1_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L
+#define UMCCH1_1_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH1_1_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH1_1_PerfMonCtl7
+#define UMCCH1_1_PerfMonCtl7__EventSelect__SHIFT 0x0
+#define UMCCH1_1_PerfMonCtl7__RdWrMask__SHIFT 0x8
+#define UMCCH1_1_PerfMonCtl7__PriorityMask__SHIFT 0xa
+#define UMCCH1_1_PerfMonCtl7__ReqSizeMask__SHIFT 0xe
+#define UMCCH1_1_PerfMonCtl7__BankSel__SHIFT 0x10
+#define UMCCH1_1_PerfMonCtl7__VCSel__SHIFT 0x18
+#define UMCCH1_1_PerfMonCtl7__SubChanMask__SHIFT 0x1d
+#define UMCCH1_1_PerfMonCtl7__Enable__SHIFT 0x1f
+#define UMCCH1_1_PerfMonCtl7__EventSelect_MASK 0x000000FFL
+#define UMCCH1_1_PerfMonCtl7__RdWrMask_MASK 0x00000300L
+#define UMCCH1_1_PerfMonCtl7__PriorityMask_MASK 0x00003C00L
+#define UMCCH1_1_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH1_1_PerfMonCtl7__BankSel_MASK 0x00FF0000L
+#define UMCCH1_1_PerfMonCtl7__VCSel_MASK 0x1F000000L
+#define UMCCH1_1_PerfMonCtl7__SubChanMask_MASK 0x60000000L
+#define UMCCH1_1_PerfMonCtl7__Enable_MASK 0x80000000L
+//UMCCH1_1_PerfMonCtr7_Lo
+#define UMCCH1_1_PerfMonCtr7_Lo__Data__SHIFT 0x0
+#define UMCCH1_1_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_1_PerfMonCtr7_Hi
+#define UMCCH1_1_PerfMonCtr7_Hi__Data__SHIFT 0x0
+#define UMCCH1_1_PerfMonCtr7_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_1_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH1_1_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH1_1_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_1_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L
+#define UMCCH1_1_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH1_1_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH1_1_PerfMonCtl8
+#define UMCCH1_1_PerfMonCtl8__EventSelect__SHIFT 0x0
+#define UMCCH1_1_PerfMonCtl8__RdWrMask__SHIFT 0x8
+#define UMCCH1_1_PerfMonCtl8__PriorityMask__SHIFT 0xa
+#define UMCCH1_1_PerfMonCtl8__ReqSizeMask__SHIFT 0xe
+#define UMCCH1_1_PerfMonCtl8__BankSel__SHIFT 0x10
+#define UMCCH1_1_PerfMonCtl8__VCSel__SHIFT 0x18
+#define UMCCH1_1_PerfMonCtl8__SubChanMask__SHIFT 0x1d
+#define UMCCH1_1_PerfMonCtl8__Enable__SHIFT 0x1f
+#define UMCCH1_1_PerfMonCtl8__EventSelect_MASK 0x000000FFL
+#define UMCCH1_1_PerfMonCtl8__RdWrMask_MASK 0x00000300L
+#define UMCCH1_1_PerfMonCtl8__PriorityMask_MASK 0x00003C00L
+#define UMCCH1_1_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH1_1_PerfMonCtl8__BankSel_MASK 0x00FF0000L
+#define UMCCH1_1_PerfMonCtl8__VCSel_MASK 0x1F000000L
+#define UMCCH1_1_PerfMonCtl8__SubChanMask_MASK 0x60000000L
+#define UMCCH1_1_PerfMonCtl8__Enable_MASK 0x80000000L
+//UMCCH1_1_PerfMonCtr8_Lo
+#define UMCCH1_1_PerfMonCtr8_Lo__Data__SHIFT 0x0
+#define UMCCH1_1_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_1_PerfMonCtr8_Hi
+#define UMCCH1_1_PerfMonCtr8_Hi__Data__SHIFT 0x0
+#define UMCCH1_1_PerfMonCtr8_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_1_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH1_1_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH1_1_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_1_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L
+#define UMCCH1_1_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH1_1_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L
+
+
+// addressBlock: umc_w_phy_umc1_umcch2_umcchdec
+//UMCCH2_1_BaseAddrCS0
+#define UMCCH2_1_BaseAddrCS0__CSEnable__SHIFT 0x0
+#define UMCCH2_1_BaseAddrCS0__BaseAddr__SHIFT 0x1
+#define UMCCH2_1_BaseAddrCS0__CSEnable_MASK 0x00000001L
+#define UMCCH2_1_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL
+//UMCCH2_1_AddrMaskCS01
+#define UMCCH2_1_AddrMaskCS01__AddrMask__SHIFT 0x1
+#define UMCCH2_1_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL
+//UMCCH2_1_AddrSelCS01
+#define UMCCH2_1_AddrSelCS01__BankBit0__SHIFT 0x0
+#define UMCCH2_1_AddrSelCS01__BankBit1__SHIFT 0x4
+#define UMCCH2_1_AddrSelCS01__BankBit2__SHIFT 0x8
+#define UMCCH2_1_AddrSelCS01__BankBit3__SHIFT 0xc
+#define UMCCH2_1_AddrSelCS01__BankBit4__SHIFT 0x10
+#define UMCCH2_1_AddrSelCS01__RowLo__SHIFT 0x18
+#define UMCCH2_1_AddrSelCS01__RowHi__SHIFT 0x1c
+#define UMCCH2_1_AddrSelCS01__BankBit0_MASK 0x0000000FL
+#define UMCCH2_1_AddrSelCS01__BankBit1_MASK 0x000000F0L
+#define UMCCH2_1_AddrSelCS01__BankBit2_MASK 0x00000F00L
+#define UMCCH2_1_AddrSelCS01__BankBit3_MASK 0x0000F000L
+#define UMCCH2_1_AddrSelCS01__BankBit4_MASK 0x001F0000L
+#define UMCCH2_1_AddrSelCS01__RowLo_MASK 0x0F000000L
+#define UMCCH2_1_AddrSelCS01__RowHi_MASK 0xF0000000L
+//UMCCH2_1_AddrHashBank0
+#define UMCCH2_1_AddrHashBank0__XorEnable__SHIFT 0x0
+#define UMCCH2_1_AddrHashBank0__ColXor__SHIFT 0x1
+#define UMCCH2_1_AddrHashBank0__RowXor__SHIFT 0xe
+#define UMCCH2_1_AddrHashBank0__XorEnable_MASK 0x00000001L
+#define UMCCH2_1_AddrHashBank0__ColXor_MASK 0x00003FFEL
+#define UMCCH2_1_AddrHashBank0__RowXor_MASK 0xFFFFC000L
+//UMCCH2_1_AddrHashBank1
+#define UMCCH2_1_AddrHashBank1__XorEnable__SHIFT 0x0
+#define UMCCH2_1_AddrHashBank1__ColXor__SHIFT 0x1
+#define UMCCH2_1_AddrHashBank1__RowXor__SHIFT 0xe
+#define UMCCH2_1_AddrHashBank1__XorEnable_MASK 0x00000001L
+#define UMCCH2_1_AddrHashBank1__ColXor_MASK 0x00003FFEL
+#define UMCCH2_1_AddrHashBank1__RowXor_MASK 0xFFFFC000L
+//UMCCH2_1_AddrHashBank2
+#define UMCCH2_1_AddrHashBank2__XorEnable__SHIFT 0x0
+#define UMCCH2_1_AddrHashBank2__ColXor__SHIFT 0x1
+#define UMCCH2_1_AddrHashBank2__RowXor__SHIFT 0xe
+#define UMCCH2_1_AddrHashBank2__XorEnable_MASK 0x00000001L
+#define UMCCH2_1_AddrHashBank2__ColXor_MASK 0x00003FFEL
+#define UMCCH2_1_AddrHashBank2__RowXor_MASK 0xFFFFC000L
+//UMCCH2_1_AddrHashBank3
+#define UMCCH2_1_AddrHashBank3__XorEnable__SHIFT 0x0
+#define UMCCH2_1_AddrHashBank3__ColXor__SHIFT 0x1
+#define UMCCH2_1_AddrHashBank3__RowXor__SHIFT 0xe
+#define UMCCH2_1_AddrHashBank3__XorEnable_MASK 0x00000001L
+#define UMCCH2_1_AddrHashBank3__ColXor_MASK 0x00003FFEL
+#define UMCCH2_1_AddrHashBank3__RowXor_MASK 0xFFFFC000L
+//UMCCH2_1_AddrHashBank4
+#define UMCCH2_1_AddrHashBank4__XorEnable__SHIFT 0x0
+#define UMCCH2_1_AddrHashBank4__ColXor__SHIFT 0x1
+#define UMCCH2_1_AddrHashBank4__RowXor__SHIFT 0xe
+#define UMCCH2_1_AddrHashBank4__XorEnable_MASK 0x00000001L
+#define UMCCH2_1_AddrHashBank4__ColXor_MASK 0x00003FFEL
+#define UMCCH2_1_AddrHashBank4__RowXor_MASK 0xFFFFC000L
+//UMCCH2_1_AddrHashBank5
+#define UMCCH2_1_AddrHashBank5__XorEnable__SHIFT 0x0
+#define UMCCH2_1_AddrHashBank5__ColXor__SHIFT 0x1
+#define UMCCH2_1_AddrHashBank5__RowXor__SHIFT 0xe
+#define UMCCH2_1_AddrHashBank5__XorEnable_MASK 0x00000001L
+#define UMCCH2_1_AddrHashBank5__ColXor_MASK 0x00003FFEL
+#define UMCCH2_1_AddrHashBank5__RowXor_MASK 0xFFFFC000L
+//UMCCH2_1_EccErrCntSel
+#define UMCCH2_1_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0
+#define UMCCH2_1_EccErrCntSel__EccErrInt__SHIFT 0xc
+#define UMCCH2_1_EccErrCntSel__EccErrCntEn__SHIFT 0xf
+#define UMCCH2_1_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL
+#define UMCCH2_1_EccErrCntSel__EccErrInt_MASK 0x00003000L
+#define UMCCH2_1_EccErrCntSel__EccErrCntEn_MASK 0x00008000L
+//UMCCH2_1_EccErrCnt
+#define UMCCH2_1_EccErrCnt__EccErrCnt__SHIFT 0x0
+#define UMCCH2_1_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL
+//UMCCH2_1_PerfMonCtlClk
+#define UMCCH2_1_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0
+#define UMCCH2_1_PerfMonCtlClk__ClkGate__SHIFT 0x16
+#define UMCCH2_1_PerfMonCtlClk__GlblReset__SHIFT 0x18
+#define UMCCH2_1_PerfMonCtlClk__GlblMonEn__SHIFT 0x19
+#define UMCCH2_1_PerfMonCtlClk__NumCounters__SHIFT 0x1a
+#define UMCCH2_1_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f
+#define UMCCH2_1_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL
+#define UMCCH2_1_PerfMonCtlClk__ClkGate_MASK 0x00400000L
+#define UMCCH2_1_PerfMonCtlClk__GlblReset_MASK 0x01000000L
+#define UMCCH2_1_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L
+#define UMCCH2_1_PerfMonCtlClk__NumCounters_MASK 0x3C000000L
+#define UMCCH2_1_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L
+//UMCCH2_1_PerfMonCtrClk_Lo
+#define UMCCH2_1_PerfMonCtrClk_Lo__Data__SHIFT 0x0
+#define UMCCH2_1_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_1_PerfMonCtrClk_Hi
+#define UMCCH2_1_PerfMonCtrClk_Hi__Data__SHIFT 0x0
+#define UMCCH2_1_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_1_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_1_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L
+//UMCCH2_1_PerfMonCtl1
+#define UMCCH2_1_PerfMonCtl1__EventSelect__SHIFT 0x0
+#define UMCCH2_1_PerfMonCtl1__RdWrMask__SHIFT 0x8
+#define UMCCH2_1_PerfMonCtl1__PriorityMask__SHIFT 0xa
+#define UMCCH2_1_PerfMonCtl1__ReqSizeMask__SHIFT 0xe
+#define UMCCH2_1_PerfMonCtl1__BankSel__SHIFT 0x10
+#define UMCCH2_1_PerfMonCtl1__VCSel__SHIFT 0x18
+#define UMCCH2_1_PerfMonCtl1__SubChanMask__SHIFT 0x1d
+#define UMCCH2_1_PerfMonCtl1__Enable__SHIFT 0x1f
+#define UMCCH2_1_PerfMonCtl1__EventSelect_MASK 0x000000FFL
+#define UMCCH2_1_PerfMonCtl1__RdWrMask_MASK 0x00000300L
+#define UMCCH2_1_PerfMonCtl1__PriorityMask_MASK 0x00003C00L
+#define UMCCH2_1_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH2_1_PerfMonCtl1__BankSel_MASK 0x00FF0000L
+#define UMCCH2_1_PerfMonCtl1__VCSel_MASK 0x1F000000L
+#define UMCCH2_1_PerfMonCtl1__SubChanMask_MASK 0x60000000L
+#define UMCCH2_1_PerfMonCtl1__Enable_MASK 0x80000000L
+//UMCCH2_1_PerfMonCtr1_Lo
+#define UMCCH2_1_PerfMonCtr1_Lo__Data__SHIFT 0x0
+#define UMCCH2_1_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_1_PerfMonCtr1_Hi
+#define UMCCH2_1_PerfMonCtr1_Hi__Data__SHIFT 0x0
+#define UMCCH2_1_PerfMonCtr1_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_1_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH2_1_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH2_1_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_1_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L
+#define UMCCH2_1_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH2_1_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH2_1_PerfMonCtl2
+#define UMCCH2_1_PerfMonCtl2__EventSelect__SHIFT 0x0
+#define UMCCH2_1_PerfMonCtl2__RdWrMask__SHIFT 0x8
+#define UMCCH2_1_PerfMonCtl2__PriorityMask__SHIFT 0xa
+#define UMCCH2_1_PerfMonCtl2__ReqSizeMask__SHIFT 0xe
+#define UMCCH2_1_PerfMonCtl2__BankSel__SHIFT 0x10
+#define UMCCH2_1_PerfMonCtl2__VCSel__SHIFT 0x18
+#define UMCCH2_1_PerfMonCtl2__SubChanMask__SHIFT 0x1d
+#define UMCCH2_1_PerfMonCtl2__Enable__SHIFT 0x1f
+#define UMCCH2_1_PerfMonCtl2__EventSelect_MASK 0x000000FFL
+#define UMCCH2_1_PerfMonCtl2__RdWrMask_MASK 0x00000300L
+#define UMCCH2_1_PerfMonCtl2__PriorityMask_MASK 0x00003C00L
+#define UMCCH2_1_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH2_1_PerfMonCtl2__BankSel_MASK 0x00FF0000L
+#define UMCCH2_1_PerfMonCtl2__VCSel_MASK 0x1F000000L
+#define UMCCH2_1_PerfMonCtl2__SubChanMask_MASK 0x60000000L
+#define UMCCH2_1_PerfMonCtl2__Enable_MASK 0x80000000L
+//UMCCH2_1_PerfMonCtr2_Lo
+#define UMCCH2_1_PerfMonCtr2_Lo__Data__SHIFT 0x0
+#define UMCCH2_1_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_1_PerfMonCtr2_Hi
+#define UMCCH2_1_PerfMonCtr2_Hi__Data__SHIFT 0x0
+#define UMCCH2_1_PerfMonCtr2_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_1_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH2_1_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH2_1_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_1_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L
+#define UMCCH2_1_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH2_1_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH2_1_PerfMonCtl3
+#define UMCCH2_1_PerfMonCtl3__EventSelect__SHIFT 0x0
+#define UMCCH2_1_PerfMonCtl3__RdWrMask__SHIFT 0x8
+#define UMCCH2_1_PerfMonCtl3__PriorityMask__SHIFT 0xa
+#define UMCCH2_1_PerfMonCtl3__ReqSizeMask__SHIFT 0xe
+#define UMCCH2_1_PerfMonCtl3__BankSel__SHIFT 0x10
+#define UMCCH2_1_PerfMonCtl3__VCSel__SHIFT 0x18
+#define UMCCH2_1_PerfMonCtl3__SubChanMask__SHIFT 0x1d
+#define UMCCH2_1_PerfMonCtl3__Enable__SHIFT 0x1f
+#define UMCCH2_1_PerfMonCtl3__EventSelect_MASK 0x000000FFL
+#define UMCCH2_1_PerfMonCtl3__RdWrMask_MASK 0x00000300L
+#define UMCCH2_1_PerfMonCtl3__PriorityMask_MASK 0x00003C00L
+#define UMCCH2_1_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH2_1_PerfMonCtl3__BankSel_MASK 0x00FF0000L
+#define UMCCH2_1_PerfMonCtl3__VCSel_MASK 0x1F000000L
+#define UMCCH2_1_PerfMonCtl3__SubChanMask_MASK 0x60000000L
+#define UMCCH2_1_PerfMonCtl3__Enable_MASK 0x80000000L
+//UMCCH2_1_PerfMonCtr3_Lo
+#define UMCCH2_1_PerfMonCtr3_Lo__Data__SHIFT 0x0
+#define UMCCH2_1_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_1_PerfMonCtr3_Hi
+#define UMCCH2_1_PerfMonCtr3_Hi__Data__SHIFT 0x0
+#define UMCCH2_1_PerfMonCtr3_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_1_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH2_1_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH2_1_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_1_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L
+#define UMCCH2_1_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH2_1_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH2_1_PerfMonCtl4
+#define UMCCH2_1_PerfMonCtl4__EventSelect__SHIFT 0x0
+#define UMCCH2_1_PerfMonCtl4__RdWrMask__SHIFT 0x8
+#define UMCCH2_1_PerfMonCtl4__PriorityMask__SHIFT 0xa
+#define UMCCH2_1_PerfMonCtl4__ReqSizeMask__SHIFT 0xe
+#define UMCCH2_1_PerfMonCtl4__BankSel__SHIFT 0x10
+#define UMCCH2_1_PerfMonCtl4__VCSel__SHIFT 0x18
+#define UMCCH2_1_PerfMonCtl4__SubChanMask__SHIFT 0x1d
+#define UMCCH2_1_PerfMonCtl4__Enable__SHIFT 0x1f
+#define UMCCH2_1_PerfMonCtl4__EventSelect_MASK 0x000000FFL
+#define UMCCH2_1_PerfMonCtl4__RdWrMask_MASK 0x00000300L
+#define UMCCH2_1_PerfMonCtl4__PriorityMask_MASK 0x00003C00L
+#define UMCCH2_1_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH2_1_PerfMonCtl4__BankSel_MASK 0x00FF0000L
+#define UMCCH2_1_PerfMonCtl4__VCSel_MASK 0x1F000000L
+#define UMCCH2_1_PerfMonCtl4__SubChanMask_MASK 0x60000000L
+#define UMCCH2_1_PerfMonCtl4__Enable_MASK 0x80000000L
+//UMCCH2_1_PerfMonCtr4_Lo
+#define UMCCH2_1_PerfMonCtr4_Lo__Data__SHIFT 0x0
+#define UMCCH2_1_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_1_PerfMonCtr4_Hi
+#define UMCCH2_1_PerfMonCtr4_Hi__Data__SHIFT 0x0
+#define UMCCH2_1_PerfMonCtr4_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_1_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH2_1_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH2_1_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_1_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L
+#define UMCCH2_1_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH2_1_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH2_1_PerfMonCtl5
+#define UMCCH2_1_PerfMonCtl5__EventSelect__SHIFT 0x0
+#define UMCCH2_1_PerfMonCtl5__RdWrMask__SHIFT 0x8
+#define UMCCH2_1_PerfMonCtl5__PriorityMask__SHIFT 0xa
+#define UMCCH2_1_PerfMonCtl5__ReqSizeMask__SHIFT 0xe
+#define UMCCH2_1_PerfMonCtl5__BankSel__SHIFT 0x10
+#define UMCCH2_1_PerfMonCtl5__VCSel__SHIFT 0x18
+#define UMCCH2_1_PerfMonCtl5__SubChanMask__SHIFT 0x1d
+#define UMCCH2_1_PerfMonCtl5__Enable__SHIFT 0x1f
+#define UMCCH2_1_PerfMonCtl5__EventSelect_MASK 0x000000FFL
+#define UMCCH2_1_PerfMonCtl5__RdWrMask_MASK 0x00000300L
+#define UMCCH2_1_PerfMonCtl5__PriorityMask_MASK 0x00003C00L
+#define UMCCH2_1_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH2_1_PerfMonCtl5__BankSel_MASK 0x00FF0000L
+#define UMCCH2_1_PerfMonCtl5__VCSel_MASK 0x1F000000L
+#define UMCCH2_1_PerfMonCtl5__SubChanMask_MASK 0x60000000L
+#define UMCCH2_1_PerfMonCtl5__Enable_MASK 0x80000000L
+//UMCCH2_1_PerfMonCtr5_Lo
+#define UMCCH2_1_PerfMonCtr5_Lo__Data__SHIFT 0x0
+#define UMCCH2_1_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_1_PerfMonCtr5_Hi
+#define UMCCH2_1_PerfMonCtr5_Hi__Data__SHIFT 0x0
+#define UMCCH2_1_PerfMonCtr5_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_1_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH2_1_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH2_1_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_1_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L
+#define UMCCH2_1_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH2_1_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH2_1_PerfMonCtl6
+#define UMCCH2_1_PerfMonCtl6__EventSelect__SHIFT 0x0
+#define UMCCH2_1_PerfMonCtl6__RdWrMask__SHIFT 0x8
+#define UMCCH2_1_PerfMonCtl6__PriorityMask__SHIFT 0xa
+#define UMCCH2_1_PerfMonCtl6__ReqSizeMask__SHIFT 0xe
+#define UMCCH2_1_PerfMonCtl6__BankSel__SHIFT 0x10
+#define UMCCH2_1_PerfMonCtl6__VCSel__SHIFT 0x18
+#define UMCCH2_1_PerfMonCtl6__SubChanMask__SHIFT 0x1d
+#define UMCCH2_1_PerfMonCtl6__Enable__SHIFT 0x1f
+#define UMCCH2_1_PerfMonCtl6__EventSelect_MASK 0x000000FFL
+#define UMCCH2_1_PerfMonCtl6__RdWrMask_MASK 0x00000300L
+#define UMCCH2_1_PerfMonCtl6__PriorityMask_MASK 0x00003C00L
+#define UMCCH2_1_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH2_1_PerfMonCtl6__BankSel_MASK 0x00FF0000L
+#define UMCCH2_1_PerfMonCtl6__VCSel_MASK 0x1F000000L
+#define UMCCH2_1_PerfMonCtl6__SubChanMask_MASK 0x60000000L
+#define UMCCH2_1_PerfMonCtl6__Enable_MASK 0x80000000L
+//UMCCH2_1_PerfMonCtr6_Lo
+#define UMCCH2_1_PerfMonCtr6_Lo__Data__SHIFT 0x0
+#define UMCCH2_1_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_1_PerfMonCtr6_Hi
+#define UMCCH2_1_PerfMonCtr6_Hi__Data__SHIFT 0x0
+#define UMCCH2_1_PerfMonCtr6_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_1_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH2_1_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH2_1_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_1_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L
+#define UMCCH2_1_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH2_1_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH2_1_PerfMonCtl7
+#define UMCCH2_1_PerfMonCtl7__EventSelect__SHIFT 0x0
+#define UMCCH2_1_PerfMonCtl7__RdWrMask__SHIFT 0x8
+#define UMCCH2_1_PerfMonCtl7__PriorityMask__SHIFT 0xa
+#define UMCCH2_1_PerfMonCtl7__ReqSizeMask__SHIFT 0xe
+#define UMCCH2_1_PerfMonCtl7__BankSel__SHIFT 0x10
+#define UMCCH2_1_PerfMonCtl7__VCSel__SHIFT 0x18
+#define UMCCH2_1_PerfMonCtl7__SubChanMask__SHIFT 0x1d
+#define UMCCH2_1_PerfMonCtl7__Enable__SHIFT 0x1f
+#define UMCCH2_1_PerfMonCtl7__EventSelect_MASK 0x000000FFL
+#define UMCCH2_1_PerfMonCtl7__RdWrMask_MASK 0x00000300L
+#define UMCCH2_1_PerfMonCtl7__PriorityMask_MASK 0x00003C00L
+#define UMCCH2_1_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH2_1_PerfMonCtl7__BankSel_MASK 0x00FF0000L
+#define UMCCH2_1_PerfMonCtl7__VCSel_MASK 0x1F000000L
+#define UMCCH2_1_PerfMonCtl7__SubChanMask_MASK 0x60000000L
+#define UMCCH2_1_PerfMonCtl7__Enable_MASK 0x80000000L
+//UMCCH2_1_PerfMonCtr7_Lo
+#define UMCCH2_1_PerfMonCtr7_Lo__Data__SHIFT 0x0
+#define UMCCH2_1_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_1_PerfMonCtr7_Hi
+#define UMCCH2_1_PerfMonCtr7_Hi__Data__SHIFT 0x0
+#define UMCCH2_1_PerfMonCtr7_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_1_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH2_1_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH2_1_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_1_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L
+#define UMCCH2_1_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH2_1_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH2_1_PerfMonCtl8
+#define UMCCH2_1_PerfMonCtl8__EventSelect__SHIFT 0x0
+#define UMCCH2_1_PerfMonCtl8__RdWrMask__SHIFT 0x8
+#define UMCCH2_1_PerfMonCtl8__PriorityMask__SHIFT 0xa
+#define UMCCH2_1_PerfMonCtl8__ReqSizeMask__SHIFT 0xe
+#define UMCCH2_1_PerfMonCtl8__BankSel__SHIFT 0x10
+#define UMCCH2_1_PerfMonCtl8__VCSel__SHIFT 0x18
+#define UMCCH2_1_PerfMonCtl8__SubChanMask__SHIFT 0x1d
+#define UMCCH2_1_PerfMonCtl8__Enable__SHIFT 0x1f
+#define UMCCH2_1_PerfMonCtl8__EventSelect_MASK 0x000000FFL
+#define UMCCH2_1_PerfMonCtl8__RdWrMask_MASK 0x00000300L
+#define UMCCH2_1_PerfMonCtl8__PriorityMask_MASK 0x00003C00L
+#define UMCCH2_1_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH2_1_PerfMonCtl8__BankSel_MASK 0x00FF0000L
+#define UMCCH2_1_PerfMonCtl8__VCSel_MASK 0x1F000000L
+#define UMCCH2_1_PerfMonCtl8__SubChanMask_MASK 0x60000000L
+#define UMCCH2_1_PerfMonCtl8__Enable_MASK 0x80000000L
+//UMCCH2_1_PerfMonCtr8_Lo
+#define UMCCH2_1_PerfMonCtr8_Lo__Data__SHIFT 0x0
+#define UMCCH2_1_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_1_PerfMonCtr8_Hi
+#define UMCCH2_1_PerfMonCtr8_Hi__Data__SHIFT 0x0
+#define UMCCH2_1_PerfMonCtr8_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_1_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH2_1_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH2_1_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_1_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L
+#define UMCCH2_1_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH2_1_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L
+
+
+// addressBlock: umc_w_phy_umc1_umcch3_umcchdec
+//UMCCH3_1_BaseAddrCS0
+#define UMCCH3_1_BaseAddrCS0__CSEnable__SHIFT 0x0
+#define UMCCH3_1_BaseAddrCS0__BaseAddr__SHIFT 0x1
+#define UMCCH3_1_BaseAddrCS0__CSEnable_MASK 0x00000001L
+#define UMCCH3_1_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL
+//UMCCH3_1_AddrMaskCS01
+#define UMCCH3_1_AddrMaskCS01__AddrMask__SHIFT 0x1
+#define UMCCH3_1_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL
+//UMCCH3_1_AddrSelCS01
+#define UMCCH3_1_AddrSelCS01__BankBit0__SHIFT 0x0
+#define UMCCH3_1_AddrSelCS01__BankBit1__SHIFT 0x4
+#define UMCCH3_1_AddrSelCS01__BankBit2__SHIFT 0x8
+#define UMCCH3_1_AddrSelCS01__BankBit3__SHIFT 0xc
+#define UMCCH3_1_AddrSelCS01__BankBit4__SHIFT 0x10
+#define UMCCH3_1_AddrSelCS01__RowLo__SHIFT 0x18
+#define UMCCH3_1_AddrSelCS01__RowHi__SHIFT 0x1c
+#define UMCCH3_1_AddrSelCS01__BankBit0_MASK 0x0000000FL
+#define UMCCH3_1_AddrSelCS01__BankBit1_MASK 0x000000F0L
+#define UMCCH3_1_AddrSelCS01__BankBit2_MASK 0x00000F00L
+#define UMCCH3_1_AddrSelCS01__BankBit3_MASK 0x0000F000L
+#define UMCCH3_1_AddrSelCS01__BankBit4_MASK 0x001F0000L
+#define UMCCH3_1_AddrSelCS01__RowLo_MASK 0x0F000000L
+#define UMCCH3_1_AddrSelCS01__RowHi_MASK 0xF0000000L
+//UMCCH3_1_AddrHashBank0
+#define UMCCH3_1_AddrHashBank0__XorEnable__SHIFT 0x0
+#define UMCCH3_1_AddrHashBank0__ColXor__SHIFT 0x1
+#define UMCCH3_1_AddrHashBank0__RowXor__SHIFT 0xe
+#define UMCCH3_1_AddrHashBank0__XorEnable_MASK 0x00000001L
+#define UMCCH3_1_AddrHashBank0__ColXor_MASK 0x00003FFEL
+#define UMCCH3_1_AddrHashBank0__RowXor_MASK 0xFFFFC000L
+//UMCCH3_1_AddrHashBank1
+#define UMCCH3_1_AddrHashBank1__XorEnable__SHIFT 0x0
+#define UMCCH3_1_AddrHashBank1__ColXor__SHIFT 0x1
+#define UMCCH3_1_AddrHashBank1__RowXor__SHIFT 0xe
+#define UMCCH3_1_AddrHashBank1__XorEnable_MASK 0x00000001L
+#define UMCCH3_1_AddrHashBank1__ColXor_MASK 0x00003FFEL
+#define UMCCH3_1_AddrHashBank1__RowXor_MASK 0xFFFFC000L
+//UMCCH3_1_AddrHashBank2
+#define UMCCH3_1_AddrHashBank2__XorEnable__SHIFT 0x0
+#define UMCCH3_1_AddrHashBank2__ColXor__SHIFT 0x1
+#define UMCCH3_1_AddrHashBank2__RowXor__SHIFT 0xe
+#define UMCCH3_1_AddrHashBank2__XorEnable_MASK 0x00000001L
+#define UMCCH3_1_AddrHashBank2__ColXor_MASK 0x00003FFEL
+#define UMCCH3_1_AddrHashBank2__RowXor_MASK 0xFFFFC000L
+//UMCCH3_1_AddrHashBank3
+#define UMCCH3_1_AddrHashBank3__XorEnable__SHIFT 0x0
+#define UMCCH3_1_AddrHashBank3__ColXor__SHIFT 0x1
+#define UMCCH3_1_AddrHashBank3__RowXor__SHIFT 0xe
+#define UMCCH3_1_AddrHashBank3__XorEnable_MASK 0x00000001L
+#define UMCCH3_1_AddrHashBank3__ColXor_MASK 0x00003FFEL
+#define UMCCH3_1_AddrHashBank3__RowXor_MASK 0xFFFFC000L
+//UMCCH3_1_AddrHashBank4
+#define UMCCH3_1_AddrHashBank4__XorEnable__SHIFT 0x0
+#define UMCCH3_1_AddrHashBank4__ColXor__SHIFT 0x1
+#define UMCCH3_1_AddrHashBank4__RowXor__SHIFT 0xe
+#define UMCCH3_1_AddrHashBank4__XorEnable_MASK 0x00000001L
+#define UMCCH3_1_AddrHashBank4__ColXor_MASK 0x00003FFEL
+#define UMCCH3_1_AddrHashBank4__RowXor_MASK 0xFFFFC000L
+//UMCCH3_1_AddrHashBank5
+#define UMCCH3_1_AddrHashBank5__XorEnable__SHIFT 0x0
+#define UMCCH3_1_AddrHashBank5__ColXor__SHIFT 0x1
+#define UMCCH3_1_AddrHashBank5__RowXor__SHIFT 0xe
+#define UMCCH3_1_AddrHashBank5__XorEnable_MASK 0x00000001L
+#define UMCCH3_1_AddrHashBank5__ColXor_MASK 0x00003FFEL
+#define UMCCH3_1_AddrHashBank5__RowXor_MASK 0xFFFFC000L
+//UMCCH3_1_EccErrCntSel
+#define UMCCH3_1_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0
+#define UMCCH3_1_EccErrCntSel__EccErrInt__SHIFT 0xc
+#define UMCCH3_1_EccErrCntSel__EccErrCntEn__SHIFT 0xf
+#define UMCCH3_1_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL
+#define UMCCH3_1_EccErrCntSel__EccErrInt_MASK 0x00003000L
+#define UMCCH3_1_EccErrCntSel__EccErrCntEn_MASK 0x00008000L
+//UMCCH3_1_EccErrCnt
+#define UMCCH3_1_EccErrCnt__EccErrCnt__SHIFT 0x0
+#define UMCCH3_1_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL
+//UMCCH3_1_PerfMonCtlClk
+#define UMCCH3_1_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0
+#define UMCCH3_1_PerfMonCtlClk__ClkGate__SHIFT 0x16
+#define UMCCH3_1_PerfMonCtlClk__GlblReset__SHIFT 0x18
+#define UMCCH3_1_PerfMonCtlClk__GlblMonEn__SHIFT 0x19
+#define UMCCH3_1_PerfMonCtlClk__NumCounters__SHIFT 0x1a
+#define UMCCH3_1_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f
+#define UMCCH3_1_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL
+#define UMCCH3_1_PerfMonCtlClk__ClkGate_MASK 0x00400000L
+#define UMCCH3_1_PerfMonCtlClk__GlblReset_MASK 0x01000000L
+#define UMCCH3_1_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L
+#define UMCCH3_1_PerfMonCtlClk__NumCounters_MASK 0x3C000000L
+#define UMCCH3_1_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L
+//UMCCH3_1_PerfMonCtrClk_Lo
+#define UMCCH3_1_PerfMonCtrClk_Lo__Data__SHIFT 0x0
+#define UMCCH3_1_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_1_PerfMonCtrClk_Hi
+#define UMCCH3_1_PerfMonCtrClk_Hi__Data__SHIFT 0x0
+#define UMCCH3_1_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_1_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_1_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L
+//UMCCH3_1_PerfMonCtl1
+#define UMCCH3_1_PerfMonCtl1__EventSelect__SHIFT 0x0
+#define UMCCH3_1_PerfMonCtl1__RdWrMask__SHIFT 0x8
+#define UMCCH3_1_PerfMonCtl1__PriorityMask__SHIFT 0xa
+#define UMCCH3_1_PerfMonCtl1__ReqSizeMask__SHIFT 0xe
+#define UMCCH3_1_PerfMonCtl1__BankSel__SHIFT 0x10
+#define UMCCH3_1_PerfMonCtl1__VCSel__SHIFT 0x18
+#define UMCCH3_1_PerfMonCtl1__SubChanMask__SHIFT 0x1d
+#define UMCCH3_1_PerfMonCtl1__Enable__SHIFT 0x1f
+#define UMCCH3_1_PerfMonCtl1__EventSelect_MASK 0x000000FFL
+#define UMCCH3_1_PerfMonCtl1__RdWrMask_MASK 0x00000300L
+#define UMCCH3_1_PerfMonCtl1__PriorityMask_MASK 0x00003C00L
+#define UMCCH3_1_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH3_1_PerfMonCtl1__BankSel_MASK 0x00FF0000L
+#define UMCCH3_1_PerfMonCtl1__VCSel_MASK 0x1F000000L
+#define UMCCH3_1_PerfMonCtl1__SubChanMask_MASK 0x60000000L
+#define UMCCH3_1_PerfMonCtl1__Enable_MASK 0x80000000L
+//UMCCH3_1_PerfMonCtr1_Lo
+#define UMCCH3_1_PerfMonCtr1_Lo__Data__SHIFT 0x0
+#define UMCCH3_1_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_1_PerfMonCtr1_Hi
+#define UMCCH3_1_PerfMonCtr1_Hi__Data__SHIFT 0x0
+#define UMCCH3_1_PerfMonCtr1_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_1_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH3_1_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH3_1_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_1_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L
+#define UMCCH3_1_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH3_1_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH3_1_PerfMonCtl2
+#define UMCCH3_1_PerfMonCtl2__EventSelect__SHIFT 0x0
+#define UMCCH3_1_PerfMonCtl2__RdWrMask__SHIFT 0x8
+#define UMCCH3_1_PerfMonCtl2__PriorityMask__SHIFT 0xa
+#define UMCCH3_1_PerfMonCtl2__ReqSizeMask__SHIFT 0xe
+#define UMCCH3_1_PerfMonCtl2__BankSel__SHIFT 0x10
+#define UMCCH3_1_PerfMonCtl2__VCSel__SHIFT 0x18
+#define UMCCH3_1_PerfMonCtl2__SubChanMask__SHIFT 0x1d
+#define UMCCH3_1_PerfMonCtl2__Enable__SHIFT 0x1f
+#define UMCCH3_1_PerfMonCtl2__EventSelect_MASK 0x000000FFL
+#define UMCCH3_1_PerfMonCtl2__RdWrMask_MASK 0x00000300L
+#define UMCCH3_1_PerfMonCtl2__PriorityMask_MASK 0x00003C00L
+#define UMCCH3_1_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH3_1_PerfMonCtl2__BankSel_MASK 0x00FF0000L
+#define UMCCH3_1_PerfMonCtl2__VCSel_MASK 0x1F000000L
+#define UMCCH3_1_PerfMonCtl2__SubChanMask_MASK 0x60000000L
+#define UMCCH3_1_PerfMonCtl2__Enable_MASK 0x80000000L
+//UMCCH3_1_PerfMonCtr2_Lo
+#define UMCCH3_1_PerfMonCtr2_Lo__Data__SHIFT 0x0
+#define UMCCH3_1_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_1_PerfMonCtr2_Hi
+#define UMCCH3_1_PerfMonCtr2_Hi__Data__SHIFT 0x0
+#define UMCCH3_1_PerfMonCtr2_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_1_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH3_1_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH3_1_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_1_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L
+#define UMCCH3_1_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH3_1_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH3_1_PerfMonCtl3
+#define UMCCH3_1_PerfMonCtl3__EventSelect__SHIFT 0x0
+#define UMCCH3_1_PerfMonCtl3__RdWrMask__SHIFT 0x8
+#define UMCCH3_1_PerfMonCtl3__PriorityMask__SHIFT 0xa
+#define UMCCH3_1_PerfMonCtl3__ReqSizeMask__SHIFT 0xe
+#define UMCCH3_1_PerfMonCtl3__BankSel__SHIFT 0x10
+#define UMCCH3_1_PerfMonCtl3__VCSel__SHIFT 0x18
+#define UMCCH3_1_PerfMonCtl3__SubChanMask__SHIFT 0x1d
+#define UMCCH3_1_PerfMonCtl3__Enable__SHIFT 0x1f
+#define UMCCH3_1_PerfMonCtl3__EventSelect_MASK 0x000000FFL
+#define UMCCH3_1_PerfMonCtl3__RdWrMask_MASK 0x00000300L
+#define UMCCH3_1_PerfMonCtl3__PriorityMask_MASK 0x00003C00L
+#define UMCCH3_1_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH3_1_PerfMonCtl3__BankSel_MASK 0x00FF0000L
+#define UMCCH3_1_PerfMonCtl3__VCSel_MASK 0x1F000000L
+#define UMCCH3_1_PerfMonCtl3__SubChanMask_MASK 0x60000000L
+#define UMCCH3_1_PerfMonCtl3__Enable_MASK 0x80000000L
+//UMCCH3_1_PerfMonCtr3_Lo
+#define UMCCH3_1_PerfMonCtr3_Lo__Data__SHIFT 0x0
+#define UMCCH3_1_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_1_PerfMonCtr3_Hi
+#define UMCCH3_1_PerfMonCtr3_Hi__Data__SHIFT 0x0
+#define UMCCH3_1_PerfMonCtr3_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_1_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH3_1_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH3_1_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_1_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L
+#define UMCCH3_1_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH3_1_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH3_1_PerfMonCtl4
+#define UMCCH3_1_PerfMonCtl4__EventSelect__SHIFT 0x0
+#define UMCCH3_1_PerfMonCtl4__RdWrMask__SHIFT 0x8
+#define UMCCH3_1_PerfMonCtl4__PriorityMask__SHIFT 0xa
+#define UMCCH3_1_PerfMonCtl4__ReqSizeMask__SHIFT 0xe
+#define UMCCH3_1_PerfMonCtl4__BankSel__SHIFT 0x10
+#define UMCCH3_1_PerfMonCtl4__VCSel__SHIFT 0x18
+#define UMCCH3_1_PerfMonCtl4__SubChanMask__SHIFT 0x1d
+#define UMCCH3_1_PerfMonCtl4__Enable__SHIFT 0x1f
+#define UMCCH3_1_PerfMonCtl4__EventSelect_MASK 0x000000FFL
+#define UMCCH3_1_PerfMonCtl4__RdWrMask_MASK 0x00000300L
+#define UMCCH3_1_PerfMonCtl4__PriorityMask_MASK 0x00003C00L
+#define UMCCH3_1_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH3_1_PerfMonCtl4__BankSel_MASK 0x00FF0000L
+#define UMCCH3_1_PerfMonCtl4__VCSel_MASK 0x1F000000L
+#define UMCCH3_1_PerfMonCtl4__SubChanMask_MASK 0x60000000L
+#define UMCCH3_1_PerfMonCtl4__Enable_MASK 0x80000000L
+//UMCCH3_1_PerfMonCtr4_Lo
+#define UMCCH3_1_PerfMonCtr4_Lo__Data__SHIFT 0x0
+#define UMCCH3_1_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_1_PerfMonCtr4_Hi
+#define UMCCH3_1_PerfMonCtr4_Hi__Data__SHIFT 0x0
+#define UMCCH3_1_PerfMonCtr4_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_1_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH3_1_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH3_1_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_1_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L
+#define UMCCH3_1_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH3_1_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH3_1_PerfMonCtl5
+#define UMCCH3_1_PerfMonCtl5__EventSelect__SHIFT 0x0
+#define UMCCH3_1_PerfMonCtl5__RdWrMask__SHIFT 0x8
+#define UMCCH3_1_PerfMonCtl5__PriorityMask__SHIFT 0xa
+#define UMCCH3_1_PerfMonCtl5__ReqSizeMask__SHIFT 0xe
+#define UMCCH3_1_PerfMonCtl5__BankSel__SHIFT 0x10
+#define UMCCH3_1_PerfMonCtl5__VCSel__SHIFT 0x18
+#define UMCCH3_1_PerfMonCtl5__SubChanMask__SHIFT 0x1d
+#define UMCCH3_1_PerfMonCtl5__Enable__SHIFT 0x1f
+#define UMCCH3_1_PerfMonCtl5__EventSelect_MASK 0x000000FFL
+#define UMCCH3_1_PerfMonCtl5__RdWrMask_MASK 0x00000300L
+#define UMCCH3_1_PerfMonCtl5__PriorityMask_MASK 0x00003C00L
+#define UMCCH3_1_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH3_1_PerfMonCtl5__BankSel_MASK 0x00FF0000L
+#define UMCCH3_1_PerfMonCtl5__VCSel_MASK 0x1F000000L
+#define UMCCH3_1_PerfMonCtl5__SubChanMask_MASK 0x60000000L
+#define UMCCH3_1_PerfMonCtl5__Enable_MASK 0x80000000L
+//UMCCH3_1_PerfMonCtr5_Lo
+#define UMCCH3_1_PerfMonCtr5_Lo__Data__SHIFT 0x0
+#define UMCCH3_1_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_1_PerfMonCtr5_Hi
+#define UMCCH3_1_PerfMonCtr5_Hi__Data__SHIFT 0x0
+#define UMCCH3_1_PerfMonCtr5_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_1_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH3_1_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH3_1_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_1_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L
+#define UMCCH3_1_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH3_1_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH3_1_PerfMonCtl6
+#define UMCCH3_1_PerfMonCtl6__EventSelect__SHIFT 0x0
+#define UMCCH3_1_PerfMonCtl6__RdWrMask__SHIFT 0x8
+#define UMCCH3_1_PerfMonCtl6__PriorityMask__SHIFT 0xa
+#define UMCCH3_1_PerfMonCtl6__ReqSizeMask__SHIFT 0xe
+#define UMCCH3_1_PerfMonCtl6__BankSel__SHIFT 0x10
+#define UMCCH3_1_PerfMonCtl6__VCSel__SHIFT 0x18
+#define UMCCH3_1_PerfMonCtl6__SubChanMask__SHIFT 0x1d
+#define UMCCH3_1_PerfMonCtl6__Enable__SHIFT 0x1f
+#define UMCCH3_1_PerfMonCtl6__EventSelect_MASK 0x000000FFL
+#define UMCCH3_1_PerfMonCtl6__RdWrMask_MASK 0x00000300L
+#define UMCCH3_1_PerfMonCtl6__PriorityMask_MASK 0x00003C00L
+#define UMCCH3_1_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH3_1_PerfMonCtl6__BankSel_MASK 0x00FF0000L
+#define UMCCH3_1_PerfMonCtl6__VCSel_MASK 0x1F000000L
+#define UMCCH3_1_PerfMonCtl6__SubChanMask_MASK 0x60000000L
+#define UMCCH3_1_PerfMonCtl6__Enable_MASK 0x80000000L
+//UMCCH3_1_PerfMonCtr6_Lo
+#define UMCCH3_1_PerfMonCtr6_Lo__Data__SHIFT 0x0
+#define UMCCH3_1_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_1_PerfMonCtr6_Hi
+#define UMCCH3_1_PerfMonCtr6_Hi__Data__SHIFT 0x0
+#define UMCCH3_1_PerfMonCtr6_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_1_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH3_1_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH3_1_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_1_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L
+#define UMCCH3_1_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH3_1_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH3_1_PerfMonCtl7
+#define UMCCH3_1_PerfMonCtl7__EventSelect__SHIFT 0x0
+#define UMCCH3_1_PerfMonCtl7__RdWrMask__SHIFT 0x8
+#define UMCCH3_1_PerfMonCtl7__PriorityMask__SHIFT 0xa
+#define UMCCH3_1_PerfMonCtl7__ReqSizeMask__SHIFT 0xe
+#define UMCCH3_1_PerfMonCtl7__BankSel__SHIFT 0x10
+#define UMCCH3_1_PerfMonCtl7__VCSel__SHIFT 0x18
+#define UMCCH3_1_PerfMonCtl7__SubChanMask__SHIFT 0x1d
+#define UMCCH3_1_PerfMonCtl7__Enable__SHIFT 0x1f
+#define UMCCH3_1_PerfMonCtl7__EventSelect_MASK 0x000000FFL
+#define UMCCH3_1_PerfMonCtl7__RdWrMask_MASK 0x00000300L
+#define UMCCH3_1_PerfMonCtl7__PriorityMask_MASK 0x00003C00L
+#define UMCCH3_1_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH3_1_PerfMonCtl7__BankSel_MASK 0x00FF0000L
+#define UMCCH3_1_PerfMonCtl7__VCSel_MASK 0x1F000000L
+#define UMCCH3_1_PerfMonCtl7__SubChanMask_MASK 0x60000000L
+#define UMCCH3_1_PerfMonCtl7__Enable_MASK 0x80000000L
+//UMCCH3_1_PerfMonCtr7_Lo
+#define UMCCH3_1_PerfMonCtr7_Lo__Data__SHIFT 0x0
+#define UMCCH3_1_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_1_PerfMonCtr7_Hi
+#define UMCCH3_1_PerfMonCtr7_Hi__Data__SHIFT 0x0
+#define UMCCH3_1_PerfMonCtr7_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_1_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH3_1_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH3_1_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_1_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L
+#define UMCCH3_1_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH3_1_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH3_1_PerfMonCtl8
+#define UMCCH3_1_PerfMonCtl8__EventSelect__SHIFT 0x0
+#define UMCCH3_1_PerfMonCtl8__RdWrMask__SHIFT 0x8
+#define UMCCH3_1_PerfMonCtl8__PriorityMask__SHIFT 0xa
+#define UMCCH3_1_PerfMonCtl8__ReqSizeMask__SHIFT 0xe
+#define UMCCH3_1_PerfMonCtl8__BankSel__SHIFT 0x10
+#define UMCCH3_1_PerfMonCtl8__VCSel__SHIFT 0x18
+#define UMCCH3_1_PerfMonCtl8__SubChanMask__SHIFT 0x1d
+#define UMCCH3_1_PerfMonCtl8__Enable__SHIFT 0x1f
+#define UMCCH3_1_PerfMonCtl8__EventSelect_MASK 0x000000FFL
+#define UMCCH3_1_PerfMonCtl8__RdWrMask_MASK 0x00000300L
+#define UMCCH3_1_PerfMonCtl8__PriorityMask_MASK 0x00003C00L
+#define UMCCH3_1_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH3_1_PerfMonCtl8__BankSel_MASK 0x00FF0000L
+#define UMCCH3_1_PerfMonCtl8__VCSel_MASK 0x1F000000L
+#define UMCCH3_1_PerfMonCtl8__SubChanMask_MASK 0x60000000L
+#define UMCCH3_1_PerfMonCtl8__Enable_MASK 0x80000000L
+//UMCCH3_1_PerfMonCtr8_Lo
+#define UMCCH3_1_PerfMonCtr8_Lo__Data__SHIFT 0x0
+#define UMCCH3_1_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_1_PerfMonCtr8_Hi
+#define UMCCH3_1_PerfMonCtr8_Hi__Data__SHIFT 0x0
+#define UMCCH3_1_PerfMonCtr8_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_1_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH3_1_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH3_1_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_1_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L
+#define UMCCH3_1_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH3_1_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L
+
+
+// addressBlock: umc_w_phy_umc1_umcch4_umcchdec
+//UMCCH4_1_BaseAddrCS0
+#define UMCCH4_1_BaseAddrCS0__CSEnable__SHIFT 0x0
+#define UMCCH4_1_BaseAddrCS0__BaseAddr__SHIFT 0x1
+#define UMCCH4_1_BaseAddrCS0__CSEnable_MASK 0x00000001L
+#define UMCCH4_1_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL
+//UMCCH4_1_AddrMaskCS01
+#define UMCCH4_1_AddrMaskCS01__AddrMask__SHIFT 0x1
+#define UMCCH4_1_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL
+//UMCCH4_1_AddrSelCS01
+#define UMCCH4_1_AddrSelCS01__BankBit0__SHIFT 0x0
+#define UMCCH4_1_AddrSelCS01__BankBit1__SHIFT 0x4
+#define UMCCH4_1_AddrSelCS01__BankBit2__SHIFT 0x8
+#define UMCCH4_1_AddrSelCS01__BankBit3__SHIFT 0xc
+#define UMCCH4_1_AddrSelCS01__BankBit4__SHIFT 0x10
+#define UMCCH4_1_AddrSelCS01__RowLo__SHIFT 0x18
+#define UMCCH4_1_AddrSelCS01__RowHi__SHIFT 0x1c
+#define UMCCH4_1_AddrSelCS01__BankBit0_MASK 0x0000000FL
+#define UMCCH4_1_AddrSelCS01__BankBit1_MASK 0x000000F0L
+#define UMCCH4_1_AddrSelCS01__BankBit2_MASK 0x00000F00L
+#define UMCCH4_1_AddrSelCS01__BankBit3_MASK 0x0000F000L
+#define UMCCH4_1_AddrSelCS01__BankBit4_MASK 0x001F0000L
+#define UMCCH4_1_AddrSelCS01__RowLo_MASK 0x0F000000L
+#define UMCCH4_1_AddrSelCS01__RowHi_MASK 0xF0000000L
+//UMCCH4_1_AddrHashBank0
+#define UMCCH4_1_AddrHashBank0__XorEnable__SHIFT 0x0
+#define UMCCH4_1_AddrHashBank0__ColXor__SHIFT 0x1
+#define UMCCH4_1_AddrHashBank0__RowXor__SHIFT 0xe
+#define UMCCH4_1_AddrHashBank0__XorEnable_MASK 0x00000001L
+#define UMCCH4_1_AddrHashBank0__ColXor_MASK 0x00003FFEL
+#define UMCCH4_1_AddrHashBank0__RowXor_MASK 0xFFFFC000L
+//UMCCH4_1_AddrHashBank1
+#define UMCCH4_1_AddrHashBank1__XorEnable__SHIFT 0x0
+#define UMCCH4_1_AddrHashBank1__ColXor__SHIFT 0x1
+#define UMCCH4_1_AddrHashBank1__RowXor__SHIFT 0xe
+#define UMCCH4_1_AddrHashBank1__XorEnable_MASK 0x00000001L
+#define UMCCH4_1_AddrHashBank1__ColXor_MASK 0x00003FFEL
+#define UMCCH4_1_AddrHashBank1__RowXor_MASK 0xFFFFC000L
+//UMCCH4_1_AddrHashBank2
+#define UMCCH4_1_AddrHashBank2__XorEnable__SHIFT 0x0
+#define UMCCH4_1_AddrHashBank2__ColXor__SHIFT 0x1
+#define UMCCH4_1_AddrHashBank2__RowXor__SHIFT 0xe
+#define UMCCH4_1_AddrHashBank2__XorEnable_MASK 0x00000001L
+#define UMCCH4_1_AddrHashBank2__ColXor_MASK 0x00003FFEL
+#define UMCCH4_1_AddrHashBank2__RowXor_MASK 0xFFFFC000L
+//UMCCH4_1_AddrHashBank3
+#define UMCCH4_1_AddrHashBank3__XorEnable__SHIFT 0x0
+#define UMCCH4_1_AddrHashBank3__ColXor__SHIFT 0x1
+#define UMCCH4_1_AddrHashBank3__RowXor__SHIFT 0xe
+#define UMCCH4_1_AddrHashBank3__XorEnable_MASK 0x00000001L
+#define UMCCH4_1_AddrHashBank3__ColXor_MASK 0x00003FFEL
+#define UMCCH4_1_AddrHashBank3__RowXor_MASK 0xFFFFC000L
+//UMCCH4_1_AddrHashBank4
+#define UMCCH4_1_AddrHashBank4__XorEnable__SHIFT 0x0
+#define UMCCH4_1_AddrHashBank4__ColXor__SHIFT 0x1
+#define UMCCH4_1_AddrHashBank4__RowXor__SHIFT 0xe
+#define UMCCH4_1_AddrHashBank4__XorEnable_MASK 0x00000001L
+#define UMCCH4_1_AddrHashBank4__ColXor_MASK 0x00003FFEL
+#define UMCCH4_1_AddrHashBank4__RowXor_MASK 0xFFFFC000L
+//UMCCH4_1_AddrHashBank5
+#define UMCCH4_1_AddrHashBank5__XorEnable__SHIFT 0x0
+#define UMCCH4_1_AddrHashBank5__ColXor__SHIFT 0x1
+#define UMCCH4_1_AddrHashBank5__RowXor__SHIFT 0xe
+#define UMCCH4_1_AddrHashBank5__XorEnable_MASK 0x00000001L
+#define UMCCH4_1_AddrHashBank5__ColXor_MASK 0x00003FFEL
+#define UMCCH4_1_AddrHashBank5__RowXor_MASK 0xFFFFC000L
+//UMCCH4_1_EccErrCntSel
+#define UMCCH4_1_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0
+#define UMCCH4_1_EccErrCntSel__EccErrInt__SHIFT 0xc
+#define UMCCH4_1_EccErrCntSel__EccErrCntEn__SHIFT 0xf
+#define UMCCH4_1_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL
+#define UMCCH4_1_EccErrCntSel__EccErrInt_MASK 0x00003000L
+#define UMCCH4_1_EccErrCntSel__EccErrCntEn_MASK 0x00008000L
+//UMCCH4_1_EccErrCnt
+#define UMCCH4_1_EccErrCnt__EccErrCnt__SHIFT 0x0
+#define UMCCH4_1_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL
+//UMCCH4_1_PerfMonCtlClk
+#define UMCCH4_1_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0
+#define UMCCH4_1_PerfMonCtlClk__ClkGate__SHIFT 0x16
+#define UMCCH4_1_PerfMonCtlClk__GlblReset__SHIFT 0x18
+#define UMCCH4_1_PerfMonCtlClk__GlblMonEn__SHIFT 0x19
+#define UMCCH4_1_PerfMonCtlClk__NumCounters__SHIFT 0x1a
+#define UMCCH4_1_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f
+#define UMCCH4_1_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL
+#define UMCCH4_1_PerfMonCtlClk__ClkGate_MASK 0x00400000L
+#define UMCCH4_1_PerfMonCtlClk__GlblReset_MASK 0x01000000L
+#define UMCCH4_1_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L
+#define UMCCH4_1_PerfMonCtlClk__NumCounters_MASK 0x3C000000L
+#define UMCCH4_1_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L
+//UMCCH4_1_PerfMonCtrClk_Lo
+#define UMCCH4_1_PerfMonCtrClk_Lo__Data__SHIFT 0x0
+#define UMCCH4_1_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_1_PerfMonCtrClk_Hi
+#define UMCCH4_1_PerfMonCtrClk_Hi__Data__SHIFT 0x0
+#define UMCCH4_1_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_1_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_1_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L
+//UMCCH4_1_PerfMonCtl1
+#define UMCCH4_1_PerfMonCtl1__EventSelect__SHIFT 0x0
+#define UMCCH4_1_PerfMonCtl1__RdWrMask__SHIFT 0x8
+#define UMCCH4_1_PerfMonCtl1__PriorityMask__SHIFT 0xa
+#define UMCCH4_1_PerfMonCtl1__ReqSizeMask__SHIFT 0xe
+#define UMCCH4_1_PerfMonCtl1__BankSel__SHIFT 0x10
+#define UMCCH4_1_PerfMonCtl1__VCSel__SHIFT 0x18
+#define UMCCH4_1_PerfMonCtl1__SubChanMask__SHIFT 0x1d
+#define UMCCH4_1_PerfMonCtl1__Enable__SHIFT 0x1f
+#define UMCCH4_1_PerfMonCtl1__EventSelect_MASK 0x000000FFL
+#define UMCCH4_1_PerfMonCtl1__RdWrMask_MASK 0x00000300L
+#define UMCCH4_1_PerfMonCtl1__PriorityMask_MASK 0x00003C00L
+#define UMCCH4_1_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH4_1_PerfMonCtl1__BankSel_MASK 0x00FF0000L
+#define UMCCH4_1_PerfMonCtl1__VCSel_MASK 0x1F000000L
+#define UMCCH4_1_PerfMonCtl1__SubChanMask_MASK 0x60000000L
+#define UMCCH4_1_PerfMonCtl1__Enable_MASK 0x80000000L
+//UMCCH4_1_PerfMonCtr1_Lo
+#define UMCCH4_1_PerfMonCtr1_Lo__Data__SHIFT 0x0
+#define UMCCH4_1_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_1_PerfMonCtr1_Hi
+#define UMCCH4_1_PerfMonCtr1_Hi__Data__SHIFT 0x0
+#define UMCCH4_1_PerfMonCtr1_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_1_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH4_1_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH4_1_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_1_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L
+#define UMCCH4_1_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH4_1_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH4_1_PerfMonCtl2
+#define UMCCH4_1_PerfMonCtl2__EventSelect__SHIFT 0x0
+#define UMCCH4_1_PerfMonCtl2__RdWrMask__SHIFT 0x8
+#define UMCCH4_1_PerfMonCtl2__PriorityMask__SHIFT 0xa
+#define UMCCH4_1_PerfMonCtl2__ReqSizeMask__SHIFT 0xe
+#define UMCCH4_1_PerfMonCtl2__BankSel__SHIFT 0x10
+#define UMCCH4_1_PerfMonCtl2__VCSel__SHIFT 0x18
+#define UMCCH4_1_PerfMonCtl2__SubChanMask__SHIFT 0x1d
+#define UMCCH4_1_PerfMonCtl2__Enable__SHIFT 0x1f
+#define UMCCH4_1_PerfMonCtl2__EventSelect_MASK 0x000000FFL
+#define UMCCH4_1_PerfMonCtl2__RdWrMask_MASK 0x00000300L
+#define UMCCH4_1_PerfMonCtl2__PriorityMask_MASK 0x00003C00L
+#define UMCCH4_1_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH4_1_PerfMonCtl2__BankSel_MASK 0x00FF0000L
+#define UMCCH4_1_PerfMonCtl2__VCSel_MASK 0x1F000000L
+#define UMCCH4_1_PerfMonCtl2__SubChanMask_MASK 0x60000000L
+#define UMCCH4_1_PerfMonCtl2__Enable_MASK 0x80000000L
+//UMCCH4_1_PerfMonCtr2_Lo
+#define UMCCH4_1_PerfMonCtr2_Lo__Data__SHIFT 0x0
+#define UMCCH4_1_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_1_PerfMonCtr2_Hi
+#define UMCCH4_1_PerfMonCtr2_Hi__Data__SHIFT 0x0
+#define UMCCH4_1_PerfMonCtr2_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_1_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH4_1_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH4_1_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_1_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L
+#define UMCCH4_1_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH4_1_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH4_1_PerfMonCtl3
+#define UMCCH4_1_PerfMonCtl3__EventSelect__SHIFT 0x0
+#define UMCCH4_1_PerfMonCtl3__RdWrMask__SHIFT 0x8
+#define UMCCH4_1_PerfMonCtl3__PriorityMask__SHIFT 0xa
+#define UMCCH4_1_PerfMonCtl3__ReqSizeMask__SHIFT 0xe
+#define UMCCH4_1_PerfMonCtl3__BankSel__SHIFT 0x10
+#define UMCCH4_1_PerfMonCtl3__VCSel__SHIFT 0x18
+#define UMCCH4_1_PerfMonCtl3__SubChanMask__SHIFT 0x1d
+#define UMCCH4_1_PerfMonCtl3__Enable__SHIFT 0x1f
+#define UMCCH4_1_PerfMonCtl3__EventSelect_MASK 0x000000FFL
+#define UMCCH4_1_PerfMonCtl3__RdWrMask_MASK 0x00000300L
+#define UMCCH4_1_PerfMonCtl3__PriorityMask_MASK 0x00003C00L
+#define UMCCH4_1_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH4_1_PerfMonCtl3__BankSel_MASK 0x00FF0000L
+#define UMCCH4_1_PerfMonCtl3__VCSel_MASK 0x1F000000L
+#define UMCCH4_1_PerfMonCtl3__SubChanMask_MASK 0x60000000L
+#define UMCCH4_1_PerfMonCtl3__Enable_MASK 0x80000000L
+//UMCCH4_1_PerfMonCtr3_Lo
+#define UMCCH4_1_PerfMonCtr3_Lo__Data__SHIFT 0x0
+#define UMCCH4_1_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_1_PerfMonCtr3_Hi
+#define UMCCH4_1_PerfMonCtr3_Hi__Data__SHIFT 0x0
+#define UMCCH4_1_PerfMonCtr3_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_1_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH4_1_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH4_1_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_1_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L
+#define UMCCH4_1_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH4_1_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH4_1_PerfMonCtl4
+#define UMCCH4_1_PerfMonCtl4__EventSelect__SHIFT 0x0
+#define UMCCH4_1_PerfMonCtl4__RdWrMask__SHIFT 0x8
+#define UMCCH4_1_PerfMonCtl4__PriorityMask__SHIFT 0xa
+#define UMCCH4_1_PerfMonCtl4__ReqSizeMask__SHIFT 0xe
+#define UMCCH4_1_PerfMonCtl4__BankSel__SHIFT 0x10
+#define UMCCH4_1_PerfMonCtl4__VCSel__SHIFT 0x18
+#define UMCCH4_1_PerfMonCtl4__SubChanMask__SHIFT 0x1d
+#define UMCCH4_1_PerfMonCtl4__Enable__SHIFT 0x1f
+#define UMCCH4_1_PerfMonCtl4__EventSelect_MASK 0x000000FFL
+#define UMCCH4_1_PerfMonCtl4__RdWrMask_MASK 0x00000300L
+#define UMCCH4_1_PerfMonCtl4__PriorityMask_MASK 0x00003C00L
+#define UMCCH4_1_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH4_1_PerfMonCtl4__BankSel_MASK 0x00FF0000L
+#define UMCCH4_1_PerfMonCtl4__VCSel_MASK 0x1F000000L
+#define UMCCH4_1_PerfMonCtl4__SubChanMask_MASK 0x60000000L
+#define UMCCH4_1_PerfMonCtl4__Enable_MASK 0x80000000L
+//UMCCH4_1_PerfMonCtr4_Lo
+#define UMCCH4_1_PerfMonCtr4_Lo__Data__SHIFT 0x0
+#define UMCCH4_1_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_1_PerfMonCtr4_Hi
+#define UMCCH4_1_PerfMonCtr4_Hi__Data__SHIFT 0x0
+#define UMCCH4_1_PerfMonCtr4_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_1_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH4_1_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH4_1_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_1_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L
+#define UMCCH4_1_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH4_1_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH4_1_PerfMonCtl5
+#define UMCCH4_1_PerfMonCtl5__EventSelect__SHIFT 0x0
+#define UMCCH4_1_PerfMonCtl5__RdWrMask__SHIFT 0x8
+#define UMCCH4_1_PerfMonCtl5__PriorityMask__SHIFT 0xa
+#define UMCCH4_1_PerfMonCtl5__ReqSizeMask__SHIFT 0xe
+#define UMCCH4_1_PerfMonCtl5__BankSel__SHIFT 0x10
+#define UMCCH4_1_PerfMonCtl5__VCSel__SHIFT 0x18
+#define UMCCH4_1_PerfMonCtl5__SubChanMask__SHIFT 0x1d
+#define UMCCH4_1_PerfMonCtl5__Enable__SHIFT 0x1f
+#define UMCCH4_1_PerfMonCtl5__EventSelect_MASK 0x000000FFL
+#define UMCCH4_1_PerfMonCtl5__RdWrMask_MASK 0x00000300L
+#define UMCCH4_1_PerfMonCtl5__PriorityMask_MASK 0x00003C00L
+#define UMCCH4_1_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH4_1_PerfMonCtl5__BankSel_MASK 0x00FF0000L
+#define UMCCH4_1_PerfMonCtl5__VCSel_MASK 0x1F000000L
+#define UMCCH4_1_PerfMonCtl5__SubChanMask_MASK 0x60000000L
+#define UMCCH4_1_PerfMonCtl5__Enable_MASK 0x80000000L
+//UMCCH4_1_PerfMonCtr5_Lo
+#define UMCCH4_1_PerfMonCtr5_Lo__Data__SHIFT 0x0
+#define UMCCH4_1_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_1_PerfMonCtr5_Hi
+#define UMCCH4_1_PerfMonCtr5_Hi__Data__SHIFT 0x0
+#define UMCCH4_1_PerfMonCtr5_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_1_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH4_1_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH4_1_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_1_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L
+#define UMCCH4_1_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH4_1_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH4_1_PerfMonCtl6
+#define UMCCH4_1_PerfMonCtl6__EventSelect__SHIFT 0x0
+#define UMCCH4_1_PerfMonCtl6__RdWrMask__SHIFT 0x8
+#define UMCCH4_1_PerfMonCtl6__PriorityMask__SHIFT 0xa
+#define UMCCH4_1_PerfMonCtl6__ReqSizeMask__SHIFT 0xe
+#define UMCCH4_1_PerfMonCtl6__BankSel__SHIFT 0x10
+#define UMCCH4_1_PerfMonCtl6__VCSel__SHIFT 0x18
+#define UMCCH4_1_PerfMonCtl6__SubChanMask__SHIFT 0x1d
+#define UMCCH4_1_PerfMonCtl6__Enable__SHIFT 0x1f
+#define UMCCH4_1_PerfMonCtl6__EventSelect_MASK 0x000000FFL
+#define UMCCH4_1_PerfMonCtl6__RdWrMask_MASK 0x00000300L
+#define UMCCH4_1_PerfMonCtl6__PriorityMask_MASK 0x00003C00L
+#define UMCCH4_1_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH4_1_PerfMonCtl6__BankSel_MASK 0x00FF0000L
+#define UMCCH4_1_PerfMonCtl6__VCSel_MASK 0x1F000000L
+#define UMCCH4_1_PerfMonCtl6__SubChanMask_MASK 0x60000000L
+#define UMCCH4_1_PerfMonCtl6__Enable_MASK 0x80000000L
+//UMCCH4_1_PerfMonCtr6_Lo
+#define UMCCH4_1_PerfMonCtr6_Lo__Data__SHIFT 0x0
+#define UMCCH4_1_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_1_PerfMonCtr6_Hi
+#define UMCCH4_1_PerfMonCtr6_Hi__Data__SHIFT 0x0
+#define UMCCH4_1_PerfMonCtr6_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_1_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH4_1_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH4_1_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_1_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L
+#define UMCCH4_1_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH4_1_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH4_1_PerfMonCtl7
+#define UMCCH4_1_PerfMonCtl7__EventSelect__SHIFT 0x0
+#define UMCCH4_1_PerfMonCtl7__RdWrMask__SHIFT 0x8
+#define UMCCH4_1_PerfMonCtl7__PriorityMask__SHIFT 0xa
+#define UMCCH4_1_PerfMonCtl7__ReqSizeMask__SHIFT 0xe
+#define UMCCH4_1_PerfMonCtl7__BankSel__SHIFT 0x10
+#define UMCCH4_1_PerfMonCtl7__VCSel__SHIFT 0x18
+#define UMCCH4_1_PerfMonCtl7__SubChanMask__SHIFT 0x1d
+#define UMCCH4_1_PerfMonCtl7__Enable__SHIFT 0x1f
+#define UMCCH4_1_PerfMonCtl7__EventSelect_MASK 0x000000FFL
+#define UMCCH4_1_PerfMonCtl7__RdWrMask_MASK 0x00000300L
+#define UMCCH4_1_PerfMonCtl7__PriorityMask_MASK 0x00003C00L
+#define UMCCH4_1_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH4_1_PerfMonCtl7__BankSel_MASK 0x00FF0000L
+#define UMCCH4_1_PerfMonCtl7__VCSel_MASK 0x1F000000L
+#define UMCCH4_1_PerfMonCtl7__SubChanMask_MASK 0x60000000L
+#define UMCCH4_1_PerfMonCtl7__Enable_MASK 0x80000000L
+//UMCCH4_1_PerfMonCtr7_Lo
+#define UMCCH4_1_PerfMonCtr7_Lo__Data__SHIFT 0x0
+#define UMCCH4_1_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_1_PerfMonCtr7_Hi
+#define UMCCH4_1_PerfMonCtr7_Hi__Data__SHIFT 0x0
+#define UMCCH4_1_PerfMonCtr7_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_1_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH4_1_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH4_1_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_1_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L
+#define UMCCH4_1_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH4_1_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH4_1_PerfMonCtl8
+#define UMCCH4_1_PerfMonCtl8__EventSelect__SHIFT 0x0
+#define UMCCH4_1_PerfMonCtl8__RdWrMask__SHIFT 0x8
+#define UMCCH4_1_PerfMonCtl8__PriorityMask__SHIFT 0xa
+#define UMCCH4_1_PerfMonCtl8__ReqSizeMask__SHIFT 0xe
+#define UMCCH4_1_PerfMonCtl8__BankSel__SHIFT 0x10
+#define UMCCH4_1_PerfMonCtl8__VCSel__SHIFT 0x18
+#define UMCCH4_1_PerfMonCtl8__SubChanMask__SHIFT 0x1d
+#define UMCCH4_1_PerfMonCtl8__Enable__SHIFT 0x1f
+#define UMCCH4_1_PerfMonCtl8__EventSelect_MASK 0x000000FFL
+#define UMCCH4_1_PerfMonCtl8__RdWrMask_MASK 0x00000300L
+#define UMCCH4_1_PerfMonCtl8__PriorityMask_MASK 0x00003C00L
+#define UMCCH4_1_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH4_1_PerfMonCtl8__BankSel_MASK 0x00FF0000L
+#define UMCCH4_1_PerfMonCtl8__VCSel_MASK 0x1F000000L
+#define UMCCH4_1_PerfMonCtl8__SubChanMask_MASK 0x60000000L
+#define UMCCH4_1_PerfMonCtl8__Enable_MASK 0x80000000L
+//UMCCH4_1_PerfMonCtr8_Lo
+#define UMCCH4_1_PerfMonCtr8_Lo__Data__SHIFT 0x0
+#define UMCCH4_1_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_1_PerfMonCtr8_Hi
+#define UMCCH4_1_PerfMonCtr8_Hi__Data__SHIFT 0x0
+#define UMCCH4_1_PerfMonCtr8_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_1_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH4_1_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH4_1_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_1_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L
+#define UMCCH4_1_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH4_1_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L
+
+
+// addressBlock: umc_w_phy_umc1_umcch5_umcchdec
+//UMCCH5_1_BaseAddrCS0
+#define UMCCH5_1_BaseAddrCS0__CSEnable__SHIFT 0x0
+#define UMCCH5_1_BaseAddrCS0__BaseAddr__SHIFT 0x1
+#define UMCCH5_1_BaseAddrCS0__CSEnable_MASK 0x00000001L
+#define UMCCH5_1_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL
+//UMCCH5_1_AddrMaskCS01
+#define UMCCH5_1_AddrMaskCS01__AddrMask__SHIFT 0x1
+#define UMCCH5_1_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL
+//UMCCH5_1_AddrSelCS01
+#define UMCCH5_1_AddrSelCS01__BankBit0__SHIFT 0x0
+#define UMCCH5_1_AddrSelCS01__BankBit1__SHIFT 0x4
+#define UMCCH5_1_AddrSelCS01__BankBit2__SHIFT 0x8
+#define UMCCH5_1_AddrSelCS01__BankBit3__SHIFT 0xc
+#define UMCCH5_1_AddrSelCS01__BankBit4__SHIFT 0x10
+#define UMCCH5_1_AddrSelCS01__RowLo__SHIFT 0x18
+#define UMCCH5_1_AddrSelCS01__RowHi__SHIFT 0x1c
+#define UMCCH5_1_AddrSelCS01__BankBit0_MASK 0x0000000FL
+#define UMCCH5_1_AddrSelCS01__BankBit1_MASK 0x000000F0L
+#define UMCCH5_1_AddrSelCS01__BankBit2_MASK 0x00000F00L
+#define UMCCH5_1_AddrSelCS01__BankBit3_MASK 0x0000F000L
+#define UMCCH5_1_AddrSelCS01__BankBit4_MASK 0x001F0000L
+#define UMCCH5_1_AddrSelCS01__RowLo_MASK 0x0F000000L
+#define UMCCH5_1_AddrSelCS01__RowHi_MASK 0xF0000000L
+//UMCCH5_1_AddrHashBank0
+#define UMCCH5_1_AddrHashBank0__XorEnable__SHIFT 0x0
+#define UMCCH5_1_AddrHashBank0__ColXor__SHIFT 0x1
+#define UMCCH5_1_AddrHashBank0__RowXor__SHIFT 0xe
+#define UMCCH5_1_AddrHashBank0__XorEnable_MASK 0x00000001L
+#define UMCCH5_1_AddrHashBank0__ColXor_MASK 0x00003FFEL
+#define UMCCH5_1_AddrHashBank0__RowXor_MASK 0xFFFFC000L
+//UMCCH5_1_AddrHashBank1
+#define UMCCH5_1_AddrHashBank1__XorEnable__SHIFT 0x0
+#define UMCCH5_1_AddrHashBank1__ColXor__SHIFT 0x1
+#define UMCCH5_1_AddrHashBank1__RowXor__SHIFT 0xe
+#define UMCCH5_1_AddrHashBank1__XorEnable_MASK 0x00000001L
+#define UMCCH5_1_AddrHashBank1__ColXor_MASK 0x00003FFEL
+#define UMCCH5_1_AddrHashBank1__RowXor_MASK 0xFFFFC000L
+//UMCCH5_1_AddrHashBank2
+#define UMCCH5_1_AddrHashBank2__XorEnable__SHIFT 0x0
+#define UMCCH5_1_AddrHashBank2__ColXor__SHIFT 0x1
+#define UMCCH5_1_AddrHashBank2__RowXor__SHIFT 0xe
+#define UMCCH5_1_AddrHashBank2__XorEnable_MASK 0x00000001L
+#define UMCCH5_1_AddrHashBank2__ColXor_MASK 0x00003FFEL
+#define UMCCH5_1_AddrHashBank2__RowXor_MASK 0xFFFFC000L
+//UMCCH5_1_AddrHashBank3
+#define UMCCH5_1_AddrHashBank3__XorEnable__SHIFT 0x0
+#define UMCCH5_1_AddrHashBank3__ColXor__SHIFT 0x1
+#define UMCCH5_1_AddrHashBank3__RowXor__SHIFT 0xe
+#define UMCCH5_1_AddrHashBank3__XorEnable_MASK 0x00000001L
+#define UMCCH5_1_AddrHashBank3__ColXor_MASK 0x00003FFEL
+#define UMCCH5_1_AddrHashBank3__RowXor_MASK 0xFFFFC000L
+//UMCCH5_1_AddrHashBank4
+#define UMCCH5_1_AddrHashBank4__XorEnable__SHIFT 0x0
+#define UMCCH5_1_AddrHashBank4__ColXor__SHIFT 0x1
+#define UMCCH5_1_AddrHashBank4__RowXor__SHIFT 0xe
+#define UMCCH5_1_AddrHashBank4__XorEnable_MASK 0x00000001L
+#define UMCCH5_1_AddrHashBank4__ColXor_MASK 0x00003FFEL
+#define UMCCH5_1_AddrHashBank4__RowXor_MASK 0xFFFFC000L
+//UMCCH5_1_AddrHashBank5
+#define UMCCH5_1_AddrHashBank5__XorEnable__SHIFT 0x0
+#define UMCCH5_1_AddrHashBank5__ColXor__SHIFT 0x1
+#define UMCCH5_1_AddrHashBank5__RowXor__SHIFT 0xe
+#define UMCCH5_1_AddrHashBank5__XorEnable_MASK 0x00000001L
+#define UMCCH5_1_AddrHashBank5__ColXor_MASK 0x00003FFEL
+#define UMCCH5_1_AddrHashBank5__RowXor_MASK 0xFFFFC000L
+//UMCCH5_1_EccErrCntSel
+#define UMCCH5_1_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0
+#define UMCCH5_1_EccErrCntSel__EccErrInt__SHIFT 0xc
+#define UMCCH5_1_EccErrCntSel__EccErrCntEn__SHIFT 0xf
+#define UMCCH5_1_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL
+#define UMCCH5_1_EccErrCntSel__EccErrInt_MASK 0x00003000L
+#define UMCCH5_1_EccErrCntSel__EccErrCntEn_MASK 0x00008000L
+//UMCCH5_1_EccErrCnt
+#define UMCCH5_1_EccErrCnt__EccErrCnt__SHIFT 0x0
+#define UMCCH5_1_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL
+//UMCCH5_1_PerfMonCtlClk
+#define UMCCH5_1_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0
+#define UMCCH5_1_PerfMonCtlClk__ClkGate__SHIFT 0x16
+#define UMCCH5_1_PerfMonCtlClk__GlblReset__SHIFT 0x18
+#define UMCCH5_1_PerfMonCtlClk__GlblMonEn__SHIFT 0x19
+#define UMCCH5_1_PerfMonCtlClk__NumCounters__SHIFT 0x1a
+#define UMCCH5_1_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f
+#define UMCCH5_1_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL
+#define UMCCH5_1_PerfMonCtlClk__ClkGate_MASK 0x00400000L
+#define UMCCH5_1_PerfMonCtlClk__GlblReset_MASK 0x01000000L
+#define UMCCH5_1_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L
+#define UMCCH5_1_PerfMonCtlClk__NumCounters_MASK 0x3C000000L
+#define UMCCH5_1_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L
+//UMCCH5_1_PerfMonCtrClk_Lo
+#define UMCCH5_1_PerfMonCtrClk_Lo__Data__SHIFT 0x0
+#define UMCCH5_1_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_1_PerfMonCtrClk_Hi
+#define UMCCH5_1_PerfMonCtrClk_Hi__Data__SHIFT 0x0
+#define UMCCH5_1_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_1_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_1_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L
+//UMCCH5_1_PerfMonCtl1
+#define UMCCH5_1_PerfMonCtl1__EventSelect__SHIFT 0x0
+#define UMCCH5_1_PerfMonCtl1__RdWrMask__SHIFT 0x8
+#define UMCCH5_1_PerfMonCtl1__PriorityMask__SHIFT 0xa
+#define UMCCH5_1_PerfMonCtl1__ReqSizeMask__SHIFT 0xe
+#define UMCCH5_1_PerfMonCtl1__BankSel__SHIFT 0x10
+#define UMCCH5_1_PerfMonCtl1__VCSel__SHIFT 0x18
+#define UMCCH5_1_PerfMonCtl1__SubChanMask__SHIFT 0x1d
+#define UMCCH5_1_PerfMonCtl1__Enable__SHIFT 0x1f
+#define UMCCH5_1_PerfMonCtl1__EventSelect_MASK 0x000000FFL
+#define UMCCH5_1_PerfMonCtl1__RdWrMask_MASK 0x00000300L
+#define UMCCH5_1_PerfMonCtl1__PriorityMask_MASK 0x00003C00L
+#define UMCCH5_1_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH5_1_PerfMonCtl1__BankSel_MASK 0x00FF0000L
+#define UMCCH5_1_PerfMonCtl1__VCSel_MASK 0x1F000000L
+#define UMCCH5_1_PerfMonCtl1__SubChanMask_MASK 0x60000000L
+#define UMCCH5_1_PerfMonCtl1__Enable_MASK 0x80000000L
+//UMCCH5_1_PerfMonCtr1_Lo
+#define UMCCH5_1_PerfMonCtr1_Lo__Data__SHIFT 0x0
+#define UMCCH5_1_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_1_PerfMonCtr1_Hi
+#define UMCCH5_1_PerfMonCtr1_Hi__Data__SHIFT 0x0
+#define UMCCH5_1_PerfMonCtr1_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_1_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH5_1_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH5_1_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_1_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L
+#define UMCCH5_1_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH5_1_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH5_1_PerfMonCtl2
+#define UMCCH5_1_PerfMonCtl2__EventSelect__SHIFT 0x0
+#define UMCCH5_1_PerfMonCtl2__RdWrMask__SHIFT 0x8
+#define UMCCH5_1_PerfMonCtl2__PriorityMask__SHIFT 0xa
+#define UMCCH5_1_PerfMonCtl2__ReqSizeMask__SHIFT 0xe
+#define UMCCH5_1_PerfMonCtl2__BankSel__SHIFT 0x10
+#define UMCCH5_1_PerfMonCtl2__VCSel__SHIFT 0x18
+#define UMCCH5_1_PerfMonCtl2__SubChanMask__SHIFT 0x1d
+#define UMCCH5_1_PerfMonCtl2__Enable__SHIFT 0x1f
+#define UMCCH5_1_PerfMonCtl2__EventSelect_MASK 0x000000FFL
+#define UMCCH5_1_PerfMonCtl2__RdWrMask_MASK 0x00000300L
+#define UMCCH5_1_PerfMonCtl2__PriorityMask_MASK 0x00003C00L
+#define UMCCH5_1_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH5_1_PerfMonCtl2__BankSel_MASK 0x00FF0000L
+#define UMCCH5_1_PerfMonCtl2__VCSel_MASK 0x1F000000L
+#define UMCCH5_1_PerfMonCtl2__SubChanMask_MASK 0x60000000L
+#define UMCCH5_1_PerfMonCtl2__Enable_MASK 0x80000000L
+//UMCCH5_1_PerfMonCtr2_Lo
+#define UMCCH5_1_PerfMonCtr2_Lo__Data__SHIFT 0x0
+#define UMCCH5_1_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_1_PerfMonCtr2_Hi
+#define UMCCH5_1_PerfMonCtr2_Hi__Data__SHIFT 0x0
+#define UMCCH5_1_PerfMonCtr2_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_1_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH5_1_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH5_1_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_1_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L
+#define UMCCH5_1_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH5_1_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH5_1_PerfMonCtl3
+#define UMCCH5_1_PerfMonCtl3__EventSelect__SHIFT 0x0
+#define UMCCH5_1_PerfMonCtl3__RdWrMask__SHIFT 0x8
+#define UMCCH5_1_PerfMonCtl3__PriorityMask__SHIFT 0xa
+#define UMCCH5_1_PerfMonCtl3__ReqSizeMask__SHIFT 0xe
+#define UMCCH5_1_PerfMonCtl3__BankSel__SHIFT 0x10
+#define UMCCH5_1_PerfMonCtl3__VCSel__SHIFT 0x18
+#define UMCCH5_1_PerfMonCtl3__SubChanMask__SHIFT 0x1d
+#define UMCCH5_1_PerfMonCtl3__Enable__SHIFT 0x1f
+#define UMCCH5_1_PerfMonCtl3__EventSelect_MASK 0x000000FFL
+#define UMCCH5_1_PerfMonCtl3__RdWrMask_MASK 0x00000300L
+#define UMCCH5_1_PerfMonCtl3__PriorityMask_MASK 0x00003C00L
+#define UMCCH5_1_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH5_1_PerfMonCtl3__BankSel_MASK 0x00FF0000L
+#define UMCCH5_1_PerfMonCtl3__VCSel_MASK 0x1F000000L
+#define UMCCH5_1_PerfMonCtl3__SubChanMask_MASK 0x60000000L
+#define UMCCH5_1_PerfMonCtl3__Enable_MASK 0x80000000L
+//UMCCH5_1_PerfMonCtr3_Lo
+#define UMCCH5_1_PerfMonCtr3_Lo__Data__SHIFT 0x0
+#define UMCCH5_1_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_1_PerfMonCtr3_Hi
+#define UMCCH5_1_PerfMonCtr3_Hi__Data__SHIFT 0x0
+#define UMCCH5_1_PerfMonCtr3_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_1_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH5_1_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH5_1_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_1_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L
+#define UMCCH5_1_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH5_1_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH5_1_PerfMonCtl4
+#define UMCCH5_1_PerfMonCtl4__EventSelect__SHIFT 0x0
+#define UMCCH5_1_PerfMonCtl4__RdWrMask__SHIFT 0x8
+#define UMCCH5_1_PerfMonCtl4__PriorityMask__SHIFT 0xa
+#define UMCCH5_1_PerfMonCtl4__ReqSizeMask__SHIFT 0xe
+#define UMCCH5_1_PerfMonCtl4__BankSel__SHIFT 0x10
+#define UMCCH5_1_PerfMonCtl4__VCSel__SHIFT 0x18
+#define UMCCH5_1_PerfMonCtl4__SubChanMask__SHIFT 0x1d
+#define UMCCH5_1_PerfMonCtl4__Enable__SHIFT 0x1f
+#define UMCCH5_1_PerfMonCtl4__EventSelect_MASK 0x000000FFL
+#define UMCCH5_1_PerfMonCtl4__RdWrMask_MASK 0x00000300L
+#define UMCCH5_1_PerfMonCtl4__PriorityMask_MASK 0x00003C00L
+#define UMCCH5_1_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH5_1_PerfMonCtl4__BankSel_MASK 0x00FF0000L
+#define UMCCH5_1_PerfMonCtl4__VCSel_MASK 0x1F000000L
+#define UMCCH5_1_PerfMonCtl4__SubChanMask_MASK 0x60000000L
+#define UMCCH5_1_PerfMonCtl4__Enable_MASK 0x80000000L
+//UMCCH5_1_PerfMonCtr4_Lo
+#define UMCCH5_1_PerfMonCtr4_Lo__Data__SHIFT 0x0
+#define UMCCH5_1_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_1_PerfMonCtr4_Hi
+#define UMCCH5_1_PerfMonCtr4_Hi__Data__SHIFT 0x0
+#define UMCCH5_1_PerfMonCtr4_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_1_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH5_1_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH5_1_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_1_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L
+#define UMCCH5_1_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH5_1_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH5_1_PerfMonCtl5
+#define UMCCH5_1_PerfMonCtl5__EventSelect__SHIFT 0x0
+#define UMCCH5_1_PerfMonCtl5__RdWrMask__SHIFT 0x8
+#define UMCCH5_1_PerfMonCtl5__PriorityMask__SHIFT 0xa
+#define UMCCH5_1_PerfMonCtl5__ReqSizeMask__SHIFT 0xe
+#define UMCCH5_1_PerfMonCtl5__BankSel__SHIFT 0x10
+#define UMCCH5_1_PerfMonCtl5__VCSel__SHIFT 0x18
+#define UMCCH5_1_PerfMonCtl5__SubChanMask__SHIFT 0x1d
+#define UMCCH5_1_PerfMonCtl5__Enable__SHIFT 0x1f
+#define UMCCH5_1_PerfMonCtl5__EventSelect_MASK 0x000000FFL
+#define UMCCH5_1_PerfMonCtl5__RdWrMask_MASK 0x00000300L
+#define UMCCH5_1_PerfMonCtl5__PriorityMask_MASK 0x00003C00L
+#define UMCCH5_1_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH5_1_PerfMonCtl5__BankSel_MASK 0x00FF0000L
+#define UMCCH5_1_PerfMonCtl5__VCSel_MASK 0x1F000000L
+#define UMCCH5_1_PerfMonCtl5__SubChanMask_MASK 0x60000000L
+#define UMCCH5_1_PerfMonCtl5__Enable_MASK 0x80000000L
+//UMCCH5_1_PerfMonCtr5_Lo
+#define UMCCH5_1_PerfMonCtr5_Lo__Data__SHIFT 0x0
+#define UMCCH5_1_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_1_PerfMonCtr5_Hi
+#define UMCCH5_1_PerfMonCtr5_Hi__Data__SHIFT 0x0
+#define UMCCH5_1_PerfMonCtr5_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_1_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH5_1_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH5_1_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_1_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L
+#define UMCCH5_1_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH5_1_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH5_1_PerfMonCtl6
+#define UMCCH5_1_PerfMonCtl6__EventSelect__SHIFT 0x0
+#define UMCCH5_1_PerfMonCtl6__RdWrMask__SHIFT 0x8
+#define UMCCH5_1_PerfMonCtl6__PriorityMask__SHIFT 0xa
+#define UMCCH5_1_PerfMonCtl6__ReqSizeMask__SHIFT 0xe
+#define UMCCH5_1_PerfMonCtl6__BankSel__SHIFT 0x10
+#define UMCCH5_1_PerfMonCtl6__VCSel__SHIFT 0x18
+#define UMCCH5_1_PerfMonCtl6__SubChanMask__SHIFT 0x1d
+#define UMCCH5_1_PerfMonCtl6__Enable__SHIFT 0x1f
+#define UMCCH5_1_PerfMonCtl6__EventSelect_MASK 0x000000FFL
+#define UMCCH5_1_PerfMonCtl6__RdWrMask_MASK 0x00000300L
+#define UMCCH5_1_PerfMonCtl6__PriorityMask_MASK 0x00003C00L
+#define UMCCH5_1_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH5_1_PerfMonCtl6__BankSel_MASK 0x00FF0000L
+#define UMCCH5_1_PerfMonCtl6__VCSel_MASK 0x1F000000L
+#define UMCCH5_1_PerfMonCtl6__SubChanMask_MASK 0x60000000L
+#define UMCCH5_1_PerfMonCtl6__Enable_MASK 0x80000000L
+//UMCCH5_1_PerfMonCtr6_Lo
+#define UMCCH5_1_PerfMonCtr6_Lo__Data__SHIFT 0x0
+#define UMCCH5_1_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_1_PerfMonCtr6_Hi
+#define UMCCH5_1_PerfMonCtr6_Hi__Data__SHIFT 0x0
+#define UMCCH5_1_PerfMonCtr6_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_1_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH5_1_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH5_1_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_1_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L
+#define UMCCH5_1_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH5_1_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH5_1_PerfMonCtl7
+#define UMCCH5_1_PerfMonCtl7__EventSelect__SHIFT 0x0
+#define UMCCH5_1_PerfMonCtl7__RdWrMask__SHIFT 0x8
+#define UMCCH5_1_PerfMonCtl7__PriorityMask__SHIFT 0xa
+#define UMCCH5_1_PerfMonCtl7__ReqSizeMask__SHIFT 0xe
+#define UMCCH5_1_PerfMonCtl7__BankSel__SHIFT 0x10
+#define UMCCH5_1_PerfMonCtl7__VCSel__SHIFT 0x18
+#define UMCCH5_1_PerfMonCtl7__SubChanMask__SHIFT 0x1d
+#define UMCCH5_1_PerfMonCtl7__Enable__SHIFT 0x1f
+#define UMCCH5_1_PerfMonCtl7__EventSelect_MASK 0x000000FFL
+#define UMCCH5_1_PerfMonCtl7__RdWrMask_MASK 0x00000300L
+#define UMCCH5_1_PerfMonCtl7__PriorityMask_MASK 0x00003C00L
+#define UMCCH5_1_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH5_1_PerfMonCtl7__BankSel_MASK 0x00FF0000L
+#define UMCCH5_1_PerfMonCtl7__VCSel_MASK 0x1F000000L
+#define UMCCH5_1_PerfMonCtl7__SubChanMask_MASK 0x60000000L
+#define UMCCH5_1_PerfMonCtl7__Enable_MASK 0x80000000L
+//UMCCH5_1_PerfMonCtr7_Lo
+#define UMCCH5_1_PerfMonCtr7_Lo__Data__SHIFT 0x0
+#define UMCCH5_1_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_1_PerfMonCtr7_Hi
+#define UMCCH5_1_PerfMonCtr7_Hi__Data__SHIFT 0x0
+#define UMCCH5_1_PerfMonCtr7_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_1_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH5_1_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH5_1_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_1_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L
+#define UMCCH5_1_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH5_1_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH5_1_PerfMonCtl8
+#define UMCCH5_1_PerfMonCtl8__EventSelect__SHIFT 0x0
+#define UMCCH5_1_PerfMonCtl8__RdWrMask__SHIFT 0x8
+#define UMCCH5_1_PerfMonCtl8__PriorityMask__SHIFT 0xa
+#define UMCCH5_1_PerfMonCtl8__ReqSizeMask__SHIFT 0xe
+#define UMCCH5_1_PerfMonCtl8__BankSel__SHIFT 0x10
+#define UMCCH5_1_PerfMonCtl8__VCSel__SHIFT 0x18
+#define UMCCH5_1_PerfMonCtl8__SubChanMask__SHIFT 0x1d
+#define UMCCH5_1_PerfMonCtl8__Enable__SHIFT 0x1f
+#define UMCCH5_1_PerfMonCtl8__EventSelect_MASK 0x000000FFL
+#define UMCCH5_1_PerfMonCtl8__RdWrMask_MASK 0x00000300L
+#define UMCCH5_1_PerfMonCtl8__PriorityMask_MASK 0x00003C00L
+#define UMCCH5_1_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH5_1_PerfMonCtl8__BankSel_MASK 0x00FF0000L
+#define UMCCH5_1_PerfMonCtl8__VCSel_MASK 0x1F000000L
+#define UMCCH5_1_PerfMonCtl8__SubChanMask_MASK 0x60000000L
+#define UMCCH5_1_PerfMonCtl8__Enable_MASK 0x80000000L
+//UMCCH5_1_PerfMonCtr8_Lo
+#define UMCCH5_1_PerfMonCtr8_Lo__Data__SHIFT 0x0
+#define UMCCH5_1_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_1_PerfMonCtr8_Hi
+#define UMCCH5_1_PerfMonCtr8_Hi__Data__SHIFT 0x0
+#define UMCCH5_1_PerfMonCtr8_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_1_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH5_1_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH5_1_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_1_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L
+#define UMCCH5_1_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH5_1_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L
+
+
+// addressBlock: umc_w_phy_umc1_umcch6_umcchdec
+//UMCCH6_1_BaseAddrCS0
+#define UMCCH6_1_BaseAddrCS0__CSEnable__SHIFT 0x0
+#define UMCCH6_1_BaseAddrCS0__BaseAddr__SHIFT 0x1
+#define UMCCH6_1_BaseAddrCS0__CSEnable_MASK 0x00000001L
+#define UMCCH6_1_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL
+//UMCCH6_1_AddrMaskCS01
+#define UMCCH6_1_AddrMaskCS01__AddrMask__SHIFT 0x1
+#define UMCCH6_1_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL
+//UMCCH6_1_AddrSelCS01
+#define UMCCH6_1_AddrSelCS01__BankBit0__SHIFT 0x0
+#define UMCCH6_1_AddrSelCS01__BankBit1__SHIFT 0x4
+#define UMCCH6_1_AddrSelCS01__BankBit2__SHIFT 0x8
+#define UMCCH6_1_AddrSelCS01__BankBit3__SHIFT 0xc
+#define UMCCH6_1_AddrSelCS01__BankBit4__SHIFT 0x10
+#define UMCCH6_1_AddrSelCS01__RowLo__SHIFT 0x18
+#define UMCCH6_1_AddrSelCS01__RowHi__SHIFT 0x1c
+#define UMCCH6_1_AddrSelCS01__BankBit0_MASK 0x0000000FL
+#define UMCCH6_1_AddrSelCS01__BankBit1_MASK 0x000000F0L
+#define UMCCH6_1_AddrSelCS01__BankBit2_MASK 0x00000F00L
+#define UMCCH6_1_AddrSelCS01__BankBit3_MASK 0x0000F000L
+#define UMCCH6_1_AddrSelCS01__BankBit4_MASK 0x001F0000L
+#define UMCCH6_1_AddrSelCS01__RowLo_MASK 0x0F000000L
+#define UMCCH6_1_AddrSelCS01__RowHi_MASK 0xF0000000L
+//UMCCH6_1_AddrHashBank0
+#define UMCCH6_1_AddrHashBank0__XorEnable__SHIFT 0x0
+#define UMCCH6_1_AddrHashBank0__ColXor__SHIFT 0x1
+#define UMCCH6_1_AddrHashBank0__RowXor__SHIFT 0xe
+#define UMCCH6_1_AddrHashBank0__XorEnable_MASK 0x00000001L
+#define UMCCH6_1_AddrHashBank0__ColXor_MASK 0x00003FFEL
+#define UMCCH6_1_AddrHashBank0__RowXor_MASK 0xFFFFC000L
+//UMCCH6_1_AddrHashBank1
+#define UMCCH6_1_AddrHashBank1__XorEnable__SHIFT 0x0
+#define UMCCH6_1_AddrHashBank1__ColXor__SHIFT 0x1
+#define UMCCH6_1_AddrHashBank1__RowXor__SHIFT 0xe
+#define UMCCH6_1_AddrHashBank1__XorEnable_MASK 0x00000001L
+#define UMCCH6_1_AddrHashBank1__ColXor_MASK 0x00003FFEL
+#define UMCCH6_1_AddrHashBank1__RowXor_MASK 0xFFFFC000L
+//UMCCH6_1_AddrHashBank2
+#define UMCCH6_1_AddrHashBank2__XorEnable__SHIFT 0x0
+#define UMCCH6_1_AddrHashBank2__ColXor__SHIFT 0x1
+#define UMCCH6_1_AddrHashBank2__RowXor__SHIFT 0xe
+#define UMCCH6_1_AddrHashBank2__XorEnable_MASK 0x00000001L
+#define UMCCH6_1_AddrHashBank2__ColXor_MASK 0x00003FFEL
+#define UMCCH6_1_AddrHashBank2__RowXor_MASK 0xFFFFC000L
+//UMCCH6_1_AddrHashBank3
+#define UMCCH6_1_AddrHashBank3__XorEnable__SHIFT 0x0
+#define UMCCH6_1_AddrHashBank3__ColXor__SHIFT 0x1
+#define UMCCH6_1_AddrHashBank3__RowXor__SHIFT 0xe
+#define UMCCH6_1_AddrHashBank3__XorEnable_MASK 0x00000001L
+#define UMCCH6_1_AddrHashBank3__ColXor_MASK 0x00003FFEL
+#define UMCCH6_1_AddrHashBank3__RowXor_MASK 0xFFFFC000L
+//UMCCH6_1_AddrHashBank4
+#define UMCCH6_1_AddrHashBank4__XorEnable__SHIFT 0x0
+#define UMCCH6_1_AddrHashBank4__ColXor__SHIFT 0x1
+#define UMCCH6_1_AddrHashBank4__RowXor__SHIFT 0xe
+#define UMCCH6_1_AddrHashBank4__XorEnable_MASK 0x00000001L
+#define UMCCH6_1_AddrHashBank4__ColXor_MASK 0x00003FFEL
+#define UMCCH6_1_AddrHashBank4__RowXor_MASK 0xFFFFC000L
+//UMCCH6_1_AddrHashBank5
+#define UMCCH6_1_AddrHashBank5__XorEnable__SHIFT 0x0
+#define UMCCH6_1_AddrHashBank5__ColXor__SHIFT 0x1
+#define UMCCH6_1_AddrHashBank5__RowXor__SHIFT 0xe
+#define UMCCH6_1_AddrHashBank5__XorEnable_MASK 0x00000001L
+#define UMCCH6_1_AddrHashBank5__ColXor_MASK 0x00003FFEL
+#define UMCCH6_1_AddrHashBank5__RowXor_MASK 0xFFFFC000L
+//UMCCH6_1_EccErrCntSel
+#define UMCCH6_1_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0
+#define UMCCH6_1_EccErrCntSel__EccErrInt__SHIFT 0xc
+#define UMCCH6_1_EccErrCntSel__EccErrCntEn__SHIFT 0xf
+#define UMCCH6_1_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL
+#define UMCCH6_1_EccErrCntSel__EccErrInt_MASK 0x00003000L
+#define UMCCH6_1_EccErrCntSel__EccErrCntEn_MASK 0x00008000L
+//UMCCH6_1_EccErrCnt
+#define UMCCH6_1_EccErrCnt__EccErrCnt__SHIFT 0x0
+#define UMCCH6_1_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL
+//UMCCH6_1_PerfMonCtlClk
+#define UMCCH6_1_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0
+#define UMCCH6_1_PerfMonCtlClk__ClkGate__SHIFT 0x16
+#define UMCCH6_1_PerfMonCtlClk__GlblReset__SHIFT 0x18
+#define UMCCH6_1_PerfMonCtlClk__GlblMonEn__SHIFT 0x19
+#define UMCCH6_1_PerfMonCtlClk__NumCounters__SHIFT 0x1a
+#define UMCCH6_1_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f
+#define UMCCH6_1_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL
+#define UMCCH6_1_PerfMonCtlClk__ClkGate_MASK 0x00400000L
+#define UMCCH6_1_PerfMonCtlClk__GlblReset_MASK 0x01000000L
+#define UMCCH6_1_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L
+#define UMCCH6_1_PerfMonCtlClk__NumCounters_MASK 0x3C000000L
+#define UMCCH6_1_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L
+//UMCCH6_1_PerfMonCtrClk_Lo
+#define UMCCH6_1_PerfMonCtrClk_Lo__Data__SHIFT 0x0
+#define UMCCH6_1_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_1_PerfMonCtrClk_Hi
+#define UMCCH6_1_PerfMonCtrClk_Hi__Data__SHIFT 0x0
+#define UMCCH6_1_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_1_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_1_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L
+//UMCCH6_1_PerfMonCtl1
+#define UMCCH6_1_PerfMonCtl1__EventSelect__SHIFT 0x0
+#define UMCCH6_1_PerfMonCtl1__RdWrMask__SHIFT 0x8
+#define UMCCH6_1_PerfMonCtl1__PriorityMask__SHIFT 0xa
+#define UMCCH6_1_PerfMonCtl1__ReqSizeMask__SHIFT 0xe
+#define UMCCH6_1_PerfMonCtl1__BankSel__SHIFT 0x10
+#define UMCCH6_1_PerfMonCtl1__VCSel__SHIFT 0x18
+#define UMCCH6_1_PerfMonCtl1__SubChanMask__SHIFT 0x1d
+#define UMCCH6_1_PerfMonCtl1__Enable__SHIFT 0x1f
+#define UMCCH6_1_PerfMonCtl1__EventSelect_MASK 0x000000FFL
+#define UMCCH6_1_PerfMonCtl1__RdWrMask_MASK 0x00000300L
+#define UMCCH6_1_PerfMonCtl1__PriorityMask_MASK 0x00003C00L
+#define UMCCH6_1_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH6_1_PerfMonCtl1__BankSel_MASK 0x00FF0000L
+#define UMCCH6_1_PerfMonCtl1__VCSel_MASK 0x1F000000L
+#define UMCCH6_1_PerfMonCtl1__SubChanMask_MASK 0x60000000L
+#define UMCCH6_1_PerfMonCtl1__Enable_MASK 0x80000000L
+//UMCCH6_1_PerfMonCtr1_Lo
+#define UMCCH6_1_PerfMonCtr1_Lo__Data__SHIFT 0x0
+#define UMCCH6_1_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_1_PerfMonCtr1_Hi
+#define UMCCH6_1_PerfMonCtr1_Hi__Data__SHIFT 0x0
+#define UMCCH6_1_PerfMonCtr1_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_1_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH6_1_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH6_1_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_1_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L
+#define UMCCH6_1_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH6_1_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH6_1_PerfMonCtl2
+#define UMCCH6_1_PerfMonCtl2__EventSelect__SHIFT 0x0
+#define UMCCH6_1_PerfMonCtl2__RdWrMask__SHIFT 0x8
+#define UMCCH6_1_PerfMonCtl2__PriorityMask__SHIFT 0xa
+#define UMCCH6_1_PerfMonCtl2__ReqSizeMask__SHIFT 0xe
+#define UMCCH6_1_PerfMonCtl2__BankSel__SHIFT 0x10
+#define UMCCH6_1_PerfMonCtl2__VCSel__SHIFT 0x18
+#define UMCCH6_1_PerfMonCtl2__SubChanMask__SHIFT 0x1d
+#define UMCCH6_1_PerfMonCtl2__Enable__SHIFT 0x1f
+#define UMCCH6_1_PerfMonCtl2__EventSelect_MASK 0x000000FFL
+#define UMCCH6_1_PerfMonCtl2__RdWrMask_MASK 0x00000300L
+#define UMCCH6_1_PerfMonCtl2__PriorityMask_MASK 0x00003C00L
+#define UMCCH6_1_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH6_1_PerfMonCtl2__BankSel_MASK 0x00FF0000L
+#define UMCCH6_1_PerfMonCtl2__VCSel_MASK 0x1F000000L
+#define UMCCH6_1_PerfMonCtl2__SubChanMask_MASK 0x60000000L
+#define UMCCH6_1_PerfMonCtl2__Enable_MASK 0x80000000L
+//UMCCH6_1_PerfMonCtr2_Lo
+#define UMCCH6_1_PerfMonCtr2_Lo__Data__SHIFT 0x0
+#define UMCCH6_1_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_1_PerfMonCtr2_Hi
+#define UMCCH6_1_PerfMonCtr2_Hi__Data__SHIFT 0x0
+#define UMCCH6_1_PerfMonCtr2_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_1_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH6_1_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH6_1_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_1_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L
+#define UMCCH6_1_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH6_1_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH6_1_PerfMonCtl3
+#define UMCCH6_1_PerfMonCtl3__EventSelect__SHIFT 0x0
+#define UMCCH6_1_PerfMonCtl3__RdWrMask__SHIFT 0x8
+#define UMCCH6_1_PerfMonCtl3__PriorityMask__SHIFT 0xa
+#define UMCCH6_1_PerfMonCtl3__ReqSizeMask__SHIFT 0xe
+#define UMCCH6_1_PerfMonCtl3__BankSel__SHIFT 0x10
+#define UMCCH6_1_PerfMonCtl3__VCSel__SHIFT 0x18
+#define UMCCH6_1_PerfMonCtl3__SubChanMask__SHIFT 0x1d
+#define UMCCH6_1_PerfMonCtl3__Enable__SHIFT 0x1f
+#define UMCCH6_1_PerfMonCtl3__EventSelect_MASK 0x000000FFL
+#define UMCCH6_1_PerfMonCtl3__RdWrMask_MASK 0x00000300L
+#define UMCCH6_1_PerfMonCtl3__PriorityMask_MASK 0x00003C00L
+#define UMCCH6_1_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH6_1_PerfMonCtl3__BankSel_MASK 0x00FF0000L
+#define UMCCH6_1_PerfMonCtl3__VCSel_MASK 0x1F000000L
+#define UMCCH6_1_PerfMonCtl3__SubChanMask_MASK 0x60000000L
+#define UMCCH6_1_PerfMonCtl3__Enable_MASK 0x80000000L
+//UMCCH6_1_PerfMonCtr3_Lo
+#define UMCCH6_1_PerfMonCtr3_Lo__Data__SHIFT 0x0
+#define UMCCH6_1_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_1_PerfMonCtr3_Hi
+#define UMCCH6_1_PerfMonCtr3_Hi__Data__SHIFT 0x0
+#define UMCCH6_1_PerfMonCtr3_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_1_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH6_1_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH6_1_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_1_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L
+#define UMCCH6_1_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH6_1_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH6_1_PerfMonCtl4
+#define UMCCH6_1_PerfMonCtl4__EventSelect__SHIFT 0x0
+#define UMCCH6_1_PerfMonCtl4__RdWrMask__SHIFT 0x8
+#define UMCCH6_1_PerfMonCtl4__PriorityMask__SHIFT 0xa
+#define UMCCH6_1_PerfMonCtl4__ReqSizeMask__SHIFT 0xe
+#define UMCCH6_1_PerfMonCtl4__BankSel__SHIFT 0x10
+#define UMCCH6_1_PerfMonCtl4__VCSel__SHIFT 0x18
+#define UMCCH6_1_PerfMonCtl4__SubChanMask__SHIFT 0x1d
+#define UMCCH6_1_PerfMonCtl4__Enable__SHIFT 0x1f
+#define UMCCH6_1_PerfMonCtl4__EventSelect_MASK 0x000000FFL
+#define UMCCH6_1_PerfMonCtl4__RdWrMask_MASK 0x00000300L
+#define UMCCH6_1_PerfMonCtl4__PriorityMask_MASK 0x00003C00L
+#define UMCCH6_1_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH6_1_PerfMonCtl4__BankSel_MASK 0x00FF0000L
+#define UMCCH6_1_PerfMonCtl4__VCSel_MASK 0x1F000000L
+#define UMCCH6_1_PerfMonCtl4__SubChanMask_MASK 0x60000000L
+#define UMCCH6_1_PerfMonCtl4__Enable_MASK 0x80000000L
+//UMCCH6_1_PerfMonCtr4_Lo
+#define UMCCH6_1_PerfMonCtr4_Lo__Data__SHIFT 0x0
+#define UMCCH6_1_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_1_PerfMonCtr4_Hi
+#define UMCCH6_1_PerfMonCtr4_Hi__Data__SHIFT 0x0
+#define UMCCH6_1_PerfMonCtr4_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_1_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH6_1_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH6_1_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_1_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L
+#define UMCCH6_1_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH6_1_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH6_1_PerfMonCtl5
+#define UMCCH6_1_PerfMonCtl5__EventSelect__SHIFT 0x0
+#define UMCCH6_1_PerfMonCtl5__RdWrMask__SHIFT 0x8
+#define UMCCH6_1_PerfMonCtl5__PriorityMask__SHIFT 0xa
+#define UMCCH6_1_PerfMonCtl5__ReqSizeMask__SHIFT 0xe
+#define UMCCH6_1_PerfMonCtl5__BankSel__SHIFT 0x10
+#define UMCCH6_1_PerfMonCtl5__VCSel__SHIFT 0x18
+#define UMCCH6_1_PerfMonCtl5__SubChanMask__SHIFT 0x1d
+#define UMCCH6_1_PerfMonCtl5__Enable__SHIFT 0x1f
+#define UMCCH6_1_PerfMonCtl5__EventSelect_MASK 0x000000FFL
+#define UMCCH6_1_PerfMonCtl5__RdWrMask_MASK 0x00000300L
+#define UMCCH6_1_PerfMonCtl5__PriorityMask_MASK 0x00003C00L
+#define UMCCH6_1_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH6_1_PerfMonCtl5__BankSel_MASK 0x00FF0000L
+#define UMCCH6_1_PerfMonCtl5__VCSel_MASK 0x1F000000L
+#define UMCCH6_1_PerfMonCtl5__SubChanMask_MASK 0x60000000L
+#define UMCCH6_1_PerfMonCtl5__Enable_MASK 0x80000000L
+//UMCCH6_1_PerfMonCtr5_Lo
+#define UMCCH6_1_PerfMonCtr5_Lo__Data__SHIFT 0x0
+#define UMCCH6_1_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_1_PerfMonCtr5_Hi
+#define UMCCH6_1_PerfMonCtr5_Hi__Data__SHIFT 0x0
+#define UMCCH6_1_PerfMonCtr5_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_1_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH6_1_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH6_1_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_1_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L
+#define UMCCH6_1_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH6_1_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH6_1_PerfMonCtl6
+#define UMCCH6_1_PerfMonCtl6__EventSelect__SHIFT 0x0
+#define UMCCH6_1_PerfMonCtl6__RdWrMask__SHIFT 0x8
+#define UMCCH6_1_PerfMonCtl6__PriorityMask__SHIFT 0xa
+#define UMCCH6_1_PerfMonCtl6__ReqSizeMask__SHIFT 0xe
+#define UMCCH6_1_PerfMonCtl6__BankSel__SHIFT 0x10
+#define UMCCH6_1_PerfMonCtl6__VCSel__SHIFT 0x18
+#define UMCCH6_1_PerfMonCtl6__SubChanMask__SHIFT 0x1d
+#define UMCCH6_1_PerfMonCtl6__Enable__SHIFT 0x1f
+#define UMCCH6_1_PerfMonCtl6__EventSelect_MASK 0x000000FFL
+#define UMCCH6_1_PerfMonCtl6__RdWrMask_MASK 0x00000300L
+#define UMCCH6_1_PerfMonCtl6__PriorityMask_MASK 0x00003C00L
+#define UMCCH6_1_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH6_1_PerfMonCtl6__BankSel_MASK 0x00FF0000L
+#define UMCCH6_1_PerfMonCtl6__VCSel_MASK 0x1F000000L
+#define UMCCH6_1_PerfMonCtl6__SubChanMask_MASK 0x60000000L
+#define UMCCH6_1_PerfMonCtl6__Enable_MASK 0x80000000L
+//UMCCH6_1_PerfMonCtr6_Lo
+#define UMCCH6_1_PerfMonCtr6_Lo__Data__SHIFT 0x0
+#define UMCCH6_1_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_1_PerfMonCtr6_Hi
+#define UMCCH6_1_PerfMonCtr6_Hi__Data__SHIFT 0x0
+#define UMCCH6_1_PerfMonCtr6_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_1_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH6_1_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH6_1_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_1_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L
+#define UMCCH6_1_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH6_1_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH6_1_PerfMonCtl7
+#define UMCCH6_1_PerfMonCtl7__EventSelect__SHIFT 0x0
+#define UMCCH6_1_PerfMonCtl7__RdWrMask__SHIFT 0x8
+#define UMCCH6_1_PerfMonCtl7__PriorityMask__SHIFT 0xa
+#define UMCCH6_1_PerfMonCtl7__ReqSizeMask__SHIFT 0xe
+#define UMCCH6_1_PerfMonCtl7__BankSel__SHIFT 0x10
+#define UMCCH6_1_PerfMonCtl7__VCSel__SHIFT 0x18
+#define UMCCH6_1_PerfMonCtl7__SubChanMask__SHIFT 0x1d
+#define UMCCH6_1_PerfMonCtl7__Enable__SHIFT 0x1f
+#define UMCCH6_1_PerfMonCtl7__EventSelect_MASK 0x000000FFL
+#define UMCCH6_1_PerfMonCtl7__RdWrMask_MASK 0x00000300L
+#define UMCCH6_1_PerfMonCtl7__PriorityMask_MASK 0x00003C00L
+#define UMCCH6_1_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH6_1_PerfMonCtl7__BankSel_MASK 0x00FF0000L
+#define UMCCH6_1_PerfMonCtl7__VCSel_MASK 0x1F000000L
+#define UMCCH6_1_PerfMonCtl7__SubChanMask_MASK 0x60000000L
+#define UMCCH6_1_PerfMonCtl7__Enable_MASK 0x80000000L
+//UMCCH6_1_PerfMonCtr7_Lo
+#define UMCCH6_1_PerfMonCtr7_Lo__Data__SHIFT 0x0
+#define UMCCH6_1_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_1_PerfMonCtr7_Hi
+#define UMCCH6_1_PerfMonCtr7_Hi__Data__SHIFT 0x0
+#define UMCCH6_1_PerfMonCtr7_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_1_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH6_1_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH6_1_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_1_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L
+#define UMCCH6_1_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH6_1_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH6_1_PerfMonCtl8
+#define UMCCH6_1_PerfMonCtl8__EventSelect__SHIFT 0x0
+#define UMCCH6_1_PerfMonCtl8__RdWrMask__SHIFT 0x8
+#define UMCCH6_1_PerfMonCtl8__PriorityMask__SHIFT 0xa
+#define UMCCH6_1_PerfMonCtl8__ReqSizeMask__SHIFT 0xe
+#define UMCCH6_1_PerfMonCtl8__BankSel__SHIFT 0x10
+#define UMCCH6_1_PerfMonCtl8__VCSel__SHIFT 0x18
+#define UMCCH6_1_PerfMonCtl8__SubChanMask__SHIFT 0x1d
+#define UMCCH6_1_PerfMonCtl8__Enable__SHIFT 0x1f
+#define UMCCH6_1_PerfMonCtl8__EventSelect_MASK 0x000000FFL
+#define UMCCH6_1_PerfMonCtl8__RdWrMask_MASK 0x00000300L
+#define UMCCH6_1_PerfMonCtl8__PriorityMask_MASK 0x00003C00L
+#define UMCCH6_1_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH6_1_PerfMonCtl8__BankSel_MASK 0x00FF0000L
+#define UMCCH6_1_PerfMonCtl8__VCSel_MASK 0x1F000000L
+#define UMCCH6_1_PerfMonCtl8__SubChanMask_MASK 0x60000000L
+#define UMCCH6_1_PerfMonCtl8__Enable_MASK 0x80000000L
+//UMCCH6_1_PerfMonCtr8_Lo
+#define UMCCH6_1_PerfMonCtr8_Lo__Data__SHIFT 0x0
+#define UMCCH6_1_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_1_PerfMonCtr8_Hi
+#define UMCCH6_1_PerfMonCtr8_Hi__Data__SHIFT 0x0
+#define UMCCH6_1_PerfMonCtr8_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_1_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH6_1_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH6_1_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_1_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L
+#define UMCCH6_1_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH6_1_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L
+
+
+// addressBlock: umc_w_phy_umc1_umcch7_umcchdec
+//UMCCH7_1_BaseAddrCS0
+#define UMCCH7_1_BaseAddrCS0__CSEnable__SHIFT 0x0
+#define UMCCH7_1_BaseAddrCS0__BaseAddr__SHIFT 0x1
+#define UMCCH7_1_BaseAddrCS0__CSEnable_MASK 0x00000001L
+#define UMCCH7_1_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL
+//UMCCH7_1_AddrMaskCS01
+#define UMCCH7_1_AddrMaskCS01__AddrMask__SHIFT 0x1
+#define UMCCH7_1_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL
+//UMCCH7_1_AddrSelCS01
+#define UMCCH7_1_AddrSelCS01__BankBit0__SHIFT 0x0
+#define UMCCH7_1_AddrSelCS01__BankBit1__SHIFT 0x4
+#define UMCCH7_1_AddrSelCS01__BankBit2__SHIFT 0x8
+#define UMCCH7_1_AddrSelCS01__BankBit3__SHIFT 0xc
+#define UMCCH7_1_AddrSelCS01__BankBit4__SHIFT 0x10
+#define UMCCH7_1_AddrSelCS01__RowLo__SHIFT 0x18
+#define UMCCH7_1_AddrSelCS01__RowHi__SHIFT 0x1c
+#define UMCCH7_1_AddrSelCS01__BankBit0_MASK 0x0000000FL
+#define UMCCH7_1_AddrSelCS01__BankBit1_MASK 0x000000F0L
+#define UMCCH7_1_AddrSelCS01__BankBit2_MASK 0x00000F00L
+#define UMCCH7_1_AddrSelCS01__BankBit3_MASK 0x0000F000L
+#define UMCCH7_1_AddrSelCS01__BankBit4_MASK 0x001F0000L
+#define UMCCH7_1_AddrSelCS01__RowLo_MASK 0x0F000000L
+#define UMCCH7_1_AddrSelCS01__RowHi_MASK 0xF0000000L
+//UMCCH7_1_AddrHashBank0
+#define UMCCH7_1_AddrHashBank0__XorEnable__SHIFT 0x0
+#define UMCCH7_1_AddrHashBank0__ColXor__SHIFT 0x1
+#define UMCCH7_1_AddrHashBank0__RowXor__SHIFT 0xe
+#define UMCCH7_1_AddrHashBank0__XorEnable_MASK 0x00000001L
+#define UMCCH7_1_AddrHashBank0__ColXor_MASK 0x00003FFEL
+#define UMCCH7_1_AddrHashBank0__RowXor_MASK 0xFFFFC000L
+//UMCCH7_1_AddrHashBank1
+#define UMCCH7_1_AddrHashBank1__XorEnable__SHIFT 0x0
+#define UMCCH7_1_AddrHashBank1__ColXor__SHIFT 0x1
+#define UMCCH7_1_AddrHashBank1__RowXor__SHIFT 0xe
+#define UMCCH7_1_AddrHashBank1__XorEnable_MASK 0x00000001L
+#define UMCCH7_1_AddrHashBank1__ColXor_MASK 0x00003FFEL
+#define UMCCH7_1_AddrHashBank1__RowXor_MASK 0xFFFFC000L
+//UMCCH7_1_AddrHashBank2
+#define UMCCH7_1_AddrHashBank2__XorEnable__SHIFT 0x0
+#define UMCCH7_1_AddrHashBank2__ColXor__SHIFT 0x1
+#define UMCCH7_1_AddrHashBank2__RowXor__SHIFT 0xe
+#define UMCCH7_1_AddrHashBank2__XorEnable_MASK 0x00000001L
+#define UMCCH7_1_AddrHashBank2__ColXor_MASK 0x00003FFEL
+#define UMCCH7_1_AddrHashBank2__RowXor_MASK 0xFFFFC000L
+//UMCCH7_1_AddrHashBank3
+#define UMCCH7_1_AddrHashBank3__XorEnable__SHIFT 0x0
+#define UMCCH7_1_AddrHashBank3__ColXor__SHIFT 0x1
+#define UMCCH7_1_AddrHashBank3__RowXor__SHIFT 0xe
+#define UMCCH7_1_AddrHashBank3__XorEnable_MASK 0x00000001L
+#define UMCCH7_1_AddrHashBank3__ColXor_MASK 0x00003FFEL
+#define UMCCH7_1_AddrHashBank3__RowXor_MASK 0xFFFFC000L
+//UMCCH7_1_AddrHashBank4
+#define UMCCH7_1_AddrHashBank4__XorEnable__SHIFT 0x0
+#define UMCCH7_1_AddrHashBank4__ColXor__SHIFT 0x1
+#define UMCCH7_1_AddrHashBank4__RowXor__SHIFT 0xe
+#define UMCCH7_1_AddrHashBank4__XorEnable_MASK 0x00000001L
+#define UMCCH7_1_AddrHashBank4__ColXor_MASK 0x00003FFEL
+#define UMCCH7_1_AddrHashBank4__RowXor_MASK 0xFFFFC000L
+//UMCCH7_1_AddrHashBank5
+#define UMCCH7_1_AddrHashBank5__XorEnable__SHIFT 0x0
+#define UMCCH7_1_AddrHashBank5__ColXor__SHIFT 0x1
+#define UMCCH7_1_AddrHashBank5__RowXor__SHIFT 0xe
+#define UMCCH7_1_AddrHashBank5__XorEnable_MASK 0x00000001L
+#define UMCCH7_1_AddrHashBank5__ColXor_MASK 0x00003FFEL
+#define UMCCH7_1_AddrHashBank5__RowXor_MASK 0xFFFFC000L
+//UMCCH7_1_EccErrCntSel
+#define UMCCH7_1_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0
+#define UMCCH7_1_EccErrCntSel__EccErrInt__SHIFT 0xc
+#define UMCCH7_1_EccErrCntSel__EccErrCntEn__SHIFT 0xf
+#define UMCCH7_1_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL
+#define UMCCH7_1_EccErrCntSel__EccErrInt_MASK 0x00003000L
+#define UMCCH7_1_EccErrCntSel__EccErrCntEn_MASK 0x00008000L
+//UMCCH7_1_EccErrCnt
+#define UMCCH7_1_EccErrCnt__EccErrCnt__SHIFT 0x0
+#define UMCCH7_1_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL
+//UMCCH7_1_PerfMonCtlClk
+#define UMCCH7_1_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0
+#define UMCCH7_1_PerfMonCtlClk__ClkGate__SHIFT 0x16
+#define UMCCH7_1_PerfMonCtlClk__GlblReset__SHIFT 0x18
+#define UMCCH7_1_PerfMonCtlClk__GlblMonEn__SHIFT 0x19
+#define UMCCH7_1_PerfMonCtlClk__NumCounters__SHIFT 0x1a
+#define UMCCH7_1_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f
+#define UMCCH7_1_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL
+#define UMCCH7_1_PerfMonCtlClk__ClkGate_MASK 0x00400000L
+#define UMCCH7_1_PerfMonCtlClk__GlblReset_MASK 0x01000000L
+#define UMCCH7_1_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L
+#define UMCCH7_1_PerfMonCtlClk__NumCounters_MASK 0x3C000000L
+#define UMCCH7_1_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L
+//UMCCH7_1_PerfMonCtrClk_Lo
+#define UMCCH7_1_PerfMonCtrClk_Lo__Data__SHIFT 0x0
+#define UMCCH7_1_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_1_PerfMonCtrClk_Hi
+#define UMCCH7_1_PerfMonCtrClk_Hi__Data__SHIFT 0x0
+#define UMCCH7_1_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_1_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_1_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L
+//UMCCH7_1_PerfMonCtl1
+#define UMCCH7_1_PerfMonCtl1__EventSelect__SHIFT 0x0
+#define UMCCH7_1_PerfMonCtl1__RdWrMask__SHIFT 0x8
+#define UMCCH7_1_PerfMonCtl1__PriorityMask__SHIFT 0xa
+#define UMCCH7_1_PerfMonCtl1__ReqSizeMask__SHIFT 0xe
+#define UMCCH7_1_PerfMonCtl1__BankSel__SHIFT 0x10
+#define UMCCH7_1_PerfMonCtl1__VCSel__SHIFT 0x18
+#define UMCCH7_1_PerfMonCtl1__SubChanMask__SHIFT 0x1d
+#define UMCCH7_1_PerfMonCtl1__Enable__SHIFT 0x1f
+#define UMCCH7_1_PerfMonCtl1__EventSelect_MASK 0x000000FFL
+#define UMCCH7_1_PerfMonCtl1__RdWrMask_MASK 0x00000300L
+#define UMCCH7_1_PerfMonCtl1__PriorityMask_MASK 0x00003C00L
+#define UMCCH7_1_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH7_1_PerfMonCtl1__BankSel_MASK 0x00FF0000L
+#define UMCCH7_1_PerfMonCtl1__VCSel_MASK 0x1F000000L
+#define UMCCH7_1_PerfMonCtl1__SubChanMask_MASK 0x60000000L
+#define UMCCH7_1_PerfMonCtl1__Enable_MASK 0x80000000L
+//UMCCH7_1_PerfMonCtr1_Lo
+#define UMCCH7_1_PerfMonCtr1_Lo__Data__SHIFT 0x0
+#define UMCCH7_1_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_1_PerfMonCtr1_Hi
+#define UMCCH7_1_PerfMonCtr1_Hi__Data__SHIFT 0x0
+#define UMCCH7_1_PerfMonCtr1_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_1_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH7_1_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH7_1_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_1_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L
+#define UMCCH7_1_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH7_1_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH7_1_PerfMonCtl2
+#define UMCCH7_1_PerfMonCtl2__EventSelect__SHIFT 0x0
+#define UMCCH7_1_PerfMonCtl2__RdWrMask__SHIFT 0x8
+#define UMCCH7_1_PerfMonCtl2__PriorityMask__SHIFT 0xa
+#define UMCCH7_1_PerfMonCtl2__ReqSizeMask__SHIFT 0xe
+#define UMCCH7_1_PerfMonCtl2__BankSel__SHIFT 0x10
+#define UMCCH7_1_PerfMonCtl2__VCSel__SHIFT 0x18
+#define UMCCH7_1_PerfMonCtl2__SubChanMask__SHIFT 0x1d
+#define UMCCH7_1_PerfMonCtl2__Enable__SHIFT 0x1f
+#define UMCCH7_1_PerfMonCtl2__EventSelect_MASK 0x000000FFL
+#define UMCCH7_1_PerfMonCtl2__RdWrMask_MASK 0x00000300L
+#define UMCCH7_1_PerfMonCtl2__PriorityMask_MASK 0x00003C00L
+#define UMCCH7_1_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH7_1_PerfMonCtl2__BankSel_MASK 0x00FF0000L
+#define UMCCH7_1_PerfMonCtl2__VCSel_MASK 0x1F000000L
+#define UMCCH7_1_PerfMonCtl2__SubChanMask_MASK 0x60000000L
+#define UMCCH7_1_PerfMonCtl2__Enable_MASK 0x80000000L
+//UMCCH7_1_PerfMonCtr2_Lo
+#define UMCCH7_1_PerfMonCtr2_Lo__Data__SHIFT 0x0
+#define UMCCH7_1_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_1_PerfMonCtr2_Hi
+#define UMCCH7_1_PerfMonCtr2_Hi__Data__SHIFT 0x0
+#define UMCCH7_1_PerfMonCtr2_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_1_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH7_1_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH7_1_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_1_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L
+#define UMCCH7_1_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH7_1_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH7_1_PerfMonCtl3
+#define UMCCH7_1_PerfMonCtl3__EventSelect__SHIFT 0x0
+#define UMCCH7_1_PerfMonCtl3__RdWrMask__SHIFT 0x8
+#define UMCCH7_1_PerfMonCtl3__PriorityMask__SHIFT 0xa
+#define UMCCH7_1_PerfMonCtl3__ReqSizeMask__SHIFT 0xe
+#define UMCCH7_1_PerfMonCtl3__BankSel__SHIFT 0x10
+#define UMCCH7_1_PerfMonCtl3__VCSel__SHIFT 0x18
+#define UMCCH7_1_PerfMonCtl3__SubChanMask__SHIFT 0x1d
+#define UMCCH7_1_PerfMonCtl3__Enable__SHIFT 0x1f
+#define UMCCH7_1_PerfMonCtl3__EventSelect_MASK 0x000000FFL
+#define UMCCH7_1_PerfMonCtl3__RdWrMask_MASK 0x00000300L
+#define UMCCH7_1_PerfMonCtl3__PriorityMask_MASK 0x00003C00L
+#define UMCCH7_1_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH7_1_PerfMonCtl3__BankSel_MASK 0x00FF0000L
+#define UMCCH7_1_PerfMonCtl3__VCSel_MASK 0x1F000000L
+#define UMCCH7_1_PerfMonCtl3__SubChanMask_MASK 0x60000000L
+#define UMCCH7_1_PerfMonCtl3__Enable_MASK 0x80000000L
+//UMCCH7_1_PerfMonCtr3_Lo
+#define UMCCH7_1_PerfMonCtr3_Lo__Data__SHIFT 0x0
+#define UMCCH7_1_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_1_PerfMonCtr3_Hi
+#define UMCCH7_1_PerfMonCtr3_Hi__Data__SHIFT 0x0
+#define UMCCH7_1_PerfMonCtr3_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_1_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH7_1_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH7_1_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_1_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L
+#define UMCCH7_1_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH7_1_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH7_1_PerfMonCtl4
+#define UMCCH7_1_PerfMonCtl4__EventSelect__SHIFT 0x0
+#define UMCCH7_1_PerfMonCtl4__RdWrMask__SHIFT 0x8
+#define UMCCH7_1_PerfMonCtl4__PriorityMask__SHIFT 0xa
+#define UMCCH7_1_PerfMonCtl4__ReqSizeMask__SHIFT 0xe
+#define UMCCH7_1_PerfMonCtl4__BankSel__SHIFT 0x10
+#define UMCCH7_1_PerfMonCtl4__VCSel__SHIFT 0x18
+#define UMCCH7_1_PerfMonCtl4__SubChanMask__SHIFT 0x1d
+#define UMCCH7_1_PerfMonCtl4__Enable__SHIFT 0x1f
+#define UMCCH7_1_PerfMonCtl4__EventSelect_MASK 0x000000FFL
+#define UMCCH7_1_PerfMonCtl4__RdWrMask_MASK 0x00000300L
+#define UMCCH7_1_PerfMonCtl4__PriorityMask_MASK 0x00003C00L
+#define UMCCH7_1_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH7_1_PerfMonCtl4__BankSel_MASK 0x00FF0000L
+#define UMCCH7_1_PerfMonCtl4__VCSel_MASK 0x1F000000L
+#define UMCCH7_1_PerfMonCtl4__SubChanMask_MASK 0x60000000L
+#define UMCCH7_1_PerfMonCtl4__Enable_MASK 0x80000000L
+//UMCCH7_1_PerfMonCtr4_Lo
+#define UMCCH7_1_PerfMonCtr4_Lo__Data__SHIFT 0x0
+#define UMCCH7_1_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_1_PerfMonCtr4_Hi
+#define UMCCH7_1_PerfMonCtr4_Hi__Data__SHIFT 0x0
+#define UMCCH7_1_PerfMonCtr4_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_1_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH7_1_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH7_1_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_1_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L
+#define UMCCH7_1_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH7_1_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH7_1_PerfMonCtl5
+#define UMCCH7_1_PerfMonCtl5__EventSelect__SHIFT 0x0
+#define UMCCH7_1_PerfMonCtl5__RdWrMask__SHIFT 0x8
+#define UMCCH7_1_PerfMonCtl5__PriorityMask__SHIFT 0xa
+#define UMCCH7_1_PerfMonCtl5__ReqSizeMask__SHIFT 0xe
+#define UMCCH7_1_PerfMonCtl5__BankSel__SHIFT 0x10
+#define UMCCH7_1_PerfMonCtl5__VCSel__SHIFT 0x18
+#define UMCCH7_1_PerfMonCtl5__SubChanMask__SHIFT 0x1d
+#define UMCCH7_1_PerfMonCtl5__Enable__SHIFT 0x1f
+#define UMCCH7_1_PerfMonCtl5__EventSelect_MASK 0x000000FFL
+#define UMCCH7_1_PerfMonCtl5__RdWrMask_MASK 0x00000300L
+#define UMCCH7_1_PerfMonCtl5__PriorityMask_MASK 0x00003C00L
+#define UMCCH7_1_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH7_1_PerfMonCtl5__BankSel_MASK 0x00FF0000L
+#define UMCCH7_1_PerfMonCtl5__VCSel_MASK 0x1F000000L
+#define UMCCH7_1_PerfMonCtl5__SubChanMask_MASK 0x60000000L
+#define UMCCH7_1_PerfMonCtl5__Enable_MASK 0x80000000L
+//UMCCH7_1_PerfMonCtr5_Lo
+#define UMCCH7_1_PerfMonCtr5_Lo__Data__SHIFT 0x0
+#define UMCCH7_1_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_1_PerfMonCtr5_Hi
+#define UMCCH7_1_PerfMonCtr5_Hi__Data__SHIFT 0x0
+#define UMCCH7_1_PerfMonCtr5_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_1_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH7_1_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH7_1_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_1_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L
+#define UMCCH7_1_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH7_1_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH7_1_PerfMonCtl6
+#define UMCCH7_1_PerfMonCtl6__EventSelect__SHIFT 0x0
+#define UMCCH7_1_PerfMonCtl6__RdWrMask__SHIFT 0x8
+#define UMCCH7_1_PerfMonCtl6__PriorityMask__SHIFT 0xa
+#define UMCCH7_1_PerfMonCtl6__ReqSizeMask__SHIFT 0xe
+#define UMCCH7_1_PerfMonCtl6__BankSel__SHIFT 0x10
+#define UMCCH7_1_PerfMonCtl6__VCSel__SHIFT 0x18
+#define UMCCH7_1_PerfMonCtl6__SubChanMask__SHIFT 0x1d
+#define UMCCH7_1_PerfMonCtl6__Enable__SHIFT 0x1f
+#define UMCCH7_1_PerfMonCtl6__EventSelect_MASK 0x000000FFL
+#define UMCCH7_1_PerfMonCtl6__RdWrMask_MASK 0x00000300L
+#define UMCCH7_1_PerfMonCtl6__PriorityMask_MASK 0x00003C00L
+#define UMCCH7_1_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH7_1_PerfMonCtl6__BankSel_MASK 0x00FF0000L
+#define UMCCH7_1_PerfMonCtl6__VCSel_MASK 0x1F000000L
+#define UMCCH7_1_PerfMonCtl6__SubChanMask_MASK 0x60000000L
+#define UMCCH7_1_PerfMonCtl6__Enable_MASK 0x80000000L
+//UMCCH7_1_PerfMonCtr6_Lo
+#define UMCCH7_1_PerfMonCtr6_Lo__Data__SHIFT 0x0
+#define UMCCH7_1_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_1_PerfMonCtr6_Hi
+#define UMCCH7_1_PerfMonCtr6_Hi__Data__SHIFT 0x0
+#define UMCCH7_1_PerfMonCtr6_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_1_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH7_1_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH7_1_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_1_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L
+#define UMCCH7_1_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH7_1_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH7_1_PerfMonCtl7
+#define UMCCH7_1_PerfMonCtl7__EventSelect__SHIFT 0x0
+#define UMCCH7_1_PerfMonCtl7__RdWrMask__SHIFT 0x8
+#define UMCCH7_1_PerfMonCtl7__PriorityMask__SHIFT 0xa
+#define UMCCH7_1_PerfMonCtl7__ReqSizeMask__SHIFT 0xe
+#define UMCCH7_1_PerfMonCtl7__BankSel__SHIFT 0x10
+#define UMCCH7_1_PerfMonCtl7__VCSel__SHIFT 0x18
+#define UMCCH7_1_PerfMonCtl7__SubChanMask__SHIFT 0x1d
+#define UMCCH7_1_PerfMonCtl7__Enable__SHIFT 0x1f
+#define UMCCH7_1_PerfMonCtl7__EventSelect_MASK 0x000000FFL
+#define UMCCH7_1_PerfMonCtl7__RdWrMask_MASK 0x00000300L
+#define UMCCH7_1_PerfMonCtl7__PriorityMask_MASK 0x00003C00L
+#define UMCCH7_1_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH7_1_PerfMonCtl7__BankSel_MASK 0x00FF0000L
+#define UMCCH7_1_PerfMonCtl7__VCSel_MASK 0x1F000000L
+#define UMCCH7_1_PerfMonCtl7__SubChanMask_MASK 0x60000000L
+#define UMCCH7_1_PerfMonCtl7__Enable_MASK 0x80000000L
+//UMCCH7_1_PerfMonCtr7_Lo
+#define UMCCH7_1_PerfMonCtr7_Lo__Data__SHIFT 0x0
+#define UMCCH7_1_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_1_PerfMonCtr7_Hi
+#define UMCCH7_1_PerfMonCtr7_Hi__Data__SHIFT 0x0
+#define UMCCH7_1_PerfMonCtr7_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_1_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH7_1_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH7_1_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_1_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L
+#define UMCCH7_1_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH7_1_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH7_1_PerfMonCtl8
+#define UMCCH7_1_PerfMonCtl8__EventSelect__SHIFT 0x0
+#define UMCCH7_1_PerfMonCtl8__RdWrMask__SHIFT 0x8
+#define UMCCH7_1_PerfMonCtl8__PriorityMask__SHIFT 0xa
+#define UMCCH7_1_PerfMonCtl8__ReqSizeMask__SHIFT 0xe
+#define UMCCH7_1_PerfMonCtl8__BankSel__SHIFT 0x10
+#define UMCCH7_1_PerfMonCtl8__VCSel__SHIFT 0x18
+#define UMCCH7_1_PerfMonCtl8__SubChanMask__SHIFT 0x1d
+#define UMCCH7_1_PerfMonCtl8__Enable__SHIFT 0x1f
+#define UMCCH7_1_PerfMonCtl8__EventSelect_MASK 0x000000FFL
+#define UMCCH7_1_PerfMonCtl8__RdWrMask_MASK 0x00000300L
+#define UMCCH7_1_PerfMonCtl8__PriorityMask_MASK 0x00003C00L
+#define UMCCH7_1_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH7_1_PerfMonCtl8__BankSel_MASK 0x00FF0000L
+#define UMCCH7_1_PerfMonCtl8__VCSel_MASK 0x1F000000L
+#define UMCCH7_1_PerfMonCtl8__SubChanMask_MASK 0x60000000L
+#define UMCCH7_1_PerfMonCtl8__Enable_MASK 0x80000000L
+//UMCCH7_1_PerfMonCtr8_Lo
+#define UMCCH7_1_PerfMonCtr8_Lo__Data__SHIFT 0x0
+#define UMCCH7_1_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_1_PerfMonCtr8_Hi
+#define UMCCH7_1_PerfMonCtr8_Hi__Data__SHIFT 0x0
+#define UMCCH7_1_PerfMonCtr8_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_1_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH7_1_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH7_1_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_1_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L
+#define UMCCH7_1_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH7_1_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L
+
+
+// addressBlock: umc_w_phy_umc2_umcch0_umcchdec
+//UMCCH0_2_BaseAddrCS0
+#define UMCCH0_2_BaseAddrCS0__CSEnable__SHIFT 0x0
+#define UMCCH0_2_BaseAddrCS0__BaseAddr__SHIFT 0x1
+#define UMCCH0_2_BaseAddrCS0__CSEnable_MASK 0x00000001L
+#define UMCCH0_2_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL
+//UMCCH0_2_AddrMaskCS01
+#define UMCCH0_2_AddrMaskCS01__AddrMask__SHIFT 0x1
+#define UMCCH0_2_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL
+//UMCCH0_2_AddrSelCS01
+#define UMCCH0_2_AddrSelCS01__BankBit0__SHIFT 0x0
+#define UMCCH0_2_AddrSelCS01__BankBit1__SHIFT 0x4
+#define UMCCH0_2_AddrSelCS01__BankBit2__SHIFT 0x8
+#define UMCCH0_2_AddrSelCS01__BankBit3__SHIFT 0xc
+#define UMCCH0_2_AddrSelCS01__BankBit4__SHIFT 0x10
+#define UMCCH0_2_AddrSelCS01__RowLo__SHIFT 0x18
+#define UMCCH0_2_AddrSelCS01__RowHi__SHIFT 0x1c
+#define UMCCH0_2_AddrSelCS01__BankBit0_MASK 0x0000000FL
+#define UMCCH0_2_AddrSelCS01__BankBit1_MASK 0x000000F0L
+#define UMCCH0_2_AddrSelCS01__BankBit2_MASK 0x00000F00L
+#define UMCCH0_2_AddrSelCS01__BankBit3_MASK 0x0000F000L
+#define UMCCH0_2_AddrSelCS01__BankBit4_MASK 0x001F0000L
+#define UMCCH0_2_AddrSelCS01__RowLo_MASK 0x0F000000L
+#define UMCCH0_2_AddrSelCS01__RowHi_MASK 0xF0000000L
+//UMCCH0_2_AddrHashBank0
+#define UMCCH0_2_AddrHashBank0__XorEnable__SHIFT 0x0
+#define UMCCH0_2_AddrHashBank0__ColXor__SHIFT 0x1
+#define UMCCH0_2_AddrHashBank0__RowXor__SHIFT 0xe
+#define UMCCH0_2_AddrHashBank0__XorEnable_MASK 0x00000001L
+#define UMCCH0_2_AddrHashBank0__ColXor_MASK 0x00003FFEL
+#define UMCCH0_2_AddrHashBank0__RowXor_MASK 0xFFFFC000L
+//UMCCH0_2_AddrHashBank1
+#define UMCCH0_2_AddrHashBank1__XorEnable__SHIFT 0x0
+#define UMCCH0_2_AddrHashBank1__ColXor__SHIFT 0x1
+#define UMCCH0_2_AddrHashBank1__RowXor__SHIFT 0xe
+#define UMCCH0_2_AddrHashBank1__XorEnable_MASK 0x00000001L
+#define UMCCH0_2_AddrHashBank1__ColXor_MASK 0x00003FFEL
+#define UMCCH0_2_AddrHashBank1__RowXor_MASK 0xFFFFC000L
+//UMCCH0_2_AddrHashBank2
+#define UMCCH0_2_AddrHashBank2__XorEnable__SHIFT 0x0
+#define UMCCH0_2_AddrHashBank2__ColXor__SHIFT 0x1
+#define UMCCH0_2_AddrHashBank2__RowXor__SHIFT 0xe
+#define UMCCH0_2_AddrHashBank2__XorEnable_MASK 0x00000001L
+#define UMCCH0_2_AddrHashBank2__ColXor_MASK 0x00003FFEL
+#define UMCCH0_2_AddrHashBank2__RowXor_MASK 0xFFFFC000L
+//UMCCH0_2_AddrHashBank3
+#define UMCCH0_2_AddrHashBank3__XorEnable__SHIFT 0x0
+#define UMCCH0_2_AddrHashBank3__ColXor__SHIFT 0x1
+#define UMCCH0_2_AddrHashBank3__RowXor__SHIFT 0xe
+#define UMCCH0_2_AddrHashBank3__XorEnable_MASK 0x00000001L
+#define UMCCH0_2_AddrHashBank3__ColXor_MASK 0x00003FFEL
+#define UMCCH0_2_AddrHashBank3__RowXor_MASK 0xFFFFC000L
+//UMCCH0_2_AddrHashBank4
+#define UMCCH0_2_AddrHashBank4__XorEnable__SHIFT 0x0
+#define UMCCH0_2_AddrHashBank4__ColXor__SHIFT 0x1
+#define UMCCH0_2_AddrHashBank4__RowXor__SHIFT 0xe
+#define UMCCH0_2_AddrHashBank4__XorEnable_MASK 0x00000001L
+#define UMCCH0_2_AddrHashBank4__ColXor_MASK 0x00003FFEL
+#define UMCCH0_2_AddrHashBank4__RowXor_MASK 0xFFFFC000L
+//UMCCH0_2_AddrHashBank5
+#define UMCCH0_2_AddrHashBank5__XorEnable__SHIFT 0x0
+#define UMCCH0_2_AddrHashBank5__ColXor__SHIFT 0x1
+#define UMCCH0_2_AddrHashBank5__RowXor__SHIFT 0xe
+#define UMCCH0_2_AddrHashBank5__XorEnable_MASK 0x00000001L
+#define UMCCH0_2_AddrHashBank5__ColXor_MASK 0x00003FFEL
+#define UMCCH0_2_AddrHashBank5__RowXor_MASK 0xFFFFC000L
+//UMCCH0_2_EccErrCntSel
+#define UMCCH0_2_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0
+#define UMCCH0_2_EccErrCntSel__EccErrInt__SHIFT 0xc
+#define UMCCH0_2_EccErrCntSel__EccErrCntEn__SHIFT 0xf
+#define UMCCH0_2_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL
+#define UMCCH0_2_EccErrCntSel__EccErrInt_MASK 0x00003000L
+#define UMCCH0_2_EccErrCntSel__EccErrCntEn_MASK 0x00008000L
+//UMCCH0_2_EccErrCnt
+#define UMCCH0_2_EccErrCnt__EccErrCnt__SHIFT 0x0
+#define UMCCH0_2_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL
+//UMCCH0_2_PerfMonCtlClk
+#define UMCCH0_2_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0
+#define UMCCH0_2_PerfMonCtlClk__ClkGate__SHIFT 0x16
+#define UMCCH0_2_PerfMonCtlClk__GlblReset__SHIFT 0x18
+#define UMCCH0_2_PerfMonCtlClk__GlblMonEn__SHIFT 0x19
+#define UMCCH0_2_PerfMonCtlClk__NumCounters__SHIFT 0x1a
+#define UMCCH0_2_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f
+#define UMCCH0_2_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL
+#define UMCCH0_2_PerfMonCtlClk__ClkGate_MASK 0x00400000L
+#define UMCCH0_2_PerfMonCtlClk__GlblReset_MASK 0x01000000L
+#define UMCCH0_2_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L
+#define UMCCH0_2_PerfMonCtlClk__NumCounters_MASK 0x3C000000L
+#define UMCCH0_2_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L
+//UMCCH0_2_PerfMonCtrClk_Lo
+#define UMCCH0_2_PerfMonCtrClk_Lo__Data__SHIFT 0x0
+#define UMCCH0_2_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_2_PerfMonCtrClk_Hi
+#define UMCCH0_2_PerfMonCtrClk_Hi__Data__SHIFT 0x0
+#define UMCCH0_2_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_2_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_2_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L
+//UMCCH0_2_PerfMonCtl1
+#define UMCCH0_2_PerfMonCtl1__EventSelect__SHIFT 0x0
+#define UMCCH0_2_PerfMonCtl1__RdWrMask__SHIFT 0x8
+#define UMCCH0_2_PerfMonCtl1__PriorityMask__SHIFT 0xa
+#define UMCCH0_2_PerfMonCtl1__ReqSizeMask__SHIFT 0xe
+#define UMCCH0_2_PerfMonCtl1__BankSel__SHIFT 0x10
+#define UMCCH0_2_PerfMonCtl1__VCSel__SHIFT 0x18
+#define UMCCH0_2_PerfMonCtl1__SubChanMask__SHIFT 0x1d
+#define UMCCH0_2_PerfMonCtl1__Enable__SHIFT 0x1f
+#define UMCCH0_2_PerfMonCtl1__EventSelect_MASK 0x000000FFL
+#define UMCCH0_2_PerfMonCtl1__RdWrMask_MASK 0x00000300L
+#define UMCCH0_2_PerfMonCtl1__PriorityMask_MASK 0x00003C00L
+#define UMCCH0_2_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH0_2_PerfMonCtl1__BankSel_MASK 0x00FF0000L
+#define UMCCH0_2_PerfMonCtl1__VCSel_MASK 0x1F000000L
+#define UMCCH0_2_PerfMonCtl1__SubChanMask_MASK 0x60000000L
+#define UMCCH0_2_PerfMonCtl1__Enable_MASK 0x80000000L
+//UMCCH0_2_PerfMonCtr1_Lo
+#define UMCCH0_2_PerfMonCtr1_Lo__Data__SHIFT 0x0
+#define UMCCH0_2_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_2_PerfMonCtr1_Hi
+#define UMCCH0_2_PerfMonCtr1_Hi__Data__SHIFT 0x0
+#define UMCCH0_2_PerfMonCtr1_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_2_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH0_2_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH0_2_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_2_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L
+#define UMCCH0_2_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH0_2_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH0_2_PerfMonCtl2
+#define UMCCH0_2_PerfMonCtl2__EventSelect__SHIFT 0x0
+#define UMCCH0_2_PerfMonCtl2__RdWrMask__SHIFT 0x8
+#define UMCCH0_2_PerfMonCtl2__PriorityMask__SHIFT 0xa
+#define UMCCH0_2_PerfMonCtl2__ReqSizeMask__SHIFT 0xe
+#define UMCCH0_2_PerfMonCtl2__BankSel__SHIFT 0x10
+#define UMCCH0_2_PerfMonCtl2__VCSel__SHIFT 0x18
+#define UMCCH0_2_PerfMonCtl2__SubChanMask__SHIFT 0x1d
+#define UMCCH0_2_PerfMonCtl2__Enable__SHIFT 0x1f
+#define UMCCH0_2_PerfMonCtl2__EventSelect_MASK 0x000000FFL
+#define UMCCH0_2_PerfMonCtl2__RdWrMask_MASK 0x00000300L
+#define UMCCH0_2_PerfMonCtl2__PriorityMask_MASK 0x00003C00L
+#define UMCCH0_2_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH0_2_PerfMonCtl2__BankSel_MASK 0x00FF0000L
+#define UMCCH0_2_PerfMonCtl2__VCSel_MASK 0x1F000000L
+#define UMCCH0_2_PerfMonCtl2__SubChanMask_MASK 0x60000000L
+#define UMCCH0_2_PerfMonCtl2__Enable_MASK 0x80000000L
+//UMCCH0_2_PerfMonCtr2_Lo
+#define UMCCH0_2_PerfMonCtr2_Lo__Data__SHIFT 0x0
+#define UMCCH0_2_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_2_PerfMonCtr2_Hi
+#define UMCCH0_2_PerfMonCtr2_Hi__Data__SHIFT 0x0
+#define UMCCH0_2_PerfMonCtr2_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_2_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH0_2_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH0_2_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_2_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L
+#define UMCCH0_2_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH0_2_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH0_2_PerfMonCtl3
+#define UMCCH0_2_PerfMonCtl3__EventSelect__SHIFT 0x0
+#define UMCCH0_2_PerfMonCtl3__RdWrMask__SHIFT 0x8
+#define UMCCH0_2_PerfMonCtl3__PriorityMask__SHIFT 0xa
+#define UMCCH0_2_PerfMonCtl3__ReqSizeMask__SHIFT 0xe
+#define UMCCH0_2_PerfMonCtl3__BankSel__SHIFT 0x10
+#define UMCCH0_2_PerfMonCtl3__VCSel__SHIFT 0x18
+#define UMCCH0_2_PerfMonCtl3__SubChanMask__SHIFT 0x1d
+#define UMCCH0_2_PerfMonCtl3__Enable__SHIFT 0x1f
+#define UMCCH0_2_PerfMonCtl3__EventSelect_MASK 0x000000FFL
+#define UMCCH0_2_PerfMonCtl3__RdWrMask_MASK 0x00000300L
+#define UMCCH0_2_PerfMonCtl3__PriorityMask_MASK 0x00003C00L
+#define UMCCH0_2_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH0_2_PerfMonCtl3__BankSel_MASK 0x00FF0000L
+#define UMCCH0_2_PerfMonCtl3__VCSel_MASK 0x1F000000L
+#define UMCCH0_2_PerfMonCtl3__SubChanMask_MASK 0x60000000L
+#define UMCCH0_2_PerfMonCtl3__Enable_MASK 0x80000000L
+//UMCCH0_2_PerfMonCtr3_Lo
+#define UMCCH0_2_PerfMonCtr3_Lo__Data__SHIFT 0x0
+#define UMCCH0_2_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_2_PerfMonCtr3_Hi
+#define UMCCH0_2_PerfMonCtr3_Hi__Data__SHIFT 0x0
+#define UMCCH0_2_PerfMonCtr3_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_2_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH0_2_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH0_2_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_2_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L
+#define UMCCH0_2_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH0_2_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH0_2_PerfMonCtl4
+#define UMCCH0_2_PerfMonCtl4__EventSelect__SHIFT 0x0
+#define UMCCH0_2_PerfMonCtl4__RdWrMask__SHIFT 0x8
+#define UMCCH0_2_PerfMonCtl4__PriorityMask__SHIFT 0xa
+#define UMCCH0_2_PerfMonCtl4__ReqSizeMask__SHIFT 0xe
+#define UMCCH0_2_PerfMonCtl4__BankSel__SHIFT 0x10
+#define UMCCH0_2_PerfMonCtl4__VCSel__SHIFT 0x18
+#define UMCCH0_2_PerfMonCtl4__SubChanMask__SHIFT 0x1d
+#define UMCCH0_2_PerfMonCtl4__Enable__SHIFT 0x1f
+#define UMCCH0_2_PerfMonCtl4__EventSelect_MASK 0x000000FFL
+#define UMCCH0_2_PerfMonCtl4__RdWrMask_MASK 0x00000300L
+#define UMCCH0_2_PerfMonCtl4__PriorityMask_MASK 0x00003C00L
+#define UMCCH0_2_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH0_2_PerfMonCtl4__BankSel_MASK 0x00FF0000L
+#define UMCCH0_2_PerfMonCtl4__VCSel_MASK 0x1F000000L
+#define UMCCH0_2_PerfMonCtl4__SubChanMask_MASK 0x60000000L
+#define UMCCH0_2_PerfMonCtl4__Enable_MASK 0x80000000L
+//UMCCH0_2_PerfMonCtr4_Lo
+#define UMCCH0_2_PerfMonCtr4_Lo__Data__SHIFT 0x0
+#define UMCCH0_2_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_2_PerfMonCtr4_Hi
+#define UMCCH0_2_PerfMonCtr4_Hi__Data__SHIFT 0x0
+#define UMCCH0_2_PerfMonCtr4_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_2_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH0_2_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH0_2_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_2_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L
+#define UMCCH0_2_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH0_2_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH0_2_PerfMonCtl5
+#define UMCCH0_2_PerfMonCtl5__EventSelect__SHIFT 0x0
+#define UMCCH0_2_PerfMonCtl5__RdWrMask__SHIFT 0x8
+#define UMCCH0_2_PerfMonCtl5__PriorityMask__SHIFT 0xa
+#define UMCCH0_2_PerfMonCtl5__ReqSizeMask__SHIFT 0xe
+#define UMCCH0_2_PerfMonCtl5__BankSel__SHIFT 0x10
+#define UMCCH0_2_PerfMonCtl5__VCSel__SHIFT 0x18
+#define UMCCH0_2_PerfMonCtl5__SubChanMask__SHIFT 0x1d
+#define UMCCH0_2_PerfMonCtl5__Enable__SHIFT 0x1f
+#define UMCCH0_2_PerfMonCtl5__EventSelect_MASK 0x000000FFL
+#define UMCCH0_2_PerfMonCtl5__RdWrMask_MASK 0x00000300L
+#define UMCCH0_2_PerfMonCtl5__PriorityMask_MASK 0x00003C00L
+#define UMCCH0_2_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH0_2_PerfMonCtl5__BankSel_MASK 0x00FF0000L
+#define UMCCH0_2_PerfMonCtl5__VCSel_MASK 0x1F000000L
+#define UMCCH0_2_PerfMonCtl5__SubChanMask_MASK 0x60000000L
+#define UMCCH0_2_PerfMonCtl5__Enable_MASK 0x80000000L
+//UMCCH0_2_PerfMonCtr5_Lo
+#define UMCCH0_2_PerfMonCtr5_Lo__Data__SHIFT 0x0
+#define UMCCH0_2_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_2_PerfMonCtr5_Hi
+#define UMCCH0_2_PerfMonCtr5_Hi__Data__SHIFT 0x0
+#define UMCCH0_2_PerfMonCtr5_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_2_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH0_2_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH0_2_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_2_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L
+#define UMCCH0_2_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH0_2_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH0_2_PerfMonCtl6
+#define UMCCH0_2_PerfMonCtl6__EventSelect__SHIFT 0x0
+#define UMCCH0_2_PerfMonCtl6__RdWrMask__SHIFT 0x8
+#define UMCCH0_2_PerfMonCtl6__PriorityMask__SHIFT 0xa
+#define UMCCH0_2_PerfMonCtl6__ReqSizeMask__SHIFT 0xe
+#define UMCCH0_2_PerfMonCtl6__BankSel__SHIFT 0x10
+#define UMCCH0_2_PerfMonCtl6__VCSel__SHIFT 0x18
+#define UMCCH0_2_PerfMonCtl6__SubChanMask__SHIFT 0x1d
+#define UMCCH0_2_PerfMonCtl6__Enable__SHIFT 0x1f
+#define UMCCH0_2_PerfMonCtl6__EventSelect_MASK 0x000000FFL
+#define UMCCH0_2_PerfMonCtl6__RdWrMask_MASK 0x00000300L
+#define UMCCH0_2_PerfMonCtl6__PriorityMask_MASK 0x00003C00L
+#define UMCCH0_2_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH0_2_PerfMonCtl6__BankSel_MASK 0x00FF0000L
+#define UMCCH0_2_PerfMonCtl6__VCSel_MASK 0x1F000000L
+#define UMCCH0_2_PerfMonCtl6__SubChanMask_MASK 0x60000000L
+#define UMCCH0_2_PerfMonCtl6__Enable_MASK 0x80000000L
+//UMCCH0_2_PerfMonCtr6_Lo
+#define UMCCH0_2_PerfMonCtr6_Lo__Data__SHIFT 0x0
+#define UMCCH0_2_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_2_PerfMonCtr6_Hi
+#define UMCCH0_2_PerfMonCtr6_Hi__Data__SHIFT 0x0
+#define UMCCH0_2_PerfMonCtr6_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_2_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH0_2_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH0_2_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_2_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L
+#define UMCCH0_2_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH0_2_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH0_2_PerfMonCtl7
+#define UMCCH0_2_PerfMonCtl7__EventSelect__SHIFT 0x0
+#define UMCCH0_2_PerfMonCtl7__RdWrMask__SHIFT 0x8
+#define UMCCH0_2_PerfMonCtl7__PriorityMask__SHIFT 0xa
+#define UMCCH0_2_PerfMonCtl7__ReqSizeMask__SHIFT 0xe
+#define UMCCH0_2_PerfMonCtl7__BankSel__SHIFT 0x10
+#define UMCCH0_2_PerfMonCtl7__VCSel__SHIFT 0x18
+#define UMCCH0_2_PerfMonCtl7__SubChanMask__SHIFT 0x1d
+#define UMCCH0_2_PerfMonCtl7__Enable__SHIFT 0x1f
+#define UMCCH0_2_PerfMonCtl7__EventSelect_MASK 0x000000FFL
+#define UMCCH0_2_PerfMonCtl7__RdWrMask_MASK 0x00000300L
+#define UMCCH0_2_PerfMonCtl7__PriorityMask_MASK 0x00003C00L
+#define UMCCH0_2_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH0_2_PerfMonCtl7__BankSel_MASK 0x00FF0000L
+#define UMCCH0_2_PerfMonCtl7__VCSel_MASK 0x1F000000L
+#define UMCCH0_2_PerfMonCtl7__SubChanMask_MASK 0x60000000L
+#define UMCCH0_2_PerfMonCtl7__Enable_MASK 0x80000000L
+//UMCCH0_2_PerfMonCtr7_Lo
+#define UMCCH0_2_PerfMonCtr7_Lo__Data__SHIFT 0x0
+#define UMCCH0_2_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_2_PerfMonCtr7_Hi
+#define UMCCH0_2_PerfMonCtr7_Hi__Data__SHIFT 0x0
+#define UMCCH0_2_PerfMonCtr7_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_2_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH0_2_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH0_2_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_2_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L
+#define UMCCH0_2_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH0_2_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH0_2_PerfMonCtl8
+#define UMCCH0_2_PerfMonCtl8__EventSelect__SHIFT 0x0
+#define UMCCH0_2_PerfMonCtl8__RdWrMask__SHIFT 0x8
+#define UMCCH0_2_PerfMonCtl8__PriorityMask__SHIFT 0xa
+#define UMCCH0_2_PerfMonCtl8__ReqSizeMask__SHIFT 0xe
+#define UMCCH0_2_PerfMonCtl8__BankSel__SHIFT 0x10
+#define UMCCH0_2_PerfMonCtl8__VCSel__SHIFT 0x18
+#define UMCCH0_2_PerfMonCtl8__SubChanMask__SHIFT 0x1d
+#define UMCCH0_2_PerfMonCtl8__Enable__SHIFT 0x1f
+#define UMCCH0_2_PerfMonCtl8__EventSelect_MASK 0x000000FFL
+#define UMCCH0_2_PerfMonCtl8__RdWrMask_MASK 0x00000300L
+#define UMCCH0_2_PerfMonCtl8__PriorityMask_MASK 0x00003C00L
+#define UMCCH0_2_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH0_2_PerfMonCtl8__BankSel_MASK 0x00FF0000L
+#define UMCCH0_2_PerfMonCtl8__VCSel_MASK 0x1F000000L
+#define UMCCH0_2_PerfMonCtl8__SubChanMask_MASK 0x60000000L
+#define UMCCH0_2_PerfMonCtl8__Enable_MASK 0x80000000L
+//UMCCH0_2_PerfMonCtr8_Lo
+#define UMCCH0_2_PerfMonCtr8_Lo__Data__SHIFT 0x0
+#define UMCCH0_2_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_2_PerfMonCtr8_Hi
+#define UMCCH0_2_PerfMonCtr8_Hi__Data__SHIFT 0x0
+#define UMCCH0_2_PerfMonCtr8_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_2_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH0_2_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH0_2_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_2_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L
+#define UMCCH0_2_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH0_2_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L
+
+
+// addressBlock: umc_w_phy_umc2_umcch1_umcchdec
+//UMCCH1_2_BaseAddrCS0
+#define UMCCH1_2_BaseAddrCS0__CSEnable__SHIFT 0x0
+#define UMCCH1_2_BaseAddrCS0__BaseAddr__SHIFT 0x1
+#define UMCCH1_2_BaseAddrCS0__CSEnable_MASK 0x00000001L
+#define UMCCH1_2_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL
+//UMCCH1_2_AddrMaskCS01
+#define UMCCH1_2_AddrMaskCS01__AddrMask__SHIFT 0x1
+#define UMCCH1_2_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL
+//UMCCH1_2_AddrSelCS01
+#define UMCCH1_2_AddrSelCS01__BankBit0__SHIFT 0x0
+#define UMCCH1_2_AddrSelCS01__BankBit1__SHIFT 0x4
+#define UMCCH1_2_AddrSelCS01__BankBit2__SHIFT 0x8
+#define UMCCH1_2_AddrSelCS01__BankBit3__SHIFT 0xc
+#define UMCCH1_2_AddrSelCS01__BankBit4__SHIFT 0x10
+#define UMCCH1_2_AddrSelCS01__RowLo__SHIFT 0x18
+#define UMCCH1_2_AddrSelCS01__RowHi__SHIFT 0x1c
+#define UMCCH1_2_AddrSelCS01__BankBit0_MASK 0x0000000FL
+#define UMCCH1_2_AddrSelCS01__BankBit1_MASK 0x000000F0L
+#define UMCCH1_2_AddrSelCS01__BankBit2_MASK 0x00000F00L
+#define UMCCH1_2_AddrSelCS01__BankBit3_MASK 0x0000F000L
+#define UMCCH1_2_AddrSelCS01__BankBit4_MASK 0x001F0000L
+#define UMCCH1_2_AddrSelCS01__RowLo_MASK 0x0F000000L
+#define UMCCH1_2_AddrSelCS01__RowHi_MASK 0xF0000000L
+//UMCCH1_2_AddrHashBank0
+#define UMCCH1_2_AddrHashBank0__XorEnable__SHIFT 0x0
+#define UMCCH1_2_AddrHashBank0__ColXor__SHIFT 0x1
+#define UMCCH1_2_AddrHashBank0__RowXor__SHIFT 0xe
+#define UMCCH1_2_AddrHashBank0__XorEnable_MASK 0x00000001L
+#define UMCCH1_2_AddrHashBank0__ColXor_MASK 0x00003FFEL
+#define UMCCH1_2_AddrHashBank0__RowXor_MASK 0xFFFFC000L
+//UMCCH1_2_AddrHashBank1
+#define UMCCH1_2_AddrHashBank1__XorEnable__SHIFT 0x0
+#define UMCCH1_2_AddrHashBank1__ColXor__SHIFT 0x1
+#define UMCCH1_2_AddrHashBank1__RowXor__SHIFT 0xe
+#define UMCCH1_2_AddrHashBank1__XorEnable_MASK 0x00000001L
+#define UMCCH1_2_AddrHashBank1__ColXor_MASK 0x00003FFEL
+#define UMCCH1_2_AddrHashBank1__RowXor_MASK 0xFFFFC000L
+//UMCCH1_2_AddrHashBank2
+#define UMCCH1_2_AddrHashBank2__XorEnable__SHIFT 0x0
+#define UMCCH1_2_AddrHashBank2__ColXor__SHIFT 0x1
+#define UMCCH1_2_AddrHashBank2__RowXor__SHIFT 0xe
+#define UMCCH1_2_AddrHashBank2__XorEnable_MASK 0x00000001L
+#define UMCCH1_2_AddrHashBank2__ColXor_MASK 0x00003FFEL
+#define UMCCH1_2_AddrHashBank2__RowXor_MASK 0xFFFFC000L
+//UMCCH1_2_AddrHashBank3
+#define UMCCH1_2_AddrHashBank3__XorEnable__SHIFT 0x0
+#define UMCCH1_2_AddrHashBank3__ColXor__SHIFT 0x1
+#define UMCCH1_2_AddrHashBank3__RowXor__SHIFT 0xe
+#define UMCCH1_2_AddrHashBank3__XorEnable_MASK 0x00000001L
+#define UMCCH1_2_AddrHashBank3__ColXor_MASK 0x00003FFEL
+#define UMCCH1_2_AddrHashBank3__RowXor_MASK 0xFFFFC000L
+//UMCCH1_2_AddrHashBank4
+#define UMCCH1_2_AddrHashBank4__XorEnable__SHIFT 0x0
+#define UMCCH1_2_AddrHashBank4__ColXor__SHIFT 0x1
+#define UMCCH1_2_AddrHashBank4__RowXor__SHIFT 0xe
+#define UMCCH1_2_AddrHashBank4__XorEnable_MASK 0x00000001L
+#define UMCCH1_2_AddrHashBank4__ColXor_MASK 0x00003FFEL
+#define UMCCH1_2_AddrHashBank4__RowXor_MASK 0xFFFFC000L
+//UMCCH1_2_AddrHashBank5
+#define UMCCH1_2_AddrHashBank5__XorEnable__SHIFT 0x0
+#define UMCCH1_2_AddrHashBank5__ColXor__SHIFT 0x1
+#define UMCCH1_2_AddrHashBank5__RowXor__SHIFT 0xe
+#define UMCCH1_2_AddrHashBank5__XorEnable_MASK 0x00000001L
+#define UMCCH1_2_AddrHashBank5__ColXor_MASK 0x00003FFEL
+#define UMCCH1_2_AddrHashBank5__RowXor_MASK 0xFFFFC000L
+//UMCCH1_2_EccErrCntSel
+#define UMCCH1_2_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0
+#define UMCCH1_2_EccErrCntSel__EccErrInt__SHIFT 0xc
+#define UMCCH1_2_EccErrCntSel__EccErrCntEn__SHIFT 0xf
+#define UMCCH1_2_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL
+#define UMCCH1_2_EccErrCntSel__EccErrInt_MASK 0x00003000L
+#define UMCCH1_2_EccErrCntSel__EccErrCntEn_MASK 0x00008000L
+//UMCCH1_2_EccErrCnt
+#define UMCCH1_2_EccErrCnt__EccErrCnt__SHIFT 0x0
+#define UMCCH1_2_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL
+//UMCCH1_2_PerfMonCtlClk
+#define UMCCH1_2_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0
+#define UMCCH1_2_PerfMonCtlClk__ClkGate__SHIFT 0x16
+#define UMCCH1_2_PerfMonCtlClk__GlblReset__SHIFT 0x18
+#define UMCCH1_2_PerfMonCtlClk__GlblMonEn__SHIFT 0x19
+#define UMCCH1_2_PerfMonCtlClk__NumCounters__SHIFT 0x1a
+#define UMCCH1_2_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f
+#define UMCCH1_2_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL
+#define UMCCH1_2_PerfMonCtlClk__ClkGate_MASK 0x00400000L
+#define UMCCH1_2_PerfMonCtlClk__GlblReset_MASK 0x01000000L
+#define UMCCH1_2_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L
+#define UMCCH1_2_PerfMonCtlClk__NumCounters_MASK 0x3C000000L
+#define UMCCH1_2_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L
+//UMCCH1_2_PerfMonCtrClk_Lo
+#define UMCCH1_2_PerfMonCtrClk_Lo__Data__SHIFT 0x0
+#define UMCCH1_2_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_2_PerfMonCtrClk_Hi
+#define UMCCH1_2_PerfMonCtrClk_Hi__Data__SHIFT 0x0
+#define UMCCH1_2_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_2_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_2_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L
+//UMCCH1_2_PerfMonCtl1
+#define UMCCH1_2_PerfMonCtl1__EventSelect__SHIFT 0x0
+#define UMCCH1_2_PerfMonCtl1__RdWrMask__SHIFT 0x8
+#define UMCCH1_2_PerfMonCtl1__PriorityMask__SHIFT 0xa
+#define UMCCH1_2_PerfMonCtl1__ReqSizeMask__SHIFT 0xe
+#define UMCCH1_2_PerfMonCtl1__BankSel__SHIFT 0x10
+#define UMCCH1_2_PerfMonCtl1__VCSel__SHIFT 0x18
+#define UMCCH1_2_PerfMonCtl1__SubChanMask__SHIFT 0x1d
+#define UMCCH1_2_PerfMonCtl1__Enable__SHIFT 0x1f
+#define UMCCH1_2_PerfMonCtl1__EventSelect_MASK 0x000000FFL
+#define UMCCH1_2_PerfMonCtl1__RdWrMask_MASK 0x00000300L
+#define UMCCH1_2_PerfMonCtl1__PriorityMask_MASK 0x00003C00L
+#define UMCCH1_2_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH1_2_PerfMonCtl1__BankSel_MASK 0x00FF0000L
+#define UMCCH1_2_PerfMonCtl1__VCSel_MASK 0x1F000000L
+#define UMCCH1_2_PerfMonCtl1__SubChanMask_MASK 0x60000000L
+#define UMCCH1_2_PerfMonCtl1__Enable_MASK 0x80000000L
+//UMCCH1_2_PerfMonCtr1_Lo
+#define UMCCH1_2_PerfMonCtr1_Lo__Data__SHIFT 0x0
+#define UMCCH1_2_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_2_PerfMonCtr1_Hi
+#define UMCCH1_2_PerfMonCtr1_Hi__Data__SHIFT 0x0
+#define UMCCH1_2_PerfMonCtr1_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_2_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH1_2_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH1_2_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_2_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L
+#define UMCCH1_2_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH1_2_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH1_2_PerfMonCtl2
+#define UMCCH1_2_PerfMonCtl2__EventSelect__SHIFT 0x0
+#define UMCCH1_2_PerfMonCtl2__RdWrMask__SHIFT 0x8
+#define UMCCH1_2_PerfMonCtl2__PriorityMask__SHIFT 0xa
+#define UMCCH1_2_PerfMonCtl2__ReqSizeMask__SHIFT 0xe
+#define UMCCH1_2_PerfMonCtl2__BankSel__SHIFT 0x10
+#define UMCCH1_2_PerfMonCtl2__VCSel__SHIFT 0x18
+#define UMCCH1_2_PerfMonCtl2__SubChanMask__SHIFT 0x1d
+#define UMCCH1_2_PerfMonCtl2__Enable__SHIFT 0x1f
+#define UMCCH1_2_PerfMonCtl2__EventSelect_MASK 0x000000FFL
+#define UMCCH1_2_PerfMonCtl2__RdWrMask_MASK 0x00000300L
+#define UMCCH1_2_PerfMonCtl2__PriorityMask_MASK 0x00003C00L
+#define UMCCH1_2_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH1_2_PerfMonCtl2__BankSel_MASK 0x00FF0000L
+#define UMCCH1_2_PerfMonCtl2__VCSel_MASK 0x1F000000L
+#define UMCCH1_2_PerfMonCtl2__SubChanMask_MASK 0x60000000L
+#define UMCCH1_2_PerfMonCtl2__Enable_MASK 0x80000000L
+//UMCCH1_2_PerfMonCtr2_Lo
+#define UMCCH1_2_PerfMonCtr2_Lo__Data__SHIFT 0x0
+#define UMCCH1_2_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_2_PerfMonCtr2_Hi
+#define UMCCH1_2_PerfMonCtr2_Hi__Data__SHIFT 0x0
+#define UMCCH1_2_PerfMonCtr2_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_2_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH1_2_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH1_2_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_2_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L
+#define UMCCH1_2_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH1_2_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH1_2_PerfMonCtl3
+#define UMCCH1_2_PerfMonCtl3__EventSelect__SHIFT 0x0
+#define UMCCH1_2_PerfMonCtl3__RdWrMask__SHIFT 0x8
+#define UMCCH1_2_PerfMonCtl3__PriorityMask__SHIFT 0xa
+#define UMCCH1_2_PerfMonCtl3__ReqSizeMask__SHIFT 0xe
+#define UMCCH1_2_PerfMonCtl3__BankSel__SHIFT 0x10
+#define UMCCH1_2_PerfMonCtl3__VCSel__SHIFT 0x18
+#define UMCCH1_2_PerfMonCtl3__SubChanMask__SHIFT 0x1d
+#define UMCCH1_2_PerfMonCtl3__Enable__SHIFT 0x1f
+#define UMCCH1_2_PerfMonCtl3__EventSelect_MASK 0x000000FFL
+#define UMCCH1_2_PerfMonCtl3__RdWrMask_MASK 0x00000300L
+#define UMCCH1_2_PerfMonCtl3__PriorityMask_MASK 0x00003C00L
+#define UMCCH1_2_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH1_2_PerfMonCtl3__BankSel_MASK 0x00FF0000L
+#define UMCCH1_2_PerfMonCtl3__VCSel_MASK 0x1F000000L
+#define UMCCH1_2_PerfMonCtl3__SubChanMask_MASK 0x60000000L
+#define UMCCH1_2_PerfMonCtl3__Enable_MASK 0x80000000L
+//UMCCH1_2_PerfMonCtr3_Lo
+#define UMCCH1_2_PerfMonCtr3_Lo__Data__SHIFT 0x0
+#define UMCCH1_2_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_2_PerfMonCtr3_Hi
+#define UMCCH1_2_PerfMonCtr3_Hi__Data__SHIFT 0x0
+#define UMCCH1_2_PerfMonCtr3_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_2_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH1_2_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH1_2_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_2_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L
+#define UMCCH1_2_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH1_2_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH1_2_PerfMonCtl4
+#define UMCCH1_2_PerfMonCtl4__EventSelect__SHIFT 0x0
+#define UMCCH1_2_PerfMonCtl4__RdWrMask__SHIFT 0x8
+#define UMCCH1_2_PerfMonCtl4__PriorityMask__SHIFT 0xa
+#define UMCCH1_2_PerfMonCtl4__ReqSizeMask__SHIFT 0xe
+#define UMCCH1_2_PerfMonCtl4__BankSel__SHIFT 0x10
+#define UMCCH1_2_PerfMonCtl4__VCSel__SHIFT 0x18
+#define UMCCH1_2_PerfMonCtl4__SubChanMask__SHIFT 0x1d
+#define UMCCH1_2_PerfMonCtl4__Enable__SHIFT 0x1f
+#define UMCCH1_2_PerfMonCtl4__EventSelect_MASK 0x000000FFL
+#define UMCCH1_2_PerfMonCtl4__RdWrMask_MASK 0x00000300L
+#define UMCCH1_2_PerfMonCtl4__PriorityMask_MASK 0x00003C00L
+#define UMCCH1_2_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH1_2_PerfMonCtl4__BankSel_MASK 0x00FF0000L
+#define UMCCH1_2_PerfMonCtl4__VCSel_MASK 0x1F000000L
+#define UMCCH1_2_PerfMonCtl4__SubChanMask_MASK 0x60000000L
+#define UMCCH1_2_PerfMonCtl4__Enable_MASK 0x80000000L
+//UMCCH1_2_PerfMonCtr4_Lo
+#define UMCCH1_2_PerfMonCtr4_Lo__Data__SHIFT 0x0
+#define UMCCH1_2_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_2_PerfMonCtr4_Hi
+#define UMCCH1_2_PerfMonCtr4_Hi__Data__SHIFT 0x0
+#define UMCCH1_2_PerfMonCtr4_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_2_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH1_2_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH1_2_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_2_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L
+#define UMCCH1_2_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH1_2_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH1_2_PerfMonCtl5
+#define UMCCH1_2_PerfMonCtl5__EventSelect__SHIFT 0x0
+#define UMCCH1_2_PerfMonCtl5__RdWrMask__SHIFT 0x8
+#define UMCCH1_2_PerfMonCtl5__PriorityMask__SHIFT 0xa
+#define UMCCH1_2_PerfMonCtl5__ReqSizeMask__SHIFT 0xe
+#define UMCCH1_2_PerfMonCtl5__BankSel__SHIFT 0x10
+#define UMCCH1_2_PerfMonCtl5__VCSel__SHIFT 0x18
+#define UMCCH1_2_PerfMonCtl5__SubChanMask__SHIFT 0x1d
+#define UMCCH1_2_PerfMonCtl5__Enable__SHIFT 0x1f
+#define UMCCH1_2_PerfMonCtl5__EventSelect_MASK 0x000000FFL
+#define UMCCH1_2_PerfMonCtl5__RdWrMask_MASK 0x00000300L
+#define UMCCH1_2_PerfMonCtl5__PriorityMask_MASK 0x00003C00L
+#define UMCCH1_2_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH1_2_PerfMonCtl5__BankSel_MASK 0x00FF0000L
+#define UMCCH1_2_PerfMonCtl5__VCSel_MASK 0x1F000000L
+#define UMCCH1_2_PerfMonCtl5__SubChanMask_MASK 0x60000000L
+#define UMCCH1_2_PerfMonCtl5__Enable_MASK 0x80000000L
+//UMCCH1_2_PerfMonCtr5_Lo
+#define UMCCH1_2_PerfMonCtr5_Lo__Data__SHIFT 0x0
+#define UMCCH1_2_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_2_PerfMonCtr5_Hi
+#define UMCCH1_2_PerfMonCtr5_Hi__Data__SHIFT 0x0
+#define UMCCH1_2_PerfMonCtr5_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_2_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH1_2_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH1_2_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_2_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L
+#define UMCCH1_2_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH1_2_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH1_2_PerfMonCtl6
+#define UMCCH1_2_PerfMonCtl6__EventSelect__SHIFT 0x0
+#define UMCCH1_2_PerfMonCtl6__RdWrMask__SHIFT 0x8
+#define UMCCH1_2_PerfMonCtl6__PriorityMask__SHIFT 0xa
+#define UMCCH1_2_PerfMonCtl6__ReqSizeMask__SHIFT 0xe
+#define UMCCH1_2_PerfMonCtl6__BankSel__SHIFT 0x10
+#define UMCCH1_2_PerfMonCtl6__VCSel__SHIFT 0x18
+#define UMCCH1_2_PerfMonCtl6__SubChanMask__SHIFT 0x1d
+#define UMCCH1_2_PerfMonCtl6__Enable__SHIFT 0x1f
+#define UMCCH1_2_PerfMonCtl6__EventSelect_MASK 0x000000FFL
+#define UMCCH1_2_PerfMonCtl6__RdWrMask_MASK 0x00000300L
+#define UMCCH1_2_PerfMonCtl6__PriorityMask_MASK 0x00003C00L
+#define UMCCH1_2_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH1_2_PerfMonCtl6__BankSel_MASK 0x00FF0000L
+#define UMCCH1_2_PerfMonCtl6__VCSel_MASK 0x1F000000L
+#define UMCCH1_2_PerfMonCtl6__SubChanMask_MASK 0x60000000L
+#define UMCCH1_2_PerfMonCtl6__Enable_MASK 0x80000000L
+//UMCCH1_2_PerfMonCtr6_Lo
+#define UMCCH1_2_PerfMonCtr6_Lo__Data__SHIFT 0x0
+#define UMCCH1_2_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_2_PerfMonCtr6_Hi
+#define UMCCH1_2_PerfMonCtr6_Hi__Data__SHIFT 0x0
+#define UMCCH1_2_PerfMonCtr6_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_2_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH1_2_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH1_2_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_2_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L
+#define UMCCH1_2_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH1_2_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH1_2_PerfMonCtl7
+#define UMCCH1_2_PerfMonCtl7__EventSelect__SHIFT 0x0
+#define UMCCH1_2_PerfMonCtl7__RdWrMask__SHIFT 0x8
+#define UMCCH1_2_PerfMonCtl7__PriorityMask__SHIFT 0xa
+#define UMCCH1_2_PerfMonCtl7__ReqSizeMask__SHIFT 0xe
+#define UMCCH1_2_PerfMonCtl7__BankSel__SHIFT 0x10
+#define UMCCH1_2_PerfMonCtl7__VCSel__SHIFT 0x18
+#define UMCCH1_2_PerfMonCtl7__SubChanMask__SHIFT 0x1d
+#define UMCCH1_2_PerfMonCtl7__Enable__SHIFT 0x1f
+#define UMCCH1_2_PerfMonCtl7__EventSelect_MASK 0x000000FFL
+#define UMCCH1_2_PerfMonCtl7__RdWrMask_MASK 0x00000300L
+#define UMCCH1_2_PerfMonCtl7__PriorityMask_MASK 0x00003C00L
+#define UMCCH1_2_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH1_2_PerfMonCtl7__BankSel_MASK 0x00FF0000L
+#define UMCCH1_2_PerfMonCtl7__VCSel_MASK 0x1F000000L
+#define UMCCH1_2_PerfMonCtl7__SubChanMask_MASK 0x60000000L
+#define UMCCH1_2_PerfMonCtl7__Enable_MASK 0x80000000L
+//UMCCH1_2_PerfMonCtr7_Lo
+#define UMCCH1_2_PerfMonCtr7_Lo__Data__SHIFT 0x0
+#define UMCCH1_2_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_2_PerfMonCtr7_Hi
+#define UMCCH1_2_PerfMonCtr7_Hi__Data__SHIFT 0x0
+#define UMCCH1_2_PerfMonCtr7_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_2_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH1_2_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH1_2_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_2_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L
+#define UMCCH1_2_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH1_2_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH1_2_PerfMonCtl8
+#define UMCCH1_2_PerfMonCtl8__EventSelect__SHIFT 0x0
+#define UMCCH1_2_PerfMonCtl8__RdWrMask__SHIFT 0x8
+#define UMCCH1_2_PerfMonCtl8__PriorityMask__SHIFT 0xa
+#define UMCCH1_2_PerfMonCtl8__ReqSizeMask__SHIFT 0xe
+#define UMCCH1_2_PerfMonCtl8__BankSel__SHIFT 0x10
+#define UMCCH1_2_PerfMonCtl8__VCSel__SHIFT 0x18
+#define UMCCH1_2_PerfMonCtl8__SubChanMask__SHIFT 0x1d
+#define UMCCH1_2_PerfMonCtl8__Enable__SHIFT 0x1f
+#define UMCCH1_2_PerfMonCtl8__EventSelect_MASK 0x000000FFL
+#define UMCCH1_2_PerfMonCtl8__RdWrMask_MASK 0x00000300L
+#define UMCCH1_2_PerfMonCtl8__PriorityMask_MASK 0x00003C00L
+#define UMCCH1_2_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH1_2_PerfMonCtl8__BankSel_MASK 0x00FF0000L
+#define UMCCH1_2_PerfMonCtl8__VCSel_MASK 0x1F000000L
+#define UMCCH1_2_PerfMonCtl8__SubChanMask_MASK 0x60000000L
+#define UMCCH1_2_PerfMonCtl8__Enable_MASK 0x80000000L
+//UMCCH1_2_PerfMonCtr8_Lo
+#define UMCCH1_2_PerfMonCtr8_Lo__Data__SHIFT 0x0
+#define UMCCH1_2_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_2_PerfMonCtr8_Hi
+#define UMCCH1_2_PerfMonCtr8_Hi__Data__SHIFT 0x0
+#define UMCCH1_2_PerfMonCtr8_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_2_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH1_2_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH1_2_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_2_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L
+#define UMCCH1_2_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH1_2_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L
+
+
+// addressBlock: umc_w_phy_umc2_umcch2_umcchdec
+//UMCCH2_2_BaseAddrCS0
+#define UMCCH2_2_BaseAddrCS0__CSEnable__SHIFT 0x0
+#define UMCCH2_2_BaseAddrCS0__BaseAddr__SHIFT 0x1
+#define UMCCH2_2_BaseAddrCS0__CSEnable_MASK 0x00000001L
+#define UMCCH2_2_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL
+//UMCCH2_2_AddrMaskCS01
+#define UMCCH2_2_AddrMaskCS01__AddrMask__SHIFT 0x1
+#define UMCCH2_2_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL
+//UMCCH2_2_AddrSelCS01
+#define UMCCH2_2_AddrSelCS01__BankBit0__SHIFT 0x0
+#define UMCCH2_2_AddrSelCS01__BankBit1__SHIFT 0x4
+#define UMCCH2_2_AddrSelCS01__BankBit2__SHIFT 0x8
+#define UMCCH2_2_AddrSelCS01__BankBit3__SHIFT 0xc
+#define UMCCH2_2_AddrSelCS01__BankBit4__SHIFT 0x10
+#define UMCCH2_2_AddrSelCS01__RowLo__SHIFT 0x18
+#define UMCCH2_2_AddrSelCS01__RowHi__SHIFT 0x1c
+#define UMCCH2_2_AddrSelCS01__BankBit0_MASK 0x0000000FL
+#define UMCCH2_2_AddrSelCS01__BankBit1_MASK 0x000000F0L
+#define UMCCH2_2_AddrSelCS01__BankBit2_MASK 0x00000F00L
+#define UMCCH2_2_AddrSelCS01__BankBit3_MASK 0x0000F000L
+#define UMCCH2_2_AddrSelCS01__BankBit4_MASK 0x001F0000L
+#define UMCCH2_2_AddrSelCS01__RowLo_MASK 0x0F000000L
+#define UMCCH2_2_AddrSelCS01__RowHi_MASK 0xF0000000L
+//UMCCH2_2_AddrHashBank0
+#define UMCCH2_2_AddrHashBank0__XorEnable__SHIFT 0x0
+#define UMCCH2_2_AddrHashBank0__ColXor__SHIFT 0x1
+#define UMCCH2_2_AddrHashBank0__RowXor__SHIFT 0xe
+#define UMCCH2_2_AddrHashBank0__XorEnable_MASK 0x00000001L
+#define UMCCH2_2_AddrHashBank0__ColXor_MASK 0x00003FFEL
+#define UMCCH2_2_AddrHashBank0__RowXor_MASK 0xFFFFC000L
+//UMCCH2_2_AddrHashBank1
+#define UMCCH2_2_AddrHashBank1__XorEnable__SHIFT 0x0
+#define UMCCH2_2_AddrHashBank1__ColXor__SHIFT 0x1
+#define UMCCH2_2_AddrHashBank1__RowXor__SHIFT 0xe
+#define UMCCH2_2_AddrHashBank1__XorEnable_MASK 0x00000001L
+#define UMCCH2_2_AddrHashBank1__ColXor_MASK 0x00003FFEL
+#define UMCCH2_2_AddrHashBank1__RowXor_MASK 0xFFFFC000L
+//UMCCH2_2_AddrHashBank2
+#define UMCCH2_2_AddrHashBank2__XorEnable__SHIFT 0x0
+#define UMCCH2_2_AddrHashBank2__ColXor__SHIFT 0x1
+#define UMCCH2_2_AddrHashBank2__RowXor__SHIFT 0xe
+#define UMCCH2_2_AddrHashBank2__XorEnable_MASK 0x00000001L
+#define UMCCH2_2_AddrHashBank2__ColXor_MASK 0x00003FFEL
+#define UMCCH2_2_AddrHashBank2__RowXor_MASK 0xFFFFC000L
+//UMCCH2_2_AddrHashBank3
+#define UMCCH2_2_AddrHashBank3__XorEnable__SHIFT 0x0
+#define UMCCH2_2_AddrHashBank3__ColXor__SHIFT 0x1
+#define UMCCH2_2_AddrHashBank3__RowXor__SHIFT 0xe
+#define UMCCH2_2_AddrHashBank3__XorEnable_MASK 0x00000001L
+#define UMCCH2_2_AddrHashBank3__ColXor_MASK 0x00003FFEL
+#define UMCCH2_2_AddrHashBank3__RowXor_MASK 0xFFFFC000L
+//UMCCH2_2_AddrHashBank4
+#define UMCCH2_2_AddrHashBank4__XorEnable__SHIFT 0x0
+#define UMCCH2_2_AddrHashBank4__ColXor__SHIFT 0x1
+#define UMCCH2_2_AddrHashBank4__RowXor__SHIFT 0xe
+#define UMCCH2_2_AddrHashBank4__XorEnable_MASK 0x00000001L
+#define UMCCH2_2_AddrHashBank4__ColXor_MASK 0x00003FFEL
+#define UMCCH2_2_AddrHashBank4__RowXor_MASK 0xFFFFC000L
+//UMCCH2_2_AddrHashBank5
+#define UMCCH2_2_AddrHashBank5__XorEnable__SHIFT 0x0
+#define UMCCH2_2_AddrHashBank5__ColXor__SHIFT 0x1
+#define UMCCH2_2_AddrHashBank5__RowXor__SHIFT 0xe
+#define UMCCH2_2_AddrHashBank5__XorEnable_MASK 0x00000001L
+#define UMCCH2_2_AddrHashBank5__ColXor_MASK 0x00003FFEL
+#define UMCCH2_2_AddrHashBank5__RowXor_MASK 0xFFFFC000L
+//UMCCH2_2_EccErrCntSel
+#define UMCCH2_2_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0
+#define UMCCH2_2_EccErrCntSel__EccErrInt__SHIFT 0xc
+#define UMCCH2_2_EccErrCntSel__EccErrCntEn__SHIFT 0xf
+#define UMCCH2_2_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL
+#define UMCCH2_2_EccErrCntSel__EccErrInt_MASK 0x00003000L
+#define UMCCH2_2_EccErrCntSel__EccErrCntEn_MASK 0x00008000L
+//UMCCH2_2_EccErrCnt
+#define UMCCH2_2_EccErrCnt__EccErrCnt__SHIFT 0x0
+#define UMCCH2_2_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL
+//UMCCH2_2_PerfMonCtlClk
+#define UMCCH2_2_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0
+#define UMCCH2_2_PerfMonCtlClk__ClkGate__SHIFT 0x16
+#define UMCCH2_2_PerfMonCtlClk__GlblReset__SHIFT 0x18
+#define UMCCH2_2_PerfMonCtlClk__GlblMonEn__SHIFT 0x19
+#define UMCCH2_2_PerfMonCtlClk__NumCounters__SHIFT 0x1a
+#define UMCCH2_2_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f
+#define UMCCH2_2_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL
+#define UMCCH2_2_PerfMonCtlClk__ClkGate_MASK 0x00400000L
+#define UMCCH2_2_PerfMonCtlClk__GlblReset_MASK 0x01000000L
+#define UMCCH2_2_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L
+#define UMCCH2_2_PerfMonCtlClk__NumCounters_MASK 0x3C000000L
+#define UMCCH2_2_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L
+//UMCCH2_2_PerfMonCtrClk_Lo
+#define UMCCH2_2_PerfMonCtrClk_Lo__Data__SHIFT 0x0
+#define UMCCH2_2_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_2_PerfMonCtrClk_Hi
+#define UMCCH2_2_PerfMonCtrClk_Hi__Data__SHIFT 0x0
+#define UMCCH2_2_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_2_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_2_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L
+//UMCCH2_2_PerfMonCtl1
+#define UMCCH2_2_PerfMonCtl1__EventSelect__SHIFT 0x0
+#define UMCCH2_2_PerfMonCtl1__RdWrMask__SHIFT 0x8
+#define UMCCH2_2_PerfMonCtl1__PriorityMask__SHIFT 0xa
+#define UMCCH2_2_PerfMonCtl1__ReqSizeMask__SHIFT 0xe
+#define UMCCH2_2_PerfMonCtl1__BankSel__SHIFT 0x10
+#define UMCCH2_2_PerfMonCtl1__VCSel__SHIFT 0x18
+#define UMCCH2_2_PerfMonCtl1__SubChanMask__SHIFT 0x1d
+#define UMCCH2_2_PerfMonCtl1__Enable__SHIFT 0x1f
+#define UMCCH2_2_PerfMonCtl1__EventSelect_MASK 0x000000FFL
+#define UMCCH2_2_PerfMonCtl1__RdWrMask_MASK 0x00000300L
+#define UMCCH2_2_PerfMonCtl1__PriorityMask_MASK 0x00003C00L
+#define UMCCH2_2_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH2_2_PerfMonCtl1__BankSel_MASK 0x00FF0000L
+#define UMCCH2_2_PerfMonCtl1__VCSel_MASK 0x1F000000L
+#define UMCCH2_2_PerfMonCtl1__SubChanMask_MASK 0x60000000L
+#define UMCCH2_2_PerfMonCtl1__Enable_MASK 0x80000000L
+//UMCCH2_2_PerfMonCtr1_Lo
+#define UMCCH2_2_PerfMonCtr1_Lo__Data__SHIFT 0x0
+#define UMCCH2_2_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_2_PerfMonCtr1_Hi
+#define UMCCH2_2_PerfMonCtr1_Hi__Data__SHIFT 0x0
+#define UMCCH2_2_PerfMonCtr1_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_2_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH2_2_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH2_2_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_2_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L
+#define UMCCH2_2_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH2_2_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH2_2_PerfMonCtl2
+#define UMCCH2_2_PerfMonCtl2__EventSelect__SHIFT 0x0
+#define UMCCH2_2_PerfMonCtl2__RdWrMask__SHIFT 0x8
+#define UMCCH2_2_PerfMonCtl2__PriorityMask__SHIFT 0xa
+#define UMCCH2_2_PerfMonCtl2__ReqSizeMask__SHIFT 0xe
+#define UMCCH2_2_PerfMonCtl2__BankSel__SHIFT 0x10
+#define UMCCH2_2_PerfMonCtl2__VCSel__SHIFT 0x18
+#define UMCCH2_2_PerfMonCtl2__SubChanMask__SHIFT 0x1d
+#define UMCCH2_2_PerfMonCtl2__Enable__SHIFT 0x1f
+#define UMCCH2_2_PerfMonCtl2__EventSelect_MASK 0x000000FFL
+#define UMCCH2_2_PerfMonCtl2__RdWrMask_MASK 0x00000300L
+#define UMCCH2_2_PerfMonCtl2__PriorityMask_MASK 0x00003C00L
+#define UMCCH2_2_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH2_2_PerfMonCtl2__BankSel_MASK 0x00FF0000L
+#define UMCCH2_2_PerfMonCtl2__VCSel_MASK 0x1F000000L
+#define UMCCH2_2_PerfMonCtl2__SubChanMask_MASK 0x60000000L
+#define UMCCH2_2_PerfMonCtl2__Enable_MASK 0x80000000L
+//UMCCH2_2_PerfMonCtr2_Lo
+#define UMCCH2_2_PerfMonCtr2_Lo__Data__SHIFT 0x0
+#define UMCCH2_2_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_2_PerfMonCtr2_Hi
+#define UMCCH2_2_PerfMonCtr2_Hi__Data__SHIFT 0x0
+#define UMCCH2_2_PerfMonCtr2_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_2_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH2_2_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH2_2_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_2_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L
+#define UMCCH2_2_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH2_2_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH2_2_PerfMonCtl3
+#define UMCCH2_2_PerfMonCtl3__EventSelect__SHIFT 0x0
+#define UMCCH2_2_PerfMonCtl3__RdWrMask__SHIFT 0x8
+#define UMCCH2_2_PerfMonCtl3__PriorityMask__SHIFT 0xa
+#define UMCCH2_2_PerfMonCtl3__ReqSizeMask__SHIFT 0xe
+#define UMCCH2_2_PerfMonCtl3__BankSel__SHIFT 0x10
+#define UMCCH2_2_PerfMonCtl3__VCSel__SHIFT 0x18
+#define UMCCH2_2_PerfMonCtl3__SubChanMask__SHIFT 0x1d
+#define UMCCH2_2_PerfMonCtl3__Enable__SHIFT 0x1f
+#define UMCCH2_2_PerfMonCtl3__EventSelect_MASK 0x000000FFL
+#define UMCCH2_2_PerfMonCtl3__RdWrMask_MASK 0x00000300L
+#define UMCCH2_2_PerfMonCtl3__PriorityMask_MASK 0x00003C00L
+#define UMCCH2_2_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH2_2_PerfMonCtl3__BankSel_MASK 0x00FF0000L
+#define UMCCH2_2_PerfMonCtl3__VCSel_MASK 0x1F000000L
+#define UMCCH2_2_PerfMonCtl3__SubChanMask_MASK 0x60000000L
+#define UMCCH2_2_PerfMonCtl3__Enable_MASK 0x80000000L
+//UMCCH2_2_PerfMonCtr3_Lo
+#define UMCCH2_2_PerfMonCtr3_Lo__Data__SHIFT 0x0
+#define UMCCH2_2_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_2_PerfMonCtr3_Hi
+#define UMCCH2_2_PerfMonCtr3_Hi__Data__SHIFT 0x0
+#define UMCCH2_2_PerfMonCtr3_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_2_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH2_2_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH2_2_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_2_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L
+#define UMCCH2_2_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH2_2_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH2_2_PerfMonCtl4
+#define UMCCH2_2_PerfMonCtl4__EventSelect__SHIFT 0x0
+#define UMCCH2_2_PerfMonCtl4__RdWrMask__SHIFT 0x8
+#define UMCCH2_2_PerfMonCtl4__PriorityMask__SHIFT 0xa
+#define UMCCH2_2_PerfMonCtl4__ReqSizeMask__SHIFT 0xe
+#define UMCCH2_2_PerfMonCtl4__BankSel__SHIFT 0x10
+#define UMCCH2_2_PerfMonCtl4__VCSel__SHIFT 0x18
+#define UMCCH2_2_PerfMonCtl4__SubChanMask__SHIFT 0x1d
+#define UMCCH2_2_PerfMonCtl4__Enable__SHIFT 0x1f
+#define UMCCH2_2_PerfMonCtl4__EventSelect_MASK 0x000000FFL
+#define UMCCH2_2_PerfMonCtl4__RdWrMask_MASK 0x00000300L
+#define UMCCH2_2_PerfMonCtl4__PriorityMask_MASK 0x00003C00L
+#define UMCCH2_2_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH2_2_PerfMonCtl4__BankSel_MASK 0x00FF0000L
+#define UMCCH2_2_PerfMonCtl4__VCSel_MASK 0x1F000000L
+#define UMCCH2_2_PerfMonCtl4__SubChanMask_MASK 0x60000000L
+#define UMCCH2_2_PerfMonCtl4__Enable_MASK 0x80000000L
+//UMCCH2_2_PerfMonCtr4_Lo
+#define UMCCH2_2_PerfMonCtr4_Lo__Data__SHIFT 0x0
+#define UMCCH2_2_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_2_PerfMonCtr4_Hi
+#define UMCCH2_2_PerfMonCtr4_Hi__Data__SHIFT 0x0
+#define UMCCH2_2_PerfMonCtr4_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_2_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH2_2_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH2_2_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_2_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L
+#define UMCCH2_2_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH2_2_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH2_2_PerfMonCtl5
+#define UMCCH2_2_PerfMonCtl5__EventSelect__SHIFT 0x0
+#define UMCCH2_2_PerfMonCtl5__RdWrMask__SHIFT 0x8
+#define UMCCH2_2_PerfMonCtl5__PriorityMask__SHIFT 0xa
+#define UMCCH2_2_PerfMonCtl5__ReqSizeMask__SHIFT 0xe
+#define UMCCH2_2_PerfMonCtl5__BankSel__SHIFT 0x10
+#define UMCCH2_2_PerfMonCtl5__VCSel__SHIFT 0x18
+#define UMCCH2_2_PerfMonCtl5__SubChanMask__SHIFT 0x1d
+#define UMCCH2_2_PerfMonCtl5__Enable__SHIFT 0x1f
+#define UMCCH2_2_PerfMonCtl5__EventSelect_MASK 0x000000FFL
+#define UMCCH2_2_PerfMonCtl5__RdWrMask_MASK 0x00000300L
+#define UMCCH2_2_PerfMonCtl5__PriorityMask_MASK 0x00003C00L
+#define UMCCH2_2_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH2_2_PerfMonCtl5__BankSel_MASK 0x00FF0000L
+#define UMCCH2_2_PerfMonCtl5__VCSel_MASK 0x1F000000L
+#define UMCCH2_2_PerfMonCtl5__SubChanMask_MASK 0x60000000L
+#define UMCCH2_2_PerfMonCtl5__Enable_MASK 0x80000000L
+//UMCCH2_2_PerfMonCtr5_Lo
+#define UMCCH2_2_PerfMonCtr5_Lo__Data__SHIFT 0x0
+#define UMCCH2_2_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_2_PerfMonCtr5_Hi
+#define UMCCH2_2_PerfMonCtr5_Hi__Data__SHIFT 0x0
+#define UMCCH2_2_PerfMonCtr5_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_2_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH2_2_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH2_2_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_2_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L
+#define UMCCH2_2_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH2_2_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH2_2_PerfMonCtl6
+#define UMCCH2_2_PerfMonCtl6__EventSelect__SHIFT 0x0
+#define UMCCH2_2_PerfMonCtl6__RdWrMask__SHIFT 0x8
+#define UMCCH2_2_PerfMonCtl6__PriorityMask__SHIFT 0xa
+#define UMCCH2_2_PerfMonCtl6__ReqSizeMask__SHIFT 0xe
+#define UMCCH2_2_PerfMonCtl6__BankSel__SHIFT 0x10
+#define UMCCH2_2_PerfMonCtl6__VCSel__SHIFT 0x18
+#define UMCCH2_2_PerfMonCtl6__SubChanMask__SHIFT 0x1d
+#define UMCCH2_2_PerfMonCtl6__Enable__SHIFT 0x1f
+#define UMCCH2_2_PerfMonCtl6__EventSelect_MASK 0x000000FFL
+#define UMCCH2_2_PerfMonCtl6__RdWrMask_MASK 0x00000300L
+#define UMCCH2_2_PerfMonCtl6__PriorityMask_MASK 0x00003C00L
+#define UMCCH2_2_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH2_2_PerfMonCtl6__BankSel_MASK 0x00FF0000L
+#define UMCCH2_2_PerfMonCtl6__VCSel_MASK 0x1F000000L
+#define UMCCH2_2_PerfMonCtl6__SubChanMask_MASK 0x60000000L
+#define UMCCH2_2_PerfMonCtl6__Enable_MASK 0x80000000L
+//UMCCH2_2_PerfMonCtr6_Lo
+#define UMCCH2_2_PerfMonCtr6_Lo__Data__SHIFT 0x0
+#define UMCCH2_2_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_2_PerfMonCtr6_Hi
+#define UMCCH2_2_PerfMonCtr6_Hi__Data__SHIFT 0x0
+#define UMCCH2_2_PerfMonCtr6_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_2_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH2_2_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH2_2_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_2_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L
+#define UMCCH2_2_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH2_2_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH2_2_PerfMonCtl7
+#define UMCCH2_2_PerfMonCtl7__EventSelect__SHIFT 0x0
+#define UMCCH2_2_PerfMonCtl7__RdWrMask__SHIFT 0x8
+#define UMCCH2_2_PerfMonCtl7__PriorityMask__SHIFT 0xa
+#define UMCCH2_2_PerfMonCtl7__ReqSizeMask__SHIFT 0xe
+#define UMCCH2_2_PerfMonCtl7__BankSel__SHIFT 0x10
+#define UMCCH2_2_PerfMonCtl7__VCSel__SHIFT 0x18
+#define UMCCH2_2_PerfMonCtl7__SubChanMask__SHIFT 0x1d
+#define UMCCH2_2_PerfMonCtl7__Enable__SHIFT 0x1f
+#define UMCCH2_2_PerfMonCtl7__EventSelect_MASK 0x000000FFL
+#define UMCCH2_2_PerfMonCtl7__RdWrMask_MASK 0x00000300L
+#define UMCCH2_2_PerfMonCtl7__PriorityMask_MASK 0x00003C00L
+#define UMCCH2_2_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH2_2_PerfMonCtl7__BankSel_MASK 0x00FF0000L
+#define UMCCH2_2_PerfMonCtl7__VCSel_MASK 0x1F000000L
+#define UMCCH2_2_PerfMonCtl7__SubChanMask_MASK 0x60000000L
+#define UMCCH2_2_PerfMonCtl7__Enable_MASK 0x80000000L
+//UMCCH2_2_PerfMonCtr7_Lo
+#define UMCCH2_2_PerfMonCtr7_Lo__Data__SHIFT 0x0
+#define UMCCH2_2_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_2_PerfMonCtr7_Hi
+#define UMCCH2_2_PerfMonCtr7_Hi__Data__SHIFT 0x0
+#define UMCCH2_2_PerfMonCtr7_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_2_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH2_2_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH2_2_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_2_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L
+#define UMCCH2_2_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH2_2_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH2_2_PerfMonCtl8
+#define UMCCH2_2_PerfMonCtl8__EventSelect__SHIFT 0x0
+#define UMCCH2_2_PerfMonCtl8__RdWrMask__SHIFT 0x8
+#define UMCCH2_2_PerfMonCtl8__PriorityMask__SHIFT 0xa
+#define UMCCH2_2_PerfMonCtl8__ReqSizeMask__SHIFT 0xe
+#define UMCCH2_2_PerfMonCtl8__BankSel__SHIFT 0x10
+#define UMCCH2_2_PerfMonCtl8__VCSel__SHIFT 0x18
+#define UMCCH2_2_PerfMonCtl8__SubChanMask__SHIFT 0x1d
+#define UMCCH2_2_PerfMonCtl8__Enable__SHIFT 0x1f
+#define UMCCH2_2_PerfMonCtl8__EventSelect_MASK 0x000000FFL
+#define UMCCH2_2_PerfMonCtl8__RdWrMask_MASK 0x00000300L
+#define UMCCH2_2_PerfMonCtl8__PriorityMask_MASK 0x00003C00L
+#define UMCCH2_2_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH2_2_PerfMonCtl8__BankSel_MASK 0x00FF0000L
+#define UMCCH2_2_PerfMonCtl8__VCSel_MASK 0x1F000000L
+#define UMCCH2_2_PerfMonCtl8__SubChanMask_MASK 0x60000000L
+#define UMCCH2_2_PerfMonCtl8__Enable_MASK 0x80000000L
+//UMCCH2_2_PerfMonCtr8_Lo
+#define UMCCH2_2_PerfMonCtr8_Lo__Data__SHIFT 0x0
+#define UMCCH2_2_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_2_PerfMonCtr8_Hi
+#define UMCCH2_2_PerfMonCtr8_Hi__Data__SHIFT 0x0
+#define UMCCH2_2_PerfMonCtr8_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_2_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH2_2_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH2_2_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_2_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L
+#define UMCCH2_2_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH2_2_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L
+
+
+// addressBlock: umc_w_phy_umc2_umcch3_umcchdec
+//UMCCH3_2_BaseAddrCS0
+#define UMCCH3_2_BaseAddrCS0__CSEnable__SHIFT 0x0
+#define UMCCH3_2_BaseAddrCS0__BaseAddr__SHIFT 0x1
+#define UMCCH3_2_BaseAddrCS0__CSEnable_MASK 0x00000001L
+#define UMCCH3_2_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL
+//UMCCH3_2_AddrMaskCS01
+#define UMCCH3_2_AddrMaskCS01__AddrMask__SHIFT 0x1
+#define UMCCH3_2_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL
+//UMCCH3_2_AddrSelCS01
+#define UMCCH3_2_AddrSelCS01__BankBit0__SHIFT 0x0
+#define UMCCH3_2_AddrSelCS01__BankBit1__SHIFT 0x4
+#define UMCCH3_2_AddrSelCS01__BankBit2__SHIFT 0x8
+#define UMCCH3_2_AddrSelCS01__BankBit3__SHIFT 0xc
+#define UMCCH3_2_AddrSelCS01__BankBit4__SHIFT 0x10
+#define UMCCH3_2_AddrSelCS01__RowLo__SHIFT 0x18
+#define UMCCH3_2_AddrSelCS01__RowHi__SHIFT 0x1c
+#define UMCCH3_2_AddrSelCS01__BankBit0_MASK 0x0000000FL
+#define UMCCH3_2_AddrSelCS01__BankBit1_MASK 0x000000F0L
+#define UMCCH3_2_AddrSelCS01__BankBit2_MASK 0x00000F00L
+#define UMCCH3_2_AddrSelCS01__BankBit3_MASK 0x0000F000L
+#define UMCCH3_2_AddrSelCS01__BankBit4_MASK 0x001F0000L
+#define UMCCH3_2_AddrSelCS01__RowLo_MASK 0x0F000000L
+#define UMCCH3_2_AddrSelCS01__RowHi_MASK 0xF0000000L
+//UMCCH3_2_AddrHashBank0
+#define UMCCH3_2_AddrHashBank0__XorEnable__SHIFT 0x0
+#define UMCCH3_2_AddrHashBank0__ColXor__SHIFT 0x1
+#define UMCCH3_2_AddrHashBank0__RowXor__SHIFT 0xe
+#define UMCCH3_2_AddrHashBank0__XorEnable_MASK 0x00000001L
+#define UMCCH3_2_AddrHashBank0__ColXor_MASK 0x00003FFEL
+#define UMCCH3_2_AddrHashBank0__RowXor_MASK 0xFFFFC000L
+//UMCCH3_2_AddrHashBank1
+#define UMCCH3_2_AddrHashBank1__XorEnable__SHIFT 0x0
+#define UMCCH3_2_AddrHashBank1__ColXor__SHIFT 0x1
+#define UMCCH3_2_AddrHashBank1__RowXor__SHIFT 0xe
+#define UMCCH3_2_AddrHashBank1__XorEnable_MASK 0x00000001L
+#define UMCCH3_2_AddrHashBank1__ColXor_MASK 0x00003FFEL
+#define UMCCH3_2_AddrHashBank1__RowXor_MASK 0xFFFFC000L
+//UMCCH3_2_AddrHashBank2
+#define UMCCH3_2_AddrHashBank2__XorEnable__SHIFT 0x0
+#define UMCCH3_2_AddrHashBank2__ColXor__SHIFT 0x1
+#define UMCCH3_2_AddrHashBank2__RowXor__SHIFT 0xe
+#define UMCCH3_2_AddrHashBank2__XorEnable_MASK 0x00000001L
+#define UMCCH3_2_AddrHashBank2__ColXor_MASK 0x00003FFEL
+#define UMCCH3_2_AddrHashBank2__RowXor_MASK 0xFFFFC000L
+//UMCCH3_2_AddrHashBank3
+#define UMCCH3_2_AddrHashBank3__XorEnable__SHIFT 0x0
+#define UMCCH3_2_AddrHashBank3__ColXor__SHIFT 0x1
+#define UMCCH3_2_AddrHashBank3__RowXor__SHIFT 0xe
+#define UMCCH3_2_AddrHashBank3__XorEnable_MASK 0x00000001L
+#define UMCCH3_2_AddrHashBank3__ColXor_MASK 0x00003FFEL
+#define UMCCH3_2_AddrHashBank3__RowXor_MASK 0xFFFFC000L
+//UMCCH3_2_AddrHashBank4
+#define UMCCH3_2_AddrHashBank4__XorEnable__SHIFT 0x0
+#define UMCCH3_2_AddrHashBank4__ColXor__SHIFT 0x1
+#define UMCCH3_2_AddrHashBank4__RowXor__SHIFT 0xe
+#define UMCCH3_2_AddrHashBank4__XorEnable_MASK 0x00000001L
+#define UMCCH3_2_AddrHashBank4__ColXor_MASK 0x00003FFEL
+#define UMCCH3_2_AddrHashBank4__RowXor_MASK 0xFFFFC000L
+//UMCCH3_2_AddrHashBank5
+#define UMCCH3_2_AddrHashBank5__XorEnable__SHIFT 0x0
+#define UMCCH3_2_AddrHashBank5__ColXor__SHIFT 0x1
+#define UMCCH3_2_AddrHashBank5__RowXor__SHIFT 0xe
+#define UMCCH3_2_AddrHashBank5__XorEnable_MASK 0x00000001L
+#define UMCCH3_2_AddrHashBank5__ColXor_MASK 0x00003FFEL
+#define UMCCH3_2_AddrHashBank5__RowXor_MASK 0xFFFFC000L
+//UMCCH3_2_EccErrCntSel
+#define UMCCH3_2_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0
+#define UMCCH3_2_EccErrCntSel__EccErrInt__SHIFT 0xc
+#define UMCCH3_2_EccErrCntSel__EccErrCntEn__SHIFT 0xf
+#define UMCCH3_2_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL
+#define UMCCH3_2_EccErrCntSel__EccErrInt_MASK 0x00003000L
+#define UMCCH3_2_EccErrCntSel__EccErrCntEn_MASK 0x00008000L
+//UMCCH3_2_EccErrCnt
+#define UMCCH3_2_EccErrCnt__EccErrCnt__SHIFT 0x0
+#define UMCCH3_2_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL
+//UMCCH3_2_PerfMonCtlClk
+#define UMCCH3_2_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0
+#define UMCCH3_2_PerfMonCtlClk__ClkGate__SHIFT 0x16
+#define UMCCH3_2_PerfMonCtlClk__GlblReset__SHIFT 0x18
+#define UMCCH3_2_PerfMonCtlClk__GlblMonEn__SHIFT 0x19
+#define UMCCH3_2_PerfMonCtlClk__NumCounters__SHIFT 0x1a
+#define UMCCH3_2_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f
+#define UMCCH3_2_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL
+#define UMCCH3_2_PerfMonCtlClk__ClkGate_MASK 0x00400000L
+#define UMCCH3_2_PerfMonCtlClk__GlblReset_MASK 0x01000000L
+#define UMCCH3_2_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L
+#define UMCCH3_2_PerfMonCtlClk__NumCounters_MASK 0x3C000000L
+#define UMCCH3_2_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L
+//UMCCH3_2_PerfMonCtrClk_Lo
+#define UMCCH3_2_PerfMonCtrClk_Lo__Data__SHIFT 0x0
+#define UMCCH3_2_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_2_PerfMonCtrClk_Hi
+#define UMCCH3_2_PerfMonCtrClk_Hi__Data__SHIFT 0x0
+#define UMCCH3_2_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_2_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_2_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L
+//UMCCH3_2_PerfMonCtl1
+#define UMCCH3_2_PerfMonCtl1__EventSelect__SHIFT 0x0
+#define UMCCH3_2_PerfMonCtl1__RdWrMask__SHIFT 0x8
+#define UMCCH3_2_PerfMonCtl1__PriorityMask__SHIFT 0xa
+#define UMCCH3_2_PerfMonCtl1__ReqSizeMask__SHIFT 0xe
+#define UMCCH3_2_PerfMonCtl1__BankSel__SHIFT 0x10
+#define UMCCH3_2_PerfMonCtl1__VCSel__SHIFT 0x18
+#define UMCCH3_2_PerfMonCtl1__SubChanMask__SHIFT 0x1d
+#define UMCCH3_2_PerfMonCtl1__Enable__SHIFT 0x1f
+#define UMCCH3_2_PerfMonCtl1__EventSelect_MASK 0x000000FFL
+#define UMCCH3_2_PerfMonCtl1__RdWrMask_MASK 0x00000300L
+#define UMCCH3_2_PerfMonCtl1__PriorityMask_MASK 0x00003C00L
+#define UMCCH3_2_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH3_2_PerfMonCtl1__BankSel_MASK 0x00FF0000L
+#define UMCCH3_2_PerfMonCtl1__VCSel_MASK 0x1F000000L
+#define UMCCH3_2_PerfMonCtl1__SubChanMask_MASK 0x60000000L
+#define UMCCH3_2_PerfMonCtl1__Enable_MASK 0x80000000L
+//UMCCH3_2_PerfMonCtr1_Lo
+#define UMCCH3_2_PerfMonCtr1_Lo__Data__SHIFT 0x0
+#define UMCCH3_2_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_2_PerfMonCtr1_Hi
+#define UMCCH3_2_PerfMonCtr1_Hi__Data__SHIFT 0x0
+#define UMCCH3_2_PerfMonCtr1_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_2_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH3_2_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH3_2_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_2_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L
+#define UMCCH3_2_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH3_2_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH3_2_PerfMonCtl2
+#define UMCCH3_2_PerfMonCtl2__EventSelect__SHIFT 0x0
+#define UMCCH3_2_PerfMonCtl2__RdWrMask__SHIFT 0x8
+#define UMCCH3_2_PerfMonCtl2__PriorityMask__SHIFT 0xa
+#define UMCCH3_2_PerfMonCtl2__ReqSizeMask__SHIFT 0xe
+#define UMCCH3_2_PerfMonCtl2__BankSel__SHIFT 0x10
+#define UMCCH3_2_PerfMonCtl2__VCSel__SHIFT 0x18
+#define UMCCH3_2_PerfMonCtl2__SubChanMask__SHIFT 0x1d
+#define UMCCH3_2_PerfMonCtl2__Enable__SHIFT 0x1f
+#define UMCCH3_2_PerfMonCtl2__EventSelect_MASK 0x000000FFL
+#define UMCCH3_2_PerfMonCtl2__RdWrMask_MASK 0x00000300L
+#define UMCCH3_2_PerfMonCtl2__PriorityMask_MASK 0x00003C00L
+#define UMCCH3_2_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH3_2_PerfMonCtl2__BankSel_MASK 0x00FF0000L
+#define UMCCH3_2_PerfMonCtl2__VCSel_MASK 0x1F000000L
+#define UMCCH3_2_PerfMonCtl2__SubChanMask_MASK 0x60000000L
+#define UMCCH3_2_PerfMonCtl2__Enable_MASK 0x80000000L
+//UMCCH3_2_PerfMonCtr2_Lo
+#define UMCCH3_2_PerfMonCtr2_Lo__Data__SHIFT 0x0
+#define UMCCH3_2_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_2_PerfMonCtr2_Hi
+#define UMCCH3_2_PerfMonCtr2_Hi__Data__SHIFT 0x0
+#define UMCCH3_2_PerfMonCtr2_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_2_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH3_2_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH3_2_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_2_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L
+#define UMCCH3_2_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH3_2_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH3_2_PerfMonCtl3
+#define UMCCH3_2_PerfMonCtl3__EventSelect__SHIFT 0x0
+#define UMCCH3_2_PerfMonCtl3__RdWrMask__SHIFT 0x8
+#define UMCCH3_2_PerfMonCtl3__PriorityMask__SHIFT 0xa
+#define UMCCH3_2_PerfMonCtl3__ReqSizeMask__SHIFT 0xe
+#define UMCCH3_2_PerfMonCtl3__BankSel__SHIFT 0x10
+#define UMCCH3_2_PerfMonCtl3__VCSel__SHIFT 0x18
+#define UMCCH3_2_PerfMonCtl3__SubChanMask__SHIFT 0x1d
+#define UMCCH3_2_PerfMonCtl3__Enable__SHIFT 0x1f
+#define UMCCH3_2_PerfMonCtl3__EventSelect_MASK 0x000000FFL
+#define UMCCH3_2_PerfMonCtl3__RdWrMask_MASK 0x00000300L
+#define UMCCH3_2_PerfMonCtl3__PriorityMask_MASK 0x00003C00L
+#define UMCCH3_2_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH3_2_PerfMonCtl3__BankSel_MASK 0x00FF0000L
+#define UMCCH3_2_PerfMonCtl3__VCSel_MASK 0x1F000000L
+#define UMCCH3_2_PerfMonCtl3__SubChanMask_MASK 0x60000000L
+#define UMCCH3_2_PerfMonCtl3__Enable_MASK 0x80000000L
+//UMCCH3_2_PerfMonCtr3_Lo
+#define UMCCH3_2_PerfMonCtr3_Lo__Data__SHIFT 0x0
+#define UMCCH3_2_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_2_PerfMonCtr3_Hi
+#define UMCCH3_2_PerfMonCtr3_Hi__Data__SHIFT 0x0
+#define UMCCH3_2_PerfMonCtr3_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_2_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH3_2_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH3_2_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_2_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L
+#define UMCCH3_2_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH3_2_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH3_2_PerfMonCtl4
+#define UMCCH3_2_PerfMonCtl4__EventSelect__SHIFT 0x0
+#define UMCCH3_2_PerfMonCtl4__RdWrMask__SHIFT 0x8
+#define UMCCH3_2_PerfMonCtl4__PriorityMask__SHIFT 0xa
+#define UMCCH3_2_PerfMonCtl4__ReqSizeMask__SHIFT 0xe
+#define UMCCH3_2_PerfMonCtl4__BankSel__SHIFT 0x10
+#define UMCCH3_2_PerfMonCtl4__VCSel__SHIFT 0x18
+#define UMCCH3_2_PerfMonCtl4__SubChanMask__SHIFT 0x1d
+#define UMCCH3_2_PerfMonCtl4__Enable__SHIFT 0x1f
+#define UMCCH3_2_PerfMonCtl4__EventSelect_MASK 0x000000FFL
+#define UMCCH3_2_PerfMonCtl4__RdWrMask_MASK 0x00000300L
+#define UMCCH3_2_PerfMonCtl4__PriorityMask_MASK 0x00003C00L
+#define UMCCH3_2_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH3_2_PerfMonCtl4__BankSel_MASK 0x00FF0000L
+#define UMCCH3_2_PerfMonCtl4__VCSel_MASK 0x1F000000L
+#define UMCCH3_2_PerfMonCtl4__SubChanMask_MASK 0x60000000L
+#define UMCCH3_2_PerfMonCtl4__Enable_MASK 0x80000000L
+//UMCCH3_2_PerfMonCtr4_Lo
+#define UMCCH3_2_PerfMonCtr4_Lo__Data__SHIFT 0x0
+#define UMCCH3_2_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_2_PerfMonCtr4_Hi
+#define UMCCH3_2_PerfMonCtr4_Hi__Data__SHIFT 0x0
+#define UMCCH3_2_PerfMonCtr4_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_2_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH3_2_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH3_2_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_2_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L
+#define UMCCH3_2_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH3_2_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH3_2_PerfMonCtl5
+#define UMCCH3_2_PerfMonCtl5__EventSelect__SHIFT 0x0
+#define UMCCH3_2_PerfMonCtl5__RdWrMask__SHIFT 0x8
+#define UMCCH3_2_PerfMonCtl5__PriorityMask__SHIFT 0xa
+#define UMCCH3_2_PerfMonCtl5__ReqSizeMask__SHIFT 0xe
+#define UMCCH3_2_PerfMonCtl5__BankSel__SHIFT 0x10
+#define UMCCH3_2_PerfMonCtl5__VCSel__SHIFT 0x18
+#define UMCCH3_2_PerfMonCtl5__SubChanMask__SHIFT 0x1d
+#define UMCCH3_2_PerfMonCtl5__Enable__SHIFT 0x1f
+#define UMCCH3_2_PerfMonCtl5__EventSelect_MASK 0x000000FFL
+#define UMCCH3_2_PerfMonCtl5__RdWrMask_MASK 0x00000300L
+#define UMCCH3_2_PerfMonCtl5__PriorityMask_MASK 0x00003C00L
+#define UMCCH3_2_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH3_2_PerfMonCtl5__BankSel_MASK 0x00FF0000L
+#define UMCCH3_2_PerfMonCtl5__VCSel_MASK 0x1F000000L
+#define UMCCH3_2_PerfMonCtl5__SubChanMask_MASK 0x60000000L
+#define UMCCH3_2_PerfMonCtl5__Enable_MASK 0x80000000L
+//UMCCH3_2_PerfMonCtr5_Lo
+#define UMCCH3_2_PerfMonCtr5_Lo__Data__SHIFT 0x0
+#define UMCCH3_2_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_2_PerfMonCtr5_Hi
+#define UMCCH3_2_PerfMonCtr5_Hi__Data__SHIFT 0x0
+#define UMCCH3_2_PerfMonCtr5_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_2_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH3_2_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH3_2_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_2_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L
+#define UMCCH3_2_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH3_2_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH3_2_PerfMonCtl6
+#define UMCCH3_2_PerfMonCtl6__EventSelect__SHIFT 0x0
+#define UMCCH3_2_PerfMonCtl6__RdWrMask__SHIFT 0x8
+#define UMCCH3_2_PerfMonCtl6__PriorityMask__SHIFT 0xa
+#define UMCCH3_2_PerfMonCtl6__ReqSizeMask__SHIFT 0xe
+#define UMCCH3_2_PerfMonCtl6__BankSel__SHIFT 0x10
+#define UMCCH3_2_PerfMonCtl6__VCSel__SHIFT 0x18
+#define UMCCH3_2_PerfMonCtl6__SubChanMask__SHIFT 0x1d
+#define UMCCH3_2_PerfMonCtl6__Enable__SHIFT 0x1f
+#define UMCCH3_2_PerfMonCtl6__EventSelect_MASK 0x000000FFL
+#define UMCCH3_2_PerfMonCtl6__RdWrMask_MASK 0x00000300L
+#define UMCCH3_2_PerfMonCtl6__PriorityMask_MASK 0x00003C00L
+#define UMCCH3_2_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH3_2_PerfMonCtl6__BankSel_MASK 0x00FF0000L
+#define UMCCH3_2_PerfMonCtl6__VCSel_MASK 0x1F000000L
+#define UMCCH3_2_PerfMonCtl6__SubChanMask_MASK 0x60000000L
+#define UMCCH3_2_PerfMonCtl6__Enable_MASK 0x80000000L
+//UMCCH3_2_PerfMonCtr6_Lo
+#define UMCCH3_2_PerfMonCtr6_Lo__Data__SHIFT 0x0
+#define UMCCH3_2_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_2_PerfMonCtr6_Hi
+#define UMCCH3_2_PerfMonCtr6_Hi__Data__SHIFT 0x0
+#define UMCCH3_2_PerfMonCtr6_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_2_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH3_2_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH3_2_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_2_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L
+#define UMCCH3_2_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH3_2_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH3_2_PerfMonCtl7
+#define UMCCH3_2_PerfMonCtl7__EventSelect__SHIFT 0x0
+#define UMCCH3_2_PerfMonCtl7__RdWrMask__SHIFT 0x8
+#define UMCCH3_2_PerfMonCtl7__PriorityMask__SHIFT 0xa
+#define UMCCH3_2_PerfMonCtl7__ReqSizeMask__SHIFT 0xe
+#define UMCCH3_2_PerfMonCtl7__BankSel__SHIFT 0x10
+#define UMCCH3_2_PerfMonCtl7__VCSel__SHIFT 0x18
+#define UMCCH3_2_PerfMonCtl7__SubChanMask__SHIFT 0x1d
+#define UMCCH3_2_PerfMonCtl7__Enable__SHIFT 0x1f
+#define UMCCH3_2_PerfMonCtl7__EventSelect_MASK 0x000000FFL
+#define UMCCH3_2_PerfMonCtl7__RdWrMask_MASK 0x00000300L
+#define UMCCH3_2_PerfMonCtl7__PriorityMask_MASK 0x00003C00L
+#define UMCCH3_2_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH3_2_PerfMonCtl7__BankSel_MASK 0x00FF0000L
+#define UMCCH3_2_PerfMonCtl7__VCSel_MASK 0x1F000000L
+#define UMCCH3_2_PerfMonCtl7__SubChanMask_MASK 0x60000000L
+#define UMCCH3_2_PerfMonCtl7__Enable_MASK 0x80000000L
+//UMCCH3_2_PerfMonCtr7_Lo
+#define UMCCH3_2_PerfMonCtr7_Lo__Data__SHIFT 0x0
+#define UMCCH3_2_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_2_PerfMonCtr7_Hi
+#define UMCCH3_2_PerfMonCtr7_Hi__Data__SHIFT 0x0
+#define UMCCH3_2_PerfMonCtr7_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_2_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH3_2_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH3_2_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_2_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L
+#define UMCCH3_2_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH3_2_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH3_2_PerfMonCtl8
+#define UMCCH3_2_PerfMonCtl8__EventSelect__SHIFT 0x0
+#define UMCCH3_2_PerfMonCtl8__RdWrMask__SHIFT 0x8
+#define UMCCH3_2_PerfMonCtl8__PriorityMask__SHIFT 0xa
+#define UMCCH3_2_PerfMonCtl8__ReqSizeMask__SHIFT 0xe
+#define UMCCH3_2_PerfMonCtl8__BankSel__SHIFT 0x10
+#define UMCCH3_2_PerfMonCtl8__VCSel__SHIFT 0x18
+#define UMCCH3_2_PerfMonCtl8__SubChanMask__SHIFT 0x1d
+#define UMCCH3_2_PerfMonCtl8__Enable__SHIFT 0x1f
+#define UMCCH3_2_PerfMonCtl8__EventSelect_MASK 0x000000FFL
+#define UMCCH3_2_PerfMonCtl8__RdWrMask_MASK 0x00000300L
+#define UMCCH3_2_PerfMonCtl8__PriorityMask_MASK 0x00003C00L
+#define UMCCH3_2_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH3_2_PerfMonCtl8__BankSel_MASK 0x00FF0000L
+#define UMCCH3_2_PerfMonCtl8__VCSel_MASK 0x1F000000L
+#define UMCCH3_2_PerfMonCtl8__SubChanMask_MASK 0x60000000L
+#define UMCCH3_2_PerfMonCtl8__Enable_MASK 0x80000000L
+//UMCCH3_2_PerfMonCtr8_Lo
+#define UMCCH3_2_PerfMonCtr8_Lo__Data__SHIFT 0x0
+#define UMCCH3_2_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_2_PerfMonCtr8_Hi
+#define UMCCH3_2_PerfMonCtr8_Hi__Data__SHIFT 0x0
+#define UMCCH3_2_PerfMonCtr8_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_2_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH3_2_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH3_2_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_2_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L
+#define UMCCH3_2_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH3_2_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L
+
+
+// addressBlock: umc_w_phy_umc2_umcch4_umcchdec
+//UMCCH4_2_BaseAddrCS0
+#define UMCCH4_2_BaseAddrCS0__CSEnable__SHIFT 0x0
+#define UMCCH4_2_BaseAddrCS0__BaseAddr__SHIFT 0x1
+#define UMCCH4_2_BaseAddrCS0__CSEnable_MASK 0x00000001L
+#define UMCCH4_2_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL
+//UMCCH4_2_AddrMaskCS01
+#define UMCCH4_2_AddrMaskCS01__AddrMask__SHIFT 0x1
+#define UMCCH4_2_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL
+//UMCCH4_2_AddrSelCS01
+#define UMCCH4_2_AddrSelCS01__BankBit0__SHIFT 0x0
+#define UMCCH4_2_AddrSelCS01__BankBit1__SHIFT 0x4
+#define UMCCH4_2_AddrSelCS01__BankBit2__SHIFT 0x8
+#define UMCCH4_2_AddrSelCS01__BankBit3__SHIFT 0xc
+#define UMCCH4_2_AddrSelCS01__BankBit4__SHIFT 0x10
+#define UMCCH4_2_AddrSelCS01__RowLo__SHIFT 0x18
+#define UMCCH4_2_AddrSelCS01__RowHi__SHIFT 0x1c
+#define UMCCH4_2_AddrSelCS01__BankBit0_MASK 0x0000000FL
+#define UMCCH4_2_AddrSelCS01__BankBit1_MASK 0x000000F0L
+#define UMCCH4_2_AddrSelCS01__BankBit2_MASK 0x00000F00L
+#define UMCCH4_2_AddrSelCS01__BankBit3_MASK 0x0000F000L
+#define UMCCH4_2_AddrSelCS01__BankBit4_MASK 0x001F0000L
+#define UMCCH4_2_AddrSelCS01__RowLo_MASK 0x0F000000L
+#define UMCCH4_2_AddrSelCS01__RowHi_MASK 0xF0000000L
+//UMCCH4_2_AddrHashBank0
+#define UMCCH4_2_AddrHashBank0__XorEnable__SHIFT 0x0
+#define UMCCH4_2_AddrHashBank0__ColXor__SHIFT 0x1
+#define UMCCH4_2_AddrHashBank0__RowXor__SHIFT 0xe
+#define UMCCH4_2_AddrHashBank0__XorEnable_MASK 0x00000001L
+#define UMCCH4_2_AddrHashBank0__ColXor_MASK 0x00003FFEL
+#define UMCCH4_2_AddrHashBank0__RowXor_MASK 0xFFFFC000L
+//UMCCH4_2_AddrHashBank1
+#define UMCCH4_2_AddrHashBank1__XorEnable__SHIFT 0x0
+#define UMCCH4_2_AddrHashBank1__ColXor__SHIFT 0x1
+#define UMCCH4_2_AddrHashBank1__RowXor__SHIFT 0xe
+#define UMCCH4_2_AddrHashBank1__XorEnable_MASK 0x00000001L
+#define UMCCH4_2_AddrHashBank1__ColXor_MASK 0x00003FFEL
+#define UMCCH4_2_AddrHashBank1__RowXor_MASK 0xFFFFC000L
+//UMCCH4_2_AddrHashBank2
+#define UMCCH4_2_AddrHashBank2__XorEnable__SHIFT 0x0
+#define UMCCH4_2_AddrHashBank2__ColXor__SHIFT 0x1
+#define UMCCH4_2_AddrHashBank2__RowXor__SHIFT 0xe
+#define UMCCH4_2_AddrHashBank2__XorEnable_MASK 0x00000001L
+#define UMCCH4_2_AddrHashBank2__ColXor_MASK 0x00003FFEL
+#define UMCCH4_2_AddrHashBank2__RowXor_MASK 0xFFFFC000L
+//UMCCH4_2_AddrHashBank3
+#define UMCCH4_2_AddrHashBank3__XorEnable__SHIFT 0x0
+#define UMCCH4_2_AddrHashBank3__ColXor__SHIFT 0x1
+#define UMCCH4_2_AddrHashBank3__RowXor__SHIFT 0xe
+#define UMCCH4_2_AddrHashBank3__XorEnable_MASK 0x00000001L
+#define UMCCH4_2_AddrHashBank3__ColXor_MASK 0x00003FFEL
+#define UMCCH4_2_AddrHashBank3__RowXor_MASK 0xFFFFC000L
+//UMCCH4_2_AddrHashBank4
+#define UMCCH4_2_AddrHashBank4__XorEnable__SHIFT 0x0
+#define UMCCH4_2_AddrHashBank4__ColXor__SHIFT 0x1
+#define UMCCH4_2_AddrHashBank4__RowXor__SHIFT 0xe
+#define UMCCH4_2_AddrHashBank4__XorEnable_MASK 0x00000001L
+#define UMCCH4_2_AddrHashBank4__ColXor_MASK 0x00003FFEL
+#define UMCCH4_2_AddrHashBank4__RowXor_MASK 0xFFFFC000L
+//UMCCH4_2_AddrHashBank5
+#define UMCCH4_2_AddrHashBank5__XorEnable__SHIFT 0x0
+#define UMCCH4_2_AddrHashBank5__ColXor__SHIFT 0x1
+#define UMCCH4_2_AddrHashBank5__RowXor__SHIFT 0xe
+#define UMCCH4_2_AddrHashBank5__XorEnable_MASK 0x00000001L
+#define UMCCH4_2_AddrHashBank5__ColXor_MASK 0x00003FFEL
+#define UMCCH4_2_AddrHashBank5__RowXor_MASK 0xFFFFC000L
+//UMCCH4_2_EccErrCntSel
+#define UMCCH4_2_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0
+#define UMCCH4_2_EccErrCntSel__EccErrInt__SHIFT 0xc
+#define UMCCH4_2_EccErrCntSel__EccErrCntEn__SHIFT 0xf
+#define UMCCH4_2_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL
+#define UMCCH4_2_EccErrCntSel__EccErrInt_MASK 0x00003000L
+#define UMCCH4_2_EccErrCntSel__EccErrCntEn_MASK 0x00008000L
+//UMCCH4_2_EccErrCnt
+#define UMCCH4_2_EccErrCnt__EccErrCnt__SHIFT 0x0
+#define UMCCH4_2_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL
+//UMCCH4_2_PerfMonCtlClk
+#define UMCCH4_2_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0
+#define UMCCH4_2_PerfMonCtlClk__ClkGate__SHIFT 0x16
+#define UMCCH4_2_PerfMonCtlClk__GlblReset__SHIFT 0x18
+#define UMCCH4_2_PerfMonCtlClk__GlblMonEn__SHIFT 0x19
+#define UMCCH4_2_PerfMonCtlClk__NumCounters__SHIFT 0x1a
+#define UMCCH4_2_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f
+#define UMCCH4_2_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL
+#define UMCCH4_2_PerfMonCtlClk__ClkGate_MASK 0x00400000L
+#define UMCCH4_2_PerfMonCtlClk__GlblReset_MASK 0x01000000L
+#define UMCCH4_2_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L
+#define UMCCH4_2_PerfMonCtlClk__NumCounters_MASK 0x3C000000L
+#define UMCCH4_2_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L
+//UMCCH4_2_PerfMonCtrClk_Lo
+#define UMCCH4_2_PerfMonCtrClk_Lo__Data__SHIFT 0x0
+#define UMCCH4_2_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_2_PerfMonCtrClk_Hi
+#define UMCCH4_2_PerfMonCtrClk_Hi__Data__SHIFT 0x0
+#define UMCCH4_2_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_2_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_2_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L
+//UMCCH4_2_PerfMonCtl1
+#define UMCCH4_2_PerfMonCtl1__EventSelect__SHIFT 0x0
+#define UMCCH4_2_PerfMonCtl1__RdWrMask__SHIFT 0x8
+#define UMCCH4_2_PerfMonCtl1__PriorityMask__SHIFT 0xa
+#define UMCCH4_2_PerfMonCtl1__ReqSizeMask__SHIFT 0xe
+#define UMCCH4_2_PerfMonCtl1__BankSel__SHIFT 0x10
+#define UMCCH4_2_PerfMonCtl1__VCSel__SHIFT 0x18
+#define UMCCH4_2_PerfMonCtl1__SubChanMask__SHIFT 0x1d
+#define UMCCH4_2_PerfMonCtl1__Enable__SHIFT 0x1f
+#define UMCCH4_2_PerfMonCtl1__EventSelect_MASK 0x000000FFL
+#define UMCCH4_2_PerfMonCtl1__RdWrMask_MASK 0x00000300L
+#define UMCCH4_2_PerfMonCtl1__PriorityMask_MASK 0x00003C00L
+#define UMCCH4_2_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH4_2_PerfMonCtl1__BankSel_MASK 0x00FF0000L
+#define UMCCH4_2_PerfMonCtl1__VCSel_MASK 0x1F000000L
+#define UMCCH4_2_PerfMonCtl1__SubChanMask_MASK 0x60000000L
+#define UMCCH4_2_PerfMonCtl1__Enable_MASK 0x80000000L
+//UMCCH4_2_PerfMonCtr1_Lo
+#define UMCCH4_2_PerfMonCtr1_Lo__Data__SHIFT 0x0
+#define UMCCH4_2_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_2_PerfMonCtr1_Hi
+#define UMCCH4_2_PerfMonCtr1_Hi__Data__SHIFT 0x0
+#define UMCCH4_2_PerfMonCtr1_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_2_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH4_2_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH4_2_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_2_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L
+#define UMCCH4_2_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH4_2_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH4_2_PerfMonCtl2
+#define UMCCH4_2_PerfMonCtl2__EventSelect__SHIFT 0x0
+#define UMCCH4_2_PerfMonCtl2__RdWrMask__SHIFT 0x8
+#define UMCCH4_2_PerfMonCtl2__PriorityMask__SHIFT 0xa
+#define UMCCH4_2_PerfMonCtl2__ReqSizeMask__SHIFT 0xe
+#define UMCCH4_2_PerfMonCtl2__BankSel__SHIFT 0x10
+#define UMCCH4_2_PerfMonCtl2__VCSel__SHIFT 0x18
+#define UMCCH4_2_PerfMonCtl2__SubChanMask__SHIFT 0x1d
+#define UMCCH4_2_PerfMonCtl2__Enable__SHIFT 0x1f
+#define UMCCH4_2_PerfMonCtl2__EventSelect_MASK 0x000000FFL
+#define UMCCH4_2_PerfMonCtl2__RdWrMask_MASK 0x00000300L
+#define UMCCH4_2_PerfMonCtl2__PriorityMask_MASK 0x00003C00L
+#define UMCCH4_2_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH4_2_PerfMonCtl2__BankSel_MASK 0x00FF0000L
+#define UMCCH4_2_PerfMonCtl2__VCSel_MASK 0x1F000000L
+#define UMCCH4_2_PerfMonCtl2__SubChanMask_MASK 0x60000000L
+#define UMCCH4_2_PerfMonCtl2__Enable_MASK 0x80000000L
+//UMCCH4_2_PerfMonCtr2_Lo
+#define UMCCH4_2_PerfMonCtr2_Lo__Data__SHIFT 0x0
+#define UMCCH4_2_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_2_PerfMonCtr2_Hi
+#define UMCCH4_2_PerfMonCtr2_Hi__Data__SHIFT 0x0
+#define UMCCH4_2_PerfMonCtr2_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_2_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH4_2_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH4_2_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_2_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L
+#define UMCCH4_2_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH4_2_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH4_2_PerfMonCtl3
+#define UMCCH4_2_PerfMonCtl3__EventSelect__SHIFT 0x0
+#define UMCCH4_2_PerfMonCtl3__RdWrMask__SHIFT 0x8
+#define UMCCH4_2_PerfMonCtl3__PriorityMask__SHIFT 0xa
+#define UMCCH4_2_PerfMonCtl3__ReqSizeMask__SHIFT 0xe
+#define UMCCH4_2_PerfMonCtl3__BankSel__SHIFT 0x10
+#define UMCCH4_2_PerfMonCtl3__VCSel__SHIFT 0x18
+#define UMCCH4_2_PerfMonCtl3__SubChanMask__SHIFT 0x1d
+#define UMCCH4_2_PerfMonCtl3__Enable__SHIFT 0x1f
+#define UMCCH4_2_PerfMonCtl3__EventSelect_MASK 0x000000FFL
+#define UMCCH4_2_PerfMonCtl3__RdWrMask_MASK 0x00000300L
+#define UMCCH4_2_PerfMonCtl3__PriorityMask_MASK 0x00003C00L
+#define UMCCH4_2_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH4_2_PerfMonCtl3__BankSel_MASK 0x00FF0000L
+#define UMCCH4_2_PerfMonCtl3__VCSel_MASK 0x1F000000L
+#define UMCCH4_2_PerfMonCtl3__SubChanMask_MASK 0x60000000L
+#define UMCCH4_2_PerfMonCtl3__Enable_MASK 0x80000000L
+//UMCCH4_2_PerfMonCtr3_Lo
+#define UMCCH4_2_PerfMonCtr3_Lo__Data__SHIFT 0x0
+#define UMCCH4_2_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_2_PerfMonCtr3_Hi
+#define UMCCH4_2_PerfMonCtr3_Hi__Data__SHIFT 0x0
+#define UMCCH4_2_PerfMonCtr3_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_2_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH4_2_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH4_2_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_2_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L
+#define UMCCH4_2_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH4_2_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH4_2_PerfMonCtl4
+#define UMCCH4_2_PerfMonCtl4__EventSelect__SHIFT 0x0
+#define UMCCH4_2_PerfMonCtl4__RdWrMask__SHIFT 0x8
+#define UMCCH4_2_PerfMonCtl4__PriorityMask__SHIFT 0xa
+#define UMCCH4_2_PerfMonCtl4__ReqSizeMask__SHIFT 0xe
+#define UMCCH4_2_PerfMonCtl4__BankSel__SHIFT 0x10
+#define UMCCH4_2_PerfMonCtl4__VCSel__SHIFT 0x18
+#define UMCCH4_2_PerfMonCtl4__SubChanMask__SHIFT 0x1d
+#define UMCCH4_2_PerfMonCtl4__Enable__SHIFT 0x1f
+#define UMCCH4_2_PerfMonCtl4__EventSelect_MASK 0x000000FFL
+#define UMCCH4_2_PerfMonCtl4__RdWrMask_MASK 0x00000300L
+#define UMCCH4_2_PerfMonCtl4__PriorityMask_MASK 0x00003C00L
+#define UMCCH4_2_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH4_2_PerfMonCtl4__BankSel_MASK 0x00FF0000L
+#define UMCCH4_2_PerfMonCtl4__VCSel_MASK 0x1F000000L
+#define UMCCH4_2_PerfMonCtl4__SubChanMask_MASK 0x60000000L
+#define UMCCH4_2_PerfMonCtl4__Enable_MASK 0x80000000L
+//UMCCH4_2_PerfMonCtr4_Lo
+#define UMCCH4_2_PerfMonCtr4_Lo__Data__SHIFT 0x0
+#define UMCCH4_2_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_2_PerfMonCtr4_Hi
+#define UMCCH4_2_PerfMonCtr4_Hi__Data__SHIFT 0x0
+#define UMCCH4_2_PerfMonCtr4_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_2_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH4_2_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH4_2_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_2_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L
+#define UMCCH4_2_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH4_2_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH4_2_PerfMonCtl5
+#define UMCCH4_2_PerfMonCtl5__EventSelect__SHIFT 0x0
+#define UMCCH4_2_PerfMonCtl5__RdWrMask__SHIFT 0x8
+#define UMCCH4_2_PerfMonCtl5__PriorityMask__SHIFT 0xa
+#define UMCCH4_2_PerfMonCtl5__ReqSizeMask__SHIFT 0xe
+#define UMCCH4_2_PerfMonCtl5__BankSel__SHIFT 0x10
+#define UMCCH4_2_PerfMonCtl5__VCSel__SHIFT 0x18
+#define UMCCH4_2_PerfMonCtl5__SubChanMask__SHIFT 0x1d
+#define UMCCH4_2_PerfMonCtl5__Enable__SHIFT 0x1f
+#define UMCCH4_2_PerfMonCtl5__EventSelect_MASK 0x000000FFL
+#define UMCCH4_2_PerfMonCtl5__RdWrMask_MASK 0x00000300L
+#define UMCCH4_2_PerfMonCtl5__PriorityMask_MASK 0x00003C00L
+#define UMCCH4_2_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH4_2_PerfMonCtl5__BankSel_MASK 0x00FF0000L
+#define UMCCH4_2_PerfMonCtl5__VCSel_MASK 0x1F000000L
+#define UMCCH4_2_PerfMonCtl5__SubChanMask_MASK 0x60000000L
+#define UMCCH4_2_PerfMonCtl5__Enable_MASK 0x80000000L
+//UMCCH4_2_PerfMonCtr5_Lo
+#define UMCCH4_2_PerfMonCtr5_Lo__Data__SHIFT 0x0
+#define UMCCH4_2_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_2_PerfMonCtr5_Hi
+#define UMCCH4_2_PerfMonCtr5_Hi__Data__SHIFT 0x0
+#define UMCCH4_2_PerfMonCtr5_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_2_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH4_2_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH4_2_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_2_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L
+#define UMCCH4_2_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH4_2_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH4_2_PerfMonCtl6
+#define UMCCH4_2_PerfMonCtl6__EventSelect__SHIFT 0x0
+#define UMCCH4_2_PerfMonCtl6__RdWrMask__SHIFT 0x8
+#define UMCCH4_2_PerfMonCtl6__PriorityMask__SHIFT 0xa
+#define UMCCH4_2_PerfMonCtl6__ReqSizeMask__SHIFT 0xe
+#define UMCCH4_2_PerfMonCtl6__BankSel__SHIFT 0x10
+#define UMCCH4_2_PerfMonCtl6__VCSel__SHIFT 0x18
+#define UMCCH4_2_PerfMonCtl6__SubChanMask__SHIFT 0x1d
+#define UMCCH4_2_PerfMonCtl6__Enable__SHIFT 0x1f
+#define UMCCH4_2_PerfMonCtl6__EventSelect_MASK 0x000000FFL
+#define UMCCH4_2_PerfMonCtl6__RdWrMask_MASK 0x00000300L
+#define UMCCH4_2_PerfMonCtl6__PriorityMask_MASK 0x00003C00L
+#define UMCCH4_2_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH4_2_PerfMonCtl6__BankSel_MASK 0x00FF0000L
+#define UMCCH4_2_PerfMonCtl6__VCSel_MASK 0x1F000000L
+#define UMCCH4_2_PerfMonCtl6__SubChanMask_MASK 0x60000000L
+#define UMCCH4_2_PerfMonCtl6__Enable_MASK 0x80000000L
+//UMCCH4_2_PerfMonCtr6_Lo
+#define UMCCH4_2_PerfMonCtr6_Lo__Data__SHIFT 0x0
+#define UMCCH4_2_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_2_PerfMonCtr6_Hi
+#define UMCCH4_2_PerfMonCtr6_Hi__Data__SHIFT 0x0
+#define UMCCH4_2_PerfMonCtr6_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_2_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH4_2_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH4_2_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_2_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L
+#define UMCCH4_2_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH4_2_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH4_2_PerfMonCtl7
+#define UMCCH4_2_PerfMonCtl7__EventSelect__SHIFT 0x0
+#define UMCCH4_2_PerfMonCtl7__RdWrMask__SHIFT 0x8
+#define UMCCH4_2_PerfMonCtl7__PriorityMask__SHIFT 0xa
+#define UMCCH4_2_PerfMonCtl7__ReqSizeMask__SHIFT 0xe
+#define UMCCH4_2_PerfMonCtl7__BankSel__SHIFT 0x10
+#define UMCCH4_2_PerfMonCtl7__VCSel__SHIFT 0x18
+#define UMCCH4_2_PerfMonCtl7__SubChanMask__SHIFT 0x1d
+#define UMCCH4_2_PerfMonCtl7__Enable__SHIFT 0x1f
+#define UMCCH4_2_PerfMonCtl7__EventSelect_MASK 0x000000FFL
+#define UMCCH4_2_PerfMonCtl7__RdWrMask_MASK 0x00000300L
+#define UMCCH4_2_PerfMonCtl7__PriorityMask_MASK 0x00003C00L
+#define UMCCH4_2_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH4_2_PerfMonCtl7__BankSel_MASK 0x00FF0000L
+#define UMCCH4_2_PerfMonCtl7__VCSel_MASK 0x1F000000L
+#define UMCCH4_2_PerfMonCtl7__SubChanMask_MASK 0x60000000L
+#define UMCCH4_2_PerfMonCtl7__Enable_MASK 0x80000000L
+//UMCCH4_2_PerfMonCtr7_Lo
+#define UMCCH4_2_PerfMonCtr7_Lo__Data__SHIFT 0x0
+#define UMCCH4_2_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_2_PerfMonCtr7_Hi
+#define UMCCH4_2_PerfMonCtr7_Hi__Data__SHIFT 0x0
+#define UMCCH4_2_PerfMonCtr7_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_2_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH4_2_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH4_2_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_2_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L
+#define UMCCH4_2_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH4_2_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH4_2_PerfMonCtl8
+#define UMCCH4_2_PerfMonCtl8__EventSelect__SHIFT 0x0
+#define UMCCH4_2_PerfMonCtl8__RdWrMask__SHIFT 0x8
+#define UMCCH4_2_PerfMonCtl8__PriorityMask__SHIFT 0xa
+#define UMCCH4_2_PerfMonCtl8__ReqSizeMask__SHIFT 0xe
+#define UMCCH4_2_PerfMonCtl8__BankSel__SHIFT 0x10
+#define UMCCH4_2_PerfMonCtl8__VCSel__SHIFT 0x18
+#define UMCCH4_2_PerfMonCtl8__SubChanMask__SHIFT 0x1d
+#define UMCCH4_2_PerfMonCtl8__Enable__SHIFT 0x1f
+#define UMCCH4_2_PerfMonCtl8__EventSelect_MASK 0x000000FFL
+#define UMCCH4_2_PerfMonCtl8__RdWrMask_MASK 0x00000300L
+#define UMCCH4_2_PerfMonCtl8__PriorityMask_MASK 0x00003C00L
+#define UMCCH4_2_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH4_2_PerfMonCtl8__BankSel_MASK 0x00FF0000L
+#define UMCCH4_2_PerfMonCtl8__VCSel_MASK 0x1F000000L
+#define UMCCH4_2_PerfMonCtl8__SubChanMask_MASK 0x60000000L
+#define UMCCH4_2_PerfMonCtl8__Enable_MASK 0x80000000L
+//UMCCH4_2_PerfMonCtr8_Lo
+#define UMCCH4_2_PerfMonCtr8_Lo__Data__SHIFT 0x0
+#define UMCCH4_2_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_2_PerfMonCtr8_Hi
+#define UMCCH4_2_PerfMonCtr8_Hi__Data__SHIFT 0x0
+#define UMCCH4_2_PerfMonCtr8_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_2_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH4_2_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH4_2_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_2_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L
+#define UMCCH4_2_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH4_2_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L
+
+
+// addressBlock: umc_w_phy_umc2_umcch5_umcchdec
+//UMCCH5_2_BaseAddrCS0
+#define UMCCH5_2_BaseAddrCS0__CSEnable__SHIFT 0x0
+#define UMCCH5_2_BaseAddrCS0__BaseAddr__SHIFT 0x1
+#define UMCCH5_2_BaseAddrCS0__CSEnable_MASK 0x00000001L
+#define UMCCH5_2_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL
+//UMCCH5_2_AddrMaskCS01
+#define UMCCH5_2_AddrMaskCS01__AddrMask__SHIFT 0x1
+#define UMCCH5_2_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL
+//UMCCH5_2_AddrSelCS01
+#define UMCCH5_2_AddrSelCS01__BankBit0__SHIFT 0x0
+#define UMCCH5_2_AddrSelCS01__BankBit1__SHIFT 0x4
+#define UMCCH5_2_AddrSelCS01__BankBit2__SHIFT 0x8
+#define UMCCH5_2_AddrSelCS01__BankBit3__SHIFT 0xc
+#define UMCCH5_2_AddrSelCS01__BankBit4__SHIFT 0x10
+#define UMCCH5_2_AddrSelCS01__RowLo__SHIFT 0x18
+#define UMCCH5_2_AddrSelCS01__RowHi__SHIFT 0x1c
+#define UMCCH5_2_AddrSelCS01__BankBit0_MASK 0x0000000FL
+#define UMCCH5_2_AddrSelCS01__BankBit1_MASK 0x000000F0L
+#define UMCCH5_2_AddrSelCS01__BankBit2_MASK 0x00000F00L
+#define UMCCH5_2_AddrSelCS01__BankBit3_MASK 0x0000F000L
+#define UMCCH5_2_AddrSelCS01__BankBit4_MASK 0x001F0000L
+#define UMCCH5_2_AddrSelCS01__RowLo_MASK 0x0F000000L
+#define UMCCH5_2_AddrSelCS01__RowHi_MASK 0xF0000000L
+//UMCCH5_2_AddrHashBank0
+#define UMCCH5_2_AddrHashBank0__XorEnable__SHIFT 0x0
+#define UMCCH5_2_AddrHashBank0__ColXor__SHIFT 0x1
+#define UMCCH5_2_AddrHashBank0__RowXor__SHIFT 0xe
+#define UMCCH5_2_AddrHashBank0__XorEnable_MASK 0x00000001L
+#define UMCCH5_2_AddrHashBank0__ColXor_MASK 0x00003FFEL
+#define UMCCH5_2_AddrHashBank0__RowXor_MASK 0xFFFFC000L
+//UMCCH5_2_AddrHashBank1
+#define UMCCH5_2_AddrHashBank1__XorEnable__SHIFT 0x0
+#define UMCCH5_2_AddrHashBank1__ColXor__SHIFT 0x1
+#define UMCCH5_2_AddrHashBank1__RowXor__SHIFT 0xe
+#define UMCCH5_2_AddrHashBank1__XorEnable_MASK 0x00000001L
+#define UMCCH5_2_AddrHashBank1__ColXor_MASK 0x00003FFEL
+#define UMCCH5_2_AddrHashBank1__RowXor_MASK 0xFFFFC000L
+//UMCCH5_2_AddrHashBank2
+#define UMCCH5_2_AddrHashBank2__XorEnable__SHIFT 0x0
+#define UMCCH5_2_AddrHashBank2__ColXor__SHIFT 0x1
+#define UMCCH5_2_AddrHashBank2__RowXor__SHIFT 0xe
+#define UMCCH5_2_AddrHashBank2__XorEnable_MASK 0x00000001L
+#define UMCCH5_2_AddrHashBank2__ColXor_MASK 0x00003FFEL
+#define UMCCH5_2_AddrHashBank2__RowXor_MASK 0xFFFFC000L
+//UMCCH5_2_AddrHashBank3
+#define UMCCH5_2_AddrHashBank3__XorEnable__SHIFT 0x0
+#define UMCCH5_2_AddrHashBank3__ColXor__SHIFT 0x1
+#define UMCCH5_2_AddrHashBank3__RowXor__SHIFT 0xe
+#define UMCCH5_2_AddrHashBank3__XorEnable_MASK 0x00000001L
+#define UMCCH5_2_AddrHashBank3__ColXor_MASK 0x00003FFEL
+#define UMCCH5_2_AddrHashBank3__RowXor_MASK 0xFFFFC000L
+//UMCCH5_2_AddrHashBank4
+#define UMCCH5_2_AddrHashBank4__XorEnable__SHIFT 0x0
+#define UMCCH5_2_AddrHashBank4__ColXor__SHIFT 0x1
+#define UMCCH5_2_AddrHashBank4__RowXor__SHIFT 0xe
+#define UMCCH5_2_AddrHashBank4__XorEnable_MASK 0x00000001L
+#define UMCCH5_2_AddrHashBank4__ColXor_MASK 0x00003FFEL
+#define UMCCH5_2_AddrHashBank4__RowXor_MASK 0xFFFFC000L
+//UMCCH5_2_AddrHashBank5
+#define UMCCH5_2_AddrHashBank5__XorEnable__SHIFT 0x0
+#define UMCCH5_2_AddrHashBank5__ColXor__SHIFT 0x1
+#define UMCCH5_2_AddrHashBank5__RowXor__SHIFT 0xe
+#define UMCCH5_2_AddrHashBank5__XorEnable_MASK 0x00000001L
+#define UMCCH5_2_AddrHashBank5__ColXor_MASK 0x00003FFEL
+#define UMCCH5_2_AddrHashBank5__RowXor_MASK 0xFFFFC000L
+//UMCCH5_2_EccErrCntSel
+#define UMCCH5_2_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0
+#define UMCCH5_2_EccErrCntSel__EccErrInt__SHIFT 0xc
+#define UMCCH5_2_EccErrCntSel__EccErrCntEn__SHIFT 0xf
+#define UMCCH5_2_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL
+#define UMCCH5_2_EccErrCntSel__EccErrInt_MASK 0x00003000L
+#define UMCCH5_2_EccErrCntSel__EccErrCntEn_MASK 0x00008000L
+//UMCCH5_2_EccErrCnt
+#define UMCCH5_2_EccErrCnt__EccErrCnt__SHIFT 0x0
+#define UMCCH5_2_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL
+//UMCCH5_2_PerfMonCtlClk
+#define UMCCH5_2_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0
+#define UMCCH5_2_PerfMonCtlClk__ClkGate__SHIFT 0x16
+#define UMCCH5_2_PerfMonCtlClk__GlblReset__SHIFT 0x18
+#define UMCCH5_2_PerfMonCtlClk__GlblMonEn__SHIFT 0x19
+#define UMCCH5_2_PerfMonCtlClk__NumCounters__SHIFT 0x1a
+#define UMCCH5_2_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f
+#define UMCCH5_2_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL
+#define UMCCH5_2_PerfMonCtlClk__ClkGate_MASK 0x00400000L
+#define UMCCH5_2_PerfMonCtlClk__GlblReset_MASK 0x01000000L
+#define UMCCH5_2_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L
+#define UMCCH5_2_PerfMonCtlClk__NumCounters_MASK 0x3C000000L
+#define UMCCH5_2_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L
+//UMCCH5_2_PerfMonCtrClk_Lo
+#define UMCCH5_2_PerfMonCtrClk_Lo__Data__SHIFT 0x0
+#define UMCCH5_2_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_2_PerfMonCtrClk_Hi
+#define UMCCH5_2_PerfMonCtrClk_Hi__Data__SHIFT 0x0
+#define UMCCH5_2_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_2_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_2_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L
+//UMCCH5_2_PerfMonCtl1
+#define UMCCH5_2_PerfMonCtl1__EventSelect__SHIFT 0x0
+#define UMCCH5_2_PerfMonCtl1__RdWrMask__SHIFT 0x8
+#define UMCCH5_2_PerfMonCtl1__PriorityMask__SHIFT 0xa
+#define UMCCH5_2_PerfMonCtl1__ReqSizeMask__SHIFT 0xe
+#define UMCCH5_2_PerfMonCtl1__BankSel__SHIFT 0x10
+#define UMCCH5_2_PerfMonCtl1__VCSel__SHIFT 0x18
+#define UMCCH5_2_PerfMonCtl1__SubChanMask__SHIFT 0x1d
+#define UMCCH5_2_PerfMonCtl1__Enable__SHIFT 0x1f
+#define UMCCH5_2_PerfMonCtl1__EventSelect_MASK 0x000000FFL
+#define UMCCH5_2_PerfMonCtl1__RdWrMask_MASK 0x00000300L
+#define UMCCH5_2_PerfMonCtl1__PriorityMask_MASK 0x00003C00L
+#define UMCCH5_2_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH5_2_PerfMonCtl1__BankSel_MASK 0x00FF0000L
+#define UMCCH5_2_PerfMonCtl1__VCSel_MASK 0x1F000000L
+#define UMCCH5_2_PerfMonCtl1__SubChanMask_MASK 0x60000000L
+#define UMCCH5_2_PerfMonCtl1__Enable_MASK 0x80000000L
+//UMCCH5_2_PerfMonCtr1_Lo
+#define UMCCH5_2_PerfMonCtr1_Lo__Data__SHIFT 0x0
+#define UMCCH5_2_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_2_PerfMonCtr1_Hi
+#define UMCCH5_2_PerfMonCtr1_Hi__Data__SHIFT 0x0
+#define UMCCH5_2_PerfMonCtr1_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_2_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH5_2_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH5_2_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_2_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L
+#define UMCCH5_2_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH5_2_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH5_2_PerfMonCtl2
+#define UMCCH5_2_PerfMonCtl2__EventSelect__SHIFT 0x0
+#define UMCCH5_2_PerfMonCtl2__RdWrMask__SHIFT 0x8
+#define UMCCH5_2_PerfMonCtl2__PriorityMask__SHIFT 0xa
+#define UMCCH5_2_PerfMonCtl2__ReqSizeMask__SHIFT 0xe
+#define UMCCH5_2_PerfMonCtl2__BankSel__SHIFT 0x10
+#define UMCCH5_2_PerfMonCtl2__VCSel__SHIFT 0x18
+#define UMCCH5_2_PerfMonCtl2__SubChanMask__SHIFT 0x1d
+#define UMCCH5_2_PerfMonCtl2__Enable__SHIFT 0x1f
+#define UMCCH5_2_PerfMonCtl2__EventSelect_MASK 0x000000FFL
+#define UMCCH5_2_PerfMonCtl2__RdWrMask_MASK 0x00000300L
+#define UMCCH5_2_PerfMonCtl2__PriorityMask_MASK 0x00003C00L
+#define UMCCH5_2_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH5_2_PerfMonCtl2__BankSel_MASK 0x00FF0000L
+#define UMCCH5_2_PerfMonCtl2__VCSel_MASK 0x1F000000L
+#define UMCCH5_2_PerfMonCtl2__SubChanMask_MASK 0x60000000L
+#define UMCCH5_2_PerfMonCtl2__Enable_MASK 0x80000000L
+//UMCCH5_2_PerfMonCtr2_Lo
+#define UMCCH5_2_PerfMonCtr2_Lo__Data__SHIFT 0x0
+#define UMCCH5_2_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_2_PerfMonCtr2_Hi
+#define UMCCH5_2_PerfMonCtr2_Hi__Data__SHIFT 0x0
+#define UMCCH5_2_PerfMonCtr2_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_2_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH5_2_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH5_2_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_2_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L
+#define UMCCH5_2_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH5_2_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH5_2_PerfMonCtl3
+#define UMCCH5_2_PerfMonCtl3__EventSelect__SHIFT 0x0
+#define UMCCH5_2_PerfMonCtl3__RdWrMask__SHIFT 0x8
+#define UMCCH5_2_PerfMonCtl3__PriorityMask__SHIFT 0xa
+#define UMCCH5_2_PerfMonCtl3__ReqSizeMask__SHIFT 0xe
+#define UMCCH5_2_PerfMonCtl3__BankSel__SHIFT 0x10
+#define UMCCH5_2_PerfMonCtl3__VCSel__SHIFT 0x18
+#define UMCCH5_2_PerfMonCtl3__SubChanMask__SHIFT 0x1d
+#define UMCCH5_2_PerfMonCtl3__Enable__SHIFT 0x1f
+#define UMCCH5_2_PerfMonCtl3__EventSelect_MASK 0x000000FFL
+#define UMCCH5_2_PerfMonCtl3__RdWrMask_MASK 0x00000300L
+#define UMCCH5_2_PerfMonCtl3__PriorityMask_MASK 0x00003C00L
+#define UMCCH5_2_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH5_2_PerfMonCtl3__BankSel_MASK 0x00FF0000L
+#define UMCCH5_2_PerfMonCtl3__VCSel_MASK 0x1F000000L
+#define UMCCH5_2_PerfMonCtl3__SubChanMask_MASK 0x60000000L
+#define UMCCH5_2_PerfMonCtl3__Enable_MASK 0x80000000L
+//UMCCH5_2_PerfMonCtr3_Lo
+#define UMCCH5_2_PerfMonCtr3_Lo__Data__SHIFT 0x0
+#define UMCCH5_2_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_2_PerfMonCtr3_Hi
+#define UMCCH5_2_PerfMonCtr3_Hi__Data__SHIFT 0x0
+#define UMCCH5_2_PerfMonCtr3_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_2_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH5_2_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH5_2_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_2_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L
+#define UMCCH5_2_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH5_2_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH5_2_PerfMonCtl4
+#define UMCCH5_2_PerfMonCtl4__EventSelect__SHIFT 0x0
+#define UMCCH5_2_PerfMonCtl4__RdWrMask__SHIFT 0x8
+#define UMCCH5_2_PerfMonCtl4__PriorityMask__SHIFT 0xa
+#define UMCCH5_2_PerfMonCtl4__ReqSizeMask__SHIFT 0xe
+#define UMCCH5_2_PerfMonCtl4__BankSel__SHIFT 0x10
+#define UMCCH5_2_PerfMonCtl4__VCSel__SHIFT 0x18
+#define UMCCH5_2_PerfMonCtl4__SubChanMask__SHIFT 0x1d
+#define UMCCH5_2_PerfMonCtl4__Enable__SHIFT 0x1f
+#define UMCCH5_2_PerfMonCtl4__EventSelect_MASK 0x000000FFL
+#define UMCCH5_2_PerfMonCtl4__RdWrMask_MASK 0x00000300L
+#define UMCCH5_2_PerfMonCtl4__PriorityMask_MASK 0x00003C00L
+#define UMCCH5_2_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH5_2_PerfMonCtl4__BankSel_MASK 0x00FF0000L
+#define UMCCH5_2_PerfMonCtl4__VCSel_MASK 0x1F000000L
+#define UMCCH5_2_PerfMonCtl4__SubChanMask_MASK 0x60000000L
+#define UMCCH5_2_PerfMonCtl4__Enable_MASK 0x80000000L
+//UMCCH5_2_PerfMonCtr4_Lo
+#define UMCCH5_2_PerfMonCtr4_Lo__Data__SHIFT 0x0
+#define UMCCH5_2_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_2_PerfMonCtr4_Hi
+#define UMCCH5_2_PerfMonCtr4_Hi__Data__SHIFT 0x0
+#define UMCCH5_2_PerfMonCtr4_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_2_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH5_2_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH5_2_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_2_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L
+#define UMCCH5_2_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH5_2_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH5_2_PerfMonCtl5
+#define UMCCH5_2_PerfMonCtl5__EventSelect__SHIFT 0x0
+#define UMCCH5_2_PerfMonCtl5__RdWrMask__SHIFT 0x8
+#define UMCCH5_2_PerfMonCtl5__PriorityMask__SHIFT 0xa
+#define UMCCH5_2_PerfMonCtl5__ReqSizeMask__SHIFT 0xe
+#define UMCCH5_2_PerfMonCtl5__BankSel__SHIFT 0x10
+#define UMCCH5_2_PerfMonCtl5__VCSel__SHIFT 0x18
+#define UMCCH5_2_PerfMonCtl5__SubChanMask__SHIFT 0x1d
+#define UMCCH5_2_PerfMonCtl5__Enable__SHIFT 0x1f
+#define UMCCH5_2_PerfMonCtl5__EventSelect_MASK 0x000000FFL
+#define UMCCH5_2_PerfMonCtl5__RdWrMask_MASK 0x00000300L
+#define UMCCH5_2_PerfMonCtl5__PriorityMask_MASK 0x00003C00L
+#define UMCCH5_2_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH5_2_PerfMonCtl5__BankSel_MASK 0x00FF0000L
+#define UMCCH5_2_PerfMonCtl5__VCSel_MASK 0x1F000000L
+#define UMCCH5_2_PerfMonCtl5__SubChanMask_MASK 0x60000000L
+#define UMCCH5_2_PerfMonCtl5__Enable_MASK 0x80000000L
+//UMCCH5_2_PerfMonCtr5_Lo
+#define UMCCH5_2_PerfMonCtr5_Lo__Data__SHIFT 0x0
+#define UMCCH5_2_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_2_PerfMonCtr5_Hi
+#define UMCCH5_2_PerfMonCtr5_Hi__Data__SHIFT 0x0
+#define UMCCH5_2_PerfMonCtr5_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_2_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH5_2_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH5_2_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_2_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L
+#define UMCCH5_2_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH5_2_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH5_2_PerfMonCtl6
+#define UMCCH5_2_PerfMonCtl6__EventSelect__SHIFT 0x0
+#define UMCCH5_2_PerfMonCtl6__RdWrMask__SHIFT 0x8
+#define UMCCH5_2_PerfMonCtl6__PriorityMask__SHIFT 0xa
+#define UMCCH5_2_PerfMonCtl6__ReqSizeMask__SHIFT 0xe
+#define UMCCH5_2_PerfMonCtl6__BankSel__SHIFT 0x10
+#define UMCCH5_2_PerfMonCtl6__VCSel__SHIFT 0x18
+#define UMCCH5_2_PerfMonCtl6__SubChanMask__SHIFT 0x1d
+#define UMCCH5_2_PerfMonCtl6__Enable__SHIFT 0x1f
+#define UMCCH5_2_PerfMonCtl6__EventSelect_MASK 0x000000FFL
+#define UMCCH5_2_PerfMonCtl6__RdWrMask_MASK 0x00000300L
+#define UMCCH5_2_PerfMonCtl6__PriorityMask_MASK 0x00003C00L
+#define UMCCH5_2_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH5_2_PerfMonCtl6__BankSel_MASK 0x00FF0000L
+#define UMCCH5_2_PerfMonCtl6__VCSel_MASK 0x1F000000L
+#define UMCCH5_2_PerfMonCtl6__SubChanMask_MASK 0x60000000L
+#define UMCCH5_2_PerfMonCtl6__Enable_MASK 0x80000000L
+//UMCCH5_2_PerfMonCtr6_Lo
+#define UMCCH5_2_PerfMonCtr6_Lo__Data__SHIFT 0x0
+#define UMCCH5_2_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_2_PerfMonCtr6_Hi
+#define UMCCH5_2_PerfMonCtr6_Hi__Data__SHIFT 0x0
+#define UMCCH5_2_PerfMonCtr6_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_2_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH5_2_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH5_2_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_2_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L
+#define UMCCH5_2_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH5_2_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH5_2_PerfMonCtl7
+#define UMCCH5_2_PerfMonCtl7__EventSelect__SHIFT 0x0
+#define UMCCH5_2_PerfMonCtl7__RdWrMask__SHIFT 0x8
+#define UMCCH5_2_PerfMonCtl7__PriorityMask__SHIFT 0xa
+#define UMCCH5_2_PerfMonCtl7__ReqSizeMask__SHIFT 0xe
+#define UMCCH5_2_PerfMonCtl7__BankSel__SHIFT 0x10
+#define UMCCH5_2_PerfMonCtl7__VCSel__SHIFT 0x18
+#define UMCCH5_2_PerfMonCtl7__SubChanMask__SHIFT 0x1d
+#define UMCCH5_2_PerfMonCtl7__Enable__SHIFT 0x1f
+#define UMCCH5_2_PerfMonCtl7__EventSelect_MASK 0x000000FFL
+#define UMCCH5_2_PerfMonCtl7__RdWrMask_MASK 0x00000300L
+#define UMCCH5_2_PerfMonCtl7__PriorityMask_MASK 0x00003C00L
+#define UMCCH5_2_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH5_2_PerfMonCtl7__BankSel_MASK 0x00FF0000L
+#define UMCCH5_2_PerfMonCtl7__VCSel_MASK 0x1F000000L
+#define UMCCH5_2_PerfMonCtl7__SubChanMask_MASK 0x60000000L
+#define UMCCH5_2_PerfMonCtl7__Enable_MASK 0x80000000L
+//UMCCH5_2_PerfMonCtr7_Lo
+#define UMCCH5_2_PerfMonCtr7_Lo__Data__SHIFT 0x0
+#define UMCCH5_2_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_2_PerfMonCtr7_Hi
+#define UMCCH5_2_PerfMonCtr7_Hi__Data__SHIFT 0x0
+#define UMCCH5_2_PerfMonCtr7_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_2_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH5_2_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH5_2_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_2_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L
+#define UMCCH5_2_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH5_2_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH5_2_PerfMonCtl8
+#define UMCCH5_2_PerfMonCtl8__EventSelect__SHIFT 0x0
+#define UMCCH5_2_PerfMonCtl8__RdWrMask__SHIFT 0x8
+#define UMCCH5_2_PerfMonCtl8__PriorityMask__SHIFT 0xa
+#define UMCCH5_2_PerfMonCtl8__ReqSizeMask__SHIFT 0xe
+#define UMCCH5_2_PerfMonCtl8__BankSel__SHIFT 0x10
+#define UMCCH5_2_PerfMonCtl8__VCSel__SHIFT 0x18
+#define UMCCH5_2_PerfMonCtl8__SubChanMask__SHIFT 0x1d
+#define UMCCH5_2_PerfMonCtl8__Enable__SHIFT 0x1f
+#define UMCCH5_2_PerfMonCtl8__EventSelect_MASK 0x000000FFL
+#define UMCCH5_2_PerfMonCtl8__RdWrMask_MASK 0x00000300L
+#define UMCCH5_2_PerfMonCtl8__PriorityMask_MASK 0x00003C00L
+#define UMCCH5_2_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH5_2_PerfMonCtl8__BankSel_MASK 0x00FF0000L
+#define UMCCH5_2_PerfMonCtl8__VCSel_MASK 0x1F000000L
+#define UMCCH5_2_PerfMonCtl8__SubChanMask_MASK 0x60000000L
+#define UMCCH5_2_PerfMonCtl8__Enable_MASK 0x80000000L
+//UMCCH5_2_PerfMonCtr8_Lo
+#define UMCCH5_2_PerfMonCtr8_Lo__Data__SHIFT 0x0
+#define UMCCH5_2_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_2_PerfMonCtr8_Hi
+#define UMCCH5_2_PerfMonCtr8_Hi__Data__SHIFT 0x0
+#define UMCCH5_2_PerfMonCtr8_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_2_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH5_2_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH5_2_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_2_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L
+#define UMCCH5_2_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH5_2_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L
+
+
+// addressBlock: umc_w_phy_umc2_umcch6_umcchdec
+//UMCCH6_2_BaseAddrCS0
+#define UMCCH6_2_BaseAddrCS0__CSEnable__SHIFT 0x0
+#define UMCCH6_2_BaseAddrCS0__BaseAddr__SHIFT 0x1
+#define UMCCH6_2_BaseAddrCS0__CSEnable_MASK 0x00000001L
+#define UMCCH6_2_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL
+//UMCCH6_2_AddrMaskCS01
+#define UMCCH6_2_AddrMaskCS01__AddrMask__SHIFT 0x1
+#define UMCCH6_2_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL
+//UMCCH6_2_AddrSelCS01
+#define UMCCH6_2_AddrSelCS01__BankBit0__SHIFT 0x0
+#define UMCCH6_2_AddrSelCS01__BankBit1__SHIFT 0x4
+#define UMCCH6_2_AddrSelCS01__BankBit2__SHIFT 0x8
+#define UMCCH6_2_AddrSelCS01__BankBit3__SHIFT 0xc
+#define UMCCH6_2_AddrSelCS01__BankBit4__SHIFT 0x10
+#define UMCCH6_2_AddrSelCS01__RowLo__SHIFT 0x18
+#define UMCCH6_2_AddrSelCS01__RowHi__SHIFT 0x1c
+#define UMCCH6_2_AddrSelCS01__BankBit0_MASK 0x0000000FL
+#define UMCCH6_2_AddrSelCS01__BankBit1_MASK 0x000000F0L
+#define UMCCH6_2_AddrSelCS01__BankBit2_MASK 0x00000F00L
+#define UMCCH6_2_AddrSelCS01__BankBit3_MASK 0x0000F000L
+#define UMCCH6_2_AddrSelCS01__BankBit4_MASK 0x001F0000L
+#define UMCCH6_2_AddrSelCS01__RowLo_MASK 0x0F000000L
+#define UMCCH6_2_AddrSelCS01__RowHi_MASK 0xF0000000L
+//UMCCH6_2_AddrHashBank0
+#define UMCCH6_2_AddrHashBank0__XorEnable__SHIFT 0x0
+#define UMCCH6_2_AddrHashBank0__ColXor__SHIFT 0x1
+#define UMCCH6_2_AddrHashBank0__RowXor__SHIFT 0xe
+#define UMCCH6_2_AddrHashBank0__XorEnable_MASK 0x00000001L
+#define UMCCH6_2_AddrHashBank0__ColXor_MASK 0x00003FFEL
+#define UMCCH6_2_AddrHashBank0__RowXor_MASK 0xFFFFC000L
+//UMCCH6_2_AddrHashBank1
+#define UMCCH6_2_AddrHashBank1__XorEnable__SHIFT 0x0
+#define UMCCH6_2_AddrHashBank1__ColXor__SHIFT 0x1
+#define UMCCH6_2_AddrHashBank1__RowXor__SHIFT 0xe
+#define UMCCH6_2_AddrHashBank1__XorEnable_MASK 0x00000001L
+#define UMCCH6_2_AddrHashBank1__ColXor_MASK 0x00003FFEL
+#define UMCCH6_2_AddrHashBank1__RowXor_MASK 0xFFFFC000L
+//UMCCH6_2_AddrHashBank2
+#define UMCCH6_2_AddrHashBank2__XorEnable__SHIFT 0x0
+#define UMCCH6_2_AddrHashBank2__ColXor__SHIFT 0x1
+#define UMCCH6_2_AddrHashBank2__RowXor__SHIFT 0xe
+#define UMCCH6_2_AddrHashBank2__XorEnable_MASK 0x00000001L
+#define UMCCH6_2_AddrHashBank2__ColXor_MASK 0x00003FFEL
+#define UMCCH6_2_AddrHashBank2__RowXor_MASK 0xFFFFC000L
+//UMCCH6_2_AddrHashBank3
+#define UMCCH6_2_AddrHashBank3__XorEnable__SHIFT 0x0
+#define UMCCH6_2_AddrHashBank3__ColXor__SHIFT 0x1
+#define UMCCH6_2_AddrHashBank3__RowXor__SHIFT 0xe
+#define UMCCH6_2_AddrHashBank3__XorEnable_MASK 0x00000001L
+#define UMCCH6_2_AddrHashBank3__ColXor_MASK 0x00003FFEL
+#define UMCCH6_2_AddrHashBank3__RowXor_MASK 0xFFFFC000L
+//UMCCH6_2_AddrHashBank4
+#define UMCCH6_2_AddrHashBank4__XorEnable__SHIFT 0x0
+#define UMCCH6_2_AddrHashBank4__ColXor__SHIFT 0x1
+#define UMCCH6_2_AddrHashBank4__RowXor__SHIFT 0xe
+#define UMCCH6_2_AddrHashBank4__XorEnable_MASK 0x00000001L
+#define UMCCH6_2_AddrHashBank4__ColXor_MASK 0x00003FFEL
+#define UMCCH6_2_AddrHashBank4__RowXor_MASK 0xFFFFC000L
+//UMCCH6_2_AddrHashBank5
+#define UMCCH6_2_AddrHashBank5__XorEnable__SHIFT 0x0
+#define UMCCH6_2_AddrHashBank5__ColXor__SHIFT 0x1
+#define UMCCH6_2_AddrHashBank5__RowXor__SHIFT 0xe
+#define UMCCH6_2_AddrHashBank5__XorEnable_MASK 0x00000001L
+#define UMCCH6_2_AddrHashBank5__ColXor_MASK 0x00003FFEL
+#define UMCCH6_2_AddrHashBank5__RowXor_MASK 0xFFFFC000L
+//UMCCH6_2_EccErrCntSel
+#define UMCCH6_2_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0
+#define UMCCH6_2_EccErrCntSel__EccErrInt__SHIFT 0xc
+#define UMCCH6_2_EccErrCntSel__EccErrCntEn__SHIFT 0xf
+#define UMCCH6_2_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL
+#define UMCCH6_2_EccErrCntSel__EccErrInt_MASK 0x00003000L
+#define UMCCH6_2_EccErrCntSel__EccErrCntEn_MASK 0x00008000L
+//UMCCH6_2_EccErrCnt
+#define UMCCH6_2_EccErrCnt__EccErrCnt__SHIFT 0x0
+#define UMCCH6_2_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL
+//UMCCH6_2_PerfMonCtlClk
+#define UMCCH6_2_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0
+#define UMCCH6_2_PerfMonCtlClk__ClkGate__SHIFT 0x16
+#define UMCCH6_2_PerfMonCtlClk__GlblReset__SHIFT 0x18
+#define UMCCH6_2_PerfMonCtlClk__GlblMonEn__SHIFT 0x19
+#define UMCCH6_2_PerfMonCtlClk__NumCounters__SHIFT 0x1a
+#define UMCCH6_2_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f
+#define UMCCH6_2_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL
+#define UMCCH6_2_PerfMonCtlClk__ClkGate_MASK 0x00400000L
+#define UMCCH6_2_PerfMonCtlClk__GlblReset_MASK 0x01000000L
+#define UMCCH6_2_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L
+#define UMCCH6_2_PerfMonCtlClk__NumCounters_MASK 0x3C000000L
+#define UMCCH6_2_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L
+//UMCCH6_2_PerfMonCtrClk_Lo
+#define UMCCH6_2_PerfMonCtrClk_Lo__Data__SHIFT 0x0
+#define UMCCH6_2_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_2_PerfMonCtrClk_Hi
+#define UMCCH6_2_PerfMonCtrClk_Hi__Data__SHIFT 0x0
+#define UMCCH6_2_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_2_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_2_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L
+//UMCCH6_2_PerfMonCtl1
+#define UMCCH6_2_PerfMonCtl1__EventSelect__SHIFT 0x0
+#define UMCCH6_2_PerfMonCtl1__RdWrMask__SHIFT 0x8
+#define UMCCH6_2_PerfMonCtl1__PriorityMask__SHIFT 0xa
+#define UMCCH6_2_PerfMonCtl1__ReqSizeMask__SHIFT 0xe
+#define UMCCH6_2_PerfMonCtl1__BankSel__SHIFT 0x10
+#define UMCCH6_2_PerfMonCtl1__VCSel__SHIFT 0x18
+#define UMCCH6_2_PerfMonCtl1__SubChanMask__SHIFT 0x1d
+#define UMCCH6_2_PerfMonCtl1__Enable__SHIFT 0x1f
+#define UMCCH6_2_PerfMonCtl1__EventSelect_MASK 0x000000FFL
+#define UMCCH6_2_PerfMonCtl1__RdWrMask_MASK 0x00000300L
+#define UMCCH6_2_PerfMonCtl1__PriorityMask_MASK 0x00003C00L
+#define UMCCH6_2_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH6_2_PerfMonCtl1__BankSel_MASK 0x00FF0000L
+#define UMCCH6_2_PerfMonCtl1__VCSel_MASK 0x1F000000L
+#define UMCCH6_2_PerfMonCtl1__SubChanMask_MASK 0x60000000L
+#define UMCCH6_2_PerfMonCtl1__Enable_MASK 0x80000000L
+//UMCCH6_2_PerfMonCtr1_Lo
+#define UMCCH6_2_PerfMonCtr1_Lo__Data__SHIFT 0x0
+#define UMCCH6_2_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_2_PerfMonCtr1_Hi
+#define UMCCH6_2_PerfMonCtr1_Hi__Data__SHIFT 0x0
+#define UMCCH6_2_PerfMonCtr1_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_2_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH6_2_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH6_2_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_2_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L
+#define UMCCH6_2_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH6_2_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH6_2_PerfMonCtl2
+#define UMCCH6_2_PerfMonCtl2__EventSelect__SHIFT 0x0
+#define UMCCH6_2_PerfMonCtl2__RdWrMask__SHIFT 0x8
+#define UMCCH6_2_PerfMonCtl2__PriorityMask__SHIFT 0xa
+#define UMCCH6_2_PerfMonCtl2__ReqSizeMask__SHIFT 0xe
+#define UMCCH6_2_PerfMonCtl2__BankSel__SHIFT 0x10
+#define UMCCH6_2_PerfMonCtl2__VCSel__SHIFT 0x18
+#define UMCCH6_2_PerfMonCtl2__SubChanMask__SHIFT 0x1d
+#define UMCCH6_2_PerfMonCtl2__Enable__SHIFT 0x1f
+#define UMCCH6_2_PerfMonCtl2__EventSelect_MASK 0x000000FFL
+#define UMCCH6_2_PerfMonCtl2__RdWrMask_MASK 0x00000300L
+#define UMCCH6_2_PerfMonCtl2__PriorityMask_MASK 0x00003C00L
+#define UMCCH6_2_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH6_2_PerfMonCtl2__BankSel_MASK 0x00FF0000L
+#define UMCCH6_2_PerfMonCtl2__VCSel_MASK 0x1F000000L
+#define UMCCH6_2_PerfMonCtl2__SubChanMask_MASK 0x60000000L
+#define UMCCH6_2_PerfMonCtl2__Enable_MASK 0x80000000L
+//UMCCH6_2_PerfMonCtr2_Lo
+#define UMCCH6_2_PerfMonCtr2_Lo__Data__SHIFT 0x0
+#define UMCCH6_2_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_2_PerfMonCtr2_Hi
+#define UMCCH6_2_PerfMonCtr2_Hi__Data__SHIFT 0x0
+#define UMCCH6_2_PerfMonCtr2_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_2_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH6_2_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH6_2_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_2_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L
+#define UMCCH6_2_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH6_2_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH6_2_PerfMonCtl3
+#define UMCCH6_2_PerfMonCtl3__EventSelect__SHIFT 0x0
+#define UMCCH6_2_PerfMonCtl3__RdWrMask__SHIFT 0x8
+#define UMCCH6_2_PerfMonCtl3__PriorityMask__SHIFT 0xa
+#define UMCCH6_2_PerfMonCtl3__ReqSizeMask__SHIFT 0xe
+#define UMCCH6_2_PerfMonCtl3__BankSel__SHIFT 0x10
+#define UMCCH6_2_PerfMonCtl3__VCSel__SHIFT 0x18
+#define UMCCH6_2_PerfMonCtl3__SubChanMask__SHIFT 0x1d
+#define UMCCH6_2_PerfMonCtl3__Enable__SHIFT 0x1f
+#define UMCCH6_2_PerfMonCtl3__EventSelect_MASK 0x000000FFL
+#define UMCCH6_2_PerfMonCtl3__RdWrMask_MASK 0x00000300L
+#define UMCCH6_2_PerfMonCtl3__PriorityMask_MASK 0x00003C00L
+#define UMCCH6_2_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH6_2_PerfMonCtl3__BankSel_MASK 0x00FF0000L
+#define UMCCH6_2_PerfMonCtl3__VCSel_MASK 0x1F000000L
+#define UMCCH6_2_PerfMonCtl3__SubChanMask_MASK 0x60000000L
+#define UMCCH6_2_PerfMonCtl3__Enable_MASK 0x80000000L
+//UMCCH6_2_PerfMonCtr3_Lo
+#define UMCCH6_2_PerfMonCtr3_Lo__Data__SHIFT 0x0
+#define UMCCH6_2_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_2_PerfMonCtr3_Hi
+#define UMCCH6_2_PerfMonCtr3_Hi__Data__SHIFT 0x0
+#define UMCCH6_2_PerfMonCtr3_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_2_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH6_2_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH6_2_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_2_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L
+#define UMCCH6_2_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH6_2_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH6_2_PerfMonCtl4
+#define UMCCH6_2_PerfMonCtl4__EventSelect__SHIFT 0x0
+#define UMCCH6_2_PerfMonCtl4__RdWrMask__SHIFT 0x8
+#define UMCCH6_2_PerfMonCtl4__PriorityMask__SHIFT 0xa
+#define UMCCH6_2_PerfMonCtl4__ReqSizeMask__SHIFT 0xe
+#define UMCCH6_2_PerfMonCtl4__BankSel__SHIFT 0x10
+#define UMCCH6_2_PerfMonCtl4__VCSel__SHIFT 0x18
+#define UMCCH6_2_PerfMonCtl4__SubChanMask__SHIFT 0x1d
+#define UMCCH6_2_PerfMonCtl4__Enable__SHIFT 0x1f
+#define UMCCH6_2_PerfMonCtl4__EventSelect_MASK 0x000000FFL
+#define UMCCH6_2_PerfMonCtl4__RdWrMask_MASK 0x00000300L
+#define UMCCH6_2_PerfMonCtl4__PriorityMask_MASK 0x00003C00L
+#define UMCCH6_2_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH6_2_PerfMonCtl4__BankSel_MASK 0x00FF0000L
+#define UMCCH6_2_PerfMonCtl4__VCSel_MASK 0x1F000000L
+#define UMCCH6_2_PerfMonCtl4__SubChanMask_MASK 0x60000000L
+#define UMCCH6_2_PerfMonCtl4__Enable_MASK 0x80000000L
+//UMCCH6_2_PerfMonCtr4_Lo
+#define UMCCH6_2_PerfMonCtr4_Lo__Data__SHIFT 0x0
+#define UMCCH6_2_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_2_PerfMonCtr4_Hi
+#define UMCCH6_2_PerfMonCtr4_Hi__Data__SHIFT 0x0
+#define UMCCH6_2_PerfMonCtr4_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_2_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH6_2_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH6_2_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_2_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L
+#define UMCCH6_2_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH6_2_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH6_2_PerfMonCtl5
+#define UMCCH6_2_PerfMonCtl5__EventSelect__SHIFT 0x0
+#define UMCCH6_2_PerfMonCtl5__RdWrMask__SHIFT 0x8
+#define UMCCH6_2_PerfMonCtl5__PriorityMask__SHIFT 0xa
+#define UMCCH6_2_PerfMonCtl5__ReqSizeMask__SHIFT 0xe
+#define UMCCH6_2_PerfMonCtl5__BankSel__SHIFT 0x10
+#define UMCCH6_2_PerfMonCtl5__VCSel__SHIFT 0x18
+#define UMCCH6_2_PerfMonCtl5__SubChanMask__SHIFT 0x1d
+#define UMCCH6_2_PerfMonCtl5__Enable__SHIFT 0x1f
+#define UMCCH6_2_PerfMonCtl5__EventSelect_MASK 0x000000FFL
+#define UMCCH6_2_PerfMonCtl5__RdWrMask_MASK 0x00000300L
+#define UMCCH6_2_PerfMonCtl5__PriorityMask_MASK 0x00003C00L
+#define UMCCH6_2_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH6_2_PerfMonCtl5__BankSel_MASK 0x00FF0000L
+#define UMCCH6_2_PerfMonCtl5__VCSel_MASK 0x1F000000L
+#define UMCCH6_2_PerfMonCtl5__SubChanMask_MASK 0x60000000L
+#define UMCCH6_2_PerfMonCtl5__Enable_MASK 0x80000000L
+//UMCCH6_2_PerfMonCtr5_Lo
+#define UMCCH6_2_PerfMonCtr5_Lo__Data__SHIFT 0x0
+#define UMCCH6_2_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_2_PerfMonCtr5_Hi
+#define UMCCH6_2_PerfMonCtr5_Hi__Data__SHIFT 0x0
+#define UMCCH6_2_PerfMonCtr5_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_2_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH6_2_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH6_2_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_2_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L
+#define UMCCH6_2_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH6_2_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH6_2_PerfMonCtl6
+#define UMCCH6_2_PerfMonCtl6__EventSelect__SHIFT 0x0
+#define UMCCH6_2_PerfMonCtl6__RdWrMask__SHIFT 0x8
+#define UMCCH6_2_PerfMonCtl6__PriorityMask__SHIFT 0xa
+#define UMCCH6_2_PerfMonCtl6__ReqSizeMask__SHIFT 0xe
+#define UMCCH6_2_PerfMonCtl6__BankSel__SHIFT 0x10
+#define UMCCH6_2_PerfMonCtl6__VCSel__SHIFT 0x18
+#define UMCCH6_2_PerfMonCtl6__SubChanMask__SHIFT 0x1d
+#define UMCCH6_2_PerfMonCtl6__Enable__SHIFT 0x1f
+#define UMCCH6_2_PerfMonCtl6__EventSelect_MASK 0x000000FFL
+#define UMCCH6_2_PerfMonCtl6__RdWrMask_MASK 0x00000300L
+#define UMCCH6_2_PerfMonCtl6__PriorityMask_MASK 0x00003C00L
+#define UMCCH6_2_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH6_2_PerfMonCtl6__BankSel_MASK 0x00FF0000L
+#define UMCCH6_2_PerfMonCtl6__VCSel_MASK 0x1F000000L
+#define UMCCH6_2_PerfMonCtl6__SubChanMask_MASK 0x60000000L
+#define UMCCH6_2_PerfMonCtl6__Enable_MASK 0x80000000L
+//UMCCH6_2_PerfMonCtr6_Lo
+#define UMCCH6_2_PerfMonCtr6_Lo__Data__SHIFT 0x0
+#define UMCCH6_2_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_2_PerfMonCtr6_Hi
+#define UMCCH6_2_PerfMonCtr6_Hi__Data__SHIFT 0x0
+#define UMCCH6_2_PerfMonCtr6_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_2_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH6_2_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH6_2_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_2_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L
+#define UMCCH6_2_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH6_2_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH6_2_PerfMonCtl7
+#define UMCCH6_2_PerfMonCtl7__EventSelect__SHIFT 0x0
+#define UMCCH6_2_PerfMonCtl7__RdWrMask__SHIFT 0x8
+#define UMCCH6_2_PerfMonCtl7__PriorityMask__SHIFT 0xa
+#define UMCCH6_2_PerfMonCtl7__ReqSizeMask__SHIFT 0xe
+#define UMCCH6_2_PerfMonCtl7__BankSel__SHIFT 0x10
+#define UMCCH6_2_PerfMonCtl7__VCSel__SHIFT 0x18
+#define UMCCH6_2_PerfMonCtl7__SubChanMask__SHIFT 0x1d
+#define UMCCH6_2_PerfMonCtl7__Enable__SHIFT 0x1f
+#define UMCCH6_2_PerfMonCtl7__EventSelect_MASK 0x000000FFL
+#define UMCCH6_2_PerfMonCtl7__RdWrMask_MASK 0x00000300L
+#define UMCCH6_2_PerfMonCtl7__PriorityMask_MASK 0x00003C00L
+#define UMCCH6_2_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH6_2_PerfMonCtl7__BankSel_MASK 0x00FF0000L
+#define UMCCH6_2_PerfMonCtl7__VCSel_MASK 0x1F000000L
+#define UMCCH6_2_PerfMonCtl7__SubChanMask_MASK 0x60000000L
+#define UMCCH6_2_PerfMonCtl7__Enable_MASK 0x80000000L
+//UMCCH6_2_PerfMonCtr7_Lo
+#define UMCCH6_2_PerfMonCtr7_Lo__Data__SHIFT 0x0
+#define UMCCH6_2_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_2_PerfMonCtr7_Hi
+#define UMCCH6_2_PerfMonCtr7_Hi__Data__SHIFT 0x0
+#define UMCCH6_2_PerfMonCtr7_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_2_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH6_2_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH6_2_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_2_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L
+#define UMCCH6_2_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH6_2_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH6_2_PerfMonCtl8
+#define UMCCH6_2_PerfMonCtl8__EventSelect__SHIFT 0x0
+#define UMCCH6_2_PerfMonCtl8__RdWrMask__SHIFT 0x8
+#define UMCCH6_2_PerfMonCtl8__PriorityMask__SHIFT 0xa
+#define UMCCH6_2_PerfMonCtl8__ReqSizeMask__SHIFT 0xe
+#define UMCCH6_2_PerfMonCtl8__BankSel__SHIFT 0x10
+#define UMCCH6_2_PerfMonCtl8__VCSel__SHIFT 0x18
+#define UMCCH6_2_PerfMonCtl8__SubChanMask__SHIFT 0x1d
+#define UMCCH6_2_PerfMonCtl8__Enable__SHIFT 0x1f
+#define UMCCH6_2_PerfMonCtl8__EventSelect_MASK 0x000000FFL
+#define UMCCH6_2_PerfMonCtl8__RdWrMask_MASK 0x00000300L
+#define UMCCH6_2_PerfMonCtl8__PriorityMask_MASK 0x00003C00L
+#define UMCCH6_2_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH6_2_PerfMonCtl8__BankSel_MASK 0x00FF0000L
+#define UMCCH6_2_PerfMonCtl8__VCSel_MASK 0x1F000000L
+#define UMCCH6_2_PerfMonCtl8__SubChanMask_MASK 0x60000000L
+#define UMCCH6_2_PerfMonCtl8__Enable_MASK 0x80000000L
+//UMCCH6_2_PerfMonCtr8_Lo
+#define UMCCH6_2_PerfMonCtr8_Lo__Data__SHIFT 0x0
+#define UMCCH6_2_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_2_PerfMonCtr8_Hi
+#define UMCCH6_2_PerfMonCtr8_Hi__Data__SHIFT 0x0
+#define UMCCH6_2_PerfMonCtr8_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_2_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH6_2_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH6_2_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_2_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L
+#define UMCCH6_2_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH6_2_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L
+
+
+// addressBlock: umc_w_phy_umc2_umcch7_umcchdec
+//UMCCH7_2_BaseAddrCS0
+#define UMCCH7_2_BaseAddrCS0__CSEnable__SHIFT 0x0
+#define UMCCH7_2_BaseAddrCS0__BaseAddr__SHIFT 0x1
+#define UMCCH7_2_BaseAddrCS0__CSEnable_MASK 0x00000001L
+#define UMCCH7_2_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL
+//UMCCH7_2_AddrMaskCS01
+#define UMCCH7_2_AddrMaskCS01__AddrMask__SHIFT 0x1
+#define UMCCH7_2_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL
+//UMCCH7_2_AddrSelCS01
+#define UMCCH7_2_AddrSelCS01__BankBit0__SHIFT 0x0
+#define UMCCH7_2_AddrSelCS01__BankBit1__SHIFT 0x4
+#define UMCCH7_2_AddrSelCS01__BankBit2__SHIFT 0x8
+#define UMCCH7_2_AddrSelCS01__BankBit3__SHIFT 0xc
+#define UMCCH7_2_AddrSelCS01__BankBit4__SHIFT 0x10
+#define UMCCH7_2_AddrSelCS01__RowLo__SHIFT 0x18
+#define UMCCH7_2_AddrSelCS01__RowHi__SHIFT 0x1c
+#define UMCCH7_2_AddrSelCS01__BankBit0_MASK 0x0000000FL
+#define UMCCH7_2_AddrSelCS01__BankBit1_MASK 0x000000F0L
+#define UMCCH7_2_AddrSelCS01__BankBit2_MASK 0x00000F00L
+#define UMCCH7_2_AddrSelCS01__BankBit3_MASK 0x0000F000L
+#define UMCCH7_2_AddrSelCS01__BankBit4_MASK 0x001F0000L
+#define UMCCH7_2_AddrSelCS01__RowLo_MASK 0x0F000000L
+#define UMCCH7_2_AddrSelCS01__RowHi_MASK 0xF0000000L
+//UMCCH7_2_AddrHashBank0
+#define UMCCH7_2_AddrHashBank0__XorEnable__SHIFT 0x0
+#define UMCCH7_2_AddrHashBank0__ColXor__SHIFT 0x1
+#define UMCCH7_2_AddrHashBank0__RowXor__SHIFT 0xe
+#define UMCCH7_2_AddrHashBank0__XorEnable_MASK 0x00000001L
+#define UMCCH7_2_AddrHashBank0__ColXor_MASK 0x00003FFEL
+#define UMCCH7_2_AddrHashBank0__RowXor_MASK 0xFFFFC000L
+//UMCCH7_2_AddrHashBank1
+#define UMCCH7_2_AddrHashBank1__XorEnable__SHIFT 0x0
+#define UMCCH7_2_AddrHashBank1__ColXor__SHIFT 0x1
+#define UMCCH7_2_AddrHashBank1__RowXor__SHIFT 0xe
+#define UMCCH7_2_AddrHashBank1__XorEnable_MASK 0x00000001L
+#define UMCCH7_2_AddrHashBank1__ColXor_MASK 0x00003FFEL
+#define UMCCH7_2_AddrHashBank1__RowXor_MASK 0xFFFFC000L
+//UMCCH7_2_AddrHashBank2
+#define UMCCH7_2_AddrHashBank2__XorEnable__SHIFT 0x0
+#define UMCCH7_2_AddrHashBank2__ColXor__SHIFT 0x1
+#define UMCCH7_2_AddrHashBank2__RowXor__SHIFT 0xe
+#define UMCCH7_2_AddrHashBank2__XorEnable_MASK 0x00000001L
+#define UMCCH7_2_AddrHashBank2__ColXor_MASK 0x00003FFEL
+#define UMCCH7_2_AddrHashBank2__RowXor_MASK 0xFFFFC000L
+//UMCCH7_2_AddrHashBank3
+#define UMCCH7_2_AddrHashBank3__XorEnable__SHIFT 0x0
+#define UMCCH7_2_AddrHashBank3__ColXor__SHIFT 0x1
+#define UMCCH7_2_AddrHashBank3__RowXor__SHIFT 0xe
+#define UMCCH7_2_AddrHashBank3__XorEnable_MASK 0x00000001L
+#define UMCCH7_2_AddrHashBank3__ColXor_MASK 0x00003FFEL
+#define UMCCH7_2_AddrHashBank3__RowXor_MASK 0xFFFFC000L
+//UMCCH7_2_AddrHashBank4
+#define UMCCH7_2_AddrHashBank4__XorEnable__SHIFT 0x0
+#define UMCCH7_2_AddrHashBank4__ColXor__SHIFT 0x1
+#define UMCCH7_2_AddrHashBank4__RowXor__SHIFT 0xe
+#define UMCCH7_2_AddrHashBank4__XorEnable_MASK 0x00000001L
+#define UMCCH7_2_AddrHashBank4__ColXor_MASK 0x00003FFEL
+#define UMCCH7_2_AddrHashBank4__RowXor_MASK 0xFFFFC000L
+//UMCCH7_2_AddrHashBank5
+#define UMCCH7_2_AddrHashBank5__XorEnable__SHIFT 0x0
+#define UMCCH7_2_AddrHashBank5__ColXor__SHIFT 0x1
+#define UMCCH7_2_AddrHashBank5__RowXor__SHIFT 0xe
+#define UMCCH7_2_AddrHashBank5__XorEnable_MASK 0x00000001L
+#define UMCCH7_2_AddrHashBank5__ColXor_MASK 0x00003FFEL
+#define UMCCH7_2_AddrHashBank5__RowXor_MASK 0xFFFFC000L
+//UMCCH7_2_EccErrCntSel
+#define UMCCH7_2_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0
+#define UMCCH7_2_EccErrCntSel__EccErrInt__SHIFT 0xc
+#define UMCCH7_2_EccErrCntSel__EccErrCntEn__SHIFT 0xf
+#define UMCCH7_2_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL
+#define UMCCH7_2_EccErrCntSel__EccErrInt_MASK 0x00003000L
+#define UMCCH7_2_EccErrCntSel__EccErrCntEn_MASK 0x00008000L
+//UMCCH7_2_EccErrCnt
+#define UMCCH7_2_EccErrCnt__EccErrCnt__SHIFT 0x0
+#define UMCCH7_2_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL
+//UMCCH7_2_PerfMonCtlClk
+#define UMCCH7_2_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0
+#define UMCCH7_2_PerfMonCtlClk__ClkGate__SHIFT 0x16
+#define UMCCH7_2_PerfMonCtlClk__GlblReset__SHIFT 0x18
+#define UMCCH7_2_PerfMonCtlClk__GlblMonEn__SHIFT 0x19
+#define UMCCH7_2_PerfMonCtlClk__NumCounters__SHIFT 0x1a
+#define UMCCH7_2_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f
+#define UMCCH7_2_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL
+#define UMCCH7_2_PerfMonCtlClk__ClkGate_MASK 0x00400000L
+#define UMCCH7_2_PerfMonCtlClk__GlblReset_MASK 0x01000000L
+#define UMCCH7_2_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L
+#define UMCCH7_2_PerfMonCtlClk__NumCounters_MASK 0x3C000000L
+#define UMCCH7_2_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L
+//UMCCH7_2_PerfMonCtrClk_Lo
+#define UMCCH7_2_PerfMonCtrClk_Lo__Data__SHIFT 0x0
+#define UMCCH7_2_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_2_PerfMonCtrClk_Hi
+#define UMCCH7_2_PerfMonCtrClk_Hi__Data__SHIFT 0x0
+#define UMCCH7_2_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_2_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_2_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L
+//UMCCH7_2_PerfMonCtl1
+#define UMCCH7_2_PerfMonCtl1__EventSelect__SHIFT 0x0
+#define UMCCH7_2_PerfMonCtl1__RdWrMask__SHIFT 0x8
+#define UMCCH7_2_PerfMonCtl1__PriorityMask__SHIFT 0xa
+#define UMCCH7_2_PerfMonCtl1__ReqSizeMask__SHIFT 0xe
+#define UMCCH7_2_PerfMonCtl1__BankSel__SHIFT 0x10
+#define UMCCH7_2_PerfMonCtl1__VCSel__SHIFT 0x18
+#define UMCCH7_2_PerfMonCtl1__SubChanMask__SHIFT 0x1d
+#define UMCCH7_2_PerfMonCtl1__Enable__SHIFT 0x1f
+#define UMCCH7_2_PerfMonCtl1__EventSelect_MASK 0x000000FFL
+#define UMCCH7_2_PerfMonCtl1__RdWrMask_MASK 0x00000300L
+#define UMCCH7_2_PerfMonCtl1__PriorityMask_MASK 0x00003C00L
+#define UMCCH7_2_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH7_2_PerfMonCtl1__BankSel_MASK 0x00FF0000L
+#define UMCCH7_2_PerfMonCtl1__VCSel_MASK 0x1F000000L
+#define UMCCH7_2_PerfMonCtl1__SubChanMask_MASK 0x60000000L
+#define UMCCH7_2_PerfMonCtl1__Enable_MASK 0x80000000L
+//UMCCH7_2_PerfMonCtr1_Lo
+#define UMCCH7_2_PerfMonCtr1_Lo__Data__SHIFT 0x0
+#define UMCCH7_2_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_2_PerfMonCtr1_Hi
+#define UMCCH7_2_PerfMonCtr1_Hi__Data__SHIFT 0x0
+#define UMCCH7_2_PerfMonCtr1_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_2_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH7_2_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH7_2_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_2_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L
+#define UMCCH7_2_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH7_2_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH7_2_PerfMonCtl2
+#define UMCCH7_2_PerfMonCtl2__EventSelect__SHIFT 0x0
+#define UMCCH7_2_PerfMonCtl2__RdWrMask__SHIFT 0x8
+#define UMCCH7_2_PerfMonCtl2__PriorityMask__SHIFT 0xa
+#define UMCCH7_2_PerfMonCtl2__ReqSizeMask__SHIFT 0xe
+#define UMCCH7_2_PerfMonCtl2__BankSel__SHIFT 0x10
+#define UMCCH7_2_PerfMonCtl2__VCSel__SHIFT 0x18
+#define UMCCH7_2_PerfMonCtl2__SubChanMask__SHIFT 0x1d
+#define UMCCH7_2_PerfMonCtl2__Enable__SHIFT 0x1f
+#define UMCCH7_2_PerfMonCtl2__EventSelect_MASK 0x000000FFL
+#define UMCCH7_2_PerfMonCtl2__RdWrMask_MASK 0x00000300L
+#define UMCCH7_2_PerfMonCtl2__PriorityMask_MASK 0x00003C00L
+#define UMCCH7_2_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH7_2_PerfMonCtl2__BankSel_MASK 0x00FF0000L
+#define UMCCH7_2_PerfMonCtl2__VCSel_MASK 0x1F000000L
+#define UMCCH7_2_PerfMonCtl2__SubChanMask_MASK 0x60000000L
+#define UMCCH7_2_PerfMonCtl2__Enable_MASK 0x80000000L
+//UMCCH7_2_PerfMonCtr2_Lo
+#define UMCCH7_2_PerfMonCtr2_Lo__Data__SHIFT 0x0
+#define UMCCH7_2_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_2_PerfMonCtr2_Hi
+#define UMCCH7_2_PerfMonCtr2_Hi__Data__SHIFT 0x0
+#define UMCCH7_2_PerfMonCtr2_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_2_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH7_2_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH7_2_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_2_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L
+#define UMCCH7_2_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH7_2_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH7_2_PerfMonCtl3
+#define UMCCH7_2_PerfMonCtl3__EventSelect__SHIFT 0x0
+#define UMCCH7_2_PerfMonCtl3__RdWrMask__SHIFT 0x8
+#define UMCCH7_2_PerfMonCtl3__PriorityMask__SHIFT 0xa
+#define UMCCH7_2_PerfMonCtl3__ReqSizeMask__SHIFT 0xe
+#define UMCCH7_2_PerfMonCtl3__BankSel__SHIFT 0x10
+#define UMCCH7_2_PerfMonCtl3__VCSel__SHIFT 0x18
+#define UMCCH7_2_PerfMonCtl3__SubChanMask__SHIFT 0x1d
+#define UMCCH7_2_PerfMonCtl3__Enable__SHIFT 0x1f
+#define UMCCH7_2_PerfMonCtl3__EventSelect_MASK 0x000000FFL
+#define UMCCH7_2_PerfMonCtl3__RdWrMask_MASK 0x00000300L
+#define UMCCH7_2_PerfMonCtl3__PriorityMask_MASK 0x00003C00L
+#define UMCCH7_2_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH7_2_PerfMonCtl3__BankSel_MASK 0x00FF0000L
+#define UMCCH7_2_PerfMonCtl3__VCSel_MASK 0x1F000000L
+#define UMCCH7_2_PerfMonCtl3__SubChanMask_MASK 0x60000000L
+#define UMCCH7_2_PerfMonCtl3__Enable_MASK 0x80000000L
+//UMCCH7_2_PerfMonCtr3_Lo
+#define UMCCH7_2_PerfMonCtr3_Lo__Data__SHIFT 0x0
+#define UMCCH7_2_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_2_PerfMonCtr3_Hi
+#define UMCCH7_2_PerfMonCtr3_Hi__Data__SHIFT 0x0
+#define UMCCH7_2_PerfMonCtr3_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_2_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH7_2_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH7_2_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_2_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L
+#define UMCCH7_2_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH7_2_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH7_2_PerfMonCtl4
+#define UMCCH7_2_PerfMonCtl4__EventSelect__SHIFT 0x0
+#define UMCCH7_2_PerfMonCtl4__RdWrMask__SHIFT 0x8
+#define UMCCH7_2_PerfMonCtl4__PriorityMask__SHIFT 0xa
+#define UMCCH7_2_PerfMonCtl4__ReqSizeMask__SHIFT 0xe
+#define UMCCH7_2_PerfMonCtl4__BankSel__SHIFT 0x10
+#define UMCCH7_2_PerfMonCtl4__VCSel__SHIFT 0x18
+#define UMCCH7_2_PerfMonCtl4__SubChanMask__SHIFT 0x1d
+#define UMCCH7_2_PerfMonCtl4__Enable__SHIFT 0x1f
+#define UMCCH7_2_PerfMonCtl4__EventSelect_MASK 0x000000FFL
+#define UMCCH7_2_PerfMonCtl4__RdWrMask_MASK 0x00000300L
+#define UMCCH7_2_PerfMonCtl4__PriorityMask_MASK 0x00003C00L
+#define UMCCH7_2_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH7_2_PerfMonCtl4__BankSel_MASK 0x00FF0000L
+#define UMCCH7_2_PerfMonCtl4__VCSel_MASK 0x1F000000L
+#define UMCCH7_2_PerfMonCtl4__SubChanMask_MASK 0x60000000L
+#define UMCCH7_2_PerfMonCtl4__Enable_MASK 0x80000000L
+//UMCCH7_2_PerfMonCtr4_Lo
+#define UMCCH7_2_PerfMonCtr4_Lo__Data__SHIFT 0x0
+#define UMCCH7_2_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_2_PerfMonCtr4_Hi
+#define UMCCH7_2_PerfMonCtr4_Hi__Data__SHIFT 0x0
+#define UMCCH7_2_PerfMonCtr4_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_2_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH7_2_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH7_2_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_2_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L
+#define UMCCH7_2_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH7_2_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH7_2_PerfMonCtl5
+#define UMCCH7_2_PerfMonCtl5__EventSelect__SHIFT 0x0
+#define UMCCH7_2_PerfMonCtl5__RdWrMask__SHIFT 0x8
+#define UMCCH7_2_PerfMonCtl5__PriorityMask__SHIFT 0xa
+#define UMCCH7_2_PerfMonCtl5__ReqSizeMask__SHIFT 0xe
+#define UMCCH7_2_PerfMonCtl5__BankSel__SHIFT 0x10
+#define UMCCH7_2_PerfMonCtl5__VCSel__SHIFT 0x18
+#define UMCCH7_2_PerfMonCtl5__SubChanMask__SHIFT 0x1d
+#define UMCCH7_2_PerfMonCtl5__Enable__SHIFT 0x1f
+#define UMCCH7_2_PerfMonCtl5__EventSelect_MASK 0x000000FFL
+#define UMCCH7_2_PerfMonCtl5__RdWrMask_MASK 0x00000300L
+#define UMCCH7_2_PerfMonCtl5__PriorityMask_MASK 0x00003C00L
+#define UMCCH7_2_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH7_2_PerfMonCtl5__BankSel_MASK 0x00FF0000L
+#define UMCCH7_2_PerfMonCtl5__VCSel_MASK 0x1F000000L
+#define UMCCH7_2_PerfMonCtl5__SubChanMask_MASK 0x60000000L
+#define UMCCH7_2_PerfMonCtl5__Enable_MASK 0x80000000L
+//UMCCH7_2_PerfMonCtr5_Lo
+#define UMCCH7_2_PerfMonCtr5_Lo__Data__SHIFT 0x0
+#define UMCCH7_2_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_2_PerfMonCtr5_Hi
+#define UMCCH7_2_PerfMonCtr5_Hi__Data__SHIFT 0x0
+#define UMCCH7_2_PerfMonCtr5_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_2_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH7_2_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH7_2_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_2_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L
+#define UMCCH7_2_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH7_2_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH7_2_PerfMonCtl6
+#define UMCCH7_2_PerfMonCtl6__EventSelect__SHIFT 0x0
+#define UMCCH7_2_PerfMonCtl6__RdWrMask__SHIFT 0x8
+#define UMCCH7_2_PerfMonCtl6__PriorityMask__SHIFT 0xa
+#define UMCCH7_2_PerfMonCtl6__ReqSizeMask__SHIFT 0xe
+#define UMCCH7_2_PerfMonCtl6__BankSel__SHIFT 0x10
+#define UMCCH7_2_PerfMonCtl6__VCSel__SHIFT 0x18
+#define UMCCH7_2_PerfMonCtl6__SubChanMask__SHIFT 0x1d
+#define UMCCH7_2_PerfMonCtl6__Enable__SHIFT 0x1f
+#define UMCCH7_2_PerfMonCtl6__EventSelect_MASK 0x000000FFL
+#define UMCCH7_2_PerfMonCtl6__RdWrMask_MASK 0x00000300L
+#define UMCCH7_2_PerfMonCtl6__PriorityMask_MASK 0x00003C00L
+#define UMCCH7_2_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH7_2_PerfMonCtl6__BankSel_MASK 0x00FF0000L
+#define UMCCH7_2_PerfMonCtl6__VCSel_MASK 0x1F000000L
+#define UMCCH7_2_PerfMonCtl6__SubChanMask_MASK 0x60000000L
+#define UMCCH7_2_PerfMonCtl6__Enable_MASK 0x80000000L
+//UMCCH7_2_PerfMonCtr6_Lo
+#define UMCCH7_2_PerfMonCtr6_Lo__Data__SHIFT 0x0
+#define UMCCH7_2_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_2_PerfMonCtr6_Hi
+#define UMCCH7_2_PerfMonCtr6_Hi__Data__SHIFT 0x0
+#define UMCCH7_2_PerfMonCtr6_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_2_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH7_2_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH7_2_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_2_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L
+#define UMCCH7_2_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH7_2_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH7_2_PerfMonCtl7
+#define UMCCH7_2_PerfMonCtl7__EventSelect__SHIFT 0x0
+#define UMCCH7_2_PerfMonCtl7__RdWrMask__SHIFT 0x8
+#define UMCCH7_2_PerfMonCtl7__PriorityMask__SHIFT 0xa
+#define UMCCH7_2_PerfMonCtl7__ReqSizeMask__SHIFT 0xe
+#define UMCCH7_2_PerfMonCtl7__BankSel__SHIFT 0x10
+#define UMCCH7_2_PerfMonCtl7__VCSel__SHIFT 0x18
+#define UMCCH7_2_PerfMonCtl7__SubChanMask__SHIFT 0x1d
+#define UMCCH7_2_PerfMonCtl7__Enable__SHIFT 0x1f
+#define UMCCH7_2_PerfMonCtl7__EventSelect_MASK 0x000000FFL
+#define UMCCH7_2_PerfMonCtl7__RdWrMask_MASK 0x00000300L
+#define UMCCH7_2_PerfMonCtl7__PriorityMask_MASK 0x00003C00L
+#define UMCCH7_2_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH7_2_PerfMonCtl7__BankSel_MASK 0x00FF0000L
+#define UMCCH7_2_PerfMonCtl7__VCSel_MASK 0x1F000000L
+#define UMCCH7_2_PerfMonCtl7__SubChanMask_MASK 0x60000000L
+#define UMCCH7_2_PerfMonCtl7__Enable_MASK 0x80000000L
+//UMCCH7_2_PerfMonCtr7_Lo
+#define UMCCH7_2_PerfMonCtr7_Lo__Data__SHIFT 0x0
+#define UMCCH7_2_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_2_PerfMonCtr7_Hi
+#define UMCCH7_2_PerfMonCtr7_Hi__Data__SHIFT 0x0
+#define UMCCH7_2_PerfMonCtr7_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_2_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH7_2_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH7_2_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_2_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L
+#define UMCCH7_2_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH7_2_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH7_2_PerfMonCtl8
+#define UMCCH7_2_PerfMonCtl8__EventSelect__SHIFT 0x0
+#define UMCCH7_2_PerfMonCtl8__RdWrMask__SHIFT 0x8
+#define UMCCH7_2_PerfMonCtl8__PriorityMask__SHIFT 0xa
+#define UMCCH7_2_PerfMonCtl8__ReqSizeMask__SHIFT 0xe
+#define UMCCH7_2_PerfMonCtl8__BankSel__SHIFT 0x10
+#define UMCCH7_2_PerfMonCtl8__VCSel__SHIFT 0x18
+#define UMCCH7_2_PerfMonCtl8__SubChanMask__SHIFT 0x1d
+#define UMCCH7_2_PerfMonCtl8__Enable__SHIFT 0x1f
+#define UMCCH7_2_PerfMonCtl8__EventSelect_MASK 0x000000FFL
+#define UMCCH7_2_PerfMonCtl8__RdWrMask_MASK 0x00000300L
+#define UMCCH7_2_PerfMonCtl8__PriorityMask_MASK 0x00003C00L
+#define UMCCH7_2_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH7_2_PerfMonCtl8__BankSel_MASK 0x00FF0000L
+#define UMCCH7_2_PerfMonCtl8__VCSel_MASK 0x1F000000L
+#define UMCCH7_2_PerfMonCtl8__SubChanMask_MASK 0x60000000L
+#define UMCCH7_2_PerfMonCtl8__Enable_MASK 0x80000000L
+//UMCCH7_2_PerfMonCtr8_Lo
+#define UMCCH7_2_PerfMonCtr8_Lo__Data__SHIFT 0x0
+#define UMCCH7_2_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_2_PerfMonCtr8_Hi
+#define UMCCH7_2_PerfMonCtr8_Hi__Data__SHIFT 0x0
+#define UMCCH7_2_PerfMonCtr8_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_2_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH7_2_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH7_2_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_2_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L
+#define UMCCH7_2_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH7_2_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L
+
+
+// addressBlock: umc_w_phy_umc3_umcch0_umcchdec
+//UMCCH0_3_BaseAddrCS0
+#define UMCCH0_3_BaseAddrCS0__CSEnable__SHIFT 0x0
+#define UMCCH0_3_BaseAddrCS0__BaseAddr__SHIFT 0x1
+#define UMCCH0_3_BaseAddrCS0__CSEnable_MASK 0x00000001L
+#define UMCCH0_3_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL
+//UMCCH0_3_AddrMaskCS01
+#define UMCCH0_3_AddrMaskCS01__AddrMask__SHIFT 0x1
+#define UMCCH0_3_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL
+//UMCCH0_3_AddrSelCS01
+#define UMCCH0_3_AddrSelCS01__BankBit0__SHIFT 0x0
+#define UMCCH0_3_AddrSelCS01__BankBit1__SHIFT 0x4
+#define UMCCH0_3_AddrSelCS01__BankBit2__SHIFT 0x8
+#define UMCCH0_3_AddrSelCS01__BankBit3__SHIFT 0xc
+#define UMCCH0_3_AddrSelCS01__BankBit4__SHIFT 0x10
+#define UMCCH0_3_AddrSelCS01__RowLo__SHIFT 0x18
+#define UMCCH0_3_AddrSelCS01__RowHi__SHIFT 0x1c
+#define UMCCH0_3_AddrSelCS01__BankBit0_MASK 0x0000000FL
+#define UMCCH0_3_AddrSelCS01__BankBit1_MASK 0x000000F0L
+#define UMCCH0_3_AddrSelCS01__BankBit2_MASK 0x00000F00L
+#define UMCCH0_3_AddrSelCS01__BankBit3_MASK 0x0000F000L
+#define UMCCH0_3_AddrSelCS01__BankBit4_MASK 0x001F0000L
+#define UMCCH0_3_AddrSelCS01__RowLo_MASK 0x0F000000L
+#define UMCCH0_3_AddrSelCS01__RowHi_MASK 0xF0000000L
+//UMCCH0_3_AddrHashBank0
+#define UMCCH0_3_AddrHashBank0__XorEnable__SHIFT 0x0
+#define UMCCH0_3_AddrHashBank0__ColXor__SHIFT 0x1
+#define UMCCH0_3_AddrHashBank0__RowXor__SHIFT 0xe
+#define UMCCH0_3_AddrHashBank0__XorEnable_MASK 0x00000001L
+#define UMCCH0_3_AddrHashBank0__ColXor_MASK 0x00003FFEL
+#define UMCCH0_3_AddrHashBank0__RowXor_MASK 0xFFFFC000L
+//UMCCH0_3_AddrHashBank1
+#define UMCCH0_3_AddrHashBank1__XorEnable__SHIFT 0x0
+#define UMCCH0_3_AddrHashBank1__ColXor__SHIFT 0x1
+#define UMCCH0_3_AddrHashBank1__RowXor__SHIFT 0xe
+#define UMCCH0_3_AddrHashBank1__XorEnable_MASK 0x00000001L
+#define UMCCH0_3_AddrHashBank1__ColXor_MASK 0x00003FFEL
+#define UMCCH0_3_AddrHashBank1__RowXor_MASK 0xFFFFC000L
+//UMCCH0_3_AddrHashBank2
+#define UMCCH0_3_AddrHashBank2__XorEnable__SHIFT 0x0
+#define UMCCH0_3_AddrHashBank2__ColXor__SHIFT 0x1
+#define UMCCH0_3_AddrHashBank2__RowXor__SHIFT 0xe
+#define UMCCH0_3_AddrHashBank2__XorEnable_MASK 0x00000001L
+#define UMCCH0_3_AddrHashBank2__ColXor_MASK 0x00003FFEL
+#define UMCCH0_3_AddrHashBank2__RowXor_MASK 0xFFFFC000L
+//UMCCH0_3_AddrHashBank3
+#define UMCCH0_3_AddrHashBank3__XorEnable__SHIFT 0x0
+#define UMCCH0_3_AddrHashBank3__ColXor__SHIFT 0x1
+#define UMCCH0_3_AddrHashBank3__RowXor__SHIFT 0xe
+#define UMCCH0_3_AddrHashBank3__XorEnable_MASK 0x00000001L
+#define UMCCH0_3_AddrHashBank3__ColXor_MASK 0x00003FFEL
+#define UMCCH0_3_AddrHashBank3__RowXor_MASK 0xFFFFC000L
+//UMCCH0_3_AddrHashBank4
+#define UMCCH0_3_AddrHashBank4__XorEnable__SHIFT 0x0
+#define UMCCH0_3_AddrHashBank4__ColXor__SHIFT 0x1
+#define UMCCH0_3_AddrHashBank4__RowXor__SHIFT 0xe
+#define UMCCH0_3_AddrHashBank4__XorEnable_MASK 0x00000001L
+#define UMCCH0_3_AddrHashBank4__ColXor_MASK 0x00003FFEL
+#define UMCCH0_3_AddrHashBank4__RowXor_MASK 0xFFFFC000L
+//UMCCH0_3_AddrHashBank5
+#define UMCCH0_3_AddrHashBank5__XorEnable__SHIFT 0x0
+#define UMCCH0_3_AddrHashBank5__ColXor__SHIFT 0x1
+#define UMCCH0_3_AddrHashBank5__RowXor__SHIFT 0xe
+#define UMCCH0_3_AddrHashBank5__XorEnable_MASK 0x00000001L
+#define UMCCH0_3_AddrHashBank5__ColXor_MASK 0x00003FFEL
+#define UMCCH0_3_AddrHashBank5__RowXor_MASK 0xFFFFC000L
+//UMCCH0_3_EccErrCntSel
+#define UMCCH0_3_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0
+#define UMCCH0_3_EccErrCntSel__EccErrInt__SHIFT 0xc
+#define UMCCH0_3_EccErrCntSel__EccErrCntEn__SHIFT 0xf
+#define UMCCH0_3_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL
+#define UMCCH0_3_EccErrCntSel__EccErrInt_MASK 0x00003000L
+#define UMCCH0_3_EccErrCntSel__EccErrCntEn_MASK 0x00008000L
+//UMCCH0_3_EccErrCnt
+#define UMCCH0_3_EccErrCnt__EccErrCnt__SHIFT 0x0
+#define UMCCH0_3_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL
+//UMCCH0_3_PerfMonCtlClk
+#define UMCCH0_3_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0
+#define UMCCH0_3_PerfMonCtlClk__ClkGate__SHIFT 0x16
+#define UMCCH0_3_PerfMonCtlClk__GlblReset__SHIFT 0x18
+#define UMCCH0_3_PerfMonCtlClk__GlblMonEn__SHIFT 0x19
+#define UMCCH0_3_PerfMonCtlClk__NumCounters__SHIFT 0x1a
+#define UMCCH0_3_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f
+#define UMCCH0_3_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL
+#define UMCCH0_3_PerfMonCtlClk__ClkGate_MASK 0x00400000L
+#define UMCCH0_3_PerfMonCtlClk__GlblReset_MASK 0x01000000L
+#define UMCCH0_3_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L
+#define UMCCH0_3_PerfMonCtlClk__NumCounters_MASK 0x3C000000L
+#define UMCCH0_3_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L
+//UMCCH0_3_PerfMonCtrClk_Lo
+#define UMCCH0_3_PerfMonCtrClk_Lo__Data__SHIFT 0x0
+#define UMCCH0_3_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_3_PerfMonCtrClk_Hi
+#define UMCCH0_3_PerfMonCtrClk_Hi__Data__SHIFT 0x0
+#define UMCCH0_3_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_3_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_3_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L
+//UMCCH0_3_PerfMonCtl1
+#define UMCCH0_3_PerfMonCtl1__EventSelect__SHIFT 0x0
+#define UMCCH0_3_PerfMonCtl1__RdWrMask__SHIFT 0x8
+#define UMCCH0_3_PerfMonCtl1__PriorityMask__SHIFT 0xa
+#define UMCCH0_3_PerfMonCtl1__ReqSizeMask__SHIFT 0xe
+#define UMCCH0_3_PerfMonCtl1__BankSel__SHIFT 0x10
+#define UMCCH0_3_PerfMonCtl1__VCSel__SHIFT 0x18
+#define UMCCH0_3_PerfMonCtl1__SubChanMask__SHIFT 0x1d
+#define UMCCH0_3_PerfMonCtl1__Enable__SHIFT 0x1f
+#define UMCCH0_3_PerfMonCtl1__EventSelect_MASK 0x000000FFL
+#define UMCCH0_3_PerfMonCtl1__RdWrMask_MASK 0x00000300L
+#define UMCCH0_3_PerfMonCtl1__PriorityMask_MASK 0x00003C00L
+#define UMCCH0_3_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH0_3_PerfMonCtl1__BankSel_MASK 0x00FF0000L
+#define UMCCH0_3_PerfMonCtl1__VCSel_MASK 0x1F000000L
+#define UMCCH0_3_PerfMonCtl1__SubChanMask_MASK 0x60000000L
+#define UMCCH0_3_PerfMonCtl1__Enable_MASK 0x80000000L
+//UMCCH0_3_PerfMonCtr1_Lo
+#define UMCCH0_3_PerfMonCtr1_Lo__Data__SHIFT 0x0
+#define UMCCH0_3_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_3_PerfMonCtr1_Hi
+#define UMCCH0_3_PerfMonCtr1_Hi__Data__SHIFT 0x0
+#define UMCCH0_3_PerfMonCtr1_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_3_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH0_3_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH0_3_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_3_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L
+#define UMCCH0_3_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH0_3_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH0_3_PerfMonCtl2
+#define UMCCH0_3_PerfMonCtl2__EventSelect__SHIFT 0x0
+#define UMCCH0_3_PerfMonCtl2__RdWrMask__SHIFT 0x8
+#define UMCCH0_3_PerfMonCtl2__PriorityMask__SHIFT 0xa
+#define UMCCH0_3_PerfMonCtl2__ReqSizeMask__SHIFT 0xe
+#define UMCCH0_3_PerfMonCtl2__BankSel__SHIFT 0x10
+#define UMCCH0_3_PerfMonCtl2__VCSel__SHIFT 0x18
+#define UMCCH0_3_PerfMonCtl2__SubChanMask__SHIFT 0x1d
+#define UMCCH0_3_PerfMonCtl2__Enable__SHIFT 0x1f
+#define UMCCH0_3_PerfMonCtl2__EventSelect_MASK 0x000000FFL
+#define UMCCH0_3_PerfMonCtl2__RdWrMask_MASK 0x00000300L
+#define UMCCH0_3_PerfMonCtl2__PriorityMask_MASK 0x00003C00L
+#define UMCCH0_3_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH0_3_PerfMonCtl2__BankSel_MASK 0x00FF0000L
+#define UMCCH0_3_PerfMonCtl2__VCSel_MASK 0x1F000000L
+#define UMCCH0_3_PerfMonCtl2__SubChanMask_MASK 0x60000000L
+#define UMCCH0_3_PerfMonCtl2__Enable_MASK 0x80000000L
+//UMCCH0_3_PerfMonCtr2_Lo
+#define UMCCH0_3_PerfMonCtr2_Lo__Data__SHIFT 0x0
+#define UMCCH0_3_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_3_PerfMonCtr2_Hi
+#define UMCCH0_3_PerfMonCtr2_Hi__Data__SHIFT 0x0
+#define UMCCH0_3_PerfMonCtr2_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_3_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH0_3_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH0_3_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_3_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L
+#define UMCCH0_3_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH0_3_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH0_3_PerfMonCtl3
+#define UMCCH0_3_PerfMonCtl3__EventSelect__SHIFT 0x0
+#define UMCCH0_3_PerfMonCtl3__RdWrMask__SHIFT 0x8
+#define UMCCH0_3_PerfMonCtl3__PriorityMask__SHIFT 0xa
+#define UMCCH0_3_PerfMonCtl3__ReqSizeMask__SHIFT 0xe
+#define UMCCH0_3_PerfMonCtl3__BankSel__SHIFT 0x10
+#define UMCCH0_3_PerfMonCtl3__VCSel__SHIFT 0x18
+#define UMCCH0_3_PerfMonCtl3__SubChanMask__SHIFT 0x1d
+#define UMCCH0_3_PerfMonCtl3__Enable__SHIFT 0x1f
+#define UMCCH0_3_PerfMonCtl3__EventSelect_MASK 0x000000FFL
+#define UMCCH0_3_PerfMonCtl3__RdWrMask_MASK 0x00000300L
+#define UMCCH0_3_PerfMonCtl3__PriorityMask_MASK 0x00003C00L
+#define UMCCH0_3_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH0_3_PerfMonCtl3__BankSel_MASK 0x00FF0000L
+#define UMCCH0_3_PerfMonCtl3__VCSel_MASK 0x1F000000L
+#define UMCCH0_3_PerfMonCtl3__SubChanMask_MASK 0x60000000L
+#define UMCCH0_3_PerfMonCtl3__Enable_MASK 0x80000000L
+//UMCCH0_3_PerfMonCtr3_Lo
+#define UMCCH0_3_PerfMonCtr3_Lo__Data__SHIFT 0x0
+#define UMCCH0_3_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_3_PerfMonCtr3_Hi
+#define UMCCH0_3_PerfMonCtr3_Hi__Data__SHIFT 0x0
+#define UMCCH0_3_PerfMonCtr3_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_3_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH0_3_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH0_3_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_3_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L
+#define UMCCH0_3_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH0_3_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH0_3_PerfMonCtl4
+#define UMCCH0_3_PerfMonCtl4__EventSelect__SHIFT 0x0
+#define UMCCH0_3_PerfMonCtl4__RdWrMask__SHIFT 0x8
+#define UMCCH0_3_PerfMonCtl4__PriorityMask__SHIFT 0xa
+#define UMCCH0_3_PerfMonCtl4__ReqSizeMask__SHIFT 0xe
+#define UMCCH0_3_PerfMonCtl4__BankSel__SHIFT 0x10
+#define UMCCH0_3_PerfMonCtl4__VCSel__SHIFT 0x18
+#define UMCCH0_3_PerfMonCtl4__SubChanMask__SHIFT 0x1d
+#define UMCCH0_3_PerfMonCtl4__Enable__SHIFT 0x1f
+#define UMCCH0_3_PerfMonCtl4__EventSelect_MASK 0x000000FFL
+#define UMCCH0_3_PerfMonCtl4__RdWrMask_MASK 0x00000300L
+#define UMCCH0_3_PerfMonCtl4__PriorityMask_MASK 0x00003C00L
+#define UMCCH0_3_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH0_3_PerfMonCtl4__BankSel_MASK 0x00FF0000L
+#define UMCCH0_3_PerfMonCtl4__VCSel_MASK 0x1F000000L
+#define UMCCH0_3_PerfMonCtl4__SubChanMask_MASK 0x60000000L
+#define UMCCH0_3_PerfMonCtl4__Enable_MASK 0x80000000L
+//UMCCH0_3_PerfMonCtr4_Lo
+#define UMCCH0_3_PerfMonCtr4_Lo__Data__SHIFT 0x0
+#define UMCCH0_3_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_3_PerfMonCtr4_Hi
+#define UMCCH0_3_PerfMonCtr4_Hi__Data__SHIFT 0x0
+#define UMCCH0_3_PerfMonCtr4_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_3_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH0_3_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH0_3_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_3_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L
+#define UMCCH0_3_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH0_3_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH0_3_PerfMonCtl5
+#define UMCCH0_3_PerfMonCtl5__EventSelect__SHIFT 0x0
+#define UMCCH0_3_PerfMonCtl5__RdWrMask__SHIFT 0x8
+#define UMCCH0_3_PerfMonCtl5__PriorityMask__SHIFT 0xa
+#define UMCCH0_3_PerfMonCtl5__ReqSizeMask__SHIFT 0xe
+#define UMCCH0_3_PerfMonCtl5__BankSel__SHIFT 0x10
+#define UMCCH0_3_PerfMonCtl5__VCSel__SHIFT 0x18
+#define UMCCH0_3_PerfMonCtl5__SubChanMask__SHIFT 0x1d
+#define UMCCH0_3_PerfMonCtl5__Enable__SHIFT 0x1f
+#define UMCCH0_3_PerfMonCtl5__EventSelect_MASK 0x000000FFL
+#define UMCCH0_3_PerfMonCtl5__RdWrMask_MASK 0x00000300L
+#define UMCCH0_3_PerfMonCtl5__PriorityMask_MASK 0x00003C00L
+#define UMCCH0_3_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH0_3_PerfMonCtl5__BankSel_MASK 0x00FF0000L
+#define UMCCH0_3_PerfMonCtl5__VCSel_MASK 0x1F000000L
+#define UMCCH0_3_PerfMonCtl5__SubChanMask_MASK 0x60000000L
+#define UMCCH0_3_PerfMonCtl5__Enable_MASK 0x80000000L
+//UMCCH0_3_PerfMonCtr5_Lo
+#define UMCCH0_3_PerfMonCtr5_Lo__Data__SHIFT 0x0
+#define UMCCH0_3_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_3_PerfMonCtr5_Hi
+#define UMCCH0_3_PerfMonCtr5_Hi__Data__SHIFT 0x0
+#define UMCCH0_3_PerfMonCtr5_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_3_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH0_3_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH0_3_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_3_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L
+#define UMCCH0_3_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH0_3_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH0_3_PerfMonCtl6
+#define UMCCH0_3_PerfMonCtl6__EventSelect__SHIFT 0x0
+#define UMCCH0_3_PerfMonCtl6__RdWrMask__SHIFT 0x8
+#define UMCCH0_3_PerfMonCtl6__PriorityMask__SHIFT 0xa
+#define UMCCH0_3_PerfMonCtl6__ReqSizeMask__SHIFT 0xe
+#define UMCCH0_3_PerfMonCtl6__BankSel__SHIFT 0x10
+#define UMCCH0_3_PerfMonCtl6__VCSel__SHIFT 0x18
+#define UMCCH0_3_PerfMonCtl6__SubChanMask__SHIFT 0x1d
+#define UMCCH0_3_PerfMonCtl6__Enable__SHIFT 0x1f
+#define UMCCH0_3_PerfMonCtl6__EventSelect_MASK 0x000000FFL
+#define UMCCH0_3_PerfMonCtl6__RdWrMask_MASK 0x00000300L
+#define UMCCH0_3_PerfMonCtl6__PriorityMask_MASK 0x00003C00L
+#define UMCCH0_3_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH0_3_PerfMonCtl6__BankSel_MASK 0x00FF0000L
+#define UMCCH0_3_PerfMonCtl6__VCSel_MASK 0x1F000000L
+#define UMCCH0_3_PerfMonCtl6__SubChanMask_MASK 0x60000000L
+#define UMCCH0_3_PerfMonCtl6__Enable_MASK 0x80000000L
+//UMCCH0_3_PerfMonCtr6_Lo
+#define UMCCH0_3_PerfMonCtr6_Lo__Data__SHIFT 0x0
+#define UMCCH0_3_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_3_PerfMonCtr6_Hi
+#define UMCCH0_3_PerfMonCtr6_Hi__Data__SHIFT 0x0
+#define UMCCH0_3_PerfMonCtr6_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_3_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH0_3_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH0_3_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_3_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L
+#define UMCCH0_3_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH0_3_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH0_3_PerfMonCtl7
+#define UMCCH0_3_PerfMonCtl7__EventSelect__SHIFT 0x0
+#define UMCCH0_3_PerfMonCtl7__RdWrMask__SHIFT 0x8
+#define UMCCH0_3_PerfMonCtl7__PriorityMask__SHIFT 0xa
+#define UMCCH0_3_PerfMonCtl7__ReqSizeMask__SHIFT 0xe
+#define UMCCH0_3_PerfMonCtl7__BankSel__SHIFT 0x10
+#define UMCCH0_3_PerfMonCtl7__VCSel__SHIFT 0x18
+#define UMCCH0_3_PerfMonCtl7__SubChanMask__SHIFT 0x1d
+#define UMCCH0_3_PerfMonCtl7__Enable__SHIFT 0x1f
+#define UMCCH0_3_PerfMonCtl7__EventSelect_MASK 0x000000FFL
+#define UMCCH0_3_PerfMonCtl7__RdWrMask_MASK 0x00000300L
+#define UMCCH0_3_PerfMonCtl7__PriorityMask_MASK 0x00003C00L
+#define UMCCH0_3_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH0_3_PerfMonCtl7__BankSel_MASK 0x00FF0000L
+#define UMCCH0_3_PerfMonCtl7__VCSel_MASK 0x1F000000L
+#define UMCCH0_3_PerfMonCtl7__SubChanMask_MASK 0x60000000L
+#define UMCCH0_3_PerfMonCtl7__Enable_MASK 0x80000000L
+//UMCCH0_3_PerfMonCtr7_Lo
+#define UMCCH0_3_PerfMonCtr7_Lo__Data__SHIFT 0x0
+#define UMCCH0_3_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_3_PerfMonCtr7_Hi
+#define UMCCH0_3_PerfMonCtr7_Hi__Data__SHIFT 0x0
+#define UMCCH0_3_PerfMonCtr7_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_3_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH0_3_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH0_3_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_3_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L
+#define UMCCH0_3_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH0_3_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH0_3_PerfMonCtl8
+#define UMCCH0_3_PerfMonCtl8__EventSelect__SHIFT 0x0
+#define UMCCH0_3_PerfMonCtl8__RdWrMask__SHIFT 0x8
+#define UMCCH0_3_PerfMonCtl8__PriorityMask__SHIFT 0xa
+#define UMCCH0_3_PerfMonCtl8__ReqSizeMask__SHIFT 0xe
+#define UMCCH0_3_PerfMonCtl8__BankSel__SHIFT 0x10
+#define UMCCH0_3_PerfMonCtl8__VCSel__SHIFT 0x18
+#define UMCCH0_3_PerfMonCtl8__SubChanMask__SHIFT 0x1d
+#define UMCCH0_3_PerfMonCtl8__Enable__SHIFT 0x1f
+#define UMCCH0_3_PerfMonCtl8__EventSelect_MASK 0x000000FFL
+#define UMCCH0_3_PerfMonCtl8__RdWrMask_MASK 0x00000300L
+#define UMCCH0_3_PerfMonCtl8__PriorityMask_MASK 0x00003C00L
+#define UMCCH0_3_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH0_3_PerfMonCtl8__BankSel_MASK 0x00FF0000L
+#define UMCCH0_3_PerfMonCtl8__VCSel_MASK 0x1F000000L
+#define UMCCH0_3_PerfMonCtl8__SubChanMask_MASK 0x60000000L
+#define UMCCH0_3_PerfMonCtl8__Enable_MASK 0x80000000L
+//UMCCH0_3_PerfMonCtr8_Lo
+#define UMCCH0_3_PerfMonCtr8_Lo__Data__SHIFT 0x0
+#define UMCCH0_3_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH0_3_PerfMonCtr8_Hi
+#define UMCCH0_3_PerfMonCtr8_Hi__Data__SHIFT 0x0
+#define UMCCH0_3_PerfMonCtr8_Hi__Overflow__SHIFT 0x10
+#define UMCCH0_3_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH0_3_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH0_3_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH0_3_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L
+#define UMCCH0_3_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH0_3_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L
+
+
+// addressBlock: umc_w_phy_umc3_umcch1_umcchdec
+//UMCCH1_3_BaseAddrCS0
+#define UMCCH1_3_BaseAddrCS0__CSEnable__SHIFT 0x0
+#define UMCCH1_3_BaseAddrCS0__BaseAddr__SHIFT 0x1
+#define UMCCH1_3_BaseAddrCS0__CSEnable_MASK 0x00000001L
+#define UMCCH1_3_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL
+//UMCCH1_3_AddrMaskCS01
+#define UMCCH1_3_AddrMaskCS01__AddrMask__SHIFT 0x1
+#define UMCCH1_3_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL
+//UMCCH1_3_AddrSelCS01
+#define UMCCH1_3_AddrSelCS01__BankBit0__SHIFT 0x0
+#define UMCCH1_3_AddrSelCS01__BankBit1__SHIFT 0x4
+#define UMCCH1_3_AddrSelCS01__BankBit2__SHIFT 0x8
+#define UMCCH1_3_AddrSelCS01__BankBit3__SHIFT 0xc
+#define UMCCH1_3_AddrSelCS01__BankBit4__SHIFT 0x10
+#define UMCCH1_3_AddrSelCS01__RowLo__SHIFT 0x18
+#define UMCCH1_3_AddrSelCS01__RowHi__SHIFT 0x1c
+#define UMCCH1_3_AddrSelCS01__BankBit0_MASK 0x0000000FL
+#define UMCCH1_3_AddrSelCS01__BankBit1_MASK 0x000000F0L
+#define UMCCH1_3_AddrSelCS01__BankBit2_MASK 0x00000F00L
+#define UMCCH1_3_AddrSelCS01__BankBit3_MASK 0x0000F000L
+#define UMCCH1_3_AddrSelCS01__BankBit4_MASK 0x001F0000L
+#define UMCCH1_3_AddrSelCS01__RowLo_MASK 0x0F000000L
+#define UMCCH1_3_AddrSelCS01__RowHi_MASK 0xF0000000L
+//UMCCH1_3_AddrHashBank0
+#define UMCCH1_3_AddrHashBank0__XorEnable__SHIFT 0x0
+#define UMCCH1_3_AddrHashBank0__ColXor__SHIFT 0x1
+#define UMCCH1_3_AddrHashBank0__RowXor__SHIFT 0xe
+#define UMCCH1_3_AddrHashBank0__XorEnable_MASK 0x00000001L
+#define UMCCH1_3_AddrHashBank0__ColXor_MASK 0x00003FFEL
+#define UMCCH1_3_AddrHashBank0__RowXor_MASK 0xFFFFC000L
+//UMCCH1_3_AddrHashBank1
+#define UMCCH1_3_AddrHashBank1__XorEnable__SHIFT 0x0
+#define UMCCH1_3_AddrHashBank1__ColXor__SHIFT 0x1
+#define UMCCH1_3_AddrHashBank1__RowXor__SHIFT 0xe
+#define UMCCH1_3_AddrHashBank1__XorEnable_MASK 0x00000001L
+#define UMCCH1_3_AddrHashBank1__ColXor_MASK 0x00003FFEL
+#define UMCCH1_3_AddrHashBank1__RowXor_MASK 0xFFFFC000L
+//UMCCH1_3_AddrHashBank2
+#define UMCCH1_3_AddrHashBank2__XorEnable__SHIFT 0x0
+#define UMCCH1_3_AddrHashBank2__ColXor__SHIFT 0x1
+#define UMCCH1_3_AddrHashBank2__RowXor__SHIFT 0xe
+#define UMCCH1_3_AddrHashBank2__XorEnable_MASK 0x00000001L
+#define UMCCH1_3_AddrHashBank2__ColXor_MASK 0x00003FFEL
+#define UMCCH1_3_AddrHashBank2__RowXor_MASK 0xFFFFC000L
+//UMCCH1_3_AddrHashBank3
+#define UMCCH1_3_AddrHashBank3__XorEnable__SHIFT 0x0
+#define UMCCH1_3_AddrHashBank3__ColXor__SHIFT 0x1
+#define UMCCH1_3_AddrHashBank3__RowXor__SHIFT 0xe
+#define UMCCH1_3_AddrHashBank3__XorEnable_MASK 0x00000001L
+#define UMCCH1_3_AddrHashBank3__ColXor_MASK 0x00003FFEL
+#define UMCCH1_3_AddrHashBank3__RowXor_MASK 0xFFFFC000L
+//UMCCH1_3_AddrHashBank4
+#define UMCCH1_3_AddrHashBank4__XorEnable__SHIFT 0x0
+#define UMCCH1_3_AddrHashBank4__ColXor__SHIFT 0x1
+#define UMCCH1_3_AddrHashBank4__RowXor__SHIFT 0xe
+#define UMCCH1_3_AddrHashBank4__XorEnable_MASK 0x00000001L
+#define UMCCH1_3_AddrHashBank4__ColXor_MASK 0x00003FFEL
+#define UMCCH1_3_AddrHashBank4__RowXor_MASK 0xFFFFC000L
+//UMCCH1_3_AddrHashBank5
+#define UMCCH1_3_AddrHashBank5__XorEnable__SHIFT 0x0
+#define UMCCH1_3_AddrHashBank5__ColXor__SHIFT 0x1
+#define UMCCH1_3_AddrHashBank5__RowXor__SHIFT 0xe
+#define UMCCH1_3_AddrHashBank5__XorEnable_MASK 0x00000001L
+#define UMCCH1_3_AddrHashBank5__ColXor_MASK 0x00003FFEL
+#define UMCCH1_3_AddrHashBank5__RowXor_MASK 0xFFFFC000L
+//UMCCH1_3_EccErrCntSel
+#define UMCCH1_3_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0
+#define UMCCH1_3_EccErrCntSel__EccErrInt__SHIFT 0xc
+#define UMCCH1_3_EccErrCntSel__EccErrCntEn__SHIFT 0xf
+#define UMCCH1_3_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL
+#define UMCCH1_3_EccErrCntSel__EccErrInt_MASK 0x00003000L
+#define UMCCH1_3_EccErrCntSel__EccErrCntEn_MASK 0x00008000L
+//UMCCH1_3_EccErrCnt
+#define UMCCH1_3_EccErrCnt__EccErrCnt__SHIFT 0x0
+#define UMCCH1_3_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL
+//UMCCH1_3_PerfMonCtlClk
+#define UMCCH1_3_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0
+#define UMCCH1_3_PerfMonCtlClk__ClkGate__SHIFT 0x16
+#define UMCCH1_3_PerfMonCtlClk__GlblReset__SHIFT 0x18
+#define UMCCH1_3_PerfMonCtlClk__GlblMonEn__SHIFT 0x19
+#define UMCCH1_3_PerfMonCtlClk__NumCounters__SHIFT 0x1a
+#define UMCCH1_3_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f
+#define UMCCH1_3_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL
+#define UMCCH1_3_PerfMonCtlClk__ClkGate_MASK 0x00400000L
+#define UMCCH1_3_PerfMonCtlClk__GlblReset_MASK 0x01000000L
+#define UMCCH1_3_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L
+#define UMCCH1_3_PerfMonCtlClk__NumCounters_MASK 0x3C000000L
+#define UMCCH1_3_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L
+//UMCCH1_3_PerfMonCtrClk_Lo
+#define UMCCH1_3_PerfMonCtrClk_Lo__Data__SHIFT 0x0
+#define UMCCH1_3_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_3_PerfMonCtrClk_Hi
+#define UMCCH1_3_PerfMonCtrClk_Hi__Data__SHIFT 0x0
+#define UMCCH1_3_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_3_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_3_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L
+//UMCCH1_3_PerfMonCtl1
+#define UMCCH1_3_PerfMonCtl1__EventSelect__SHIFT 0x0
+#define UMCCH1_3_PerfMonCtl1__RdWrMask__SHIFT 0x8
+#define UMCCH1_3_PerfMonCtl1__PriorityMask__SHIFT 0xa
+#define UMCCH1_3_PerfMonCtl1__ReqSizeMask__SHIFT 0xe
+#define UMCCH1_3_PerfMonCtl1__BankSel__SHIFT 0x10
+#define UMCCH1_3_PerfMonCtl1__VCSel__SHIFT 0x18
+#define UMCCH1_3_PerfMonCtl1__SubChanMask__SHIFT 0x1d
+#define UMCCH1_3_PerfMonCtl1__Enable__SHIFT 0x1f
+#define UMCCH1_3_PerfMonCtl1__EventSelect_MASK 0x000000FFL
+#define UMCCH1_3_PerfMonCtl1__RdWrMask_MASK 0x00000300L
+#define UMCCH1_3_PerfMonCtl1__PriorityMask_MASK 0x00003C00L
+#define UMCCH1_3_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH1_3_PerfMonCtl1__BankSel_MASK 0x00FF0000L
+#define UMCCH1_3_PerfMonCtl1__VCSel_MASK 0x1F000000L
+#define UMCCH1_3_PerfMonCtl1__SubChanMask_MASK 0x60000000L
+#define UMCCH1_3_PerfMonCtl1__Enable_MASK 0x80000000L
+//UMCCH1_3_PerfMonCtr1_Lo
+#define UMCCH1_3_PerfMonCtr1_Lo__Data__SHIFT 0x0
+#define UMCCH1_3_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_3_PerfMonCtr1_Hi
+#define UMCCH1_3_PerfMonCtr1_Hi__Data__SHIFT 0x0
+#define UMCCH1_3_PerfMonCtr1_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_3_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH1_3_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH1_3_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_3_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L
+#define UMCCH1_3_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH1_3_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH1_3_PerfMonCtl2
+#define UMCCH1_3_PerfMonCtl2__EventSelect__SHIFT 0x0
+#define UMCCH1_3_PerfMonCtl2__RdWrMask__SHIFT 0x8
+#define UMCCH1_3_PerfMonCtl2__PriorityMask__SHIFT 0xa
+#define UMCCH1_3_PerfMonCtl2__ReqSizeMask__SHIFT 0xe
+#define UMCCH1_3_PerfMonCtl2__BankSel__SHIFT 0x10
+#define UMCCH1_3_PerfMonCtl2__VCSel__SHIFT 0x18
+#define UMCCH1_3_PerfMonCtl2__SubChanMask__SHIFT 0x1d
+#define UMCCH1_3_PerfMonCtl2__Enable__SHIFT 0x1f
+#define UMCCH1_3_PerfMonCtl2__EventSelect_MASK 0x000000FFL
+#define UMCCH1_3_PerfMonCtl2__RdWrMask_MASK 0x00000300L
+#define UMCCH1_3_PerfMonCtl2__PriorityMask_MASK 0x00003C00L
+#define UMCCH1_3_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH1_3_PerfMonCtl2__BankSel_MASK 0x00FF0000L
+#define UMCCH1_3_PerfMonCtl2__VCSel_MASK 0x1F000000L
+#define UMCCH1_3_PerfMonCtl2__SubChanMask_MASK 0x60000000L
+#define UMCCH1_3_PerfMonCtl2__Enable_MASK 0x80000000L
+//UMCCH1_3_PerfMonCtr2_Lo
+#define UMCCH1_3_PerfMonCtr2_Lo__Data__SHIFT 0x0
+#define UMCCH1_3_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_3_PerfMonCtr2_Hi
+#define UMCCH1_3_PerfMonCtr2_Hi__Data__SHIFT 0x0
+#define UMCCH1_3_PerfMonCtr2_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_3_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH1_3_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH1_3_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_3_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L
+#define UMCCH1_3_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH1_3_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH1_3_PerfMonCtl3
+#define UMCCH1_3_PerfMonCtl3__EventSelect__SHIFT 0x0
+#define UMCCH1_3_PerfMonCtl3__RdWrMask__SHIFT 0x8
+#define UMCCH1_3_PerfMonCtl3__PriorityMask__SHIFT 0xa
+#define UMCCH1_3_PerfMonCtl3__ReqSizeMask__SHIFT 0xe
+#define UMCCH1_3_PerfMonCtl3__BankSel__SHIFT 0x10
+#define UMCCH1_3_PerfMonCtl3__VCSel__SHIFT 0x18
+#define UMCCH1_3_PerfMonCtl3__SubChanMask__SHIFT 0x1d
+#define UMCCH1_3_PerfMonCtl3__Enable__SHIFT 0x1f
+#define UMCCH1_3_PerfMonCtl3__EventSelect_MASK 0x000000FFL
+#define UMCCH1_3_PerfMonCtl3__RdWrMask_MASK 0x00000300L
+#define UMCCH1_3_PerfMonCtl3__PriorityMask_MASK 0x00003C00L
+#define UMCCH1_3_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH1_3_PerfMonCtl3__BankSel_MASK 0x00FF0000L
+#define UMCCH1_3_PerfMonCtl3__VCSel_MASK 0x1F000000L
+#define UMCCH1_3_PerfMonCtl3__SubChanMask_MASK 0x60000000L
+#define UMCCH1_3_PerfMonCtl3__Enable_MASK 0x80000000L
+//UMCCH1_3_PerfMonCtr3_Lo
+#define UMCCH1_3_PerfMonCtr3_Lo__Data__SHIFT 0x0
+#define UMCCH1_3_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_3_PerfMonCtr3_Hi
+#define UMCCH1_3_PerfMonCtr3_Hi__Data__SHIFT 0x0
+#define UMCCH1_3_PerfMonCtr3_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_3_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH1_3_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH1_3_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_3_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L
+#define UMCCH1_3_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH1_3_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH1_3_PerfMonCtl4
+#define UMCCH1_3_PerfMonCtl4__EventSelect__SHIFT 0x0
+#define UMCCH1_3_PerfMonCtl4__RdWrMask__SHIFT 0x8
+#define UMCCH1_3_PerfMonCtl4__PriorityMask__SHIFT 0xa
+#define UMCCH1_3_PerfMonCtl4__ReqSizeMask__SHIFT 0xe
+#define UMCCH1_3_PerfMonCtl4__BankSel__SHIFT 0x10
+#define UMCCH1_3_PerfMonCtl4__VCSel__SHIFT 0x18
+#define UMCCH1_3_PerfMonCtl4__SubChanMask__SHIFT 0x1d
+#define UMCCH1_3_PerfMonCtl4__Enable__SHIFT 0x1f
+#define UMCCH1_3_PerfMonCtl4__EventSelect_MASK 0x000000FFL
+#define UMCCH1_3_PerfMonCtl4__RdWrMask_MASK 0x00000300L
+#define UMCCH1_3_PerfMonCtl4__PriorityMask_MASK 0x00003C00L
+#define UMCCH1_3_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH1_3_PerfMonCtl4__BankSel_MASK 0x00FF0000L
+#define UMCCH1_3_PerfMonCtl4__VCSel_MASK 0x1F000000L
+#define UMCCH1_3_PerfMonCtl4__SubChanMask_MASK 0x60000000L
+#define UMCCH1_3_PerfMonCtl4__Enable_MASK 0x80000000L
+//UMCCH1_3_PerfMonCtr4_Lo
+#define UMCCH1_3_PerfMonCtr4_Lo__Data__SHIFT 0x0
+#define UMCCH1_3_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_3_PerfMonCtr4_Hi
+#define UMCCH1_3_PerfMonCtr4_Hi__Data__SHIFT 0x0
+#define UMCCH1_3_PerfMonCtr4_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_3_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH1_3_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH1_3_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_3_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L
+#define UMCCH1_3_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH1_3_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH1_3_PerfMonCtl5
+#define UMCCH1_3_PerfMonCtl5__EventSelect__SHIFT 0x0
+#define UMCCH1_3_PerfMonCtl5__RdWrMask__SHIFT 0x8
+#define UMCCH1_3_PerfMonCtl5__PriorityMask__SHIFT 0xa
+#define UMCCH1_3_PerfMonCtl5__ReqSizeMask__SHIFT 0xe
+#define UMCCH1_3_PerfMonCtl5__BankSel__SHIFT 0x10
+#define UMCCH1_3_PerfMonCtl5__VCSel__SHIFT 0x18
+#define UMCCH1_3_PerfMonCtl5__SubChanMask__SHIFT 0x1d
+#define UMCCH1_3_PerfMonCtl5__Enable__SHIFT 0x1f
+#define UMCCH1_3_PerfMonCtl5__EventSelect_MASK 0x000000FFL
+#define UMCCH1_3_PerfMonCtl5__RdWrMask_MASK 0x00000300L
+#define UMCCH1_3_PerfMonCtl5__PriorityMask_MASK 0x00003C00L
+#define UMCCH1_3_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH1_3_PerfMonCtl5__BankSel_MASK 0x00FF0000L
+#define UMCCH1_3_PerfMonCtl5__VCSel_MASK 0x1F000000L
+#define UMCCH1_3_PerfMonCtl5__SubChanMask_MASK 0x60000000L
+#define UMCCH1_3_PerfMonCtl5__Enable_MASK 0x80000000L
+//UMCCH1_3_PerfMonCtr5_Lo
+#define UMCCH1_3_PerfMonCtr5_Lo__Data__SHIFT 0x0
+#define UMCCH1_3_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_3_PerfMonCtr5_Hi
+#define UMCCH1_3_PerfMonCtr5_Hi__Data__SHIFT 0x0
+#define UMCCH1_3_PerfMonCtr5_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_3_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH1_3_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH1_3_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_3_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L
+#define UMCCH1_3_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH1_3_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH1_3_PerfMonCtl6
+#define UMCCH1_3_PerfMonCtl6__EventSelect__SHIFT 0x0
+#define UMCCH1_3_PerfMonCtl6__RdWrMask__SHIFT 0x8
+#define UMCCH1_3_PerfMonCtl6__PriorityMask__SHIFT 0xa
+#define UMCCH1_3_PerfMonCtl6__ReqSizeMask__SHIFT 0xe
+#define UMCCH1_3_PerfMonCtl6__BankSel__SHIFT 0x10
+#define UMCCH1_3_PerfMonCtl6__VCSel__SHIFT 0x18
+#define UMCCH1_3_PerfMonCtl6__SubChanMask__SHIFT 0x1d
+#define UMCCH1_3_PerfMonCtl6__Enable__SHIFT 0x1f
+#define UMCCH1_3_PerfMonCtl6__EventSelect_MASK 0x000000FFL
+#define UMCCH1_3_PerfMonCtl6__RdWrMask_MASK 0x00000300L
+#define UMCCH1_3_PerfMonCtl6__PriorityMask_MASK 0x00003C00L
+#define UMCCH1_3_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH1_3_PerfMonCtl6__BankSel_MASK 0x00FF0000L
+#define UMCCH1_3_PerfMonCtl6__VCSel_MASK 0x1F000000L
+#define UMCCH1_3_PerfMonCtl6__SubChanMask_MASK 0x60000000L
+#define UMCCH1_3_PerfMonCtl6__Enable_MASK 0x80000000L
+//UMCCH1_3_PerfMonCtr6_Lo
+#define UMCCH1_3_PerfMonCtr6_Lo__Data__SHIFT 0x0
+#define UMCCH1_3_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_3_PerfMonCtr6_Hi
+#define UMCCH1_3_PerfMonCtr6_Hi__Data__SHIFT 0x0
+#define UMCCH1_3_PerfMonCtr6_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_3_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH1_3_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH1_3_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_3_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L
+#define UMCCH1_3_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH1_3_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH1_3_PerfMonCtl7
+#define UMCCH1_3_PerfMonCtl7__EventSelect__SHIFT 0x0
+#define UMCCH1_3_PerfMonCtl7__RdWrMask__SHIFT 0x8
+#define UMCCH1_3_PerfMonCtl7__PriorityMask__SHIFT 0xa
+#define UMCCH1_3_PerfMonCtl7__ReqSizeMask__SHIFT 0xe
+#define UMCCH1_3_PerfMonCtl7__BankSel__SHIFT 0x10
+#define UMCCH1_3_PerfMonCtl7__VCSel__SHIFT 0x18
+#define UMCCH1_3_PerfMonCtl7__SubChanMask__SHIFT 0x1d
+#define UMCCH1_3_PerfMonCtl7__Enable__SHIFT 0x1f
+#define UMCCH1_3_PerfMonCtl7__EventSelect_MASK 0x000000FFL
+#define UMCCH1_3_PerfMonCtl7__RdWrMask_MASK 0x00000300L
+#define UMCCH1_3_PerfMonCtl7__PriorityMask_MASK 0x00003C00L
+#define UMCCH1_3_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH1_3_PerfMonCtl7__BankSel_MASK 0x00FF0000L
+#define UMCCH1_3_PerfMonCtl7__VCSel_MASK 0x1F000000L
+#define UMCCH1_3_PerfMonCtl7__SubChanMask_MASK 0x60000000L
+#define UMCCH1_3_PerfMonCtl7__Enable_MASK 0x80000000L
+//UMCCH1_3_PerfMonCtr7_Lo
+#define UMCCH1_3_PerfMonCtr7_Lo__Data__SHIFT 0x0
+#define UMCCH1_3_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_3_PerfMonCtr7_Hi
+#define UMCCH1_3_PerfMonCtr7_Hi__Data__SHIFT 0x0
+#define UMCCH1_3_PerfMonCtr7_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_3_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH1_3_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH1_3_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_3_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L
+#define UMCCH1_3_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH1_3_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH1_3_PerfMonCtl8
+#define UMCCH1_3_PerfMonCtl8__EventSelect__SHIFT 0x0
+#define UMCCH1_3_PerfMonCtl8__RdWrMask__SHIFT 0x8
+#define UMCCH1_3_PerfMonCtl8__PriorityMask__SHIFT 0xa
+#define UMCCH1_3_PerfMonCtl8__ReqSizeMask__SHIFT 0xe
+#define UMCCH1_3_PerfMonCtl8__BankSel__SHIFT 0x10
+#define UMCCH1_3_PerfMonCtl8__VCSel__SHIFT 0x18
+#define UMCCH1_3_PerfMonCtl8__SubChanMask__SHIFT 0x1d
+#define UMCCH1_3_PerfMonCtl8__Enable__SHIFT 0x1f
+#define UMCCH1_3_PerfMonCtl8__EventSelect_MASK 0x000000FFL
+#define UMCCH1_3_PerfMonCtl8__RdWrMask_MASK 0x00000300L
+#define UMCCH1_3_PerfMonCtl8__PriorityMask_MASK 0x00003C00L
+#define UMCCH1_3_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH1_3_PerfMonCtl8__BankSel_MASK 0x00FF0000L
+#define UMCCH1_3_PerfMonCtl8__VCSel_MASK 0x1F000000L
+#define UMCCH1_3_PerfMonCtl8__SubChanMask_MASK 0x60000000L
+#define UMCCH1_3_PerfMonCtl8__Enable_MASK 0x80000000L
+//UMCCH1_3_PerfMonCtr8_Lo
+#define UMCCH1_3_PerfMonCtr8_Lo__Data__SHIFT 0x0
+#define UMCCH1_3_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH1_3_PerfMonCtr8_Hi
+#define UMCCH1_3_PerfMonCtr8_Hi__Data__SHIFT 0x0
+#define UMCCH1_3_PerfMonCtr8_Hi__Overflow__SHIFT 0x10
+#define UMCCH1_3_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH1_3_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH1_3_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH1_3_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L
+#define UMCCH1_3_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH1_3_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L
+
+
+// addressBlock: umc_w_phy_umc3_umcch2_umcchdec
+//UMCCH2_3_BaseAddrCS0
+#define UMCCH2_3_BaseAddrCS0__CSEnable__SHIFT 0x0
+#define UMCCH2_3_BaseAddrCS0__BaseAddr__SHIFT 0x1
+#define UMCCH2_3_BaseAddrCS0__CSEnable_MASK 0x00000001L
+#define UMCCH2_3_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL
+//UMCCH2_3_AddrMaskCS01
+#define UMCCH2_3_AddrMaskCS01__AddrMask__SHIFT 0x1
+#define UMCCH2_3_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL
+//UMCCH2_3_AddrSelCS01
+#define UMCCH2_3_AddrSelCS01__BankBit0__SHIFT 0x0
+#define UMCCH2_3_AddrSelCS01__BankBit1__SHIFT 0x4
+#define UMCCH2_3_AddrSelCS01__BankBit2__SHIFT 0x8
+#define UMCCH2_3_AddrSelCS01__BankBit3__SHIFT 0xc
+#define UMCCH2_3_AddrSelCS01__BankBit4__SHIFT 0x10
+#define UMCCH2_3_AddrSelCS01__RowLo__SHIFT 0x18
+#define UMCCH2_3_AddrSelCS01__RowHi__SHIFT 0x1c
+#define UMCCH2_3_AddrSelCS01__BankBit0_MASK 0x0000000FL
+#define UMCCH2_3_AddrSelCS01__BankBit1_MASK 0x000000F0L
+#define UMCCH2_3_AddrSelCS01__BankBit2_MASK 0x00000F00L
+#define UMCCH2_3_AddrSelCS01__BankBit3_MASK 0x0000F000L
+#define UMCCH2_3_AddrSelCS01__BankBit4_MASK 0x001F0000L
+#define UMCCH2_3_AddrSelCS01__RowLo_MASK 0x0F000000L
+#define UMCCH2_3_AddrSelCS01__RowHi_MASK 0xF0000000L
+//UMCCH2_3_AddrHashBank0
+#define UMCCH2_3_AddrHashBank0__XorEnable__SHIFT 0x0
+#define UMCCH2_3_AddrHashBank0__ColXor__SHIFT 0x1
+#define UMCCH2_3_AddrHashBank0__RowXor__SHIFT 0xe
+#define UMCCH2_3_AddrHashBank0__XorEnable_MASK 0x00000001L
+#define UMCCH2_3_AddrHashBank0__ColXor_MASK 0x00003FFEL
+#define UMCCH2_3_AddrHashBank0__RowXor_MASK 0xFFFFC000L
+//UMCCH2_3_AddrHashBank1
+#define UMCCH2_3_AddrHashBank1__XorEnable__SHIFT 0x0
+#define UMCCH2_3_AddrHashBank1__ColXor__SHIFT 0x1
+#define UMCCH2_3_AddrHashBank1__RowXor__SHIFT 0xe
+#define UMCCH2_3_AddrHashBank1__XorEnable_MASK 0x00000001L
+#define UMCCH2_3_AddrHashBank1__ColXor_MASK 0x00003FFEL
+#define UMCCH2_3_AddrHashBank1__RowXor_MASK 0xFFFFC000L
+//UMCCH2_3_AddrHashBank2
+#define UMCCH2_3_AddrHashBank2__XorEnable__SHIFT 0x0
+#define UMCCH2_3_AddrHashBank2__ColXor__SHIFT 0x1
+#define UMCCH2_3_AddrHashBank2__RowXor__SHIFT 0xe
+#define UMCCH2_3_AddrHashBank2__XorEnable_MASK 0x00000001L
+#define UMCCH2_3_AddrHashBank2__ColXor_MASK 0x00003FFEL
+#define UMCCH2_3_AddrHashBank2__RowXor_MASK 0xFFFFC000L
+//UMCCH2_3_AddrHashBank3
+#define UMCCH2_3_AddrHashBank3__XorEnable__SHIFT 0x0
+#define UMCCH2_3_AddrHashBank3__ColXor__SHIFT 0x1
+#define UMCCH2_3_AddrHashBank3__RowXor__SHIFT 0xe
+#define UMCCH2_3_AddrHashBank3__XorEnable_MASK 0x00000001L
+#define UMCCH2_3_AddrHashBank3__ColXor_MASK 0x00003FFEL
+#define UMCCH2_3_AddrHashBank3__RowXor_MASK 0xFFFFC000L
+//UMCCH2_3_AddrHashBank4
+#define UMCCH2_3_AddrHashBank4__XorEnable__SHIFT 0x0
+#define UMCCH2_3_AddrHashBank4__ColXor__SHIFT 0x1
+#define UMCCH2_3_AddrHashBank4__RowXor__SHIFT 0xe
+#define UMCCH2_3_AddrHashBank4__XorEnable_MASK 0x00000001L
+#define UMCCH2_3_AddrHashBank4__ColXor_MASK 0x00003FFEL
+#define UMCCH2_3_AddrHashBank4__RowXor_MASK 0xFFFFC000L
+//UMCCH2_3_AddrHashBank5
+#define UMCCH2_3_AddrHashBank5__XorEnable__SHIFT 0x0
+#define UMCCH2_3_AddrHashBank5__ColXor__SHIFT 0x1
+#define UMCCH2_3_AddrHashBank5__RowXor__SHIFT 0xe
+#define UMCCH2_3_AddrHashBank5__XorEnable_MASK 0x00000001L
+#define UMCCH2_3_AddrHashBank5__ColXor_MASK 0x00003FFEL
+#define UMCCH2_3_AddrHashBank5__RowXor_MASK 0xFFFFC000L
+//UMCCH2_3_EccErrCntSel
+#define UMCCH2_3_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0
+#define UMCCH2_3_EccErrCntSel__EccErrInt__SHIFT 0xc
+#define UMCCH2_3_EccErrCntSel__EccErrCntEn__SHIFT 0xf
+#define UMCCH2_3_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL
+#define UMCCH2_3_EccErrCntSel__EccErrInt_MASK 0x00003000L
+#define UMCCH2_3_EccErrCntSel__EccErrCntEn_MASK 0x00008000L
+//UMCCH2_3_EccErrCnt
+#define UMCCH2_3_EccErrCnt__EccErrCnt__SHIFT 0x0
+#define UMCCH2_3_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL
+//UMCCH2_3_PerfMonCtlClk
+#define UMCCH2_3_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0
+#define UMCCH2_3_PerfMonCtlClk__ClkGate__SHIFT 0x16
+#define UMCCH2_3_PerfMonCtlClk__GlblReset__SHIFT 0x18
+#define UMCCH2_3_PerfMonCtlClk__GlblMonEn__SHIFT 0x19
+#define UMCCH2_3_PerfMonCtlClk__NumCounters__SHIFT 0x1a
+#define UMCCH2_3_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f
+#define UMCCH2_3_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL
+#define UMCCH2_3_PerfMonCtlClk__ClkGate_MASK 0x00400000L
+#define UMCCH2_3_PerfMonCtlClk__GlblReset_MASK 0x01000000L
+#define UMCCH2_3_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L
+#define UMCCH2_3_PerfMonCtlClk__NumCounters_MASK 0x3C000000L
+#define UMCCH2_3_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L
+//UMCCH2_3_PerfMonCtrClk_Lo
+#define UMCCH2_3_PerfMonCtrClk_Lo__Data__SHIFT 0x0
+#define UMCCH2_3_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_3_PerfMonCtrClk_Hi
+#define UMCCH2_3_PerfMonCtrClk_Hi__Data__SHIFT 0x0
+#define UMCCH2_3_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_3_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_3_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L
+//UMCCH2_3_PerfMonCtl1
+#define UMCCH2_3_PerfMonCtl1__EventSelect__SHIFT 0x0
+#define UMCCH2_3_PerfMonCtl1__RdWrMask__SHIFT 0x8
+#define UMCCH2_3_PerfMonCtl1__PriorityMask__SHIFT 0xa
+#define UMCCH2_3_PerfMonCtl1__ReqSizeMask__SHIFT 0xe
+#define UMCCH2_3_PerfMonCtl1__BankSel__SHIFT 0x10
+#define UMCCH2_3_PerfMonCtl1__VCSel__SHIFT 0x18
+#define UMCCH2_3_PerfMonCtl1__SubChanMask__SHIFT 0x1d
+#define UMCCH2_3_PerfMonCtl1__Enable__SHIFT 0x1f
+#define UMCCH2_3_PerfMonCtl1__EventSelect_MASK 0x000000FFL
+#define UMCCH2_3_PerfMonCtl1__RdWrMask_MASK 0x00000300L
+#define UMCCH2_3_PerfMonCtl1__PriorityMask_MASK 0x00003C00L
+#define UMCCH2_3_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH2_3_PerfMonCtl1__BankSel_MASK 0x00FF0000L
+#define UMCCH2_3_PerfMonCtl1__VCSel_MASK 0x1F000000L
+#define UMCCH2_3_PerfMonCtl1__SubChanMask_MASK 0x60000000L
+#define UMCCH2_3_PerfMonCtl1__Enable_MASK 0x80000000L
+//UMCCH2_3_PerfMonCtr1_Lo
+#define UMCCH2_3_PerfMonCtr1_Lo__Data__SHIFT 0x0
+#define UMCCH2_3_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_3_PerfMonCtr1_Hi
+#define UMCCH2_3_PerfMonCtr1_Hi__Data__SHIFT 0x0
+#define UMCCH2_3_PerfMonCtr1_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_3_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH2_3_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH2_3_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_3_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L
+#define UMCCH2_3_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH2_3_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH2_3_PerfMonCtl2
+#define UMCCH2_3_PerfMonCtl2__EventSelect__SHIFT 0x0
+#define UMCCH2_3_PerfMonCtl2__RdWrMask__SHIFT 0x8
+#define UMCCH2_3_PerfMonCtl2__PriorityMask__SHIFT 0xa
+#define UMCCH2_3_PerfMonCtl2__ReqSizeMask__SHIFT 0xe
+#define UMCCH2_3_PerfMonCtl2__BankSel__SHIFT 0x10
+#define UMCCH2_3_PerfMonCtl2__VCSel__SHIFT 0x18
+#define UMCCH2_3_PerfMonCtl2__SubChanMask__SHIFT 0x1d
+#define UMCCH2_3_PerfMonCtl2__Enable__SHIFT 0x1f
+#define UMCCH2_3_PerfMonCtl2__EventSelect_MASK 0x000000FFL
+#define UMCCH2_3_PerfMonCtl2__RdWrMask_MASK 0x00000300L
+#define UMCCH2_3_PerfMonCtl2__PriorityMask_MASK 0x00003C00L
+#define UMCCH2_3_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH2_3_PerfMonCtl2__BankSel_MASK 0x00FF0000L
+#define UMCCH2_3_PerfMonCtl2__VCSel_MASK 0x1F000000L
+#define UMCCH2_3_PerfMonCtl2__SubChanMask_MASK 0x60000000L
+#define UMCCH2_3_PerfMonCtl2__Enable_MASK 0x80000000L
+//UMCCH2_3_PerfMonCtr2_Lo
+#define UMCCH2_3_PerfMonCtr2_Lo__Data__SHIFT 0x0
+#define UMCCH2_3_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_3_PerfMonCtr2_Hi
+#define UMCCH2_3_PerfMonCtr2_Hi__Data__SHIFT 0x0
+#define UMCCH2_3_PerfMonCtr2_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_3_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH2_3_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH2_3_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_3_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L
+#define UMCCH2_3_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH2_3_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH2_3_PerfMonCtl3
+#define UMCCH2_3_PerfMonCtl3__EventSelect__SHIFT 0x0
+#define UMCCH2_3_PerfMonCtl3__RdWrMask__SHIFT 0x8
+#define UMCCH2_3_PerfMonCtl3__PriorityMask__SHIFT 0xa
+#define UMCCH2_3_PerfMonCtl3__ReqSizeMask__SHIFT 0xe
+#define UMCCH2_3_PerfMonCtl3__BankSel__SHIFT 0x10
+#define UMCCH2_3_PerfMonCtl3__VCSel__SHIFT 0x18
+#define UMCCH2_3_PerfMonCtl3__SubChanMask__SHIFT 0x1d
+#define UMCCH2_3_PerfMonCtl3__Enable__SHIFT 0x1f
+#define UMCCH2_3_PerfMonCtl3__EventSelect_MASK 0x000000FFL
+#define UMCCH2_3_PerfMonCtl3__RdWrMask_MASK 0x00000300L
+#define UMCCH2_3_PerfMonCtl3__PriorityMask_MASK 0x00003C00L
+#define UMCCH2_3_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH2_3_PerfMonCtl3__BankSel_MASK 0x00FF0000L
+#define UMCCH2_3_PerfMonCtl3__VCSel_MASK 0x1F000000L
+#define UMCCH2_3_PerfMonCtl3__SubChanMask_MASK 0x60000000L
+#define UMCCH2_3_PerfMonCtl3__Enable_MASK 0x80000000L
+//UMCCH2_3_PerfMonCtr3_Lo
+#define UMCCH2_3_PerfMonCtr3_Lo__Data__SHIFT 0x0
+#define UMCCH2_3_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_3_PerfMonCtr3_Hi
+#define UMCCH2_3_PerfMonCtr3_Hi__Data__SHIFT 0x0
+#define UMCCH2_3_PerfMonCtr3_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_3_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH2_3_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH2_3_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_3_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L
+#define UMCCH2_3_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH2_3_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH2_3_PerfMonCtl4
+#define UMCCH2_3_PerfMonCtl4__EventSelect__SHIFT 0x0
+#define UMCCH2_3_PerfMonCtl4__RdWrMask__SHIFT 0x8
+#define UMCCH2_3_PerfMonCtl4__PriorityMask__SHIFT 0xa
+#define UMCCH2_3_PerfMonCtl4__ReqSizeMask__SHIFT 0xe
+#define UMCCH2_3_PerfMonCtl4__BankSel__SHIFT 0x10
+#define UMCCH2_3_PerfMonCtl4__VCSel__SHIFT 0x18
+#define UMCCH2_3_PerfMonCtl4__SubChanMask__SHIFT 0x1d
+#define UMCCH2_3_PerfMonCtl4__Enable__SHIFT 0x1f
+#define UMCCH2_3_PerfMonCtl4__EventSelect_MASK 0x000000FFL
+#define UMCCH2_3_PerfMonCtl4__RdWrMask_MASK 0x00000300L
+#define UMCCH2_3_PerfMonCtl4__PriorityMask_MASK 0x00003C00L
+#define UMCCH2_3_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH2_3_PerfMonCtl4__BankSel_MASK 0x00FF0000L
+#define UMCCH2_3_PerfMonCtl4__VCSel_MASK 0x1F000000L
+#define UMCCH2_3_PerfMonCtl4__SubChanMask_MASK 0x60000000L
+#define UMCCH2_3_PerfMonCtl4__Enable_MASK 0x80000000L
+//UMCCH2_3_PerfMonCtr4_Lo
+#define UMCCH2_3_PerfMonCtr4_Lo__Data__SHIFT 0x0
+#define UMCCH2_3_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_3_PerfMonCtr4_Hi
+#define UMCCH2_3_PerfMonCtr4_Hi__Data__SHIFT 0x0
+#define UMCCH2_3_PerfMonCtr4_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_3_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH2_3_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH2_3_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_3_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L
+#define UMCCH2_3_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH2_3_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH2_3_PerfMonCtl5
+#define UMCCH2_3_PerfMonCtl5__EventSelect__SHIFT 0x0
+#define UMCCH2_3_PerfMonCtl5__RdWrMask__SHIFT 0x8
+#define UMCCH2_3_PerfMonCtl5__PriorityMask__SHIFT 0xa
+#define UMCCH2_3_PerfMonCtl5__ReqSizeMask__SHIFT 0xe
+#define UMCCH2_3_PerfMonCtl5__BankSel__SHIFT 0x10
+#define UMCCH2_3_PerfMonCtl5__VCSel__SHIFT 0x18
+#define UMCCH2_3_PerfMonCtl5__SubChanMask__SHIFT 0x1d
+#define UMCCH2_3_PerfMonCtl5__Enable__SHIFT 0x1f
+#define UMCCH2_3_PerfMonCtl5__EventSelect_MASK 0x000000FFL
+#define UMCCH2_3_PerfMonCtl5__RdWrMask_MASK 0x00000300L
+#define UMCCH2_3_PerfMonCtl5__PriorityMask_MASK 0x00003C00L
+#define UMCCH2_3_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH2_3_PerfMonCtl5__BankSel_MASK 0x00FF0000L
+#define UMCCH2_3_PerfMonCtl5__VCSel_MASK 0x1F000000L
+#define UMCCH2_3_PerfMonCtl5__SubChanMask_MASK 0x60000000L
+#define UMCCH2_3_PerfMonCtl5__Enable_MASK 0x80000000L
+//UMCCH2_3_PerfMonCtr5_Lo
+#define UMCCH2_3_PerfMonCtr5_Lo__Data__SHIFT 0x0
+#define UMCCH2_3_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_3_PerfMonCtr5_Hi
+#define UMCCH2_3_PerfMonCtr5_Hi__Data__SHIFT 0x0
+#define UMCCH2_3_PerfMonCtr5_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_3_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH2_3_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH2_3_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_3_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L
+#define UMCCH2_3_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH2_3_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH2_3_PerfMonCtl6
+#define UMCCH2_3_PerfMonCtl6__EventSelect__SHIFT 0x0
+#define UMCCH2_3_PerfMonCtl6__RdWrMask__SHIFT 0x8
+#define UMCCH2_3_PerfMonCtl6__PriorityMask__SHIFT 0xa
+#define UMCCH2_3_PerfMonCtl6__ReqSizeMask__SHIFT 0xe
+#define UMCCH2_3_PerfMonCtl6__BankSel__SHIFT 0x10
+#define UMCCH2_3_PerfMonCtl6__VCSel__SHIFT 0x18
+#define UMCCH2_3_PerfMonCtl6__SubChanMask__SHIFT 0x1d
+#define UMCCH2_3_PerfMonCtl6__Enable__SHIFT 0x1f
+#define UMCCH2_3_PerfMonCtl6__EventSelect_MASK 0x000000FFL
+#define UMCCH2_3_PerfMonCtl6__RdWrMask_MASK 0x00000300L
+#define UMCCH2_3_PerfMonCtl6__PriorityMask_MASK 0x00003C00L
+#define UMCCH2_3_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH2_3_PerfMonCtl6__BankSel_MASK 0x00FF0000L
+#define UMCCH2_3_PerfMonCtl6__VCSel_MASK 0x1F000000L
+#define UMCCH2_3_PerfMonCtl6__SubChanMask_MASK 0x60000000L
+#define UMCCH2_3_PerfMonCtl6__Enable_MASK 0x80000000L
+//UMCCH2_3_PerfMonCtr6_Lo
+#define UMCCH2_3_PerfMonCtr6_Lo__Data__SHIFT 0x0
+#define UMCCH2_3_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_3_PerfMonCtr6_Hi
+#define UMCCH2_3_PerfMonCtr6_Hi__Data__SHIFT 0x0
+#define UMCCH2_3_PerfMonCtr6_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_3_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH2_3_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH2_3_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_3_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L
+#define UMCCH2_3_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH2_3_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH2_3_PerfMonCtl7
+#define UMCCH2_3_PerfMonCtl7__EventSelect__SHIFT 0x0
+#define UMCCH2_3_PerfMonCtl7__RdWrMask__SHIFT 0x8
+#define UMCCH2_3_PerfMonCtl7__PriorityMask__SHIFT 0xa
+#define UMCCH2_3_PerfMonCtl7__ReqSizeMask__SHIFT 0xe
+#define UMCCH2_3_PerfMonCtl7__BankSel__SHIFT 0x10
+#define UMCCH2_3_PerfMonCtl7__VCSel__SHIFT 0x18
+#define UMCCH2_3_PerfMonCtl7__SubChanMask__SHIFT 0x1d
+#define UMCCH2_3_PerfMonCtl7__Enable__SHIFT 0x1f
+#define UMCCH2_3_PerfMonCtl7__EventSelect_MASK 0x000000FFL
+#define UMCCH2_3_PerfMonCtl7__RdWrMask_MASK 0x00000300L
+#define UMCCH2_3_PerfMonCtl7__PriorityMask_MASK 0x00003C00L
+#define UMCCH2_3_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH2_3_PerfMonCtl7__BankSel_MASK 0x00FF0000L
+#define UMCCH2_3_PerfMonCtl7__VCSel_MASK 0x1F000000L
+#define UMCCH2_3_PerfMonCtl7__SubChanMask_MASK 0x60000000L
+#define UMCCH2_3_PerfMonCtl7__Enable_MASK 0x80000000L
+//UMCCH2_3_PerfMonCtr7_Lo
+#define UMCCH2_3_PerfMonCtr7_Lo__Data__SHIFT 0x0
+#define UMCCH2_3_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_3_PerfMonCtr7_Hi
+#define UMCCH2_3_PerfMonCtr7_Hi__Data__SHIFT 0x0
+#define UMCCH2_3_PerfMonCtr7_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_3_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH2_3_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH2_3_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_3_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L
+#define UMCCH2_3_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH2_3_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH2_3_PerfMonCtl8
+#define UMCCH2_3_PerfMonCtl8__EventSelect__SHIFT 0x0
+#define UMCCH2_3_PerfMonCtl8__RdWrMask__SHIFT 0x8
+#define UMCCH2_3_PerfMonCtl8__PriorityMask__SHIFT 0xa
+#define UMCCH2_3_PerfMonCtl8__ReqSizeMask__SHIFT 0xe
+#define UMCCH2_3_PerfMonCtl8__BankSel__SHIFT 0x10
+#define UMCCH2_3_PerfMonCtl8__VCSel__SHIFT 0x18
+#define UMCCH2_3_PerfMonCtl8__SubChanMask__SHIFT 0x1d
+#define UMCCH2_3_PerfMonCtl8__Enable__SHIFT 0x1f
+#define UMCCH2_3_PerfMonCtl8__EventSelect_MASK 0x000000FFL
+#define UMCCH2_3_PerfMonCtl8__RdWrMask_MASK 0x00000300L
+#define UMCCH2_3_PerfMonCtl8__PriorityMask_MASK 0x00003C00L
+#define UMCCH2_3_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH2_3_PerfMonCtl8__BankSel_MASK 0x00FF0000L
+#define UMCCH2_3_PerfMonCtl8__VCSel_MASK 0x1F000000L
+#define UMCCH2_3_PerfMonCtl8__SubChanMask_MASK 0x60000000L
+#define UMCCH2_3_PerfMonCtl8__Enable_MASK 0x80000000L
+//UMCCH2_3_PerfMonCtr8_Lo
+#define UMCCH2_3_PerfMonCtr8_Lo__Data__SHIFT 0x0
+#define UMCCH2_3_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH2_3_PerfMonCtr8_Hi
+#define UMCCH2_3_PerfMonCtr8_Hi__Data__SHIFT 0x0
+#define UMCCH2_3_PerfMonCtr8_Hi__Overflow__SHIFT 0x10
+#define UMCCH2_3_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH2_3_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH2_3_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH2_3_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L
+#define UMCCH2_3_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH2_3_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L
+
+
+// addressBlock: umc_w_phy_umc3_umcch3_umcchdec
+//UMCCH3_3_BaseAddrCS0
+#define UMCCH3_3_BaseAddrCS0__CSEnable__SHIFT 0x0
+#define UMCCH3_3_BaseAddrCS0__BaseAddr__SHIFT 0x1
+#define UMCCH3_3_BaseAddrCS0__CSEnable_MASK 0x00000001L
+#define UMCCH3_3_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL
+//UMCCH3_3_AddrMaskCS01
+#define UMCCH3_3_AddrMaskCS01__AddrMask__SHIFT 0x1
+#define UMCCH3_3_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL
+//UMCCH3_3_AddrSelCS01
+#define UMCCH3_3_AddrSelCS01__BankBit0__SHIFT 0x0
+#define UMCCH3_3_AddrSelCS01__BankBit1__SHIFT 0x4
+#define UMCCH3_3_AddrSelCS01__BankBit2__SHIFT 0x8
+#define UMCCH3_3_AddrSelCS01__BankBit3__SHIFT 0xc
+#define UMCCH3_3_AddrSelCS01__BankBit4__SHIFT 0x10
+#define UMCCH3_3_AddrSelCS01__RowLo__SHIFT 0x18
+#define UMCCH3_3_AddrSelCS01__RowHi__SHIFT 0x1c
+#define UMCCH3_3_AddrSelCS01__BankBit0_MASK 0x0000000FL
+#define UMCCH3_3_AddrSelCS01__BankBit1_MASK 0x000000F0L
+#define UMCCH3_3_AddrSelCS01__BankBit2_MASK 0x00000F00L
+#define UMCCH3_3_AddrSelCS01__BankBit3_MASK 0x0000F000L
+#define UMCCH3_3_AddrSelCS01__BankBit4_MASK 0x001F0000L
+#define UMCCH3_3_AddrSelCS01__RowLo_MASK 0x0F000000L
+#define UMCCH3_3_AddrSelCS01__RowHi_MASK 0xF0000000L
+//UMCCH3_3_AddrHashBank0
+#define UMCCH3_3_AddrHashBank0__XorEnable__SHIFT 0x0
+#define UMCCH3_3_AddrHashBank0__ColXor__SHIFT 0x1
+#define UMCCH3_3_AddrHashBank0__RowXor__SHIFT 0xe
+#define UMCCH3_3_AddrHashBank0__XorEnable_MASK 0x00000001L
+#define UMCCH3_3_AddrHashBank0__ColXor_MASK 0x00003FFEL
+#define UMCCH3_3_AddrHashBank0__RowXor_MASK 0xFFFFC000L
+//UMCCH3_3_AddrHashBank1
+#define UMCCH3_3_AddrHashBank1__XorEnable__SHIFT 0x0
+#define UMCCH3_3_AddrHashBank1__ColXor__SHIFT 0x1
+#define UMCCH3_3_AddrHashBank1__RowXor__SHIFT 0xe
+#define UMCCH3_3_AddrHashBank1__XorEnable_MASK 0x00000001L
+#define UMCCH3_3_AddrHashBank1__ColXor_MASK 0x00003FFEL
+#define UMCCH3_3_AddrHashBank1__RowXor_MASK 0xFFFFC000L
+//UMCCH3_3_AddrHashBank2
+#define UMCCH3_3_AddrHashBank2__XorEnable__SHIFT 0x0
+#define UMCCH3_3_AddrHashBank2__ColXor__SHIFT 0x1
+#define UMCCH3_3_AddrHashBank2__RowXor__SHIFT 0xe
+#define UMCCH3_3_AddrHashBank2__XorEnable_MASK 0x00000001L
+#define UMCCH3_3_AddrHashBank2__ColXor_MASK 0x00003FFEL
+#define UMCCH3_3_AddrHashBank2__RowXor_MASK 0xFFFFC000L
+//UMCCH3_3_AddrHashBank3
+#define UMCCH3_3_AddrHashBank3__XorEnable__SHIFT 0x0
+#define UMCCH3_3_AddrHashBank3__ColXor__SHIFT 0x1
+#define UMCCH3_3_AddrHashBank3__RowXor__SHIFT 0xe
+#define UMCCH3_3_AddrHashBank3__XorEnable_MASK 0x00000001L
+#define UMCCH3_3_AddrHashBank3__ColXor_MASK 0x00003FFEL
+#define UMCCH3_3_AddrHashBank3__RowXor_MASK 0xFFFFC000L
+//UMCCH3_3_AddrHashBank4
+#define UMCCH3_3_AddrHashBank4__XorEnable__SHIFT 0x0
+#define UMCCH3_3_AddrHashBank4__ColXor__SHIFT 0x1
+#define UMCCH3_3_AddrHashBank4__RowXor__SHIFT 0xe
+#define UMCCH3_3_AddrHashBank4__XorEnable_MASK 0x00000001L
+#define UMCCH3_3_AddrHashBank4__ColXor_MASK 0x00003FFEL
+#define UMCCH3_3_AddrHashBank4__RowXor_MASK 0xFFFFC000L
+//UMCCH3_3_AddrHashBank5
+#define UMCCH3_3_AddrHashBank5__XorEnable__SHIFT 0x0
+#define UMCCH3_3_AddrHashBank5__ColXor__SHIFT 0x1
+#define UMCCH3_3_AddrHashBank5__RowXor__SHIFT 0xe
+#define UMCCH3_3_AddrHashBank5__XorEnable_MASK 0x00000001L
+#define UMCCH3_3_AddrHashBank5__ColXor_MASK 0x00003FFEL
+#define UMCCH3_3_AddrHashBank5__RowXor_MASK 0xFFFFC000L
+//UMCCH3_3_EccErrCntSel
+#define UMCCH3_3_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0
+#define UMCCH3_3_EccErrCntSel__EccErrInt__SHIFT 0xc
+#define UMCCH3_3_EccErrCntSel__EccErrCntEn__SHIFT 0xf
+#define UMCCH3_3_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL
+#define UMCCH3_3_EccErrCntSel__EccErrInt_MASK 0x00003000L
+#define UMCCH3_3_EccErrCntSel__EccErrCntEn_MASK 0x00008000L
+//UMCCH3_3_EccErrCnt
+#define UMCCH3_3_EccErrCnt__EccErrCnt__SHIFT 0x0
+#define UMCCH3_3_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL
+//UMCCH3_3_PerfMonCtlClk
+#define UMCCH3_3_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0
+#define UMCCH3_3_PerfMonCtlClk__ClkGate__SHIFT 0x16
+#define UMCCH3_3_PerfMonCtlClk__GlblReset__SHIFT 0x18
+#define UMCCH3_3_PerfMonCtlClk__GlblMonEn__SHIFT 0x19
+#define UMCCH3_3_PerfMonCtlClk__NumCounters__SHIFT 0x1a
+#define UMCCH3_3_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f
+#define UMCCH3_3_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL
+#define UMCCH3_3_PerfMonCtlClk__ClkGate_MASK 0x00400000L
+#define UMCCH3_3_PerfMonCtlClk__GlblReset_MASK 0x01000000L
+#define UMCCH3_3_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L
+#define UMCCH3_3_PerfMonCtlClk__NumCounters_MASK 0x3C000000L
+#define UMCCH3_3_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L
+//UMCCH3_3_PerfMonCtrClk_Lo
+#define UMCCH3_3_PerfMonCtrClk_Lo__Data__SHIFT 0x0
+#define UMCCH3_3_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_3_PerfMonCtrClk_Hi
+#define UMCCH3_3_PerfMonCtrClk_Hi__Data__SHIFT 0x0
+#define UMCCH3_3_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_3_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_3_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L
+//UMCCH3_3_PerfMonCtl1
+#define UMCCH3_3_PerfMonCtl1__EventSelect__SHIFT 0x0
+#define UMCCH3_3_PerfMonCtl1__RdWrMask__SHIFT 0x8
+#define UMCCH3_3_PerfMonCtl1__PriorityMask__SHIFT 0xa
+#define UMCCH3_3_PerfMonCtl1__ReqSizeMask__SHIFT 0xe
+#define UMCCH3_3_PerfMonCtl1__BankSel__SHIFT 0x10
+#define UMCCH3_3_PerfMonCtl1__VCSel__SHIFT 0x18
+#define UMCCH3_3_PerfMonCtl1__SubChanMask__SHIFT 0x1d
+#define UMCCH3_3_PerfMonCtl1__Enable__SHIFT 0x1f
+#define UMCCH3_3_PerfMonCtl1__EventSelect_MASK 0x000000FFL
+#define UMCCH3_3_PerfMonCtl1__RdWrMask_MASK 0x00000300L
+#define UMCCH3_3_PerfMonCtl1__PriorityMask_MASK 0x00003C00L
+#define UMCCH3_3_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH3_3_PerfMonCtl1__BankSel_MASK 0x00FF0000L
+#define UMCCH3_3_PerfMonCtl1__VCSel_MASK 0x1F000000L
+#define UMCCH3_3_PerfMonCtl1__SubChanMask_MASK 0x60000000L
+#define UMCCH3_3_PerfMonCtl1__Enable_MASK 0x80000000L
+//UMCCH3_3_PerfMonCtr1_Lo
+#define UMCCH3_3_PerfMonCtr1_Lo__Data__SHIFT 0x0
+#define UMCCH3_3_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_3_PerfMonCtr1_Hi
+#define UMCCH3_3_PerfMonCtr1_Hi__Data__SHIFT 0x0
+#define UMCCH3_3_PerfMonCtr1_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_3_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH3_3_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH3_3_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_3_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L
+#define UMCCH3_3_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH3_3_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH3_3_PerfMonCtl2
+#define UMCCH3_3_PerfMonCtl2__EventSelect__SHIFT 0x0
+#define UMCCH3_3_PerfMonCtl2__RdWrMask__SHIFT 0x8
+#define UMCCH3_3_PerfMonCtl2__PriorityMask__SHIFT 0xa
+#define UMCCH3_3_PerfMonCtl2__ReqSizeMask__SHIFT 0xe
+#define UMCCH3_3_PerfMonCtl2__BankSel__SHIFT 0x10
+#define UMCCH3_3_PerfMonCtl2__VCSel__SHIFT 0x18
+#define UMCCH3_3_PerfMonCtl2__SubChanMask__SHIFT 0x1d
+#define UMCCH3_3_PerfMonCtl2__Enable__SHIFT 0x1f
+#define UMCCH3_3_PerfMonCtl2__EventSelect_MASK 0x000000FFL
+#define UMCCH3_3_PerfMonCtl2__RdWrMask_MASK 0x00000300L
+#define UMCCH3_3_PerfMonCtl2__PriorityMask_MASK 0x00003C00L
+#define UMCCH3_3_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH3_3_PerfMonCtl2__BankSel_MASK 0x00FF0000L
+#define UMCCH3_3_PerfMonCtl2__VCSel_MASK 0x1F000000L
+#define UMCCH3_3_PerfMonCtl2__SubChanMask_MASK 0x60000000L
+#define UMCCH3_3_PerfMonCtl2__Enable_MASK 0x80000000L
+//UMCCH3_3_PerfMonCtr2_Lo
+#define UMCCH3_3_PerfMonCtr2_Lo__Data__SHIFT 0x0
+#define UMCCH3_3_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_3_PerfMonCtr2_Hi
+#define UMCCH3_3_PerfMonCtr2_Hi__Data__SHIFT 0x0
+#define UMCCH3_3_PerfMonCtr2_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_3_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH3_3_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH3_3_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_3_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L
+#define UMCCH3_3_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH3_3_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH3_3_PerfMonCtl3
+#define UMCCH3_3_PerfMonCtl3__EventSelect__SHIFT 0x0
+#define UMCCH3_3_PerfMonCtl3__RdWrMask__SHIFT 0x8
+#define UMCCH3_3_PerfMonCtl3__PriorityMask__SHIFT 0xa
+#define UMCCH3_3_PerfMonCtl3__ReqSizeMask__SHIFT 0xe
+#define UMCCH3_3_PerfMonCtl3__BankSel__SHIFT 0x10
+#define UMCCH3_3_PerfMonCtl3__VCSel__SHIFT 0x18
+#define UMCCH3_3_PerfMonCtl3__SubChanMask__SHIFT 0x1d
+#define UMCCH3_3_PerfMonCtl3__Enable__SHIFT 0x1f
+#define UMCCH3_3_PerfMonCtl3__EventSelect_MASK 0x000000FFL
+#define UMCCH3_3_PerfMonCtl3__RdWrMask_MASK 0x00000300L
+#define UMCCH3_3_PerfMonCtl3__PriorityMask_MASK 0x00003C00L
+#define UMCCH3_3_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH3_3_PerfMonCtl3__BankSel_MASK 0x00FF0000L
+#define UMCCH3_3_PerfMonCtl3__VCSel_MASK 0x1F000000L
+#define UMCCH3_3_PerfMonCtl3__SubChanMask_MASK 0x60000000L
+#define UMCCH3_3_PerfMonCtl3__Enable_MASK 0x80000000L
+//UMCCH3_3_PerfMonCtr3_Lo
+#define UMCCH3_3_PerfMonCtr3_Lo__Data__SHIFT 0x0
+#define UMCCH3_3_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_3_PerfMonCtr3_Hi
+#define UMCCH3_3_PerfMonCtr3_Hi__Data__SHIFT 0x0
+#define UMCCH3_3_PerfMonCtr3_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_3_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH3_3_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH3_3_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_3_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L
+#define UMCCH3_3_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH3_3_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH3_3_PerfMonCtl4
+#define UMCCH3_3_PerfMonCtl4__EventSelect__SHIFT 0x0
+#define UMCCH3_3_PerfMonCtl4__RdWrMask__SHIFT 0x8
+#define UMCCH3_3_PerfMonCtl4__PriorityMask__SHIFT 0xa
+#define UMCCH3_3_PerfMonCtl4__ReqSizeMask__SHIFT 0xe
+#define UMCCH3_3_PerfMonCtl4__BankSel__SHIFT 0x10
+#define UMCCH3_3_PerfMonCtl4__VCSel__SHIFT 0x18
+#define UMCCH3_3_PerfMonCtl4__SubChanMask__SHIFT 0x1d
+#define UMCCH3_3_PerfMonCtl4__Enable__SHIFT 0x1f
+#define UMCCH3_3_PerfMonCtl4__EventSelect_MASK 0x000000FFL
+#define UMCCH3_3_PerfMonCtl4__RdWrMask_MASK 0x00000300L
+#define UMCCH3_3_PerfMonCtl4__PriorityMask_MASK 0x00003C00L
+#define UMCCH3_3_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH3_3_PerfMonCtl4__BankSel_MASK 0x00FF0000L
+#define UMCCH3_3_PerfMonCtl4__VCSel_MASK 0x1F000000L
+#define UMCCH3_3_PerfMonCtl4__SubChanMask_MASK 0x60000000L
+#define UMCCH3_3_PerfMonCtl4__Enable_MASK 0x80000000L
+//UMCCH3_3_PerfMonCtr4_Lo
+#define UMCCH3_3_PerfMonCtr4_Lo__Data__SHIFT 0x0
+#define UMCCH3_3_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_3_PerfMonCtr4_Hi
+#define UMCCH3_3_PerfMonCtr4_Hi__Data__SHIFT 0x0
+#define UMCCH3_3_PerfMonCtr4_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_3_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH3_3_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH3_3_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_3_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L
+#define UMCCH3_3_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH3_3_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH3_3_PerfMonCtl5
+#define UMCCH3_3_PerfMonCtl5__EventSelect__SHIFT 0x0
+#define UMCCH3_3_PerfMonCtl5__RdWrMask__SHIFT 0x8
+#define UMCCH3_3_PerfMonCtl5__PriorityMask__SHIFT 0xa
+#define UMCCH3_3_PerfMonCtl5__ReqSizeMask__SHIFT 0xe
+#define UMCCH3_3_PerfMonCtl5__BankSel__SHIFT 0x10
+#define UMCCH3_3_PerfMonCtl5__VCSel__SHIFT 0x18
+#define UMCCH3_3_PerfMonCtl5__SubChanMask__SHIFT 0x1d
+#define UMCCH3_3_PerfMonCtl5__Enable__SHIFT 0x1f
+#define UMCCH3_3_PerfMonCtl5__EventSelect_MASK 0x000000FFL
+#define UMCCH3_3_PerfMonCtl5__RdWrMask_MASK 0x00000300L
+#define UMCCH3_3_PerfMonCtl5__PriorityMask_MASK 0x00003C00L
+#define UMCCH3_3_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH3_3_PerfMonCtl5__BankSel_MASK 0x00FF0000L
+#define UMCCH3_3_PerfMonCtl5__VCSel_MASK 0x1F000000L
+#define UMCCH3_3_PerfMonCtl5__SubChanMask_MASK 0x60000000L
+#define UMCCH3_3_PerfMonCtl5__Enable_MASK 0x80000000L
+//UMCCH3_3_PerfMonCtr5_Lo
+#define UMCCH3_3_PerfMonCtr5_Lo__Data__SHIFT 0x0
+#define UMCCH3_3_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_3_PerfMonCtr5_Hi
+#define UMCCH3_3_PerfMonCtr5_Hi__Data__SHIFT 0x0
+#define UMCCH3_3_PerfMonCtr5_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_3_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH3_3_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH3_3_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_3_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L
+#define UMCCH3_3_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH3_3_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH3_3_PerfMonCtl6
+#define UMCCH3_3_PerfMonCtl6__EventSelect__SHIFT 0x0
+#define UMCCH3_3_PerfMonCtl6__RdWrMask__SHIFT 0x8
+#define UMCCH3_3_PerfMonCtl6__PriorityMask__SHIFT 0xa
+#define UMCCH3_3_PerfMonCtl6__ReqSizeMask__SHIFT 0xe
+#define UMCCH3_3_PerfMonCtl6__BankSel__SHIFT 0x10
+#define UMCCH3_3_PerfMonCtl6__VCSel__SHIFT 0x18
+#define UMCCH3_3_PerfMonCtl6__SubChanMask__SHIFT 0x1d
+#define UMCCH3_3_PerfMonCtl6__Enable__SHIFT 0x1f
+#define UMCCH3_3_PerfMonCtl6__EventSelect_MASK 0x000000FFL
+#define UMCCH3_3_PerfMonCtl6__RdWrMask_MASK 0x00000300L
+#define UMCCH3_3_PerfMonCtl6__PriorityMask_MASK 0x00003C00L
+#define UMCCH3_3_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH3_3_PerfMonCtl6__BankSel_MASK 0x00FF0000L
+#define UMCCH3_3_PerfMonCtl6__VCSel_MASK 0x1F000000L
+#define UMCCH3_3_PerfMonCtl6__SubChanMask_MASK 0x60000000L
+#define UMCCH3_3_PerfMonCtl6__Enable_MASK 0x80000000L
+//UMCCH3_3_PerfMonCtr6_Lo
+#define UMCCH3_3_PerfMonCtr6_Lo__Data__SHIFT 0x0
+#define UMCCH3_3_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_3_PerfMonCtr6_Hi
+#define UMCCH3_3_PerfMonCtr6_Hi__Data__SHIFT 0x0
+#define UMCCH3_3_PerfMonCtr6_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_3_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH3_3_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH3_3_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_3_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L
+#define UMCCH3_3_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH3_3_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH3_3_PerfMonCtl7
+#define UMCCH3_3_PerfMonCtl7__EventSelect__SHIFT 0x0
+#define UMCCH3_3_PerfMonCtl7__RdWrMask__SHIFT 0x8
+#define UMCCH3_3_PerfMonCtl7__PriorityMask__SHIFT 0xa
+#define UMCCH3_3_PerfMonCtl7__ReqSizeMask__SHIFT 0xe
+#define UMCCH3_3_PerfMonCtl7__BankSel__SHIFT 0x10
+#define UMCCH3_3_PerfMonCtl7__VCSel__SHIFT 0x18
+#define UMCCH3_3_PerfMonCtl7__SubChanMask__SHIFT 0x1d
+#define UMCCH3_3_PerfMonCtl7__Enable__SHIFT 0x1f
+#define UMCCH3_3_PerfMonCtl7__EventSelect_MASK 0x000000FFL
+#define UMCCH3_3_PerfMonCtl7__RdWrMask_MASK 0x00000300L
+#define UMCCH3_3_PerfMonCtl7__PriorityMask_MASK 0x00003C00L
+#define UMCCH3_3_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH3_3_PerfMonCtl7__BankSel_MASK 0x00FF0000L
+#define UMCCH3_3_PerfMonCtl7__VCSel_MASK 0x1F000000L
+#define UMCCH3_3_PerfMonCtl7__SubChanMask_MASK 0x60000000L
+#define UMCCH3_3_PerfMonCtl7__Enable_MASK 0x80000000L
+//UMCCH3_3_PerfMonCtr7_Lo
+#define UMCCH3_3_PerfMonCtr7_Lo__Data__SHIFT 0x0
+#define UMCCH3_3_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_3_PerfMonCtr7_Hi
+#define UMCCH3_3_PerfMonCtr7_Hi__Data__SHIFT 0x0
+#define UMCCH3_3_PerfMonCtr7_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_3_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH3_3_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH3_3_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_3_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L
+#define UMCCH3_3_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH3_3_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH3_3_PerfMonCtl8
+#define UMCCH3_3_PerfMonCtl8__EventSelect__SHIFT 0x0
+#define UMCCH3_3_PerfMonCtl8__RdWrMask__SHIFT 0x8
+#define UMCCH3_3_PerfMonCtl8__PriorityMask__SHIFT 0xa
+#define UMCCH3_3_PerfMonCtl8__ReqSizeMask__SHIFT 0xe
+#define UMCCH3_3_PerfMonCtl8__BankSel__SHIFT 0x10
+#define UMCCH3_3_PerfMonCtl8__VCSel__SHIFT 0x18
+#define UMCCH3_3_PerfMonCtl8__SubChanMask__SHIFT 0x1d
+#define UMCCH3_3_PerfMonCtl8__Enable__SHIFT 0x1f
+#define UMCCH3_3_PerfMonCtl8__EventSelect_MASK 0x000000FFL
+#define UMCCH3_3_PerfMonCtl8__RdWrMask_MASK 0x00000300L
+#define UMCCH3_3_PerfMonCtl8__PriorityMask_MASK 0x00003C00L
+#define UMCCH3_3_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH3_3_PerfMonCtl8__BankSel_MASK 0x00FF0000L
+#define UMCCH3_3_PerfMonCtl8__VCSel_MASK 0x1F000000L
+#define UMCCH3_3_PerfMonCtl8__SubChanMask_MASK 0x60000000L
+#define UMCCH3_3_PerfMonCtl8__Enable_MASK 0x80000000L
+//UMCCH3_3_PerfMonCtr8_Lo
+#define UMCCH3_3_PerfMonCtr8_Lo__Data__SHIFT 0x0
+#define UMCCH3_3_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH3_3_PerfMonCtr8_Hi
+#define UMCCH3_3_PerfMonCtr8_Hi__Data__SHIFT 0x0
+#define UMCCH3_3_PerfMonCtr8_Hi__Overflow__SHIFT 0x10
+#define UMCCH3_3_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH3_3_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH3_3_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH3_3_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L
+#define UMCCH3_3_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH3_3_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L
+
+
+// addressBlock: umc_w_phy_umc3_umcch4_umcchdec
+//UMCCH4_3_BaseAddrCS0
+#define UMCCH4_3_BaseAddrCS0__CSEnable__SHIFT 0x0
+#define UMCCH4_3_BaseAddrCS0__BaseAddr__SHIFT 0x1
+#define UMCCH4_3_BaseAddrCS0__CSEnable_MASK 0x00000001L
+#define UMCCH4_3_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL
+//UMCCH4_3_AddrMaskCS01
+#define UMCCH4_3_AddrMaskCS01__AddrMask__SHIFT 0x1
+#define UMCCH4_3_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL
+//UMCCH4_3_AddrSelCS01
+#define UMCCH4_3_AddrSelCS01__BankBit0__SHIFT 0x0
+#define UMCCH4_3_AddrSelCS01__BankBit1__SHIFT 0x4
+#define UMCCH4_3_AddrSelCS01__BankBit2__SHIFT 0x8
+#define UMCCH4_3_AddrSelCS01__BankBit3__SHIFT 0xc
+#define UMCCH4_3_AddrSelCS01__BankBit4__SHIFT 0x10
+#define UMCCH4_3_AddrSelCS01__RowLo__SHIFT 0x18
+#define UMCCH4_3_AddrSelCS01__RowHi__SHIFT 0x1c
+#define UMCCH4_3_AddrSelCS01__BankBit0_MASK 0x0000000FL
+#define UMCCH4_3_AddrSelCS01__BankBit1_MASK 0x000000F0L
+#define UMCCH4_3_AddrSelCS01__BankBit2_MASK 0x00000F00L
+#define UMCCH4_3_AddrSelCS01__BankBit3_MASK 0x0000F000L
+#define UMCCH4_3_AddrSelCS01__BankBit4_MASK 0x001F0000L
+#define UMCCH4_3_AddrSelCS01__RowLo_MASK 0x0F000000L
+#define UMCCH4_3_AddrSelCS01__RowHi_MASK 0xF0000000L
+//UMCCH4_3_AddrHashBank0
+#define UMCCH4_3_AddrHashBank0__XorEnable__SHIFT 0x0
+#define UMCCH4_3_AddrHashBank0__ColXor__SHIFT 0x1
+#define UMCCH4_3_AddrHashBank0__RowXor__SHIFT 0xe
+#define UMCCH4_3_AddrHashBank0__XorEnable_MASK 0x00000001L
+#define UMCCH4_3_AddrHashBank0__ColXor_MASK 0x00003FFEL
+#define UMCCH4_3_AddrHashBank0__RowXor_MASK 0xFFFFC000L
+//UMCCH4_3_AddrHashBank1
+#define UMCCH4_3_AddrHashBank1__XorEnable__SHIFT 0x0
+#define UMCCH4_3_AddrHashBank1__ColXor__SHIFT 0x1
+#define UMCCH4_3_AddrHashBank1__RowXor__SHIFT 0xe
+#define UMCCH4_3_AddrHashBank1__XorEnable_MASK 0x00000001L
+#define UMCCH4_3_AddrHashBank1__ColXor_MASK 0x00003FFEL
+#define UMCCH4_3_AddrHashBank1__RowXor_MASK 0xFFFFC000L
+//UMCCH4_3_AddrHashBank2
+#define UMCCH4_3_AddrHashBank2__XorEnable__SHIFT 0x0
+#define UMCCH4_3_AddrHashBank2__ColXor__SHIFT 0x1
+#define UMCCH4_3_AddrHashBank2__RowXor__SHIFT 0xe
+#define UMCCH4_3_AddrHashBank2__XorEnable_MASK 0x00000001L
+#define UMCCH4_3_AddrHashBank2__ColXor_MASK 0x00003FFEL
+#define UMCCH4_3_AddrHashBank2__RowXor_MASK 0xFFFFC000L
+//UMCCH4_3_AddrHashBank3
+#define UMCCH4_3_AddrHashBank3__XorEnable__SHIFT 0x0
+#define UMCCH4_3_AddrHashBank3__ColXor__SHIFT 0x1
+#define UMCCH4_3_AddrHashBank3__RowXor__SHIFT 0xe
+#define UMCCH4_3_AddrHashBank3__XorEnable_MASK 0x00000001L
+#define UMCCH4_3_AddrHashBank3__ColXor_MASK 0x00003FFEL
+#define UMCCH4_3_AddrHashBank3__RowXor_MASK 0xFFFFC000L
+//UMCCH4_3_AddrHashBank4
+#define UMCCH4_3_AddrHashBank4__XorEnable__SHIFT 0x0
+#define UMCCH4_3_AddrHashBank4__ColXor__SHIFT 0x1
+#define UMCCH4_3_AddrHashBank4__RowXor__SHIFT 0xe
+#define UMCCH4_3_AddrHashBank4__XorEnable_MASK 0x00000001L
+#define UMCCH4_3_AddrHashBank4__ColXor_MASK 0x00003FFEL
+#define UMCCH4_3_AddrHashBank4__RowXor_MASK 0xFFFFC000L
+//UMCCH4_3_AddrHashBank5
+#define UMCCH4_3_AddrHashBank5__XorEnable__SHIFT 0x0
+#define UMCCH4_3_AddrHashBank5__ColXor__SHIFT 0x1
+#define UMCCH4_3_AddrHashBank5__RowXor__SHIFT 0xe
+#define UMCCH4_3_AddrHashBank5__XorEnable_MASK 0x00000001L
+#define UMCCH4_3_AddrHashBank5__ColXor_MASK 0x00003FFEL
+#define UMCCH4_3_AddrHashBank5__RowXor_MASK 0xFFFFC000L
+//UMCCH4_3_EccErrCntSel
+#define UMCCH4_3_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0
+#define UMCCH4_3_EccErrCntSel__EccErrInt__SHIFT 0xc
+#define UMCCH4_3_EccErrCntSel__EccErrCntEn__SHIFT 0xf
+#define UMCCH4_3_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL
+#define UMCCH4_3_EccErrCntSel__EccErrInt_MASK 0x00003000L
+#define UMCCH4_3_EccErrCntSel__EccErrCntEn_MASK 0x00008000L
+//UMCCH4_3_EccErrCnt
+#define UMCCH4_3_EccErrCnt__EccErrCnt__SHIFT 0x0
+#define UMCCH4_3_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL
+//UMCCH4_3_PerfMonCtlClk
+#define UMCCH4_3_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0
+#define UMCCH4_3_PerfMonCtlClk__ClkGate__SHIFT 0x16
+#define UMCCH4_3_PerfMonCtlClk__GlblReset__SHIFT 0x18
+#define UMCCH4_3_PerfMonCtlClk__GlblMonEn__SHIFT 0x19
+#define UMCCH4_3_PerfMonCtlClk__NumCounters__SHIFT 0x1a
+#define UMCCH4_3_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f
+#define UMCCH4_3_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL
+#define UMCCH4_3_PerfMonCtlClk__ClkGate_MASK 0x00400000L
+#define UMCCH4_3_PerfMonCtlClk__GlblReset_MASK 0x01000000L
+#define UMCCH4_3_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L
+#define UMCCH4_3_PerfMonCtlClk__NumCounters_MASK 0x3C000000L
+#define UMCCH4_3_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L
+//UMCCH4_3_PerfMonCtrClk_Lo
+#define UMCCH4_3_PerfMonCtrClk_Lo__Data__SHIFT 0x0
+#define UMCCH4_3_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_3_PerfMonCtrClk_Hi
+#define UMCCH4_3_PerfMonCtrClk_Hi__Data__SHIFT 0x0
+#define UMCCH4_3_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_3_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_3_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L
+//UMCCH4_3_PerfMonCtl1
+#define UMCCH4_3_PerfMonCtl1__EventSelect__SHIFT 0x0
+#define UMCCH4_3_PerfMonCtl1__RdWrMask__SHIFT 0x8
+#define UMCCH4_3_PerfMonCtl1__PriorityMask__SHIFT 0xa
+#define UMCCH4_3_PerfMonCtl1__ReqSizeMask__SHIFT 0xe
+#define UMCCH4_3_PerfMonCtl1__BankSel__SHIFT 0x10
+#define UMCCH4_3_PerfMonCtl1__VCSel__SHIFT 0x18
+#define UMCCH4_3_PerfMonCtl1__SubChanMask__SHIFT 0x1d
+#define UMCCH4_3_PerfMonCtl1__Enable__SHIFT 0x1f
+#define UMCCH4_3_PerfMonCtl1__EventSelect_MASK 0x000000FFL
+#define UMCCH4_3_PerfMonCtl1__RdWrMask_MASK 0x00000300L
+#define UMCCH4_3_PerfMonCtl1__PriorityMask_MASK 0x00003C00L
+#define UMCCH4_3_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH4_3_PerfMonCtl1__BankSel_MASK 0x00FF0000L
+#define UMCCH4_3_PerfMonCtl1__VCSel_MASK 0x1F000000L
+#define UMCCH4_3_PerfMonCtl1__SubChanMask_MASK 0x60000000L
+#define UMCCH4_3_PerfMonCtl1__Enable_MASK 0x80000000L
+//UMCCH4_3_PerfMonCtr1_Lo
+#define UMCCH4_3_PerfMonCtr1_Lo__Data__SHIFT 0x0
+#define UMCCH4_3_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_3_PerfMonCtr1_Hi
+#define UMCCH4_3_PerfMonCtr1_Hi__Data__SHIFT 0x0
+#define UMCCH4_3_PerfMonCtr1_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_3_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH4_3_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH4_3_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_3_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L
+#define UMCCH4_3_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH4_3_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH4_3_PerfMonCtl2
+#define UMCCH4_3_PerfMonCtl2__EventSelect__SHIFT 0x0
+#define UMCCH4_3_PerfMonCtl2__RdWrMask__SHIFT 0x8
+#define UMCCH4_3_PerfMonCtl2__PriorityMask__SHIFT 0xa
+#define UMCCH4_3_PerfMonCtl2__ReqSizeMask__SHIFT 0xe
+#define UMCCH4_3_PerfMonCtl2__BankSel__SHIFT 0x10
+#define UMCCH4_3_PerfMonCtl2__VCSel__SHIFT 0x18
+#define UMCCH4_3_PerfMonCtl2__SubChanMask__SHIFT 0x1d
+#define UMCCH4_3_PerfMonCtl2__Enable__SHIFT 0x1f
+#define UMCCH4_3_PerfMonCtl2__EventSelect_MASK 0x000000FFL
+#define UMCCH4_3_PerfMonCtl2__RdWrMask_MASK 0x00000300L
+#define UMCCH4_3_PerfMonCtl2__PriorityMask_MASK 0x00003C00L
+#define UMCCH4_3_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH4_3_PerfMonCtl2__BankSel_MASK 0x00FF0000L
+#define UMCCH4_3_PerfMonCtl2__VCSel_MASK 0x1F000000L
+#define UMCCH4_3_PerfMonCtl2__SubChanMask_MASK 0x60000000L
+#define UMCCH4_3_PerfMonCtl2__Enable_MASK 0x80000000L
+//UMCCH4_3_PerfMonCtr2_Lo
+#define UMCCH4_3_PerfMonCtr2_Lo__Data__SHIFT 0x0
+#define UMCCH4_3_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_3_PerfMonCtr2_Hi
+#define UMCCH4_3_PerfMonCtr2_Hi__Data__SHIFT 0x0
+#define UMCCH4_3_PerfMonCtr2_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_3_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH4_3_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH4_3_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_3_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L
+#define UMCCH4_3_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH4_3_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH4_3_PerfMonCtl3
+#define UMCCH4_3_PerfMonCtl3__EventSelect__SHIFT 0x0
+#define UMCCH4_3_PerfMonCtl3__RdWrMask__SHIFT 0x8
+#define UMCCH4_3_PerfMonCtl3__PriorityMask__SHIFT 0xa
+#define UMCCH4_3_PerfMonCtl3__ReqSizeMask__SHIFT 0xe
+#define UMCCH4_3_PerfMonCtl3__BankSel__SHIFT 0x10
+#define UMCCH4_3_PerfMonCtl3__VCSel__SHIFT 0x18
+#define UMCCH4_3_PerfMonCtl3__SubChanMask__SHIFT 0x1d
+#define UMCCH4_3_PerfMonCtl3__Enable__SHIFT 0x1f
+#define UMCCH4_3_PerfMonCtl3__EventSelect_MASK 0x000000FFL
+#define UMCCH4_3_PerfMonCtl3__RdWrMask_MASK 0x00000300L
+#define UMCCH4_3_PerfMonCtl3__PriorityMask_MASK 0x00003C00L
+#define UMCCH4_3_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH4_3_PerfMonCtl3__BankSel_MASK 0x00FF0000L
+#define UMCCH4_3_PerfMonCtl3__VCSel_MASK 0x1F000000L
+#define UMCCH4_3_PerfMonCtl3__SubChanMask_MASK 0x60000000L
+#define UMCCH4_3_PerfMonCtl3__Enable_MASK 0x80000000L
+//UMCCH4_3_PerfMonCtr3_Lo
+#define UMCCH4_3_PerfMonCtr3_Lo__Data__SHIFT 0x0
+#define UMCCH4_3_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_3_PerfMonCtr3_Hi
+#define UMCCH4_3_PerfMonCtr3_Hi__Data__SHIFT 0x0
+#define UMCCH4_3_PerfMonCtr3_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_3_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH4_3_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH4_3_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_3_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L
+#define UMCCH4_3_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH4_3_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH4_3_PerfMonCtl4
+#define UMCCH4_3_PerfMonCtl4__EventSelect__SHIFT 0x0
+#define UMCCH4_3_PerfMonCtl4__RdWrMask__SHIFT 0x8
+#define UMCCH4_3_PerfMonCtl4__PriorityMask__SHIFT 0xa
+#define UMCCH4_3_PerfMonCtl4__ReqSizeMask__SHIFT 0xe
+#define UMCCH4_3_PerfMonCtl4__BankSel__SHIFT 0x10
+#define UMCCH4_3_PerfMonCtl4__VCSel__SHIFT 0x18
+#define UMCCH4_3_PerfMonCtl4__SubChanMask__SHIFT 0x1d
+#define UMCCH4_3_PerfMonCtl4__Enable__SHIFT 0x1f
+#define UMCCH4_3_PerfMonCtl4__EventSelect_MASK 0x000000FFL
+#define UMCCH4_3_PerfMonCtl4__RdWrMask_MASK 0x00000300L
+#define UMCCH4_3_PerfMonCtl4__PriorityMask_MASK 0x00003C00L
+#define UMCCH4_3_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH4_3_PerfMonCtl4__BankSel_MASK 0x00FF0000L
+#define UMCCH4_3_PerfMonCtl4__VCSel_MASK 0x1F000000L
+#define UMCCH4_3_PerfMonCtl4__SubChanMask_MASK 0x60000000L
+#define UMCCH4_3_PerfMonCtl4__Enable_MASK 0x80000000L
+//UMCCH4_3_PerfMonCtr4_Lo
+#define UMCCH4_3_PerfMonCtr4_Lo__Data__SHIFT 0x0
+#define UMCCH4_3_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_3_PerfMonCtr4_Hi
+#define UMCCH4_3_PerfMonCtr4_Hi__Data__SHIFT 0x0
+#define UMCCH4_3_PerfMonCtr4_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_3_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH4_3_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH4_3_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_3_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L
+#define UMCCH4_3_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH4_3_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH4_3_PerfMonCtl5
+#define UMCCH4_3_PerfMonCtl5__EventSelect__SHIFT 0x0
+#define UMCCH4_3_PerfMonCtl5__RdWrMask__SHIFT 0x8
+#define UMCCH4_3_PerfMonCtl5__PriorityMask__SHIFT 0xa
+#define UMCCH4_3_PerfMonCtl5__ReqSizeMask__SHIFT 0xe
+#define UMCCH4_3_PerfMonCtl5__BankSel__SHIFT 0x10
+#define UMCCH4_3_PerfMonCtl5__VCSel__SHIFT 0x18
+#define UMCCH4_3_PerfMonCtl5__SubChanMask__SHIFT 0x1d
+#define UMCCH4_3_PerfMonCtl5__Enable__SHIFT 0x1f
+#define UMCCH4_3_PerfMonCtl5__EventSelect_MASK 0x000000FFL
+#define UMCCH4_3_PerfMonCtl5__RdWrMask_MASK 0x00000300L
+#define UMCCH4_3_PerfMonCtl5__PriorityMask_MASK 0x00003C00L
+#define UMCCH4_3_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH4_3_PerfMonCtl5__BankSel_MASK 0x00FF0000L
+#define UMCCH4_3_PerfMonCtl5__VCSel_MASK 0x1F000000L
+#define UMCCH4_3_PerfMonCtl5__SubChanMask_MASK 0x60000000L
+#define UMCCH4_3_PerfMonCtl5__Enable_MASK 0x80000000L
+//UMCCH4_3_PerfMonCtr5_Lo
+#define UMCCH4_3_PerfMonCtr5_Lo__Data__SHIFT 0x0
+#define UMCCH4_3_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_3_PerfMonCtr5_Hi
+#define UMCCH4_3_PerfMonCtr5_Hi__Data__SHIFT 0x0
+#define UMCCH4_3_PerfMonCtr5_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_3_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH4_3_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH4_3_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_3_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L
+#define UMCCH4_3_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH4_3_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH4_3_PerfMonCtl6
+#define UMCCH4_3_PerfMonCtl6__EventSelect__SHIFT 0x0
+#define UMCCH4_3_PerfMonCtl6__RdWrMask__SHIFT 0x8
+#define UMCCH4_3_PerfMonCtl6__PriorityMask__SHIFT 0xa
+#define UMCCH4_3_PerfMonCtl6__ReqSizeMask__SHIFT 0xe
+#define UMCCH4_3_PerfMonCtl6__BankSel__SHIFT 0x10
+#define UMCCH4_3_PerfMonCtl6__VCSel__SHIFT 0x18
+#define UMCCH4_3_PerfMonCtl6__SubChanMask__SHIFT 0x1d
+#define UMCCH4_3_PerfMonCtl6__Enable__SHIFT 0x1f
+#define UMCCH4_3_PerfMonCtl6__EventSelect_MASK 0x000000FFL
+#define UMCCH4_3_PerfMonCtl6__RdWrMask_MASK 0x00000300L
+#define UMCCH4_3_PerfMonCtl6__PriorityMask_MASK 0x00003C00L
+#define UMCCH4_3_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH4_3_PerfMonCtl6__BankSel_MASK 0x00FF0000L
+#define UMCCH4_3_PerfMonCtl6__VCSel_MASK 0x1F000000L
+#define UMCCH4_3_PerfMonCtl6__SubChanMask_MASK 0x60000000L
+#define UMCCH4_3_PerfMonCtl6__Enable_MASK 0x80000000L
+//UMCCH4_3_PerfMonCtr6_Lo
+#define UMCCH4_3_PerfMonCtr6_Lo__Data__SHIFT 0x0
+#define UMCCH4_3_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_3_PerfMonCtr6_Hi
+#define UMCCH4_3_PerfMonCtr6_Hi__Data__SHIFT 0x0
+#define UMCCH4_3_PerfMonCtr6_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_3_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH4_3_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH4_3_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_3_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L
+#define UMCCH4_3_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH4_3_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH4_3_PerfMonCtl7
+#define UMCCH4_3_PerfMonCtl7__EventSelect__SHIFT 0x0
+#define UMCCH4_3_PerfMonCtl7__RdWrMask__SHIFT 0x8
+#define UMCCH4_3_PerfMonCtl7__PriorityMask__SHIFT 0xa
+#define UMCCH4_3_PerfMonCtl7__ReqSizeMask__SHIFT 0xe
+#define UMCCH4_3_PerfMonCtl7__BankSel__SHIFT 0x10
+#define UMCCH4_3_PerfMonCtl7__VCSel__SHIFT 0x18
+#define UMCCH4_3_PerfMonCtl7__SubChanMask__SHIFT 0x1d
+#define UMCCH4_3_PerfMonCtl7__Enable__SHIFT 0x1f
+#define UMCCH4_3_PerfMonCtl7__EventSelect_MASK 0x000000FFL
+#define UMCCH4_3_PerfMonCtl7__RdWrMask_MASK 0x00000300L
+#define UMCCH4_3_PerfMonCtl7__PriorityMask_MASK 0x00003C00L
+#define UMCCH4_3_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH4_3_PerfMonCtl7__BankSel_MASK 0x00FF0000L
+#define UMCCH4_3_PerfMonCtl7__VCSel_MASK 0x1F000000L
+#define UMCCH4_3_PerfMonCtl7__SubChanMask_MASK 0x60000000L
+#define UMCCH4_3_PerfMonCtl7__Enable_MASK 0x80000000L
+//UMCCH4_3_PerfMonCtr7_Lo
+#define UMCCH4_3_PerfMonCtr7_Lo__Data__SHIFT 0x0
+#define UMCCH4_3_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_3_PerfMonCtr7_Hi
+#define UMCCH4_3_PerfMonCtr7_Hi__Data__SHIFT 0x0
+#define UMCCH4_3_PerfMonCtr7_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_3_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH4_3_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH4_3_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_3_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L
+#define UMCCH4_3_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH4_3_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH4_3_PerfMonCtl8
+#define UMCCH4_3_PerfMonCtl8__EventSelect__SHIFT 0x0
+#define UMCCH4_3_PerfMonCtl8__RdWrMask__SHIFT 0x8
+#define UMCCH4_3_PerfMonCtl8__PriorityMask__SHIFT 0xa
+#define UMCCH4_3_PerfMonCtl8__ReqSizeMask__SHIFT 0xe
+#define UMCCH4_3_PerfMonCtl8__BankSel__SHIFT 0x10
+#define UMCCH4_3_PerfMonCtl8__VCSel__SHIFT 0x18
+#define UMCCH4_3_PerfMonCtl8__SubChanMask__SHIFT 0x1d
+#define UMCCH4_3_PerfMonCtl8__Enable__SHIFT 0x1f
+#define UMCCH4_3_PerfMonCtl8__EventSelect_MASK 0x000000FFL
+#define UMCCH4_3_PerfMonCtl8__RdWrMask_MASK 0x00000300L
+#define UMCCH4_3_PerfMonCtl8__PriorityMask_MASK 0x00003C00L
+#define UMCCH4_3_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH4_3_PerfMonCtl8__BankSel_MASK 0x00FF0000L
+#define UMCCH4_3_PerfMonCtl8__VCSel_MASK 0x1F000000L
+#define UMCCH4_3_PerfMonCtl8__SubChanMask_MASK 0x60000000L
+#define UMCCH4_3_PerfMonCtl8__Enable_MASK 0x80000000L
+//UMCCH4_3_PerfMonCtr8_Lo
+#define UMCCH4_3_PerfMonCtr8_Lo__Data__SHIFT 0x0
+#define UMCCH4_3_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH4_3_PerfMonCtr8_Hi
+#define UMCCH4_3_PerfMonCtr8_Hi__Data__SHIFT 0x0
+#define UMCCH4_3_PerfMonCtr8_Hi__Overflow__SHIFT 0x10
+#define UMCCH4_3_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH4_3_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH4_3_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH4_3_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L
+#define UMCCH4_3_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH4_3_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L
+
+
+// addressBlock: umc_w_phy_umc3_umcch5_umcchdec
+//UMCCH5_3_BaseAddrCS0
+#define UMCCH5_3_BaseAddrCS0__CSEnable__SHIFT 0x0
+#define UMCCH5_3_BaseAddrCS0__BaseAddr__SHIFT 0x1
+#define UMCCH5_3_BaseAddrCS0__CSEnable_MASK 0x00000001L
+#define UMCCH5_3_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL
+//UMCCH5_3_AddrMaskCS01
+#define UMCCH5_3_AddrMaskCS01__AddrMask__SHIFT 0x1
+#define UMCCH5_3_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL
+//UMCCH5_3_AddrSelCS01
+#define UMCCH5_3_AddrSelCS01__BankBit0__SHIFT 0x0
+#define UMCCH5_3_AddrSelCS01__BankBit1__SHIFT 0x4
+#define UMCCH5_3_AddrSelCS01__BankBit2__SHIFT 0x8
+#define UMCCH5_3_AddrSelCS01__BankBit3__SHIFT 0xc
+#define UMCCH5_3_AddrSelCS01__BankBit4__SHIFT 0x10
+#define UMCCH5_3_AddrSelCS01__RowLo__SHIFT 0x18
+#define UMCCH5_3_AddrSelCS01__RowHi__SHIFT 0x1c
+#define UMCCH5_3_AddrSelCS01__BankBit0_MASK 0x0000000FL
+#define UMCCH5_3_AddrSelCS01__BankBit1_MASK 0x000000F0L
+#define UMCCH5_3_AddrSelCS01__BankBit2_MASK 0x00000F00L
+#define UMCCH5_3_AddrSelCS01__BankBit3_MASK 0x0000F000L
+#define UMCCH5_3_AddrSelCS01__BankBit4_MASK 0x001F0000L
+#define UMCCH5_3_AddrSelCS01__RowLo_MASK 0x0F000000L
+#define UMCCH5_3_AddrSelCS01__RowHi_MASK 0xF0000000L
+//UMCCH5_3_AddrHashBank0
+#define UMCCH5_3_AddrHashBank0__XorEnable__SHIFT 0x0
+#define UMCCH5_3_AddrHashBank0__ColXor__SHIFT 0x1
+#define UMCCH5_3_AddrHashBank0__RowXor__SHIFT 0xe
+#define UMCCH5_3_AddrHashBank0__XorEnable_MASK 0x00000001L
+#define UMCCH5_3_AddrHashBank0__ColXor_MASK 0x00003FFEL
+#define UMCCH5_3_AddrHashBank0__RowXor_MASK 0xFFFFC000L
+//UMCCH5_3_AddrHashBank1
+#define UMCCH5_3_AddrHashBank1__XorEnable__SHIFT 0x0
+#define UMCCH5_3_AddrHashBank1__ColXor__SHIFT 0x1
+#define UMCCH5_3_AddrHashBank1__RowXor__SHIFT 0xe
+#define UMCCH5_3_AddrHashBank1__XorEnable_MASK 0x00000001L
+#define UMCCH5_3_AddrHashBank1__ColXor_MASK 0x00003FFEL
+#define UMCCH5_3_AddrHashBank1__RowXor_MASK 0xFFFFC000L
+//UMCCH5_3_AddrHashBank2
+#define UMCCH5_3_AddrHashBank2__XorEnable__SHIFT 0x0
+#define UMCCH5_3_AddrHashBank2__ColXor__SHIFT 0x1
+#define UMCCH5_3_AddrHashBank2__RowXor__SHIFT 0xe
+#define UMCCH5_3_AddrHashBank2__XorEnable_MASK 0x00000001L
+#define UMCCH5_3_AddrHashBank2__ColXor_MASK 0x00003FFEL
+#define UMCCH5_3_AddrHashBank2__RowXor_MASK 0xFFFFC000L
+//UMCCH5_3_AddrHashBank3
+#define UMCCH5_3_AddrHashBank3__XorEnable__SHIFT 0x0
+#define UMCCH5_3_AddrHashBank3__ColXor__SHIFT 0x1
+#define UMCCH5_3_AddrHashBank3__RowXor__SHIFT 0xe
+#define UMCCH5_3_AddrHashBank3__XorEnable_MASK 0x00000001L
+#define UMCCH5_3_AddrHashBank3__ColXor_MASK 0x00003FFEL
+#define UMCCH5_3_AddrHashBank3__RowXor_MASK 0xFFFFC000L
+//UMCCH5_3_AddrHashBank4
+#define UMCCH5_3_AddrHashBank4__XorEnable__SHIFT 0x0
+#define UMCCH5_3_AddrHashBank4__ColXor__SHIFT 0x1
+#define UMCCH5_3_AddrHashBank4__RowXor__SHIFT 0xe
+#define UMCCH5_3_AddrHashBank4__XorEnable_MASK 0x00000001L
+#define UMCCH5_3_AddrHashBank4__ColXor_MASK 0x00003FFEL
+#define UMCCH5_3_AddrHashBank4__RowXor_MASK 0xFFFFC000L
+//UMCCH5_3_AddrHashBank5
+#define UMCCH5_3_AddrHashBank5__XorEnable__SHIFT 0x0
+#define UMCCH5_3_AddrHashBank5__ColXor__SHIFT 0x1
+#define UMCCH5_3_AddrHashBank5__RowXor__SHIFT 0xe
+#define UMCCH5_3_AddrHashBank5__XorEnable_MASK 0x00000001L
+#define UMCCH5_3_AddrHashBank5__ColXor_MASK 0x00003FFEL
+#define UMCCH5_3_AddrHashBank5__RowXor_MASK 0xFFFFC000L
+//UMCCH5_3_EccErrCntSel
+#define UMCCH5_3_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0
+#define UMCCH5_3_EccErrCntSel__EccErrInt__SHIFT 0xc
+#define UMCCH5_3_EccErrCntSel__EccErrCntEn__SHIFT 0xf
+#define UMCCH5_3_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL
+#define UMCCH5_3_EccErrCntSel__EccErrInt_MASK 0x00003000L
+#define UMCCH5_3_EccErrCntSel__EccErrCntEn_MASK 0x00008000L
+//UMCCH5_3_EccErrCnt
+#define UMCCH5_3_EccErrCnt__EccErrCnt__SHIFT 0x0
+#define UMCCH5_3_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL
+//UMCCH5_3_PerfMonCtlClk
+#define UMCCH5_3_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0
+#define UMCCH5_3_PerfMonCtlClk__ClkGate__SHIFT 0x16
+#define UMCCH5_3_PerfMonCtlClk__GlblReset__SHIFT 0x18
+#define UMCCH5_3_PerfMonCtlClk__GlblMonEn__SHIFT 0x19
+#define UMCCH5_3_PerfMonCtlClk__NumCounters__SHIFT 0x1a
+#define UMCCH5_3_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f
+#define UMCCH5_3_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL
+#define UMCCH5_3_PerfMonCtlClk__ClkGate_MASK 0x00400000L
+#define UMCCH5_3_PerfMonCtlClk__GlblReset_MASK 0x01000000L
+#define UMCCH5_3_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L
+#define UMCCH5_3_PerfMonCtlClk__NumCounters_MASK 0x3C000000L
+#define UMCCH5_3_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L
+//UMCCH5_3_PerfMonCtrClk_Lo
+#define UMCCH5_3_PerfMonCtrClk_Lo__Data__SHIFT 0x0
+#define UMCCH5_3_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_3_PerfMonCtrClk_Hi
+#define UMCCH5_3_PerfMonCtrClk_Hi__Data__SHIFT 0x0
+#define UMCCH5_3_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_3_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_3_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L
+//UMCCH5_3_PerfMonCtl1
+#define UMCCH5_3_PerfMonCtl1__EventSelect__SHIFT 0x0
+#define UMCCH5_3_PerfMonCtl1__RdWrMask__SHIFT 0x8
+#define UMCCH5_3_PerfMonCtl1__PriorityMask__SHIFT 0xa
+#define UMCCH5_3_PerfMonCtl1__ReqSizeMask__SHIFT 0xe
+#define UMCCH5_3_PerfMonCtl1__BankSel__SHIFT 0x10
+#define UMCCH5_3_PerfMonCtl1__VCSel__SHIFT 0x18
+#define UMCCH5_3_PerfMonCtl1__SubChanMask__SHIFT 0x1d
+#define UMCCH5_3_PerfMonCtl1__Enable__SHIFT 0x1f
+#define UMCCH5_3_PerfMonCtl1__EventSelect_MASK 0x000000FFL
+#define UMCCH5_3_PerfMonCtl1__RdWrMask_MASK 0x00000300L
+#define UMCCH5_3_PerfMonCtl1__PriorityMask_MASK 0x00003C00L
+#define UMCCH5_3_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH5_3_PerfMonCtl1__BankSel_MASK 0x00FF0000L
+#define UMCCH5_3_PerfMonCtl1__VCSel_MASK 0x1F000000L
+#define UMCCH5_3_PerfMonCtl1__SubChanMask_MASK 0x60000000L
+#define UMCCH5_3_PerfMonCtl1__Enable_MASK 0x80000000L
+//UMCCH5_3_PerfMonCtr1_Lo
+#define UMCCH5_3_PerfMonCtr1_Lo__Data__SHIFT 0x0
+#define UMCCH5_3_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_3_PerfMonCtr1_Hi
+#define UMCCH5_3_PerfMonCtr1_Hi__Data__SHIFT 0x0
+#define UMCCH5_3_PerfMonCtr1_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_3_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH5_3_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH5_3_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_3_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L
+#define UMCCH5_3_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH5_3_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH5_3_PerfMonCtl2
+#define UMCCH5_3_PerfMonCtl2__EventSelect__SHIFT 0x0
+#define UMCCH5_3_PerfMonCtl2__RdWrMask__SHIFT 0x8
+#define UMCCH5_3_PerfMonCtl2__PriorityMask__SHIFT 0xa
+#define UMCCH5_3_PerfMonCtl2__ReqSizeMask__SHIFT 0xe
+#define UMCCH5_3_PerfMonCtl2__BankSel__SHIFT 0x10
+#define UMCCH5_3_PerfMonCtl2__VCSel__SHIFT 0x18
+#define UMCCH5_3_PerfMonCtl2__SubChanMask__SHIFT 0x1d
+#define UMCCH5_3_PerfMonCtl2__Enable__SHIFT 0x1f
+#define UMCCH5_3_PerfMonCtl2__EventSelect_MASK 0x000000FFL
+#define UMCCH5_3_PerfMonCtl2__RdWrMask_MASK 0x00000300L
+#define UMCCH5_3_PerfMonCtl2__PriorityMask_MASK 0x00003C00L
+#define UMCCH5_3_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH5_3_PerfMonCtl2__BankSel_MASK 0x00FF0000L
+#define UMCCH5_3_PerfMonCtl2__VCSel_MASK 0x1F000000L
+#define UMCCH5_3_PerfMonCtl2__SubChanMask_MASK 0x60000000L
+#define UMCCH5_3_PerfMonCtl2__Enable_MASK 0x80000000L
+//UMCCH5_3_PerfMonCtr2_Lo
+#define UMCCH5_3_PerfMonCtr2_Lo__Data__SHIFT 0x0
+#define UMCCH5_3_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_3_PerfMonCtr2_Hi
+#define UMCCH5_3_PerfMonCtr2_Hi__Data__SHIFT 0x0
+#define UMCCH5_3_PerfMonCtr2_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_3_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH5_3_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH5_3_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_3_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L
+#define UMCCH5_3_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH5_3_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH5_3_PerfMonCtl3
+#define UMCCH5_3_PerfMonCtl3__EventSelect__SHIFT 0x0
+#define UMCCH5_3_PerfMonCtl3__RdWrMask__SHIFT 0x8
+#define UMCCH5_3_PerfMonCtl3__PriorityMask__SHIFT 0xa
+#define UMCCH5_3_PerfMonCtl3__ReqSizeMask__SHIFT 0xe
+#define UMCCH5_3_PerfMonCtl3__BankSel__SHIFT 0x10
+#define UMCCH5_3_PerfMonCtl3__VCSel__SHIFT 0x18
+#define UMCCH5_3_PerfMonCtl3__SubChanMask__SHIFT 0x1d
+#define UMCCH5_3_PerfMonCtl3__Enable__SHIFT 0x1f
+#define UMCCH5_3_PerfMonCtl3__EventSelect_MASK 0x000000FFL
+#define UMCCH5_3_PerfMonCtl3__RdWrMask_MASK 0x00000300L
+#define UMCCH5_3_PerfMonCtl3__PriorityMask_MASK 0x00003C00L
+#define UMCCH5_3_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH5_3_PerfMonCtl3__BankSel_MASK 0x00FF0000L
+#define UMCCH5_3_PerfMonCtl3__VCSel_MASK 0x1F000000L
+#define UMCCH5_3_PerfMonCtl3__SubChanMask_MASK 0x60000000L
+#define UMCCH5_3_PerfMonCtl3__Enable_MASK 0x80000000L
+//UMCCH5_3_PerfMonCtr3_Lo
+#define UMCCH5_3_PerfMonCtr3_Lo__Data__SHIFT 0x0
+#define UMCCH5_3_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_3_PerfMonCtr3_Hi
+#define UMCCH5_3_PerfMonCtr3_Hi__Data__SHIFT 0x0
+#define UMCCH5_3_PerfMonCtr3_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_3_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH5_3_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH5_3_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_3_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L
+#define UMCCH5_3_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH5_3_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH5_3_PerfMonCtl4
+#define UMCCH5_3_PerfMonCtl4__EventSelect__SHIFT 0x0
+#define UMCCH5_3_PerfMonCtl4__RdWrMask__SHIFT 0x8
+#define UMCCH5_3_PerfMonCtl4__PriorityMask__SHIFT 0xa
+#define UMCCH5_3_PerfMonCtl4__ReqSizeMask__SHIFT 0xe
+#define UMCCH5_3_PerfMonCtl4__BankSel__SHIFT 0x10
+#define UMCCH5_3_PerfMonCtl4__VCSel__SHIFT 0x18
+#define UMCCH5_3_PerfMonCtl4__SubChanMask__SHIFT 0x1d
+#define UMCCH5_3_PerfMonCtl4__Enable__SHIFT 0x1f
+#define UMCCH5_3_PerfMonCtl4__EventSelect_MASK 0x000000FFL
+#define UMCCH5_3_PerfMonCtl4__RdWrMask_MASK 0x00000300L
+#define UMCCH5_3_PerfMonCtl4__PriorityMask_MASK 0x00003C00L
+#define UMCCH5_3_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH5_3_PerfMonCtl4__BankSel_MASK 0x00FF0000L
+#define UMCCH5_3_PerfMonCtl4__VCSel_MASK 0x1F000000L
+#define UMCCH5_3_PerfMonCtl4__SubChanMask_MASK 0x60000000L
+#define UMCCH5_3_PerfMonCtl4__Enable_MASK 0x80000000L
+//UMCCH5_3_PerfMonCtr4_Lo
+#define UMCCH5_3_PerfMonCtr4_Lo__Data__SHIFT 0x0
+#define UMCCH5_3_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_3_PerfMonCtr4_Hi
+#define UMCCH5_3_PerfMonCtr4_Hi__Data__SHIFT 0x0
+#define UMCCH5_3_PerfMonCtr4_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_3_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH5_3_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH5_3_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_3_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L
+#define UMCCH5_3_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH5_3_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH5_3_PerfMonCtl5
+#define UMCCH5_3_PerfMonCtl5__EventSelect__SHIFT 0x0
+#define UMCCH5_3_PerfMonCtl5__RdWrMask__SHIFT 0x8
+#define UMCCH5_3_PerfMonCtl5__PriorityMask__SHIFT 0xa
+#define UMCCH5_3_PerfMonCtl5__ReqSizeMask__SHIFT 0xe
+#define UMCCH5_3_PerfMonCtl5__BankSel__SHIFT 0x10
+#define UMCCH5_3_PerfMonCtl5__VCSel__SHIFT 0x18
+#define UMCCH5_3_PerfMonCtl5__SubChanMask__SHIFT 0x1d
+#define UMCCH5_3_PerfMonCtl5__Enable__SHIFT 0x1f
+#define UMCCH5_3_PerfMonCtl5__EventSelect_MASK 0x000000FFL
+#define UMCCH5_3_PerfMonCtl5__RdWrMask_MASK 0x00000300L
+#define UMCCH5_3_PerfMonCtl5__PriorityMask_MASK 0x00003C00L
+#define UMCCH5_3_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH5_3_PerfMonCtl5__BankSel_MASK 0x00FF0000L
+#define UMCCH5_3_PerfMonCtl5__VCSel_MASK 0x1F000000L
+#define UMCCH5_3_PerfMonCtl5__SubChanMask_MASK 0x60000000L
+#define UMCCH5_3_PerfMonCtl5__Enable_MASK 0x80000000L
+//UMCCH5_3_PerfMonCtr5_Lo
+#define UMCCH5_3_PerfMonCtr5_Lo__Data__SHIFT 0x0
+#define UMCCH5_3_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_3_PerfMonCtr5_Hi
+#define UMCCH5_3_PerfMonCtr5_Hi__Data__SHIFT 0x0
+#define UMCCH5_3_PerfMonCtr5_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_3_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH5_3_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH5_3_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_3_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L
+#define UMCCH5_3_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH5_3_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH5_3_PerfMonCtl6
+#define UMCCH5_3_PerfMonCtl6__EventSelect__SHIFT 0x0
+#define UMCCH5_3_PerfMonCtl6__RdWrMask__SHIFT 0x8
+#define UMCCH5_3_PerfMonCtl6__PriorityMask__SHIFT 0xa
+#define UMCCH5_3_PerfMonCtl6__ReqSizeMask__SHIFT 0xe
+#define UMCCH5_3_PerfMonCtl6__BankSel__SHIFT 0x10
+#define UMCCH5_3_PerfMonCtl6__VCSel__SHIFT 0x18
+#define UMCCH5_3_PerfMonCtl6__SubChanMask__SHIFT 0x1d
+#define UMCCH5_3_PerfMonCtl6__Enable__SHIFT 0x1f
+#define UMCCH5_3_PerfMonCtl6__EventSelect_MASK 0x000000FFL
+#define UMCCH5_3_PerfMonCtl6__RdWrMask_MASK 0x00000300L
+#define UMCCH5_3_PerfMonCtl6__PriorityMask_MASK 0x00003C00L
+#define UMCCH5_3_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH5_3_PerfMonCtl6__BankSel_MASK 0x00FF0000L
+#define UMCCH5_3_PerfMonCtl6__VCSel_MASK 0x1F000000L
+#define UMCCH5_3_PerfMonCtl6__SubChanMask_MASK 0x60000000L
+#define UMCCH5_3_PerfMonCtl6__Enable_MASK 0x80000000L
+//UMCCH5_3_PerfMonCtr6_Lo
+#define UMCCH5_3_PerfMonCtr6_Lo__Data__SHIFT 0x0
+#define UMCCH5_3_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_3_PerfMonCtr6_Hi
+#define UMCCH5_3_PerfMonCtr6_Hi__Data__SHIFT 0x0
+#define UMCCH5_3_PerfMonCtr6_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_3_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH5_3_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH5_3_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_3_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L
+#define UMCCH5_3_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH5_3_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH5_3_PerfMonCtl7
+#define UMCCH5_3_PerfMonCtl7__EventSelect__SHIFT 0x0
+#define UMCCH5_3_PerfMonCtl7__RdWrMask__SHIFT 0x8
+#define UMCCH5_3_PerfMonCtl7__PriorityMask__SHIFT 0xa
+#define UMCCH5_3_PerfMonCtl7__ReqSizeMask__SHIFT 0xe
+#define UMCCH5_3_PerfMonCtl7__BankSel__SHIFT 0x10
+#define UMCCH5_3_PerfMonCtl7__VCSel__SHIFT 0x18
+#define UMCCH5_3_PerfMonCtl7__SubChanMask__SHIFT 0x1d
+#define UMCCH5_3_PerfMonCtl7__Enable__SHIFT 0x1f
+#define UMCCH5_3_PerfMonCtl7__EventSelect_MASK 0x000000FFL
+#define UMCCH5_3_PerfMonCtl7__RdWrMask_MASK 0x00000300L
+#define UMCCH5_3_PerfMonCtl7__PriorityMask_MASK 0x00003C00L
+#define UMCCH5_3_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH5_3_PerfMonCtl7__BankSel_MASK 0x00FF0000L
+#define UMCCH5_3_PerfMonCtl7__VCSel_MASK 0x1F000000L
+#define UMCCH5_3_PerfMonCtl7__SubChanMask_MASK 0x60000000L
+#define UMCCH5_3_PerfMonCtl7__Enable_MASK 0x80000000L
+//UMCCH5_3_PerfMonCtr7_Lo
+#define UMCCH5_3_PerfMonCtr7_Lo__Data__SHIFT 0x0
+#define UMCCH5_3_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_3_PerfMonCtr7_Hi
+#define UMCCH5_3_PerfMonCtr7_Hi__Data__SHIFT 0x0
+#define UMCCH5_3_PerfMonCtr7_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_3_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH5_3_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH5_3_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_3_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L
+#define UMCCH5_3_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH5_3_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH5_3_PerfMonCtl8
+#define UMCCH5_3_PerfMonCtl8__EventSelect__SHIFT 0x0
+#define UMCCH5_3_PerfMonCtl8__RdWrMask__SHIFT 0x8
+#define UMCCH5_3_PerfMonCtl8__PriorityMask__SHIFT 0xa
+#define UMCCH5_3_PerfMonCtl8__ReqSizeMask__SHIFT 0xe
+#define UMCCH5_3_PerfMonCtl8__BankSel__SHIFT 0x10
+#define UMCCH5_3_PerfMonCtl8__VCSel__SHIFT 0x18
+#define UMCCH5_3_PerfMonCtl8__SubChanMask__SHIFT 0x1d
+#define UMCCH5_3_PerfMonCtl8__Enable__SHIFT 0x1f
+#define UMCCH5_3_PerfMonCtl8__EventSelect_MASK 0x000000FFL
+#define UMCCH5_3_PerfMonCtl8__RdWrMask_MASK 0x00000300L
+#define UMCCH5_3_PerfMonCtl8__PriorityMask_MASK 0x00003C00L
+#define UMCCH5_3_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH5_3_PerfMonCtl8__BankSel_MASK 0x00FF0000L
+#define UMCCH5_3_PerfMonCtl8__VCSel_MASK 0x1F000000L
+#define UMCCH5_3_PerfMonCtl8__SubChanMask_MASK 0x60000000L
+#define UMCCH5_3_PerfMonCtl8__Enable_MASK 0x80000000L
+//UMCCH5_3_PerfMonCtr8_Lo
+#define UMCCH5_3_PerfMonCtr8_Lo__Data__SHIFT 0x0
+#define UMCCH5_3_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH5_3_PerfMonCtr8_Hi
+#define UMCCH5_3_PerfMonCtr8_Hi__Data__SHIFT 0x0
+#define UMCCH5_3_PerfMonCtr8_Hi__Overflow__SHIFT 0x10
+#define UMCCH5_3_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH5_3_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH5_3_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH5_3_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L
+#define UMCCH5_3_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH5_3_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L
+
+
+// addressBlock: umc_w_phy_umc3_umcch6_umcchdec
+//UMCCH6_3_BaseAddrCS0
+#define UMCCH6_3_BaseAddrCS0__CSEnable__SHIFT 0x0
+#define UMCCH6_3_BaseAddrCS0__BaseAddr__SHIFT 0x1
+#define UMCCH6_3_BaseAddrCS0__CSEnable_MASK 0x00000001L
+#define UMCCH6_3_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL
+//UMCCH6_3_AddrMaskCS01
+#define UMCCH6_3_AddrMaskCS01__AddrMask__SHIFT 0x1
+#define UMCCH6_3_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL
+//UMCCH6_3_AddrSelCS01
+#define UMCCH6_3_AddrSelCS01__BankBit0__SHIFT 0x0
+#define UMCCH6_3_AddrSelCS01__BankBit1__SHIFT 0x4
+#define UMCCH6_3_AddrSelCS01__BankBit2__SHIFT 0x8
+#define UMCCH6_3_AddrSelCS01__BankBit3__SHIFT 0xc
+#define UMCCH6_3_AddrSelCS01__BankBit4__SHIFT 0x10
+#define UMCCH6_3_AddrSelCS01__RowLo__SHIFT 0x18
+#define UMCCH6_3_AddrSelCS01__RowHi__SHIFT 0x1c
+#define UMCCH6_3_AddrSelCS01__BankBit0_MASK 0x0000000FL
+#define UMCCH6_3_AddrSelCS01__BankBit1_MASK 0x000000F0L
+#define UMCCH6_3_AddrSelCS01__BankBit2_MASK 0x00000F00L
+#define UMCCH6_3_AddrSelCS01__BankBit3_MASK 0x0000F000L
+#define UMCCH6_3_AddrSelCS01__BankBit4_MASK 0x001F0000L
+#define UMCCH6_3_AddrSelCS01__RowLo_MASK 0x0F000000L
+#define UMCCH6_3_AddrSelCS01__RowHi_MASK 0xF0000000L
+//UMCCH6_3_AddrHashBank0
+#define UMCCH6_3_AddrHashBank0__XorEnable__SHIFT 0x0
+#define UMCCH6_3_AddrHashBank0__ColXor__SHIFT 0x1
+#define UMCCH6_3_AddrHashBank0__RowXor__SHIFT 0xe
+#define UMCCH6_3_AddrHashBank0__XorEnable_MASK 0x00000001L
+#define UMCCH6_3_AddrHashBank0__ColXor_MASK 0x00003FFEL
+#define UMCCH6_3_AddrHashBank0__RowXor_MASK 0xFFFFC000L
+//UMCCH6_3_AddrHashBank1
+#define UMCCH6_3_AddrHashBank1__XorEnable__SHIFT 0x0
+#define UMCCH6_3_AddrHashBank1__ColXor__SHIFT 0x1
+#define UMCCH6_3_AddrHashBank1__RowXor__SHIFT 0xe
+#define UMCCH6_3_AddrHashBank1__XorEnable_MASK 0x00000001L
+#define UMCCH6_3_AddrHashBank1__ColXor_MASK 0x00003FFEL
+#define UMCCH6_3_AddrHashBank1__RowXor_MASK 0xFFFFC000L
+//UMCCH6_3_AddrHashBank2
+#define UMCCH6_3_AddrHashBank2__XorEnable__SHIFT 0x0
+#define UMCCH6_3_AddrHashBank2__ColXor__SHIFT 0x1
+#define UMCCH6_3_AddrHashBank2__RowXor__SHIFT 0xe
+#define UMCCH6_3_AddrHashBank2__XorEnable_MASK 0x00000001L
+#define UMCCH6_3_AddrHashBank2__ColXor_MASK 0x00003FFEL
+#define UMCCH6_3_AddrHashBank2__RowXor_MASK 0xFFFFC000L
+//UMCCH6_3_AddrHashBank3
+#define UMCCH6_3_AddrHashBank3__XorEnable__SHIFT 0x0
+#define UMCCH6_3_AddrHashBank3__ColXor__SHIFT 0x1
+#define UMCCH6_3_AddrHashBank3__RowXor__SHIFT 0xe
+#define UMCCH6_3_AddrHashBank3__XorEnable_MASK 0x00000001L
+#define UMCCH6_3_AddrHashBank3__ColXor_MASK 0x00003FFEL
+#define UMCCH6_3_AddrHashBank3__RowXor_MASK 0xFFFFC000L
+//UMCCH6_3_AddrHashBank4
+#define UMCCH6_3_AddrHashBank4__XorEnable__SHIFT 0x0
+#define UMCCH6_3_AddrHashBank4__ColXor__SHIFT 0x1
+#define UMCCH6_3_AddrHashBank4__RowXor__SHIFT 0xe
+#define UMCCH6_3_AddrHashBank4__XorEnable_MASK 0x00000001L
+#define UMCCH6_3_AddrHashBank4__ColXor_MASK 0x00003FFEL
+#define UMCCH6_3_AddrHashBank4__RowXor_MASK 0xFFFFC000L
+//UMCCH6_3_AddrHashBank5
+#define UMCCH6_3_AddrHashBank5__XorEnable__SHIFT 0x0
+#define UMCCH6_3_AddrHashBank5__ColXor__SHIFT 0x1
+#define UMCCH6_3_AddrHashBank5__RowXor__SHIFT 0xe
+#define UMCCH6_3_AddrHashBank5__XorEnable_MASK 0x00000001L
+#define UMCCH6_3_AddrHashBank5__ColXor_MASK 0x00003FFEL
+#define UMCCH6_3_AddrHashBank5__RowXor_MASK 0xFFFFC000L
+//UMCCH6_3_EccErrCntSel
+#define UMCCH6_3_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0
+#define UMCCH6_3_EccErrCntSel__EccErrInt__SHIFT 0xc
+#define UMCCH6_3_EccErrCntSel__EccErrCntEn__SHIFT 0xf
+#define UMCCH6_3_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL
+#define UMCCH6_3_EccErrCntSel__EccErrInt_MASK 0x00003000L
+#define UMCCH6_3_EccErrCntSel__EccErrCntEn_MASK 0x00008000L
+//UMCCH6_3_EccErrCnt
+#define UMCCH6_3_EccErrCnt__EccErrCnt__SHIFT 0x0
+#define UMCCH6_3_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL
+//UMCCH6_3_PerfMonCtlClk
+#define UMCCH6_3_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0
+#define UMCCH6_3_PerfMonCtlClk__ClkGate__SHIFT 0x16
+#define UMCCH6_3_PerfMonCtlClk__GlblReset__SHIFT 0x18
+#define UMCCH6_3_PerfMonCtlClk__GlblMonEn__SHIFT 0x19
+#define UMCCH6_3_PerfMonCtlClk__NumCounters__SHIFT 0x1a
+#define UMCCH6_3_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f
+#define UMCCH6_3_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL
+#define UMCCH6_3_PerfMonCtlClk__ClkGate_MASK 0x00400000L
+#define UMCCH6_3_PerfMonCtlClk__GlblReset_MASK 0x01000000L
+#define UMCCH6_3_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L
+#define UMCCH6_3_PerfMonCtlClk__NumCounters_MASK 0x3C000000L
+#define UMCCH6_3_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L
+//UMCCH6_3_PerfMonCtrClk_Lo
+#define UMCCH6_3_PerfMonCtrClk_Lo__Data__SHIFT 0x0
+#define UMCCH6_3_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_3_PerfMonCtrClk_Hi
+#define UMCCH6_3_PerfMonCtrClk_Hi__Data__SHIFT 0x0
+#define UMCCH6_3_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_3_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_3_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L
+//UMCCH6_3_PerfMonCtl1
+#define UMCCH6_3_PerfMonCtl1__EventSelect__SHIFT 0x0
+#define UMCCH6_3_PerfMonCtl1__RdWrMask__SHIFT 0x8
+#define UMCCH6_3_PerfMonCtl1__PriorityMask__SHIFT 0xa
+#define UMCCH6_3_PerfMonCtl1__ReqSizeMask__SHIFT 0xe
+#define UMCCH6_3_PerfMonCtl1__BankSel__SHIFT 0x10
+#define UMCCH6_3_PerfMonCtl1__VCSel__SHIFT 0x18
+#define UMCCH6_3_PerfMonCtl1__SubChanMask__SHIFT 0x1d
+#define UMCCH6_3_PerfMonCtl1__Enable__SHIFT 0x1f
+#define UMCCH6_3_PerfMonCtl1__EventSelect_MASK 0x000000FFL
+#define UMCCH6_3_PerfMonCtl1__RdWrMask_MASK 0x00000300L
+#define UMCCH6_3_PerfMonCtl1__PriorityMask_MASK 0x00003C00L
+#define UMCCH6_3_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH6_3_PerfMonCtl1__BankSel_MASK 0x00FF0000L
+#define UMCCH6_3_PerfMonCtl1__VCSel_MASK 0x1F000000L
+#define UMCCH6_3_PerfMonCtl1__SubChanMask_MASK 0x60000000L
+#define UMCCH6_3_PerfMonCtl1__Enable_MASK 0x80000000L
+//UMCCH6_3_PerfMonCtr1_Lo
+#define UMCCH6_3_PerfMonCtr1_Lo__Data__SHIFT 0x0
+#define UMCCH6_3_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_3_PerfMonCtr1_Hi
+#define UMCCH6_3_PerfMonCtr1_Hi__Data__SHIFT 0x0
+#define UMCCH6_3_PerfMonCtr1_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_3_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH6_3_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH6_3_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_3_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L
+#define UMCCH6_3_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH6_3_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH6_3_PerfMonCtl2
+#define UMCCH6_3_PerfMonCtl2__EventSelect__SHIFT 0x0
+#define UMCCH6_3_PerfMonCtl2__RdWrMask__SHIFT 0x8
+#define UMCCH6_3_PerfMonCtl2__PriorityMask__SHIFT 0xa
+#define UMCCH6_3_PerfMonCtl2__ReqSizeMask__SHIFT 0xe
+#define UMCCH6_3_PerfMonCtl2__BankSel__SHIFT 0x10
+#define UMCCH6_3_PerfMonCtl2__VCSel__SHIFT 0x18
+#define UMCCH6_3_PerfMonCtl2__SubChanMask__SHIFT 0x1d
+#define UMCCH6_3_PerfMonCtl2__Enable__SHIFT 0x1f
+#define UMCCH6_3_PerfMonCtl2__EventSelect_MASK 0x000000FFL
+#define UMCCH6_3_PerfMonCtl2__RdWrMask_MASK 0x00000300L
+#define UMCCH6_3_PerfMonCtl2__PriorityMask_MASK 0x00003C00L
+#define UMCCH6_3_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH6_3_PerfMonCtl2__BankSel_MASK 0x00FF0000L
+#define UMCCH6_3_PerfMonCtl2__VCSel_MASK 0x1F000000L
+#define UMCCH6_3_PerfMonCtl2__SubChanMask_MASK 0x60000000L
+#define UMCCH6_3_PerfMonCtl2__Enable_MASK 0x80000000L
+//UMCCH6_3_PerfMonCtr2_Lo
+#define UMCCH6_3_PerfMonCtr2_Lo__Data__SHIFT 0x0
+#define UMCCH6_3_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_3_PerfMonCtr2_Hi
+#define UMCCH6_3_PerfMonCtr2_Hi__Data__SHIFT 0x0
+#define UMCCH6_3_PerfMonCtr2_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_3_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH6_3_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH6_3_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_3_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L
+#define UMCCH6_3_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH6_3_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH6_3_PerfMonCtl3
+#define UMCCH6_3_PerfMonCtl3__EventSelect__SHIFT 0x0
+#define UMCCH6_3_PerfMonCtl3__RdWrMask__SHIFT 0x8
+#define UMCCH6_3_PerfMonCtl3__PriorityMask__SHIFT 0xa
+#define UMCCH6_3_PerfMonCtl3__ReqSizeMask__SHIFT 0xe
+#define UMCCH6_3_PerfMonCtl3__BankSel__SHIFT 0x10
+#define UMCCH6_3_PerfMonCtl3__VCSel__SHIFT 0x18
+#define UMCCH6_3_PerfMonCtl3__SubChanMask__SHIFT 0x1d
+#define UMCCH6_3_PerfMonCtl3__Enable__SHIFT 0x1f
+#define UMCCH6_3_PerfMonCtl3__EventSelect_MASK 0x000000FFL
+#define UMCCH6_3_PerfMonCtl3__RdWrMask_MASK 0x00000300L
+#define UMCCH6_3_PerfMonCtl3__PriorityMask_MASK 0x00003C00L
+#define UMCCH6_3_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH6_3_PerfMonCtl3__BankSel_MASK 0x00FF0000L
+#define UMCCH6_3_PerfMonCtl3__VCSel_MASK 0x1F000000L
+#define UMCCH6_3_PerfMonCtl3__SubChanMask_MASK 0x60000000L
+#define UMCCH6_3_PerfMonCtl3__Enable_MASK 0x80000000L
+//UMCCH6_3_PerfMonCtr3_Lo
+#define UMCCH6_3_PerfMonCtr3_Lo__Data__SHIFT 0x0
+#define UMCCH6_3_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_3_PerfMonCtr3_Hi
+#define UMCCH6_3_PerfMonCtr3_Hi__Data__SHIFT 0x0
+#define UMCCH6_3_PerfMonCtr3_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_3_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH6_3_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH6_3_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_3_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L
+#define UMCCH6_3_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH6_3_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH6_3_PerfMonCtl4
+#define UMCCH6_3_PerfMonCtl4__EventSelect__SHIFT 0x0
+#define UMCCH6_3_PerfMonCtl4__RdWrMask__SHIFT 0x8
+#define UMCCH6_3_PerfMonCtl4__PriorityMask__SHIFT 0xa
+#define UMCCH6_3_PerfMonCtl4__ReqSizeMask__SHIFT 0xe
+#define UMCCH6_3_PerfMonCtl4__BankSel__SHIFT 0x10
+#define UMCCH6_3_PerfMonCtl4__VCSel__SHIFT 0x18
+#define UMCCH6_3_PerfMonCtl4__SubChanMask__SHIFT 0x1d
+#define UMCCH6_3_PerfMonCtl4__Enable__SHIFT 0x1f
+#define UMCCH6_3_PerfMonCtl4__EventSelect_MASK 0x000000FFL
+#define UMCCH6_3_PerfMonCtl4__RdWrMask_MASK 0x00000300L
+#define UMCCH6_3_PerfMonCtl4__PriorityMask_MASK 0x00003C00L
+#define UMCCH6_3_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH6_3_PerfMonCtl4__BankSel_MASK 0x00FF0000L
+#define UMCCH6_3_PerfMonCtl4__VCSel_MASK 0x1F000000L
+#define UMCCH6_3_PerfMonCtl4__SubChanMask_MASK 0x60000000L
+#define UMCCH6_3_PerfMonCtl4__Enable_MASK 0x80000000L
+//UMCCH6_3_PerfMonCtr4_Lo
+#define UMCCH6_3_PerfMonCtr4_Lo__Data__SHIFT 0x0
+#define UMCCH6_3_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_3_PerfMonCtr4_Hi
+#define UMCCH6_3_PerfMonCtr4_Hi__Data__SHIFT 0x0
+#define UMCCH6_3_PerfMonCtr4_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_3_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH6_3_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH6_3_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_3_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L
+#define UMCCH6_3_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH6_3_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH6_3_PerfMonCtl5
+#define UMCCH6_3_PerfMonCtl5__EventSelect__SHIFT 0x0
+#define UMCCH6_3_PerfMonCtl5__RdWrMask__SHIFT 0x8
+#define UMCCH6_3_PerfMonCtl5__PriorityMask__SHIFT 0xa
+#define UMCCH6_3_PerfMonCtl5__ReqSizeMask__SHIFT 0xe
+#define UMCCH6_3_PerfMonCtl5__BankSel__SHIFT 0x10
+#define UMCCH6_3_PerfMonCtl5__VCSel__SHIFT 0x18
+#define UMCCH6_3_PerfMonCtl5__SubChanMask__SHIFT 0x1d
+#define UMCCH6_3_PerfMonCtl5__Enable__SHIFT 0x1f
+#define UMCCH6_3_PerfMonCtl5__EventSelect_MASK 0x000000FFL
+#define UMCCH6_3_PerfMonCtl5__RdWrMask_MASK 0x00000300L
+#define UMCCH6_3_PerfMonCtl5__PriorityMask_MASK 0x00003C00L
+#define UMCCH6_3_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH6_3_PerfMonCtl5__BankSel_MASK 0x00FF0000L
+#define UMCCH6_3_PerfMonCtl5__VCSel_MASK 0x1F000000L
+#define UMCCH6_3_PerfMonCtl5__SubChanMask_MASK 0x60000000L
+#define UMCCH6_3_PerfMonCtl5__Enable_MASK 0x80000000L
+//UMCCH6_3_PerfMonCtr5_Lo
+#define UMCCH6_3_PerfMonCtr5_Lo__Data__SHIFT 0x0
+#define UMCCH6_3_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_3_PerfMonCtr5_Hi
+#define UMCCH6_3_PerfMonCtr5_Hi__Data__SHIFT 0x0
+#define UMCCH6_3_PerfMonCtr5_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_3_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH6_3_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH6_3_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_3_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L
+#define UMCCH6_3_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH6_3_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH6_3_PerfMonCtl6
+#define UMCCH6_3_PerfMonCtl6__EventSelect__SHIFT 0x0
+#define UMCCH6_3_PerfMonCtl6__RdWrMask__SHIFT 0x8
+#define UMCCH6_3_PerfMonCtl6__PriorityMask__SHIFT 0xa
+#define UMCCH6_3_PerfMonCtl6__ReqSizeMask__SHIFT 0xe
+#define UMCCH6_3_PerfMonCtl6__BankSel__SHIFT 0x10
+#define UMCCH6_3_PerfMonCtl6__VCSel__SHIFT 0x18
+#define UMCCH6_3_PerfMonCtl6__SubChanMask__SHIFT 0x1d
+#define UMCCH6_3_PerfMonCtl6__Enable__SHIFT 0x1f
+#define UMCCH6_3_PerfMonCtl6__EventSelect_MASK 0x000000FFL
+#define UMCCH6_3_PerfMonCtl6__RdWrMask_MASK 0x00000300L
+#define UMCCH6_3_PerfMonCtl6__PriorityMask_MASK 0x00003C00L
+#define UMCCH6_3_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH6_3_PerfMonCtl6__BankSel_MASK 0x00FF0000L
+#define UMCCH6_3_PerfMonCtl6__VCSel_MASK 0x1F000000L
+#define UMCCH6_3_PerfMonCtl6__SubChanMask_MASK 0x60000000L
+#define UMCCH6_3_PerfMonCtl6__Enable_MASK 0x80000000L
+//UMCCH6_3_PerfMonCtr6_Lo
+#define UMCCH6_3_PerfMonCtr6_Lo__Data__SHIFT 0x0
+#define UMCCH6_3_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_3_PerfMonCtr6_Hi
+#define UMCCH6_3_PerfMonCtr6_Hi__Data__SHIFT 0x0
+#define UMCCH6_3_PerfMonCtr6_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_3_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH6_3_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH6_3_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_3_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L
+#define UMCCH6_3_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH6_3_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH6_3_PerfMonCtl7
+#define UMCCH6_3_PerfMonCtl7__EventSelect__SHIFT 0x0
+#define UMCCH6_3_PerfMonCtl7__RdWrMask__SHIFT 0x8
+#define UMCCH6_3_PerfMonCtl7__PriorityMask__SHIFT 0xa
+#define UMCCH6_3_PerfMonCtl7__ReqSizeMask__SHIFT 0xe
+#define UMCCH6_3_PerfMonCtl7__BankSel__SHIFT 0x10
+#define UMCCH6_3_PerfMonCtl7__VCSel__SHIFT 0x18
+#define UMCCH6_3_PerfMonCtl7__SubChanMask__SHIFT 0x1d
+#define UMCCH6_3_PerfMonCtl7__Enable__SHIFT 0x1f
+#define UMCCH6_3_PerfMonCtl7__EventSelect_MASK 0x000000FFL
+#define UMCCH6_3_PerfMonCtl7__RdWrMask_MASK 0x00000300L
+#define UMCCH6_3_PerfMonCtl7__PriorityMask_MASK 0x00003C00L
+#define UMCCH6_3_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH6_3_PerfMonCtl7__BankSel_MASK 0x00FF0000L
+#define UMCCH6_3_PerfMonCtl7__VCSel_MASK 0x1F000000L
+#define UMCCH6_3_PerfMonCtl7__SubChanMask_MASK 0x60000000L
+#define UMCCH6_3_PerfMonCtl7__Enable_MASK 0x80000000L
+//UMCCH6_3_PerfMonCtr7_Lo
+#define UMCCH6_3_PerfMonCtr7_Lo__Data__SHIFT 0x0
+#define UMCCH6_3_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_3_PerfMonCtr7_Hi
+#define UMCCH6_3_PerfMonCtr7_Hi__Data__SHIFT 0x0
+#define UMCCH6_3_PerfMonCtr7_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_3_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH6_3_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH6_3_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_3_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L
+#define UMCCH6_3_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH6_3_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH6_3_PerfMonCtl8
+#define UMCCH6_3_PerfMonCtl8__EventSelect__SHIFT 0x0
+#define UMCCH6_3_PerfMonCtl8__RdWrMask__SHIFT 0x8
+#define UMCCH6_3_PerfMonCtl8__PriorityMask__SHIFT 0xa
+#define UMCCH6_3_PerfMonCtl8__ReqSizeMask__SHIFT 0xe
+#define UMCCH6_3_PerfMonCtl8__BankSel__SHIFT 0x10
+#define UMCCH6_3_PerfMonCtl8__VCSel__SHIFT 0x18
+#define UMCCH6_3_PerfMonCtl8__SubChanMask__SHIFT 0x1d
+#define UMCCH6_3_PerfMonCtl8__Enable__SHIFT 0x1f
+#define UMCCH6_3_PerfMonCtl8__EventSelect_MASK 0x000000FFL
+#define UMCCH6_3_PerfMonCtl8__RdWrMask_MASK 0x00000300L
+#define UMCCH6_3_PerfMonCtl8__PriorityMask_MASK 0x00003C00L
+#define UMCCH6_3_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH6_3_PerfMonCtl8__BankSel_MASK 0x00FF0000L
+#define UMCCH6_3_PerfMonCtl8__VCSel_MASK 0x1F000000L
+#define UMCCH6_3_PerfMonCtl8__SubChanMask_MASK 0x60000000L
+#define UMCCH6_3_PerfMonCtl8__Enable_MASK 0x80000000L
+//UMCCH6_3_PerfMonCtr8_Lo
+#define UMCCH6_3_PerfMonCtr8_Lo__Data__SHIFT 0x0
+#define UMCCH6_3_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH6_3_PerfMonCtr8_Hi
+#define UMCCH6_3_PerfMonCtr8_Hi__Data__SHIFT 0x0
+#define UMCCH6_3_PerfMonCtr8_Hi__Overflow__SHIFT 0x10
+#define UMCCH6_3_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH6_3_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH6_3_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH6_3_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L
+#define UMCCH6_3_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH6_3_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L
+
+
+// addressBlock: umc_w_phy_umc3_umcch7_umcchdec
+//UMCCH7_3_BaseAddrCS0
+#define UMCCH7_3_BaseAddrCS0__CSEnable__SHIFT 0x0
+#define UMCCH7_3_BaseAddrCS0__BaseAddr__SHIFT 0x1
+#define UMCCH7_3_BaseAddrCS0__CSEnable_MASK 0x00000001L
+#define UMCCH7_3_BaseAddrCS0__BaseAddr_MASK 0xFFFFFFFEL
+//UMCCH7_3_AddrMaskCS01
+#define UMCCH7_3_AddrMaskCS01__AddrMask__SHIFT 0x1
+#define UMCCH7_3_AddrMaskCS01__AddrMask_MASK 0xFFFFFFFEL
+//UMCCH7_3_AddrSelCS01
+#define UMCCH7_3_AddrSelCS01__BankBit0__SHIFT 0x0
+#define UMCCH7_3_AddrSelCS01__BankBit1__SHIFT 0x4
+#define UMCCH7_3_AddrSelCS01__BankBit2__SHIFT 0x8
+#define UMCCH7_3_AddrSelCS01__BankBit3__SHIFT 0xc
+#define UMCCH7_3_AddrSelCS01__BankBit4__SHIFT 0x10
+#define UMCCH7_3_AddrSelCS01__RowLo__SHIFT 0x18
+#define UMCCH7_3_AddrSelCS01__RowHi__SHIFT 0x1c
+#define UMCCH7_3_AddrSelCS01__BankBit0_MASK 0x0000000FL
+#define UMCCH7_3_AddrSelCS01__BankBit1_MASK 0x000000F0L
+#define UMCCH7_3_AddrSelCS01__BankBit2_MASK 0x00000F00L
+#define UMCCH7_3_AddrSelCS01__BankBit3_MASK 0x0000F000L
+#define UMCCH7_3_AddrSelCS01__BankBit4_MASK 0x001F0000L
+#define UMCCH7_3_AddrSelCS01__RowLo_MASK 0x0F000000L
+#define UMCCH7_3_AddrSelCS01__RowHi_MASK 0xF0000000L
+//UMCCH7_3_AddrHashBank0
+#define UMCCH7_3_AddrHashBank0__XorEnable__SHIFT 0x0
+#define UMCCH7_3_AddrHashBank0__ColXor__SHIFT 0x1
+#define UMCCH7_3_AddrHashBank0__RowXor__SHIFT 0xe
+#define UMCCH7_3_AddrHashBank0__XorEnable_MASK 0x00000001L
+#define UMCCH7_3_AddrHashBank0__ColXor_MASK 0x00003FFEL
+#define UMCCH7_3_AddrHashBank0__RowXor_MASK 0xFFFFC000L
+//UMCCH7_3_AddrHashBank1
+#define UMCCH7_3_AddrHashBank1__XorEnable__SHIFT 0x0
+#define UMCCH7_3_AddrHashBank1__ColXor__SHIFT 0x1
+#define UMCCH7_3_AddrHashBank1__RowXor__SHIFT 0xe
+#define UMCCH7_3_AddrHashBank1__XorEnable_MASK 0x00000001L
+#define UMCCH7_3_AddrHashBank1__ColXor_MASK 0x00003FFEL
+#define UMCCH7_3_AddrHashBank1__RowXor_MASK 0xFFFFC000L
+//UMCCH7_3_AddrHashBank2
+#define UMCCH7_3_AddrHashBank2__XorEnable__SHIFT 0x0
+#define UMCCH7_3_AddrHashBank2__ColXor__SHIFT 0x1
+#define UMCCH7_3_AddrHashBank2__RowXor__SHIFT 0xe
+#define UMCCH7_3_AddrHashBank2__XorEnable_MASK 0x00000001L
+#define UMCCH7_3_AddrHashBank2__ColXor_MASK 0x00003FFEL
+#define UMCCH7_3_AddrHashBank2__RowXor_MASK 0xFFFFC000L
+//UMCCH7_3_AddrHashBank3
+#define UMCCH7_3_AddrHashBank3__XorEnable__SHIFT 0x0
+#define UMCCH7_3_AddrHashBank3__ColXor__SHIFT 0x1
+#define UMCCH7_3_AddrHashBank3__RowXor__SHIFT 0xe
+#define UMCCH7_3_AddrHashBank3__XorEnable_MASK 0x00000001L
+#define UMCCH7_3_AddrHashBank3__ColXor_MASK 0x00003FFEL
+#define UMCCH7_3_AddrHashBank3__RowXor_MASK 0xFFFFC000L
+//UMCCH7_3_AddrHashBank4
+#define UMCCH7_3_AddrHashBank4__XorEnable__SHIFT 0x0
+#define UMCCH7_3_AddrHashBank4__ColXor__SHIFT 0x1
+#define UMCCH7_3_AddrHashBank4__RowXor__SHIFT 0xe
+#define UMCCH7_3_AddrHashBank4__XorEnable_MASK 0x00000001L
+#define UMCCH7_3_AddrHashBank4__ColXor_MASK 0x00003FFEL
+#define UMCCH7_3_AddrHashBank4__RowXor_MASK 0xFFFFC000L
+//UMCCH7_3_AddrHashBank5
+#define UMCCH7_3_AddrHashBank5__XorEnable__SHIFT 0x0
+#define UMCCH7_3_AddrHashBank5__ColXor__SHIFT 0x1
+#define UMCCH7_3_AddrHashBank5__RowXor__SHIFT 0xe
+#define UMCCH7_3_AddrHashBank5__XorEnable_MASK 0x00000001L
+#define UMCCH7_3_AddrHashBank5__ColXor_MASK 0x00003FFEL
+#define UMCCH7_3_AddrHashBank5__RowXor_MASK 0xFFFFC000L
+//UMCCH7_3_EccErrCntSel
+#define UMCCH7_3_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0
+#define UMCCH7_3_EccErrCntSel__EccErrInt__SHIFT 0xc
+#define UMCCH7_3_EccErrCntSel__EccErrCntEn__SHIFT 0xf
+#define UMCCH7_3_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL
+#define UMCCH7_3_EccErrCntSel__EccErrInt_MASK 0x00003000L
+#define UMCCH7_3_EccErrCntSel__EccErrCntEn_MASK 0x00008000L
+//UMCCH7_3_EccErrCnt
+#define UMCCH7_3_EccErrCnt__EccErrCnt__SHIFT 0x0
+#define UMCCH7_3_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL
+//UMCCH7_3_PerfMonCtlClk
+#define UMCCH7_3_PerfMonCtlClk__GlblResetMsk__SHIFT 0x0
+#define UMCCH7_3_PerfMonCtlClk__ClkGate__SHIFT 0x16
+#define UMCCH7_3_PerfMonCtlClk__GlblReset__SHIFT 0x18
+#define UMCCH7_3_PerfMonCtlClk__GlblMonEn__SHIFT 0x19
+#define UMCCH7_3_PerfMonCtlClk__NumCounters__SHIFT 0x1a
+#define UMCCH7_3_PerfMonCtlClk__CtrClkEn__SHIFT 0x1f
+#define UMCCH7_3_PerfMonCtlClk__GlblResetMsk_MASK 0x000001FFL
+#define UMCCH7_3_PerfMonCtlClk__ClkGate_MASK 0x00400000L
+#define UMCCH7_3_PerfMonCtlClk__GlblReset_MASK 0x01000000L
+#define UMCCH7_3_PerfMonCtlClk__GlblMonEn_MASK 0x02000000L
+#define UMCCH7_3_PerfMonCtlClk__NumCounters_MASK 0x3C000000L
+#define UMCCH7_3_PerfMonCtlClk__CtrClkEn_MASK 0x80000000L
+//UMCCH7_3_PerfMonCtrClk_Lo
+#define UMCCH7_3_PerfMonCtrClk_Lo__Data__SHIFT 0x0
+#define UMCCH7_3_PerfMonCtrClk_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_3_PerfMonCtrClk_Hi
+#define UMCCH7_3_PerfMonCtrClk_Hi__Data__SHIFT 0x0
+#define UMCCH7_3_PerfMonCtrClk_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_3_PerfMonCtrClk_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_3_PerfMonCtrClk_Hi__Overflow_MASK 0x00010000L
+//UMCCH7_3_PerfMonCtl1
+#define UMCCH7_3_PerfMonCtl1__EventSelect__SHIFT 0x0
+#define UMCCH7_3_PerfMonCtl1__RdWrMask__SHIFT 0x8
+#define UMCCH7_3_PerfMonCtl1__PriorityMask__SHIFT 0xa
+#define UMCCH7_3_PerfMonCtl1__ReqSizeMask__SHIFT 0xe
+#define UMCCH7_3_PerfMonCtl1__BankSel__SHIFT 0x10
+#define UMCCH7_3_PerfMonCtl1__VCSel__SHIFT 0x18
+#define UMCCH7_3_PerfMonCtl1__SubChanMask__SHIFT 0x1d
+#define UMCCH7_3_PerfMonCtl1__Enable__SHIFT 0x1f
+#define UMCCH7_3_PerfMonCtl1__EventSelect_MASK 0x000000FFL
+#define UMCCH7_3_PerfMonCtl1__RdWrMask_MASK 0x00000300L
+#define UMCCH7_3_PerfMonCtl1__PriorityMask_MASK 0x00003C00L
+#define UMCCH7_3_PerfMonCtl1__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH7_3_PerfMonCtl1__BankSel_MASK 0x00FF0000L
+#define UMCCH7_3_PerfMonCtl1__VCSel_MASK 0x1F000000L
+#define UMCCH7_3_PerfMonCtl1__SubChanMask_MASK 0x60000000L
+#define UMCCH7_3_PerfMonCtl1__Enable_MASK 0x80000000L
+//UMCCH7_3_PerfMonCtr1_Lo
+#define UMCCH7_3_PerfMonCtr1_Lo__Data__SHIFT 0x0
+#define UMCCH7_3_PerfMonCtr1_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_3_PerfMonCtr1_Hi
+#define UMCCH7_3_PerfMonCtr1_Hi__Data__SHIFT 0x0
+#define UMCCH7_3_PerfMonCtr1_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_3_PerfMonCtr1_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH7_3_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH7_3_PerfMonCtr1_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_3_PerfMonCtr1_Hi__Overflow_MASK 0x00010000L
+#define UMCCH7_3_PerfMonCtr1_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH7_3_PerfMonCtr1_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH7_3_PerfMonCtl2
+#define UMCCH7_3_PerfMonCtl2__EventSelect__SHIFT 0x0
+#define UMCCH7_3_PerfMonCtl2__RdWrMask__SHIFT 0x8
+#define UMCCH7_3_PerfMonCtl2__PriorityMask__SHIFT 0xa
+#define UMCCH7_3_PerfMonCtl2__ReqSizeMask__SHIFT 0xe
+#define UMCCH7_3_PerfMonCtl2__BankSel__SHIFT 0x10
+#define UMCCH7_3_PerfMonCtl2__VCSel__SHIFT 0x18
+#define UMCCH7_3_PerfMonCtl2__SubChanMask__SHIFT 0x1d
+#define UMCCH7_3_PerfMonCtl2__Enable__SHIFT 0x1f
+#define UMCCH7_3_PerfMonCtl2__EventSelect_MASK 0x000000FFL
+#define UMCCH7_3_PerfMonCtl2__RdWrMask_MASK 0x00000300L
+#define UMCCH7_3_PerfMonCtl2__PriorityMask_MASK 0x00003C00L
+#define UMCCH7_3_PerfMonCtl2__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH7_3_PerfMonCtl2__BankSel_MASK 0x00FF0000L
+#define UMCCH7_3_PerfMonCtl2__VCSel_MASK 0x1F000000L
+#define UMCCH7_3_PerfMonCtl2__SubChanMask_MASK 0x60000000L
+#define UMCCH7_3_PerfMonCtl2__Enable_MASK 0x80000000L
+//UMCCH7_3_PerfMonCtr2_Lo
+#define UMCCH7_3_PerfMonCtr2_Lo__Data__SHIFT 0x0
+#define UMCCH7_3_PerfMonCtr2_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_3_PerfMonCtr2_Hi
+#define UMCCH7_3_PerfMonCtr2_Hi__Data__SHIFT 0x0
+#define UMCCH7_3_PerfMonCtr2_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_3_PerfMonCtr2_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH7_3_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH7_3_PerfMonCtr2_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_3_PerfMonCtr2_Hi__Overflow_MASK 0x00010000L
+#define UMCCH7_3_PerfMonCtr2_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH7_3_PerfMonCtr2_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH7_3_PerfMonCtl3
+#define UMCCH7_3_PerfMonCtl3__EventSelect__SHIFT 0x0
+#define UMCCH7_3_PerfMonCtl3__RdWrMask__SHIFT 0x8
+#define UMCCH7_3_PerfMonCtl3__PriorityMask__SHIFT 0xa
+#define UMCCH7_3_PerfMonCtl3__ReqSizeMask__SHIFT 0xe
+#define UMCCH7_3_PerfMonCtl3__BankSel__SHIFT 0x10
+#define UMCCH7_3_PerfMonCtl3__VCSel__SHIFT 0x18
+#define UMCCH7_3_PerfMonCtl3__SubChanMask__SHIFT 0x1d
+#define UMCCH7_3_PerfMonCtl3__Enable__SHIFT 0x1f
+#define UMCCH7_3_PerfMonCtl3__EventSelect_MASK 0x000000FFL
+#define UMCCH7_3_PerfMonCtl3__RdWrMask_MASK 0x00000300L
+#define UMCCH7_3_PerfMonCtl3__PriorityMask_MASK 0x00003C00L
+#define UMCCH7_3_PerfMonCtl3__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH7_3_PerfMonCtl3__BankSel_MASK 0x00FF0000L
+#define UMCCH7_3_PerfMonCtl3__VCSel_MASK 0x1F000000L
+#define UMCCH7_3_PerfMonCtl3__SubChanMask_MASK 0x60000000L
+#define UMCCH7_3_PerfMonCtl3__Enable_MASK 0x80000000L
+//UMCCH7_3_PerfMonCtr3_Lo
+#define UMCCH7_3_PerfMonCtr3_Lo__Data__SHIFT 0x0
+#define UMCCH7_3_PerfMonCtr3_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_3_PerfMonCtr3_Hi
+#define UMCCH7_3_PerfMonCtr3_Hi__Data__SHIFT 0x0
+#define UMCCH7_3_PerfMonCtr3_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_3_PerfMonCtr3_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH7_3_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH7_3_PerfMonCtr3_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_3_PerfMonCtr3_Hi__Overflow_MASK 0x00010000L
+#define UMCCH7_3_PerfMonCtr3_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH7_3_PerfMonCtr3_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH7_3_PerfMonCtl4
+#define UMCCH7_3_PerfMonCtl4__EventSelect__SHIFT 0x0
+#define UMCCH7_3_PerfMonCtl4__RdWrMask__SHIFT 0x8
+#define UMCCH7_3_PerfMonCtl4__PriorityMask__SHIFT 0xa
+#define UMCCH7_3_PerfMonCtl4__ReqSizeMask__SHIFT 0xe
+#define UMCCH7_3_PerfMonCtl4__BankSel__SHIFT 0x10
+#define UMCCH7_3_PerfMonCtl4__VCSel__SHIFT 0x18
+#define UMCCH7_3_PerfMonCtl4__SubChanMask__SHIFT 0x1d
+#define UMCCH7_3_PerfMonCtl4__Enable__SHIFT 0x1f
+#define UMCCH7_3_PerfMonCtl4__EventSelect_MASK 0x000000FFL
+#define UMCCH7_3_PerfMonCtl4__RdWrMask_MASK 0x00000300L
+#define UMCCH7_3_PerfMonCtl4__PriorityMask_MASK 0x00003C00L
+#define UMCCH7_3_PerfMonCtl4__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH7_3_PerfMonCtl4__BankSel_MASK 0x00FF0000L
+#define UMCCH7_3_PerfMonCtl4__VCSel_MASK 0x1F000000L
+#define UMCCH7_3_PerfMonCtl4__SubChanMask_MASK 0x60000000L
+#define UMCCH7_3_PerfMonCtl4__Enable_MASK 0x80000000L
+//UMCCH7_3_PerfMonCtr4_Lo
+#define UMCCH7_3_PerfMonCtr4_Lo__Data__SHIFT 0x0
+#define UMCCH7_3_PerfMonCtr4_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_3_PerfMonCtr4_Hi
+#define UMCCH7_3_PerfMonCtr4_Hi__Data__SHIFT 0x0
+#define UMCCH7_3_PerfMonCtr4_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_3_PerfMonCtr4_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH7_3_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH7_3_PerfMonCtr4_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_3_PerfMonCtr4_Hi__Overflow_MASK 0x00010000L
+#define UMCCH7_3_PerfMonCtr4_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH7_3_PerfMonCtr4_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH7_3_PerfMonCtl5
+#define UMCCH7_3_PerfMonCtl5__EventSelect__SHIFT 0x0
+#define UMCCH7_3_PerfMonCtl5__RdWrMask__SHIFT 0x8
+#define UMCCH7_3_PerfMonCtl5__PriorityMask__SHIFT 0xa
+#define UMCCH7_3_PerfMonCtl5__ReqSizeMask__SHIFT 0xe
+#define UMCCH7_3_PerfMonCtl5__BankSel__SHIFT 0x10
+#define UMCCH7_3_PerfMonCtl5__VCSel__SHIFT 0x18
+#define UMCCH7_3_PerfMonCtl5__SubChanMask__SHIFT 0x1d
+#define UMCCH7_3_PerfMonCtl5__Enable__SHIFT 0x1f
+#define UMCCH7_3_PerfMonCtl5__EventSelect_MASK 0x000000FFL
+#define UMCCH7_3_PerfMonCtl5__RdWrMask_MASK 0x00000300L
+#define UMCCH7_3_PerfMonCtl5__PriorityMask_MASK 0x00003C00L
+#define UMCCH7_3_PerfMonCtl5__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH7_3_PerfMonCtl5__BankSel_MASK 0x00FF0000L
+#define UMCCH7_3_PerfMonCtl5__VCSel_MASK 0x1F000000L
+#define UMCCH7_3_PerfMonCtl5__SubChanMask_MASK 0x60000000L
+#define UMCCH7_3_PerfMonCtl5__Enable_MASK 0x80000000L
+//UMCCH7_3_PerfMonCtr5_Lo
+#define UMCCH7_3_PerfMonCtr5_Lo__Data__SHIFT 0x0
+#define UMCCH7_3_PerfMonCtr5_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_3_PerfMonCtr5_Hi
+#define UMCCH7_3_PerfMonCtr5_Hi__Data__SHIFT 0x0
+#define UMCCH7_3_PerfMonCtr5_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_3_PerfMonCtr5_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH7_3_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH7_3_PerfMonCtr5_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_3_PerfMonCtr5_Hi__Overflow_MASK 0x00010000L
+#define UMCCH7_3_PerfMonCtr5_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH7_3_PerfMonCtr5_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH7_3_PerfMonCtl6
+#define UMCCH7_3_PerfMonCtl6__EventSelect__SHIFT 0x0
+#define UMCCH7_3_PerfMonCtl6__RdWrMask__SHIFT 0x8
+#define UMCCH7_3_PerfMonCtl6__PriorityMask__SHIFT 0xa
+#define UMCCH7_3_PerfMonCtl6__ReqSizeMask__SHIFT 0xe
+#define UMCCH7_3_PerfMonCtl6__BankSel__SHIFT 0x10
+#define UMCCH7_3_PerfMonCtl6__VCSel__SHIFT 0x18
+#define UMCCH7_3_PerfMonCtl6__SubChanMask__SHIFT 0x1d
+#define UMCCH7_3_PerfMonCtl6__Enable__SHIFT 0x1f
+#define UMCCH7_3_PerfMonCtl6__EventSelect_MASK 0x000000FFL
+#define UMCCH7_3_PerfMonCtl6__RdWrMask_MASK 0x00000300L
+#define UMCCH7_3_PerfMonCtl6__PriorityMask_MASK 0x00003C00L
+#define UMCCH7_3_PerfMonCtl6__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH7_3_PerfMonCtl6__BankSel_MASK 0x00FF0000L
+#define UMCCH7_3_PerfMonCtl6__VCSel_MASK 0x1F000000L
+#define UMCCH7_3_PerfMonCtl6__SubChanMask_MASK 0x60000000L
+#define UMCCH7_3_PerfMonCtl6__Enable_MASK 0x80000000L
+//UMCCH7_3_PerfMonCtr6_Lo
+#define UMCCH7_3_PerfMonCtr6_Lo__Data__SHIFT 0x0
+#define UMCCH7_3_PerfMonCtr6_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_3_PerfMonCtr6_Hi
+#define UMCCH7_3_PerfMonCtr6_Hi__Data__SHIFT 0x0
+#define UMCCH7_3_PerfMonCtr6_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_3_PerfMonCtr6_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH7_3_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH7_3_PerfMonCtr6_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_3_PerfMonCtr6_Hi__Overflow_MASK 0x00010000L
+#define UMCCH7_3_PerfMonCtr6_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH7_3_PerfMonCtr6_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH7_3_PerfMonCtl7
+#define UMCCH7_3_PerfMonCtl7__EventSelect__SHIFT 0x0
+#define UMCCH7_3_PerfMonCtl7__RdWrMask__SHIFT 0x8
+#define UMCCH7_3_PerfMonCtl7__PriorityMask__SHIFT 0xa
+#define UMCCH7_3_PerfMonCtl7__ReqSizeMask__SHIFT 0xe
+#define UMCCH7_3_PerfMonCtl7__BankSel__SHIFT 0x10
+#define UMCCH7_3_PerfMonCtl7__VCSel__SHIFT 0x18
+#define UMCCH7_3_PerfMonCtl7__SubChanMask__SHIFT 0x1d
+#define UMCCH7_3_PerfMonCtl7__Enable__SHIFT 0x1f
+#define UMCCH7_3_PerfMonCtl7__EventSelect_MASK 0x000000FFL
+#define UMCCH7_3_PerfMonCtl7__RdWrMask_MASK 0x00000300L
+#define UMCCH7_3_PerfMonCtl7__PriorityMask_MASK 0x00003C00L
+#define UMCCH7_3_PerfMonCtl7__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH7_3_PerfMonCtl7__BankSel_MASK 0x00FF0000L
+#define UMCCH7_3_PerfMonCtl7__VCSel_MASK 0x1F000000L
+#define UMCCH7_3_PerfMonCtl7__SubChanMask_MASK 0x60000000L
+#define UMCCH7_3_PerfMonCtl7__Enable_MASK 0x80000000L
+//UMCCH7_3_PerfMonCtr7_Lo
+#define UMCCH7_3_PerfMonCtr7_Lo__Data__SHIFT 0x0
+#define UMCCH7_3_PerfMonCtr7_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_3_PerfMonCtr7_Hi
+#define UMCCH7_3_PerfMonCtr7_Hi__Data__SHIFT 0x0
+#define UMCCH7_3_PerfMonCtr7_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_3_PerfMonCtr7_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH7_3_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH7_3_PerfMonCtr7_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_3_PerfMonCtr7_Hi__Overflow_MASK 0x00010000L
+#define UMCCH7_3_PerfMonCtr7_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH7_3_PerfMonCtr7_Hi__ThreshCnt_MASK 0xFFF00000L
+//UMCCH7_3_PerfMonCtl8
+#define UMCCH7_3_PerfMonCtl8__EventSelect__SHIFT 0x0
+#define UMCCH7_3_PerfMonCtl8__RdWrMask__SHIFT 0x8
+#define UMCCH7_3_PerfMonCtl8__PriorityMask__SHIFT 0xa
+#define UMCCH7_3_PerfMonCtl8__ReqSizeMask__SHIFT 0xe
+#define UMCCH7_3_PerfMonCtl8__BankSel__SHIFT 0x10
+#define UMCCH7_3_PerfMonCtl8__VCSel__SHIFT 0x18
+#define UMCCH7_3_PerfMonCtl8__SubChanMask__SHIFT 0x1d
+#define UMCCH7_3_PerfMonCtl8__Enable__SHIFT 0x1f
+#define UMCCH7_3_PerfMonCtl8__EventSelect_MASK 0x000000FFL
+#define UMCCH7_3_PerfMonCtl8__RdWrMask_MASK 0x00000300L
+#define UMCCH7_3_PerfMonCtl8__PriorityMask_MASK 0x00003C00L
+#define UMCCH7_3_PerfMonCtl8__ReqSizeMask_MASK 0x0000C000L
+#define UMCCH7_3_PerfMonCtl8__BankSel_MASK 0x00FF0000L
+#define UMCCH7_3_PerfMonCtl8__VCSel_MASK 0x1F000000L
+#define UMCCH7_3_PerfMonCtl8__SubChanMask_MASK 0x60000000L
+#define UMCCH7_3_PerfMonCtl8__Enable_MASK 0x80000000L
+//UMCCH7_3_PerfMonCtr8_Lo
+#define UMCCH7_3_PerfMonCtr8_Lo__Data__SHIFT 0x0
+#define UMCCH7_3_PerfMonCtr8_Lo__Data_MASK 0xFFFFFFFFL
+//UMCCH7_3_PerfMonCtr8_Hi
+#define UMCCH7_3_PerfMonCtr8_Hi__Data__SHIFT 0x0
+#define UMCCH7_3_PerfMonCtr8_Hi__Overflow__SHIFT 0x10
+#define UMCCH7_3_PerfMonCtr8_Hi__ThreshCntEn__SHIFT 0x12
+#define UMCCH7_3_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14
+#define UMCCH7_3_PerfMonCtr8_Hi__Data_MASK 0x0000FFFFL
+#define UMCCH7_3_PerfMonCtr8_Hi__Overflow_MASK 0x00010000L
+#define UMCCH7_3_PerfMonCtr8_Hi__ThreshCntEn_MASK 0x000C0000L
+#define UMCCH7_3_PerfMonCtr8_Hi__ThreshCnt_MASK 0xFFF00000L
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_offset.h
new file mode 100644
index 000000000000..98d22bd5b304
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_offset.h
@@ -0,0 +1,1462 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef _vcn_2_6_0_OFFSET_HEADER
+#define _vcn_2_6_0_OFFSET_HEADER
+
+
+
+// addressBlock: uvd0_ecpudec
+// base address: 0x1fd00
+#define regUVD_VCPU_CACHE_OFFSET0 0x0140
+#define regUVD_VCPU_CACHE_OFFSET0_BASE_IDX 1
+#define regUVD_VCPU_CACHE_SIZE0 0x0141
+#define regUVD_VCPU_CACHE_SIZE0_BASE_IDX 1
+#define regUVD_VCPU_CACHE_OFFSET1 0x0142
+#define regUVD_VCPU_CACHE_OFFSET1_BASE_IDX 1
+#define regUVD_VCPU_CACHE_SIZE1 0x0143
+#define regUVD_VCPU_CACHE_SIZE1_BASE_IDX 1
+#define regUVD_VCPU_CACHE_OFFSET2 0x0144
+#define regUVD_VCPU_CACHE_OFFSET2_BASE_IDX 1
+#define regUVD_VCPU_CACHE_SIZE2 0x0145
+#define regUVD_VCPU_CACHE_SIZE2_BASE_IDX 1
+#define regUVD_VCPU_CACHE_OFFSET3 0x0146
+#define regUVD_VCPU_CACHE_OFFSET3_BASE_IDX 1
+#define regUVD_VCPU_CACHE_SIZE3 0x0147
+#define regUVD_VCPU_CACHE_SIZE3_BASE_IDX 1
+#define regUVD_VCPU_CACHE_OFFSET4 0x0148
+#define regUVD_VCPU_CACHE_OFFSET4_BASE_IDX 1
+#define regUVD_VCPU_CACHE_SIZE4 0x0149
+#define regUVD_VCPU_CACHE_SIZE4_BASE_IDX 1
+#define regUVD_VCPU_CACHE_OFFSET5 0x014a
+#define regUVD_VCPU_CACHE_OFFSET5_BASE_IDX 1
+#define regUVD_VCPU_CACHE_SIZE5 0x014b
+#define regUVD_VCPU_CACHE_SIZE5_BASE_IDX 1
+#define regUVD_VCPU_CACHE_OFFSET6 0x014c
+#define regUVD_VCPU_CACHE_OFFSET6_BASE_IDX 1
+#define regUVD_VCPU_CACHE_SIZE6 0x014d
+#define regUVD_VCPU_CACHE_SIZE6_BASE_IDX 1
+#define regUVD_VCPU_CACHE_OFFSET7 0x014e
+#define regUVD_VCPU_CACHE_OFFSET7_BASE_IDX 1
+#define regUVD_VCPU_CACHE_SIZE7 0x014f
+#define regUVD_VCPU_CACHE_SIZE7_BASE_IDX 1
+#define regUVD_VCPU_CACHE_OFFSET8 0x0150
+#define regUVD_VCPU_CACHE_OFFSET8_BASE_IDX 1
+#define regUVD_VCPU_CACHE_SIZE8 0x0151
+#define regUVD_VCPU_CACHE_SIZE8_BASE_IDX 1
+#define regUVD_VCPU_NONCACHE_OFFSET0 0x0152
+#define regUVD_VCPU_NONCACHE_OFFSET0_BASE_IDX 1
+#define regUVD_VCPU_NONCACHE_SIZE0 0x0153
+#define regUVD_VCPU_NONCACHE_SIZE0_BASE_IDX 1
+#define regUVD_VCPU_NONCACHE_OFFSET1 0x0154
+#define regUVD_VCPU_NONCACHE_OFFSET1_BASE_IDX 1
+#define regUVD_VCPU_NONCACHE_SIZE1 0x0155
+#define regUVD_VCPU_NONCACHE_SIZE1_BASE_IDX 1
+#define regUVD_VCPU_CNTL 0x0156
+#define regUVD_VCPU_CNTL_BASE_IDX 1
+#define regUVD_VCPU_PRID 0x0157
+#define regUVD_VCPU_PRID_BASE_IDX 1
+#define regUVD_VCPU_TRCE 0x0158
+#define regUVD_VCPU_TRCE_BASE_IDX 1
+#define regUVD_VCPU_TRCE_RD 0x0159
+#define regUVD_VCPU_TRCE_RD_BASE_IDX 1
+#define regUVD_VCPU_IND_INDEX 0x015b
+#define regUVD_VCPU_IND_INDEX_BASE_IDX 1
+#define regUVD_VCPU_IND_DATA 0x015c
+#define regUVD_VCPU_IND_DATA_BASE_IDX 1
+
+
+// addressBlock: uvd0_jpegnpdec
+// base address: 0x1e200
+#define regUVD_JPEG_CNTL 0x0080
+#define regUVD_JPEG_CNTL_BASE_IDX 0
+#define regUVD_JPEG_RB_BASE 0x0081
+#define regUVD_JPEG_RB_BASE_BASE_IDX 0
+#define regUVD_JPEG_RB_WPTR 0x0082
+#define regUVD_JPEG_RB_WPTR_BASE_IDX 0
+#define regUVD_JPEG_RB_RPTR 0x0083
+#define regUVD_JPEG_RB_RPTR_BASE_IDX 0
+#define regUVD_JPEG_RB_SIZE 0x0084
+#define regUVD_JPEG_RB_SIZE_BASE_IDX 0
+#define regUVD_JPEG_DEC_CNT 0x0085
+#define regUVD_JPEG_DEC_CNT_BASE_IDX 0
+#define regUVD_JPEG_SPS_INFO 0x0086
+#define regUVD_JPEG_SPS_INFO_BASE_IDX 0
+#define regUVD_JPEG_SPS1_INFO 0x0087
+#define regUVD_JPEG_SPS1_INFO_BASE_IDX 0
+#define regUVD_JPEG_RE_TIMER 0x0088
+#define regUVD_JPEG_RE_TIMER_BASE_IDX 0
+#define regUVD_JPEG_DEC_SCRATCH0 0x0089
+#define regUVD_JPEG_DEC_SCRATCH0_BASE_IDX 0
+#define regUVD_JPEG_INT_EN 0x008a
+#define regUVD_JPEG_INT_EN_BASE_IDX 0
+#define regUVD_JPEG_INT_STAT 0x008b
+#define regUVD_JPEG_INT_STAT_BASE_IDX 0
+#define regUVD_JPEG_TIER_CNTL0 0x008d
+#define regUVD_JPEG_TIER_CNTL0_BASE_IDX 0
+#define regUVD_JPEG_TIER_CNTL1 0x008e
+#define regUVD_JPEG_TIER_CNTL1_BASE_IDX 0
+#define regUVD_JPEG_TIER_CNTL2 0x008f
+#define regUVD_JPEG_TIER_CNTL2_BASE_IDX 0
+#define regUVD_JPEG_TIER_STATUS 0x0090
+#define regUVD_JPEG_TIER_STATUS_BASE_IDX 0
+#define regUVD_JPEG_OUTBUF_CNTL 0x009c
+#define regUVD_JPEG_OUTBUF_CNTL_BASE_IDX 0
+#define regUVD_JPEG_OUTBUF_WPTR 0x009d
+#define regUVD_JPEG_OUTBUF_WPTR_BASE_IDX 0
+#define regUVD_JPEG_OUTBUF_RPTR 0x009e
+#define regUVD_JPEG_OUTBUF_RPTR_BASE_IDX 0
+#define regUVD_JPEG_PITCH 0x009f
+#define regUVD_JPEG_PITCH_BASE_IDX 0
+#define regUVD_JPEG_UV_PITCH 0x00a0
+#define regUVD_JPEG_UV_PITCH_BASE_IDX 0
+#define regJPEG_DEC_Y_GFX8_TILING_SURFACE 0x00a1
+#define regJPEG_DEC_Y_GFX8_TILING_SURFACE_BASE_IDX 0
+#define regJPEG_DEC_UV_GFX8_TILING_SURFACE 0x00a2
+#define regJPEG_DEC_UV_GFX8_TILING_SURFACE_BASE_IDX 0
+#define regJPEG_DEC_GFX8_ADDR_CONFIG 0x00a3
+#define regJPEG_DEC_GFX8_ADDR_CONFIG_BASE_IDX 0
+#define regJPEG_DEC_Y_GFX10_TILING_SURFACE 0x00a4
+#define regJPEG_DEC_Y_GFX10_TILING_SURFACE_BASE_IDX 0
+#define regJPEG_DEC_UV_GFX10_TILING_SURFACE 0x00a5
+#define regJPEG_DEC_UV_GFX10_TILING_SURFACE_BASE_IDX 0
+#define regJPEG_DEC_GFX10_ADDR_CONFIG 0x00a6
+#define regJPEG_DEC_GFX10_ADDR_CONFIG_BASE_IDX 0
+#define regJPEG_DEC_ADDR_MODE 0x00a7
+#define regJPEG_DEC_ADDR_MODE_BASE_IDX 0
+#define regUVD_JPEG_OUTPUT_XY 0x00a8
+#define regUVD_JPEG_OUTPUT_XY_BASE_IDX 0
+#define regUVD_JPEG_GPCOM_CMD 0x00a9
+#define regUVD_JPEG_GPCOM_CMD_BASE_IDX 0
+#define regUVD_JPEG_GPCOM_DATA0 0x00aa
+#define regUVD_JPEG_GPCOM_DATA0_BASE_IDX 0
+#define regUVD_JPEG_GPCOM_DATA1 0x00ab
+#define regUVD_JPEG_GPCOM_DATA1_BASE_IDX 0
+#define regUVD_JPEG_INDEX 0x00ac
+#define regUVD_JPEG_INDEX_BASE_IDX 0
+#define regUVD_JPEG_DATA 0x00ad
+#define regUVD_JPEG_DATA_BASE_IDX 0
+#define regUVD_JPEG_SCRATCH1 0x00ae
+#define regUVD_JPEG_SCRATCH1_BASE_IDX 0
+#define regUVD_JPEG_DEC_SOFT_RST 0x00af
+#define regUVD_JPEG_DEC_SOFT_RST_BASE_IDX 0
+
+
+// addressBlock: uvd0_lmi_adpdec
+// base address: 0x20870
+#define regUVD_LMI_RE_64BIT_BAR_LOW 0x041c
+#define regUVD_LMI_RE_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_RE_64BIT_BAR_HIGH 0x041d
+#define regUVD_LMI_RE_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_IT_64BIT_BAR_LOW 0x041e
+#define regUVD_LMI_IT_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_IT_64BIT_BAR_HIGH 0x041f
+#define regUVD_LMI_IT_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_MP_64BIT_BAR_LOW 0x0420
+#define regUVD_LMI_MP_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_MP_64BIT_BAR_HIGH 0x0421
+#define regUVD_LMI_MP_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_CM_64BIT_BAR_LOW 0x0422
+#define regUVD_LMI_CM_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_CM_64BIT_BAR_HIGH 0x0423
+#define regUVD_LMI_CM_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_DB_64BIT_BAR_LOW 0x0424
+#define regUVD_LMI_DB_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_DB_64BIT_BAR_HIGH 0x0425
+#define regUVD_LMI_DB_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_DBW_64BIT_BAR_LOW 0x0426
+#define regUVD_LMI_DBW_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_DBW_64BIT_BAR_HIGH 0x0427
+#define regUVD_LMI_DBW_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_IDCT_64BIT_BAR_LOW 0x0428
+#define regUVD_LMI_IDCT_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_IDCT_64BIT_BAR_HIGH 0x0429
+#define regUVD_LMI_IDCT_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_MPRD_S0_64BIT_BAR_LOW 0x042a
+#define regUVD_LMI_MPRD_S0_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_MPRD_S0_64BIT_BAR_HIGH 0x042b
+#define regUVD_LMI_MPRD_S0_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_MPRD_S1_64BIT_BAR_LOW 0x042c
+#define regUVD_LMI_MPRD_S1_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_MPRD_S1_64BIT_BAR_HIGH 0x042d
+#define regUVD_LMI_MPRD_S1_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_MPRD_DBW_64BIT_BAR_LOW 0x042e
+#define regUVD_LMI_MPRD_DBW_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_MPRD_DBW_64BIT_BAR_HIGH 0x042f
+#define regUVD_LMI_MPRD_DBW_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_MPC_64BIT_BAR_LOW 0x0430
+#define regUVD_LMI_MPC_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_MPC_64BIT_BAR_HIGH 0x0431
+#define regUVD_LMI_MPC_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x0432
+#define regUVD_LMI_RBC_RB_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x0433
+#define regUVD_LMI_RBC_RB_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x0434
+#define regUVD_LMI_RBC_IB_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x0435
+#define regUVD_LMI_RBC_IB_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_LBSI_64BIT_BAR_LOW 0x0436
+#define regUVD_LMI_LBSI_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_LBSI_64BIT_BAR_HIGH 0x0437
+#define regUVD_LMI_LBSI_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW 0x0438
+#define regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH 0x0439
+#define regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW 0x043a
+#define regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH 0x043b
+#define regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x043c
+#define regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x043d
+#define regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_CENC_64BIT_BAR_LOW 0x043e
+#define regUVD_LMI_CENC_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_CENC_64BIT_BAR_HIGH 0x043f
+#define regUVD_LMI_CENC_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_SRE_64BIT_BAR_LOW 0x0440
+#define regUVD_LMI_SRE_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_SRE_64BIT_BAR_HIGH 0x0441
+#define regUVD_LMI_SRE_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW 0x0442
+#define regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH 0x0443
+#define regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW 0x0444
+#define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH 0x0445
+#define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW 0x0446
+#define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH 0x0447
+#define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_MIF_REF_64BIT_BAR_LOW 0x0448
+#define regUVD_LMI_MIF_REF_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_MIF_REF_64BIT_BAR_HIGH 0x0449
+#define regUVD_LMI_MIF_REF_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_MIF_DBW_64BIT_BAR_LOW 0x044a
+#define regUVD_LMI_MIF_DBW_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH 0x044b
+#define regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW 0x044c
+#define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH 0x044d
+#define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW 0x044e
+#define regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH 0x044f
+#define regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW 0x0450
+#define regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH 0x0451
+#define regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW 0x0452
+#define regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH 0x0453
+#define regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW 0x0454
+#define regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH 0x0455
+#define regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW 0x0456
+#define regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH 0x0457
+#define regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW 0x0458
+#define regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH 0x0459
+#define regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW 0x045a
+#define regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH 0x045b
+#define regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW 0x045c
+#define regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH 0x045d
+#define regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW 0x045e
+#define regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH 0x045f
+#define regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 0x0468
+#define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 0x0469
+#define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW 0x046a
+#define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH 0x046b
+#define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 0x046c
+#define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 0x046d
+#define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW 0x046e
+#define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH 0x046f
+#define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW 0x0470
+#define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH 0x0471
+#define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW 0x0472
+#define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH 0x0473
+#define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW 0x0474
+#define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH 0x0475
+#define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW 0x0476
+#define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH 0x0477
+#define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW 0x0478
+#define regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH 0x0479
+#define regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW 0x047a
+#define regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH 0x047b
+#define regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_SPH_64BIT_BAR_HIGH 0x047c
+#define regUVD_LMI_SPH_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW 0x047d
+#define regUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH 0x047e
+#define regUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW 0x047f
+#define regUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH 0x0480
+#define regUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW 0x0481
+#define regUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH 0x0482
+#define regUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW 0x0483
+#define regUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH 0x0484
+#define regUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW 0x0485
+#define regUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH 0x0486
+#define regUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW 0x0487
+#define regUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH 0x0488
+#define regUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW 0x0489
+#define regUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH 0x048a
+#define regUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW 0x048b
+#define regUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH 0x048c
+#define regUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_MMSCH_NC_VMID 0x048d
+#define regUVD_LMI_MMSCH_NC_VMID_BASE_IDX 1
+#define regUVD_LMI_MMSCH_CTRL 0x048e
+#define regUVD_LMI_MMSCH_CTRL_BASE_IDX 1
+#define regUVD_MMSCH_LMI_STATUS 0x048f
+#define regUVD_MMSCH_LMI_STATUS_BASE_IDX 1
+#define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW 0x0490
+#define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH 0x0491
+#define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW 0x0492
+#define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH 0x0493
+#define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW 0x0494
+#define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH 0x0495
+#define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW 0x0496
+#define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH 0x0497
+#define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_ADP_ATOMIC_CONFIG 0x0499
+#define regUVD_ADP_ATOMIC_CONFIG_BASE_IDX 1
+#define regUVD_LMI_ARB_CTRL2 0x049a
+#define regUVD_LMI_ARB_CTRL2_BASE_IDX 1
+#define regUVD_LMI_VCPU_CACHE_VMIDS_MULTI 0x049f
+#define regUVD_LMI_VCPU_CACHE_VMIDS_MULTI_BASE_IDX 1
+#define regUVD_LMI_VCPU_NC_VMIDS_MULTI 0x04a0
+#define regUVD_LMI_VCPU_NC_VMIDS_MULTI_BASE_IDX 1
+#define regUVD_LMI_LAT_CTRL 0x04a1
+#define regUVD_LMI_LAT_CTRL_BASE_IDX 1
+#define regUVD_LMI_LAT_CNTR 0x04a2
+#define regUVD_LMI_LAT_CNTR_BASE_IDX 1
+#define regUVD_LMI_AVG_LAT_CNTR 0x04a3
+#define regUVD_LMI_AVG_LAT_CNTR_BASE_IDX 1
+#define regUVD_LMI_SPH 0x04a4
+#define regUVD_LMI_SPH_BASE_IDX 1
+#define regUVD_LMI_VCPU_CACHE_VMID 0x04a5
+#define regUVD_LMI_VCPU_CACHE_VMID_BASE_IDX 1
+#define regUVD_LMI_CTRL2 0x04a6
+#define regUVD_LMI_CTRL2_BASE_IDX 1
+#define regUVD_LMI_URGENT_CTRL 0x04a7
+#define regUVD_LMI_URGENT_CTRL_BASE_IDX 1
+#define regUVD_LMI_CTRL 0x04a8
+#define regUVD_LMI_CTRL_BASE_IDX 1
+#define regUVD_LMI_STATUS 0x04a9
+#define regUVD_LMI_STATUS_BASE_IDX 1
+#define regUVD_LMI_PERFMON_CTRL 0x04ac
+#define regUVD_LMI_PERFMON_CTRL_BASE_IDX 1
+#define regUVD_LMI_PERFMON_COUNT_LO 0x04ad
+#define regUVD_LMI_PERFMON_COUNT_LO_BASE_IDX 1
+#define regUVD_LMI_PERFMON_COUNT_HI 0x04ae
+#define regUVD_LMI_PERFMON_COUNT_HI_BASE_IDX 1
+#define regUVD_LMI_ADP_SWAP_CNTL 0x04af
+#define regUVD_LMI_ADP_SWAP_CNTL_BASE_IDX 1
+#define regUVD_LMI_RBC_RB_VMID 0x04b0
+#define regUVD_LMI_RBC_RB_VMID_BASE_IDX 1
+#define regUVD_LMI_RBC_IB_VMID 0x04b1
+#define regUVD_LMI_RBC_IB_VMID_BASE_IDX 1
+#define regUVD_LMI_MC_CREDITS 0x04b2
+#define regUVD_LMI_MC_CREDITS_BASE_IDX 1
+#define regUVD_LMI_ADP_IND_INDEX 0x04b6
+#define regUVD_LMI_ADP_IND_INDEX_BASE_IDX 1
+#define regUVD_LMI_ADP_IND_DATA 0x04b7
+#define regUVD_LMI_ADP_IND_DATA_BASE_IDX 1
+#define regVCN_RAS_CNTL 0x04b9
+#define regVCN_RAS_CNTL_BASE_IDX 1
+
+
+// addressBlock: uvd0_mmsch_dec
+// base address: 0x1e000
+#define regMMSCH_UCODE_ADDR 0x0000
+#define regMMSCH_UCODE_ADDR_BASE_IDX 0
+#define regMMSCH_UCODE_DATA 0x0001
+#define regMMSCH_UCODE_DATA_BASE_IDX 0
+#define regMMSCH_SRAM_ADDR 0x0002
+#define regMMSCH_SRAM_ADDR_BASE_IDX 0
+#define regMMSCH_SRAM_DATA 0x0003
+#define regMMSCH_SRAM_DATA_BASE_IDX 0
+#define regMMSCH_VF_SRAM_OFFSET 0x0004
+#define regMMSCH_VF_SRAM_OFFSET_BASE_IDX 0
+#define regMMSCH_DB_SRAM_OFFSET 0x0005
+#define regMMSCH_DB_SRAM_OFFSET_BASE_IDX 0
+#define regMMSCH_CTX_SRAM_OFFSET 0x0006
+#define regMMSCH_CTX_SRAM_OFFSET_BASE_IDX 0
+#define regMMSCH_INTR 0x0008
+#define regMMSCH_INTR_BASE_IDX 0
+#define regMMSCH_INTR_ACK 0x0009
+#define regMMSCH_INTR_ACK_BASE_IDX 0
+#define regMMSCH_INTR_STATUS 0x000a
+#define regMMSCH_INTR_STATUS_BASE_IDX 0
+#define regMMSCH_VF_VMID 0x000b
+#define regMMSCH_VF_VMID_BASE_IDX 0
+#define regMMSCH_VF_CTX_ADDR_LO 0x000c
+#define regMMSCH_VF_CTX_ADDR_LO_BASE_IDX 0
+#define regMMSCH_VF_CTX_ADDR_HI 0x000d
+#define regMMSCH_VF_CTX_ADDR_HI_BASE_IDX 0
+#define regMMSCH_VF_CTX_SIZE 0x000e
+#define regMMSCH_VF_CTX_SIZE_BASE_IDX 0
+#define regMMSCH_VF_GPCOM_ADDR_LO 0x000f
+#define regMMSCH_VF_GPCOM_ADDR_LO_BASE_IDX 0
+#define regMMSCH_VF_GPCOM_ADDR_HI 0x0010
+#define regMMSCH_VF_GPCOM_ADDR_HI_BASE_IDX 0
+#define regMMSCH_VF_GPCOM_SIZE 0x0011
+#define regMMSCH_VF_GPCOM_SIZE_BASE_IDX 0
+#define regMMSCH_VF_MAILBOX_HOST 0x0012
+#define regMMSCH_VF_MAILBOX_HOST_BASE_IDX 0
+#define regMMSCH_VF_MAILBOX_RESP 0x0013
+#define regMMSCH_VF_MAILBOX_RESP_BASE_IDX 0
+#define regMMSCH_VF_MAILBOX_0 0x0014
+#define regMMSCH_VF_MAILBOX_0_BASE_IDX 0
+#define regMMSCH_VF_MAILBOX_0_RESP 0x0015
+#define regMMSCH_VF_MAILBOX_0_RESP_BASE_IDX 0
+#define regMMSCH_VF_MAILBOX_1 0x0016
+#define regMMSCH_VF_MAILBOX_1_BASE_IDX 0
+#define regMMSCH_VF_MAILBOX_1_RESP 0x0017
+#define regMMSCH_VF_MAILBOX_1_RESP_BASE_IDX 0
+#define regMMSCH_CNTL 0x001c
+#define regMMSCH_CNTL_BASE_IDX 0
+#define regMMSCH_NONCACHE_OFFSET0 0x001d
+#define regMMSCH_NONCACHE_OFFSET0_BASE_IDX 0
+#define regMMSCH_NONCACHE_SIZE0 0x001e
+#define regMMSCH_NONCACHE_SIZE0_BASE_IDX 0
+#define regMMSCH_NONCACHE_OFFSET1 0x001f
+#define regMMSCH_NONCACHE_OFFSET1_BASE_IDX 0
+#define regMMSCH_NONCACHE_SIZE1 0x0020
+#define regMMSCH_NONCACHE_SIZE1_BASE_IDX 0
+#define regMMSCH_PROC_STATE1 0x0026
+#define regMMSCH_PROC_STATE1_BASE_IDX 0
+#define regMMSCH_LAST_MC_ADDR 0x0027
+#define regMMSCH_LAST_MC_ADDR_BASE_IDX 0
+#define regMMSCH_LAST_MEM_ACCESS_HI 0x0028
+#define regMMSCH_LAST_MEM_ACCESS_HI_BASE_IDX 0
+#define regMMSCH_LAST_MEM_ACCESS_LO 0x0029
+#define regMMSCH_LAST_MEM_ACCESS_LO_BASE_IDX 0
+#define regMMSCH_SCRATCH_0 0x002b
+#define regMMSCH_SCRATCH_0_BASE_IDX 0
+#define regMMSCH_SCRATCH_1 0x002c
+#define regMMSCH_SCRATCH_1_BASE_IDX 0
+#define regMMSCH_GPUIOV_SCH_BLOCK_0 0x002d
+#define regMMSCH_GPUIOV_SCH_BLOCK_0_BASE_IDX 0
+#define regMMSCH_GPUIOV_CMD_CONTROL_0 0x002e
+#define regMMSCH_GPUIOV_CMD_CONTROL_0_BASE_IDX 0
+#define regMMSCH_GPUIOV_CMD_STATUS_0 0x002f
+#define regMMSCH_GPUIOV_CMD_STATUS_0_BASE_IDX 0
+#define regMMSCH_GPUIOV_VM_BUSY_STATUS_0 0x0030
+#define regMMSCH_GPUIOV_VM_BUSY_STATUS_0_BASE_IDX 0
+#define regMMSCH_GPUIOV_ACTIVE_FCNS_0 0x0031
+#define regMMSCH_GPUIOV_ACTIVE_FCNS_0_BASE_IDX 0
+#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_0 0x0032
+#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_0_BASE_IDX 0
+#define regMMSCH_GPUIOV_DW6_0 0x0033
+#define regMMSCH_GPUIOV_DW6_0_BASE_IDX 0
+#define regMMSCH_GPUIOV_DW7_0 0x0034
+#define regMMSCH_GPUIOV_DW7_0_BASE_IDX 0
+#define regMMSCH_GPUIOV_DW8_0 0x0035
+#define regMMSCH_GPUIOV_DW8_0_BASE_IDX 0
+#define regMMSCH_GPUIOV_SCH_BLOCK_1 0x0036
+#define regMMSCH_GPUIOV_SCH_BLOCK_1_BASE_IDX 0
+#define regMMSCH_GPUIOV_CMD_CONTROL_1 0x0037
+#define regMMSCH_GPUIOV_CMD_CONTROL_1_BASE_IDX 0
+#define regMMSCH_GPUIOV_CMD_STATUS_1 0x0038
+#define regMMSCH_GPUIOV_CMD_STATUS_1_BASE_IDX 0
+#define regMMSCH_GPUIOV_VM_BUSY_STATUS_1 0x0039
+#define regMMSCH_GPUIOV_VM_BUSY_STATUS_1_BASE_IDX 0
+#define regMMSCH_GPUIOV_ACTIVE_FCNS_1 0x003a
+#define regMMSCH_GPUIOV_ACTIVE_FCNS_1_BASE_IDX 0
+#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_1 0x003b
+#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_1_BASE_IDX 0
+#define regMMSCH_GPUIOV_DW6_1 0x003c
+#define regMMSCH_GPUIOV_DW6_1_BASE_IDX 0
+#define regMMSCH_GPUIOV_DW7_1 0x003d
+#define regMMSCH_GPUIOV_DW7_1_BASE_IDX 0
+#define regMMSCH_GPUIOV_DW8_1 0x003e
+#define regMMSCH_GPUIOV_DW8_1_BASE_IDX 0
+#define regMMSCH_GPUIOV_CNTXT 0x003f
+#define regMMSCH_GPUIOV_CNTXT_BASE_IDX 0
+#define regMMSCH_SCRATCH_2 0x0040
+#define regMMSCH_SCRATCH_2_BASE_IDX 0
+#define regMMSCH_SCRATCH_3 0x0041
+#define regMMSCH_SCRATCH_3_BASE_IDX 0
+#define regMMSCH_SCRATCH_4 0x0042
+#define regMMSCH_SCRATCH_4_BASE_IDX 0
+#define regMMSCH_SCRATCH_5 0x0043
+#define regMMSCH_SCRATCH_5_BASE_IDX 0
+#define regMMSCH_SCRATCH_6 0x0044
+#define regMMSCH_SCRATCH_6_BASE_IDX 0
+#define regMMSCH_SCRATCH_7 0x0045
+#define regMMSCH_SCRATCH_7_BASE_IDX 0
+#define regMMSCH_VFID_FIFO_HEAD_0 0x0046
+#define regMMSCH_VFID_FIFO_HEAD_0_BASE_IDX 0
+#define regMMSCH_VFID_FIFO_TAIL_0 0x0047
+#define regMMSCH_VFID_FIFO_TAIL_0_BASE_IDX 0
+#define regMMSCH_VFID_FIFO_HEAD_1 0x0048
+#define regMMSCH_VFID_FIFO_HEAD_1_BASE_IDX 0
+#define regMMSCH_VFID_FIFO_TAIL_1 0x0049
+#define regMMSCH_VFID_FIFO_TAIL_1_BASE_IDX 0
+#define regMMSCH_NACK_STATUS 0x004a
+#define regMMSCH_NACK_STATUS_BASE_IDX 0
+#define regMMSCH_VF_MAILBOX0_DATA 0x004b
+#define regMMSCH_VF_MAILBOX0_DATA_BASE_IDX 0
+#define regMMSCH_VF_MAILBOX1_DATA 0x004c
+#define regMMSCH_VF_MAILBOX1_DATA_BASE_IDX 0
+#define regMMSCH_GPUIOV_SCH_BLOCK_IP_0 0x004d
+#define regMMSCH_GPUIOV_SCH_BLOCK_IP_0_BASE_IDX 0
+#define regMMSCH_GPUIOV_CMD_STATUS_IP_0 0x004e
+#define regMMSCH_GPUIOV_CMD_STATUS_IP_0_BASE_IDX 0
+#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0 0x004f
+#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0_BASE_IDX 0
+#define regMMSCH_GPUIOV_SCH_BLOCK_IP_1 0x0050
+#define regMMSCH_GPUIOV_SCH_BLOCK_IP_1_BASE_IDX 0
+#define regMMSCH_GPUIOV_CMD_STATUS_IP_1 0x0051
+#define regMMSCH_GPUIOV_CMD_STATUS_IP_1_BASE_IDX 0
+#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1 0x0052
+#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1_BASE_IDX 0
+#define regMMSCH_GPUIOV_CNTXT_IP 0x0053
+#define regMMSCH_GPUIOV_CNTXT_IP_BASE_IDX 0
+#define regMMSCH_GPUIOV_SCH_BLOCK_2 0x0054
+#define regMMSCH_GPUIOV_SCH_BLOCK_2_BASE_IDX 0
+#define regMMSCH_GPUIOV_CMD_CONTROL_2 0x0055
+#define regMMSCH_GPUIOV_CMD_CONTROL_2_BASE_IDX 0
+#define regMMSCH_GPUIOV_CMD_STATUS_2 0x0056
+#define regMMSCH_GPUIOV_CMD_STATUS_2_BASE_IDX 0
+#define regMMSCH_GPUIOV_VM_BUSY_STATUS_2 0x0057
+#define regMMSCH_GPUIOV_VM_BUSY_STATUS_2_BASE_IDX 0
+#define regMMSCH_GPUIOV_ACTIVE_FCNS_2 0x0058
+#define regMMSCH_GPUIOV_ACTIVE_FCNS_2_BASE_IDX 0
+#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_2 0x0059
+#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_2_BASE_IDX 0
+#define regMMSCH_GPUIOV_DW6_2 0x005a
+#define regMMSCH_GPUIOV_DW6_2_BASE_IDX 0
+#define regMMSCH_GPUIOV_DW7_2 0x005b
+#define regMMSCH_GPUIOV_DW7_2_BASE_IDX 0
+#define regMMSCH_GPUIOV_DW8_2 0x005c
+#define regMMSCH_GPUIOV_DW8_2_BASE_IDX 0
+#define regMMSCH_GPUIOV_SCH_BLOCK_IP_2 0x005d
+#define regMMSCH_GPUIOV_SCH_BLOCK_IP_2_BASE_IDX 0
+#define regMMSCH_GPUIOV_CMD_STATUS_IP_2 0x005e
+#define regMMSCH_GPUIOV_CMD_STATUS_IP_2_BASE_IDX 0
+#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2 0x005f
+#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2_BASE_IDX 0
+#define regMMSCH_VFID_FIFO_HEAD_2 0x0060
+#define regMMSCH_VFID_FIFO_HEAD_2_BASE_IDX 0
+#define regMMSCH_VFID_FIFO_TAIL_2 0x0061
+#define regMMSCH_VFID_FIFO_TAIL_2_BASE_IDX 0
+#define regMMSCH_VM_BUSY_STATUS_0 0x0062
+#define regMMSCH_VM_BUSY_STATUS_0_BASE_IDX 0
+#define regMMSCH_VM_BUSY_STATUS_1 0x0063
+#define regMMSCH_VM_BUSY_STATUS_1_BASE_IDX 0
+#define regMMSCH_VM_BUSY_STATUS_2 0x0064
+#define regMMSCH_VM_BUSY_STATUS_2_BASE_IDX 0
+
+
+// addressBlock: uvd0_uvd_jmi_dec
+// base address: 0x1e500
+#define regUVD_JADP_MCIF_URGENT_CTRL 0x0141
+#define regUVD_JADP_MCIF_URGENT_CTRL_BASE_IDX 0
+#define regUVD_JMI_URGENT_CTRL 0x0142
+#define regUVD_JMI_URGENT_CTRL_BASE_IDX 0
+#define regUVD_JPEG_DEC_PF_CTRL 0x0143
+#define regUVD_JPEG_DEC_PF_CTRL_BASE_IDX 0
+#define regUVD_JPEG_ENC_PF_CTRL 0x0144
+#define regUVD_JPEG_ENC_PF_CTRL_BASE_IDX 0
+#define regUVD_JMI_CTRL 0x0145
+#define regUVD_JMI_CTRL_BASE_IDX 0
+#define regUVD_LMI_JRBC_CTRL 0x0146
+#define regUVD_LMI_JRBC_CTRL_BASE_IDX 0
+#define regUVD_LMI_JPEG_CTRL 0x0147
+#define regUVD_LMI_JPEG_CTRL_BASE_IDX 0
+#define regUVD_JMI_EJRBC_CTRL 0x0148
+#define regUVD_JMI_EJRBC_CTRL_BASE_IDX 0
+#define regUVD_LMI_EJPEG_CTRL 0x0149
+#define regUVD_LMI_EJPEG_CTRL_BASE_IDX 0
+#define regUVD_JMI_SCALER_CTRL 0x014a
+#define regUVD_JMI_SCALER_CTRL_BASE_IDX 0
+#define regJPEG_LMI_DROP 0x014b
+#define regJPEG_LMI_DROP_BASE_IDX 0
+#define regUVD_JMI_EJPEG_DROP 0x014c
+#define regUVD_JMI_EJPEG_DROP_BASE_IDX 0
+#define regJPEG_MEMCHECK_CLAMPING 0x014d
+#define regJPEG_MEMCHECK_CLAMPING_BASE_IDX 0
+#define regUVD_JMI_EJPEG_MEMCHECK_CLAMPING 0x014e
+#define regUVD_JMI_EJPEG_MEMCHECK_CLAMPING_BASE_IDX 0
+#define regUVD_LMI_JRBC_IB_VMID 0x014f
+#define regUVD_LMI_JRBC_IB_VMID_BASE_IDX 0
+#define regUVD_LMI_JRBC_RB_VMID 0x0150
+#define regUVD_LMI_JRBC_RB_VMID_BASE_IDX 0
+#define regUVD_LMI_JPEG_VMID 0x0151
+#define regUVD_LMI_JPEG_VMID_BASE_IDX 0
+#define regUVD_JMI_ENC_JRBC_IB_VMID 0x0152
+#define regUVD_JMI_ENC_JRBC_IB_VMID_BASE_IDX 0
+#define regUVD_JMI_ENC_JRBC_RB_VMID 0x0153
+#define regUVD_JMI_ENC_JRBC_RB_VMID_BASE_IDX 0
+#define regUVD_JMI_ENC_JPEG_VMID 0x0154
+#define regUVD_JMI_ENC_JPEG_VMID_BASE_IDX 0
+#define regUVD_JMI_EJPEG_RAS_CNTL 0x0156
+#define regUVD_JMI_EJPEG_RAS_CNTL_BASE_IDX 0
+#define regJPEG_MEMCHECK_SAFE_ADDR 0x0157
+#define regJPEG_MEMCHECK_SAFE_ADDR_BASE_IDX 0
+#define regJPEG_MEMCHECK_SAFE_ADDR_64BIT 0x0158
+#define regJPEG_MEMCHECK_SAFE_ADDR_64BIT_BASE_IDX 0
+#define regUVD_JMI_LAT_CTRL 0x0159
+#define regUVD_JMI_LAT_CTRL_BASE_IDX 0
+#define regUVD_JMI_LAT_CNTR 0x015a
+#define regUVD_JMI_LAT_CNTR_BASE_IDX 0
+#define regUVD_JMI_AVG_LAT_CNTR 0x015b
+#define regUVD_JMI_AVG_LAT_CNTR_BASE_IDX 0
+#define regUVD_JMI_PERFMON_CTRL 0x015c
+#define regUVD_JMI_PERFMON_CTRL_BASE_IDX 0
+#define regUVD_JMI_PERFMON_COUNT_LO 0x015d
+#define regUVD_JMI_PERFMON_COUNT_LO_BASE_IDX 0
+#define regUVD_JMI_PERFMON_COUNT_HI 0x015e
+#define regUVD_JMI_PERFMON_COUNT_HI_BASE_IDX 0
+#define regUVD_JMI_CLEAN_STATUS 0x015f
+#define regUVD_JMI_CLEAN_STATUS_BASE_IDX 0
+#define regUVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x0160
+#define regUVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX 0
+#define regUVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x0161
+#define regUVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX 0
+#define regUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x0162
+#define regUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX 0
+#define regUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x0163
+#define regUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX 0
+#define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0x0164
+#define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX 0
+#define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0x0165
+#define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX 0
+#define regUVD_LMI_JRBC_RB_64BIT_BAR_LOW 0x0166
+#define regUVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX 0
+#define regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH 0x0167
+#define regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX 0
+#define regUVD_LMI_JRBC_IB_64BIT_BAR_LOW 0x0168
+#define regUVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX 0
+#define regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH 0x0169
+#define regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX 0
+#define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 0x016a
+#define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0
+#define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x016b
+#define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0
+#define regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW 0x016c
+#define regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0
+#define regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH 0x016d
+#define regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0
+#define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 0x016e
+#define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0
+#define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 0x016f
+#define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0
+#define regUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW 0x0170
+#define regUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0
+#define regUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH 0x0171
+#define regUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0
+#define regUVD_JMI_PEL_RD_64BIT_BAR_LOW 0x0172
+#define regUVD_JMI_PEL_RD_64BIT_BAR_LOW_BASE_IDX 0
+#define regUVD_JMI_PEL_RD_64BIT_BAR_HIGH 0x0173
+#define regUVD_JMI_PEL_RD_64BIT_BAR_HIGH_BASE_IDX 0
+#define regUVD_JMI_BS_WR_64BIT_BAR_LOW 0x0174
+#define regUVD_JMI_BS_WR_64BIT_BAR_LOW_BASE_IDX 0
+#define regUVD_JMI_BS_WR_64BIT_BAR_HIGH 0x0175
+#define regUVD_JMI_BS_WR_64BIT_BAR_HIGH_BASE_IDX 0
+#define regUVD_JMI_SCALAR_RD_64BIT_BAR_LOW 0x0176
+#define regUVD_JMI_SCALAR_RD_64BIT_BAR_LOW_BASE_IDX 0
+#define regUVD_JMI_SCALAR_RD_64BIT_BAR_HIGH 0x0177
+#define regUVD_JMI_SCALAR_RD_64BIT_BAR_HIGH_BASE_IDX 0
+#define regUVD_JMI_SCALAR_WR_64BIT_BAR_LOW 0x0178
+#define regUVD_JMI_SCALAR_WR_64BIT_BAR_LOW_BASE_IDX 0
+#define regUVD_JMI_SCALAR_WR_64BIT_BAR_HIGH 0x0179
+#define regUVD_JMI_SCALAR_WR_64BIT_BAR_HIGH_BASE_IDX 0
+#define regUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0x017a
+#define regUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX 0
+#define regUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0x017b
+#define regUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX 0
+#define regUVD_LMI_EJRBC_RB_64BIT_BAR_LOW 0x017c
+#define regUVD_LMI_EJRBC_RB_64BIT_BAR_LOW_BASE_IDX 0
+#define regUVD_LMI_EJRBC_RB_64BIT_BAR_HIGH 0x017d
+#define regUVD_LMI_EJRBC_RB_64BIT_BAR_HIGH_BASE_IDX 0
+#define regUVD_LMI_EJRBC_IB_64BIT_BAR_LOW 0x017e
+#define regUVD_LMI_EJRBC_IB_64BIT_BAR_LOW_BASE_IDX 0
+#define regUVD_LMI_EJRBC_IB_64BIT_BAR_HIGH 0x017f
+#define regUVD_LMI_EJRBC_IB_64BIT_BAR_HIGH_BASE_IDX 0
+#define regUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW 0x0180
+#define regUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0
+#define regUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x0181
+#define regUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0
+#define regUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW 0x0182
+#define regUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0
+#define regUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH 0x0183
+#define regUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0
+#define regUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW 0x0184
+#define regUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0
+#define regUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH 0x0185
+#define regUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0
+#define regUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW 0x0186
+#define regUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0
+#define regUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH 0x0187
+#define regUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0
+#define regUVD_LMI_JPEG_PREEMPT_VMID 0x0188
+#define regUVD_LMI_JPEG_PREEMPT_VMID_BASE_IDX 0
+#define regUVD_LMI_ENC_JPEG_PREEMPT_VMID 0x0189
+#define regUVD_LMI_ENC_JPEG_PREEMPT_VMID_BASE_IDX 0
+#define regUVD_LMI_JPEG2_VMID 0x018a
+#define regUVD_LMI_JPEG2_VMID_BASE_IDX 0
+#define regUVD_LMI_JPEG2_READ_64BIT_BAR_LOW 0x018b
+#define regUVD_LMI_JPEG2_READ_64BIT_BAR_LOW_BASE_IDX 0
+#define regUVD_LMI_JPEG2_READ_64BIT_BAR_HIGH 0x018c
+#define regUVD_LMI_JPEG2_READ_64BIT_BAR_HIGH_BASE_IDX 0
+#define regUVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW 0x018d
+#define regUVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW_BASE_IDX 0
+#define regUVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH 0x018e
+#define regUVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH_BASE_IDX 0
+#define regUVD_LMI_JPEG_CTRL2 0x018f
+#define regUVD_LMI_JPEG_CTRL2_BASE_IDX 0
+#define regUVD_JMI_DEC_SWAP_CNTL 0x0190
+#define regUVD_JMI_DEC_SWAP_CNTL_BASE_IDX 0
+#define regUVD_JMI_ENC_SWAP_CNTL 0x0191
+#define regUVD_JMI_ENC_SWAP_CNTL_BASE_IDX 0
+#define regUVD_JMI_CNTL 0x0192
+#define regUVD_JMI_CNTL_BASE_IDX 0
+#define regUVD_JMI_ATOMIC_CNTL 0x0193
+#define regUVD_JMI_ATOMIC_CNTL_BASE_IDX 0
+#define regUVD_JMI_ATOMIC_CNTL2 0x0194
+#define regUVD_JMI_ATOMIC_CNTL2_BASE_IDX 0
+#define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW 0x0195
+#define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW_BASE_IDX 0
+#define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH 0x0196
+#define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH_BASE_IDX 0
+#define regUVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW 0x0197
+#define regUVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW_BASE_IDX 0
+#define regUVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH 0x0198
+#define regUVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH_BASE_IDX 0
+#define regJPEG2_LMI_DROP 0x0199
+#define regJPEG2_LMI_DROP_BASE_IDX 0
+#define regUVD_JMI_HUFF_FENCE_64BIT_BAR_LOW 0x019a
+#define regUVD_JMI_HUFF_FENCE_64BIT_BAR_LOW_BASE_IDX 0
+#define regUVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH 0x019b
+#define regUVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH_BASE_IDX 0
+#define regUVD_JMI_DEC_SWAP_CNTL2 0x019c
+#define regUVD_JMI_DEC_SWAP_CNTL2_BASE_IDX 0
+#define regUVD_JMI_DJPEG_RAS_CNTL 0x019f
+#define regUVD_JMI_DJPEG_RAS_CNTL_BASE_IDX 0
+
+
+// addressBlock: uvd0_uvd_jpeg_common_dec
+// base address: 0x1e700
+#define regJPEG_SOFT_RESET_STATUS 0x01c0
+#define regJPEG_SOFT_RESET_STATUS_BASE_IDX 0
+#define regJPEG_SYS_INT_EN 0x01c1
+#define regJPEG_SYS_INT_EN_BASE_IDX 0
+#define regJPEG_SYS_INT_STATUS 0x01c2
+#define regJPEG_SYS_INT_STATUS_BASE_IDX 0
+#define regJPEG_SYS_INT_ACK 0x01c3
+#define regJPEG_SYS_INT_ACK_BASE_IDX 0
+#define regJPEG_MEMCHECK_SYS_INT_EN 0x01c4
+#define regJPEG_MEMCHECK_SYS_INT_EN_BASE_IDX 0
+#define regJPEG_MEMCHECK_SYS_INT_STAT 0x01c5
+#define regJPEG_MEMCHECK_SYS_INT_STAT_BASE_IDX 0
+#define regJPEG_MEMCHECK_SYS_INT_ACK 0x01c6
+#define regJPEG_MEMCHECK_SYS_INT_ACK_BASE_IDX 0
+#define regJPEG_MASTINT_EN 0x01c8
+#define regJPEG_MASTINT_EN_BASE_IDX 0
+#define regJPEG_IH_CTRL 0x01c9
+#define regJPEG_IH_CTRL_BASE_IDX 0
+#define regJRBBM_ARB_CTRL 0x01cb
+#define regJRBBM_ARB_CTRL_BASE_IDX 0
+
+
+// addressBlock: uvd0_uvd_jpeg_common_sclk_dec
+// base address: 0x1e780
+#define regJPEG_CGC_GATE 0x01e0
+#define regJPEG_CGC_GATE_BASE_IDX 0
+#define regJPEG_CGC_CTRL 0x01e1
+#define regJPEG_CGC_CTRL_BASE_IDX 0
+#define regJPEG_CGC_STATUS 0x01e2
+#define regJPEG_CGC_STATUS_BASE_IDX 0
+#define regJPEG_COMN_CGC_MEM_CTRL 0x01e3
+#define regJPEG_COMN_CGC_MEM_CTRL_BASE_IDX 0
+#define regJPEG_DEC_CGC_MEM_CTRL 0x01e4
+#define regJPEG_DEC_CGC_MEM_CTRL_BASE_IDX 0
+#define regJPEG2_DEC_CGC_MEM_CTRL 0x01e5
+#define regJPEG2_DEC_CGC_MEM_CTRL_BASE_IDX 0
+#define regJPEG_ENC_CGC_MEM_CTRL 0x01e6
+#define regJPEG_ENC_CGC_MEM_CTRL_BASE_IDX 0
+#define regJPEG_SOFT_RESET2 0x01e7
+#define regJPEG_SOFT_RESET2_BASE_IDX 0
+#define regJPEG_PERF_BANK_CONF 0x01e8
+#define regJPEG_PERF_BANK_CONF_BASE_IDX 0
+#define regJPEG_PERF_BANK_EVENT_SEL 0x01e9
+#define regJPEG_PERF_BANK_EVENT_SEL_BASE_IDX 0
+#define regJPEG_PERF_BANK_COUNT0 0x01ea
+#define regJPEG_PERF_BANK_COUNT0_BASE_IDX 0
+#define regJPEG_PERF_BANK_COUNT1 0x01eb
+#define regJPEG_PERF_BANK_COUNT1_BASE_IDX 0
+#define regJPEG_PERF_BANK_COUNT2 0x01ec
+#define regJPEG_PERF_BANK_COUNT2_BASE_IDX 0
+#define regJPEG_PERF_BANK_COUNT3 0x01ed
+#define regJPEG_PERF_BANK_COUNT3_BASE_IDX 0
+
+
+// addressBlock: uvd0_uvd_jpeg_enc_dec
+// base address: 0x1e300
+#define regUVD_JPEG_ENC_INT_EN 0x00c1
+#define regUVD_JPEG_ENC_INT_EN_BASE_IDX 0
+#define regUVD_JPEG_ENC_INT_STATUS 0x00c2
+#define regUVD_JPEG_ENC_INT_STATUS_BASE_IDX 0
+#define regUVD_JPEG_ENC_ENGINE_CNTL 0x00c5
+#define regUVD_JPEG_ENC_ENGINE_CNTL_BASE_IDX 0
+#define regUVD_JPEG_ENC_SCRATCH1 0x00ce
+#define regUVD_JPEG_ENC_SCRATCH1_BASE_IDX 0
+
+
+// addressBlock: uvd0_uvd_jpeg_enc_sclk_dec
+// base address: 0x1e380
+#define regUVD_JPEG_ENC_SPS_INFO 0x00e0
+#define regUVD_JPEG_ENC_SPS_INFO_BASE_IDX 0
+#define regUVD_JPEG_ENC_SPS_INFO1 0x00e1
+#define regUVD_JPEG_ENC_SPS_INFO1_BASE_IDX 0
+#define regUVD_JPEG_ENC_TBL_SIZE 0x00e2
+#define regUVD_JPEG_ENC_TBL_SIZE_BASE_IDX 0
+#define regUVD_JPEG_ENC_TBL_CNTL 0x00e3
+#define regUVD_JPEG_ENC_TBL_CNTL_BASE_IDX 0
+#define regUVD_JPEG_ENC_MC_REQ_CNTL 0x00e4
+#define regUVD_JPEG_ENC_MC_REQ_CNTL_BASE_IDX 0
+#define regUVD_JPEG_ENC_STATUS 0x00e5
+#define regUVD_JPEG_ENC_STATUS_BASE_IDX 0
+#define regUVD_JPEG_ENC_PITCH 0x00e6
+#define regUVD_JPEG_ENC_PITCH_BASE_IDX 0
+#define regUVD_JPEG_ENC_LUMA_BASE 0x00e7
+#define regUVD_JPEG_ENC_LUMA_BASE_BASE_IDX 0
+#define regUVD_JPEG_ENC_CHROMAU_BASE 0x00e8
+#define regUVD_JPEG_ENC_CHROMAU_BASE_BASE_IDX 0
+#define regUVD_JPEG_ENC_CHROMAV_BASE 0x00e9
+#define regUVD_JPEG_ENC_CHROMAV_BASE_BASE_IDX 0
+#define regJPEG_ENC_Y_GFX10_TILING_SURFACE 0x00ea
+#define regJPEG_ENC_Y_GFX10_TILING_SURFACE_BASE_IDX 0
+#define regJPEG_ENC_UV_GFX10_TILING_SURFACE 0x00eb
+#define regJPEG_ENC_UV_GFX10_TILING_SURFACE_BASE_IDX 0
+#define regJPEG_ENC_GFX10_ADDR_CONFIG 0x00ec
+#define regJPEG_ENC_GFX10_ADDR_CONFIG_BASE_IDX 0
+#define regJPEG_ENC_ADDR_MODE 0x00ed
+#define regJPEG_ENC_ADDR_MODE_BASE_IDX 0
+#define regUVD_JPEG_ENC_GPCOM_CMD 0x00ee
+#define regUVD_JPEG_ENC_GPCOM_CMD_BASE_IDX 0
+#define regUVD_JPEG_ENC_GPCOM_DATA0 0x00ef
+#define regUVD_JPEG_ENC_GPCOM_DATA0_BASE_IDX 0
+#define regUVD_JPEG_ENC_GPCOM_DATA1 0x00f0
+#define regUVD_JPEG_ENC_GPCOM_DATA1_BASE_IDX 0
+#define regUVD_JPEG_TBL_DAT0 0x00f1
+#define regUVD_JPEG_TBL_DAT0_BASE_IDX 0
+#define regUVD_JPEG_TBL_DAT1 0x00f2
+#define regUVD_JPEG_TBL_DAT1_BASE_IDX 0
+#define regUVD_JPEG_TBL_IDX 0x00f3
+#define regUVD_JPEG_TBL_IDX_BASE_IDX 0
+#define regUVD_JPEG_ENC_CGC_CNTL 0x00f5
+#define regUVD_JPEG_ENC_CGC_CNTL_BASE_IDX 0
+#define regUVD_JPEG_ENC_SCRATCH0 0x00f6
+#define regUVD_JPEG_ENC_SCRATCH0_BASE_IDX 0
+#define regUVD_JPEG_ENC_SOFT_RST 0x00f7
+#define regUVD_JPEG_ENC_SOFT_RST_BASE_IDX 0
+
+
+// addressBlock: uvd0_uvd_jrbc_dec
+// base address: 0x1e400
+#define regUVD_JRBC_RB_WPTR 0x0100
+#define regUVD_JRBC_RB_WPTR_BASE_IDX 0
+#define regUVD_JRBC_RB_CNTL 0x0101
+#define regUVD_JRBC_RB_CNTL_BASE_IDX 0
+#define regUVD_JRBC_IB_SIZE 0x0102
+#define regUVD_JRBC_IB_SIZE_BASE_IDX 0
+#define regUVD_JRBC_URGENT_CNTL 0x0103
+#define regUVD_JRBC_URGENT_CNTL_BASE_IDX 0
+#define regUVD_JRBC_RB_REF_DATA 0x0104
+#define regUVD_JRBC_RB_REF_DATA_BASE_IDX 0
+#define regUVD_JRBC_RB_COND_RD_TIMER 0x0105
+#define regUVD_JRBC_RB_COND_RD_TIMER_BASE_IDX 0
+#define regUVD_JRBC_SOFT_RESET 0x0108
+#define regUVD_JRBC_SOFT_RESET_BASE_IDX 0
+#define regUVD_JRBC_STATUS 0x0109
+#define regUVD_JRBC_STATUS_BASE_IDX 0
+#define regUVD_JRBC_RB_RPTR 0x010a
+#define regUVD_JRBC_RB_RPTR_BASE_IDX 0
+#define regUVD_JRBC_RB_BUF_STATUS 0x010b
+#define regUVD_JRBC_RB_BUF_STATUS_BASE_IDX 0
+#define regUVD_JRBC_IB_BUF_STATUS 0x010c
+#define regUVD_JRBC_IB_BUF_STATUS_BASE_IDX 0
+#define regUVD_JRBC_IB_SIZE_UPDATE 0x010d
+#define regUVD_JRBC_IB_SIZE_UPDATE_BASE_IDX 0
+#define regUVD_JRBC_IB_COND_RD_TIMER 0x010e
+#define regUVD_JRBC_IB_COND_RD_TIMER_BASE_IDX 0
+#define regUVD_JRBC_IB_REF_DATA 0x010f
+#define regUVD_JRBC_IB_REF_DATA_BASE_IDX 0
+#define regUVD_JPEG_PREEMPT_CMD 0x0110
+#define regUVD_JPEG_PREEMPT_CMD_BASE_IDX 0
+#define regUVD_JPEG_PREEMPT_FENCE_DATA0 0x0111
+#define regUVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX 0
+#define regUVD_JPEG_PREEMPT_FENCE_DATA1 0x0112
+#define regUVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX 0
+#define regUVD_JRBC_RB_SIZE 0x0113
+#define regUVD_JRBC_RB_SIZE_BASE_IDX 0
+#define regUVD_JRBC_SCRATCH0 0x0114
+#define regUVD_JRBC_SCRATCH0_BASE_IDX 0
+
+
+// addressBlock: uvd0_uvd_jrbc_enc_dec
+// base address: 0x1e480
+#define regUVD_JRBC_ENC_RB_WPTR 0x0120
+#define regUVD_JRBC_ENC_RB_WPTR_BASE_IDX 0
+#define regUVD_JRBC_ENC_RB_CNTL 0x0121
+#define regUVD_JRBC_ENC_RB_CNTL_BASE_IDX 0
+#define regUVD_JRBC_ENC_IB_SIZE 0x0122
+#define regUVD_JRBC_ENC_IB_SIZE_BASE_IDX 0
+#define regUVD_JRBC_ENC_URGENT_CNTL 0x0123
+#define regUVD_JRBC_ENC_URGENT_CNTL_BASE_IDX 0
+#define regUVD_JRBC_ENC_RB_REF_DATA 0x0124
+#define regUVD_JRBC_ENC_RB_REF_DATA_BASE_IDX 0
+#define regUVD_JRBC_ENC_RB_COND_RD_TIMER 0x0125
+#define regUVD_JRBC_ENC_RB_COND_RD_TIMER_BASE_IDX 0
+#define regUVD_JRBC_ENC_SOFT_RESET 0x0128
+#define regUVD_JRBC_ENC_SOFT_RESET_BASE_IDX 0
+#define regUVD_JRBC_ENC_STATUS 0x0129
+#define regUVD_JRBC_ENC_STATUS_BASE_IDX 0
+#define regUVD_JRBC_ENC_RB_RPTR 0x012a
+#define regUVD_JRBC_ENC_RB_RPTR_BASE_IDX 0
+#define regUVD_JRBC_ENC_RB_BUF_STATUS 0x012b
+#define regUVD_JRBC_ENC_RB_BUF_STATUS_BASE_IDX 0
+#define regUVD_JRBC_ENC_IB_BUF_STATUS 0x012c
+#define regUVD_JRBC_ENC_IB_BUF_STATUS_BASE_IDX 0
+#define regUVD_JRBC_ENC_IB_SIZE_UPDATE 0x012d
+#define regUVD_JRBC_ENC_IB_SIZE_UPDATE_BASE_IDX 0
+#define regUVD_JRBC_ENC_IB_COND_RD_TIMER 0x012e
+#define regUVD_JRBC_ENC_IB_COND_RD_TIMER_BASE_IDX 0
+#define regUVD_JRBC_ENC_IB_REF_DATA 0x012f
+#define regUVD_JRBC_ENC_IB_REF_DATA_BASE_IDX 0
+#define regUVD_JPEG_ENC_PREEMPT_CMD 0x0130
+#define regUVD_JPEG_ENC_PREEMPT_CMD_BASE_IDX 0
+#define regUVD_JPEG_ENC_PREEMPT_FENCE_DATA0 0x0131
+#define regUVD_JPEG_ENC_PREEMPT_FENCE_DATA0_BASE_IDX 0
+#define regUVD_JPEG_ENC_PREEMPT_FENCE_DATA1 0x0132
+#define regUVD_JPEG_ENC_PREEMPT_FENCE_DATA1_BASE_IDX 0
+#define regUVD_JRBC_ENC_RB_SIZE 0x0133
+#define regUVD_JRBC_ENC_RB_SIZE_BASE_IDX 0
+#define regUVD_JRBC_ENC_SCRATCH0 0x0134
+#define regUVD_JRBC_ENC_SCRATCH0_BASE_IDX 0
+
+
+// addressBlock: uvd0_uvd_mpcdec
+// base address: 0x20310
+#define regUVD_MP_SWAP_CNTL 0x02c4
+#define regUVD_MP_SWAP_CNTL_BASE_IDX 1
+#define regUVD_MP_SWAP_CNTL2 0x02c5
+#define regUVD_MP_SWAP_CNTL2_BASE_IDX 1
+#define regUVD_MPC_LUMA_SRCH 0x02c6
+#define regUVD_MPC_LUMA_SRCH_BASE_IDX 1
+#define regUVD_MPC_LUMA_HIT 0x02c7
+#define regUVD_MPC_LUMA_HIT_BASE_IDX 1
+#define regUVD_MPC_LUMA_HITPEND 0x02c8
+#define regUVD_MPC_LUMA_HITPEND_BASE_IDX 1
+#define regUVD_MPC_CHROMA_SRCH 0x02c9
+#define regUVD_MPC_CHROMA_SRCH_BASE_IDX 1
+#define regUVD_MPC_CHROMA_HIT 0x02ca
+#define regUVD_MPC_CHROMA_HIT_BASE_IDX 1
+#define regUVD_MPC_CHROMA_HITPEND 0x02cb
+#define regUVD_MPC_CHROMA_HITPEND_BASE_IDX 1
+#define regUVD_MPC_CNTL 0x02cc
+#define regUVD_MPC_CNTL_BASE_IDX 1
+#define regUVD_MPC_PITCH 0x02cd
+#define regUVD_MPC_PITCH_BASE_IDX 1
+#define regUVD_MPC_SET_MUXA0 0x02ce
+#define regUVD_MPC_SET_MUXA0_BASE_IDX 1
+#define regUVD_MPC_SET_MUXA1 0x02cf
+#define regUVD_MPC_SET_MUXA1_BASE_IDX 1
+#define regUVD_MPC_SET_MUXB0 0x02d0
+#define regUVD_MPC_SET_MUXB0_BASE_IDX 1
+#define regUVD_MPC_SET_MUXB1 0x02d1
+#define regUVD_MPC_SET_MUXB1_BASE_IDX 1
+#define regUVD_MPC_SET_MUX 0x02d2
+#define regUVD_MPC_SET_MUX_BASE_IDX 1
+#define regUVD_MPC_SET_ALU 0x02d3
+#define regUVD_MPC_SET_ALU_BASE_IDX 1
+#define regUVD_MPC_PERF0 0x02d4
+#define regUVD_MPC_PERF0_BASE_IDX 1
+#define regUVD_MPC_PERF1 0x02d5
+#define regUVD_MPC_PERF1_BASE_IDX 1
+#define regUVD_MPC_IND_INDEX 0x02d6
+#define regUVD_MPC_IND_INDEX_BASE_IDX 1
+#define regUVD_MPC_IND_DATA 0x02d7
+#define regUVD_MPC_IND_DATA_BASE_IDX 1
+
+
+// addressBlock: uvd0_uvd_pg_dec
+// base address: 0x1f800
+#define regUVD_PGFSM_CONFIG 0x0000
+#define regUVD_PGFSM_CONFIG_BASE_IDX 1
+#define regUVD_PGFSM_STATUS 0x0001
+#define regUVD_PGFSM_STATUS_BASE_IDX 1
+#define regUVD_POWER_STATUS 0x0004
+#define regUVD_POWER_STATUS_BASE_IDX 1
+#define regUVD_PG_IND_INDEX 0x0005
+#define regUVD_PG_IND_INDEX_BASE_IDX 1
+#define regUVD_PG_IND_DATA 0x0006
+#define regUVD_PG_IND_DATA_BASE_IDX 1
+#define regCC_UVD_HARVESTING 0x0007
+#define regCC_UVD_HARVESTING_BASE_IDX 1
+#define regUVD_JPEG_POWER_STATUS 0x000a
+#define regUVD_JPEG_POWER_STATUS_BASE_IDX 1
+#define regUVD_DPG_LMA_CTL 0x0011
+#define regUVD_DPG_LMA_CTL_BASE_IDX 1
+#define regUVD_DPG_LMA_DATA 0x0012
+#define regUVD_DPG_LMA_DATA_BASE_IDX 1
+#define regUVD_DPG_LMA_MASK 0x0013
+#define regUVD_DPG_LMA_MASK_BASE_IDX 1
+#define regUVD_DPG_PAUSE 0x0014
+#define regUVD_DPG_PAUSE_BASE_IDX 1
+#define regUVD_SCRATCH1 0x0015
+#define regUVD_SCRATCH1_BASE_IDX 1
+#define regUVD_SCRATCH2 0x0016
+#define regUVD_SCRATCH2_BASE_IDX 1
+#define regUVD_SCRATCH3 0x0017
+#define regUVD_SCRATCH3_BASE_IDX 1
+#define regUVD_SCRATCH4 0x0018
+#define regUVD_SCRATCH4_BASE_IDX 1
+#define regUVD_SCRATCH5 0x0019
+#define regUVD_SCRATCH5_BASE_IDX 1
+#define regUVD_SCRATCH6 0x001a
+#define regUVD_SCRATCH6_BASE_IDX 1
+#define regUVD_SCRATCH7 0x001b
+#define regUVD_SCRATCH7_BASE_IDX 1
+#define regUVD_SCRATCH8 0x001c
+#define regUVD_SCRATCH8_BASE_IDX 1
+#define regUVD_SCRATCH9 0x001d
+#define regUVD_SCRATCH9_BASE_IDX 1
+#define regUVD_SCRATCH10 0x001e
+#define regUVD_SCRATCH10_BASE_IDX 1
+#define regUVD_SCRATCH11 0x001f
+#define regUVD_SCRATCH11_BASE_IDX 1
+#define regUVD_SCRATCH12 0x0020
+#define regUVD_SCRATCH12_BASE_IDX 1
+#define regUVD_SCRATCH13 0x0021
+#define regUVD_SCRATCH13_BASE_IDX 1
+#define regUVD_SCRATCH14 0x0022
+#define regUVD_SCRATCH14_BASE_IDX 1
+#define regUVD_FREE_COUNTER_REG 0x0024
+#define regUVD_FREE_COUNTER_REG_BASE_IDX 1
+#define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x0025
+#define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1
+#define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x0026
+#define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1
+#define regUVD_DPG_VCPU_CACHE_OFFSET0 0x0027
+#define regUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX 1
+#define regUVD_DPG_LMI_VCPU_CACHE_VMID 0x0028
+#define regUVD_DPG_LMI_VCPU_CACHE_VMID_BASE_IDX 1
+#define regUVD_PF_STATUS 0x0039
+#define regUVD_PF_STATUS_BASE_IDX 1
+#define regUVD_FW_VERSION 0x003a
+#define regUVD_FW_VERSION_BASE_IDX 1
+#define regUVD_DPG_CLK_EN_VCPU_REPORT 0x003c
+#define regUVD_DPG_CLK_EN_VCPU_REPORT_BASE_IDX 1
+#define regUVD_GFX8_ADDR_CONFIG 0x0049
+#define regUVD_GFX8_ADDR_CONFIG_BASE_IDX 1
+#define regUVD_GFX10_ADDR_CONFIG 0x004a
+#define regUVD_GFX10_ADDR_CONFIG_BASE_IDX 1
+#define regUVD_GPCNT2_CNTL 0x004b
+#define regUVD_GPCNT2_CNTL_BASE_IDX 1
+#define regUVD_GPCNT2_TARGET_LOWER 0x004c
+#define regUVD_GPCNT2_TARGET_LOWER_BASE_IDX 1
+#define regUVD_GPCNT2_STATUS_LOWER 0x004d
+#define regUVD_GPCNT2_STATUS_LOWER_BASE_IDX 1
+#define regUVD_GPCNT2_TARGET_UPPER 0x004e
+#define regUVD_GPCNT2_TARGET_UPPER_BASE_IDX 1
+#define regUVD_GPCNT2_STATUS_UPPER 0x004f
+#define regUVD_GPCNT2_STATUS_UPPER_BASE_IDX 1
+#define regUVD_GPCNT3_CNTL 0x0050
+#define regUVD_GPCNT3_CNTL_BASE_IDX 1
+#define regUVD_GPCNT3_TARGET_LOWER 0x0051
+#define regUVD_GPCNT3_TARGET_LOWER_BASE_IDX 1
+#define regUVD_GPCNT3_STATUS_LOWER 0x0052
+#define regUVD_GPCNT3_STATUS_LOWER_BASE_IDX 1
+#define regUVD_GPCNT3_TARGET_UPPER 0x0053
+#define regUVD_GPCNT3_TARGET_UPPER_BASE_IDX 1
+#define regUVD_GPCNT3_STATUS_UPPER 0x0054
+#define regUVD_GPCNT3_STATUS_UPPER_BASE_IDX 1
+#define regUVD_VCLK_DS_CNTL 0x0055
+#define regUVD_VCLK_DS_CNTL_BASE_IDX 1
+#define regUVD_DCLK_DS_CNTL 0x0056
+#define regUVD_DCLK_DS_CNTL_BASE_IDX 1
+#define regUVD_RAS_VCPU_VCODEC_STATUS 0x0057
+#define regUVD_RAS_VCPU_VCODEC_STATUS_BASE_IDX 1
+#define regUVD_RAS_MMSCH_FATAL_ERROR 0x0058
+#define regUVD_RAS_MMSCH_FATAL_ERROR_BASE_IDX 1
+#define regUVD_RAS_JPEG0_STATUS 0x0059
+#define regUVD_RAS_JPEG0_STATUS_BASE_IDX 1
+#define regUVD_RAS_JPEG1_STATUS 0x005a
+#define regUVD_RAS_JPEG1_STATUS_BASE_IDX 1
+#define regUVD_RAS_CNTL_PMI_ARB 0x005b
+#define regUVD_RAS_CNTL_PMI_ARB_BASE_IDX 1
+
+
+// addressBlock: uvd0_uvd_rbcdec
+// base address: 0x20370
+#define regUVD_RBC_IB_SIZE 0x02dc
+#define regUVD_RBC_IB_SIZE_BASE_IDX 1
+#define regUVD_RBC_IB_SIZE_UPDATE 0x02dd
+#define regUVD_RBC_IB_SIZE_UPDATE_BASE_IDX 1
+#define regUVD_RBC_RB_CNTL 0x02de
+#define regUVD_RBC_RB_CNTL_BASE_IDX 1
+#define regUVD_RBC_RB_RPTR_ADDR 0x02df
+#define regUVD_RBC_RB_RPTR_ADDR_BASE_IDX 1
+#define regUVD_RBC_RB_RPTR 0x02e0
+#define regUVD_RBC_RB_RPTR_BASE_IDX 1
+#define regUVD_RBC_RB_WPTR 0x02e1
+#define regUVD_RBC_RB_WPTR_BASE_IDX 1
+#define regUVD_RBC_VCPU_ACCESS 0x02e2
+#define regUVD_RBC_VCPU_ACCESS_BASE_IDX 1
+#define regUVD_FW_SEMAPHORE_CNTL 0x02e3
+#define regUVD_FW_SEMAPHORE_CNTL_BASE_IDX 1
+#define regUVD_RBC_READ_REQ_URGENT_CNTL 0x02e5
+#define regUVD_RBC_READ_REQ_URGENT_CNTL_BASE_IDX 1
+#define regUVD_RBC_RB_WPTR_CNTL 0x02e6
+#define regUVD_RBC_RB_WPTR_CNTL_BASE_IDX 1
+#define regUVD_RBC_WPTR_STATUS 0x02e7
+#define regUVD_RBC_WPTR_STATUS_BASE_IDX 1
+#define regUVD_RBC_WPTR_POLL_CNTL 0x02e8
+#define regUVD_RBC_WPTR_POLL_CNTL_BASE_IDX 1
+#define regUVD_RBC_WPTR_POLL_ADDR 0x02e9
+#define regUVD_RBC_WPTR_POLL_ADDR_BASE_IDX 1
+#define regUVD_SEMA_CMD 0x02ea
+#define regUVD_SEMA_CMD_BASE_IDX 1
+#define regUVD_SEMA_ADDR_LOW 0x02eb
+#define regUVD_SEMA_ADDR_LOW_BASE_IDX 1
+#define regUVD_SEMA_ADDR_HIGH 0x02ec
+#define regUVD_SEMA_ADDR_HIGH_BASE_IDX 1
+#define regUVD_ENGINE_CNTL 0x02ed
+#define regUVD_ENGINE_CNTL_BASE_IDX 1
+#define regUVD_SEMA_TIMEOUT_STATUS 0x02ee
+#define regUVD_SEMA_TIMEOUT_STATUS_BASE_IDX 1
+#define regUVD_SEMA_CNTL 0x02ef
+#define regUVD_SEMA_CNTL_BASE_IDX 1
+#define regUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x02f0
+#define regUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1
+#define regUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x02f1
+#define regUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL_BASE_IDX 1
+#define regUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x02f2
+#define regUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1
+#define regUVD_JOB_START 0x02f3
+#define regUVD_JOB_START_BASE_IDX 1
+#define regUVD_RBC_BUF_STATUS 0x02f4
+#define regUVD_RBC_BUF_STATUS_BASE_IDX 1
+#define regUVD_RBC_SWAP_CNTL 0x02f5
+#define regUVD_RBC_SWAP_CNTL_BASE_IDX 1
+
+
+// addressBlock: uvd0_uvddec
+// base address: 0x1fa00
+#define regUVD_STATUS 0x0080
+#define regUVD_STATUS_BASE_IDX 1
+#define regUVD_ENC_PIPE_BUSY 0x0081
+#define regUVD_ENC_PIPE_BUSY_BASE_IDX 1
+#define regUVD_FW_POWER_STATUS 0x0082
+#define regUVD_FW_POWER_STATUS_BASE_IDX 1
+#define regUVD_CNTL 0x0083
+#define regUVD_CNTL_BASE_IDX 1
+#define regUVD_SOFT_RESET 0x0084
+#define regUVD_SOFT_RESET_BASE_IDX 1
+#define regUVD_SOFT_RESET2 0x0085
+#define regUVD_SOFT_RESET2_BASE_IDX 1
+#define regUVD_MMSCH_SOFT_RESET 0x0086
+#define regUVD_MMSCH_SOFT_RESET_BASE_IDX 1
+#define regUVD_WIG_CTRL 0x0087
+#define regUVD_WIG_CTRL_BASE_IDX 1
+#define regUVD_CGC_GATE 0x0088
+#define regUVD_CGC_GATE_BASE_IDX 1
+#define regUVD_CGC_STATUS 0x0089
+#define regUVD_CGC_STATUS_BASE_IDX 1
+#define regUVD_CGC_CTRL 0x008a
+#define regUVD_CGC_CTRL_BASE_IDX 1
+#define regUVD_CGC_UDEC_STATUS 0x008b
+#define regUVD_CGC_UDEC_STATUS_BASE_IDX 1
+#define regUVD_SUVD_CGC_GATE 0x008c
+#define regUVD_SUVD_CGC_GATE_BASE_IDX 1
+#define regUVD_SUVD_CGC_STATUS 0x008d
+#define regUVD_SUVD_CGC_STATUS_BASE_IDX 1
+#define regUVD_SUVD_CGC_CTRL 0x008e
+#define regUVD_SUVD_CGC_CTRL_BASE_IDX 1
+#define regUVD_GPCOM_VCPU_CMD 0x008f
+#define regUVD_GPCOM_VCPU_CMD_BASE_IDX 1
+#define regUVD_GPCOM_VCPU_DATA0 0x0090
+#define regUVD_GPCOM_VCPU_DATA0_BASE_IDX 1
+#define regUVD_GPCOM_VCPU_DATA1 0x0091
+#define regUVD_GPCOM_VCPU_DATA1_BASE_IDX 1
+#define regUVD_GPCOM_SYS_CMD 0x0092
+#define regUVD_GPCOM_SYS_CMD_BASE_IDX 1
+#define regUVD_GPCOM_SYS_DATA0 0x0093
+#define regUVD_GPCOM_SYS_DATA0_BASE_IDX 1
+#define regUVD_GPCOM_SYS_DATA1 0x0094
+#define regUVD_GPCOM_SYS_DATA1_BASE_IDX 1
+#define regUVD_VCPU_INT_EN 0x0095
+#define regUVD_VCPU_INT_EN_BASE_IDX 1
+#define regUVD_VCPU_INT_STATUS 0x0096
+#define regUVD_VCPU_INT_STATUS_BASE_IDX 1
+#define regUVD_VCPU_INT_ACK 0x0097
+#define regUVD_VCPU_INT_ACK_BASE_IDX 1
+#define regUVD_VCPU_INT_ROUTE 0x0098
+#define regUVD_VCPU_INT_ROUTE_BASE_IDX 1
+#define regUVD_DRV_FW_MSG 0x0099
+#define regUVD_DRV_FW_MSG_BASE_IDX 1
+#define regUVD_FW_DRV_MSG_ACK 0x009a
+#define regUVD_FW_DRV_MSG_ACK_BASE_IDX 1
+#define regUVD_SUVD_INT_EN 0x009b
+#define regUVD_SUVD_INT_EN_BASE_IDX 1
+#define regUVD_SUVD_INT_STATUS 0x009c
+#define regUVD_SUVD_INT_STATUS_BASE_IDX 1
+#define regUVD_SUVD_INT_ACK 0x009d
+#define regUVD_SUVD_INT_ACK_BASE_IDX 1
+#define regUVD_ENC_VCPU_INT_EN 0x009e
+#define regUVD_ENC_VCPU_INT_EN_BASE_IDX 1
+#define regUVD_ENC_VCPU_INT_STATUS 0x009f
+#define regUVD_ENC_VCPU_INT_STATUS_BASE_IDX 1
+#define regUVD_ENC_VCPU_INT_ACK 0x00a0
+#define regUVD_ENC_VCPU_INT_ACK_BASE_IDX 1
+#define regUVD_MASTINT_EN 0x00a1
+#define regUVD_MASTINT_EN_BASE_IDX 1
+#define regUVD_SYS_INT_EN 0x00a2
+#define regUVD_SYS_INT_EN_BASE_IDX 1
+#define regUVD_SYS_INT_STATUS 0x00a3
+#define regUVD_SYS_INT_STATUS_BASE_IDX 1
+#define regUVD_SYS_INT_ACK 0x00a4
+#define regUVD_SYS_INT_ACK_BASE_IDX 1
+#define regUVD_JOB_DONE 0x00a5
+#define regUVD_JOB_DONE_BASE_IDX 1
+#define regUVD_CBUF_ID 0x00a6
+#define regUVD_CBUF_ID_BASE_IDX 1
+#define regUVD_CONTEXT_ID 0x00a7
+#define regUVD_CONTEXT_ID_BASE_IDX 1
+#define regUVD_CONTEXT_ID2 0x00a8
+#define regUVD_CONTEXT_ID2_BASE_IDX 1
+#define regUVD_NO_OP 0x00a9
+#define regUVD_NO_OP_BASE_IDX 1
+#define regUVD_RB_BASE_LO 0x00aa
+#define regUVD_RB_BASE_LO_BASE_IDX 1
+#define regUVD_RB_BASE_HI 0x00ab
+#define regUVD_RB_BASE_HI_BASE_IDX 1
+#define regUVD_RB_SIZE 0x00ac
+#define regUVD_RB_SIZE_BASE_IDX 1
+#define regUVD_RB_RPTR 0x00ad
+#define regUVD_RB_RPTR_BASE_IDX 1
+#define regUVD_RB_WPTR 0x00ae
+#define regUVD_RB_WPTR_BASE_IDX 1
+#define regUVD_RB_BASE_LO2 0x00af
+#define regUVD_RB_BASE_LO2_BASE_IDX 1
+#define regUVD_RB_BASE_HI2 0x00b0
+#define regUVD_RB_BASE_HI2_BASE_IDX 1
+#define regUVD_RB_SIZE2 0x00b1
+#define regUVD_RB_SIZE2_BASE_IDX 1
+#define regUVD_RB_RPTR2 0x00b2
+#define regUVD_RB_RPTR2_BASE_IDX 1
+#define regUVD_RB_WPTR2 0x00b3
+#define regUVD_RB_WPTR2_BASE_IDX 1
+#define regUVD_RB_BASE_LO3 0x00b4
+#define regUVD_RB_BASE_LO3_BASE_IDX 1
+#define regUVD_RB_BASE_HI3 0x00b5
+#define regUVD_RB_BASE_HI3_BASE_IDX 1
+#define regUVD_RB_SIZE3 0x00b6
+#define regUVD_RB_SIZE3_BASE_IDX 1
+#define regUVD_RB_RPTR3 0x00b7
+#define regUVD_RB_RPTR3_BASE_IDX 1
+#define regUVD_RB_WPTR3 0x00b8
+#define regUVD_RB_WPTR3_BASE_IDX 1
+#define regUVD_RB_BASE_LO4 0x00b9
+#define regUVD_RB_BASE_LO4_BASE_IDX 1
+#define regUVD_RB_BASE_HI4 0x00ba
+#define regUVD_RB_BASE_HI4_BASE_IDX 1
+#define regUVD_RB_SIZE4 0x00bb
+#define regUVD_RB_SIZE4_BASE_IDX 1
+#define regUVD_RB_RPTR4 0x00bc
+#define regUVD_RB_RPTR4_BASE_IDX 1
+#define regUVD_RB_WPTR4 0x00bd
+#define regUVD_RB_WPTR4_BASE_IDX 1
+#define regUVD_OUT_RB_BASE_LO 0x00be
+#define regUVD_OUT_RB_BASE_LO_BASE_IDX 1
+#define regUVD_OUT_RB_BASE_HI 0x00bf
+#define regUVD_OUT_RB_BASE_HI_BASE_IDX 1
+#define regUVD_OUT_RB_SIZE 0x00c0
+#define regUVD_OUT_RB_SIZE_BASE_IDX 1
+#define regUVD_OUT_RB_RPTR 0x00c1
+#define regUVD_OUT_RB_RPTR_BASE_IDX 1
+#define regUVD_OUT_RB_WPTR 0x00c2
+#define regUVD_OUT_RB_WPTR_BASE_IDX 1
+#define regUVD_IOV_MAILBOX 0x00c4
+#define regUVD_IOV_MAILBOX_BASE_IDX 1
+#define regUVD_IOV_MAILBOX_RESP 0x00c5
+#define regUVD_IOV_MAILBOX_RESP_BASE_IDX 1
+#define regUVD_RB_ARB_CTRL 0x00c6
+#define regUVD_RB_ARB_CTRL_BASE_IDX 1
+#define regUVD_CTX_INDEX 0x00c7
+#define regUVD_CTX_INDEX_BASE_IDX 1
+#define regUVD_CTX_DATA 0x00c8
+#define regUVD_CTX_DATA_BASE_IDX 1
+#define regUVD_CXW_WR 0x00c9
+#define regUVD_CXW_WR_BASE_IDX 1
+#define regUVD_CXW_WR_INT_ID 0x00ca
+#define regUVD_CXW_WR_INT_ID_BASE_IDX 1
+#define regUVD_CXW_WR_INT_CTX_ID 0x00cb
+#define regUVD_CXW_WR_INT_CTX_ID_BASE_IDX 1
+#define regUVD_CXW_INT_ID 0x00cc
+#define regUVD_CXW_INT_ID_BASE_IDX 1
+#define regUVD_MPEG2_ERROR 0x00cd
+#define regUVD_MPEG2_ERROR_BASE_IDX 1
+#define regUVD_TOP_CTRL 0x00cf
+#define regUVD_TOP_CTRL_BASE_IDX 1
+#define regUVD_YBASE 0x00d0
+#define regUVD_YBASE_BASE_IDX 1
+#define regUVD_UVBASE 0x00d1
+#define regUVD_UVBASE_BASE_IDX 1
+#define regUVD_PITCH 0x00d2
+#define regUVD_PITCH_BASE_IDX 1
+#define regUVD_WIDTH 0x00d3
+#define regUVD_WIDTH_BASE_IDX 1
+#define regUVD_HEIGHT 0x00d4
+#define regUVD_HEIGHT_BASE_IDX 1
+#define regUVD_PICCOUNT 0x00d5
+#define regUVD_PICCOUNT_BASE_IDX 1
+#define regUVD_MPRD_INITIAL_XY 0x00d6
+#define regUVD_MPRD_INITIAL_XY_BASE_IDX 1
+#define regUVD_MPEG2_CTRL 0x00d7
+#define regUVD_MPEG2_CTRL_BASE_IDX 1
+#define regUVD_MB_CTL_BUF_BASE 0x00d8
+#define regUVD_MB_CTL_BUF_BASE_BASE_IDX 1
+#define regUVD_PIC_CTL_BUF_BASE 0x00d9
+#define regUVD_PIC_CTL_BUF_BASE_BASE_IDX 1
+#define regUVD_DXVA_BUF_SIZE 0x00da
+#define regUVD_DXVA_BUF_SIZE_BASE_IDX 1
+#define regUVD_SCRATCH_NP 0x00db
+#define regUVD_SCRATCH_NP_BASE_IDX 1
+#define regUVD_CLK_SWT_HANDSHAKE 0x00dc
+#define regUVD_CLK_SWT_HANDSHAKE_BASE_IDX 1
+#define regUVD_VERSION 0x00dd
+#define regUVD_VERSION_BASE_IDX 1
+#define regUVD_GP_SCRATCH0 0x00de
+#define regUVD_GP_SCRATCH0_BASE_IDX 1
+#define regUVD_GP_SCRATCH1 0x00df
+#define regUVD_GP_SCRATCH1_BASE_IDX 1
+#define regUVD_GP_SCRATCH2 0x00e0
+#define regUVD_GP_SCRATCH2_BASE_IDX 1
+#define regUVD_GP_SCRATCH3 0x00e1
+#define regUVD_GP_SCRATCH3_BASE_IDX 1
+#define regUVD_GP_SCRATCH4 0x00e2
+#define regUVD_GP_SCRATCH4_BASE_IDX 1
+#define regUVD_GP_SCRATCH5 0x00e3
+#define regUVD_GP_SCRATCH5_BASE_IDX 1
+#define regUVD_GP_SCRATCH6 0x00e4
+#define regUVD_GP_SCRATCH6_BASE_IDX 1
+#define regUVD_GP_SCRATCH7 0x00e5
+#define regUVD_GP_SCRATCH7_BASE_IDX 1
+#define regUVD_GP_SCRATCH8 0x00e6
+#define regUVD_GP_SCRATCH8_BASE_IDX 1
+#define regUVD_GP_SCRATCH9 0x00e7
+#define regUVD_GP_SCRATCH9_BASE_IDX 1
+#define regUVD_GP_SCRATCH10 0x00e8
+#define regUVD_GP_SCRATCH10_BASE_IDX 1
+#define regUVD_GP_SCRATCH11 0x00e9
+#define regUVD_GP_SCRATCH11_BASE_IDX 1
+#define regUVD_GP_SCRATCH12 0x00ea
+#define regUVD_GP_SCRATCH12_BASE_IDX 1
+#define regUVD_GP_SCRATCH13 0x00eb
+#define regUVD_GP_SCRATCH13_BASE_IDX 1
+#define regUVD_GP_SCRATCH14 0x00ec
+#define regUVD_GP_SCRATCH14_BASE_IDX 1
+#define regUVD_GP_SCRATCH15 0x00ed
+#define regUVD_GP_SCRATCH15_BASE_IDX 1
+#define regUVD_GP_SCRATCH16 0x00ee
+#define regUVD_GP_SCRATCH16_BASE_IDX 1
+#define regUVD_GP_SCRATCH17 0x00ef
+#define regUVD_GP_SCRATCH17_BASE_IDX 1
+#define regUVD_GP_SCRATCH18 0x00f0
+#define regUVD_GP_SCRATCH18_BASE_IDX 1
+#define regUVD_GP_SCRATCH19 0x00f1
+#define regUVD_GP_SCRATCH19_BASE_IDX 1
+#define regUVD_GP_SCRATCH20 0x00f2
+#define regUVD_GP_SCRATCH20_BASE_IDX 1
+#define regUVD_GP_SCRATCH21 0x00f3
+#define regUVD_GP_SCRATCH21_BASE_IDX 1
+#define regUVD_GP_SCRATCH22 0x00f4
+#define regUVD_GP_SCRATCH22_BASE_IDX 1
+#define regUVD_GP_SCRATCH23 0x00f5
+#define regUVD_GP_SCRATCH23_BASE_IDX 1
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h
new file mode 100644
index 000000000000..f61a5bbb1973
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h
@@ -0,0 +1,4535 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef _vcn_2_6_0_SH_MASK_HEADER
+#define _vcn_2_6_0_SH_MASK_HEADER
+
+
+// addressBlock: uvd0_ecpudec
+//UVD_VCPU_CACHE_OFFSET0
+#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0
+#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_SIZE0
+#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0
+#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_OFFSET1
+#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0
+#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_SIZE1
+#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0
+#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_OFFSET2
+#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0
+#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_SIZE2
+#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0
+#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_OFFSET3
+#define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3__SHIFT 0x0
+#define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_SIZE3
+#define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3__SHIFT 0x0
+#define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_OFFSET4
+#define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4__SHIFT 0x0
+#define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_SIZE4
+#define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4__SHIFT 0x0
+#define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_OFFSET5
+#define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5__SHIFT 0x0
+#define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_SIZE5
+#define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5__SHIFT 0x0
+#define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_OFFSET6
+#define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6__SHIFT 0x0
+#define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_SIZE6
+#define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6__SHIFT 0x0
+#define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_OFFSET7
+#define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7__SHIFT 0x0
+#define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_SIZE7
+#define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7__SHIFT 0x0
+#define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_OFFSET8
+#define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8__SHIFT 0x0
+#define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_SIZE8
+#define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8__SHIFT 0x0
+#define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8_MASK 0x001FFFFFL
+//UVD_VCPU_NONCACHE_OFFSET0
+#define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0__SHIFT 0x0
+#define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0_MASK 0x01FFFFFFL
+//UVD_VCPU_NONCACHE_SIZE0
+#define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0__SHIFT 0x0
+#define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0_MASK 0x001FFFFFL
+//UVD_VCPU_NONCACHE_OFFSET1
+#define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1__SHIFT 0x0
+#define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1_MASK 0x01FFFFFFL
+//UVD_VCPU_NONCACHE_SIZE1
+#define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1__SHIFT 0x0
+#define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1_MASK 0x001FFFFFL
+//UVD_VCPU_CNTL
+#define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0
+#define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5
+#define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6
+#define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7
+#define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8
+#define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9
+#define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa
+#define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb
+#define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10
+#define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12
+#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14
+#define UVD_VCPU_CNTL__BLK_RST__SHIFT 0x1c
+#define UVD_VCPU_CNTL__IRQ_ERR_MASK 0x0000000FL
+#define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x00000020L
+#define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x00000040L
+#define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00000080L
+#define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x00000100L
+#define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L
+#define UVD_VCPU_CNTL__TRCE_EN_MASK 0x00000400L
+#define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x00001800L
+#define UVD_VCPU_CNTL__JTAG_EN_MASK 0x00010000L
+#define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x00040000L
+#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L
+#define UVD_VCPU_CNTL__BLK_RST_MASK 0x10000000L
+//UVD_VCPU_PRID
+#define UVD_VCPU_PRID__PRID__SHIFT 0x0
+#define UVD_VCPU_PRID__PRID_MASK 0x0000FFFFL
+//UVD_VCPU_TRCE
+#define UVD_VCPU_TRCE__PC__SHIFT 0x0
+#define UVD_VCPU_TRCE__PC_MASK 0x0FFFFFFFL
+//UVD_VCPU_TRCE_RD
+#define UVD_VCPU_TRCE_RD__DATA__SHIFT 0x0
+#define UVD_VCPU_TRCE_RD__DATA_MASK 0xFFFFFFFFL
+//UVD_VCPU_IND_INDEX
+#define UVD_VCPU_IND_INDEX__INDEX__SHIFT 0x0
+#define UVD_VCPU_IND_INDEX__INDEX_MASK 0x000001FFL
+//UVD_VCPU_IND_DATA
+#define UVD_VCPU_IND_DATA__DATA__SHIFT 0x0
+#define UVD_VCPU_IND_DATA__DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: uvd0_jpegnpdec
+//UVD_JPEG_CNTL
+#define UVD_JPEG_CNTL__REQUEST_EN__SHIFT 0x1
+#define UVD_JPEG_CNTL__ERR_RST_EN__SHIFT 0x2
+#define UVD_JPEG_CNTL__HUFF_SPEED_EN__SHIFT 0x3
+#define UVD_JPEG_CNTL__HUFF_SPEED_STATUS__SHIFT 0x4
+#define UVD_JPEG_CNTL__REQUEST_EN_MASK 0x00000002L
+#define UVD_JPEG_CNTL__ERR_RST_EN_MASK 0x00000004L
+#define UVD_JPEG_CNTL__HUFF_SPEED_EN_MASK 0x00000008L
+#define UVD_JPEG_CNTL__HUFF_SPEED_STATUS_MASK 0x00000010L
+//UVD_JPEG_RB_BASE
+#define UVD_JPEG_RB_BASE__RB_BYTE_OFF__SHIFT 0x0
+#define UVD_JPEG_RB_BASE__RB_BASE__SHIFT 0x6
+#define UVD_JPEG_RB_BASE__RB_BYTE_OFF_MASK 0x0000003FL
+#define UVD_JPEG_RB_BASE__RB_BASE_MASK 0xFFFFFFC0L
+//UVD_JPEG_RB_WPTR
+#define UVD_JPEG_RB_WPTR__RB_WPTR__SHIFT 0x4
+#define UVD_JPEG_RB_WPTR__RB_WPTR_MASK 0x3FFFFFF0L
+//UVD_JPEG_RB_RPTR
+#define UVD_JPEG_RB_RPTR__RB_RPTR__SHIFT 0x4
+#define UVD_JPEG_RB_RPTR__RB_RPTR_MASK 0x3FFFFFF0L
+//UVD_JPEG_RB_SIZE
+#define UVD_JPEG_RB_SIZE__RB_SIZE__SHIFT 0x4
+#define UVD_JPEG_RB_SIZE__RB_SIZE_MASK 0x3FFFFFF0L
+//UVD_JPEG_DEC_CNT
+#define UVD_JPEG_DEC_CNT__DECODE_COUNT__SHIFT 0x0
+#define UVD_JPEG_DEC_CNT__DECODE_COUNT_MASK 0xFFFFFFFFL
+//UVD_JPEG_SPS_INFO
+#define UVD_JPEG_SPS_INFO__PIC_WIDTH__SHIFT 0x0
+#define UVD_JPEG_SPS_INFO__PIC_HEIGHT__SHIFT 0x10
+#define UVD_JPEG_SPS_INFO__PIC_WIDTH_MASK 0x0000FFFFL
+#define UVD_JPEG_SPS_INFO__PIC_HEIGHT_MASK 0xFFFF0000L
+//UVD_JPEG_SPS1_INFO
+#define UVD_JPEG_SPS1_INFO__CHROMA_FORMAT_IDC__SHIFT 0x0
+#define UVD_JPEG_SPS1_INFO__YUV422_SUBFORMAT__SHIFT 0x3
+#define UVD_JPEG_SPS1_INFO__OUT_FMT_422__SHIFT 0x4
+#define UVD_JPEG_SPS1_INFO__CHROMA_FORMAT_IDC_MASK 0x00000007L
+#define UVD_JPEG_SPS1_INFO__YUV422_SUBFORMAT_MASK 0x00000008L
+#define UVD_JPEG_SPS1_INFO__OUT_FMT_422_MASK 0x00000010L
+//UVD_JPEG_RE_TIMER
+#define UVD_JPEG_RE_TIMER__TIMER_OUT__SHIFT 0x0
+#define UVD_JPEG_RE_TIMER__TIMER_OUT_EN__SHIFT 0x10
+#define UVD_JPEG_RE_TIMER__TIMER_OUT_MASK 0x000000FFL
+#define UVD_JPEG_RE_TIMER__TIMER_OUT_EN_MASK 0x00010000L
+//UVD_JPEG_DEC_SCRATCH0
+#define UVD_JPEG_DEC_SCRATCH0__SCRATCH0__SHIFT 0x0
+#define UVD_JPEG_DEC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL
+//UVD_JPEG_INT_EN
+#define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN__SHIFT 0x0
+#define UVD_JPEG_INT_EN__JOB_AVAIL_EN__SHIFT 0x1
+#define UVD_JPEG_INT_EN__FENCE_VAL_EN__SHIFT 0x2
+#define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN__SHIFT 0x6
+#define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN__SHIFT 0x7
+#define UVD_JPEG_INT_EN__EOI_ERR_EN__SHIFT 0x8
+#define UVD_JPEG_INT_EN__HFM_ERR_EN__SHIFT 0x9
+#define UVD_JPEG_INT_EN__RST_ERR_EN__SHIFT 0xa
+#define UVD_JPEG_INT_EN__ECS_MK_ERR_EN__SHIFT 0xb
+#define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN__SHIFT 0xc
+#define UVD_JPEG_INT_EN__MARKER_ERR_EN__SHIFT 0xd
+#define UVD_JPEG_INT_EN__FMT_ERR_EN__SHIFT 0xe
+#define UVD_JPEG_INT_EN__PROFILE_ERR_EN__SHIFT 0xf
+#define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN_MASK 0x00000001L
+#define UVD_JPEG_INT_EN__JOB_AVAIL_EN_MASK 0x00000002L
+#define UVD_JPEG_INT_EN__FENCE_VAL_EN_MASK 0x00000004L
+#define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN_MASK 0x00000040L
+#define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN_MASK 0x00000080L
+#define UVD_JPEG_INT_EN__EOI_ERR_EN_MASK 0x00000100L
+#define UVD_JPEG_INT_EN__HFM_ERR_EN_MASK 0x00000200L
+#define UVD_JPEG_INT_EN__RST_ERR_EN_MASK 0x00000400L
+#define UVD_JPEG_INT_EN__ECS_MK_ERR_EN_MASK 0x00000800L
+#define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN_MASK 0x00001000L
+#define UVD_JPEG_INT_EN__MARKER_ERR_EN_MASK 0x00002000L
+#define UVD_JPEG_INT_EN__FMT_ERR_EN_MASK 0x00004000L
+#define UVD_JPEG_INT_EN__PROFILE_ERR_EN_MASK 0x00008000L
+//UVD_JPEG_INT_STAT
+#define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT__SHIFT 0x0
+#define UVD_JPEG_INT_STAT__JOB_AVAIL_INT__SHIFT 0x1
+#define UVD_JPEG_INT_STAT__FENCE_VAL_INT__SHIFT 0x2
+#define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT__SHIFT 0x6
+#define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT__SHIFT 0x7
+#define UVD_JPEG_INT_STAT__EOI_ERR_INT__SHIFT 0x8
+#define UVD_JPEG_INT_STAT__HFM_ERR_INT__SHIFT 0x9
+#define UVD_JPEG_INT_STAT__RST_ERR_INT__SHIFT 0xa
+#define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT__SHIFT 0xb
+#define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT__SHIFT 0xc
+#define UVD_JPEG_INT_STAT__MARKER_ERR_INT__SHIFT 0xd
+#define UVD_JPEG_INT_STAT__FMT_ERR_INT__SHIFT 0xe
+#define UVD_JPEG_INT_STAT__PROFILE_ERR_INT__SHIFT 0xf
+#define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT_MASK 0x00000001L
+#define UVD_JPEG_INT_STAT__JOB_AVAIL_INT_MASK 0x00000002L
+#define UVD_JPEG_INT_STAT__FENCE_VAL_INT_MASK 0x00000004L
+#define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT_MASK 0x00000040L
+#define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT_MASK 0x00000080L
+#define UVD_JPEG_INT_STAT__EOI_ERR_INT_MASK 0x00000100L
+#define UVD_JPEG_INT_STAT__HFM_ERR_INT_MASK 0x00000200L
+#define UVD_JPEG_INT_STAT__RST_ERR_INT_MASK 0x00000400L
+#define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT_MASK 0x00000800L
+#define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT_MASK 0x00001000L
+#define UVD_JPEG_INT_STAT__MARKER_ERR_INT_MASK 0x00002000L
+#define UVD_JPEG_INT_STAT__FMT_ERR_INT_MASK 0x00004000L
+#define UVD_JPEG_INT_STAT__PROFILE_ERR_INT_MASK 0x00008000L
+//UVD_JPEG_TIER_CNTL0
+#define UVD_JPEG_TIER_CNTL0__TIER_SEL__SHIFT 0x0
+#define UVD_JPEG_TIER_CNTL0__Y_COMP_ID__SHIFT 0x2
+#define UVD_JPEG_TIER_CNTL0__U_COMP_ID__SHIFT 0x4
+#define UVD_JPEG_TIER_CNTL0__V_COMP_ID__SHIFT 0x6
+#define UVD_JPEG_TIER_CNTL0__Y_H_SAMP_FAC__SHIFT 0x8
+#define UVD_JPEG_TIER_CNTL0__Y_V_SAMP_FAC__SHIFT 0xb
+#define UVD_JPEG_TIER_CNTL0__U_H_SAMP_FAC__SHIFT 0xe
+#define UVD_JPEG_TIER_CNTL0__U_V_SAMP_FAC__SHIFT 0x11
+#define UVD_JPEG_TIER_CNTL0__V_H_SAMP_FAC__SHIFT 0x14
+#define UVD_JPEG_TIER_CNTL0__V_V_SAMP_FAC__SHIFT 0x17
+#define UVD_JPEG_TIER_CNTL0__Y_TQ__SHIFT 0x1a
+#define UVD_JPEG_TIER_CNTL0__U_TQ__SHIFT 0x1c
+#define UVD_JPEG_TIER_CNTL0__V_TQ__SHIFT 0x1e
+#define UVD_JPEG_TIER_CNTL0__TIER_SEL_MASK 0x00000003L
+#define UVD_JPEG_TIER_CNTL0__Y_COMP_ID_MASK 0x0000000CL
+#define UVD_JPEG_TIER_CNTL0__U_COMP_ID_MASK 0x00000030L
+#define UVD_JPEG_TIER_CNTL0__V_COMP_ID_MASK 0x000000C0L
+#define UVD_JPEG_TIER_CNTL0__Y_H_SAMP_FAC_MASK 0x00000700L
+#define UVD_JPEG_TIER_CNTL0__Y_V_SAMP_FAC_MASK 0x00003800L
+#define UVD_JPEG_TIER_CNTL0__U_H_SAMP_FAC_MASK 0x0001C000L
+#define UVD_JPEG_TIER_CNTL0__U_V_SAMP_FAC_MASK 0x000E0000L
+#define UVD_JPEG_TIER_CNTL0__V_H_SAMP_FAC_MASK 0x00700000L
+#define UVD_JPEG_TIER_CNTL0__V_V_SAMP_FAC_MASK 0x03800000L
+#define UVD_JPEG_TIER_CNTL0__Y_TQ_MASK 0x0C000000L
+#define UVD_JPEG_TIER_CNTL0__U_TQ_MASK 0x30000000L
+#define UVD_JPEG_TIER_CNTL0__V_TQ_MASK 0xC0000000L
+//UVD_JPEG_TIER_CNTL1
+#define UVD_JPEG_TIER_CNTL1__SRC_WIDTH__SHIFT 0x0
+#define UVD_JPEG_TIER_CNTL1__SRC_HEIGHT__SHIFT 0x10
+#define UVD_JPEG_TIER_CNTL1__SRC_WIDTH_MASK 0x0000FFFFL
+#define UVD_JPEG_TIER_CNTL1__SRC_HEIGHT_MASK 0xFFFF0000L
+//UVD_JPEG_TIER_CNTL2
+#define UVD_JPEG_TIER_CNTL2__TBL_ECS_SEL__SHIFT 0x0
+#define UVD_JPEG_TIER_CNTL2__TBL_TYPE__SHIFT 0x1
+#define UVD_JPEG_TIER_CNTL2__TQ__SHIFT 0x2
+#define UVD_JPEG_TIER_CNTL2__TH__SHIFT 0x4
+#define UVD_JPEG_TIER_CNTL2__TC__SHIFT 0x6
+#define UVD_JPEG_TIER_CNTL2__TD__SHIFT 0x7
+#define UVD_JPEG_TIER_CNTL2__TA__SHIFT 0xa
+#define UVD_JPEG_TIER_CNTL2__TIER2_HTBL_CNTLEN__SHIFT 0xe
+#define UVD_JPEG_TIER_CNTL2__DRI_VAL__SHIFT 0x10
+#define UVD_JPEG_TIER_CNTL2__TBL_ECS_SEL_MASK 0x00000001L
+#define UVD_JPEG_TIER_CNTL2__TBL_TYPE_MASK 0x00000002L
+#define UVD_JPEG_TIER_CNTL2__TQ_MASK 0x0000000CL
+#define UVD_JPEG_TIER_CNTL2__TH_MASK 0x00000030L
+#define UVD_JPEG_TIER_CNTL2__TC_MASK 0x00000040L
+#define UVD_JPEG_TIER_CNTL2__TD_MASK 0x00000380L
+#define UVD_JPEG_TIER_CNTL2__TA_MASK 0x00001C00L
+#define UVD_JPEG_TIER_CNTL2__TIER2_HTBL_CNTLEN_MASK 0x00004000L
+#define UVD_JPEG_TIER_CNTL2__DRI_VAL_MASK 0xFFFF0000L
+//UVD_JPEG_TIER_STATUS
+#define UVD_JPEG_TIER_STATUS__BSI_FETCH_DONE__SHIFT 0x0
+#define UVD_JPEG_TIER_STATUS__DECODE_DONE__SHIFT 0x1
+#define UVD_JPEG_TIER_STATUS__BSI_FETCH_DONE_MASK 0x00000001L
+#define UVD_JPEG_TIER_STATUS__DECODE_DONE_MASK 0x00000002L
+//UVD_JPEG_OUTBUF_CNTL
+#define UVD_JPEG_OUTBUF_CNTL__OUTBUF_CNT__SHIFT 0x0
+#define UVD_JPEG_OUTBUF_CNTL__HGT_ALIGN__SHIFT 0x2
+#define UVD_JPEG_OUTBUF_CNTL__JPEG0_DECODE_DONE_FIX__SHIFT 0x6
+#define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_MAX_CNT__SHIFT 0x7
+#define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_TIMER__SHIFT 0x9
+#define UVD_JPEG_OUTBUF_CNTL__OUTBUF_CNT_MASK 0x00000003L
+#define UVD_JPEG_OUTBUF_CNTL__HGT_ALIGN_MASK 0x00000004L
+#define UVD_JPEG_OUTBUF_CNTL__JPEG0_DECODE_DONE_FIX_MASK 0x00000040L
+#define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_MAX_CNT_MASK 0x00000180L
+#define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_TIMER_MASK 0x00001E00L
+//UVD_JPEG_OUTBUF_WPTR
+#define UVD_JPEG_OUTBUF_WPTR__OUTBUF_WPTR__SHIFT 0x0
+#define UVD_JPEG_OUTBUF_WPTR__OUTBUF_WPTR_MASK 0xFFFFFFFFL
+//UVD_JPEG_OUTBUF_RPTR
+#define UVD_JPEG_OUTBUF_RPTR__OUTBUF_RPTR__SHIFT 0x0
+#define UVD_JPEG_OUTBUF_RPTR__OUTBUF_RPTR_MASK 0xFFFFFFFFL
+//UVD_JPEG_PITCH
+#define UVD_JPEG_PITCH__PITCH__SHIFT 0x0
+#define UVD_JPEG_PITCH__PITCH_MASK 0xFFFFFFFFL
+//UVD_JPEG_UV_PITCH
+#define UVD_JPEG_UV_PITCH__UV_PITCH__SHIFT 0x0
+#define UVD_JPEG_UV_PITCH__UV_PITCH_MASK 0xFFFFFFFFL
+//JPEG_DEC_Y_GFX8_TILING_SURFACE
+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_WIDTH__SHIFT 0x0
+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_HEIGHT__SHIFT 0x2
+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT__SHIFT 0x4
+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__NUM_BANKS__SHIFT 0x6
+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__PIPE_CONFIG__SHIFT 0x8
+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__TILE_SPLIT__SHIFT 0xd
+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__ARRAY_MODE__SHIFT 0x10
+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_WIDTH_MASK 0x00000003L
+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_HEIGHT_MASK 0x0000000CL
+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__NUM_BANKS_MASK 0x000000C0L
+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__PIPE_CONFIG_MASK 0x00001F00L
+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__TILE_SPLIT_MASK 0x0000E000L
+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__ARRAY_MODE_MASK 0x000F0000L
+//JPEG_DEC_UV_GFX8_TILING_SURFACE
+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_WIDTH__SHIFT 0x0
+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_HEIGHT__SHIFT 0x2
+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT__SHIFT 0x4
+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__NUM_BANKS__SHIFT 0x6
+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__PIPE_CONFIG__SHIFT 0x8
+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__TILE_SPLIT__SHIFT 0xd
+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__ARRAY_MODE__SHIFT 0x10
+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_WIDTH_MASK 0x00000003L
+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_HEIGHT_MASK 0x0000000CL
+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__NUM_BANKS_MASK 0x000000C0L
+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__PIPE_CONFIG_MASK 0x00001F00L
+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__TILE_SPLIT_MASK 0x0000E000L
+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__ARRAY_MODE_MASK 0x000F0000L
+//JPEG_DEC_GFX8_ADDR_CONFIG
+#define JPEG_DEC_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define JPEG_DEC_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L
+//JPEG_DEC_Y_GFX10_TILING_SURFACE
+#define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0
+#define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL
+//JPEG_DEC_UV_GFX10_TILING_SURFACE
+#define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0
+#define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL
+//JPEG_DEC_GFX10_ADDR_CONFIG
+#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
+#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
+#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
+#define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
+#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
+//JPEG_DEC_ADDR_MODE
+#define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y__SHIFT 0x0
+#define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV__SHIFT 0x2
+#define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL__SHIFT 0xc
+#define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y_MASK 0x00000003L
+#define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV_MASK 0x0000000CL
+#define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL_MASK 0x00007000L
+//UVD_JPEG_OUTPUT_XY
+#define UVD_JPEG_OUTPUT_XY__OUTPUT_X__SHIFT 0x0
+#define UVD_JPEG_OUTPUT_XY__OUTPUT_Y__SHIFT 0x10
+#define UVD_JPEG_OUTPUT_XY__OUTPUT_X_MASK 0x00003FFFL
+#define UVD_JPEG_OUTPUT_XY__OUTPUT_Y_MASK 0x3FFF0000L
+//UVD_JPEG_GPCOM_CMD
+#define UVD_JPEG_GPCOM_CMD__CMD__SHIFT 0x1
+#define UVD_JPEG_GPCOM_CMD__CMD_MASK 0x0000000EL
+//UVD_JPEG_GPCOM_DATA0
+#define UVD_JPEG_GPCOM_DATA0__DATA0__SHIFT 0x0
+#define UVD_JPEG_GPCOM_DATA0__DATA0_MASK 0xFFFFFFFFL
+//UVD_JPEG_GPCOM_DATA1
+#define UVD_JPEG_GPCOM_DATA1__DATA1__SHIFT 0x0
+#define UVD_JPEG_GPCOM_DATA1__DATA1_MASK 0xFFFFFFFFL
+//UVD_JPEG_INDEX
+#define UVD_JPEG_INDEX__INDEX__SHIFT 0x0
+#define UVD_JPEG_INDEX__INDEX_MASK 0x000001FFL
+//UVD_JPEG_DATA
+#define UVD_JPEG_DATA__DATA__SHIFT 0x0
+#define UVD_JPEG_DATA__DATA_MASK 0xFFFFFFFFL
+//UVD_JPEG_SCRATCH1
+#define UVD_JPEG_SCRATCH1__SCRATCH1__SHIFT 0x0
+#define UVD_JPEG_SCRATCH1__SCRATCH1_MASK 0xFFFFFFFFL
+//UVD_JPEG_DEC_SOFT_RST
+#define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET__SHIFT 0x0
+#define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS__SHIFT 0x10
+#define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET_MASK 0x00000001L
+#define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS_MASK 0x00010000L
+
+
+// addressBlock: uvd0_lmi_adpdec
+//UVD_LMI_RE_64BIT_BAR_LOW
+#define UVD_LMI_RE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_RE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_RE_64BIT_BAR_HIGH
+#define UVD_LMI_RE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_RE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_IT_64BIT_BAR_LOW
+#define UVD_LMI_IT_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_IT_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_IT_64BIT_BAR_HIGH
+#define UVD_LMI_IT_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_IT_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MP_64BIT_BAR_LOW
+#define UVD_LMI_MP_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MP_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MP_64BIT_BAR_HIGH
+#define UVD_LMI_MP_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MP_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_CM_64BIT_BAR_LOW
+#define UVD_LMI_CM_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_CM_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_CM_64BIT_BAR_HIGH
+#define UVD_LMI_CM_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_CM_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_DB_64BIT_BAR_LOW
+#define UVD_LMI_DB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_DB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_DB_64BIT_BAR_HIGH
+#define UVD_LMI_DB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_DB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_DBW_64BIT_BAR_LOW
+#define UVD_LMI_DBW_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_DBW_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_DBW_64BIT_BAR_HIGH
+#define UVD_LMI_DBW_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_DBW_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_IDCT_64BIT_BAR_LOW
+#define UVD_LMI_IDCT_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_IDCT_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_IDCT_64BIT_BAR_HIGH
+#define UVD_LMI_IDCT_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_IDCT_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MPRD_S0_64BIT_BAR_LOW
+#define UVD_LMI_MPRD_S0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MPRD_S0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MPRD_S0_64BIT_BAR_HIGH
+#define UVD_LMI_MPRD_S0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MPRD_S0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MPRD_S1_64BIT_BAR_LOW
+#define UVD_LMI_MPRD_S1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MPRD_S1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MPRD_S1_64BIT_BAR_HIGH
+#define UVD_LMI_MPRD_S1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MPRD_S1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MPRD_DBW_64BIT_BAR_LOW
+#define UVD_LMI_MPRD_DBW_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MPRD_DBW_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MPRD_DBW_64BIT_BAR_HIGH
+#define UVD_LMI_MPRD_DBW_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MPRD_DBW_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MPC_64BIT_BAR_LOW
+#define UVD_LMI_MPC_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MPC_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MPC_64BIT_BAR_HIGH
+#define UVD_LMI_MPC_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MPC_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_RBC_RB_64BIT_BAR_LOW
+#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_RBC_RB_64BIT_BAR_HIGH
+#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_RBC_IB_64BIT_BAR_LOW
+#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_RBC_IB_64BIT_BAR_HIGH
+#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_LBSI_64BIT_BAR_LOW
+#define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_LBSI_64BIT_BAR_HIGH
+#define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_NC0_64BIT_BAR_LOW
+#define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH
+#define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_NC1_64BIT_BAR_LOW
+#define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH
+#define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW
+#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH
+#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_CENC_64BIT_BAR_LOW
+#define UVD_LMI_CENC_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_CENC_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_CENC_64BIT_BAR_HIGH
+#define UVD_LMI_CENC_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_CENC_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_SRE_64BIT_BAR_LOW
+#define UVD_LMI_SRE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_SRE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_SRE_64BIT_BAR_HIGH
+#define UVD_LMI_SRE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_SRE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW
+#define UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH
+#define UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW
+#define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH
+#define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW
+#define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH
+#define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_REF_64BIT_BAR_LOW
+#define UVD_LMI_MIF_REF_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MIF_REF_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_REF_64BIT_BAR_HIGH
+#define UVD_LMI_MIF_REF_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MIF_REF_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_DBW_64BIT_BAR_LOW
+#define UVD_LMI_MIF_DBW_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MIF_DBW_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_DBW_64BIT_BAR_HIGH
+#define UVD_LMI_MIF_DBW_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MIF_DBW_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW
+#define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH
+#define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_BSP0_64BIT_BAR_LOW
+#define UVD_LMI_MIF_BSP0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MIF_BSP0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH
+#define UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_BSP1_64BIT_BAR_LOW
+#define UVD_LMI_MIF_BSP1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MIF_BSP1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH
+#define UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_BSP2_64BIT_BAR_LOW
+#define UVD_LMI_MIF_BSP2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MIF_BSP2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH
+#define UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_BSP3_64BIT_BAR_LOW
+#define UVD_LMI_MIF_BSP3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MIF_BSP3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH
+#define UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_BSD0_64BIT_BAR_LOW
+#define UVD_LMI_MIF_BSD0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MIF_BSD0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH
+#define UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_BSD1_64BIT_BAR_LOW
+#define UVD_LMI_MIF_BSD1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MIF_BSD1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH
+#define UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_BSD2_64BIT_BAR_LOW
+#define UVD_LMI_MIF_BSD2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MIF_BSD2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH
+#define UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_BSD3_64BIT_BAR_LOW
+#define UVD_LMI_MIF_BSD3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MIF_BSD3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH
+#define UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_BSD4_64BIT_BAR_LOW
+#define UVD_LMI_MIF_BSD4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MIF_BSD4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH
+#define UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW
+#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH
+#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW
+#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH
+#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW
+#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH
+#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW
+#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH
+#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW
+#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH
+#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW
+#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH
+#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW
+#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH
+#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW
+#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH
+#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_SCLR_64BIT_BAR_LOW
+#define UVD_LMI_MIF_SCLR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MIF_SCLR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH
+#define UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW
+#define UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH
+#define UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_SPH_64BIT_BAR_HIGH
+#define UVD_LMI_SPH_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_SPH_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW
+#define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH
+#define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW
+#define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH
+#define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW
+#define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH
+#define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW
+#define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH
+#define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW
+#define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH
+#define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW
+#define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH
+#define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW
+#define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH
+#define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW
+#define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH
+#define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MMSCH_NC_VMID
+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID__SHIFT 0x0
+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID__SHIFT 0x4
+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID__SHIFT 0x8
+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID__SHIFT 0xc
+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID__SHIFT 0x10
+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID__SHIFT 0x14
+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID__SHIFT 0x18
+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID__SHIFT 0x1c
+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID_MASK 0x0000000FL
+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID_MASK 0x000000F0L
+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID_MASK 0x00000F00L
+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID_MASK 0x0000F000L
+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID_MASK 0x000F0000L
+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID_MASK 0x00F00000L
+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID_MASK 0x0F000000L
+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID_MASK 0xF0000000L
+//UVD_LMI_MMSCH_CTRL
+#define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN__SHIFT 0x0
+#define UVD_LMI_MMSCH_CTRL__MMSCH_VM__SHIFT 0x1
+#define UVD_LMI_MMSCH_CTRL__PRIV_CLIENT_MMSCH__SHIFT 0x2
+#define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP__SHIFT 0x3
+#define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP__SHIFT 0x5
+#define UVD_LMI_MMSCH_CTRL__MMSCH_RD__SHIFT 0x7
+#define UVD_LMI_MMSCH_CTRL__MMSCH_WR__SHIFT 0x9
+#define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP__SHIFT 0xb
+#define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP__SHIFT 0xc
+#define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN_MASK 0x00000001L
+#define UVD_LMI_MMSCH_CTRL__MMSCH_VM_MASK 0x00000002L
+#define UVD_LMI_MMSCH_CTRL__PRIV_CLIENT_MMSCH_MASK 0x00000004L
+#define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP_MASK 0x00000018L
+#define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP_MASK 0x00000060L
+#define UVD_LMI_MMSCH_CTRL__MMSCH_RD_MASK 0x00000180L
+#define UVD_LMI_MMSCH_CTRL__MMSCH_WR_MASK 0x00000600L
+#define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP_MASK 0x00000800L
+#define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP_MASK 0x00001000L
+//UVD_MMSCH_LMI_STATUS
+#define UVD_MMSCH_LMI_STATUS__MMSCH_LMI_WRITE_CLEAN__SHIFT 0x2
+#define UVD_MMSCH_LMI_STATUS__MMSCH_RD_CLEAN__SHIFT 0xd
+#define UVD_MMSCH_LMI_STATUS__MMSCH_WR_CLEAN__SHIFT 0xe
+#define UVD_MMSCH_LMI_STATUS__MMSCH_LMI_WRITE_CLEAN_MASK 0x00000004L
+#define UVD_MMSCH_LMI_STATUS__MMSCH_RD_CLEAN_MASK 0x00002000L
+#define UVD_MMSCH_LMI_STATUS__MMSCH_WR_CLEAN_MASK 0x00004000L
+//UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW
+#define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH
+#define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW
+#define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH
+#define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW
+#define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH
+#define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW
+#define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH
+#define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_ADP_ATOMIC_CONFIG
+#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER0_WR_CACHE__SHIFT 0x0
+#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER1_WR_CACHE__SHIFT 0x4
+#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER2_WR_CACHE__SHIFT 0x8
+#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER3_WR_CACHE__SHIFT 0xc
+#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_RD_URG__SHIFT 0x10
+#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER0_WR_CACHE_MASK 0x0000000FL
+#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER1_WR_CACHE_MASK 0x000000F0L
+#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER2_WR_CACHE_MASK 0x00000F00L
+#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER3_WR_CACHE_MASK 0x0000F000L
+#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_RD_URG_MASK 0x000F0000L
+//UVD_LMI_ARB_CTRL2
+#define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN__SHIFT 0x0
+#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN__SHIFT 0x1
+#define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST__SHIFT 0x2
+#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST__SHIFT 0x6
+#define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX__SHIFT 0xa
+#define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX__SHIFT 0x14
+#define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN_MASK 0x00000001L
+#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN_MASK 0x00000002L
+#define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST_MASK 0x0000003CL
+#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST_MASK 0x000003C0L
+#define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX_MASK 0x000FFC00L
+#define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX_MASK 0xFFF00000L
+//UVD_LMI_VCPU_CACHE_VMIDS_MULTI
+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID__SHIFT 0x4
+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID__SHIFT 0x8
+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID__SHIFT 0xc
+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID__SHIFT 0x10
+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID__SHIFT 0x14
+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID__SHIFT 0x18
+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID__SHIFT 0x1c
+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID_MASK 0x0000000FL
+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID_MASK 0x000000F0L
+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID_MASK 0x00000F00L
+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID_MASK 0x0000F000L
+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID_MASK 0x000F0000L
+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID_MASK 0x00F00000L
+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID_MASK 0x0F000000L
+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID_MASK 0xF0000000L
+//UVD_LMI_VCPU_NC_VMIDS_MULTI
+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID__SHIFT 0x4
+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID__SHIFT 0x8
+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID__SHIFT 0xc
+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID__SHIFT 0x10
+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID__SHIFT 0x14
+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID__SHIFT 0x18
+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID_MASK 0x000000F0L
+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID_MASK 0x00000F00L
+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID_MASK 0x0000F000L
+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID_MASK 0x000F0000L
+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID_MASK 0x00F00000L
+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID_MASK 0x0F000000L
+//UVD_LMI_LAT_CTRL
+#define UVD_LMI_LAT_CTRL__SCALE__SHIFT 0x0
+#define UVD_LMI_LAT_CTRL__MAX_START__SHIFT 0x8
+#define UVD_LMI_LAT_CTRL__MIN_START__SHIFT 0x9
+#define UVD_LMI_LAT_CTRL__AVG_START__SHIFT 0xa
+#define UVD_LMI_LAT_CTRL__PERFMON_SYNC__SHIFT 0xb
+#define UVD_LMI_LAT_CTRL__SKIP__SHIFT 0x10
+#define UVD_LMI_LAT_CTRL__SCALE_MASK 0x000000FFL
+#define UVD_LMI_LAT_CTRL__MAX_START_MASK 0x00000100L
+#define UVD_LMI_LAT_CTRL__MIN_START_MASK 0x00000200L
+#define UVD_LMI_LAT_CTRL__AVG_START_MASK 0x00000400L
+#define UVD_LMI_LAT_CTRL__PERFMON_SYNC_MASK 0x00000800L
+#define UVD_LMI_LAT_CTRL__SKIP_MASK 0x000F0000L
+//UVD_LMI_LAT_CNTR
+#define UVD_LMI_LAT_CNTR__MAX_LAT__SHIFT 0x0
+#define UVD_LMI_LAT_CNTR__MIN_LAT__SHIFT 0x8
+#define UVD_LMI_LAT_CNTR__MAX_LAT_MASK 0x000000FFL
+#define UVD_LMI_LAT_CNTR__MIN_LAT_MASK 0x0000FF00L
+//UVD_LMI_AVG_LAT_CNTR
+#define UVD_LMI_AVG_LAT_CNTR__ENV_LOW__SHIFT 0x0
+#define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH__SHIFT 0x8
+#define UVD_LMI_AVG_LAT_CNTR__ENV_HIT__SHIFT 0x10
+#define UVD_LMI_AVG_LAT_CNTR__ENV_LOW_MASK 0x000000FFL
+#define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH_MASK 0x0000FF00L
+#define UVD_LMI_AVG_LAT_CNTR__ENV_HIT_MASK 0xFFFF0000L
+//UVD_LMI_SPH
+#define UVD_LMI_SPH__ADDR__SHIFT 0x0
+#define UVD_LMI_SPH__STS__SHIFT 0x1c
+#define UVD_LMI_SPH__STS_VALID__SHIFT 0x1e
+#define UVD_LMI_SPH__STS_OVERFLOW__SHIFT 0x1f
+#define UVD_LMI_SPH__ADDR_MASK 0x0FFFFFFFL
+#define UVD_LMI_SPH__STS_MASK 0x30000000L
+#define UVD_LMI_SPH__STS_VALID_MASK 0x40000000L
+#define UVD_LMI_SPH__STS_OVERFLOW_MASK 0x80000000L
+//UVD_LMI_VCPU_CACHE_VMID
+#define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL
+//UVD_LMI_CTRL2
+#define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0
+#define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1
+#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2
+#define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3
+#define UVD_LMI_CTRL2__CRC1_RESET__SHIFT 0x4
+#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7
+#define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8
+#define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9
+#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb
+#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd
+#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe
+#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf
+#define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10
+#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11
+#define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP__SHIFT 0x19
+#define UVD_LMI_CTRL2__NJ_MIF_GATING__SHIFT 0x1a
+#define UVD_LMI_CTRL2__CRC1_SEL__SHIFT 0x1b
+#define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L
+#define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L
+#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L
+#define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x00000008L
+#define UVD_LMI_CTRL2__CRC1_RESET_MASK 0x00000010L
+#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x00000080L
+#define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L
+#define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L
+#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L
+#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x00002000L
+#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x00004000L
+#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x00008000L
+#define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x00010000L
+#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x01FE0000L
+#define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP_MASK 0x02000000L
+#define UVD_LMI_CTRL2__NJ_MIF_GATING_MASK 0x04000000L
+#define UVD_LMI_CTRL2__CRC1_SEL_MASK 0xF8000000L
+//UVD_LMI_URGENT_CTRL
+#define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL__SHIFT 0x0
+#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL__SHIFT 0x1
+#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT__SHIFT 0x2
+#define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL__SHIFT 0x8
+#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL__SHIFT 0x9
+#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT 0xa
+#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL__SHIFT 0x10
+#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL__SHIFT 0x11
+#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT__SHIFT 0x12
+#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL__SHIFT 0x18
+#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL__SHIFT 0x19
+#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT__SHIFT 0x1a
+#define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL_MASK 0x00000001L
+#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL_MASK 0x00000002L
+#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT_MASK 0x0000003CL
+#define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL_MASK 0x00000100L
+#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL_MASK 0x00000200L
+#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT_MASK 0x00003C00L
+#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL_MASK 0x00010000L
+#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL_MASK 0x00020000L
+#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT_MASK 0x003C0000L
+#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL_MASK 0x01000000L
+#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL_MASK 0x02000000L
+#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT_MASK 0x3C000000L
+//UVD_LMI_CTRL
+#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0
+#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8
+#define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9
+#define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb
+#define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc
+#define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd
+#define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe
+#define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf
+#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14
+#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15
+#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16
+#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17
+#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18
+#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19
+#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a
+#define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ__SHIFT 0x1b
+#define UVD_LMI_CTRL__MC_BLK_RST__SHIFT 0x1c
+#define UVD_LMI_CTRL__UMC_BLK_RST__SHIFT 0x1d
+#define UVD_LMI_CTRL__RFU__SHIFT 0x1e
+#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0x000000FFL
+#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L
+#define UVD_LMI_CTRL__REQ_MODE_MASK 0x00000200L
+#define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000800L
+#define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x00001000L
+#define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x00002000L
+#define UVD_LMI_CTRL__CRC_RESET_MASK 0x00004000L
+#define UVD_LMI_CTRL__CRC_SEL_MASK 0x000F8000L
+#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x00100000L
+#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L
+#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x00400000L
+#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x00800000L
+#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L
+#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L
+#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x04000000L
+#define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ_MASK 0x08000000L
+#define UVD_LMI_CTRL__MC_BLK_RST_MASK 0x10000000L
+#define UVD_LMI_CTRL__UMC_BLK_RST_MASK 0x20000000L
+#define UVD_LMI_CTRL__RFU_MASK 0xC0000000L
+//UVD_LMI_STATUS
+#define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0
+#define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1
+#define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2
+#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3
+#define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4
+#define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5
+#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6
+#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7
+#define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8
+#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9
+#define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa
+#define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb
+#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc
+#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd
+#define UVD_LMI_STATUS__BSP0_WRITE_CLEAN__SHIFT 0x12
+#define UVD_LMI_STATUS__BSP1_WRITE_CLEAN__SHIFT 0x13
+#define UVD_LMI_STATUS__BSP2_WRITE_CLEAN__SHIFT 0x14
+#define UVD_LMI_STATUS__BSP3_WRITE_CLEAN__SHIFT 0x15
+#define UVD_LMI_STATUS__CENC_READ_CLEAN__SHIFT 0x16
+#define UVD_LMI_STATUS__READ_CLEAN_MASK 0x00000001L
+#define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x00000002L
+#define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x00000004L
+#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x00000008L
+#define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x00000010L
+#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x00000020L
+#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x00000040L
+#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x00000080L
+#define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x00000100L
+#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x00000200L
+#define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x00000400L
+#define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x00000800L
+#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x00001000L
+#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x00002000L
+#define UVD_LMI_STATUS__BSP0_WRITE_CLEAN_MASK 0x00040000L
+#define UVD_LMI_STATUS__BSP1_WRITE_CLEAN_MASK 0x00080000L
+#define UVD_LMI_STATUS__BSP2_WRITE_CLEAN_MASK 0x00100000L
+#define UVD_LMI_STATUS__BSP3_WRITE_CLEAN_MASK 0x00200000L
+#define UVD_LMI_STATUS__CENC_READ_CLEAN_MASK 0x00400000L
+//UVD_LMI_PERFMON_CTRL
+#define UVD_LMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0
+#define UVD_LMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8
+#define UVD_LMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L
+#define UVD_LMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00001F00L
+//UVD_LMI_PERFMON_COUNT_LO
+#define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0
+#define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL
+//UVD_LMI_PERFMON_COUNT_HI
+#define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0
+#define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL
+//UVD_LMI_ADP_SWAP_CNTL
+#define UVD_LMI_ADP_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6
+#define UVD_LMI_ADP_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8
+#define UVD_LMI_ADP_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa
+#define UVD_LMI_ADP_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc
+#define UVD_LMI_ADP_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe
+#define UVD_LMI_ADP_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10
+#define UVD_LMI_ADP_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12
+#define UVD_LMI_ADP_SWAP_CNTL__ACAP_MC_SWAP__SHIFT 0x14
+#define UVD_LMI_ADP_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18
+#define UVD_LMI_ADP_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c
+#define UVD_LMI_ADP_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e
+#define UVD_LMI_ADP_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0x000000C0L
+#define UVD_LMI_ADP_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000300L
+#define UVD_LMI_ADP_SWAP_CNTL__CM_MC_SWAP_MASK 0x00000C00L
+#define UVD_LMI_ADP_SWAP_CNTL__IT_MC_SWAP_MASK 0x00003000L
+#define UVD_LMI_ADP_SWAP_CNTL__DB_R_MC_SWAP_MASK 0x0000C000L
+#define UVD_LMI_ADP_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x00030000L
+#define UVD_LMI_ADP_SWAP_CNTL__CSM_MC_SWAP_MASK 0x000C0000L
+#define UVD_LMI_ADP_SWAP_CNTL__ACAP_MC_SWAP_MASK 0x00300000L
+#define UVD_LMI_ADP_SWAP_CNTL__DBW_MC_SWAP_MASK 0x03000000L
+#define UVD_LMI_ADP_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000L
+#define UVD_LMI_ADP_SWAP_CNTL__MP_MC_SWAP_MASK 0xC0000000L
+//UVD_LMI_RBC_RB_VMID
+#define UVD_LMI_RBC_RB_VMID__RB_VMID__SHIFT 0x0
+#define UVD_LMI_RBC_RB_VMID__RB_VMID_MASK 0x0000000FL
+//UVD_LMI_RBC_IB_VMID
+#define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0
+#define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0x0000000FL
+//UVD_LMI_MC_CREDITS
+#define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS__SHIFT 0x0
+#define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS__SHIFT 0x8
+#define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS__SHIFT 0x10
+#define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS__SHIFT 0x18
+#define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS_MASK 0x0000003FL
+#define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS_MASK 0x00003F00L
+#define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS_MASK 0x003F0000L
+#define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS_MASK 0x3F000000L
+//UVD_LMI_ADP_IND_INDEX
+#define UVD_LMI_ADP_IND_INDEX__INDEX__SHIFT 0x0
+#define UVD_LMI_ADP_IND_INDEX__INDEX_MASK 0x00001FFFL
+//UVD_LMI_ADP_IND_DATA
+#define UVD_LMI_ADP_IND_DATA__DATA__SHIFT 0x0
+#define UVD_LMI_ADP_IND_DATA__DATA_MASK 0xFFFFFFFFL
+//VCN_RAS_CNTL
+#define VCN_RAS_CNTL__VCPU_VCODEC_IH_EN__SHIFT 0x0
+#define VCN_RAS_CNTL__MMSCH_FATAL_ERROR_EN__SHIFT 0x1
+#define VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN__SHIFT 0x4
+#define VCN_RAS_CNTL__MMSCH_PMI_EN__SHIFT 0x5
+#define VCN_RAS_CNTL__VCPU_VCODEC_REARM__SHIFT 0x8
+#define VCN_RAS_CNTL__MMSCH_REARM__SHIFT 0x9
+#define VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN__SHIFT 0xc
+#define VCN_RAS_CNTL__VCPU_VCODEC_READY__SHIFT 0x10
+#define VCN_RAS_CNTL__MMSCH_READY__SHIFT 0x11
+#define VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK 0x00000001L
+#define VCN_RAS_CNTL__MMSCH_FATAL_ERROR_EN_MASK 0x00000002L
+#define VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK 0x00000010L
+#define VCN_RAS_CNTL__MMSCH_PMI_EN_MASK 0x00000020L
+#define VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK 0x00000100L
+#define VCN_RAS_CNTL__MMSCH_REARM_MASK 0x00000200L
+#define VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK 0x00001000L
+#define VCN_RAS_CNTL__VCPU_VCODEC_READY_MASK 0x00010000L
+#define VCN_RAS_CNTL__MMSCH_READY_MASK 0x00020000L
+
+
+// addressBlock: uvd0_mmsch_dec
+//MMSCH_UCODE_ADDR
+#define MMSCH_UCODE_ADDR__UCODE_ADDR__SHIFT 0x2
+#define MMSCH_UCODE_ADDR__UCODE_LOCK__SHIFT 0x1f
+#define MMSCH_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFCL
+#define MMSCH_UCODE_ADDR__UCODE_LOCK_MASK 0x80000000L
+//MMSCH_UCODE_DATA
+#define MMSCH_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define MMSCH_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
+//MMSCH_SRAM_ADDR
+#define MMSCH_SRAM_ADDR__SRAM_ADDR__SHIFT 0x2
+#define MMSCH_SRAM_ADDR__SRAM_LOCK__SHIFT 0x1f
+#define MMSCH_SRAM_ADDR__SRAM_ADDR_MASK 0x00001FFCL
+#define MMSCH_SRAM_ADDR__SRAM_LOCK_MASK 0x80000000L
+//MMSCH_SRAM_DATA
+#define MMSCH_SRAM_DATA__SRAM_DATA__SHIFT 0x0
+#define MMSCH_SRAM_DATA__SRAM_DATA_MASK 0xFFFFFFFFL
+//MMSCH_VF_SRAM_OFFSET
+#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_OFFSET__SHIFT 0x2
+#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_NUM_DW_PER_VF__SHIFT 0x10
+#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_OFFSET_MASK 0x00001FFCL
+#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_NUM_DW_PER_VF_MASK 0x00FF0000L
+//MMSCH_DB_SRAM_OFFSET
+#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_OFFSET__SHIFT 0x2
+#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_ENG__SHIFT 0x10
+#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_RING_PER_ENG__SHIFT 0x18
+#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_OFFSET_MASK 0x00001FFCL
+#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_ENG_MASK 0x00FF0000L
+#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_RING_PER_ENG_MASK 0xFF000000L
+//MMSCH_CTX_SRAM_OFFSET
+#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_OFFSET__SHIFT 0x2
+#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_SIZE__SHIFT 0x10
+#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_OFFSET_MASK 0x00001FFCL
+#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_SIZE_MASK 0xFFFF0000L
+//MMSCH_INTR
+#define MMSCH_INTR__INTR__SHIFT 0x0
+#define MMSCH_INTR__INTR_MASK 0x00001FFFL
+//MMSCH_INTR_ACK
+#define MMSCH_INTR_ACK__INTR__SHIFT 0x0
+#define MMSCH_INTR_ACK__INTR_MASK 0x00001FFFL
+//MMSCH_INTR_STATUS
+#define MMSCH_INTR_STATUS__INTR__SHIFT 0x0
+#define MMSCH_INTR_STATUS__INTR_MASK 0x00001FFFL
+//MMSCH_VF_VMID
+#define MMSCH_VF_VMID__VF_CTX_VMID__SHIFT 0x0
+#define MMSCH_VF_VMID__VF_GPCOM_VMID__SHIFT 0x5
+#define MMSCH_VF_VMID__VF_CTX_VMID_MASK 0x0000001FL
+#define MMSCH_VF_VMID__VF_GPCOM_VMID_MASK 0x000003E0L
+//MMSCH_VF_CTX_ADDR_LO
+#define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO__SHIFT 0x6
+#define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO_MASK 0xFFFFFFC0L
+//MMSCH_VF_CTX_ADDR_HI
+#define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI__SHIFT 0x0
+#define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI_MASK 0xFFFFFFFFL
+//MMSCH_VF_CTX_SIZE
+#define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE__SHIFT 0x0
+#define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE_MASK 0xFFFFFFFFL
+//MMSCH_VF_GPCOM_ADDR_LO
+#define MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO__SHIFT 0x6
+#define MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO_MASK 0xFFFFFFC0L
+//MMSCH_VF_GPCOM_ADDR_HI
+#define MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI__SHIFT 0x0
+#define MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI_MASK 0xFFFFFFFFL
+//MMSCH_VF_GPCOM_SIZE
+#define MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE__SHIFT 0x0
+#define MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE_MASK 0xFFFFFFFFL
+//MMSCH_VF_MAILBOX_HOST
+#define MMSCH_VF_MAILBOX_HOST__DATA__SHIFT 0x0
+#define MMSCH_VF_MAILBOX_HOST__DATA_MASK 0xFFFFFFFFL
+//MMSCH_VF_MAILBOX_RESP
+#define MMSCH_VF_MAILBOX_RESP__RESP__SHIFT 0x0
+#define MMSCH_VF_MAILBOX_RESP__RESP_MASK 0xFFFFFFFFL
+//MMSCH_VF_MAILBOX_0
+#define MMSCH_VF_MAILBOX_0__DATA__SHIFT 0x0
+#define MMSCH_VF_MAILBOX_0__DATA_MASK 0xFFFFFFFFL
+//MMSCH_VF_MAILBOX_0_RESP
+#define MMSCH_VF_MAILBOX_0_RESP__RESP__SHIFT 0x0
+#define MMSCH_VF_MAILBOX_0_RESP__RESP_MASK 0xFFFFFFFFL
+//MMSCH_VF_MAILBOX_1
+#define MMSCH_VF_MAILBOX_1__DATA__SHIFT 0x0
+#define MMSCH_VF_MAILBOX_1__DATA_MASK 0xFFFFFFFFL
+//MMSCH_VF_MAILBOX_1_RESP
+#define MMSCH_VF_MAILBOX_1_RESP__RESP__SHIFT 0x0
+#define MMSCH_VF_MAILBOX_1_RESP__RESP_MASK 0xFFFFFFFFL
+//MMSCH_CNTL
+#define MMSCH_CNTL__CLK_EN__SHIFT 0x0
+#define MMSCH_CNTL__ED_ENABLE__SHIFT 0x1
+#define MMSCH_CNTL__MMSCH_IRQ_ERR__SHIFT 0x5
+#define MMSCH_CNTL__MMSCH_NACK_INTR_EN__SHIFT 0x9
+#define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN__SHIFT 0xa
+#define MMSCH_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14
+#define MMSCH_CNTL__TIMEOUT_DIS__SHIFT 0x1c
+#define MMSCH_CNTL__CLK_EN_MASK 0x00000001L
+#define MMSCH_CNTL__ED_ENABLE_MASK 0x00000002L
+#define MMSCH_CNTL__MMSCH_IRQ_ERR_MASK 0x000001E0L
+#define MMSCH_CNTL__MMSCH_NACK_INTR_EN_MASK 0x00000200L
+#define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN_MASK 0x00000400L
+#define MMSCH_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L
+#define MMSCH_CNTL__TIMEOUT_DIS_MASK 0x10000000L
+//MMSCH_NONCACHE_OFFSET0
+#define MMSCH_NONCACHE_OFFSET0__OFFSET__SHIFT 0x0
+#define MMSCH_NONCACHE_OFFSET0__OFFSET_MASK 0x0FFFFFFFL
+//MMSCH_NONCACHE_SIZE0
+#define MMSCH_NONCACHE_SIZE0__SIZE__SHIFT 0x0
+#define MMSCH_NONCACHE_SIZE0__SIZE_MASK 0x00FFFFFFL
+//MMSCH_NONCACHE_OFFSET1
+#define MMSCH_NONCACHE_OFFSET1__OFFSET__SHIFT 0x0
+#define MMSCH_NONCACHE_OFFSET1__OFFSET_MASK 0x0FFFFFFFL
+//MMSCH_NONCACHE_SIZE1
+#define MMSCH_NONCACHE_SIZE1__SIZE__SHIFT 0x0
+#define MMSCH_NONCACHE_SIZE1__SIZE_MASK 0x00FFFFFFL
+//MMSCH_PROC_STATE1
+#define MMSCH_PROC_STATE1__PC__SHIFT 0x0
+#define MMSCH_PROC_STATE1__PC_MASK 0xFFFFFFFFL
+//MMSCH_LAST_MC_ADDR
+#define MMSCH_LAST_MC_ADDR__MC_ADDR__SHIFT 0x0
+#define MMSCH_LAST_MC_ADDR__RW__SHIFT 0x1f
+#define MMSCH_LAST_MC_ADDR__MC_ADDR_MASK 0x0FFFFFFFL
+#define MMSCH_LAST_MC_ADDR__RW_MASK 0x80000000L
+//MMSCH_LAST_MEM_ACCESS_HI
+#define MMSCH_LAST_MEM_ACCESS_HI__PROC_CMD__SHIFT 0x0
+#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_RPTR__SHIFT 0x8
+#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_WPTR__SHIFT 0xc
+#define MMSCH_LAST_MEM_ACCESS_HI__PROC_CMD_MASK 0x00000007L
+#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_RPTR_MASK 0x00000700L
+#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_WPTR_MASK 0x00007000L
+//MMSCH_LAST_MEM_ACCESS_LO
+#define MMSCH_LAST_MEM_ACCESS_LO__PROC_ADDR__SHIFT 0x0
+#define MMSCH_LAST_MEM_ACCESS_LO__PROC_ADDR_MASK 0xFFFFFFFFL
+//MMSCH_SCRATCH_0
+#define MMSCH_SCRATCH_0__SCRATCH_0__SHIFT 0x0
+#define MMSCH_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL
+//MMSCH_SCRATCH_1
+#define MMSCH_SCRATCH_1__SCRATCH_1__SHIFT 0x0
+#define MMSCH_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL
+//MMSCH_GPUIOV_SCH_BLOCK_0
+#define MMSCH_GPUIOV_SCH_BLOCK_0__ID__SHIFT 0x0
+#define MMSCH_GPUIOV_SCH_BLOCK_0__VERSION__SHIFT 0x4
+#define MMSCH_GPUIOV_SCH_BLOCK_0__SIZE__SHIFT 0x8
+#define MMSCH_GPUIOV_SCH_BLOCK_0__ID_MASK 0x0000000FL
+#define MMSCH_GPUIOV_SCH_BLOCK_0__VERSION_MASK 0x000000F0L
+#define MMSCH_GPUIOV_SCH_BLOCK_0__SIZE_MASK 0x0000FF00L
+//MMSCH_GPUIOV_CMD_CONTROL_0
+#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_TYPE__SHIFT 0x0
+#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE__SHIFT 0x4
+#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_INTR_EN__SHIFT 0x5
+#define MMSCH_GPUIOV_CMD_CONTROL_0__VM_BUSY_INTR_EN__SHIFT 0x6
+#define MMSCH_GPUIOV_CMD_CONTROL_0__FUNCTINO_ID__SHIFT 0x8
+#define MMSCH_GPUIOV_CMD_CONTROL_0__NEXT_FUNCTINO_ID__SHIFT 0x10
+#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_TYPE_MASK 0x0000000FL
+#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_MASK 0x00000010L
+#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_INTR_EN_MASK 0x00000020L
+#define MMSCH_GPUIOV_CMD_CONTROL_0__VM_BUSY_INTR_EN_MASK 0x00000040L
+#define MMSCH_GPUIOV_CMD_CONTROL_0__FUNCTINO_ID_MASK 0x0000FF00L
+#define MMSCH_GPUIOV_CMD_CONTROL_0__NEXT_FUNCTINO_ID_MASK 0x00FF0000L
+//MMSCH_GPUIOV_CMD_STATUS_0
+#define MMSCH_GPUIOV_CMD_STATUS_0__CMD_STATUS__SHIFT 0x0
+#define MMSCH_GPUIOV_CMD_STATUS_0__CMD_STATUS_MASK 0x0000000FL
+//MMSCH_GPUIOV_VM_BUSY_STATUS_0
+#define MMSCH_GPUIOV_VM_BUSY_STATUS_0__BUSY__SHIFT 0x0
+#define MMSCH_GPUIOV_VM_BUSY_STATUS_0__BUSY_MASK 0xFFFFFFFFL
+//MMSCH_GPUIOV_ACTIVE_FCNS_0
+#define MMSCH_GPUIOV_ACTIVE_FCNS_0__ACTIVE_FCNS__SHIFT 0x0
+#define MMSCH_GPUIOV_ACTIVE_FCNS_0__ACTIVE_FCNS_MASK 0xFFFFFFFFL
+//MMSCH_GPUIOV_ACTIVE_FCN_ID_0
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID__SHIFT 0x0
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_STATUS__SHIFT 0x8
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_MASK 0x000000FFL
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_STATUS_MASK 0x00000F00L
+//MMSCH_GPUIOV_DW6_0
+#define MMSCH_GPUIOV_DW6_0__DATA__SHIFT 0x0
+#define MMSCH_GPUIOV_DW6_0__DATA_MASK 0xFFFFFFFFL
+//MMSCH_GPUIOV_DW7_0
+#define MMSCH_GPUIOV_DW7_0__DATA__SHIFT 0x0
+#define MMSCH_GPUIOV_DW7_0__DATA_MASK 0xFFFFFFFFL
+//MMSCH_GPUIOV_DW8_0
+#define MMSCH_GPUIOV_DW8_0__DATA__SHIFT 0x0
+#define MMSCH_GPUIOV_DW8_0__DATA_MASK 0xFFFFFFFFL
+//MMSCH_GPUIOV_SCH_BLOCK_1
+#define MMSCH_GPUIOV_SCH_BLOCK_1__ID__SHIFT 0x0
+#define MMSCH_GPUIOV_SCH_BLOCK_1__VERSION__SHIFT 0x4
+#define MMSCH_GPUIOV_SCH_BLOCK_1__SIZE__SHIFT 0x8
+#define MMSCH_GPUIOV_SCH_BLOCK_1__ID_MASK 0x0000000FL
+#define MMSCH_GPUIOV_SCH_BLOCK_1__VERSION_MASK 0x000000F0L
+#define MMSCH_GPUIOV_SCH_BLOCK_1__SIZE_MASK 0x0000FF00L
+//MMSCH_GPUIOV_CMD_CONTROL_1
+#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_TYPE__SHIFT 0x0
+#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE__SHIFT 0x4
+#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_INTR_EN__SHIFT 0x5
+#define MMSCH_GPUIOV_CMD_CONTROL_1__VM_BUSY_INTR_EN__SHIFT 0x6
+#define MMSCH_GPUIOV_CMD_CONTROL_1__FUNCTINO_ID__SHIFT 0x8
+#define MMSCH_GPUIOV_CMD_CONTROL_1__NEXT_FUNCTINO_ID__SHIFT 0x10
+#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_TYPE_MASK 0x0000000FL
+#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_MASK 0x00000010L
+#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L
+#define MMSCH_GPUIOV_CMD_CONTROL_1__VM_BUSY_INTR_EN_MASK 0x00000040L
+#define MMSCH_GPUIOV_CMD_CONTROL_1__FUNCTINO_ID_MASK 0x0000FF00L
+#define MMSCH_GPUIOV_CMD_CONTROL_1__NEXT_FUNCTINO_ID_MASK 0x00FF0000L
+//MMSCH_GPUIOV_CMD_STATUS_1
+#define MMSCH_GPUIOV_CMD_STATUS_1__CMD_STATUS__SHIFT 0x0
+#define MMSCH_GPUIOV_CMD_STATUS_1__CMD_STATUS_MASK 0x0000000FL
+//MMSCH_GPUIOV_VM_BUSY_STATUS_1
+#define MMSCH_GPUIOV_VM_BUSY_STATUS_1__BUSY__SHIFT 0x0
+#define MMSCH_GPUIOV_VM_BUSY_STATUS_1__BUSY_MASK 0xFFFFFFFFL
+//MMSCH_GPUIOV_ACTIVE_FCNS_1
+#define MMSCH_GPUIOV_ACTIVE_FCNS_1__ACTIVE_FCNS__SHIFT 0x0
+#define MMSCH_GPUIOV_ACTIVE_FCNS_1__ACTIVE_FCNS_MASK 0xFFFFFFFFL
+//MMSCH_GPUIOV_ACTIVE_FCN_ID_1
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID__SHIFT 0x0
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_STATUS__SHIFT 0x8
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_MASK 0x000000FFL
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_STATUS_MASK 0x00000F00L
+//MMSCH_GPUIOV_DW6_1
+#define MMSCH_GPUIOV_DW6_1__DATA__SHIFT 0x0
+#define MMSCH_GPUIOV_DW6_1__DATA_MASK 0xFFFFFFFFL
+//MMSCH_GPUIOV_DW7_1
+#define MMSCH_GPUIOV_DW7_1__DATA__SHIFT 0x0
+#define MMSCH_GPUIOV_DW7_1__DATA_MASK 0xFFFFFFFFL
+//MMSCH_GPUIOV_DW8_1
+#define MMSCH_GPUIOV_DW8_1__DATA__SHIFT 0x0
+#define MMSCH_GPUIOV_DW8_1__DATA_MASK 0xFFFFFFFFL
+//MMSCH_GPUIOV_CNTXT
+#define MMSCH_GPUIOV_CNTXT__CNTXT_SIZE__SHIFT 0x0
+#define MMSCH_GPUIOV_CNTXT__CNTXT_LOCATION__SHIFT 0x7
+#define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET__SHIFT 0xa
+#define MMSCH_GPUIOV_CNTXT__CNTXT_SIZE_MASK 0x0000007FL
+#define MMSCH_GPUIOV_CNTXT__CNTXT_LOCATION_MASK 0x00000080L
+#define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET_MASK 0xFFFFFC00L
+//MMSCH_SCRATCH_2
+#define MMSCH_SCRATCH_2__SCRATCH_2__SHIFT 0x0
+#define MMSCH_SCRATCH_2__SCRATCH_2_MASK 0xFFFFFFFFL
+//MMSCH_SCRATCH_3
+#define MMSCH_SCRATCH_3__SCRATCH_3__SHIFT 0x0
+#define MMSCH_SCRATCH_3__SCRATCH_3_MASK 0xFFFFFFFFL
+//MMSCH_SCRATCH_4
+#define MMSCH_SCRATCH_4__SCRATCH_4__SHIFT 0x0
+#define MMSCH_SCRATCH_4__SCRATCH_4_MASK 0xFFFFFFFFL
+//MMSCH_SCRATCH_5
+#define MMSCH_SCRATCH_5__SCRATCH_5__SHIFT 0x0
+#define MMSCH_SCRATCH_5__SCRATCH_5_MASK 0xFFFFFFFFL
+//MMSCH_SCRATCH_6
+#define MMSCH_SCRATCH_6__SCRATCH_6__SHIFT 0x0
+#define MMSCH_SCRATCH_6__SCRATCH_6_MASK 0xFFFFFFFFL
+//MMSCH_SCRATCH_7
+#define MMSCH_SCRATCH_7__SCRATCH_7__SHIFT 0x0
+#define MMSCH_SCRATCH_7__SCRATCH_7_MASK 0xFFFFFFFFL
+//MMSCH_VFID_FIFO_HEAD_0
+#define MMSCH_VFID_FIFO_HEAD_0__HEAD__SHIFT 0x0
+#define MMSCH_VFID_FIFO_HEAD_0__HEAD_MASK 0x0000003FL
+//MMSCH_VFID_FIFO_TAIL_0
+#define MMSCH_VFID_FIFO_TAIL_0__TAIL__SHIFT 0x0
+#define MMSCH_VFID_FIFO_TAIL_0__TAIL_MASK 0x0000003FL
+//MMSCH_VFID_FIFO_HEAD_1
+#define MMSCH_VFID_FIFO_HEAD_1__HEAD__SHIFT 0x0
+#define MMSCH_VFID_FIFO_HEAD_1__HEAD_MASK 0x0000003FL
+//MMSCH_VFID_FIFO_TAIL_1
+#define MMSCH_VFID_FIFO_TAIL_1__TAIL__SHIFT 0x0
+#define MMSCH_VFID_FIFO_TAIL_1__TAIL_MASK 0x0000003FL
+//MMSCH_NACK_STATUS
+#define MMSCH_NACK_STATUS__WR_NACK_STATUS__SHIFT 0x0
+#define MMSCH_NACK_STATUS__RD_NACK_STATUS__SHIFT 0x2
+#define MMSCH_NACK_STATUS__WR_NACK_STATUS_MASK 0x00000003L
+#define MMSCH_NACK_STATUS__RD_NACK_STATUS_MASK 0x0000000CL
+//MMSCH_VF_MAILBOX0_DATA
+#define MMSCH_VF_MAILBOX0_DATA__DATA__SHIFT 0x0
+#define MMSCH_VF_MAILBOX0_DATA__DATA_MASK 0xFFFFFFFFL
+//MMSCH_VF_MAILBOX1_DATA
+#define MMSCH_VF_MAILBOX1_DATA__DATA__SHIFT 0x0
+#define MMSCH_VF_MAILBOX1_DATA__DATA_MASK 0xFFFFFFFFL
+//MMSCH_GPUIOV_SCH_BLOCK_IP_0
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__ID__SHIFT 0x0
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__VERSION__SHIFT 0x4
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__SIZE__SHIFT 0x8
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__ID_MASK 0x0000000FL
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__VERSION_MASK 0x000000F0L
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__SIZE_MASK 0x0000FF00L
+//MMSCH_GPUIOV_CMD_STATUS_IP_0
+#define MMSCH_GPUIOV_CMD_STATUS_IP_0__CMD_STATUS__SHIFT 0x0
+#define MMSCH_GPUIOV_CMD_STATUS_IP_0__CMD_STATUS_MASK 0x0000000FL
+//MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID__SHIFT 0x0
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_STATUS__SHIFT 0x8
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_MASK 0x000000FFL
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_STATUS_MASK 0x00000F00L
+//MMSCH_GPUIOV_SCH_BLOCK_IP_1
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__ID__SHIFT 0x0
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__VERSION__SHIFT 0x4
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__SIZE__SHIFT 0x8
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__ID_MASK 0x0000000FL
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__VERSION_MASK 0x000000F0L
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__SIZE_MASK 0x0000FF00L
+//MMSCH_GPUIOV_CMD_STATUS_IP_1
+#define MMSCH_GPUIOV_CMD_STATUS_IP_1__CMD_STATUS__SHIFT 0x0
+#define MMSCH_GPUIOV_CMD_STATUS_IP_1__CMD_STATUS_MASK 0x0000000FL
+//MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID__SHIFT 0x0
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_STATUS__SHIFT 0x8
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_MASK 0x000000FFL
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_STATUS_MASK 0x00000F00L
+//MMSCH_GPUIOV_CNTXT_IP
+#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_SIZE__SHIFT 0x0
+#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_LOCATION__SHIFT 0x7
+#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_SIZE_MASK 0x0000007FL
+#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_LOCATION_MASK 0x00000080L
+//MMSCH_GPUIOV_SCH_BLOCK_2
+#define MMSCH_GPUIOV_SCH_BLOCK_2__ID__SHIFT 0x0
+#define MMSCH_GPUIOV_SCH_BLOCK_2__VERSION__SHIFT 0x4
+#define MMSCH_GPUIOV_SCH_BLOCK_2__SIZE__SHIFT 0x8
+#define MMSCH_GPUIOV_SCH_BLOCK_2__ID_MASK 0x0000000FL
+#define MMSCH_GPUIOV_SCH_BLOCK_2__VERSION_MASK 0x000000F0L
+#define MMSCH_GPUIOV_SCH_BLOCK_2__SIZE_MASK 0x0000FF00L
+//MMSCH_GPUIOV_CMD_CONTROL_2
+#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_TYPE__SHIFT 0x0
+#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE__SHIFT 0x4
+#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_INTR_EN__SHIFT 0x5
+#define MMSCH_GPUIOV_CMD_CONTROL_2__VM_BUSY_INTR_EN__SHIFT 0x6
+#define MMSCH_GPUIOV_CMD_CONTROL_2__FUNCTINO_ID__SHIFT 0x8
+#define MMSCH_GPUIOV_CMD_CONTROL_2__NEXT_FUNCTINO_ID__SHIFT 0x10
+#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_TYPE_MASK 0x0000000FL
+#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_MASK 0x00000010L
+#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_INTR_EN_MASK 0x00000020L
+#define MMSCH_GPUIOV_CMD_CONTROL_2__VM_BUSY_INTR_EN_MASK 0x00000040L
+#define MMSCH_GPUIOV_CMD_CONTROL_2__FUNCTINO_ID_MASK 0x0000FF00L
+#define MMSCH_GPUIOV_CMD_CONTROL_2__NEXT_FUNCTINO_ID_MASK 0x00FF0000L
+//MMSCH_GPUIOV_CMD_STATUS_2
+#define MMSCH_GPUIOV_CMD_STATUS_2__CMD_STATUS__SHIFT 0x0
+#define MMSCH_GPUIOV_CMD_STATUS_2__CMD_STATUS_MASK 0x0000000FL
+//MMSCH_GPUIOV_VM_BUSY_STATUS_2
+#define MMSCH_GPUIOV_VM_BUSY_STATUS_2__BUSY__SHIFT 0x0
+#define MMSCH_GPUIOV_VM_BUSY_STATUS_2__BUSY_MASK 0xFFFFFFFFL
+//MMSCH_GPUIOV_ACTIVE_FCNS_2
+#define MMSCH_GPUIOV_ACTIVE_FCNS_2__ACTIVE_FCNS__SHIFT 0x0
+#define MMSCH_GPUIOV_ACTIVE_FCNS_2__ACTIVE_FCNS_MASK 0xFFFFFFFFL
+//MMSCH_GPUIOV_ACTIVE_FCN_ID_2
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID__SHIFT 0x0
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_STATUS__SHIFT 0x8
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_MASK 0x000000FFL
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_STATUS_MASK 0x00000F00L
+//MMSCH_GPUIOV_DW6_2
+#define MMSCH_GPUIOV_DW6_2__DATA__SHIFT 0x0
+#define MMSCH_GPUIOV_DW6_2__DATA_MASK 0xFFFFFFFFL
+//MMSCH_GPUIOV_DW7_2
+#define MMSCH_GPUIOV_DW7_2__DATA__SHIFT 0x0
+#define MMSCH_GPUIOV_DW7_2__DATA_MASK 0xFFFFFFFFL
+//MMSCH_GPUIOV_DW8_2
+#define MMSCH_GPUIOV_DW8_2__DATA__SHIFT 0x0
+#define MMSCH_GPUIOV_DW8_2__DATA_MASK 0xFFFFFFFFL
+//MMSCH_GPUIOV_SCH_BLOCK_IP_2
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__ID__SHIFT 0x0
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__VERSION__SHIFT 0x4
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE__SHIFT 0x8
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__ID_MASK 0x0000000FL
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__VERSION_MASK 0x000000F0L
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE_MASK 0x0000FF00L
+//MMSCH_GPUIOV_CMD_STATUS_IP_2
+#define MMSCH_GPUIOV_CMD_STATUS_IP_2__CMD_STATUS__SHIFT 0x0
+#define MMSCH_GPUIOV_CMD_STATUS_IP_2__CMD_STATUS_MASK 0x0000000FL
+//MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID__SHIFT 0x0
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_STATUS__SHIFT 0x8
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_MASK 0x000000FFL
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_STATUS_MASK 0x00000F00L
+//MMSCH_VFID_FIFO_HEAD_2
+#define MMSCH_VFID_FIFO_HEAD_2__HEAD__SHIFT 0x0
+#define MMSCH_VFID_FIFO_HEAD_2__HEAD_MASK 0x0000003FL
+//MMSCH_VFID_FIFO_TAIL_2
+#define MMSCH_VFID_FIFO_TAIL_2__TAIL__SHIFT 0x0
+#define MMSCH_VFID_FIFO_TAIL_2__TAIL_MASK 0x0000003FL
+//MMSCH_VM_BUSY_STATUS_0
+#define MMSCH_VM_BUSY_STATUS_0__BUSY__SHIFT 0x0
+#define MMSCH_VM_BUSY_STATUS_0__BUSY_MASK 0xFFFFFFFFL
+//MMSCH_VM_BUSY_STATUS_1
+#define MMSCH_VM_BUSY_STATUS_1__BUSY__SHIFT 0x0
+#define MMSCH_VM_BUSY_STATUS_1__BUSY_MASK 0xFFFFFFFFL
+//MMSCH_VM_BUSY_STATUS_2
+#define MMSCH_VM_BUSY_STATUS_2__BUSY__SHIFT 0x0
+#define MMSCH_VM_BUSY_STATUS_2__BUSY_MASK 0xFFFFFFFFL
+
+
+// addressBlock: uvd0_uvd_jmi_dec
+//UVD_JADP_MCIF_URGENT_CTRL
+#define UVD_JADP_MCIF_URGENT_CTRL__WR_WATERMARK__SHIFT 0x0
+#define UVD_JADP_MCIF_URGENT_CTRL__RD_WATERMARK__SHIFT 0x6
+#define UVD_JADP_MCIF_URGENT_CTRL__WR_RD_URGENT_TIMER__SHIFT 0xb
+#define UVD_JADP_MCIF_URGENT_CTRL__WR_URGENT_PROG_STEP__SHIFT 0x11
+#define UVD_JADP_MCIF_URGENT_CTRL__RD_URGENT_PROG_STEP__SHIFT 0x15
+#define UVD_JADP_MCIF_URGENT_CTRL__WR_QOS_EN__SHIFT 0x19
+#define UVD_JADP_MCIF_URGENT_CTRL__RD_QOS_EN__SHIFT 0x1a
+#define UVD_JADP_MCIF_URGENT_CTRL__WR_WATERMARK_MASK 0x0000003FL
+#define UVD_JADP_MCIF_URGENT_CTRL__RD_WATERMARK_MASK 0x000007C0L
+#define UVD_JADP_MCIF_URGENT_CTRL__WR_RD_URGENT_TIMER_MASK 0x0001F800L
+#define UVD_JADP_MCIF_URGENT_CTRL__WR_URGENT_PROG_STEP_MASK 0x001E0000L
+#define UVD_JADP_MCIF_URGENT_CTRL__RD_URGENT_PROG_STEP_MASK 0x01E00000L
+#define UVD_JADP_MCIF_URGENT_CTRL__WR_QOS_EN_MASK 0x02000000L
+#define UVD_JADP_MCIF_URGENT_CTRL__RD_QOS_EN_MASK 0x04000000L
+//UVD_JMI_URGENT_CTRL
+#define UVD_JMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL__SHIFT 0x0
+#define UVD_JMI_URGENT_CTRL__ASSERT_MC_RD_URGENT__SHIFT 0x4
+#define UVD_JMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL__SHIFT 0x10
+#define UVD_JMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT 0x14
+#define UVD_JMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL_MASK 0x00000001L
+#define UVD_JMI_URGENT_CTRL__ASSERT_MC_RD_URGENT_MASK 0x000000F0L
+#define UVD_JMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL_MASK 0x00010000L
+#define UVD_JMI_URGENT_CTRL__ASSERT_MC_WR_URGENT_MASK 0x00F00000L
+//UVD_JPEG_DEC_PF_CTRL
+#define UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS__SHIFT 0x0
+#define UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING__SHIFT 0x1
+#define UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS_MASK 0x00000001L
+#define UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING_MASK 0x00000002L
+//UVD_JPEG_ENC_PF_CTRL
+#define UVD_JPEG_ENC_PF_CTRL__ENC_PF_HANDLING_DIS__SHIFT 0x0
+#define UVD_JPEG_ENC_PF_CTRL__ENC_PF_SW_GATING__SHIFT 0x1
+#define UVD_JPEG_ENC_PF_CTRL__ENC_PF_HANDLING_DIS_MASK 0x00000001L
+#define UVD_JPEG_ENC_PF_CTRL__ENC_PF_SW_GATING_MASK 0x00000002L
+//UVD_JMI_CTRL
+#define UVD_JMI_CTRL__STALL_MC_ARB__SHIFT 0x0
+#define UVD_JMI_CTRL__MASK_MC_URGENT__SHIFT 0x1
+#define UVD_JMI_CTRL__ASSERT_MC_URGENT__SHIFT 0x2
+#define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER__SHIFT 0x8
+#define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER__SHIFT 0x10
+#define UVD_JMI_CTRL__CRC_RESET__SHIFT 0x18
+#define UVD_JMI_CTRL__CRC_SEL__SHIFT 0x19
+#define UVD_JMI_CTRL__STALL_MC_ARB_MASK 0x00000001L
+#define UVD_JMI_CTRL__MASK_MC_URGENT_MASK 0x00000002L
+#define UVD_JMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000004L
+#define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER_MASK 0x0000FF00L
+#define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER_MASK 0x00FF0000L
+#define UVD_JMI_CTRL__CRC_RESET_MASK 0x01000000L
+#define UVD_JMI_CTRL__CRC_SEL_MASK 0x1E000000L
+//UVD_LMI_JRBC_CTRL
+#define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0
+#define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1
+#define UVD_LMI_JRBC_CTRL__RD_MAX_BURST__SHIFT 0x4
+#define UVD_LMI_JRBC_CTRL__WR_MAX_BURST__SHIFT 0x8
+#define UVD_LMI_JRBC_CTRL__RD_SWAP__SHIFT 0x14
+#define UVD_LMI_JRBC_CTRL__WR_SWAP__SHIFT 0x16
+#define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L
+#define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L
+#define UVD_LMI_JRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L
+#define UVD_LMI_JRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L
+#define UVD_LMI_JRBC_CTRL__RD_SWAP_MASK 0x00300000L
+#define UVD_LMI_JRBC_CTRL__WR_SWAP_MASK 0x00C00000L
+//UVD_LMI_JPEG_CTRL
+#define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0
+#define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1
+#define UVD_LMI_JPEG_CTRL__RD_MAX_BURST__SHIFT 0x4
+#define UVD_LMI_JPEG_CTRL__WR_MAX_BURST__SHIFT 0x8
+#define UVD_LMI_JPEG_CTRL__RD_SWAP__SHIFT 0x14
+#define UVD_LMI_JPEG_CTRL__WR_SWAP__SHIFT 0x16
+#define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L
+#define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L
+#define UVD_LMI_JPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L
+#define UVD_LMI_JPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L
+#define UVD_LMI_JPEG_CTRL__RD_SWAP_MASK 0x00300000L
+#define UVD_LMI_JPEG_CTRL__WR_SWAP_MASK 0x00C00000L
+//UVD_JMI_EJRBC_CTRL
+#define UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0
+#define UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1
+#define UVD_JMI_EJRBC_CTRL__RD_MAX_BURST__SHIFT 0x4
+#define UVD_JMI_EJRBC_CTRL__WR_MAX_BURST__SHIFT 0x8
+#define UVD_JMI_EJRBC_CTRL__RD_SWAP__SHIFT 0x14
+#define UVD_JMI_EJRBC_CTRL__WR_SWAP__SHIFT 0x16
+#define UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L
+#define UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L
+#define UVD_JMI_EJRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L
+#define UVD_JMI_EJRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L
+#define UVD_JMI_EJRBC_CTRL__RD_SWAP_MASK 0x00300000L
+#define UVD_JMI_EJRBC_CTRL__WR_SWAP_MASK 0x00C00000L
+//UVD_LMI_EJPEG_CTRL
+#define UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0
+#define UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1
+#define UVD_LMI_EJPEG_CTRL__RD_MAX_BURST__SHIFT 0x4
+#define UVD_LMI_EJPEG_CTRL__WR_MAX_BURST__SHIFT 0x8
+#define UVD_LMI_EJPEG_CTRL__RD_SWAP__SHIFT 0x14
+#define UVD_LMI_EJPEG_CTRL__WR_SWAP__SHIFT 0x16
+#define UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L
+#define UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L
+#define UVD_LMI_EJPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L
+#define UVD_LMI_EJPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L
+#define UVD_LMI_EJPEG_CTRL__RD_SWAP_MASK 0x00300000L
+#define UVD_LMI_EJPEG_CTRL__WR_SWAP_MASK 0x00C00000L
+//UVD_JMI_SCALER_CTRL
+#define UVD_JMI_SCALER_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0
+#define UVD_JMI_SCALER_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1
+#define UVD_JMI_SCALER_CTRL__RD_MAX_BURST__SHIFT 0x4
+#define UVD_JMI_SCALER_CTRL__WR_MAX_BURST__SHIFT 0x8
+#define UVD_JMI_SCALER_CTRL__RD_SWAP__SHIFT 0x14
+#define UVD_JMI_SCALER_CTRL__WR_SWAP__SHIFT 0x16
+#define UVD_JMI_SCALER_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L
+#define UVD_JMI_SCALER_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L
+#define UVD_JMI_SCALER_CTRL__RD_MAX_BURST_MASK 0x000000F0L
+#define UVD_JMI_SCALER_CTRL__WR_MAX_BURST_MASK 0x00000F00L
+#define UVD_JMI_SCALER_CTRL__RD_SWAP_MASK 0x00300000L
+#define UVD_JMI_SCALER_CTRL__WR_SWAP_MASK 0x00C00000L
+//JPEG_LMI_DROP
+#define JPEG_LMI_DROP__JPEG_WR_DROP__SHIFT 0x0
+#define JPEG_LMI_DROP__JRBC_WR_DROP__SHIFT 0x1
+#define JPEG_LMI_DROP__JPEG_RD_DROP__SHIFT 0x2
+#define JPEG_LMI_DROP__JRBC_RD_DROP__SHIFT 0x3
+#define JPEG_LMI_DROP__JPEG_WR_DROP_MASK 0x00000001L
+#define JPEG_LMI_DROP__JRBC_WR_DROP_MASK 0x00000002L
+#define JPEG_LMI_DROP__JPEG_RD_DROP_MASK 0x00000004L
+#define JPEG_LMI_DROP__JRBC_RD_DROP_MASK 0x00000008L
+//UVD_JMI_EJPEG_DROP
+#define UVD_JMI_EJPEG_DROP__EJRBC_RD_DROP__SHIFT 0x0
+#define UVD_JMI_EJPEG_DROP__EJRBC_WR_DROP__SHIFT 0x1
+#define UVD_JMI_EJPEG_DROP__EJPEG_RD_DROP__SHIFT 0x2
+#define UVD_JMI_EJPEG_DROP__EJPEG_WR_DROP__SHIFT 0x3
+#define UVD_JMI_EJPEG_DROP__SCALAR_RD_DROP__SHIFT 0x4
+#define UVD_JMI_EJPEG_DROP__SCALAR_WR_DROP__SHIFT 0x5
+#define UVD_JMI_EJPEG_DROP__EJRBC_RD_DROP_MASK 0x00000001L
+#define UVD_JMI_EJPEG_DROP__EJRBC_WR_DROP_MASK 0x00000002L
+#define UVD_JMI_EJPEG_DROP__EJPEG_RD_DROP_MASK 0x00000004L
+#define UVD_JMI_EJPEG_DROP__EJPEG_WR_DROP_MASK 0x00000008L
+#define UVD_JMI_EJPEG_DROP__SCALAR_RD_DROP_MASK 0x00000010L
+#define UVD_JMI_EJPEG_DROP__SCALAR_WR_DROP_MASK 0x00000020L
+//JPEG_MEMCHECK_CLAMPING
+#define JPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN__SHIFT 0xd
+#define JPEG_MEMCHECK_CLAMPING__JPEG2_WR_CLAMPING_EN__SHIFT 0xe
+#define JPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN__SHIFT 0x16
+#define JPEG_MEMCHECK_CLAMPING__JPEG2_RD_CLAMPING_EN__SHIFT 0x17
+#define JPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN__SHIFT 0x19
+#define JPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN__SHIFT 0x1a
+#define JPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN__SHIFT 0x1f
+#define JPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN_MASK 0x00002000L
+#define JPEG_MEMCHECK_CLAMPING__JPEG2_WR_CLAMPING_EN_MASK 0x00004000L
+#define JPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN_MASK 0x00400000L
+#define JPEG_MEMCHECK_CLAMPING__JPEG2_RD_CLAMPING_EN_MASK 0x00800000L
+#define JPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN_MASK 0x02000000L
+#define JPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN_MASK 0x04000000L
+#define JPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN_MASK 0x80000000L
+//UVD_JMI_EJPEG_MEMCHECK_CLAMPING
+#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN__SHIFT 0x0
+#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN__SHIFT 0x1
+#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN__SHIFT 0x2
+#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN__SHIFT 0x3
+#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_RD_CLAMPING_EN__SHIFT 0x4
+#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_WR_CLAMPING_EN__SHIFT 0x5
+#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN__SHIFT 0x1f
+#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN_MASK 0x00000001L
+#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN_MASK 0x00000002L
+#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN_MASK 0x00000004L
+#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN_MASK 0x00000008L
+#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_RD_CLAMPING_EN_MASK 0x00000010L
+#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_WR_CLAMPING_EN_MASK 0x00000020L
+#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN_MASK 0x80000000L
+//UVD_LMI_JRBC_IB_VMID
+#define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0
+#define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4
+#define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8
+#define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL
+#define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L
+#define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L
+//UVD_LMI_JRBC_RB_VMID
+#define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0
+#define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4
+#define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8
+#define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL
+#define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L
+#define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L
+//UVD_LMI_JPEG_VMID
+#define UVD_LMI_JPEG_VMID__JPEG_RD_VMID__SHIFT 0x0
+#define UVD_LMI_JPEG_VMID__JPEG_WR_VMID__SHIFT 0x4
+#define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID__SHIFT 0x8
+#define UVD_LMI_JPEG_VMID__JPEG_RD_VMID_MASK 0x0000000FL
+#define UVD_LMI_JPEG_VMID__JPEG_WR_VMID_MASK 0x000000F0L
+#define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID_MASK 0x00000F00L
+//UVD_JMI_ENC_JRBC_IB_VMID
+#define UVD_JMI_ENC_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0
+#define UVD_JMI_ENC_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4
+#define UVD_JMI_ENC_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8
+#define UVD_JMI_ENC_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL
+#define UVD_JMI_ENC_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L
+#define UVD_JMI_ENC_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L
+//UVD_JMI_ENC_JRBC_RB_VMID
+#define UVD_JMI_ENC_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0
+#define UVD_JMI_ENC_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4
+#define UVD_JMI_ENC_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8
+#define UVD_JMI_ENC_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL
+#define UVD_JMI_ENC_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L
+#define UVD_JMI_ENC_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L
+//UVD_JMI_ENC_JPEG_VMID
+#define UVD_JMI_ENC_JPEG_VMID__PEL_RD_VMID__SHIFT 0x0
+#define UVD_JMI_ENC_JPEG_VMID__BS_WR_VMID__SHIFT 0x5
+#define UVD_JMI_ENC_JPEG_VMID__SCALAR_RD_VMID__SHIFT 0xa
+#define UVD_JMI_ENC_JPEG_VMID__SCALAR_WR_VMID__SHIFT 0xf
+#define UVD_JMI_ENC_JPEG_VMID__HUFF_FENCE_VMID__SHIFT 0x13
+#define UVD_JMI_ENC_JPEG_VMID__ATOMIC_USER1_WR_VMID__SHIFT 0x17
+#define UVD_JMI_ENC_JPEG_VMID__PEL_RD_VMID_MASK 0x0000000FL
+#define UVD_JMI_ENC_JPEG_VMID__BS_WR_VMID_MASK 0x000001E0L
+#define UVD_JMI_ENC_JPEG_VMID__SCALAR_RD_VMID_MASK 0x00003C00L
+#define UVD_JMI_ENC_JPEG_VMID__SCALAR_WR_VMID_MASK 0x00078000L
+#define UVD_JMI_ENC_JPEG_VMID__HUFF_FENCE_VMID_MASK 0x00780000L
+#define UVD_JMI_ENC_JPEG_VMID__ATOMIC_USER1_WR_VMID_MASK 0x07800000L
+//UVD_JMI_EJPEG_RAS_CNTL
+#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_IH_EN__SHIFT 0x0
+#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_PMI_EN__SHIFT 0x1
+#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_REARM__SHIFT 0x2
+#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_STALL_EN__SHIFT 0x3
+#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_READY__SHIFT 0x4
+#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_IH_EN_MASK 0x00000001L
+#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_PMI_EN_MASK 0x00000002L
+#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_REARM_MASK 0x00000004L
+#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_STALL_EN_MASK 0x00000008L
+#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_READY_MASK 0x00000010L
+//JPEG_MEMCHECK_SAFE_ADDR
+#define JPEG_MEMCHECK_SAFE_ADDR__MEMCHECK_SAFE_ADDR__SHIFT 0x0
+#define JPEG_MEMCHECK_SAFE_ADDR__MEMCHECK_SAFE_ADDR_MASK 0xFFFFFFFFL
+//JPEG_MEMCHECK_SAFE_ADDR_64BIT
+#define JPEG_MEMCHECK_SAFE_ADDR_64BIT__MEMCHECK_SAFE_ADDR_64BIT__SHIFT 0x0
+#define JPEG_MEMCHECK_SAFE_ADDR_64BIT__MEMCHECK_SAFE_ADDR_64BIT_MASK 0xFFFFFFFFL
+//UVD_JMI_LAT_CTRL
+#define UVD_JMI_LAT_CTRL__SCALE__SHIFT 0x0
+#define UVD_JMI_LAT_CTRL__MAX_START__SHIFT 0x8
+#define UVD_JMI_LAT_CTRL__MIN_START__SHIFT 0x9
+#define UVD_JMI_LAT_CTRL__AVG_START__SHIFT 0xa
+#define UVD_JMI_LAT_CTRL__PERFMON_SYNC__SHIFT 0xb
+#define UVD_JMI_LAT_CTRL__SKIP__SHIFT 0x10
+#define UVD_JMI_LAT_CTRL__SCALE_MASK 0x000000FFL
+#define UVD_JMI_LAT_CTRL__MAX_START_MASK 0x00000100L
+#define UVD_JMI_LAT_CTRL__MIN_START_MASK 0x00000200L
+#define UVD_JMI_LAT_CTRL__AVG_START_MASK 0x00000400L
+#define UVD_JMI_LAT_CTRL__PERFMON_SYNC_MASK 0x00000800L
+#define UVD_JMI_LAT_CTRL__SKIP_MASK 0x000F0000L
+//UVD_JMI_LAT_CNTR
+#define UVD_JMI_LAT_CNTR__MAX_LAT__SHIFT 0x0
+#define UVD_JMI_LAT_CNTR__MIN_LAT__SHIFT 0x8
+#define UVD_JMI_LAT_CNTR__MAX_LAT_MASK 0x000000FFL
+#define UVD_JMI_LAT_CNTR__MIN_LAT_MASK 0x0000FF00L
+//UVD_JMI_AVG_LAT_CNTR
+#define UVD_JMI_AVG_LAT_CNTR__ENV_LOW__SHIFT 0x0
+#define UVD_JMI_AVG_LAT_CNTR__ENV_HIGH__SHIFT 0x8
+#define UVD_JMI_AVG_LAT_CNTR__ENV_HIT__SHIFT 0x10
+#define UVD_JMI_AVG_LAT_CNTR__ENV_LOW_MASK 0x000000FFL
+#define UVD_JMI_AVG_LAT_CNTR__ENV_HIGH_MASK 0x0000FF00L
+#define UVD_JMI_AVG_LAT_CNTR__ENV_HIT_MASK 0xFFFF0000L
+//UVD_JMI_PERFMON_CTRL
+#define UVD_JMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0
+#define UVD_JMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8
+#define UVD_JMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L
+#define UVD_JMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00000F00L
+//UVD_JMI_PERFMON_COUNT_LO
+#define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0
+#define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL
+//UVD_JMI_PERFMON_COUNT_HI
+#define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0
+#define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL
+//UVD_JMI_CLEAN_STATUS
+#define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN__SHIFT 0x0
+#define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_RAW__SHIFT 0x1
+#define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN__SHIFT 0x2
+#define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_RAW__SHIFT 0x3
+#define UVD_JMI_CLEAN_STATUS__DJRBC_READ_CLEAN__SHIFT 0x4
+#define UVD_JMI_CLEAN_STATUS__EJRBC_READ_CLEAN__SHIFT 0x5
+#define UVD_JMI_CLEAN_STATUS__JPEG_READ_CLEAN__SHIFT 0x6
+#define UVD_JMI_CLEAN_STATUS__PEL_READ_CLEAN__SHIFT 0x7
+#define UVD_JMI_CLEAN_STATUS__SCALAR_READ_CLEAN__SHIFT 0x8
+#define UVD_JMI_CLEAN_STATUS__DJRBC_WRITE_CLEAN__SHIFT 0x9
+#define UVD_JMI_CLEAN_STATUS__EJRBC_WRITE_CLEAN__SHIFT 0xa
+#define UVD_JMI_CLEAN_STATUS__BS_WRITE_CLEAN__SHIFT 0xb
+#define UVD_JMI_CLEAN_STATUS__JPEG_WRITE_CLEAN__SHIFT 0xc
+#define UVD_JMI_CLEAN_STATUS__SCALAR_WRITE_CLEAN__SHIFT 0xd
+#define UVD_JMI_CLEAN_STATUS__MC_WRITE_PENDING__SHIFT 0xe
+#define UVD_JMI_CLEAN_STATUS__JPEG2_WRITE_CLEAN__SHIFT 0xf
+#define UVD_JMI_CLEAN_STATUS__JPEG2_READ_CLEAN__SHIFT 0x10
+#define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_MASK 0x00000001L
+#define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_RAW_MASK 0x00000002L
+#define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_MASK 0x00000004L
+#define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_RAW_MASK 0x00000008L
+#define UVD_JMI_CLEAN_STATUS__DJRBC_READ_CLEAN_MASK 0x00000010L
+#define UVD_JMI_CLEAN_STATUS__EJRBC_READ_CLEAN_MASK 0x00000020L
+#define UVD_JMI_CLEAN_STATUS__JPEG_READ_CLEAN_MASK 0x00000040L
+#define UVD_JMI_CLEAN_STATUS__PEL_READ_CLEAN_MASK 0x00000080L
+#define UVD_JMI_CLEAN_STATUS__SCALAR_READ_CLEAN_MASK 0x00000100L
+#define UVD_JMI_CLEAN_STATUS__DJRBC_WRITE_CLEAN_MASK 0x00000200L
+#define UVD_JMI_CLEAN_STATUS__EJRBC_WRITE_CLEAN_MASK 0x00000400L
+#define UVD_JMI_CLEAN_STATUS__BS_WRITE_CLEAN_MASK 0x00000800L
+#define UVD_JMI_CLEAN_STATUS__JPEG_WRITE_CLEAN_MASK 0x00001000L
+#define UVD_JMI_CLEAN_STATUS__SCALAR_WRITE_CLEAN_MASK 0x00002000L
+#define UVD_JMI_CLEAN_STATUS__MC_WRITE_PENDING_MASK 0x00004000L
+#define UVD_JMI_CLEAN_STATUS__JPEG2_WRITE_CLEAN_MASK 0x00008000L
+#define UVD_JMI_CLEAN_STATUS__JPEG2_READ_CLEAN_MASK 0x00010000L
+//UVD_LMI_JPEG_READ_64BIT_BAR_LOW
+#define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_JPEG_READ_64BIT_BAR_HIGH
+#define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW
+#define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH
+#define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW
+#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH
+#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_JRBC_RB_64BIT_BAR_LOW
+#define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_JRBC_RB_64BIT_BAR_HIGH
+#define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_JRBC_IB_64BIT_BAR_LOW
+#define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_JRBC_IB_64BIT_BAR_HIGH
+#define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW
+#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH
+#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW
+#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH
+#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW
+#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH
+#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW
+#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH
+#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_JMI_PEL_RD_64BIT_BAR_LOW
+#define UVD_JMI_PEL_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_JMI_PEL_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_JMI_PEL_RD_64BIT_BAR_HIGH
+#define UVD_JMI_PEL_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_JMI_PEL_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_JMI_BS_WR_64BIT_BAR_LOW
+#define UVD_JMI_BS_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_JMI_BS_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_JMI_BS_WR_64BIT_BAR_HIGH
+#define UVD_JMI_BS_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_JMI_BS_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_JMI_SCALAR_RD_64BIT_BAR_LOW
+#define UVD_JMI_SCALAR_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_JMI_SCALAR_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_JMI_SCALAR_RD_64BIT_BAR_HIGH
+#define UVD_JMI_SCALAR_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_JMI_SCALAR_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_JMI_SCALAR_WR_64BIT_BAR_LOW
+#define UVD_JMI_SCALAR_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_JMI_SCALAR_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_JMI_SCALAR_WR_64BIT_BAR_HIGH
+#define UVD_JMI_SCALAR_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_JMI_SCALAR_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW
+#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH
+#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_EJRBC_RB_64BIT_BAR_LOW
+#define UVD_LMI_EJRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_EJRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH
+#define UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_EJRBC_IB_64BIT_BAR_LOW
+#define UVD_LMI_EJRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_EJRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH
+#define UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW
+#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH
+#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW
+#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH
+#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW
+#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH
+#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW
+#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH
+#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_JPEG_PREEMPT_VMID
+#define UVD_LMI_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0
+#define UVD_LMI_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL
+//UVD_LMI_ENC_JPEG_PREEMPT_VMID
+#define UVD_LMI_ENC_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0
+#define UVD_LMI_ENC_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL
+//UVD_LMI_JPEG2_VMID
+#define UVD_LMI_JPEG2_VMID__JPEG2_RD_VMID__SHIFT 0x0
+#define UVD_LMI_JPEG2_VMID__JPEG2_WR_VMID__SHIFT 0x4
+#define UVD_LMI_JPEG2_VMID__JPEG2_RD_VMID_MASK 0x0000000FL
+#define UVD_LMI_JPEG2_VMID__JPEG2_WR_VMID_MASK 0x000000F0L
+//UVD_LMI_JPEG2_READ_64BIT_BAR_LOW
+#define UVD_LMI_JPEG2_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_JPEG2_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH
+#define UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW
+#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH
+#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_JPEG_CTRL2
+#define UVD_LMI_JPEG_CTRL2__ARB_RD_WAIT_EN__SHIFT 0x0
+#define UVD_LMI_JPEG_CTRL2__ARB_WR_WAIT_EN__SHIFT 0x1
+#define UVD_LMI_JPEG_CTRL2__RD_MAX_BURST__SHIFT 0x4
+#define UVD_LMI_JPEG_CTRL2__WR_MAX_BURST__SHIFT 0x8
+#define UVD_LMI_JPEG_CTRL2__RD_SWAP__SHIFT 0x14
+#define UVD_LMI_JPEG_CTRL2__WR_SWAP__SHIFT 0x16
+#define UVD_LMI_JPEG_CTRL2__ARB_RD_WAIT_EN_MASK 0x00000001L
+#define UVD_LMI_JPEG_CTRL2__ARB_WR_WAIT_EN_MASK 0x00000002L
+#define UVD_LMI_JPEG_CTRL2__RD_MAX_BURST_MASK 0x000000F0L
+#define UVD_LMI_JPEG_CTRL2__WR_MAX_BURST_MASK 0x00000F00L
+#define UVD_LMI_JPEG_CTRL2__RD_SWAP_MASK 0x00300000L
+#define UVD_LMI_JPEG_CTRL2__WR_SWAP_MASK 0x00C00000L
+//UVD_JMI_DEC_SWAP_CNTL
+#define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0
+#define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2
+#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4
+#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6
+#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8
+#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa
+#define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc
+#define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP__SHIFT 0xe
+#define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP__SHIFT 0x10
+#define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L
+#define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL
+#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L
+#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L
+#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L
+#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L
+#define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L
+#define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP_MASK 0x0000C000L
+#define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP_MASK 0x00030000L
+//UVD_JMI_ENC_SWAP_CNTL
+#define UVD_JMI_ENC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0
+#define UVD_JMI_ENC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2
+#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4
+#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6
+#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8
+#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa
+#define UVD_JMI_ENC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc
+#define UVD_JMI_ENC_SWAP_CNTL__PEL_RD_MC_SWAP__SHIFT 0xe
+#define UVD_JMI_ENC_SWAP_CNTL__BS_WR_MC_SWAP__SHIFT 0x10
+#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_RD_MC_SWAP__SHIFT 0x12
+#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_WR_MC_SWAP__SHIFT 0x14
+#define UVD_JMI_ENC_SWAP_CNTL__HUFF_FENCE_MC_SWAP__SHIFT 0x16
+#define UVD_JMI_ENC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L
+#define UVD_JMI_ENC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL
+#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L
+#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L
+#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L
+#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L
+#define UVD_JMI_ENC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L
+#define UVD_JMI_ENC_SWAP_CNTL__PEL_RD_MC_SWAP_MASK 0x0000C000L
+#define UVD_JMI_ENC_SWAP_CNTL__BS_WR_MC_SWAP_MASK 0x00030000L
+#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_RD_MC_SWAP_MASK 0x000C0000L
+#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_WR_MC_SWAP_MASK 0x00300000L
+#define UVD_JMI_ENC_SWAP_CNTL__HUFF_FENCE_MC_SWAP_MASK 0x00C00000L
+//UVD_JMI_CNTL
+#define UVD_JMI_CNTL__SOFT_RESET__SHIFT 0x0
+#define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX__SHIFT 0x8
+#define UVD_JMI_CNTL__SOFT_RESET_MASK 0x00000001L
+#define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX_MASK 0x0003FF00L
+//UVD_JMI_ATOMIC_CNTL
+#define UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en__SHIFT 0x0
+#define UVD_JMI_ATOMIC_CNTL__atomic_max_burst__SHIFT 0x1
+#define UVD_JMI_ATOMIC_CNTL__atomic_wr_drop__SHIFT 0x5
+#define UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en__SHIFT 0x6
+#define UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG__SHIFT 0x7
+#define UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE__SHIFT 0xb
+#define UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en_MASK 0x00000001L
+#define UVD_JMI_ATOMIC_CNTL__atomic_max_burst_MASK 0x0000001EL
+#define UVD_JMI_ATOMIC_CNTL__atomic_wr_drop_MASK 0x00000020L
+#define UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en_MASK 0x00000040L
+#define UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG_MASK 0x00000780L
+#define UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE_MASK 0x00000800L
+//UVD_JMI_ATOMIC_CNTL2
+#define UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap__SHIFT 0x10
+#define UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP__SHIFT 0x18
+#define UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap_MASK 0x00FF0000L
+#define UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP_MASK 0xFF000000L
+//UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW
+#define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH
+#define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW
+#define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH
+#define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//JPEG2_LMI_DROP
+#define JPEG2_LMI_DROP__JPEG2_WR_DROP__SHIFT 0x0
+#define JPEG2_LMI_DROP__JPEG2_RD_DROP__SHIFT 0x1
+#define JPEG2_LMI_DROP__JPEG2_WR_DROP_MASK 0x00000001L
+#define JPEG2_LMI_DROP__JPEG2_RD_DROP_MASK 0x00000002L
+//UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW
+#define UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH
+#define UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_JMI_DEC_SWAP_CNTL2
+#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_RD_MC_SWAP__SHIFT 0x0
+#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_WR_MC_SWAP__SHIFT 0x2
+#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_RD_MC_SWAP_MASK 0x00000003L
+#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_WR_MC_SWAP_MASK 0x0000000CL
+//UVD_JMI_DJPEG_RAS_CNTL
+#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_IH_EN__SHIFT 0x0
+#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_PMI_EN__SHIFT 0x1
+#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_REARM__SHIFT 0x2
+#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_STALL_EN__SHIFT 0x3
+#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_READY__SHIFT 0x4
+#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_IH_EN_MASK 0x00000001L
+#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_PMI_EN_MASK 0x00000002L
+#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_REARM_MASK 0x00000004L
+#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_STALL_EN_MASK 0x00000008L
+#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_READY_MASK 0x00000010L
+
+
+// addressBlock: uvd0_uvd_jpeg_common_dec
+//JPEG_SOFT_RESET_STATUS
+#define JPEG_SOFT_RESET_STATUS__JPEG_DEC_RESET_STATUS__SHIFT 0x0
+#define JPEG_SOFT_RESET_STATUS__JPEG2_DEC_RESET_STATUS__SHIFT 0x1
+#define JPEG_SOFT_RESET_STATUS__DJRBC_RESET_STATUS__SHIFT 0x2
+#define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS__SHIFT 0x3
+#define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS__SHIFT 0x4
+#define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS__SHIFT 0x5
+#define JPEG_SOFT_RESET_STATUS__JPEG_DEC_RESET_STATUS_MASK 0x00000001L
+#define JPEG_SOFT_RESET_STATUS__JPEG2_DEC_RESET_STATUS_MASK 0x00000002L
+#define JPEG_SOFT_RESET_STATUS__DJRBC_RESET_STATUS_MASK 0x00000004L
+#define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS_MASK 0x00000008L
+#define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS_MASK 0x00000010L
+#define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS_MASK 0x00000020L
+//JPEG_SYS_INT_EN
+#define JPEG_SYS_INT_EN__DJPEG_CORE__SHIFT 0x0
+#define JPEG_SYS_INT_EN__DJRBC__SHIFT 0x1
+#define JPEG_SYS_INT_EN__DJPEG_PF_RPT__SHIFT 0x2
+#define JPEG_SYS_INT_EN__EJPEG_PF_RPT__SHIFT 0x3
+#define JPEG_SYS_INT_EN__EJPEG_CORE__SHIFT 0x4
+#define JPEG_SYS_INT_EN__EJRBC__SHIFT 0x5
+#define JPEG_SYS_INT_EN__DJPEG_CORE2__SHIFT 0x6
+#define JPEG_SYS_INT_EN__DJPEG_RAS_CNTL__SHIFT 0x7
+#define JPEG_SYS_INT_EN__EJPEG_RAS_CNTL__SHIFT 0x8
+#define JPEG_SYS_INT_EN__DJPEG_CORE_MASK 0x00000001L
+#define JPEG_SYS_INT_EN__DJRBC_MASK 0x00000002L
+#define JPEG_SYS_INT_EN__DJPEG_PF_RPT_MASK 0x00000004L
+#define JPEG_SYS_INT_EN__EJPEG_PF_RPT_MASK 0x00000008L
+#define JPEG_SYS_INT_EN__EJPEG_CORE_MASK 0x00000010L
+#define JPEG_SYS_INT_EN__EJRBC_MASK 0x00000020L
+#define JPEG_SYS_INT_EN__DJPEG_CORE2_MASK 0x00000040L
+#define JPEG_SYS_INT_EN__DJPEG_RAS_CNTL_MASK 0x00000080L
+#define JPEG_SYS_INT_EN__EJPEG_RAS_CNTL_MASK 0x00000100L
+//JPEG_SYS_INT_STATUS
+#define JPEG_SYS_INT_STATUS__DJPEG_CORE__SHIFT 0x0
+#define JPEG_SYS_INT_STATUS__DJRBC__SHIFT 0x1
+#define JPEG_SYS_INT_STATUS__DJPEG_PF_RPT__SHIFT 0x2
+#define JPEG_SYS_INT_STATUS__EJPEG_PF_RPT__SHIFT 0x3
+#define JPEG_SYS_INT_STATUS__EJPEG_CORE__SHIFT 0x4
+#define JPEG_SYS_INT_STATUS__EJRBC__SHIFT 0x5
+#define JPEG_SYS_INT_STATUS__DJPEG_CORE2__SHIFT 0x6
+#define JPEG_SYS_INT_STATUS__DJPEG_RAS_CNTL__SHIFT 0x7
+#define JPEG_SYS_INT_STATUS__EJPEG_RAS_CNTL__SHIFT 0x8
+#define JPEG_SYS_INT_STATUS__DJPEG_CORE_MASK 0x00000001L
+#define JPEG_SYS_INT_STATUS__DJRBC_MASK 0x00000002L
+#define JPEG_SYS_INT_STATUS__DJPEG_PF_RPT_MASK 0x00000004L
+#define JPEG_SYS_INT_STATUS__EJPEG_PF_RPT_MASK 0x00000008L
+#define JPEG_SYS_INT_STATUS__EJPEG_CORE_MASK 0x00000010L
+#define JPEG_SYS_INT_STATUS__EJRBC_MASK 0x00000020L
+#define JPEG_SYS_INT_STATUS__DJPEG_CORE2_MASK 0x00000040L
+#define JPEG_SYS_INT_STATUS__DJPEG_RAS_CNTL_MASK 0x00000080L
+#define JPEG_SYS_INT_STATUS__EJPEG_RAS_CNTL_MASK 0x00000100L
+//JPEG_SYS_INT_ACK
+#define JPEG_SYS_INT_ACK__DJPEG_CORE__SHIFT 0x0
+#define JPEG_SYS_INT_ACK__DJRBC__SHIFT 0x1
+#define JPEG_SYS_INT_ACK__DJPEG_PF_RPT__SHIFT 0x2
+#define JPEG_SYS_INT_ACK__EJPEG_PF_RPT__SHIFT 0x3
+#define JPEG_SYS_INT_ACK__EJPEG_CORE__SHIFT 0x4
+#define JPEG_SYS_INT_ACK__EJRBC__SHIFT 0x5
+#define JPEG_SYS_INT_ACK__DJPEG_CORE2__SHIFT 0x6
+#define JPEG_SYS_INT_ACK__DJPEG_RAS_CNTL__SHIFT 0x7
+#define JPEG_SYS_INT_ACK__EJPEG_RAS_CNTL__SHIFT 0x8
+#define JPEG_SYS_INT_ACK__DJPEG_CORE_MASK 0x00000001L
+#define JPEG_SYS_INT_ACK__DJRBC_MASK 0x00000002L
+#define JPEG_SYS_INT_ACK__DJPEG_PF_RPT_MASK 0x00000004L
+#define JPEG_SYS_INT_ACK__EJPEG_PF_RPT_MASK 0x00000008L
+#define JPEG_SYS_INT_ACK__EJPEG_CORE_MASK 0x00000010L
+#define JPEG_SYS_INT_ACK__EJRBC_MASK 0x00000020L
+#define JPEG_SYS_INT_ACK__DJPEG_CORE2_MASK 0x00000040L
+#define JPEG_SYS_INT_ACK__DJPEG_RAS_CNTL_MASK 0x00000080L
+#define JPEG_SYS_INT_ACK__EJPEG_RAS_CNTL_MASK 0x00000100L
+//JPEG_MEMCHECK_SYS_INT_EN
+#define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_RD_ERR_EN__SHIFT 0x0
+#define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_RD_ERR_EN__SHIFT 0x1
+#define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH_RD_ERR_EN__SHIFT 0x2
+#define JPEG_MEMCHECK_SYS_INT_EN__PELFETCH_RD_ERR_EN__SHIFT 0x3
+#define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_RD_ERR_EN__SHIFT 0x4
+#define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_RD_ERR_EN__SHIFT 0x5
+#define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_WR_ERR_EN__SHIFT 0x6
+#define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_WR_ERR_EN__SHIFT 0x7
+#define JPEG_MEMCHECK_SYS_INT_EN__BS_WR_ERR_EN__SHIFT 0x8
+#define JPEG_MEMCHECK_SYS_INT_EN__OBUF_WR_ERR_EN__SHIFT 0x9
+#define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_WR_ERR_EN__SHIFT 0xa
+#define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_WR_ERR_EN__SHIFT 0xb
+#define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_RD_ERR_EN_MASK 0x00000001L
+#define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_RD_ERR_EN_MASK 0x00000002L
+#define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH_RD_ERR_EN_MASK 0x00000004L
+#define JPEG_MEMCHECK_SYS_INT_EN__PELFETCH_RD_ERR_EN_MASK 0x00000008L
+#define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_RD_ERR_EN_MASK 0x00000010L
+#define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_RD_ERR_EN_MASK 0x00000020L
+#define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_WR_ERR_EN_MASK 0x00000040L
+#define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_WR_ERR_EN_MASK 0x00000080L
+#define JPEG_MEMCHECK_SYS_INT_EN__BS_WR_ERR_EN_MASK 0x00000100L
+#define JPEG_MEMCHECK_SYS_INT_EN__OBUF_WR_ERR_EN_MASK 0x00000200L
+#define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_WR_ERR_EN_MASK 0x00000400L
+#define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_WR_ERR_EN_MASK 0x00000800L
+//JPEG_MEMCHECK_SYS_INT_STAT
+#define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_HI_ERR__SHIFT 0x0
+#define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_LO_ERR__SHIFT 0x1
+#define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_HI_ERR__SHIFT 0x2
+#define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_LO_ERR__SHIFT 0x3
+#define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_HI_ERR__SHIFT 0x4
+#define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_LO_ERR__SHIFT 0x5
+#define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_HI_ERR__SHIFT 0x6
+#define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_LO_ERR__SHIFT 0x7
+#define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_HI_ERR__SHIFT 0x8
+#define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_LO_ERR__SHIFT 0x9
+#define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_HI_ERR__SHIFT 0xa
+#define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_LO_ERR__SHIFT 0xb
+#define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_HI_ERR__SHIFT 0xc
+#define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_LO_ERR__SHIFT 0xd
+#define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_HI_ERR__SHIFT 0xe
+#define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_LO_ERR__SHIFT 0xf
+#define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_HI_ERR__SHIFT 0x10
+#define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_LO_ERR__SHIFT 0x11
+#define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_HI_ERR__SHIFT 0x12
+#define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_LO_ERR__SHIFT 0x13
+#define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_HI_ERR__SHIFT 0x14
+#define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_LO_ERR__SHIFT 0x15
+#define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_HI_ERR__SHIFT 0x16
+#define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_LO_ERR__SHIFT 0x17
+#define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_HI_ERR_MASK 0x00000001L
+#define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_LO_ERR_MASK 0x00000002L
+#define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_HI_ERR_MASK 0x00000004L
+#define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_LO_ERR_MASK 0x00000008L
+#define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_HI_ERR_MASK 0x00000010L
+#define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_LO_ERR_MASK 0x00000020L
+#define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_HI_ERR_MASK 0x00000040L
+#define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_LO_ERR_MASK 0x00000080L
+#define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_HI_ERR_MASK 0x00000100L
+#define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_LO_ERR_MASK 0x00000200L
+#define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_HI_ERR_MASK 0x00000400L
+#define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_LO_ERR_MASK 0x00000800L
+#define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_HI_ERR_MASK 0x00001000L
+#define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_LO_ERR_MASK 0x00002000L
+#define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_HI_ERR_MASK 0x00004000L
+#define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_LO_ERR_MASK 0x00008000L
+#define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_HI_ERR_MASK 0x00010000L
+#define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_LO_ERR_MASK 0x00020000L
+#define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_HI_ERR_MASK 0x00040000L
+#define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_LO_ERR_MASK 0x00080000L
+#define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_HI_ERR_MASK 0x00100000L
+#define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_LO_ERR_MASK 0x00200000L
+#define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_HI_ERR_MASK 0x00400000L
+#define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_LO_ERR_MASK 0x00800000L
+//JPEG_MEMCHECK_SYS_INT_ACK
+#define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_HI_ERR__SHIFT 0x0
+#define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_LO_ERR__SHIFT 0x1
+#define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_HI_ERR__SHIFT 0x2
+#define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_LO_ERR__SHIFT 0x3
+#define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_HI_ERR__SHIFT 0x4
+#define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_LO_ERR__SHIFT 0x5
+#define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_HI_ERR__SHIFT 0x6
+#define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_LO_ERR__SHIFT 0x7
+#define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_HI_ERR__SHIFT 0x8
+#define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_LO_ERR__SHIFT 0x9
+#define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_HI_ERR__SHIFT 0xa
+#define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_LO_ERR__SHIFT 0xb
+#define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_HI_ERR__SHIFT 0xc
+#define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_LO_ERR__SHIFT 0xd
+#define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_HI_ERR__SHIFT 0xe
+#define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_LO_ERR__SHIFT 0xf
+#define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_HI_ERR__SHIFT 0x10
+#define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_LO_ERR__SHIFT 0x11
+#define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_HI_ERR__SHIFT 0x12
+#define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_LO_ERR__SHIFT 0x13
+#define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_HI_ERR__SHIFT 0x14
+#define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_LO_ERR__SHIFT 0x15
+#define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_HI_ERR__SHIFT 0x16
+#define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_LO_ERR__SHIFT 0x17
+#define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_HI_ERR_MASK 0x00000001L
+#define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_LO_ERR_MASK 0x00000002L
+#define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_HI_ERR_MASK 0x00000004L
+#define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_LO_ERR_MASK 0x00000008L
+#define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_HI_ERR_MASK 0x00000010L
+#define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_LO_ERR_MASK 0x00000020L
+#define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_HI_ERR_MASK 0x00000040L
+#define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_LO_ERR_MASK 0x00000080L
+#define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_HI_ERR_MASK 0x00000100L
+#define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_LO_ERR_MASK 0x00000200L
+#define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_HI_ERR_MASK 0x00000400L
+#define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_LO_ERR_MASK 0x00000800L
+#define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_HI_ERR_MASK 0x00001000L
+#define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_LO_ERR_MASK 0x00002000L
+#define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_HI_ERR_MASK 0x00004000L
+#define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_LO_ERR_MASK 0x00008000L
+#define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_HI_ERR_MASK 0x00010000L
+#define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_LO_ERR_MASK 0x00020000L
+#define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_HI_ERR_MASK 0x00040000L
+#define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_LO_ERR_MASK 0x00080000L
+#define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_HI_ERR_MASK 0x00100000L
+#define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_LO_ERR_MASK 0x00200000L
+#define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_HI_ERR_MASK 0x00400000L
+#define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_LO_ERR_MASK 0x00800000L
+//JPEG_MASTINT_EN
+#define JPEG_MASTINT_EN__OVERRUN_RST__SHIFT 0x0
+#define JPEG_MASTINT_EN__INT_OVERRUN__SHIFT 0x4
+#define JPEG_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L
+#define JPEG_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L
+//JPEG_IH_CTRL
+#define JPEG_IH_CTRL__IH_SOFT_RESET__SHIFT 0x0
+#define JPEG_IH_CTRL__IH_STALL_EN__SHIFT 0x1
+#define JPEG_IH_CTRL__IH_STATUS_CLEAN__SHIFT 0x2
+#define JPEG_IH_CTRL__IH_VMID__SHIFT 0x3
+#define JPEG_IH_CTRL__IH_USER_DATA__SHIFT 0x7
+#define JPEG_IH_CTRL__IH_RINGID__SHIFT 0x13
+#define JPEG_IH_CTRL__IH_SOFT_RESET_MASK 0x00000001L
+#define JPEG_IH_CTRL__IH_STALL_EN_MASK 0x00000002L
+#define JPEG_IH_CTRL__IH_STATUS_CLEAN_MASK 0x00000004L
+#define JPEG_IH_CTRL__IH_VMID_MASK 0x00000078L
+#define JPEG_IH_CTRL__IH_USER_DATA_MASK 0x0007FF80L
+#define JPEG_IH_CTRL__IH_RINGID_MASK 0x07F80000L
+//JRBBM_ARB_CTRL
+#define JRBBM_ARB_CTRL__DJRBC_DROP__SHIFT 0x0
+#define JRBBM_ARB_CTRL__EJRBC_DROP__SHIFT 0x1
+#define JRBBM_ARB_CTRL__SRBM_DROP__SHIFT 0x2
+#define JRBBM_ARB_CTRL__DJRBC_DROP_MASK 0x00000001L
+#define JRBBM_ARB_CTRL__EJRBC_DROP_MASK 0x00000002L
+#define JRBBM_ARB_CTRL__SRBM_DROP_MASK 0x00000004L
+
+
+// addressBlock: uvd0_uvd_jpeg_common_sclk_dec
+//JPEG_CGC_GATE
+#define JPEG_CGC_GATE__JPEG_DEC__SHIFT 0x0
+#define JPEG_CGC_GATE__JPEG2_DEC__SHIFT 0x1
+#define JPEG_CGC_GATE__JPEG_ENC__SHIFT 0x2
+#define JPEG_CGC_GATE__JMCIF__SHIFT 0x3
+#define JPEG_CGC_GATE__JRBBM__SHIFT 0x4
+#define JPEG_CGC_GATE__JPEG_DEC_MASK 0x00000001L
+#define JPEG_CGC_GATE__JPEG2_DEC_MASK 0x00000002L
+#define JPEG_CGC_GATE__JPEG_ENC_MASK 0x00000004L
+#define JPEG_CGC_GATE__JMCIF_MASK 0x00000008L
+#define JPEG_CGC_GATE__JRBBM_MASK 0x00000010L
+//JPEG_CGC_CTRL
+#define JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0
+#define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x1
+#define JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x5
+#define JPEG_CGC_CTRL__DYN_OCLK_RAMP_EN__SHIFT 0xa
+#define JPEG_CGC_CTRL__DYN_RCLK_RAMP_EN__SHIFT 0xb
+#define JPEG_CGC_CTRL__GATER_DIV_ID__SHIFT 0xc
+#define JPEG_CGC_CTRL__JPEG_DEC_MODE__SHIFT 0x10
+#define JPEG_CGC_CTRL__JPEG2_DEC_MODE__SHIFT 0x11
+#define JPEG_CGC_CTRL__JPEG_ENC_MODE__SHIFT 0x12
+#define JPEG_CGC_CTRL__JMCIF_MODE__SHIFT 0x13
+#define JPEG_CGC_CTRL__JRBBM_MODE__SHIFT 0x14
+#define JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L
+#define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000001EL
+#define JPEG_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000003E0L
+#define JPEG_CGC_CTRL__DYN_OCLK_RAMP_EN_MASK 0x00000400L
+#define JPEG_CGC_CTRL__DYN_RCLK_RAMP_EN_MASK 0x00000800L
+#define JPEG_CGC_CTRL__GATER_DIV_ID_MASK 0x00007000L
+#define JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK 0x00010000L
+#define JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK 0x00020000L
+#define JPEG_CGC_CTRL__JPEG_ENC_MODE_MASK 0x00040000L
+#define JPEG_CGC_CTRL__JMCIF_MODE_MASK 0x00080000L
+#define JPEG_CGC_CTRL__JRBBM_MODE_MASK 0x00100000L
+//JPEG_CGC_STATUS
+#define JPEG_CGC_STATUS__JPEG_DEC_VCLK_ACTIVE__SHIFT 0x0
+#define JPEG_CGC_STATUS__JPEG_DEC_SCLK_ACTIVE__SHIFT 0x1
+#define JPEG_CGC_STATUS__JPEG2_DEC_VCLK_ACTIVE__SHIFT 0x2
+#define JPEG_CGC_STATUS__JPEG2_DEC_SCLK_ACTIVE__SHIFT 0x3
+#define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE__SHIFT 0x4
+#define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE__SHIFT 0x5
+#define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE__SHIFT 0x6
+#define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE__SHIFT 0x7
+#define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE__SHIFT 0x8
+#define JPEG_CGC_STATUS__JPEG_DEC_VCLK_ACTIVE_MASK 0x00000001L
+#define JPEG_CGC_STATUS__JPEG_DEC_SCLK_ACTIVE_MASK 0x00000002L
+#define JPEG_CGC_STATUS__JPEG2_DEC_VCLK_ACTIVE_MASK 0x00000004L
+#define JPEG_CGC_STATUS__JPEG2_DEC_SCLK_ACTIVE_MASK 0x00000008L
+#define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE_MASK 0x00000010L
+#define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE_MASK 0x00000020L
+#define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE_MASK 0x00000040L
+#define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE_MASK 0x00000080L
+#define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE_MASK 0x00000100L
+//JPEG_COMN_CGC_MEM_CTRL
+#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN__SHIFT 0x0
+#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN__SHIFT 0x1
+#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN__SHIFT 0x2
+#define JPEG_COMN_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10
+#define JPEG_COMN_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14
+#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN_MASK 0x00000001L
+#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN_MASK 0x00000002L
+#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN_MASK 0x00000004L
+#define JPEG_COMN_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0x000F0000L
+#define JPEG_COMN_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0x00F00000L
+//JPEG_DEC_CGC_MEM_CTRL
+#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_EN__SHIFT 0x0
+#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_DS_EN__SHIFT 0x1
+#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_SD_EN__SHIFT 0x2
+#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_EN_MASK 0x00000001L
+#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_DS_EN_MASK 0x00000002L
+#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_SD_EN_MASK 0x00000004L
+//JPEG2_DEC_CGC_MEM_CTRL
+#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_EN__SHIFT 0x0
+#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_DS_EN__SHIFT 0x1
+#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_SD_EN__SHIFT 0x2
+#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_EN_MASK 0x00000001L
+#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_DS_EN_MASK 0x00000002L
+#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_SD_EN_MASK 0x00000004L
+//JPEG_ENC_CGC_MEM_CTRL
+#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN__SHIFT 0x0
+#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN__SHIFT 0x1
+#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN__SHIFT 0x2
+#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN_MASK 0x00000001L
+#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN_MASK 0x00000002L
+#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN_MASK 0x00000004L
+//JPEG_SOFT_RESET2
+#define JPEG_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT 0x0
+#define JPEG_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK 0x00000001L
+//JPEG_PERF_BANK_CONF
+#define JPEG_PERF_BANK_CONF__RESET__SHIFT 0x0
+#define JPEG_PERF_BANK_CONF__PEEK__SHIFT 0x8
+#define JPEG_PERF_BANK_CONF__CONCATENATE__SHIFT 0x10
+#define JPEG_PERF_BANK_CONF__RESET_MASK 0x0000000FL
+#define JPEG_PERF_BANK_CONF__PEEK_MASK 0x00000F00L
+#define JPEG_PERF_BANK_CONF__CONCATENATE_MASK 0x00030000L
+//JPEG_PERF_BANK_EVENT_SEL
+#define JPEG_PERF_BANK_EVENT_SEL__SEL0__SHIFT 0x0
+#define JPEG_PERF_BANK_EVENT_SEL__SEL1__SHIFT 0x8
+#define JPEG_PERF_BANK_EVENT_SEL__SEL2__SHIFT 0x10
+#define JPEG_PERF_BANK_EVENT_SEL__SEL3__SHIFT 0x18
+#define JPEG_PERF_BANK_EVENT_SEL__SEL0_MASK 0x000000FFL
+#define JPEG_PERF_BANK_EVENT_SEL__SEL1_MASK 0x0000FF00L
+#define JPEG_PERF_BANK_EVENT_SEL__SEL2_MASK 0x00FF0000L
+#define JPEG_PERF_BANK_EVENT_SEL__SEL3_MASK 0xFF000000L
+//JPEG_PERF_BANK_COUNT0
+#define JPEG_PERF_BANK_COUNT0__COUNT__SHIFT 0x0
+#define JPEG_PERF_BANK_COUNT0__COUNT_MASK 0xFFFFFFFFL
+//JPEG_PERF_BANK_COUNT1
+#define JPEG_PERF_BANK_COUNT1__COUNT__SHIFT 0x0
+#define JPEG_PERF_BANK_COUNT1__COUNT_MASK 0xFFFFFFFFL
+//JPEG_PERF_BANK_COUNT2
+#define JPEG_PERF_BANK_COUNT2__COUNT__SHIFT 0x0
+#define JPEG_PERF_BANK_COUNT2__COUNT_MASK 0xFFFFFFFFL
+//JPEG_PERF_BANK_COUNT3
+#define JPEG_PERF_BANK_COUNT3__COUNT__SHIFT 0x0
+#define JPEG_PERF_BANK_COUNT3__COUNT_MASK 0xFFFFFFFFL
+
+
+// addressBlock: uvd0_uvd_jpeg_enc_dec
+//UVD_JPEG_ENC_INT_EN
+#define UVD_JPEG_ENC_INT_EN__HUFF_JOB_DONE_INT_EN__SHIFT 0x0
+#define UVD_JPEG_ENC_INT_EN__SCLR_JOB_DONE_INT_EN__SHIFT 0x1
+#define UVD_JPEG_ENC_INT_EN__HUFF_ERROR_INT_EN__SHIFT 0x2
+#define UVD_JPEG_ENC_INT_EN__SCLR_ERROR_INT_EN__SHIFT 0x3
+#define UVD_JPEG_ENC_INT_EN__QTBL_ERROR_INT_EN__SHIFT 0x4
+#define UVD_JPEG_ENC_INT_EN__PIC_SIZE_ERROR_INT_EN__SHIFT 0x5
+#define UVD_JPEG_ENC_INT_EN__FENCE_VAL_INT_EN__SHIFT 0x6
+#define UVD_JPEG_ENC_INT_EN__HUFF_JOB_DONE_INT_EN_MASK 0x00000001L
+#define UVD_JPEG_ENC_INT_EN__SCLR_JOB_DONE_INT_EN_MASK 0x00000002L
+#define UVD_JPEG_ENC_INT_EN__HUFF_ERROR_INT_EN_MASK 0x00000004L
+#define UVD_JPEG_ENC_INT_EN__SCLR_ERROR_INT_EN_MASK 0x00000008L
+#define UVD_JPEG_ENC_INT_EN__QTBL_ERROR_INT_EN_MASK 0x00000010L
+#define UVD_JPEG_ENC_INT_EN__PIC_SIZE_ERROR_INT_EN_MASK 0x00000020L
+#define UVD_JPEG_ENC_INT_EN__FENCE_VAL_INT_EN_MASK 0x00000040L
+//UVD_JPEG_ENC_INT_STATUS
+#define UVD_JPEG_ENC_INT_STATUS__HUFF_JOB_DONE_STATUS__SHIFT 0x0
+#define UVD_JPEG_ENC_INT_STATUS__SCLR_JOB_DONE_STATUS__SHIFT 0x1
+#define UVD_JPEG_ENC_INT_STATUS__HUFF_ERROR_STATUS__SHIFT 0x2
+#define UVD_JPEG_ENC_INT_STATUS__SCLR_ERROR_STATUS__SHIFT 0x3
+#define UVD_JPEG_ENC_INT_STATUS__QTBL_ERROR_STATUS__SHIFT 0x4
+#define UVD_JPEG_ENC_INT_STATUS__PIC_SIZE_ERROR_STATUS__SHIFT 0x5
+#define UVD_JPEG_ENC_INT_STATUS__FENCE_VAL_STATUS__SHIFT 0x6
+#define UVD_JPEG_ENC_INT_STATUS__HUFF_JOB_DONE_STATUS_MASK 0x00000001L
+#define UVD_JPEG_ENC_INT_STATUS__SCLR_JOB_DONE_STATUS_MASK 0x00000002L
+#define UVD_JPEG_ENC_INT_STATUS__HUFF_ERROR_STATUS_MASK 0x00000004L
+#define UVD_JPEG_ENC_INT_STATUS__SCLR_ERROR_STATUS_MASK 0x00000008L
+#define UVD_JPEG_ENC_INT_STATUS__QTBL_ERROR_STATUS_MASK 0x00000010L
+#define UVD_JPEG_ENC_INT_STATUS__PIC_SIZE_ERROR_STATUS_MASK 0x00000020L
+#define UVD_JPEG_ENC_INT_STATUS__FENCE_VAL_STATUS_MASK 0x00000040L
+//UVD_JPEG_ENC_ENGINE_CNTL
+#define UVD_JPEG_ENC_ENGINE_CNTL__HUFF_WR_COMB_DIS__SHIFT 0x0
+#define UVD_JPEG_ENC_ENGINE_CNTL__DISTINCT_CHROMA_QUANT_TABLES__SHIFT 0x1
+#define UVD_JPEG_ENC_ENGINE_CNTL__SCALAR_EN__SHIFT 0x2
+#define UVD_JPEG_ENC_ENGINE_CNTL__ENCODE_EN__SHIFT 0x3
+#define UVD_JPEG_ENC_ENGINE_CNTL__CMP_NEEDED__SHIFT 0x4
+#define UVD_JPEG_ENC_ENGINE_CNTL__ECS_RESTRICT_32B_EN__SHIFT 0x9
+#define UVD_JPEG_ENC_ENGINE_CNTL__HUFF_WR_COMB_DIS_MASK 0x00000001L
+#define UVD_JPEG_ENC_ENGINE_CNTL__DISTINCT_CHROMA_QUANT_TABLES_MASK 0x00000002L
+#define UVD_JPEG_ENC_ENGINE_CNTL__SCALAR_EN_MASK 0x00000004L
+#define UVD_JPEG_ENC_ENGINE_CNTL__ENCODE_EN_MASK 0x00000008L
+#define UVD_JPEG_ENC_ENGINE_CNTL__CMP_NEEDED_MASK 0x00000010L
+#define UVD_JPEG_ENC_ENGINE_CNTL__ECS_RESTRICT_32B_EN_MASK 0x00000200L
+//UVD_JPEG_ENC_SCRATCH1
+#define UVD_JPEG_ENC_SCRATCH1__SCRATCH1__SHIFT 0x0
+#define UVD_JPEG_ENC_SCRATCH1__SCRATCH1_MASK 0xFFFFFFFFL
+
+
+// addressBlock: uvd0_uvd_jpeg_enc_sclk_dec
+//UVD_JPEG_ENC_SPS_INFO
+#define UVD_JPEG_ENC_SPS_INFO__SRC_FORMAT__SHIFT 0x0
+#define UVD_JPEG_ENC_SPS_INFO__YUY2_SUBFORMAT__SHIFT 0x3
+#define UVD_JPEG_ENC_SPS_INFO__OUT_FMT_422__SHIFT 0x4
+#define UVD_JPEG_ENC_SPS_INFO__SRC_FORMAT_MASK 0x00000007L
+#define UVD_JPEG_ENC_SPS_INFO__YUY2_SUBFORMAT_MASK 0x00000008L
+#define UVD_JPEG_ENC_SPS_INFO__OUT_FMT_422_MASK 0x00000010L
+//UVD_JPEG_ENC_SPS_INFO1
+#define UVD_JPEG_ENC_SPS_INFO1__SRC_WIDTH__SHIFT 0x0
+#define UVD_JPEG_ENC_SPS_INFO1__SRC_HEIGHT__SHIFT 0x10
+#define UVD_JPEG_ENC_SPS_INFO1__SRC_WIDTH_MASK 0x0000FFFFL
+#define UVD_JPEG_ENC_SPS_INFO1__SRC_HEIGHT_MASK 0xFFFF0000L
+//UVD_JPEG_ENC_TBL_SIZE
+#define UVD_JPEG_ENC_TBL_SIZE__TBL_SIZE__SHIFT 0x6
+#define UVD_JPEG_ENC_TBL_SIZE__TBL_SIZE_MASK 0x00000FC0L
+//UVD_JPEG_ENC_TBL_CNTL
+#define UVD_JPEG_ENC_TBL_CNTL__TBL_PEL_SEL__SHIFT 0x0
+#define UVD_JPEG_ENC_TBL_CNTL__TBL_TYPE__SHIFT 0x1
+#define UVD_JPEG_ENC_TBL_CNTL__TBL_SUBTYPE__SHIFT 0x2
+#define UVD_JPEG_ENC_TBL_CNTL__HTBL_CNTLEN__SHIFT 0x4
+#define UVD_JPEG_ENC_TBL_CNTL__TBL_PEL_SEL_MASK 0x00000001L
+#define UVD_JPEG_ENC_TBL_CNTL__TBL_TYPE_MASK 0x00000002L
+#define UVD_JPEG_ENC_TBL_CNTL__TBL_SUBTYPE_MASK 0x0000000CL
+#define UVD_JPEG_ENC_TBL_CNTL__HTBL_CNTLEN_MASK 0x00000010L
+//UVD_JPEG_ENC_MC_REQ_CNTL
+#define UVD_JPEG_ENC_MC_REQ_CNTL__RD_REQ_PRIORITY_MARK__SHIFT 0x0
+#define UVD_JPEG_ENC_MC_REQ_CNTL__RD_REQ_PRIORITY_MARK_MASK 0x0000003FL
+//UVD_JPEG_ENC_STATUS
+#define UVD_JPEG_ENC_STATUS__PEL_FETCH_IDLE__SHIFT 0x0
+#define UVD_JPEG_ENC_STATUS__HUFF_CORE_IDLE__SHIFT 0x1
+#define UVD_JPEG_ENC_STATUS__FDCT_IDLE__SHIFT 0x2
+#define UVD_JPEG_ENC_STATUS__SCALAR_IDLE__SHIFT 0x3
+#define UVD_JPEG_ENC_STATUS__PEL_FETCH_IDLE_MASK 0x00000001L
+#define UVD_JPEG_ENC_STATUS__HUFF_CORE_IDLE_MASK 0x00000002L
+#define UVD_JPEG_ENC_STATUS__FDCT_IDLE_MASK 0x00000004L
+#define UVD_JPEG_ENC_STATUS__SCALAR_IDLE_MASK 0x00000008L
+//UVD_JPEG_ENC_PITCH
+#define UVD_JPEG_ENC_PITCH__PITCH_Y__SHIFT 0x0
+#define UVD_JPEG_ENC_PITCH__PITCH_UV__SHIFT 0x10
+#define UVD_JPEG_ENC_PITCH__PITCH_Y_MASK 0x00000FFFL
+#define UVD_JPEG_ENC_PITCH__PITCH_UV_MASK 0x0FFF0000L
+//UVD_JPEG_ENC_LUMA_BASE
+#define UVD_JPEG_ENC_LUMA_BASE__LUMA_BASE__SHIFT 0x0
+#define UVD_JPEG_ENC_LUMA_BASE__LUMA_BASE_MASK 0xFFFFFFFFL
+//UVD_JPEG_ENC_CHROMAU_BASE
+#define UVD_JPEG_ENC_CHROMAU_BASE__CHROMAU_BASE__SHIFT 0x0
+#define UVD_JPEG_ENC_CHROMAU_BASE__CHROMAU_BASE_MASK 0xFFFFFFFFL
+//UVD_JPEG_ENC_CHROMAV_BASE
+#define UVD_JPEG_ENC_CHROMAV_BASE__CHROMAV_BASE__SHIFT 0x0
+#define UVD_JPEG_ENC_CHROMAV_BASE__CHROMAV_BASE_MASK 0xFFFFFFFFL
+//JPEG_ENC_Y_GFX10_TILING_SURFACE
+#define JPEG_ENC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0
+#define JPEG_ENC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL
+//JPEG_ENC_UV_GFX10_TILING_SURFACE
+#define JPEG_ENC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0
+#define JPEG_ENC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL
+//JPEG_ENC_GFX10_ADDR_CONFIG
+#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define JPEG_ENC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
+#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
+#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
+#define JPEG_ENC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
+#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
+//JPEG_ENC_ADDR_MODE
+#define JPEG_ENC_ADDR_MODE__ADDR_MODE_Y__SHIFT 0x0
+#define JPEG_ENC_ADDR_MODE__ADDR_MODE_UV__SHIFT 0x2
+#define JPEG_ENC_ADDR_MODE__ADDR_LIB_SEL__SHIFT 0xc
+#define JPEG_ENC_ADDR_MODE__ADDR_MODE_Y_MASK 0x00000003L
+#define JPEG_ENC_ADDR_MODE__ADDR_MODE_UV_MASK 0x0000000CL
+#define JPEG_ENC_ADDR_MODE__ADDR_LIB_SEL_MASK 0x00007000L
+//UVD_JPEG_ENC_GPCOM_CMD
+#define UVD_JPEG_ENC_GPCOM_CMD__CMD__SHIFT 0x1
+#define UVD_JPEG_ENC_GPCOM_CMD__CMD_MASK 0x0000000EL
+//UVD_JPEG_ENC_GPCOM_DATA0
+#define UVD_JPEG_ENC_GPCOM_DATA0__DATA0__SHIFT 0x0
+#define UVD_JPEG_ENC_GPCOM_DATA0__DATA0_MASK 0xFFFFFFFFL
+//UVD_JPEG_ENC_GPCOM_DATA1
+#define UVD_JPEG_ENC_GPCOM_DATA1__DATA1__SHIFT 0x0
+#define UVD_JPEG_ENC_GPCOM_DATA1__DATA1_MASK 0xFFFFFFFFL
+//UVD_JPEG_TBL_DAT0
+#define UVD_JPEG_TBL_DAT0__TBL_DAT_31_0__SHIFT 0x0
+#define UVD_JPEG_TBL_DAT0__TBL_DAT_31_0_MASK 0xFFFFFFFFL
+//UVD_JPEG_TBL_DAT1
+#define UVD_JPEG_TBL_DAT1__TBL_DAT_63_32__SHIFT 0x0
+#define UVD_JPEG_TBL_DAT1__TBL_DAT_63_32_MASK 0xFFFFFFFFL
+//UVD_JPEG_TBL_IDX
+#define UVD_JPEG_TBL_IDX__TBL_IDX__SHIFT 0x0
+#define UVD_JPEG_TBL_IDX__TBL_IDX_MASK 0x000000FFL
+//UVD_JPEG_ENC_CGC_CNTL
+#define UVD_JPEG_ENC_CGC_CNTL__CGC_EN__SHIFT 0x0
+#define UVD_JPEG_ENC_CGC_CNTL__CGC_EN_MASK 0x00000001L
+//UVD_JPEG_ENC_SCRATCH0
+#define UVD_JPEG_ENC_SCRATCH0__SCRATCH0__SHIFT 0x0
+#define UVD_JPEG_ENC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL
+//UVD_JPEG_ENC_SOFT_RST
+#define UVD_JPEG_ENC_SOFT_RST__SOFT_RST__SHIFT 0x0
+#define UVD_JPEG_ENC_SOFT_RST__RESET_STATUS__SHIFT 0x10
+#define UVD_JPEG_ENC_SOFT_RST__SOFT_RST_MASK 0x00000001L
+#define UVD_JPEG_ENC_SOFT_RST__RESET_STATUS_MASK 0x00010000L
+
+
+// addressBlock: uvd0_uvd_jrbc_dec
+//UVD_JRBC_RB_WPTR
+#define UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT 0x4
+#define UVD_JRBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L
+//UVD_JRBC_RB_CNTL
+#define UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0
+#define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1
+#define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4
+#define UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L
+#define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L
+#define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L
+//UVD_JRBC_IB_SIZE
+#define UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT 0x4
+#define UVD_JRBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L
+//UVD_JRBC_URGENT_CNTL
+#define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0
+#define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L
+//UVD_JRBC_RB_REF_DATA
+#define UVD_JRBC_RB_REF_DATA__REF_DATA__SHIFT 0x0
+#define UVD_JRBC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL
+//UVD_JRBC_RB_COND_RD_TIMER
+#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0
+#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10
+#define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18
+#define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19
+#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL
+#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L
+#define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L
+#define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L
+//UVD_JRBC_SOFT_RESET
+#define UVD_JRBC_SOFT_RESET__RESET__SHIFT 0x0
+#define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11
+#define UVD_JRBC_SOFT_RESET__RESET_MASK 0x00000001L
+#define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L
+//UVD_JRBC_STATUS
+#define UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT 0x0
+#define UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT 0x1
+#define UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2
+#define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3
+#define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4
+#define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5
+#define UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6
+#define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7
+#define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8
+#define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9
+#define UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa
+#define UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT 0xb
+#define UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT 0xc
+#define UVD_JRBC_STATUS__INT_EN__SHIFT 0x10
+#define UVD_JRBC_STATUS__INT_ACK__SHIFT 0x11
+#define UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L
+#define UVD_JRBC_STATUS__IB_JOB_DONE_MASK 0x00000002L
+#define UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L
+#define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L
+#define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L
+#define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L
+#define UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L
+#define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L
+#define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L
+#define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L
+#define UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L
+#define UVD_JRBC_STATUS__PREEMPT_STATUS_MASK 0x00000800L
+#define UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L
+#define UVD_JRBC_STATUS__INT_EN_MASK 0x00010000L
+#define UVD_JRBC_STATUS__INT_ACK_MASK 0x00020000L
+//UVD_JRBC_RB_RPTR
+#define UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT 0x4
+#define UVD_JRBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L
+//UVD_JRBC_RB_BUF_STATUS
+#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0
+#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10
+#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18
+#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL
+#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L
+#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L
+//UVD_JRBC_IB_BUF_STATUS
+#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0
+#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10
+#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18
+#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL
+#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L
+#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L
+//UVD_JRBC_IB_SIZE_UPDATE
+#define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4
+#define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L
+//UVD_JRBC_IB_COND_RD_TIMER
+#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0
+#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10
+#define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18
+#define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19
+#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL
+#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L
+#define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L
+#define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L
+//UVD_JRBC_IB_REF_DATA
+#define UVD_JRBC_IB_REF_DATA__REF_DATA__SHIFT 0x0
+#define UVD_JRBC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL
+//UVD_JPEG_PREEMPT_CMD
+#define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0
+#define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1
+#define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2
+#define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L
+#define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L
+#define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L
+//UVD_JPEG_PREEMPT_FENCE_DATA0
+#define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0
+#define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL
+//UVD_JPEG_PREEMPT_FENCE_DATA1
+#define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0
+#define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL
+//UVD_JRBC_RB_SIZE
+#define UVD_JRBC_RB_SIZE__RB_SIZE__SHIFT 0x4
+#define UVD_JRBC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L
+//UVD_JRBC_SCRATCH0
+#define UVD_JRBC_SCRATCH0__SCRATCH0__SHIFT 0x0
+#define UVD_JRBC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL
+
+
+// addressBlock: uvd0_uvd_jrbc_enc_dec
+//UVD_JRBC_ENC_RB_WPTR
+#define UVD_JRBC_ENC_RB_WPTR__RB_WPTR__SHIFT 0x4
+#define UVD_JRBC_ENC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L
+//UVD_JRBC_ENC_RB_CNTL
+#define UVD_JRBC_ENC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0
+#define UVD_JRBC_ENC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1
+#define UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4
+#define UVD_JRBC_ENC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L
+#define UVD_JRBC_ENC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L
+#define UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L
+//UVD_JRBC_ENC_IB_SIZE
+#define UVD_JRBC_ENC_IB_SIZE__IB_SIZE__SHIFT 0x4
+#define UVD_JRBC_ENC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L
+//UVD_JRBC_ENC_URGENT_CNTL
+#define UVD_JRBC_ENC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0
+#define UVD_JRBC_ENC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L
+//UVD_JRBC_ENC_RB_REF_DATA
+#define UVD_JRBC_ENC_RB_REF_DATA__REF_DATA__SHIFT 0x0
+#define UVD_JRBC_ENC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL
+//UVD_JRBC_ENC_RB_COND_RD_TIMER
+#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0
+#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10
+#define UVD_JRBC_ENC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18
+#define UVD_JRBC_ENC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19
+#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL
+#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L
+#define UVD_JRBC_ENC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L
+#define UVD_JRBC_ENC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L
+//UVD_JRBC_ENC_SOFT_RESET
+#define UVD_JRBC_ENC_SOFT_RESET__RESET__SHIFT 0x0
+#define UVD_JRBC_ENC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11
+#define UVD_JRBC_ENC_SOFT_RESET__RESET_MASK 0x00000001L
+#define UVD_JRBC_ENC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L
+//UVD_JRBC_ENC_STATUS
+#define UVD_JRBC_ENC_STATUS__RB_JOB_DONE__SHIFT 0x0
+#define UVD_JRBC_ENC_STATUS__IB_JOB_DONE__SHIFT 0x1
+#define UVD_JRBC_ENC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2
+#define UVD_JRBC_ENC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3
+#define UVD_JRBC_ENC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4
+#define UVD_JRBC_ENC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5
+#define UVD_JRBC_ENC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6
+#define UVD_JRBC_ENC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7
+#define UVD_JRBC_ENC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8
+#define UVD_JRBC_ENC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9
+#define UVD_JRBC_ENC_STATUS__RB_TRAP_STATUS__SHIFT 0xa
+#define UVD_JRBC_ENC_STATUS__PREEMPT_STATUS__SHIFT 0xb
+#define UVD_JRBC_ENC_STATUS__IB_TRAP_STATUS__SHIFT 0xc
+#define UVD_JRBC_ENC_STATUS__INT_EN__SHIFT 0x10
+#define UVD_JRBC_ENC_STATUS__INT_ACK__SHIFT 0x11
+#define UVD_JRBC_ENC_STATUS__RB_JOB_DONE_MASK 0x00000001L
+#define UVD_JRBC_ENC_STATUS__IB_JOB_DONE_MASK 0x00000002L
+#define UVD_JRBC_ENC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L
+#define UVD_JRBC_ENC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L
+#define UVD_JRBC_ENC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L
+#define UVD_JRBC_ENC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L
+#define UVD_JRBC_ENC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L
+#define UVD_JRBC_ENC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L
+#define UVD_JRBC_ENC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L
+#define UVD_JRBC_ENC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L
+#define UVD_JRBC_ENC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L
+#define UVD_JRBC_ENC_STATUS__PREEMPT_STATUS_MASK 0x00000800L
+#define UVD_JRBC_ENC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L
+#define UVD_JRBC_ENC_STATUS__INT_EN_MASK 0x00010000L
+#define UVD_JRBC_ENC_STATUS__INT_ACK_MASK 0x00020000L
+//UVD_JRBC_ENC_RB_RPTR
+#define UVD_JRBC_ENC_RB_RPTR__RB_RPTR__SHIFT 0x4
+#define UVD_JRBC_ENC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L
+//UVD_JRBC_ENC_RB_BUF_STATUS
+#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0
+#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10
+#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18
+#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL
+#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L
+#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L
+//UVD_JRBC_ENC_IB_BUF_STATUS
+#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0
+#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10
+#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18
+#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL
+#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L
+#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L
+//UVD_JRBC_ENC_IB_SIZE_UPDATE
+#define UVD_JRBC_ENC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4
+#define UVD_JRBC_ENC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L
+//UVD_JRBC_ENC_IB_COND_RD_TIMER
+#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0
+#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10
+#define UVD_JRBC_ENC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18
+#define UVD_JRBC_ENC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19
+#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL
+#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L
+#define UVD_JRBC_ENC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L
+#define UVD_JRBC_ENC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L
+//UVD_JRBC_ENC_IB_REF_DATA
+#define UVD_JRBC_ENC_IB_REF_DATA__REF_DATA__SHIFT 0x0
+#define UVD_JRBC_ENC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL
+//UVD_JPEG_ENC_PREEMPT_CMD
+#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0
+#define UVD_JPEG_ENC_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1
+#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2
+#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L
+#define UVD_JPEG_ENC_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L
+#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L
+//UVD_JPEG_ENC_PREEMPT_FENCE_DATA0
+#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0
+#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL
+//UVD_JPEG_ENC_PREEMPT_FENCE_DATA1
+#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0
+#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL
+//UVD_JRBC_ENC_RB_SIZE
+#define UVD_JRBC_ENC_RB_SIZE__RB_SIZE__SHIFT 0x4
+#define UVD_JRBC_ENC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L
+//UVD_JRBC_ENC_SCRATCH0
+#define UVD_JRBC_ENC_SCRATCH0__SCRATCH0__SHIFT 0x0
+#define UVD_JRBC_ENC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL
+
+
+// addressBlock: uvd0_uvd_mpcdec
+//UVD_MP_SWAP_CNTL
+#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0
+#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2
+#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4
+#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6
+#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8
+#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa
+#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc
+#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe
+#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10
+#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12
+#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14
+#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16
+#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18
+#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a
+#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c
+#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e
+#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x00000003L
+#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0x0000000CL
+#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x00000030L
+#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0x000000C0L
+#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x00000300L
+#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0x00000C00L
+#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x00003000L
+#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0x0000C000L
+#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x00030000L
+#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0x000C0000L
+#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x00300000L
+#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0x00C00000L
+#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x03000000L
+#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0x0C000000L
+#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000L
+#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xC0000000L
+//UVD_MP_SWAP_CNTL2
+#define UVD_MP_SWAP_CNTL2__MP_REF16_MC_SWAP__SHIFT 0x0
+#define UVD_MP_SWAP_CNTL2__MP_REF16_MC_SWAP_MASK 0x00000003L
+//UVD_MPC_LUMA_SRCH
+#define UVD_MPC_LUMA_SRCH__CNTR__SHIFT 0x0
+#define UVD_MPC_LUMA_SRCH__CNTR_MASK 0xFFFFFFFFL
+//UVD_MPC_LUMA_HIT
+#define UVD_MPC_LUMA_HIT__CNTR__SHIFT 0x0
+#define UVD_MPC_LUMA_HIT__CNTR_MASK 0xFFFFFFFFL
+//UVD_MPC_LUMA_HITPEND
+#define UVD_MPC_LUMA_HITPEND__CNTR__SHIFT 0x0
+#define UVD_MPC_LUMA_HITPEND__CNTR_MASK 0xFFFFFFFFL
+//UVD_MPC_CHROMA_SRCH
+#define UVD_MPC_CHROMA_SRCH__CNTR__SHIFT 0x0
+#define UVD_MPC_CHROMA_SRCH__CNTR_MASK 0xFFFFFFFFL
+//UVD_MPC_CHROMA_HIT
+#define UVD_MPC_CHROMA_HIT__CNTR__SHIFT 0x0
+#define UVD_MPC_CHROMA_HIT__CNTR_MASK 0xFFFFFFFFL
+//UVD_MPC_CHROMA_HITPEND
+#define UVD_MPC_CHROMA_HITPEND__CNTR__SHIFT 0x0
+#define UVD_MPC_CHROMA_HITPEND__CNTR_MASK 0xFFFFFFFFL
+//UVD_MPC_CNTL
+#define UVD_MPC_CNTL__BLK_RST__SHIFT 0x0
+#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3
+#define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6
+#define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10
+#define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12
+#define UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP__SHIFT 0x13
+#define UVD_MPC_CNTL__TEST_MODE_EN__SHIFT 0x14
+#define UVD_MPC_CNTL__BLK_RST_MASK 0x00000001L
+#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L
+#define UVD_MPC_CNTL__PERF_RST_MASK 0x00000040L
+#define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x00030000L
+#define UVD_MPC_CNTL__URGENT_EN_MASK 0x00040000L
+#define UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP_MASK 0x00080000L
+#define UVD_MPC_CNTL__TEST_MODE_EN_MASK 0x00100000L
+//UVD_MPC_PITCH
+#define UVD_MPC_PITCH__LUMA_PITCH__SHIFT 0x0
+#define UVD_MPC_PITCH__LUMA_PITCH_MASK 0x000007FFL
+//UVD_MPC_SET_MUXA0
+#define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0
+#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6
+#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc
+#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12
+#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18
+#define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x0000003FL
+#define UVD_MPC_SET_MUXA0__VARA_1_MASK 0x00000FC0L
+#define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x0003F000L
+#define UVD_MPC_SET_MUXA0__VARA_3_MASK 0x00FC0000L
+#define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3F000000L
+//UVD_MPC_SET_MUXA1
+#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0
+#define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6
+#define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc
+#define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x0000003FL
+#define UVD_MPC_SET_MUXA1__VARA_6_MASK 0x00000FC0L
+#define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x0003F000L
+//UVD_MPC_SET_MUXB0
+#define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0
+#define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6
+#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc
+#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12
+#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18
+#define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x0000003FL
+#define UVD_MPC_SET_MUXB0__VARB_1_MASK 0x00000FC0L
+#define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x0003F000L
+#define UVD_MPC_SET_MUXB0__VARB_3_MASK 0x00FC0000L
+#define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3F000000L
+//UVD_MPC_SET_MUXB1
+#define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0
+#define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6
+#define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc
+#define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x0000003FL
+#define UVD_MPC_SET_MUXB1__VARB_6_MASK 0x00000FC0L
+#define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x0003F000L
+//UVD_MPC_SET_MUX
+#define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0
+#define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3
+#define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6
+#define UVD_MPC_SET_MUX__SET_0_MASK 0x00000007L
+#define UVD_MPC_SET_MUX__SET_1_MASK 0x00000038L
+#define UVD_MPC_SET_MUX__SET_2_MASK 0x000001C0L
+//UVD_MPC_SET_ALU
+#define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0
+#define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4
+#define UVD_MPC_SET_ALU__FUNCT_MASK 0x00000007L
+#define UVD_MPC_SET_ALU__OPERAND_MASK 0x00000FF0L
+//UVD_MPC_PERF0
+#define UVD_MPC_PERF0__MAX_LAT__SHIFT 0x0
+#define UVD_MPC_PERF0__MAX_LAT_MASK 0x000003FFL
+//UVD_MPC_PERF1
+#define UVD_MPC_PERF1__AVE_LAT__SHIFT 0x0
+#define UVD_MPC_PERF1__AVE_LAT_MASK 0x000003FFL
+//UVD_MPC_IND_INDEX
+#define UVD_MPC_IND_INDEX__INDEX__SHIFT 0x0
+#define UVD_MPC_IND_INDEX__INDEX_MASK 0x000001FFL
+//UVD_MPC_IND_DATA
+#define UVD_MPC_IND_DATA__DATA__SHIFT 0x0
+#define UVD_MPC_IND_DATA__DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: uvd0_uvd_pg_dec
+//UVD_PGFSM_CONFIG
+#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 0x0
+#define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 0x2
+#define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 0x4
+#define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 0x6
+#define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 0x8
+#define UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 0xa
+#define UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 0xc
+#define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 0xe
+#define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 0x10
+#define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 0x12
+#define UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT 0x14
+#define UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT 0x16
+#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG_MASK 0x00000003L
+#define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG_MASK 0x0000000CL
+#define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG_MASK 0x00000030L
+#define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG_MASK 0x000000C0L
+#define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG_MASK 0x00000300L
+#define UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG_MASK 0x00000C00L
+#define UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG_MASK 0x00003000L
+#define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG_MASK 0x0000C000L
+#define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG_MASK 0x00030000L
+#define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG_MASK 0x000C0000L
+#define UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG_MASK 0x00300000L
+#define UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG_MASK 0x00C00000L
+//UVD_PGFSM_STATUS
+#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 0x0
+#define UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 0x2
+#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 0x4
+#define UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 0x6
+#define UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 0x8
+#define UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT 0xa
+#define UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT 0xc
+#define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 0xe
+#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 0x10
+#define UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 0x12
+#define UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT 0x14
+#define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT 0x16
+#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS_MASK 0x00000003L
+#define UVD_PGFSM_STATUS__UVDU_PWR_STATUS_MASK 0x0000000CL
+#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK 0x00000030L
+#define UVD_PGFSM_STATUS__UVDC_PWR_STATUS_MASK 0x000000C0L
+#define UVD_PGFSM_STATUS__UVDB_PWR_STATUS_MASK 0x00000300L
+#define UVD_PGFSM_STATUS__UVDIL_PWR_STATUS_MASK 0x00000C00L
+#define UVD_PGFSM_STATUS__UVDIR_PWR_STATUS_MASK 0x00003000L
+#define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS_MASK 0x0000C000L
+#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS_MASK 0x00030000L
+#define UVD_PGFSM_STATUS__UVDE_PWR_STATUS_MASK 0x000C0000L
+#define UVD_PGFSM_STATUS__UVDW_PWR_STATUS_MASK 0x00300000L
+#define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK 0x00C00000L
+//UVD_POWER_STATUS
+#define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0
+#define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2
+#define UVD_POWER_STATUS__UVD_CG_MODE__SHIFT 0x4
+#define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8
+#define UVD_POWER_STATUS__RBC_SNOOP_DIS__SHIFT 0x9
+#define UVD_POWER_STATUS__SW_RB_SNOOP_DIS__SHIFT 0xb
+#define UVD_POWER_STATUS__STALL_DPG_POWER_UP__SHIFT 0x1f
+#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000003L
+#define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L
+#define UVD_POWER_STATUS__UVD_CG_MODE_MASK 0x00000030L
+#define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L
+#define UVD_POWER_STATUS__RBC_SNOOP_DIS_MASK 0x00000200L
+#define UVD_POWER_STATUS__SW_RB_SNOOP_DIS_MASK 0x00000800L
+#define UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK 0x80000000L
+//UVD_PG_IND_INDEX
+#define UVD_PG_IND_INDEX__INDEX__SHIFT 0x0
+#define UVD_PG_IND_INDEX__INDEX_MASK 0x0000003FL
+//UVD_PG_IND_DATA
+#define UVD_PG_IND_DATA__DATA__SHIFT 0x0
+#define UVD_PG_IND_DATA__DATA_MASK 0xFFFFFFFFL
+//CC_UVD_HARVESTING
+#define CC_UVD_HARVESTING__MMSCH_DISABLE__SHIFT 0x0
+#define CC_UVD_HARVESTING__UVD_DISABLE__SHIFT 0x1
+#define CC_UVD_HARVESTING__MMSCH_DISABLE_MASK 0x00000001L
+#define CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L
+//UVD_JPEG_POWER_STATUS
+#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS__SHIFT 0x0
+#define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE__SHIFT 0x4
+#define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS__SHIFT 0x8
+#define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS__SHIFT 0x9
+#define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP__SHIFT 0x1f
+#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK 0x00000001L
+#define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK 0x00000010L
+#define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS_MASK 0x00000100L
+#define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS_MASK 0x00000200L
+#define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP_MASK 0x80000000L
+//UVD_DPG_LMA_CTL
+#define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0
+#define UVD_DPG_LMA_CTL__MASK_EN__SHIFT 0x1
+#define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT 0x2
+#define UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT 0x4
+#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0x10
+#define UVD_DPG_LMA_CTL__READ_WRITE_MASK 0x00000001L
+#define UVD_DPG_LMA_CTL__MASK_EN_MASK 0x00000002L
+#define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT_MASK 0x00000004L
+#define UVD_DPG_LMA_CTL__SRAM_SEL_MASK 0x00000010L
+#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR_MASK 0xFFFF0000L
+//UVD_DPG_LMA_DATA
+#define UVD_DPG_LMA_DATA__LMA_DATA__SHIFT 0x0
+#define UVD_DPG_LMA_DATA__LMA_DATA_MASK 0xFFFFFFFFL
+//UVD_DPG_LMA_MASK
+#define UVD_DPG_LMA_MASK__LMA_MASK__SHIFT 0x0
+#define UVD_DPG_LMA_MASK__LMA_MASK_MASK 0xFFFFFFFFL
+//UVD_DPG_PAUSE
+#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ__SHIFT 0x0
+#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT 0x1
+#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT 0x2
+#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK__SHIFT 0x3
+#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK 0x00000001L
+#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK 0x00000002L
+#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK 0x00000004L
+#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK 0x00000008L
+//UVD_SCRATCH1
+#define UVD_SCRATCH1__SCRATCH1_DATA__SHIFT 0x0
+#define UVD_SCRATCH1__SCRATCH1_DATA_MASK 0xFFFFFFFFL
+//UVD_SCRATCH2
+#define UVD_SCRATCH2__SCRATCH2_DATA__SHIFT 0x0
+#define UVD_SCRATCH2__SCRATCH2_DATA_MASK 0xFFFFFFFFL
+//UVD_SCRATCH3
+#define UVD_SCRATCH3__SCRATCH3_DATA__SHIFT 0x0
+#define UVD_SCRATCH3__SCRATCH3_DATA_MASK 0xFFFFFFFFL
+//UVD_SCRATCH4
+#define UVD_SCRATCH4__SCRATCH4_DATA__SHIFT 0x0
+#define UVD_SCRATCH4__SCRATCH4_DATA_MASK 0xFFFFFFFFL
+//UVD_SCRATCH5
+#define UVD_SCRATCH5__SCRATCH5_DATA__SHIFT 0x0
+#define UVD_SCRATCH5__SCRATCH5_DATA_MASK 0xFFFFFFFFL
+//UVD_SCRATCH6
+#define UVD_SCRATCH6__SCRATCH6_DATA__SHIFT 0x0
+#define UVD_SCRATCH6__SCRATCH6_DATA_MASK 0xFFFFFFFFL
+//UVD_SCRATCH7
+#define UVD_SCRATCH7__SCRATCH7_DATA__SHIFT 0x0
+#define UVD_SCRATCH7__SCRATCH7_DATA_MASK 0xFFFFFFFFL
+//UVD_SCRATCH8
+#define UVD_SCRATCH8__SCRATCH8_DATA__SHIFT 0x0
+#define UVD_SCRATCH8__SCRATCH8_DATA_MASK 0xFFFFFFFFL
+//UVD_SCRATCH9
+#define UVD_SCRATCH9__SCRATCH9_DATA__SHIFT 0x0
+#define UVD_SCRATCH9__SCRATCH9_DATA_MASK 0xFFFFFFFFL
+//UVD_SCRATCH10
+#define UVD_SCRATCH10__SCRATCH10_DATA__SHIFT 0x0
+#define UVD_SCRATCH10__SCRATCH10_DATA_MASK 0xFFFFFFFFL
+//UVD_SCRATCH11
+#define UVD_SCRATCH11__SCRATCH11_DATA__SHIFT 0x0
+#define UVD_SCRATCH11__SCRATCH11_DATA_MASK 0xFFFFFFFFL
+//UVD_SCRATCH12
+#define UVD_SCRATCH12__SCRATCH12_DATA__SHIFT 0x0
+#define UVD_SCRATCH12__SCRATCH12_DATA_MASK 0xFFFFFFFFL
+//UVD_SCRATCH13
+#define UVD_SCRATCH13__SCRATCH13_DATA__SHIFT 0x0
+#define UVD_SCRATCH13__SCRATCH13_DATA_MASK 0xFFFFFFFFL
+//UVD_SCRATCH14
+#define UVD_SCRATCH14__SCRATCH14_DATA__SHIFT 0x0
+#define UVD_SCRATCH14__SCRATCH14_DATA_MASK 0xFFFFFFFFL
+//UVD_FREE_COUNTER_REG
+#define UVD_FREE_COUNTER_REG__FREE_COUNTER__SHIFT 0x0
+#define UVD_FREE_COUNTER_REG__FREE_COUNTER_MASK 0xFFFFFFFFL
+//UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW
+#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH
+#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_DPG_VCPU_CACHE_OFFSET0
+#define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0
+#define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x01FFFFFFL
+//UVD_DPG_LMI_VCPU_CACHE_VMID
+#define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0
+#define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL
+//UVD_PF_STATUS
+#define UVD_PF_STATUS__JPEG_PF_OCCURED__SHIFT 0x0
+#define UVD_PF_STATUS__NJ_PF_OCCURED__SHIFT 0x1
+#define UVD_PF_STATUS__ENCODER0_PF_OCCURED__SHIFT 0x2
+#define UVD_PF_STATUS__ENCODER1_PF_OCCURED__SHIFT 0x3
+#define UVD_PF_STATUS__ENCODER2_PF_OCCURED__SHIFT 0x4
+#define UVD_PF_STATUS__ENCODER3_PF_OCCURED__SHIFT 0x5
+#define UVD_PF_STATUS__ENCODER4_PF_OCCURED__SHIFT 0x6
+#define UVD_PF_STATUS__EJPEG_PF_OCCURED__SHIFT 0x7
+#define UVD_PF_STATUS__JPEG_PF_CLEAR__SHIFT 0x8
+#define UVD_PF_STATUS__NJ_PF_CLEAR__SHIFT 0x9
+#define UVD_PF_STATUS__ENCODER0_PF_CLEAR__SHIFT 0xa
+#define UVD_PF_STATUS__ENCODER1_PF_CLEAR__SHIFT 0xb
+#define UVD_PF_STATUS__ENCODER2_PF_CLEAR__SHIFT 0xc
+#define UVD_PF_STATUS__ENCODER3_PF_CLEAR__SHIFT 0xd
+#define UVD_PF_STATUS__ENCODER4_PF_CLEAR__SHIFT 0xe
+#define UVD_PF_STATUS__EJPEG_PF_CLEAR__SHIFT 0xf
+#define UVD_PF_STATUS__NJ_ATM_PF_OCCURED__SHIFT 0x10
+#define UVD_PF_STATUS__DJ_ATM_PF_OCCURED__SHIFT 0x11
+#define UVD_PF_STATUS__EJ_ATM_PF_OCCURED__SHIFT 0x12
+#define UVD_PF_STATUS__JPEG_PF_OCCURED_MASK 0x00000001L
+#define UVD_PF_STATUS__NJ_PF_OCCURED_MASK 0x00000002L
+#define UVD_PF_STATUS__ENCODER0_PF_OCCURED_MASK 0x00000004L
+#define UVD_PF_STATUS__ENCODER1_PF_OCCURED_MASK 0x00000008L
+#define UVD_PF_STATUS__ENCODER2_PF_OCCURED_MASK 0x00000010L
+#define UVD_PF_STATUS__ENCODER3_PF_OCCURED_MASK 0x00000020L
+#define UVD_PF_STATUS__ENCODER4_PF_OCCURED_MASK 0x00000040L
+#define UVD_PF_STATUS__EJPEG_PF_OCCURED_MASK 0x00000080L
+#define UVD_PF_STATUS__JPEG_PF_CLEAR_MASK 0x00000100L
+#define UVD_PF_STATUS__NJ_PF_CLEAR_MASK 0x00000200L
+#define UVD_PF_STATUS__ENCODER0_PF_CLEAR_MASK 0x00000400L
+#define UVD_PF_STATUS__ENCODER1_PF_CLEAR_MASK 0x00000800L
+#define UVD_PF_STATUS__ENCODER2_PF_CLEAR_MASK 0x00001000L
+#define UVD_PF_STATUS__ENCODER3_PF_CLEAR_MASK 0x00002000L
+#define UVD_PF_STATUS__ENCODER4_PF_CLEAR_MASK 0x00004000L
+#define UVD_PF_STATUS__EJPEG_PF_CLEAR_MASK 0x00008000L
+#define UVD_PF_STATUS__NJ_ATM_PF_OCCURED_MASK 0x00010000L
+#define UVD_PF_STATUS__DJ_ATM_PF_OCCURED_MASK 0x00020000L
+#define UVD_PF_STATUS__EJ_ATM_PF_OCCURED_MASK 0x00040000L
+//UVD_FW_VERSION
+#define UVD_FW_VERSION__FW_VERSION__SHIFT 0x0
+#define UVD_FW_VERSION__FW_VERSION_MASK 0xFFFFFFFFL
+//UVD_DPG_CLK_EN_VCPU_REPORT
+#define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN__SHIFT 0x0
+#define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT__SHIFT 0x1
+#define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN_MASK 0x00000001L
+#define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT_MASK 0x000000FEL
+//UVD_GFX8_ADDR_CONFIG
+#define UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L
+//UVD_GFX10_ADDR_CONFIG
+#define UVD_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define UVD_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
+#define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
+#define UVD_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
+#define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define UVD_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
+#define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
+//UVD_GPCNT2_CNTL
+#define UVD_GPCNT2_CNTL__CLR__SHIFT 0x0
+#define UVD_GPCNT2_CNTL__START__SHIFT 0x1
+#define UVD_GPCNT2_CNTL__COUNTUP__SHIFT 0x2
+#define UVD_GPCNT2_CNTL__CLR_MASK 0x00000001L
+#define UVD_GPCNT2_CNTL__START_MASK 0x00000002L
+#define UVD_GPCNT2_CNTL__COUNTUP_MASK 0x00000004L
+//UVD_GPCNT2_TARGET_LOWER
+#define UVD_GPCNT2_TARGET_LOWER__TARGET__SHIFT 0x0
+#define UVD_GPCNT2_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL
+//UVD_GPCNT2_STATUS_LOWER
+#define UVD_GPCNT2_STATUS_LOWER__COUNT__SHIFT 0x0
+#define UVD_GPCNT2_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL
+//UVD_GPCNT2_TARGET_UPPER
+#define UVD_GPCNT2_TARGET_UPPER__TARGET__SHIFT 0x0
+#define UVD_GPCNT2_TARGET_UPPER__TARGET_MASK 0x0000FFFFL
+//UVD_GPCNT2_STATUS_UPPER
+#define UVD_GPCNT2_STATUS_UPPER__COUNT__SHIFT 0x0
+#define UVD_GPCNT2_STATUS_UPPER__COUNT_MASK 0x0000FFFFL
+//UVD_GPCNT3_CNTL
+#define UVD_GPCNT3_CNTL__CLR__SHIFT 0x0
+#define UVD_GPCNT3_CNTL__START__SHIFT 0x1
+#define UVD_GPCNT3_CNTL__COUNTUP__SHIFT 0x2
+#define UVD_GPCNT3_CNTL__FREQ__SHIFT 0x3
+#define UVD_GPCNT3_CNTL__DIV__SHIFT 0xa
+#define UVD_GPCNT3_CNTL__CLR_MASK 0x00000001L
+#define UVD_GPCNT3_CNTL__START_MASK 0x00000002L
+#define UVD_GPCNT3_CNTL__COUNTUP_MASK 0x00000004L
+#define UVD_GPCNT3_CNTL__FREQ_MASK 0x000003F8L
+#define UVD_GPCNT3_CNTL__DIV_MASK 0x0001FC00L
+//UVD_GPCNT3_TARGET_LOWER
+#define UVD_GPCNT3_TARGET_LOWER__TARGET__SHIFT 0x0
+#define UVD_GPCNT3_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL
+//UVD_GPCNT3_STATUS_LOWER
+#define UVD_GPCNT3_STATUS_LOWER__COUNT__SHIFT 0x0
+#define UVD_GPCNT3_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL
+//UVD_GPCNT3_TARGET_UPPER
+#define UVD_GPCNT3_TARGET_UPPER__TARGET__SHIFT 0x0
+#define UVD_GPCNT3_TARGET_UPPER__TARGET_MASK 0x0000FFFFL
+//UVD_GPCNT3_STATUS_UPPER
+#define UVD_GPCNT3_STATUS_UPPER__COUNT__SHIFT 0x0
+#define UVD_GPCNT3_STATUS_UPPER__COUNT_MASK 0x0000FFFFL
+//UVD_VCLK_DS_CNTL
+#define UVD_VCLK_DS_CNTL__VCLK_DS_EN__SHIFT 0x0
+#define UVD_VCLK_DS_CNTL__VCLK_DS_STATUS__SHIFT 0x4
+#define UVD_VCLK_DS_CNTL__VCLK_DS_HYSTERESIS_CNT__SHIFT 0x10
+#define UVD_VCLK_DS_CNTL__VCLK_DS_EN_MASK 0x00000001L
+#define UVD_VCLK_DS_CNTL__VCLK_DS_STATUS_MASK 0x00000010L
+#define UVD_VCLK_DS_CNTL__VCLK_DS_HYSTERESIS_CNT_MASK 0xFFFF0000L
+//UVD_DCLK_DS_CNTL
+#define UVD_DCLK_DS_CNTL__DCLK_DS_EN__SHIFT 0x0
+#define UVD_DCLK_DS_CNTL__DCLK_DS_STATUS__SHIFT 0x4
+#define UVD_DCLK_DS_CNTL__DCLK_DS_HYSTERESIS_CNT__SHIFT 0x10
+#define UVD_DCLK_DS_CNTL__DCLK_DS_EN_MASK 0x00000001L
+#define UVD_DCLK_DS_CNTL__DCLK_DS_STATUS_MASK 0x00000010L
+#define UVD_DCLK_DS_CNTL__DCLK_DS_HYSTERESIS_CNT_MASK 0xFFFF0000L
+//UVD_RAS_VCPU_VCODEC_STATUS
+#define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_VF__SHIFT 0x0
+#define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_PF__SHIFT 0x1f
+#define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_VF_MASK 0x7FFFFFFFL
+#define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_PF_MASK 0x80000000L
+//UVD_RAS_MMSCH_FATAL_ERROR
+#define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_VF__SHIFT 0x0
+#define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_PF__SHIFT 0x1f
+#define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_VF_MASK 0x7FFFFFFFL
+#define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_PF_MASK 0x80000000L
+//UVD_RAS_JPEG0_STATUS
+#define UVD_RAS_JPEG0_STATUS__POISONED_VF__SHIFT 0x0
+#define UVD_RAS_JPEG0_STATUS__POISONED_PF__SHIFT 0x1f
+#define UVD_RAS_JPEG0_STATUS__POISONED_VF_MASK 0x7FFFFFFFL
+#define UVD_RAS_JPEG0_STATUS__POISONED_PF_MASK 0x80000000L
+//UVD_RAS_JPEG1_STATUS
+#define UVD_RAS_JPEG1_STATUS__POISONED_VF__SHIFT 0x0
+#define UVD_RAS_JPEG1_STATUS__POISONED_PF__SHIFT 0x1f
+#define UVD_RAS_JPEG1_STATUS__POISONED_VF_MASK 0x7FFFFFFFL
+#define UVD_RAS_JPEG1_STATUS__POISONED_PF_MASK 0x80000000L
+//UVD_RAS_CNTL_PMI_ARB
+#define UVD_RAS_CNTL_PMI_ARB__STAT_VCPU_VCODEC__SHIFT 0x0
+#define UVD_RAS_CNTL_PMI_ARB__ACK_VCPU_VCODEC__SHIFT 0x1
+#define UVD_RAS_CNTL_PMI_ARB__STAT_MMSCH__SHIFT 0x2
+#define UVD_RAS_CNTL_PMI_ARB__ACK_MMSCH__SHIFT 0x3
+#define UVD_RAS_CNTL_PMI_ARB__STAT_JPEG0__SHIFT 0x4
+#define UVD_RAS_CNTL_PMI_ARB__ACK_JPEG0__SHIFT 0x5
+#define UVD_RAS_CNTL_PMI_ARB__STAT_JPEG1__SHIFT 0x6
+#define UVD_RAS_CNTL_PMI_ARB__ACK_JPEG1__SHIFT 0x7
+#define UVD_RAS_CNTL_PMI_ARB__STAT_VCPU_VCODEC_MASK 0x00000001L
+#define UVD_RAS_CNTL_PMI_ARB__ACK_VCPU_VCODEC_MASK 0x00000002L
+#define UVD_RAS_CNTL_PMI_ARB__STAT_MMSCH_MASK 0x00000004L
+#define UVD_RAS_CNTL_PMI_ARB__ACK_MMSCH_MASK 0x00000008L
+#define UVD_RAS_CNTL_PMI_ARB__STAT_JPEG0_MASK 0x00000010L
+#define UVD_RAS_CNTL_PMI_ARB__ACK_JPEG0_MASK 0x00000020L
+#define UVD_RAS_CNTL_PMI_ARB__STAT_JPEG1_MASK 0x00000040L
+#define UVD_RAS_CNTL_PMI_ARB__ACK_JPEG1_MASK 0x00000080L
+
+
+// addressBlock: uvd0_uvd_rbcdec
+//UVD_RBC_IB_SIZE
+#define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4
+#define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L
+//UVD_RBC_IB_SIZE_UPDATE
+#define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4
+#define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L
+//UVD_RBC_RB_CNTL
+#define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0
+#define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8
+#define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10
+#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14
+#define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18
+#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c
+#define UVD_RBC_RB_CNTL__BLK_RST__SHIFT 0x1d
+#define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x0000001FL
+#define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x00001F00L
+#define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x00010000L
+#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x00100000L
+#define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x01000000L
+#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000L
+#define UVD_RBC_RB_CNTL__BLK_RST_MASK 0x20000000L
+//UVD_RBC_RB_RPTR_ADDR
+#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0
+#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFFL
+//UVD_RBC_RB_RPTR
+#define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4
+#define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L
+//UVD_RBC_RB_WPTR
+#define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4
+#define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L
+//UVD_RBC_VCPU_ACCESS
+#define UVD_RBC_VCPU_ACCESS__ENABLE_RBC__SHIFT 0x0
+#define UVD_RBC_VCPU_ACCESS__ENABLE_RBC_MASK 0x00000001L
+//UVD_FW_SEMAPHORE_CNTL
+#define UVD_FW_SEMAPHORE_CNTL__START__SHIFT 0x0
+#define UVD_FW_SEMAPHORE_CNTL__BUSY__SHIFT 0x8
+#define UVD_FW_SEMAPHORE_CNTL__PASS__SHIFT 0x9
+#define UVD_FW_SEMAPHORE_CNTL__START_MASK 0x00000001L
+#define UVD_FW_SEMAPHORE_CNTL__BUSY_MASK 0x00000100L
+#define UVD_FW_SEMAPHORE_CNTL__PASS_MASK 0x00000200L
+//UVD_RBC_READ_REQ_URGENT_CNTL
+#define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0
+#define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L
+//UVD_RBC_RB_WPTR_CNTL
+#define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x0
+#define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK 0x00007FFFL
+//UVD_RBC_WPTR_STATUS
+#define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE__SHIFT 0x4
+#define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE_MASK 0x007FFFF0L
+//UVD_RBC_WPTR_POLL_CNTL
+#define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ__SHIFT 0x0
+#define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ_MASK 0x0000FFFFL
+#define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//UVD_RBC_WPTR_POLL_ADDR
+#define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR__SHIFT 0x2
+#define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR_MASK 0xFFFFFFFCL
+//UVD_SEMA_CMD
+#define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
+#define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
+#define UVD_SEMA_CMD__MODE__SHIFT 0x6
+#define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7
+#define UVD_SEMA_CMD__VMID__SHIFT 0x8
+#define UVD_SEMA_CMD__REQ_CMD_MASK 0x0000000FL
+#define UVD_SEMA_CMD__WR_PHASE_MASK 0x00000030L
+#define UVD_SEMA_CMD__MODE_MASK 0x00000040L
+#define UVD_SEMA_CMD__VMID_EN_MASK 0x00000080L
+#define UVD_SEMA_CMD__VMID_MASK 0x00000F00L
+//UVD_SEMA_ADDR_LOW
+#define UVD_SEMA_ADDR_LOW__ADDR_26_3__SHIFT 0x0
+#define UVD_SEMA_ADDR_LOW__ADDR_26_3_MASK 0x00FFFFFFL
+//UVD_SEMA_ADDR_HIGH
+#define UVD_SEMA_ADDR_HIGH__ADDR_47_27__SHIFT 0x0
+#define UVD_SEMA_ADDR_HIGH__ADDR_47_27_MASK 0x001FFFFFL
+//UVD_ENGINE_CNTL
+#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0
+#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1
+#define UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE__SHIFT 0x2
+#define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x00000001L
+#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x00000002L
+#define UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE_MASK 0x00000004L
+//UVD_SEMA_TIMEOUT_STATUS
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000001L
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x00000002L
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000004L
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x00000008L
+//UVD_SEMA_CNTL
+#define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0
+#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1
+#define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x00000001L
+#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x00000002L
+//UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x00000001L
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x001FFFFEL
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L
+//UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x00000001L
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x001FFFFEL
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L
+//UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x00000001L
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x001FFFFEL
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L
+//UVD_JOB_START
+#define UVD_JOB_START__JOB_START__SHIFT 0x0
+#define UVD_JOB_START__JOB_START_MASK 0x00000001L
+//UVD_RBC_BUF_STATUS
+#define UVD_RBC_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0
+#define UVD_RBC_BUF_STATUS__IB_BUF_VALID__SHIFT 0x8
+#define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10
+#define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x13
+#define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x16
+#define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x19
+#define UVD_RBC_BUF_STATUS__RB_BUF_VALID_MASK 0x000000FFL
+#define UVD_RBC_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FF00L
+#define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x00070000L
+#define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x00380000L
+#define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x01C00000L
+#define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x0E000000L
+//UVD_RBC_SWAP_CNTL
+#define UVD_RBC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0
+#define UVD_RBC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2
+#define UVD_RBC_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4
+#define UVD_RBC_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a
+#define UVD_RBC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L
+#define UVD_RBC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL
+#define UVD_RBC_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x00000030L
+#define UVD_RBC_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0x0C000000L
+
+
+// addressBlock: uvd0_uvddec
+//UVD_STATUS
+#define UVD_STATUS__RBC_BUSY__SHIFT 0x0
+#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1
+#define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT 0x10
+#define UVD_STATUS__SYS_GPCOM_REQ__SHIFT 0x1f
+#define UVD_STATUS__RBC_BUSY_MASK 0x00000001L
+#define UVD_STATUS__VCPU_REPORT_MASK 0x000000FEL
+#define UVD_STATUS__RBC_ACCESS_GPCOM_MASK 0x00010000L
+#define UVD_STATUS__SYS_GPCOM_REQ_MASK 0x80000000L
+//UVD_ENC_PIPE_BUSY
+#define UVD_ENC_PIPE_BUSY__IME_BUSY__SHIFT 0x0
+#define UVD_ENC_PIPE_BUSY__SMP_BUSY__SHIFT 0x1
+#define UVD_ENC_PIPE_BUSY__SIT_BUSY__SHIFT 0x2
+#define UVD_ENC_PIPE_BUSY__SDB_BUSY__SHIFT 0x3
+#define UVD_ENC_PIPE_BUSY__ENT_BUSY__SHIFT 0x4
+#define UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY__SHIFT 0x5
+#define UVD_ENC_PIPE_BUSY__LCM_BUSY__SHIFT 0x6
+#define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY__SHIFT 0x7
+#define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY__SHIFT 0x8
+#define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY__SHIFT 0xa
+#define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY__SHIFT 0x10
+#define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY__SHIFT 0x11
+#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY__SHIFT 0x12
+#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY__SHIFT 0x13
+#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY__SHIFT 0x14
+#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY__SHIFT 0x15
+#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY__SHIFT 0x16
+#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY__SHIFT 0x17
+#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY__SHIFT 0x18
+#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY__SHIFT 0x19
+#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY__SHIFT 0x1a
+#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY__SHIFT 0x1b
+#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY__SHIFT 0x1c
+#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY__SHIFT 0x1d
+#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY__SHIFT 0x1e
+#define UVD_ENC_PIPE_BUSY__IME_BUSY_MASK 0x00000001L
+#define UVD_ENC_PIPE_BUSY__SMP_BUSY_MASK 0x00000002L
+#define UVD_ENC_PIPE_BUSY__SIT_BUSY_MASK 0x00000004L
+#define UVD_ENC_PIPE_BUSY__SDB_BUSY_MASK 0x00000008L
+#define UVD_ENC_PIPE_BUSY__ENT_BUSY_MASK 0x00000010L
+#define UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY_MASK 0x00000020L
+#define UVD_ENC_PIPE_BUSY__LCM_BUSY_MASK 0x00000040L
+#define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY_MASK 0x00000080L
+#define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY_MASK 0x00000100L
+#define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY_MASK 0x00000400L
+#define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY_MASK 0x00010000L
+#define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY_MASK 0x00020000L
+#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY_MASK 0x00040000L
+#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY_MASK 0x00080000L
+#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY_MASK 0x00100000L
+#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY_MASK 0x00200000L
+#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY_MASK 0x00400000L
+#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY_MASK 0x00800000L
+#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY_MASK 0x01000000L
+#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY_MASK 0x02000000L
+#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY_MASK 0x04000000L
+#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY_MASK 0x08000000L
+#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY_MASK 0x10000000L
+#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY_MASK 0x20000000L
+#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY_MASK 0x40000000L
+//UVD_FW_POWER_STATUS
+#define UVD_FW_POWER_STATUS__UVDF_PWR_OFF__SHIFT 0x0
+#define UVD_FW_POWER_STATUS__UVDC_PWR_OFF__SHIFT 0x1
+#define UVD_FW_POWER_STATUS__UVDB_PWR_OFF__SHIFT 0x2
+#define UVD_FW_POWER_STATUS__UVDIL_PWR_OFF__SHIFT 0x3
+#define UVD_FW_POWER_STATUS__UVDIR_PWR_OFF__SHIFT 0x4
+#define UVD_FW_POWER_STATUS__UVDTD_PWR_OFF__SHIFT 0x5
+#define UVD_FW_POWER_STATUS__UVDTE_PWR_OFF__SHIFT 0x6
+#define UVD_FW_POWER_STATUS__UVDE_PWR_OFF__SHIFT 0x7
+#define UVD_FW_POWER_STATUS__UVDW_PWR_OFF__SHIFT 0x8
+#define UVD_FW_POWER_STATUS__UVDF_PWR_OFF_MASK 0x00000001L
+#define UVD_FW_POWER_STATUS__UVDC_PWR_OFF_MASK 0x00000002L
+#define UVD_FW_POWER_STATUS__UVDB_PWR_OFF_MASK 0x00000004L
+#define UVD_FW_POWER_STATUS__UVDIL_PWR_OFF_MASK 0x00000008L
+#define UVD_FW_POWER_STATUS__UVDIR_PWR_OFF_MASK 0x00000010L
+#define UVD_FW_POWER_STATUS__UVDTD_PWR_OFF_MASK 0x00000020L
+#define UVD_FW_POWER_STATUS__UVDTE_PWR_OFF_MASK 0x00000040L
+#define UVD_FW_POWER_STATUS__UVDE_PWR_OFF_MASK 0x00000080L
+#define UVD_FW_POWER_STATUS__UVDW_PWR_OFF_MASK 0x00000100L
+//UVD_CNTL
+#define UVD_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT 0x11
+#define UVD_CNTL__SUVD_EN__SHIFT 0x13
+#define UVD_CNTL__CABAC_MB_ACC__SHIFT 0x1c
+#define UVD_CNTL__LRBBM_SAFE_SYNC_DIS__SHIFT 0x1f
+#define UVD_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x00020000L
+#define UVD_CNTL__SUVD_EN_MASK 0x00080000L
+#define UVD_CNTL__CABAC_MB_ACC_MASK 0x10000000L
+#define UVD_CNTL__LRBBM_SAFE_SYNC_DIS_MASK 0x80000000L
+//UVD_SOFT_RESET
+#define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0
+#define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1
+#define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2
+#define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3
+#define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4
+#define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6
+#define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7
+#define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8
+#define UVD_SOFT_RESET__EFC_SOFT_RESET__SHIFT 0x9
+#define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa
+#define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb
+#define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc
+#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd
+#define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe
+#define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf
+#define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10
+#define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11
+#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12
+#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13
+#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14
+#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15
+#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16
+#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS__SHIFT 0x17
+#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS__SHIFT 0x18
+#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS__SHIFT 0x19
+#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a
+#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b
+#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c
+#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d
+#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e
+#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f
+#define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x00000001L
+#define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x00000002L
+#define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x00000004L
+#define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x00000008L
+#define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x00000010L
+#define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x00000040L
+#define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000080L
+#define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x00000100L
+#define UVD_SOFT_RESET__EFC_SOFT_RESET_MASK 0x00000200L
+#define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x00000400L
+#define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x00000800L
+#define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x00001000L
+#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x00002000L
+#define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x00004000L
+#define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x00008000L
+#define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x00010000L
+#define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x00020000L
+#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x00040000L
+#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x00080000L
+#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x00100000L
+#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x00200000L
+#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x00400000L
+#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS_MASK 0x00800000L
+#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS_MASK 0x01000000L
+#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS_MASK 0x02000000L
+#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x04000000L
+#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x08000000L
+#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000L
+#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000L
+#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000L
+#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000L
+//UVD_SOFT_RESET2
+#define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT 0x0
+#define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS__SHIFT 0x10
+#define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS__SHIFT 0x11
+#define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK 0x00000001L
+#define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS_MASK 0x00010000L
+#define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS_MASK 0x00020000L
+//UVD_MMSCH_SOFT_RESET
+#define UVD_MMSCH_SOFT_RESET__MMSCH_RESET__SHIFT 0x0
+#define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x1
+#define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK__SHIFT 0x1f
+#define UVD_MMSCH_SOFT_RESET__MMSCH_RESET_MASK 0x00000001L
+#define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000002L
+#define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK_MASK 0x80000000L
+//UVD_WIG_CTRL
+#define UVD_WIG_CTRL__AVM_SOFT_RESET__SHIFT 0x0
+#define UVD_WIG_CTRL__ACAP_SOFT_RESET__SHIFT 0x1
+#define UVD_WIG_CTRL__WIG_SOFT_RESET__SHIFT 0x2
+#define UVD_WIG_CTRL__WIG_REGCLK_FORCE_ON__SHIFT 0x3
+#define UVD_WIG_CTRL__AVM_REGCLK_FORCE_ON__SHIFT 0x4
+#define UVD_WIG_CTRL__AVM_SOFT_RESET_MASK 0x00000001L
+#define UVD_WIG_CTRL__ACAP_SOFT_RESET_MASK 0x00000002L
+#define UVD_WIG_CTRL__WIG_SOFT_RESET_MASK 0x00000004L
+#define UVD_WIG_CTRL__WIG_REGCLK_FORCE_ON_MASK 0x00000008L
+#define UVD_WIG_CTRL__AVM_REGCLK_FORCE_ON_MASK 0x00000010L
+//UVD_CGC_GATE
+#define UVD_CGC_GATE__SYS__SHIFT 0x0
+#define UVD_CGC_GATE__UDEC__SHIFT 0x1
+#define UVD_CGC_GATE__MPEG2__SHIFT 0x2
+#define UVD_CGC_GATE__REGS__SHIFT 0x3
+#define UVD_CGC_GATE__RBC__SHIFT 0x4
+#define UVD_CGC_GATE__LMI_MC__SHIFT 0x5
+#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6
+#define UVD_CGC_GATE__IDCT__SHIFT 0x7
+#define UVD_CGC_GATE__MPRD__SHIFT 0x8
+#define UVD_CGC_GATE__MPC__SHIFT 0x9
+#define UVD_CGC_GATE__LBSI__SHIFT 0xa
+#define UVD_CGC_GATE__LRBBM__SHIFT 0xb
+#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc
+#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd
+#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe
+#define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf
+#define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10
+#define UVD_CGC_GATE__WCB__SHIFT 0x11
+#define UVD_CGC_GATE__VCPU__SHIFT 0x12
+#define UVD_CGC_GATE__MMSCH__SHIFT 0x14
+#define UVD_CGC_GATE__SYS_MASK 0x00000001L
+#define UVD_CGC_GATE__UDEC_MASK 0x00000002L
+#define UVD_CGC_GATE__MPEG2_MASK 0x00000004L
+#define UVD_CGC_GATE__REGS_MASK 0x00000008L
+#define UVD_CGC_GATE__RBC_MASK 0x00000010L
+#define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L
+#define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L
+#define UVD_CGC_GATE__IDCT_MASK 0x00000080L
+#define UVD_CGC_GATE__MPRD_MASK 0x00000100L
+#define UVD_CGC_GATE__MPC_MASK 0x00000200L
+#define UVD_CGC_GATE__LBSI_MASK 0x00000400L
+#define UVD_CGC_GATE__LRBBM_MASK 0x00000800L
+#define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L
+#define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L
+#define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L
+#define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L
+#define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L
+#define UVD_CGC_GATE__WCB_MASK 0x00020000L
+#define UVD_CGC_GATE__VCPU_MASK 0x00040000L
+#define UVD_CGC_GATE__MMSCH_MASK 0x00100000L
+//UVD_CGC_STATUS
+#define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0
+#define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1
+#define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2
+#define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3
+#define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4
+#define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5
+#define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6
+#define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7
+#define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8
+#define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9
+#define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa
+#define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb
+#define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc
+#define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd
+#define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe
+#define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf
+#define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10
+#define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11
+#define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12
+#define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13
+#define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14
+#define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15
+#define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16
+#define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17
+#define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18
+#define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19
+#define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a
+#define UVD_CGC_STATUS__MMSCH_SCLK__SHIFT 0x1b
+#define UVD_CGC_STATUS__MMSCH_VCLK__SHIFT 0x1c
+#define UVD_CGC_STATUS__ALL_ENC_ACTIVE__SHIFT 0x1d
+#define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT 0x1f
+#define UVD_CGC_STATUS__SYS_SCLK_MASK 0x00000001L
+#define UVD_CGC_STATUS__SYS_DCLK_MASK 0x00000002L
+#define UVD_CGC_STATUS__SYS_VCLK_MASK 0x00000004L
+#define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x00000008L
+#define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x00000010L
+#define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x00000020L
+#define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x00000040L
+#define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x00000080L
+#define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x00000100L
+#define UVD_CGC_STATUS__REGS_SCLK_MASK 0x00000200L
+#define UVD_CGC_STATUS__REGS_VCLK_MASK 0x00000400L
+#define UVD_CGC_STATUS__RBC_SCLK_MASK 0x00000800L
+#define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x00001000L
+#define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x00002000L
+#define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x00004000L
+#define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x00008000L
+#define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x00010000L
+#define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x00020000L
+#define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x00040000L
+#define UVD_CGC_STATUS__MPC_SCLK_MASK 0x00080000L
+#define UVD_CGC_STATUS__MPC_DCLK_MASK 0x00100000L
+#define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x00200000L
+#define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x00400000L
+#define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x00800000L
+#define UVD_CGC_STATUS__WCB_SCLK_MASK 0x01000000L
+#define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x02000000L
+#define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x04000000L
+#define UVD_CGC_STATUS__MMSCH_SCLK_MASK 0x08000000L
+#define UVD_CGC_STATUS__MMSCH_VCLK_MASK 0x10000000L
+#define UVD_CGC_STATUS__ALL_ENC_ACTIVE_MASK 0x20000000L
+#define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK 0x80000000L
+//UVD_CGC_CTRL
+#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0
+#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2
+#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6
+#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb
+#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc
+#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd
+#define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe
+#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf
+#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10
+#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11
+#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12
+#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13
+#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14
+#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15
+#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16
+#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17
+#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18
+#define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19
+#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a
+#define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b
+#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c
+#define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d
+#define UVD_CGC_CTRL__MMSCH_MODE__SHIFT 0x1f
+#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L
+#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL
+#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L
+#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L
+#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L
+#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L
+#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L
+#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L
+#define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L
+#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L
+#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L
+#define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L
+#define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L
+#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L
+#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L
+#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L
+#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L
+#define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L
+#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L
+#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L
+#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L
+#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L
+#define UVD_CGC_CTRL__MMSCH_MODE_MASK 0x80000000L
+//UVD_CGC_UDEC_STATUS
+#define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0
+#define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1
+#define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2
+#define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3
+#define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4
+#define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5
+#define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6
+#define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7
+#define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8
+#define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9
+#define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa
+#define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb
+#define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc
+#define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd
+#define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe
+#define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x00000001L
+#define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x00000002L
+#define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x00000004L
+#define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x00000008L
+#define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x00000010L
+#define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x00000020L
+#define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x00000040L
+#define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x00000080L
+#define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x00000100L
+#define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x00000200L
+#define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x00000400L
+#define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x00000800L
+#define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x00001000L
+#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x00002000L
+#define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x00004000L
+//UVD_SUVD_CGC_GATE
+#define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0
+#define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1
+#define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2
+#define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3
+#define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4
+#define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
+#define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6
+#define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7
+#define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8
+#define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9
+#define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
+#define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb
+#define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc
+#define UVD_SUVD_CGC_GATE__SCLR__SHIFT 0xd
+#define UVD_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe
+#define UVD_SUVD_CGC_GATE__ENT__SHIFT 0xf
+#define UVD_SUVD_CGC_GATE__IME__SHIFT 0x10
+#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11
+#define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12
+#define UVD_SUVD_CGC_GATE__SITE__SHIFT 0x13
+#define UVD_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14
+#define UVD_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15
+#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16
+#define UVD_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17
+#define UVD_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18
+#define UVD_SUVD_CGC_GATE__EFC__SHIFT 0x19
+#define UVD_SUVD_CGC_GATE__SRE_MASK 0x00000001L
+#define UVD_SUVD_CGC_GATE__SIT_MASK 0x00000002L
+#define UVD_SUVD_CGC_GATE__SMP_MASK 0x00000004L
+#define UVD_SUVD_CGC_GATE__SCM_MASK 0x00000008L
+#define UVD_SUVD_CGC_GATE__SDB_MASK 0x00000010L
+#define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L
+#define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L
+#define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L
+#define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L
+#define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L
+#define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L
+#define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L
+#define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L
+#define UVD_SUVD_CGC_GATE__SCLR_MASK 0x00002000L
+#define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L
+#define UVD_SUVD_CGC_GATE__ENT_MASK 0x00008000L
+#define UVD_SUVD_CGC_GATE__IME_MASK 0x00010000L
+#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L
+#define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L
+#define UVD_SUVD_CGC_GATE__SITE_MASK 0x00080000L
+#define UVD_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L
+#define UVD_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L
+#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L
+#define UVD_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L
+#define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L
+#define UVD_SUVD_CGC_GATE__EFC_MASK 0x02000000L
+//UVD_SUVD_CGC_STATUS
+#define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0
+#define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT 0x1
+#define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2
+#define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3
+#define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT 0x4
+#define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5
+#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6
+#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT 0x7
+#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT 0x8
+#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9
+#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa
+#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb
+#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT 0xc
+#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd
+#define UVD_SUVD_CGC_STATUS__SCLR_DCLK__SHIFT 0xe
+#define UVD_SUVD_CGC_STATUS__UVD_SC__SHIFT 0xf
+#define UVD_SUVD_CGC_STATUS__ENT_DCLK__SHIFT 0x10
+#define UVD_SUVD_CGC_STATUS__IME_DCLK__SHIFT 0x11
+#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK__SHIFT 0x12
+#define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK__SHIFT 0x13
+#define UVD_SUVD_CGC_STATUS__SITE_DCLK__SHIFT 0x14
+#define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK__SHIFT 0x15
+#define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK__SHIFT 0x16
+#define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK__SHIFT 0x17
+#define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK__SHIFT 0x18
+#define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK__SHIFT 0x19
+#define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK__SHIFT 0x1a
+#define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK__SHIFT 0x1b
+#define UVD_SUVD_CGC_STATUS__EFC_DCLK__SHIFT 0x1c
+#define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x00000001L
+#define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x00000002L
+#define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x00000004L
+#define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x00000008L
+#define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x00000010L
+#define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x00000020L
+#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x00000040L
+#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x00000080L
+#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x00000100L
+#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x00000200L
+#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK 0x00000400L
+#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x00000800L
+#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK 0x00001000L
+#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x00002000L
+#define UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK 0x00004000L
+#define UVD_SUVD_CGC_STATUS__UVD_SC_MASK 0x00008000L
+#define UVD_SUVD_CGC_STATUS__ENT_DCLK_MASK 0x00010000L
+#define UVD_SUVD_CGC_STATUS__IME_DCLK_MASK 0x00020000L
+#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK_MASK 0x00040000L
+#define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK_MASK 0x00080000L
+#define UVD_SUVD_CGC_STATUS__SITE_DCLK_MASK 0x00100000L
+#define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK_MASK 0x00200000L
+#define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK_MASK 0x00400000L
+#define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK_MASK 0x00800000L
+#define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK_MASK 0x01000000L
+#define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK_MASK 0x02000000L
+#define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK_MASK 0x04000000L
+#define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK_MASK 0x08000000L
+#define UVD_SUVD_CGC_STATUS__EFC_DCLK_MASK 0x10000000L
+//UVD_SUVD_CGC_CTRL
+#define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0
+#define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1
+#define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2
+#define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3
+#define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4
+#define UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5
+#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6
+#define UVD_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7
+#define UVD_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8
+#define UVD_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9
+#define UVD_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
+#define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L
+#define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L
+#define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L
+#define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L
+#define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L
+#define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L
+#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L
+#define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L
+#define UVD_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L
+#define UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L
+#define UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L
+//UVD_GPCOM_VCPU_CMD
+#define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0
+#define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1
+#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f
+#define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x00000001L
+#define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7FFFFFFEL
+#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000L
+//UVD_GPCOM_VCPU_DATA0
+#define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0
+#define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xFFFFFFFFL
+//UVD_GPCOM_VCPU_DATA1
+#define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0
+#define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xFFFFFFFFL
+//UVD_GPCOM_SYS_CMD
+#define UVD_GPCOM_SYS_CMD__CMD_SEND__SHIFT 0x0
+#define UVD_GPCOM_SYS_CMD__CMD__SHIFT 0x1
+#define UVD_GPCOM_SYS_CMD__CMD_SOURCE__SHIFT 0x1f
+#define UVD_GPCOM_SYS_CMD__CMD_SEND_MASK 0x00000001L
+#define UVD_GPCOM_SYS_CMD__CMD_MASK 0x7FFFFFFEL
+#define UVD_GPCOM_SYS_CMD__CMD_SOURCE_MASK 0x80000000L
+//UVD_GPCOM_SYS_DATA0
+#define UVD_GPCOM_SYS_DATA0__DATA0__SHIFT 0x0
+#define UVD_GPCOM_SYS_DATA0__DATA0_MASK 0xFFFFFFFFL
+//UVD_GPCOM_SYS_DATA1
+#define UVD_GPCOM_SYS_DATA1__DATA1__SHIFT 0x0
+#define UVD_GPCOM_SYS_DATA1__DATA1_MASK 0xFFFFFFFFL
+//UVD_VCPU_INT_EN
+#define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0
+#define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1
+#define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2
+#define UVD_VCPU_INT_EN__NJ_PF_RPT_EN__SHIFT 0x3
+#define UVD_VCPU_INT_EN__SW_RB1_INT_EN__SHIFT 0x4
+#define UVD_VCPU_INT_EN__SW_RB2_INT_EN__SHIFT 0x5
+#define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6
+#define UVD_VCPU_INT_EN__SW_RB3_INT_EN__SHIFT 0x7
+#define UVD_VCPU_INT_EN__SW_RB4_INT_EN__SHIFT 0x9
+#define UVD_VCPU_INT_EN__SW_RB5_INT_EN__SHIFT 0xa
+#define UVD_VCPU_INT_EN__LBSI_EN__SHIFT 0xb
+#define UVD_VCPU_INT_EN__UDEC_EN__SHIFT 0xc
+#define UVD_VCPU_INT_EN__SUVD_EN__SHIFT 0xf
+#define UVD_VCPU_INT_EN__RPTR_WR_EN__SHIFT 0x10
+#define UVD_VCPU_INT_EN__JOB_START_EN__SHIFT 0x11
+#define UVD_VCPU_INT_EN__NJ_PF_EN__SHIFT 0x12
+#define UVD_VCPU_INT_EN__RASCNTL_VCPU_VCODEC_EN__SHIFT 0x16
+#define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17
+#define UVD_VCPU_INT_EN__IDCT_EN__SHIFT 0x18
+#define UVD_VCPU_INT_EN__MPRD_EN__SHIFT 0x19
+#define UVD_VCPU_INT_EN__AVM_INT_EN__SHIFT 0x1a
+#define UVD_VCPU_INT_EN__CLK_SWT_EN__SHIFT 0x1b
+#define UVD_VCPU_INT_EN__MIF_HWINT_EN__SHIFT 0x1c
+#define UVD_VCPU_INT_EN__MPRD_ERR_EN__SHIFT 0x1d
+#define UVD_VCPU_INT_EN__DRV_FW_REQ_EN__SHIFT 0x1e
+#define UVD_VCPU_INT_EN__DRV_FW_ACK_EN__SHIFT 0x1f
+#define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L
+#define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L
+#define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L
+#define UVD_VCPU_INT_EN__NJ_PF_RPT_EN_MASK 0x00000008L
+#define UVD_VCPU_INT_EN__SW_RB1_INT_EN_MASK 0x00000010L
+#define UVD_VCPU_INT_EN__SW_RB2_INT_EN_MASK 0x00000020L
+#define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L
+#define UVD_VCPU_INT_EN__SW_RB3_INT_EN_MASK 0x00000080L
+#define UVD_VCPU_INT_EN__SW_RB4_INT_EN_MASK 0x00000200L
+#define UVD_VCPU_INT_EN__SW_RB5_INT_EN_MASK 0x00000400L
+#define UVD_VCPU_INT_EN__LBSI_EN_MASK 0x00000800L
+#define UVD_VCPU_INT_EN__UDEC_EN_MASK 0x00001000L
+#define UVD_VCPU_INT_EN__SUVD_EN_MASK 0x00008000L
+#define UVD_VCPU_INT_EN__RPTR_WR_EN_MASK 0x00010000L
+#define UVD_VCPU_INT_EN__JOB_START_EN_MASK 0x00020000L
+#define UVD_VCPU_INT_EN__NJ_PF_EN_MASK 0x00040000L
+#define UVD_VCPU_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK 0x00400000L
+#define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L
+#define UVD_VCPU_INT_EN__IDCT_EN_MASK 0x01000000L
+#define UVD_VCPU_INT_EN__MPRD_EN_MASK 0x02000000L
+#define UVD_VCPU_INT_EN__AVM_INT_EN_MASK 0x04000000L
+#define UVD_VCPU_INT_EN__CLK_SWT_EN_MASK 0x08000000L
+#define UVD_VCPU_INT_EN__MIF_HWINT_EN_MASK 0x10000000L
+#define UVD_VCPU_INT_EN__MPRD_ERR_EN_MASK 0x20000000L
+#define UVD_VCPU_INT_EN__DRV_FW_REQ_EN_MASK 0x40000000L
+#define UVD_VCPU_INT_EN__DRV_FW_ACK_EN_MASK 0x80000000L
+//UVD_VCPU_INT_STATUS
+#define UVD_VCPU_INT_STATUS__PIF_ADDR_ERR_INT__SHIFT 0x0
+#define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT__SHIFT 0x1
+#define UVD_VCPU_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT__SHIFT 0x2
+#define UVD_VCPU_INT_STATUS__NJ_PF_RPT_INT__SHIFT 0x3
+#define UVD_VCPU_INT_STATUS__SW_RB1_INT__SHIFT 0x4
+#define UVD_VCPU_INT_STATUS__SW_RB2_INT__SHIFT 0x5
+#define UVD_VCPU_INT_STATUS__RBC_REG_PRIV_FAULT_INT__SHIFT 0x6
+#define UVD_VCPU_INT_STATUS__SW_RB3_INT__SHIFT 0x7
+#define UVD_VCPU_INT_STATUS__SW_RB4_INT__SHIFT 0x9
+#define UVD_VCPU_INT_STATUS__SW_RB5_INT__SHIFT 0xa
+#define UVD_VCPU_INT_STATUS__LBSI_INT__SHIFT 0xb
+#define UVD_VCPU_INT_STATUS__UDEC_INT__SHIFT 0xc
+#define UVD_VCPU_INT_STATUS__SUVD_INT__SHIFT 0xf
+#define UVD_VCPU_INT_STATUS__RPTR_WR_INT__SHIFT 0x10
+#define UVD_VCPU_INT_STATUS__JOB_START_INT__SHIFT 0x11
+#define UVD_VCPU_INT_STATUS__NJ_PF_INT__SHIFT 0x12
+#define UVD_VCPU_INT_STATUS__GPCOM_INT__SHIFT 0x14
+#define UVD_VCPU_INT_STATUS__RASCNTL_VCPU_VCODEC_INT__SHIFT 0x15
+#define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT__SHIFT 0x17
+#define UVD_VCPU_INT_STATUS__IDCT_INT__SHIFT 0x18
+#define UVD_VCPU_INT_STATUS__MPRD_INT__SHIFT 0x19
+#define UVD_VCPU_INT_STATUS__AVM_INT__SHIFT 0x1a
+#define UVD_VCPU_INT_STATUS__CLK_SWT_INT__SHIFT 0x1b
+#define UVD_VCPU_INT_STATUS__MIF_HWINT__SHIFT 0x1c
+#define UVD_VCPU_INT_STATUS__MPRD_ERR_INT__SHIFT 0x1d
+#define UVD_VCPU_INT_STATUS__DRV_FW_REQ_INT__SHIFT 0x1e
+#define UVD_VCPU_INT_STATUS__DRV_FW_ACK_INT__SHIFT 0x1f
+#define UVD_VCPU_INT_STATUS__PIF_ADDR_ERR_INT_MASK 0x00000001L
+#define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT_MASK 0x00000002L
+#define UVD_VCPU_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT_MASK 0x00000004L
+#define UVD_VCPU_INT_STATUS__NJ_PF_RPT_INT_MASK 0x00000008L
+#define UVD_VCPU_INT_STATUS__SW_RB1_INT_MASK 0x00000010L
+#define UVD_VCPU_INT_STATUS__SW_RB2_INT_MASK 0x00000020L
+#define UVD_VCPU_INT_STATUS__RBC_REG_PRIV_FAULT_INT_MASK 0x00000040L
+#define UVD_VCPU_INT_STATUS__SW_RB3_INT_MASK 0x00000080L
+#define UVD_VCPU_INT_STATUS__SW_RB4_INT_MASK 0x00000200L
+#define UVD_VCPU_INT_STATUS__SW_RB5_INT_MASK 0x00000400L
+#define UVD_VCPU_INT_STATUS__LBSI_INT_MASK 0x00000800L
+#define UVD_VCPU_INT_STATUS__UDEC_INT_MASK 0x00001000L
+#define UVD_VCPU_INT_STATUS__SUVD_INT_MASK 0x00008000L
+#define UVD_VCPU_INT_STATUS__RPTR_WR_INT_MASK 0x00010000L
+#define UVD_VCPU_INT_STATUS__JOB_START_INT_MASK 0x00020000L
+#define UVD_VCPU_INT_STATUS__NJ_PF_INT_MASK 0x00040000L
+#define UVD_VCPU_INT_STATUS__GPCOM_INT_MASK 0x00100000L
+#define UVD_VCPU_INT_STATUS__RASCNTL_VCPU_VCODEC_INT_MASK 0x00200000L
+#define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT_MASK 0x00800000L
+#define UVD_VCPU_INT_STATUS__IDCT_INT_MASK 0x01000000L
+#define UVD_VCPU_INT_STATUS__MPRD_INT_MASK 0x02000000L
+#define UVD_VCPU_INT_STATUS__AVM_INT_MASK 0x04000000L
+#define UVD_VCPU_INT_STATUS__CLK_SWT_INT_MASK 0x08000000L
+#define UVD_VCPU_INT_STATUS__MIF_HWINT_MASK 0x10000000L
+#define UVD_VCPU_INT_STATUS__MPRD_ERR_INT_MASK 0x20000000L
+#define UVD_VCPU_INT_STATUS__DRV_FW_REQ_INT_MASK 0x40000000L
+#define UVD_VCPU_INT_STATUS__DRV_FW_ACK_INT_MASK 0x80000000L
+//UVD_VCPU_INT_ACK
+#define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0
+#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1
+#define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2
+#define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK__SHIFT 0x3
+#define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK__SHIFT 0x4
+#define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK__SHIFT 0x5
+#define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6
+#define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK__SHIFT 0x7
+#define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK__SHIFT 0x9
+#define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK__SHIFT 0xa
+#define UVD_VCPU_INT_ACK__LBSI_ACK__SHIFT 0xb
+#define UVD_VCPU_INT_ACK__UDEC_ACK__SHIFT 0xc
+#define UVD_VCPU_INT_ACK__SUVD_ACK__SHIFT 0xf
+#define UVD_VCPU_INT_ACK__RPTR_WR_ACK__SHIFT 0x10
+#define UVD_VCPU_INT_ACK__JOB_START_ACK__SHIFT 0x11
+#define UVD_VCPU_INT_ACK__NJ_PF_ACK__SHIFT 0x12
+#define UVD_VCPU_INT_ACK__RASCNTL_VCPU_VCODEC_ACK__SHIFT 0x16
+#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17
+#define UVD_VCPU_INT_ACK__IDCT_ACK__SHIFT 0x18
+#define UVD_VCPU_INT_ACK__MPRD_ACK__SHIFT 0x19
+#define UVD_VCPU_INT_ACK__AVM_INT_ACK__SHIFT 0x1a
+#define UVD_VCPU_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b
+#define UVD_VCPU_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c
+#define UVD_VCPU_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d
+#define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK__SHIFT 0x1e
+#define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK__SHIFT 0x1f
+#define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L
+#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L
+#define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L
+#define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK_MASK 0x00000008L
+#define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK_MASK 0x00000010L
+#define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK_MASK 0x00000020L
+#define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L
+#define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK_MASK 0x00000080L
+#define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK_MASK 0x00000200L
+#define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK_MASK 0x00000400L
+#define UVD_VCPU_INT_ACK__LBSI_ACK_MASK 0x00000800L
+#define UVD_VCPU_INT_ACK__UDEC_ACK_MASK 0x00001000L
+#define UVD_VCPU_INT_ACK__SUVD_ACK_MASK 0x00008000L
+#define UVD_VCPU_INT_ACK__RPTR_WR_ACK_MASK 0x00010000L
+#define UVD_VCPU_INT_ACK__JOB_START_ACK_MASK 0x00020000L
+#define UVD_VCPU_INT_ACK__NJ_PF_ACK_MASK 0x00040000L
+#define UVD_VCPU_INT_ACK__RASCNTL_VCPU_VCODEC_ACK_MASK 0x00400000L
+#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L
+#define UVD_VCPU_INT_ACK__IDCT_ACK_MASK 0x01000000L
+#define UVD_VCPU_INT_ACK__MPRD_ACK_MASK 0x02000000L
+#define UVD_VCPU_INT_ACK__AVM_INT_ACK_MASK 0x04000000L
+#define UVD_VCPU_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L
+#define UVD_VCPU_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L
+#define UVD_VCPU_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L
+#define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK_MASK 0x40000000L
+#define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK_MASK 0x80000000L
+//UVD_VCPU_INT_ROUTE
+#define UVD_VCPU_INT_ROUTE__DRV_FW_MSG__SHIFT 0x0
+#define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK__SHIFT 0x1
+#define UVD_VCPU_INT_ROUTE__VCPU_GPCOM__SHIFT 0x2
+#define UVD_VCPU_INT_ROUTE__DRV_FW_MSG_MASK 0x00000001L
+#define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK_MASK 0x00000002L
+#define UVD_VCPU_INT_ROUTE__VCPU_GPCOM_MASK 0x00000004L
+//UVD_DRV_FW_MSG
+#define UVD_DRV_FW_MSG__MSG__SHIFT 0x0
+#define UVD_DRV_FW_MSG__MSG_MASK 0xFFFFFFFFL
+//UVD_FW_DRV_MSG_ACK
+#define UVD_FW_DRV_MSG_ACK__ACK__SHIFT 0x0
+#define UVD_FW_DRV_MSG_ACK__ACK_MASK 0x00000001L
+//UVD_SUVD_INT_EN
+#define UVD_SUVD_INT_EN__SRE_FUNC_INT_EN__SHIFT 0x0
+#define UVD_SUVD_INT_EN__SRE_ERR_INT_EN__SHIFT 0x5
+#define UVD_SUVD_INT_EN__SIT_FUNC_INT_EN__SHIFT 0x6
+#define UVD_SUVD_INT_EN__SIT_ERR_INT_EN__SHIFT 0xb
+#define UVD_SUVD_INT_EN__SMP_FUNC_INT_EN__SHIFT 0xc
+#define UVD_SUVD_INT_EN__SMP_ERR_INT_EN__SHIFT 0x11
+#define UVD_SUVD_INT_EN__SCM_FUNC_INT_EN__SHIFT 0x12
+#define UVD_SUVD_INT_EN__SCM_ERR_INT_EN__SHIFT 0x17
+#define UVD_SUVD_INT_EN__SDB_FUNC_INT_EN__SHIFT 0x18
+#define UVD_SUVD_INT_EN__SDB_ERR_INT_EN__SHIFT 0x1d
+#define UVD_SUVD_INT_EN__SRE_FUNC_INT_EN_MASK 0x0000001FL
+#define UVD_SUVD_INT_EN__SRE_ERR_INT_EN_MASK 0x00000020L
+#define UVD_SUVD_INT_EN__SIT_FUNC_INT_EN_MASK 0x000007C0L
+#define UVD_SUVD_INT_EN__SIT_ERR_INT_EN_MASK 0x00000800L
+#define UVD_SUVD_INT_EN__SMP_FUNC_INT_EN_MASK 0x0001F000L
+#define UVD_SUVD_INT_EN__SMP_ERR_INT_EN_MASK 0x00020000L
+#define UVD_SUVD_INT_EN__SCM_FUNC_INT_EN_MASK 0x007C0000L
+#define UVD_SUVD_INT_EN__SCM_ERR_INT_EN_MASK 0x00800000L
+#define UVD_SUVD_INT_EN__SDB_FUNC_INT_EN_MASK 0x1F000000L
+#define UVD_SUVD_INT_EN__SDB_ERR_INT_EN_MASK 0x20000000L
+//UVD_SUVD_INT_STATUS
+#define UVD_SUVD_INT_STATUS__SRE_FUNC_INT__SHIFT 0x0
+#define UVD_SUVD_INT_STATUS__SRE_ERR_INT__SHIFT 0x5
+#define UVD_SUVD_INT_STATUS__SIT_FUNC_INT__SHIFT 0x6
+#define UVD_SUVD_INT_STATUS__SIT_ERR_INT__SHIFT 0xb
+#define UVD_SUVD_INT_STATUS__SMP_FUNC_INT__SHIFT 0xc
+#define UVD_SUVD_INT_STATUS__SMP_ERR_INT__SHIFT 0x11
+#define UVD_SUVD_INT_STATUS__SCM_FUNC_INT__SHIFT 0x12
+#define UVD_SUVD_INT_STATUS__SCM_ERR_INT__SHIFT 0x17
+#define UVD_SUVD_INT_STATUS__SDB_FUNC_INT__SHIFT 0x18
+#define UVD_SUVD_INT_STATUS__SDB_ERR_INT__SHIFT 0x1d
+#define UVD_SUVD_INT_STATUS__SRE_FUNC_INT_MASK 0x0000001FL
+#define UVD_SUVD_INT_STATUS__SRE_ERR_INT_MASK 0x00000020L
+#define UVD_SUVD_INT_STATUS__SIT_FUNC_INT_MASK 0x000007C0L
+#define UVD_SUVD_INT_STATUS__SIT_ERR_INT_MASK 0x00000800L
+#define UVD_SUVD_INT_STATUS__SMP_FUNC_INT_MASK 0x0001F000L
+#define UVD_SUVD_INT_STATUS__SMP_ERR_INT_MASK 0x00020000L
+#define UVD_SUVD_INT_STATUS__SCM_FUNC_INT_MASK 0x007C0000L
+#define UVD_SUVD_INT_STATUS__SCM_ERR_INT_MASK 0x00800000L
+#define UVD_SUVD_INT_STATUS__SDB_FUNC_INT_MASK 0x1F000000L
+#define UVD_SUVD_INT_STATUS__SDB_ERR_INT_MASK 0x20000000L
+//UVD_SUVD_INT_ACK
+#define UVD_SUVD_INT_ACK__SRE_FUNC_INT_ACK__SHIFT 0x0
+#define UVD_SUVD_INT_ACK__SRE_ERR_INT_ACK__SHIFT 0x5
+#define UVD_SUVD_INT_ACK__SIT_FUNC_INT_ACK__SHIFT 0x6
+#define UVD_SUVD_INT_ACK__SIT_ERR_INT_ACK__SHIFT 0xb
+#define UVD_SUVD_INT_ACK__SMP_FUNC_INT_ACK__SHIFT 0xc
+#define UVD_SUVD_INT_ACK__SMP_ERR_INT_ACK__SHIFT 0x11
+#define UVD_SUVD_INT_ACK__SCM_FUNC_INT_ACK__SHIFT 0x12
+#define UVD_SUVD_INT_ACK__SCM_ERR_INT_ACK__SHIFT 0x17
+#define UVD_SUVD_INT_ACK__SDB_FUNC_INT_ACK__SHIFT 0x18
+#define UVD_SUVD_INT_ACK__SDB_ERR_INT_ACK__SHIFT 0x1d
+#define UVD_SUVD_INT_ACK__SRE_FUNC_INT_ACK_MASK 0x0000001FL
+#define UVD_SUVD_INT_ACK__SRE_ERR_INT_ACK_MASK 0x00000020L
+#define UVD_SUVD_INT_ACK__SIT_FUNC_INT_ACK_MASK 0x000007C0L
+#define UVD_SUVD_INT_ACK__SIT_ERR_INT_ACK_MASK 0x00000800L
+#define UVD_SUVD_INT_ACK__SMP_FUNC_INT_ACK_MASK 0x0001F000L
+#define UVD_SUVD_INT_ACK__SMP_ERR_INT_ACK_MASK 0x00020000L
+#define UVD_SUVD_INT_ACK__SCM_FUNC_INT_ACK_MASK 0x007C0000L
+#define UVD_SUVD_INT_ACK__SCM_ERR_INT_ACK_MASK 0x00800000L
+#define UVD_SUVD_INT_ACK__SDB_FUNC_INT_ACK_MASK 0x1F000000L
+#define UVD_SUVD_INT_ACK__SDB_ERR_INT_ACK_MASK 0x20000000L
+//UVD_ENC_VCPU_INT_EN
+#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN__SHIFT 0x0
+#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN__SHIFT 0x1
+#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN__SHIFT 0x2
+#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN_MASK 0x00000001L
+#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN_MASK 0x00000002L
+#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN_MASK 0x00000004L
+//UVD_ENC_VCPU_INT_STATUS
+#define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR_INT__SHIFT 0x0
+#define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR2_INT__SHIFT 0x1
+#define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR3_INT__SHIFT 0x2
+#define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR_INT_MASK 0x00000001L
+#define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR2_INT_MASK 0x00000002L
+#define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR3_INT_MASK 0x00000004L
+//UVD_ENC_VCPU_INT_ACK
+#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK__SHIFT 0x0
+#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK__SHIFT 0x1
+#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK__SHIFT 0x2
+#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK_MASK 0x00000001L
+#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK_MASK 0x00000002L
+#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK_MASK 0x00000004L
+//UVD_MASTINT_EN
+#define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0
+#define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1
+#define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2
+#define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4
+#define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L
+#define UVD_MASTINT_EN__VCPU_EN_MASK 0x00000002L
+#define UVD_MASTINT_EN__SYS_EN_MASK 0x00000004L
+#define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x00FFFFF0L
+//UVD_SYS_INT_EN
+#define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0
+#define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1
+#define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2
+#define UVD_SYS_INT_EN__CXW_WR_EN__SHIFT 0x3
+#define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6
+#define UVD_SYS_INT_EN__LBSI_EN__SHIFT 0xb
+#define UVD_SYS_INT_EN__UDEC_EN__SHIFT 0xc
+#define UVD_SYS_INT_EN__SUVD_EN__SHIFT 0xf
+#define UVD_SYS_INT_EN__JOB_DONE_EN__SHIFT 0x10
+#define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17
+#define UVD_SYS_INT_EN__IDCT_EN__SHIFT 0x18
+#define UVD_SYS_INT_EN__MPRD_EN__SHIFT 0x19
+#define UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN__SHIFT 0x1a
+#define UVD_SYS_INT_EN__CLK_SWT_EN__SHIFT 0x1b
+#define UVD_SYS_INT_EN__MIF_HWINT_EN__SHIFT 0x1c
+#define UVD_SYS_INT_EN__MPRD_ERR_EN__SHIFT 0x1d
+#define UVD_SYS_INT_EN__AVM_INT_EN__SHIFT 0x1f
+#define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L
+#define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L
+#define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L
+#define UVD_SYS_INT_EN__CXW_WR_EN_MASK 0x00000008L
+#define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L
+#define UVD_SYS_INT_EN__LBSI_EN_MASK 0x00000800L
+#define UVD_SYS_INT_EN__UDEC_EN_MASK 0x00001000L
+#define UVD_SYS_INT_EN__SUVD_EN_MASK 0x00008000L
+#define UVD_SYS_INT_EN__JOB_DONE_EN_MASK 0x00010000L
+#define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L
+#define UVD_SYS_INT_EN__IDCT_EN_MASK 0x01000000L
+#define UVD_SYS_INT_EN__MPRD_EN_MASK 0x02000000L
+#define UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK 0x04000000L
+#define UVD_SYS_INT_EN__CLK_SWT_EN_MASK 0x08000000L
+#define UVD_SYS_INT_EN__MIF_HWINT_EN_MASK 0x10000000L
+#define UVD_SYS_INT_EN__MPRD_ERR_EN_MASK 0x20000000L
+#define UVD_SYS_INT_EN__AVM_INT_EN_MASK 0x80000000L
+//UVD_SYS_INT_STATUS
+#define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT__SHIFT 0x0
+#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT__SHIFT 0x1
+#define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT__SHIFT 0x2
+#define UVD_SYS_INT_STATUS__CXW_WR_INT__SHIFT 0x3
+#define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT__SHIFT 0x6
+#define UVD_SYS_INT_STATUS__LBSI_INT__SHIFT 0xb
+#define UVD_SYS_INT_STATUS__UDEC_INT__SHIFT 0xc
+#define UVD_SYS_INT_STATUS__SUVD_INT__SHIFT 0xf
+#define UVD_SYS_INT_STATUS__JOB_DONE_INT__SHIFT 0x10
+#define UVD_SYS_INT_STATUS__GPCOM_INT__SHIFT 0x12
+#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT__SHIFT 0x17
+#define UVD_SYS_INT_STATUS__IDCT_INT__SHIFT 0x18
+#define UVD_SYS_INT_STATUS__MPRD_INT__SHIFT 0x19
+#define UVD_SYS_INT_STATUS__CLK_SWT_INT__SHIFT 0x1b
+#define UVD_SYS_INT_STATUS__MIF_HWINT__SHIFT 0x1c
+#define UVD_SYS_INT_STATUS__MPRD_ERR_INT__SHIFT 0x1d
+#define UVD_SYS_INT_STATUS__RASCNTL_VCPU_VCODEC_INT__SHIFT 0x1e
+#define UVD_SYS_INT_STATUS__AVM_INT__SHIFT 0x1f
+#define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT_MASK 0x00000001L
+#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT_MASK 0x00000002L
+#define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT_MASK 0x00000004L
+#define UVD_SYS_INT_STATUS__CXW_WR_INT_MASK 0x00000008L
+#define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT_MASK 0x00000040L
+#define UVD_SYS_INT_STATUS__LBSI_INT_MASK 0x00000800L
+#define UVD_SYS_INT_STATUS__UDEC_INT_MASK 0x00001000L
+#define UVD_SYS_INT_STATUS__SUVD_INT_MASK 0x00008000L
+#define UVD_SYS_INT_STATUS__JOB_DONE_INT_MASK 0x00010000L
+#define UVD_SYS_INT_STATUS__GPCOM_INT_MASK 0x00040000L
+#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT_MASK 0x00800000L
+#define UVD_SYS_INT_STATUS__IDCT_INT_MASK 0x01000000L
+#define UVD_SYS_INT_STATUS__MPRD_INT_MASK 0x02000000L
+#define UVD_SYS_INT_STATUS__CLK_SWT_INT_MASK 0x08000000L
+#define UVD_SYS_INT_STATUS__MIF_HWINT_MASK 0x10000000L
+#define UVD_SYS_INT_STATUS__MPRD_ERR_INT_MASK 0x20000000L
+#define UVD_SYS_INT_STATUS__RASCNTL_VCPU_VCODEC_INT_MASK 0x40000000L
+#define UVD_SYS_INT_STATUS__AVM_INT_MASK 0x80000000L
+//UVD_SYS_INT_ACK
+#define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0
+#define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1
+#define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2
+#define UVD_SYS_INT_ACK__CXW_WR_ACK__SHIFT 0x3
+#define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6
+#define UVD_SYS_INT_ACK__LBSI_ACK__SHIFT 0xb
+#define UVD_SYS_INT_ACK__UDEC_ACK__SHIFT 0xc
+#define UVD_SYS_INT_ACK__SUVD_ACK__SHIFT 0xf
+#define UVD_SYS_INT_ACK__JOB_DONE_ACK__SHIFT 0x10
+#define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17
+#define UVD_SYS_INT_ACK__IDCT_ACK__SHIFT 0x18
+#define UVD_SYS_INT_ACK__MPRD_ACK__SHIFT 0x19
+#define UVD_SYS_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b
+#define UVD_SYS_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c
+#define UVD_SYS_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d
+#define UVD_SYS_INT_ACK__RASCNTL_VCPU_VCODEC_ACK__SHIFT 0x1e
+#define UVD_SYS_INT_ACK__AVM_INT_ACK__SHIFT 0x1f
+#define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L
+#define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L
+#define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L
+#define UVD_SYS_INT_ACK__CXW_WR_ACK_MASK 0x00000008L
+#define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L
+#define UVD_SYS_INT_ACK__LBSI_ACK_MASK 0x00000800L
+#define UVD_SYS_INT_ACK__UDEC_ACK_MASK 0x00001000L
+#define UVD_SYS_INT_ACK__SUVD_ACK_MASK 0x00008000L
+#define UVD_SYS_INT_ACK__JOB_DONE_ACK_MASK 0x00010000L
+#define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L
+#define UVD_SYS_INT_ACK__IDCT_ACK_MASK 0x01000000L
+#define UVD_SYS_INT_ACK__MPRD_ACK_MASK 0x02000000L
+#define UVD_SYS_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L
+#define UVD_SYS_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L
+#define UVD_SYS_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L
+#define UVD_SYS_INT_ACK__RASCNTL_VCPU_VCODEC_ACK_MASK 0x40000000L
+#define UVD_SYS_INT_ACK__AVM_INT_ACK_MASK 0x80000000L
+//UVD_JOB_DONE
+#define UVD_JOB_DONE__JOB_DONE__SHIFT 0x0
+#define UVD_JOB_DONE__JOB_DONE_MASK 0x00000003L
+//UVD_CBUF_ID
+#define UVD_CBUF_ID__CBUF_ID__SHIFT 0x0
+#define UVD_CBUF_ID__CBUF_ID_MASK 0xFFFFFFFFL
+//UVD_CONTEXT_ID
+#define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0
+#define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xFFFFFFFFL
+//UVD_CONTEXT_ID2
+#define UVD_CONTEXT_ID2__CONTEXT_ID2__SHIFT 0x0
+#define UVD_CONTEXT_ID2__CONTEXT_ID2_MASK 0xFFFFFFFFL
+//UVD_NO_OP
+#define UVD_NO_OP__NO_OP__SHIFT 0x0
+#define UVD_NO_OP__NO_OP_MASK 0xFFFFFFFFL
+//UVD_RB_BASE_LO
+#define UVD_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6
+#define UVD_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L
+//UVD_RB_BASE_HI
+#define UVD_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0
+#define UVD_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL
+//UVD_RB_SIZE
+#define UVD_RB_SIZE__RB_SIZE__SHIFT 0x4
+#define UVD_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L
+//UVD_RB_RPTR
+#define UVD_RB_RPTR__RB_RPTR__SHIFT 0x4
+#define UVD_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L
+//UVD_RB_WPTR
+#define UVD_RB_WPTR__RB_WPTR__SHIFT 0x4
+#define UVD_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L
+//UVD_RB_BASE_LO2
+#define UVD_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6
+#define UVD_RB_BASE_LO2__RB_BASE_LO_MASK 0xFFFFFFC0L
+//UVD_RB_BASE_HI2
+#define UVD_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0
+#define UVD_RB_BASE_HI2__RB_BASE_HI_MASK 0xFFFFFFFFL
+//UVD_RB_SIZE2
+#define UVD_RB_SIZE2__RB_SIZE__SHIFT 0x4
+#define UVD_RB_SIZE2__RB_SIZE_MASK 0x007FFFF0L
+//UVD_RB_RPTR2
+#define UVD_RB_RPTR2__RB_RPTR__SHIFT 0x4
+#define UVD_RB_RPTR2__RB_RPTR_MASK 0x007FFFF0L
+//UVD_RB_WPTR2
+#define UVD_RB_WPTR2__RB_WPTR__SHIFT 0x4
+#define UVD_RB_WPTR2__RB_WPTR_MASK 0x007FFFF0L
+//UVD_RB_BASE_LO3
+#define UVD_RB_BASE_LO3__RB_BASE_LO__SHIFT 0x6
+#define UVD_RB_BASE_LO3__RB_BASE_LO_MASK 0xFFFFFFC0L
+//UVD_RB_BASE_HI3
+#define UVD_RB_BASE_HI3__RB_BASE_HI__SHIFT 0x0
+#define UVD_RB_BASE_HI3__RB_BASE_HI_MASK 0xFFFFFFFFL
+//UVD_RB_SIZE3
+#define UVD_RB_SIZE3__RB_SIZE__SHIFT 0x4
+#define UVD_RB_SIZE3__RB_SIZE_MASK 0x007FFFF0L
+//UVD_RB_RPTR3
+#define UVD_RB_RPTR3__RB_RPTR__SHIFT 0x4
+#define UVD_RB_RPTR3__RB_RPTR_MASK 0x007FFFF0L
+//UVD_RB_WPTR3
+#define UVD_RB_WPTR3__RB_WPTR__SHIFT 0x4
+#define UVD_RB_WPTR3__RB_WPTR_MASK 0x007FFFF0L
+//UVD_RB_BASE_LO4
+#define UVD_RB_BASE_LO4__RB_BASE_LO__SHIFT 0x6
+#define UVD_RB_BASE_LO4__RB_BASE_LO_MASK 0xFFFFFFC0L
+//UVD_RB_BASE_HI4
+#define UVD_RB_BASE_HI4__RB_BASE_HI__SHIFT 0x0
+#define UVD_RB_BASE_HI4__RB_BASE_HI_MASK 0xFFFFFFFFL
+//UVD_RB_SIZE4
+#define UVD_RB_SIZE4__RB_SIZE__SHIFT 0x4
+#define UVD_RB_SIZE4__RB_SIZE_MASK 0x007FFFF0L
+//UVD_RB_RPTR4
+#define UVD_RB_RPTR4__RB_RPTR__SHIFT 0x4
+#define UVD_RB_RPTR4__RB_RPTR_MASK 0x007FFFF0L
+//UVD_RB_WPTR4
+#define UVD_RB_WPTR4__RB_WPTR__SHIFT 0x4
+#define UVD_RB_WPTR4__RB_WPTR_MASK 0x007FFFF0L
+//UVD_OUT_RB_BASE_LO
+#define UVD_OUT_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6
+#define UVD_OUT_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L
+//UVD_OUT_RB_BASE_HI
+#define UVD_OUT_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0
+#define UVD_OUT_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL
+//UVD_OUT_RB_SIZE
+#define UVD_OUT_RB_SIZE__RB_SIZE__SHIFT 0x4
+#define UVD_OUT_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L
+//UVD_OUT_RB_RPTR
+#define UVD_OUT_RB_RPTR__RB_RPTR__SHIFT 0x4
+#define UVD_OUT_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L
+//UVD_OUT_RB_WPTR
+#define UVD_OUT_RB_WPTR__RB_WPTR__SHIFT 0x4
+#define UVD_OUT_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L
+//UVD_IOV_MAILBOX
+#define UVD_IOV_MAILBOX__MAILBOX__SHIFT 0x0
+#define UVD_IOV_MAILBOX__MAILBOX_MASK 0xFFFFFFFFL
+//UVD_IOV_MAILBOX_RESP
+#define UVD_IOV_MAILBOX_RESP__RESP__SHIFT 0x0
+#define UVD_IOV_MAILBOX_RESP__RESP_MASK 0xFFFFFFFFL
+//UVD_RB_ARB_CTRL
+#define UVD_RB_ARB_CTRL__SRBM_DROP__SHIFT 0x0
+#define UVD_RB_ARB_CTRL__SRBM_DIS__SHIFT 0x1
+#define UVD_RB_ARB_CTRL__VCPU_DROP__SHIFT 0x2
+#define UVD_RB_ARB_CTRL__VCPU_DIS__SHIFT 0x3
+#define UVD_RB_ARB_CTRL__RBC_DROP__SHIFT 0x4
+#define UVD_RB_ARB_CTRL__RBC_DIS__SHIFT 0x5
+#define UVD_RB_ARB_CTRL__FWOFLD_DROP__SHIFT 0x6
+#define UVD_RB_ARB_CTRL__FWOFLD_DIS__SHIFT 0x7
+#define UVD_RB_ARB_CTRL__FAST_PATH_EN__SHIFT 0x8
+#define UVD_RB_ARB_CTRL__SRBM_DROP_MASK 0x00000001L
+#define UVD_RB_ARB_CTRL__SRBM_DIS_MASK 0x00000002L
+#define UVD_RB_ARB_CTRL__VCPU_DROP_MASK 0x00000004L
+#define UVD_RB_ARB_CTRL__VCPU_DIS_MASK 0x00000008L
+#define UVD_RB_ARB_CTRL__RBC_DROP_MASK 0x00000010L
+#define UVD_RB_ARB_CTRL__RBC_DIS_MASK 0x00000020L
+#define UVD_RB_ARB_CTRL__FWOFLD_DROP_MASK 0x00000040L
+#define UVD_RB_ARB_CTRL__FWOFLD_DIS_MASK 0x00000080L
+#define UVD_RB_ARB_CTRL__FAST_PATH_EN_MASK 0x00000100L
+//UVD_CTX_INDEX
+#define UVD_CTX_INDEX__INDEX__SHIFT 0x0
+#define UVD_CTX_INDEX__INDEX_MASK 0x000001FFL
+//UVD_CTX_DATA
+#define UVD_CTX_DATA__DATA__SHIFT 0x0
+#define UVD_CTX_DATA__DATA_MASK 0xFFFFFFFFL
+//UVD_CXW_WR
+#define UVD_CXW_WR__DAT__SHIFT 0x0
+#define UVD_CXW_WR__STAT__SHIFT 0x1f
+#define UVD_CXW_WR__DAT_MASK 0x0FFFFFFFL
+#define UVD_CXW_WR__STAT_MASK 0x80000000L
+//UVD_CXW_WR_INT_ID
+#define UVD_CXW_WR_INT_ID__ID__SHIFT 0x0
+#define UVD_CXW_WR_INT_ID__ID_MASK 0x000000FFL
+//UVD_CXW_WR_INT_CTX_ID
+#define UVD_CXW_WR_INT_CTX_ID__ID__SHIFT 0x0
+#define UVD_CXW_WR_INT_CTX_ID__ID_MASK 0x0FFFFFFFL
+//UVD_CXW_INT_ID
+#define UVD_CXW_INT_ID__ID__SHIFT 0x0
+#define UVD_CXW_INT_ID__ID_MASK 0x000000FFL
+//UVD_MPEG2_ERROR
+#define UVD_MPEG2_ERROR__STATUS__SHIFT 0x0
+#define UVD_MPEG2_ERROR__STATUS_MASK 0xFFFFFFFFL
+//UVD_TOP_CTRL
+#define UVD_TOP_CTRL__STANDARD__SHIFT 0x0
+#define UVD_TOP_CTRL__STD_VERSION__SHIFT 0x4
+#define UVD_TOP_CTRL__STANDARD_MASK 0x0000000FL
+#define UVD_TOP_CTRL__STD_VERSION_MASK 0x000000F0L
+//UVD_YBASE
+#define UVD_YBASE__DUM__SHIFT 0x0
+#define UVD_YBASE__DUM_MASK 0xFFFFFFFFL
+//UVD_UVBASE
+#define UVD_UVBASE__DUM__SHIFT 0x0
+#define UVD_UVBASE__DUM_MASK 0xFFFFFFFFL
+//UVD_PITCH
+#define UVD_PITCH__DUM__SHIFT 0x0
+#define UVD_PITCH__DUM_MASK 0xFFFFFFFFL
+//UVD_WIDTH
+#define UVD_WIDTH__DUM__SHIFT 0x0
+#define UVD_WIDTH__DUM_MASK 0xFFFFFFFFL
+//UVD_HEIGHT
+#define UVD_HEIGHT__DUM__SHIFT 0x0
+#define UVD_HEIGHT__DUM_MASK 0xFFFFFFFFL
+//UVD_PICCOUNT
+#define UVD_PICCOUNT__DUM__SHIFT 0x0
+#define UVD_PICCOUNT__DUM_MASK 0xFFFFFFFFL
+//UVD_MPRD_INITIAL_XY
+#define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_X__SHIFT 0x0
+#define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_Y__SHIFT 0x10
+#define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_X_MASK 0x00000FFFL
+#define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_Y_MASK 0x0FFF0000L
+//UVD_MPEG2_CTRL
+#define UVD_MPEG2_CTRL__EN__SHIFT 0x0
+#define UVD_MPEG2_CTRL__TRICK_MODE__SHIFT 0x1
+#define UVD_MPEG2_CTRL__NUM_MB_PER_JOB__SHIFT 0x10
+#define UVD_MPEG2_CTRL__EN_MASK 0x00000001L
+#define UVD_MPEG2_CTRL__TRICK_MODE_MASK 0x00000002L
+#define UVD_MPEG2_CTRL__NUM_MB_PER_JOB_MASK 0xFFFF0000L
+//UVD_MB_CTL_BUF_BASE
+#define UVD_MB_CTL_BUF_BASE__BASE__SHIFT 0x0
+#define UVD_MB_CTL_BUF_BASE__BASE_MASK 0xFFFFFFFFL
+//UVD_PIC_CTL_BUF_BASE
+#define UVD_PIC_CTL_BUF_BASE__BASE__SHIFT 0x0
+#define UVD_PIC_CTL_BUF_BASE__BASE_MASK 0xFFFFFFFFL
+//UVD_DXVA_BUF_SIZE
+#define UVD_DXVA_BUF_SIZE__PIC_SIZE__SHIFT 0x0
+#define UVD_DXVA_BUF_SIZE__MB_SIZE__SHIFT 0x10
+#define UVD_DXVA_BUF_SIZE__PIC_SIZE_MASK 0x0000FFFFL
+#define UVD_DXVA_BUF_SIZE__MB_SIZE_MASK 0xFFFF0000L
+//UVD_SCRATCH_NP
+#define UVD_SCRATCH_NP__DATA__SHIFT 0x0
+#define UVD_SCRATCH_NP__DATA_MASK 0xFFFFFFFFL
+//UVD_CLK_SWT_HANDSHAKE
+#define UVD_CLK_SWT_HANDSHAKE__CLK_SWT_TYPE__SHIFT 0x0
+#define UVD_CLK_SWT_HANDSHAKE__CLK_DOMAIN_SWT__SHIFT 0x8
+#define UVD_CLK_SWT_HANDSHAKE__CLK_SWT_TYPE_MASK 0x00000003L
+#define UVD_CLK_SWT_HANDSHAKE__CLK_DOMAIN_SWT_MASK 0x00000300L
+//UVD_VERSION
+#define UVD_VERSION__MINOR_VERSION__SHIFT 0x0
+#define UVD_VERSION__MAJOR_VERSION__SHIFT 0x10
+#define UVD_VERSION__INSTANCE_ID__SHIFT 0x1c
+#define UVD_VERSION__MINOR_VERSION_MASK 0x0000FFFFL
+#define UVD_VERSION__MAJOR_VERSION_MASK 0x0FFF0000L
+#define UVD_VERSION__INSTANCE_ID_MASK 0xF0000000L
+//UVD_GP_SCRATCH0
+#define UVD_GP_SCRATCH0__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH0__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH1
+#define UVD_GP_SCRATCH1__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH1__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH2
+#define UVD_GP_SCRATCH2__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH2__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH3
+#define UVD_GP_SCRATCH3__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH3__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH4
+#define UVD_GP_SCRATCH4__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH4__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH5
+#define UVD_GP_SCRATCH5__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH5__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH6
+#define UVD_GP_SCRATCH6__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH6__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH7
+#define UVD_GP_SCRATCH7__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH7__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH8
+#define UVD_GP_SCRATCH8__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH8__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH9
+#define UVD_GP_SCRATCH9__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH9__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH10
+#define UVD_GP_SCRATCH10__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH10__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH11
+#define UVD_GP_SCRATCH11__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH11__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH12
+#define UVD_GP_SCRATCH12__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH12__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH13
+#define UVD_GP_SCRATCH13__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH13__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH14
+#define UVD_GP_SCRATCH14__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH14__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH15
+#define UVD_GP_SCRATCH15__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH15__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH16
+#define UVD_GP_SCRATCH16__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH16__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH17
+#define UVD_GP_SCRATCH17__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH17__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH18
+#define UVD_GP_SCRATCH18__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH18__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH19
+#define UVD_GP_SCRATCH19__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH19__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH20
+#define UVD_GP_SCRATCH20__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH20__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH21
+#define UVD_GP_SCRATCH21__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH21__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH22
+#define UVD_GP_SCRATCH22__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH22__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH23
+#define UVD_GP_SCRATCH23__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH23__DATA_MASK 0xFFFFFFFFL
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/atombios.h b/drivers/gpu/drm/amd/include/atombios.h
index c1d7b1d0b952..47eb84598b96 100644
--- a/drivers/gpu/drm/amd/include/atombios.h
+++ b/drivers/gpu/drm/amd/include/atombios.h
@@ -1987,9 +1987,9 @@ typedef struct _PIXEL_CLOCK_PARAMETERS_V6
#define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c
#define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00
#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04
-#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6 0x08 //for V6, the correct defintion for 36bpp should be 2 for 36bpp(2:1)
+#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6 0x08 //for V6, the correct definition for 36bpp should be 2 for 36bpp(2:1)
#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08
-#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6 0x04 //for V6, the correct defintion for 30bpp should be 1 for 36bpp(5:4)
+#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6 0x04 //for V6, the correct definition for 30bpp should be 1 for 36bpp(5:4)
#define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c
#define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10
#define PIXEL_CLOCK_V6_MISC_GEN_DPREFCLK 0x40
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h
index 3cb8d4c5c1a3..f2564ba21c0b 100644
--- a/drivers/gpu/drm/amd/include/atomfirmware.h
+++ b/drivers/gpu/drm/amd/include/atomfirmware.h
@@ -180,6 +180,7 @@ enum atom_voltage_type
enum atom_dgpu_vram_type {
ATOM_DGPU_VRAM_TYPE_GDDR5 = 0x50,
ATOM_DGPU_VRAM_TYPE_HBM2 = 0x60,
+ ATOM_DGPU_VRAM_TYPE_HBM2E = 0x61,
ATOM_DGPU_VRAM_TYPE_GDDR6 = 0x70,
};
@@ -596,7 +597,10 @@ struct atom_firmware_info_v3_4 {
uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt
uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt
uint32_t fw_reserved_size_in_kb; // VBIOS reserved extra fw size in unit of kb.
- uint32_t reserved[5];
+ uint32_t pspbl_init_done_reg_addr;
+ uint32_t pspbl_init_done_value;
+ uint32_t pspbl_init_done_check_timeout; // time out in unit of us when polling pspbl init done
+ uint32_t reserved[2];
};
/*
@@ -977,6 +981,40 @@ struct atom_display_controller_info_v4_2
uint8_t reserved3[8];
};
+struct atom_display_controller_info_v4_3
+{
+ struct atom_common_table_header table_header;
+ uint32_t display_caps;
+ uint32_t bootup_dispclk_10khz;
+ uint16_t dce_refclk_10khz;
+ uint16_t i2c_engine_refclk_10khz;
+ uint16_t dvi_ss_percentage; // in unit of 0.001%
+ uint16_t dvi_ss_rate_10hz;
+ uint16_t hdmi_ss_percentage; // in unit of 0.001%
+ uint16_t hdmi_ss_rate_10hz;
+ uint16_t dp_ss_percentage; // in unit of 0.001%
+ uint16_t dp_ss_rate_10hz;
+ uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
+ uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
+ uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
+ uint8_t ss_reserved;
+ uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
+ uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
+ uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
+ uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
+ uint16_t dpphy_refclk_10khz;
+ uint16_t reserved2;
+ uint8_t dcnip_min_ver;
+ uint8_t dcnip_max_ver;
+ uint8_t max_disp_pipe_num;
+ uint8_t max_vbios_active_disp_pipe_num;
+ uint8_t max_ppll_num;
+ uint8_t max_disp_phy_num;
+ uint8_t max_aux_pairs;
+ uint8_t remotedisplayconfig;
+ uint8_t reserved3[8];
+};
+
struct atom_display_controller_info_v4_4 {
struct atom_common_table_header table_header;
uint32_t display_caps;
@@ -1039,7 +1077,9 @@ enum dce_info_caps_def
DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 =0x04,
// only for VBIOS
DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING =0x08,
-
+ // only for VBIOS
+ DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE =0x20,
+ DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE = 0x40,
};
/*
@@ -1528,6 +1568,47 @@ struct atom_gfx_info_v2_4
uint32_t sram_custom_rm_fuses_val;
};
+struct atom_gfx_info_v2_7 {
+ struct atom_common_table_header table_header;
+ uint8_t gfxip_min_ver;
+ uint8_t gfxip_max_ver;
+ uint8_t max_shader_engines;
+ uint8_t reserved;
+ uint8_t max_cu_per_sh;
+ uint8_t max_sh_per_se;
+ uint8_t max_backends_per_se;
+ uint8_t max_texture_channel_caches;
+ uint32_t regaddr_cp_dma_src_addr;
+ uint32_t regaddr_cp_dma_src_addr_hi;
+ uint32_t regaddr_cp_dma_dst_addr;
+ uint32_t regaddr_cp_dma_dst_addr_hi;
+ uint32_t regaddr_cp_dma_command;
+ uint32_t regaddr_cp_status;
+ uint32_t regaddr_rlc_gpu_clock_32;
+ uint32_t rlc_gpu_timer_refclk;
+ uint8_t active_cu_per_sh;
+ uint8_t active_rb_per_se;
+ uint16_t gcgoldenoffset;
+ uint16_t gc_num_gprs;
+ uint16_t gc_gsprim_buff_depth;
+ uint16_t gc_parameter_cache_depth;
+ uint16_t gc_wave_size;
+ uint16_t gc_max_waves_per_simd;
+ uint16_t gc_lds_size;
+ uint8_t gc_num_max_gs_thds;
+ uint8_t gc_gs_table_depth;
+ uint8_t gc_double_offchip_lds_buffer;
+ uint8_t gc_max_scratch_slots_per_cu;
+ uint32_t sram_rm_fuses_val;
+ uint32_t sram_custom_rm_fuses_val;
+ uint8_t cut_cu;
+ uint8_t active_cu_total;
+ uint8_t cu_reserved[2];
+ uint32_t gc_config;
+ uint8_t inactive_cu_per_se[8];
+ uint32_t reserved2[6];
+};
+
/*
***************************************************************************
Data Table smu_info structure
@@ -2332,6 +2413,59 @@ struct atom_smc_dpm_info_v4_9
};
+struct atom_smc_dpm_info_v4_10
+{
+ struct atom_common_table_header table_header;
+
+ // SECTION: BOARD PARAMETERS
+ // Telemetry Settings
+ uint16_t GfxMaxCurrent; // in Amps
+ uint8_t GfxOffset; // in Amps
+ uint8_t Padding_TelemetryGfx;
+
+ uint16_t SocMaxCurrent; // in Amps
+ uint8_t SocOffset; // in Amps
+ uint8_t Padding_TelemetrySoc;
+
+ uint16_t MemMaxCurrent; // in Amps
+ uint8_t MemOffset; // in Amps
+ uint8_t Padding_TelemetryMem;
+
+ uint16_t BoardMaxCurrent; // in Amps
+ uint8_t BoardOffset; // in Amps
+ uint8_t Padding_TelemetryBoardInput;
+
+ // Platform input telemetry voltage coefficient
+ uint32_t BoardVoltageCoeffA; // decode by /1000
+ uint32_t BoardVoltageCoeffB; // decode by /1000
+
+ // GPIO Settings
+ uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
+ uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
+ uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
+ uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
+
+ // UCLK Spread Spectrum
+ uint8_t UclkSpreadEnabled; // on or off
+ uint8_t UclkSpreadPercent; // Q4.4
+ uint16_t UclkSpreadFreq; // kHz
+
+ // FCLK Spread Spectrum
+ uint8_t FclkSpreadEnabled; // on or off
+ uint8_t FclkSpreadPercent; // Q4.4
+ uint16_t FclkSpreadFreq; // kHz
+
+ // I2C Controller Structure
+ struct smudpm_i2c_controller_config_v3 I2cControllers[8];
+
+ // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence
+ uint8_t GpioI2cScl; // Serial Clock
+ uint8_t GpioI2cSda; // Serial Data
+ uint16_t spare5;
+
+ uint32_t reserved[16];
+};
+
/*
***************************************************************************
Data Table asic_profiling_info structure
@@ -2537,7 +2671,18 @@ struct atom_umc_info_v3_3
uint32_t pstate_uclk_10khz[4];
uint16_t umcgoldenoffset;
uint16_t densitygoldenoffset;
- uint32_t reserved[4];
+ uint32_t umc_config1;
+ uint32_t bist_data_startaddr;
+ uint32_t reserved[2];
+};
+
+enum atom_umc_config1_def {
+ UMC_CONFIG1__ENABLE_PSTATE_PHASE_STORE_TRAIN = 0x00000001,
+ UMC_CONFIG1__ENABLE_AUTO_FRAMING = 0x00000002,
+ UMC_CONFIG1__ENABLE_RESTORE_BIST_DATA = 0x00000004,
+ UMC_CONFIG1__DISABLE_STROBE_MODE = 0x00000008,
+ UMC_CONFIG1__DEBUG_DATA_PARITY_EN = 0x00000010,
+ UMC_CONFIG1__ENABLE_ECC_CAPABLE = 0x00010000,
};
/*
@@ -2789,6 +2934,22 @@ struct atom_vram_info_header_v2_5 {
struct atom_vram_module_v11 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
};
+struct atom_vram_info_header_v2_6 {
+ struct atom_common_table_header table_header;
+ uint16_t mem_adjust_tbloffset;
+ uint16_t mem_clk_patch_tbloffset;
+ uint16_t mc_adjust_pertile_tbloffset;
+ uint16_t mc_phyinit_tbloffset;
+ uint16_t dram_data_remap_tbloffset;
+ uint16_t tmrs_seq_offset;
+ uint16_t post_ucode_init_offset;
+ uint16_t vram_rsd2;
+ uint8_t vram_module_num;
+ uint8_t umcip_min_ver;
+ uint8_t umcip_max_ver;
+ uint8_t mc_phy_tile_num;
+ struct atom_vram_module_v9 vram_module[16];
+};
/*
***************************************************************************
Data Table voltageobject_info structure
@@ -3175,6 +3336,47 @@ enum atom_smu11_syspll3_1_clock_id {
SMU11_SYSPLL3_1_LCLK_ID = 2, // LCLK
};
+enum atom_smu12_syspll_id {
+ SMU12_SYSPLL0_ID = 0,
+ SMU12_SYSPLL1_ID = 1,
+ SMU12_SYSPLL2_ID = 2,
+ SMU12_SYSPLL3_0_ID = 3,
+ SMU12_SYSPLL3_1_ID = 4,
+};
+
+enum atom_smu12_syspll0_clock_id {
+ SMU12_SYSPLL0_SMNCLK_ID = 0, // SOCCLK
+ SMU12_SYSPLL0_SOCCLK_ID = 1, // SOCCLK
+ SMU12_SYSPLL0_MP0CLK_ID = 2, // MP0CLK
+ SMU12_SYSPLL0_MP1CLK_ID = 3, // MP1CLK
+ SMU12_SYSPLL0_MP2CLK_ID = 4, // MP2CLK
+ SMU12_SYSPLL0_VCLK_ID = 5, // VCLK
+ SMU12_SYSPLL0_LCLK_ID = 6, // LCLK
+ SMU12_SYSPLL0_DCLK_ID = 7, // DCLK
+ SMU12_SYSPLL0_ACLK_ID = 8, // ACLK
+ SMU12_SYSPLL0_ISPCLK_ID = 9, // ISPCLK
+ SMU12_SYSPLL0_SHUBCLK_ID = 10, // SHUBCLK
+};
+
+enum atom_smu12_syspll1_clock_id {
+ SMU12_SYSPLL1_DISPCLK_ID = 0, // DISPCLK
+ SMU12_SYSPLL1_DPPCLK_ID = 1, // DPPCLK
+ SMU12_SYSPLL1_DPREFCLK_ID = 2, // DPREFCLK
+ SMU12_SYSPLL1_DCFCLK_ID = 3, // DCFCLK
+};
+
+enum atom_smu12_syspll2_clock_id {
+ SMU12_SYSPLL2_Pre_GFXCLK_ID = 0, // Pre_GFXCLK
+};
+
+enum atom_smu12_syspll3_0_clock_id {
+ SMU12_SYSPLL3_0_FCLK_ID = 0, // FCLK
+};
+
+enum atom_smu12_syspll3_1_clock_id {
+ SMU12_SYSPLL3_1_UMCCLK_ID = 0, // UMCCLK
+};
+
struct atom_get_smu_clock_info_output_parameters_v3_1
{
union {
diff --git a/drivers/gpu/drm/amd/include/ivsrcid/dcn/irqsrcs_dcn_1_0.h b/drivers/gpu/drm/amd/include/ivsrcid/dcn/irqsrcs_dcn_1_0.h
index ac9fa3a9bd07..754170a86ea4 100644
--- a/drivers/gpu/drm/amd/include/ivsrcid/dcn/irqsrcs_dcn_1_0.h
+++ b/drivers/gpu/drm/amd/include/ivsrcid/dcn/irqsrcs_dcn_1_0.h
@@ -1130,5 +1130,9 @@
#define DCN_1_0__SRCID__HUBP6_FLIP_AWAY_INTERRUPT 0x63 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP6_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse
#define DCN_1_0__SRCID__HUBP7_FLIP_AWAY_INTERRUPT 0x64 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP7_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse
+#define DCN_1_0__SRCID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT 0x68
+#define DCN_1_0__CTXID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT 6
+#define DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT 0x68 // DMCUB_IHC_outbox1_ready_int IHC_DMCUB_outbox1_ready_int_ack DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE24 Level/Pulse
+#define DCN_1_0__CTXID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT 8
#endif // __IRQSRCS_DCN_1_0_H__
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index a41875ac5dfb..353468667036 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -48,6 +48,7 @@ enum amd_dpm_forced_level {
AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
+ AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200,
};
enum amd_pm_state_type {
@@ -95,10 +96,14 @@ enum pp_clock_type {
PP_SOCCLK,
PP_FCLK,
PP_DCEFCLK,
+ PP_VCLK,
+ PP_DCLK,
OD_SCLK,
OD_MCLK,
OD_VDDC_CURVE,
OD_RANGE,
+ OD_VDDGFX_OFFSET,
+ OD_CCLK,
};
enum amd_pp_sensors {
@@ -226,6 +231,8 @@ enum pp_df_cstate {
#define XGMI_MODE_PSTATE_D3 0
#define XGMI_MODE_PSTATE_D0 1
+#define NUM_HBM_INSTANCES 4
+
struct seq_file;
enum amd_pp_clock_type;
struct amd_pp_simple_clock_info;
@@ -235,6 +242,9 @@ struct pp_display_clock_request;
struct pp_clock_levels_with_voltage;
struct pp_clock_levels_with_latency;
struct amd_pp_clocks;
+struct pp_smu_wm_range_sets;
+struct pp_smu_nv_clock_table;
+struct dpm_clocks;
struct amd_pm_funcs {
/* export for dpm on ci and si */
@@ -281,7 +291,8 @@ struct amd_pm_funcs {
uint32_t block_type, bool gate);
int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
int (*set_power_limit)(void *handle, uint32_t n);
- int (*get_power_limit)(void *handle, uint32_t *limit, bool default_limit);
+ int (*get_power_limit)(void *handle, uint32_t *limit, uint32_t *max_limit,
+ bool default_limit);
int (*get_power_profile_mode)(void *handle, char *buf);
int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size);
@@ -328,6 +339,17 @@ struct amd_pm_funcs {
int (*set_df_cstate)(void *handle, enum pp_df_cstate state);
int (*set_xgmi_pstate)(void *handle, uint32_t pstate);
ssize_t (*get_gpu_metrics)(void *handle, void **table);
+ int (*set_watermarks_for_clock_ranges)(void *handle,
+ struct pp_smu_wm_range_sets *ranges);
+ int (*display_disable_memory_clock_switch)(void *handle,
+ bool disable_memory_clock_switch);
+ int (*get_max_sustainable_clocks_by_dc)(void *handle,
+ struct pp_smu_nv_clock_table *max_clocks);
+ int (*get_uclk_dpm_states)(void *handle,
+ unsigned int *clock_values_in_khz,
+ unsigned int *num_states);
+ int (*get_dpm_clock_table)(void *handle,
+ struct dpm_clocks *clock_table);
};
struct metrics_table_header {
@@ -336,6 +358,10 @@ struct metrics_table_header {
uint8_t content_revision;
};
+/*
+ * gpu_metrics_v1_0 is not recommended as it's not naturally aligned.
+ * Use gpu_metrics_v1_1 or later instead.
+ */
struct gpu_metrics_v1_0 {
struct metrics_table_header common_header;
@@ -388,6 +414,69 @@ struct gpu_metrics_v1_0 {
uint8_t pcie_link_speed; // in 0.1 GT/s
};
+struct gpu_metrics_v1_1 {
+ struct metrics_table_header common_header;
+
+ /* Temperature */
+ uint16_t temperature_edge;
+ uint16_t temperature_hotspot;
+ uint16_t temperature_mem;
+ uint16_t temperature_vrgfx;
+ uint16_t temperature_vrsoc;
+ uint16_t temperature_vrmem;
+
+ /* Utilization */
+ uint16_t average_gfx_activity;
+ uint16_t average_umc_activity; // memory controller
+ uint16_t average_mm_activity; // UVD or VCN
+
+ /* Power/Energy */
+ uint16_t average_socket_power;
+ uint64_t energy_accumulator;
+
+ /* Driver attached timestamp (in ns) */
+ uint64_t system_clock_counter;
+
+ /* Average clocks */
+ uint16_t average_gfxclk_frequency;
+ uint16_t average_socclk_frequency;
+ uint16_t average_uclk_frequency;
+ uint16_t average_vclk0_frequency;
+ uint16_t average_dclk0_frequency;
+ uint16_t average_vclk1_frequency;
+ uint16_t average_dclk1_frequency;
+
+ /* Current clocks */
+ uint16_t current_gfxclk;
+ uint16_t current_socclk;
+ uint16_t current_uclk;
+ uint16_t current_vclk0;
+ uint16_t current_dclk0;
+ uint16_t current_vclk1;
+ uint16_t current_dclk1;
+
+ /* Throttle status */
+ uint32_t throttle_status;
+
+ /* Fans */
+ uint16_t current_fan_speed;
+
+ /* Link width/speed */
+ uint16_t pcie_link_width;
+ uint16_t pcie_link_speed; // in 0.1 GT/s
+
+ uint16_t padding;
+
+ uint32_t gfx_activity_acc;
+ uint32_t mem_activity_acc;
+
+ uint16_t temperature_hbm[NUM_HBM_INSTANCES];
+};
+
+/*
+ * gpu_metrics_v2_0 is not recommended as it's not naturally aligned.
+ * Use gpu_metrics_v2_1 or later instead.
+ */
struct gpu_metrics_v2_0 {
struct metrics_table_header common_header;
@@ -438,4 +527,54 @@ struct gpu_metrics_v2_0 {
uint16_t padding;
};
+struct gpu_metrics_v2_1 {
+ struct metrics_table_header common_header;
+
+ /* Temperature */
+ uint16_t temperature_gfx; // gfx temperature on APUs
+ uint16_t temperature_soc; // soc temperature on APUs
+ uint16_t temperature_core[8]; // CPU core temperature on APUs
+ uint16_t temperature_l3[2];
+
+ /* Utilization */
+ uint16_t average_gfx_activity;
+ uint16_t average_mm_activity; // UVD or VCN
+
+ /* Driver attached timestamp (in ns) */
+ uint64_t system_clock_counter;
+
+ /* Power/Energy */
+ uint16_t average_socket_power; // dGPU + APU power on A + A platform
+ uint16_t average_cpu_power;
+ uint16_t average_soc_power;
+ uint16_t average_gfx_power;
+ uint16_t average_core_power[8]; // CPU core power on APUs
+
+ /* Average clocks */
+ uint16_t average_gfxclk_frequency;
+ uint16_t average_socclk_frequency;
+ uint16_t average_uclk_frequency;
+ uint16_t average_fclk_frequency;
+ uint16_t average_vclk_frequency;
+ uint16_t average_dclk_frequency;
+
+ /* Current clocks */
+ uint16_t current_gfxclk;
+ uint16_t current_socclk;
+ uint16_t current_uclk;
+ uint16_t current_fclk;
+ uint16_t current_vclk;
+ uint16_t current_dclk;
+ uint16_t current_coreclk[8]; // CPU core clocks
+ uint16_t current_l3clk[2];
+
+ /* Throttle status */
+ uint32_t throttle_status;
+
+ /* Fans */
+ uint16_t fan_pwm;
+
+ uint16_t padding[3];
+};
+
#endif
diff --git a/drivers/gpu/drm/amd/include/soc15_ih_clientid.h b/drivers/gpu/drm/amd/include/soc15_ih_clientid.h
index fb67bb55ed79..1ace2cff0883 100644
--- a/drivers/gpu/drm/amd/include/soc15_ih_clientid.h
+++ b/drivers/gpu/drm/amd/include/soc15_ih_clientid.h
@@ -24,8 +24,10 @@
#ifndef __SOC15_IH_CLIENTID_H__
#define __SOC15_IH_CLIENTID_H__
- /*
- * vega10+ IH clients
+/*
+ * Vega10+ IH clients
+ * Whenever this structure is updated, which should not happen, make sure
+ * soc15_ih_clientid_name in the below is also updated accordingly.
*/
enum soc15_ih_clientid {
SOC15_IH_CLIENTID_IH = 0x00,
@@ -54,6 +56,7 @@ enum soc15_ih_clientid {
SOC15_IH_CLIENTID_DF = 0x17,
SOC15_IH_CLIENTID_VCE1 = 0x18,
SOC15_IH_CLIENTID_PWR = 0x19,
+ SOC15_IH_CLIENTID_RESERVED = 0x1a,
SOC15_IH_CLIENTID_UTCL2 = 0x1b,
SOC15_IH_CLIENTID_EA = 0x1c,
SOC15_IH_CLIENTID_UTCL2LOG = 0x1d,
@@ -74,6 +77,8 @@ enum soc15_ih_clientid {
SOC15_IH_CLIENTID_VMC1 = SOC15_IH_CLIENTID_PCIE0,
};
+extern const char *soc15_ih_clientid_name[];
+
#endif
diff --git a/drivers/gpu/drm/amd/include/vi_structs.h b/drivers/gpu/drm/amd/include/vi_structs.h
index c17613287cd0..50ebf885fa7c 100644
--- a/drivers/gpu/drm/amd/include/vi_structs.h
+++ b/drivers/gpu/drm/amd/include/vi_structs.h
@@ -397,22 +397,22 @@ struct vi_mqd {
uint32_t reserved60;
uint32_t reserved61;
uint32_t reserved62;
- uint32_t reserved63;
- uint32_t reserved64;
- uint32_t reserved65;
- uint32_t reserved66;
- uint32_t reserved67;
- uint32_t reserved68;
- uint32_t reserved69;
- uint32_t reserved70;
- uint32_t reserved71;
- uint32_t reserved72;
- uint32_t reserved73;
- uint32_t reserved74;
- uint32_t reserved75;
- uint32_t reserved76;
- uint32_t reserved77;
- uint32_t reserved78;
+ uint32_t queue_doorbell_id0;
+ uint32_t queue_doorbell_id1;
+ uint32_t queue_doorbell_id2;
+ uint32_t queue_doorbell_id3;
+ uint32_t queue_doorbell_id4;
+ uint32_t queue_doorbell_id5;
+ uint32_t queue_doorbell_id6;
+ uint32_t queue_doorbell_id7;
+ uint32_t queue_doorbell_id8;
+ uint32_t queue_doorbell_id9;
+ uint32_t queue_doorbell_id10;
+ uint32_t queue_doorbell_id11;
+ uint32_t queue_doorbell_id12;
+ uint32_t queue_doorbell_id13;
+ uint32_t queue_doorbell_id14;
+ uint32_t queue_doorbell_id15;
uint32_t reserved_t[256];
};