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-rw-r--r--drivers/net/wireless/ath/ath10k/ahb.c20
-rw-r--r--drivers/net/wireless/ath/ath10k/core.c12
-rw-r--r--drivers/net/wireless/ath/ath10k/core.h3
-rw-r--r--drivers/net/wireless/ath/ath10k/debug.c4
-rw-r--r--drivers/net/wireless/ath/ath10k/htt.h6
-rw-r--r--drivers/net/wireless/ath/ath10k/mac.c13
-rw-r--r--drivers/net/wireless/ath/ath10k/snoc.c8
-rw-r--r--drivers/net/wireless/ath/ath10k/wmi.c34
-rw-r--r--drivers/net/wireless/ath/ath10k/wmi.h2
-rw-r--r--drivers/net/wireless/ath/ath11k/ahb.c8
-rw-r--r--drivers/net/wireless/ath/ath11k/ce.c4
-rw-r--r--drivers/net/wireless/ath/ath11k/core.c89
-rw-r--r--drivers/net/wireless/ath/ath11k/core.h16
-rw-r--r--drivers/net/wireless/ath/ath11k/debug.c2
-rw-r--r--drivers/net/wireless/ath/ath11k/debug.h49
-rw-r--r--drivers/net/wireless/ath/ath11k/debugfs_htt_stats.c114
-rw-r--r--drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h43
-rw-r--r--drivers/net/wireless/ath/ath11k/dp_rx.c8
-rw-r--r--drivers/net/wireless/ath/ath11k/dp_tx.c12
-rw-r--r--drivers/net/wireless/ath/ath11k/hal.c10
-rw-r--r--drivers/net/wireless/ath/ath11k/hal_rx.c24
-rw-r--r--drivers/net/wireless/ath/ath11k/htc.c42
-rw-r--r--drivers/net/wireless/ath/ath11k/hw.c5
-rw-r--r--drivers/net/wireless/ath/ath11k/hw.h1
-rw-r--r--drivers/net/wireless/ath/ath11k/mac.c539
-rw-r--r--drivers/net/wireless/ath/ath11k/mhi.c6
-rw-r--r--drivers/net/wireless/ath/ath11k/pci.c25
-rw-r--r--drivers/net/wireless/ath/ath11k/pcic.c6
-rw-r--r--drivers/net/wireless/ath/ath11k/peer.c4
-rw-r--r--drivers/net/wireless/ath/ath11k/qmi.c73
-rw-r--r--drivers/net/wireless/ath/ath11k/reg.c4
-rw-r--r--drivers/net/wireless/ath/ath11k/testmode.c387
-rw-r--r--drivers/net/wireless/ath/ath11k/testmode.h6
-rw-r--r--drivers/net/wireless/ath/ath11k/testmode_i.h18
-rw-r--r--drivers/net/wireless/ath/ath11k/wmi.c628
-rw-r--r--drivers/net/wireless/ath/ath11k/wmi.h70
-rw-r--r--drivers/net/wireless/ath/ath11k/wow.c3
-rw-r--r--drivers/net/wireless/ath/ath12k/core.c2
-rw-r--r--drivers/net/wireless/ath/ath12k/core.h1
-rw-r--r--drivers/net/wireless/ath/ath12k/dp_rx.c27
-rw-r--r--drivers/net/wireless/ath/ath12k/hal.c16
-rw-r--r--drivers/net/wireless/ath/ath12k/hal.h2
-rw-r--r--drivers/net/wireless/ath/ath12k/hw.c6
-rw-r--r--drivers/net/wireless/ath/ath12k/hw.h2
-rw-r--r--drivers/net/wireless/ath/ath12k/mac.c51
-rw-r--r--drivers/net/wireless/ath/ath12k/pci.c14
-rw-r--r--drivers/net/wireless/ath/ath12k/qmi.c6
-rw-r--r--drivers/net/wireless/ath/ath12k/qmi.h1
-rw-r--r--drivers/net/wireless/ath/ath12k/wmi.c103
-rw-r--r--drivers/net/wireless/ath/ath12k/wmi.h10
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_hw.c27
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_hst.c8
-rw-r--r--drivers/net/wireless/ath/ath9k/main.c11
-rw-r--r--drivers/net/wireless/ath/ath9k/wmi.c4
-rw-r--r--drivers/net/wireless/ath/wil6210/fw.h4
-rw-r--r--drivers/net/wireless/ath/wil6210/wmi.h2
-rw-r--r--drivers/net/wireless/atmel/Kconfig2
-rw-r--r--drivers/net/wireless/atmel/atmel_cs.c13
-rw-r--r--drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c6
-rw-r--r--drivers/net/wireless/broadcom/brcm80211/brcmfmac/tracepoint.h7
-rw-r--r--drivers/net/wireless/broadcom/brcm80211/brcmfmac/wcc/core.c4
-rw-r--r--drivers/net/wireless/broadcom/brcm80211/brcmsmac/brcms_trace_brcmsmac_msg.h8
-rw-r--r--drivers/net/wireless/broadcom/brcm80211/brcmutil/utils.c4
-rw-r--r--drivers/net/wireless/intel/iwlwifi/Makefile1
-rw-r--r--drivers/net/wireless/intel/iwlwifi/cfg/1000.c10
-rw-r--r--drivers/net/wireless/intel/iwlwifi/cfg/2000.c18
-rw-r--r--drivers/net/wireless/intel/iwlwifi/cfg/22000.c832
-rw-r--r--drivers/net/wireless/intel/iwlwifi/cfg/5000.c10
-rw-r--r--drivers/net/wireless/intel/iwlwifi/cfg/6000.c18
-rw-r--r--drivers/net/wireless/intel/iwlwifi/cfg/7000.c22
-rw-r--r--drivers/net/wireless/intel/iwlwifi/cfg/8000.c10
-rw-r--r--drivers/net/wireless/intel/iwlwifi/cfg/9000.c10
-rw-r--r--drivers/net/wireless/intel/iwlwifi/cfg/ax210.c301
-rw-r--r--drivers/net/wireless/intel/iwlwifi/cfg/bz.c183
-rw-r--r--drivers/net/wireless/intel/iwlwifi/cfg/sc.c166
-rw-r--r--drivers/net/wireless/intel/iwlwifi/dvm/rs.c43
-rw-r--r--drivers/net/wireless/intel/iwlwifi/fw/acpi.c121
-rw-r--r--drivers/net/wireless/intel/iwlwifi/fw/acpi.h41
-rw-r--r--drivers/net/wireless/intel/iwlwifi/fw/api/binding.h14
-rw-r--r--drivers/net/wireless/intel/iwlwifi/fw/api/commands.h23
-rw-r--r--drivers/net/wireless/intel/iwlwifi/fw/api/config.h15
-rw-r--r--drivers/net/wireless/intel/iwlwifi/fw/api/context.h13
-rw-r--r--drivers/net/wireless/intel/iwlwifi/fw/api/d3.h6
-rw-r--r--drivers/net/wireless/intel/iwlwifi/fw/api/datapath.h6
-rw-r--r--drivers/net/wireless/intel/iwlwifi/fw/api/location.h16
-rw-r--r--drivers/net/wireless/intel/iwlwifi/fw/api/mac-cfg.h65
-rw-r--r--drivers/net/wireless/intel/iwlwifi/fw/api/mac.h24
-rw-r--r--drivers/net/wireless/intel/iwlwifi/fw/api/nvm-reg.h46
-rw-r--r--drivers/net/wireless/intel/iwlwifi/fw/api/offload.h3
-rw-r--r--drivers/net/wireless/intel/iwlwifi/fw/api/phy-ctxt.h6
-rw-r--r--drivers/net/wireless/intel/iwlwifi/fw/api/phy.h10
-rw-r--r--drivers/net/wireless/intel/iwlwifi/fw/api/power.h2
-rw-r--r--drivers/net/wireless/intel/iwlwifi/fw/api/rs.h2
-rw-r--r--drivers/net/wireless/intel/iwlwifi/fw/api/rx.h6
-rw-r--r--drivers/net/wireless/intel/iwlwifi/fw/api/scan.h41
-rw-r--r--drivers/net/wireless/intel/iwlwifi/fw/api/time-event.h7
-rw-r--r--drivers/net/wireless/intel/iwlwifi/fw/api/tx.h13
-rw-r--r--drivers/net/wireless/intel/iwlwifi/fw/dbg.c72
-rw-r--r--drivers/net/wireless/intel/iwlwifi/fw/dbg.h18
-rw-r--r--drivers/net/wireless/intel/iwlwifi/fw/debugfs.c35
-rw-r--r--drivers/net/wireless/intel/iwlwifi/fw/dump.c15
-rw-r--r--drivers/net/wireless/intel/iwlwifi/fw/file.h6
-rw-r--r--drivers/net/wireless/intel/iwlwifi/fw/pnvm.c234
-rw-r--r--drivers/net/wireless/intel/iwlwifi/fw/pnvm.h27
-rw-r--r--drivers/net/wireless/intel/iwlwifi/fw/runtime.h6
-rw-r--r--drivers/net/wireless/intel/iwlwifi/fw/uefi.c272
-rw-r--r--drivers/net/wireless/intel/iwlwifi/fw/uefi.h47
-rw-r--r--drivers/net/wireless/intel/iwlwifi/iwl-config.h69
-rw-r--r--drivers/net/wireless/intel/iwlwifi/iwl-context-info-gen3.h32
-rw-r--r--drivers/net/wireless/intel/iwlwifi/iwl-context-info.h5
-rw-r--r--drivers/net/wireless/intel/iwlwifi/iwl-dbg-tlv.c56
-rw-r--r--drivers/net/wireless/intel/iwlwifi/iwl-drv.c75
-rw-r--r--drivers/net/wireless/intel/iwlwifi/iwl-drv.h6
-rw-r--r--drivers/net/wireless/intel/iwlwifi/iwl-io.c4
-rw-r--r--drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c155
-rw-r--r--drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.h4
-rw-r--r--drivers/net/wireless/intel/iwlwifi/iwl-prph.h6
-rw-r--r--drivers/net/wireless/intel/iwlwifi/iwl-trans.h108
-rw-r--r--drivers/net/wireless/intel/iwlwifi/mei/main.c5
-rw-r--r--drivers/net/wireless/intel/iwlwifi/mvm/binding.c10
-rw-r--r--drivers/net/wireless/intel/iwlwifi/mvm/constants.h6
-rw-r--r--drivers/net/wireless/intel/iwlwifi/mvm/d3.c420
-rw-r--r--drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c6
-rw-r--r--drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c202
-rw-r--r--drivers/net/wireless/intel/iwlwifi/mvm/ftm-initiator.c48
-rw-r--r--drivers/net/wireless/intel/iwlwifi/mvm/ftm-responder.c23
-rw-r--r--drivers/net/wireless/intel/iwlwifi/mvm/fw.c93
-rw-r--r--drivers/net/wireless/intel/iwlwifi/mvm/link.c37
-rw-r--r--drivers/net/wireless/intel/iwlwifi/mvm/mac-ctxt.c122
-rw-r--r--drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c200
-rw-r--r--drivers/net/wireless/intel/iwlwifi/mvm/mld-key.c99
-rw-r--r--drivers/net/wireless/intel/iwlwifi/mvm/mld-mac.c26
-rw-r--r--drivers/net/wireless/intel/iwlwifi/mvm/mld-mac80211.c177
-rw-r--r--drivers/net/wireless/intel/iwlwifi/mvm/mld-sta.c28
-rw-r--r--drivers/net/wireless/intel/iwlwifi/mvm/mvm.h105
-rw-r--r--drivers/net/wireless/intel/iwlwifi/mvm/nvm.c63
-rw-r--r--drivers/net/wireless/intel/iwlwifi/mvm/offloading.c4
-rw-r--r--drivers/net/wireless/intel/iwlwifi/mvm/ops.c16
-rw-r--r--drivers/net/wireless/intel/iwlwifi/mvm/phy-ctxt.c15
-rw-r--r--drivers/net/wireless/intel/iwlwifi/mvm/power.c56
-rw-r--r--drivers/net/wireless/intel/iwlwifi/mvm/rs-fw.c77
-rw-r--r--drivers/net/wireless/intel/iwlwifi/mvm/rs.c11
-rw-r--r--drivers/net/wireless/intel/iwlwifi/mvm/rx.c10
-rw-r--r--drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c46
-rw-r--r--drivers/net/wireless/intel/iwlwifi/mvm/scan.c163
-rw-r--r--drivers/net/wireless/intel/iwlwifi/mvm/sf.c5
-rw-r--r--drivers/net/wireless/intel/iwlwifi/mvm/sta.c90
-rw-r--r--drivers/net/wireless/intel/iwlwifi/mvm/sta.h20
-rw-r--r--drivers/net/wireless/intel/iwlwifi/mvm/time-event.c4
-rw-r--r--drivers/net/wireless/intel/iwlwifi/mvm/tx.c150
-rw-r--r--drivers/net/wireless/intel/iwlwifi/mvm/utils.c26
-rw-r--r--drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info-gen3.c273
-rw-r--r--drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info.c8
-rw-r--r--drivers/net/wireless/intel/iwlwifi/pcie/drv.c517
-rw-r--r--drivers/net/wireless/intel/iwlwifi/pcie/internal.h12
-rw-r--r--drivers/net/wireless/intel/iwlwifi/pcie/rx.c31
-rw-r--r--drivers/net/wireless/intel/iwlwifi/pcie/trans-gen2.c13
-rw-r--r--drivers/net/wireless/intel/iwlwifi/pcie/trans.c67
-rw-r--r--drivers/net/wireless/intel/iwlwifi/pcie/tx.c5
-rw-r--r--drivers/net/wireless/intel/iwlwifi/queue/tx.c12
-rw-r--r--drivers/net/wireless/intersil/hostap/Kconfig2
-rw-r--r--drivers/net/wireless/intersil/hostap/hostap_ioctl.c2
-rw-r--r--drivers/net/wireless/intersil/orinoco/orinoco_cs.c13
-rw-r--r--drivers/net/wireless/intersil/orinoco/spectrum_cs.c13
-rw-r--r--drivers/net/wireless/intersil/p54/p54spi.c1
-rw-r--r--drivers/net/wireless/legacy/ray_cs.c33
-rw-r--r--drivers/net/wireless/legacy/wl3501_cs.c16
-rw-r--r--drivers/net/wireless/marvell/mwifiex/11n.h4
-rw-r--r--drivers/net/wireless/marvell/mwifiex/cfg80211.c8
-rw-r--r--drivers/net/wireless/marvell/mwifiex/scan.c6
-rw-r--r--drivers/net/wireless/marvell/mwifiex/wmm.h15
-rw-r--r--drivers/net/wireless/mediatek/mt7601u/debugfs.c2
-rw-r--r--drivers/net/wireless/mediatek/mt7601u/trace.h2
-rw-r--r--drivers/net/wireless/microchip/wilc1000/hif.c8
-rw-r--r--drivers/net/wireless/microchip/wilc1000/hif.h2
-rw-r--r--drivers/net/wireless/microchip/wilc1000/wlan_cfg.h2
-rw-r--r--drivers/net/wireless/microchip/wilc1000/wlan_if.h2
-rw-r--r--drivers/net/wireless/ralink/rt2x00/rt2x00link.c2
-rw-r--r--drivers/net/wireless/realtek/rtl8xxxu/Kconfig3
-rw-r--r--drivers/net/wireless/realtek/rtl8xxxu/Makefile2
-rw-r--r--drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h84
-rw-r--r--drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c3
-rw-r--r--drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188f.c25
-rw-r--r--drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c28
-rw-r--r--drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192f.c2090
-rw-r--r--drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8710b.c37
-rw-r--r--drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c5
-rw-r--r--drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c567
-rw-r--r--drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h52
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/base.c20
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/base.h1
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/core.c10
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/core.h2
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/pci.c7
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c8
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8188ee/led.c40
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8188ee/led.h5
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8188ee/sw.c1
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.c2
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c8
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8192ce/led.c41
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8192ce/led.h5
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8192ce/sw.c1
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.c2
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8192cu/led.c56
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8192cu/led.h6
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8192cu/sw.c2
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.c4
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c8
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8192de/led.c42
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8192de/led.h5
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.c1
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c2
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c8
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8192ee/led.c40
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8192ee/led.h5
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8192ee/sw.c1
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c16
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8192se/led.c42
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8192se/led.h5
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8192se/sw.c1
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c8
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8723ae/led.c42
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8723ae/led.h5
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8723ae/sw.c1
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.c2
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c8
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8723be/led.c42
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8723be/led.h5
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8723be/sw.c1
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c14
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8821ae/led.c60
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8821ae/led.h9
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/rtl8821ae/sw.c1
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/usb.c42
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/wifi.h29
-rw-r--r--drivers/net/wireless/realtek/rtw88/Kconfig11
-rw-r--r--drivers/net/wireless/realtek/rtw88/Makefile3
-rw-r--r--drivers/net/wireless/realtek/rtw88/debug.c59
-rw-r--r--drivers/net/wireless/realtek/rtw88/fw.c68
-rw-r--r--drivers/net/wireless/realtek/rtw88/fw.h13
-rw-r--r--drivers/net/wireless/realtek/rtw88/mac.c6
-rw-r--r--drivers/net/wireless/realtek/rtw88/mac80211.c13
-rw-r--r--drivers/net/wireless/realtek/rtw88/main.c15
-rw-r--r--drivers/net/wireless/realtek/rtw88/main.h1
-rw-r--r--drivers/net/wireless/realtek/rtw88/pci.c5
-rw-r--r--drivers/net/wireless/realtek/rtw88/ps.c3
-rw-r--r--drivers/net/wireless/realtek/rtw88/reg.h2
-rw-r--r--drivers/net/wireless/realtek/rtw88/rtw8723d.c15
-rw-r--r--drivers/net/wireless/realtek/rtw88/rtw8723d.h6
-rw-r--r--drivers/net/wireless/realtek/rtw88/rtw8723ds.c41
-rw-r--r--drivers/net/wireless/realtek/rtw88/sdio.c24
-rw-r--r--drivers/net/wireless/realtek/rtw88/tx.c94
-rw-r--r--drivers/net/wireless/realtek/rtw88/tx.h124
-rw-r--r--drivers/net/wireless/realtek/rtw88/usb.c17
-rw-r--r--drivers/net/wireless/realtek/rtw89/Kconfig14
-rw-r--r--drivers/net/wireless/realtek/rtw89/Makefile12
-rw-r--r--drivers/net/wireless/realtek/rtw89/acpi.c52
-rw-r--r--drivers/net/wireless/realtek/rtw89/acpi.h21
-rw-r--r--drivers/net/wireless/realtek/rtw89/coex.c9
-rw-r--r--drivers/net/wireless/realtek/rtw89/core.c261
-rw-r--r--drivers/net/wireless/realtek/rtw89/core.h217
-rw-r--r--drivers/net/wireless/realtek/rtw89/debug.c60
-rw-r--r--drivers/net/wireless/realtek/rtw89/efuse.c21
-rw-r--r--drivers/net/wireless/realtek/rtw89/efuse.h1
-rw-r--r--drivers/net/wireless/realtek/rtw89/fw.c175
-rw-r--r--drivers/net/wireless/realtek/rtw89/fw.h281
-rw-r--r--drivers/net/wireless/realtek/rtw89/mac.c160
-rw-r--r--drivers/net/wireless/realtek/rtw89/mac.h5
-rw-r--r--drivers/net/wireless/realtek/rtw89/mac80211.c16
-rw-r--r--drivers/net/wireless/realtek/rtw89/pci.c25
-rw-r--r--drivers/net/wireless/realtek/rtw89/pci.h1
-rw-r--r--drivers/net/wireless/realtek/rtw89/phy.c344
-rw-r--r--drivers/net/wireless/realtek/rtw89/phy.h12
-rw-r--r--drivers/net/wireless/realtek/rtw89/reg.h134
-rw-r--r--drivers/net/wireless/realtek/rtw89/regd.c324
-rw-r--r--drivers/net/wireless/realtek/rtw89/rtw8851b.c2442
-rw-r--r--drivers/net/wireless/realtek/rtw89/rtw8851b.h76
-rw-r--r--drivers/net/wireless/realtek/rtw89/rtw8851b_rfk.c3621
-rw-r--r--drivers/net/wireless/realtek/rtw89/rtw8851b_rfk.h28
-rw-r--r--drivers/net/wireless/realtek/rtw89/rtw8851b_table.c252
-rw-r--r--drivers/net/wireless/realtek/rtw89/rtw8851b_table.h2
-rw-r--r--drivers/net/wireless/realtek/rtw89/rtw8851be.c86
-rw-r--r--drivers/net/wireless/realtek/rtw89/rtw8852a.c15
-rw-r--r--drivers/net/wireless/realtek/rtw89/rtw8852a_rfk.c36
-rw-r--r--drivers/net/wireless/realtek/rtw89/rtw8852a_rfk.h1
-rw-r--r--drivers/net/wireless/realtek/rtw89/rtw8852b.c8
-rw-r--r--drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.c8
-rw-r--r--drivers/net/wireless/realtek/rtw89/rtw8852b_table.c2
-rw-r--r--drivers/net/wireless/realtek/rtw89/rtw8852b_table.h2
-rw-r--r--drivers/net/wireless/realtek/rtw89/rtw8852c.c8
-rw-r--r--drivers/net/wireless/realtek/rtw89/rtw8852c_rfk.c11
-rw-r--r--drivers/net/wireless/realtek/rtw89/rtw8852c_table.c27992
-rw-r--r--drivers/net/wireless/realtek/rtw89/rtw8852c_table.h2
-rw-r--r--drivers/net/wireless/realtek/rtw89/ser.c48
-rw-r--r--drivers/net/wireless/realtek/rtw89/txrx.h176
-rw-r--r--drivers/net/wireless/realtek/rtw89/wow.c2
-rw-r--r--drivers/net/wireless/rsi/rsi_91x_sdio.c9
-rw-r--r--drivers/net/wireless/virtual/mac80211_hwsim.c23
299 files changed, 40846 insertions, 9660 deletions
diff --git a/drivers/net/wireless/ath/ath10k/ahb.c b/drivers/net/wireless/ath/ath10k/ahb.c
index f0c615fa5614..4a006fb4d424 100644
--- a/drivers/net/wireless/ath/ath10k/ahb.c
+++ b/drivers/net/wireless/ath/ath10k/ahb.c
@@ -27,7 +27,7 @@ MODULE_DEVICE_TABLE(of, ath10k_ahb_of_match);
static inline struct ath10k_ahb *ath10k_ahb_priv(struct ath10k *ar)
{
- return &((struct ath10k_pci *)ar->drv_priv)->ahb[0];
+ return &ath10k_pci_priv(ar)->ahb[0];
}
static void ath10k_ahb_write32(struct ath10k *ar, u32 offset, u32 value)
@@ -816,23 +816,13 @@ err_resource_deinit:
err_core_destroy:
ath10k_core_destroy(ar);
- platform_set_drvdata(pdev, NULL);
return ret;
}
-static int ath10k_ahb_remove(struct platform_device *pdev)
+static void ath10k_ahb_remove(struct platform_device *pdev)
{
struct ath10k *ar = platform_get_drvdata(pdev);
- struct ath10k_ahb *ar_ahb;
-
- if (!ar)
- return -EINVAL;
-
- ar_ahb = ath10k_ahb_priv(ar);
-
- if (!ar_ahb)
- return -EINVAL;
ath10k_dbg(ar, ATH10K_DBG_AHB, "ahb remove\n");
@@ -844,10 +834,6 @@ static int ath10k_ahb_remove(struct platform_device *pdev)
ath10k_ahb_clock_disable(ar);
ath10k_ahb_resource_deinit(ar);
ath10k_core_destroy(ar);
-
- platform_set_drvdata(pdev, NULL);
-
- return 0;
}
static struct platform_driver ath10k_ahb_driver = {
@@ -856,7 +842,7 @@ static struct platform_driver ath10k_ahb_driver = {
.of_match_table = ath10k_ahb_of_match,
},
.probe = ath10k_ahb_probe,
- .remove = ath10k_ahb_remove,
+ .remove_new = ath10k_ahb_remove,
};
int ath10k_ahb_init(void)
diff --git a/drivers/net/wireless/ath/ath10k/core.c b/drivers/net/wireless/ath/ath10k/core.c
index 5eb131ab916f..6cdb225b7eac 100644
--- a/drivers/net/wireless/ath/ath10k/core.c
+++ b/drivers/net/wireless/ath/ath10k/core.c
@@ -2504,7 +2504,6 @@ EXPORT_SYMBOL(ath10k_core_napi_sync_disable);
static void ath10k_core_restart(struct work_struct *work)
{
struct ath10k *ar = container_of(work, struct ath10k, restart_work);
- struct ath10k_vif *arvif;
int ret;
set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
@@ -2543,14 +2542,6 @@ static void ath10k_core_restart(struct work_struct *work)
ar->state = ATH10K_STATE_RESTARTING;
ath10k_halt(ar);
ath10k_scan_finish(ar);
- if (ar->hw_params.hw_restart_disconnect) {
- list_for_each_entry(arvif, &ar->arvifs, list) {
- if (arvif->is_up &&
- arvif->vdev_type == WMI_VDEV_TYPE_STA)
- ieee80211_hw_restart_disconnect(arvif->vif);
- }
- }
-
ieee80211_restart_hw(ar->hw);
break;
case ATH10K_STATE_OFF:
@@ -3643,6 +3634,9 @@ struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
mutex_init(&ar->dump_mutex);
spin_lock_init(&ar->data_lock);
+ for (int ac = 0; ac < IEEE80211_NUM_ACS; ac++)
+ spin_lock_init(&ar->queue_lock[ac]);
+
INIT_LIST_HEAD(&ar->peers);
init_waitqueue_head(&ar->peer_mapping_wq);
init_waitqueue_head(&ar->htt.empty_tx_wq);
diff --git a/drivers/net/wireless/ath/ath10k/core.h b/drivers/net/wireless/ath/ath10k/core.h
index f5de8ce8fb45..4b5239de4018 100644
--- a/drivers/net/wireless/ath/ath10k/core.h
+++ b/drivers/net/wireless/ath/ath10k/core.h
@@ -1170,6 +1170,9 @@ struct ath10k {
/* protects shared structure data */
spinlock_t data_lock;
+ /* serialize wake_tx_queue calls per ac */
+ spinlock_t queue_lock[IEEE80211_NUM_ACS];
+
struct list_head arvifs;
struct list_head peers;
struct ath10k_peer *peer_map[ATH10K_MAX_NUM_PEER_IDS];
diff --git a/drivers/net/wireless/ath/ath10k/debug.c b/drivers/net/wireless/ath/ath10k/debug.c
index b9aea1510f7b..f9518e1c9903 100644
--- a/drivers/net/wireless/ath/ath10k/debug.c
+++ b/drivers/net/wireless/ath/ath10k/debug.c
@@ -293,8 +293,8 @@ void ath10k_debug_fw_stats_process(struct ath10k *ar, struct sk_buff *skb)
goto free;
}
- num_peers = ath10k_wmi_fw_stats_num_peers(&ar->debug.fw_stats.peers);
- num_vdevs = ath10k_wmi_fw_stats_num_vdevs(&ar->debug.fw_stats.vdevs);
+ num_peers = list_count_nodes(&ar->debug.fw_stats.peers);
+ num_vdevs = list_count_nodes(&ar->debug.fw_stats.vdevs);
is_start = (list_empty(&ar->debug.fw_stats.pdevs) &&
!list_empty(&stats.pdevs));
is_end = (!list_empty(&ar->debug.fw_stats.pdevs) &&
diff --git a/drivers/net/wireless/ath/ath10k/htt.h b/drivers/net/wireless/ath/ath10k/htt.h
index c051a22fce14..e0c9f45e7476 100644
--- a/drivers/net/wireless/ath/ath10k/htt.h
+++ b/drivers/net/wireless/ath/ath10k/htt.h
@@ -707,7 +707,7 @@ struct htt_rx_indication_prefix {
__le16 fw_rx_desc_bytes;
u8 pad0;
u8 pad1;
-};
+} __packed;
struct htt_rx_indication {
struct htt_rx_indication_hdr hdr;
@@ -1565,7 +1565,7 @@ struct htt_tx_fetch_ind {
/* ath10k_htt_get_tx_fetch_ind_resp_ids() */
DECLARE_FLEX_ARRAY(__le32, resp_ids);
DECLARE_FLEX_ARRAY(struct htt_tx_fetch_record, records);
- };
+ } __packed;
} __packed;
static inline void *
@@ -1723,7 +1723,7 @@ struct htt_resp {
struct htt_tx_mode_switch_ind tx_mode_switch_ind;
struct htt_channel_change chan_change;
struct htt_peer_tx_stats peer_tx_stats;
- };
+ } __packed;
} __packed;
/*** host side structures follow ***/
diff --git a/drivers/net/wireless/ath/ath10k/mac.c b/drivers/net/wireless/ath/ath10k/mac.c
index 7675858f069b..03e7bc5b6c0b 100644
--- a/drivers/net/wireless/ath/ath10k/mac.c
+++ b/drivers/net/wireless/ath/ath10k/mac.c
@@ -4732,13 +4732,14 @@ static void ath10k_mac_op_wake_tx_queue(struct ieee80211_hw *hw,
{
struct ath10k *ar = hw->priv;
int ret;
- u8 ac;
+ u8 ac = txq->ac;
ath10k_htt_tx_txq_update(hw, txq);
if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH)
return;
- ac = txq->ac;
+ spin_lock_bh(&ar->queue_lock[ac]);
+
ieee80211_txq_schedule_start(hw, ac);
txq = ieee80211_next_txq(hw, ac);
if (!txq)
@@ -4753,6 +4754,7 @@ static void ath10k_mac_op_wake_tx_queue(struct ieee80211_hw *hw,
ath10k_htt_tx_txq_update(hw, txq);
out:
ieee80211_txq_schedule_end(hw, ac);
+ spin_unlock_bh(&ar->queue_lock[ac]);
}
/* Must not be called with conf_mutex held as workers can use that also. */
@@ -8107,6 +8109,7 @@ static void ath10k_reconfig_complete(struct ieee80211_hw *hw,
enum ieee80211_reconfig_type reconfig_type)
{
struct ath10k *ar = hw->priv;
+ struct ath10k_vif *arvif;
if (reconfig_type != IEEE80211_RECONFIG_TYPE_RESTART)
return;
@@ -8121,6 +8124,12 @@ static void ath10k_reconfig_complete(struct ieee80211_hw *hw,
ar->state = ATH10K_STATE_ON;
ieee80211_wake_queues(ar->hw);
clear_bit(ATH10K_FLAG_RESTARTING, &ar->dev_flags);
+ if (ar->hw_params.hw_restart_disconnect) {
+ list_for_each_entry(arvif, &ar->arvifs, list) {
+ if (arvif->is_up && arvif->vdev_type == WMI_VDEV_TYPE_STA)
+ ieee80211_hw_restart_disconnect(arvif->vif);
+ }
+ }
}
mutex_unlock(&ar->conf_mutex);
diff --git a/drivers/net/wireless/ath/ath10k/snoc.c b/drivers/net/wireless/ath/ath10k/snoc.c
index 5128a452c65f..26214c00cd0d 100644
--- a/drivers/net/wireless/ath/ath10k/snoc.c
+++ b/drivers/net/wireless/ath/ath10k/snoc.c
@@ -1848,7 +1848,7 @@ static int ath10k_snoc_free_resources(struct ath10k *ar)
return 0;
}
-static int ath10k_snoc_remove(struct platform_device *pdev)
+static void ath10k_snoc_remove(struct platform_device *pdev)
{
struct ath10k *ar = platform_get_drvdata(pdev);
struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
@@ -1861,8 +1861,6 @@ static int ath10k_snoc_remove(struct platform_device *pdev)
wait_for_completion_timeout(&ar->driver_recovery, 3 * HZ);
ath10k_snoc_free_resources(ar);
-
- return 0;
}
static void ath10k_snoc_shutdown(struct platform_device *pdev)
@@ -1875,8 +1873,8 @@ static void ath10k_snoc_shutdown(struct platform_device *pdev)
static struct platform_driver ath10k_snoc_driver = {
.probe = ath10k_snoc_probe,
- .remove = ath10k_snoc_remove,
- .shutdown = ath10k_snoc_shutdown,
+ .remove_new = ath10k_snoc_remove,
+ .shutdown = ath10k_snoc_shutdown,
.driver = {
.name = "ath10k_snoc",
.of_match_table = ath10k_snoc_dt_match,
diff --git a/drivers/net/wireless/ath/ath10k/wmi.c b/drivers/net/wireless/ath/ath10k/wmi.c
index 980d4124fa28..05fa7d4c0e1a 100644
--- a/drivers/net/wireless/ath/ath10k/wmi.c
+++ b/drivers/net/wireless/ath/ath10k/wmi.c
@@ -8164,28 +8164,6 @@ ath10k_wmi_10_2_4_op_gen_pdev_get_tpc_config(struct ath10k *ar, u32 param)
return skb;
}
-size_t ath10k_wmi_fw_stats_num_peers(struct list_head *head)
-{
- struct ath10k_fw_stats_peer *i;
- size_t num = 0;
-
- list_for_each_entry(i, head, list)
- ++num;
-
- return num;
-}
-
-size_t ath10k_wmi_fw_stats_num_vdevs(struct list_head *head)
-{
- struct ath10k_fw_stats_vdev *i;
- size_t num = 0;
-
- list_for_each_entry(i, head, list)
- ++num;
-
- return num;
-}
-
static void
ath10k_wmi_fw_pdev_base_stats_fill(const struct ath10k_fw_stats_pdev *pdev,
char *buf, u32 *length)
@@ -8462,8 +8440,8 @@ void ath10k_wmi_main_op_fw_stats_fill(struct ath10k *ar,
goto unlock;
}
- num_peers = ath10k_wmi_fw_stats_num_peers(&fw_stats->peers);
- num_vdevs = ath10k_wmi_fw_stats_num_vdevs(&fw_stats->vdevs);
+ num_peers = list_count_nodes(&fw_stats->peers);
+ num_vdevs = list_count_nodes(&fw_stats->vdevs);
ath10k_wmi_fw_pdev_base_stats_fill(pdev, buf, &len);
ath10k_wmi_fw_pdev_tx_stats_fill(pdev, buf, &len);
@@ -8520,8 +8498,8 @@ void ath10k_wmi_10x_op_fw_stats_fill(struct ath10k *ar,
goto unlock;
}
- num_peers = ath10k_wmi_fw_stats_num_peers(&fw_stats->peers);
- num_vdevs = ath10k_wmi_fw_stats_num_vdevs(&fw_stats->vdevs);
+ num_peers = list_count_nodes(&fw_stats->peers);
+ num_vdevs = list_count_nodes(&fw_stats->vdevs);
ath10k_wmi_fw_pdev_base_stats_fill(pdev, buf, &len);
ath10k_wmi_fw_pdev_extra_stats_fill(pdev, buf, &len);
@@ -8668,8 +8646,8 @@ void ath10k_wmi_10_4_op_fw_stats_fill(struct ath10k *ar,
goto unlock;
}
- num_peers = ath10k_wmi_fw_stats_num_peers(&fw_stats->peers);
- num_vdevs = ath10k_wmi_fw_stats_num_vdevs(&fw_stats->vdevs);
+ num_peers = list_count_nodes(&fw_stats->peers);
+ num_vdevs = list_count_nodes(&fw_stats->vdevs);
ath10k_wmi_fw_pdev_base_stats_fill(pdev, buf, &len);
ath10k_wmi_fw_pdev_extra_stats_fill(pdev, buf, &len);
diff --git a/drivers/net/wireless/ath/ath10k/wmi.h b/drivers/net/wireless/ath/ath10k/wmi.h
index 6de3cc4640a0..6d04a66fe5e0 100644
--- a/drivers/net/wireless/ath/ath10k/wmi.h
+++ b/drivers/net/wireless/ath/ath10k/wmi.h
@@ -7502,8 +7502,6 @@ void ath10k_wmi_main_op_fw_stats_fill(struct ath10k *ar,
void ath10k_wmi_10x_op_fw_stats_fill(struct ath10k *ar,
struct ath10k_fw_stats *fw_stats,
char *buf);
-size_t ath10k_wmi_fw_stats_num_peers(struct list_head *head);
-size_t ath10k_wmi_fw_stats_num_vdevs(struct list_head *head);
void ath10k_wmi_10_4_op_fw_stats_fill(struct ath10k *ar,
struct ath10k_fw_stats *fw_stats,
char *buf);
diff --git a/drivers/net/wireless/ath/ath11k/ahb.c b/drivers/net/wireless/ath/ath11k/ahb.c
index 5cbba9a8b6ba..1cebba7889d7 100644
--- a/drivers/net/wireless/ath/ath11k/ahb.c
+++ b/drivers/net/wireless/ath/ath11k/ahb.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause-Clear
/*
* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/module.h>
@@ -734,7 +734,7 @@ static int ath11k_ahb_hif_suspend(struct ath11k_base *ab)
return ret;
}
- ath11k_dbg(ab, ATH11K_DBG_AHB, "ahb device suspended\n");
+ ath11k_dbg(ab, ATH11K_DBG_AHB, "device suspended\n");
return ret;
}
@@ -777,7 +777,7 @@ static int ath11k_ahb_hif_resume(struct ath11k_base *ab)
return -ETIMEDOUT;
}
- ath11k_dbg(ab, ATH11K_DBG_AHB, "ahb device resumed\n");
+ ath11k_dbg(ab, ATH11K_DBG_AHB, "device resumed\n");
return 0;
}
@@ -1127,6 +1127,7 @@ static int ath11k_ahb_probe(struct platform_device *pdev)
switch (hw_rev) {
case ATH11K_HW_IPQ8074:
case ATH11K_HW_IPQ6018_HW10:
+ case ATH11K_HW_IPQ5018_HW10:
hif_ops = &ath11k_ahb_hif_ops_ipq8074;
pci_ops = NULL;
break;
@@ -1155,6 +1156,7 @@ static int ath11k_ahb_probe(struct platform_device *pdev)
ab->hif.ops = hif_ops;
ab->pdev = pdev;
ab->hw_rev = hw_rev;
+ ab->fw_mode = ATH11K_FIRMWARE_MODE_NORMAL;
platform_set_drvdata(pdev, ab);
ret = ath11k_pcic_register_pci_ops(ab, pci_ops);
diff --git a/drivers/net/wireless/ath/ath11k/ce.c b/drivers/net/wireless/ath/ath11k/ce.c
index f2da95fd4253..289d47ae92af 100644
--- a/drivers/net/wireless/ath/ath11k/ce.c
+++ b/drivers/net/wireless/ath/ath11k/ce.c
@@ -442,7 +442,7 @@ static void ath11k_ce_recv_process_cb(struct ath11k_ce_pipe *pipe)
}
while ((skb = __skb_dequeue(&list))) {
- ath11k_dbg(ab, ATH11K_DBG_AHB, "rx ce pipe %d len %d\n",
+ ath11k_dbg(ab, ATH11K_DBG_CE, "rx ce pipe %d len %d\n",
pipe->pipe_num, skb->len);
pipe->recv_cb(ab, skb);
}
@@ -520,7 +520,7 @@ static void ath11k_ce_tx_process_cb(struct ath11k_ce_pipe *pipe)
}
while ((skb = __skb_dequeue(&list))) {
- ath11k_dbg(ab, ATH11K_DBG_AHB, "tx ce pipe %d len %d\n",
+ ath11k_dbg(ab, ATH11K_DBG_CE, "tx ce pipe %d len %d\n",
pipe->pipe_num, skb->len);
pipe->send_cb(ab, skb);
}
diff --git a/drivers/net/wireless/ath/ath11k/core.c b/drivers/net/wireless/ath/ath11k/core.c
index b1b90bd34d67..bebfd342e28b 100644
--- a/drivers/net/wireless/ath/ath11k/core.c
+++ b/drivers/net/wireless/ath/ath11k/core.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause-Clear
/*
* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/module.h>
@@ -32,6 +32,10 @@ module_param_named(frame_mode, ath11k_frame_mode, uint, 0644);
MODULE_PARM_DESC(frame_mode,
"Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)");
+bool ath11k_ftm_mode;
+module_param_named(ftm_mode, ath11k_ftm_mode, bool, 0444);
+MODULE_PARM_DESC(ftm_mode, "Boots up in factory test mode");
+
static const struct ath11k_hw_params ath11k_hw_params[] = {
{
.hw_rev = ATH11K_HW_IPQ8074,
@@ -664,6 +668,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
.hal_params = &ath11k_hw_hal_params_ipq8074,
.single_pdev_only = false,
.cold_boot_calib = true,
+ .cbcal_restart_fw = true,
.fix_l1ss = true,
.supports_dynamic_smps_6ghz = false,
.alloc_cacheable_memory = true,
@@ -874,16 +879,16 @@ static void ath11k_core_check_cc_code_bdfext(const struct dmi_header *hdr, void
case ATH11K_SMBIOS_CC_ISO:
ab->new_alpha2[0] = (smbios->cc_code >> 8) & 0xff;
ab->new_alpha2[1] = smbios->cc_code & 0xff;
- ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot smbios cc_code %c%c\n",
+ ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios cc_code %c%c\n",
ab->new_alpha2[0], ab->new_alpha2[1]);
break;
case ATH11K_SMBIOS_CC_WW:
ab->new_alpha2[0] = '0';
ab->new_alpha2[1] = '0';
- ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot smbios worldwide regdomain\n");
+ ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios worldwide regdomain\n");
break;
default:
- ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot ignore smbios country code setting %d\n",
+ ath11k_dbg(ab, ATH11K_DBG_BOOT, "ignore smbios country code setting %d\n",
smbios->country_code_flag);
break;
}
@@ -961,7 +966,8 @@ int ath11k_core_check_dt(struct ath11k_base *ab)
}
static int __ath11k_core_create_board_name(struct ath11k_base *ab, char *name,
- size_t name_len, bool with_variant)
+ size_t name_len, bool with_variant,
+ bool bus_type_mode)
{
/* strlen(',variant=') + strlen(ab->qmi.target.bdf_ext) */
char variant[9 + ATH11K_QMI_BDF_EXT_STR_LENGTH] = { 0 };
@@ -972,15 +978,20 @@ static int __ath11k_core_create_board_name(struct ath11k_base *ab, char *name,
switch (ab->id.bdf_search) {
case ATH11K_BDF_SEARCH_BUS_AND_BOARD:
- scnprintf(name, name_len,
- "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x,qmi-chip-id=%d,qmi-board-id=%d%s",
- ath11k_bus_str(ab->hif.bus),
- ab->id.vendor, ab->id.device,
- ab->id.subsystem_vendor,
- ab->id.subsystem_device,
- ab->qmi.target.chip_id,
- ab->qmi.target.board_id,
- variant);
+ if (bus_type_mode)
+ scnprintf(name, name_len,
+ "bus=%s",
+ ath11k_bus_str(ab->hif.bus));
+ else
+ scnprintf(name, name_len,
+ "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x,qmi-chip-id=%d,qmi-board-id=%d%s",
+ ath11k_bus_str(ab->hif.bus),
+ ab->id.vendor, ab->id.device,
+ ab->id.subsystem_vendor,
+ ab->id.subsystem_device,
+ ab->qmi.target.chip_id,
+ ab->qmi.target.board_id,
+ variant);
break;
default:
scnprintf(name, name_len,
@@ -991,7 +1002,7 @@ static int __ath11k_core_create_board_name(struct ath11k_base *ab, char *name,
break;
}
- ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot using board name '%s'\n", name);
+ ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board name '%s'\n", name);
return 0;
}
@@ -999,13 +1010,19 @@ static int __ath11k_core_create_board_name(struct ath11k_base *ab, char *name,
static int ath11k_core_create_board_name(struct ath11k_base *ab, char *name,
size_t name_len)
{
- return __ath11k_core_create_board_name(ab, name, name_len, true);
+ return __ath11k_core_create_board_name(ab, name, name_len, true, false);
}
static int ath11k_core_create_fallback_board_name(struct ath11k_base *ab, char *name,
size_t name_len)
{
- return __ath11k_core_create_board_name(ab, name, name_len, false);
+ return __ath11k_core_create_board_name(ab, name, name_len, false, false);
+}
+
+static int ath11k_core_create_bus_type_board_name(struct ath11k_base *ab, char *name,
+ size_t name_len)
+{
+ return __ath11k_core_create_board_name(ab, name, name_len, false, true);
}
const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab,
@@ -1024,7 +1041,7 @@ const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab,
if (ret)
return ERR_PTR(ret);
- ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot firmware request %s size %zu\n",
+ ath11k_dbg(ab, ATH11K_DBG_BOOT, "firmware request %s size %zu\n",
path, fw->size);
return fw;
@@ -1085,7 +1102,7 @@ static int ath11k_core_parse_bd_ie_board(struct ath11k_base *ab,
name_match_found = true;
ath11k_dbg(ab, ATH11K_DBG_BOOT,
- "boot found match %s for name '%s'",
+ "found match %s for name '%s'",
ath11k_bd_ie_type_str(ie_id),
boardname);
} else if (board_ie_id == data_id) {
@@ -1094,7 +1111,7 @@ static int ath11k_core_parse_bd_ie_board(struct ath11k_base *ab,
goto next;
ath11k_dbg(ab, ATH11K_DBG_BOOT,
- "boot found %s for '%s'",
+ "found %s for '%s'",
ath11k_bd_ie_type_str(ie_id),
boardname);
@@ -1309,7 +1326,7 @@ success:
int ath11k_core_fetch_regdb(struct ath11k_base *ab, struct ath11k_board_data *bd)
{
- char boardname[BOARD_NAME_SIZE];
+ char boardname[BOARD_NAME_SIZE], default_boardname[BOARD_NAME_SIZE];
int ret;
ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE);
@@ -1326,6 +1343,21 @@ int ath11k_core_fetch_regdb(struct ath11k_base *ab, struct ath11k_board_data *bd
if (!ret)
goto exit;
+ ret = ath11k_core_create_bus_type_board_name(ab, default_boardname,
+ BOARD_NAME_SIZE);
+ if (ret) {
+ ath11k_dbg(ab, ATH11K_DBG_BOOT,
+ "failed to create default board name for regdb: %d", ret);
+ goto exit;
+ }
+
+ ret = ath11k_core_fetch_board_data_api_n(ab, bd, default_boardname,
+ ATH11K_BD_IE_REGDB,
+ ATH11K_BD_IE_REGDB_NAME,
+ ATH11K_BD_IE_REGDB_DATA);
+ if (!ret)
+ goto exit;
+
ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_REGDB_FILE_NAME);
if (ret)
ath11k_dbg(ab, ATH11K_DBG_BOOT, "failed to fetch %s from %s\n",
@@ -1354,6 +1386,11 @@ static int ath11k_core_soc_create(struct ath11k_base *ab)
{
int ret;
+ if (ath11k_ftm_mode) {
+ ab->fw_mode = ATH11K_FIRMWARE_MODE_FTM;
+ ath11k_info(ab, "Booting in factory test mode\n");
+ }
+
ret = ath11k_qmi_init_service(ab);
if (ret) {
ath11k_err(ab, "failed to initialize qmi :%d\n", ret);
@@ -1580,7 +1617,7 @@ int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab)
{
int ret;
- ret = ath11k_core_start_firmware(ab, ATH11K_FIRMWARE_MODE_NORMAL);
+ ret = ath11k_core_start_firmware(ab, ab->fw_mode);
if (ret) {
ath11k_err(ab, "failed to start firmware: %d\n", ret);
return ret;
@@ -1745,7 +1782,8 @@ void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab)
for (i = 0; i < ab->num_radios; i++) {
pdev = &ab->pdevs[i];
ar = pdev->ar;
- if (!ar || ar->state == ATH11K_STATE_OFF)
+ if (!ar || ar->state == ATH11K_STATE_OFF ||
+ ar->state == ATH11K_STATE_FTM)
continue;
ieee80211_stop_queues(ar->hw);
@@ -1814,7 +1852,12 @@ static void ath11k_core_post_reconfigure_recovery(struct ath11k_base *ab)
ath11k_warn(ab,
"device is wedged, will not restart radio %d\n", i);
break;
+ case ATH11K_STATE_FTM:
+ ath11k_dbg(ab, ATH11K_DBG_TESTMODE,
+ "fw mode reset done radio %d\n", i);
+ break;
}
+
mutex_unlock(&ar->conf_mutex);
}
complete(&ab->driver_recovery);
diff --git a/drivers/net/wireless/ath/ath11k/core.h b/drivers/net/wireless/ath/ath11k/core.h
index 0830276e5028..9d15b4390b9c 100644
--- a/drivers/net/wireless/ath/ath11k/core.h
+++ b/drivers/net/wireless/ath/ath11k/core.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-3-Clause-Clear */
/*
* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef ATH11K_CORE_H
@@ -52,6 +52,7 @@
#define ATH11K_SMBIOS_BDF_EXT_MAGIC "BDF_"
extern unsigned int ath11k_frame_mode;
+extern bool ath11k_ftm_mode;
#define ATH11K_SCAN_TIMEOUT_HZ (20 * HZ)
@@ -277,6 +278,7 @@ enum ath11k_dev_flags {
ATH11K_FLAG_FIXED_MEM_RGN,
ATH11K_FLAG_DEVICE_INIT_DONE,
ATH11K_FLAG_MULTI_MSI_VECTORS,
+ ATH11K_FLAG_FTM_SEGMENTED,
};
enum ath11k_monitor_flags {
@@ -530,6 +532,7 @@ enum ath11k_state {
ATH11K_STATE_RESTARTING,
ATH11K_STATE_RESTARTED,
ATH11K_STATE_WEDGED,
+ ATH11K_STATE_FTM,
/* Add other states as required */
};
@@ -709,6 +712,8 @@ struct ath11k {
u32 last_ppdu_id;
u32 cached_ppdu_id;
int monitor_vdev_id;
+ struct completion fw_mode_reset;
+ u8 ftm_msgref;
#ifdef CONFIG_ATH11K_DEBUGFS
struct ath11k_debug debug;
#endif
@@ -838,6 +843,7 @@ struct ath11k_msi_config {
/* Master structure to hold the hw data which may be used in core module */
struct ath11k_base {
enum ath11k_hw_rev hw_rev;
+ enum ath11k_firmware_mode fw_mode;
struct platform_device *pdev;
struct device *dev;
struct ath11k_qmi qmi;
@@ -978,6 +984,14 @@ struct ath11k_base {
const struct ath11k_pci_ops *ops;
} pci;
+#ifdef CONFIG_NL80211_TESTMODE
+ struct {
+ u32 data_pos;
+ u32 expected_seq;
+ u8 *eventdata;
+ } testmode;
+#endif
+
/* must be last */
u8 drv_priv[] __aligned(sizeof(void *));
};
diff --git a/drivers/net/wireless/ath/ath11k/debug.c b/drivers/net/wireless/ath/ath11k/debug.c
index 958d87429062..f5c8a34c8802 100644
--- a/drivers/net/wireless/ath/ath11k/debug.c
+++ b/drivers/net/wireless/ath/ath11k/debug.c
@@ -66,7 +66,7 @@ void __ath11k_dbg(struct ath11k_base *ab, enum ath11k_debug_mask mask,
vaf.va = &args;
if (ath11k_debug_mask & mask)
- dev_printk(KERN_DEBUG, ab->dev, "%pV", &vaf);
+ dev_printk(KERN_DEBUG, ab->dev, "%s %pV", ath11k_dbg_str(mask), &vaf);
trace_ath11k_log_dbg(ab, mask, &vaf);
diff --git a/drivers/net/wireless/ath/ath11k/debug.h b/drivers/net/wireless/ath/ath11k/debug.h
index 91545640c47b..9c52804ef8ac 100644
--- a/drivers/net/wireless/ath/ath11k/debug.h
+++ b/drivers/net/wireless/ath/ath11k/debug.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: BSD-3-Clause-Clear */
/*
* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _ATH11K_DEBUG_H_
@@ -21,13 +22,57 @@ enum ath11k_debug_mask {
ATH11K_DBG_MGMT = 0x00000100,
ATH11K_DBG_REG = 0x00000200,
ATH11K_DBG_TESTMODE = 0x00000400,
- ATH11k_DBG_HAL = 0x00000800,
+ ATH11K_DBG_HAL = 0x00000800,
ATH11K_DBG_PCI = 0x00001000,
ATH11K_DBG_DP_TX = 0x00002000,
ATH11K_DBG_DP_RX = 0x00004000,
- ATH11K_DBG_ANY = 0xffffffff,
+ ATH11K_DBG_CE = 0x00008000,
};
+static inline const char *ath11k_dbg_str(enum ath11k_debug_mask mask)
+{
+ switch (mask) {
+ case ATH11K_DBG_AHB:
+ return "ahb";
+ case ATH11K_DBG_WMI:
+ return "wmi";
+ case ATH11K_DBG_HTC:
+ return "htc";
+ case ATH11K_DBG_DP_HTT:
+ return "dp_htt";
+ case ATH11K_DBG_MAC:
+ return "mac";
+ case ATH11K_DBG_BOOT:
+ return "boot";
+ case ATH11K_DBG_QMI:
+ return "qmi";
+ case ATH11K_DBG_DATA:
+ return "data";
+ case ATH11K_DBG_MGMT:
+ return "mgmt";
+ case ATH11K_DBG_REG:
+ return "reg";
+ case ATH11K_DBG_TESTMODE:
+ return "testmode";
+ case ATH11K_DBG_HAL:
+ return "hal";
+ case ATH11K_DBG_PCI:
+ return "pci";
+ case ATH11K_DBG_DP_TX:
+ return "dp_tx";
+ case ATH11K_DBG_DP_RX:
+ return "dp_rx";
+ case ATH11K_DBG_CE:
+ return "ce";
+
+ /* no default handler to allow compiler to check that the
+ * enum is fully handled
+ */
+ }
+
+ return "<?>";
+}
+
__printf(2, 3) void ath11k_info(struct ath11k_base *ab, const char *fmt, ...);
__printf(2, 3) void ath11k_err(struct ath11k_base *ab, const char *fmt, ...);
__printf(2, 3) void ath11k_warn(struct ath11k_base *ab, const char *fmt, ...);
diff --git a/drivers/net/wireless/ath/ath11k/debugfs_htt_stats.c b/drivers/net/wireless/ath/ath11k/debugfs_htt_stats.c
index b3efca6bd7dd..0207fc4910f3 100644
--- a/drivers/net/wireless/ath/ath11k/debugfs_htt_stats.c
+++ b/drivers/net/wireless/ath/ath11k/debugfs_htt_stats.c
@@ -4011,6 +4011,114 @@ void htt_print_phy_stats_tlv(const void *tag_buf,
stats_req->buf_len = len;
}
+static inline void
+htt_print_phy_reset_counters_tlv(const void *tag_buf,
+ u16 tag_len,
+ struct debug_htt_stats_req *stats_req)
+{
+ const struct htt_phy_reset_counters_tlv *htt_stats_buf = tag_buf;
+ u8 *buf = stats_req->buf;
+ u32 len = stats_req->buf_len;
+ u32 buf_len = ATH11K_HTT_STATS_BUF_SIZE;
+
+ if (tag_len < sizeof(*htt_stats_buf))
+ return;
+
+ len += scnprintf(buf + len, buf_len - len, "HTT_PHY_RESET_COUNTERS_TLV:\n");
+
+ len += scnprintf(buf + len, buf_len - len, "pdev_id = %u\n",
+ htt_stats_buf->pdev_id);
+ len += scnprintf(buf + len, buf_len - len, "cf_active_low_fail_cnt = %u\n",
+ htt_stats_buf->cf_active_low_fail_cnt);
+ len += scnprintf(buf + len, buf_len - len, "cf_active_low_pass_cnt = %u\n",
+ htt_stats_buf->cf_active_low_pass_cnt);
+ len += scnprintf(buf + len, buf_len - len, "phy_off_through_vreg_cnt = %u\n",
+ htt_stats_buf->phy_off_through_vreg_cnt);
+ len += scnprintf(buf + len, buf_len - len, "force_calibration_cnt = %u\n",
+ htt_stats_buf->force_calibration_cnt);
+ len += scnprintf(buf + len, buf_len - len, "rf_mode_switch_phy_off_cnt = %u\n",
+ htt_stats_buf->rf_mode_switch_phy_off_cnt);
+
+ stats_req->buf_len = len;
+}
+
+static inline void
+htt_print_phy_reset_stats_tlv(const void *tag_buf,
+ u16 tag_len,
+ struct debug_htt_stats_req *stats_req)
+{
+ const struct htt_phy_reset_stats_tlv *htt_stats_buf = tag_buf;
+ u8 *buf = stats_req->buf;
+ u32 len = stats_req->buf_len;
+ u32 buf_len = ATH11K_HTT_STATS_BUF_SIZE;
+
+ if (tag_len < sizeof(*htt_stats_buf))
+ return;
+
+ len += scnprintf(buf + len, buf_len - len, "HTT_PHY_RESET_STATS_TLV:\n");
+
+ len += scnprintf(buf + len, buf_len - len, "pdev_id = %u\n",
+ htt_stats_buf->pdev_id);
+ len += scnprintf(buf + len, buf_len - len, "chan_mhz = %u\n",
+ htt_stats_buf->chan_mhz);
+ len += scnprintf(buf + len, buf_len - len, "chan_band_center_freq1 = %u\n",
+ htt_stats_buf->chan_band_center_freq1);
+ len += scnprintf(buf + len, buf_len - len, "chan_band_center_freq2 = %u\n",
+ htt_stats_buf->chan_band_center_freq2);
+ len += scnprintf(buf + len, buf_len - len, "chan_phy_mode = %u\n",
+ htt_stats_buf->chan_phy_mode);
+ len += scnprintf(buf + len, buf_len - len, "chan_flags = 0x%0x\n",
+ htt_stats_buf->chan_flags);
+ len += scnprintf(buf + len, buf_len - len, "chan_num = %u\n",
+ htt_stats_buf->chan_num);
+ len += scnprintf(buf + len, buf_len - len, "reset_cause = 0x%0x\n",
+ htt_stats_buf->reset_cause);
+ len += scnprintf(buf + len, buf_len - len, "prev_reset_cause = 0x%0x\n",
+ htt_stats_buf->prev_reset_cause);
+ len += scnprintf(buf + len, buf_len - len, "phy_warm_reset_src = 0x%0x\n",
+ htt_stats_buf->phy_warm_reset_src);
+ len += scnprintf(buf + len, buf_len - len, "rx_gain_tbl_mode = %d\n",
+ htt_stats_buf->rx_gain_tbl_mode);
+ len += scnprintf(buf + len, buf_len - len, "xbar_val = 0x%0x\n",
+ htt_stats_buf->xbar_val);
+ len += scnprintf(buf + len, buf_len - len, "force_calibration = %u\n",
+ htt_stats_buf->force_calibration);
+ len += scnprintf(buf + len, buf_len - len, "phyrf_mode = %u\n",
+ htt_stats_buf->phyrf_mode);
+ len += scnprintf(buf + len, buf_len - len, "phy_homechan = %u\n",
+ htt_stats_buf->phy_homechan);
+ len += scnprintf(buf + len, buf_len - len, "phy_tx_ch_mask = 0x%0x\n",
+ htt_stats_buf->phy_tx_ch_mask);
+ len += scnprintf(buf + len, buf_len - len, "phy_rx_ch_mask = 0x%0x\n",
+ htt_stats_buf->phy_rx_ch_mask);
+ len += scnprintf(buf + len, buf_len - len, "phybb_ini_mask = 0x%0x\n",
+ htt_stats_buf->phybb_ini_mask);
+ len += scnprintf(buf + len, buf_len - len, "phyrf_ini_mask = 0x%0x\n",
+ htt_stats_buf->phyrf_ini_mask);
+ len += scnprintf(buf + len, buf_len - len, "phy_dfs_en_mask = 0x%0x\n",
+ htt_stats_buf->phy_dfs_en_mask);
+ len += scnprintf(buf + len, buf_len - len, "phy_sscan_en_mask = 0x%0x\n",
+ htt_stats_buf->phy_sscan_en_mask);
+ len += scnprintf(buf + len, buf_len - len, "phy_synth_sel_mask = 0x%0x\n",
+ htt_stats_buf->phy_synth_sel_mask);
+ len += scnprintf(buf + len, buf_len - len, "phy_adfs_freq = %u\n",
+ htt_stats_buf->phy_adfs_freq);
+ len += scnprintf(buf + len, buf_len - len, "cck_fir_settings = 0x%0x\n",
+ htt_stats_buf->cck_fir_settings);
+ len += scnprintf(buf + len, buf_len - len, "phy_dyn_pri_chan = %u\n",
+ htt_stats_buf->phy_dyn_pri_chan);
+ len += scnprintf(buf + len, buf_len - len, "cca_thresh = 0x%0x\n",
+ htt_stats_buf->cca_thresh);
+ len += scnprintf(buf + len, buf_len - len, "dyn_cca_status = %u\n",
+ htt_stats_buf->dyn_cca_status);
+ len += scnprintf(buf + len, buf_len - len, "rxdesense_thresh_hw = 0x%x\n",
+ htt_stats_buf->rxdesense_thresh_hw);
+ len += scnprintf(buf + len, buf_len - len, "rxdesense_thresh_sw = 0x%x\n",
+ htt_stats_buf->rxdesense_thresh_sw);
+
+ stats_req->buf_len = len;
+}
+
static inline
void htt_print_peer_ctrl_path_txrx_stats_tlv(const void *tag_buf,
struct debug_htt_stats_req *stats_req)
@@ -4425,6 +4533,12 @@ static int ath11k_dbg_htt_ext_stats_parse(struct ath11k_base *ab,
case HTT_STATS_PHY_STATS_TAG:
htt_print_phy_stats_tlv(tag_buf, stats_req);
break;
+ case HTT_STATS_PHY_RESET_COUNTERS_TAG:
+ htt_print_phy_reset_counters_tlv(tag_buf, len, stats_req);
+ break;
+ case HTT_STATS_PHY_RESET_STATS_TAG:
+ htt_print_phy_reset_stats_tlv(tag_buf, len, stats_req);
+ break;
case HTT_STATS_PEER_CTRL_PATH_TXRX_STATS_TAG:
htt_print_peer_ctrl_path_txrx_stats_tlv(tag_buf, stats_req);
break;
diff --git a/drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h b/drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h
index 0bbd58a380de..96219301f05b 100644
--- a/drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h
+++ b/drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h
@@ -111,6 +111,8 @@ enum htt_tlv_tag_t {
HTT_STATS_TXBF_OFDMA_STEER_STATS_TAG = 116,
HTT_STATS_PHY_COUNTERS_TAG = 121,
HTT_STATS_PHY_STATS_TAG = 122,
+ HTT_STATS_PHY_RESET_COUNTERS_TAG = 123,
+ HTT_STATS_PHY_RESET_STATS_TAG = 124,
HTT_STATS_MAX_TAG,
};
@@ -1964,6 +1966,47 @@ struct htt_phy_stats_tlv {
u32 fw_run_time;
};
+struct htt_phy_reset_counters_tlv {
+ u32 pdev_id;
+ u32 cf_active_low_fail_cnt;
+ u32 cf_active_low_pass_cnt;
+ u32 phy_off_through_vreg_cnt;
+ u32 force_calibration_cnt;
+ u32 rf_mode_switch_phy_off_cnt;
+};
+
+struct htt_phy_reset_stats_tlv {
+ u32 pdev_id;
+ u32 chan_mhz;
+ u32 chan_band_center_freq1;
+ u32 chan_band_center_freq2;
+ u32 chan_phy_mode;
+ u32 chan_flags;
+ u32 chan_num;
+ u32 reset_cause;
+ u32 prev_reset_cause;
+ u32 phy_warm_reset_src;
+ u32 rx_gain_tbl_mode;
+ u32 xbar_val;
+ u32 force_calibration;
+ u32 phyrf_mode;
+ u32 phy_homechan;
+ u32 phy_tx_ch_mask;
+ u32 phy_rx_ch_mask;
+ u32 phybb_ini_mask;
+ u32 phyrf_ini_mask;
+ u32 phy_dfs_en_mask;
+ u32 phy_sscan_en_mask;
+ u32 phy_synth_sel_mask;
+ u32 phy_adfs_freq;
+ u32 cck_fir_settings;
+ u32 phy_dyn_pri_chan;
+ u32 cca_thresh;
+ u32 dyn_cca_status;
+ u32 rxdesense_thresh_hw;
+ u32 rxdesense_thresh_sw;
+};
+
struct htt_peer_ctrl_path_txrx_stats_tlv {
/* peer mac address */
u8 peer_mac_addr[ETH_ALEN];
diff --git a/drivers/net/wireless/ath/ath11k/dp_rx.c b/drivers/net/wireless/ath/ath11k/dp_rx.c
index f67ce62b2b48..5c76664ba0dd 100644
--- a/drivers/net/wireless/ath/ath11k/dp_rx.c
+++ b/drivers/net/wireless/ath/ath11k/dp_rx.c
@@ -1651,7 +1651,7 @@ static void ath11k_htt_backpressure_event_handler(struct ath11k_base *ab,
backpressure_time = *data;
- ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "htt backpressure event, pdev %d, ring type %d,ring id %d, hp %d tp %d, backpressure time %d\n",
+ ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "backpressure event, pdev %d, ring type %d,ring id %d, hp %d tp %d, backpressure time %d\n",
pdev_id, ring_type, ring_id, hp, tp, backpressure_time);
if (ring_type == HTT_BACKPRESSURE_UMAC_RING_TYPE) {
@@ -2466,7 +2466,7 @@ static void ath11k_dp_rx_deliver_msdu(struct ath11k *ar, struct napi_struct *nap
spin_unlock_bh(&ar->ab->base_lock);
ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
- "rx skb %pK len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",
+ "rx skb %p len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",
msdu,
msdu->len,
peer ? peer->addr : NULL,
@@ -4908,7 +4908,7 @@ ath11k_dp_rx_mon_merg_msdus(struct ath11k *ar,
goto err_merge_fail;
ath11k_dbg(ab, ATH11K_DBG_DATA,
- "mpdu_buf %pK mpdu_buf->len %u",
+ "mpdu_buf %p mpdu_buf->len %u",
prev_buf, prev_buf->len);
} else {
ath11k_dbg(ab, ATH11K_DBG_DATA,
@@ -5099,7 +5099,7 @@ static void ath11k_dp_rx_mon_dest_process(struct ath11k *ar, int mac_id,
if (!mon_dst_srng) {
ath11k_warn(ar->ab,
- "HAL Monitor Destination Ring Init Failed -- %pK",
+ "HAL Monitor Destination Ring Init Failed -- %p",
mon_dst_srng);
return;
}
diff --git a/drivers/net/wireless/ath/ath11k/dp_tx.c b/drivers/net/wireless/ath/ath11k/dp_tx.c
index 08a28464eb7a..a34833de7c67 100644
--- a/drivers/net/wireless/ath/ath11k/dp_tx.c
+++ b/drivers/net/wireless/ath/ath11k/dp_tx.c
@@ -964,14 +964,10 @@ int ath11k_dp_tx_htt_srng_setup(struct ath11k_base *ab, u32 ring_id,
params.low_threshold);
}
- ath11k_dbg(ab, ATH11k_DBG_HAL,
- "%s msi_addr_lo:0x%x, msi_addr_hi:0x%x, msi_data:0x%x\n",
- __func__, cmd->ring_msi_addr_lo, cmd->ring_msi_addr_hi,
- cmd->msi_data);
-
- ath11k_dbg(ab, ATH11k_DBG_HAL,
- "ring_id:%d, ring_type:%d, intr_info:0x%x, flags:0x%x\n",
- ring_id, ring_type, cmd->intr_info, cmd->info2);
+ ath11k_dbg(ab, ATH11K_DBG_DP_TX,
+ "htt srng setup msi_addr_lo 0x%x msi_addr_hi 0x%x msi_data 0x%x ring_id %d ring_type %d intr_info 0x%x flags 0x%x\n",
+ cmd->ring_msi_addr_lo, cmd->ring_msi_addr_hi,
+ cmd->msi_data, ring_id, ring_type, cmd->intr_info, cmd->info2);
ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb);
if (ret)
diff --git a/drivers/net/wireless/ath/ath11k/hal.c b/drivers/net/wireless/ath/ath11k/hal.c
index 22422237500c..0a99aa7ddbf4 100644
--- a/drivers/net/wireless/ath/ath11k/hal.c
+++ b/drivers/net/wireless/ath/ath11k/hal.c
@@ -1009,8 +1009,8 @@ int ath11k_hal_srng_setup(struct ath11k_base *ab, enum hal_ring_type type,
srng->u.src_ring.hp_addr =
(u32 *)((unsigned long)ab->mem + reg_base);
else
- ath11k_dbg(ab, ATH11k_DBG_HAL,
- "hal type %d ring_num %d reg_base 0x%x shadow 0x%lx\n",
+ ath11k_dbg(ab, ATH11K_DBG_HAL,
+ "type %d ring_num %d reg_base 0x%x shadow 0x%lx\n",
type, ring_num,
reg_base,
(unsigned long)srng->u.src_ring.hp_addr -
@@ -1043,7 +1043,7 @@ int ath11k_hal_srng_setup(struct ath11k_base *ab, enum hal_ring_type type,
(u32 *)((unsigned long)ab->mem + reg_base +
(HAL_REO1_RING_TP(ab) - HAL_REO1_RING_HP(ab)));
else
- ath11k_dbg(ab, ATH11k_DBG_HAL,
+ ath11k_dbg(ab, ATH11K_DBG_HAL,
"type %d ring_num %d target_reg 0x%x shadow 0x%lx\n",
type, ring_num,
reg_base + (HAL_REO1_RING_TP(ab) -
@@ -1118,8 +1118,8 @@ int ath11k_hal_srng_update_shadow_config(struct ath11k_base *ab,
ath11k_hal_srng_update_hp_tp_addr(ab, shadow_cfg_idx, ring_type,
ring_num);
- ath11k_dbg(ab, ATH11k_DBG_HAL,
- "target_reg %x, shadow reg 0x%x shadow_idx 0x%x, ring_type %d, ring num %d",
+ ath11k_dbg(ab, ATH11K_DBG_HAL,
+ "update shadow config target_reg %x shadow reg 0x%x shadow_idx 0x%x ring_type %d ring num %d",
target_reg,
HAL_SHADOW_REG(ab, shadow_cfg_idx),
shadow_cfg_idx,
diff --git a/drivers/net/wireless/ath/ath11k/hal_rx.c b/drivers/net/wireless/ath/ath11k/hal_rx.c
index bb1d40034aa8..e5ed5efb139e 100644
--- a/drivers/net/wireless/ath/ath11k/hal_rx.c
+++ b/drivers/net/wireless/ath/ath11k/hal_rx.c
@@ -442,54 +442,54 @@ void ath11k_hal_reo_status_queue_stats(struct ath11k_base *ab, u32 *reo_desc,
FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS,
desc->hdr.info0);
- ath11k_dbg(ab, ATH11k_DBG_HAL, "Queue stats status:\n");
- ath11k_dbg(ab, ATH11k_DBG_HAL, "header: cmd_num %d status %d\n",
+ ath11k_dbg(ab, ATH11K_DBG_HAL, "Queue stats status:\n");
+ ath11k_dbg(ab, ATH11K_DBG_HAL, "header: cmd_num %d status %d\n",
status->uniform_hdr.cmd_num,
status->uniform_hdr.cmd_status);
- ath11k_dbg(ab, ATH11k_DBG_HAL, "ssn %ld cur_idx %ld\n",
+ ath11k_dbg(ab, ATH11K_DBG_HAL, "ssn %ld cur_idx %ld\n",
FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_SSN,
desc->info0),
FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_CUR_IDX,
desc->info0));
- ath11k_dbg(ab, ATH11k_DBG_HAL, "pn = [%08x, %08x, %08x, %08x]\n",
+ ath11k_dbg(ab, ATH11K_DBG_HAL, "pn = [%08x, %08x, %08x, %08x]\n",
desc->pn[0], desc->pn[1], desc->pn[2], desc->pn[3]);
- ath11k_dbg(ab, ATH11k_DBG_HAL,
+ ath11k_dbg(ab, ATH11K_DBG_HAL,
"last_rx: enqueue_tstamp %08x dequeue_tstamp %08x\n",
desc->last_rx_enqueue_timestamp,
desc->last_rx_dequeue_timestamp);
- ath11k_dbg(ab, ATH11k_DBG_HAL,
+ ath11k_dbg(ab, ATH11K_DBG_HAL,
"rx_bitmap [%08x %08x %08x %08x %08x %08x %08x %08x]\n",
desc->rx_bitmap[0], desc->rx_bitmap[1], desc->rx_bitmap[2],
desc->rx_bitmap[3], desc->rx_bitmap[4], desc->rx_bitmap[5],
desc->rx_bitmap[6], desc->rx_bitmap[7]);
- ath11k_dbg(ab, ATH11k_DBG_HAL, "count: cur_mpdu %ld cur_msdu %ld\n",
+ ath11k_dbg(ab, ATH11K_DBG_HAL, "count: cur_mpdu %ld cur_msdu %ld\n",
FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MPDU_COUNT,
desc->info1),
FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MSDU_COUNT,
desc->info1));
- ath11k_dbg(ab, ATH11k_DBG_HAL, "fwd_timeout %ld fwd_bar %ld dup_count %ld\n",
+ ath11k_dbg(ab, ATH11K_DBG_HAL, "fwd_timeout %ld fwd_bar %ld dup_count %ld\n",
FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_TIMEOUT_COUNT,
desc->info2),
FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_FDTB_COUNT,
desc->info2),
FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_DUPLICATE_COUNT,
desc->info2));
- ath11k_dbg(ab, ATH11k_DBG_HAL, "frames_in_order %ld bar_rcvd %ld\n",
+ ath11k_dbg(ab, ATH11K_DBG_HAL, "frames_in_order %ld bar_rcvd %ld\n",
FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_FIO_COUNT,
desc->info3),
FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_BAR_RCVD_CNT,
desc->info3));
- ath11k_dbg(ab, ATH11k_DBG_HAL, "num_mpdus %d num_msdus %d total_bytes %d\n",
+ ath11k_dbg(ab, ATH11K_DBG_HAL, "num_mpdus %d num_msdus %d total_bytes %d\n",
desc->num_mpdu_frames, desc->num_msdu_frames,
desc->total_bytes);
- ath11k_dbg(ab, ATH11k_DBG_HAL, "late_rcvd %ld win_jump_2k %ld hole_cnt %ld\n",
+ ath11k_dbg(ab, ATH11K_DBG_HAL, "late_rcvd %ld win_jump_2k %ld hole_cnt %ld\n",
FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_LATE_RX_MPDU,
desc->info4),
FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_WINDOW_JMP2K,
desc->info4),
FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_HOLE_COUNT,
desc->info4));
- ath11k_dbg(ab, ATH11k_DBG_HAL, "looping count %ld\n",
+ ath11k_dbg(ab, ATH11K_DBG_HAL, "looping count %ld\n",
FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO5_LOOPING_CNT,
desc->info5));
}
diff --git a/drivers/net/wireless/ath/ath11k/htc.c b/drivers/net/wireless/ath/ath11k/htc.c
index ca3aedc0252d..2c2e425c8665 100644
--- a/drivers/net/wireless/ath/ath11k/htc.c
+++ b/drivers/net/wireless/ath/ath11k/htc.c
@@ -46,7 +46,6 @@ static struct sk_buff *ath11k_htc_build_tx_ctrl_skb(void *ab)
skb_cb = ATH11K_SKB_CB(skb);
memset(skb_cb, 0, sizeof(*skb_cb));
- ath11k_dbg(ab, ATH11K_DBG_HTC, "%s: skb %pK\n", __func__, skb);
return skb;
}
@@ -96,7 +95,7 @@ int ath11k_htc_send(struct ath11k_htc *htc,
spin_lock_bh(&htc->tx_lock);
if (ep->tx_credits < credits) {
ath11k_dbg(ab, ATH11K_DBG_HTC,
- "htc insufficient credits ep %d required %d available %d\n",
+ "ep %d insufficient credits required %d total %d\n",
eid, credits, ep->tx_credits);
spin_unlock_bh(&htc->tx_lock);
ret = -EAGAIN;
@@ -104,7 +103,7 @@ int ath11k_htc_send(struct ath11k_htc *htc,
}
ep->tx_credits -= credits;
ath11k_dbg(ab, ATH11K_DBG_HTC,
- "htc ep %d consumed %d credits (total %d)\n",
+ "ep %d credits consumed %d total %d\n",
eid, credits, ep->tx_credits);
spin_unlock_bh(&htc->tx_lock);
}
@@ -119,6 +118,9 @@ int ath11k_htc_send(struct ath11k_htc *htc,
goto err_credits;
}
+ ath11k_dbg(ab, ATH11K_DBG_HTC, "tx skb %p eid %d paddr %pad\n",
+ skb, skb_cb->eid, &skb_cb->paddr);
+
ret = ath11k_ce_send(htc->ab, skb, ep->ul_pipe_id, ep->eid);
if (ret)
goto err_unmap;
@@ -132,7 +134,7 @@ err_credits:
spin_lock_bh(&htc->tx_lock);
ep->tx_credits += credits;
ath11k_dbg(ab, ATH11K_DBG_HTC,
- "htc ep %d reverted %d credits back (total %d)\n",
+ "ep %d credits reverted %d total %d\n",
eid, credits, ep->tx_credits);
spin_unlock_bh(&htc->tx_lock);
@@ -167,7 +169,7 @@ ath11k_htc_process_credit_report(struct ath11k_htc *htc,
ep = &htc->endpoint[report->eid];
ep->tx_credits += report->credits;
- ath11k_dbg(ab, ATH11K_DBG_HTC, "htc ep %d got %d credits (total %d)\n",
+ ath11k_dbg(ab, ATH11K_DBG_HTC, "ep %d credits got %d total %d\n",
report->eid, report->credits, ep->tx_credits);
if (ep->ep_ops.ep_tx_credits) {
@@ -239,7 +241,7 @@ static int ath11k_htc_process_trailer(struct ath11k_htc *htc,
static void ath11k_htc_suspend_complete(struct ath11k_base *ab, bool ack)
{
- ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot suspend complete %d\n", ack);
+ ath11k_dbg(ab, ATH11K_DBG_BOOT, "suspend complete %d\n", ack);
if (ack)
set_bit(ATH11K_FLAG_HTC_SUSPEND_COMPLETE, &ab->dev_flags);
@@ -276,7 +278,7 @@ void ath11k_htc_tx_completion_handler(struct ath11k_base *ab,
static void ath11k_htc_wakeup_from_suspend(struct ath11k_base *ab)
{
- ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot wakeup from suspend is received\n");
+ ath11k_dbg(ab, ATH11K_DBG_BOOT, "wakeup from suspend is received\n");
}
void ath11k_htc_rx_completion_handler(struct ath11k_base *ab,
@@ -287,7 +289,7 @@ void ath11k_htc_rx_completion_handler(struct ath11k_base *ab,
struct ath11k_htc_hdr *hdr;
struct ath11k_htc_ep *ep;
u16 payload_len;
- u32 trailer_len = 0;
+ u32 message_id, trailer_len = 0;
size_t min_len;
u8 eid;
bool trailer_present;
@@ -322,6 +324,9 @@ void ath11k_htc_rx_completion_handler(struct ath11k_base *ab,
trailer_present = (FIELD_GET(HTC_HDR_FLAGS, hdr->htc_info)) &
ATH11K_HTC_FLAG_TRAILER_PRESENT;
+ ath11k_dbg(ab, ATH11K_DBG_HTC, "rx ep %d skb %p trailer_present %d\n",
+ eid, skb, trailer_present);
+
if (trailer_present) {
u8 *trailer;
@@ -354,7 +359,12 @@ void ath11k_htc_rx_completion_handler(struct ath11k_base *ab,
if (eid == ATH11K_HTC_EP_0) {
struct ath11k_htc_msg *msg = (struct ath11k_htc_msg *)skb->data;
- switch (FIELD_GET(HTC_MSG_MESSAGEID, msg->msg_svc_id)) {
+ message_id = FIELD_GET(HTC_MSG_MESSAGEID, msg->msg_svc_id);
+
+ ath11k_dbg(ab, ATH11K_DBG_HTC, "rx ep %d skb %p message_id %d\n",
+ eid, skb, message_id);
+
+ switch (message_id) {
case ATH11K_HTC_MSG_READY_ID:
case ATH11K_HTC_MSG_CONNECT_SERVICE_RESP_ID:
/* handle HTC control message */
@@ -393,8 +403,6 @@ void ath11k_htc_rx_completion_handler(struct ath11k_base *ab,
goto out;
}
- ath11k_dbg(ab, ATH11K_DBG_HTC, "htc rx completion ep %d skb %pK\n",
- eid, skb);
ep->ep_ops.ep_rx_complete(ab, skb);
/* poll tx completion for interrupt disabled CE's */
@@ -564,7 +572,7 @@ int ath11k_htc_wait_target(struct ath11k_htc *htc)
htc->target_credit_size = credit_size;
ath11k_dbg(ab, ATH11K_DBG_HTC,
- "Target ready! transmit resources: %d size:%d\n",
+ "target ready total_transmit_credits %d target_credit_size %d\n",
htc->total_transmit_credits, htc->target_credit_size);
if ((htc->total_transmit_credits == 0) ||
@@ -615,7 +623,7 @@ int ath11k_htc_connect_service(struct ath11k_htc *htc,
conn_req->service_id);
if (!tx_alloc)
ath11k_dbg(ab, ATH11K_DBG_BOOT,
- "boot htc service %s does not allocate target credits\n",
+ "htc service %s does not allocate target credits\n",
htc_service_name(conn_req->service_id));
skb = ath11k_htc_build_tx_ctrl_skb(htc->ab);
@@ -680,7 +688,7 @@ int ath11k_htc_connect_service(struct ath11k_htc *htc,
}
ath11k_dbg(ab, ATH11K_DBG_HTC,
- "HTC Service %s connect response: status: 0x%lx, assigned ep: 0x%lx\n",
+ "service %s connect response status 0x%lx assigned ep 0x%lx\n",
htc_service_name(service_id),
FIELD_GET(HTC_SVC_RESP_MSG_STATUS, resp_msg->flags_len),
FIELD_GET(HTC_SVC_RESP_MSG_ENDPOINTID, resp_msg->flags_len));
@@ -740,14 +748,14 @@ setup:
return status;
ath11k_dbg(ab, ATH11K_DBG_BOOT,
- "boot htc service '%s' ul pipe %d dl pipe %d eid %d ready\n",
+ "htc service '%s' ul pipe %d dl pipe %d eid %d ready\n",
htc_service_name(ep->service_id), ep->ul_pipe_id,
ep->dl_pipe_id, ep->eid);
if (disable_credit_flow_ctrl && ep->tx_credit_flow_enabled) {
ep->tx_credit_flow_enabled = false;
ath11k_dbg(ab, ATH11K_DBG_BOOT,
- "boot htc service '%s' eid %d TX flow control disabled\n",
+ "htc service '%s' eid %d tx flow control disabled\n",
htc_service_name(ep->service_id), assigned_eid);
}
@@ -773,7 +781,7 @@ int ath11k_htc_start(struct ath11k_htc *htc)
ATH11K_HTC_MSG_SETUP_COMPLETE_EX_ID);
if (ab->hw_params.credit_flow)
- ath11k_dbg(ab, ATH11K_DBG_HTC, "HTC is using TX credit flow control\n");
+ ath11k_dbg(ab, ATH11K_DBG_HTC, "using tx credit flow control\n");
else
msg->flags |= ATH11K_GLOBAL_DISABLE_CREDIT_FLOW;
diff --git a/drivers/net/wireless/ath/ath11k/hw.c b/drivers/net/wireless/ath/ath11k/hw.c
index eb995f9cf0fa..d7b5ec6e6904 100644
--- a/drivers/net/wireless/ath/ath11k/hw.c
+++ b/drivers/net/wireless/ath/ath11k/hw.c
@@ -202,6 +202,9 @@ static void ath11k_init_wmi_config_ipq8074(struct ath11k_base *ab,
config->twt_ap_sta_count = 1000;
config->flag1 |= WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64;
config->flag1 |= WMI_RSRC_CFG_FLAG1_ACK_RSSI;
+ config->ema_max_vap_cnt = ab->num_radios;
+ config->ema_max_profile_period = TARGET_EMA_MAX_PROFILE_PERIOD;
+ config->beacon_tx_offload_max_vdev += config->ema_max_vap_cnt;
}
static int ath11k_hw_mac_id_to_pdev_id_ipq8074(struct ath11k_hw_params *hw,
@@ -1175,7 +1178,7 @@ const struct ath11k_hw_ops ipq5018_ops = {
.mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
.rx_desc_mac_addr2_valid = ath11k_hw_ipq9074_rx_desc_mac_addr2_valid,
.rx_desc_mpdu_start_addr2 = ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2,
-
+ .get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector,
};
#define ATH11K_TX_RING_MASK_0 BIT(0)
diff --git a/drivers/net/wireless/ath/ath11k/hw.h b/drivers/net/wireless/ath/ath11k/hw.h
index 6a5dd2dbdb3a..f5533630a7f9 100644
--- a/drivers/net/wireless/ath/ath11k/hw.h
+++ b/drivers/net/wireless/ath/ath11k/hw.h
@@ -64,6 +64,7 @@
#define TARGET_NUM_WDS_ENTRIES 32
#define TARGET_DMA_BURST_SIZE 1
#define TARGET_RX_BATCHMODE 1
+#define TARGET_EMA_MAX_PROFILE_PERIOD 8
#define ATH11K_HW_MAX_QUEUES 4
#define ATH11K_QUEUE_LEN 4096
diff --git a/drivers/net/wireless/ath/ath11k/mac.c b/drivers/net/wireless/ath/ath11k/mac.c
index 1c93f1afccc5..8c77ade49437 100644
--- a/drivers/net/wireless/ath/ath11k/mac.c
+++ b/drivers/net/wireless/ath/ath11k/mac.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause-Clear
/*
* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <net/mac80211.h>
@@ -433,7 +433,7 @@ u8 ath11k_mac_bitrate_to_idx(const struct ieee80211_supported_band *sband,
}
static u32
-ath11k_mac_max_ht_nss(const u8 ht_mcs_mask[IEEE80211_HT_MCS_MASK_LEN])
+ath11k_mac_max_ht_nss(const u8 *ht_mcs_mask)
{
int nss;
@@ -445,7 +445,7 @@ ath11k_mac_max_ht_nss(const u8 ht_mcs_mask[IEEE80211_HT_MCS_MASK_LEN])
}
static u32
-ath11k_mac_max_vht_nss(const u16 vht_mcs_mask[NL80211_VHT_NSS_MAX])
+ath11k_mac_max_vht_nss(const u16 *vht_mcs_mask)
{
int nss;
@@ -457,7 +457,7 @@ ath11k_mac_max_vht_nss(const u16 vht_mcs_mask[NL80211_VHT_NSS_MAX])
}
static u32
-ath11k_mac_max_he_nss(const u16 he_mcs_mask[NL80211_HE_NSS_MAX])
+ath11k_mac_max_he_nss(const u16 *he_mcs_mask)
{
int nss;
@@ -643,7 +643,10 @@ struct ath11k *ath11k_mac_get_ar_by_pdev_id(struct ath11k_base *ab, u32 pdev_id)
return NULL;
for (i = 0; i < ab->num_radios; i++) {
- pdev = rcu_dereference(ab->pdevs_active[i]);
+ if (ab->fw_mode == ATH11K_FIRMWARE_MODE_FTM)
+ pdev = &ab->pdevs[i];
+ else
+ pdev = rcu_dereference(ab->pdevs_active[i]);
if (pdev && pdev->pdev_id == pdev_id)
return (pdev->ar ? pdev->ar : NULL);
@@ -815,7 +818,7 @@ static int ath11k_recalc_rtscts_prot(struct ath11k_vif *arvif)
arvif->rtscts_prot_mode = rts_cts;
- ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac vdev %d recalc rts/cts prot %d\n",
+ ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "vdev %d recalc rts/cts prot %d\n",
arvif->vdev_id, rts_cts);
ret = ath11k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id,
@@ -964,14 +967,14 @@ static int ath11k_mac_monitor_vdev_start(struct ath11k *ar, int vdev_id,
return ret;
}
- ret = ath11k_wmi_vdev_up(ar, vdev_id, 0, ar->mac_addr);
+ ret = ath11k_wmi_vdev_up(ar, vdev_id, 0, ar->mac_addr, NULL, 0, 0);
if (ret) {
ath11k_warn(ar->ab, "failed to put up monitor vdev %i: %d\n",
vdev_id, ret);
goto vdev_stop;
}
- ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac monitor vdev %i started\n",
+ ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "monitor vdev %i started\n",
vdev_id);
return 0;
@@ -1025,7 +1028,7 @@ static int ath11k_mac_monitor_vdev_stop(struct ath11k *ar)
return ret;
}
- ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac monitor vdev %i stopped\n",
+ ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "monitor vdev %i stopped\n",
ar->monitor_vdev_id);
return 0;
@@ -1096,7 +1099,7 @@ static int ath11k_mac_monitor_vdev_create(struct ath11k *ar)
ar->num_created_vdevs++;
set_bit(ATH11K_FLAG_MONITOR_VDEV_CREATED, &ar->monitor_flags);
- ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac monitor vdev %d created\n",
+ ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "monitor vdev %d created\n",
ar->monitor_vdev_id);
return 0;
@@ -1131,7 +1134,7 @@ static int ath11k_mac_monitor_vdev_delete(struct ath11k *ar)
if (time_left == 0) {
ath11k_warn(ar->ab, "Timeout in receiving vdev delete response\n");
} else {
- ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac monitor vdev %d deleted\n",
+ ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "monitor vdev %d deleted\n",
ar->monitor_vdev_id);
ar->allocated_vdev_map &= ~(1LL << ar->monitor_vdev_id);
@@ -1177,7 +1180,7 @@ static int ath11k_mac_monitor_start(struct ath11k *ar)
return ret;
}
- ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac monitor started\n");
+ ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "monitor started\n");
return 0;
}
@@ -1207,7 +1210,7 @@ static int ath11k_mac_monitor_stop(struct ath11k *ar)
return ret;
}
- ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac monitor stopped ret %d\n", ret);
+ ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "monitor stopped ret %d\n", ret);
return 0;
}
@@ -1258,7 +1261,7 @@ static int ath11k_mac_vif_setup_ps(struct ath11k_vif *arvif)
psmode = WMI_STA_PS_MODE_DISABLED;
}
- ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac vdev %d psmode %s\n",
+ ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "vdev %d psmode %s\n",
arvif->vdev_id, psmode ? "enable" : "disable");
ret = ath11k_wmi_pdev_set_ps_mode(ar, arvif->vdev_id, psmode);
@@ -1351,28 +1354,92 @@ err_mon_del:
return ret;
}
-static int ath11k_mac_setup_bcn_tmpl(struct ath11k_vif *arvif)
+static void ath11k_mac_setup_nontx_vif_rsnie(struct ath11k_vif *arvif,
+ bool tx_arvif_rsnie_present,
+ const u8 *profile, u8 profile_len)
{
- struct ath11k *ar = arvif->ar;
- struct ath11k_base *ab = ar->ab;
- struct ieee80211_hw *hw = ar->hw;
- struct ieee80211_vif *vif = arvif->vif;
- struct ieee80211_mutable_offsets offs = {};
- struct sk_buff *bcn;
- struct ieee80211_mgmt *mgmt;
- u8 *ies;
- int ret;
+ if (cfg80211_find_ie(WLAN_EID_RSN, profile, profile_len)) {
+ arvif->rsnie_present = true;
+ } else if (tx_arvif_rsnie_present) {
+ int i;
+ u8 nie_len;
+ const u8 *nie = cfg80211_find_ext_ie(WLAN_EID_EXT_NON_INHERITANCE,
+ profile, profile_len);
+ if (!nie)
+ return;
- if (arvif->vdev_type != WMI_VDEV_TYPE_AP)
- return 0;
+ nie_len = nie[1];
+ nie += 2;
+ for (i = 0; i < nie_len; i++) {
+ if (nie[i] == WLAN_EID_RSN) {
+ arvif->rsnie_present = false;
+ break;
+ }
+ }
+ }
+}
- bcn = ieee80211_beacon_get_template(hw, vif, &offs, 0);
- if (!bcn) {
- ath11k_warn(ab, "failed to get beacon template from mac80211\n");
- return -EPERM;
+static bool ath11k_mac_set_nontx_vif_params(struct ath11k_vif *tx_arvif,
+ struct ath11k_vif *arvif,
+ struct sk_buff *bcn)
+{
+ struct ieee80211_mgmt *mgmt;
+ const u8 *ies, *profile, *next_profile;
+ int ies_len;
+
+ ies = bcn->data + ieee80211_get_hdrlen_from_skb(bcn);
+ mgmt = (struct ieee80211_mgmt *)bcn->data;
+ ies += sizeof(mgmt->u.beacon);
+ ies_len = skb_tail_pointer(bcn) - ies;
+
+ ies = cfg80211_find_ie(WLAN_EID_MULTIPLE_BSSID, ies, ies_len);
+ arvif->rsnie_present = tx_arvif->rsnie_present;
+
+ while (ies) {
+ u8 mbssid_len;
+
+ ies_len -= (2 + ies[1]);
+ mbssid_len = ies[1] - 1;
+ profile = &ies[3];
+
+ while (mbssid_len) {
+ u8 profile_len;
+
+ profile_len = profile[1];
+ next_profile = profile + (2 + profile_len);
+ mbssid_len -= (2 + profile_len);
+
+ profile += 2;
+ profile_len -= (2 + profile[1]);
+ profile += (2 + profile[1]); /* nontx capabilities */
+ profile_len -= (2 + profile[1]);
+ profile += (2 + profile[1]); /* SSID */
+ if (profile[2] == arvif->vif->bss_conf.bssid_index) {
+ profile_len -= 5;
+ profile = profile + 5;
+ ath11k_mac_setup_nontx_vif_rsnie(arvif,
+ tx_arvif->rsnie_present,
+ profile,
+ profile_len);
+ return true;
+ }
+ profile = next_profile;
+ }
+ ies = cfg80211_find_ie(WLAN_EID_MULTIPLE_BSSID, profile,
+ ies_len);
}
+ return false;
+}
+
+static void ath11k_mac_set_vif_params(struct ath11k_vif *arvif,
+ struct sk_buff *bcn)
+{
+ struct ieee80211_mgmt *mgmt;
+ u8 *ies;
+
ies = bcn->data + ieee80211_get_hdrlen_from_skb(bcn);
+ mgmt = (struct ieee80211_mgmt *)bcn->data;
ies += sizeof(mgmt->u.beacon);
if (cfg80211_find_ie(WLAN_EID_RSN, ies, (skb_tail_pointer(bcn) - ies)))
@@ -1386,9 +1453,95 @@ static int ath11k_mac_setup_bcn_tmpl(struct ath11k_vif *arvif)
arvif->wpaie_present = true;
else
arvif->wpaie_present = false;
+}
+
+static int ath11k_mac_setup_bcn_tmpl_ema(struct ath11k_vif *arvif)
+{
+ struct ath11k_vif *tx_arvif;
+ struct ieee80211_ema_beacons *beacons;
+ int ret = 0;
+ bool nontx_vif_params_set = false;
+ u32 params = 0;
+ u8 i = 0;
+
+ tx_arvif = (void *)arvif->vif->mbssid_tx_vif->drv_priv;
- ret = ath11k_wmi_bcn_tmpl(ar, arvif->vdev_id, &offs, bcn);
+ beacons = ieee80211_beacon_get_template_ema_list(tx_arvif->ar->hw,
+ tx_arvif->vif, 0);
+ if (!beacons || !beacons->cnt) {
+ ath11k_warn(arvif->ar->ab,
+ "failed to get ema beacon templates from mac80211\n");
+ return -EPERM;
+ }
+ if (tx_arvif == arvif)
+ ath11k_mac_set_vif_params(tx_arvif, beacons->bcn[0].skb);
+ else
+ arvif->wpaie_present = tx_arvif->wpaie_present;
+
+ for (i = 0; i < beacons->cnt; i++) {
+ if (tx_arvif != arvif && !nontx_vif_params_set)
+ nontx_vif_params_set =
+ ath11k_mac_set_nontx_vif_params(tx_arvif, arvif,
+ beacons->bcn[i].skb);
+
+ params = beacons->cnt;
+ params |= (i << WMI_EMA_TMPL_IDX_SHIFT);
+ params |= ((!i ? 1 : 0) << WMI_EMA_FIRST_TMPL_SHIFT);
+ params |= ((i + 1 == beacons->cnt ? 1 : 0) << WMI_EMA_LAST_TMPL_SHIFT);
+
+ ret = ath11k_wmi_bcn_tmpl(tx_arvif->ar, tx_arvif->vdev_id,
+ &beacons->bcn[i].offs,
+ beacons->bcn[i].skb, params);
+ if (ret) {
+ ath11k_warn(tx_arvif->ar->ab,
+ "failed to set ema beacon template id %i error %d\n",
+ i, ret);
+ break;
+ }
+ }
+
+ ieee80211_beacon_free_ema_list(beacons);
+
+ if (tx_arvif != arvif && !nontx_vif_params_set)
+ return -EINVAL; /* Profile not found in the beacons */
+
+ return ret;
+}
+
+static int ath11k_mac_setup_bcn_tmpl_mbssid(struct ath11k_vif *arvif)
+{
+ struct ath11k *ar = arvif->ar;
+ struct ath11k_base *ab = ar->ab;
+ struct ath11k_vif *tx_arvif = arvif;
+ struct ieee80211_hw *hw = ar->hw;
+ struct ieee80211_vif *vif = arvif->vif;
+ struct ieee80211_mutable_offsets offs = {};
+ struct sk_buff *bcn;
+ int ret;
+
+ if (arvif->vif->mbssid_tx_vif) {
+ tx_arvif = (void *)arvif->vif->mbssid_tx_vif->drv_priv;
+ if (tx_arvif != arvif) {
+ ar = tx_arvif->ar;
+ ab = ar->ab;
+ hw = ar->hw;
+ vif = tx_arvif->vif;
+ }
+ }
+
+ bcn = ieee80211_beacon_get_template(hw, vif, &offs, 0);
+ if (!bcn) {
+ ath11k_warn(ab, "failed to get beacon template from mac80211\n");
+ return -EPERM;
+ }
+
+ if (tx_arvif == arvif)
+ ath11k_mac_set_vif_params(tx_arvif, bcn);
+ else if (!ath11k_mac_set_nontx_vif_params(tx_arvif, arvif, bcn))
+ return -EINVAL;
+
+ ret = ath11k_wmi_bcn_tmpl(ar, arvif->vdev_id, &offs, bcn, 0);
kfree_skb(bcn);
if (ret)
@@ -1398,6 +1551,26 @@ static int ath11k_mac_setup_bcn_tmpl(struct ath11k_vif *arvif)
return ret;
}
+static int ath11k_mac_setup_bcn_tmpl(struct ath11k_vif *arvif)
+{
+ struct ieee80211_vif *vif = arvif->vif;
+
+ if (arvif->vdev_type != WMI_VDEV_TYPE_AP)
+ return 0;
+
+ /* Target does not expect beacon templates for the already up
+ * non-transmitting interfaces, and results in a crash if sent.
+ */
+ if (vif->mbssid_tx_vif &&
+ arvif != (void *)vif->mbssid_tx_vif->drv_priv && arvif->is_up)
+ return 0;
+
+ if (vif->bss_conf.ema_ap && vif->mbssid_tx_vif)
+ return ath11k_mac_setup_bcn_tmpl_ema(arvif);
+
+ return ath11k_mac_setup_bcn_tmpl_mbssid(arvif);
+}
+
void ath11k_mac_bcn_tx_event(struct ath11k_vif *arvif)
{
struct ieee80211_vif *vif = arvif->vif;
@@ -1423,6 +1596,7 @@ static void ath11k_control_beaconing(struct ath11k_vif *arvif,
struct ieee80211_bss_conf *info)
{
struct ath11k *ar = arvif->ar;
+ struct ath11k_vif *tx_arvif = NULL;
int ret = 0;
lockdep_assert_held(&arvif->ar->conf_mutex);
@@ -1451,8 +1625,14 @@ static void ath11k_control_beaconing(struct ath11k_vif *arvif,
ether_addr_copy(arvif->bssid, info->bssid);
+ if (arvif->vif->mbssid_tx_vif)
+ tx_arvif = (struct ath11k_vif *)arvif->vif->mbssid_tx_vif->drv_priv;
+
ret = ath11k_wmi_vdev_up(arvif->ar, arvif->vdev_id, arvif->aid,
- arvif->bssid);
+ arvif->bssid,
+ tx_arvif ? tx_arvif->bssid : NULL,
+ info->bssid_index,
+ 1 << info->bssid_indicator);
if (ret) {
ath11k_warn(ar->ab, "failed to bring up vdev %d: %i\n",
arvif->vdev_id, ret);
@@ -1461,7 +1641,7 @@ static void ath11k_control_beaconing(struct ath11k_vif *arvif,
arvif->is_up = true;
- ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac vdev %d up\n", arvif->vdev_id);
+ ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "vdev %d up\n", arvif->vdev_id);
}
static void ath11k_mac_handle_beacon_iter(void *data, u8 *mac,
@@ -1658,7 +1838,7 @@ static void ath11k_peer_assoc_h_rates(struct ath11k *ar,
}
static bool
-ath11k_peer_assoc_h_ht_masked(const u8 ht_mcs_mask[IEEE80211_HT_MCS_MASK_LEN])
+ath11k_peer_assoc_h_ht_masked(const u8 *ht_mcs_mask)
{
int nss;
@@ -1670,7 +1850,7 @@ ath11k_peer_assoc_h_ht_masked(const u8 ht_mcs_mask[IEEE80211_HT_MCS_MASK_LEN])
}
static bool
-ath11k_peer_assoc_h_vht_masked(const u16 vht_mcs_mask[])
+ath11k_peer_assoc_h_vht_masked(const u16 *vht_mcs_mask)
{
int nss;
@@ -1784,7 +1964,7 @@ static void ath11k_peer_assoc_h_ht(struct ath11k *ar,
arg->peer_nss = min(sta->deflink.rx_nss, max_nss);
}
- ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac ht peer %pM mcs cnt %d nss %d\n",
+ ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "ht peer %pM mcs cnt %d nss %d\n",
arg->peer_mac,
arg->peer_ht_rates.num_rates,
arg->peer_nss);
@@ -1948,7 +2128,7 @@ static void ath11k_peer_assoc_h_vht(struct ath11k *ar,
}
if (!user_rate_valid) {
- ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac setting vht range mcs value to peer supported nss %d for peer %pM\n",
+ ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "setting vht range mcs value to peer supported nss %d for peer %pM\n",
sta->deflink.rx_nss, sta->addr);
vht_mcs_mask[sta->deflink.rx_nss - 1] = vht_mcs_mask[vht_nss - 1];
}
@@ -2005,7 +2185,7 @@ static void ath11k_peer_assoc_h_vht(struct ath11k *ar,
}
ath11k_dbg(ar->ab, ATH11K_DBG_MAC,
- "mac vht peer %pM max_mpdu %d flags 0x%x nss_override 0x%x\n",
+ "vht peer %pM max_mpdu %d flags 0x%x nss_override 0x%x\n",
sta->addr, arg->peer_max_mpdu, arg->peer_flags,
arg->peer_bw_rxnss_override);
}
@@ -2065,7 +2245,7 @@ static u16 ath11k_peer_assoc_h_he_limit(u16 tx_mcs_set,
}
static bool
-ath11k_peer_assoc_h_he_masked(const u16 he_mcs_mask[NL80211_HE_NSS_MAX])
+ath11k_peer_assoc_h_he_masked(const u16 *he_mcs_mask)
{
int nss;
@@ -2230,7 +2410,7 @@ static void ath11k_peer_assoc_h_he(struct ath11k *ar,
}
if (!user_rate_valid) {
- ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac setting he range mcs value to peer supported nss %d for peer %pM\n",
+ ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "setting he range mcs value to peer supported nss %d for peer %pM\n",
sta->deflink.rx_nss, sta->addr);
he_mcs_mask[sta->deflink.rx_nss - 1] = he_mcs_mask[he_nss - 1];
}
@@ -2311,7 +2491,7 @@ static void ath11k_peer_assoc_h_he(struct ath11k *ar,
}
ath11k_dbg(ar->ab, ATH11K_DBG_MAC,
- "mac he peer %pM nss %d mcs cnt %d nss_override 0x%x\n",
+ "he peer %pM nss %d mcs cnt %d nss_override 0x%x\n",
sta->addr, arg->peer_nss,
arg->peer_he_mcs_count,
arg->peer_bw_rxnss_override);
@@ -2431,7 +2611,7 @@ static void ath11k_peer_assoc_h_qos(struct ath11k *ar,
break;
}
- ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac peer %pM qos %d\n",
+ ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "peer %pM qos %d\n",
sta->addr, arg->qos_flag);
}
@@ -2448,7 +2628,7 @@ static int ath11k_peer_assoc_qos_ap(struct ath11k *ar,
params.vdev_id = arvif->vdev_id;
- ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac uapsd_queues 0x%x max_sp %d\n",
+ ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "uapsd_queues 0x%x max_sp %d\n",
sta->uapsd_queues, sta->max_sp);
uapsd = 0;
@@ -2634,7 +2814,7 @@ static void ath11k_peer_assoc_h_phymode(struct ath11k *ar,
break;
}
- ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac peer %pM phymode %s\n",
+ ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "peer %pM phymode %s\n",
sta->addr, ath11k_wmi_phymode_str(phymode));
arg->peer_phymode = phymode;
@@ -2825,7 +3005,7 @@ static void ath11k_bss_assoc(struct ieee80211_hw *hw,
lockdep_assert_held(&ar->conf_mutex);
- ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac vdev %i assoc bssid %pM aid %d\n",
+ ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "vdev %i assoc bssid %pM aid %d\n",
arvif->vdev_id, arvif->bssid, arvif->aid);
rcu_read_lock();
@@ -2879,7 +3059,8 @@ static void ath11k_bss_assoc(struct ieee80211_hw *hw,
arvif->aid = vif->cfg.aid;
ether_addr_copy(arvif->bssid, bss_conf->bssid);
- ret = ath11k_wmi_vdev_up(ar, arvif->vdev_id, arvif->aid, arvif->bssid);
+ ret = ath11k_wmi_vdev_up(ar, arvif->vdev_id, arvif->aid, arvif->bssid,
+ NULL, 0, 0);
if (ret) {
ath11k_warn(ar->ab, "failed to set vdev %d up: %d\n",
arvif->vdev_id, ret);
@@ -2890,7 +3071,7 @@ static void ath11k_bss_assoc(struct ieee80211_hw *hw,
arvif->rekey_data.enable_offload = false;
ath11k_dbg(ar->ab, ATH11K_DBG_MAC,
- "mac vdev %d up (associated) bssid %pM aid %d\n",
+ "vdev %d up (associated) bssid %pM aid %d\n",
arvif->vdev_id, bss_conf->bssid, vif->cfg.aid);
spin_lock_bh(&ar->ab->base_lock);
@@ -2935,7 +3116,7 @@ static void ath11k_bss_disassoc(struct ieee80211_hw *hw,
lockdep_assert_held(&ar->conf_mutex);
- ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac vdev %i disassoc bssid %pM\n",
+ ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "vdev %i disassoc bssid %pM\n",
arvif->vdev_id, arvif->bssid);
ret = ath11k_wmi_vdev_down(ar, arvif->vdev_id);
@@ -3084,7 +3265,7 @@ static int ath11k_mac_config_obss_pd(struct ath11k *ar,
}
ath11k_dbg(ar->ab, ATH11K_DBG_MAC,
- "mac obss pd sr_ctrl %x non_srg_thres %u srg_max %u\n",
+ "obss pd sr_ctrl %x non_srg_thres %u srg_max %u\n",
he_obss_pd->sr_ctrl, he_obss_pd->non_srg_max_offset,
he_obss_pd->max_offset);
@@ -3412,7 +3593,7 @@ static void ath11k_mac_op_bss_info_changed(struct ieee80211_hw *hw,
}
if (changed & BSS_CHANGED_TXPOWER) {
- ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac vdev_id %i txpower %d\n",
+ ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "vdev_id %i txpower %d\n",
arvif->vdev_id, info->txpower);
arvif->txpower = info->txpower;
@@ -3453,7 +3634,7 @@ static void ath11k_mac_op_bss_info_changed(struct ieee80211_hw *hw,
rate = ATH11K_HW_RATE_CODE(hw_value, 0, preamble);
ath11k_dbg(ar->ab, ATH11K_DBG_MAC,
- "mac vdev %d mcast_rate %x\n",
+ "vdev %d mcast_rate %x\n",
arvif->vdev_id, rate);
vdev_param = WMI_VDEV_PARAM_MCAST_DATA_RATE;
@@ -3562,7 +3743,7 @@ static void ath11k_mac_op_bss_info_changed(struct ieee80211_hw *hw,
memcpy(arvif->arp_ns_offload.mac_addr, vif->addr, ETH_ALEN);
arvif->arp_ns_offload.ipv4_count = ipv4_cnt;
- ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac arp_addr_cnt %d vif->addr %pM, offload_addr %pI4\n",
+ ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "arp_addr_cnt %d vif->addr %pM, offload_addr %pI4\n",
vif->cfg.arp_addr_cnt,
vif->addr, arvif->arp_ns_offload.ipv4_addr);
}
@@ -4160,6 +4341,20 @@ exit:
}
static int
+ath11k_mac_bitrate_mask_num_ht_rates(struct ath11k *ar,
+ enum nl80211_band band,
+ const struct cfg80211_bitrate_mask *mask)
+{
+ int num_rates = 0;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(mask->control[band].ht_mcs); i++)
+ num_rates += hweight8(mask->control[band].ht_mcs[i]);
+
+ return num_rates;
+}
+
+static int
ath11k_mac_bitrate_mask_num_vht_rates(struct ath11k *ar,
enum nl80211_band band,
const struct cfg80211_bitrate_mask *mask)
@@ -4270,7 +4465,7 @@ ath11k_mac_set_peer_he_fixed_rate(struct ath11k_vif *arvif,
return -EINVAL;
ath11k_dbg(ar->ab, ATH11K_DBG_MAC,
- "mac setting fixed he rate for peer %pM, device will not switch to any other selected rates",
+ "setting fixed he rate for peer %pM, device will not switch to any other selected rates",
sta->addr);
rate_code = ATH11K_HW_RATE_CODE(he_rate, nss - 1,
@@ -4288,6 +4483,54 @@ ath11k_mac_set_peer_he_fixed_rate(struct ath11k_vif *arvif,
return ret;
}
+static int
+ath11k_mac_set_peer_ht_fixed_rate(struct ath11k_vif *arvif,
+ struct ieee80211_sta *sta,
+ const struct cfg80211_bitrate_mask *mask,
+ enum nl80211_band band)
+{
+ struct ath11k *ar = arvif->ar;
+ u8 ht_rate, nss = 0;
+ u32 rate_code;
+ int ret, i;
+
+ lockdep_assert_held(&ar->conf_mutex);
+
+ for (i = 0; i < ARRAY_SIZE(mask->control[band].ht_mcs); i++) {
+ if (hweight8(mask->control[band].ht_mcs[i]) == 1) {
+ nss = i + 1;
+ ht_rate = ffs(mask->control[band].ht_mcs[i]) - 1;
+ }
+ }
+
+ if (!nss) {
+ ath11k_warn(ar->ab, "No single HT Fixed rate found to set for %pM",
+ sta->addr);
+ return -EINVAL;
+ }
+
+ /* Avoid updating invalid nss as fixed rate*/
+ if (nss > sta->deflink.rx_nss)
+ return -EINVAL;
+
+ ath11k_dbg(ar->ab, ATH11K_DBG_MAC,
+ "Setting Fixed HT Rate for peer %pM. Device will not switch to any other selected rates",
+ sta->addr);
+
+ rate_code = ATH11K_HW_RATE_CODE(ht_rate, nss - 1,
+ WMI_RATE_PREAMBLE_HT);
+ ret = ath11k_wmi_set_peer_param(ar, sta->addr,
+ arvif->vdev_id,
+ WMI_PEER_PARAM_FIXED_RATE,
+ rate_code);
+ if (ret)
+ ath11k_warn(ar->ab,
+ "failed to update STA %pM HT Fixed Rate %d: %d\n",
+ sta->addr, rate_code, ret);
+
+ return ret;
+}
+
static int ath11k_station_assoc(struct ath11k *ar,
struct ieee80211_vif *vif,
struct ieee80211_sta *sta,
@@ -4299,7 +4542,7 @@ static int ath11k_station_assoc(struct ath11k *ar,
struct cfg80211_chan_def def;
enum nl80211_band band;
struct cfg80211_bitrate_mask *mask;
- u8 num_vht_rates, num_he_rates;
+ u8 num_ht_rates, num_vht_rates, num_he_rates;
lockdep_assert_held(&ar->conf_mutex);
@@ -4327,6 +4570,7 @@ static int ath11k_station_assoc(struct ath11k *ar,
num_vht_rates = ath11k_mac_bitrate_mask_num_vht_rates(ar, band, mask);
num_he_rates = ath11k_mac_bitrate_mask_num_he_rates(ar, band, mask);
+ num_ht_rates = ath11k_mac_bitrate_mask_num_ht_rates(ar, band, mask);
/* If single VHT/HE rate is configured (by set_bitrate_mask()),
* peer_assoc will disable VHT/HE. This is now enabled by a peer specific
@@ -4343,6 +4587,11 @@ static int ath11k_station_assoc(struct ath11k *ar,
band);
if (ret)
return ret;
+ } else if (sta->deflink.ht_cap.ht_supported && num_ht_rates == 1) {
+ ret = ath11k_mac_set_peer_ht_fixed_rate(arvif, sta, mask,
+ band);
+ if (ret)
+ return ret;
}
/* Re-assoc is run only to update supported rates for given station. It
@@ -4416,7 +4665,7 @@ static void ath11k_sta_rc_update_wk(struct work_struct *wk)
const u16 *vht_mcs_mask;
const u16 *he_mcs_mask;
u32 changed, bw, nss, smps, bw_prev;
- int err, num_vht_rates, num_he_rates;
+ int err, num_ht_rates, num_vht_rates, num_he_rates;
const struct cfg80211_bitrate_mask *mask;
struct peer_assoc_params peer_arg;
enum wmi_phy_mode peer_phymode;
@@ -4458,14 +4707,14 @@ static void ath11k_sta_rc_update_wk(struct work_struct *wk)
ath11k_peer_assoc_h_phymode(ar, arvif->vif, sta, &peer_arg);
peer_phymode = peer_arg.peer_phymode;
- ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac update sta %pM peer bw %d phymode %d\n",
+ ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "update sta %pM peer bw %d phymode %d\n",
sta->addr, bw, peer_phymode);
if (bw > bw_prev) {
/* BW is upgraded. In this case we send WMI_PEER_PHYMODE
* followed by WMI_PEER_CHWIDTH
*/
- ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac BW upgrade for sta %pM new BW %d, old BW %d\n",
+ ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "BW upgrade for sta %pM new BW %d, old BW %d\n",
sta->addr, bw, bw_prev);
err = ath11k_wmi_set_peer_param(ar, sta->addr, arvif->vdev_id,
@@ -4487,7 +4736,7 @@ static void ath11k_sta_rc_update_wk(struct work_struct *wk)
/* BW is downgraded. In this case we send WMI_PEER_CHWIDTH
* followed by WMI_PEER_PHYMODE
*/
- ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac BW downgrade for sta %pM new BW %d,old BW %d\n",
+ ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "BW downgrade for sta %pM new BW %d,old BW %d\n",
sta->addr, bw, bw_prev);
err = ath11k_wmi_set_peer_param(ar, sta->addr, arvif->vdev_id,
@@ -4509,7 +4758,7 @@ static void ath11k_sta_rc_update_wk(struct work_struct *wk)
}
if (changed & IEEE80211_RC_NSS_CHANGED) {
- ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac update sta %pM nss %d\n",
+ ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "update sta %pM nss %d\n",
sta->addr, nss);
err = ath11k_wmi_set_peer_param(ar, sta->addr, arvif->vdev_id,
@@ -4520,7 +4769,7 @@ static void ath11k_sta_rc_update_wk(struct work_struct *wk)
}
if (changed & IEEE80211_RC_SMPS_CHANGED) {
- ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac update sta %pM smps %d\n",
+ ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "update sta %pM smps %d\n",
sta->addr, smps);
err = ath11k_wmi_set_peer_param(ar, sta->addr, arvif->vdev_id,
@@ -4532,6 +4781,8 @@ static void ath11k_sta_rc_update_wk(struct work_struct *wk)
if (changed & IEEE80211_RC_SUPP_RATES_CHANGED) {
mask = &arvif->bitrate_mask;
+ num_ht_rates = ath11k_mac_bitrate_mask_num_ht_rates(ar, band,
+ mask);
num_vht_rates = ath11k_mac_bitrate_mask_num_vht_rates(ar, band,
mask);
num_he_rates = ath11k_mac_bitrate_mask_num_he_rates(ar, band,
@@ -4554,6 +4805,9 @@ static void ath11k_sta_rc_update_wk(struct work_struct *wk)
} else if (sta->deflink.he_cap.has_he && num_he_rates == 1) {
ath11k_mac_set_peer_he_fixed_rate(arvif, sta, mask,
band);
+ } else if (sta->deflink.ht_cap.ht_supported && num_ht_rates == 1) {
+ ath11k_mac_set_peer_ht_fixed_rate(arvif, sta, mask,
+ band);
} else {
/* If the peer is non-VHT/HE or no fixed VHT/HE rate
* is provided in the new bitrate mask we set the
@@ -4973,7 +5227,7 @@ static void ath11k_mac_op_sta_rc_update(struct ieee80211_hw *hw,
spin_unlock_bh(&ar->ab->base_lock);
ath11k_dbg(ar->ab, ATH11K_DBG_MAC,
- "mac sta rc update for %pM changed %08x bw %d nss %d smps %d\n",
+ "sta rc update for %pM changed %08x bw %d nss %d smps %d\n",
sta->addr, changed, sta->deflink.bandwidth,
sta->deflink.rx_nss,
sta->deflink.smps_mode);
@@ -5784,7 +6038,7 @@ static int ath11k_mac_mgmt_tx_wmi(struct ath11k *ar, struct ath11k_vif *arvif,
spin_unlock_bh(&ar->txmgmt_idr_lock);
ath11k_dbg(ar->ab, ATH11K_DBG_MAC,
- "mac tx mgmt frame, buf id %d\n", buf_id);
+ "tx mgmt frame, buf id %d\n", buf_id);
if (buf_id < 0)
return -ENOSPC;
@@ -5861,7 +6115,7 @@ static void ath11k_mgmt_over_wmi_tx_work(struct work_struct *work)
ath11k_mgmt_over_wmi_tx_drop(ar, skb);
} else {
ath11k_dbg(ar->ab, ATH11K_DBG_MAC,
- "mac tx mgmt frame, vdev_id %d\n",
+ "tx mgmt frame, vdev_id %d\n",
arvif->vdev_id);
}
} else {
@@ -6020,6 +6274,11 @@ static int ath11k_mac_op_start(struct ieee80211_hw *hw)
struct ath11k_pdev *pdev = ar->pdev;
int ret;
+ if (ath11k_ftm_mode) {
+ ath11k_warn(ab, "mac operations not supported in factory test mode\n");
+ return -EOPNOTSUPP;
+ }
+
ath11k_mac_drain_tx(ar);
mutex_lock(&ar->conf_mutex);
@@ -6034,6 +6293,7 @@ static int ath11k_mac_op_start(struct ieee80211_hw *hw)
case ATH11K_STATE_RESTARTED:
case ATH11K_STATE_WEDGED:
case ATH11K_STATE_ON:
+ case ATH11K_STATE_FTM:
WARN_ON(1);
ret = -EINVAL;
goto err;
@@ -6181,17 +6441,62 @@ static void ath11k_mac_op_stop(struct ieee80211_hw *hw)
atomic_set(&ar->num_pending_mgmt_tx, 0);
}
-static void
-ath11k_mac_setup_vdev_create_params(struct ath11k_vif *arvif,
- struct vdev_create_params *params)
+static int ath11k_mac_setup_vdev_params_mbssid(struct ath11k_vif *arvif,
+ u32 *flags, u32 *tx_vdev_id)
+{
+ struct ath11k *ar = arvif->ar;
+ struct ath11k_vif *tx_arvif;
+ struct ieee80211_vif *tx_vif;
+
+ *tx_vdev_id = 0;
+ tx_vif = arvif->vif->mbssid_tx_vif;
+ if (!tx_vif) {
+ *flags = WMI_HOST_VDEV_FLAGS_NON_MBSSID_AP;
+ return 0;
+ }
+
+ tx_arvif = (void *)tx_vif->drv_priv;
+
+ if (arvif->vif->bss_conf.nontransmitted) {
+ if (ar->hw->wiphy != ieee80211_vif_to_wdev(tx_vif)->wiphy)
+ return -EINVAL;
+
+ *flags = WMI_HOST_VDEV_FLAGS_NON_TRANSMIT_AP;
+ *tx_vdev_id = ath11k_vif_to_arvif(tx_vif)->vdev_id;
+ } else if (tx_arvif == arvif) {
+ *flags = WMI_HOST_VDEV_FLAGS_TRANSMIT_AP;
+ } else {
+ return -EINVAL;
+ }
+
+ if (arvif->vif->bss_conf.ema_ap)
+ *flags |= WMI_HOST_VDEV_FLAGS_EMA_MODE;
+
+ return 0;
+}
+
+static int ath11k_mac_setup_vdev_create_params(struct ath11k_vif *arvif,
+ struct vdev_create_params *params)
{
struct ath11k *ar = arvif->ar;
struct ath11k_pdev *pdev = ar->pdev;
+ int ret;
params->if_id = arvif->vdev_id;
params->type = arvif->vdev_type;
params->subtype = arvif->vdev_subtype;
params->pdev_id = pdev->pdev_id;
+ params->mbssid_flags = 0;
+ params->mbssid_tx_vdev_id = 0;
+
+ if (!test_bit(WMI_TLV_SERVICE_MBSS_PARAM_IN_VDEV_START_SUPPORT,
+ ar->ab->wmi_ab.svc_map)) {
+ ret = ath11k_mac_setup_vdev_params_mbssid(arvif,
+ &params->mbssid_flags,
+ &params->mbssid_tx_vdev_id);
+ if (ret)
+ return ret;
+ }
if (pdev->cap.supported_bands & WMI_HOST_WLAN_2G_CAP) {
params->chains[NL80211_BAND_2GHZ].tx = ar->num_tx_chains;
@@ -6206,6 +6511,7 @@ ath11k_mac_setup_vdev_create_params(struct ath11k_vif *arvif,
params->chains[NL80211_BAND_6GHZ].tx = ar->num_tx_chains;
params->chains[NL80211_BAND_6GHZ].rx = ar->num_rx_chains;
}
+ return 0;
}
static void ath11k_mac_op_update_vif_offload(struct ieee80211_hw *hw,
@@ -6281,7 +6587,7 @@ void ath11k_mac_11d_scan_start(struct ath11k *ar, u32 vdev_id)
mutex_lock(&ar->ab->vdev_id_11d_lock);
- ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac vdev id for 11d scan %d\n",
+ ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "vdev id for 11d scan %d\n",
ar->vdev_id_11d_scan);
if (ar->regdom_set_by_user)
@@ -6300,7 +6606,7 @@ void ath11k_mac_11d_scan_start(struct ath11k *ar, u32 vdev_id)
param.start_interval_msec = 0;
param.scan_period_msec = ATH11K_SCAN_11D_INTERVAL;
- ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac start 11d scan\n");
+ ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "start 11d scan\n");
ret = ath11k_wmi_send_11d_scan_start_cmd(ar, &param);
if (ret) {
@@ -6329,11 +6635,11 @@ void ath11k_mac_11d_scan_stop(struct ath11k *ar)
if (!test_bit(WMI_TLV_SERVICE_11D_OFFLOAD, ar->ab->wmi_ab.svc_map))
return;
- ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac stop 11d scan\n");
+ ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "stop 11d scan\n");
mutex_lock(&ar->ab->vdev_id_11d_lock);
- ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac stop 11d vdev id %d\n",
+ ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "stop 11d vdev id %d\n",
ar->vdev_id_11d_scan);
if (ar->state_11d == ATH11K_11D_PREPARING) {
@@ -6364,7 +6670,7 @@ void ath11k_mac_11d_scan_stop_all(struct ath11k_base *ab)
struct ath11k_pdev *pdev;
int i;
- ath11k_dbg(ab, ATH11K_DBG_MAC, "mac stop soc 11d scan\n");
+ ath11k_dbg(ab, ATH11K_DBG_MAC, "stop soc 11d scan\n");
for (i = 0; i < ab->num_radios; i++) {
pdev = &ab->pdevs[i];
@@ -6492,7 +6798,7 @@ static int ath11k_mac_op_add_interface(struct ieee80211_hw *hw,
break;
}
- ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac add interface id %d type %d subtype %d map %llx\n",
+ ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "add interface id %d type %d subtype %d map %llx\n",
arvif->vdev_id, arvif->vdev_type, arvif->vdev_subtype,
ab->free_vdev_map);
@@ -6500,7 +6806,12 @@ static int ath11k_mac_op_add_interface(struct ieee80211_hw *hw,
for (i = 0; i < ARRAY_SIZE(vif->hw_queue); i++)
vif->hw_queue[i] = i % (ATH11K_HW_MAX_QUEUES - 1);
- ath11k_mac_setup_vdev_create_params(arvif, &vdev_param);
+ ret = ath11k_mac_setup_vdev_create_params(arvif, &vdev_param);
+ if (ret) {
+ ath11k_warn(ab, "failed to create vdev parameters %d: %d\n",
+ arvif->vdev_id, ret);
+ goto err;
+ }
ret = ath11k_wmi_vdev_create(ar, vif->addr, &vdev_param);
if (ret) {
@@ -6678,7 +6989,7 @@ static void ath11k_mac_op_remove_interface(struct ieee80211_hw *hw,
mutex_lock(&ar->conf_mutex);
- ath11k_dbg(ab, ATH11K_DBG_MAC, "mac remove interface (vdev %d)\n",
+ ath11k_dbg(ab, ATH11K_DBG_MAC, "remove interface (vdev %d)\n",
arvif->vdev_id);
ret = ath11k_spectral_vif_stop(arvif);
@@ -6833,7 +7144,7 @@ static int ath11k_mac_op_add_chanctx(struct ieee80211_hw *hw,
struct ath11k_base *ab = ar->ab;
ath11k_dbg(ab, ATH11K_DBG_MAC,
- "mac chanctx add freq %u width %d ptr %pK\n",
+ "chanctx add freq %u width %d ptr %p\n",
ctx->def.chan->center_freq, ctx->def.width, ctx);
mutex_lock(&ar->conf_mutex);
@@ -6857,7 +7168,7 @@ static void ath11k_mac_op_remove_chanctx(struct ieee80211_hw *hw,
struct ath11k_base *ab = ar->ab;
ath11k_dbg(ab, ATH11K_DBG_MAC,
- "mac chanctx remove freq %u width %d ptr %pK\n",
+ "chanctx remove freq %u width %d ptr %p\n",
ctx->def.chan->center_freq, ctx->def.width, ctx);
mutex_lock(&ar->conf_mutex);
@@ -6905,6 +7216,17 @@ ath11k_mac_vdev_start_restart(struct ath11k_vif *arvif,
arg.pref_tx_streams = ar->num_tx_chains;
arg.pref_rx_streams = ar->num_rx_chains;
+ arg.mbssid_flags = 0;
+ arg.mbssid_tx_vdev_id = 0;
+ if (test_bit(WMI_TLV_SERVICE_MBSS_PARAM_IN_VDEV_START_SUPPORT,
+ ar->ab->wmi_ab.svc_map)) {
+ ret = ath11k_mac_setup_vdev_params_mbssid(arvif,
+ &arg.mbssid_flags,
+ &arg.mbssid_tx_vdev_id);
+ if (ret)
+ return ret;
+ }
+
if (arvif->vdev_type == WMI_VDEV_TYPE_AP) {
arg.ssid = arvif->u.ap.ssid;
arg.ssid_len = arvif->u.ap.ssid_len;
@@ -6926,7 +7248,7 @@ ath11k_mac_vdev_start_restart(struct ath11k_vif *arvif,
arg.channel.passive |= !!(chandef->chan->flags & IEEE80211_CHAN_NO_IR);
ath11k_dbg(ab, ATH11K_DBG_MAC,
- "mac vdev %d start center_freq %d phymode %s\n",
+ "vdev %d start center_freq %d phymode %s\n",
arg.vdev_id, arg.channel.freq,
ath11k_wmi_phymode_str(arg.channel.mode));
@@ -7071,7 +7393,8 @@ ath11k_mac_update_vif_chan(struct ath11k *ar,
int n_vifs)
{
struct ath11k_base *ab = ar->ab;
- struct ath11k_vif *arvif;
+ struct ath11k_vif *arvif, *tx_arvif = NULL;
+ struct ieee80211_vif *mbssid_tx_vif;
int ret;
int i;
bool monitor_vif = false;
@@ -7125,8 +7448,15 @@ ath11k_mac_update_vif_chan(struct ath11k *ar,
ath11k_warn(ab, "failed to update bcn tmpl during csa: %d\n",
ret);
+ mbssid_tx_vif = arvif->vif->mbssid_tx_vif;
+ if (mbssid_tx_vif)
+ tx_arvif = (struct ath11k_vif *)mbssid_tx_vif->drv_priv;
+
ret = ath11k_wmi_vdev_up(arvif->ar, arvif->vdev_id, arvif->aid,
- arvif->bssid);
+ arvif->bssid,
+ tx_arvif ? tx_arvif->bssid : NULL,
+ arvif->vif->bss_conf.bssid_index,
+ 1 << arvif->vif->bss_conf.bssid_indicator);
if (ret) {
ath11k_warn(ab, "failed to bring vdev up %d: %d\n",
arvif->vdev_id, ret);
@@ -7192,7 +7522,7 @@ static void ath11k_mac_op_change_chanctx(struct ieee80211_hw *hw,
mutex_lock(&ar->conf_mutex);
ath11k_dbg(ab, ATH11K_DBG_MAC,
- "mac chanctx change freq %u width %d ptr %pK changed %x\n",
+ "chanctx change freq %u width %d ptr %p changed %x\n",
ctx->def.chan->center_freq, ctx->def.width, ctx, changed);
/* This shouldn't really happen because channel switching should use
@@ -7244,7 +7574,8 @@ static int ath11k_start_vdev_delay(struct ieee80211_hw *hw,
}
if (arvif->vdev_type == WMI_VDEV_TYPE_MONITOR) {
- ret = ath11k_wmi_vdev_up(ar, arvif->vdev_id, 0, ar->mac_addr);
+ ret = ath11k_wmi_vdev_up(ar, arvif->vdev_id, 0, ar->mac_addr,
+ NULL, 0, 0);
if (ret) {
ath11k_warn(ab, "failed put monitor up: %d\n", ret);
return ret;
@@ -7272,7 +7603,7 @@ ath11k_mac_op_assign_vif_chanctx(struct ieee80211_hw *hw,
mutex_lock(&ar->conf_mutex);
ath11k_dbg(ab, ATH11K_DBG_MAC,
- "mac chanctx assign ptr %pK vdev_id %i\n",
+ "chanctx assign ptr %p vdev_id %i\n",
ctx, arvif->vdev_id);
/* for QCA6390 bss peer must be created before vdev_start */
@@ -7362,7 +7693,7 @@ ath11k_mac_op_unassign_vif_chanctx(struct ieee80211_hw *hw,
mutex_lock(&ar->conf_mutex);
ath11k_dbg(ab, ATH11K_DBG_MAC,
- "mac chanctx unassign ptr %pK vdev_id %i\n",
+ "chanctx unassign ptr %p vdev_id %i\n",
ctx, arvif->vdev_id);
WARN_ON(!arvif->is_started);
@@ -7406,7 +7737,7 @@ ath11k_mac_op_unassign_vif_chanctx(struct ieee80211_hw *hw,
arvif->bssid, arvif->vdev_id, ret);
else
ath11k_dbg(ar->ab, ATH11K_DBG_MAC,
- "mac removed peer %pM vdev %d after vdev stop\n",
+ "removed peer %pM vdev %d after vdev stop\n",
arvif->bssid, arvif->vdev_id);
}
@@ -7441,7 +7772,7 @@ ath11k_mac_op_switch_vif_chanctx(struct ieee80211_hw *hw,
mutex_lock(&ar->conf_mutex);
ath11k_dbg(ar->ab, ATH11K_DBG_MAC,
- "mac chanctx switch n_vifs %d mode %d\n",
+ "chanctx switch n_vifs %d mode %d\n",
n_vifs, mode);
ath11k_mac_update_vif_chan(ar, vifs, n_vifs);
@@ -7542,20 +7873,6 @@ static void ath11k_mac_op_flush(struct ieee80211_hw *hw, struct ieee80211_vif *v
ath11k_mac_flush_tx_complete(ar);
}
-static int
-ath11k_mac_bitrate_mask_num_ht_rates(struct ath11k *ar,
- enum nl80211_band band,
- const struct cfg80211_bitrate_mask *mask)
-{
- int num_rates = 0;
- int i;
-
- for (i = 0; i < ARRAY_SIZE(mask->control[band].ht_mcs); i++)
- num_rates += hweight16(mask->control[band].ht_mcs[i]);
-
- return num_rates;
-}
-
static bool
ath11k_mac_has_single_legacy_rate(struct ath11k *ar,
enum nl80211_band band,
@@ -7787,7 +8104,7 @@ static int ath11k_mac_set_rate_params(struct ath11k_vif *arvif,
lockdep_assert_held(&ar->conf_mutex);
ath11k_dbg(ar->ab, ATH11K_DBG_MAC,
- "mac set rate params vdev %i rate 0x%02x nss 0x%02x sgi 0x%02x ldpc 0x%02x he_gi 0x%02x he_ltf 0x%02x he_fixed_rate %d\n",
+ "set rate params vdev %i rate 0x%02x nss 0x%02x sgi 0x%02x ldpc 0x%02x he_gi 0x%02x he_ltf 0x%02x he_fixed_rate %d\n",
arvif->vdev_id, rate, nss, sgi, ldpc, he_gi,
he_ltf, he_fixed_rate);
@@ -8292,7 +8609,7 @@ static void ath11k_mac_put_chain_rssi(struct station_info *sinfo,
arsta->chain_signal[i] = ATH11K_INVALID_RSSI_FULL;
ath11k_dbg(ar->ab, ATH11K_DBG_MAC,
- "mac sta statistics %s rssi[%d] %d\n", pre, i, rssi);
+ "sta statistics %s rssi[%d] %d\n", pre, i, rssi);
if (rssi != ATH11K_DEFAULT_NOISE_FLOOR &&
rssi != ATH11K_INVALID_RSSI_FULL &&
@@ -8356,7 +8673,7 @@ static void ath11k_mac_op_sta_statistics(struct ieee80211_hw *hw,
signal = arsta->rssi_beacon;
ath11k_dbg(ar->ab, ATH11K_DBG_MAC,
- "mac sta statistics db2dbm %u rssi comb %d rssi beacon %d\n",
+ "sta statistics db2dbm %u rssi comb %d rssi beacon %d\n",
db2dbm, arsta->rssi_comb, arsta->rssi_beacon);
if (signal) {
@@ -8403,7 +8720,7 @@ static void ath11k_mac_op_ipv6_changed(struct ieee80211_hw *hw,
struct list_head *p;
u32 count, scope;
- ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac op ipv6 changed\n");
+ ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "op ipv6 changed\n");
offload = &arvif->arp_ns_offload;
count = 0;
@@ -8428,7 +8745,7 @@ static void ath11k_mac_op_ipv6_changed(struct ieee80211_hw *hw,
memcpy(offload->ipv6_addr[count], &ifa6->addr.s6_addr,
sizeof(ifa6->addr.s6_addr));
offload->ipv6_type[count] = ATH11K_IPV6_UC_TYPE;
- ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac count %d ipv6 uc %pI6 scope %d\n",
+ ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "count %d ipv6 uc %pI6 scope %d\n",
count, offload->ipv6_addr[count],
scope);
count++;
@@ -8448,7 +8765,7 @@ static void ath11k_mac_op_ipv6_changed(struct ieee80211_hw *hw,
memcpy(offload->ipv6_addr[count], &ifaca6->aca_addr,
sizeof(ifaca6->aca_addr));
offload->ipv6_type[count] = ATH11K_IPV6_AC_TYPE;
- ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac count %d ipv6 ac %pI6 scope %d\n",
+ ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "count %d ipv6 ac %pI6 scope %d\n",
count, offload->ipv6_addr[count],
scope);
count++;
@@ -8474,7 +8791,7 @@ static void ath11k_mac_op_set_rekey_data(struct ieee80211_hw *hw,
struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif);
struct ath11k_rekey_data *rekey_data = &arvif->rekey_data;
- ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac set rekey data vdev %d\n",
+ ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "set rekey data vdev %d\n",
arvif->vdev_id);
mutex_lock(&ar->conf_mutex);
@@ -8892,7 +9209,7 @@ static int ath11k_mac_setup_channels_rates(struct ath11k *ar,
}
if (supported_bands & WMI_HOST_WLAN_5G_CAP) {
- if (reg_cap->high_5ghz_chan >= ATH11K_MAX_6G_FREQ) {
+ if (reg_cap->high_5ghz_chan >= ATH11K_MIN_6G_FREQ) {
channels = kmemdup(ath11k_6ghz_channels,
sizeof(ath11k_6ghz_channels), GFP_KERNEL);
if (!channels) {
@@ -9001,19 +9318,23 @@ static int ath11k_mac_setup_iface_combinations(struct ath11k *ar)
static const u8 ath11k_if_types_ext_capa[] = {
[0] = WLAN_EXT_CAPA1_EXT_CHANNEL_SWITCHING,
+ [2] = WLAN_EXT_CAPA3_MULTI_BSSID_SUPPORT,
[7] = WLAN_EXT_CAPA8_OPMODE_NOTIF,
};
static const u8 ath11k_if_types_ext_capa_sta[] = {
[0] = WLAN_EXT_CAPA1_EXT_CHANNEL_SWITCHING,
+ [2] = WLAN_EXT_CAPA3_MULTI_BSSID_SUPPORT,
[7] = WLAN_EXT_CAPA8_OPMODE_NOTIF,
[9] = WLAN_EXT_CAPA10_TWT_REQUESTER_SUPPORT,
};
static const u8 ath11k_if_types_ext_capa_ap[] = {
[0] = WLAN_EXT_CAPA1_EXT_CHANNEL_SWITCHING,
+ [2] = WLAN_EXT_CAPA3_MULTI_BSSID_SUPPORT,
[7] = WLAN_EXT_CAPA8_OPMODE_NOTIF,
[9] = WLAN_EXT_CAPA10_TWT_RESPONDER_SUPPORT,
+ [10] = WLAN_EXT_CAPA11_EMA_SUPPORT,
};
static const struct wiphy_iftype_ext_capab ath11k_iftypes_ext_capa[] = {
@@ -9251,6 +9572,9 @@ static int __ath11k_mac_register(struct ath11k *ar)
wiphy_ext_feature_set(ar->hw->wiphy,
NL80211_EXT_FEATURE_ENABLE_FTM_RESPONDER);
+ ar->hw->wiphy->mbssid_max_interfaces = TARGET_NUM_VDEVS(ab);
+ ar->hw->wiphy->ema_max_profile_periodicity = TARGET_EMA_MAX_PROFILE_PERIOD;
+
ath11k_reg_init(ar);
if (!test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) {
@@ -9468,6 +9792,7 @@ void ath11k_mac_destroy(struct ath11k_base *ab)
if (!ar)
continue;
+ ath11k_fw_stats_free(&ar->fw_stats);
ieee80211_free_hw(ar->hw);
pdev->ar = NULL;
}
diff --git a/drivers/net/wireless/ath/ath11k/mhi.c b/drivers/net/wireless/ath/ath11k/mhi.c
index a62ee05c5409..3ac689f1def4 100644
--- a/drivers/net/wireless/ath/ath11k/mhi.c
+++ b/drivers/net/wireless/ath/ath11k/mhi.c
@@ -211,7 +211,7 @@ void ath11k_mhi_set_mhictrl_reset(struct ath11k_base *ab)
val = ath11k_pcic_read32(ab, MHISTATUS);
- ath11k_dbg(ab, ATH11K_DBG_PCI, "MHISTATUS 0x%x\n", val);
+ ath11k_dbg(ab, ATH11K_DBG_PCI, "mhistatus 0x%x\n", val);
/* Observed on QCA6390 that after SOC_GLOBAL_RESET, MHISTATUS
* has SYSERR bit set and thus need to set MHICTRL_RESET
@@ -263,7 +263,7 @@ static int ath11k_mhi_get_msi(struct ath11k_pci *ab_pci)
if (ret)
return ret;
- ath11k_dbg(ab, ATH11K_DBG_PCI, "Number of assigned MSI for MHI is %d, base vector is %d\n",
+ ath11k_dbg(ab, ATH11K_DBG_PCI, "num_vectors %d base_vector %d\n",
num_vectors, base_vector);
irq = kcalloc(num_vectors, sizeof(int), GFP_KERNEL);
@@ -325,7 +325,7 @@ static void ath11k_mhi_op_status_cb(struct mhi_controller *mhi_cntrl,
{
struct ath11k_base *ab = dev_get_drvdata(mhi_cntrl->cntrl_dev);
- ath11k_dbg(ab, ATH11K_DBG_BOOT, "mhi notify status reason %s\n",
+ ath11k_dbg(ab, ATH11K_DBG_BOOT, "notify status reason %s\n",
ath11k_mhi_op_callback_to_str(cb));
switch (cb) {
diff --git a/drivers/net/wireless/ath/ath11k/pci.c b/drivers/net/wireless/ath/ath11k/pci.c
index 7b33731a50ee..79e2cbe82638 100644
--- a/drivers/net/wireless/ath/ath11k/pci.c
+++ b/drivers/net/wireless/ath/ath11k/pci.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause-Clear
/*
* Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.
- * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/module.h>
@@ -203,10 +203,10 @@ static void ath11k_pci_clear_dbg_registers(struct ath11k_base *ab)
/* read cookie */
val = ath11k_pcic_read32(ab, PCIE_Q6_COOKIE_ADDR);
- ath11k_dbg(ab, ATH11K_DBG_PCI, "cookie:0x%x\n", val);
+ ath11k_dbg(ab, ATH11K_DBG_PCI, "pcie_q6_cookie_addr 0x%x\n", val);
val = ath11k_pcic_read32(ab, WLAON_WARM_SW_ENTRY);
- ath11k_dbg(ab, ATH11K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val);
+ ath11k_dbg(ab, ATH11K_DBG_PCI, "wlaon_warm_sw_entry 0x%x\n", val);
/* TODO: exact time to sleep is uncertain */
mdelay(10);
@@ -218,13 +218,13 @@ static void ath11k_pci_clear_dbg_registers(struct ath11k_base *ab)
mdelay(10);
val = ath11k_pcic_read32(ab, WLAON_WARM_SW_ENTRY);
- ath11k_dbg(ab, ATH11K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val);
+ ath11k_dbg(ab, ATH11K_DBG_PCI, "wlaon_warm_sw_entry 0x%x\n", val);
/* A read clear register. clear the register to prevent
* Q6 from entering wrong code path.
*/
val = ath11k_pcic_read32(ab, WLAON_SOC_RESET_CAUSE_REG);
- ath11k_dbg(ab, ATH11K_DBG_PCI, "soc reset cause:%d\n", val);
+ ath11k_dbg(ab, ATH11K_DBG_PCI, "soc reset cause %d\n", val);
}
static int ath11k_pci_set_link_reg(struct ath11k_base *ab,
@@ -312,14 +312,14 @@ static void ath11k_pci_enable_ltssm(struct ath11k_base *ab)
val = ath11k_pcic_read32(ab, PCIE_PCIE_PARF_LTSSM);
}
- ath11k_dbg(ab, ATH11K_DBG_PCI, "pci ltssm 0x%x\n", val);
+ ath11k_dbg(ab, ATH11K_DBG_PCI, "ltssm 0x%x\n", val);
val = ath11k_pcic_read32(ab, GCC_GCC_PCIE_HOT_RST);
val |= GCC_GCC_PCIE_HOT_RST_VAL;
ath11k_pcic_write32(ab, GCC_GCC_PCIE_HOT_RST, val);
val = ath11k_pcic_read32(ab, GCC_GCC_PCIE_HOT_RST);
- ath11k_dbg(ab, ATH11K_DBG_PCI, "pci pcie_hot_rst 0x%x\n", val);
+ ath11k_dbg(ab, ATH11K_DBG_PCI, "pcie_hot_rst 0x%x\n", val);
mdelay(5);
}
@@ -433,7 +433,7 @@ static int ath11k_pci_alloc_msi(struct ath11k_pci *ab_pci)
}
clear_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags);
ab->pci.msi.config = &msi_config_one_msi;
- ath11k_dbg(ab, ATH11K_DBG_PCI, "request MSI one vector\n");
+ ath11k_dbg(ab, ATH11K_DBG_PCI, "request one msi vector\n");
}
ath11k_info(ab, "MSI vectors: %d\n", num_vectors);
@@ -487,7 +487,7 @@ static int ath11k_pci_config_msi_data(struct ath11k_pci *ab_pci)
ab_pci->ab->pci.msi.ep_base_data = msi_desc->msg.data;
- ath11k_dbg(ab_pci->ab, ATH11K_DBG_PCI, "pci after request_irq msi_ep_base_data %d\n",
+ ath11k_dbg(ab_pci->ab, ATH11K_DBG_PCI, "after request_irq msi_ep_base_data %d\n",
ab_pci->ab->pci.msi.ep_base_data);
return 0;
@@ -545,7 +545,7 @@ static int ath11k_pci_claim(struct ath11k_pci *ab_pci, struct pci_dev *pdev)
ab->mem_ce = ab->mem;
- ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot pci_mem 0x%pK\n", ab->mem);
+ ath11k_dbg(ab, ATH11K_DBG_BOOT, "pci_mem 0x%p\n", ab->mem);
return 0;
release_region:
@@ -575,7 +575,7 @@ static void ath11k_pci_aspm_disable(struct ath11k_pci *ab_pci)
pcie_capability_read_word(ab_pci->pdev, PCI_EXP_LNKCTL,
&ab_pci->link_ctl);
- ath11k_dbg(ab, ATH11K_DBG_PCI, "pci link_ctl 0x%04x L0s %d L1 %d\n",
+ ath11k_dbg(ab, ATH11K_DBG_PCI, "link_ctl 0x%04x L0s %d L1 %d\n",
ab_pci->link_ctl,
u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L0S),
u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L1));
@@ -709,7 +709,7 @@ static void ath11k_pci_read_hw_version(struct ath11k_base *ab, u32 *major, u32 *
*minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK,
soc_hw_version);
- ath11k_dbg(ab, ATH11K_DBG_PCI, "pci tcsr_soc_hw_version major %d minor %d\n",
+ ath11k_dbg(ab, ATH11K_DBG_PCI, "tcsr_soc_hw_version major %d minor %d\n",
*major, *minor);
}
@@ -745,6 +745,7 @@ static int ath11k_pci_probe(struct pci_dev *pdev,
ab_pci->ab = ab;
ab_pci->pdev = pdev;
ab->hif.ops = &ath11k_pci_hif_ops;
+ ab->fw_mode = ATH11K_FIRMWARE_MODE_NORMAL;
pci_set_drvdata(pdev, ab);
spin_lock_init(&ab_pci->window_lock);
diff --git a/drivers/net/wireless/ath/ath11k/pcic.c b/drivers/net/wireless/ath/ath11k/pcic.c
index 30d66147223f..c899616fbee4 100644
--- a/drivers/net/wireless/ath/ath11k/pcic.c
+++ b/drivers/net/wireless/ath/ath11k/pcic.c
@@ -263,7 +263,7 @@ int ath11k_pcic_get_user_msi_assignment(struct ath11k_base *ab, char *user_name,
*user_base_data = *base_vector + ab->pci.msi.ep_base_data;
ath11k_dbg(ab, ATH11K_DBG_PCI,
- "Assign MSI to user: %s, num_vectors: %d, user_base_data: %u, base_vector: %u\n",
+ "msi assignment %s num_vectors %d user_base_data %u base_vector %u\n",
user_name, *num_vectors, *user_base_data,
*base_vector);
@@ -527,7 +527,7 @@ static irqreturn_t ath11k_pcic_ext_interrupt_handler(int irq, void *arg)
if (!test_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags))
return IRQ_HANDLED;
- ath11k_dbg(irq_grp->ab, ATH11K_DBG_PCI, "ext irq:%d\n", irq);
+ ath11k_dbg(irq_grp->ab, ATH11K_DBG_PCI, "ext irq %d\n", irq);
/* last interrupt received for this group */
irq_grp->timestamp = jiffies;
@@ -597,7 +597,7 @@ static int ath11k_pcic_ext_irq_config(struct ath11k_base *ab)
ab->irq_num[irq_idx] = irq;
ath11k_dbg(ab, ATH11K_DBG_PCI,
- "irq:%d group:%d\n", irq, i);
+ "irq %d group %d\n", irq, i);
irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY);
ret = request_irq(irq, ath11k_pcic_ext_interrupt_handler,
diff --git a/drivers/net/wireless/ath/ath11k/peer.c b/drivers/net/wireless/ath/ath11k/peer.c
index 1380811827a8..114aa3a9a339 100644
--- a/drivers/net/wireless/ath/ath11k/peer.c
+++ b/drivers/net/wireless/ath/ath11k/peer.c
@@ -106,7 +106,7 @@ void ath11k_peer_unmap_event(struct ath11k_base *ab, u16 peer_id)
goto exit;
}
- ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "htt peer unmap vdev %d peer %pM id %d\n",
+ ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "peer unmap vdev %d peer %pM id %d\n",
peer->vdev_id, peer->addr, peer_id);
list_del(&peer->list);
@@ -138,7 +138,7 @@ void ath11k_peer_map_event(struct ath11k_base *ab, u8 vdev_id, u16 peer_id,
wake_up(&ab->peer_mapping_wq);
}
- ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "htt peer map vdev %d peer %pM id %d\n",
+ ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "peer map vdev %d peer %pM id %d\n",
vdev_id, mac_addr, peer_id);
exit:
diff --git a/drivers/net/wireless/ath/ath11k/qmi.c b/drivers/net/wireless/ath/ath11k/qmi.c
index 26b252e62909..d4eaf7d2ba84 100644
--- a/drivers/net/wireless/ath/ath11k/qmi.c
+++ b/drivers/net/wireless/ath/ath11k/qmi.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause-Clear
/*
* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/elf.h>
@@ -1755,7 +1755,7 @@ static int ath11k_qmi_host_cap_send(struct ath11k_base *ab)
req.nm_modem |= PLATFORM_CAP_PCIE_PME_D3COLD;
- ath11k_dbg(ab, ATH11K_DBG_QMI, "qmi host cap request\n");
+ ath11k_dbg(ab, ATH11K_DBG_QMI, "host cap request\n");
ret = qmi_txn_init(&ab->qmi.handle, &txn,
qmi_wlanfw_host_cap_resp_msg_v01_ei, &resp);
@@ -1833,7 +1833,7 @@ static int ath11k_qmi_fw_ind_register_send(struct ath11k_base *ab)
if (ret < 0)
goto out;
- ath11k_dbg(ab, ATH11K_DBG_QMI, "qmi indication register request\n");
+ ath11k_dbg(ab, ATH11K_DBG_QMI, "indication register request\n");
ret = qmi_send_request(&ab->qmi.handle, NULL, &txn,
QMI_WLANFW_IND_REGISTER_REQ_V01,
@@ -1889,7 +1889,7 @@ static int ath11k_qmi_respond_fw_mem_request(struct ath11k_base *ab)
test_bit(ATH11K_FLAG_FIXED_MEM_RGN, &ab->dev_flags)) &&
ab->qmi.target_mem_delayed) {
delayed = true;
- ath11k_dbg(ab, ATH11K_DBG_QMI, "qmi delays mem_request %d\n",
+ ath11k_dbg(ab, ATH11K_DBG_QMI, "delays mem_request %d\n",
ab->qmi.mem_seg_count);
memset(req, 0, sizeof(*req));
} else {
@@ -1901,7 +1901,7 @@ static int ath11k_qmi_respond_fw_mem_request(struct ath11k_base *ab)
req->mem_seg[i].size = ab->qmi.target_mem[i].size;
req->mem_seg[i].type = ab->qmi.target_mem[i].type;
ath11k_dbg(ab, ATH11K_DBG_QMI,
- "qmi req mem_seg[%d] %pad %u %u\n", i,
+ "req mem_seg[%d] %pad %u %u\n", i,
&ab->qmi.target_mem[i].paddr,
ab->qmi.target_mem[i].size,
ab->qmi.target_mem[i].type);
@@ -1913,7 +1913,7 @@ static int ath11k_qmi_respond_fw_mem_request(struct ath11k_base *ab)
if (ret < 0)
goto out;
- ath11k_dbg(ab, ATH11K_DBG_QMI, "qmi respond memory request delayed %i\n",
+ ath11k_dbg(ab, ATH11K_DBG_QMI, "respond memory request delayed %i\n",
delayed);
ret = qmi_send_request(&ab->qmi.handle, NULL, &txn,
@@ -2002,7 +2002,7 @@ static int ath11k_qmi_alloc_target_mem_chunk(struct ath11k_base *ab)
if (!chunk->vaddr) {
if (ab->qmi.mem_seg_count <= ATH11K_QMI_FW_MEM_REQ_SEGMENT_CNT) {
ath11k_dbg(ab, ATH11K_DBG_QMI,
- "qmi dma allocation failed (%d B type %u), will try later with small size\n",
+ "dma allocation failed (%d B type %u), will try later with small size\n",
chunk->size,
chunk->type);
ath11k_qmi_free_target_mem_chunk(ab);
@@ -2036,7 +2036,7 @@ static int ath11k_qmi_assign_target_mem_chunk(struct ath11k_base *ab)
hremote_node = of_parse_phandle(dev->of_node, "memory-region", 0);
if (!hremote_node) {
ath11k_dbg(ab, ATH11K_DBG_QMI,
- "qmi fail to get hremote_node\n");
+ "fail to get hremote_node\n");
return -ENODEV;
}
@@ -2044,13 +2044,13 @@ static int ath11k_qmi_assign_target_mem_chunk(struct ath11k_base *ab)
of_node_put(hremote_node);
if (ret) {
ath11k_dbg(ab, ATH11K_DBG_QMI,
- "qmi fail to get reg from hremote\n");
+ "fail to get reg from hremote\n");
return ret;
}
if (res.end - res.start + 1 < ab->qmi.target_mem[i].size) {
ath11k_dbg(ab, ATH11K_DBG_QMI,
- "qmi fail to assign memory of sz\n");
+ "fail to assign memory of sz\n");
return -EINVAL;
}
@@ -2058,6 +2058,9 @@ static int ath11k_qmi_assign_target_mem_chunk(struct ath11k_base *ab)
ab->qmi.target_mem[idx].iaddr =
ioremap(ab->qmi.target_mem[idx].paddr,
ab->qmi.target_mem[i].size);
+ if (!ab->qmi.target_mem[idx].iaddr)
+ return -EIO;
+
ab->qmi.target_mem[idx].size = ab->qmi.target_mem[i].size;
host_ddr_sz = ab->qmi.target_mem[i].size;
ab->qmi.target_mem[idx].type = ab->qmi.target_mem[i].type;
@@ -2083,6 +2086,8 @@ static int ath11k_qmi_assign_target_mem_chunk(struct ath11k_base *ab)
ab->qmi.target_mem[idx].iaddr =
ioremap(ab->qmi.target_mem[idx].paddr,
ab->qmi.target_mem[i].size);
+ if (!ab->qmi.target_mem[idx].iaddr)
+ return -EIO;
} else {
ab->qmi.target_mem[idx].paddr =
ATH11K_QMI_CALDB_ADDRESS;
@@ -2198,7 +2203,7 @@ static int ath11k_qmi_request_target_cap(struct ath11k_base *ab)
if (ret < 0)
goto out;
- ath11k_dbg(ab, ATH11K_DBG_QMI, "qmi target cap request\n");
+ ath11k_dbg(ab, ATH11K_DBG_QMI, "target cap request\n");
ret = qmi_send_request(&ab->qmi.handle, NULL, &txn,
QMI_WLANFW_CAP_REQ_V01,
@@ -2251,7 +2256,7 @@ static int ath11k_qmi_request_target_cap(struct ath11k_base *ab)
if (resp.eeprom_read_timeout_valid) {
ab->qmi.target.eeprom_caldata =
resp.eeprom_read_timeout;
- ath11k_dbg(ab, ATH11K_DBG_QMI, "qmi cal data supported from eeprom\n");
+ ath11k_dbg(ab, ATH11K_DBG_QMI, "cal data supported from eeprom\n");
}
fw_build_id = ab->qmi.target.fw_build_id;
@@ -2348,7 +2353,7 @@ static int ath11k_qmi_load_file_target_mem(struct ath11k_base *ab,
if (ret < 0)
goto err_iounmap;
- ath11k_dbg(ab, ATH11K_DBG_QMI, "qmi bdf download req fixed addr type %d\n",
+ ath11k_dbg(ab, ATH11K_DBG_QMI, "bdf download req fixed addr type %d\n",
type);
ret = qmi_send_request(&ab->qmi.handle, NULL, &txn,
@@ -2381,7 +2386,7 @@ static int ath11k_qmi_load_file_target_mem(struct ath11k_base *ab,
remaining -= req->data_len;
temp += req->data_len;
req->seg_id++;
- ath11k_dbg(ab, ATH11K_DBG_QMI, "qmi bdf download request remaining %i\n",
+ ath11k_dbg(ab, ATH11K_DBG_QMI, "bdf download request remaining %i\n",
remaining);
}
}
@@ -2427,7 +2432,7 @@ static int ath11k_qmi_load_bdf_qmi(struct ath11k_base *ab,
else
bdf_type = ATH11K_QMI_BDF_TYPE_BIN;
- ath11k_dbg(ab, ATH11K_DBG_QMI, "qmi bdf_type %d\n", bdf_type);
+ ath11k_dbg(ab, ATH11K_DBG_QMI, "bdf_type %d\n", bdf_type);
fw_size = min_t(u32, ab->hw_params.fw.board_size, bd.len);
@@ -2457,6 +2462,14 @@ static int ath11k_qmi_load_bdf_qmi(struct ath11k_base *ab,
fw_entry = ath11k_core_firmware_request(ab, ATH11K_DEFAULT_CAL_FILE);
if (IS_ERR(fw_entry)) {
+ /* Caldata may not be present during first time calibration in
+ * factory hence allow to boot without loading caldata in ftm mode
+ */
+ if (ath11k_ftm_mode) {
+ ath11k_info(ab,
+ "Booting without cal data file in factory test mode\n");
+ return 0;
+ }
ret = PTR_ERR(fw_entry);
ath11k_warn(ab,
"qmi failed to load CAL data file:%s\n",
@@ -2474,14 +2487,14 @@ success:
goto out_qmi_cal;
}
- ath11k_dbg(ab, ATH11K_DBG_QMI, "qmi caldata type: %u\n", file_type);
+ ath11k_dbg(ab, ATH11K_DBG_QMI, "caldata type: %u\n", file_type);
out_qmi_cal:
if (!ab->qmi.target.eeprom_caldata)
release_firmware(fw_entry);
out:
ath11k_core_free_bdf(ab, &bd);
- ath11k_dbg(ab, ATH11K_DBG_QMI, "qmi BDF download sequence completed\n");
+ ath11k_dbg(ab, ATH11K_DBG_QMI, "BDF download sequence completed\n");
return ret;
}
@@ -2566,7 +2579,7 @@ static int ath11k_qmi_wlanfw_m3_info_send(struct ath11k_base *ab)
if (ret < 0)
goto out;
- ath11k_dbg(ab, ATH11K_DBG_QMI, "qmi m3 info req\n");
+ ath11k_dbg(ab, ATH11K_DBG_QMI, "m3 info req\n");
ret = qmi_send_request(&ab->qmi.handle, NULL, &txn,
QMI_WLANFW_M3_INFO_REQ_V01,
@@ -2615,7 +2628,7 @@ static int ath11k_qmi_wlanfw_mode_send(struct ath11k_base *ab,
if (ret < 0)
goto out;
- ath11k_dbg(ab, ATH11K_DBG_QMI, "qmi wlan mode req mode %d\n", mode);
+ ath11k_dbg(ab, ATH11K_DBG_QMI, "wlan mode req mode %d\n", mode);
ret = qmi_send_request(&ab->qmi.handle, NULL, &txn,
QMI_WLANFW_WLAN_MODE_REQ_V01,
@@ -2710,7 +2723,7 @@ static int ath11k_qmi_wlanfw_wlan_cfg_send(struct ath11k_base *ab)
if (ret < 0)
goto out;
- ath11k_dbg(ab, ATH11K_DBG_QMI, "qmi wlan cfg req\n");
+ ath11k_dbg(ab, ATH11K_DBG_QMI, "wlan cfg req\n");
ret = qmi_send_request(&ab->qmi.handle, NULL, &txn,
QMI_WLANFW_WLAN_CFG_REQ_V01,
@@ -2787,7 +2800,7 @@ void ath11k_qmi_firmware_stop(struct ath11k_base *ab)
{
int ret;
- ath11k_dbg(ab, ATH11K_DBG_QMI, "qmi firmware stop\n");
+ ath11k_dbg(ab, ATH11K_DBG_QMI, "firmware stop\n");
ret = ath11k_qmi_wlanfw_mode_send(ab, ATH11K_FIRMWARE_MODE_OFF);
if (ret < 0) {
@@ -2801,7 +2814,7 @@ int ath11k_qmi_firmware_start(struct ath11k_base *ab,
{
int ret;
- ath11k_dbg(ab, ATH11K_DBG_QMI, "qmi firmware start\n");
+ ath11k_dbg(ab, ATH11K_DBG_QMI, "firmware start\n");
if (ab->hw_params.fw_wmi_diag_event) {
ret = ath11k_qmi_wlanfw_wlan_ini_send(ab, true);
@@ -2959,7 +2972,7 @@ static void ath11k_qmi_msg_mem_request_cb(struct qmi_handle *qmi_hdl,
const struct qmi_wlanfw_request_mem_ind_msg_v01 *msg = data;
int i, ret;
- ath11k_dbg(ab, ATH11K_DBG_QMI, "qmi firmware request memory request\n");
+ ath11k_dbg(ab, ATH11K_DBG_QMI, "firmware request memory request\n");
if (msg->mem_seg_len == 0 ||
msg->mem_seg_len > ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01)
@@ -2971,7 +2984,7 @@ static void ath11k_qmi_msg_mem_request_cb(struct qmi_handle *qmi_hdl,
for (i = 0; i < qmi->mem_seg_count ; i++) {
ab->qmi.target_mem[i].type = msg->mem_seg[i].type;
ab->qmi.target_mem[i].size = msg->mem_seg[i].size;
- ath11k_dbg(ab, ATH11K_DBG_QMI, "qmi mem seg type %d size %d\n",
+ ath11k_dbg(ab, ATH11K_DBG_QMI, "mem seg type %d size %d\n",
msg->mem_seg[i].type, msg->mem_seg[i].size);
}
@@ -3003,7 +3016,7 @@ static void ath11k_qmi_msg_mem_ready_cb(struct qmi_handle *qmi_hdl,
struct ath11k_qmi *qmi = container_of(qmi_hdl, struct ath11k_qmi, handle);
struct ath11k_base *ab = qmi->ab;
- ath11k_dbg(ab, ATH11K_DBG_QMI, "qmi firmware memory ready indication\n");
+ ath11k_dbg(ab, ATH11K_DBG_QMI, "firmware memory ready indication\n");
ath11k_qmi_driver_event_post(qmi, ATH11K_QMI_EVENT_FW_MEM_READY, NULL);
}
@@ -3015,7 +3028,7 @@ static void ath11k_qmi_msg_fw_ready_cb(struct qmi_handle *qmi_hdl,
struct ath11k_qmi *qmi = container_of(qmi_hdl, struct ath11k_qmi, handle);
struct ath11k_base *ab = qmi->ab;
- ath11k_dbg(ab, ATH11K_DBG_QMI, "qmi firmware ready\n");
+ ath11k_dbg(ab, ATH11K_DBG_QMI, "firmware ready\n");
if (!ab->qmi.cal_done) {
ab->qmi.cal_done = 1;
@@ -3036,7 +3049,7 @@ static void ath11k_qmi_msg_cold_boot_cal_done_cb(struct qmi_handle *qmi_hdl,
ab->qmi.cal_done = 1;
wake_up(&ab->qmi.cold_boot_waitq);
- ath11k_dbg(ab, ATH11K_DBG_QMI, "qmi cold boot calibration done\n");
+ ath11k_dbg(ab, ATH11K_DBG_QMI, "cold boot calibration done\n");
}
static void ath11k_qmi_msg_fw_init_done_cb(struct qmi_handle *qmi_hdl,
@@ -3049,7 +3062,7 @@ static void ath11k_qmi_msg_fw_init_done_cb(struct qmi_handle *qmi_hdl,
struct ath11k_base *ab = qmi->ab;
ath11k_qmi_driver_event_post(qmi, ATH11K_QMI_EVENT_FW_INIT_DONE, NULL);
- ath11k_dbg(ab, ATH11K_DBG_QMI, "qmi firmware init done\n");
+ ath11k_dbg(ab, ATH11K_DBG_QMI, "firmware init done\n");
}
static const struct qmi_msg_handler ath11k_qmi_msg_handlers[] = {
@@ -3114,7 +3127,7 @@ static int ath11k_qmi_ops_new_server(struct qmi_handle *qmi_hdl,
return ret;
}
- ath11k_dbg(ab, ATH11K_DBG_QMI, "qmi wifi fw qmi service connected\n");
+ ath11k_dbg(ab, ATH11K_DBG_QMI, "wifi fw qmi service connected\n");
ath11k_qmi_driver_event_post(qmi, ATH11K_QMI_EVENT_SERVER_ARRIVE, NULL);
return ret;
@@ -3126,7 +3139,7 @@ static void ath11k_qmi_ops_del_server(struct qmi_handle *qmi_hdl,
struct ath11k_qmi *qmi = container_of(qmi_hdl, struct ath11k_qmi, handle);
struct ath11k_base *ab = qmi->ab;
- ath11k_dbg(ab, ATH11K_DBG_QMI, "qmi wifi fw del server\n");
+ ath11k_dbg(ab, ATH11K_DBG_QMI, "wifi fw del server\n");
ath11k_qmi_driver_event_post(qmi, ATH11K_QMI_EVENT_SERVER_EXIT, NULL);
}
diff --git a/drivers/net/wireless/ath/ath11k/reg.c b/drivers/net/wireless/ath/ath11k/reg.c
index 67443457f4da..7f9fb968dac6 100644
--- a/drivers/net/wireless/ath/ath11k/reg.c
+++ b/drivers/net/wireless/ath/ath11k/reg.c
@@ -123,7 +123,7 @@ int ath11k_reg_update_chan_list(struct ath11k *ar, bool wait)
ar->state_11d = ATH11K_11D_IDLE;
}
ath11k_dbg(ar->ab, ATH11K_DBG_REG,
- "reg 11d scan wait left time %d\n", left);
+ "11d scan wait left time %d\n", left);
}
if (wait &&
@@ -136,7 +136,7 @@ int ath11k_reg_update_chan_list(struct ath11k *ar, bool wait)
"failed to receive hw scan complete: timed out\n");
ath11k_dbg(ar->ab, ATH11K_DBG_REG,
- "reg hw scan wait left time %d\n", left);
+ "hw scan wait left time %d\n", left);
}
if (ar->state == ATH11K_STATE_RESTARTING)
diff --git a/drivers/net/wireless/ath/ath11k/testmode.c b/drivers/net/wireless/ath/ath11k/testmode.c
index 4bf1931adbaa..8fc5cddb28bd 100644
--- a/drivers/net/wireless/ath/ath11k/testmode.c
+++ b/drivers/net/wireless/ath/ath11k/testmode.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause-Clear
/*
* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "testmode.h"
@@ -11,6 +12,9 @@
#include "core.h"
#include "testmode_i.h"
+#define ATH11K_FTM_SEGHDR_CURRENT_SEQ GENMASK(3, 0)
+#define ATH11K_FTM_SEGHDR_TOTAL_SEGMENTS GENMASK(7, 4)
+
static const struct nla_policy ath11k_tm_policy[ATH11K_TM_ATTR_MAX + 1] = {
[ATH11K_TM_ATTR_CMD] = { .type = NLA_U32 },
[ATH11K_TM_ATTR_DATA] = { .type = NLA_BINARY,
@@ -20,58 +24,162 @@ static const struct nla_policy ath11k_tm_policy[ATH11K_TM_ATTR_MAX + 1] = {
[ATH11K_TM_ATTR_VERSION_MINOR] = { .type = NLA_U32 },
};
-/* Returns true if callee consumes the skb and the skb should be discarded.
- * Returns false if skb is not used. Does not sleep.
+static struct ath11k *ath11k_tm_get_ar(struct ath11k_base *ab)
+{
+ struct ath11k_pdev *pdev;
+ struct ath11k *ar = NULL;
+ int i;
+
+ for (i = 0; i < ab->num_radios; i++) {
+ pdev = &ab->pdevs[i];
+ ar = pdev->ar;
+
+ if (ar && ar->state == ATH11K_STATE_FTM)
+ break;
+ }
+
+ return ar;
+}
+
+/* This function handles unsegmented events. Data in various events are aggregated
+ * in application layer, this event is unsegmented from host perspective.
*/
-bool ath11k_tm_event_wmi(struct ath11k *ar, u32 cmd_id, struct sk_buff *skb)
+static void ath11k_tm_wmi_event_unsegmented(struct ath11k_base *ab, u32 cmd_id,
+ struct sk_buff *skb)
{
struct sk_buff *nl_skb;
- bool consumed;
- int ret;
+ struct ath11k *ar;
- ath11k_dbg(ar->ab, ATH11K_DBG_TESTMODE,
- "testmode event wmi cmd_id %d skb %pK skb->len %d\n",
- cmd_id, skb, skb->len);
+ ath11k_dbg(ab, ATH11K_DBG_TESTMODE,
+ "event wmi cmd_id %d skb length %d\n",
+ cmd_id, skb->len);
+ ath11k_dbg_dump(ab, ATH11K_DBG_TESTMODE, NULL, "", skb->data, skb->len);
- ath11k_dbg_dump(ar->ab, ATH11K_DBG_TESTMODE, NULL, "", skb->data, skb->len);
+ ar = ath11k_tm_get_ar(ab);
+ if (!ar) {
+ ath11k_warn(ab, "testmode event not handled due to invalid pdev\n");
+ return;
+ }
spin_lock_bh(&ar->data_lock);
- consumed = true;
-
nl_skb = cfg80211_testmode_alloc_event_skb(ar->hw->wiphy,
- 2 * sizeof(u32) + skb->len,
+ 2 * nla_total_size(sizeof(u32)) +
+ nla_total_size(skb->len),
GFP_ATOMIC);
if (!nl_skb) {
- ath11k_warn(ar->ab,
- "failed to allocate skb for testmode wmi event\n");
+ ath11k_warn(ab,
+ "failed to allocate skb for unsegmented testmode wmi event\n");
goto out;
}
- ret = nla_put_u32(nl_skb, ATH11K_TM_ATTR_CMD, ATH11K_TM_CMD_WMI);
- if (ret) {
- ath11k_warn(ar->ab,
- "failed to put testmode wmi event cmd attribute: %d\n",
- ret);
+ if (nla_put_u32(nl_skb, ATH11K_TM_ATTR_CMD, ATH11K_TM_CMD_WMI) ||
+ nla_put_u32(nl_skb, ATH11K_TM_ATTR_WMI_CMDID, cmd_id) ||
+ nla_put(nl_skb, ATH11K_TM_ATTR_DATA, skb->len, skb->data)) {
+ ath11k_warn(ab, "failed to populate testmode unsegmented event\n");
kfree_skb(nl_skb);
goto out;
}
- ret = nla_put_u32(nl_skb, ATH11K_TM_ATTR_WMI_CMDID, cmd_id);
- if (ret) {
- ath11k_warn(ar->ab,
- "failed to put testmode wmi even cmd_id: %d\n",
- ret);
- kfree_skb(nl_skb);
+ cfg80211_testmode_event(nl_skb, GFP_ATOMIC);
+ spin_unlock_bh(&ar->data_lock);
+ return;
+
+out:
+ spin_unlock_bh(&ar->data_lock);
+ ath11k_warn(ab, "Failed to send testmode event to higher layers\n");
+}
+
+/* This function handles segmented events. Data of various events received
+ * from firmware is aggregated and sent to application layer
+ */
+static int ath11k_tm_process_event(struct ath11k_base *ab, u32 cmd_id,
+ const struct wmi_ftm_event_msg *ftm_msg,
+ u16 length)
+{
+ struct sk_buff *nl_skb;
+ int ret = 0;
+ struct ath11k *ar;
+ u8 const *buf_pos;
+ u16 datalen;
+ u8 total_segments, current_seq;
+ u32 data_pos;
+ u32 pdev_id;
+
+ ath11k_dbg(ab, ATH11K_DBG_TESTMODE,
+ "event wmi cmd_id %d ftm event msg %pK datalen %d\n",
+ cmd_id, ftm_msg, length);
+ ath11k_dbg_dump(ab, ATH11K_DBG_TESTMODE, NULL, "", ftm_msg, length);
+ pdev_id = DP_HW2SW_MACID(ftm_msg->seg_hdr.pdev_id);
+
+ if (pdev_id >= ab->num_radios) {
+ ath11k_warn(ab, "testmode event not handled due to invalid pdev id: %d\n",
+ pdev_id);
+ return -EINVAL;
+ }
+
+ ar = ab->pdevs[pdev_id].ar;
+ if (!ar) {
+ ath11k_warn(ab, "testmode event not handled due to absence of pdev\n");
+ return -ENODEV;
+ }
+
+ current_seq = FIELD_GET(ATH11K_FTM_SEGHDR_CURRENT_SEQ,
+ ftm_msg->seg_hdr.segmentinfo);
+ total_segments = FIELD_GET(ATH11K_FTM_SEGHDR_TOTAL_SEGMENTS,
+ ftm_msg->seg_hdr.segmentinfo);
+ datalen = length - (sizeof(struct wmi_ftm_seg_hdr));
+ buf_pos = ftm_msg->data;
+
+ spin_lock_bh(&ar->data_lock);
+
+ if (current_seq == 0) {
+ ab->testmode.expected_seq = 0;
+ ab->testmode.data_pos = 0;
+ }
+
+ data_pos = ab->testmode.data_pos;
+
+ if ((data_pos + datalen) > ATH11K_FTM_EVENT_MAX_BUF_LENGTH) {
+ ath11k_warn(ab, "Invalid ftm event length at %d: %d\n",
+ data_pos, datalen);
+ ret = -EINVAL;
goto out;
}
- ret = nla_put(nl_skb, ATH11K_TM_ATTR_DATA, skb->len, skb->data);
- if (ret) {
- ath11k_warn(ar->ab,
- "failed to copy skb to testmode wmi event: %d\n",
- ret);
+ memcpy(&ab->testmode.eventdata[data_pos], buf_pos, datalen);
+ data_pos += datalen;
+
+ if (++ab->testmode.expected_seq != total_segments) {
+ ab->testmode.data_pos = data_pos;
+ ath11k_dbg(ab, ATH11K_DBG_TESTMODE,
+ "partial data received current_seq %d total_seg %d\n",
+ current_seq, total_segments);
+ goto out;
+ }
+
+ ath11k_dbg(ab, ATH11K_DBG_TESTMODE,
+ "total data length pos %d len %d\n",
+ data_pos, ftm_msg->seg_hdr.len);
+ nl_skb = cfg80211_testmode_alloc_event_skb(ar->hw->wiphy,
+ 2 * nla_total_size(sizeof(u32)) +
+ nla_total_size(data_pos),
+ GFP_ATOMIC);
+ if (!nl_skb) {
+ ath11k_warn(ab,
+ "failed to allocate skb for segmented testmode wmi event\n");
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ if (nla_put_u32(nl_skb, ATH11K_TM_ATTR_CMD,
+ ATH11K_TM_CMD_WMI_FTM) ||
+ nla_put_u32(nl_skb, ATH11K_TM_ATTR_WMI_CMDID, cmd_id) ||
+ nla_put(nl_skb, ATH11K_TM_ATTR_DATA, data_pos,
+ &ab->testmode.eventdata[0])) {
+ ath11k_warn(ab, "failed to populate segmented testmode event");
kfree_skb(nl_skb);
+ ret = -ENOBUFS;
goto out;
}
@@ -79,8 +187,45 @@ bool ath11k_tm_event_wmi(struct ath11k *ar, u32 cmd_id, struct sk_buff *skb)
out:
spin_unlock_bh(&ar->data_lock);
+ return ret;
+}
+
+static void ath11k_tm_wmi_event_segmented(struct ath11k_base *ab, u32 cmd_id,
+ struct sk_buff *skb)
+{
+ const void **tb;
+ const struct wmi_ftm_event_msg *ev;
+ u16 length;
+ int ret;
+
+ tb = ath11k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC);
+ if (IS_ERR(tb)) {
+ ret = PTR_ERR(tb);
+ ath11k_warn(ab, "failed to parse ftm event tlv: %d\n", ret);
+ return;
+ }
+
+ ev = tb[WMI_TAG_ARRAY_BYTE];
+ if (!ev) {
+ ath11k_warn(ab, "failed to fetch ftm msg\n");
+ kfree(tb);
+ return;
+ }
- return consumed;
+ length = skb->len - TLV_HDR_SIZE;
+ ret = ath11k_tm_process_event(ab, cmd_id, ev, length);
+ if (ret)
+ ath11k_warn(ab, "Failed to process ftm event\n");
+
+ kfree(tb);
+}
+
+void ath11k_tm_wmi_event(struct ath11k_base *ab, u32 cmd_id, struct sk_buff *skb)
+{
+ if (test_bit(ATH11K_FLAG_FTM_SEGMENTED, &ab->dev_flags))
+ ath11k_tm_wmi_event_segmented(ab, cmd_id, skb);
+ else
+ ath11k_tm_wmi_event_unsegmented(ab, cmd_id, skb);
}
static int ath11k_tm_cmd_get_version(struct ath11k *ar, struct nlattr *tb[])
@@ -89,7 +234,7 @@ static int ath11k_tm_cmd_get_version(struct ath11k *ar, struct nlattr *tb[])
int ret;
ath11k_dbg(ar->ab, ATH11K_DBG_TESTMODE,
- "testmode cmd get version_major %d version_minor %d\n",
+ "cmd get version_major %d version_minor %d\n",
ATH11K_TESTMODE_VERSION_MAJOR,
ATH11K_TESTMODE_VERSION_MINOR);
@@ -115,21 +260,56 @@ static int ath11k_tm_cmd_get_version(struct ath11k *ar, struct nlattr *tb[])
return cfg80211_testmode_reply(skb);
}
-static int ath11k_tm_cmd_wmi(struct ath11k *ar, struct nlattr *tb[])
+static int ath11k_tm_cmd_testmode_start(struct ath11k *ar, struct nlattr *tb[])
+{
+ int ret;
+
+ mutex_lock(&ar->conf_mutex);
+
+ if (ar->state == ATH11K_STATE_FTM) {
+ ret = -EALREADY;
+ goto err;
+ }
+
+ /* start utf only when the driver is not in use */
+ if (ar->state != ATH11K_STATE_OFF) {
+ ret = -EBUSY;
+ goto err;
+ }
+
+ ar->ab->testmode.eventdata = kzalloc(ATH11K_FTM_EVENT_MAX_BUF_LENGTH,
+ GFP_KERNEL);
+ if (!ar->ab->testmode.eventdata) {
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ ar->state = ATH11K_STATE_FTM;
+ ar->ftm_msgref = 0;
+
+ mutex_unlock(&ar->conf_mutex);
+
+ ath11k_dbg(ar->ab, ATH11K_DBG_TESTMODE, "cmd start\n");
+ return 0;
+
+err:
+ mutex_unlock(&ar->conf_mutex);
+ return ret;
+}
+
+static int ath11k_tm_cmd_wmi(struct ath11k *ar, struct nlattr *tb[],
+ struct ieee80211_vif *vif)
{
struct ath11k_pdev_wmi *wmi = ar->wmi;
struct sk_buff *skb;
+ struct ath11k_vif *arvif;
u32 cmd_id, buf_len;
- int ret;
+ int ret, tag;
void *buf;
+ u32 *ptr;
mutex_lock(&ar->conf_mutex);
- if (ar->state != ATH11K_STATE_ON) {
- ret = -ENETDOWN;
- goto out;
- }
-
if (!tb[ATH11K_TM_ATTR_DATA]) {
ret = -EINVAL;
goto out;
@@ -142,11 +322,45 @@ static int ath11k_tm_cmd_wmi(struct ath11k *ar, struct nlattr *tb[])
buf = nla_data(tb[ATH11K_TM_ATTR_DATA]);
buf_len = nla_len(tb[ATH11K_TM_ATTR_DATA]);
+ if (!buf_len) {
+ ath11k_warn(ar->ab, "No data present in testmode wmi command\n");
+ ret = -EINVAL;
+ goto out;
+ }
+
cmd_id = nla_get_u32(tb[ATH11K_TM_ATTR_WMI_CMDID]);
+ /* Make sure that the buffer length is long enough to
+ * hold TLV and pdev/vdev id.
+ */
+ if (buf_len < sizeof(struct wmi_tlv) + sizeof(u32)) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ ptr = buf;
+ tag = FIELD_GET(WMI_TLV_TAG, *ptr);
+
+ /* pdev/vdev id start after TLV header */
+ ptr++;
+
+ if (tag == WMI_TAG_PDEV_SET_PARAM_CMD)
+ *ptr = ar->pdev->pdev_id;
+
+ if (ar->ab->fw_mode != ATH11K_FIRMWARE_MODE_FTM &&
+ (tag == WMI_TAG_VDEV_SET_PARAM_CMD || tag == WMI_TAG_UNIT_TEST_CMD)) {
+ if (vif) {
+ arvif = (struct ath11k_vif *)vif->drv_priv;
+ *ptr = arvif->vdev_id;
+ } else {
+ ret = -EINVAL;
+ goto out;
+ }
+ }
+
ath11k_dbg(ar->ab, ATH11K_DBG_TESTMODE,
- "testmode cmd wmi cmd_id %d buf %pK buf_len %d\n",
- cmd_id, buf, buf_len);
+ "cmd wmi cmd_id %d buf length %d\n",
+ cmd_id, buf_len);
ath11k_dbg_dump(ar->ab, ATH11K_DBG_TESTMODE, NULL, "", buf, buf_len);
@@ -173,6 +387,91 @@ out:
return ret;
}
+static int ath11k_tm_cmd_wmi_ftm(struct ath11k *ar, struct nlattr *tb[])
+{
+ struct ath11k_pdev_wmi *wmi = ar->wmi;
+ struct ath11k_base *ab = ar->ab;
+ struct sk_buff *skb;
+ u32 cmd_id, buf_len, hdr_info;
+ int ret;
+ void *buf;
+ u8 segnumber = 0, seginfo;
+ u16 chunk_len, total_bytes, num_segments;
+ u8 *bufpos;
+ struct wmi_ftm_cmd *ftm_cmd;
+
+ set_bit(ATH11K_FLAG_FTM_SEGMENTED, &ab->dev_flags);
+
+ mutex_lock(&ar->conf_mutex);
+
+ if (ar->state != ATH11K_STATE_FTM) {
+ ret = -ENETDOWN;
+ goto out;
+ }
+
+ if (!tb[ATH11K_TM_ATTR_DATA]) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ buf = nla_data(tb[ATH11K_TM_ATTR_DATA]);
+ buf_len = nla_len(tb[ATH11K_TM_ATTR_DATA]);
+ cmd_id = WMI_PDEV_UTF_CMDID;
+
+ ath11k_dbg(ar->ab, ATH11K_DBG_TESTMODE,
+ "cmd wmi ftm cmd_id %d buffer length %d\n",
+ cmd_id, buf_len);
+ ath11k_dbg_dump(ar->ab, ATH11K_DBG_TESTMODE, NULL, "", buf, buf_len);
+
+ bufpos = buf;
+ total_bytes = buf_len;
+ num_segments = total_bytes / MAX_WMI_UTF_LEN;
+
+ if (buf_len - (num_segments * MAX_WMI_UTF_LEN))
+ num_segments++;
+
+ while (buf_len) {
+ chunk_len = min_t(u16, buf_len, MAX_WMI_UTF_LEN);
+
+ skb = ath11k_wmi_alloc_skb(wmi->wmi_ab, (chunk_len +
+ sizeof(struct wmi_ftm_cmd)));
+ if (!skb) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ ftm_cmd = (struct wmi_ftm_cmd *)skb->data;
+ hdr_info = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_ARRAY_BYTE) |
+ FIELD_PREP(WMI_TLV_LEN, (chunk_len +
+ sizeof(struct wmi_ftm_seg_hdr)));
+ ftm_cmd->tlv_header = hdr_info;
+ ftm_cmd->seg_hdr.len = total_bytes;
+ ftm_cmd->seg_hdr.msgref = ar->ftm_msgref;
+ seginfo = FIELD_PREP(ATH11K_FTM_SEGHDR_TOTAL_SEGMENTS, num_segments) |
+ FIELD_PREP(ATH11K_FTM_SEGHDR_CURRENT_SEQ, segnumber);
+ ftm_cmd->seg_hdr.segmentinfo = seginfo;
+ segnumber++;
+
+ memcpy(&ftm_cmd->data, bufpos, chunk_len);
+
+ ret = ath11k_wmi_cmd_send(wmi, skb, cmd_id);
+ if (ret) {
+ ath11k_warn(ar->ab, "failed to send wmi ftm command: %d\n", ret);
+ goto out;
+ }
+
+ buf_len -= chunk_len;
+ bufpos += chunk_len;
+ }
+
+ ar->ftm_msgref++;
+ ret = 0;
+
+out:
+ mutex_unlock(&ar->conf_mutex);
+ return ret;
+}
+
int ath11k_tm_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
void *data, int len)
{
@@ -192,7 +491,11 @@ int ath11k_tm_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
case ATH11K_TM_CMD_GET_VERSION:
return ath11k_tm_cmd_get_version(ar, tb);
case ATH11K_TM_CMD_WMI:
- return ath11k_tm_cmd_wmi(ar, tb);
+ return ath11k_tm_cmd_wmi(ar, tb, vif);
+ case ATH11K_TM_CMD_TESTMODE_START:
+ return ath11k_tm_cmd_testmode_start(ar, tb);
+ case ATH11K_TM_CMD_WMI_FTM:
+ return ath11k_tm_cmd_wmi_ftm(ar, tb);
default:
return -EOPNOTSUPP;
}
diff --git a/drivers/net/wireless/ath/ath11k/testmode.h b/drivers/net/wireless/ath/ath11k/testmode.h
index aaa122ed9069..2f62f2c4422f 100644
--- a/drivers/net/wireless/ath/ath11k/testmode.h
+++ b/drivers/net/wireless/ath/ath11k/testmode.h
@@ -1,22 +1,22 @@
/* SPDX-License-Identifier: BSD-3-Clause-Clear */
/*
* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "core.h"
#ifdef CONFIG_NL80211_TESTMODE
-bool ath11k_tm_event_wmi(struct ath11k *ar, u32 cmd_id, struct sk_buff *skb);
+void ath11k_tm_wmi_event(struct ath11k_base *ab, u32 cmd_id, struct sk_buff *skb);
int ath11k_tm_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
void *data, int len);
#else
-static inline bool ath11k_tm_event_wmi(struct ath11k *ar, u32 cmd_id,
+static inline void ath11k_tm_wmi_event(struct ath11k_base *ab, u32 cmd_id,
struct sk_buff *skb)
{
- return false;
}
static inline int ath11k_tm_cmd(struct ieee80211_hw *hw,
diff --git a/drivers/net/wireless/ath/ath11k/testmode_i.h b/drivers/net/wireless/ath/ath11k/testmode_i.h
index 4bae2a9eeea4..91b83873d660 100644
--- a/drivers/net/wireless/ath/ath11k/testmode_i.h
+++ b/drivers/net/wireless/ath/ath11k/testmode_i.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: BSD-3-Clause-Clear */
/*
* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/* "API" level of the ath11k testmode interface. Bump it after every
@@ -11,9 +12,10 @@
/* Bump this after every _compatible_ interface change, for example
* addition of a new command or an attribute.
*/
-#define ATH11K_TESTMODE_VERSION_MINOR 0
+#define ATH11K_TESTMODE_VERSION_MINOR 1
#define ATH11K_TM_DATA_MAX_LEN 5000
+#define ATH11K_FTM_EVENT_MAX_BUF_LENGTH 2048
enum ath11k_tm_attr {
__ATH11K_TM_ATTR_INVALID = 0,
@@ -47,4 +49,18 @@ enum ath11k_tm_cmd {
* ATH11K_TM_ATTR_DATA.
*/
ATH11K_TM_CMD_WMI = 1,
+
+ /* Boots the UTF firmware, the netdev interface must be down at the
+ * time.
+ */
+ ATH11K_TM_CMD_TESTMODE_START = 2,
+
+ /* The command used to transmit a FTM WMI command to the firmware
+ * and the event to receive WMI events from the firmware. The data
+ * received only contain the payload, need to add the tlv header
+ * and send the cmd to firmware with command id WMI_PDEV_UTF_CMDID.
+ * The data payload size could be large and the driver needs to
+ * send segmented data to firmware.
+ */
+ ATH11K_TM_CMD_WMI_FTM = 3,
};
diff --git a/drivers/net/wireless/ath/ath11k/wmi.c b/drivers/net/wireless/ath/ath11k/wmi.c
index d0b59bc2905a..23ad6825e5be 100644
--- a/drivers/net/wireless/ath/ath11k/wmi.c
+++ b/drivers/net/wireless/ath/ath11k/wmi.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause-Clear
/*
* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
- * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021, 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/skbuff.h>
#include <linux/ctype.h>
@@ -19,6 +19,7 @@
#include "mac.h"
#include "hw.h"
#include "peer.h"
+#include "testmode.h"
struct wmi_tlv_policy {
size_t min_len;
@@ -237,9 +238,8 @@ static int ath11k_wmi_tlv_parse(struct ath11k_base *ar, const void **tb,
(void *)tb);
}
-static const void **
-ath11k_wmi_tlv_parse_alloc(struct ath11k_base *ab, const void *ptr,
- size_t len, gfp_t gfp)
+const void **ath11k_wmi_tlv_parse_alloc(struct ath11k_base *ab, const void *ptr,
+ size_t len, gfp_t gfp)
{
const void **tb;
int ret;
@@ -606,6 +606,8 @@ static int ath11k_service_ready_event(struct ath11k_base *ab, struct sk_buff *sk
return ret;
}
+ ath11k_dbg(ab, ATH11K_DBG_WMI, "event service ready");
+
return 0;
}
@@ -690,6 +692,8 @@ int ath11k_wmi_mgmt_send(struct ath11k *ar, u32 vdev_id, u32 buf_id,
dev_kfree_skb(skb);
}
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "cmd mgmt tx send");
+
return ret;
}
@@ -724,6 +728,9 @@ int ath11k_wmi_vdev_create(struct ath11k *ar, u8 *macaddr,
cmd->vdev_subtype = param->subtype;
cmd->num_cfg_txrx_streams = WMI_NUM_SUPPORTED_BAND_MAX;
cmd->pdev_id = param->pdev_id;
+ cmd->mbssid_flags = param->mbssid_flags;
+ cmd->mbssid_tx_vdev_id = param->mbssid_tx_vdev_id;
+
ether_addr_copy(cmd->vdev_macaddr.addr, macaddr);
ptr = skb->data + sizeof(*cmd);
@@ -763,7 +770,7 @@ int ath11k_wmi_vdev_create(struct ath11k *ar, u8 *macaddr,
}
ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "WMI vdev create: id %d type %d subtype %d macaddr %pM pdevid %d\n",
+ "cmd vdev create id %d type %d subtype %d macaddr %pM pdevid %d\n",
param->if_id, param->type, param->subtype,
macaddr, param->pdev_id);
@@ -792,7 +799,7 @@ int ath11k_wmi_vdev_delete(struct ath11k *ar, u8 vdev_id)
dev_kfree_skb(skb);
}
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "WMI vdev delete id %d\n", vdev_id);
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "cmd vdev delete id %d\n", vdev_id);
return ret;
}
@@ -820,7 +827,7 @@ int ath11k_wmi_vdev_stop(struct ath11k *ar, u8 vdev_id)
dev_kfree_skb(skb);
}
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "WMI vdev stop id 0x%x\n", vdev_id);
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "cmd vdev stop id 0x%x\n", vdev_id);
return ret;
}
@@ -848,7 +855,7 @@ int ath11k_wmi_vdev_down(struct ath11k *ar, u8 vdev_id)
dev_kfree_skb(skb);
}
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "WMI vdev down id 0x%x\n", vdev_id);
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "cmd vdev down id 0x%x\n", vdev_id);
return ret;
}
@@ -941,6 +948,8 @@ int ath11k_wmi_vdev_start(struct ath11k *ar, struct wmi_vdev_start_req_arg *arg,
cmd->cac_duration_ms = arg->cac_duration_ms;
cmd->regdomain = arg->regdomain;
cmd->he_ops = arg->he_ops;
+ cmd->mbssid_flags = arg->mbssid_flags;
+ cmd->mbssid_tx_vdev_id = arg->mbssid_tx_vdev_id;
if (!restart) {
if (arg->ssid) {
@@ -989,14 +998,15 @@ int ath11k_wmi_vdev_start(struct ath11k *ar, struct wmi_vdev_start_req_arg *arg,
dev_kfree_skb(skb);
}
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "vdev %s id 0x%x freq 0x%x mode 0x%x\n",
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "cmd vdev %s id 0x%x freq 0x%x mode 0x%x\n",
restart ? "restart" : "start", arg->vdev_id,
arg->channel.freq, arg->channel.mode);
return ret;
}
-int ath11k_wmi_vdev_up(struct ath11k *ar, u32 vdev_id, u32 aid, const u8 *bssid)
+int ath11k_wmi_vdev_up(struct ath11k *ar, u32 vdev_id, u32 aid, const u8 *bssid,
+ u8 *tx_bssid, u32 nontx_profile_idx, u32 nontx_profile_cnt)
{
struct ath11k_pdev_wmi *wmi = ar->wmi;
struct wmi_vdev_up_cmd *cmd;
@@ -1020,14 +1030,19 @@ int ath11k_wmi_vdev_up(struct ath11k *ar, u32 vdev_id, u32 aid, const u8 *bssid)
ether_addr_copy(cmd->vdev_bssid.addr, bssid);
+ cmd->nontx_profile_idx = nontx_profile_idx;
+ cmd->nontx_profile_cnt = nontx_profile_cnt;
+ if (tx_bssid)
+ ether_addr_copy(cmd->tx_vdev_bssid.addr, tx_bssid);
+
if (arvif && arvif->vif->type == NL80211_IFTYPE_STATION) {
bss_conf = &arvif->vif->bss_conf;
if (bss_conf->nontransmitted) {
- ether_addr_copy(cmd->trans_bssid.addr,
+ ether_addr_copy(cmd->tx_vdev_bssid.addr,
bss_conf->transmitter_bssid);
- cmd->profile_idx = bss_conf->bssid_index;
- cmd->profile_num = bss_conf->bssid_indicator;
+ cmd->nontx_profile_idx = bss_conf->bssid_index;
+ cmd->nontx_profile_cnt = bss_conf->bssid_indicator;
}
}
@@ -1038,7 +1053,7 @@ int ath11k_wmi_vdev_up(struct ath11k *ar, u32 vdev_id, u32 aid, const u8 *bssid)
}
ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "WMI mgmt vdev up id 0x%x assoc id %d bssid %pM\n",
+ "cmd vdev up id 0x%x assoc id %d bssid %pM\n",
vdev_id, aid, bssid);
return ret;
@@ -1071,7 +1086,7 @@ int ath11k_wmi_send_peer_create_cmd(struct ath11k *ar,
}
ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "WMI peer create vdev_id %d peer_addr %pM\n",
+ "cmd peer create vdev_id %d peer_addr %pM\n",
param->vdev_id, param->peer_addr);
return ret;
@@ -1096,16 +1111,16 @@ int ath11k_wmi_send_peer_delete_cmd(struct ath11k *ar,
ether_addr_copy(cmd->peer_macaddr.addr, peer_addr);
cmd->vdev_id = vdev_id;
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "WMI peer delete vdev_id %d peer_addr %pM\n",
- vdev_id, peer_addr);
-
ret = ath11k_wmi_cmd_send(wmi, skb, WMI_PEER_DELETE_CMDID);
if (ret) {
ath11k_warn(ar->ab, "failed to send WMI_PEER_DELETE cmd\n");
dev_kfree_skb(skb);
}
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
+ "cmd peer delete vdev_id %d peer_addr %pM\n",
+ vdev_id, peer_addr);
+
return ret;
}
@@ -1134,11 +1149,6 @@ int ath11k_wmi_send_pdev_set_regdomain(struct ath11k *ar,
cmd->dfs_domain = param->dfs_domain;
cmd->pdev_id = param->pdev_id;
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "WMI pdev regd rd %d rd2g %d rd5g %d domain %d pdev id %d\n",
- param->current_rd_in_use, param->current_rd_2g,
- param->current_rd_5g, param->dfs_domain, param->pdev_id);
-
ret = ath11k_wmi_cmd_send(wmi, skb, WMI_PDEV_SET_REGDOMAIN_CMDID);
if (ret) {
ath11k_warn(ar->ab,
@@ -1146,6 +1156,11 @@ int ath11k_wmi_send_pdev_set_regdomain(struct ath11k *ar,
dev_kfree_skb(skb);
}
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
+ "cmd pdev regd rd %d rd2g %d rd5g %d domain %d pdev id %d\n",
+ param->current_rd_in_use, param->current_rd_2g,
+ param->current_rd_5g, param->dfs_domain, param->pdev_id);
+
return ret;
}
@@ -1176,7 +1191,7 @@ int ath11k_wmi_set_peer_param(struct ath11k *ar, const u8 *peer_addr,
}
ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "WMI vdev %d peer 0x%pM set param %d value %d\n",
+ "cmd peer set param vdev %d peer 0x%pM set param %d value %d\n",
vdev_id, peer_addr, param_id, param_val);
return ret;
@@ -1211,7 +1226,7 @@ int ath11k_wmi_send_peer_flush_tids_cmd(struct ath11k *ar,
}
ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "WMI peer flush vdev_id %d peer_addr %pM tids %08x\n",
+ "cmd peer flush tids vdev_id %d peer_addr %pM tids %08x\n",
param->vdev_id, peer_addr, param->peer_tid_bitmap);
return ret;
@@ -1254,7 +1269,7 @@ int ath11k_wmi_peer_rx_reorder_queue_setup(struct ath11k *ar,
}
ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "wmi rx reorder queue setup addr %pM vdev_id %d tid %d\n",
+ "cmd peer reorder queue setup addr %pM vdev_id %d tid %d\n",
addr, vdev_id, tid);
return ret;
@@ -1282,10 +1297,6 @@ ath11k_wmi_rx_reord_queue_remove(struct ath11k *ar,
cmd->vdev_id = param->vdev_id;
cmd->tid_mask = param->peer_tid_bitmap;
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "%s: peer_macaddr %pM vdev_id %d, tid_map %d", __func__,
- param->peer_macaddr, param->vdev_id, param->peer_tid_bitmap);
-
ret = ath11k_wmi_cmd_send(wmi, skb,
WMI_PEER_REORDER_QUEUE_REMOVE_CMDID);
if (ret) {
@@ -1294,6 +1305,10 @@ ath11k_wmi_rx_reord_queue_remove(struct ath11k *ar,
dev_kfree_skb(skb);
}
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
+ "cmd peer reorder queue remove peer_macaddr %pM vdev_id %d tid_map %d",
+ param->peer_macaddr, param->vdev_id, param->peer_tid_bitmap);
+
return ret;
}
@@ -1323,7 +1338,7 @@ int ath11k_wmi_pdev_set_param(struct ath11k *ar, u32 param_id,
}
ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "WMI pdev set param %d pdev id %d value %d\n",
+ "cmd pdev set param %d pdev id %d value %d\n",
param_id, pdev_id, param_value);
return ret;
@@ -1354,7 +1369,7 @@ int ath11k_wmi_pdev_set_ps_mode(struct ath11k *ar, int vdev_id,
}
ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "WMI vdev set psmode %d vdev id %d\n",
+ "cmd sta powersave mode psmode %d vdev id %d\n",
psmode, vdev_id);
return ret;
@@ -1387,7 +1402,7 @@ int ath11k_wmi_pdev_suspend(struct ath11k *ar, u32 suspend_opt,
}
ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "WMI pdev suspend pdev_id %d\n", pdev_id);
+ "cmd pdev suspend pdev_id %d\n", pdev_id);
return ret;
}
@@ -1409,15 +1424,15 @@ int ath11k_wmi_pdev_resume(struct ath11k *ar, u32 pdev_id)
FIELD_PREP(WMI_TLV_LEN, sizeof(*cmd) - TLV_HDR_SIZE);
cmd->pdev_id = pdev_id;
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "WMI pdev resume pdev id %d\n", pdev_id);
-
ret = ath11k_wmi_cmd_send(wmi, skb, WMI_PDEV_RESUME_CMDID);
if (ret) {
ath11k_warn(ar->ab, "failed to send WMI_PDEV_RESUME cmd\n");
dev_kfree_skb(skb);
}
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
+ "cmd pdev resume pdev id %d\n", pdev_id);
+
return ret;
}
@@ -1445,9 +1460,6 @@ int ath11k_wmi_pdev_bss_chan_info_request(struct ath11k *ar,
cmd->req_type = type;
cmd->pdev_id = ar->pdev->pdev_id;
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "WMI bss chan info req type %d\n", type);
-
ret = ath11k_wmi_cmd_send(wmi, skb,
WMI_PDEV_BSS_CHAN_INFO_REQUEST_CMDID);
if (ret) {
@@ -1456,6 +1468,9 @@ int ath11k_wmi_pdev_bss_chan_info_request(struct ath11k *ar,
dev_kfree_skb(skb);
}
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
+ "cmd pdev bss chan info request type %d\n", type);
+
return ret;
}
@@ -1488,7 +1503,7 @@ int ath11k_wmi_send_set_ap_ps_param_cmd(struct ath11k *ar, u8 *peer_addr,
}
ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "WMI set ap ps vdev id %d peer %pM param %d value %d\n",
+ "cmd ap ps peer param vdev id %d peer %pM param %d value %d\n",
param->vdev_id, peer_addr, param->param, param->value);
return ret;
@@ -1515,16 +1530,16 @@ int ath11k_wmi_set_sta_ps_param(struct ath11k *ar, u32 vdev_id,
cmd->param = param;
cmd->value = param_value;
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "WMI set sta ps vdev_id %d param %d value %d\n",
- vdev_id, param, param_value);
-
ret = ath11k_wmi_cmd_send(wmi, skb, WMI_STA_POWERSAVE_PARAM_CMDID);
if (ret) {
ath11k_warn(ar->ab, "failed to send WMI_STA_POWERSAVE_PARAM_CMDID");
dev_kfree_skb(skb);
}
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
+ "cmd set powersave param vdev_id %d param %d value %d\n",
+ vdev_id, param, param_value);
+
return ret;
}
@@ -1554,6 +1569,9 @@ int ath11k_wmi_force_fw_hang_cmd(struct ath11k *ar, u32 type, u32 delay_time_ms)
ath11k_warn(ar->ab, "Failed to send WMI_FORCE_FW_HANG_CMDID");
dev_kfree_skb(skb);
}
+
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "cmd force fw hang");
+
return ret;
}
@@ -1585,7 +1603,7 @@ int ath11k_wmi_vdev_set_param_cmd(struct ath11k *ar, u32 vdev_id,
}
ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "WMI vdev id 0x%x set param %d value %d\n",
+ "cmd vdev set param vdev 0x%x param %d value %d\n",
vdev_id, param_id, param_value);
return ret;
@@ -1618,7 +1636,7 @@ int ath11k_wmi_send_stats_request_cmd(struct ath11k *ar,
}
ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "WMI request stats 0x%x vdev id %d pdev id %d\n",
+ "cmd request stats 0x%x vdev id %d pdev id %d\n",
param->stats_id, param->vdev_id, param->pdev_id);
return ret;
@@ -1647,7 +1665,7 @@ int ath11k_wmi_send_pdev_temperature_cmd(struct ath11k *ar)
}
ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "WMI pdev get temperature for pdev_id %d\n", ar->pdev->pdev_id);
+ "cmd pdev get temperature for pdev_id %d\n", ar->pdev->pdev_id);
return ret;
}
@@ -1672,10 +1690,6 @@ int ath11k_wmi_send_bcn_offload_control_cmd(struct ath11k *ar,
cmd->vdev_id = vdev_id;
cmd->bcn_ctrl_op = bcn_ctrl_op;
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "WMI bcn ctrl offload vdev id %d ctrl_op %d\n",
- vdev_id, bcn_ctrl_op);
-
ret = ath11k_wmi_cmd_send(wmi, skb, WMI_BCN_OFFLOAD_CTRL_CMDID);
if (ret) {
ath11k_warn(ar->ab,
@@ -1683,12 +1697,16 @@ int ath11k_wmi_send_bcn_offload_control_cmd(struct ath11k *ar,
dev_kfree_skb(skb);
}
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
+ "cmd bcn offload ctrl vdev id %d ctrl_op %d\n",
+ vdev_id, bcn_ctrl_op);
+
return ret;
}
int ath11k_wmi_bcn_tmpl(struct ath11k *ar, u32 vdev_id,
struct ieee80211_mutable_offsets *offs,
- struct sk_buff *bcn)
+ struct sk_buff *bcn, u32 ema_params)
{
struct ath11k_pdev_wmi *wmi = ar->wmi;
struct wmi_bcn_tmpl_cmd *cmd;
@@ -1726,6 +1744,8 @@ int ath11k_wmi_bcn_tmpl(struct ath11k *ar, u32 vdev_id,
}
cmd->buf_len = bcn->len;
+ cmd->mbssid_ie_offset = offs->mbssid_off;
+ cmd->ema_params = ema_params;
ptr = skb->data + sizeof(*cmd);
@@ -1750,6 +1770,8 @@ int ath11k_wmi_bcn_tmpl(struct ath11k *ar, u32 vdev_id,
dev_kfree_skb(skb);
}
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "cmd bcn tmpl");
+
return ret;
}
@@ -1799,7 +1821,7 @@ int ath11k_wmi_vdev_install_key(struct ath11k *ar,
}
ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "WMI vdev install key idx %d cipher %d len %d\n",
+ "cmd vdev install key idx %d cipher %d len %d\n",
arg->key_idx, arg->key_cipher, arg->key_len);
return ret;
@@ -2035,7 +2057,7 @@ int ath11k_wmi_send_peer_assoc_cmd(struct ath11k *ar,
}
ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "wmi peer assoc vdev id %d assoc id %d peer mac %pM peer_flags %x rate_caps %x peer_caps %x listen_intval %d ht_caps %x max_mpdu %d nss %d phymode %d peer_mpdu_density %d vht_caps %x he cap_info %x he ops %x he cap_info_ext %x he phy %x %x %x peer_bw_rxnss_override %x\n",
+ "cmd peer assoc vdev id %d assoc id %d peer mac %pM peer_flags %x rate_caps %x peer_caps %x listen_intval %d ht_caps %x max_mpdu %d nss %d phymode %d peer_mpdu_density %d vht_caps %x he cap_info %x he ops %x he cap_info_ext %x he phy %x %x %x peer_bw_rxnss_override %x\n",
cmd->vdev_id, cmd->peer_associd, param->peer_mac,
cmd->peer_flags, cmd->peer_rate_caps, cmd->peer_caps,
cmd->peer_listen_intval, cmd->peer_ht_caps,
@@ -2352,6 +2374,8 @@ int ath11k_wmi_send_scan_start_cmd(struct ath11k *ar,
dev_kfree_skb(skb);
}
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "cmd start scan");
+
return ret;
}
@@ -2400,6 +2424,8 @@ int ath11k_wmi_send_scan_stop_cmd(struct ath11k *ar,
dev_kfree_skb(skb);
}
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "cmd stop scan");
+
return ret;
}
@@ -2444,7 +2470,7 @@ int ath11k_wmi_send_scan_chan_list_cmd(struct ath11k *ar,
cmd->flags |= WMI_APPEND_TO_EXISTING_CHAN_LIST_FLAG;
ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "WMI no.of chan = %d len = %d pdev_id = %d num_sends = %d\n",
+ "no.of chan = %d len = %d pdev_id = %d num_sends = %d\n",
num_send_chans, len, cmd->pdev_id, num_sends);
ptr = skb->data + sizeof(*cmd);
@@ -2503,7 +2529,7 @@ int ath11k_wmi_send_scan_chan_list_cmd(struct ath11k *ar,
tchan_info->maxregpower);
ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "WMI chan scan list chan[%d] = %u, chan_info->info %8x\n",
+ "chan scan list chan[%d] = %u, chan_info->info %8x\n",
i, chan_info->mhz, chan_info->info);
ptr += sizeof(*chan_info);
@@ -2518,6 +2544,9 @@ int ath11k_wmi_send_scan_chan_list_cmd(struct ath11k *ar,
return ret;
}
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "cmd scan chan list channels %d",
+ num_send_chans);
+
num_sends++;
}
@@ -2577,7 +2606,7 @@ int ath11k_wmi_send_wmm_update_cmd_tlv(struct ath11k *ar, u32 vdev_id,
wmm_param->no_ack = wmi_wmm_arg->no_ack;
ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "wmi wmm set ac %d aifs %d cwmin %d cwmax %d txop %d acm %d no_ack %d\n",
+ "wmm set ac %d aifs %d cwmin %d cwmax %d txop %d acm %d no_ack %d\n",
ac, wmm_param->aifs, wmm_param->cwmin,
wmm_param->cwmax, wmm_param->txoplimit,
wmm_param->acm, wmm_param->no_ack);
@@ -2590,6 +2619,8 @@ int ath11k_wmi_send_wmm_update_cmd_tlv(struct ath11k *ar, u32 vdev_id,
dev_kfree_skb(skb);
}
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "cmd vdev set wmm params");
+
return ret;
}
@@ -2613,9 +2644,6 @@ int ath11k_wmi_send_dfs_phyerr_offload_enable_cmd(struct ath11k *ar,
cmd->pdev_id = pdev_id;
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "WMI dfs phy err offload enable pdev id %d\n", pdev_id);
-
ret = ath11k_wmi_cmd_send(wmi, skb,
WMI_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMDID);
if (ret) {
@@ -2624,6 +2652,9 @@ int ath11k_wmi_send_dfs_phyerr_offload_enable_cmd(struct ath11k *ar,
dev_kfree_skb(skb);
}
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
+ "cmd pdev dfs phyerr offload enable pdev id %d\n", pdev_id);
+
return ret;
}
@@ -2648,10 +2679,6 @@ int ath11k_wmi_delba_send(struct ath11k *ar, u32 vdev_id, const u8 *mac,
cmd->initiator = initiator;
cmd->reasoncode = reason;
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "wmi delba send vdev_id 0x%X mac_addr %pM tid %u initiator %u reason %u\n",
- vdev_id, mac, tid, initiator, reason);
-
ret = ath11k_wmi_cmd_send(wmi, skb, WMI_DELBA_SEND_CMDID);
if (ret) {
@@ -2660,6 +2687,10 @@ int ath11k_wmi_delba_send(struct ath11k *ar, u32 vdev_id, const u8 *mac,
dev_kfree_skb(skb);
}
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
+ "cmd delba send vdev_id 0x%X mac_addr %pM tid %u initiator %u reason %u\n",
+ vdev_id, mac, tid, initiator, reason);
+
return ret;
}
@@ -2684,10 +2715,6 @@ int ath11k_wmi_addba_set_resp(struct ath11k *ar, u32 vdev_id, const u8 *mac,
cmd->tid = tid;
cmd->statuscode = status;
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "wmi addba set resp vdev_id 0x%X mac_addr %pM tid %u status %u\n",
- vdev_id, mac, tid, status);
-
ret = ath11k_wmi_cmd_send(wmi, skb, WMI_ADDBA_SET_RESP_CMDID);
if (ret) {
@@ -2696,6 +2723,10 @@ int ath11k_wmi_addba_set_resp(struct ath11k *ar, u32 vdev_id, const u8 *mac,
dev_kfree_skb(skb);
}
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
+ "cmd addba set resp vdev_id 0x%X mac_addr %pM tid %u status %u\n",
+ vdev_id, mac, tid, status);
+
return ret;
}
@@ -2719,10 +2750,6 @@ int ath11k_wmi_addba_send(struct ath11k *ar, u32 vdev_id, const u8 *mac,
cmd->tid = tid;
cmd->buffersize = buf_size;
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "wmi addba send vdev_id 0x%X mac_addr %pM tid %u bufsize %u\n",
- vdev_id, mac, tid, buf_size);
-
ret = ath11k_wmi_cmd_send(wmi, skb, WMI_ADDBA_SEND_CMDID);
if (ret) {
@@ -2731,6 +2758,10 @@ int ath11k_wmi_addba_send(struct ath11k *ar, u32 vdev_id, const u8 *mac,
dev_kfree_skb(skb);
}
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
+ "cmd addba send vdev_id 0x%X mac_addr %pM tid %u bufsize %u\n",
+ vdev_id, mac, tid, buf_size);
+
return ret;
}
@@ -2752,10 +2783,6 @@ int ath11k_wmi_addba_clear_resp(struct ath11k *ar, u32 vdev_id, const u8 *mac)
cmd->vdev_id = vdev_id;
ether_addr_copy(cmd->peer_macaddr.addr, mac);
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "wmi addba clear resp vdev_id 0x%X mac_addr %pM\n",
- vdev_id, mac);
-
ret = ath11k_wmi_cmd_send(wmi, skb, WMI_ADDBA_CLEAR_RESP_CMDID);
if (ret) {
@@ -2764,6 +2791,10 @@ int ath11k_wmi_addba_clear_resp(struct ath11k *ar, u32 vdev_id, const u8 *mac)
dev_kfree_skb(skb);
}
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
+ "cmd addba clear resp vdev_id 0x%X mac_addr %pM\n",
+ vdev_id, mac);
+
return ret;
}
@@ -2812,6 +2843,8 @@ int ath11k_wmi_pdev_peer_pktlog_filter(struct ath11k *ar, u8 *addr, u8 enable)
dev_kfree_skb(skb);
}
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "cmd pdev pktlog filter");
+
return ret;
}
@@ -2851,21 +2884,27 @@ ath11k_wmi_send_init_country_cmd(struct ath11k *ar,
cmd->cc_info.regdom_id = init_cc_params.cc_info.regdom_id;
break;
default:
+ ath11k_warn(ar->ab, "unknown cc params flags: 0x%x",
+ init_cc_params.flags);
ret = -EINVAL;
- goto out;
+ goto err;
}
ret = ath11k_wmi_cmd_send(wmi, skb,
WMI_SET_INIT_COUNTRY_CMDID);
-
-out:
if (ret) {
ath11k_warn(ar->ab,
"failed to send WMI_SET_INIT_COUNTRY CMD :%d\n",
ret);
- dev_kfree_skb(skb);
+ goto err;
}
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "cmd set init country");
+
+ return 0;
+
+err:
+ dev_kfree_skb(skb);
return ret;
}
@@ -2888,20 +2927,20 @@ int ath11k_wmi_send_set_current_country_cmd(struct ath11k *ar,
cmd->pdev_id = ar->pdev->pdev_id;
memcpy(&cmd->new_alpha2, &param->alpha2, 3);
- ret = ath11k_wmi_cmd_send(wmi, skb, WMI_SET_CURRENT_COUNTRY_CMDID);
-
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "set current country pdev id %d alpha2 %c%c\n",
- ar->pdev->pdev_id,
- param->alpha2[0],
- param->alpha2[1]);
+ ret = ath11k_wmi_cmd_send(wmi, skb, WMI_SET_CURRENT_COUNTRY_CMDID);
if (ret) {
ath11k_warn(ar->ab,
"failed to send WMI_SET_CURRENT_COUNTRY_CMDID: %d\n", ret);
dev_kfree_skb(skb);
}
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
+ "cmd set current country pdev id %d alpha2 %c%c\n",
+ ar->pdev->pdev_id,
+ param->alpha2[0],
+ param->alpha2[1]);
+
return ret;
}
@@ -2962,7 +3001,7 @@ ath11k_wmi_send_thermal_mitigation_param_cmd(struct ath11k *ar,
}
ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "WMI vdev set thermal throt pdev_id %d enable %d dc %d dc_per_event %x levels %d\n",
+ "cmd therm throt set conf pdev_id %d enable %d dc %d dc_per_event %x levels %d\n",
ar->pdev->pdev_id, param->enable, param->dc,
param->dc_per_event, THERMAL_LEVELS);
@@ -2989,20 +3028,20 @@ int ath11k_wmi_send_11d_scan_start_cmd(struct ath11k *ar,
cmd->vdev_id = param->vdev_id;
cmd->scan_period_msec = param->scan_period_msec;
cmd->start_interval_msec = param->start_interval_msec;
- ret = ath11k_wmi_cmd_send(wmi, skb, WMI_11D_SCAN_START_CMDID);
-
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "send 11d scan start vdev id %d period %d ms internal %d ms\n",
- cmd->vdev_id,
- cmd->scan_period_msec,
- cmd->start_interval_msec);
+ ret = ath11k_wmi_cmd_send(wmi, skb, WMI_11D_SCAN_START_CMDID);
if (ret) {
ath11k_warn(ar->ab,
"failed to send WMI_11D_SCAN_START_CMDID: %d\n", ret);
dev_kfree_skb(skb);
}
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
+ "cmd 11d scan start vdev id %d period %d ms internal %d ms\n",
+ cmd->vdev_id,
+ cmd->scan_period_msec,
+ cmd->start_interval_msec);
+
return ret;
}
@@ -3023,18 +3062,18 @@ int ath11k_wmi_send_11d_scan_stop_cmd(struct ath11k *ar, u32 vdev_id)
FIELD_PREP(WMI_TLV_LEN, sizeof(*cmd) - TLV_HDR_SIZE);
cmd->vdev_id = vdev_id;
- ret = ath11k_wmi_cmd_send(wmi, skb, WMI_11D_SCAN_STOP_CMDID);
-
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "send 11d scan stop vdev id %d\n",
- cmd->vdev_id);
+ ret = ath11k_wmi_cmd_send(wmi, skb, WMI_11D_SCAN_STOP_CMDID);
if (ret) {
ath11k_warn(ar->ab,
"failed to send WMI_11D_SCAN_STOP_CMDID: %d\n", ret);
dev_kfree_skb(skb);
}
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
+ "cmd 11d scan stop vdev id %d\n",
+ cmd->vdev_id);
+
return ret;
}
@@ -3065,6 +3104,8 @@ int ath11k_wmi_pdev_pktlog_enable(struct ath11k *ar, u32 pktlog_filter)
dev_kfree_skb(skb);
}
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "cmd pdev pktlog enable");
+
return ret;
}
@@ -3093,6 +3134,8 @@ int ath11k_wmi_pdev_pktlog_disable(struct ath11k *ar)
dev_kfree_skb(skb);
}
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "cmd pdev pktlog disable");
+
return ret;
}
@@ -3162,10 +3205,14 @@ int ath11k_wmi_send_twt_enable_cmd(struct ath11k *ar, u32 pdev_id,
if (ret) {
ath11k_warn(ab, "Failed to send WMI_TWT_ENABLE_CMDID");
dev_kfree_skb(skb);
- } else {
- ar->twt_enabled = 1;
+ return ret;
}
- return ret;
+
+ ar->twt_enabled = 1;
+
+ ath11k_dbg(ab, ATH11K_DBG_WMI, "cmd twt enable");
+
+ return 0;
}
int
@@ -3192,10 +3239,14 @@ ath11k_wmi_send_twt_disable_cmd(struct ath11k *ar, u32 pdev_id)
if (ret) {
ath11k_warn(ab, "Failed to send WMI_TWT_DISABLE_CMDID");
dev_kfree_skb(skb);
- } else {
- ar->twt_enabled = 0;
+ return ret;
}
- return ret;
+
+ ath11k_dbg(ab, ATH11K_DBG_WMI, "cmd twt disable");
+
+ ar->twt_enabled = 0;
+
+ return 0;
}
int ath11k_wmi_send_twt_add_dialog_cmd(struct ath11k *ar,
@@ -3234,21 +3285,22 @@ int ath11k_wmi_send_twt_add_dialog_cmd(struct ath11k *ar,
if (params->flag_protection)
cmd->flags |= WMI_TWT_ADD_DIALOG_FLAG_PROTECTION;
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "wmi add twt dialog vdev %u dialog id %u wake interval %u mantissa %u wake duration %u service period offset %u flags 0x%x\n",
- cmd->vdev_id, cmd->dialog_id, cmd->wake_intvl_us,
- cmd->wake_intvl_mantis, cmd->wake_dura_us, cmd->sp_offset_us,
- cmd->flags);
-
ret = ath11k_wmi_cmd_send(wmi, skb, WMI_TWT_ADD_DIALOG_CMDID);
-
if (ret) {
ath11k_warn(ab,
"failed to send wmi command to add twt dialog: %d",
ret);
dev_kfree_skb(skb);
+ return ret;
}
- return ret;
+
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
+ "cmd twt add dialog vdev %u dialog id %u wake interval %u mantissa %u wake duration %u service period offset %u flags 0x%x\n",
+ cmd->vdev_id, cmd->dialog_id, cmd->wake_intvl_us,
+ cmd->wake_intvl_mantis, cmd->wake_dura_us, cmd->sp_offset_us,
+ cmd->flags);
+
+ return 0;
}
int ath11k_wmi_send_twt_del_dialog_cmd(struct ath11k *ar,
@@ -3274,18 +3326,20 @@ int ath11k_wmi_send_twt_del_dialog_cmd(struct ath11k *ar,
ether_addr_copy(cmd->peer_macaddr.addr, params->peer_macaddr);
cmd->dialog_id = params->dialog_id;
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "wmi delete twt dialog vdev %u dialog id %u\n",
- cmd->vdev_id, cmd->dialog_id);
-
ret = ath11k_wmi_cmd_send(wmi, skb, WMI_TWT_DEL_DIALOG_CMDID);
if (ret) {
ath11k_warn(ab,
"failed to send wmi command to delete twt dialog: %d",
ret);
dev_kfree_skb(skb);
+ return ret;
}
- return ret;
+
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
+ "cmd twt del dialog vdev %u dialog id %u\n",
+ cmd->vdev_id, cmd->dialog_id);
+
+ return 0;
}
int ath11k_wmi_send_twt_pause_dialog_cmd(struct ath11k *ar,
@@ -3312,18 +3366,20 @@ int ath11k_wmi_send_twt_pause_dialog_cmd(struct ath11k *ar,
ether_addr_copy(cmd->peer_macaddr.addr, params->peer_macaddr);
cmd->dialog_id = params->dialog_id;
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "wmi pause twt dialog vdev %u dialog id %u\n",
- cmd->vdev_id, cmd->dialog_id);
-
ret = ath11k_wmi_cmd_send(wmi, skb, WMI_TWT_PAUSE_DIALOG_CMDID);
if (ret) {
ath11k_warn(ab,
"failed to send wmi command to pause twt dialog: %d",
ret);
dev_kfree_skb(skb);
+ return ret;
}
- return ret;
+
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
+ "cmd twt pause dialog vdev %u dialog id %u\n",
+ cmd->vdev_id, cmd->dialog_id);
+
+ return 0;
}
int ath11k_wmi_send_twt_resume_dialog_cmd(struct ath11k *ar,
@@ -3352,19 +3408,21 @@ int ath11k_wmi_send_twt_resume_dialog_cmd(struct ath11k *ar,
cmd->sp_offset_us = params->sp_offset_us;
cmd->next_twt_size = params->next_twt_size;
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "wmi resume twt dialog vdev %u dialog id %u service period offset %u next twt subfield size %u\n",
- cmd->vdev_id, cmd->dialog_id, cmd->sp_offset_us,
- cmd->next_twt_size);
-
ret = ath11k_wmi_cmd_send(wmi, skb, WMI_TWT_RESUME_DIALOG_CMDID);
if (ret) {
ath11k_warn(ab,
"failed to send wmi command to resume twt dialog: %d",
ret);
dev_kfree_skb(skb);
+ return ret;
}
- return ret;
+
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
+ "cmd twt resume dialog vdev %u dialog id %u service period offset %u next twt subfield size %u\n",
+ cmd->vdev_id, cmd->dialog_id, cmd->sp_offset_us,
+ cmd->next_twt_size);
+
+ return 0;
}
int
@@ -3398,8 +3456,12 @@ ath11k_wmi_send_obss_spr_cmd(struct ath11k *ar, u32 vdev_id,
ath11k_warn(ab,
"Failed to send WMI_PDEV_OBSS_PD_SPATIAL_REUSE_CMDID");
dev_kfree_skb(skb);
+ return ret;
}
- return ret;
+
+ ath11k_dbg(ab, ATH11K_DBG_WMI, "cmd pdev obss pd spatial reuse");
+
+ return 0;
}
int
@@ -3424,19 +3486,20 @@ ath11k_wmi_pdev_set_srg_bss_color_bitmap(struct ath11k *ar, u32 *bitmap)
cmd->pdev_id = ar->pdev->pdev_id;
memcpy(cmd->bitmap, bitmap, sizeof(cmd->bitmap));
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "obss pd pdev_id %d bss color bitmap %08x %08x\n",
- cmd->pdev_id, cmd->bitmap[0], cmd->bitmap[1]);
-
ret = ath11k_wmi_cmd_send(wmi, skb,
WMI_PDEV_SET_SRG_BSS_COLOR_BITMAP_CMDID);
if (ret) {
ath11k_warn(ab,
"failed to send WMI_PDEV_SET_SRG_BSS_COLOR_BITMAP_CMDID");
dev_kfree_skb(skb);
+ return ret;
}
- return ret;
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
+ "cmd pdev set srg bss color bitmap pdev_id %d bss color bitmap %08x %08x\n",
+ cmd->pdev_id, cmd->bitmap[0], cmd->bitmap[1]);
+
+ return 0;
}
int
@@ -3462,19 +3525,20 @@ ath11k_wmi_pdev_set_srg_patial_bssid_bitmap(struct ath11k *ar, u32 *bitmap)
cmd->pdev_id = ar->pdev->pdev_id;
memcpy(cmd->bitmap, bitmap, sizeof(cmd->bitmap));
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "obss pd pdev_id %d partial bssid bitmap %08x %08x\n",
- cmd->pdev_id, cmd->bitmap[0], cmd->bitmap[1]);
-
ret = ath11k_wmi_cmd_send(wmi, skb,
WMI_PDEV_SET_SRG_PARTIAL_BSSID_BITMAP_CMDID);
if (ret) {
ath11k_warn(ab,
"failed to send WMI_PDEV_SET_SRG_PARTIAL_BSSID_BITMAP_CMDID");
dev_kfree_skb(skb);
+ return ret;
}
- return ret;
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
+ "cmd pdev set srg partial bssid bitmap pdev_id %d partial bssid bitmap %08x %08x\n",
+ cmd->pdev_id, cmd->bitmap[0], cmd->bitmap[1]);
+
+ return 0;
}
int
@@ -3500,19 +3564,20 @@ ath11k_wmi_pdev_srg_obss_color_enable_bitmap(struct ath11k *ar, u32 *bitmap)
cmd->pdev_id = ar->pdev->pdev_id;
memcpy(cmd->bitmap, bitmap, sizeof(cmd->bitmap));
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "obss pd srg pdev_id %d bss color enable bitmap %08x %08x\n",
- cmd->pdev_id, cmd->bitmap[0], cmd->bitmap[1]);
-
ret = ath11k_wmi_cmd_send(wmi, skb,
WMI_PDEV_SET_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID);
if (ret) {
ath11k_warn(ab,
"failed to send WMI_PDEV_SET_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID");
dev_kfree_skb(skb);
+ return ret;
}
- return ret;
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
+ "cmd pdev set srg obsscolor enable pdev_id %d bss color enable bitmap %08x %08x\n",
+ cmd->pdev_id, cmd->bitmap[0], cmd->bitmap[1]);
+
+ return 0;
}
int
@@ -3538,19 +3603,20 @@ ath11k_wmi_pdev_srg_obss_bssid_enable_bitmap(struct ath11k *ar, u32 *bitmap)
cmd->pdev_id = ar->pdev->pdev_id;
memcpy(cmd->bitmap, bitmap, sizeof(cmd->bitmap));
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "obss pd srg pdev_id %d bssid enable bitmap %08x %08x\n",
- cmd->pdev_id, cmd->bitmap[0], cmd->bitmap[1]);
-
ret = ath11k_wmi_cmd_send(wmi, skb,
WMI_PDEV_SET_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID);
if (ret) {
ath11k_warn(ab,
"failed to send WMI_PDEV_SET_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID");
dev_kfree_skb(skb);
+ return ret;
}
- return ret;
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
+ "cmd pdev set srg obss bssid enable bitmap pdev_id %d bssid enable bitmap %08x %08x\n",
+ cmd->pdev_id, cmd->bitmap[0], cmd->bitmap[1]);
+
+ return 0;
}
int
@@ -3576,19 +3642,20 @@ ath11k_wmi_pdev_non_srg_obss_color_enable_bitmap(struct ath11k *ar, u32 *bitmap)
cmd->pdev_id = ar->pdev->pdev_id;
memcpy(cmd->bitmap, bitmap, sizeof(cmd->bitmap));
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "obss pd non_srg pdev_id %d bss color enable bitmap %08x %08x\n",
- cmd->pdev_id, cmd->bitmap[0], cmd->bitmap[1]);
-
ret = ath11k_wmi_cmd_send(wmi, skb,
WMI_PDEV_SET_NON_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID);
if (ret) {
ath11k_warn(ab,
"failed to send WMI_PDEV_SET_NON_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID");
dev_kfree_skb(skb);
+ return ret;
}
- return ret;
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
+ "cmd pdev set non srg obss color enable bitmap pdev_id %d bss color enable bitmap %08x %08x\n",
+ cmd->pdev_id, cmd->bitmap[0], cmd->bitmap[1]);
+
+ return 0;
}
int
@@ -3614,19 +3681,20 @@ ath11k_wmi_pdev_non_srg_obss_bssid_enable_bitmap(struct ath11k *ar, u32 *bitmap)
cmd->pdev_id = ar->pdev->pdev_id;
memcpy(cmd->bitmap, bitmap, sizeof(cmd->bitmap));
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "obss pd non_srg pdev_id %d bssid enable bitmap %08x %08x\n",
- cmd->pdev_id, cmd->bitmap[0], cmd->bitmap[1]);
-
ret = ath11k_wmi_cmd_send(wmi, skb,
WMI_PDEV_SET_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID);
if (ret) {
ath11k_warn(ab,
"failed to send WMI_PDEV_SET_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID");
dev_kfree_skb(skb);
+ return ret;
}
- return ret;
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
+ "cmd pdev set non srg obss bssid enable bitmap pdev_id %d bssid enable bitmap %08x %08x\n",
+ cmd->pdev_id, cmd->bitmap[0], cmd->bitmap[1]);
+
+ return 0;
}
int
@@ -3659,18 +3727,20 @@ ath11k_wmi_send_obss_color_collision_cfg_cmd(struct ath11k *ar, u32 vdev_id,
cmd->free_slot_expiry_time_ms = 0;
cmd->flags = 0;
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "wmi_send_obss_color_collision_cfg id %d type %d bss_color %d detect_period %d scan_period %d\n",
- cmd->vdev_id, cmd->evt_type, cmd->current_bss_color,
- cmd->detection_period_ms, cmd->scan_period_ms);
-
ret = ath11k_wmi_cmd_send(wmi, skb,
WMI_OBSS_COLOR_COLLISION_DET_CONFIG_CMDID);
if (ret) {
ath11k_warn(ab, "Failed to send WMI_OBSS_COLOR_COLLISION_DET_CONFIG_CMDID");
dev_kfree_skb(skb);
+ return ret;
}
- return ret;
+
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
+ "cmd obss color collision det config id %d type %d bss_color %d detect_period %d scan_period %d\n",
+ cmd->vdev_id, cmd->evt_type, cmd->current_bss_color,
+ cmd->detection_period_ms, cmd->scan_period_ms);
+
+ return 0;
}
int ath11k_wmi_send_bss_color_change_enable_cmd(struct ath11k *ar, u32 vdev_id,
@@ -3694,17 +3764,19 @@ int ath11k_wmi_send_bss_color_change_enable_cmd(struct ath11k *ar, u32 vdev_id,
cmd->vdev_id = vdev_id;
cmd->enable = enable ? 1 : 0;
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "wmi_send_bss_color_change_enable id %d enable %d\n",
- cmd->vdev_id, cmd->enable);
-
ret = ath11k_wmi_cmd_send(wmi, skb,
WMI_BSS_COLOR_CHANGE_ENABLE_CMDID);
if (ret) {
ath11k_warn(ab, "Failed to send WMI_BSS_COLOR_CHANGE_ENABLE_CMDID");
dev_kfree_skb(skb);
+ return ret;
}
- return ret;
+
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
+ "cmd bss color change enable id %d enable %d\n",
+ cmd->vdev_id, cmd->enable);
+
+ return 0;
}
int ath11k_wmi_fils_discovery_tmpl(struct ath11k *ar, u32 vdev_id,
@@ -3721,7 +3793,7 @@ int ath11k_wmi_fils_discovery_tmpl(struct ath11k *ar, u32 vdev_id,
len = sizeof(*cmd) + TLV_HDR_SIZE + aligned_len;
ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "WMI vdev %i set FILS discovery template\n", vdev_id);
+ "vdev %i set FILS discovery template\n", vdev_id);
skb = ath11k_wmi_alloc_skb(ar->wmi->wmi_ab, len);
if (!skb)
@@ -3746,8 +3818,12 @@ int ath11k_wmi_fils_discovery_tmpl(struct ath11k *ar, u32 vdev_id,
"WMI vdev %i failed to send FILS discovery template command\n",
vdev_id);
dev_kfree_skb(skb);
+ return ret;
}
- return ret;
+
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "cmd fils discovery tmpl");
+
+ return 0;
}
int ath11k_wmi_probe_resp_tmpl(struct ath11k *ar, u32 vdev_id,
@@ -3762,7 +3838,7 @@ int ath11k_wmi_probe_resp_tmpl(struct ath11k *ar, u32 vdev_id,
size_t aligned_len = roundup(tmpl->len, 4);
ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "WMI vdev %i set probe response template\n", vdev_id);
+ "vdev %i set probe response template\n", vdev_id);
len = sizeof(*cmd) + sizeof(*probe_info) + TLV_HDR_SIZE + aligned_len;
@@ -3799,8 +3875,12 @@ int ath11k_wmi_probe_resp_tmpl(struct ath11k *ar, u32 vdev_id,
"WMI vdev %i failed to send probe response template command\n",
vdev_id);
dev_kfree_skb(skb);
+ return ret;
}
- return ret;
+
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "cmd ");
+
+ return 0;
}
int ath11k_wmi_fils_discovery(struct ath11k *ar, u32 vdev_id, u32 interval,
@@ -3811,7 +3891,7 @@ int ath11k_wmi_fils_discovery(struct ath11k *ar, u32 vdev_id, u32 interval,
struct wmi_fils_discovery_cmd *cmd;
ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "WMI vdev %i set %s interval to %u TU\n",
+ "vdev %i set %s interval to %u TU\n",
vdev_id, unsol_bcast_probe_resp_enabled ?
"unsolicited broadcast probe response" : "FILS discovery",
interval);
@@ -3834,8 +3914,12 @@ int ath11k_wmi_fils_discovery(struct ath11k *ar, u32 vdev_id, u32 interval,
"WMI vdev %i failed to send FILS discovery enable/disable command\n",
vdev_id);
dev_kfree_skb(skb);
+ return ret;
}
- return ret;
+
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "cmd enable fils");
+
+ return 0;
}
static void
@@ -3853,6 +3937,8 @@ ath11k_wmi_obss_color_collision_event(struct ath11k_base *ab, struct sk_buff *sk
return;
}
+ ath11k_dbg(ab, ATH11K_DBG_WMI, "event obss color collision");
+
rcu_read_lock();
ev = tb[WMI_TAG_OBSS_COLOR_COLLISION_EVT];
@@ -3987,6 +4073,9 @@ ath11k_wmi_copy_resource_config(struct wmi_resource_config *wmi_cfg,
~(1 << WMI_CFG_HOST_SERVICE_FLAG_REG_CC_EXT);
wmi_cfg->host_service_flags |= (tg_cfg->is_reg_cc_ext_event_supported <<
WMI_CFG_HOST_SERVICE_FLAG_REG_CC_EXT);
+ wmi_cfg->flags2 = WMI_RSRC_CFG_FLAG2_CALC_NEXT_DTIM_COUNT_SET;
+ wmi_cfg->ema_max_vap_cnt = tg_cfg->ema_max_vap_cnt;
+ wmi_cfg->ema_max_profile_period = tg_cfg->ema_max_profile_period;
}
static int ath11k_init_cmd_send(struct ath11k_pdev_wmi *wmi,
@@ -4044,7 +4133,7 @@ static int ath11k_init_cmd_send(struct ath11k_pdev_wmi *wmi,
host_mem_chunks[idx].req_id = param->mem_chunks[idx].req_id;
ath11k_dbg(ab, ATH11K_DBG_WMI,
- "WMI host mem chunk req_id %d paddr 0x%llx len %d\n",
+ "host mem chunk req_id %d paddr 0x%llx len %d\n",
param->mem_chunks[idx].req_id,
(u64)param->mem_chunks[idx].paddr,
param->mem_chunks[idx].len);
@@ -4098,9 +4187,12 @@ static int ath11k_init_cmd_send(struct ath11k_pdev_wmi *wmi,
if (ret) {
ath11k_warn(ab, "failed to send WMI_INIT_CMDID\n");
dev_kfree_skb(skb);
+ return ret;
}
- return ret;
+ ath11k_dbg(ab, ATH11K_DBG_WMI, "cmd wmi init");
+
+ return 0;
}
int ath11k_wmi_pdev_lro_cfg(struct ath11k *ar,
@@ -4131,7 +4223,7 @@ int ath11k_wmi_pdev_lro_cfg(struct ath11k *ar,
}
ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "WMI lro cfg cmd pdev_id 0x%x\n", pdev_id);
+ "cmd lro config pdev_id 0x%x\n", pdev_id);
return 0;
err:
dev_kfree_skb(skb);
@@ -4189,9 +4281,12 @@ int ath11k_wmi_set_hw_mode(struct ath11k_base *ab,
if (ret) {
ath11k_warn(ab, "failed to send WMI_PDEV_SET_HW_MODE_CMDID\n");
dev_kfree_skb(skb);
+ return ret;
}
- return ret;
+ ath11k_dbg(ab, ATH11K_DBG_WMI, "cmd pdev set hw mode %d", cmd->hw_mode_index);
+
+ return 0;
}
int ath11k_wmi_cmd_init(struct ath11k_base *ab)
@@ -4252,7 +4347,7 @@ int ath11k_wmi_vdev_spectral_conf(struct ath11k *ar,
}
ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "WMI spectral scan config cmd vdev_id 0x%x\n",
+ "cmd vdev spectral scan configure vdev_id 0x%x\n",
param->vdev_id);
return 0;
@@ -4290,7 +4385,7 @@ int ath11k_wmi_vdev_spectral_enable(struct ath11k *ar, u32 vdev_id,
}
ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "WMI spectral enable cmd vdev id 0x%x\n",
+ "cmd vdev spectral scan enable vdev id 0x%x\n",
vdev_id);
return 0;
@@ -4336,7 +4431,7 @@ int ath11k_wmi_pdev_dma_ring_cfg(struct ath11k *ar,
}
ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "WMI DMA ring cfg req cmd pdev_id 0x%x\n",
+ "cmd pdev dma ring cfg req pdev_id 0x%x\n",
param->pdev_id);
return 0;
@@ -4442,6 +4537,8 @@ static void ath11k_wmi_pdev_dma_ring_buf_release_event(struct ath11k_base *ab,
return;
}
+ ath11k_dbg(ab, ATH11K_DBG_WMI, "event pdev dma ring buf release");
+
param.fixed = parse.fixed;
param.buf_entry = parse.buf_entry;
param.num_buf_entry = parse.num_buf_entry;
@@ -4836,6 +4933,8 @@ static int ath11k_service_ready_ext_event(struct ath11k_base *ab,
goto err;
}
+ ath11k_dbg(ab, ATH11K_DBG_WMI, "event service ready ext");
+
if (!test_bit(WMI_TLV_SERVICE_EXT2_MSG, ab->wmi_ab.svc_map))
complete(&ab->wmi_ab.service_ready);
@@ -4886,6 +4985,8 @@ static int ath11k_service_ready_ext2_event(struct ath11k_base *ab,
goto err;
}
+ ath11k_dbg(ab, ATH11K_DBG_WMI, "event service ready ext2");
+
complete(&ab->wmi_ab.service_ready);
return 0;
@@ -5757,7 +5858,7 @@ static int wmi_process_mgmt_tx_comp(struct ath11k *ar,
WARN_ON_ONCE(1);
ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "wmi mgmt tx comp pending %d desc id %d\n",
+ "mgmt tx comp pending %d desc id %d\n",
num_mgmt, tx_compl_param->desc_id);
if (!num_mgmt)
@@ -6326,7 +6427,7 @@ static int ath11k_wmi_tlv_rssi_chain_parse(struct ath11k_base *ab,
stats->stats_id = WMI_REQUEST_RSSI_PER_CHAIN_STAT;
ath11k_dbg(ab, ATH11K_DBG_WMI,
- "wmi stats vdev id %d mac %pM\n",
+ "stats vdev id %d mac %pM\n",
stats_rssi->vdev_id, stats_rssi->peer_macaddr.addr);
arvif = ath11k_mac_get_arvif(ar, stats_rssi->vdev_id);
@@ -6338,7 +6439,7 @@ static int ath11k_wmi_tlv_rssi_chain_parse(struct ath11k_base *ab,
}
ath11k_dbg(ab, ATH11K_DBG_WMI,
- "wmi stats bssid %pM vif %pK\n",
+ "stats bssid %pM vif %p\n",
arvif->bssid, arvif->vif);
sta = ieee80211_find_sta_by_ifaddr(ar->hw,
@@ -6359,7 +6460,7 @@ static int ath11k_wmi_tlv_rssi_chain_parse(struct ath11k_base *ab,
for (j = 0; j < ARRAY_SIZE(arsta->chain_signal); j++) {
arsta->chain_signal[j] = stats_rssi->rssi_avg_beacon[j];
ath11k_dbg(ab, ATH11K_DBG_WMI,
- "wmi stats beacon rssi[%d] %d data rssi[%d] %d\n",
+ "stats beacon rssi[%d] %d data rssi[%d] %d\n",
j,
stats_rssi->rssi_avg_beacon[j],
j,
@@ -6442,7 +6543,7 @@ static int ath11k_wmi_tlv_fw_stats_data_parse(struct ath11k_base *ab,
arsta = (struct ath11k_sta *)sta->drv_priv;
arsta->rssi_beacon = src->beacon_snr;
ath11k_dbg(ab, ATH11K_DBG_WMI,
- "wmi stats vdev id %d snr %d\n",
+ "stats vdev id %d snr %d\n",
src->vdev_id, src->beacon_snr);
} else {
ath11k_dbg(ab, ATH11K_DBG_WMI,
@@ -6512,7 +6613,7 @@ static int ath11k_wmi_tlv_fw_stats_parse(struct ath11k_base *ab,
parse->rssi_num = parse->rssi->num_per_chain_rssi_stats;
ath11k_dbg(ab, ATH11K_DBG_WMI,
- "wmi stats id 0x%x num chain %d\n",
+ "stats id 0x%x num chain %d\n",
parse->ev->stats_id,
parse->rssi_num);
break;
@@ -6548,28 +6649,6 @@ int ath11k_wmi_pull_fw_stats(struct ath11k_base *ab, struct sk_buff *skb,
&parse);
}
-size_t ath11k_wmi_fw_stats_num_vdevs(struct list_head *head)
-{
- struct ath11k_fw_stats_vdev *i;
- size_t num = 0;
-
- list_for_each_entry(i, head, list)
- ++num;
-
- return num;
-}
-
-static size_t ath11k_wmi_fw_stats_num_bcn(struct list_head *head)
-{
- struct ath11k_fw_stats_bcn *i;
- size_t num = 0;
-
- list_for_each_entry(i, head, list)
- ++num;
-
- return num;
-}
-
static void
ath11k_wmi_fw_pdev_base_stats_fill(const struct ath11k_fw_stats_pdev *pdev,
char *buf, u32 *length)
@@ -6880,7 +6959,7 @@ void ath11k_wmi_fw_stats_fill(struct ath11k *ar,
}
if (stats_id == WMI_REQUEST_BCN_STAT) {
- num_bcn = ath11k_wmi_fw_stats_num_bcn(&fw_stats->bcn);
+ num_bcn = list_count_nodes(&fw_stats->bcn);
len += scnprintf(buf + len, buf_len - len, "\n");
len += scnprintf(buf + len, buf_len - len, "%30s (%zu)\n",
@@ -6933,7 +7012,7 @@ static int ath11k_reg_11d_new_cc_event(struct ath11k_base *ab, struct sk_buff *s
memcpy(&ab->new_alpha2, &ev->new_alpha2, 2);
spin_unlock_bh(&ab->base_lock);
- ath11k_dbg(ab, ATH11K_DBG_WMI, "wmi 11d new cc %c%c\n",
+ ath11k_dbg(ab, ATH11K_DBG_WMI, "event 11d new cc %c%c\n",
ab->new_alpha2[0],
ab->new_alpha2[1]);
@@ -7017,6 +7096,8 @@ static int ath11k_reg_chan_list_event(struct ath11k_base *ab,
goto fallback;
}
+ ath11k_dbg(ab, ATH11K_DBG_WMI, "event reg chan list id %d", id);
+
if (reg_info->status_code != REG_SET_CC_STATUS_PASS) {
/* In case of failure to set the requested ctry,
* fw retains the current regd. We print a failure info
@@ -7182,6 +7263,8 @@ static int ath11k_ready_event(struct ath11k_base *ab, struct sk_buff *skb)
return ret;
}
+ ath11k_dbg(ab, ATH11K_DBG_WMI, "event ready");
+
complete(&ab->wmi_ab.unified_ready);
return 0;
}
@@ -7196,6 +7279,8 @@ static void ath11k_peer_delete_resp_event(struct ath11k_base *ab, struct sk_buff
return;
}
+ ath11k_dbg(ab, ATH11K_DBG_WMI, "event peer delete resp");
+
rcu_read_lock();
ar = ath11k_mac_get_ar_by_vdev_id(ab, peer_del_resp.vdev_id);
if (!ar) {
@@ -7235,7 +7320,7 @@ static void ath11k_vdev_delete_resp_event(struct ath11k_base *ab,
rcu_read_unlock();
- ath11k_dbg(ab, ATH11K_DBG_WMI, "vdev delete resp for vdev id %d\n",
+ ath11k_dbg(ab, ATH11K_DBG_WMI, "event vdev delete resp for vdev id %d\n",
vdev_id);
}
@@ -7266,6 +7351,8 @@ static void ath11k_vdev_start_resp_event(struct ath11k_base *ab, struct sk_buff
return;
}
+ ath11k_dbg(ab, ATH11K_DBG_WMI, "event start resp event");
+
rcu_read_lock();
ar = ath11k_mac_get_ar_by_vdev_id(ab, vdev_start_resp.vdev_id);
if (!ar) {
@@ -7304,6 +7391,8 @@ static void ath11k_bcn_tx_status_event(struct ath11k_base *ab, struct sk_buff *s
return;
}
+ ath11k_dbg(ab, ATH11K_DBG_WMI, "event offload bcn tx status");
+
rcu_read_lock();
arvif = ath11k_mac_get_arvif_by_vdev_id(ab, vdev_id);
if (!arvif) {
@@ -7343,7 +7432,7 @@ static void ath11k_wmi_event_peer_sta_ps_state_chg(struct ath11k_base *ab,
}
ath11k_dbg(ab, ATH11K_DBG_WMI,
- "peer sta ps change ev addr %pM state %u sup_bitmap %x ps_valid %u ts %u\n",
+ "event peer sta ps change ev addr %pM state %u sup_bitmap %x ps_valid %u ts %u\n",
ev->peer_macaddr.addr, ev->peer_ps_state,
ev->ps_supported_bitmap, ev->peer_ps_valid,
ev->peer_ps_timestamp);
@@ -7427,6 +7516,8 @@ static void ath11k_vdev_stopped_event(struct ath11k_base *ab, struct sk_buff *sk
return;
}
+ ath11k_dbg(ab, ATH11K_DBG_WMI, "event vdev stopped");
+
rcu_read_lock();
ar = ath11k_mac_get_ar_by_vdev_id(ab, vdev_id);
if (!ar) {
@@ -7460,7 +7551,7 @@ static void ath11k_mgmt_rx_event(struct ath11k_base *ab, struct sk_buff *skb)
memset(status, 0, sizeof(*status));
- ath11k_dbg(ab, ATH11K_DBG_MGMT, "mgmt rx event status %08x\n",
+ ath11k_dbg(ab, ATH11K_DBG_MGMT, "event mgmt rx status %08x\n",
rx_ev.status);
rcu_read_lock();
@@ -7503,7 +7594,7 @@ static void ath11k_mgmt_rx_event(struct ath11k_base *ab, struct sk_buff *skb)
if (rx_ev.phy_mode == MODE_11B &&
(status->band == NL80211_BAND_5GHZ || status->band == NL80211_BAND_6GHZ))
ath11k_dbg(ab, ATH11K_DBG_WMI,
- "wmi mgmt rx 11b (CCK) on 5/6GHz, band = %d\n", status->band);
+ "mgmt rx 11b (CCK) on 5/6GHz, band = %d\n", status->band);
sband = &ar->mac.sbands[status->band];
@@ -7543,7 +7634,7 @@ static void ath11k_mgmt_rx_event(struct ath11k_base *ab, struct sk_buff *skb)
ath11k_mac_handle_beacon(ar, skb);
ath11k_dbg(ab, ATH11K_DBG_MGMT,
- "event mgmt rx skb %pK len %d ftype %02x stype %02x\n",
+ "event mgmt rx skb %p len %d ftype %02x stype %02x\n",
skb, skb->len,
fc & IEEE80211_FCTL_FTYPE, fc & IEEE80211_FCTL_STYPE);
@@ -7579,7 +7670,7 @@ static void ath11k_mgmt_tx_compl_event(struct ath11k_base *ab, struct sk_buff *s
wmi_process_mgmt_tx_comp(ar, &tx_compl_param);
ath11k_dbg(ab, ATH11K_DBG_MGMT,
- "mgmt tx compl ev pdev_id %d, desc_id %d, status %d ack_rssi %d",
+ "event mgmt tx compl ev pdev_id %d, desc_id %d, status %d ack_rssi %d",
tx_compl_param.pdev_id, tx_compl_param.desc_id,
tx_compl_param.status, tx_compl_param.ack_rssi);
@@ -7650,7 +7741,7 @@ static void ath11k_scan_event(struct ath11k_base *ab, struct sk_buff *skb)
spin_lock_bh(&ar->data_lock);
ath11k_dbg(ab, ATH11K_DBG_WMI,
- "scan event %s type %d reason %d freq %d req_id %d scan_id %d vdev_id %d state %s (%d)\n",
+ "event scan %s type %d reason %d freq %d req_id %d scan_id %d vdev_id %d state %s (%d)\n",
ath11k_wmi_event_scan_type_str(scan_ev.event_type, scan_ev.reason),
scan_ev.event_type, scan_ev.reason, scan_ev.channel_freq,
scan_ev.scan_req_id, scan_ev.scan_id, scan_ev.vdev_id,
@@ -7733,7 +7824,7 @@ static void ath11k_peer_sta_kickout_event(struct ath11k_base *ab, struct sk_buff
goto exit;
}
- ath11k_dbg(ab, ATH11K_DBG_WMI, "peer sta kickout event %pM",
+ ath11k_dbg(ab, ATH11K_DBG_WMI, "event peer sta kickout %pM",
arg.mac_addr);
ieee80211_report_low_ack(sta, 10);
@@ -7753,7 +7844,7 @@ static void ath11k_roam_event(struct ath11k_base *ab, struct sk_buff *skb)
}
ath11k_dbg(ab, ATH11K_DBG_WMI,
- "wmi roam event vdev %u reason 0x%08x rssi %d\n",
+ "event roam vdev %u reason 0x%08x rssi %d\n",
roam_ev.vdev_id, roam_ev.reason, roam_ev.rssi);
rcu_read_lock();
@@ -7800,7 +7891,7 @@ static void ath11k_chan_info_event(struct ath11k_base *ab, struct sk_buff *skb)
}
ath11k_dbg(ab, ATH11K_DBG_WMI,
- "chan info vdev_id %d err_code %d freq %d cmd_flags %d noise_floor %d rx_clear_count %d cycle_count %d mac_clk_mhz %d\n",
+ "event chan info vdev_id %d err_code %d freq %d cmd_flags %d noise_floor %d rx_clear_count %d cycle_count %d mac_clk_mhz %d\n",
ch_info_ev.vdev_id, ch_info_ev.err_code, ch_info_ev.freq,
ch_info_ev.cmd_flags, ch_info_ev.noise_floor,
ch_info_ev.rx_clear_count, ch_info_ev.cycle_count,
@@ -7889,7 +7980,7 @@ ath11k_pdev_bss_chan_info_event(struct ath11k_base *ab, struct sk_buff *skb)
bss_ch_info_ev.rx_bss_cycle_count_low;
ath11k_dbg(ab, ATH11K_DBG_WMI,
- "pdev bss chan info:\n pdev_id: %d freq: %d noise: %d cycle: busy %llu total %llu tx %llu rx %llu rx_bss %llu\n",
+ "event pdev bss chan info:\n pdev_id: %d freq: %d noise: %d cycle: busy %llu total %llu tx %llu rx %llu rx_bss %llu\n",
bss_ch_info_ev.pdev_id, bss_ch_info_ev.freq,
bss_ch_info_ev.noise_floor, busy, total,
tx, rx, rx_bss);
@@ -7943,7 +8034,7 @@ static void ath11k_vdev_install_key_compl_event(struct ath11k_base *ab,
}
ath11k_dbg(ab, ATH11K_DBG_WMI,
- "vdev install key ev idx %d flags %08x macaddr %pM status %d\n",
+ "event vdev install key ev idx %d flags %08x macaddr %pM status %d\n",
install_key_compl.key_idx, install_key_compl.key_flags,
install_key_compl.macaddr, install_key_compl.status);
@@ -8026,6 +8117,8 @@ static void ath11k_service_available_event(struct ath11k_base *ab, struct sk_buf
NULL);
if (ret)
ath11k_warn(ab, "failed to parse services available tlv %d\n", ret);
+
+ ath11k_dbg(ab, ATH11K_DBG_WMI, "event service available");
}
static void ath11k_peer_assoc_conf_event(struct ath11k_base *ab, struct sk_buff *skb)
@@ -8039,7 +8132,7 @@ static void ath11k_peer_assoc_conf_event(struct ath11k_base *ab, struct sk_buff
}
ath11k_dbg(ab, ATH11K_DBG_WMI,
- "peer assoc conf ev vdev id %d macaddr %pM\n",
+ "event peer assoc conf ev vdev id %d macaddr %pM\n",
peer_assoc_conf.vdev_id, peer_assoc_conf.macaddr);
rcu_read_lock();
@@ -8072,6 +8165,8 @@ static void ath11k_update_stats_event(struct ath11k_base *ab, struct sk_buff *sk
goto free;
}
+ ath11k_dbg(ab, ATH11K_DBG_WMI, "event update stats");
+
rcu_read_lock();
ar = ath11k_mac_get_ar_by_pdev_id(ab, stats.pdev_id);
if (!ar) {
@@ -8103,6 +8198,11 @@ complete:
rcu_read_unlock();
spin_unlock_bh(&ar->data_lock);
+ /* Since the stats's pdev, vdev and beacon list are spliced and reinitialised
+ * at this point, no need to free the individual list.
+ */
+ return;
+
free:
ath11k_fw_stats_free(&stats);
}
@@ -8132,7 +8232,7 @@ static void ath11k_pdev_ctl_failsafe_check_event(struct ath11k_base *ab,
}
ath11k_dbg(ab, ATH11K_DBG_WMI,
- "pdev ctl failsafe check ev status %d\n",
+ "event pdev ctl failsafe check status %d\n",
ev->ctl_failsafe_status);
/* If ctl_failsafe_status is set to 1 FW will max out the Transmit power
@@ -8199,7 +8299,7 @@ ath11k_wmi_pdev_csa_switch_count_status_event(struct ath11k_base *ab,
}
ath11k_dbg(ab, ATH11K_DBG_WMI,
- "pdev csa switch count %d for pdev %d, num_vdevs %d",
+ "event pdev csa switch count %d for pdev %d, num_vdevs %d",
ev->current_switch_count, ev->pdev_id,
ev->num_vdevs);
@@ -8232,7 +8332,7 @@ ath11k_wmi_pdev_dfs_radar_detected_event(struct ath11k_base *ab, struct sk_buff
}
ath11k_dbg(ab, ATH11K_DBG_WMI,
- "pdev dfs radar detected on pdev %d, detection mode %d, chan freq %d, chan_width %d, detector id %d, seg id %d, timestamp %d, chirp %d, freq offset %d, sidx %d",
+ "event pdev dfs radar detected on pdev %d, detection mode %d, chan freq %d, chan_width %d, detector id %d, seg id %d, timestamp %d, chirp %d, freq offset %d, sidx %d",
ev->pdev_id, ev->detection_mode, ev->chan_freq, ev->chan_width,
ev->detector_id, ev->segment_id, ev->timestamp, ev->is_chirp,
ev->freq_offset, ev->sidx);
@@ -8280,8 +8380,8 @@ ath11k_wmi_pdev_temperature_event(struct ath11k_base *ab,
return;
}
- ath11k_dbg(ab, ATH11K_DBG_WMI,
- "pdev temperature ev temp %d pdev_id %d\n", ev->temp, ev->pdev_id);
+ ath11k_dbg(ab, ATH11K_DBG_WMI, "event pdev temperature ev temp %d pdev_id %d\n",
+ ev->temp, ev->pdev_id);
ar = ath11k_mac_get_ar_by_pdev_id(ab, ev->pdev_id);
if (!ar) {
@@ -8311,6 +8411,8 @@ static void ath11k_fils_discovery_event(struct ath11k_base *ab,
return;
}
+ ath11k_dbg(ab, ATH11K_DBG_WMI, "event fils discovery");
+
ev = tb[WMI_TAG_HOST_SWFDA_EVENT];
if (!ev) {
ath11k_warn(ab, "failed to fetch FILS discovery event\n");
@@ -8341,6 +8443,8 @@ static void ath11k_probe_resp_tx_status_event(struct ath11k_base *ab,
return;
}
+ ath11k_dbg(ab, ATH11K_DBG_WMI, "event probe resp tx status");
+
ev = tb[WMI_TAG_OFFLOAD_PRB_RSP_TX_STATUS_EVENT];
if (!ev) {
ath11k_warn(ab,
@@ -8407,6 +8511,8 @@ static void ath11k_wmi_event_wow_wakeup_host(struct ath11k_base *ab, struct sk_b
return;
}
+ ath11k_dbg(ab, ATH11K_DBG_WMI, "event wow wakeup host");
+
complete(&ab->wow.wakeup_completed);
}
@@ -8414,6 +8520,8 @@ static void
ath11k_wmi_diag_event(struct ath11k_base *ab,
struct sk_buff *skb)
{
+ ath11k_dbg(ab, ATH11K_DBG_WMI, "event diag");
+
trace_ath11k_wmi_diag(ab, skb->data, skb->len);
}
@@ -8461,6 +8569,8 @@ static void ath11k_wmi_twt_add_dialog_event(struct ath11k_base *ab,
return;
}
+ ath11k_dbg(ab, ATH11K_DBG_WMI, "event twt add dialog");
+
ev = tb[WMI_TAG_TWT_ADD_DIALOG_COMPLETE_EVENT];
if (!ev) {
ath11k_warn(ab, "failed to fetch twt add dialog wmi event\n");
@@ -8509,7 +8619,7 @@ static void ath11k_wmi_gtk_offload_status_event(struct ath11k_base *ab,
return;
}
- ath11k_dbg(ab, ATH11K_DBG_WMI, "wmi gtk offload event refresh_cnt %d\n",
+ ath11k_dbg(ab, ATH11K_DBG_WMI, "event gtk offload refresh_cnt %d\n",
ev->refresh_cnt);
ath11k_dbg_dump(ab, ATH11K_DBG_WMI, "replay_cnt",
NULL, ev->replay_ctr.counter, GTK_REPLAY_COUNTER_BYTES);
@@ -8612,6 +8722,9 @@ static void ath11k_wmi_tlv_op_rx(struct ath11k_base *ab, struct sk_buff *skb)
case WMI_PDEV_CSA_SWITCH_COUNT_STATUS_EVENTID:
ath11k_wmi_pdev_csa_switch_count_status_event(ab, skb);
break;
+ case WMI_PDEV_UTF_EVENTID:
+ ath11k_tm_wmi_event(ab, id, skb);
+ break;
case WMI_PDEV_TEMPERATURE_EVENTID:
ath11k_wmi_pdev_temperature_event(ab, skb);
break;
@@ -8630,19 +8743,6 @@ static void ath11k_wmi_tlv_op_rx(struct ath11k_base *ab, struct sk_buff *skb)
case WMI_TWT_ADD_DIALOG_EVENTID:
ath11k_wmi_twt_add_dialog_event(ab, skb);
break;
- /* add Unsupported events here */
- case WMI_TBTTOFFSET_EXT_UPDATE_EVENTID:
- case WMI_PEER_OPER_MODE_CHANGE_EVENTID:
- case WMI_TWT_ENABLE_EVENTID:
- case WMI_TWT_DISABLE_EVENTID:
- case WMI_TWT_DEL_DIALOG_EVENTID:
- case WMI_TWT_PAUSE_DIALOG_EVENTID:
- case WMI_TWT_RESUME_DIALOG_EVENTID:
- case WMI_PDEV_DMA_RING_CFG_RSP_EVENTID:
- case WMI_PEER_CREATE_CONF_EVENTID:
- ath11k_dbg(ab, ATH11K_DBG_WMI,
- "ignoring unsupported event 0x%x\n", id);
- break;
case WMI_PDEV_DFS_RADAR_DETECTION_EVENTID:
ath11k_wmi_pdev_dfs_radar_detected_event(ab, skb);
break;
@@ -8664,9 +8764,8 @@ static void ath11k_wmi_tlv_op_rx(struct ath11k_base *ab, struct sk_buff *skb)
case WMI_GTK_OFFLOAD_STATUS_EVENTID:
ath11k_wmi_gtk_offload_status_event(ab, skb);
break;
- /* TODO: Add remaining events */
default:
- ath11k_dbg(ab, ATH11K_DBG_WMI, "Unknown eventid: 0x%x\n", id);
+ ath11k_dbg(ab, ATH11K_DBG_WMI, "unsupported event id 0x%x\n", id);
break;
}
@@ -8763,7 +8862,7 @@ ath11k_wmi_send_unit_test_cmd(struct ath11k *ar,
}
ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "WMI unit test : module %d vdev %d n_args %d token %d\n",
+ "cmd unit test module %d vdev %d n_args %d token %d\n",
cmd->module_id, cmd->vdev_id, cmd->num_args,
cmd->diag_token);
@@ -8855,6 +8954,9 @@ int ath11k_wmi_fw_dbglog_cfg(struct ath11k *ar, u32 *module_id_bitmap,
"failed to send WMI_DBGLOG_CFG_CMDID\n");
dev_kfree_skb(skb);
}
+
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "cmd dbglog cfg");
+
return ret;
}
@@ -8960,7 +9062,7 @@ int ath11k_wmi_hw_data_filter_cmd(struct ath11k *ar, u32 vdev_id,
cmd->hw_filter_bitmap = ((u32)~0U);
ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "wmi hw data filter enable %d filter_bitmap 0x%x\n",
+ "hw data filter enable %d filter_bitmap 0x%x\n",
enable, filter_bitmap);
return ath11k_wmi_cmd_send(ar->wmi, skb, WMI_HW_DATA_FILTER_CMDID);
@@ -8982,7 +9084,7 @@ int ath11k_wmi_wow_host_wakeup_ind(struct ath11k *ar)
WMI_TAG_WOW_HOSTWAKEUP_FROM_SLEEP_CMD) |
FIELD_PREP(WMI_TLV_LEN, sizeof(*cmd) - TLV_HDR_SIZE);
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "wmi tlv wow host wakeup ind\n");
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "tlv wow host wakeup ind\n");
return ath11k_wmi_cmd_send(ar->wmi, skb, WMI_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID);
}
@@ -9004,7 +9106,7 @@ int ath11k_wmi_wow_enable(struct ath11k *ar)
cmd->enable = 1;
cmd->pause_iface_config = WOW_IFACE_PAUSE_ENABLED;
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "wmi tlv wow enable\n");
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "tlv wow enable\n");
return ath11k_wmi_cmd_send(ar->wmi, skb, WMI_WOW_ENABLE_CMDID);
}
@@ -9031,7 +9133,7 @@ int ath11k_wmi_scan_prob_req_oui(struct ath11k *ar,
FIELD_PREP(WMI_TLV_LEN, sizeof(*cmd) - TLV_HDR_SIZE);
cmd->prob_req_oui = prob_req_oui;
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "wmi scan prob req oui %d\n",
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "scan prob req oui %d\n",
prob_req_oui);
return ath11k_wmi_cmd_send(ar->wmi, skb, WMI_SCAN_PROB_REQ_OUI_CMDID);
@@ -9058,7 +9160,7 @@ int ath11k_wmi_wow_add_wakeup_event(struct ath11k *ar, u32 vdev_id,
cmd->is_add = enable;
cmd->event_bitmap = (1 << event);
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "wmi tlv wow add wakeup event %s enable %d vdev_id %d\n",
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "tlv wow add wakeup event %s enable %d vdev_id %d\n",
wow_wakeup_event(event), enable, vdev_id);
return ath11k_wmi_cmd_send(ar->wmi, skb, WMI_WOW_ENABLE_DISABLE_WAKE_EVENT_CMDID);
@@ -9163,7 +9265,7 @@ int ath11k_wmi_wow_add_pattern(struct ath11k *ar, u32 vdev_id, u32 pattern_id,
WMI_TAG_ARRAY_UINT32) |
FIELD_PREP(WMI_TLV_LEN, sizeof(u32));
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "wmi tlv wow add pattern vdev_id %d pattern_id %d pattern_offset %d\n",
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "tlv wow add pattern vdev_id %d pattern_id %d pattern_offset %d\n",
vdev_id, pattern_id, pattern_offset);
return ath11k_wmi_cmd_send(ar->wmi, skb, WMI_WOW_ADD_WAKE_PATTERN_CMDID);
@@ -9189,7 +9291,7 @@ int ath11k_wmi_wow_del_pattern(struct ath11k *ar, u32 vdev_id, u32 pattern_id)
cmd->pattern_id = pattern_id;
cmd->pattern_type = WOW_BITMAP_PATTERN;
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "wmi tlv wow del pattern vdev_id %d pattern_id %d\n",
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "tlv wow del pattern vdev_id %d pattern_id %d\n",
vdev_id, pattern_id);
return ath11k_wmi_cmd_send(ar->wmi, skb, WMI_WOW_DEL_WAKE_PATTERN_CMDID);
@@ -9302,7 +9404,7 @@ ath11k_wmi_op_gen_config_pno_start(struct ath11k *ar,
for (i = 0; i < cmd->num_of_channels; i++)
channel_list[i] = pno->a_networks[0].channels[i];
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "wmi tlv start pno config vdev_id %d\n",
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "tlv start pno config vdev_id %d\n",
vdev_id);
return skb;
@@ -9328,7 +9430,7 @@ static struct sk_buff *ath11k_wmi_op_gen_config_pno_stop(struct ath11k *ar,
cmd->flags = WMI_NLO_CONFIG_STOP;
ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "wmi tlv stop pno config vdev_id %d\n", vdev_id);
+ "tlv stop pno config vdev_id %d\n", vdev_id);
return skb;
}
@@ -9405,7 +9507,7 @@ static void ath11k_wmi_fill_ns_offload(struct ath11k *ar,
}
ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "wmi index %d ns_solicited %pI6 target %pI6",
+ "index %d ns_solicited %pI6 target %pI6",
i, ns->solicitation_ipaddr,
ns->target_ipaddr[0]);
}
@@ -9443,7 +9545,7 @@ static void ath11k_wmi_fill_arp_offload(struct ath11k *ar,
memcpy(arp->target_ipaddr, offload->ipv4_addr[i], 4);
ath11k_ce_byte_swap(arp->target_ipaddr, 4);
- ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "wmi arp offload address %pI4",
+ ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "arp offload address %pI4",
arp->target_ipaddr);
}
@@ -9676,7 +9778,7 @@ int ath11k_wmi_sta_keepalive(struct ath11k *ar,
}
ath11k_dbg(ar->ab, ATH11K_DBG_WMI,
- "wmi sta keepalive vdev %d enabled %d method %d interval %d\n",
+ "sta keepalive vdev %d enabled %d method %d interval %d\n",
arg->vdev_id, arg->enabled, arg->method, arg->interval);
return ath11k_wmi_cmd_send(wmi, skb, WMI_STA_KEEPALIVE_CMDID);
diff --git a/drivers/net/wireless/ath/ath11k/wmi.h b/drivers/net/wireless/ath/ath11k/wmi.h
index 92fddb77669c..100bb816b592 100644
--- a/drivers/net/wireless/ath/ath11k/wmi.h
+++ b/drivers/net/wireless/ath/ath11k/wmi.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: BSD-3-Clause-Clear */
/*
* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef ATH11K_WMI_H
@@ -68,6 +69,7 @@ struct wmi_tlv {
#define WMI_APPEND_TO_EXISTING_CHAN_LIST_FLAG 1
+#define MAX_WMI_UTF_LEN 252
#define WMI_BA_MODE_BUFFER_SIZE_256 3
/*
* HW mode config type replicated from FW header
@@ -137,6 +139,14 @@ enum {
WMI_AUTORATE_3200NS_GI = BIT(11),
};
+enum {
+ WMI_HOST_VDEV_FLAGS_NON_MBSSID_AP = 0x00000001,
+ WMI_HOST_VDEV_FLAGS_TRANSMIT_AP = 0x00000002,
+ WMI_HOST_VDEV_FLAGS_NON_TRANSMIT_AP = 0x00000004,
+ WMI_HOST_VDEV_FLAGS_EMA_MODE = 0x00000008,
+ WMI_HOST_VDEV_FLAGS_SCAN_MODE_VAP = 0x00000010,
+};
+
/*
* wmi command groups.
*/
@@ -2096,6 +2106,7 @@ enum wmi_tlv_service {
WMI_TLV_SERVICE_EXT2_MSG = 220,
WMI_TLV_SERVICE_PEER_POWER_SAVE_DURATION_SUPPORT = 246,
WMI_TLV_SERVICE_SRG_SRP_SPATIAL_REUSE_SUPPORT = 249,
+ WMI_TLV_SERVICE_MBSS_PARAM_IN_VDEV_START_SUPPORT = 253,
WMI_TLV_SERVICE_PASSIVE_SCAN_START_TIME_ENHANCE = 263,
/* The second 128 bits */
@@ -2317,6 +2328,7 @@ struct wmi_init_cmd {
} __packed;
#define WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64 BIT(5)
+#define WMI_RSRC_CFG_FLAG2_CALC_NEXT_DTIM_COUNT_SET BIT(9)
#define WMI_RSRC_CFG_FLAG1_ACK_RSSI BIT(18)
#define WMI_CFG_HOST_SERVICE_FLAG_REG_CC_EXT 4
@@ -2389,6 +2401,9 @@ struct wmi_resource_config {
u32 msdu_flow_override_config1;
u32 flags2;
u32 host_service_flags;
+ u32 max_rnr_neighbours;
+ u32 ema_max_vap_cnt;
+ u32 ema_max_profile_period;
} __packed;
struct wmi_service_ready_event {
@@ -2579,6 +2594,8 @@ struct vdev_create_params {
u8 rx;
} chains[NUM_NL80211_BANDS];
u32 pdev_id;
+ u32 mbssid_flags;
+ u32 mbssid_tx_vdev_id;
};
struct wmi_vdev_create_cmd {
@@ -2589,6 +2606,8 @@ struct wmi_vdev_create_cmd {
struct wmi_mac_addr vdev_macaddr;
u32 num_cfg_txrx_streams;
u32 pdev_id;
+ u32 mbssid_flags;
+ u32 mbssid_tx_vdev_id;
} __packed;
struct wmi_vdev_txrx_streams {
@@ -2608,9 +2627,9 @@ struct wmi_vdev_up_cmd {
u32 vdev_id;
u32 vdev_assoc_id;
struct wmi_mac_addr vdev_bssid;
- struct wmi_mac_addr trans_bssid;
- u32 profile_idx;
- u32 profile_num;
+ struct wmi_mac_addr tx_vdev_bssid;
+ u32 nontx_profile_idx;
+ u32 nontx_profile_cnt;
} __packed;
struct wmi_vdev_stop_cmd {
@@ -2652,6 +2671,9 @@ struct wmi_vdev_start_request_cmd {
u32 he_ops;
u32 cac_duration_ms;
u32 regdomain;
+ u32 min_data_rate;
+ u32 mbssid_flags;
+ u32 mbssid_tx_vdev_id;
} __packed;
#define MGMT_TX_DL_FRM_LEN 64
@@ -2821,6 +2843,9 @@ struct wmi_vdev_start_req_arg {
u32 pref_rx_streams;
u32 pref_tx_streams;
u32 num_noa_descriptors;
+ u32 min_data_rate;
+ u32 mbssid_flags;
+ u32 mbssid_tx_vdev_id;
};
struct peer_create_params {
@@ -3541,8 +3566,30 @@ struct wmi_get_pdev_temperature_cmd {
u32 pdev_id;
} __packed;
+struct wmi_ftm_seg_hdr {
+ u32 len;
+ u32 msgref;
+ u32 segmentinfo;
+ u32 pdev_id;
+} __packed;
+
+struct wmi_ftm_cmd {
+ u32 tlv_header;
+ struct wmi_ftm_seg_hdr seg_hdr;
+ u8 data[];
+} __packed;
+
+struct wmi_ftm_event_msg {
+ struct wmi_ftm_seg_hdr seg_hdr;
+ u8 data[];
+} __packed;
+
#define WMI_BEACON_TX_BUFFER_SIZE 512
+#define WMI_EMA_TMPL_IDX_SHIFT 8
+#define WMI_EMA_FIRST_TMPL_SHIFT 16
+#define WMI_EMA_LAST_TMPL_SHIFT 24
+
struct wmi_bcn_tmpl_cmd {
u32 tlv_header;
u32 vdev_id;
@@ -3553,6 +3600,11 @@ struct wmi_bcn_tmpl_cmd {
u32 csa_event_bitmap;
u32 mbssid_ie_offset;
u32 esp_ie_offset;
+ u32 csc_switch_count_offset;
+ u32 csc_event_bitmap;
+ u32 mu_edca_ie_offset;
+ u32 feature_enable_bitmap;
+ u32 ema_params;
} __packed;
struct wmi_key_seq_counter {
@@ -5646,6 +5698,8 @@ struct target_resource_config {
u32 twt_ap_pdev_count;
u32 twt_ap_sta_count;
u8 is_reg_cc_ext_event_supported;
+ u32 ema_max_vap_cnt;
+ u32 ema_max_profile_period;
};
enum wmi_debug_log_param {
@@ -6266,6 +6320,8 @@ enum wmi_sta_keepalive_method {
#define WMI_STA_KEEPALIVE_INTERVAL_DEFAULT 30
#define WMI_STA_KEEPALIVE_INTERVAL_DISABLE 0
+const void **ath11k_wmi_tlv_parse_alloc(struct ath11k_base *ab, const void *ptr,
+ size_t len, gfp_t gfp);
int ath11k_wmi_cmd_send(struct ath11k_pdev_wmi *wmi, struct sk_buff *skb,
u32 cmd_id);
struct sk_buff *ath11k_wmi_alloc_skb(struct ath11k_wmi_base *wmi_sc, u32 len);
@@ -6273,10 +6329,11 @@ int ath11k_wmi_mgmt_send(struct ath11k *ar, u32 vdev_id, u32 buf_id,
struct sk_buff *frame);
int ath11k_wmi_bcn_tmpl(struct ath11k *ar, u32 vdev_id,
struct ieee80211_mutable_offsets *offs,
- struct sk_buff *bcn);
+ struct sk_buff *bcn, u32 ema_param);
int ath11k_wmi_vdev_down(struct ath11k *ar, u8 vdev_id);
int ath11k_wmi_vdev_up(struct ath11k *ar, u32 vdev_id, u32 aid,
- const u8 *bssid);
+ const u8 *bssid, u8 *tx_bssid, u32 nontx_profile_idx,
+ u32 nontx_profile_cnt);
int ath11k_wmi_vdev_stop(struct ath11k *ar, u8 vdev_id);
int ath11k_wmi_vdev_start(struct ath11k *ar, struct wmi_vdev_start_req_arg *arg,
bool restart);
@@ -6372,9 +6429,6 @@ int ath11k_wmi_send_pdev_set_regdomain(struct ath11k *ar,
struct pdev_set_regdomain_params *param);
int ath11k_wmi_pull_fw_stats(struct ath11k_base *ab, struct sk_buff *skb,
struct ath11k_fw_stats *stats);
-size_t ath11k_wmi_fw_stats_num_peers(struct list_head *head);
-size_t ath11k_wmi_fw_stats_num_peers_extd(struct list_head *head);
-size_t ath11k_wmi_fw_stats_num_vdevs(struct list_head *head);
void ath11k_wmi_fw_stats_fill(struct ath11k *ar,
struct ath11k_fw_stats *fw_stats, u32 stats_id,
char *buf);
diff --git a/drivers/net/wireless/ath/ath11k/wow.c b/drivers/net/wireless/ath/ath11k/wow.c
index 1dec23b0699c..99d8ba45a75b 100644
--- a/drivers/net/wireless/ath/ath11k/wow.c
+++ b/drivers/net/wireless/ath/ath11k/wow.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause-Clear
/*
* Copyright (c) 2020 The Linux Foundation. All rights reserved.
- * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/delay.h>
@@ -838,6 +838,7 @@ exit:
case ATH11K_STATE_RESTARTING:
case ATH11K_STATE_RESTARTED:
case ATH11K_STATE_WEDGED:
+ case ATH11K_STATE_FTM:
ath11k_warn(ar->ab, "encountered unexpected device state %d on resume, cannot recover\n",
ar->state);
ret = -EIO;
diff --git a/drivers/net/wireless/ath/ath12k/core.c b/drivers/net/wireless/ath/ath12k/core.c
index a89e66653f04..3df8059d5512 100644
--- a/drivers/net/wireless/ath/ath12k/core.c
+++ b/drivers/net/wireless/ath/ath12k/core.c
@@ -706,6 +706,7 @@ static void ath12k_core_pre_reconfigure_recovery(struct ath12k_base *ab)
idr_for_each(&ar->txmgmt_idr,
ath12k_mac_tx_mgmt_pending_free, ar);
idr_destroy(&ar->txmgmt_idr);
+ wake_up(&ar->txmgmt_empty_waitq);
}
wake_up(&ab->wmi_ab.tx_credits_wq);
@@ -885,6 +886,7 @@ void ath12k_core_deinit(struct ath12k_base *ab)
void ath12k_core_free(struct ath12k_base *ab)
{
+ timer_delete_sync(&ab->rx_replenish_retry);
destroy_workqueue(ab->workqueue_aux);
destroy_workqueue(ab->workqueue);
kfree(ab);
diff --git a/drivers/net/wireless/ath/ath12k/core.h b/drivers/net/wireless/ath/ath12k/core.h
index 9439052a652e..2f93296db792 100644
--- a/drivers/net/wireless/ath/ath12k/core.h
+++ b/drivers/net/wireless/ath/ath12k/core.h
@@ -533,6 +533,7 @@ struct ath12k {
/* protects txmgmt_idr data */
spinlock_t txmgmt_idr_lock;
atomic_t num_pending_mgmt_tx;
+ wait_queue_head_t txmgmt_empty_waitq;
/* cycle count is reported twice for each visited channel during scan.
* access protected by data_lock
diff --git a/drivers/net/wireless/ath/ath12k/dp_rx.c b/drivers/net/wireless/ath/ath12k/dp_rx.c
index e78478a5b978..ffd9a2018610 100644
--- a/drivers/net/wireless/ath/ath12k/dp_rx.c
+++ b/drivers/net/wireless/ath/ath12k/dp_rx.c
@@ -193,11 +193,11 @@ static void ath12k_dp_rxdesc_set_msdu_len(struct ath12k_base *ab,
ab->hw_params->hal_ops->rx_desc_set_msdu_len(desc, len);
}
-static bool ath12k_dp_rx_h_is_mcbc(struct ath12k_base *ab,
- struct hal_rx_desc *desc)
+static bool ath12k_dp_rx_h_is_da_mcbc(struct ath12k_base *ab,
+ struct hal_rx_desc *desc)
{
return (ath12k_dp_rx_h_first_msdu(ab, desc) &&
- ab->hw_params->hal_ops->rx_desc_is_mcbc(desc));
+ ab->hw_params->hal_ops->rx_desc_is_da_mcbc(desc));
}
static bool ath12k_dp_rxdesc_mac_addr2_valid(struct ath12k_base *ab,
@@ -978,7 +978,19 @@ int ath12k_dp_rx_peer_tid_setup(struct ath12k *ar, const u8 *peer_mac, int vdev_
return ret;
}
- return ret;
+ if (!ab->hw_params->reoq_lut_support) {
+ ret = ath12k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
+ peer_mac,
+ paddr, tid, 1,
+ ba_win_sz);
+ if (ret) {
+ ath12k_warn(ab, "failed to setup peer rx reorder queuefor tid %d: %d\n",
+ tid, ret);
+ return ret;
+ }
+ }
+
+ return 0;
}
rx_tid->tid = tid;
@@ -1362,11 +1374,6 @@ ath12k_update_per_peer_tx_stats(struct ath12k *ar,
* Firmware rate's control to be skipped for this?
*/
- if (flags == WMI_RATE_PREAMBLE_HE && mcs > 11) {
- ath12k_warn(ab, "Invalid HE mcs %d peer stats", mcs);
- return;
- }
-
if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH12K_HE_MCS_MAX) {
ath12k_warn(ab, "Invalid HE mcs %d peer stats", mcs);
return;
@@ -2201,7 +2208,7 @@ static void ath12k_dp_rx_h_mpdu(struct ath12k *ar,
/* PN for multicast packets will be checked in mac80211 */
rxcb = ATH12K_SKB_RXCB(msdu);
- fill_crypto_hdr = ath12k_dp_rx_h_is_mcbc(ar->ab, rx_desc);
+ fill_crypto_hdr = ath12k_dp_rx_h_is_da_mcbc(ar->ab, rx_desc);
rxcb->is_mcbc = fill_crypto_hdr;
if (rxcb->is_mcbc)
diff --git a/drivers/net/wireless/ath/ath12k/hal.c b/drivers/net/wireless/ath/ath12k/hal.c
index 0ec53afe9915..e7a150e7158e 100644
--- a/drivers/net/wireless/ath/ath12k/hal.c
+++ b/drivers/net/wireless/ath/ath12k/hal.c
@@ -447,10 +447,10 @@ static u8 *ath12k_hw_qcn9274_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc)
return desc->u.qcn9274.mpdu_start.addr2;
}
-static bool ath12k_hw_qcn9274_rx_desc_is_mcbc(struct hal_rx_desc *desc)
+static bool ath12k_hw_qcn9274_rx_desc_is_da_mcbc(struct hal_rx_desc *desc)
{
- return __le32_to_cpu(desc->u.qcn9274.mpdu_start.info6) &
- RX_MPDU_START_INFO6_MCAST_BCAST;
+ return __le16_to_cpu(desc->u.qcn9274.msdu_end.info5) &
+ RX_MSDU_END_INFO5_DA_IS_MCBC;
}
static void ath12k_hw_qcn9274_rx_desc_get_dot11_hdr(struct hal_rx_desc *desc,
@@ -708,7 +708,7 @@ const struct hal_ops hal_qcn9274_ops = {
.rx_desc_get_msdu_end_offset = ath12k_hw_qcn9274_rx_desc_get_msdu_end_offset,
.rx_desc_mac_addr2_valid = ath12k_hw_qcn9274_rx_desc_mac_addr2_valid,
.rx_desc_mpdu_start_addr2 = ath12k_hw_qcn9274_rx_desc_mpdu_start_addr2,
- .rx_desc_is_mcbc = ath12k_hw_qcn9274_rx_desc_is_mcbc,
+ .rx_desc_is_da_mcbc = ath12k_hw_qcn9274_rx_desc_is_da_mcbc,
.rx_desc_get_dot11_hdr = ath12k_hw_qcn9274_rx_desc_get_dot11_hdr,
.rx_desc_get_crypto_header = ath12k_hw_qcn9274_rx_desc_get_crypto_hdr,
.rx_desc_get_mpdu_frame_ctl = ath12k_hw_qcn9274_rx_desc_get_mpdu_frame_ctl,
@@ -887,10 +887,10 @@ static u8 *ath12k_hw_wcn7850_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc)
return desc->u.wcn7850.mpdu_start.addr2;
}
-static bool ath12k_hw_wcn7850_rx_desc_is_mcbc(struct hal_rx_desc *desc)
+static bool ath12k_hw_wcn7850_rx_desc_is_da_mcbc(struct hal_rx_desc *desc)
{
- return __le32_to_cpu(desc->u.wcn7850.mpdu_start.info6) &
- RX_MPDU_START_INFO6_MCAST_BCAST;
+ return __le16_to_cpu(desc->u.wcn7850.msdu_end.info5) &
+ RX_MSDU_END_INFO5_DA_IS_MCBC;
}
static void ath12k_hw_wcn7850_rx_desc_get_dot11_hdr(struct hal_rx_desc *desc,
@@ -1163,7 +1163,7 @@ const struct hal_ops hal_wcn7850_ops = {
.rx_desc_get_msdu_end_offset = ath12k_hw_wcn7850_rx_desc_get_msdu_end_offset,
.rx_desc_mac_addr2_valid = ath12k_hw_wcn7850_rx_desc_mac_addr2_valid,
.rx_desc_mpdu_start_addr2 = ath12k_hw_wcn7850_rx_desc_mpdu_start_addr2,
- .rx_desc_is_mcbc = ath12k_hw_wcn7850_rx_desc_is_mcbc,
+ .rx_desc_is_da_mcbc = ath12k_hw_wcn7850_rx_desc_is_da_mcbc,
.rx_desc_get_dot11_hdr = ath12k_hw_wcn7850_rx_desc_get_dot11_hdr,
.rx_desc_get_crypto_header = ath12k_hw_wcn7850_rx_desc_get_crypto_hdr,
.rx_desc_get_mpdu_frame_ctl = ath12k_hw_wcn7850_rx_desc_get_mpdu_frame_ctl,
diff --git a/drivers/net/wireless/ath/ath12k/hal.h b/drivers/net/wireless/ath/ath12k/hal.h
index 0d4fa12ea622..66035a787c72 100644
--- a/drivers/net/wireless/ath/ath12k/hal.h
+++ b/drivers/net/wireless/ath/ath12k/hal.h
@@ -1063,7 +1063,7 @@ struct hal_ops {
u32 (*rx_desc_get_msdu_end_offset)(void);
bool (*rx_desc_mac_addr2_valid)(struct hal_rx_desc *desc);
u8* (*rx_desc_mpdu_start_addr2)(struct hal_rx_desc *desc);
- bool (*rx_desc_is_mcbc)(struct hal_rx_desc *desc);
+ bool (*rx_desc_is_da_mcbc)(struct hal_rx_desc *desc);
void (*rx_desc_get_dot11_hdr)(struct hal_rx_desc *desc,
struct ieee80211_hdr *hdr);
u16 (*rx_desc_get_mpdu_frame_ctl)(struct hal_rx_desc *desc);
diff --git a/drivers/net/wireless/ath/ath12k/hw.c b/drivers/net/wireless/ath/ath12k/hw.c
index 1ffac7e3deaa..5991cc91cd00 100644
--- a/drivers/net/wireless/ath/ath12k/hw.c
+++ b/drivers/net/wireless/ath/ath12k/hw.c
@@ -906,6 +906,7 @@ static const struct ath12k_hw_params ath12k_hw_params[] = {
.hal_ops = &hal_qcn9274_ops,
+ .qmi_cnss_feature_bitmap = BIT(CNSS_QDSS_CFG_MISS_V01),
},
{
.name = "wcn7850 hw2.0",
@@ -960,6 +961,9 @@ static const struct ath12k_hw_params ath12k_hw_params[] = {
.wmi_init = ath12k_wmi_init_wcn7850,
.hal_ops = &hal_wcn7850_ops,
+
+ .qmi_cnss_feature_bitmap = BIT(CNSS_QDSS_CFG_MISS_V01) |
+ BIT(CNSS_PCIE_PERST_NO_PULL_V01),
},
{
.name = "qcn9274 hw2.0",
@@ -1013,6 +1017,8 @@ static const struct ath12k_hw_params ath12k_hw_params[] = {
.wmi_init = ath12k_wmi_init_qcn9274,
.hal_ops = &hal_qcn9274_ops,
+
+ .qmi_cnss_feature_bitmap = BIT(CNSS_QDSS_CFG_MISS_V01),
},
};
diff --git a/drivers/net/wireless/ath/ath12k/hw.h b/drivers/net/wireless/ath/ath12k/hw.h
index e3461004188b..e6c4223c283c 100644
--- a/drivers/net/wireless/ath/ath12k/hw.h
+++ b/drivers/net/wireless/ath/ath12k/hw.h
@@ -184,6 +184,8 @@ struct ath12k_hw_params {
struct ath12k_wmi_resource_config_arg *config);
const struct hal_ops *hal_ops;
+
+ u64 qmi_cnss_feature_bitmap;
};
struct ath12k_hw_ops {
diff --git a/drivers/net/wireless/ath/ath12k/mac.c b/drivers/net/wireless/ath/ath12k/mac.c
index ee792822b411..1bb9802ef569 100644
--- a/drivers/net/wireless/ath/ath12k/mac.c
+++ b/drivers/net/wireless/ath/ath12k/mac.c
@@ -381,7 +381,7 @@ u8 ath12k_mac_bitrate_to_idx(const struct ieee80211_supported_band *sband,
}
static u32
-ath12k_mac_max_ht_nss(const u8 ht_mcs_mask[IEEE80211_HT_MCS_MASK_LEN])
+ath12k_mac_max_ht_nss(const u8 *ht_mcs_mask)
{
int nss;
@@ -393,7 +393,7 @@ ath12k_mac_max_ht_nss(const u8 ht_mcs_mask[IEEE80211_HT_MCS_MASK_LEN])
}
static u32
-ath12k_mac_max_vht_nss(const u16 vht_mcs_mask[NL80211_VHT_NSS_MAX])
+ath12k_mac_max_vht_nss(const u16 *vht_mcs_mask)
{
int nss;
@@ -771,6 +771,9 @@ static int ath12k_mac_vdev_setup_sync(struct ath12k *ar)
if (test_bit(ATH12K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags))
return -ESHUTDOWN;
+ ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "vdev setup timeout %d\n",
+ ATH12K_VDEV_SETUP_TIMEOUT_HZ);
+
if (!wait_for_completion_timeout(&ar->vdev_setup_done,
ATH12K_VDEV_SETUP_TIMEOUT_HZ))
return -ETIMEDOUT;
@@ -1303,7 +1306,7 @@ static void ath12k_peer_assoc_h_rates(struct ath12k *ar,
}
static bool
-ath12k_peer_assoc_h_ht_masked(const u8 ht_mcs_mask[IEEE80211_HT_MCS_MASK_LEN])
+ath12k_peer_assoc_h_ht_masked(const u8 *ht_mcs_mask)
{
int nss;
@@ -1315,7 +1318,7 @@ ath12k_peer_assoc_h_ht_masked(const u8 ht_mcs_mask[IEEE80211_HT_MCS_MASK_LEN])
}
static bool
-ath12k_peer_assoc_h_vht_masked(const u16 vht_mcs_mask[NL80211_VHT_NSS_MAX])
+ath12k_peer_assoc_h_vht_masked(const u16 *vht_mcs_mask)
{
int nss;
@@ -4375,6 +4378,21 @@ static int __ath12k_set_antenna(struct ath12k *ar, u32 tx_ant, u32 rx_ant)
return 0;
}
+static void ath12k_mgmt_over_wmi_tx_drop(struct ath12k *ar, struct sk_buff *skb)
+{
+ int num_mgmt;
+
+ ieee80211_free_txskb(ar->hw, skb);
+
+ num_mgmt = atomic_dec_if_positive(&ar->num_pending_mgmt_tx);
+
+ if (num_mgmt < 0)
+ WARN_ON_ONCE(1);
+
+ if (!num_mgmt)
+ wake_up(&ar->txmgmt_empty_waitq);
+}
+
int ath12k_mac_tx_mgmt_pending_free(int buf_id, void *skb, void *ctx)
{
struct sk_buff *msdu = skb;
@@ -4391,7 +4409,7 @@ int ath12k_mac_tx_mgmt_pending_free(int buf_id, void *skb, void *ctx)
info = IEEE80211_SKB_CB(msdu);
memset(&info->status, 0, sizeof(info->status));
- ieee80211_free_txskb(ar->hw, msdu);
+ ath12k_mgmt_over_wmi_tx_drop(ar, skb);
return 0;
}
@@ -4425,6 +4443,7 @@ static int ath12k_mac_mgmt_tx_wmi(struct ath12k *ar, struct ath12k_vif *arvif,
int buf_id;
int ret;
+ ATH12K_SKB_CB(skb)->ar = ar;
spin_lock_bh(&ar->txmgmt_idr_lock);
buf_id = idr_alloc(&ar->txmgmt_idr, skb, 0,
ATH12K_TX_MGMT_NUM_PENDING_MAX, GFP_ATOMIC);
@@ -4475,7 +4494,7 @@ static void ath12k_mgmt_over_wmi_tx_purge(struct ath12k *ar)
struct sk_buff *skb;
while ((skb = skb_dequeue(&ar->wmi_mgmt_tx_queue)) != NULL)
- ieee80211_free_txskb(ar->hw, skb);
+ ath12k_mgmt_over_wmi_tx_drop(ar, skb);
}
static void ath12k_mgmt_over_wmi_tx_work(struct work_struct *work)
@@ -4490,7 +4509,7 @@ static void ath12k_mgmt_over_wmi_tx_work(struct work_struct *work)
skb_cb = ATH12K_SKB_CB(skb);
if (!skb_cb->vif) {
ath12k_warn(ar->ab, "no vif found for mgmt frame\n");
- ieee80211_free_txskb(ar->hw, skb);
+ ath12k_mgmt_over_wmi_tx_drop(ar, skb);
continue;
}
@@ -4501,16 +4520,14 @@ static void ath12k_mgmt_over_wmi_tx_work(struct work_struct *work)
if (ret) {
ath12k_warn(ar->ab, "failed to tx mgmt frame, vdev_id %d :%d\n",
arvif->vdev_id, ret);
- ieee80211_free_txskb(ar->hw, skb);
- } else {
- atomic_inc(&ar->num_pending_mgmt_tx);
+ ath12k_mgmt_over_wmi_tx_drop(ar, skb);
}
} else {
ath12k_warn(ar->ab,
"dropping mgmt frame for vdev %d, is_started %d\n",
arvif->vdev_id,
arvif->is_started);
- ieee80211_free_txskb(ar->hw, skb);
+ ath12k_mgmt_over_wmi_tx_drop(ar, skb);
}
}
}
@@ -4535,12 +4552,13 @@ static int ath12k_mac_mgmt_tx(struct ath12k *ar, struct sk_buff *skb,
return -ENOSPC;
}
- if (skb_queue_len(q) == ATH12K_TX_MGMT_NUM_PENDING_MAX) {
+ if (skb_queue_len_lockless(q) >= ATH12K_TX_MGMT_NUM_PENDING_MAX) {
ath12k_warn(ar->ab, "mgmt tx queue is full\n");
return -ENOSPC;
}
skb_queue_tail(q, skb);
+ atomic_inc(&ar->num_pending_mgmt_tx);
ieee80211_queue_work(ar->hw, &ar->wmi_mgmt_tx_work);
return 0;
@@ -5910,7 +5928,6 @@ ath12k_mac_op_unassign_vif_chanctx(struct ieee80211_hw *hw,
}
arvif->is_started = false;
- mutex_unlock(&ar->conf_mutex);
}
ret = ath12k_mac_vdev_stop(arvif);
@@ -6014,6 +6031,13 @@ static void ath12k_mac_op_flush(struct ieee80211_hw *hw, struct ieee80211_vif *v
ATH12K_FLUSH_TIMEOUT);
if (time_left == 0)
ath12k_warn(ar->ab, "failed to flush transmit queue %ld\n", time_left);
+
+ time_left = wait_event_timeout(ar->txmgmt_empty_waitq,
+ (atomic_read(&ar->num_pending_mgmt_tx) == 0),
+ ATH12K_FLUSH_TIMEOUT);
+ if (time_left == 0)
+ ath12k_warn(ar->ab, "failed to flush mgmt transmit queue %ld\n",
+ time_left);
}
static int
@@ -6991,6 +7015,7 @@ int ath12k_mac_register(struct ath12k_base *ab)
if (ret)
goto err_cleanup;
+ init_waitqueue_head(&ar->txmgmt_empty_waitq);
idr_init(&ar->txmgmt_idr);
spin_lock_init(&ar->txmgmt_idr_lock);
}
diff --git a/drivers/net/wireless/ath/ath12k/pci.c b/drivers/net/wireless/ath/ath12k/pci.c
index 9f174daf324c..5990a55801f0 100644
--- a/drivers/net/wireless/ath/ath12k/pci.c
+++ b/drivers/net/wireless/ath/ath12k/pci.c
@@ -1227,8 +1227,20 @@ static int ath12k_pci_probe(struct pci_dev *pdev,
case WCN7850_DEVICE_ID:
ab_pci->msi_config = &ath12k_msi_config[0];
ab->static_window_map = false;
- ab->hw_rev = ATH12K_HW_WCN7850_HW20;
ab_pci->pci_ops = &ath12k_pci_ops_wcn7850;
+ ath12k_pci_read_hw_version(ab, &soc_hw_version_major,
+ &soc_hw_version_minor);
+ switch (soc_hw_version_major) {
+ case ATH12K_PCI_SOC_HW_VERSION_2:
+ ab->hw_rev = ATH12K_HW_WCN7850_HW20;
+ break;
+ default:
+ dev_err(&pdev->dev,
+ "Unknown hardware version found for WCN7850: 0x%x\n",
+ soc_hw_version_major);
+ ret = -EOPNOTSUPP;
+ goto err_pci_free_region;
+ }
break;
default:
diff --git a/drivers/net/wireless/ath/ath12k/qmi.c b/drivers/net/wireless/ath/ath12k/qmi.c
index 0a7892b1a8f8..b510c2de1bd4 100644
--- a/drivers/net/wireless/ath/ath12k/qmi.c
+++ b/drivers/net/wireless/ath/ath12k/qmi.c
@@ -1942,8 +1942,10 @@ static int ath12k_qmi_host_cap_send(struct ath12k_base *ab)
req.cal_done_valid = 1;
req.cal_done = ab->qmi.cal_done;
- req.feature_list_valid = 1;
- req.feature_list = BIT(CNSS_QDSS_CFG_MISS_V01);
+ if (ab->hw_params->qmi_cnss_feature_bitmap) {
+ req.feature_list_valid = 1;
+ req.feature_list = ab->hw_params->qmi_cnss_feature_bitmap;
+ }
/* BRINGUP: here we are piggybacking a lot of stuff using
* internal_sleep_clock, should it be split?
diff --git a/drivers/net/wireless/ath/ath12k/qmi.h b/drivers/net/wireless/ath/ath12k/qmi.h
index ad87f19903db..df76149c49f5 100644
--- a/drivers/net/wireless/ath/ath12k/qmi.h
+++ b/drivers/net/wireless/ath/ath12k/qmi.h
@@ -189,6 +189,7 @@ struct wlfw_host_mlo_chip_info_s_v01 {
enum ath12k_qmi_cnss_feature {
CNSS_FEATURE_MIN_ENUM_VAL_V01 = INT_MIN,
CNSS_QDSS_CFG_MISS_V01 = 3,
+ CNSS_PCIE_PERST_NO_PULL_V01 = 4,
CNSS_MAX_FEATURE_V01 = 64,
CNSS_FEATURE_MAX_ENUM_VAL_V01 = INT_MAX,
};
diff --git a/drivers/net/wireless/ath/ath12k/wmi.c b/drivers/net/wireless/ath/ath12k/wmi.c
index 7ae0bb78b2b5..6512267ae4ca 100644
--- a/drivers/net/wireless/ath/ath12k/wmi.c
+++ b/drivers/net/wireless/ath/ath12k/wmi.c
@@ -3181,8 +3181,8 @@ ath12k_wmi_copy_resource_config(struct ath12k_wmi_resource_config_params *wmi_cf
wmi_cfg->sched_params = cpu_to_le32(tg_cfg->sched_params);
wmi_cfg->twt_ap_pdev_count = cpu_to_le32(tg_cfg->twt_ap_pdev_count);
wmi_cfg->twt_ap_sta_count = cpu_to_le32(tg_cfg->twt_ap_sta_count);
- wmi_cfg->host_service_flags =
- cpu_to_le32(1 << WMI_RSRC_CFG_HOST_SVC_FLAG_REG_CC_EXT_SUPPORT_BIT);
+ wmi_cfg->host_service_flags = cpu_to_le32(tg_cfg->is_reg_cc_ext_event_supported <<
+ WMI_RSRC_CFG_HOST_SVC_FLAG_REG_CC_EXT_SUPPORT_BIT);
}
static int ath12k_init_cmd_send(struct ath12k_wmi_pdev *wmi,
@@ -3390,6 +3390,10 @@ int ath12k_wmi_cmd_init(struct ath12k_base *ab)
struct ath12k_wmi_base *wmi_sc = &ab->wmi_ab;
struct ath12k_wmi_init_cmd_arg arg = {};
+ if (test_bit(WMI_TLV_SERVICE_REG_CC_EXT_EVENT_SUPPORT,
+ ab->wmi_ab.svc_map))
+ arg.res_cfg.is_reg_cc_ext_event_supported = true;
+
ab->hw_params->wmi_init(ab, &arg.res_cfg);
arg.num_mem_chunks = wmi_sc->num_mem_chunks;
@@ -4640,6 +4644,7 @@ static int wmi_process_mgmt_tx_comp(struct ath12k *ar, u32 desc_id,
struct sk_buff *msdu;
struct ieee80211_tx_info *info;
struct ath12k_skb_cb *skb_cb;
+ int num_mgmt;
spin_lock_bh(&ar->txmgmt_idr_lock);
msdu = idr_find(&ar->txmgmt_idr, desc_id);
@@ -4663,10 +4668,15 @@ static int wmi_process_mgmt_tx_comp(struct ath12k *ar, u32 desc_id,
ieee80211_tx_status_irqsafe(ar->hw, msdu);
+ num_mgmt = atomic_dec_if_positive(&ar->num_pending_mgmt_tx);
+
/* WARN when we received this event without doing any mgmt tx */
- if (atomic_dec_if_positive(&ar->num_pending_mgmt_tx) < 0)
+ if (num_mgmt < 0)
WARN_ON_ONCE(1);
+ if (!num_mgmt)
+ wake_up(&ar->txmgmt_empty_waitq);
+
return 0;
}
@@ -5979,47 +5989,72 @@ static void ath12k_vdev_install_key_compl_event(struct ath12k_base *ab,
rcu_read_unlock();
}
-static void ath12k_service_available_event(struct ath12k_base *ab, struct sk_buff *skb)
+static int ath12k_wmi_tlv_services_parser(struct ath12k_base *ab,
+ u16 tag, u16 len,
+ const void *ptr,
+ void *data)
{
- const void **tb;
const struct wmi_service_available_event *ev;
- int ret;
+ u32 *wmi_ext2_service_bitmap;
int i, j;
+ u16 expected_len;
- tb = ath12k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC);
- if (IS_ERR(tb)) {
- ret = PTR_ERR(tb);
- ath12k_warn(ab, "failed to parse tlv: %d\n", ret);
- return;
+ expected_len = WMI_SERVICE_SEGMENT_BM_SIZE32 * sizeof(u32);
+ if (len < expected_len) {
+ ath12k_warn(ab, "invalid length %d for the WMI services available tag 0x%x\n",
+ len, tag);
+ return -EINVAL;
}
- ev = tb[WMI_TAG_SERVICE_AVAILABLE_EVENT];
- if (!ev) {
- ath12k_warn(ab, "failed to fetch svc available ev");
- kfree(tb);
- return;
- }
+ switch (tag) {
+ case WMI_TAG_SERVICE_AVAILABLE_EVENT:
+ ev = (struct wmi_service_available_event *)ptr;
+ for (i = 0, j = WMI_MAX_SERVICE;
+ i < WMI_SERVICE_SEGMENT_BM_SIZE32 && j < WMI_MAX_EXT_SERVICE;
+ i++) {
+ do {
+ if (le32_to_cpu(ev->wmi_service_segment_bitmap[i]) &
+ BIT(j % WMI_AVAIL_SERVICE_BITS_IN_SIZE32))
+ set_bit(j, ab->wmi_ab.svc_map);
+ } while (++j % WMI_AVAIL_SERVICE_BITS_IN_SIZE32);
+ }
- /* TODO: Use wmi_service_segment_offset information to get the service
- * especially when more services are advertised in multiple service
- * available events.
- */
- for (i = 0, j = WMI_MAX_SERVICE;
- i < WMI_SERVICE_SEGMENT_BM_SIZE32 && j < WMI_MAX_EXT_SERVICE;
- i++) {
- do {
- if (le32_to_cpu(ev->wmi_service_segment_bitmap[i]) &
- BIT(j % WMI_AVAIL_SERVICE_BITS_IN_SIZE32))
- set_bit(j, ab->wmi_ab.svc_map);
- } while (++j % WMI_AVAIL_SERVICE_BITS_IN_SIZE32);
+ ath12k_dbg(ab, ATH12K_DBG_WMI,
+ "wmi_ext_service_bitmap 0x%x 0x%x 0x%x 0x%x",
+ ev->wmi_service_segment_bitmap[0],
+ ev->wmi_service_segment_bitmap[1],
+ ev->wmi_service_segment_bitmap[2],
+ ev->wmi_service_segment_bitmap[3]);
+ break;
+ case WMI_TAG_ARRAY_UINT32:
+ wmi_ext2_service_bitmap = (u32 *)ptr;
+ for (i = 0, j = WMI_MAX_EXT_SERVICE;
+ i < WMI_SERVICE_SEGMENT_BM_SIZE32 && j < WMI_MAX_EXT2_SERVICE;
+ i++) {
+ do {
+ if (wmi_ext2_service_bitmap[i] &
+ BIT(j % WMI_AVAIL_SERVICE_BITS_IN_SIZE32))
+ set_bit(j, ab->wmi_ab.svc_map);
+ } while (++j % WMI_AVAIL_SERVICE_BITS_IN_SIZE32);
+ }
+
+ ath12k_dbg(ab, ATH12K_DBG_WMI,
+ "wmi_ext2_service_bitmap 0x%04x 0x%04x 0x%04x 0x%04x",
+ wmi_ext2_service_bitmap[0], wmi_ext2_service_bitmap[1],
+ wmi_ext2_service_bitmap[2], wmi_ext2_service_bitmap[3]);
+ break;
}
+ return 0;
+}
- ath12k_dbg(ab, ATH12K_DBG_WMI,
- "wmi_ext_service_bitmap 0:0x%x, 1:0x%x, 2:0x%x, 3:0x%x",
- ev->wmi_service_segment_bitmap[0], ev->wmi_service_segment_bitmap[1],
- ev->wmi_service_segment_bitmap[2], ev->wmi_service_segment_bitmap[3]);
+static int ath12k_service_available_event(struct ath12k_base *ab, struct sk_buff *skb)
+{
+ int ret;
- kfree(tb);
+ ret = ath12k_wmi_tlv_iter(ab, skb->data, skb->len,
+ ath12k_wmi_tlv_services_parser,
+ NULL);
+ return ret;
}
static void ath12k_peer_assoc_conf_event(struct ath12k_base *ab, struct sk_buff *skb)
diff --git a/drivers/net/wireless/ath/ath12k/wmi.h b/drivers/net/wireless/ath/ath12k/wmi.h
index 08a8c9e0f59f..d89c12bfb009 100644
--- a/drivers/net/wireless/ath/ath12k/wmi.h
+++ b/drivers/net/wireless/ath/ath12k/wmi.h
@@ -2148,7 +2148,10 @@ enum wmi_tlv_service {
WMI_TLV_SERVICE_FREQINFO_IN_METADATA = 219,
WMI_TLV_SERVICE_EXT2_MSG = 220,
- WMI_MAX_EXT_SERVICE
+ WMI_MAX_EXT_SERVICE = 256,
+
+ WMI_TLV_SERVICE_REG_CC_EXT_EVENT_SUPPORT = 281,
+ WMI_MAX_EXT2_SERVICE,
};
enum {
@@ -2333,6 +2336,7 @@ struct ath12k_wmi_resource_config_arg {
u32 sched_params;
u32 twt_ap_pdev_count;
u32 twt_ap_sta_count;
+ bool is_reg_cc_ext_event_supported;
};
struct ath12k_wmi_init_cmd_arg {
@@ -2682,7 +2686,7 @@ struct ath12k_wmi_ssid_params {
u8 ssid[ATH12K_WMI_SSID_LEN];
} __packed;
-#define ATH12K_VDEV_SETUP_TIMEOUT_HZ (1 * HZ)
+#define ATH12K_VDEV_SETUP_TIMEOUT_HZ (5 * HZ)
struct wmi_vdev_start_request_cmd {
__le32 tlv_header;
@@ -4664,7 +4668,7 @@ struct ath12k_wmi_base {
struct completion service_ready;
struct completion unified_ready;
- DECLARE_BITMAP(svc_map, WMI_MAX_EXT_SERVICE);
+ DECLARE_BITMAP(svc_map, WMI_MAX_EXT2_SERVICE);
wait_queue_head_t tx_credits_wq;
const struct wmi_peer_flags_map *peer_flags;
u32 num_mem_chunks;
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
index 4f27a9fb1482..e9bd13eeee92 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
@@ -1099,17 +1099,22 @@ static bool ath9k_hw_verify_hang(struct ath_hw *ah, unsigned int queue)
{
u32 dma_dbg_chain, dma_dbg_complete;
u8 dcu_chain_state, dcu_complete_state;
+ unsigned int dbg_reg, reg_offset;
int i;
- for (i = 0; i < NUM_STATUS_READS; i++) {
- if (queue < 6)
- dma_dbg_chain = REG_READ(ah, AR_DMADBG_4);
- else
- dma_dbg_chain = REG_READ(ah, AR_DMADBG_5);
+ if (queue < 6) {
+ dbg_reg = AR_DMADBG_4;
+ reg_offset = queue * 5;
+ } else {
+ dbg_reg = AR_DMADBG_5;
+ reg_offset = (queue - 6) * 5;
+ }
+ for (i = 0; i < NUM_STATUS_READS; i++) {
+ dma_dbg_chain = REG_READ(ah, dbg_reg);
dma_dbg_complete = REG_READ(ah, AR_DMADBG_6);
- dcu_chain_state = (dma_dbg_chain >> (5 * queue)) & 0x1f;
+ dcu_chain_state = (dma_dbg_chain >> reg_offset) & 0x1f;
dcu_complete_state = dma_dbg_complete & 0x3;
if ((dcu_chain_state != 0x6) || (dcu_complete_state != 0x1))
@@ -1128,6 +1133,7 @@ static bool ar9003_hw_detect_mac_hang(struct ath_hw *ah)
u8 dcu_chain_state, dcu_complete_state;
bool dcu_wait_frdone = false;
unsigned long chk_dcu = 0;
+ unsigned int reg_offset;
unsigned int i = 0;
dma_dbg_4 = REG_READ(ah, AR_DMADBG_4);
@@ -1139,12 +1145,15 @@ static bool ar9003_hw_detect_mac_hang(struct ath_hw *ah)
goto exit;
for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
- if (i < 6)
+ if (i < 6) {
chk_dbg = dma_dbg_4;
- else
+ reg_offset = i * 5;
+ } else {
chk_dbg = dma_dbg_5;
+ reg_offset = (i - 6) * 5;
+ }
- dcu_chain_state = (chk_dbg >> (5 * i)) & 0x1f;
+ dcu_chain_state = (chk_dbg >> reg_offset) & 0x1f;
if (dcu_chain_state == 0x6) {
dcu_wait_frdone = true;
chk_dcu |= BIT(i);
diff --git a/drivers/net/wireless/ath/ath9k/htc_hst.c b/drivers/net/wireless/ath/ath9k/htc_hst.c
index fe62ff668f75..99667aba289d 100644
--- a/drivers/net/wireless/ath/ath9k/htc_hst.c
+++ b/drivers/net/wireless/ath/ath9k/htc_hst.c
@@ -114,7 +114,13 @@ static void htc_process_conn_rsp(struct htc_target *target,
if (svc_rspmsg->status == HTC_SERVICE_SUCCESS) {
epid = svc_rspmsg->endpoint_id;
- if (epid < 0 || epid >= ENDPOINT_MAX)
+
+ /* Check that the received epid for the endpoint to attach
+ * a new service is valid. ENDPOINT0 can't be used here as it
+ * is already reserved for HTC_CTRL_RSVD_SVC service and thus
+ * should not be modified.
+ */
+ if (epid <= ENDPOINT0 || epid >= ENDPOINT_MAX)
return;
service_id = be16_to_cpu(svc_rspmsg->service_id);
diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c
index a4197c14f0a9..6360d3356e25 100644
--- a/drivers/net/wireless/ath/ath9k/main.c
+++ b/drivers/net/wireless/ath/ath9k/main.c
@@ -203,7 +203,7 @@ void ath_cancel_work(struct ath_softc *sc)
void ath_restart_work(struct ath_softc *sc)
{
ieee80211_queue_delayed_work(sc->hw, &sc->hw_check_work,
- ATH_HW_CHECK_POLL_INT);
+ msecs_to_jiffies(ATH_HW_CHECK_POLL_INT));
if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah))
ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
@@ -850,7 +850,7 @@ static bool ath9k_txq_list_has_key(struct list_head *txq_list, u32 keyix)
static bool ath9k_txq_has_key(struct ath_softc *sc, u32 keyix)
{
struct ath_hw *ah = sc->sc_ah;
- int i;
+ int i, j;
struct ath_txq *txq;
bool key_in_use = false;
@@ -868,8 +868,9 @@ static bool ath9k_txq_has_key(struct ath_softc *sc, u32 keyix)
if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
int idx = txq->txq_tailidx;
- while (!key_in_use &&
- !list_empty(&txq->txq_fifo[idx])) {
+ for (j = 0; !key_in_use &&
+ !list_empty(&txq->txq_fifo[idx]) &&
+ j < ATH_TXFIFO_DEPTH; j++) {
key_in_use = ath9k_txq_list_has_key(
&txq->txq_fifo[idx], keyix);
INCR(idx, ATH_TXFIFO_DEPTH);
@@ -2239,7 +2240,7 @@ void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop,
}
ieee80211_queue_delayed_work(hw, &sc->hw_check_work,
- ATH_HW_CHECK_POLL_INT);
+ msecs_to_jiffies(ATH_HW_CHECK_POLL_INT));
}
static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
diff --git a/drivers/net/wireless/ath/ath9k/wmi.c b/drivers/net/wireless/ath/ath9k/wmi.c
index 19345b8f7bfd..d652c647d56b 100644
--- a/drivers/net/wireless/ath/ath9k/wmi.c
+++ b/drivers/net/wireless/ath/ath9k/wmi.c
@@ -221,6 +221,10 @@ static void ath9k_wmi_ctrl_rx(void *priv, struct sk_buff *skb,
if (unlikely(wmi->stopped))
goto free_skb;
+ /* Validate the obtained SKB. */
+ if (unlikely(skb->len < sizeof(struct wmi_cmd_hdr)))
+ goto free_skb;
+
hdr = (struct wmi_cmd_hdr *) skb->data;
cmd_id = be16_to_cpu(hdr->command_id);
diff --git a/drivers/net/wireless/ath/wil6210/fw.h b/drivers/net/wireless/ath/wil6210/fw.h
index 440614d61156..aa1620e0d24f 100644
--- a/drivers/net/wireless/ath/wil6210/fw.h
+++ b/drivers/net/wireless/ath/wil6210/fw.h
@@ -47,7 +47,7 @@ struct wil_fw_record_fill { /* type == wil_fw_type_fill */
* for informational purpose, data_size is @head.size from record header
*/
struct wil_fw_record_comment { /* type == wil_fw_type_comment */
- u8 data[0]; /* free-form data [data_size], see above */
+ DECLARE_FLEX_ARRAY(u8, data); /* free-form data [data_size], see above */
} __packed;
/* Comment header - common for all comment record types */
@@ -131,7 +131,7 @@ struct wil_fw_data_dwrite {
* data_size is @head.size where @head is record header
*/
struct wil_fw_record_direct_write { /* type == wil_fw_type_direct_write */
- struct wil_fw_data_dwrite data[0];
+ DECLARE_FLEX_ARRAY(struct wil_fw_data_dwrite, data);
} __packed;
/* verify condition: [@addr] & @mask == @value
diff --git a/drivers/net/wireless/ath/wil6210/wmi.h b/drivers/net/wireless/ath/wil6210/wmi.h
index 9affa4525609..71bf2ae27a98 100644
--- a/drivers/net/wireless/ath/wil6210/wmi.h
+++ b/drivers/net/wireless/ath/wil6210/wmi.h
@@ -2763,7 +2763,7 @@ struct wmi_rf_xpm_write_result_event {
/* WMI_TX_MGMT_PACKET_EVENTID */
struct wmi_tx_mgmt_packet_event {
- u8 payload[0];
+ DECLARE_FLEX_ARRAY(u8, payload);
} __packed;
/* WMI_RX_MGMT_PACKET_EVENTID */
diff --git a/drivers/net/wireless/atmel/Kconfig b/drivers/net/wireless/atmel/Kconfig
index ca45a1021cf4..bafdd57b049a 100644
--- a/drivers/net/wireless/atmel/Kconfig
+++ b/drivers/net/wireless/atmel/Kconfig
@@ -14,7 +14,7 @@ if WLAN_VENDOR_ATMEL
config ATMEL
tristate "Atmel at76c50x chipset 802.11b support"
- depends on CFG80211 && (PCI || PCMCIA)
+ depends on CFG80211 && (PCI || PCMCIA) && HAS_IOPORT
select WIRELESS_EXT
select WEXT_PRIV
select FW_LOADER
diff --git a/drivers/net/wireless/atmel/atmel_cs.c b/drivers/net/wireless/atmel/atmel_cs.c
index 453bb84cb338..58bba9875d36 100644
--- a/drivers/net/wireless/atmel/atmel_cs.c
+++ b/drivers/net/wireless/atmel/atmel_cs.c
@@ -72,6 +72,7 @@ struct local_info {
static int atmel_probe(struct pcmcia_device *p_dev)
{
struct local_info *local;
+ int ret;
dev_dbg(&p_dev->dev, "atmel_attach()\n");
@@ -82,8 +83,16 @@ static int atmel_probe(struct pcmcia_device *p_dev)
p_dev->priv = local;
- return atmel_config(p_dev);
-} /* atmel_attach */
+ ret = atmel_config(p_dev);
+ if (ret)
+ goto err_free_priv;
+
+ return 0;
+
+err_free_priv:
+ kfree(p_dev->priv);
+ return ret;
+}
static void atmel_detach(struct pcmcia_device *link)
{
diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c
index 9f9bf08a70bb..2ef92ef25517 100644
--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c
+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c
@@ -972,6 +972,7 @@ static int brcmf_chip_recognition(struct brcmf_chip_priv *ci)
u32 regdata;
u32 socitype;
int ret;
+ const u32 READ_FAILED = 0xFFFFFFFF;
/* Get CC core rev
* Chipid is assume to be at offset 0 from SI_ENUM_BASE
@@ -980,6 +981,11 @@ static int brcmf_chip_recognition(struct brcmf_chip_priv *ci)
*/
regdata = ci->ops->read32(ci->ctx,
CORE_CC_REG(ci->pub.enum_base, chipid));
+ if (regdata == READ_FAILED) {
+ brcmf_err("MMIO read failed: 0x%08x\n", regdata);
+ return -ENODEV;
+ }
+
ci->pub.chip = regdata & CID_ID_MASK;
ci->pub.chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
socitype = (regdata & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/tracepoint.h b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/tracepoint.h
index 5a139d7ed47a..5d66e94c806d 100644
--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/tracepoint.h
+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/tracepoint.h
@@ -28,6 +28,11 @@ static inline void trace_ ## name(proto) {}
#define MAX_MSG_LEN 100
+#pragma GCC diagnostic push
+#ifndef __clang__
+#pragma GCC diagnostic ignored "-Wsuggest-attribute=format"
+#endif
+
TRACE_EVENT(brcmf_err,
TP_PROTO(const char *func, struct va_format *vaf),
TP_ARGS(func, vaf),
@@ -123,6 +128,8 @@ TRACE_EVENT(brcmf_sdpcm_hdr,
__entry->len, ((u8 *)__get_dynamic_array(hdr))[4])
);
+#pragma GCC diagnostic pop
+
#ifdef CONFIG_BRCM_TRACING
#undef TRACE_INCLUDE_PATH
diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/wcc/core.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/wcc/core.c
index 02de99818efa..5573a47766ad 100644
--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/wcc/core.c
+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/wcc/core.c
@@ -12,13 +12,13 @@
static int brcmf_wcc_attach(struct brcmf_pub *drvr)
{
- pr_err("%s: executing\n", __func__);
+ pr_debug("%s: executing\n", __func__);
return 0;
}
static void brcmf_wcc_detach(struct brcmf_pub *drvr)
{
- pr_err("%s: executing\n", __func__);
+ pr_debug("%s: executing\n", __func__);
}
const struct brcmf_fwvid_ops brcmf_wcc_ops = {
diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmsmac/brcms_trace_brcmsmac_msg.h b/drivers/net/wireless/broadcom/brcm80211/brcmsmac/brcms_trace_brcmsmac_msg.h
index 488456420353..42b0a91656c4 100644
--- a/drivers/net/wireless/broadcom/brcm80211/brcmsmac/brcms_trace_brcmsmac_msg.h
+++ b/drivers/net/wireless/broadcom/brcm80211/brcmsmac/brcms_trace_brcmsmac_msg.h
@@ -24,6 +24,11 @@
#define MAX_MSG_LEN 100
+#pragma GCC diagnostic push
+#ifndef __clang__
+#pragma GCC diagnostic ignored "-Wsuggest-attribute=format"
+#endif
+
DECLARE_EVENT_CLASS(brcms_msg_event,
TP_PROTO(struct va_format *vaf),
TP_ARGS(vaf),
@@ -71,6 +76,9 @@ TRACE_EVENT(brcms_dbg,
),
TP_printk("%s: %s", __get_str(func), __get_str(msg))
);
+
+#pragma GCC diagnostic pop
+
#endif /* __TRACE_BRCMSMAC_MSG_H */
#ifdef CONFIG_BRCM_TRACING
diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmutil/utils.c b/drivers/net/wireless/broadcom/brcm80211/brcmutil/utils.c
index e87e68cc46e2..fe94db0ba3f3 100644
--- a/drivers/net/wireless/broadcom/brcm80211/brcmutil/utils.c
+++ b/drivers/net/wireless/broadcom/brcm80211/brcmutil/utils.c
@@ -186,7 +186,7 @@ struct sk_buff *brcmu_pktq_peek_tail(struct pktq *pq, int *prec_out)
{
int prec;
- if (pq->len == 0)
+ if (pktq_empty(pq))
return NULL;
for (prec = 0; prec < pq->hi_prec; prec++)
@@ -223,7 +223,7 @@ struct sk_buff *brcmu_pktq_mdeq(struct pktq *pq, uint prec_bmp,
struct sk_buff *p;
int prec;
- if (pq->len == 0)
+ if (pktq_empty(pq))
return NULL;
while ((prec = pq->hi_prec) > 0 &&
diff --git a/drivers/net/wireless/intel/iwlwifi/Makefile b/drivers/net/wireless/intel/iwlwifi/Makefile
index 75a703eb1bdf..b983982aee45 100644
--- a/drivers/net/wireless/intel/iwlwifi/Makefile
+++ b/drivers/net/wireless/intel/iwlwifi/Makefile
@@ -11,6 +11,7 @@ iwlwifi-objs += pcie/ctxt-info.o pcie/ctxt-info-gen3.o
iwlwifi-objs += pcie/trans-gen2.o pcie/tx-gen2.o
iwlwifi-$(CONFIG_IWLDVM) += cfg/1000.o cfg/2000.o cfg/5000.o cfg/6000.o
iwlwifi-$(CONFIG_IWLMVM) += cfg/7000.o cfg/8000.o cfg/9000.o cfg/22000.o
+iwlwifi-$(CONFIG_IWLMVM) += cfg/ax210.o cfg/bz.o cfg/sc.o
iwlwifi-objs += iwl-dbg-tlv.o
iwlwifi-objs += iwl-trans.o
iwlwifi-objs += queue/tx.o
diff --git a/drivers/net/wireless/intel/iwlwifi/cfg/1000.c b/drivers/net/wireless/intel/iwlwifi/cfg/1000.c
index 116defb15afb..f172ffd2a841 100644
--- a/drivers/net/wireless/intel/iwlwifi/cfg/1000.c
+++ b/drivers/net/wireless/intel/iwlwifi/cfg/1000.c
@@ -2,7 +2,7 @@
/******************************************************************************
*
* Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
- * Copyright(c) 2018 - 2020 Intel Corporation
+ * Copyright(c) 2018 - 2020, 2023 Intel Corporation
*****************************************************************************/
#include <linux/module.h>
@@ -22,11 +22,11 @@
#define EEPROM_1000_TX_POWER_VERSION (4)
#define EEPROM_1000_EEPROM_VERSION (0x15C)
-#define IWL1000_FW_PRE "iwlwifi-1000-"
-#define IWL1000_MODULE_FIRMWARE(api) IWL1000_FW_PRE __stringify(api) ".ucode"
+#define IWL1000_FW_PRE "iwlwifi-1000"
+#define IWL1000_MODULE_FIRMWARE(api) IWL1000_FW_PRE "-" __stringify(api) ".ucode"
-#define IWL100_FW_PRE "iwlwifi-100-"
-#define IWL100_MODULE_FIRMWARE(api) IWL100_FW_PRE __stringify(api) ".ucode"
+#define IWL100_FW_PRE "iwlwifi-100"
+#define IWL100_MODULE_FIRMWARE(api) IWL100_FW_PRE "-" __stringify(api) ".ucode"
static const struct iwl_base_params iwl1000_base_params = {
diff --git a/drivers/net/wireless/intel/iwlwifi/cfg/2000.c b/drivers/net/wireless/intel/iwlwifi/cfg/2000.c
index ab2038a3fbe2..6f3f26da0ad5 100644
--- a/drivers/net/wireless/intel/iwlwifi/cfg/2000.c
+++ b/drivers/net/wireless/intel/iwlwifi/cfg/2000.c
@@ -2,7 +2,7 @@
/******************************************************************************
*
* Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
- * Copyright(c) 2018 - 2020 Intel Corporation
+ * Copyright(c) 2018 - 2020, 2023 Intel Corporation
*****************************************************************************/
#include <linux/module.h>
@@ -28,17 +28,17 @@
#define EEPROM_2000_EEPROM_VERSION (0x805)
-#define IWL2030_FW_PRE "iwlwifi-2030-"
-#define IWL2030_MODULE_FIRMWARE(api) IWL2030_FW_PRE __stringify(api) ".ucode"
+#define IWL2030_FW_PRE "iwlwifi-2030"
+#define IWL2030_MODULE_FIRMWARE(api) IWL2030_FW_PRE "-" __stringify(api) ".ucode"
-#define IWL2000_FW_PRE "iwlwifi-2000-"
-#define IWL2000_MODULE_FIRMWARE(api) IWL2000_FW_PRE __stringify(api) ".ucode"
+#define IWL2000_FW_PRE "iwlwifi-2000"
+#define IWL2000_MODULE_FIRMWARE(api) IWL2000_FW_PRE "-" __stringify(api) ".ucode"
-#define IWL105_FW_PRE "iwlwifi-105-"
-#define IWL105_MODULE_FIRMWARE(api) IWL105_FW_PRE __stringify(api) ".ucode"
+#define IWL105_FW_PRE "iwlwifi-105"
+#define IWL105_MODULE_FIRMWARE(api) IWL105_FW_PRE "-" __stringify(api) ".ucode"
-#define IWL135_FW_PRE "iwlwifi-135-"
-#define IWL135_MODULE_FIRMWARE(api) IWL135_FW_PRE __stringify(api) ".ucode"
+#define IWL135_FW_PRE "iwlwifi-135"
+#define IWL135_MODULE_FIRMWARE(api) IWL135_FW_PRE "-" __stringify(api) ".ucode"
static const struct iwl_base_params iwl2000_base_params = {
.eeprom_size = OTP_LOW_IMAGE_SIZE_2K,
diff --git a/drivers/net/wireless/intel/iwlwifi/cfg/22000.c b/drivers/net/wireless/intel/iwlwifi/cfg/22000.c
index b6f82510e980..aa4320ca4c30 100644
--- a/drivers/net/wireless/intel/iwlwifi/cfg/22000.c
+++ b/drivers/net/wireless/intel/iwlwifi/cfg/22000.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
* Copyright (C) 2015-2017 Intel Deutschland GmbH
- * Copyright (C) 2018-2022 Intel Corporation
+ * Copyright (C) 2018-2023 Intel Corporation
*/
#include <linux/module.h>
#include <linux/stringify.h>
@@ -10,10 +10,10 @@
#include "fw/api/txq.h"
/* Highest firmware API version supported */
-#define IWL_22000_UCODE_API_MAX 78
+#define IWL_22000_UCODE_API_MAX 77
/* Lowest firmware API version supported */
-#define IWL_22000_UCODE_API_MIN 39
+#define IWL_22000_UCODE_API_MIN 50
/* NVM versions */
#define IWL_22000_NVM_VERSION 0x0a1d
@@ -26,162 +26,26 @@
#define IWL_22000_SMEM_OFFSET 0x400000
#define IWL_22000_SMEM_LEN 0xD0000
-#define IWL_QU_B_HR_B_FW_PRE "iwlwifi-Qu-b0-hr-b0-"
-#define IWL_QNJ_B_HR_B_FW_PRE "iwlwifi-QuQnj-b0-hr-b0-"
-#define IWL_QU_C_HR_B_FW_PRE "iwlwifi-Qu-c0-hr-b0-"
-#define IWL_QU_B_JF_B_FW_PRE "iwlwifi-Qu-b0-jf-b0-"
-#define IWL_QU_C_JF_B_FW_PRE "iwlwifi-Qu-c0-jf-b0-"
-#define IWL_QUZ_A_HR_B_FW_PRE "iwlwifi-QuZ-a0-hr-b0-"
-#define IWL_QUZ_A_JF_B_FW_PRE "iwlwifi-QuZ-a0-jf-b0-"
-#define IWL_QNJ_B_JF_B_FW_PRE "iwlwifi-QuQnj-b0-jf-b0-"
-#define IWL_CC_A_FW_PRE "iwlwifi-cc-a0-"
-#define IWL_SO_A_JF_B_FW_PRE "iwlwifi-so-a0-jf-b0-"
-#define IWL_SO_A_HR_B_FW_PRE "iwlwifi-so-a0-hr-b0-"
-#define IWL_SO_A_GF_A_FW_PRE "iwlwifi-so-a0-gf-a0-"
-#define IWL_TY_A_GF_A_FW_PRE "iwlwifi-ty-a0-gf-a0-"
-#define IWL_SO_A_GF4_A_FW_PRE "iwlwifi-so-a0-gf4-a0-"
-#define IWL_SO_A_MR_A_FW_PRE "iwlwifi-so-a0-mr-a0-"
-#define IWL_SNJ_A_GF4_A_FW_PRE "iwlwifi-SoSnj-a0-gf4-a0-"
-#define IWL_SNJ_A_GF_A_FW_PRE "iwlwifi-SoSnj-a0-gf-a0-"
-#define IWL_SNJ_A_HR_B_FW_PRE "iwlwifi-SoSnj-a0-hr-b0-"
-#define IWL_SNJ_A_JF_B_FW_PRE "iwlwifi-SoSnj-a0-jf-b0-"
-#define IWL_MA_A_HR_B_FW_PRE "iwlwifi-ma-a0-hr-b0-"
-#define IWL_MA_A_GF_A_FW_PRE "iwlwifi-ma-a0-gf-a0-"
-#define IWL_MA_A_GF4_A_FW_PRE "iwlwifi-ma-a0-gf4-a0-"
-#define IWL_MA_A_MR_A_FW_PRE "iwlwifi-ma-a0-mr-a0-"
-#define IWL_MA_A_FM_A_FW_PRE "iwlwifi-ma-a0-fm-a0-"
-#define IWL_MA_B_HR_B_FW_PRE "iwlwifi-ma-b0-hr-b0-"
-#define IWL_MA_B_GF_A_FW_PRE "iwlwifi-ma-b0-gf-a0-"
-#define IWL_MA_B_GF4_A_FW_PRE "iwlwifi-ma-b0-gf4-a0-"
-#define IWL_MA_B_MR_A_FW_PRE "iwlwifi-ma-b0-mr-a0-"
-#define IWL_MA_B_FM_A_FW_PRE "iwlwifi-ma-b0-fm-a0-"
-#define IWL_SNJ_A_MR_A_FW_PRE "iwlwifi-SoSnj-a0-mr-a0-"
-#define IWL_BZ_A_HR_A_FW_PRE "iwlwifi-bz-a0-hr-b0-"
-#define IWL_BZ_A_HR_B_FW_PRE "iwlwifi-bz-a0-hr-b0-"
-#define IWL_BZ_A_GF_A_FW_PRE "iwlwifi-bz-a0-gf-a0-"
-#define IWL_BZ_A_GF4_A_FW_PRE "iwlwifi-bz-a0-gf4-a0-"
-#define IWL_BZ_A_MR_A_FW_PRE "iwlwifi-bz-a0-mr-a0-"
-#define IWL_BZ_A_FM_A_FW_PRE "iwlwifi-bz-a0-fm-a0-"
-#define IWL_BZ_A_FM4_A_FW_PRE "iwlwifi-bz-a0-fm4-a0-"
-#define IWL_BZ_A_FM_B_FW_PRE "iwlwifi-bz-a0-fm-b0-"
-#define IWL_BZ_A_FM4_B_FW_PRE "iwlwifi-bz-a0-fm4-b0-"
-#define IWL_GL_A_FM_A_FW_PRE "iwlwifi-gl-a0-fm-a0-"
-#define IWL_GL_B_FM_B_FW_PRE "iwlwifi-gl-b0-fm-b0-"
-#define IWL_BZ_Z_GF_A_FW_PRE "iwlwifi-bz-z0-gf-a0-"
-#define IWL_BNJ_A_FM_A_FW_PRE "iwlwifi-BzBnj-a0-fm-a0-"
-#define IWL_BNJ_A_FM4_A_FW_PRE "iwlwifi-BzBnj-a0-fm4-a0-"
-#define IWL_BNJ_B_FM4_B_FW_PRE "iwlwifi-BzBnj-b0-fm4-b0-"
-#define IWL_BNJ_A_GF_A_FW_PRE "iwlwifi-BzBnj-a0-gf-a0-"
-#define IWL_BNJ_B_GF_A_FW_PRE "iwlwifi-BzBnj-b0-gf-a0-"
-#define IWL_BNJ_A_GF4_A_FW_PRE "iwlwifi-BzBnj-a0-gf4-a0-"
-#define IWL_BNJ_B_GF4_A_FW_PRE "iwlwifi-BzBnj-b0-gf4-a0-"
-#define IWL_BNJ_A_HR_A_FW_PRE "iwlwifi-BzBnj-a0-hr-b0-"
-#define IWL_BNJ_A_HR_B_FW_PRE "iwlwifi-BzBnj-a0-hr-b0-"
-#define IWL_BNJ_B_HR_A_FW_PRE "iwlwifi-BzBnj-b0-hr-b0-"
-#define IWL_BNJ_B_HR_B_FW_PRE "iwlwifi-BzBnj-b0-hr-b0-"
-#define IWL_BNJ_B_FM_B_FW_PRE "iwlwifi-BzBnj-b0-fm-b0-"
-
+#define IWL_QU_B_HR_B_FW_PRE "iwlwifi-Qu-b0-hr-b0"
+#define IWL_QU_C_HR_B_FW_PRE "iwlwifi-Qu-c0-hr-b0"
+#define IWL_QU_B_JF_B_FW_PRE "iwlwifi-Qu-b0-jf-b0"
+#define IWL_QU_C_JF_B_FW_PRE "iwlwifi-Qu-c0-jf-b0"
+#define IWL_QUZ_A_HR_B_FW_PRE "iwlwifi-QuZ-a0-hr-b0"
+#define IWL_QUZ_A_JF_B_FW_PRE "iwlwifi-QuZ-a0-jf-b0"
+#define IWL_CC_A_FW_PRE "iwlwifi-cc-a0"
#define IWL_QU_B_HR_B_MODULE_FIRMWARE(api) \
- IWL_QU_B_HR_B_FW_PRE __stringify(api) ".ucode"
-#define IWL_QNJ_B_HR_B_MODULE_FIRMWARE(api) \
- IWL_QNJ_B_HR_B_FW_PRE __stringify(api) ".ucode"
+ IWL_QU_B_HR_B_FW_PRE "-" __stringify(api) ".ucode"
#define IWL_QUZ_A_HR_B_MODULE_FIRMWARE(api) \
- IWL_QUZ_A_HR_B_FW_PRE __stringify(api) ".ucode"
+ IWL_QUZ_A_HR_B_FW_PRE "-" __stringify(api) ".ucode"
#define IWL_QUZ_A_JF_B_MODULE_FIRMWARE(api) \
- IWL_QUZ_A_JF_B_FW_PRE __stringify(api) ".ucode"
+ IWL_QUZ_A_JF_B_FW_PRE "-" __stringify(api) ".ucode"
#define IWL_QU_C_HR_B_MODULE_FIRMWARE(api) \
- IWL_QU_C_HR_B_FW_PRE __stringify(api) ".ucode"
+ IWL_QU_C_HR_B_FW_PRE "-" __stringify(api) ".ucode"
#define IWL_QU_B_JF_B_MODULE_FIRMWARE(api) \
- IWL_QU_B_JF_B_FW_PRE __stringify(api) ".ucode"
-#define IWL_QNJ_B_JF_B_MODULE_FIRMWARE(api) \
- IWL_QNJ_B_JF_B_FW_PRE __stringify(api) ".ucode"
+ IWL_QU_B_JF_B_FW_PRE "-" __stringify(api) ".ucode"
#define IWL_CC_A_MODULE_FIRMWARE(api) \
- IWL_CC_A_FW_PRE __stringify(api) ".ucode"
-#define IWL_SO_A_JF_B_MODULE_FIRMWARE(api) \
- IWL_SO_A_JF_B_FW_PRE __stringify(api) ".ucode"
-#define IWL_SO_A_HR_B_MODULE_FIRMWARE(api) \
- IWL_SO_A_HR_B_FW_PRE __stringify(api) ".ucode"
-#define IWL_SO_A_GF_A_MODULE_FIRMWARE(api) \
- IWL_SO_A_GF_A_FW_PRE __stringify(api) ".ucode"
-#define IWL_TY_A_GF_A_MODULE_FIRMWARE(api) \
- IWL_TY_A_GF_A_FW_PRE __stringify(api) ".ucode"
-#define IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(api) \
- IWL_SNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode"
-#define IWL_SNJ_A_GF_A_MODULE_FIRMWARE(api) \
- IWL_SNJ_A_GF_A_FW_PRE __stringify(api) ".ucode"
-#define IWL_SNJ_A_HR_B_MODULE_FIRMWARE(api) \
- IWL_SNJ_A_HR_B_FW_PRE __stringify(api) ".ucode"
-#define IWL_SNJ_A_JF_B_MODULE_FIRMWARE(api) \
- IWL_SNJ_A_JF_B_FW_PRE __stringify(api) ".ucode"
-#define IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(api) \
- IWL_MA_A_HR_B_FW_PRE __stringify(api) ".ucode"
-#define IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(api) \
- IWL_MA_A_GF_A_FW_PRE __stringify(api) ".ucode"
-#define IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(api) \
- IWL_MA_A_GF4_A_FW_PRE __stringify(api) ".ucode"
-#define IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(api) \
- IWL_MA_A_MR_A_FW_PRE __stringify(api) ".ucode"
-#define IWL_MA_A_FM_A_FW_MODULE_FIRMWARE(api) \
- IWL_MA_A_FM_A_FW_PRE __stringify(api) ".ucode"
-#define IWL_MA_B_HR_B_FW_MODULE_FIRMWARE(api) \
- IWL_MA_B_HR_B_FW_PRE __stringify(api) ".ucode"
-#define IWL_MA_B_GF_A_FW_MODULE_FIRMWARE(api) \
- IWL_MA_B_GF_A_FW_PRE __stringify(api) ".ucode"
-#define IWL_MA_B_GF4_A_FW_MODULE_FIRMWARE(api) \
- IWL_MA_B_GF4_A_FW_PRE __stringify(api) ".ucode"
-#define IWL_MA_B_MR_A_FW_MODULE_FIRMWARE(api) \
- IWL_MA_B_MR_A_FW_PRE __stringify(api) ".ucode"
-#define IWL_MA_B_FM_A_FW_MODULE_FIRMWARE(api) \
- IWL_MA_B_FM_A_FW_PRE __stringify(api) ".ucode"
-#define IWL_SNJ_A_MR_A_MODULE_FIRMWARE(api) \
- IWL_SNJ_A_MR_A_FW_PRE __stringify(api) ".ucode"
-#define IWL_BZ_A_HR_A_MODULE_FIRMWARE(api) \
- IWL_BZ_A_HR_A_FW_PRE __stringify(api) ".ucode"
-#define IWL_BZ_A_HR_B_MODULE_FIRMWARE(api) \
- IWL_BZ_A_HR_B_FW_PRE __stringify(api) ".ucode"
-#define IWL_BZ_A_GF_A_MODULE_FIRMWARE(api) \
- IWL_BZ_A_GF_A_FW_PRE __stringify(api) ".ucode"
-#define IWL_BZ_A_GF4_A_MODULE_FIRMWARE(api) \
- IWL_BZ_A_GF4_A_FW_PRE __stringify(api) ".ucode"
-#define IWL_BZ_A_MR_A_MODULE_FIRMWARE(api) \
- IWL_BZ_A_MR_A_FW_PRE __stringify(api) ".ucode"
-#define IWL_BZ_A_FM_A_MODULE_FIRMWARE(api) \
- IWL_BZ_A_FM_A_FW_PRE __stringify(api) ".ucode"
-#define IWL_BZ_A_FM4_A_MODULE_FIRMWARE(api) \
- IWL_BZ_A_FM4_A_FW_PRE __stringify(api) ".ucode"
-#define IWL_BZ_A_FM_B_MODULE_FIRMWARE(api) \
- IWL_BZ_A_FM_B_FW_PRE __stringify(api) ".ucode"
-#define IWL_BZ_A_FM4_B_MODULE_FIRMWARE(api) \
- IWL_BZ_A_FM4_B_FW_PRE __stringify(api) ".ucode"
-#define IWL_GL_A_FM_A_MODULE_FIRMWARE(api) \
- IWL_GL_A_FM_A_FW_PRE __stringify(api) ".ucode"
-#define IWL_GL_B_FM_B_MODULE_FIRMWARE(api) \
- IWL_GL_B_FM_B_FW_PRE __stringify(api) ".ucode"
-#define IWL_BNJ_A_FM_A_MODULE_FIRMWARE(api) \
- IWL_BNJ_A_FM_A_FW_PRE __stringify(api) ".ucode"
-#define IWL_BNJ_A_FM4_A_MODULE_FIRMWARE(api) \
- IWL_BNJ_A_FM4_A_FW_PRE __stringify(api) ".ucode"
-#define IWL_BNJ_B_FM4_B_MODULE_FIRMWARE(api) \
- IWL_BNJ_B_FM4_B_FW_PRE __stringify(api) ".ucode"
-#define IWL_BNJ_A_GF_A_MODULE_FIRMWARE(api) \
- IWL_BNJ_A_GF_A_FW_PRE __stringify(api) ".ucode"
-#define IWL_BNJ_B_GF_A_MODULE_FIRMWARE(api) \
- IWL_BNJ_B_GF_A_FW_PRE __stringify(api) ".ucode"
-#define IWL_BNJ_A_GF4_A_MODULE_FIRMWARE(api) \
- IWL_BNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode"
-#define IWL_BNJ_B_GF4_A_MODULE_FIRMWARE(api) \
- IWL_BNJ_B_GF4_A_FW_PRE __stringify(api) ".ucode"
-#define IWL_BNJ_A_HR_A_MODULE_FIRMWARE(api) \
- IWL_BNJ_A_HR_A_FW_PRE __stringify(api) ".ucode"
-#define IWL_BNJ_A_HR_B_MODULE_FIRMWARE(api) \
- IWL_BNJ_A_HR_B_FW_PRE __stringify(api) ".ucode"
-#define IWL_BNJ_B_HR_A_MODULE_FIRMWARE(api) \
- IWL_BNJ_B_HR_A_FW_PRE __stringify(api) ".ucode"
-#define IWL_BNJ_B_HR_B_MODULE_FIRMWARE(api) \
- IWL_BNJ_B_HR_B_FW_PRE __stringify(api) ".ucode"
-#define IWL_BNJ_B_FM_B_MODULE_FIRMWARE(api) \
- IWL_BNJ_B_FM_B_FW_PRE __stringify(api) ".ucode"
+ IWL_CC_A_FW_PRE "-" __stringify(api) ".ucode"
static const struct iwl_base_params iwl_22000_base_params = {
.eeprom_size = OTP_LOW_IMAGE_SIZE_32K,
@@ -195,34 +59,14 @@ static const struct iwl_base_params iwl_22000_base_params = {
.pcie_l1_allowed = true,
};
-static const struct iwl_base_params iwl_ax210_base_params = {
- .eeprom_size = OTP_LOW_IMAGE_SIZE_32K,
- .num_of_queues = 512,
- .max_tfd_queue_size = 65536,
- .shadow_ram_support = true,
- .led_compensation = 57,
- .wd_timeout = IWL_LONG_WD_TIMEOUT,
- .max_event_log_size = 512,
- .shadow_reg_enable = true,
- .pcie_l1_allowed = true,
-};
-
-static const struct iwl_ht_params iwl_22000_ht_params = {
+const struct iwl_ht_params iwl_22000_ht_params = {
.stbc = true,
.ldpc = true,
.ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ) |
BIT(NL80211_BAND_6GHZ),
};
-static const struct iwl_ht_params iwl_gl_a_ht_params = {
- .stbc = false, /* we explicitly disable STBC for GL step A */
- .ldpc = true,
- .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ) |
- BIT(NL80211_BAND_6GHZ),
-};
-
#define IWL_DEVICE_22000_COMMON \
- .ucode_api_max = IWL_22000_UCODE_API_MAX, \
.ucode_api_min = IWL_22000_UCODE_API_MIN, \
.led_mode = IWL_LED_RF_STATE, \
.nvm_hw_section_num = 10, \
@@ -261,6 +105,7 @@ static const struct iwl_ht_params iwl_gl_a_ht_params = {
#define IWL_DEVICE_22500 \
IWL_DEVICE_22000_COMMON, \
+ .ucode_api_max = IWL_22000_UCODE_API_MAX, \
.trans.device_family = IWL_DEVICE_FAMILY_22000, \
.trans.base_params = &iwl_22000_base_params, \
.gp2_reg_addr = 0xa02c68, \
@@ -275,108 +120,6 @@ static const struct iwl_ht_params iwl_gl_a_ht_params = {
}, \
}
-#define IWL_DEVICE_AX210 \
- IWL_DEVICE_22000_COMMON, \
- .trans.umac_prph_offset = 0x300000, \
- .trans.device_family = IWL_DEVICE_FAMILY_AX210, \
- .trans.base_params = &iwl_ax210_base_params, \
- .min_txq_size = 128, \
- .gp2_reg_addr = 0xd02c68, \
- .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_HE, \
- .mon_dram_regs = { \
- .write_ptr = { \
- .addr = DBGC_CUR_DBGBUF_STATUS, \
- .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \
- }, \
- .cycle_cnt = { \
- .addr = DBGC_DBGBUF_WRAP_AROUND, \
- .mask = 0xffffffff, \
- }, \
- .cur_frag = { \
- .addr = DBGC_CUR_DBGBUF_STATUS, \
- .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \
- }, \
- }
-
-#define IWL_DEVICE_BZ_COMMON \
- .ucode_api_max = IWL_22000_UCODE_API_MAX, \
- .ucode_api_min = IWL_22000_UCODE_API_MIN, \
- .led_mode = IWL_LED_RF_STATE, \
- .nvm_hw_section_num = 10, \
- .non_shared_ant = ANT_B, \
- .dccm_offset = IWL_22000_DCCM_OFFSET, \
- .dccm_len = IWL_22000_DCCM_LEN, \
- .dccm2_offset = IWL_22000_DCCM2_OFFSET, \
- .dccm2_len = IWL_22000_DCCM2_LEN, \
- .smem_offset = IWL_22000_SMEM_OFFSET, \
- .smem_len = IWL_22000_SMEM_LEN, \
- .apmg_not_supported = true, \
- .trans.mq_rx_supported = true, \
- .vht_mu_mimo_supported = true, \
- .mac_addr_from_csr = 0x30, \
- .nvm_ver = IWL_22000_NVM_VERSION, \
- .trans.use_tfh = true, \
- .trans.rf_id = true, \
- .trans.gen2 = true, \
- .nvm_type = IWL_NVM_EXT, \
- .dbgc_supported = true, \
- .min_umac_error_event_table = 0xD0000, \
- .d3_debug_data_base_addr = 0x401000, \
- .d3_debug_data_length = 60 * 1024, \
- .mon_smem_regs = { \
- .write_ptr = { \
- .addr = LDBG_M2S_BUF_WPTR, \
- .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \
- }, \
- .cycle_cnt = { \
- .addr = LDBG_M2S_BUF_WRAP_CNT, \
- .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \
- }, \
- }, \
- .trans.umac_prph_offset = 0x300000, \
- .trans.device_family = IWL_DEVICE_FAMILY_BZ, \
- .trans.base_params = &iwl_ax210_base_params, \
- .min_txq_size = 128, \
- .gp2_reg_addr = 0xd02c68, \
- .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_EHT, \
- .mon_dram_regs = { \
- .write_ptr = { \
- .addr = DBGC_CUR_DBGBUF_STATUS, \
- .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \
- }, \
- .cycle_cnt = { \
- .addr = DBGC_DBGBUF_WRAP_AROUND, \
- .mask = 0xffffffff, \
- }, \
- .cur_frag = { \
- .addr = DBGC_CUR_DBGBUF_STATUS, \
- .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \
- }, \
- }, \
- .mon_dbgi_regs = { \
- .write_ptr = { \
- .addr = DBGI_SRAM_FIFO_POINTERS, \
- .mask = DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK, \
- }, \
- }
-
-#define IWL_DEVICE_BZ \
- IWL_DEVICE_BZ_COMMON, \
- .ht_params = &iwl_22000_ht_params
-
-#define IWL_DEVICE_GL_A \
- IWL_DEVICE_BZ_COMMON, \
- .ht_params = &iwl_gl_a_ht_params
-
-const struct iwl_cfg_trans_params iwl_qnj_trans_cfg = {
- .mq_rx_supported = true,
- .use_tfh = true,
- .rf_id = true,
- .gen2 = true,
- .device_family = IWL_DEVICE_FAMILY_22000,
- .base_params = &iwl_22000_base_params,
-};
-
const struct iwl_cfg_trans_params iwl_qu_trans_cfg = {
.mq_rx_supported = true,
.use_tfh = true,
@@ -414,59 +157,6 @@ const struct iwl_cfg_trans_params iwl_qu_long_latency_trans_cfg = {
.ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
};
-const struct iwl_cfg_trans_params iwl_snj_trans_cfg = {
- .mq_rx_supported = true,
- .use_tfh = true,
- .rf_id = true,
- .gen2 = true,
- .device_family = IWL_DEVICE_FAMILY_AX210,
- .base_params = &iwl_ax210_base_params,
- .umac_prph_offset = 0x300000,
-};
-
-const struct iwl_cfg_trans_params iwl_so_trans_cfg = {
- .mq_rx_supported = true,
- .use_tfh = true,
- .rf_id = true,
- .gen2 = true,
- .device_family = IWL_DEVICE_FAMILY_AX210,
- .base_params = &iwl_ax210_base_params,
- .umac_prph_offset = 0x300000,
- .integrated = true,
- /* TODO: the following values need to be checked */
- .xtal_latency = 500,
- .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US,
-};
-
-const struct iwl_cfg_trans_params iwl_so_long_latency_trans_cfg = {
- .mq_rx_supported = true,
- .use_tfh = true,
- .rf_id = true,
- .gen2 = true,
- .device_family = IWL_DEVICE_FAMILY_AX210,
- .base_params = &iwl_ax210_base_params,
- .umac_prph_offset = 0x300000,
- .integrated = true,
- .low_latency_xtal = true,
- .xtal_latency = 12000,
- .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
-};
-
-const struct iwl_cfg_trans_params iwl_so_long_latency_imr_trans_cfg = {
- .mq_rx_supported = true,
- .use_tfh = true,
- .rf_id = true,
- .gen2 = true,
- .device_family = IWL_DEVICE_FAMILY_AX210,
- .base_params = &iwl_ax210_base_params,
- .umac_prph_offset = 0x300000,
- .integrated = true,
- .low_latency_xtal = true,
- .xtal_latency = 12000,
- .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
- .imr_enabled = true,
-};
-
/*
* If the device doesn't support HE, no need to have that many buffers.
* 22000 devices can split multiple frames into a single RB, so fewer are
@@ -476,7 +166,6 @@ const struct iwl_cfg_trans_params iwl_so_long_latency_imr_trans_cfg = {
*/
#define IWL_NUM_RBDS_NON_HE 512
#define IWL_NUM_RBDS_22000_HE 2048
-#define IWL_NUM_RBDS_AX210_HE 4096
/*
* All JF radio modules are part of the 9000 series, but the MAC part
@@ -507,18 +196,6 @@ const struct iwl_cfg iwl9560_quz_a0_jf_b0_cfg = {
.num_rbds = IWL_NUM_RBDS_NON_HE,
};
-const struct iwl_cfg iwl9560_qnj_b0_jf_b0_cfg = {
- .fw_name_pre = IWL_QNJ_B_JF_B_FW_PRE,
- IWL_DEVICE_22500,
- /*
- * This device doesn't support receiving BlockAck with a large bitmap
- * so we need to restrict the size of transmitted aggregation to the
- * HT size; mac80211 would otherwise pick the HE max (256) by default.
- */
- .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
- .num_rbds = IWL_NUM_RBDS_NON_HE,
-};
-
const struct iwl_cfg_trans_params iwl_ax200_trans_cfg = {
.device_family = IWL_DEVICE_FAMILY_22000,
.base_params = &iwl_22000_base_params,
@@ -529,41 +206,11 @@ const struct iwl_cfg_trans_params iwl_ax200_trans_cfg = {
.bisr_workaround = 1,
};
-const struct iwl_cfg_trans_params iwl_ma_trans_cfg = {
- .device_family = IWL_DEVICE_FAMILY_AX210,
- .base_params = &iwl_ax210_base_params,
- .mq_rx_supported = true,
- .use_tfh = true,
- .rf_id = true,
- .gen2 = true,
- .integrated = true,
- .umac_prph_offset = 0x300000
-};
-
-const struct iwl_cfg_trans_params iwl_bz_trans_cfg = {
- .device_family = IWL_DEVICE_FAMILY_BZ,
- .base_params = &iwl_ax210_base_params,
- .mq_rx_supported = true,
- .use_tfh = true,
- .rf_id = true,
- .gen2 = true,
- .integrated = true,
- .umac_prph_offset = 0x300000,
- .xtal_latency = 12000,
- .low_latency_xtal = true,
- .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
-};
-
const char iwl_ax101_name[] = "Intel(R) Wi-Fi 6 AX101";
const char iwl_ax200_name[] = "Intel(R) Wi-Fi 6 AX200 160MHz";
const char iwl_ax201_name[] = "Intel(R) Wi-Fi 6 AX201 160MHz";
const char iwl_ax203_name[] = "Intel(R) Wi-Fi 6 AX203";
const char iwl_ax204_name[] = "Intel(R) Wi-Fi 6 AX204 160MHz";
-const char iwl_ax211_name[] = "Intel(R) Wi-Fi 6E AX211 160MHz";
-const char iwl_ax221_name[] = "Intel(R) Wi-Fi 6E AX221 160MHz";
-const char iwl_ax231_name[] = "Intel(R) Wi-Fi 6E AX231 160MHz";
-const char iwl_ax411_name[] = "Intel(R) Wi-Fi 6E AX411 160MHz";
-const char iwl_bz_name[] = "Intel(R) TBD Bz device";
const char iwl_ax200_killer_1650w_name[] =
"Killer(R) Wi-Fi 6 AX1650w 160MHz Wireless Network Adapter (200D2W)";
@@ -573,18 +220,6 @@ const char iwl_ax201_killer_1650s_name[] =
"Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)";
const char iwl_ax201_killer_1650i_name[] =
"Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)";
-const char iwl_ax210_killer_1675w_name[] =
- "Killer(R) Wi-Fi 6E AX1675w 160MHz Wireless Network Adapter (210D2W)";
-const char iwl_ax210_killer_1675x_name[] =
- "Killer(R) Wi-Fi 6E AX1675x 160MHz Wireless Network Adapter (210NGW)";
-const char iwl_ax211_killer_1675s_name[] =
- "Killer(R) Wi-Fi 6E AX1675s 160MHz Wireless Network Adapter (211NGW)";
-const char iwl_ax211_killer_1675i_name[] =
- "Killer(R) Wi-Fi 6E AX1675i 160MHz Wireless Network Adapter (211NGW)";
-const char iwl_ax411_killer_1690s_name[] =
- "Killer(R) Wi-Fi 6E AX1690s 160MHz Wireless Network Adapter (411D2W)";
-const char iwl_ax411_killer_1690i_name[] =
- "Killer(R) Wi-Fi 6E AX1690i 160MHz Wireless Network Adapter (411NGW)";
const struct iwl_cfg iwl_qu_b0_hr1_b0 = {
.fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
@@ -778,203 +413,6 @@ const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0 = {
.num_rbds = IWL_NUM_RBDS_22000_HE,
};
-const struct iwl_cfg iwl_qnj_b0_hr_b0_cfg = {
- .fw_name_pre = IWL_QNJ_B_HR_B_FW_PRE,
- IWL_DEVICE_22500,
- /*
- * This device doesn't support receiving BlockAck with a large bitmap
- * so we need to restrict the size of transmitted aggregation to the
- * HT size; mac80211 would otherwise pick the HE max (256) by default.
- */
- .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
- .num_rbds = IWL_NUM_RBDS_22000_HE,
-};
-
-const struct iwl_cfg iwlax210_2ax_cfg_so_jf_b0 = {
- .name = "Intel(R) Wireless-AC 9560 160MHz",
- .fw_name_pre = IWL_SO_A_JF_B_FW_PRE,
- IWL_DEVICE_AX210,
- .num_rbds = IWL_NUM_RBDS_NON_HE,
-};
-
-const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0 = {
- .name = iwl_ax211_name,
- .fw_name_pre = IWL_SO_A_GF_A_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_AX210,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0_long = {
- .name = iwl_ax211_name,
- .fw_name_pre = IWL_SO_A_GF_A_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_AX210,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
- .trans.xtal_latency = 12000,
- .trans.low_latency_xtal = true,
-};
-
-const struct iwl_cfg iwlax210_2ax_cfg_ty_gf_a0 = {
- .name = "Intel(R) Wi-Fi 6 AX210 160MHz",
- .fw_name_pre = IWL_TY_A_GF_A_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_AX210,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0 = {
- .name = iwl_ax411_name,
- .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_AX210,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0_long = {
- .name = iwl_ax411_name,
- .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_AX210,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
- .trans.xtal_latency = 12000,
- .trans.low_latency_xtal = true,
-};
-
-const struct iwl_cfg iwlax411_2ax_cfg_sosnj_gf4_a0 = {
- .name = iwl_ax411_name,
- .fw_name_pre = IWL_SNJ_A_GF4_A_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_AX210,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwlax211_cfg_snj_gf_a0 = {
- .name = iwl_ax211_name,
- .fw_name_pre = IWL_SNJ_A_GF_A_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_AX210,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_snj_hr_b0 = {
- .fw_name_pre = IWL_SNJ_A_HR_B_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_AX210,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_snj_a0_jf_b0 = {
- .fw_name_pre = IWL_SNJ_A_JF_B_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_AX210,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_ma_a0_hr_b0 = {
- .fw_name_pre = IWL_MA_A_HR_B_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_AX210,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_ma_a0_gf_a0 = {
- .fw_name_pre = IWL_MA_A_GF_A_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_AX210,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_ma_a0_gf4_a0 = {
- .fw_name_pre = IWL_MA_A_GF4_A_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_AX210,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_ma_a0_mr_a0 = {
- .fw_name_pre = IWL_MA_A_MR_A_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_AX210,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_ma_a0_ms_a0 = {
- .fw_name_pre = IWL_MA_A_MR_A_FW_PRE,
- .uhb_supported = false,
- IWL_DEVICE_AX210,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_ma_b0_fm_a0 = {
- .fw_name_pre = IWL_MA_B_FM_A_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_AX210,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_ma_b0_hr_b0 = {
- .fw_name_pre = IWL_MA_B_HR_B_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_AX210,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_ma_b0_gf_a0 = {
- .fw_name_pre = IWL_MA_B_GF_A_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_AX210,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_ma_b0_gf4_a0 = {
- .fw_name_pre = IWL_MA_B_GF4_A_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_AX210,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_ma_b0_mr_a0 = {
- .fw_name_pre = IWL_MA_B_MR_A_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_AX210,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_so_a0_ms_a0 = {
- .fw_name_pre = IWL_SO_A_MR_A_FW_PRE,
- .uhb_supported = false,
- IWL_DEVICE_AX210,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_ma_a0_fm_a0 = {
- .fw_name_pre = IWL_MA_A_FM_A_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_AX210,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_snj_a0_mr_a0 = {
- .fw_name_pre = IWL_SNJ_A_MR_A_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_AX210,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_snj_a0_ms_a0 = {
- .fw_name_pre = IWL_SNJ_A_MR_A_FW_PRE,
- .uhb_supported = false,
- IWL_DEVICE_AX210,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_so_a0_hr_a0 = {
- .fw_name_pre = IWL_SO_A_HR_B_FW_PRE,
- IWL_DEVICE_AX210,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
const struct iwl_cfg iwl_cfg_quz_a0_hr_b0 = {
.fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
IWL_DEVICE_22500,
@@ -987,243 +425,9 @@ const struct iwl_cfg iwl_cfg_quz_a0_hr_b0 = {
.num_rbds = IWL_NUM_RBDS_22000_HE,
};
-const struct iwl_cfg iwl_cfg_bz_a0_hr_a0 = {
- .fw_name_pre = IWL_BZ_A_HR_A_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_BZ,
- .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_bz_a0_hr_b0 = {
- .fw_name_pre = IWL_BZ_A_HR_B_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_BZ,
- .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_bz_a0_gf_a0 = {
- .fw_name_pre = IWL_BZ_A_GF_A_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_BZ,
- .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_bz_a0_gf4_a0 = {
- .fw_name_pre = IWL_BZ_A_GF4_A_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_BZ,
- .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_bz_a0_mr_a0 = {
- .fw_name_pre = IWL_BZ_A_MR_A_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_BZ,
- .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_bz_a0_fm_a0 = {
- .fw_name_pre = IWL_BZ_A_FM_A_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_BZ,
- .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_bz_a0_fm4_a0 = {
- .fw_name_pre = IWL_BZ_A_FM4_A_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_BZ,
- .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_bz_a0_fm_b0 = {
- .fw_name_pre = IWL_BZ_A_FM_B_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_BZ,
- .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_bz_a0_fm4_b0 = {
- .fw_name_pre = IWL_BZ_A_FM4_B_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_BZ,
- .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_gl_a0_fm_a0 = {
- .fw_name_pre = IWL_GL_A_FM_A_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_GL_A,
- .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_gl_b0_fm_b0 = {
- .fw_name_pre = IWL_GL_B_FM_B_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_BZ,
- .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_bz_z0_gf_a0 = {
- .fw_name_pre = IWL_BZ_Z_GF_A_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_BZ,
- .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_bnj_a0_fm_a0 = {
- .fw_name_pre = IWL_BNJ_A_FM_A_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_BZ,
- .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_bnj_a0_fm4_a0 = {
- .fw_name_pre = IWL_BNJ_A_FM4_A_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_BZ,
- .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_bnj_b0_fm4_b0 = {
- .fw_name_pre = IWL_BNJ_B_FM4_B_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_BZ,
- .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_bnj_a0_gf_a0 = {
- .fw_name_pre = IWL_BNJ_A_GF_A_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_BZ,
- .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_bnj_b0_gf_a0 = {
- .fw_name_pre = IWL_BNJ_B_GF_A_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_BZ,
- .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_bnj_a0_gf4_a0 = {
- .fw_name_pre = IWL_BNJ_A_GF4_A_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_BZ,
- .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_bnj_b0_gf4_a0 = {
- .fw_name_pre = IWL_BNJ_B_GF4_A_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_BZ,
- .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_bnj_a0_hr_a0 = {
- .fw_name_pre = IWL_BNJ_A_HR_A_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_BZ,
- .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_bnj_a0_hr_b0 = {
- .fw_name_pre = IWL_BNJ_A_HR_B_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_BZ,
- .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_bnj_b0_hr_a0 = {
- .fw_name_pre = IWL_BNJ_B_HR_A_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_BZ,
- .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_bnj_b0_hr_b0 = {
- .fw_name_pre = IWL_BNJ_B_HR_B_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_BZ,
- .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
-
-const struct iwl_cfg iwl_cfg_bnj_b0_fm_b0 = {
- .fw_name_pre = IWL_BNJ_B_FM_B_FW_PRE,
- .uhb_supported = true,
- IWL_DEVICE_BZ,
- .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
- .num_rbds = IWL_NUM_RBDS_AX210_HE,
-};
MODULE_FIRMWARE(IWL_QU_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_QNJ_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
MODULE_FIRMWARE(IWL_QU_C_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
MODULE_FIRMWARE(IWL_QU_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
MODULE_FIRMWARE(IWL_QUZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
MODULE_FIRMWARE(IWL_QUZ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_QNJ_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
MODULE_FIRMWARE(IWL_CC_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_SO_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_SO_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_SO_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_TY_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_SNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_SNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_SNJ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_MA_A_FM_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_MA_B_HR_B_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_MA_B_GF_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_MA_B_GF4_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_MA_B_MR_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_MA_B_FM_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_SNJ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_BZ_A_HR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_BZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_BZ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_BZ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_BZ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_BZ_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_BZ_A_FM_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_GL_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_BNJ_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_BNJ_A_FM4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_BNJ_B_FM4_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_BNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_BNJ_B_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_BNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_BNJ_B_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_BNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_BNJ_B_HR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_BNJ_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_BZ_A_FM4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_BZ_A_FM4_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_GL_B_FM_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL_BNJ_B_FM_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
diff --git a/drivers/net/wireless/intel/iwlwifi/cfg/5000.c b/drivers/net/wireless/intel/iwlwifi/cfg/5000.c
index e2e23d2bc1fe..de7ede59a994 100644
--- a/drivers/net/wireless/intel/iwlwifi/cfg/5000.c
+++ b/drivers/net/wireless/intel/iwlwifi/cfg/5000.c
@@ -2,7 +2,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
- * Copyright(c) 2018 - 2020 Intel Corporation
+ * Copyright(c) 2018 - 2020, 2023 Intel Corporation
*****************************************************************************/
#include <linux/module.h>
@@ -24,11 +24,11 @@
#define EEPROM_5050_TX_POWER_VERSION (4)
#define EEPROM_5050_EEPROM_VERSION (0x21E)
-#define IWL5000_FW_PRE "iwlwifi-5000-"
-#define IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE __stringify(api) ".ucode"
+#define IWL5000_FW_PRE "iwlwifi-5000"
+#define IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE "-" __stringify(api) ".ucode"
-#define IWL5150_FW_PRE "iwlwifi-5150-"
-#define IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE __stringify(api) ".ucode"
+#define IWL5150_FW_PRE "iwlwifi-5150"
+#define IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE "-" __stringify(api) ".ucode"
static const struct iwl_base_params iwl5000_base_params = {
.eeprom_size = IWLAGN_EEPROM_IMG_SIZE,
diff --git a/drivers/net/wireless/intel/iwlwifi/cfg/6000.c b/drivers/net/wireless/intel/iwlwifi/cfg/6000.c
index 20929e59c2f4..f013cf420569 100644
--- a/drivers/net/wireless/intel/iwlwifi/cfg/6000.c
+++ b/drivers/net/wireless/intel/iwlwifi/cfg/6000.c
@@ -2,7 +2,7 @@
/******************************************************************************
*
* Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
- * Copyright(c) 2018 - 2020 Intel Corporation
+ * Copyright(c) 2018 - 2020, 2023 Intel Corporation
*****************************************************************************/
#include <linux/module.h>
@@ -37,17 +37,17 @@
#define EEPROM_6035_TX_POWER_VERSION (6)
#define EEPROM_6035_EEPROM_VERSION (0x753)
-#define IWL6000_FW_PRE "iwlwifi-6000-"
-#define IWL6000_MODULE_FIRMWARE(api) IWL6000_FW_PRE __stringify(api) ".ucode"
+#define IWL6000_FW_PRE "iwlwifi-6000"
+#define IWL6000_MODULE_FIRMWARE(api) IWL6000_FW_PRE "-" __stringify(api) ".ucode"
-#define IWL6050_FW_PRE "iwlwifi-6050-"
-#define IWL6050_MODULE_FIRMWARE(api) IWL6050_FW_PRE __stringify(api) ".ucode"
+#define IWL6050_FW_PRE "iwlwifi-6050"
+#define IWL6050_MODULE_FIRMWARE(api) IWL6050_FW_PRE "-" __stringify(api) ".ucode"
-#define IWL6005_FW_PRE "iwlwifi-6000g2a-"
-#define IWL6005_MODULE_FIRMWARE(api) IWL6005_FW_PRE __stringify(api) ".ucode"
+#define IWL6005_FW_PRE "iwlwifi-6000g2a"
+#define IWL6005_MODULE_FIRMWARE(api) IWL6005_FW_PRE "-" __stringify(api) ".ucode"
-#define IWL6030_FW_PRE "iwlwifi-6000g2b-"
-#define IWL6030_MODULE_FIRMWARE(api) IWL6030_FW_PRE __stringify(api) ".ucode"
+#define IWL6030_FW_PRE "iwlwifi-6000g2b"
+#define IWL6030_MODULE_FIRMWARE(api) IWL6030_FW_PRE "-" __stringify(api) ".ucode"
static const struct iwl_base_params iwl6000_base_params = {
.eeprom_size = OTP_LOW_IMAGE_SIZE_2K,
diff --git a/drivers/net/wireless/intel/iwlwifi/cfg/7000.c b/drivers/net/wireless/intel/iwlwifi/cfg/7000.c
index b24dc5523a52..4e2afdedf4c6 100644
--- a/drivers/net/wireless/intel/iwlwifi/cfg/7000.c
+++ b/drivers/net/wireless/intel/iwlwifi/cfg/7000.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
- * Copyright (C) 2012-2014, 2018-2020 Intel Corporation
+ * Copyright (C) 2012-2014, 2018-2020, 2023 Intel Corporation
* Copyright (C) 2013-2014 Intel Mobile Communications GmbH
* Copyright (C) 2015 Intel Deutschland GmbH
*/
@@ -34,20 +34,20 @@
#define IWL3160_DCCM_LEN 0x10000
#define IWL7265_DCCM_LEN 0x17A00
-#define IWL7260_FW_PRE "iwlwifi-7260-"
-#define IWL7260_MODULE_FIRMWARE(api) IWL7260_FW_PRE __stringify(api) ".ucode"
+#define IWL7260_FW_PRE "iwlwifi-7260"
+#define IWL7260_MODULE_FIRMWARE(api) IWL7260_FW_PRE "-" __stringify(api) ".ucode"
-#define IWL3160_FW_PRE "iwlwifi-3160-"
-#define IWL3160_MODULE_FIRMWARE(api) IWL3160_FW_PRE __stringify(api) ".ucode"
+#define IWL3160_FW_PRE "iwlwifi-3160"
+#define IWL3160_MODULE_FIRMWARE(api) IWL3160_FW_PRE "-" __stringify(api) ".ucode"
-#define IWL3168_FW_PRE "iwlwifi-3168-"
-#define IWL3168_MODULE_FIRMWARE(api) IWL3168_FW_PRE __stringify(api) ".ucode"
+#define IWL3168_FW_PRE "iwlwifi-3168"
+#define IWL3168_MODULE_FIRMWARE(api) IWL3168_FW_PRE "-" __stringify(api) ".ucode"
-#define IWL7265_FW_PRE "iwlwifi-7265-"
-#define IWL7265_MODULE_FIRMWARE(api) IWL7265_FW_PRE __stringify(api) ".ucode"
+#define IWL7265_FW_PRE "iwlwifi-7265"
+#define IWL7265_MODULE_FIRMWARE(api) IWL7265_FW_PRE "-" __stringify(api) ".ucode"
-#define IWL7265D_FW_PRE "iwlwifi-7265D-"
-#define IWL7265D_MODULE_FIRMWARE(api) IWL7265D_FW_PRE __stringify(api) ".ucode"
+#define IWL7265D_FW_PRE "iwlwifi-7265D"
+#define IWL7265D_MODULE_FIRMWARE(api) IWL7265D_FW_PRE "-" __stringify(api) ".ucode"
static const struct iwl_base_params iwl7000_base_params = {
.eeprom_size = OTP_LOW_IMAGE_SIZE_16K,
diff --git a/drivers/net/wireless/intel/iwlwifi/cfg/8000.c b/drivers/net/wireless/intel/iwlwifi/cfg/8000.c
index a6454287d506..d09cf8d7dc01 100644
--- a/drivers/net/wireless/intel/iwlwifi/cfg/8000.c
+++ b/drivers/net/wireless/intel/iwlwifi/cfg/8000.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
- * Copyright (C) 2014, 2018-2020 Intel Corporation
+ * Copyright (C) 2014, 2018-2020, 2023 Intel Corporation
* Copyright (C) 2014-2015 Intel Mobile Communications GmbH
* Copyright (C) 2016 Intel Deutschland GmbH
*/
@@ -27,13 +27,13 @@
#define IWL8260_SMEM_OFFSET 0x400000
#define IWL8260_SMEM_LEN 0x68000
-#define IWL8000_FW_PRE "iwlwifi-8000C-"
+#define IWL8000_FW_PRE "iwlwifi-8000C"
#define IWL8000_MODULE_FIRMWARE(api) \
- IWL8000_FW_PRE __stringify(api) ".ucode"
+ IWL8000_FW_PRE "-" __stringify(api) ".ucode"
-#define IWL8265_FW_PRE "iwlwifi-8265-"
+#define IWL8265_FW_PRE "iwlwifi-8265"
#define IWL8265_MODULE_FIRMWARE(api) \
- IWL8265_FW_PRE __stringify(api) ".ucode"
+ IWL8265_FW_PRE "-" __stringify(api) ".ucode"
#define DEFAULT_NVM_FILE_FAMILY_8000C "nvmData-8000C"
diff --git a/drivers/net/wireless/intel/iwlwifi/cfg/9000.c b/drivers/net/wireless/intel/iwlwifi/cfg/9000.c
index 7a7ca06d46c1..0130d9a9b78b 100644
--- a/drivers/net/wireless/intel/iwlwifi/cfg/9000.c
+++ b/drivers/net/wireless/intel/iwlwifi/cfg/9000.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
* Copyright (C) 2015-2017 Intel Deutschland GmbH
- * Copyright (C) 2018-2021 Intel Corporation
+ * Copyright (C) 2018-2021, 2023 Intel Corporation
*/
#include <linux/module.h>
#include <linux/stringify.h>
@@ -26,12 +26,12 @@
#define IWL9000_SMEM_OFFSET 0x400000
#define IWL9000_SMEM_LEN 0x68000
-#define IWL9000_FW_PRE "iwlwifi-9000-pu-b0-jf-b0-"
-#define IWL9260_FW_PRE "iwlwifi-9260-th-b0-jf-b0-"
+#define IWL9000_FW_PRE "iwlwifi-9000-pu-b0-jf-b0"
+#define IWL9260_FW_PRE "iwlwifi-9260-th-b0-jf-b0"
#define IWL9000_MODULE_FIRMWARE(api) \
- IWL9000_FW_PRE __stringify(api) ".ucode"
+ IWL9000_FW_PRE "-" __stringify(api) ".ucode"
#define IWL9260_MODULE_FIRMWARE(api) \
- IWL9260_FW_PRE __stringify(api) ".ucode"
+ IWL9260_FW_PRE "-" __stringify(api) ".ucode"
static const struct iwl_base_params iwl9000_base_params = {
.eeprom_size = OTP_LOW_IMAGE_SIZE_32K,
diff --git a/drivers/net/wireless/intel/iwlwifi/cfg/ax210.c b/drivers/net/wireless/intel/iwlwifi/cfg/ax210.c
new file mode 100644
index 000000000000..8d5f9dce71d5
--- /dev/null
+++ b/drivers/net/wireless/intel/iwlwifi/cfg/ax210.c
@@ -0,0 +1,301 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * Copyright (C) 2015-2017 Intel Deutschland GmbH
+ * Copyright (C) 2018-2023 Intel Corporation
+ */
+#include <linux/module.h>
+#include <linux/stringify.h>
+#include "iwl-config.h"
+#include "iwl-prph.h"
+#include "fw/api/txq.h"
+
+/* Highest firmware API version supported */
+#define IWL_AX210_UCODE_API_MAX 83
+
+/* Lowest firmware API version supported */
+#define IWL_AX210_UCODE_API_MIN 59
+
+/* NVM versions */
+#define IWL_AX210_NVM_VERSION 0x0a1d
+
+/* Memory offsets and lengths */
+#define IWL_AX210_DCCM_OFFSET 0x800000 /* LMAC1 */
+#define IWL_AX210_DCCM_LEN 0x10000 /* LMAC1 */
+#define IWL_AX210_DCCM2_OFFSET 0x880000
+#define IWL_AX210_DCCM2_LEN 0x8000
+#define IWL_AX210_SMEM_OFFSET 0x400000
+#define IWL_AX210_SMEM_LEN 0xD0000
+
+#define IWL_SO_A_JF_B_FW_PRE "iwlwifi-so-a0-jf-b0"
+#define IWL_SO_A_HR_B_FW_PRE "iwlwifi-so-a0-hr-b0"
+#define IWL_SO_A_GF_A_FW_PRE "iwlwifi-so-a0-gf-a0"
+#define IWL_TY_A_GF_A_FW_PRE "iwlwifi-ty-a0-gf-a0"
+#define IWL_SO_A_GF4_A_FW_PRE "iwlwifi-so-a0-gf4-a0"
+#define IWL_SO_A_MR_A_FW_PRE "iwlwifi-so-a0-mr-a0"
+#define IWL_MA_A_HR_B_FW_PRE "iwlwifi-ma-a0-hr-b0"
+#define IWL_MA_A_GF_A_FW_PRE "iwlwifi-ma-a0-gf-a0"
+#define IWL_MA_A_GF4_A_FW_PRE "iwlwifi-ma-a0-gf4-a0"
+#define IWL_MA_A_MR_A_FW_PRE "iwlwifi-ma-a0-mr-a0"
+#define IWL_MA_B_HR_B_FW_PRE "iwlwifi-ma-b0-hr-b0"
+#define IWL_MA_B_GF_A_FW_PRE "iwlwifi-ma-b0-gf-a0"
+#define IWL_MA_B_GF4_A_FW_PRE "iwlwifi-ma-b0-gf4-a0"
+#define IWL_MA_B_MR_A_FW_PRE "iwlwifi-ma-b0-mr-a0"
+
+#define IWL_SO_A_JF_B_MODULE_FIRMWARE(api) \
+ IWL_SO_A_JF_B_FW_PRE "-" __stringify(api) ".ucode"
+#define IWL_SO_A_HR_B_MODULE_FIRMWARE(api) \
+ IWL_SO_A_HR_B_FW_PRE "-" __stringify(api) ".ucode"
+#define IWL_SO_A_GF_A_MODULE_FIRMWARE(api) \
+ IWL_SO_A_GF_A_FW_PRE "-" __stringify(api) ".ucode"
+#define IWL_TY_A_GF_A_MODULE_FIRMWARE(api) \
+ IWL_TY_A_GF_A_FW_PRE "-" __stringify(api) ".ucode"
+#define IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(api) \
+ IWL_MA_A_HR_B_FW_PRE "-" __stringify(api) ".ucode"
+#define IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(api) \
+ IWL_MA_A_GF_A_FW_PRE "-" __stringify(api) ".ucode"
+#define IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(api) \
+ IWL_MA_A_GF4_A_FW_PRE "-" __stringify(api) ".ucode"
+#define IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(api) \
+ IWL_MA_A_MR_A_FW_PRE "-" __stringify(api) ".ucode"
+#define IWL_MA_B_HR_B_FW_MODULE_FIRMWARE(api) \
+ IWL_MA_B_HR_B_FW_PRE "-" __stringify(api) ".ucode"
+#define IWL_MA_B_GF_A_FW_MODULE_FIRMWARE(api) \
+ IWL_MA_B_GF_A_FW_PRE "-" __stringify(api) ".ucode"
+#define IWL_MA_B_GF4_A_FW_MODULE_FIRMWARE(api) \
+ IWL_MA_B_GF4_A_FW_PRE "-" __stringify(api) ".ucode"
+#define IWL_MA_B_MR_A_FW_MODULE_FIRMWARE(api) \
+ IWL_MA_B_MR_A_FW_PRE "-" __stringify(api) ".ucode"
+
+static const struct iwl_base_params iwl_ax210_base_params = {
+ .eeprom_size = OTP_LOW_IMAGE_SIZE_32K,
+ .num_of_queues = 512,
+ .max_tfd_queue_size = 65536,
+ .shadow_ram_support = true,
+ .led_compensation = 57,
+ .wd_timeout = IWL_LONG_WD_TIMEOUT,
+ .max_event_log_size = 512,
+ .shadow_reg_enable = true,
+ .pcie_l1_allowed = true,
+};
+
+#define IWL_DEVICE_AX210_COMMON \
+ .ucode_api_min = IWL_AX210_UCODE_API_MIN, \
+ .led_mode = IWL_LED_RF_STATE, \
+ .nvm_hw_section_num = 10, \
+ .non_shared_ant = ANT_B, \
+ .dccm_offset = IWL_AX210_DCCM_OFFSET, \
+ .dccm_len = IWL_AX210_DCCM_LEN, \
+ .dccm2_offset = IWL_AX210_DCCM2_OFFSET, \
+ .dccm2_len = IWL_AX210_DCCM2_LEN, \
+ .smem_offset = IWL_AX210_SMEM_OFFSET, \
+ .smem_len = IWL_AX210_SMEM_LEN, \
+ .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, \
+ .apmg_not_supported = true, \
+ .trans.mq_rx_supported = true, \
+ .vht_mu_mimo_supported = true, \
+ .mac_addr_from_csr = 0x380, \
+ .ht_params = &iwl_22000_ht_params, \
+ .nvm_ver = IWL_AX210_NVM_VERSION, \
+ .trans.rf_id = true, \
+ .trans.gen2 = true, \
+ .nvm_type = IWL_NVM_EXT, \
+ .dbgc_supported = true, \
+ .min_umac_error_event_table = 0x400000, \
+ .d3_debug_data_base_addr = 0x401000, \
+ .d3_debug_data_length = 60 * 1024, \
+ .mon_smem_regs = { \
+ .write_ptr = { \
+ .addr = LDBG_M2S_BUF_WPTR, \
+ .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \
+ }, \
+ .cycle_cnt = { \
+ .addr = LDBG_M2S_BUF_WRAP_CNT, \
+ .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \
+ }, \
+ }
+
+#define IWL_DEVICE_AX210 \
+ IWL_DEVICE_AX210_COMMON, \
+ .ucode_api_max = IWL_AX210_UCODE_API_MAX, \
+ .trans.umac_prph_offset = 0x300000, \
+ .trans.device_family = IWL_DEVICE_FAMILY_AX210, \
+ .trans.base_params = &iwl_ax210_base_params, \
+ .min_txq_size = 128, \
+ .gp2_reg_addr = 0xd02c68, \
+ .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_HE, \
+ .mon_dram_regs = { \
+ .write_ptr = { \
+ .addr = DBGC_CUR_DBGBUF_STATUS, \
+ .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \
+ }, \
+ .cycle_cnt = { \
+ .addr = DBGC_DBGBUF_WRAP_AROUND, \
+ .mask = 0xffffffff, \
+ }, \
+ .cur_frag = { \
+ .addr = DBGC_CUR_DBGBUF_STATUS, \
+ .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \
+ }, \
+ }
+
+const struct iwl_cfg_trans_params iwl_so_trans_cfg = {
+ .mq_rx_supported = true,
+ .rf_id = true,
+ .gen2 = true,
+ .device_family = IWL_DEVICE_FAMILY_AX210,
+ .base_params = &iwl_ax210_base_params,
+ .umac_prph_offset = 0x300000,
+ .integrated = true,
+ /* TODO: the following values need to be checked */
+ .xtal_latency = 500,
+ .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US,
+};
+
+const struct iwl_cfg_trans_params iwl_so_long_latency_trans_cfg = {
+ .mq_rx_supported = true,
+ .rf_id = true,
+ .gen2 = true,
+ .device_family = IWL_DEVICE_FAMILY_AX210,
+ .base_params = &iwl_ax210_base_params,
+ .umac_prph_offset = 0x300000,
+ .integrated = true,
+ .low_latency_xtal = true,
+ .xtal_latency = 12000,
+ .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
+};
+
+const struct iwl_cfg_trans_params iwl_so_long_latency_imr_trans_cfg = {
+ .mq_rx_supported = true,
+ .rf_id = true,
+ .gen2 = true,
+ .device_family = IWL_DEVICE_FAMILY_AX210,
+ .base_params = &iwl_ax210_base_params,
+ .umac_prph_offset = 0x300000,
+ .integrated = true,
+ .low_latency_xtal = true,
+ .xtal_latency = 12000,
+ .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
+ .imr_enabled = true,
+};
+
+/*
+ * If the device doesn't support HE, no need to have that many buffers.
+ * AX210 devices can split multiple frames into a single RB, so fewer are
+ * needed; AX210 cannot (but use smaller RBs by default) - these sizes
+ * were picked according to 8 MSDUs inside 256 A-MSDUs in an A-MPDU, with
+ * additional overhead to account for processing time.
+ */
+#define IWL_NUM_RBDS_NON_HE 512
+#define IWL_NUM_RBDS_AX210_HE 4096
+
+const struct iwl_cfg_trans_params iwl_ma_trans_cfg = {
+ .device_family = IWL_DEVICE_FAMILY_AX210,
+ .base_params = &iwl_ax210_base_params,
+ .mq_rx_supported = true,
+ .rf_id = true,
+ .gen2 = true,
+ .integrated = true,
+ .umac_prph_offset = 0x300000
+};
+
+const char iwl_ax211_name[] = "Intel(R) Wi-Fi 6E AX211 160MHz";
+const char iwl_ax221_name[] = "Intel(R) Wi-Fi 6E AX221 160MHz";
+const char iwl_ax231_name[] = "Intel(R) Wi-Fi 6E AX231 160MHz";
+const char iwl_ax411_name[] = "Intel(R) Wi-Fi 6E AX411 160MHz";
+
+const char iwl_ax210_killer_1675w_name[] =
+ "Killer(R) Wi-Fi 6E AX1675w 160MHz Wireless Network Adapter (210D2W)";
+const char iwl_ax210_killer_1675x_name[] =
+ "Killer(R) Wi-Fi 6E AX1675x 160MHz Wireless Network Adapter (210NGW)";
+const char iwl_ax211_killer_1675s_name[] =
+ "Killer(R) Wi-Fi 6E AX1675s 160MHz Wireless Network Adapter (211NGW)";
+const char iwl_ax211_killer_1675i_name[] =
+ "Killer(R) Wi-Fi 6E AX1675i 160MHz Wireless Network Adapter (211NGW)";
+const char iwl_ax411_killer_1690s_name[] =
+ "Killer(R) Wi-Fi 6E AX1690s 160MHz Wireless Network Adapter (411D2W)";
+const char iwl_ax411_killer_1690i_name[] =
+ "Killer(R) Wi-Fi 6E AX1690i 160MHz Wireless Network Adapter (411NGW)";
+
+const struct iwl_cfg iwlax210_2ax_cfg_so_jf_b0 = {
+ .name = "Intel(R) Wireless-AC 9560 160MHz",
+ .fw_name_pre = IWL_SO_A_JF_B_FW_PRE,
+ IWL_DEVICE_AX210,
+ .num_rbds = IWL_NUM_RBDS_NON_HE,
+};
+
+const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0 = {
+ .name = iwl_ax211_name,
+ .fw_name_pre = IWL_SO_A_GF_A_FW_PRE,
+ .uhb_supported = true,
+ IWL_DEVICE_AX210,
+ .num_rbds = IWL_NUM_RBDS_AX210_HE,
+};
+
+const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0_long = {
+ .name = iwl_ax211_name,
+ .fw_name_pre = IWL_SO_A_GF_A_FW_PRE,
+ .uhb_supported = true,
+ IWL_DEVICE_AX210,
+ .num_rbds = IWL_NUM_RBDS_AX210_HE,
+ .trans.xtal_latency = 12000,
+ .trans.low_latency_xtal = true,
+};
+
+const struct iwl_cfg iwlax210_2ax_cfg_ty_gf_a0 = {
+ .name = "Intel(R) Wi-Fi 6 AX210 160MHz",
+ .fw_name_pre = IWL_TY_A_GF_A_FW_PRE,
+ .uhb_supported = true,
+ IWL_DEVICE_AX210,
+ .num_rbds = IWL_NUM_RBDS_AX210_HE,
+};
+
+const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0 = {
+ .name = iwl_ax411_name,
+ .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE,
+ .uhb_supported = true,
+ IWL_DEVICE_AX210,
+ .num_rbds = IWL_NUM_RBDS_AX210_HE,
+};
+
+const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0_long = {
+ .name = iwl_ax411_name,
+ .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE,
+ .uhb_supported = true,
+ IWL_DEVICE_AX210,
+ .num_rbds = IWL_NUM_RBDS_AX210_HE,
+ .trans.xtal_latency = 12000,
+ .trans.low_latency_xtal = true,
+};
+
+const struct iwl_cfg iwl_cfg_so_a0_ms_a0 = {
+ .fw_name_pre = IWL_SO_A_MR_A_FW_PRE,
+ .uhb_supported = false,
+ IWL_DEVICE_AX210,
+ .num_rbds = IWL_NUM_RBDS_AX210_HE,
+};
+
+const struct iwl_cfg iwl_cfg_ma = {
+ .fw_name_mac = "ma",
+ .uhb_supported = true,
+ IWL_DEVICE_AX210,
+ .num_rbds = IWL_NUM_RBDS_AX210_HE,
+};
+
+const struct iwl_cfg iwl_cfg_so_a0_hr_a0 = {
+ .fw_name_pre = IWL_SO_A_HR_B_FW_PRE,
+ IWL_DEVICE_AX210,
+ .num_rbds = IWL_NUM_RBDS_AX210_HE,
+};
+
+MODULE_FIRMWARE(IWL_SO_A_JF_B_MODULE_FIRMWARE(IWL_AX210_UCODE_API_MAX));
+MODULE_FIRMWARE(IWL_SO_A_HR_B_MODULE_FIRMWARE(IWL_AX210_UCODE_API_MAX));
+MODULE_FIRMWARE(IWL_SO_A_GF_A_MODULE_FIRMWARE(IWL_AX210_UCODE_API_MAX));
+MODULE_FIRMWARE(IWL_TY_A_GF_A_MODULE_FIRMWARE(IWL_AX210_UCODE_API_MAX));
+MODULE_FIRMWARE(IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(IWL_AX210_UCODE_API_MAX));
+MODULE_FIRMWARE(IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(IWL_AX210_UCODE_API_MAX));
+MODULE_FIRMWARE(IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(IWL_AX210_UCODE_API_MAX));
+MODULE_FIRMWARE(IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(IWL_AX210_UCODE_API_MAX));
+MODULE_FIRMWARE(IWL_MA_B_HR_B_FW_MODULE_FIRMWARE(IWL_AX210_UCODE_API_MAX));
+MODULE_FIRMWARE(IWL_MA_B_GF_A_FW_MODULE_FIRMWARE(IWL_AX210_UCODE_API_MAX));
+MODULE_FIRMWARE(IWL_MA_B_GF4_A_FW_MODULE_FIRMWARE(IWL_AX210_UCODE_API_MAX));
+MODULE_FIRMWARE(IWL_MA_B_MR_A_FW_MODULE_FIRMWARE(IWL_AX210_UCODE_API_MAX));
diff --git a/drivers/net/wireless/intel/iwlwifi/cfg/bz.c b/drivers/net/wireless/intel/iwlwifi/cfg/bz.c
new file mode 100644
index 000000000000..b9893b22e41d
--- /dev/null
+++ b/drivers/net/wireless/intel/iwlwifi/cfg/bz.c
@@ -0,0 +1,183 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * Copyright (C) 2015-2017 Intel Deutschland GmbH
+ * Copyright (C) 2018-2023 Intel Corporation
+ */
+#include <linux/module.h>
+#include <linux/stringify.h>
+#include "iwl-config.h"
+#include "iwl-prph.h"
+#include "fw/api/txq.h"
+
+/* Highest firmware API version supported */
+#define IWL_BZ_UCODE_API_MAX 83
+
+/* Lowest firmware API version supported */
+#define IWL_BZ_UCODE_API_MIN 80
+
+/* NVM versions */
+#define IWL_BZ_NVM_VERSION 0x0a1d
+
+/* Memory offsets and lengths */
+#define IWL_BZ_DCCM_OFFSET 0x800000 /* LMAC1 */
+#define IWL_BZ_DCCM_LEN 0x10000 /* LMAC1 */
+#define IWL_BZ_DCCM2_OFFSET 0x880000
+#define IWL_BZ_DCCM2_LEN 0x8000
+#define IWL_BZ_SMEM_OFFSET 0x400000
+#define IWL_BZ_SMEM_LEN 0xD0000
+
+#define IWL_BZ_A_HR_B_FW_PRE "iwlwifi-bz-a0-hr-b0"
+#define IWL_BZ_A_GF_A_FW_PRE "iwlwifi-bz-a0-gf-a0"
+#define IWL_BZ_A_GF4_A_FW_PRE "iwlwifi-bz-a0-gf4-a0"
+#define IWL_BZ_A_FM_B_FW_PRE "iwlwifi-bz-a0-fm-b0"
+#define IWL_BZ_A_FM_C_FW_PRE "iwlwifi-bz-a0-fm-c0"
+#define IWL_BZ_A_FM4_B_FW_PRE "iwlwifi-bz-a0-fm4-b0"
+#define IWL_GL_B_FM_B_FW_PRE "iwlwifi-gl-b0-fm-b0"
+#define IWL_GL_C_FM_C_FW_PRE "iwlwifi-gl-c0-fm-c0"
+
+#define IWL_BZ_A_HR_B_MODULE_FIRMWARE(api) \
+ IWL_BZ_A_HR_B_FW_PRE "-" __stringify(api) ".ucode"
+#define IWL_BZ_A_GF_A_MODULE_FIRMWARE(api) \
+ IWL_BZ_A_GF_A_FW_PRE "-" __stringify(api) ".ucode"
+#define IWL_BZ_A_GF4_A_MODULE_FIRMWARE(api) \
+ IWL_BZ_A_GF4_A_FW_PRE "-" __stringify(api) ".ucode"
+#define IWL_BZ_A_FM_B_MODULE_FIRMWARE(api) \
+ IWL_BZ_A_FM_B_FW_PRE "-" __stringify(api) ".ucode"
+#define IWL_BZ_A_FM_C_MODULE_FIRMWARE(api) \
+ IWL_BZ_A_FM_C_FW_PRE "-" __stringify(api) ".ucode"
+#define IWL_BZ_A_FM4_B_MODULE_FIRMWARE(api) \
+ IWL_BZ_A_FM4_B_FW_PRE "-" __stringify(api) ".ucode"
+#define IWL_GL_B_FM_B_MODULE_FIRMWARE(api) \
+ IWL_GL_B_FM_B_FW_PRE "-" __stringify(api) ".ucode"
+#define IWL_GL_C_FM_C_MODULE_FIRMWARE(api) \
+ IWL_GL_C_FM_C_FW_PRE "-" __stringify(api) ".ucode"
+
+static const struct iwl_base_params iwl_bz_base_params = {
+ .eeprom_size = OTP_LOW_IMAGE_SIZE_32K,
+ .num_of_queues = 512,
+ .max_tfd_queue_size = 65536,
+ .shadow_ram_support = true,
+ .led_compensation = 57,
+ .wd_timeout = IWL_LONG_WD_TIMEOUT,
+ .max_event_log_size = 512,
+ .shadow_reg_enable = true,
+ .pcie_l1_allowed = true,
+};
+
+#define IWL_DEVICE_BZ_COMMON \
+ .ucode_api_max = IWL_BZ_UCODE_API_MAX, \
+ .ucode_api_min = IWL_BZ_UCODE_API_MIN, \
+ .led_mode = IWL_LED_RF_STATE, \
+ .nvm_hw_section_num = 10, \
+ .non_shared_ant = ANT_B, \
+ .dccm_offset = IWL_BZ_DCCM_OFFSET, \
+ .dccm_len = IWL_BZ_DCCM_LEN, \
+ .dccm2_offset = IWL_BZ_DCCM2_OFFSET, \
+ .dccm2_len = IWL_BZ_DCCM2_LEN, \
+ .smem_offset = IWL_BZ_SMEM_OFFSET, \
+ .smem_len = IWL_BZ_SMEM_LEN, \
+ .apmg_not_supported = true, \
+ .trans.mq_rx_supported = true, \
+ .vht_mu_mimo_supported = true, \
+ .mac_addr_from_csr = 0x30, \
+ .nvm_ver = IWL_BZ_NVM_VERSION, \
+ .trans.rf_id = true, \
+ .trans.gen2 = true, \
+ .nvm_type = IWL_NVM_EXT, \
+ .dbgc_supported = true, \
+ .min_umac_error_event_table = 0xD0000, \
+ .d3_debug_data_base_addr = 0x401000, \
+ .d3_debug_data_length = 60 * 1024, \
+ .mon_smem_regs = { \
+ .write_ptr = { \
+ .addr = LDBG_M2S_BUF_WPTR, \
+ .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \
+ }, \
+ .cycle_cnt = { \
+ .addr = LDBG_M2S_BUF_WRAP_CNT, \
+ .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \
+ }, \
+ }, \
+ .trans.umac_prph_offset = 0x300000, \
+ .trans.device_family = IWL_DEVICE_FAMILY_BZ, \
+ .trans.base_params = &iwl_bz_base_params, \
+ .min_txq_size = 128, \
+ .gp2_reg_addr = 0xd02c68, \
+ .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_EHT, \
+ .mon_dram_regs = { \
+ .write_ptr = { \
+ .addr = DBGC_CUR_DBGBUF_STATUS, \
+ .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \
+ }, \
+ .cycle_cnt = { \
+ .addr = DBGC_DBGBUF_WRAP_AROUND, \
+ .mask = 0xffffffff, \
+ }, \
+ .cur_frag = { \
+ .addr = DBGC_CUR_DBGBUF_STATUS, \
+ .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \
+ }, \
+ }, \
+ .mon_dbgi_regs = { \
+ .write_ptr = { \
+ .addr = DBGI_SRAM_FIFO_POINTERS, \
+ .mask = DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK, \
+ }, \
+ }
+
+#define IWL_DEVICE_BZ \
+ IWL_DEVICE_BZ_COMMON, \
+ .ht_params = &iwl_22000_ht_params
+
+#define IWL_DEVICE_GL_A \
+ IWL_DEVICE_BZ_COMMON, \
+ .ht_params = &iwl_gl_a_ht_params
+
+/*
+ * If the device doesn't support HE, no need to have that many buffers.
+ * These sizes were picked according to 8 MSDUs inside 256 A-MSDUs in an
+ * A-MPDU, with additional overhead to account for processing time.
+ */
+#define IWL_NUM_RBDS_NON_HE 512
+#define IWL_NUM_RBDS_BZ_HE 4096
+
+const struct iwl_cfg_trans_params iwl_bz_trans_cfg = {
+ .device_family = IWL_DEVICE_FAMILY_BZ,
+ .base_params = &iwl_bz_base_params,
+ .mq_rx_supported = true,
+ .rf_id = true,
+ .gen2 = true,
+ .integrated = true,
+ .umac_prph_offset = 0x300000,
+ .xtal_latency = 12000,
+ .low_latency_xtal = true,
+ .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
+};
+
+const char iwl_bz_name[] = "Intel(R) TBD Bz device";
+
+const struct iwl_cfg iwl_cfg_bz = {
+ .fw_name_mac = "bz",
+ .uhb_supported = true,
+ IWL_DEVICE_BZ,
+ .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
+ .num_rbds = IWL_NUM_RBDS_BZ_HE,
+};
+
+const struct iwl_cfg iwl_cfg_gl = {
+ .fw_name_mac = "gl",
+ .uhb_supported = true,
+ IWL_DEVICE_BZ,
+ .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
+ .num_rbds = IWL_NUM_RBDS_BZ_HE,
+};
+
+
+MODULE_FIRMWARE(IWL_BZ_A_HR_B_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX));
+MODULE_FIRMWARE(IWL_BZ_A_GF_A_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX));
+MODULE_FIRMWARE(IWL_BZ_A_GF4_A_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX));
+MODULE_FIRMWARE(IWL_BZ_A_FM_B_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX));
+MODULE_FIRMWARE(IWL_BZ_A_FM_C_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX));
+MODULE_FIRMWARE(IWL_BZ_A_FM4_B_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX));
+MODULE_FIRMWARE(IWL_GL_B_FM_B_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX));
+MODULE_FIRMWARE(IWL_GL_C_FM_C_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX));
diff --git a/drivers/net/wireless/intel/iwlwifi/cfg/sc.c b/drivers/net/wireless/intel/iwlwifi/cfg/sc.c
new file mode 100644
index 000000000000..ad283fd22e2a
--- /dev/null
+++ b/drivers/net/wireless/intel/iwlwifi/cfg/sc.c
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * Copyright (C) 2015-2017 Intel Deutschland GmbH
+ * Copyright (C) 2018-2023 Intel Corporation
+ */
+#include <linux/module.h>
+#include <linux/stringify.h>
+#include "iwl-config.h"
+#include "iwl-prph.h"
+#include "fw/api/txq.h"
+
+/* Highest firmware API version supported */
+#define IWL_SC_UCODE_API_MAX 83
+
+/* Lowest firmware API version supported */
+#define IWL_SC_UCODE_API_MIN 82
+
+/* NVM versions */
+#define IWL_SC_NVM_VERSION 0x0a1d
+
+/* Memory offsets and lengths */
+#define IWL_SC_DCCM_OFFSET 0x800000 /* LMAC1 */
+#define IWL_SC_DCCM_LEN 0x10000 /* LMAC1 */
+#define IWL_SC_DCCM2_OFFSET 0x880000
+#define IWL_SC_DCCM2_LEN 0x8000
+#define IWL_SC_SMEM_OFFSET 0x400000
+#define IWL_SC_SMEM_LEN 0xD0000
+
+#define IWL_SC_A_FM_B_FW_PRE "iwlwifi-sc-a0-fm-b0"
+#define IWL_SC_A_FM_C_FW_PRE "iwlwifi-sc-a0-fm-c0"
+#define IWL_SC_A_HR_A_FW_PRE "iwlwifi-sc-a0-hr-b0"
+#define IWL_SC_A_HR_B_FW_PRE "iwlwifi-sc-a0-hr-b0"
+#define IWL_SC_A_GF_A_FW_PRE "iwlwifi-sc-a0-gf-a0"
+#define IWL_SC_A_GF4_A_FW_PRE "iwlwifi-sc-a0-gf4-a0"
+#define IWL_SC_A_WH_A_FW_PRE "iwlwifi-sc-a0-wh-a0"
+
+#define IWL_SC_A_FM_B_FW_MODULE_FIRMWARE(api) \
+ IWL_SC_A_FM_B_FW_PRE "-" __stringify(api) ".ucode"
+#define IWL_SC_A_FM_C_FW_MODULE_FIRMWARE(api) \
+ IWL_SC_A_FM_C_FW_PRE "-" __stringify(api) ".ucode"
+#define IWL_SC_A_HR_A_FW_MODULE_FIRMWARE(api) \
+ IWL_SC_A_HR_A_FW_PRE "-" __stringify(api) ".ucode"
+#define IWL_SC_A_HR_B_FW_MODULE_FIRMWARE(api) \
+ IWL_SC_A_HR_B_FW_PRE "-" __stringify(api) ".ucode"
+#define IWL_SC_A_GF_A_FW_MODULE_FIRMWARE(api) \
+ IWL_SC_A_GF_A_FW_PRE "-" __stringify(api) ".ucode"
+#define IWL_SC_A_GF4_A_FW_MODULE_FIRMWARE(api) \
+ IWL_SC_A_GF4_A_FW_PRE "-" __stringify(api) ".ucode"
+#define IWL_SC_A_WH_A_FW_MODULE_FIRMWARE(api) \
+ IWL_SC_A_WH_A_FW_PRE "-" __stringify(api) ".ucode"
+
+static const struct iwl_base_params iwl_sc_base_params = {
+ .eeprom_size = OTP_LOW_IMAGE_SIZE_32K,
+ .num_of_queues = 512,
+ .max_tfd_queue_size = 65536,
+ .shadow_ram_support = true,
+ .led_compensation = 57,
+ .wd_timeout = IWL_LONG_WD_TIMEOUT,
+ .max_event_log_size = 512,
+ .shadow_reg_enable = true,
+ .pcie_l1_allowed = true,
+};
+
+#define IWL_DEVICE_BZ_COMMON \
+ .ucode_api_max = IWL_SC_UCODE_API_MAX, \
+ .ucode_api_min = IWL_SC_UCODE_API_MIN, \
+ .led_mode = IWL_LED_RF_STATE, \
+ .nvm_hw_section_num = 10, \
+ .non_shared_ant = ANT_B, \
+ .dccm_offset = IWL_SC_DCCM_OFFSET, \
+ .dccm_len = IWL_SC_DCCM_LEN, \
+ .dccm2_offset = IWL_SC_DCCM2_OFFSET, \
+ .dccm2_len = IWL_SC_DCCM2_LEN, \
+ .smem_offset = IWL_SC_SMEM_OFFSET, \
+ .smem_len = IWL_SC_SMEM_LEN, \
+ .apmg_not_supported = true, \
+ .trans.mq_rx_supported = true, \
+ .vht_mu_mimo_supported = true, \
+ .mac_addr_from_csr = 0x30, \
+ .nvm_ver = IWL_SC_NVM_VERSION, \
+ .trans.rf_id = true, \
+ .trans.gen2 = true, \
+ .nvm_type = IWL_NVM_EXT, \
+ .dbgc_supported = true, \
+ .min_umac_error_event_table = 0xD0000, \
+ .d3_debug_data_base_addr = 0x401000, \
+ .d3_debug_data_length = 60 * 1024, \
+ .mon_smem_regs = { \
+ .write_ptr = { \
+ .addr = LDBG_M2S_BUF_WPTR, \
+ .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \
+ }, \
+ .cycle_cnt = { \
+ .addr = LDBG_M2S_BUF_WRAP_CNT, \
+ .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \
+ }, \
+ }, \
+ .trans.umac_prph_offset = 0x300000, \
+ .trans.device_family = IWL_DEVICE_FAMILY_SC, \
+ .trans.base_params = &iwl_sc_base_params, \
+ .min_txq_size = 128, \
+ .gp2_reg_addr = 0xd02c68, \
+ .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_EHT, \
+ .mon_dram_regs = { \
+ .write_ptr = { \
+ .addr = DBGC_CUR_DBGBUF_STATUS, \
+ .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \
+ }, \
+ .cycle_cnt = { \
+ .addr = DBGC_DBGBUF_WRAP_AROUND, \
+ .mask = 0xffffffff, \
+ }, \
+ .cur_frag = { \
+ .addr = DBGC_CUR_DBGBUF_STATUS, \
+ .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \
+ }, \
+ }, \
+ .mon_dbgi_regs = { \
+ .write_ptr = { \
+ .addr = DBGI_SRAM_FIFO_POINTERS, \
+ .mask = DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK, \
+ }, \
+ }
+
+#define IWL_DEVICE_SC \
+ IWL_DEVICE_BZ_COMMON, \
+ .ht_params = &iwl_22000_ht_params
+
+/*
+ * If the device doesn't support HE, no need to have that many buffers.
+ * These sizes were picked according to 8 MSDUs inside 256 A-MSDUs in an
+ * A-MPDU, with additional overhead to account for processing time.
+ */
+#define IWL_NUM_RBDS_NON_HE 512
+#define IWL_NUM_RBDS_SC_HE 4096
+
+const struct iwl_cfg_trans_params iwl_sc_trans_cfg = {
+ .device_family = IWL_DEVICE_FAMILY_SC,
+ .base_params = &iwl_sc_base_params,
+ .mq_rx_supported = true,
+ .rf_id = true,
+ .gen2 = true,
+ .integrated = true,
+ .umac_prph_offset = 0x300000,
+ .xtal_latency = 12000,
+ .low_latency_xtal = true,
+ .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
+};
+
+const char iwl_sc_name[] = "Intel(R) TBD Sc device";
+
+const struct iwl_cfg iwl_cfg_sc = {
+ .fw_name_mac = "sc",
+ .uhb_supported = true,
+ IWL_DEVICE_SC,
+ .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
+ .num_rbds = IWL_NUM_RBDS_SC_HE,
+};
+
+MODULE_FIRMWARE(IWL_SC_A_FM_B_FW_MODULE_FIRMWARE(IWL_SC_UCODE_API_MAX));
+MODULE_FIRMWARE(IWL_SC_A_FM_C_FW_MODULE_FIRMWARE(IWL_SC_UCODE_API_MAX));
+MODULE_FIRMWARE(IWL_SC_A_HR_A_FW_MODULE_FIRMWARE(IWL_SC_UCODE_API_MAX));
+MODULE_FIRMWARE(IWL_SC_A_HR_B_FW_MODULE_FIRMWARE(IWL_SC_UCODE_API_MAX));
+MODULE_FIRMWARE(IWL_SC_A_GF_A_FW_MODULE_FIRMWARE(IWL_SC_UCODE_API_MAX));
+MODULE_FIRMWARE(IWL_SC_A_GF4_A_FW_MODULE_FIRMWARE(IWL_SC_UCODE_API_MAX));
+MODULE_FIRMWARE(IWL_SC_A_WH_A_FW_MODULE_FIRMWARE(IWL_SC_UCODE_API_MAX));
diff --git a/drivers/net/wireless/intel/iwlwifi/dvm/rs.c b/drivers/net/wireless/intel/iwlwifi/dvm/rs.c
index 687c906a9d72..f4a6f76cf193 100644
--- a/drivers/net/wireless/intel/iwlwifi/dvm/rs.c
+++ b/drivers/net/wireless/intel/iwlwifi/dvm/rs.c
@@ -2,7 +2,7 @@
/******************************************************************************
*
* Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
- * Copyright (C) 2019 - 2020, 2022 Intel Corporation
+ * Copyright (C) 2019 - 2020, 2022 - 2023 Intel Corporation
*****************************************************************************/
#include <linux/kernel.h>
#include <linux/skbuff.h>
@@ -125,7 +125,7 @@ static int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
return idx;
}
- return -1;
+ return IWL_RATE_INVALID;
}
static void rs_rate_scale_perform(struct iwl_priv *priv,
@@ -203,23 +203,6 @@ static const u16 expected_tpt_mimo3_40MHz[4][IWL_RATE_COUNT] = {
{0, 0, 0, 0, 277, 0, 478, 624, 737, 911, 1026, 1070, 1109}, /* AGG+SGI */
};
-/* mbps, mcs */
-static const struct iwl_rate_mcs_info iwl_rate_mcs[IWL_RATE_COUNT] = {
- { "1", "BPSK DSSS"},
- { "2", "QPSK DSSS"},
- {"5.5", "BPSK CCK"},
- { "11", "QPSK CCK"},
- { "6", "BPSK 1/2"},
- { "9", "BPSK 1/2"},
- { "12", "QPSK 1/2"},
- { "18", "QPSK 3/4"},
- { "24", "16QAM 1/2"},
- { "36", "16QAM 3/4"},
- { "48", "64QAM 2/3"},
- { "54", "64QAM 3/4"},
- { "60", "64QAM 5/6"},
-};
-
#define MCS_INDEX_PER_STREAM (8)
static void rs_rate_scale_clear_window(struct iwl_rate_scale_data *window)
@@ -3089,6 +3072,23 @@ static ssize_t rs_sta_dbgfs_scale_table_read(struct file *file,
int index = 0;
ssize_t ret;
+ /* mbps, mcs */
+ static const struct iwl_rate_mcs_info iwl_rate_mcs[IWL_RATE_COUNT] = {
+ { "1", "BPSK DSSS"},
+ { "2", "QPSK DSSS"},
+ {"5.5", "BPSK CCK"},
+ { "11", "QPSK CCK"},
+ { "6", "BPSK 1/2"},
+ { "9", "BPSK 1/2"},
+ { "12", "QPSK 1/2"},
+ { "18", "QPSK 3/4"},
+ { "24", "16QAM 1/2"},
+ { "36", "16QAM 3/4"},
+ { "48", "64QAM 2/3"},
+ { "54", "64QAM 3/4"},
+ { "60", "64QAM 5/6"},
+ };
+
struct iwl_lq_sta *lq_sta = file->private_data;
struct iwl_priv *priv;
struct iwl_scale_tbl_info *tbl = &(lq_sta->lq_info[lq_sta->active_tbl]);
@@ -3146,7 +3146,10 @@ static ssize_t rs_sta_dbgfs_scale_table_read(struct file *file,
for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
index = iwl_hwrate_to_plcp_idx(
le32_to_cpu(lq_sta->lq.rs_table[i].rate_n_flags));
- if (is_legacy(tbl->lq_type)) {
+ if (index == IWL_RATE_INVALID) {
+ desc += sprintf(buff + desc, " rate[%d] 0x%X invalid rate\n",
+ i, le32_to_cpu(lq_sta->lq.rs_table[i].rate_n_flags));
+ } else if (is_legacy(tbl->lq_type)) {
desc += sprintf(buff+desc, " rate[%d] 0x%X %smbps\n",
i, le32_to_cpu(lq_sta->lq.rs_table[i].rate_n_flags),
iwl_rate_mcs[index].mbps);
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/acpi.c b/drivers/net/wireless/intel/iwlwifi/fw/acpi.c
index cb9181f05501..dfe8357036eb 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/acpi.c
+++ b/drivers/net/wireless/intel/iwlwifi/fw/acpi.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
* Copyright (C) 2017 Intel Deutschland GmbH
- * Copyright (C) 2019-2022 Intel Corporation
+ * Copyright (C) 2019-2023 Intel Corporation
*/
#include <linux/uuid.h>
#include <linux/dmi.h>
@@ -41,6 +41,34 @@ static const struct dmi_system_id dmi_ppag_approved_list[] = {
DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
},
},
+ { .ident = "GOOGLE-HP",
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "Google"),
+ DMI_MATCH(DMI_BOARD_VENDOR, "HP"),
+ },
+ },
+ { .ident = "GOOGLE-ASUS",
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "Google"),
+ DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTek COMPUTER INC."),
+ },
+ },
+ { .ident = "GOOGLE-SAMSUNG",
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "Google"),
+ DMI_MATCH(DMI_BOARD_VENDOR, "SAMSUNG ELECTRONICS CO., LTD"),
+ },
+ },
+ { .ident = "DELL",
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
+ },
+ },
+ { .ident = "DELL",
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "Alienware"),
+ },
+ },
{}
};
@@ -66,7 +94,7 @@ static int iwl_acpi_get_handle(struct device *dev, acpi_string method,
return 0;
}
-void *iwl_acpi_get_object(struct device *dev, acpi_string method)
+static void *iwl_acpi_get_object(struct device *dev, acpi_string method)
{
struct acpi_buffer buf = {ACPI_ALLOCATE_BUFFER, NULL};
acpi_handle handle;
@@ -87,7 +115,6 @@ void *iwl_acpi_get_object(struct device *dev, acpi_string method)
}
return buf.pointer;
}
-IWL_EXPORT_SYMBOL(iwl_acpi_get_object);
/*
* Generic function for evaluating a method defined in the device specific
@@ -209,11 +236,12 @@ int iwl_acpi_get_dsm_u32(struct device *dev, int rev, int func,
}
IWL_EXPORT_SYMBOL(iwl_acpi_get_dsm_u32);
-union acpi_object *iwl_acpi_get_wifi_pkg_range(struct device *dev,
- union acpi_object *data,
- int min_data_size,
- int max_data_size,
- int *tbl_rev)
+static union acpi_object *
+iwl_acpi_get_wifi_pkg_range(struct device *dev,
+ union acpi_object *data,
+ int min_data_size,
+ int max_data_size,
+ int *tbl_rev)
{
int i;
union acpi_object *wifi_pkg;
@@ -264,7 +292,16 @@ union acpi_object *iwl_acpi_get_wifi_pkg_range(struct device *dev,
found:
return wifi_pkg;
}
-IWL_EXPORT_SYMBOL(iwl_acpi_get_wifi_pkg_range);
+
+static union acpi_object *
+iwl_acpi_get_wifi_pkg(struct device *dev,
+ union acpi_object *data,
+ int data_size, int *tbl_rev)
+{
+ return iwl_acpi_get_wifi_pkg_range(dev, data, data_size, data_size,
+ tbl_rev);
+}
+
int iwl_acpi_get_tas(struct iwl_fw_runtime *fwrt,
union iwl_tas_config_cmd *cmd, int fw_ver)
@@ -1141,33 +1178,48 @@ int iwl_read_ppag_table(struct iwl_fw_runtime *fwrt, union iwl_ppag_table_cmd *c
*/
cmd->v1.flags = cpu_to_le32(fwrt->ppag_flags);
+ IWL_DEBUG_RADIO(fwrt, "PPAG cmd ver is %d\n", cmd_ver);
if (cmd_ver == 1) {
num_sub_bands = IWL_NUM_SUB_BANDS_V1;
gain = cmd->v1.gain[0];
*cmd_size = sizeof(cmd->v1);
if (fwrt->ppag_ver == 1 || fwrt->ppag_ver == 2) {
+ /* in this case FW supports revision 0 */
IWL_DEBUG_RADIO(fwrt,
- "PPAG table rev is %d but FW supports v1, sending truncated table\n",
+ "PPAG table rev is %d, send truncated table\n",
fwrt->ppag_ver);
- cmd->v1.flags &= cpu_to_le32(IWL_PPAG_ETSI_MASK);
}
} else if (cmd_ver >= 2 && cmd_ver <= 4) {
num_sub_bands = IWL_NUM_SUB_BANDS_V2;
gain = cmd->v2.gain[0];
*cmd_size = sizeof(cmd->v2);
if (fwrt->ppag_ver == 0) {
+ /* in this case FW supports revisions 1 or 2 */
IWL_DEBUG_RADIO(fwrt,
- "PPAG table is v1 but FW supports v2, sending padded table\n");
- } else if (cmd_ver == 2 && fwrt->ppag_ver == 2) {
- IWL_DEBUG_RADIO(fwrt,
- "PPAG table is v3 but FW supports v2, sending partial bitmap.\n");
- cmd->v1.flags &= cpu_to_le32(IWL_PPAG_ETSI_MASK);
+ "PPAG table rev is 0, send padded table\n");
}
} else {
IWL_DEBUG_RADIO(fwrt, "Unsupported PPAG command version\n");
return -EINVAL;
}
+ /* ppag mode */
+ IWL_DEBUG_RADIO(fwrt,
+ "PPAG MODE bits were read from bios: %d\n",
+ cmd->v1.flags & cpu_to_le32(ACPI_PPAG_MASK));
+ if ((cmd_ver == 1 && !fw_has_capa(&fwrt->fw->ucode_capa,
+ IWL_UCODE_TLV_CAPA_PPAG_CHINA_BIOS_SUPPORT)) ||
+ (cmd_ver == 2 && fwrt->ppag_ver == 2)) {
+ cmd->v1.flags &= cpu_to_le32(IWL_PPAG_ETSI_MASK);
+ IWL_DEBUG_RADIO(fwrt, "masking ppag China bit\n");
+ } else {
+ IWL_DEBUG_RADIO(fwrt, "isn't masking ppag China bit\n");
+ }
+
+ IWL_DEBUG_RADIO(fwrt,
+ "PPAG MODE bits going to be sent: %d\n",
+ cmd->v1.flags & cpu_to_le32(ACPI_PPAG_MASK));
+
for (i = 0; i < IWL_NUM_CHAIN_LIMITS; i++) {
for (j = 0; j < num_sub_bands; j++) {
gain[i * num_sub_bands + j] =
@@ -1196,3 +1248,40 @@ bool iwl_acpi_is_ppag_approved(struct iwl_fw_runtime *fwrt)
return true;
}
IWL_EXPORT_SYMBOL(iwl_acpi_is_ppag_approved);
+
+void iwl_acpi_get_phy_filters(struct iwl_fw_runtime *fwrt,
+ struct iwl_phy_specific_cfg *filters)
+{
+ struct iwl_phy_specific_cfg tmp = {};
+ union acpi_object *wifi_pkg, *data;
+ int tbl_rev, i;
+
+ data = iwl_acpi_get_object(fwrt->dev, ACPI_WPFC_METHOD);
+ if (IS_ERR(data))
+ return;
+
+ /* try to read wtas table revision 1 or revision 0*/
+ wifi_pkg = iwl_acpi_get_wifi_pkg(fwrt->dev, data,
+ ACPI_WPFC_WIFI_DATA_SIZE,
+ &tbl_rev);
+ if (IS_ERR(wifi_pkg))
+ goto out_free;
+
+ if (tbl_rev != 0)
+ goto out_free;
+
+ BUILD_BUG_ON(ARRAY_SIZE(filters->filter_cfg_chains) != ACPI_WPFC_WIFI_DATA_SIZE);
+
+ for (i = 0; i < ARRAY_SIZE(filters->filter_cfg_chains); i++) {
+ if (wifi_pkg->package.elements[i].type != ACPI_TYPE_INTEGER)
+ return;
+ tmp.filter_cfg_chains[i] =
+ cpu_to_le32(wifi_pkg->package.elements[i].integer.value);
+ }
+
+ IWL_DEBUG_RADIO(fwrt, "Loaded WPFC filter config from ACPI\n");
+ *filters = tmp;
+out_free:
+ kfree(data);
+}
+IWL_EXPORT_SYMBOL(iwl_acpi_get_phy_filters);
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/acpi.h b/drivers/net/wireless/intel/iwlwifi/fw/acpi.h
index 6f361c59106f..c36c62d6414d 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/acpi.h
+++ b/drivers/net/wireless/intel/iwlwifi/fw/acpi.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/*
* Copyright (C) 2017 Intel Deutschland GmbH
- * Copyright (C) 2018-2022 Intel Corporation
+ * Copyright (C) 2018-2023 Intel Corporation
*/
#ifndef __iwl_fw_acpi__
#define __iwl_fw_acpi__
@@ -11,6 +11,7 @@
#include "fw/api/power.h"
#include "fw/api/phy.h"
#include "fw/api/nvm-reg.h"
+#include "fw/api/config.h"
#include "fw/img.h"
#include "iwl-trans.h"
@@ -23,6 +24,7 @@
#define ACPI_ECKV_METHOD "ECKV"
#define ACPI_PPAG_METHOD "PPAG"
#define ACPI_WTAS_METHOD "WTAS"
+#define ACPI_WPFC_METHOD "WPFC"
#define ACPI_WIFI_DOMAIN (0x07)
@@ -54,6 +56,7 @@
#define ACPI_EWRD_WIFI_DATA_SIZE_REV2 ((ACPI_SAR_PROFILE_NUM - 1) * \
ACPI_SAR_NUM_CHAINS_REV2 * \
ACPI_SAR_NUM_SUB_BANDS_REV2 + 3)
+#define ACPI_WPFC_WIFI_DATA_SIZE 4 /* 4 filter config words */
/* revision 0 and 1 are identical, except for the semantics in the FW */
#define ACPI_GEO_NUM_BANDS_REV0 2
@@ -168,19 +171,12 @@ struct iwl_fw_runtime;
extern const guid_t iwl_guid;
extern const guid_t iwl_rfi_guid;
-void *iwl_acpi_get_object(struct device *dev, acpi_string method);
-
int iwl_acpi_get_dsm_u8(struct device *dev, int rev, int func,
const guid_t *guid, u8 *value);
int iwl_acpi_get_dsm_u32(struct device *dev, int rev, int func,
const guid_t *guid, u32 *value);
-union acpi_object *iwl_acpi_get_wifi_pkg_range(struct device *dev,
- union acpi_object *data,
- int min_data_size,
- int max_data_size,
- int *tbl_rev);
/**
* iwl_acpi_get_mcc - read MCC from ACPI, if available
*
@@ -232,12 +228,10 @@ int iwl_read_ppag_table(struct iwl_fw_runtime *fwrt, union iwl_ppag_table_cmd *c
bool iwl_acpi_is_ppag_approved(struct iwl_fw_runtime *fwrt);
-#else /* CONFIG_ACPI */
+void iwl_acpi_get_phy_filters(struct iwl_fw_runtime *fwrt,
+ struct iwl_phy_specific_cfg *filters);
-static inline void *iwl_acpi_get_object(struct device *dev, acpi_string method)
-{
- return ERR_PTR(-ENOENT);
-}
+#else /* CONFIG_ACPI */
static inline void *iwl_acpi_get_dsm_object(struct device *dev, int rev,
int func, union acpi_object *args)
@@ -257,15 +251,6 @@ static inline int iwl_acpi_get_dsm_u32(struct device *dev, int rev, int func,
return -ENOENT;
}
-static inline union acpi_object *
-iwl_acpi_get_wifi_pkg_range(struct device *dev,
- union acpi_object *data,
- int min_data_size, int max_data_size,
- int *tbl_rev)
-{
- return ERR_PTR(-ENOENT);
-}
-
static inline int iwl_acpi_get_mcc(struct device *dev, char *mcc)
{
return -ENOENT;
@@ -335,15 +320,11 @@ static inline bool iwl_acpi_is_ppag_approved(struct iwl_fw_runtime *fwrt)
return false;
}
-#endif /* CONFIG_ACPI */
-
-static inline union acpi_object *
-iwl_acpi_get_wifi_pkg(struct device *dev,
- union acpi_object *data,
- int data_size, int *tbl_rev)
+static inline void iwl_acpi_get_phy_filters(struct iwl_fw_runtime *fwrt,
+ struct iwl_phy_specific_cfg *filters)
{
- return iwl_acpi_get_wifi_pkg_range(dev, data, data_size, data_size,
- tbl_rev);
}
+#endif /* CONFIG_ACPI */
+
#endif /* __iwl_fw_acpi__ */
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/api/binding.h b/drivers/net/wireless/intel/iwlwifi/fw/api/binding.h
index 29e2816e7052..d9044ada6a43 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/api/binding.h
+++ b/drivers/net/wireless/intel/iwlwifi/fw/api/binding.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/*
- * Copyright (C) 2012-2014, 2020 Intel Corporation
+ * Copyright (C) 2012-2014, 2020, 2022 Intel Corporation
* Copyright (C) 2013-2015 Intel Mobile Communications GmbH
* Copyright (C) 2016-2017 Intel Deutschland GmbH
*/
@@ -18,7 +18,7 @@
* ( BINDING_CONTEXT_CMD = 0x2b )
* @id_and_color: ID and color of the relevant Binding,
* &enum iwl_ctxt_id_and_color
- * @action: action to perform, one of FW_CTXT_ACTION_*
+ * @action: action to perform, see &enum iwl_ctxt_action
* @macs: array of MAC id and colors which belong to the binding,
* &enum iwl_ctxt_id_and_color
* @phy: PHY id and color which belongs to the binding,
@@ -38,7 +38,7 @@ struct iwl_binding_cmd_v1 {
* ( BINDING_CONTEXT_CMD = 0x2b )
* @id_and_color: ID and color of the relevant Binding,
* &enum iwl_ctxt_id_and_color
- * @action: action to perform, one of FW_CTXT_ACTION_*
+ * @action: action to perform, see &enum iwl_ctxt_action
* @macs: array of MAC id and colors which belong to the binding
* &enum iwl_ctxt_id_and_color
* @phy: PHY id and color which belongs to the binding
@@ -59,14 +59,6 @@ struct iwl_binding_cmd {
#define IWL_LMAC_24G_INDEX 0
#define IWL_LMAC_5G_INDEX 1
-static inline u32 iwl_mvm_get_lmac_id(const struct iwl_fw *fw,
- enum nl80211_band band){
- if (!fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_CDB_SUPPORT) ||
- band == NL80211_BAND_2GHZ)
- return IWL_LMAC_24G_INDEX;
- return IWL_LMAC_5G_INDEX;
-}
-
/* The maximal number of fragments in the FW's schedule session */
#define IWL_MVM_MAX_QUOTA 128
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/api/commands.h b/drivers/net/wireless/intel/iwlwifi/fw/api/commands.h
index 111d96cbde6f..13cb0d53a1a3 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/api/commands.h
+++ b/drivers/net/wireless/intel/iwlwifi/fw/api/commands.h
@@ -139,11 +139,6 @@ enum iwl_legacy_cmds {
REMOVE_STA = 0x19,
/**
- * @FW_GET_ITEM_CMD: uses &struct iwl_fw_get_item_cmd
- */
- FW_GET_ITEM_CMD = 0x1a,
-
- /**
* @TX_CMD: uses &struct iwl_tx_cmd or &struct iwl_tx_cmd_gen2 or
* &struct iwl_tx_cmd_gen3,
* response in &struct iwl_mvm_tx_resp or
@@ -534,12 +529,6 @@ enum iwl_legacy_cmds {
PROT_OFFLOAD_CONFIG_CMD = 0xd4,
/**
- * @OFFLOADS_QUERY_CMD:
- * No data in command, response in &struct iwl_wowlan_status
- */
- OFFLOADS_QUERY_CMD = 0xd5,
-
- /**
* @D0I3_END_CMD: End D0i3/D3 state, no command data
*/
D0I3_END_CMD = 0xed,
@@ -566,18 +555,22 @@ enum iwl_legacy_cmds {
WOWLAN_TKIP_PARAM = 0xe3,
/**
- * @WOWLAN_KEK_KCK_MATERIAL: &struct iwl_wowlan_kek_kck_material_cmd
+ * @WOWLAN_KEK_KCK_MATERIAL: &struct iwl_wowlan_kek_kck_material_cmd_v2,
+ * &struct iwl_wowlan_kek_kck_material_cmd_v3 or
+ * &struct iwl_wowlan_kek_kck_material_cmd_v4
*/
WOWLAN_KEK_KCK_MATERIAL = 0xe4,
/**
- * @WOWLAN_GET_STATUSES: response in &struct iwl_wowlan_status
+ * @WOWLAN_GET_STATUSES: response in &struct iwl_wowlan_status_v6,
+ * &struct iwl_wowlan_status_v7, &struct iwl_wowlan_status_v9 or
+ * &struct iwl_wowlan_status_v12
*/
WOWLAN_GET_STATUSES = 0xe5,
/**
- * @SCAN_OFFLOAD_PROFILES_QUERY_CMD:
- * No command data, response is &struct iwl_scan_offload_profiles_query
+ * @SCAN_OFFLOAD_PROFILES_QUERY_CMD: No command data, response is
+ * &struct iwl_scan_offload_profiles_query_v1
*/
SCAN_OFFLOAD_PROFILES_QUERY_CMD = 0x56,
};
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/api/config.h b/drivers/net/wireless/intel/iwlwifi/fw/api/config.h
index 087354b3c308..4419631604b4 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/api/config.h
+++ b/drivers/net/wireless/intel/iwlwifi/fw/api/config.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/*
- * Copyright (C) 2012-2014, 2018-2019 Intel Corporation
+ * Copyright (C) 2012-2014, 2018-2019, 2023 Intel Corporation
* Copyright (C) 2013-2015 Intel Mobile Communications GmbH
* Copyright (C) 2016-2017 Intel Deutschland GmbH
*/
@@ -67,17 +67,12 @@ enum iwl_calib_cfg {
* Sent as part of the phy configuration command (v3) to configure specific FW
* defined PHY filters that can be applied to each antenna.
*
- * @filter_cfg_chain_a: filter config id for LMAC1 chain A
- * @filter_cfg_chain_b: filter config id for LMAC1 chain B
- * @filter_cfg_chain_c: filter config id for LMAC2 chain A
- * @filter_cfg_chain_d: filter config id for LMAC2 chain B
- * values: 0 - no filter; 0xffffffff - reserved; otherwise - filter id
+ * @filter_cfg_chains: filter config id for LMAC1 chain A, LMAC1 chain B,
+ * LMAC2 chain A, LMAC2 chain B (in that order)
+ * values: 0: no filter; 0xffffffff: reserved; otherwise: filter id
*/
struct iwl_phy_specific_cfg {
- __le32 filter_cfg_chain_a;
- __le32 filter_cfg_chain_b;
- __le32 filter_cfg_chain_c;
- __le32 filter_cfg_chain_d;
+ __le32 filter_cfg_chains[4];
} __packed; /* PHY_SPECIFIC_CONFIGURATION_API_VER_1*/
/**
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/api/context.h b/drivers/net/wireless/intel/iwlwifi/fw/api/context.h
index 105ba7170c3f..1fa5678c1cd6 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/api/context.h
+++ b/drivers/net/wireless/intel/iwlwifi/fw/api/context.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/*
- * Copyright (C) 2012-2014 Intel Corporation
+ * Copyright (C) 2012-2014, 2022 Intel Corporation
* Copyright (C) 2013-2015 Intel Mobile Communications GmbH
* Copyright (C) 2016-2017 Intel Deutschland GmbH
*/
@@ -26,13 +26,18 @@ enum iwl_ctxt_id_and_color {
#define FW_CMD_ID_AND_COLOR(_id, _color) (((_id) << FW_CTXT_ID_POS) |\
((_color) << FW_CTXT_COLOR_POS))
-/* Possible actions on PHYs, MACs and Bindings */
+/**
+ * enum iwl_ctxt_action - Posssible actions on PHYs, MACs, Bindings and other
+ * @FW_CTXT_ACTION_INVALID: unused, invalid action
+ * @FW_CTXT_ACTION_ADD: add the context
+ * @FW_CTXT_ACTION_MODIFY: modify the context
+ * @FW_CTXT_ACTION_REMOVE: remove the context
+ */
enum iwl_ctxt_action {
- FW_CTXT_ACTION_STUB = 0,
+ FW_CTXT_ACTION_INVALID = 0,
FW_CTXT_ACTION_ADD,
FW_CTXT_ACTION_MODIFY,
FW_CTXT_ACTION_REMOVE,
- FW_CTXT_ACTION_NUM
}; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */
#endif /* __iwl_fw_api_context_h__ */
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/api/d3.h b/drivers/net/wireless/intel/iwlwifi/fw/api/d3.h
index 8a613e150a02..72d461c47323 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/api/d3.h
+++ b/drivers/net/wireless/intel/iwlwifi/fw/api/d3.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/*
- * Copyright (C) 2012-2014, 2018-2022 Intel Corporation
+ * Copyright (C) 2012-2014, 2018-2023 Intel Corporation
* Copyright (C) 2013-2014 Intel Mobile Communications GmbH
* Copyright (C) 2015-2017 Intel Deutschland GmbH
*/
@@ -47,12 +47,14 @@ struct iwl_d3_manager_config {
* @IWL_D3_PROTO_OFFLOAD_NS: NS (Neighbor Solicitation) is enabled
* @IWL_D3_PROTO_IPV4_VALID: IPv4 data is valid
* @IWL_D3_PROTO_IPV6_VALID: IPv6 data is valid
+ * @IWL_D3_PROTO_OFFLOAD_BTM: BTM offload is enabled
*/
enum iwl_proto_offloads {
IWL_D3_PROTO_OFFLOAD_ARP = BIT(0),
IWL_D3_PROTO_OFFLOAD_NS = BIT(1),
IWL_D3_PROTO_IPV4_VALID = BIT(2),
IWL_D3_PROTO_IPV6_VALID = BIT(3),
+ IWL_D3_PROTO_OFFLOAD_BTM = BIT(4),
};
#define IWL_PROTO_OFFLOAD_NUM_IPV6_ADDRS_V1 2
@@ -394,6 +396,7 @@ struct iwl_wowlan_config_cmd {
#define WOWLAN_KEY_MAX_SIZE 32
#define WOWLAN_GTK_KEYS_NUM 2
#define WOWLAN_IGTK_KEYS_NUM 2
+#define WOWLAN_IGTK_MIN_INDEX 4
/*
* WOWLAN_TSC_RSC_PARAMS
@@ -610,6 +613,7 @@ struct iwl_wowlan_gtk_status_v3 {
} __packed; /* WOWLAN_GTK_MATERIAL_VER_3 */
#define IWL_WOWLAN_GTK_IDX_MASK (BIT(0) | BIT(1))
+#define IWL_WOWLAN_IGTK_BIGTK_IDX_MASK (BIT(0))
/**
* struct iwl_wowlan_igtk_status - IGTK status
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/api/datapath.h b/drivers/net/wireless/intel/iwlwifi/fw/api/datapath.h
index 6f59381b9f9a..751b596ea1a5 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/api/datapath.h
+++ b/drivers/net/wireless/intel/iwlwifi/fw/api/datapath.h
@@ -38,7 +38,9 @@ enum iwl_data_path_subcmd_ids {
WNM_80211V_TIMING_MEASUREMENT_CONFIG_CMD = 0x4,
/**
- * @STA_HE_CTXT_CMD: &struct iwl_he_sta_context_cmd
+ * @STA_HE_CTXT_CMD: &struct iwl_he_sta_context_cmd_v1,
+ * &struct iwl_he_sta_context_cmd_v2 or
+ * &struct iwl_he_sta_context_cmd_v3
*/
STA_HE_CTXT_CMD = 0x7,
@@ -447,7 +449,7 @@ struct iwl_sad_properties {
* @phy_id: PHY index
* @rlc: RLC properties, &struct iwl_rlc_properties
* @sad: SAD (single antenna diversity) options, &struct iwl_sad_properties
- * @flags: flags, &enum iwl_rlc_flags
+ * @flags: flags (unused)
* @reserved: reserved
*/
struct iwl_rlc_config_cmd {
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/api/location.h b/drivers/net/wireless/intel/iwlwifi/fw/api/location.h
index 12af94e166ed..b044990c7b87 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/api/location.h
+++ b/drivers/net/wireless/intel/iwlwifi/fw/api/location.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/*
* Copyright (C) 2015-2017 Intel Deutschland GmbH
- * Copyright (C) 2018-2021 Intel Corporation
+ * Copyright (C) 2018-2022 Intel Corporation
*/
#ifndef __iwl_fw_api_location_h__
#define __iwl_fw_api_location_h__
@@ -35,8 +35,11 @@ enum iwl_location_subcmd_ids {
*/
TOF_RANGE_REQ_EXT_CMD = 0x3,
/**
- * @TOF_RESPONDER_CONFIG_CMD: FTM responder configuration,
- * uses &struct iwl_tof_responder_config_cmd
+ * @TOF_RESPONDER_CONFIG_CMD: FTM responder configuration, one of
+ * &struct iwl_tof_responder_config_cmd_v6,
+ * &struct iwl_tof_responder_config_cmd_v7,
+ * &struct iwl_tof_responder_config_cmd_v8 or
+ * &struct iwl_tof_responder_config_cmd_v9
*/
TOF_RESPONDER_CONFIG_CMD = 0x4,
/**
@@ -69,8 +72,11 @@ enum iwl_location_subcmd_ids {
*/
TOF_MCSI_DEBUG_NOTIF = 0xFE,
/**
- * @TOF_RANGE_RESPONSE_NOTIF: ranging response, using
- * &struct iwl_tof_range_rsp_ntfy
+ * @TOF_RANGE_RESPONSE_NOTIF: ranging response, using one of
+ * &struct iwl_tof_range_rsp_ntfy_v5,
+ * &struct iwl_tof_range_rsp_ntfy_v6,
+ * &struct iwl_tof_range_rsp_ntfy_v7 or
+ * &struct iwl_tof_range_rsp_ntfy_v8
*/
TOF_RANGE_RESPONSE_NOTIF = 0xFF,
};
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/api/mac-cfg.h b/drivers/net/wireless/intel/iwlwifi/fw/api/mac-cfg.h
index 74f2efbad34e..184db5a6f06f 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/api/mac-cfg.h
+++ b/drivers/net/wireless/intel/iwlwifi/fw/api/mac-cfg.h
@@ -140,40 +140,60 @@ struct iwl_missed_vap_notif {
*
* @id_and_color: ID and color of the MAC
*/
-struct iwl_channel_switch_start_notif {
+struct iwl_channel_switch_start_notif_v1 {
__le32 id_and_color;
} __packed; /* CHANNEL_SWITCH_START_NTFY_API_S_VER_1 */
+/**
+ * struct iwl_channel_switch_start_notif - Channel switch start notification
+ *
+ * @link_id: FW link id
+ */
+struct iwl_channel_switch_start_notif {
+ __le32 link_id;
+} __packed; /* CHANNEL_SWITCH_START_NTFY_API_S_VER_3 */
+
#define CS_ERR_COUNT_ERROR BIT(0)
#define CS_ERR_LONG_DELAY_AFTER_CS BIT(1)
#define CS_ERR_LONG_TX_BLOCK BIT(2)
#define CS_ERR_TX_BLOCK_TIMER_EXPIRED BIT(3)
/**
- * struct iwl_channel_switch_error_notif - Channel switch error notification
+ * struct iwl_channel_switch_error_notif_v1 - Channel switch error notification
*
* @mac_id: the mac for which the ucode sends the notification for
* @csa_err_mask: mask of channel switch error that can occur
*/
-struct iwl_channel_switch_error_notif {
+struct iwl_channel_switch_error_notif_v1 {
__le32 mac_id;
__le32 csa_err_mask;
} __packed; /* CHANNEL_SWITCH_ERROR_NTFY_API_S_VER_1 */
/**
+ * struct iwl_channel_switch_error_notif - Channel switch error notification
+ *
+ * @link_id: FW link id
+ * @csa_err_mask: mask of channel switch error that can occur
+ */
+struct iwl_channel_switch_error_notif {
+ __le32 link_id;
+ __le32 csa_err_mask;
+} __packed; /* CHANNEL_SWITCH_ERROR_NTFY_API_S_VER_2 */
+
+/**
* struct iwl_cancel_channel_switch_cmd - Cancel Channel Switch command
*
- * @mac_id: the mac that should cancel the channel switch
+ * @id: the id of the link or mac that should cancel the channel switch
*/
struct iwl_cancel_channel_switch_cmd {
- __le32 mac_id;
+ __le32 id;
} __packed; /* MAC_CANCEL_CHANNEL_SWITCH_S_VER_1 */
/**
* struct iwl_chan_switch_te_cmd - Channel Switch Time Event command
*
* @mac_id: MAC ID for channel switch
- * @action: action to perform, one of FW_CTXT_ACTION_*
+ * @action: action to perform, see &enum iwl_ctxt_action
* @tsf: beacon tsf
* @cs_count: channel switch count from CSA/eCSA IE
* @cs_delayed_bcn_count: if set to N (!= 0) GO/AP can delay N beacon intervals
@@ -211,17 +231,30 @@ struct iwl_mac_low_latency_cmd {
* struct iwl_mac_client_data - configuration data for client MAC context
*
* @is_assoc: 1 for associated state, 0 otherwise
+ * @esr_transition_timeout: the timeout required by the AP for the
+ * eSR transition.
+ * Available only from version 2 of the command.
+ * This values comes from the EMLSR transition delay in the EML
+ * Capabilities subfield.
+ * @medium_sync_delay: the value as it appeasr in P802.11be_D2.2 Figure 9-1002j.
* @assoc_id: unique ID assigned by the AP during association
+ * @reserved1: alignment
* @data_policy: see &enum iwl_mac_data_policy
+ * @reserved2: alignment
* @ctwin: client traffic window in TU (period after TBTT when GO is present).
* 0 indicates that there is no CT window.
*/
struct iwl_mac_client_data {
- __le32 is_assoc;
- __le32 assoc_id;
- __le32 data_policy;
+ u8 is_assoc;
+ u8 esr_transition_timeout;
+ __le16 medium_sync_delay;
+
+ __le16 assoc_id;
+ __le16 reserved1;
+ __le16 data_policy;
+ __le16 reserved2;
__le32 ctwin;
-} __packed; /* MAC_CONTEXT_CONFIG_CLIENT_DATA_API_S_VER_1 */
+} __packed; /* MAC_CONTEXT_CONFIG_CLIENT_DATA_API_S_VER_2 */
/**
* struct iwl_mac_p2p_dev_data - configuration data for P2P device MAC context
@@ -263,7 +296,7 @@ enum iwl_mac_config_filter_flags {
* ( MAC_CONTEXT_CONFIG_CMD = 0x8 )
*
* @id_and_color: ID and color of the MAC
- * @action: action to perform, one of FW_CTXT_ACTION_*
+ * @action: action to perform, see &enum iwl_ctxt_action
* @mac_type: one of &enum iwl_mac_types
* @local_mld_addr: mld address
* @reserved_for_local_mld_addr: reserved
@@ -292,12 +325,12 @@ struct iwl_mac_config_cmd {
__le16 he_ap_support;
__le32 eht_support;
__le32 nic_not_ack_enabled;
- /* MAC_CONTEXT_CONFIG_SPECIFIC_DATA_API_U_VER_1 */
+ /* MAC_CONTEXT_CONFIG_SPECIFIC_DATA_API_U_VER_2 */
union {
struct iwl_mac_client_data client;
struct iwl_mac_p2p_dev_data p2p_dev;
};
-} __packed; /* MAC_CONTEXT_CONFIG_CMD_API_S_VER_1 */
+} __packed; /* MAC_CONTEXT_CONFIG_CMD_API_S_VER_2 */
/**
* enum iwl_link_ctx_modify_flags - indicate to the fw what fields are being
@@ -390,7 +423,7 @@ enum iwl_link_ctx_flags {
* in MLD API
* ( LINK_CONFIG_CMD =0x9 )
*
- * @action: action to perform, one of FW_CTXT_ACTION_*
+ * @action: action to perform, see &enum iwl_ctxt_action
* @link_id: the id of the link that this cmd configures
* @mac_id: interface ID. Relevant only if action is FW_CTXT_ACTION_ADD
* @phy_id: PHY index. Can be changed only if the link was inactive
@@ -430,6 +463,7 @@ enum iwl_link_ctx_flags {
* @reserved_for_ref_bssid_addr: reserved
* @bssid_index: index of the associated VAP
* @bss_color: 11ax AP ID that is used in the HE SIG-A to mark inter BSS frame
+ * @spec_link_id: link_id as the AP knows it
* @reserved: alignment
* @ibss_bssid_addr: bssid for ibss
* @reserved_for_ibss_bssid_addr: reserved
@@ -469,7 +503,8 @@ struct iwl_link_config_cmd {
__le16 reserved_for_ref_bssid_addr;
u8 bssid_index;
u8 bss_color;
- u8 reserved[2];
+ u8 spec_link_id;
+ u8 reserved;
u8 ibss_bssid_addr[6];
__le16 reserved_for_ibss_bssid_addr;
__le32 reserved1[8];
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/api/mac.h b/drivers/net/wireless/intel/iwlwifi/fw/api/mac.h
index e3eda251c728..55882190251c 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/api/mac.h
+++ b/drivers/net/wireless/intel/iwlwifi/fw/api/mac.h
@@ -295,7 +295,7 @@ struct iwl_ac_qos {
* struct iwl_mac_ctx_cmd - command structure to configure MAC contexts
* ( MAC_CONTEXT_CMD = 0x28 )
* @id_and_color: ID and color of the MAC
- * @action: action to perform, one of FW_CTXT_ACTION_*
+ * @action: action to perform, see &enum iwl_ctxt_action
* @mac_type: one of &enum iwl_mac_types
* @tsf_id: TSF HW timer, one of &enum iwl_tsf_id
* @node_addr: MAC address
@@ -353,7 +353,7 @@ struct iwl_nonqos_seq_query_cmd {
} __packed; /* NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */
/**
- * struct iwl_missed_beacons_notif - information on missed beacons
+ * struct iwl_missed_beacons_notif_ver_3 - information on missed beacons
* ( MISSED_BEACONS_NOTIFICATION = 0xa2 )
* @mac_id: interface ID
* @consec_missed_beacons_since_last_rx: number of consecutive missed
@@ -362,7 +362,7 @@ struct iwl_nonqos_seq_query_cmd {
* @num_expected_beacons: number of expected beacons
* @num_recvd_beacons: number of received beacons
*/
-struct iwl_missed_beacons_notif {
+struct iwl_missed_beacons_notif_ver_3 {
__le32 mac_id;
__le32 consec_missed_beacons_since_last_rx;
__le32 consec_missed_beacons;
@@ -371,6 +371,24 @@ struct iwl_missed_beacons_notif {
} __packed; /* MISSED_BEACON_NTFY_API_S_VER_3 */
/**
+ * struct iwl_missed_beacons_notif - information on missed beacons
+ * ( MISSED_BEACONS_NOTIFICATION = 0xa2 )
+ * @link_id: fw link ID
+ * @consec_missed_beacons_since_last_rx: number of consecutive missed
+ * beacons since last RX.
+ * @consec_missed_beacons: number of consecutive missed beacons
+ * @num_expected_beacons: number of expected beacons
+ * @num_recvd_beacons: number of received beacons
+ */
+struct iwl_missed_beacons_notif {
+ __le32 link_id;
+ __le32 consec_missed_beacons_since_last_rx;
+ __le32 consec_missed_beacons;
+ __le32 num_expected_beacons;
+ __le32 num_recvd_beacons;
+} __packed; /* MISSED_BEACON_NTFY_API_S_VER_4 */
+
+/**
* struct iwl_he_backoff_conf - used for backoff configuration
* Per each trigger-based AC, (set by MU EDCA Parameter set info-element)
* used for backoff configuration of TXF5..TXF8 trigger based.
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/api/nvm-reg.h b/drivers/net/wireless/intel/iwlwifi/fw/api/nvm-reg.h
index 91bfde6d5367..28bfabb399b2 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/api/nvm-reg.h
+++ b/drivers/net/wireless/intel/iwlwifi/fw/api/nvm-reg.h
@@ -17,7 +17,12 @@ enum iwl_regulatory_and_nvm_subcmd_ids {
NVM_ACCESS_COMPLETE = 0x0,
/**
- * @LARI_CONFIG_CHANGE: &struct iwl_lari_config_change_cmd
+ * @LARI_CONFIG_CHANGE: &struct iwl_lari_config_change_cmd_v1,
+ * &struct iwl_lari_config_change_cmd_v2,
+ * &struct iwl_lari_config_change_cmd_v3,
+ * &struct iwl_lari_config_change_cmd_v4,
+ * &struct iwl_lari_config_change_cmd_v5 or
+ * &struct iwl_lari_config_change_cmd_v6
*/
LARI_CONFIG_CHANGE = 0x1,
@@ -29,12 +34,12 @@ enum iwl_regulatory_and_nvm_subcmd_ids {
NVM_GET_INFO = 0x2,
/**
- * @TAS_CONFIG: &struct iwl_tas_config_cmd
+ * @TAS_CONFIG: &union iwl_tas_config_cmd
*/
TAS_CONFIG = 0x3,
/**
- * @SAR_OFFSET_MAPPING_TABLE_CMD: &iwl_sar_offset_mapping_cmd
+ * @SAR_OFFSET_MAPPING_TABLE_CMD: &struct iwl_sar_offset_mapping_cmd
*/
SAR_OFFSET_MAPPING_TABLE_CMD = 0x4,
@@ -317,7 +322,7 @@ struct iwl_mcc_update_resp_v3 {
} __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_3 */
/**
- * struct iwl_mcc_update_resp - response to MCC_UPDATE_CMD.
+ * struct iwl_mcc_update_resp_v4 - response to MCC_UPDATE_CMD.
* Contains the new channel control profile map, if changed, and the new MCC
* (mobile country code).
* The new MCC may be different than what was requested in MCC_UPDATE_CMD.
@@ -333,7 +338,7 @@ struct iwl_mcc_update_resp_v3 {
* @channels: channel control data map, DWORD for each channel. Only the first
* 16bits are used.
*/
-struct iwl_mcc_update_resp {
+struct iwl_mcc_update_resp_v4 {
__le32 status;
__le16 mcc;
__le16 cap;
@@ -346,6 +351,37 @@ struct iwl_mcc_update_resp {
} __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_4 */
/**
+ * struct iwl_mcc_update_resp_v8 - response to MCC_UPDATE_CMD.
+ * Contains the new channel control profile map, if changed, and the new MCC
+ * (mobile country code).
+ * The new MCC may be different than what was requested in MCC_UPDATE_CMD.
+ * @status: see &enum iwl_mcc_update_status
+ * @mcc: the new applied MCC
+ * @padding: padding for 2 bytes.
+ * @cap: capabilities for all channels which matches the MCC
+ * @time: time elapsed from the MCC test start (in units of 30 seconds)
+ * @geo_info: geographic specific profile information
+ * see &enum iwl_geo_information.
+ * @source_id: the MCC source, see iwl_mcc_source
+ * @reserved: for four bytes alignment.
+ * @n_channels: number of channels in @channels_data.
+ * @channels: channel control data map, DWORD for each channel. Only the first
+ * 16bits are used.
+ */
+struct iwl_mcc_update_resp_v8 {
+ __le32 status;
+ __le16 mcc;
+ u8 padding[2];
+ __le32 cap;
+ __le16 time;
+ __le16 geo_info;
+ u8 source_id;
+ u8 reserved[3];
+ __le32 n_channels;
+ __le32 channels[];
+} __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_8 */
+
+/**
* struct iwl_mcc_chub_notif - chub notifies of mcc change
* (MCC_CHUB_UPDATE_CMD = 0xc9)
* The Chub (Communication Hub, CommsHUB) is a HW component that connects to
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/api/offload.h b/drivers/net/wireless/intel/iwlwifi/fw/api/offload.h
index a0123f81f5d8..898bf351f6e4 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/api/offload.h
+++ b/drivers/net/wireless/intel/iwlwifi/fw/api/offload.h
@@ -28,7 +28,8 @@ enum iwl_prot_offload_subcmd_ids {
D3_END_NOTIFICATION = 0xFE,
/**
- * @STORED_BEACON_NTF: &struct iwl_stored_beacon_notif
+ * @STORED_BEACON_NTF: &struct iwl_stored_beacon_notif_v2 or
+ * &struct iwl_stored_beacon_notif_v3
*/
STORED_BEACON_NTF = 0xFF,
};
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/api/phy-ctxt.h b/drivers/net/wireless/intel/iwlwifi/fw/api/phy-ctxt.h
index 2f7d8558becd..8fe42cff1102 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/api/phy-ctxt.h
+++ b/drivers/net/wireless/intel/iwlwifi/fw/api/phy-ctxt.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/*
- * Copyright (C) 2012-2014, 2018, 2020-2021 Intel Corporation
+ * Copyright (C) 2012-2014, 2018, 2020-2022 Intel Corporation
* Copyright (C) 2013-2015 Intel Mobile Communications GmbH
* Copyright (C) 2016-2017 Intel Deutschland GmbH
*/
@@ -116,7 +116,7 @@ struct iwl_phy_context_cmd_tail {
* struct iwl_phy_context_cmd - config of the PHY context
* ( PHY_CONTEXT_CMD = 0x8 )
* @id_and_color: ID and color of the relevant Binding
- * @action: action to perform, one of FW_CTXT_ACTION_*
+ * @action: action to perform, see &enum iwl_ctxt_action
* @apply_time: 0 means immediate apply and context switch.
* other value means apply new params after X usecs
* @tx_param_color: ???
@@ -138,7 +138,7 @@ struct iwl_phy_context_cmd_v1 {
* struct iwl_phy_context_cmd - config of the PHY context
* ( PHY_CONTEXT_CMD = 0x8 )
* @id_and_color: ID and color of the relevant Binding
- * @action: action to perform, one of FW_CTXT_ACTION_*
+ * @action: action to perform, see &enum iwl_ctxt_action
* @lmac_id: the lmac id the phy context belongs to
* @ci: channel info
* @rxchain_info: ???
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/api/phy.h b/drivers/net/wireless/intel/iwlwifi/fw/api/phy.h
index b1b9c29859c1..5a3f30e5e06d 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/api/phy.h
+++ b/drivers/net/wireless/intel/iwlwifi/fw/api/phy.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/*
- * Copyright (C) 2012-2014, 2019-2021 Intel Corporation
+ * Copyright (C) 2012-2014, 2019-2022 Intel Corporation
* Copyright (C) 2013-2015 Intel Mobile Communications GmbH
* Copyright (C) 2016-2017 Intel Deutschland GmbH
*/
@@ -29,12 +29,16 @@ enum iwl_phy_ops_subcmd_ids {
TEMP_REPORTING_THRESHOLDS_CMD = 0x04,
/**
- * @PER_CHAIN_LIMIT_OFFSET_CMD: &struct iwl_geo_tx_power_profiles_cmd
+ * @PER_CHAIN_LIMIT_OFFSET_CMD: &struct iwl_geo_tx_power_profiles_cmd_v1,
+ * &struct iwl_geo_tx_power_profiles_cmd_v2,
+ * &struct iwl_geo_tx_power_profiles_cmd_v3,
+ * &struct iwl_geo_tx_power_profiles_cmd_v4 or
+ * &struct iwl_geo_tx_power_profiles_cmd_v5
*/
PER_CHAIN_LIMIT_OFFSET_CMD = 0x05,
/**
- * @PER_PLATFORM_ANT_GAIN_CMD: &struct iwl_ppag_table_cmd
+ * @PER_PLATFORM_ANT_GAIN_CMD: &union iwl_ppag_table_cmd
*/
PER_PLATFORM_ANT_GAIN_CMD = 0x07,
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/api/power.h b/drivers/net/wireless/intel/iwlwifi/fw/api/power.h
index f92cac1da764..85d89f559f6c 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/api/power.h
+++ b/drivers/net/wireless/intel/iwlwifi/fw/api/power.h
@@ -537,7 +537,7 @@ union iwl_ppag_table_cmd {
struct iwl_sar_offset_mapping_cmd {
u8 offset_map[MCC_TO_SAR_OFFSET_TABLE_ROW_SIZE]
[MCC_TO_SAR_OFFSET_TABLE_COL_SIZE];
- u16 reserved;
+ __le16 reserved;
} __packed; /*SAR_OFFSET_MAPPING_TABLE_CMD_API_S*/
/**
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/api/rs.h b/drivers/net/wireless/intel/iwlwifi/fw/api/rs.h
index c9a48fc5fac8..a1a272433b09 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/api/rs.h
+++ b/drivers/net/wireless/intel/iwlwifi/fw/api/rs.h
@@ -21,6 +21,7 @@
* @IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK: enable HE Dual Carrier Modulation
* for BPSK (MCS 0) with 2 spatial
* streams
+ * @IWL_TLC_MNG_CFG_FLAGS_EHT_EXTRA_LTF_MSK: enable support for EHT extra LTF
*/
enum iwl_tlc_mng_cfg_flags {
IWL_TLC_MNG_CFG_FLAGS_STBC_MSK = BIT(0),
@@ -28,6 +29,7 @@ enum iwl_tlc_mng_cfg_flags {
IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK = BIT(2),
IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK = BIT(3),
IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK = BIT(4),
+ IWL_TLC_MNG_CFG_FLAGS_EHT_EXTRA_LTF_MSK = BIT(6),
};
/**
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/api/rx.h b/drivers/net/wireless/intel/iwlwifi/fw/api/rx.h
index fdd8b01f09e4..25e2e23dce3d 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/api/rx.h
+++ b/drivers/net/wireless/intel/iwlwifi/fw/api/rx.h
@@ -292,7 +292,7 @@ enum iwl_rx_phy_he_data0 {
/* TSF overload low dword */
enum iwl_rx_phy_eht_data0 {
/* info type: EHT any */
- /* 1 bits reserved */
+ IWL_RX_PHY_DATA0_EHT_VALIDATE = BIT(0),
IWL_RX_PHY_DATA0_EHT_UPLINK = BIT(1),
IWL_RX_PHY_DATA0_EHT_BSS_COLOR_MASK = 0x000000fc,
IWL_RX_PHY_DATA0_ETH_SPATIAL_REUSE_MASK = 0x00000f00,
@@ -367,8 +367,8 @@ enum iwl_rx_phy_eht_data1 {
/* number of EHT-LTF symbols 0 - 1 EHT-LTF, 1 - 2 EHT-LTFs, 2 - 4 EHT-LTFs,
* 3 - 6 EHT-LTFs, 4 - 8 EHT-LTFs */
IWL_RX_PHY_DATA1_EHT_SIG_LTF_NUM = 0x000000e0,
- IWL_RX_PHY_DATA1_EHT_B0 = 0x00000100,
- IWL_RX_PHY_DATA1_EHT_RU_B1_B7_ALLOC = 0x0000fe00,
+ IWL_RX_PHY_DATA1_EHT_RU_ALLOC_B0 = 0x00000100,
+ IWL_RX_PHY_DATA1_EHT_RU_ALLOC_B1_B7 = 0x0000fe00,
};
/* goes into Metadata DW 7 */
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/api/scan.h b/drivers/net/wireless/intel/iwlwifi/fw/api/scan.h
index ec96ba053a5c..93078f8cc08c 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/api/scan.h
+++ b/drivers/net/wireless/intel/iwlwifi/fw/api/scan.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/*
- * Copyright (C) 2012-2014, 2018-2022 Intel Corporation
+ * Copyright (C) 2012-2014, 2018-2023 Intel Corporation
* Copyright (C) 2013-2015 Intel Mobile Communications GmbH
* Copyright (C) 2016-2017 Intel Deutschland GmbH
*/
@@ -727,8 +727,10 @@ enum iwl_umac_scan_general_params_flags2 {
* @iter_interval: interval between two scan iterations on one channel.
*/
struct iwl_scan_channel_cfg_umac {
+#define IWL_CHAN_CFG_FLAGS_BAND_POS 30
__le32 flags;
- /* Both versions are of the same size, so use a union without adjusting
+
+ /* All versions are of the same size, so use a union without adjusting
* the command size later
*/
union {
@@ -746,6 +748,12 @@ struct iwl_scan_channel_cfg_umac {
* SCAN_CHANNEL_CONFIG_API_S_VER_3
* SCAN_CHANNEL_CONFIG_API_S_VER_4
*/
+ struct {
+ u8 channel_num;
+ u8 psd_20;
+ u8 iter_count;
+ u8 iter_interval;
+ } v5; /* SCAN_CHANNEL_CONFIG_API_S_VER_5 */
};
} __packed;
@@ -982,7 +990,7 @@ struct iwl_scan_channel_params_v4 {
SCAN_CHANNEL_PARAMS_API_S_VER_5 */
/**
- * struct iwl_scan_channel_params_v6
+ * struct iwl_scan_channel_params_v7
* @flags: channel flags &enum iwl_scan_channel_flags
* @count: num of channels in scan request
* @n_aps_override: override the number of APs the FW uses to calculate dwell
@@ -992,7 +1000,7 @@ struct iwl_scan_channel_params_v4 {
* @channel_config: array of explicit channel configurations
* for 2.4Ghz and 5.2Ghz bands
*/
-struct iwl_scan_channel_params_v6 {
+struct iwl_scan_channel_params_v7 {
u8 flags;
u8 count;
u8 n_aps_override[2];
@@ -1003,7 +1011,8 @@ struct iwl_scan_channel_params_v6 {
* struct iwl_scan_general_params_v11
* @flags: &enum iwl_umac_scan_general_flags_v2
* @reserved: reserved for future
- * @scan_start_mac_id: report the scan start TSF time according to this mac TSF
+ * @scan_start_mac_or_link_id: report the scan start TSF time according to this
+ * mac (up to verion 11) or link (starting with version 12) TSF
* @active_dwell: dwell time for active scan per LMAC
* @adwell_default_2g: adaptive dwell default number of APs
* for 2.4GHz channel
@@ -1026,7 +1035,7 @@ struct iwl_scan_channel_params_v6 {
struct iwl_scan_general_params_v11 {
__le16 flags;
u8 reserved;
- u8 scan_start_mac_id;
+ u8 scan_start_mac_or_link_id;
u8 active_dwell[SCAN_TWO_LMACS];
u8 adwell_default_2g;
u8 adwell_default_5g;
@@ -1038,7 +1047,7 @@ struct iwl_scan_general_params_v11 {
__le32 scan_priority;
u8 passive_dwell[SCAN_TWO_LMACS];
u8 num_of_fragments[SCAN_TWO_LMACS];
-} __packed; /* SCAN_GENERAL_PARAMS_API_S_VER_11 and *_VER_10 */
+} __packed; /* SCAN_GENERAL_PARAMS_API_S_VER_12, *_VER_11 and *_VER_10 */
/**
* struct iwl_scan_periodic_parms_v1
@@ -1067,18 +1076,18 @@ struct iwl_scan_req_params_v12 {
} __packed; /* SCAN_REQUEST_PARAMS_API_S_VER_12 */
/**
- * struct iwl_scan_req_params_v15
+ * struct iwl_scan_req_params_v16
* @general_params: &struct iwl_scan_general_params_v11
- * @channel_params: &struct iwl_scan_channel_params_v6
+ * @channel_params: &struct iwl_scan_channel_params_v7
* @periodic_params: &struct iwl_scan_periodic_parms_v1
* @probe_params: &struct iwl_scan_probe_params_v4
*/
-struct iwl_scan_req_params_v15 {
+struct iwl_scan_req_params_v17 {
struct iwl_scan_general_params_v11 general_params;
- struct iwl_scan_channel_params_v6 channel_params;
+ struct iwl_scan_channel_params_v7 channel_params;
struct iwl_scan_periodic_parms_v1 periodic_params;
struct iwl_scan_probe_params_v4 probe_params;
-} __packed; /* SCAN_REQUEST_PARAMS_API_S_VER_15 and *_VER_14 */
+} __packed; /* SCAN_REQUEST_PARAMS_API_S_VER_17 - 14 */
/**
* struct iwl_scan_req_umac_v12
@@ -1093,16 +1102,16 @@ struct iwl_scan_req_umac_v12 {
} __packed; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_12 */
/**
- * struct iwl_scan_req_umac_v15
+ * struct iwl_scan_req_umac_v16
* @uid: scan id, &enum iwl_umac_scan_uid_offsets
* @ooc_priority: out of channel priority - &enum iwl_scan_priority
* @scan_params: scan parameters
*/
-struct iwl_scan_req_umac_v15 {
+struct iwl_scan_req_umac_v17 {
__le32 uid;
__le32 ooc_priority;
- struct iwl_scan_req_params_v15 scan_params;
-} __packed; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_15 and *_VER_14 */
+ struct iwl_scan_req_params_v17 scan_params;
+} __packed; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_17 - 14 */
/**
* struct iwl_umac_scan_abort
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/api/time-event.h b/drivers/net/wireless/intel/iwlwifi/fw/api/time-event.h
index 904cd78a9fa0..7cc706731d70 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/api/time-event.h
+++ b/drivers/net/wireless/intel/iwlwifi/fw/api/time-event.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/*
- * Copyright (C) 2012-2014, 2018-2020 Intel Corporation
+ * Copyright (C) 2012-2014, 2018-2020, 2022 Intel Corporation
* Copyright (C) 2013-2015 Intel Mobile Communications GmbH
* Copyright (C) 2016-2017 Intel Deutschland GmbH
*/
@@ -292,7 +292,7 @@ struct iwl_hs20_roc_req_tail {
* ( HOT_SPOT_CMD 0x53 )
*
* @id_and_color: ID and color of the MAC
- * @action: action to perform, one of FW_CTXT_ACTION_*
+ * @action: action to perform, see &enum iwl_ctxt_action
* @event_unique_id: If the action FW_CTXT_ACTION_REMOVE then the
* event_unique_id should be the id of the time event assigned by ucode.
* Otherwise ignore the event_unique_id.
@@ -377,7 +377,8 @@ enum iwl_mvm_session_prot_conf_id {
* struct iwl_mvm_session_prot_cmd - configure a session protection
* @id_and_color: the id and color of the mac for which this session protection
* is sent
- * @action: can be either FW_CTXT_ACTION_ADD or FW_CTXT_ACTION_REMOVE
+ * @action: can be either FW_CTXT_ACTION_ADD or FW_CTXT_ACTION_REMOVE,
+ * see &enum iwl_ctxt_action
* @conf_id: see &enum iwl_mvm_session_prot_conf_id
* @duration_tu: the duration of the whole protection in TUs.
* @repetition_count: not used
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/api/tx.h b/drivers/net/wireless/intel/iwlwifi/fw/api/tx.h
index 97edf5477ba7..842360b1e995 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/api/tx.h
+++ b/drivers/net/wireless/intel/iwlwifi/fw/api/tx.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/*
- * Copyright (C) 2012-2014, 2018-2022 Intel Corporation
+ * Copyright (C) 2012-2014, 2018-2023 Intel Corporation
* Copyright (C) 2016-2017 Intel Deutschland GmbH
*/
#ifndef __iwl_fw_api_tx_h__
@@ -177,17 +177,6 @@ enum iwl_tx_offload_assist_flags_pos {
#define IWL_TX_CMD_OFFLD_MH_MASK 0x1f
#define IWL_TX_CMD_OFFLD_IP_HDR_MASK 0x3f
-enum iwl_tx_offload_assist_bz {
- IWL_TX_CMD_OFFLD_BZ_RESULT_OFFS = 0x000003ff,
- IWL_TX_CMD_OFFLD_BZ_START_OFFS = 0x001ff800,
- IWL_TX_CMD_OFFLD_BZ_MH_LEN = 0x07c00000,
- IWL_TX_CMD_OFFLD_BZ_MH_PAD = 0x08000000,
- IWL_TX_CMD_OFFLD_BZ_AMSDU = 0x10000000,
- IWL_TX_CMD_OFFLD_BZ_ZERO2ONES = 0x20000000,
- IWL_TX_CMD_OFFLD_BZ_ENABLE_CSUM = 0x40000000,
- IWL_TX_CMD_OFFLD_BZ_PARTIAL_CSUM = 0x80000000,
-};
-
/* TODO: complete documentation for try_cnt and btkill_cnt */
/**
* struct iwl_tx_cmd - TX command struct to FW
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/dbg.c b/drivers/net/wireless/intel/iwlwifi/fw/dbg.c
index 55219974b92b..3ab6a68f1e9f 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/dbg.c
+++ b/drivers/net/wireless/intel/iwlwifi/fw/dbg.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
- * Copyright (C) 2005-2014, 2018-2021 Intel Corporation
+ * Copyright (C) 2005-2014, 2018-2023 Intel Corporation
* Copyright (C) 2013-2015 Intel Mobile Communications GmbH
* Copyright (C) 2015-2017 Intel Deutschland GmbH
*/
@@ -1038,7 +1038,7 @@ iwl_dump_ini_prph_mac_iter(struct iwl_fw_runtime *fwrt,
range->range_data_size = reg->dev_addr.size;
for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) {
prph_val = iwl_read_prph(fwrt->trans, addr + i);
- if ((prph_val & ~0xf) == 0xa5a5a5a0)
+ if (iwl_trans_is_hw_error_value(prph_val))
return -EBUSY;
*val++ = cpu_to_le32(prph_val);
}
@@ -1562,7 +1562,7 @@ iwl_dump_ini_dbgi_sram_iter(struct iwl_fw_runtime *fwrt,
prph_data = iwl_read_prph_no_grab(fwrt->trans, (i % 2) ?
DBGI_SRAM_TARGET_ACCESS_RDATA_MSB :
DBGI_SRAM_TARGET_ACCESS_RDATA_LSB);
- if ((prph_data & ~0xf) == 0xa5a5a5a0) {
+ if (iwl_trans_is_hw_error_value(prph_data)) {
iwl_trans_release_nic_access(fwrt->trans);
return -EBUSY;
}
@@ -2034,7 +2034,6 @@ static u32
iwl_dump_ini_imr_get_size(struct iwl_fw_runtime *fwrt,
struct iwl_dump_ini_region_data *reg_data)
{
- u32 size = 0;
u32 ranges = 0;
u32 imr_enable = fwrt->trans->dbg.imr_data.imr_enable;
u32 imr_size = fwrt->trans->dbg.imr_data.imr_size;
@@ -2044,17 +2043,16 @@ iwl_dump_ini_imr_get_size(struct iwl_fw_runtime *fwrt,
IWL_DEBUG_INFO(fwrt,
"WRT: Invalid imr data enable: %d, imr_size: %d, sram_size: %d\n",
imr_enable, imr_size, sram_size);
- return size;
+ return 0;
}
- size = imr_size;
ranges = iwl_dump_ini_imr_ranges(fwrt, reg_data);
- if (!size && !ranges) {
- IWL_ERR(fwrt, "WRT: imr_size :=%d, ranges :=%d\n", size, ranges);
+ if (!ranges) {
+ IWL_ERR(fwrt, "WRT: ranges :=%d\n", ranges);
return 0;
}
- size += sizeof(struct iwl_fw_ini_error_dump) +
+ imr_size += sizeof(struct iwl_fw_ini_error_dump) +
ranges * sizeof(struct iwl_fw_ini_error_dump_range);
- return size;
+ return imr_size;
}
/**
@@ -3156,6 +3154,51 @@ static int iwl_fw_dbg_restart_recording(struct iwl_trans *trans,
return 0;
}
+int iwl_fw_send_timestamp_marker_cmd(struct iwl_fw_runtime *fwrt)
+{
+ struct iwl_mvm_marker marker = {
+ .dw_len = sizeof(struct iwl_mvm_marker) / 4,
+ .marker_id = MARKER_ID_SYNC_CLOCK,
+ };
+ struct iwl_host_cmd hcmd = {
+ .flags = CMD_ASYNC,
+ .id = WIDE_ID(LONG_GROUP, MARKER_CMD),
+ .dataflags = {},
+ };
+ struct iwl_mvm_marker_rsp *resp;
+ int cmd_ver = iwl_fw_lookup_cmd_ver(fwrt->fw,
+ WIDE_ID(LONG_GROUP, MARKER_CMD),
+ IWL_FW_CMD_VER_UNKNOWN);
+ int ret;
+
+ if (cmd_ver == 1) {
+ /* the real timestamp is taken from the ftrace clock
+ * this is for finding the match between fw and kernel logs
+ */
+ marker.timestamp = cpu_to_le64(fwrt->timestamp.seq++);
+ } else if (cmd_ver == 2) {
+ marker.timestamp = cpu_to_le64(ktime_get_boottime_ns());
+ } else {
+ IWL_DEBUG_INFO(fwrt,
+ "Invalid version of Marker CMD. Ver = %d\n",
+ cmd_ver);
+ return -EINVAL;
+ }
+
+ hcmd.data[0] = &marker;
+ hcmd.len[0] = sizeof(marker);
+
+ ret = iwl_trans_send_cmd(fwrt->trans, &hcmd);
+
+ if (cmd_ver > 1 && hcmd.resp_pkt) {
+ resp = (void *)hcmd.resp_pkt->data;
+ IWL_DEBUG_INFO(fwrt, "FW GP2 time: %u\n",
+ le32_to_cpu(resp->gp2));
+ }
+
+ return ret;
+}
+
void iwl_fw_dbg_stop_restart_recording(struct iwl_fw_runtime *fwrt,
struct iwl_fw_dbg_params *params,
bool stop)
@@ -3166,12 +3209,15 @@ void iwl_fw_dbg_stop_restart_recording(struct iwl_fw_runtime *fwrt,
return;
if (fw_has_capa(&fwrt->fw->ucode_capa,
- IWL_UCODE_TLV_CAPA_DBG_SUSPEND_RESUME_CMD_SUPP))
+ IWL_UCODE_TLV_CAPA_DBG_SUSPEND_RESUME_CMD_SUPP)) {
+ if (stop)
+ iwl_fw_send_timestamp_marker_cmd(fwrt);
ret = iwl_fw_dbg_suspend_resume_hcmd(fwrt->trans, stop);
- else if (stop)
+ } else if (stop) {
iwl_fw_dbg_stop_recording(fwrt->trans, params);
- else
+ } else {
ret = iwl_fw_dbg_restart_recording(fwrt->trans, params);
+ }
#ifdef CONFIG_IWLWIFI_DEBUGFS
if (!ret) {
if (stop)
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/dbg.h b/drivers/net/wireless/intel/iwlwifi/fw/dbg.h
index be7806407de8..4227fbd2b977 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/dbg.h
+++ b/drivers/net/wireless/intel/iwlwifi/fw/dbg.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/*
- * Copyright (C) 2005-2014, 2018-2019, 2021-2022 Intel Corporation
+ * Copyright (C) 2005-2014, 2018-2019, 2021-2023 Intel Corporation
* Copyright (C) 2013-2015 Intel Mobile Communications GmbH
* Copyright (C) 2015-2017 Intel Deutschland GmbH
*/
@@ -227,6 +227,8 @@ static inline void iwl_fw_flush_dumps(struct iwl_fw_runtime *fwrt)
flush_delayed_work(&fwrt->dump.wks[i].wk);
}
+int iwl_fw_send_timestamp_marker_cmd(struct iwl_fw_runtime *fwrt);
+
#ifdef CONFIG_IWLWIFI_DEBUGFS
static inline void iwl_fw_cancel_timestamp(struct iwl_fw_runtime *fwrt)
{
@@ -327,4 +329,18 @@ void iwl_fwrt_dump_error_logs(struct iwl_fw_runtime *fwrt);
void iwl_send_dbg_dump_complete_cmd(struct iwl_fw_runtime *fwrt,
u32 timepoint,
u32 timepoint_data);
+
+#define IWL_FW_CHECK_FAILED(_obj, _fmt, ...) \
+ IWL_ERR_LIMIT(_obj, _fmt, __VA_ARGS__)
+
+#define IWL_FW_CHECK(_obj, _cond, _fmt, ...) \
+ ({ \
+ bool __cond = (_cond); \
+ \
+ if (unlikely(__cond)) \
+ IWL_FW_CHECK_FAILED(_obj, _fmt, __VA_ARGS__); \
+ \
+ unlikely(__cond); \
+ })
+
#endif /* __iwl_fw_dbg_h__ */
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/debugfs.c b/drivers/net/wireless/intel/iwlwifi/fw/debugfs.c
index 607e07ed2477..3cdbc6ac7ae5 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/debugfs.c
+++ b/drivers/net/wireless/intel/iwlwifi/fw/debugfs.c
@@ -123,28 +123,6 @@ static const struct file_operations iwl_dbgfs_##name##_ops = { \
#define FWRT_DEBUGFS_ADD_FILE(name, parent, mode) \
FWRT_DEBUGFS_ADD_FILE_ALIAS(#name, name, parent, mode)
-static int iwl_fw_send_timestamp_marker_cmd(struct iwl_fw_runtime *fwrt)
-{
- struct iwl_mvm_marker marker = {
- .dw_len = sizeof(struct iwl_mvm_marker) / 4,
- .marker_id = MARKER_ID_SYNC_CLOCK,
-
- /* the real timestamp is taken from the ftrace clock
- * this is for finding the match between fw and kernel logs
- */
- .timestamp = cpu_to_le64(fwrt->timestamp.seq++),
- };
-
- struct iwl_host_cmd hcmd = {
- .id = MARKER_CMD,
- .flags = CMD_ASYNC,
- .data[0] = &marker,
- .len[0] = sizeof(marker),
- };
-
- return iwl_trans_send_cmd(fwrt->trans, &hcmd);
-}
-
static int iwl_dbgfs_enabled_severities_write(struct iwl_fw_runtime *fwrt,
char *buf, size_t count)
{
@@ -354,9 +332,18 @@ static int iwl_dbgfs_fw_info_seq_show(struct seq_file *seq, void *v)
const struct iwl_fw *fw = priv->fwrt->fw;
const struct iwl_fw_cmd_version *ver;
u32 cmd_id;
-
- if (!state->pos)
+ int has_capa;
+
+ if (!state->pos) {
+ seq_puts(seq, "fw_capa:\n");
+ has_capa = fw_has_capa(&fw->ucode_capa,
+ IWL_UCODE_TLV_CAPA_PPAG_CHINA_BIOS_SUPPORT) ? 1 : 0;
+ seq_printf(seq,
+ " %d: %d\n",
+ IWL_UCODE_TLV_CAPA_PPAG_CHINA_BIOS_SUPPORT,
+ has_capa);
seq_puts(seq, "fw_api_ver:\n");
+ }
ver = &fw->ucode_capa.cmd_versions[state->pos];
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/dump.c b/drivers/net/wireless/intel/iwlwifi/fw/dump.c
index f86f7b4baa18..5876f917e536 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/dump.c
+++ b/drivers/net/wireless/intel/iwlwifi/fw/dump.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
- * Copyright (C) 2012-2014, 2018-2022 Intel Corporation
+ * Copyright (C) 2012-2014, 2018-2023 Intel Corporation
* Copyright (C) 2013-2014 Intel Mobile Communications GmbH
* Copyright (C) 2015-2017 Intel Deutschland GmbH
*/
@@ -194,7 +194,7 @@ static void iwl_fwrt_dump_lmac_error_log(struct iwl_fw_runtime *fwrt, u8 lmac_nu
/* check if there is a HW error */
val = iwl_trans_read_mem32(trans, base);
- if (((val & ~0xf) == 0xa5a5a5a0) || ((val & ~0xf) == 0x5a5a5a50)) {
+ if (iwl_trans_is_hw_error_value(val)) {
int err;
IWL_ERR(trans, "HW error, resetting before reading\n");
@@ -467,6 +467,10 @@ static void iwl_fwrt_dump_fseq_regs(struct iwl_fw_runtime *fwrt)
FSEQ_REG(CNVR_AUX_MISC_CHIP),
FSEQ_REG(CNVR_SCU_SD_REGS_SD_REG_DIG_DCDC_VTRIM),
FSEQ_REG(CNVR_SCU_SD_REGS_SD_REG_ACTIVE_VDIG_MIRROR),
+ FSEQ_REG(FSEQ_PREV_CNVIO_INIT_VERSION),
+ FSEQ_REG(FSEQ_WIFI_FSEQ_VERSION),
+ FSEQ_REG(FSEQ_BT_FSEQ_VERSION),
+ FSEQ_REG(FSEQ_CLASS_TP_VERSION),
};
if (!iwl_trans_grab_nic_access(trans))
@@ -507,11 +511,16 @@ void iwl_fwrt_dump_error_logs(struct iwl_fw_runtime *fwrt)
iwl_fwrt_dump_fseq_regs(fwrt);
if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_22000) {
pc_data = fwrt->trans->dbg.pc_data;
+
+ if (!iwl_trans_grab_nic_access(fwrt->trans))
+ return;
for (count = 0; count < fwrt->trans->dbg.num_pc;
count++, pc_data++)
IWL_ERR(fwrt, "%s: 0x%x\n",
pc_data->pc_name,
- pc_data->pc_address);
+ iwl_read_prph_no_grab(fwrt->trans,
+ pc_data->pc_address));
+ iwl_trans_release_nic_access(fwrt->trans);
}
if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/file.h b/drivers/net/wireless/intel/iwlwifi/fw/file.h
index cddf09d6be1c..b36e9613a52c 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/file.h
+++ b/drivers/net/wireless/intel/iwlwifi/fw/file.h
@@ -323,6 +323,7 @@ typedef unsigned int __bitwise iwl_ucode_tlv_capa_t;
* is supported.
* @IWL_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC
* @IWL_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan (no longer used)
+ * @IWL_UCODE_TLV_CAPA_FRAGMENTED_PNVM_IMG: supports fragmented PNVM image
* @IWL_UCODE_TLV_CAPA_SOC_LATENCY_SUPPORT: the firmware supports setting
* stabilization latency for SoCs.
* @IWL_UCODE_TLV_CAPA_STA_PM_NOTIF: firmware will send STA PM notification
@@ -398,6 +399,7 @@ enum iwl_ucode_tlv_capa {
IWL_UCODE_TLV_CAPA_GSCAN_SUPPORT = (__force iwl_ucode_tlv_capa_t)31,
/* set 1 */
+ IWL_UCODE_TLV_CAPA_FRAGMENTED_PNVM_IMG = (__force iwl_ucode_tlv_capa_t)32,
IWL_UCODE_TLV_CAPA_SOC_LATENCY_SUPPORT = (__force iwl_ucode_tlv_capa_t)37,
IWL_UCODE_TLV_CAPA_STA_PM_NOTIF = (__force iwl_ucode_tlv_capa_t)38,
IWL_UCODE_TLV_CAPA_BINDING_CDB_SUPPORT = (__force iwl_ucode_tlv_capa_t)39,
@@ -462,6 +464,10 @@ enum iwl_ucode_tlv_capa {
IWL_UCODE_TLV_CAPA_BIGTK_TX_SUPPORT = (__force iwl_ucode_tlv_capa_t)109,
IWL_UCODE_TLV_CAPA_MLD_API_SUPPORT = (__force iwl_ucode_tlv_capa_t)110,
IWL_UCODE_TLV_CAPA_SCAN_DONT_TOGGLE_ANT = (__force iwl_ucode_tlv_capa_t)111,
+ IWL_UCODE_TLV_CAPA_PPAG_CHINA_BIOS_SUPPORT = (__force iwl_ucode_tlv_capa_t)112,
+ IWL_UCODE_TLV_CAPA_OFFLOAD_BTM_SUPPORT = (__force iwl_ucode_tlv_capa_t)113,
+ IWL_UCODE_TLV_CAPA_STA_EXP_MFP_SUPPORT = (__force iwl_ucode_tlv_capa_t)114,
+ IWL_UCODE_TLV_CAPA_SNIFF_VALIDATE_SUPPORT = (__force iwl_ucode_tlv_capa_t)116,
#ifdef __CHECKER__
/* sparse says it cannot increment the previous enum member */
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/pnvm.c b/drivers/net/wireless/intel/iwlwifi/fw/pnvm.c
index c6f2672fdc73..650e4bde9c17 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/pnvm.c
+++ b/drivers/net/wireless/intel/iwlwifi/fw/pnvm.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
- * Copyright(c) 2020-2022 Intel Corporation
+ * Copyright(c) 2020-2023 Intel Corporation
*/
#include "iwl-drv.h"
@@ -31,18 +31,18 @@ static bool iwl_pnvm_complete_fn(struct iwl_notif_wait_data *notif_wait,
}
static int iwl_pnvm_handle_section(struct iwl_trans *trans, const u8 *data,
- size_t len)
+ size_t len,
+ struct iwl_pnvm_image *pnvm_data)
{
const struct iwl_ucode_tlv *tlv;
u32 sha1 = 0;
u16 mac_type = 0, rf_id = 0;
- u8 *pnvm_data = NULL, *tmp;
bool hw_match = false;
- u32 size = 0;
- int ret;
IWL_DEBUG_FW(trans, "Handling PNVM section\n");
+ memset(pnvm_data, 0, sizeof(*pnvm_data));
+
while (len >= sizeof(*tlv)) {
u32 tlv_len, tlv_type;
@@ -55,8 +55,7 @@ static int iwl_pnvm_handle_section(struct iwl_trans *trans, const u8 *data,
if (len < tlv_len) {
IWL_ERR(trans, "invalid TLV len: %zd/%u\n",
len, tlv_len);
- ret = -EINVAL;
- goto out;
+ return -EINVAL;
}
data += sizeof(*tlv);
@@ -75,6 +74,7 @@ static int iwl_pnvm_handle_section(struct iwl_trans *trans, const u8 *data,
IWL_DEBUG_FW(trans,
"Got IWL_UCODE_TLV_PNVM_VERSION %0x\n",
sha1);
+ pnvm_data->version = sha1;
break;
case IWL_UCODE_TLV_HW_TYPE:
if (tlv_len < 2 * sizeof(__le16)) {
@@ -112,26 +112,26 @@ static int iwl_pnvm_handle_section(struct iwl_trans *trans, const u8 *data,
break;
}
- IWL_DEBUG_FW(trans, "Adding data (size %d)\n",
- data_len);
-
- tmp = krealloc(pnvm_data, size + data_len, GFP_KERNEL);
- if (!tmp) {
+ if (pnvm_data->n_chunks == IPC_DRAM_MAP_ENTRY_NUM_MAX) {
IWL_DEBUG_FW(trans,
- "Couldn't allocate (more) pnvm_data\n");
-
- ret = -ENOMEM;
- goto out;
+ "too many payloads to allocate in DRAM.\n");
+ return -EINVAL;
}
- pnvm_data = tmp;
-
- memcpy(pnvm_data + size, section->data, data_len);
+ IWL_DEBUG_FW(trans, "Adding data (size %d)\n",
+ data_len);
- size += data_len;
+ pnvm_data->chunks[pnvm_data->n_chunks].data = section->data;
+ pnvm_data->chunks[pnvm_data->n_chunks].len = data_len;
+ pnvm_data->n_chunks++;
break;
}
+ case IWL_UCODE_TLV_MEM_DESC:
+ if (iwl_uefi_handle_tlv_mem_desc(trans, data, tlv_len,
+ pnvm_data))
+ return -EINVAL;
+ break;
case IWL_UCODE_TLV_PNVM_SKU:
IWL_DEBUG_FW(trans,
"New PNVM section started, stop parsing.\n");
@@ -152,26 +152,20 @@ done:
"HW mismatch, skipping PNVM section (need mac_type 0x%x rf_id 0x%x)\n",
CSR_HW_REV_TYPE(trans->hw_rev),
CSR_HW_RFID_TYPE(trans->hw_rf_id));
- ret = -ENOENT;
- goto out;
+ return -ENOENT;
}
- if (!size) {
+ if (!pnvm_data->n_chunks) {
IWL_DEBUG_FW(trans, "Empty PNVM, skipping.\n");
- ret = -ENOENT;
- goto out;
+ return -ENOENT;
}
- IWL_INFO(trans, "loaded PNVM version %08x\n", sha1);
-
- ret = iwl_trans_set_pnvm(trans, pnvm_data, size);
-out:
- kfree(pnvm_data);
- return ret;
+ return 0;
}
static int iwl_pnvm_parse(struct iwl_trans *trans, const u8 *data,
- size_t len)
+ size_t len,
+ struct iwl_pnvm_image *pnvm_data)
{
const struct iwl_ucode_tlv *tlv;
@@ -212,7 +206,8 @@ static int iwl_pnvm_parse(struct iwl_trans *trans, const u8 *data,
trans->sku_id[2] == le32_to_cpu(sku_id->data[2])) {
int ret;
- ret = iwl_pnvm_handle_section(trans, data, len);
+ ret = iwl_pnvm_handle_section(trans, data, len,
+ pnvm_data);
if (!ret)
return 0;
} else {
@@ -255,89 +250,136 @@ static int iwl_pnvm_get_from_fs(struct iwl_trans *trans, u8 **data, size_t *len)
return 0;
}
-int iwl_pnvm_load(struct iwl_trans *trans,
- struct iwl_notif_wait_data *notif_wait)
+static u8 *iwl_get_pnvm_image(struct iwl_trans *trans_p, size_t *len)
{
- u8 *data;
- size_t len;
struct pnvm_sku_package *package;
- struct iwl_notification_wait pnvm_wait;
- static const u16 ntf_cmds[] = { WIDE_ID(REGULATORY_AND_NVM_GROUP,
- PNVM_INIT_COMPLETE_NTFY) };
- int ret;
-
- /* if the SKU_ID is empty, there's nothing to do */
- if (!trans->sku_id[0] && !trans->sku_id[1] && !trans->sku_id[2])
- return 0;
-
- /*
- * If we already loaded (or tried to load) it before, we just
- * need to set it again.
- */
- if (trans->pnvm_loaded) {
- ret = iwl_trans_set_pnvm(trans, NULL, 0);
- if (ret)
- return ret;
- goto skip_parse;
- }
+ u8 *image = NULL;
/* First attempt to get the PNVM from BIOS */
- package = iwl_uefi_get_pnvm(trans, &len);
+ package = iwl_uefi_get_pnvm(trans_p, len);
if (!IS_ERR_OR_NULL(package)) {
- if (len >= sizeof(*package)) {
+ if (*len >= sizeof(*package)) {
/* we need only the data */
- len -= sizeof(*package);
- data = kmemdup(package->data, len, GFP_KERNEL);
- } else {
- data = NULL;
+ *len -= sizeof(*package);
+ image = kmemdup(package->data, *len, GFP_KERNEL);
}
-
/* free package regardless of whether kmemdup succeeded */
kfree(package);
-
- if (data)
- goto parse;
+ if (image)
+ return image;
}
/* If it's not available, try from the filesystem */
- ret = iwl_pnvm_get_from_fs(trans, &data, &len);
+ if (iwl_pnvm_get_from_fs(trans_p, &image, len))
+ return NULL;
+ return image;
+}
+
+static void iwl_pnvm_load_pnvm_to_trans(struct iwl_trans *trans,
+ const struct iwl_ucode_capabilities *capa)
+{
+ struct iwl_pnvm_image *pnvm_data = NULL;
+ u8 *data = NULL;
+ size_t length;
+ int ret;
+
+ /* failed to get/parse the image in the past, no use trying again */
+ if (trans->fail_to_parse_pnvm_image)
+ return;
+
+ if (trans->pnvm_loaded)
+ goto set;
+
+ data = iwl_get_pnvm_image(trans, &length);
+ if (!data) {
+ trans->fail_to_parse_pnvm_image = true;
+ return;
+ }
+
+ pnvm_data = kzalloc(sizeof(*pnvm_data), GFP_KERNEL);
+ if (!pnvm_data)
+ goto free;
+
+ ret = iwl_pnvm_parse(trans, data, length, pnvm_data);
if (ret) {
- /*
- * Pretend we've loaded it - at least we've tried and
- * couldn't load it at all, so there's no point in
- * trying again over and over.
- */
- trans->pnvm_loaded = true;
-
- goto skip_parse;
+ trans->fail_to_parse_pnvm_image = true;
+ goto free;
}
-parse:
- iwl_pnvm_parse(trans, data, len);
+ ret = iwl_trans_load_pnvm(trans, pnvm_data, capa);
+ if (ret)
+ goto free;
+ IWL_INFO(trans, "loaded PNVM version %08x\n", pnvm_data->version);
+set:
+ iwl_trans_set_pnvm(trans, capa);
+free:
kfree(data);
+ kfree(pnvm_data);
+}
-skip_parse:
- /* now try to get the reduce power table, if not loaded yet */
- if (!trans->reduce_power_loaded) {
- data = iwl_uefi_get_reduced_power(trans, &len);
- if (IS_ERR_OR_NULL(data)) {
- /*
- * Pretend we've loaded it - at least we've tried and
- * couldn't load it at all, so there's no point in
- * trying again over and over.
- */
- trans->reduce_power_loaded = true;
- } else {
- ret = iwl_trans_set_reduce_power(trans, data, len);
- if (ret)
- IWL_DEBUG_FW(trans,
- "Failed to set reduce power table %d\n",
- ret);
- kfree(data);
- }
+static void
+iwl_pnvm_load_reduce_power_to_trans(struct iwl_trans *trans,
+ const struct iwl_ucode_capabilities *capa)
+{
+ struct iwl_pnvm_image *pnvm_data = NULL;
+ u8 *data = NULL;
+ size_t length;
+ int ret;
+
+ if (trans->failed_to_load_reduce_power_image)
+ return;
+
+ if (trans->reduce_power_loaded)
+ goto set;
+
+ data = iwl_uefi_get_reduced_power(trans, &length);
+ if (IS_ERR(data)) {
+ trans->failed_to_load_reduce_power_image = true;
+ return;
}
+ pnvm_data = kzalloc(sizeof(*pnvm_data), GFP_KERNEL);
+ if (!pnvm_data)
+ goto free;
+
+ ret = iwl_uefi_reduce_power_parse(trans, data, length, pnvm_data);
+ if (ret) {
+ trans->failed_to_load_reduce_power_image = true;
+ goto free;
+ }
+
+ ret = iwl_trans_load_reduce_power(trans, pnvm_data, capa);
+ if (ret) {
+ IWL_DEBUG_FW(trans,
+ "Failed to load reduce power table %d\n",
+ ret);
+ trans->failed_to_load_reduce_power_image = true;
+ goto free;
+ }
+
+set:
+ iwl_trans_set_reduce_power(trans, capa);
+free:
+ kfree(data);
+ kfree(pnvm_data);
+}
+
+int iwl_pnvm_load(struct iwl_trans *trans,
+ struct iwl_notif_wait_data *notif_wait,
+ const struct iwl_ucode_capabilities *capa)
+{
+ struct iwl_notification_wait pnvm_wait;
+ static const u16 ntf_cmds[] = { WIDE_ID(REGULATORY_AND_NVM_GROUP,
+ PNVM_INIT_COMPLETE_NTFY) };
+
+ /* if the SKU_ID is empty, there's nothing to do */
+ if (!trans->sku_id[0] && !trans->sku_id[1] && !trans->sku_id[2])
+ return 0;
+
+ iwl_pnvm_load_pnvm_to_trans(trans, capa);
+ iwl_pnvm_load_reduce_power_to_trans(trans, capa);
+
iwl_init_notification_wait(notif_wait, &pnvm_wait,
ntf_cmds, ARRAY_SIZE(ntf_cmds),
iwl_pnvm_complete_fn, trans);
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/pnvm.h b/drivers/net/wireless/intel/iwlwifi/fw/pnvm.h
index 203c367dd4de..1bac3466154c 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/pnvm.h
+++ b/drivers/net/wireless/intel/iwlwifi/fw/pnvm.h
@@ -1,13 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
-/******************************************************************************
- *
- * Copyright(c) 2020-2021 Intel Corporation
- *
- *****************************************************************************/
-
+/*
+ * Copyright(c) 2020-2023 Intel Corporation
+ */
#ifndef __IWL_PNVM_H__
#define __IWL_PNVM_H__
+#include "iwl-drv.h"
#include "fw/notif-wait.h"
#define MVM_UCODE_PNVM_TIMEOUT (HZ / 4)
@@ -15,24 +13,17 @@
#define MAX_PNVM_NAME 64
int iwl_pnvm_load(struct iwl_trans *trans,
- struct iwl_notif_wait_data *notif_wait);
+ struct iwl_notif_wait_data *notif_wait,
+ const struct iwl_ucode_capabilities *capa);
static inline
void iwl_pnvm_get_fs_name(struct iwl_trans *trans,
u8 *pnvm_name, size_t max_len)
{
- int pre_len;
-
- /*
- * The prefix unfortunately includes a hyphen at the end, so
- * don't add the dot here...
- */
- snprintf(pnvm_name, max_len, "%spnvm", trans->cfg->fw_name_pre);
+ char _fw_name_pre[FW_NAME_PRE_BUFSIZE];
- /* ...but replace the hyphen with the dot here. */
- pre_len = strlen(trans->cfg->fw_name_pre);
- if (pre_len < max_len && pre_len > 0)
- pnvm_name[pre_len - 1] = '.';
+ snprintf(pnvm_name, max_len, "%s.pnvm",
+ iwl_drv_get_fwname_pre(trans, _fw_name_pre));
}
#endif /* __IWL_PNVM_H__ */
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/runtime.h b/drivers/net/wireless/intel/iwlwifi/fw/runtime.h
index df689a9b7e2c..702586945533 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/runtime.h
+++ b/drivers/net/wireless/intel/iwlwifi/fw/runtime.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/*
* Copyright (C) 2017 Intel Deutschland GmbH
- * Copyright (C) 2018-2022 Intel Corporation
+ * Copyright (C) 2018-2023 Intel Corporation
*/
#ifndef __iwl_fw_runtime_h__
#define __iwl_fw_runtime_h__
@@ -146,12 +146,14 @@ struct iwl_fw_runtime {
u32 umac_minor;
} fw_ver;
} dump;
-#ifdef CONFIG_IWLWIFI_DEBUGFS
struct {
+#ifdef CONFIG_IWLWIFI_DEBUGFS
struct delayed_work wk;
u32 delay;
+#endif
u64 seq;
} timestamp;
+#ifdef CONFIG_IWLWIFI_DEBUGFS
bool tpc_enabled;
#endif /* CONFIG_IWLWIFI_DEBUGFS */
#ifdef CONFIG_ACPI
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/uefi.c b/drivers/net/wireless/intel/iwlwifi/fw/uefi.c
index 01afea33c38c..9877988db0d2 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/uefi.c
+++ b/drivers/net/wireless/intel/iwlwifi/fw/uefi.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
- * Copyright(c) 2021-2022 Intel Corporation
+ * Copyright(c) 2021-2023 Intel Corporation
*/
#include "iwl-drv.h"
@@ -17,52 +17,109 @@
0xb2, 0xec, 0xf5, 0xa3, \
0x59, 0x4f, 0x4a, 0xea)
-void *iwl_uefi_get_pnvm(struct iwl_trans *trans, size_t *len)
+struct iwl_uefi_pnvm_mem_desc {
+ __le32 addr;
+ __le32 size;
+ const u8 data[];
+} __packed;
+
+static void *iwl_uefi_get_variable(efi_char16_t *name, efi_guid_t *guid,
+ unsigned long *data_size)
{
- void *data;
- unsigned long package_size;
efi_status_t status;
+ void *data;
- *len = 0;
+ if (!data_size)
+ return ERR_PTR(-EINVAL);
if (!efi_rt_services_supported(EFI_RT_SUPPORTED_GET_VARIABLE))
return ERR_PTR(-ENODEV);
- /*
- * TODO: we hardcode a maximum length here, because reading
- * from the UEFI is not working. To implement this properly,
- * we have to call efivar_entry_size().
- */
- package_size = IWL_HARDCODED_PNVM_SIZE;
+ /* first call with NULL data to get the exact entry size */
+ *data_size = 0;
+ status = efi.get_variable(name, guid, NULL, data_size, NULL);
+ if (status != EFI_BUFFER_TOO_SMALL || !*data_size)
+ return ERR_PTR(-EIO);
- data = kmalloc(package_size, GFP_KERNEL);
+ data = kmalloc(*data_size, GFP_KERNEL);
if (!data)
return ERR_PTR(-ENOMEM);
- status = efi.get_variable(IWL_UEFI_OEM_PNVM_NAME, &IWL_EFI_VAR_GUID,
- NULL, &package_size, data);
+ status = efi.get_variable(name, guid, NULL, data_size, data);
if (status != EFI_SUCCESS) {
- IWL_DEBUG_FW(trans,
- "PNVM UEFI variable not found 0x%lx (len %lu)\n",
- status, package_size);
kfree(data);
return ERR_PTR(-ENOENT);
}
+ return data;
+}
+
+void *iwl_uefi_get_pnvm(struct iwl_trans *trans, size_t *len)
+{
+ unsigned long package_size;
+ void *data;
+
+ *len = 0;
+
+ data = iwl_uefi_get_variable(IWL_UEFI_OEM_PNVM_NAME, &IWL_EFI_VAR_GUID,
+ &package_size);
+ if (IS_ERR(data)) {
+ IWL_DEBUG_FW(trans,
+ "PNVM UEFI variable not found 0x%lx (len %lu)\n",
+ PTR_ERR(data), package_size);
+ return data;
+ }
+
IWL_DEBUG_FW(trans, "Read PNVM from UEFI with size %lu\n", package_size);
*len = package_size;
return data;
}
-static void *iwl_uefi_reduce_power_section(struct iwl_trans *trans,
- const u8 *data, size_t len)
+int iwl_uefi_handle_tlv_mem_desc(struct iwl_trans *trans, const u8 *data,
+ u32 tlv_len, struct iwl_pnvm_image *pnvm_data)
+{
+ const struct iwl_uefi_pnvm_mem_desc *desc = (const void *)data;
+ u32 data_len;
+
+ if (tlv_len < sizeof(*desc)) {
+ IWL_DEBUG_FW(trans, "TLV len (%d) is too small\n", tlv_len);
+ return -EINVAL;
+ }
+
+ data_len = tlv_len - sizeof(*desc);
+
+ IWL_DEBUG_FW(trans,
+ "Handle IWL_UCODE_TLV_MEM_DESC, len %d data_len %d\n",
+ tlv_len, data_len);
+
+ if (le32_to_cpu(desc->size) != data_len) {
+ IWL_DEBUG_FW(trans, "invalid mem desc size %d\n", desc->size);
+ return -EINVAL;
+ }
+
+ if (pnvm_data->n_chunks == IPC_DRAM_MAP_ENTRY_NUM_MAX) {
+ IWL_DEBUG_FW(trans, "too many payloads to allocate in DRAM.\n");
+ return -EINVAL;
+ }
+
+ IWL_DEBUG_FW(trans, "Adding data (size %d)\n", data_len);
+
+ pnvm_data->chunks[pnvm_data->n_chunks].data = desc->data;
+ pnvm_data->chunks[pnvm_data->n_chunks].len = data_len;
+ pnvm_data->n_chunks++;
+
+ return 0;
+}
+
+static int iwl_uefi_reduce_power_section(struct iwl_trans *trans,
+ const u8 *data, size_t len,
+ struct iwl_pnvm_image *pnvm_data)
{
const struct iwl_ucode_tlv *tlv;
- u8 *reduce_power_data = NULL, *tmp;
- u32 size = 0;
IWL_DEBUG_FW(trans, "Handling REDUCE_POWER section\n");
+ memset(pnvm_data, 0, sizeof(*pnvm_data));
while (len >= sizeof(*tlv)) {
u32 tlv_len, tlv_type;
@@ -76,39 +133,17 @@ static void *iwl_uefi_reduce_power_section(struct iwl_trans *trans,
if (len < tlv_len) {
IWL_ERR(trans, "invalid TLV len: %zd/%u\n",
len, tlv_len);
- kfree(reduce_power_data);
- reduce_power_data = ERR_PTR(-EINVAL);
- goto out;
+ return -EINVAL;
}
data += sizeof(*tlv);
switch (tlv_type) {
- case IWL_UCODE_TLV_MEM_DESC: {
- IWL_DEBUG_FW(trans,
- "Got IWL_UCODE_TLV_MEM_DESC len %d\n",
- tlv_len);
-
- IWL_DEBUG_FW(trans, "Adding data (size %d)\n", tlv_len);
-
- tmp = krealloc(reduce_power_data, size + tlv_len, GFP_KERNEL);
- if (!tmp) {
- IWL_DEBUG_FW(trans,
- "Couldn't allocate (more) reduce_power_data\n");
-
- kfree(reduce_power_data);
- reduce_power_data = ERR_PTR(-ENOMEM);
- goto out;
- }
-
- reduce_power_data = tmp;
-
- memcpy(reduce_power_data + size, data, tlv_len);
-
- size += tlv_len;
-
+ case IWL_UCODE_TLV_MEM_DESC:
+ if (iwl_uefi_handle_tlv_mem_desc(trans, data, tlv_len,
+ pnvm_data))
+ return -EINVAL;
break;
- }
case IWL_UCODE_TLV_PNVM_SKU:
IWL_DEBUG_FW(trans,
"New REDUCE_POWER section started, stop parsing.\n");
@@ -124,27 +159,18 @@ static void *iwl_uefi_reduce_power_section(struct iwl_trans *trans,
}
done:
- if (!size) {
+ if (!pnvm_data->n_chunks) {
IWL_DEBUG_FW(trans, "Empty REDUCE_POWER, skipping.\n");
- /* Better safe than sorry, but 'reduce_power_data' should
- * always be NULL if !size.
- */
- kfree(reduce_power_data);
- reduce_power_data = ERR_PTR(-ENOENT);
- goto out;
+ return -ENOENT;
}
-
- IWL_INFO(trans, "loaded REDUCE_POWER\n");
-
-out:
- return reduce_power_data;
+ return 0;
}
-static void *iwl_uefi_reduce_power_parse(struct iwl_trans *trans,
- const u8 *data, size_t len)
+int iwl_uefi_reduce_power_parse(struct iwl_trans *trans,
+ const u8 *data, size_t len,
+ struct iwl_pnvm_image *pnvm_data)
{
const struct iwl_ucode_tlv *tlv;
- void *sec_data;
IWL_DEBUG_FW(trans, "Parsing REDUCE_POWER data\n");
@@ -160,7 +186,7 @@ static void *iwl_uefi_reduce_power_parse(struct iwl_trans *trans,
if (len < tlv_len) {
IWL_ERR(trans, "invalid TLV len: %zd/%u\n",
len, tlv_len);
- return ERR_PTR(-EINVAL);
+ return -EINVAL;
}
if (tlv_type == IWL_UCODE_TLV_PNVM_SKU) {
@@ -181,11 +207,11 @@ static void *iwl_uefi_reduce_power_parse(struct iwl_trans *trans,
if (trans->sku_id[0] == le32_to_cpu(sku_id->data[0]) &&
trans->sku_id[1] == le32_to_cpu(sku_id->data[1]) &&
trans->sku_id[2] == le32_to_cpu(sku_id->data[2])) {
- sec_data = iwl_uefi_reduce_power_section(trans,
- data,
- len);
- if (!IS_ERR(sec_data))
- return sec_data;
+ int ret = iwl_uefi_reduce_power_section(trans,
+ data, len,
+ pnvm_data);
+ if (!ret)
+ return 0;
} else {
IWL_DEBUG_FW(trans, "SKU ID didn't match!\n");
}
@@ -195,51 +221,45 @@ static void *iwl_uefi_reduce_power_parse(struct iwl_trans *trans,
}
}
- return ERR_PTR(-ENOENT);
+ return -ENOENT;
}
-void *iwl_uefi_get_reduced_power(struct iwl_trans *trans, size_t *len)
+u8 *iwl_uefi_get_reduced_power(struct iwl_trans *trans, size_t *len)
{
struct pnvm_sku_package *package;
- void *data = NULL;
unsigned long package_size;
- efi_status_t status;
+ u8 *data;
- *len = 0;
+ package = iwl_uefi_get_variable(IWL_UEFI_REDUCED_POWER_NAME,
+ &IWL_EFI_VAR_GUID, &package_size);
- if (!efi_rt_services_supported(EFI_RT_SUPPORTED_GET_VARIABLE))
- return ERR_PTR(-ENODEV);
-
- /*
- * TODO: we hardcode a maximum length here, because reading
- * from the UEFI is not working. To implement this properly,
- * we have to call efivar_entry_size().
- */
- package_size = IWL_HARDCODED_REDUCE_POWER_SIZE;
-
- package = kmalloc(package_size, GFP_KERNEL);
- if (!package)
- return ERR_PTR(-ENOMEM);
-
- status = efi.get_variable(IWL_UEFI_REDUCED_POWER_NAME, &IWL_EFI_VAR_GUID,
- NULL, &package_size, package);
- if (status != EFI_SUCCESS) {
+ if (IS_ERR(package)) {
IWL_DEBUG_FW(trans,
"Reduced Power UEFI variable not found 0x%lx (len %lu)\n",
- status, package_size);
+ PTR_ERR(package), package_size);
+ return ERR_CAST(package);
+ }
+
+ if (package_size < sizeof(*package)) {
+ IWL_DEBUG_FW(trans,
+ "Invalid Reduced Power UEFI variable len (%lu)\n",
+ package_size);
kfree(package);
- return ERR_PTR(-ENOENT);
+ return ERR_PTR(-EINVAL);
}
IWL_DEBUG_FW(trans, "Read reduced power from UEFI with size %lu\n",
package_size);
- *len = package_size;
IWL_DEBUG_FW(trans, "rev %d, total_size %d, n_skus %d\n",
package->rev, package->total_size, package->n_skus);
- data = iwl_uefi_reduce_power_parse(trans, package->data,
- *len - sizeof(*package));
+ *len = package_size - sizeof(*package);
+ data = kmemdup(package->data, *len, GFP_KERNEL);
+ if (!data) {
+ kfree(package);
+ return ERR_PTR(-ENOMEM);
+ }
kfree(package);
@@ -264,31 +284,27 @@ void iwl_uefi_get_step_table(struct iwl_trans *trans)
{
struct uefi_cnv_common_step_data *data;
unsigned long package_size;
- efi_status_t status;
int ret;
if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
return;
- if (!efi_rt_services_supported(EFI_RT_SUPPORTED_GET_VARIABLE))
- return;
+ data = iwl_uefi_get_variable(IWL_UEFI_STEP_NAME, &IWL_EFI_VAR_GUID,
+ &package_size);
- /* TODO: we hardcode a maximum length here, because reading
- * from the UEFI is not working. To implement this properly,
- * we have to call efivar_entry_size().
- */
- package_size = IWL_HARDCODED_STEP_SIZE;
-
- data = kmalloc(package_size, GFP_KERNEL);
- if (!data)
+ if (IS_ERR(data)) {
+ IWL_DEBUG_FW(trans,
+ "STEP UEFI variable not found 0x%lx\n",
+ PTR_ERR(data));
return;
+ }
- status = efi.get_variable(IWL_UEFI_STEP_NAME, &IWL_EFI_VAR_GUID,
- NULL, &package_size, data);
- if (status != EFI_SUCCESS) {
+ if (package_size < sizeof(*data)) {
IWL_DEBUG_FW(trans,
- "STEP UEFI variable not found 0x%lx\n", status);
- goto out_free;
+ "Invalid STEP table UEFI variable len (%lu)\n",
+ package_size);
+ kfree(data);
+ return;
}
IWL_DEBUG_FW(trans, "Read STEP from UEFI with size %lu\n",
@@ -298,7 +314,6 @@ void iwl_uefi_get_step_table(struct iwl_trans *trans)
if (ret < 0)
IWL_DEBUG_FW(trans, "Cannot read STEP tables. rev is invalid\n");
-out_free:
kfree(data);
}
IWL_EXPORT_SYMBOL(iwl_uefi_get_step_table);
@@ -341,29 +356,26 @@ void iwl_uefi_get_sgom_table(struct iwl_trans *trans,
{
struct uefi_cnv_wlan_sgom_data *data;
unsigned long package_size;
- efi_status_t status;
int ret;
- if (!fwrt->geo_enabled ||
- !efi_rt_services_supported(EFI_RT_SUPPORTED_GET_VARIABLE))
+ if (!fwrt->geo_enabled)
return;
- /* TODO: we hardcode a maximum length here, because reading
- * from the UEFI is not working. To implement this properly,
- * we have to call efivar_entry_size().
- */
- package_size = IWL_HARDCODED_SGOM_SIZE;
-
- data = kmalloc(package_size, GFP_KERNEL);
- if (!data)
+ data = iwl_uefi_get_variable(IWL_UEFI_SGOM_NAME, &IWL_EFI_VAR_GUID,
+ &package_size);
+ if (IS_ERR(data)) {
+ IWL_DEBUG_FW(trans,
+ "SGOM UEFI variable not found 0x%lx\n",
+ PTR_ERR(data));
return;
+ }
- status = efi.get_variable(IWL_UEFI_SGOM_NAME, &IWL_EFI_VAR_GUID,
- NULL, &package_size, data);
- if (status != EFI_SUCCESS) {
+ if (package_size < sizeof(*data)) {
IWL_DEBUG_FW(trans,
- "SGOM UEFI variable not found 0x%lx\n", status);
- goto out_free;
+ "Invalid SGOM table UEFI variable len (%lu)\n",
+ package_size);
+ kfree(data);
+ return;
}
IWL_DEBUG_FW(trans, "Read SGOM from UEFI with size %lu\n",
@@ -373,9 +385,7 @@ void iwl_uefi_get_sgom_table(struct iwl_trans *trans,
if (ret < 0)
IWL_DEBUG_FW(trans, "Cannot read SGOM tables. rev is invalid\n");
-out_free:
kfree(data);
-
}
IWL_EXPORT_SYMBOL(iwl_uefi_get_sgom_table);
#endif /* CONFIG_ACPI */
diff --git a/drivers/net/wireless/intel/iwlwifi/fw/uefi.h b/drivers/net/wireless/intel/iwlwifi/fw/uefi.h
index 17089bc74cf9..1369cc4855c3 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/uefi.h
+++ b/drivers/net/wireless/intel/iwlwifi/fw/uefi.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/*
- * Copyright(c) 2021-2022 Intel Corporation
+ * Copyright(c) 2021-2023 Intel Corporation
*/
#ifndef __iwl_fw_uefi__
#define __iwl_fw_uefi__
@@ -10,16 +10,7 @@
#define IWL_UEFI_SGOM_NAME L"UefiCnvWlanSarGeoOffsetMapping"
#define IWL_UEFI_STEP_NAME L"UefiCnvCommonSTEP"
-/*
- * TODO: we have these hardcoded values that the caller must pass,
- * because reading from the UEFI is not working. To implement this
- * properly, we have to change iwl_pnvm_get_from_uefi() to call
- * efivar_entry_size() and return the value to the caller instead.
- */
-#define IWL_HARDCODED_PNVM_SIZE 4096
-#define IWL_HARDCODED_REDUCE_POWER_SIZE 32768
-#define IWL_HARDCODED_SGOM_SIZE 339
-#define IWL_HARDCODED_STEP_SIZE 6
+#define IWL_SGOM_MAP_SIZE 339
struct pnvm_sku_package {
u8 rev;
@@ -31,7 +22,7 @@ struct pnvm_sku_package {
struct uefi_cnv_wlan_sgom_data {
u8 revision;
- u8 offset_map[IWL_HARDCODED_SGOM_SIZE - 1];
+ u8 offset_map[IWL_SGOM_MAP_SIZE - 1];
} __packed;
struct uefi_cnv_common_step_data {
@@ -50,24 +41,42 @@ struct uefi_cnv_common_step_data {
*/
#ifdef CONFIG_EFI
void *iwl_uefi_get_pnvm(struct iwl_trans *trans, size_t *len);
-void *iwl_uefi_get_reduced_power(struct iwl_trans *trans, size_t *len);
+u8 *iwl_uefi_get_reduced_power(struct iwl_trans *trans, size_t *len);
+int iwl_uefi_reduce_power_parse(struct iwl_trans *trans,
+ const u8 *data, size_t len,
+ struct iwl_pnvm_image *pnvm_data);
void iwl_uefi_get_step_table(struct iwl_trans *trans);
+int iwl_uefi_handle_tlv_mem_desc(struct iwl_trans *trans, const u8 *data,
+ u32 tlv_len, struct iwl_pnvm_image *pnvm_data);
#else /* CONFIG_EFI */
-static inline
-void *iwl_uefi_get_pnvm(struct iwl_trans *trans, size_t *len)
+static inline void *iwl_uefi_get_pnvm(struct iwl_trans *trans, size_t *len)
{
return ERR_PTR(-EOPNOTSUPP);
}
-static inline
-void *iwl_uefi_get_reduced_power(struct iwl_trans *trans, size_t *len)
+static inline int
+iwl_uefi_reduce_power_parse(struct iwl_trans *trans,
+ const u8 *data, size_t len,
+ struct iwl_pnvm_image *pnvm_data)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline u8 *
+iwl_uefi_get_reduced_power(struct iwl_trans *trans, size_t *len)
{
return ERR_PTR(-EOPNOTSUPP);
}
-static inline
-void iwl_uefi_get_step_table(struct iwl_trans *trans)
+static inline void iwl_uefi_get_step_table(struct iwl_trans *trans)
+{
+}
+
+static inline int
+iwl_uefi_handle_tlv_mem_desc(struct iwl_trans *trans, const u8 *data,
+ u32 tlv_len, struct iwl_pnvm_image *pnvm_data)
{
+ return 0;
}
#endif /* CONFIG_EFI */
diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-config.h b/drivers/net/wireless/intel/iwlwifi/iwl-config.h
index 411b7d4fcc9a..742096c5a36a 100644
--- a/drivers/net/wireless/intel/iwlwifi/iwl-config.h
+++ b/drivers/net/wireless/intel/iwlwifi/iwl-config.h
@@ -2,6 +2,7 @@
/*
* Copyright (C) 2005-2014, 2018-2021 Intel Corporation
* Copyright (C) 2016-2017 Intel Deutschland GmbH
+ * Copyright (C) 2018-2023 Intel Corporation
*/
#ifndef __IWL_CONFIG_H__
#define __IWL_CONFIG_H__
@@ -34,6 +35,7 @@ enum iwl_device_family {
IWL_DEVICE_FAMILY_22000,
IWL_DEVICE_FAMILY_AX210,
IWL_DEVICE_FAMILY_BZ,
+ IWL_DEVICE_FAMILY_SC,
};
/*
@@ -307,7 +309,9 @@ struct iwl_fw_mon_regs {
* @name: Official name of the device
* @fw_name_pre: Firmware filename prefix. The api version and extension
* (.ucode) will be added to filename before loading from disk. The
- * filename is constructed as fw_name_pre<api>.ucode.
+ * filename is constructed as <fw_name_pre>-<api>.ucode.
+ * @fw_name_mac: MAC name for this config, the remaining pieces of the
+ * name will be generated dynamically
* @ucode_api_max: Highest version of uCode API supported by driver.
* @ucode_api_min: Lowest version of uCode API supported by driver.
* @max_inst_size: The maximal length of the fw inst section (only DVM)
@@ -361,6 +365,7 @@ struct iwl_cfg {
/* params specific to an individual device within a device family */
const char *name;
const char *fw_name_pre;
+ const char *fw_name_mac;
/* params likely to change within a device family */
const struct iwl_ht_params *ht_params;
const struct iwl_eeprom_params *eeprom_params;
@@ -388,7 +393,6 @@ struct iwl_cfg {
high_temp:1,
mac_addr_from_csr:10,
lp_xtal_workaround:1,
- disable_dummy_notification:1,
apmg_not_supported:1,
vht_mu_mimo_supported:1,
cdb:1,
@@ -416,17 +420,15 @@ struct iwl_cfg {
#define IWL_CFG_ANY (~0)
#define IWL_CFG_MAC_TYPE_PU 0x31
-#define IWL_CFG_MAC_TYPE_PNJ 0x32
#define IWL_CFG_MAC_TYPE_TH 0x32
#define IWL_CFG_MAC_TYPE_QU 0x33
#define IWL_CFG_MAC_TYPE_QUZ 0x35
-#define IWL_CFG_MAC_TYPE_QNJ 0x36
#define IWL_CFG_MAC_TYPE_SO 0x37
-#define IWL_CFG_MAC_TYPE_SNJ 0x42
#define IWL_CFG_MAC_TYPE_SOF 0x43
#define IWL_CFG_MAC_TYPE_MA 0x44
#define IWL_CFG_MAC_TYPE_BZ 0x46
#define IWL_CFG_MAC_TYPE_GL 0x47
+#define IWL_CFG_MAC_TYPE_SC 0x48
#define IWL_CFG_RF_TYPE_TH 0x105
#define IWL_CFG_RF_TYPE_TH1 0x108
@@ -438,6 +440,7 @@ struct iwl_cfg {
#define IWL_CFG_RF_TYPE_MR 0x110
#define IWL_CFG_RF_TYPE_MS 0x111
#define IWL_CFG_RF_TYPE_FM 0x112
+#define IWL_CFG_RF_TYPE_WH 0x113
#define IWL_CFG_RF_ID_TH 0x1
#define IWL_CFG_RF_ID_TH1 0x1
@@ -486,17 +489,16 @@ extern const struct iwl_cfg_trans_params iwl9000_trans_cfg;
extern const struct iwl_cfg_trans_params iwl9560_trans_cfg;
extern const struct iwl_cfg_trans_params iwl9560_long_latency_trans_cfg;
extern const struct iwl_cfg_trans_params iwl9560_shared_clk_trans_cfg;
-extern const struct iwl_cfg_trans_params iwl_qnj_trans_cfg;
extern const struct iwl_cfg_trans_params iwl_qu_trans_cfg;
extern const struct iwl_cfg_trans_params iwl_qu_medium_latency_trans_cfg;
extern const struct iwl_cfg_trans_params iwl_qu_long_latency_trans_cfg;
extern const struct iwl_cfg_trans_params iwl_ax200_trans_cfg;
-extern const struct iwl_cfg_trans_params iwl_snj_trans_cfg;
extern const struct iwl_cfg_trans_params iwl_so_trans_cfg;
extern const struct iwl_cfg_trans_params iwl_so_long_latency_trans_cfg;
extern const struct iwl_cfg_trans_params iwl_so_long_latency_imr_trans_cfg;
extern const struct iwl_cfg_trans_params iwl_ma_trans_cfg;
extern const struct iwl_cfg_trans_params iwl_bz_trans_cfg;
+extern const struct iwl_cfg_trans_params iwl_sc_trans_cfg;
extern const char iwl9162_name[];
extern const char iwl9260_name[];
extern const char iwl9260_1_name[];
@@ -535,6 +537,7 @@ extern const char iwl_ax221_name[];
extern const char iwl_ax231_name[];
extern const char iwl_ax411_name[];
extern const char iwl_bz_name[];
+extern const char iwl_sc_name[];
#if IS_ENABLED(CONFIG_IWLDVM)
extern const struct iwl_cfg iwl5300_agn_cfg;
extern const struct iwl_cfg iwl5100_agn_cfg;
@@ -580,6 +583,7 @@ extern const struct iwl_cfg iwl105_bgn_d_cfg;
extern const struct iwl_cfg iwl135_bgn_cfg;
#endif /* CONFIG_IWLDVM */
#if IS_ENABLED(CONFIG_IWLMVM)
+extern const struct iwl_ht_params iwl_22000_ht_params;
extern const struct iwl_cfg iwl7260_2ac_cfg;
extern const struct iwl_cfg iwl7260_2ac_cfg_high_temp;
extern const struct iwl_cfg iwl7260_2n_cfg;
@@ -604,7 +608,6 @@ extern const struct iwl_cfg iwl9260_2ac_cfg;
extern const struct iwl_cfg iwl9560_qu_b0_jf_b0_cfg;
extern const struct iwl_cfg iwl9560_qu_c0_jf_b0_cfg;
extern const struct iwl_cfg iwl9560_quz_a0_jf_b0_cfg;
-extern const struct iwl_cfg iwl9560_qnj_b0_jf_b0_cfg;
extern const struct iwl_cfg iwl9560_2ac_cfg_soc;
extern const struct iwl_cfg iwl_qu_b0_hr1_b0;
extern const struct iwl_cfg iwl_qu_c0_hr1_b0;
@@ -623,57 +626,23 @@ extern const struct iwl_cfg killer1650s_2ax_cfg_qu_c0_hr_b0;
extern const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0;
extern const struct iwl_cfg killer1650x_2ax_cfg;
extern const struct iwl_cfg killer1650w_2ax_cfg;
-extern const struct iwl_cfg iwl_qnj_b0_hr_b0_cfg;
extern const struct iwl_cfg iwlax210_2ax_cfg_so_jf_b0;
extern const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0;
extern const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0_long;
extern const struct iwl_cfg iwlax210_2ax_cfg_ty_gf_a0;
extern const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0;
extern const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0_long;
-extern const struct iwl_cfg iwlax411_2ax_cfg_sosnj_gf4_a0;
-extern const struct iwl_cfg iwlax211_cfg_snj_gf_a0;
-extern const struct iwl_cfg iwl_cfg_snj_hr_b0;
-extern const struct iwl_cfg iwl_cfg_snj_a0_jf_b0;
-extern const struct iwl_cfg iwl_cfg_ma_a0_hr_b0;
-extern const struct iwl_cfg iwl_cfg_ma_a0_gf_a0;
-extern const struct iwl_cfg iwl_cfg_ma_a0_gf4_a0;
-extern const struct iwl_cfg iwl_cfg_ma_a0_mr_a0;
-extern const struct iwl_cfg iwl_cfg_ma_a0_ms_a0;
-extern const struct iwl_cfg iwl_cfg_ma_a0_fm_a0;
-extern const struct iwl_cfg iwl_cfg_ma_b0_hr_b0;
-extern const struct iwl_cfg iwl_cfg_ma_b0_gf_a0;
-extern const struct iwl_cfg iwl_cfg_ma_b0_gf4_a0;
-extern const struct iwl_cfg iwl_cfg_ma_b0_mr_a0;
-extern const struct iwl_cfg iwl_cfg_ma_b0_fm_a0;
-extern const struct iwl_cfg iwl_cfg_snj_a0_mr_a0;
-extern const struct iwl_cfg iwl_cfg_snj_a0_ms_a0;
+
+extern const struct iwl_cfg iwl_cfg_ma;
+
extern const struct iwl_cfg iwl_cfg_so_a0_hr_a0;
extern const struct iwl_cfg iwl_cfg_so_a0_ms_a0;
extern const struct iwl_cfg iwl_cfg_quz_a0_hr_b0;
-extern const struct iwl_cfg iwl_cfg_bz_a0_hr_a0;
-extern const struct iwl_cfg iwl_cfg_bz_a0_hr_b0;
-extern const struct iwl_cfg iwl_cfg_bz_a0_gf_a0;
-extern const struct iwl_cfg iwl_cfg_bz_a0_gf4_a0;
-extern const struct iwl_cfg iwl_cfg_bz_a0_mr_a0;
-extern const struct iwl_cfg iwl_cfg_bz_a0_fm_a0;
-extern const struct iwl_cfg iwl_cfg_bz_a0_fm4_a0;
-extern const struct iwl_cfg iwl_cfg_bz_a0_fm_b0;
-extern const struct iwl_cfg iwl_cfg_bz_a0_fm4_b0;
-extern const struct iwl_cfg iwl_cfg_gl_a0_fm_a0;
-extern const struct iwl_cfg iwl_cfg_gl_b0_fm_b0;
-extern const struct iwl_cfg iwl_cfg_bz_z0_gf_a0;
-extern const struct iwl_cfg iwl_cfg_bnj_a0_fm_a0;
-extern const struct iwl_cfg iwl_cfg_bnj_a0_fm4_a0;
-extern const struct iwl_cfg iwl_cfg_bnj_a0_gf_a0;
-extern const struct iwl_cfg iwl_cfg_bnj_b0_gf_a0;
-extern const struct iwl_cfg iwl_cfg_bnj_a0_gf4_a0;
-extern const struct iwl_cfg iwl_cfg_bnj_b0_gf4_a0;
-extern const struct iwl_cfg iwl_cfg_bnj_a0_hr_a0;
-extern const struct iwl_cfg iwl_cfg_bnj_a0_hr_b0;
-extern const struct iwl_cfg iwl_cfg_bnj_b0_hr_a0;
-extern const struct iwl_cfg iwl_cfg_bnj_b0_hr_b0;
-extern const struct iwl_cfg iwl_cfg_bnj_b0_fm_b0;
-extern const struct iwl_cfg iwl_cfg_bnj_b0_fm4_b0;
+
+extern const struct iwl_cfg iwl_cfg_bz;
+extern const struct iwl_cfg iwl_cfg_gl;
+
+extern const struct iwl_cfg iwl_cfg_sc;
#endif /* CONFIG_IWLMVM */
#endif /* __IWL_CONFIG_H__ */
diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-context-info-gen3.h b/drivers/net/wireless/intel/iwlwifi/iwl-context-info-gen3.h
index 3f7278014009..96bf353469b8 100644
--- a/drivers/net/wireless/intel/iwlwifi/iwl-context-info-gen3.h
+++ b/drivers/net/wireless/intel/iwlwifi/iwl-context-info-gen3.h
@@ -13,6 +13,8 @@
#define CSR_IML_SIZE_ADDR 0x128
#define CSR_IML_RESP_ADDR 0x12c
+#define UNFRAGMENTED_PNVM_PAYLOADS_NUMBER 2
+
/* Set bit for enabling automatic function boot */
#define CSR_AUTO_FUNC_BOOT_ENA BIT(1)
/* Set bit for initiating function boot */
@@ -96,9 +98,9 @@ struct iwl_prph_scratch_control {
} __packed; /* PERIPH_SCRATCH_CONTROL_S */
/*
- * struct iwl_prph_scratch_pnvm_cfg - ror config
+ * struct iwl_prph_scratch_pnvm_cfg - PNVM scratch
* @pnvm_base_addr: PNVM start address
- * @pnvm_size: PNVM size in DWs
+ * @pnvm_size: the size of the PNVM image in bytes
* @reserved: reserved
*/
struct iwl_prph_scratch_pnvm_cfg {
@@ -107,6 +109,14 @@ struct iwl_prph_scratch_pnvm_cfg {
__le32 reserved;
} __packed; /* PERIPH_SCRATCH_PNVM_CFG_S */
+/**
+ * struct iwl_prph_scrath_mem_desc_addr_array
+ * @mem_descs: array of dram addresses.
+ * Each address is the beggining of a pnvm payload.
+ */
+struct iwl_prph_scrath_mem_desc_addr_array {
+ __le64 mem_descs[IPC_DRAM_MAP_ENTRY_NUM_MAX];
+} __packed; /* PERIPH_SCRATCH_MEM_DESC_ADDR_ARRAY_S_VER_1 */
/*
* struct iwl_prph_scratch_hwm_cfg - hwm config
* @hwm_base_addr: hwm start address
@@ -132,7 +142,7 @@ struct iwl_prph_scratch_rbd_cfg {
/*
* struct iwl_prph_scratch_uefi_cfg - prph scratch reduce power table
* @base_addr: reduce power table address
- * @size: table size in dwords
+ * @size: the size of the entire power table image
*/
struct iwl_prph_scratch_uefi_cfg {
__le64 base_addr;
@@ -277,10 +287,18 @@ int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
const struct fw_img *fw);
void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans, bool alive);
-int iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans,
- const void *data, u32 len);
-int iwl_trans_pcie_ctx_info_gen3_set_reduce_power(struct iwl_trans *trans,
- const void *data, u32 len);
+int iwl_trans_pcie_ctx_info_gen3_load_pnvm(struct iwl_trans *trans,
+ const struct iwl_pnvm_image *pnvm_payloads,
+ const struct iwl_ucode_capabilities *capa);
+void iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans,
+ const struct iwl_ucode_capabilities *capa);
+int
+iwl_trans_pcie_ctx_info_gen3_load_reduce_power(struct iwl_trans *trans,
+ const struct iwl_pnvm_image *payloads,
+ const struct iwl_ucode_capabilities *capa);
+void
+iwl_trans_pcie_ctx_info_gen3_set_reduce_power(struct iwl_trans *trans,
+ const struct iwl_ucode_capabilities *capa);
int iwl_trans_pcie_ctx_info_gen3_set_step(struct iwl_trans *trans,
u32 mbx_addr_0_step, u32 mbx_addr_1_step);
#endif /* __iwl_context_info_file_gen3_h__ */
diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-context-info.h b/drivers/net/wireless/intel/iwlwifi/iwl-context-info.h
index 4354d5acac9f..1a1321db137c 100644
--- a/drivers/net/wireless/intel/iwlwifi/iwl-context-info.h
+++ b/drivers/net/wireless/intel/iwlwifi/iwl-context-info.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/*
* Copyright (C) 2017 Intel Deutschland GmbH
- * Copyright (C) 2018-2020 Intel Corporation
+ * Copyright (C) 2018-2020, 2022 Intel Corporation
*/
#ifndef __iwl_context_info_file_h__
#define __iwl_context_info_file_h__
@@ -177,6 +177,9 @@ void iwl_pcie_ctxt_info_free_paging(struct iwl_trans *trans);
int iwl_pcie_init_fw_sec(struct iwl_trans *trans,
const struct fw_img *fw,
struct iwl_context_info_dram *ctxt_dram);
+void *iwl_pcie_ctxt_info_dma_alloc_coherent(struct iwl_trans *trans,
+ size_t size,
+ dma_addr_t *phys);
int iwl_pcie_ctxt_info_alloc_dma(struct iwl_trans *trans,
const void *data, u32 len,
struct iwl_dram_data *dram);
diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-dbg-tlv.c b/drivers/net/wireless/intel/iwlwifi/iwl-dbg-tlv.c
index 898d5dcf1012..ef5baee6c9c5 100644
--- a/drivers/net/wireless/intel/iwlwifi/iwl-dbg-tlv.c
+++ b/drivers/net/wireless/intel/iwlwifi/iwl-dbg-tlv.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
- * Copyright (C) 2018-2022 Intel Corporation
+ * Copyright (C) 2018-2023 Intel Corporation
*/
#include <linux/firmware.h>
#include "iwl-drv.h"
@@ -586,8 +586,14 @@ static int iwl_dbg_tlv_alloc_fragments(struct iwl_fw_runtime *fwrt,
fw_mon_cfg = &fwrt->trans->dbg.fw_mon_cfg[alloc_id];
fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
- if (fw_mon->num_frags ||
- fw_mon_cfg->buf_location !=
+ if (fw_mon->num_frags) {
+ for (i = 0; i < fw_mon->num_frags; i++)
+ memset(fw_mon->frags[i].block, 0,
+ fw_mon->frags[i].size);
+ return 0;
+ }
+
+ if (fw_mon_cfg->buf_location !=
cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH))
return 0;
@@ -738,7 +744,8 @@ static int iwl_dbg_tlv_update_dram(struct iwl_fw_runtime *fwrt,
if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) !=
IWL_FW_INI_LOCATION_DRAM_PATH) {
- IWL_DEBUG_FW(fwrt, "DRAM_PATH is not supported alloc_id %u\n", alloc_id);
+ IWL_DEBUG_FW(fwrt, "WRT: alloc_id %u location is not in DRAM_PATH\n",
+ alloc_id);
return -1;
}
@@ -794,11 +801,14 @@ static void iwl_dbg_tlv_update_drams(struct iwl_fw_runtime *fwrt)
IWL_UCODE_TLV_CAPA_DRAM_FRAG_SUPPORT))
return;
- dram_info->first_word = cpu_to_le32(DRAM_INFO_FIRST_MAGIC_WORD);
- dram_info->second_word = cpu_to_le32(DRAM_INFO_SECOND_MAGIC_WORD);
+ memset(dram_info, 0, sizeof(*dram_info));
for (i = IWL_FW_INI_ALLOCATION_ID_DBGC1;
i < IWL_FW_INI_ALLOCATION_NUM; i++) {
+ if (fwrt->trans->dbg.fw_mon_cfg[i].buf_location ==
+ IWL_FW_INI_LOCATION_INVALID)
+ continue;
+
ret = iwl_dbg_tlv_update_dram(fwrt, i, dram_info);
if (!ret)
dram_alloc = true;
@@ -808,11 +818,10 @@ static void iwl_dbg_tlv_update_drams(struct iwl_fw_runtime *fwrt)
i, ret);
}
- if (dram_alloc)
- IWL_DEBUG_FW(fwrt, "block data after %08x\n",
- dram_info->first_word);
- else
- memset(frags->block, 0, sizeof(*dram_info));
+ if (dram_alloc) {
+ dram_info->first_word = cpu_to_le32(DRAM_INFO_FIRST_MAGIC_WORD);
+ dram_info->second_word = cpu_to_le32(DRAM_INFO_SECOND_MAGIC_WORD);
+ }
}
static void iwl_dbg_tlv_send_hcmds(struct iwl_fw_runtime *fwrt,
@@ -1269,18 +1278,23 @@ static void iwl_dbg_tlv_init_cfg(struct iwl_fw_runtime *fwrt)
int ret, i;
u32 failed_alloc = 0;
- if (*ini_dest != IWL_FW_INI_LOCATION_INVALID)
- return;
-
- IWL_DEBUG_FW(fwrt,
- "WRT: Generating active triggers list, domain 0x%x\n",
- fwrt->trans->dbg.domains_bitmap);
+ if (*ini_dest == IWL_FW_INI_LOCATION_INVALID) {
+ IWL_DEBUG_FW(fwrt,
+ "WRT: Generating active triggers list, domain 0x%x\n",
+ fwrt->trans->dbg.domains_bitmap);
- for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.time_point); i++) {
- struct iwl_dbg_tlv_time_point_data *tp =
- &fwrt->trans->dbg.time_point[i];
+ for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.time_point); i++) {
+ struct iwl_dbg_tlv_time_point_data *tp =
+ &fwrt->trans->dbg.time_point[i];
- iwl_dbg_tlv_gen_active_trig_list(fwrt, tp);
+ iwl_dbg_tlv_gen_active_trig_list(fwrt, tp);
+ }
+ } else if (*ini_dest != IWL_FW_INI_LOCATION_DRAM_PATH) {
+ /* For DRAM, go through the loop below to clear all the buffers
+ * properly on restart, otherwise garbage may be left there and
+ * leak into new debug dumps.
+ */
+ return;
}
*ini_dest = IWL_FW_INI_LOCATION_INVALID;
diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-drv.c b/drivers/net/wireless/intel/iwlwifi/iwl-drv.c
index 34feb4d29adc..3d87d26845e7 100644
--- a/drivers/net/wireless/intel/iwlwifi/iwl-drv.c
+++ b/drivers/net/wireless/intel/iwlwifi/iwl-drv.c
@@ -158,12 +158,71 @@ static int iwl_alloc_fw_desc(struct iwl_drv *drv, struct fw_desc *desc,
return 0;
}
+static inline char iwl_drv_get_step(int step)
+{
+ if (step == SILICON_Z_STEP)
+ return 'z';
+ return 'a' + step;
+}
+
+const char *iwl_drv_get_fwname_pre(struct iwl_trans *trans, char *buf)
+{
+ char mac_step, rf_step;
+ const char *rf, *cdb;
+
+ if (trans->cfg->fw_name_pre)
+ return trans->cfg->fw_name_pre;
+
+ if (WARN_ON(!trans->cfg->fw_name_mac))
+ return "unconfigured";
+
+ mac_step = iwl_drv_get_step(trans->hw_rev_step);
+
+ switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) {
+ case IWL_CFG_RF_TYPE_HR1:
+ case IWL_CFG_RF_TYPE_HR2:
+ rf = "hr";
+ break;
+ case IWL_CFG_RF_TYPE_GF:
+ rf = "gf";
+ break;
+ case IWL_CFG_RF_TYPE_MR:
+ rf = "mr";
+ break;
+ case IWL_CFG_RF_TYPE_MS:
+ rf = "ms";
+ break;
+ case IWL_CFG_RF_TYPE_FM:
+ rf = "fm";
+ break;
+ case IWL_CFG_RF_TYPE_WH:
+ rf = "wh";
+ break;
+ default:
+ return "unknown-rf";
+ }
+
+ cdb = CSR_HW_RFID_IS_CDB(trans->hw_rf_id) ? "4" : "";
+
+ rf_step = iwl_drv_get_step(CSR_HW_RFID_STEP(trans->hw_rf_id));
+
+ scnprintf(buf, FW_NAME_PRE_BUFSIZE,
+ "iwlwifi-%s-%c0-%s%s-%c0",
+ trans->cfg->fw_name_mac, mac_step,
+ rf, cdb, rf_step);
+
+ return buf;
+}
+IWL_EXPORT_SYMBOL(iwl_drv_get_fwname_pre);
+
static void iwl_req_fw_callback(const struct firmware *ucode_raw,
void *context);
static int iwl_request_firmware(struct iwl_drv *drv, bool first)
{
const struct iwl_cfg *cfg = drv->trans->cfg;
+ char _fw_name_pre[FW_NAME_PRE_BUFSIZE];
+ const char *fw_name_pre;
if (drv->trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_9000 &&
(drv->trans->hw_rev_step != SILICON_B_STEP &&
@@ -174,6 +233,8 @@ static int iwl_request_firmware(struct iwl_drv *drv, bool first)
return -EINVAL;
}
+ fw_name_pre = iwl_drv_get_fwname_pre(drv->trans, _fw_name_pre);
+
if (first)
drv->fw_index = cfg->ucode_api_max;
else
@@ -183,13 +244,13 @@ static int iwl_request_firmware(struct iwl_drv *drv, bool first)
IWL_ERR(drv, "no suitable firmware found!\n");
if (cfg->ucode_api_min == cfg->ucode_api_max) {
- IWL_ERR(drv, "%s%d is required\n", cfg->fw_name_pre,
+ IWL_ERR(drv, "%s-%d is required\n", fw_name_pre,
cfg->ucode_api_max);
} else {
- IWL_ERR(drv, "minimum version required: %s%d\n",
- cfg->fw_name_pre, cfg->ucode_api_min);
- IWL_ERR(drv, "maximum version supported: %s%d\n",
- cfg->fw_name_pre, cfg->ucode_api_max);
+ IWL_ERR(drv, "minimum version required: %s-%d\n",
+ fw_name_pre, cfg->ucode_api_min);
+ IWL_ERR(drv, "maximum version supported: %s-%d\n",
+ fw_name_pre, cfg->ucode_api_max);
}
IWL_ERR(drv,
@@ -197,8 +258,8 @@ static int iwl_request_firmware(struct iwl_drv *drv, bool first)
return -ENOENT;
}
- snprintf(drv->firmware_name, sizeof(drv->firmware_name), "%s%d.ucode",
- cfg->fw_name_pre, drv->fw_index);
+ snprintf(drv->firmware_name, sizeof(drv->firmware_name), "%s-%d.ucode",
+ fw_name_pre, drv->fw_index);
IWL_DEBUG_FW_INFO(drv, "attempting to load firmware '%s'\n",
drv->firmware_name);
diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-drv.h b/drivers/net/wireless/intel/iwlwifi/iwl-drv.h
index 80073f973334..6c19989e4ab7 100644
--- a/drivers/net/wireless/intel/iwlwifi/iwl-drv.h
+++ b/drivers/net/wireless/intel/iwlwifi/iwl-drv.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/*
- * Copyright (C) 2005-2014, 2020-2021 Intel Corporation
+ * Copyright (C) 2005-2014, 2020-2021, 2023 Intel Corporation
* Copyright (C) 2013-2014 Intel Mobile Communications GmbH
*/
#ifndef __iwl_drv_h__
@@ -92,4 +92,8 @@ void iwl_drv_stop(struct iwl_drv *drv);
/* max retry for init flow */
#define IWL_MAX_INIT_RETRY 2
+#define FW_NAME_PRE_BUFSIZE 64
+struct iwl_trans;
+const char *iwl_drv_get_fwname_pre(struct iwl_trans *trans, char *buf);
+
#endif /* __iwl_drv_h__ */
diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-io.c b/drivers/net/wireless/intel/iwlwifi/iwl-io.c
index 396f2c997da6..c60f9466c5fd 100644
--- a/drivers/net/wireless/intel/iwlwifi/iwl-io.c
+++ b/drivers/net/wireless/intel/iwlwifi/iwl-io.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
- * Copyright (C) 2003-2014, 2018-2021 Intel Corporation
+ * Copyright (C) 2003-2014, 2018-2022 Intel Corporation
* Copyright (C) 2015-2016 Intel Deutschland GmbH
*/
#include <linux/delay.h>
@@ -72,6 +72,7 @@ u32 iwl_read_direct32(struct iwl_trans *trans, u32 reg)
return value;
}
+ /* return as if we have a HW timeout/failure */
return 0x5a5a5a5a;
}
IWL_EXPORT_SYMBOL(iwl_read_direct32);
@@ -143,6 +144,7 @@ u32 iwl_read_prph(struct iwl_trans *trans, u32 ofs)
return val;
}
+ /* return as if we have a HW timeout/failure */
return 0x5a5a5a5a;
}
IWL_EXPORT_SYMBOL(iwl_read_prph);
diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c b/drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c
index 7dcb1c3ab728..8c23f57f5c89 100644
--- a/drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c
+++ b/drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
- * Copyright (C) 2005-2014, 2018-2022 Intel Corporation
+ * Copyright (C) 2005-2014, 2018-2023 Intel Corporation
* Copyright (C) 2013-2015 Intel Mobile Communications GmbH
* Copyright (C) 2016-2017 Intel Deutschland GmbH
*/
@@ -173,34 +173,34 @@ enum iwl_nvm_channel_flags {
};
/**
- * enum iwl_reg_capa_flags - global flags applied for the whole regulatory
+ * enum iwl_reg_capa_flags_v1 - global flags applied for the whole regulatory
* domain.
- * @REG_CAPA_BF_CCD_LOW_BAND: Beam-forming or Cyclic Delay Diversity in the
+ * @REG_CAPA_V1_BF_CCD_LOW_BAND: Beam-forming or Cyclic Delay Diversity in the
* 2.4Ghz band is allowed.
- * @REG_CAPA_BF_CCD_HIGH_BAND: Beam-forming or Cyclic Delay Diversity in the
+ * @REG_CAPA_V1_BF_CCD_HIGH_BAND: Beam-forming or Cyclic Delay Diversity in the
* 5Ghz band is allowed.
- * @REG_CAPA_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed
+ * @REG_CAPA_V1_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed
* for this regulatory domain (valid only in 5Ghz).
- * @REG_CAPA_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed
+ * @REG_CAPA_V1_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed
* for this regulatory domain (valid only in 5Ghz).
- * @REG_CAPA_MCS_8_ALLOWED: 11ac with MCS 8 is allowed.
- * @REG_CAPA_MCS_9_ALLOWED: 11ac with MCS 9 is allowed.
- * @REG_CAPA_40MHZ_FORBIDDEN: 11n channel with a width of 40Mhz is forbidden
+ * @REG_CAPA_V1_MCS_8_ALLOWED: 11ac with MCS 8 is allowed.
+ * @REG_CAPA_V1_MCS_9_ALLOWED: 11ac with MCS 9 is allowed.
+ * @REG_CAPA_V1_40MHZ_FORBIDDEN: 11n channel with a width of 40Mhz is forbidden
* for this regulatory domain (valid only in 5Ghz).
- * @REG_CAPA_DC_HIGH_ENABLED: DC HIGH allowed.
- * @REG_CAPA_11AX_DISABLED: 11ax is forbidden for this regulatory domain.
+ * @REG_CAPA_V1_DC_HIGH_ENABLED: DC HIGH allowed.
+ * @REG_CAPA_V1_11AX_DISABLED: 11ax is forbidden for this regulatory domain.
*/
-enum iwl_reg_capa_flags {
- REG_CAPA_BF_CCD_LOW_BAND = BIT(0),
- REG_CAPA_BF_CCD_HIGH_BAND = BIT(1),
- REG_CAPA_160MHZ_ALLOWED = BIT(2),
- REG_CAPA_80MHZ_ALLOWED = BIT(3),
- REG_CAPA_MCS_8_ALLOWED = BIT(4),
- REG_CAPA_MCS_9_ALLOWED = BIT(5),
- REG_CAPA_40MHZ_FORBIDDEN = BIT(7),
- REG_CAPA_DC_HIGH_ENABLED = BIT(9),
- REG_CAPA_11AX_DISABLED = BIT(10),
-};
+enum iwl_reg_capa_flags_v1 {
+ REG_CAPA_V1_BF_CCD_LOW_BAND = BIT(0),
+ REG_CAPA_V1_BF_CCD_HIGH_BAND = BIT(1),
+ REG_CAPA_V1_160MHZ_ALLOWED = BIT(2),
+ REG_CAPA_V1_80MHZ_ALLOWED = BIT(3),
+ REG_CAPA_V1_MCS_8_ALLOWED = BIT(4),
+ REG_CAPA_V1_MCS_9_ALLOWED = BIT(5),
+ REG_CAPA_V1_40MHZ_FORBIDDEN = BIT(7),
+ REG_CAPA_V1_DC_HIGH_ENABLED = BIT(9),
+ REG_CAPA_V1_11AX_DISABLED = BIT(10),
+}; /* GEO_CHANNEL_CAPABILITIES_API_S_VER_1 */
/**
* enum iwl_reg_capa_flags_v2 - global flags applied for the whole regulatory
@@ -234,7 +234,31 @@ enum iwl_reg_capa_flags_v2 {
REG_CAPA_V2_WEATHER_DISABLED = BIT(7),
REG_CAPA_V2_40MHZ_ALLOWED = BIT(8),
REG_CAPA_V2_11AX_DISABLED = BIT(10),
-};
+}; /* GEO_CHANNEL_CAPABILITIES_API_S_VER_2 */
+
+/**
+ * enum iwl_reg_capa_flags_v4 - global flags applied for the whole regulatory
+ * domain.
+ * @REG_CAPA_V4_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed
+ * for this regulatory domain (valid only in 5Ghz).
+ * @REG_CAPA_V4_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed
+ * for this regulatory domain (valid only in 5Ghz).
+ * @REG_CAPA_V4_MCS_12_ALLOWED: 11ac with MCS 12 is allowed.
+ * @REG_CAPA_V4_MCS_13_ALLOWED: 11ac with MCS 13 is allowed.
+ * @REG_CAPA_V4_11BE_DISABLED: 11be is forbidden for this regulatory domain.
+ * @REG_CAPA_V4_11AX_DISABLED: 11ax is forbidden for this regulatory domain.
+ * @REG_CAPA_V4_320MHZ_ALLOWED: 11be channel with a width of 320Mhz is allowed
+ * for this regulatory domain (valid only in 5GHz).
+ */
+enum iwl_reg_capa_flags_v4 {
+ REG_CAPA_V4_160MHZ_ALLOWED = BIT(3),
+ REG_CAPA_V4_80MHZ_ALLOWED = BIT(4),
+ REG_CAPA_V4_MCS_12_ALLOWED = BIT(5),
+ REG_CAPA_V4_MCS_13_ALLOWED = BIT(6),
+ REG_CAPA_V4_11BE_DISABLED = BIT(8),
+ REG_CAPA_V4_11AX_DISABLED = BIT(13),
+ REG_CAPA_V4_320MHZ_ALLOWED = BIT(16),
+}; /* GEO_CHANNEL_CAPABILITIES_API_S_VER_4 */
/*
* API v2 for reg_capa_flags is relevant from version 6 and onwards of the
@@ -242,23 +266,33 @@ enum iwl_reg_capa_flags_v2 {
*/
#define REG_CAPA_V2_RESP_VER 6
+/* API v4 for reg_capa_flags is relevant from version 8 and onwards of the
+ * MCC update command response.
+ */
+#define REG_CAPA_V4_RESP_VER 8
+
/**
* struct iwl_reg_capa - struct for global regulatory capabilities, Used for
* handling the different APIs of reg_capa_flags.
*
* @allow_40mhz: 11n channel with a width of 40Mhz is allowed
- * for this regulatory domain (valid only in 5Ghz).
+ * for this regulatory domain.
* @allow_80mhz: 11ac channel with a width of 80Mhz is allowed
- * for this regulatory domain (valid only in 5Ghz).
+ * for this regulatory domain (valid only in 5 and 6 Ghz).
* @allow_160mhz: 11ac channel with a width of 160Mhz is allowed
- * for this regulatory domain (valid only in 5Ghz).
+ * for this regulatory domain (valid only in 5 and 6 Ghz).
+ * @allow_320mhz: 11be channel with a width of 320Mhz is allowed
+ * for this regulatory domain (valid only in 6 Ghz).
* @disable_11ax: 11ax is forbidden for this regulatory domain.
+ * @disable_11be: 11be is forbidden for this regulatory domain.
*/
struct iwl_reg_capa {
- u16 allow_40mhz;
- u16 allow_80mhz;
- u16 allow_160mhz;
- u16 disable_11ax;
+ bool allow_40mhz;
+ bool allow_80mhz;
+ bool allow_160mhz;
+ bool allow_320mhz;
+ bool disable_11ax;
+ bool disable_11be;
};
static inline void iwl_nvm_print_channel_flags(struct device *dev, u32 level,
@@ -464,6 +498,9 @@ static void iwl_init_vht_hw_capab(struct iwl_trans *trans,
IEEE80211_VHT_MAX_AMPDU_1024K <<
IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT;
+ if (!trans->cfg->ht_params->stbc)
+ vht_cap->cap &= ~IEEE80211_VHT_CAP_RXSTBC_MASK;
+
if (data->vht160_supported)
vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ |
IEEE80211_VHT_CAP_SHORT_GI_160;
@@ -479,7 +516,7 @@ static void iwl_init_vht_hw_capab(struct iwl_trans *trans,
num_tx_ants = 1;
}
- if (num_tx_ants > 1)
+ if (trans->cfg->ht_params->stbc && num_tx_ants > 1)
vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
else
vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN;
@@ -643,8 +680,7 @@ static const struct ieee80211_sband_iftype_data iwl_he_eht_capa[] = {
IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK,
.phy_cap_info[1] =
IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK |
- IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK |
- IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK,
+ IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK,
.phy_cap_info[3] =
IEEE80211_EHT_PHY_CAP3_NG_16_SU_FEEDBACK |
IEEE80211_EHT_PHY_CAP3_NG_16_MU_FEEDBACK |
@@ -853,6 +889,10 @@ iwl_nvm_fixup_sband_iftd(struct iwl_trans *trans,
const struct iwl_fw *fw)
{
bool is_ap = iftype_data->types_mask & BIT(NL80211_IFTYPE_AP);
+ bool no_320;
+
+ no_320 = !trans->trans_cfg->integrated &&
+ trans->pcie_link_speed < PCI_EXP_LNKSTA_CLS_8_0GB;
if (!data->sku_cap_11be_enable || iwlwifi_mod_params.disable_11be)
iftype_data->eht_cap.has_eht = false;
@@ -879,8 +919,12 @@ iwl_nvm_fixup_sband_iftd(struct iwl_trans *trans,
IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK);
break;
case NL80211_BAND_6GHZ:
- iftype_data->eht_cap.eht_cap_elem.phy_cap_info[0] |=
- IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ;
+ if (!no_320) {
+ iftype_data->eht_cap.eht_cap_elem.phy_cap_info[0] |=
+ IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ;
+ iftype_data->eht_cap.eht_cap_elem.phy_cap_info[1] |=
+ IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK;
+ }
fallthrough;
case NL80211_BAND_5GHZ:
iftype_data->he_cap.he_cap_elem.phy_cap_info[0] |=
@@ -975,6 +1019,8 @@ iwl_nvm_fixup_sband_iftd(struct iwl_trans *trans,
iftype_data->eht_cap.eht_cap_elem.phy_cap_info[6] &=
~(IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_MASK |
IEEE80211_EHT_PHY_CAP6_EHT_DUP_6GHZ_SUPP);
+ iftype_data->eht_cap.eht_cap_elem.phy_cap_info[5] |=
+ IEEE80211_EHT_PHY_CAP5_SUPP_EXTRA_EHT_LTF;
}
if (fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_BROADCAST_TWT))
@@ -986,6 +1032,13 @@ iwl_nvm_fixup_sband_iftd(struct iwl_trans *trans,
iftype_data->vendor_elems.data = iwl_vendor_caps;
iftype_data->vendor_elems.len = ARRAY_SIZE(iwl_vendor_caps);
}
+
+ if (!trans->cfg->ht_params->stbc) {
+ iftype_data->he_cap.he_cap_elem.phy_cap_info[2] &=
+ ~IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ;
+ iftype_data->he_cap.he_cap_elem.phy_cap_info[7] &=
+ ~IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ;
+ }
}
static void iwl_init_he_hw_capab(struct iwl_trans *trans,
@@ -1521,27 +1574,41 @@ static u32 iwl_nvm_get_regdom_bw_flags(const u16 *nvm_chan,
if (!reg_capa.allow_160mhz)
flags |= NL80211_RRF_NO_160MHZ;
+
+ if (!reg_capa.allow_320mhz)
+ flags |= NL80211_RRF_NO_320MHZ;
}
+
if (reg_capa.disable_11ax)
flags |= NL80211_RRF_NO_HE;
+ if (reg_capa.disable_11be)
+ flags |= NL80211_RRF_NO_EHT;
+
return flags;
}
-static struct iwl_reg_capa iwl_get_reg_capa(u16 flags, u8 resp_ver)
+static struct iwl_reg_capa iwl_get_reg_capa(u32 flags, u8 resp_ver)
{
- struct iwl_reg_capa reg_capa;
-
- if (resp_ver >= REG_CAPA_V2_RESP_VER) {
+ struct iwl_reg_capa reg_capa = {};
+
+ if (resp_ver >= REG_CAPA_V4_RESP_VER) {
+ reg_capa.allow_40mhz = true;
+ reg_capa.allow_80mhz = flags & REG_CAPA_V4_80MHZ_ALLOWED;
+ reg_capa.allow_160mhz = flags & REG_CAPA_V4_160MHZ_ALLOWED;
+ reg_capa.allow_320mhz = flags & REG_CAPA_V4_320MHZ_ALLOWED;
+ reg_capa.disable_11ax = flags & REG_CAPA_V4_11AX_DISABLED;
+ reg_capa.disable_11be = flags & REG_CAPA_V4_11BE_DISABLED;
+ } else if (resp_ver >= REG_CAPA_V2_RESP_VER) {
reg_capa.allow_40mhz = flags & REG_CAPA_V2_40MHZ_ALLOWED;
reg_capa.allow_80mhz = flags & REG_CAPA_V2_80MHZ_ALLOWED;
reg_capa.allow_160mhz = flags & REG_CAPA_V2_160MHZ_ALLOWED;
reg_capa.disable_11ax = flags & REG_CAPA_V2_11AX_DISABLED;
} else {
- reg_capa.allow_40mhz = !(flags & REG_CAPA_40MHZ_FORBIDDEN);
- reg_capa.allow_80mhz = flags & REG_CAPA_80MHZ_ALLOWED;
- reg_capa.allow_160mhz = flags & REG_CAPA_160MHZ_ALLOWED;
- reg_capa.disable_11ax = flags & REG_CAPA_11AX_DISABLED;
+ reg_capa.allow_40mhz = !(flags & REG_CAPA_V1_40MHZ_FORBIDDEN);
+ reg_capa.allow_80mhz = flags & REG_CAPA_V1_80MHZ_ALLOWED;
+ reg_capa.allow_160mhz = flags & REG_CAPA_V1_160MHZ_ALLOWED;
+ reg_capa.disable_11ax = flags & REG_CAPA_V1_11AX_DISABLED;
}
return reg_capa;
}
@@ -1549,7 +1616,7 @@ static struct iwl_reg_capa iwl_get_reg_capa(u16 flags, u8 resp_ver)
struct ieee80211_regdomain *
iwl_parse_nvm_mcc_info(struct device *dev, const struct iwl_cfg *cfg,
int num_of_ch, __le32 *channels, u16 fw_mcc,
- u16 geo_info, u16 cap, u8 resp_ver)
+ u16 geo_info, u32 cap, u8 resp_ver)
{
int ch_idx;
u16 ch_flags;
diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.h b/drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.h
index e01f7751cf11..c79f72d54482 100644
--- a/drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.h
+++ b/drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/*
- * Copyright (C) 2005-2015, 2018-2021 Intel Corporation
+ * Copyright (C) 2005-2015, 2018-2022 Intel Corporation
* Copyright (C) 2016-2017 Intel Deutschland GmbH
*/
#ifndef __iwl_nvm_parse_h__
@@ -50,7 +50,7 @@ iwl_parse_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg,
struct ieee80211_regdomain *
iwl_parse_nvm_mcc_info(struct device *dev, const struct iwl_cfg *cfg,
int num_of_ch, __le32 *channels, u16 fw_mcc,
- u16 geo_info, u16 cap, u8 resp_ver);
+ u16 geo_info, u32 cap, u8 resp_ver);
/**
* struct iwl_nvm_section - describes an NVM section in memory.
diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-prph.h b/drivers/net/wireless/intel/iwlwifi/iwl-prph.h
index 0dfe00eae05d..6dd381ff0f9e 100644
--- a/drivers/net/wireless/intel/iwlwifi/iwl-prph.h
+++ b/drivers/net/wireless/intel/iwlwifi/iwl-prph.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/*
- * Copyright (C) 2005-2014, 2018-2022 Intel Corporation
+ * Copyright (C) 2005-2014, 2018-2023 Intel Corporation
* Copyright (C) 2013-2015 Intel Mobile Communications GmbH
* Copyright (C) 2016 Intel Deutschland GmbH
*/
@@ -486,6 +486,10 @@ enum {
#define FSEQ_ALIVE_TOKEN 0xA340F0
#define FSEQ_CNVI_ID 0xA3408C
#define FSEQ_CNVR_ID 0xA34090
+#define FSEQ_PREV_CNVIO_INIT_VERSION 0xA34084
+#define FSEQ_WIFI_FSEQ_VERSION 0xA34040
+#define FSEQ_BT_FSEQ_VERSION 0xA34044
+#define FSEQ_CLASS_TP_VERSION 0xA34078
#define IWL_D3_SLEEP_STATUS_SUSPEND 0xD3
#define IWL_D3_SLEEP_STATUS_RESUME 0xD0
diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-trans.h b/drivers/net/wireless/intel/iwlwifi/iwl-trans.h
index 9f1228b5a384..d02943d0ea62 100644
--- a/drivers/net/wireless/intel/iwlwifi/iwl-trans.h
+++ b/drivers/net/wireless/intel/iwlwifi/iwl-trans.h
@@ -459,6 +459,24 @@ struct iwl_trans_rxq_dma_data {
u64 ur_bd_cb;
};
+/* maximal number of DRAM MAP entries supported by FW */
+#define IPC_DRAM_MAP_ENTRY_NUM_MAX 64
+
+/**
+ * struct iwl_pnvm_image - contains info about the parsed pnvm image
+ * @chunks: array of pointers to pnvm payloads and their sizes
+ * @n_chunks: the number of the pnvm payloads.
+ * @version: the version of the loaded PNVM image
+ */
+struct iwl_pnvm_image {
+ struct {
+ const void *data;
+ u32 len;
+ } chunks[IPC_DRAM_MAP_ENTRY_NUM_MAX];
+ u32 n_chunks;
+ u32 version;
+};
+
/**
* struct iwl_trans_ops - transport specific operations
*
@@ -541,8 +559,11 @@ struct iwl_trans_rxq_dma_data {
* Note that the transport must fill in the proper file headers.
* @debugfs_cleanup: used in the driver unload flow to make a proper cleanup
* of the trans debugfs
+ * @load_pnvm: save the pnvm data in DRAM
* @set_pnvm: set the pnvm data in the prph scratch buffer, inside the
* context info.
+ * @load_reduce_power: copy reduce power table to the corresponding DRAM memory
+ * @set_reduce_power: set reduce power table addresses in the sratch buffer
* @interrupts: disable/enable interrupts to transport
*/
struct iwl_trans_ops {
@@ -614,9 +635,17 @@ struct iwl_trans_ops {
void *sanitize_ctx);
void (*debugfs_cleanup)(struct iwl_trans *trans);
void (*sync_nmi)(struct iwl_trans *trans);
- int (*set_pnvm)(struct iwl_trans *trans, const void *data, u32 len);
- int (*set_reduce_power)(struct iwl_trans *trans,
- const void *data, u32 len);
+ int (*load_pnvm)(struct iwl_trans *trans,
+ const struct iwl_pnvm_image *pnvm_payloads,
+ const struct iwl_ucode_capabilities *capa);
+ void (*set_pnvm)(struct iwl_trans *trans,
+ const struct iwl_ucode_capabilities *capa);
+ int (*load_reduce_power)(struct iwl_trans *trans,
+ const struct iwl_pnvm_image *payloads,
+ const struct iwl_ucode_capabilities *capa);
+ void (*set_reduce_power)(struct iwl_trans *trans,
+ const struct iwl_ucode_capabilities *capa);
+
void (*interrupts)(struct iwl_trans *trans, bool enable);
int (*imr_dma_data)(struct iwl_trans *trans,
u32 dst_addr, u64 src_addr,
@@ -705,6 +734,19 @@ struct iwl_dram_data {
};
/**
+ * @drams: array of several DRAM areas that contains the pnvm and power
+ * reduction table payloads.
+ * @n_regions: number of DRAM regions that were allocated
+ * @prph_scratch_mem_desc: points to a structure allocated in dram,
+ * designed to show FW where all the payloads are.
+ */
+struct iwl_dram_regions {
+ struct iwl_dram_data drams[IPC_DRAM_MAP_ENTRY_NUM_MAX];
+ struct iwl_dram_data prph_scratch_mem_desc;
+ u8 n_regions;
+};
+
+/**
* struct iwl_fw_mon - fw monitor per allocation id
* @num_frags: number of fragments
* @frags: an array of DRAM buffer fragments
@@ -1004,6 +1046,8 @@ struct iwl_trans_txqs {
* @hw_rev_step: The mac step of the HW
* @pm_support: set to true in start_hw if link pm is supported
* @ltr_enabled: set to true if the LTR is enabled
+ * @fail_to_parse_pnvm_image: set to true if pnvm parsing failed
+ * @failed_to_load_reduce_power_image: set to true if pnvm loading failed
* @wide_cmd_header: true when ucode supports wide command header format
* @wait_command_queue: wait queue for sync commands
* @num_rx_queues: number of RX queues allocated by the transport;
@@ -1023,6 +1067,8 @@ struct iwl_trans_txqs {
* @iwl_trans_txqs: transport tx queues data.
* @mbx_addr_0_step: step address data 0
* @mbx_addr_1_step: step address data 1
+ * @pcie_link_speed: current PCIe link speed (%PCI_EXP_LNKSTA_CLS_*),
+ * only valid for discrete (not integrated) NICs
*/
struct iwl_trans {
bool csme_own;
@@ -1051,7 +1097,9 @@ struct iwl_trans {
bool pm_support;
bool ltr_enabled;
u8 pnvm_loaded:1;
+ u8 fail_to_parse_pnvm_image:1;
u8 reduce_power_loaded:1;
+ u8 failed_to_load_reduce_power_image:1;
const struct iwl_hcmd_arr *command_groups;
int command_groups_size;
@@ -1083,6 +1131,8 @@ struct iwl_trans {
u32 mbx_addr_0_step;
u32 mbx_addr_1_step;
+ u8 pcie_link_speed;
+
/* pointer to trans specific struct */
/*Ensure that this pointer will always be aligned to sizeof pointer */
char trans_specific[] __aligned(sizeof(void *));
@@ -1160,7 +1210,7 @@ static inline int iwl_trans_d3_suspend(struct iwl_trans *trans, bool test,
{
might_sleep();
if (!trans->ops->d3_suspend)
- return 0;
+ return -EOPNOTSUPP;
return trans->ops->d3_suspend(trans, test, reset);
}
@@ -1171,7 +1221,7 @@ static inline int iwl_trans_d3_resume(struct iwl_trans *trans,
{
might_sleep();
if (!trans->ops->d3_resume)
- return 0;
+ return -EOPNOTSUPP;
return trans->ops->d3_resume(trans, status, test, reset);
}
@@ -1515,33 +1565,34 @@ static inline void iwl_trans_sync_nmi(struct iwl_trans *trans)
void iwl_trans_sync_nmi_with_addr(struct iwl_trans *trans, u32 inta_addr,
u32 sw_err_bit);
-static inline int iwl_trans_set_pnvm(struct iwl_trans *trans,
- const void *data, u32 len)
+static inline int iwl_trans_load_pnvm(struct iwl_trans *trans,
+ const struct iwl_pnvm_image *pnvm_data,
+ const struct iwl_ucode_capabilities *capa)
{
- if (trans->ops->set_pnvm) {
- int ret = trans->ops->set_pnvm(trans, data, len);
-
- if (ret)
- return ret;
- }
-
- trans->pnvm_loaded = true;
-
- return 0;
+ return trans->ops->load_pnvm(trans, pnvm_data, capa);
}
-static inline int iwl_trans_set_reduce_power(struct iwl_trans *trans,
- const void *data, u32 len)
+static inline void iwl_trans_set_pnvm(struct iwl_trans *trans,
+ const struct iwl_ucode_capabilities *capa)
{
- if (trans->ops->set_reduce_power) {
- int ret = trans->ops->set_reduce_power(trans, data, len);
+ if (trans->ops->set_pnvm)
+ trans->ops->set_pnvm(trans, capa);
+}
- if (ret)
- return ret;
- }
+static inline int iwl_trans_load_reduce_power
+ (struct iwl_trans *trans,
+ const struct iwl_pnvm_image *payloads,
+ const struct iwl_ucode_capabilities *capa)
+{
+ return trans->ops->load_reduce_power(trans, payloads, capa);
+}
- trans->reduce_power_loaded = true;
- return 0;
+static inline void
+iwl_trans_set_reduce_power(struct iwl_trans *trans,
+ const struct iwl_ucode_capabilities *capa)
+{
+ if (trans->ops->set_reduce_power)
+ trans->ops->set_reduce_power(trans, capa);
}
static inline bool iwl_trans_dbg_ini_valid(struct iwl_trans *trans)
@@ -1566,6 +1617,11 @@ struct iwl_trans *iwl_trans_alloc(unsigned int priv_size,
int iwl_trans_init(struct iwl_trans *trans);
void iwl_trans_free(struct iwl_trans *trans);
+static inline bool iwl_trans_is_hw_error_value(u32 val)
+{
+ return ((val & ~0xf) == 0xa5a5a5a0) || ((val & ~0xf) == 0x5a5a5a50);
+}
+
/*****************************************************
* driver (transport) register/unregister functions
******************************************************/
diff --git a/drivers/net/wireless/intel/iwlwifi/mei/main.c b/drivers/net/wireless/intel/iwlwifi/mei/main.c
index 0a29fb013005..54445f39fd55 100644
--- a/drivers/net/wireless/intel/iwlwifi/mei/main.c
+++ b/drivers/net/wireless/intel/iwlwifi/mei/main.c
@@ -1791,9 +1791,8 @@ int iwl_mei_register(void *priv, const struct iwl_mei_ops *ops)
if (iwl_mei_is_connected()) {
if (mei->amt_enabled)
iwl_mei_send_sap_msg(mei->cldev,
- SAP_MSG_NOTIF_WIFIDR_UP,
- false);
- ops->rfkill(priv, mei->link_prot_state);
+ SAP_MSG_NOTIF_WIFIDR_UP);
+ ops->rfkill(priv, mei->link_prot_state, false);
}
}
ret = 0;
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/binding.c b/drivers/net/wireless/intel/iwlwifi/mvm/binding.c
index ef50ccabcc73..458b97930059 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/binding.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/binding.c
@@ -32,7 +32,7 @@ static int iwl_mvm_binding_cmd(struct iwl_mvm *mvm, u32 action,
if (fw_has_capa(&mvm->fw->ucode_capa,
IWL_UCODE_TLV_CAPA_BINDING_CDB_SUPPORT)) {
size = sizeof(cmd);
- cmd.lmac_id = cpu_to_le32(iwl_mvm_get_lmac_id(mvm->fw,
+ cmd.lmac_id = cpu_to_le32(iwl_mvm_get_lmac_id(mvm,
phyctxt->channel->band));
} else {
size = IWL_BINDING_CMD_SIZE_V1;
@@ -164,3 +164,11 @@ int iwl_mvm_binding_remove_vif(struct iwl_mvm *mvm, struct ieee80211_vif *vif)
return ret;
}
+
+u32 iwl_mvm_get_lmac_id(struct iwl_mvm *mvm, enum nl80211_band band)
+{
+ if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_CDB_SUPPORT) ||
+ band == NL80211_BAND_2GHZ)
+ return IWL_LMAC_24G_INDEX;
+ return IWL_LMAC_5G_INDEX;
+}
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/constants.h b/drivers/net/wireless/intel/iwlwifi/mvm/constants.h
index c604f9f39b24..243eccc68cb0 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/constants.h
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/constants.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/*
* Copyright (C) 2013-2015 Intel Mobile Communications GmbH
- * Copyright (C) 2013-2014, 2018-2021 Intel Corporation
+ * Copyright (C) 2013-2014, 2018-2023 Intel Corporation
* Copyright (C) 2015 Intel Deutschland GmbH
*/
#ifndef __MVM_CONSTANTS_H
@@ -109,10 +109,6 @@
#define IWL_MVM_USE_TWT true
#define IWL_MVM_AMPDU_CONSEC_DROPS_DELBA 20
#define IWL_MVM_USE_NSSN_SYNC 0
-#define IWL_MVM_PHY_FILTER_CHAIN_A 0
-#define IWL_MVM_PHY_FILTER_CHAIN_B 0
-#define IWL_MVM_PHY_FILTER_CHAIN_C 0
-#define IWL_MVM_PHY_FILTER_CHAIN_D 0
#define IWL_MVM_FTM_INITIATOR_ENABLE_SMOOTH false
#define IWL_MVM_FTM_INITIATOR_SMOOTH_ALPHA 40
/* 20016 pSec is 6 meter RTT, meaning 3 meter range */
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/d3.c b/drivers/net/wireless/intel/iwlwifi/mvm/d3.c
index 6d1007f24b4a..f6488b4bbe68 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/d3.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/d3.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
- * Copyright (C) 2012-2014, 2018-2022 Intel Corporation
+ * Copyright (C) 2012-2014, 2018-2023 Intel Corporation
* Copyright (C) 2013-2015 Intel Mobile Communications GmbH
* Copyright (C) 2016-2017 Intel Deutschland GmbH
*/
@@ -1380,6 +1380,14 @@ int iwl_mvm_suspend(struct ieee80211_hw *hw, struct cfg80211_wowlan *wowlan)
return __iwl_mvm_suspend(hw, wowlan, false);
}
+struct iwl_multicast_key_data {
+ u8 key[WOWLAN_KEY_MAX_SIZE];
+ u8 len;
+ u8 flags;
+ u8 id;
+ u8 ipn[6];
+};
+
/* converted data from the different status responses */
struct iwl_wowlan_status_data {
u64 replay_ctr;
@@ -1398,7 +1406,8 @@ struct iwl_wowlan_status_data {
u8 key[WOWLAN_KEY_MAX_SIZE];
u8 len;
u8 flags;
- } gtk;
+ u8 id;
+ } gtk[WOWLAN_GTK_KEYS_NUM];
struct {
/*
@@ -1428,12 +1437,7 @@ struct iwl_wowlan_status_data {
} tkip, aes;
} ptk;
- struct {
- u64 ipn;
- u8 key[WOWLAN_KEY_MAX_SIZE];
- u8 len;
- u8 flags;
- } igtk;
+ struct iwl_multicast_key_data igtk;
u8 *wake_packet;
};
@@ -1758,7 +1762,7 @@ static void iwl_mvm_set_key_rx_seq(struct ieee80211_key_conf *key,
s8 new_key_id = -1;
if (status->num_of_gtk_rekeys)
- new_key_id = status->gtk.flags &
+ new_key_id = status->gtk[0].flags &
IWL_WOWLAN_GTK_IDX_MASK;
/* Don't install a new key's value to an old key */
@@ -1777,20 +1781,18 @@ static void iwl_mvm_set_key_rx_seq(struct ieee80211_key_conf *key,
struct iwl_mvm_d3_gtk_iter_data {
struct iwl_mvm *mvm;
struct iwl_wowlan_status_data *status;
- void *last_gtk;
- u32 cipher;
- bool find_phase, unhandled_cipher;
+ u32 gtk_cipher, igtk_cipher;
+ bool unhandled_cipher, igtk_support;
int num_keys;
};
-static void iwl_mvm_d3_update_keys(struct ieee80211_hw *hw,
- struct ieee80211_vif *vif,
- struct ieee80211_sta *sta,
- struct ieee80211_key_conf *key,
- void *_data)
+static void iwl_mvm_d3_find_last_keys(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif,
+ struct ieee80211_sta *sta,
+ struct ieee80211_key_conf *key,
+ void *_data)
{
struct iwl_mvm_d3_gtk_iter_data *data = _data;
- struct iwl_wowlan_status_data *status = data->status;
if (data->unhandled_cipher)
return;
@@ -1805,51 +1807,230 @@ static void iwl_mvm_d3_update_keys(struct ieee80211_hw *hw,
case WLAN_CIPHER_SUITE_GCMP_256:
case WLAN_CIPHER_SUITE_TKIP:
/* we support these */
+ data->gtk_cipher = key->cipher;
+ break;
+ case WLAN_CIPHER_SUITE_BIP_GMAC_128:
+ case WLAN_CIPHER_SUITE_BIP_GMAC_256:
+ case WLAN_CIPHER_SUITE_BIP_CMAC_256:
+ case WLAN_CIPHER_SUITE_AES_CMAC:
+ /* we support these */
+ if (data->igtk_support &&
+ (key->keyidx == 4 || key->keyidx == 5)) {
+ data->igtk_cipher = key->cipher;
+ } else {
+ data->unhandled_cipher = true;
+ return;
+ }
break;
default:
- /* everything else (even CMAC for MFP) - disconnect from AP */
+ /* everything else - disconnect from AP */
data->unhandled_cipher = true;
return;
}
data->num_keys++;
+}
- /*
- * pairwise key - update sequence counters only;
- * note that this assumes no TDLS sessions are active
- */
- if (sta) {
- if (data->find_phase)
- return;
+static void
+iwl_mvm_d3_set_igtk_bigtk_ipn(const struct iwl_multicast_key_data *key,
+ struct ieee80211_key_seq *seq, u32 cipher)
+{
+ switch (cipher) {
+ case WLAN_CIPHER_SUITE_BIP_GMAC_128:
+ case WLAN_CIPHER_SUITE_BIP_GMAC_256:
+ BUILD_BUG_ON(sizeof(seq->aes_gmac.pn) != sizeof(key->ipn));
+ memcpy(seq->aes_gmac.pn, key->ipn, sizeof(seq->aes_gmac.pn));
+ break;
+ case WLAN_CIPHER_SUITE_BIP_CMAC_256:
+ BUILD_BUG_ON(sizeof(seq->aes_cmac.pn) != sizeof(key->ipn));
+ memcpy(seq->aes_cmac.pn, key->ipn, sizeof(seq->aes_cmac.pn));
+ break;
+ }
+}
+
+static void iwl_mvm_d3_update_keys(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif,
+ struct ieee80211_sta *sta,
+ struct ieee80211_key_conf *key,
+ void *_data)
+{
+ struct iwl_mvm_d3_gtk_iter_data *data = _data;
+ struct iwl_wowlan_status_data *status = data->status;
+ s8 keyidx;
+
+ if (data->unhandled_cipher)
+ return;
- switch (key->cipher) {
- case WLAN_CIPHER_SUITE_CCMP:
- case WLAN_CIPHER_SUITE_GCMP:
- case WLAN_CIPHER_SUITE_GCMP_256:
+ switch (key->cipher) {
+ case WLAN_CIPHER_SUITE_WEP40:
+ case WLAN_CIPHER_SUITE_WEP104:
+ /* ignore WEP completely, nothing to do */
+ return;
+ case WLAN_CIPHER_SUITE_CCMP:
+ case WLAN_CIPHER_SUITE_GCMP:
+ case WLAN_CIPHER_SUITE_GCMP_256:
+ if (sta) {
atomic64_set(&key->tx_pn, status->ptk.aes.tx_pn);
iwl_mvm_set_aes_ptk_rx_seq(data->mvm, status, sta, key);
- break;
- case WLAN_CIPHER_SUITE_TKIP:
+ return;
+ }
+ fallthrough;
+ case WLAN_CIPHER_SUITE_TKIP:
+ if (sta) {
atomic64_set(&key->tx_pn, status->ptk.tkip.tx_pn);
iwl_mvm_set_key_rx_seq_tids(key, status->ptk.tkip.seq);
- break;
+ return;
}
+ keyidx = key->keyidx;
+ /* The current key is always sent by the FW, even if it wasn't
+ * rekeyed during D3.
+ * We remove an existing key if it has the same index as
+ * a new key
+ */
+ if (status->num_of_gtk_rekeys &&
+ ((status->gtk[0].len && keyidx == status->gtk[0].id) ||
+ (status->gtk[1].len && keyidx == status->gtk[1].id))) {
+ ieee80211_remove_key(key);
+ } else {
+ iwl_mvm_set_key_rx_seq(key, data->status, false);
+ }
+ break;
+ case WLAN_CIPHER_SUITE_BIP_GMAC_128:
+ case WLAN_CIPHER_SUITE_BIP_GMAC_256:
+ case WLAN_CIPHER_SUITE_BIP_CMAC_256:
+ case WLAN_CIPHER_SUITE_AES_CMAC:
+ if (key->keyidx == 4 || key->keyidx == 5) {
+ /* remove rekeyed key */
+ if (status->num_of_gtk_rekeys) {
+ ieee80211_remove_key(key);
+ } else {
+ struct ieee80211_key_seq seq;
- /* that's it for this key */
- return;
+ iwl_mvm_d3_set_igtk_bigtk_ipn(&status->igtk,
+ &seq,
+ key->cipher);
+ ieee80211_set_key_rx_seq(key, 0, &seq);
+ }
+ }
}
+}
- if (data->find_phase) {
- data->last_gtk = key;
- data->cipher = key->cipher;
- return;
+static bool iwl_mvm_gtk_rekey(struct iwl_wowlan_status_data *status,
+ struct ieee80211_vif *vif,
+ struct iwl_mvm *mvm, u32 gtk_cipher)
+{
+ int i;
+ struct ieee80211_key_conf *key;
+ struct {
+ struct ieee80211_key_conf conf;
+ u8 key[32];
+ } conf = {
+ .conf.cipher = gtk_cipher,
+ };
+
+ BUILD_BUG_ON(WLAN_KEY_LEN_CCMP != WLAN_KEY_LEN_GCMP);
+ BUILD_BUG_ON(sizeof(conf.key) < WLAN_KEY_LEN_CCMP);
+ BUILD_BUG_ON(sizeof(conf.key) < WLAN_KEY_LEN_GCMP_256);
+ BUILD_BUG_ON(sizeof(conf.key) < WLAN_KEY_LEN_TKIP);
+ BUILD_BUG_ON(sizeof(conf.key) < sizeof(status->gtk[0].key));
+
+ switch (gtk_cipher) {
+ case WLAN_CIPHER_SUITE_CCMP:
+ case WLAN_CIPHER_SUITE_GCMP:
+ conf.conf.keylen = WLAN_KEY_LEN_CCMP;
+ break;
+ case WLAN_CIPHER_SUITE_GCMP_256:
+ conf.conf.keylen = WLAN_KEY_LEN_GCMP_256;
+ break;
+ case WLAN_CIPHER_SUITE_TKIP:
+ conf.conf.keylen = WLAN_KEY_LEN_TKIP;
+ break;
+ default:
+ WARN_ON(1);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(status->gtk); i++) {
+ if (!status->gtk[i].len)
+ continue;
+
+ conf.conf.keyidx = status->gtk[i].id;
+ IWL_DEBUG_WOWLAN(mvm,
+ "Received from FW GTK cipher %d, key index %d\n",
+ conf.conf.cipher, conf.conf.keyidx);
+ memcpy(conf.conf.key, status->gtk[i].key,
+ sizeof(status->gtk[i].key));
+
+ key = ieee80211_gtk_rekey_add(vif, &conf.conf);
+ if (IS_ERR(key))
+ return false;
+ iwl_mvm_set_key_rx_seq_idx(key, status, i);
}
- if (data->status->num_of_gtk_rekeys)
- ieee80211_remove_key(key);
+ return true;
+}
+
+static bool
+iwl_mvm_d3_igtk_bigtk_rekey_add(struct iwl_wowlan_status_data *status,
+ struct ieee80211_vif *vif, u32 cipher,
+ struct iwl_multicast_key_data *key_data)
+{
+ struct ieee80211_key_conf *key_config;
+ struct {
+ struct ieee80211_key_conf conf;
+ u8 key[WOWLAN_KEY_MAX_SIZE];
+ } conf = {
+ .conf.cipher = cipher,
+ .conf.keyidx = key_data->id,
+ };
+ struct ieee80211_key_seq seq;
+
+ if (!key_data->len)
+ return true;
+
+ iwl_mvm_d3_set_igtk_bigtk_ipn(key_data, &seq, conf.conf.cipher);
+
+ switch (cipher) {
+ case WLAN_CIPHER_SUITE_BIP_GMAC_128:
+ conf.conf.keylen = WLAN_KEY_LEN_BIP_GMAC_128;
+ break;
+ case WLAN_CIPHER_SUITE_BIP_GMAC_256:
+ conf.conf.keylen = WLAN_KEY_LEN_BIP_GMAC_256;
+ break;
+ case WLAN_CIPHER_SUITE_AES_CMAC:
+ conf.conf.keylen = WLAN_KEY_LEN_AES_CMAC;
+ break;
+ case WLAN_CIPHER_SUITE_BIP_CMAC_256:
+ conf.conf.keylen = WLAN_KEY_LEN_BIP_CMAC_256;
+ break;
+ default:
+ WARN_ON(1);
+ }
+ BUILD_BUG_ON(sizeof(conf.key) < sizeof(key_data->key));
+ memcpy(conf.conf.key, key_data->key, conf.conf.keylen);
+
+ key_config = ieee80211_gtk_rekey_add(vif, &conf.conf);
+ if (IS_ERR(key_config))
+ return false;
+ ieee80211_set_key_rx_seq(key_config, 0, &seq);
+ return true;
+}
+
+static int iwl_mvm_lookup_wowlan_status_ver(struct iwl_mvm *mvm)
+{
+ u8 notif_ver;
+
+ if (!fw_has_api(&mvm->fw->ucode_capa,
+ IWL_UCODE_TLV_API_WOWLAN_KEY_MATERIAL))
+ return 6;
+
+ /* default to 7 (when we have IWL_UCODE_TLV_API_WOWLAN_KEY_MATERIAL) */
+ notif_ver = iwl_fw_lookup_notif_ver(mvm->fw, LONG_GROUP,
+ WOWLAN_GET_STATUSES, 0);
+ if (!notif_ver)
+ notif_ver = iwl_fw_lookup_notif_ver(mvm->fw, LEGACY_GROUP,
+ WOWLAN_GET_STATUSES, 7);
- if (data->last_gtk == key)
- iwl_mvm_set_key_rx_seq(key, data->status, false);
+ return notif_ver;
}
static bool iwl_mvm_setup_connection_keep(struct iwl_mvm *mvm,
@@ -1871,71 +2052,41 @@ static bool iwl_mvm_setup_connection_keep(struct iwl_mvm *mvm,
if (status->wakeup_reasons & disconnection_reasons)
return false;
+ if (iwl_mvm_lookup_wowlan_status_ver(mvm) > 6 ||
+ iwl_fw_lookup_notif_ver(mvm->fw, PROT_OFFLOAD_GROUP,
+ WOWLAN_INFO_NOTIFICATION,
+ 0))
+ gtkdata.igtk_support = true;
+
/* find last GTK that we used initially, if any */
- gtkdata.find_phase = true;
ieee80211_iter_keys(mvm->hw, vif,
- iwl_mvm_d3_update_keys, &gtkdata);
+ iwl_mvm_d3_find_last_keys, &gtkdata);
/* not trying to keep connections with MFP/unhandled ciphers */
if (gtkdata.unhandled_cipher)
return false;
if (!gtkdata.num_keys)
goto out;
- if (!gtkdata.last_gtk)
- return false;
/*
* invalidate all other GTKs that might still exist and update
* the one that we used
*/
- gtkdata.find_phase = false;
ieee80211_iter_keys(mvm->hw, vif,
iwl_mvm_d3_update_keys, &gtkdata);
- IWL_DEBUG_WOWLAN(mvm, "num of GTK rekeying %d\n",
- status->num_of_gtk_rekeys);
if (status->num_of_gtk_rekeys) {
- struct ieee80211_key_conf *key;
- struct {
- struct ieee80211_key_conf conf;
- u8 key[32];
- } conf = {
- .conf.cipher = gtkdata.cipher,
- .conf.keyidx =
- status->gtk.flags & IWL_WOWLAN_GTK_IDX_MASK,
- };
- __be64 replay_ctr;
+ __be64 replay_ctr = cpu_to_be64(status->replay_ctr);
- IWL_DEBUG_WOWLAN(mvm,
- "Received from FW GTK cipher %d, key index %d\n",
- conf.conf.cipher, conf.conf.keyidx);
-
- BUILD_BUG_ON(WLAN_KEY_LEN_CCMP != WLAN_KEY_LEN_GCMP);
- BUILD_BUG_ON(sizeof(conf.key) < WLAN_KEY_LEN_CCMP);
- BUILD_BUG_ON(sizeof(conf.key) < WLAN_KEY_LEN_GCMP_256);
- BUILD_BUG_ON(sizeof(conf.key) < WLAN_KEY_LEN_TKIP);
- BUILD_BUG_ON(sizeof(conf.key) < sizeof(status->gtk.key));
+ IWL_DEBUG_WOWLAN(mvm, "num of GTK rekeying %d\n",
+ status->num_of_gtk_rekeys);
- memcpy(conf.conf.key, status->gtk.key, sizeof(status->gtk.key));
-
- switch (gtkdata.cipher) {
- case WLAN_CIPHER_SUITE_CCMP:
- case WLAN_CIPHER_SUITE_GCMP:
- conf.conf.keylen = WLAN_KEY_LEN_CCMP;
- break;
- case WLAN_CIPHER_SUITE_GCMP_256:
- conf.conf.keylen = WLAN_KEY_LEN_GCMP_256;
- break;
- case WLAN_CIPHER_SUITE_TKIP:
- conf.conf.keylen = WLAN_KEY_LEN_TKIP;
- break;
- }
-
- key = ieee80211_gtk_rekey_add(vif, &conf.conf);
- if (IS_ERR(key))
+ if (!iwl_mvm_gtk_rekey(status, vif, mvm, gtkdata.gtk_cipher))
return false;
- iwl_mvm_set_key_rx_seq(key, status, true);
- replay_ctr = cpu_to_be64(status->replay_ctr);
+ if (!iwl_mvm_d3_igtk_bigtk_rekey_add(status, vif,
+ gtkdata.igtk_cipher,
+ &status->igtk))
+ return false;
ieee80211_gtk_rekey_notify(vif, vif->bss_conf.bssid,
(void *)&replay_ctr, GFP_KERNEL);
@@ -1955,60 +2106,70 @@ out:
static void iwl_mvm_convert_gtk_v2(struct iwl_wowlan_status_data *status,
struct iwl_wowlan_gtk_status_v2 *data)
{
- BUILD_BUG_ON(sizeof(status->gtk.key) < sizeof(data->key));
+ BUILD_BUG_ON(sizeof(status->gtk[0].key) < sizeof(data->key));
BUILD_BUG_ON(NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY +
sizeof(data->tkip_mic_key) >
- sizeof(status->gtk.key));
+ sizeof(status->gtk[0].key));
- status->gtk.len = data->key_len;
- status->gtk.flags = data->key_flags;
+ status->gtk[0].len = data->key_len;
+ status->gtk[0].flags = data->key_flags;
- memcpy(status->gtk.key, data->key, sizeof(data->key));
+ memcpy(status->gtk[0].key, data->key, sizeof(data->key));
/* if it's as long as the TKIP encryption key, copy MIC key */
- if (status->gtk.len == NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY)
- memcpy(status->gtk.key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY,
+ if (status->gtk[0].len == NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY)
+ memcpy(status->gtk[0].key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY,
data->tkip_mic_key, sizeof(data->tkip_mic_key));
}
static void iwl_mvm_convert_gtk_v3(struct iwl_wowlan_status_data *status,
struct iwl_wowlan_gtk_status_v3 *data)
{
- /* The parts we need are identical in v2 and v3 */
-#define CHECK(_f) do { \
- BUILD_BUG_ON(offsetof(struct iwl_wowlan_gtk_status_v2, _f) != \
- offsetof(struct iwl_wowlan_gtk_status_v3, _f)); \
- BUILD_BUG_ON(offsetofend(struct iwl_wowlan_gtk_status_v2, _f) !=\
- offsetofend(struct iwl_wowlan_gtk_status_v3, _f)); \
-} while (0)
+ int data_idx, status_idx = 0;
- CHECK(key);
- CHECK(key_len);
- CHECK(key_flags);
- CHECK(tkip_mic_key);
-#undef CHECK
+ BUILD_BUG_ON(sizeof(status->gtk[0].key) < sizeof(data[0].key));
+ BUILD_BUG_ON(NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY +
+ sizeof(data[0].tkip_mic_key) >
+ sizeof(status->gtk[0].key));
+ BUILD_BUG_ON(ARRAY_SIZE(status->gtk) < WOWLAN_GTK_KEYS_NUM);
+ for (data_idx = 0; data_idx < ARRAY_SIZE(status->gtk); data_idx++) {
+ if (!(data[data_idx].key_len))
+ continue;
+ status->gtk[status_idx].len = data[data_idx].key_len;
+ status->gtk[status_idx].flags = data[data_idx].key_flags;
+ status->gtk[status_idx].id = status->gtk[status_idx].flags &
+ IWL_WOWLAN_GTK_IDX_MASK;
- iwl_mvm_convert_gtk_v2(status, (void *)data);
+ memcpy(status->gtk[status_idx].key, data[data_idx].key,
+ sizeof(data[data_idx].key));
+
+ /* if it's as long as the TKIP encryption key, copy MIC key */
+ if (status->gtk[status_idx].len ==
+ NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY)
+ memcpy(status->gtk[status_idx].key +
+ NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY,
+ data[data_idx].tkip_mic_key,
+ sizeof(data[data_idx].tkip_mic_key));
+ status_idx++;
+ }
}
static void iwl_mvm_convert_igtk(struct iwl_wowlan_status_data *status,
struct iwl_wowlan_igtk_status *data)
{
- const u8 *ipn = data->ipn;
-
BUILD_BUG_ON(sizeof(status->igtk.key) < sizeof(data->key));
+ if (!data->key_len)
+ return;
+
status->igtk.len = data->key_len;
status->igtk.flags = data->key_flags;
+ status->igtk.id = u32_get_bits(data->key_flags,
+ IWL_WOWLAN_IGTK_BIGTK_IDX_MASK)
+ + WOWLAN_IGTK_MIN_INDEX;
memcpy(status->igtk.key, data->key, sizeof(data->key));
-
- status->igtk.ipn = ((u64)ipn[5] << 0) |
- ((u64)ipn[4] << 8) |
- ((u64)ipn[3] << 16) |
- ((u64)ipn[2] << 24) |
- ((u64)ipn[1] << 32) |
- ((u64)ipn[0] << 40);
+ memcpy(status->igtk.ipn, data->ipn, sizeof(data->ipn));
}
static void iwl_mvm_parse_wowlan_info_notif(struct iwl_mvm *mvm,
@@ -2031,7 +2192,7 @@ static void iwl_mvm_parse_wowlan_info_notif(struct iwl_mvm *mvm,
}
iwl_mvm_convert_key_counters_v5(status, &data->gtk[0].sc);
- iwl_mvm_convert_gtk_v3(status, &data->gtk[0]);
+ iwl_mvm_convert_gtk_v3(status, data->gtk);
iwl_mvm_convert_igtk(status, &data->igtk[0]);
status->replay_ctr = le64_to_cpu(data->replay_ctr);
@@ -2139,14 +2300,9 @@ iwl_mvm_send_wowlan_get_status(struct iwl_mvm *mvm, u8 sta_id)
len = iwl_rx_packet_payload_len(cmd.resp_pkt);
/* default to 7 (when we have IWL_UCODE_TLV_API_WOWLAN_KEY_MATERIAL) */
- notif_ver = iwl_fw_lookup_notif_ver(mvm->fw, LONG_GROUP,
- WOWLAN_GET_STATUSES, 0);
- if (!notif_ver)
- notif_ver = iwl_fw_lookup_notif_ver(mvm->fw, LEGACY_GROUP,
- WOWLAN_GET_STATUSES, 7);
+ notif_ver = iwl_mvm_lookup_wowlan_status_ver(mvm);
- if (!fw_has_api(&mvm->fw->ucode_capa,
- IWL_UCODE_TLV_API_WOWLAN_KEY_MATERIAL)) {
+ if (notif_ver < 7) {
struct iwl_wowlan_status_v6 *v6 = (void *)cmd.resp_pkt->data;
status = iwl_mvm_parse_wowlan_status_common_v6(mvm, v6, len);
@@ -2154,29 +2310,29 @@ iwl_mvm_send_wowlan_get_status(struct iwl_mvm *mvm, u8 sta_id)
goto out_free_resp;
BUILD_BUG_ON(sizeof(v6->gtk.decrypt_key) >
- sizeof(status->gtk.key));
+ sizeof(status->gtk[0].key));
BUILD_BUG_ON(NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY +
sizeof(v6->gtk.tkip_mic_key) >
- sizeof(status->gtk.key));
+ sizeof(status->gtk[0].key));
/* copy GTK info to the right place */
- memcpy(status->gtk.key, v6->gtk.decrypt_key,
+ memcpy(status->gtk[0].key, v6->gtk.decrypt_key,
sizeof(v6->gtk.decrypt_key));
- memcpy(status->gtk.key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY,
+ memcpy(status->gtk[0].key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY,
v6->gtk.tkip_mic_key,
sizeof(v6->gtk.tkip_mic_key));
iwl_mvm_convert_key_counters(status, &v6->gtk.rsc.all_tsc_rsc);
/* hardcode the key length to 16 since v6 only supports 16 */
- status->gtk.len = 16;
+ status->gtk[0].len = 16;
/*
* The key index only uses 2 bits (values 0 to 3) and
* we always set bit 7 which means this is the
* currently used key.
*/
- status->gtk.flags = v6->gtk.key_index | BIT(7);
+ status->gtk[0].flags = v6->gtk.key_index | BIT(7);
} else if (notif_ver == 7) {
struct iwl_wowlan_status_v7 *v7 = (void *)cmd.resp_pkt->data;
@@ -2210,7 +2366,7 @@ iwl_mvm_send_wowlan_get_status(struct iwl_mvm *mvm, u8 sta_id)
goto out_free_resp;
iwl_mvm_convert_key_counters_v5(status, &v12->gtk[0].sc);
- iwl_mvm_convert_gtk_v3(status, &v12->gtk[0]);
+ iwl_mvm_convert_gtk_v3(status, v12->gtk);
iwl_mvm_convert_igtk(status, &v12->igtk[0]);
status->tid_tear_down = v12->tid_tear_down;
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c b/drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c
index 3613b1fdc5d9..cb4ecad6103f 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
- * Copyright (C) 2012-2014, 2018-2021 Intel Corporation
+ * Copyright (C) 2012-2014, 2018-2023 Intel Corporation
* Copyright (C) 2013-2015 Intel Mobile Communications GmbH
* Copyright (C) 2016-2017 Intel Deutschland GmbH
*/
@@ -554,7 +554,7 @@ static ssize_t iwl_dbgfs_uapsd_misbehaving_read(struct file *file,
char buf[20];
int len;
- len = sprintf(buf, "%pM\n", mvmvif->uapsd_misbehaving_bssid);
+ len = sprintf(buf, "%pM\n", mvmvif->uapsd_misbehaving_ap_addr);
return simple_read_from_buffer(user_buf, count, ppos, buf, len);
}
@@ -567,7 +567,7 @@ static ssize_t iwl_dbgfs_uapsd_misbehaving_write(struct ieee80211_vif *vif,
bool ret;
mutex_lock(&mvm->mutex);
- ret = mac_pton(buf, mvmvif->uapsd_misbehaving_bssid);
+ ret = mac_pton(buf, mvmvif->uapsd_misbehaving_ap_addr);
mutex_unlock(&mvm->mutex);
return ret ? count : -EINVAL;
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c b/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c
index 84a488538427..cf27f106d4d5 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c
@@ -15,6 +15,7 @@
#include "iwl-io.h"
#include "debugfs.h"
#include "iwl-modparams.h"
+#include "iwl-drv.h"
#include "fw/error-dump.h"
#include "fw/api/phy-ctxt.h"
@@ -391,13 +392,14 @@ static ssize_t iwl_dbgfs_stations_read(struct file *file, char __user *user_buf,
return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
}
-static ssize_t iwl_dbgfs_rs_data_read(struct file *file, char __user *user_buf,
+static ssize_t iwl_dbgfs_rs_data_read(struct ieee80211_link_sta *link_sta,
+ struct iwl_mvm_sta *mvmsta,
+ struct iwl_mvm *mvm,
+ struct iwl_mvm_link_sta *mvm_link_sta,
+ char __user *user_buf,
size_t count, loff_t *ppos)
{
- struct ieee80211_sta *sta = file->private_data;
- struct iwl_mvm_sta *mvmsta = iwl_mvm_sta_from_mac80211(sta);
- struct iwl_lq_sta_rs_fw *lq_sta = &mvmsta->deflink.lq_sta.rs_fw;
- struct iwl_mvm *mvm = lq_sta->pers.drv;
+ struct iwl_lq_sta_rs_fw *lq_sta = &mvm_link_sta->lq_sta.rs_fw;
static const size_t bufsz = 2048;
char *buff;
int desc = 0;
@@ -407,8 +409,6 @@ static ssize_t iwl_dbgfs_rs_data_read(struct file *file, char __user *user_buf,
if (!buff)
return -ENOMEM;
- mutex_lock(&mvm->mutex);
-
desc += scnprintf(buff + desc, bufsz - desc, "sta_id %d\n",
lq_sta->pers.sta_id);
desc += scnprintf(buff + desc, bufsz - desc,
@@ -429,18 +429,19 @@ static ssize_t iwl_dbgfs_rs_data_read(struct file *file, char __user *user_buf,
lq_sta->last_rate_n_flags);
if (desc < bufsz - 1)
buff[desc++] = '\n';
- mutex_unlock(&mvm->mutex);
ret = simple_read_from_buffer(user_buf, count, ppos, buff, desc);
kfree(buff);
return ret;
}
-static ssize_t iwl_dbgfs_amsdu_len_write(struct ieee80211_sta *sta,
+static ssize_t iwl_dbgfs_amsdu_len_write(struct ieee80211_link_sta *link_sta,
+ struct iwl_mvm_sta *mvmsta,
+ struct iwl_mvm *mvm,
+ struct iwl_mvm_link_sta *mvm_link_sta,
char *buf, size_t count,
loff_t *ppos)
{
- struct iwl_mvm_sta *mvmsta = iwl_mvm_sta_from_mac80211(sta);
int i;
u16 amsdu_len;
@@ -448,36 +449,39 @@ static ssize_t iwl_dbgfs_amsdu_len_write(struct ieee80211_sta *sta,
return -EINVAL;
/* only change from debug set <-> debug unset */
- if (amsdu_len && mvmsta->orig_amsdu_len)
+ if (amsdu_len && mvm_link_sta->orig_amsdu_len)
return -EBUSY;
if (amsdu_len) {
- mvmsta->orig_amsdu_len = sta->cur->max_amsdu_len;
- sta->deflink.agg.max_amsdu_len = amsdu_len;
- sta->deflink.agg.max_amsdu_len = amsdu_len;
- for (i = 0; i < ARRAY_SIZE(sta->deflink.agg.max_tid_amsdu_len); i++)
- sta->deflink.agg.max_tid_amsdu_len[i] = amsdu_len;
+ mvm_link_sta->orig_amsdu_len = link_sta->agg.max_amsdu_len;
+ link_sta->agg.max_amsdu_len = amsdu_len;
+ link_sta->agg.max_amsdu_len = amsdu_len;
+ for (i = 0; i < ARRAY_SIZE(link_sta->agg.max_tid_amsdu_len); i++)
+ link_sta->agg.max_tid_amsdu_len[i] = amsdu_len;
} else {
- sta->deflink.agg.max_amsdu_len = mvmsta->orig_amsdu_len;
- mvmsta->orig_amsdu_len = 0;
+ link_sta->agg.max_amsdu_len = mvm_link_sta->orig_amsdu_len;
+ mvm_link_sta->orig_amsdu_len = 0;
}
+ ieee80211_sta_recalc_aggregates(link_sta->sta);
+
return count;
}
-static ssize_t iwl_dbgfs_amsdu_len_read(struct file *file,
+static ssize_t iwl_dbgfs_amsdu_len_read(struct ieee80211_link_sta *link_sta,
+ struct iwl_mvm_sta *mvmsta,
+ struct iwl_mvm *mvm,
+ struct iwl_mvm_link_sta *mvm_link_sta,
char __user *user_buf,
size_t count, loff_t *ppos)
{
- struct ieee80211_sta *sta = file->private_data;
- struct iwl_mvm_sta *mvmsta = iwl_mvm_sta_from_mac80211(sta);
-
char buf[32];
int pos;
- pos = scnprintf(buf, sizeof(buf), "current %d ", sta->cur->max_amsdu_len);
+ pos = scnprintf(buf, sizeof(buf), "current %d ",
+ link_sta->agg.max_amsdu_len);
pos += scnprintf(buf + pos, sizeof(buf) - pos, "stored %d\n",
- mvmsta->orig_amsdu_len);
+ mvm_link_sta->orig_amsdu_len);
return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
}
@@ -712,6 +716,7 @@ static ssize_t iwl_dbgfs_fw_ver_read(struct file *file, char __user *user_buf,
struct iwl_mvm *mvm = file->private_data;
char *buff, *pos, *endpos;
static const size_t bufsz = 1024;
+ char _fw_name_pre[FW_NAME_PRE_BUFSIZE];
int ret;
buff = kmalloc(bufsz, GFP_KERNEL);
@@ -722,7 +727,7 @@ static ssize_t iwl_dbgfs_fw_ver_read(struct file *file, char __user *user_buf,
endpos = pos + bufsz;
pos += scnprintf(pos, endpos - pos, "FW prefix: %s\n",
- mvm->trans->cfg->fw_name_pre);
+ iwl_drv_get_fwname_pre(mvm->trans, _fw_name_pre));
pos += scnprintf(pos, endpos - pos, "FW: %s\n",
mvm->fwrt.fw->human_readable);
pos += scnprintf(pos, endpos - pos, "Device: %s\n",
@@ -1596,17 +1601,127 @@ static ssize_t iwl_dbgfs_dbg_time_point_write(struct iwl_mvm *mvm,
#define MVM_DEBUGFS_ADD_FILE(name, parent, mode) \
MVM_DEBUGFS_ADD_FILE_ALIAS(#name, name, parent, mode)
-#define MVM_DEBUGFS_WRITE_STA_FILE_OPS(name, bufsz) \
- _MVM_DEBUGFS_WRITE_FILE_OPS(name, bufsz, struct ieee80211_sta)
-#define MVM_DEBUGFS_READ_WRITE_STA_FILE_OPS(name, bufsz) \
- _MVM_DEBUGFS_READ_WRITE_FILE_OPS(name, bufsz, struct ieee80211_sta)
+static ssize_t
+_iwl_dbgfs_link_sta_wrap_write(ssize_t (*real)(struct ieee80211_link_sta *,
+ struct iwl_mvm_sta *,
+ struct iwl_mvm *,
+ struct iwl_mvm_link_sta *,
+ char *,
+ size_t, loff_t *),
+ struct file *file,
+ char *buf, size_t buf_size, loff_t *ppos)
+{
+ struct ieee80211_link_sta *link_sta = file->private_data;
+ struct iwl_mvm_sta *mvmsta = iwl_mvm_sta_from_mac80211(link_sta->sta);
+ struct iwl_mvm *mvm = iwl_mvm_vif_from_mac80211(mvmsta->vif)->mvm;
+ struct iwl_mvm_link_sta *mvm_link_sta;
+ ssize_t ret;
-#define MVM_DEBUGFS_ADD_STA_FILE_ALIAS(alias, name, parent, mode) do { \
- debugfs_create_file(alias, mode, parent, sta, \
- &iwl_dbgfs_##name##_ops); \
- } while (0)
-#define MVM_DEBUGFS_ADD_STA_FILE(name, parent, mode) \
- MVM_DEBUGFS_ADD_STA_FILE_ALIAS(#name, name, parent, mode)
+ mutex_lock(&mvm->mutex);
+
+ mvm_link_sta = rcu_dereference_protected(mvmsta->link[link_sta->link_id],
+ lockdep_is_held(&mvm->mutex));
+ if (WARN_ON(!mvm_link_sta)) {
+ mutex_unlock(&mvm->mutex);
+ return -ENODEV;
+ }
+
+ ret = real(link_sta, mvmsta, mvm, mvm_link_sta, buf, buf_size, ppos);
+
+ mutex_unlock(&mvm->mutex);
+
+ return ret;
+}
+
+static ssize_t
+_iwl_dbgfs_link_sta_wrap_read(ssize_t (*real)(struct ieee80211_link_sta *,
+ struct iwl_mvm_sta *,
+ struct iwl_mvm *,
+ struct iwl_mvm_link_sta *,
+ char __user *,
+ size_t, loff_t *),
+ struct file *file,
+ char __user *user_buf, size_t count, loff_t *ppos)
+{
+ struct ieee80211_link_sta *link_sta = file->private_data;
+ struct iwl_mvm_sta *mvmsta = iwl_mvm_sta_from_mac80211(link_sta->sta);
+ struct iwl_mvm *mvm = iwl_mvm_vif_from_mac80211(mvmsta->vif)->mvm;
+ struct iwl_mvm_link_sta *mvm_link_sta;
+ ssize_t ret;
+
+ mutex_lock(&mvm->mutex);
+
+ mvm_link_sta = rcu_dereference_protected(mvmsta->link[link_sta->link_id],
+ lockdep_is_held(&mvm->mutex));
+ if (WARN_ON(!mvm_link_sta)) {
+ mutex_unlock(&mvm->mutex);
+ return -ENODEV;
+ }
+
+ ret = real(link_sta, mvmsta, mvm, mvm_link_sta, user_buf, count, ppos);
+
+ mutex_unlock(&mvm->mutex);
+
+ return ret;
+}
+
+#define MVM_DEBUGFS_LINK_STA_WRITE_WRAPPER(name, buflen) \
+static ssize_t _iwl_dbgfs_link_sta_##name##_write(struct file *file, \
+ const char __user *user_buf, \
+ size_t count, loff_t *ppos) \
+{ \
+ char buf[buflen] = {}; \
+ size_t buf_size = min(count, sizeof(buf) - 1); \
+ \
+ if (copy_from_user(buf, user_buf, sizeof(buf))) \
+ return -EFAULT; \
+ \
+ return _iwl_dbgfs_link_sta_wrap_write(iwl_dbgfs_##name##_write, \
+ file, \
+ buf, buf_size, ppos); \
+} \
+
+#define MVM_DEBUGFS_LINK_STA_READ_WRAPPER(name) \
+static ssize_t _iwl_dbgfs_link_sta_##name##_read(struct file *file, \
+ char __user *user_buf, \
+ size_t count, loff_t *ppos) \
+{ \
+ return _iwl_dbgfs_link_sta_wrap_read(iwl_dbgfs_##name##_read, \
+ file, \
+ user_buf, count, ppos); \
+} \
+
+#define MVM_DEBUGFS_WRITE_LINK_STA_FILE_OPS(name, bufsz) \
+MVM_DEBUGFS_LINK_STA_WRITE_WRAPPER(name, bufsz) \
+static const struct file_operations iwl_dbgfs_link_sta_##name##_ops = { \
+ .write = _iwl_dbgfs_link_sta_##name##_write, \
+ .open = simple_open, \
+ .llseek = generic_file_llseek, \
+}
+
+#define MVM_DEBUGFS_READ_LINK_STA_FILE_OPS(name) \
+MVM_DEBUGFS_LINK_STA_READ_WRAPPER(name) \
+static const struct file_operations iwl_dbgfs_link_sta_##name##_ops = { \
+ .read = _iwl_dbgfs_link_sta_##name##_read, \
+ .open = simple_open, \
+ .llseek = generic_file_llseek, \
+}
+
+#define MVM_DEBUGFS_READ_WRITE_LINK_STA_FILE_OPS(name, bufsz) \
+MVM_DEBUGFS_LINK_STA_READ_WRAPPER(name) \
+MVM_DEBUGFS_LINK_STA_WRITE_WRAPPER(name, bufsz) \
+static const struct file_operations iwl_dbgfs_link_sta_##name##_ops = { \
+ .read = _iwl_dbgfs_link_sta_##name##_read, \
+ .write = _iwl_dbgfs_link_sta_##name##_write, \
+ .open = simple_open, \
+ .llseek = generic_file_llseek, \
+}
+
+#define MVM_DEBUGFS_ADD_LINK_STA_FILE_ALIAS(alias, name, parent, mode) \
+ debugfs_create_file(alias, mode, parent, link_sta, \
+ &iwl_dbgfs_link_sta_##name##_ops)
+#define MVM_DEBUGFS_ADD_LINK_STA_FILE(name, parent, mode) \
+ MVM_DEBUGFS_ADD_LINK_STA_FILE_ALIAS(#name, name, parent, mode)
static ssize_t
iwl_dbgfs_prph_reg_read(struct file *file,
@@ -1891,7 +2006,7 @@ MVM_DEBUGFS_READ_WRITE_FILE_OPS(sram, 64);
MVM_DEBUGFS_READ_WRITE_FILE_OPS(set_nic_temperature, 64);
MVM_DEBUGFS_READ_FILE_OPS(nic_temp);
MVM_DEBUGFS_READ_FILE_OPS(stations);
-MVM_DEBUGFS_READ_FILE_OPS(rs_data);
+MVM_DEBUGFS_READ_LINK_STA_FILE_OPS(rs_data);
MVM_DEBUGFS_READ_FILE_OPS(bt_notif);
MVM_DEBUGFS_READ_FILE_OPS(bt_cmd);
MVM_DEBUGFS_READ_WRITE_FILE_OPS(disable_power_off, 64);
@@ -1921,7 +2036,7 @@ MVM_DEBUGFS_READ_FILE_OPS(sar_geo_profile);
MVM_DEBUGFS_READ_FILE_OPS(wifi_6e_enable);
#endif
-MVM_DEBUGFS_READ_WRITE_STA_FILE_OPS(amsdu_len, 16);
+MVM_DEBUGFS_READ_WRITE_LINK_STA_FILE_OPS(amsdu_len, 16);
MVM_DEBUGFS_READ_WRITE_FILE_OPS(he_sniffer_params, 32);
@@ -2068,17 +2183,18 @@ static const struct file_operations iwl_dbgfs_mem_ops = {
.llseek = default_llseek,
};
-void iwl_mvm_sta_add_debugfs(struct ieee80211_hw *hw,
- struct ieee80211_vif *vif,
- struct ieee80211_sta *sta,
- struct dentry *dir)
+void iwl_mvm_link_sta_add_debugfs(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif,
+ struct ieee80211_link_sta *link_sta,
+ struct dentry *dir)
{
struct iwl_mvm *mvm = IWL_MAC80211_GET_MVM(hw);
if (iwl_mvm_has_tlc_offload(mvm)) {
- MVM_DEBUGFS_ADD_STA_FILE(rs_data, dir, 0400);
+ MVM_DEBUGFS_ADD_LINK_STA_FILE(rs_data, dir, 0400);
}
- MVM_DEBUGFS_ADD_STA_FILE(amsdu_len, dir, 0600);
+
+ MVM_DEBUGFS_ADD_LINK_STA_FILE(amsdu_len, dir, 0600);
}
void iwl_mvm_dbgfs_register(struct iwl_mvm *mvm)
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/ftm-initiator.c b/drivers/net/wireless/intel/iwlwifi/mvm/ftm-initiator.c
index 652a603c4500..233ae81884a0 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/ftm-initiator.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/ftm-initiator.c
@@ -72,15 +72,24 @@ int iwl_mvm_ftm_add_pasn_sta(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
* the TK is already configured for this station, so it
* shouldn't be set again here.
*/
- if (vif->cfg.assoc &&
- !memcmp(addr, vif->bss_conf.bssid, ETH_ALEN)) {
+ if (vif->cfg.assoc) {
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
+ struct ieee80211_bss_conf *link_conf;
+ unsigned int link_id;
struct ieee80211_sta *sta;
+ u8 sta_id;
rcu_read_lock();
- sta = rcu_dereference(mvm->fw_id_to_mac_id[mvmvif->deflink.ap_sta_id]);
- if (!IS_ERR_OR_NULL(sta) && sta->mfp)
- expected_tk_len = 0;
+ for_each_vif_active_link(vif, link_conf, link_id) {
+ if (memcmp(addr, link_conf->bssid, ETH_ALEN))
+ continue;
+
+ sta_id = mvmvif->link[link_id]->ap_sta_id;
+ sta = rcu_dereference(mvm->fw_id_to_mac_id[sta_id]);
+ if (!IS_ERR_OR_NULL(sta) && sta->mfp)
+ expected_tk_len = 0;
+ break;
+ }
rcu_read_unlock();
}
@@ -518,25 +527,30 @@ iwl_mvm_ftm_put_target(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
iwl_mvm_ftm_put_target_common(mvm, peer, target);
- if (vif->cfg.assoc &&
- !memcmp(peer->addr, vif->bss_conf.bssid, ETH_ALEN)) {
+ if (vif->cfg.assoc) {
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
struct ieee80211_sta *sta;
+ struct ieee80211_bss_conf *link_conf;
+ unsigned int link_id;
rcu_read_lock();
+ for_each_vif_active_link(vif, link_conf, link_id) {
+ if (memcmp(peer->addr, link_conf->bssid, ETH_ALEN))
+ continue;
+
+ target->sta_id = mvmvif->link[link_id]->ap_sta_id;
+ sta = rcu_dereference(mvm->fw_id_to_mac_id[target->sta_id]);
+ if (WARN_ON_ONCE(IS_ERR_OR_NULL(sta))) {
+ rcu_read_unlock();
+ return PTR_ERR_OR_ZERO(sta);
+ }
- sta = rcu_dereference(mvm->fw_id_to_mac_id[mvmvif->deflink.ap_sta_id]);
- if (WARN_ON_ONCE(IS_ERR_OR_NULL(sta))) {
- rcu_read_unlock();
- return PTR_ERR_OR_ZERO(sta);
+ if (sta->mfp && (peer->ftm.trigger_based ||
+ peer->ftm.non_trigger_based))
+ FTM_PUT_FLAG(PMF);
+ break;
}
-
- if (sta->mfp && (peer->ftm.trigger_based || peer->ftm.non_trigger_based))
- FTM_PUT_FLAG(PMF);
-
rcu_read_unlock();
-
- target->sta_id = mvmvif->deflink.ap_sta_id;
} else {
target->sta_id = IWL_MVM_INVALID_STA;
}
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/ftm-responder.c b/drivers/net/wireless/intel/iwlwifi/mvm/ftm-responder.c
index 1b6fb73ddfc7..b49781d1a07a 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/ftm-responder.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/ftm-responder.c
@@ -104,7 +104,8 @@ iwl_mvm_ftm_responder_set_ndp(struct iwl_mvm *mvm,
static int
iwl_mvm_ftm_responder_cmd(struct iwl_mvm *mvm,
struct ieee80211_vif *vif,
- struct cfg80211_chan_def *chandef)
+ struct cfg80211_chan_def *chandef,
+ struct ieee80211_bss_conf *link_conf)
{
u32 cmd_id = WIDE_ID(LOCATION_GROUP, TOF_RESPONDER_CONFIG_CMD);
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
@@ -119,7 +120,7 @@ iwl_mvm_ftm_responder_cmd(struct iwl_mvm *mvm,
cpu_to_le32(IWL_TOF_RESPONDER_CMD_VALID_CHAN_INFO |
IWL_TOF_RESPONDER_CMD_VALID_BSSID |
IWL_TOF_RESPONDER_CMD_VALID_STA_ID),
- .sta_id = mvmvif->deflink.bcast_sta.sta_id,
+ .sta_id = mvmvif->link[link_conf->link_id]->bcast_sta.sta_id,
};
u8 cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd_id, 6);
int err;
@@ -386,7 +387,8 @@ int iwl_mvm_ftm_resp_remove_pasn_sta(struct iwl_mvm *mvm,
return -EINVAL;
}
-int iwl_mvm_ftm_start_responder(struct iwl_mvm *mvm, struct ieee80211_vif *vif)
+int iwl_mvm_ftm_start_responder(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
+ struct ieee80211_bss_conf *bss_conf)
{
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
struct ieee80211_ftm_responder_params *params;
@@ -395,11 +397,11 @@ int iwl_mvm_ftm_start_responder(struct iwl_mvm *mvm, struct ieee80211_vif *vif)
struct iwl_mvm_phy_ctxt *phy_ctxt;
int ret;
- params = vif->bss_conf.ftmr_params;
+ params = bss_conf->ftmr_params;
lockdep_assert_held(&mvm->mutex);
- if (WARN_ON_ONCE(!vif->bss_conf.ftm_responder))
+ if (WARN_ON_ONCE(!bss_conf->ftm_responder))
return -EINVAL;
if (vif->p2p || vif->type != NL80211_IFTYPE_AP ||
@@ -409,7 +411,7 @@ int iwl_mvm_ftm_start_responder(struct iwl_mvm *mvm, struct ieee80211_vif *vif)
}
rcu_read_lock();
- pctx = rcu_dereference(vif->bss_conf.chanctx_conf);
+ pctx = rcu_dereference(bss_conf->chanctx_conf);
/* Copy the ctx to unlock the rcu and send the phy ctxt. We don't care
* about changes in the ctx after releasing the lock because the driver
* is still protected by the mutex. */
@@ -424,7 +426,7 @@ int iwl_mvm_ftm_start_responder(struct iwl_mvm *mvm, struct ieee80211_vif *vif)
if (ret)
return ret;
- ret = iwl_mvm_ftm_responder_cmd(mvm, vif, &ctx.def);
+ ret = iwl_mvm_ftm_responder_cmd(mvm, vif, &ctx.def, bss_conf);
if (ret)
return ret;
@@ -446,13 +448,14 @@ void iwl_mvm_ftm_responder_clear(struct iwl_mvm *mvm,
}
void iwl_mvm_ftm_restart_responder(struct iwl_mvm *mvm,
- struct ieee80211_vif *vif)
+ struct ieee80211_vif *vif,
+ struct ieee80211_bss_conf *bss_conf)
{
- if (!vif->bss_conf.ftm_responder)
+ if (!bss_conf->ftm_responder)
return;
iwl_mvm_ftm_responder_clear(mvm, vif);
- iwl_mvm_ftm_start_responder(mvm, vif);
+ iwl_mvm_ftm_start_responder(mvm, vif, bss_conf);
}
void iwl_mvm_ftm_responder_stats(struct iwl_mvm *mvm,
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/fw.c b/drivers/net/wireless/intel/iwlwifi/mvm/fw.c
index 205c09bc9863..1f5db65a088d 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/fw.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/fw.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
- * Copyright (C) 2012-2014, 2018-2022 Intel Corporation
+ * Copyright (C) 2012-2014, 2018-2023 Intel Corporation
* Copyright (C) 2013-2015 Intel Mobile Communications GmbH
* Copyright (C) 2016-2017 Intel Deutschland GmbH
*/
@@ -433,7 +433,8 @@ static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm,
/* if reached this point, Alive notification was received */
iwl_mei_alive_notif(true);
- ret = iwl_pnvm_load(mvm->trans, &mvm->notif_wait);
+ ret = iwl_pnvm_load(mvm->trans, &mvm->notif_wait,
+ &mvm->fw->ucode_capa);
if (ret) {
IWL_ERR(mvm, "Timeout waiting for PNVM load!\n");
iwl_fw_set_current_image(&mvm->fwrt, old_type);
@@ -477,40 +478,13 @@ static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm,
return 0;
}
-#ifdef CONFIG_ACPI
-static void iwl_mvm_phy_filter_init(struct iwl_mvm *mvm,
- struct iwl_phy_specific_cfg *phy_filters)
-{
- /*
- * TODO: read specific phy config from BIOS
- * ACPI table for this feature has not been defined yet,
- * so for now we use hardcoded values.
- */
-
- if (IWL_MVM_PHY_FILTER_CHAIN_A) {
- phy_filters->filter_cfg_chain_a =
- cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_A);
- }
- if (IWL_MVM_PHY_FILTER_CHAIN_B) {
- phy_filters->filter_cfg_chain_b =
- cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_B);
- }
- if (IWL_MVM_PHY_FILTER_CHAIN_C) {
- phy_filters->filter_cfg_chain_c =
- cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_C);
- }
- if (IWL_MVM_PHY_FILTER_CHAIN_D) {
- phy_filters->filter_cfg_chain_d =
- cpu_to_le32(IWL_MVM_PHY_FILTER_CHAIN_D);
- }
-}
-#else /* CONFIG_ACPI */
-
static void iwl_mvm_phy_filter_init(struct iwl_mvm *mvm,
struct iwl_phy_specific_cfg *phy_filters)
{
-}
+#ifdef CONFIG_ACPI
+ *phy_filters = mvm->phy_filters;
#endif /* CONFIG_ACPI */
+}
#if defined(CONFIG_ACPI) && defined(CONFIG_EFI)
static int iwl_mvm_sgom_init(struct iwl_mvm *mvm)
@@ -559,7 +533,6 @@ static int iwl_send_phy_cfg_cmd(struct iwl_mvm *mvm)
u32 cmd_id = PHY_CONFIGURATION_CMD;
struct iwl_phy_cfg_cmd_v3 phy_cfg_cmd;
enum iwl_ucode_type ucode_type = mvm->fwrt.cur_fw_img;
- struct iwl_phy_specific_cfg phy_filters = {};
u8 cmd_ver;
size_t cmd_size;
@@ -590,11 +563,8 @@ static int iwl_send_phy_cfg_cmd(struct iwl_mvm *mvm)
cmd_ver = iwl_fw_lookup_cmd_ver(mvm->fw, cmd_id,
IWL_FW_CMD_VER_UNKNOWN);
- if (cmd_ver == 3) {
- iwl_mvm_phy_filter_init(mvm, &phy_filters);
- memcpy(&phy_cfg_cmd.phy_specific_cfg, &phy_filters,
- sizeof(struct iwl_phy_specific_cfg));
- }
+ if (cmd_ver >= 3)
+ iwl_mvm_phy_filter_init(mvm, &phy_cfg_cmd.phy_specific_cfg);
IWL_DEBUG_INFO(mvm, "Sending Phy CFG command: 0x%x\n",
phy_cfg_cmd.phy_cfg);
@@ -1104,7 +1074,26 @@ static const struct dmi_system_id dmi_tas_approved_list[] = {
DMI_MATCH(DMI_SYS_VENDOR, "Microsoft Corporation"),
},
},
-
+ { .ident = "Acer",
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
+ },
+ },
+ { .ident = "ASUS",
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+ },
+ },
+ { .ident = "MSI",
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "Micro-Star International Co., Ltd."),
+ },
+ },
+ { .ident = "Honor",
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "HONOR"),
+ },
+ },
/* keep last */
{}
};
@@ -1162,7 +1151,7 @@ static void iwl_mvm_tas_init(struct iwl_mvm *mvm)
if (ret == 0)
return;
- if (!dmi_check_system(dmi_tas_approved_list)) {
+ if (!iwl_mvm_is_vendor_in_approved_list()) {
IWL_DEBUG_RADIO(mvm,
"System vendor '%s' is not in the approved list, disabling TAS in US and Canada.\n",
dmi_get_system_info(DMI_SYS_VENDOR));
@@ -1176,6 +1165,10 @@ static void iwl_mvm_tas_init(struct iwl_mvm *mvm)
"Unable to add US/Canada to TAS block list, disabling TAS\n");
return;
}
+ } else {
+ IWL_DEBUG_RADIO(mvm,
+ "System vendor '%s' is in the approved list.\n",
+ dmi_get_system_info(DMI_SYS_VENDOR));
}
/* v4 is the same size as v3, so no need to differentiate here */
@@ -1356,6 +1349,8 @@ void iwl_mvm_get_acpi_tables(struct iwl_mvm *mvm)
/* we don't fail if the table is not available */
}
}
+
+ iwl_acpi_get_phy_filters(&mvm->fwrt, &mvm->phy_filters);
}
#else /* CONFIG_ACPI */
@@ -1571,6 +1566,8 @@ int iwl_mvm_up(struct iwl_mvm *mvm)
goto error;
}
+ iwl_mvm_lari_cfg(mvm);
+
/* Init RSS configuration */
ret = iwl_configure_rxq(&mvm->fwrt);
if (ret)
@@ -1591,6 +1588,9 @@ int iwl_mvm_up(struct iwl_mvm *mvm)
RCU_INIT_POINTER(mvm->fw_id_to_link_sta[i], NULL);
}
+ for (i = 0; i < IWL_MVM_FW_MAX_LINK_ID + 1; i++)
+ RCU_INIT_POINTER(mvm->link_id_to_link_conf[i], NULL);
+
memset(&mvm->fw_link_ids_map, 0, sizeof(mvm->fw_link_ids_map));
mvm->tdls_cs.peer.sta_id = IWL_MVM_INVALID_STA;
@@ -1610,7 +1610,7 @@ int iwl_mvm_up(struct iwl_mvm *mvm)
* internal aux station for all aux activities that don't
* requires a dedicated data queue.
*/
- if (iwl_fw_lookup_cmd_ver(mvm->fw, ADD_STA, 0) < 12) {
+ if (!iwl_mvm_has_new_station_api(mvm->fw)) {
/*
* In old version the aux station uses mac id like other
* station and not lmac id
@@ -1678,7 +1678,6 @@ int iwl_mvm_up(struct iwl_mvm *mvm)
if (ret)
goto error;
- iwl_mvm_lari_cfg(mvm);
/*
* RTNL is not taken during Ct-kill, but we don't need to scan/Tx
* anyway, so don't init MCC.
@@ -1699,9 +1698,11 @@ int iwl_mvm_up(struct iwl_mvm *mvm)
if (test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status)) {
iwl_mvm_send_recovery_cmd(mvm, ERROR_RECOVERY_UPDATE_DB);
- iwl_mvm_time_sync_config(mvm, mvm->time_sync.peer_addr,
- IWL_TIME_SYNC_PROTOCOL_TM |
- IWL_TIME_SYNC_PROTOCOL_FTM);
+
+ if (mvm->time_sync.active)
+ iwl_mvm_time_sync_config(mvm, mvm->time_sync.peer_addr,
+ IWL_TIME_SYNC_PROTOCOL_TM |
+ IWL_TIME_SYNC_PROTOCOL_FTM);
}
if (!mvm->ptp_data.ptp_clock)
@@ -1777,7 +1778,7 @@ int iwl_mvm_load_d3_fw(struct iwl_mvm *mvm)
RCU_INIT_POINTER(mvm->fw_id_to_link_sta[i], NULL);
}
- if (iwl_fw_lookup_cmd_ver(mvm->fw, ADD_STA, 0) < 12) {
+ if (!iwl_mvm_has_new_station_api(mvm->fw)) {
/*
* Add auxiliary station for scanning.
* Newer versions of this command implies that the fw uses
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/link.c b/drivers/net/wireless/intel/iwlwifi/mvm/link.c
index 3814915cb1a6..ace82e2c5bd9 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/link.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/link.c
@@ -63,6 +63,9 @@ int iwl_mvm_add_link(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
mvmvif);
if (link_info->fw_link_id == IWL_MVM_FW_LINK_ID_INVALID)
return -EINVAL;
+
+ rcu_assign_pointer(mvm->link_id_to_link_conf[link_info->fw_link_id],
+ link_conf);
}
/* Update SF - Disable if needed. if this fails, SF might still be on
@@ -73,6 +76,7 @@ int iwl_mvm_add_link(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
cmd.link_id = cpu_to_le32(link_info->fw_link_id);
cmd.mac_id = cpu_to_le32(mvmvif->id);
+ cmd.spec_link_id = link_conf->link_id;
/* P2P-Device already has a valid PHY context during add */
phyctxt = link_info->phy_ctxt;
if (phyctxt)
@@ -85,6 +89,8 @@ int iwl_mvm_add_link(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
if (vif->type == NL80211_IFTYPE_ADHOC && link_conf->bssid)
memcpy(cmd.ibss_bssid_addr, link_conf->bssid, ETH_ALEN);
+ cmd.listen_lmac = cpu_to_le32(link_info->listen_lmac);
+
return iwl_mvm_link_cmd_send(mvm, &cmd, FW_CTXT_ACTION_ADD);
}
@@ -114,24 +120,6 @@ int iwl_mvm_link_changed(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
if (!link_info->phy_ctxt)
return 0;
- /* check there aren't too many active links */
- if (!link_info->active && active) {
- int i, count = 0;
-
- /* link with phy_ctxt is active in FW */
- for_each_mvm_vif_valid_link(mvmvif, i)
- if (mvmvif->link[i]->phy_ctxt)
- count++;
-
- if (vif->type == NL80211_IFTYPE_AP) {
- if (count > mvm->fw->ucode_capa.num_beacons)
- return -EOPNOTSUPP;
- /* this should be per HW or such */
- } else if (count >= IWL_MVM_FW_MAX_ACTIVE_LINKS_NUM) {
- return -EOPNOTSUPP;
- }
- }
-
/* Catch early if driver tries to activate or deactivate a link
* twice.
*/
@@ -163,10 +151,6 @@ int iwl_mvm_link_changed(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
if (vif->type == NL80211_IFTYPE_ADHOC && link_conf->bssid)
memcpy(cmd.ibss_bssid_addr, link_conf->bssid, ETH_ALEN);
- /* TODO: set a value to cmd.listen_lmac when system requiremens
- * will define it
- */
-
iwl_mvm_set_fw_basic_rates(mvm, vif, link_conf,
&cmd.cck_rates, &cmd.ofdm_rates);
@@ -179,7 +163,7 @@ int iwl_mvm_link_changed(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
&cmd.protection_flags,
ht_flag, LINK_PROT_FLG_TGG_PROTECT);
- iwl_mvm_set_fw_qos_params(mvm, vif, link_conf, &cmd.ac[0],
+ iwl_mvm_set_fw_qos_params(mvm, vif, link_conf, cmd.ac,
&cmd.qos_flags);
@@ -204,7 +188,7 @@ int iwl_mvm_link_changed(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
/* TODO how to set ndp_fdbk_buff_th_exp? */
- if (iwl_mvm_set_fw_mu_edca_params(mvm, mvmvif,
+ if (iwl_mvm_set_fw_mu_edca_params(mvm, mvmvif->link[link_id],
&cmd.trig_based_txf[0])) {
flags |= LINK_FLG_MU_EDCA_CW;
flags_mask |= LINK_FLG_MU_EDCA_CW;
@@ -241,6 +225,8 @@ send_cmd:
cmd.modify_mask = cpu_to_le32(changes);
cmd.flags = cpu_to_le32(flags);
cmd.flags_mask = cpu_to_le32(flags_mask);
+ cmd.spec_link_id = link_conf->link_id;
+ cmd.listen_lmac = cpu_to_le32(link_info->listen_lmac);
ret = iwl_mvm_link_cmd_send(mvm, &cmd, FW_CTXT_ACTION_MODIFY);
if (!ret && (changes & LINK_CONTEXT_MODIFY_ACTIVE))
@@ -262,9 +248,12 @@ int iwl_mvm_remove_link(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
link_info->fw_link_id == IWL_MVM_FW_LINK_ID_INVALID))
return -EINVAL;
+ RCU_INIT_POINTER(mvm->link_id_to_link_conf[link_info->fw_link_id],
+ NULL);
cmd.link_id = cpu_to_le32(link_info->fw_link_id);
iwl_mvm_release_fw_link_id(mvm, link_info->fw_link_id);
link_info->fw_link_id = IWL_MVM_FW_LINK_ID_INVALID;
+ cmd.spec_link_id = link_conf->link_id;
ret = iwl_mvm_link_cmd_send(mvm, &cmd, FW_CTXT_ACTION_REMOVE);
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/mac-ctxt.c b/drivers/net/wireless/intel/iwlwifi/mvm/mac-ctxt.c
index cc90f2884cff..7369a45f7f2b 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/mac-ctxt.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/mac-ctxt.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
- * Copyright (C) 2012-2014, 2018-2022 Intel Corporation
+ * Copyright (C) 2012-2014, 2018-2023 Intel Corporation
* Copyright (C) 2013-2014 Intel Mobile Communications GmbH
* Copyright (C) 2015-2017 Intel Deutschland GmbH
*/
@@ -470,19 +470,24 @@ void iwl_mvm_set_fw_qos_params(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
struct iwl_ac_qos *ac, __le32 *qos_flags)
{
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
+ struct iwl_mvm_vif_link_info *mvm_link =
+ mvmvif->link[link_conf->link_id];
int i;
+ if (!mvm_link)
+ return;
+
for (i = 0; i < IEEE80211_NUM_ACS; i++) {
u8 txf = iwl_mvm_mac_ac_to_tx_fifo(mvm, i);
u8 ucode_ac = iwl_mvm_mac80211_ac_to_ucode_ac(i);
ac[ucode_ac].cw_min =
- cpu_to_le16(mvmvif->deflink.queue_params[i].cw_min);
+ cpu_to_le16(mvm_link->queue_params[i].cw_min);
ac[ucode_ac].cw_max =
- cpu_to_le16(mvmvif->deflink.queue_params[i].cw_max);
+ cpu_to_le16(mvm_link->queue_params[i].cw_max);
ac[ucode_ac].edca_txop =
- cpu_to_le16(mvmvif->deflink.queue_params[i].txop * 32);
- ac[ucode_ac].aifsn = mvmvif->deflink.queue_params[i].aifs;
+ cpu_to_le16(mvm_link->queue_params[i].txop * 32);
+ ac[ucode_ac].aifsn = mvm_link->queue_params[i].aifs;
ac[ucode_ac].fifos_mask = BIT(txf);
}
@@ -558,7 +563,7 @@ static void iwl_mvm_mac_ctxt_cmd_common(struct iwl_mvm *mvm,
cmd->filter_flags = 0;
- iwl_mvm_set_fw_qos_params(mvm, vif, &vif->bss_conf, &cmd->ac[0],
+ iwl_mvm_set_fw_qos_params(mvm, vif, &vif->bss_conf, cmd->ac,
&cmd->qos_flags);
/* The fw does not distinguish between ht and fat */
@@ -629,17 +634,17 @@ __le32 iwl_mvm_mac_ctxt_cmd_p2p_sta_get_oppps_ctwin(struct iwl_mvm *mvm,
IEEE80211_P2P_OPPPS_CTWINDOW_MASK);
}
-__le32 iwl_mvm_mac_ctxt_cmd_sta_get_twt_policy(struct iwl_mvm *mvm,
- struct ieee80211_vif *vif)
+u32 iwl_mvm_mac_ctxt_cmd_sta_get_twt_policy(struct iwl_mvm *mvm,
+ struct ieee80211_vif *vif)
{
- __le32 twt_policy = cpu_to_le32(0);
+ u32 twt_policy = 0;
if (vif->bss_conf.twt_requester && IWL_MVM_USE_TWT)
- twt_policy |= cpu_to_le32(TWT_SUPPORTED);
+ twt_policy |= TWT_SUPPORTED;
if (vif->bss_conf.twt_protected)
- twt_policy |= cpu_to_le32(PROTECTED_TWT_SUPPORTED);
+ twt_policy |= PROTECTED_TWT_SUPPORTED;
if (vif->bss_conf.twt_broadcast)
- twt_policy |= cpu_to_le32(BROADCAST_TWT_SUPPORTED);
+ twt_policy |= BROADCAST_TWT_SUPPORTED;
return twt_policy;
}
@@ -711,7 +716,7 @@ static int iwl_mvm_mac_ctxt_cmd_sta(struct iwl_mvm *mvm,
if (vif->bss_conf.he_support && !iwlwifi_mod_params.disable_11ax) {
cmd.filter_flags |= cpu_to_le32(MAC_FILTER_IN_11AX);
ctxt_sta->data_policy |=
- iwl_mvm_mac_ctxt_cmd_sta_get_twt_policy(mvm, vif);
+ cpu_to_le32(iwl_mvm_mac_ctxt_cmd_sta_get_twt_policy(mvm, vif));
}
@@ -888,7 +893,7 @@ u8 iwl_mvm_mac_ctxt_get_lowest_rate(struct iwl_mvm *mvm,
u8 rate;
u32 i;
- if (link_id == IEEE80211_LINK_UNSPECIFIED && vif->valid_links) {
+ if (link_id == IEEE80211_LINK_UNSPECIFIED && ieee80211_vif_is_mld(vif)) {
for (i = 0; i < ARRAY_SIZE(mvmvif->link); i++) {
if (!mvmvif->link[i])
continue;
@@ -1111,6 +1116,10 @@ static int iwl_mvm_mac_ctxt_send_beacon_v9(struct iwl_mvm *mvm,
beacon_cmd.flags = cpu_to_le16(flags);
beacon_cmd.byte_cnt = cpu_to_le16((u16)beacon->len);
+
+ if (WARN_ON(!mvmvif->link[link_conf->link_id]))
+ return -EINVAL;
+
if (iwl_fw_lookup_cmd_ver(mvm->fw, BEACON_TEMPLATE_CMD, 0) > 12)
beacon_cmd.link_id =
cpu_to_le32(mvmvif->link[link_conf->link_id]->fw_link_id);
@@ -1555,21 +1564,38 @@ void iwl_mvm_rx_missed_beacons_notif(struct iwl_mvm *mvm,
u32 stop_trig_missed_bcon, stop_trig_missed_bcon_since_rx;
u32 rx_missed_bcon, rx_missed_bcon_since_rx;
struct ieee80211_vif *vif;
- u32 id = le32_to_cpu(mb->mac_id);
+ /* Id can be mac/link id depending on the notification version */
+ u32 id = le32_to_cpu(mb->link_id);
union iwl_dbg_tlv_tp_data tp_data = { .fw_pkt = pkt };
u32 mac_type;
+ u8 notif_ver = iwl_fw_lookup_notif_ver(mvm->fw, LEGACY_GROUP,
+ MISSED_BEACONS_NOTIFICATION,
+ 0);
+
+ rcu_read_lock();
+
+ /* before version four the ID in the notification refers to mac ID */
+ if (notif_ver < 4) {
+ vif = iwl_mvm_rcu_dereference_vif_id(mvm, id, true);
+ } else {
+ struct ieee80211_bss_conf *bss_conf =
+ iwl_mvm_rcu_fw_link_id_to_link_conf(mvm, id, true);
+
+ if (!bss_conf)
+ goto out;
+
+ vif = bss_conf->vif;
+ }
IWL_DEBUG_INFO(mvm,
- "missed bcn mac_id=%u, consecutive=%u (%u, %u, %u)\n",
- le32_to_cpu(mb->mac_id),
+ "missed bcn %s_id=%u, consecutive=%u (%u, %u, %u)\n",
+ notif_ver < 4 ? "mac" : "link",
+ id,
le32_to_cpu(mb->consec_missed_beacons),
le32_to_cpu(mb->consec_missed_beacons_since_last_rx),
le32_to_cpu(mb->num_recvd_beacons),
le32_to_cpu(mb->num_expected_beacons));
- rcu_read_lock();
-
- vif = iwl_mvm_rcu_dereference_vif_id(mvm, id, true);
if (!vif)
goto out;
@@ -1730,20 +1756,47 @@ void iwl_mvm_channel_switch_start_notif(struct iwl_mvm *mvm,
struct iwl_rx_cmd_buffer *rxb)
{
struct iwl_rx_packet *pkt = rxb_addr(rxb);
- struct iwl_channel_switch_start_notif *notif = (void *)pkt->data;
struct ieee80211_vif *csa_vif, *vif;
- struct iwl_mvm_vif *mvmvif;
- u32 id_n_color, csa_id, mac_id;
+ struct iwl_mvm_vif *mvmvif, *csa_mvmvif;
+ u32 id_n_color, csa_id;
+ /* save mac_id or link_id to use later to cancel csa if needed */
+ u32 id;
+ u8 notif_ver = iwl_fw_lookup_notif_ver(mvm->fw, MAC_CONF_GROUP,
+ CHANNEL_SWITCH_START_NOTIF, 0);
+ bool csa_active;
- id_n_color = le32_to_cpu(notif->id_and_color);
- mac_id = id_n_color & FW_CTXT_ID_MSK;
+ rcu_read_lock();
- if (WARN_ON_ONCE(mac_id >= NUM_MAC_INDEX_DRIVER))
- return;
+ if (notif_ver < 3) {
+ struct iwl_channel_switch_start_notif_v1 *notif = (void *)pkt->data;
+ u32 mac_id;
+
+ id_n_color = le32_to_cpu(notif->id_and_color);
+ mac_id = id_n_color & FW_CTXT_ID_MSK;
+
+ vif = iwl_mvm_rcu_dereference_vif_id(mvm, mac_id, true);
+ if (!vif)
+ goto out_unlock;
+
+ id = mac_id;
+ csa_active = vif->bss_conf.csa_active;
+ } else {
+ struct iwl_channel_switch_start_notif *notif = (void *)pkt->data;
+ u32 link_id = le32_to_cpu(notif->link_id);
+ struct ieee80211_bss_conf *bss_conf =
+ iwl_mvm_rcu_fw_link_id_to_link_conf(mvm, link_id, true);
+
+ if (!bss_conf)
+ goto out_unlock;
+
+ id = link_id;
+ vif = bss_conf->vif;
+ csa_active = bss_conf->csa_active;
+ }
- rcu_read_lock();
- vif = rcu_dereference(mvm->vif_id_to_mac[mac_id]);
mvmvif = iwl_mvm_vif_from_mac80211(vif);
+ if (notif_ver >= 3)
+ id_n_color = FW_CMD_ID_AND_COLOR(mvmvif->id, mvmvif->color);
switch (vif->type) {
case NL80211_IFTYPE_AP:
@@ -1752,7 +1805,8 @@ void iwl_mvm_channel_switch_start_notif(struct iwl_mvm *mvm,
csa_vif != vif))
goto out_unlock;
- csa_id = FW_CMD_ID_AND_COLOR(mvmvif->id, mvmvif->color);
+ csa_mvmvif = iwl_mvm_vif_from_mac80211(csa_vif);
+ csa_id = FW_CMD_ID_AND_COLOR(csa_mvmvif->id, csa_mvmvif->color);
if (WARN(csa_id != id_n_color,
"channel switch noa notification on unexpected vif (csa_vif=%d, notif=%d)",
csa_id, id_n_color))
@@ -1777,9 +1831,9 @@ void iwl_mvm_channel_switch_start_notif(struct iwl_mvm *mvm,
*/
if (iwl_fw_lookup_notif_ver(mvm->fw, MAC_CONF_GROUP,
CHANNEL_SWITCH_ERROR_NOTIF,
- 0) && !vif->bss_conf.csa_active) {
+ 0) && !csa_active) {
IWL_DEBUG_INFO(mvm, "Channel Switch was canceled\n");
- iwl_mvm_cancel_channel_switch(mvm, vif, mac_id);
+ iwl_mvm_cancel_channel_switch(mvm, vif, id);
break;
}
@@ -1802,7 +1856,7 @@ void iwl_mvm_channel_switch_error_notif(struct iwl_mvm *mvm,
struct iwl_rx_packet *pkt = rxb_addr(rxb);
struct iwl_channel_switch_error_notif *notif = (void *)pkt->data;
struct ieee80211_vif *vif;
- u32 id = le32_to_cpu(notif->mac_id);
+ u32 id = le32_to_cpu(notif->link_id);
u32 csa_err_mask = le32_to_cpu(notif->csa_err_mask);
rcu_read_lock();
@@ -1812,7 +1866,7 @@ void iwl_mvm_channel_switch_error_notif(struct iwl_mvm *mvm,
return;
}
- IWL_DEBUG_INFO(mvm, "FW reports CSA error: mac_id=%u, csa_err_mask=%u\n",
+ IWL_DEBUG_INFO(mvm, "FW reports CSA error: id=%u, csa_err_mask=%u\n",
id, csa_err_mask);
if (csa_err_mask & (CS_ERR_COUNT_ERROR |
CS_ERR_LONG_DELAY_AFTER_CS |
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c b/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c
index 17f788a5ff6b..ce7905faa08f 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c
@@ -108,7 +108,7 @@ struct ieee80211_regdomain *iwl_mvm_get_regdomain(struct wiphy *wiphy,
struct ieee80211_regdomain *regd = NULL;
struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
struct iwl_mvm *mvm = IWL_MAC80211_GET_MVM(hw);
- struct iwl_mcc_update_resp *resp;
+ struct iwl_mcc_update_resp_v8 *resp;
u8 resp_ver;
IWL_DEBUG_LAR(mvm, "Getting regdomain data for %s from FW\n", alpha2);
@@ -138,7 +138,7 @@ struct ieee80211_regdomain *iwl_mvm_get_regdomain(struct wiphy *wiphy,
resp->channels,
__le16_to_cpu(resp->mcc),
__le16_to_cpu(resp->geo_info),
- __le16_to_cpu(resp->cap), resp_ver);
+ le32_to_cpu(resp->cap), resp_ver);
/* Store the return source id */
src_id = resp->source_id;
if (IS_ERR_OR_NULL(regd)) {
@@ -245,12 +245,21 @@ static const u8 tm_if_types_ext_capa_sta[] = {
/* Additional interface types for which extended capabilities are
* specified separately
*/
+
+#define IWL_MVM_EMLSR_CAPA (IEEE80211_EML_CAP_EMLSR_SUPP | \
+ IEEE80211_EML_CAP_EMLSR_PADDING_DELAY_32US << \
+ __bf_shf(IEEE80211_EML_CAP_EMLSR_PADDING_DELAY) | \
+ IEEE80211_EML_CAP_EMLSR_TRANSITION_DELAY_64US << \
+ __bf_shf(IEEE80211_EML_CAP_EMLSR_TRANSITION_DELAY))
+
static const struct wiphy_iftype_ext_capab add_iftypes_ext_capa[] = {
{
.iftype = NL80211_IFTYPE_STATION,
.extended_capabilities = he_if_types_ext_capa_sta,
.extended_capabilities_mask = he_if_types_ext_capa_sta,
.extended_capabilities_len = sizeof(he_if_types_ext_capa_sta),
+ /* relevant only if EHT is supported */
+ .eml_capabilities = IWL_MVM_EMLSR_CAPA,
},
{
.iftype = NL80211_IFTYPE_STATION,
@@ -258,7 +267,7 @@ static const struct wiphy_iftype_ext_capab add_iftypes_ext_capa[] = {
.extended_capabilities_mask = tm_if_types_ext_capa_sta,
.extended_capabilities_len = sizeof(tm_if_types_ext_capa_sta),
/* relevant only if EHT is supported */
- .eml_capabilities = IEEE80211_EML_CAP_EMLSR_SUPP,
+ .eml_capabilities = IWL_MVM_EMLSR_CAPA,
},
};
@@ -1029,6 +1038,7 @@ static void iwl_mvm_cleanup_iterator(void *data, u8 *mac,
mvmvif->link[link_id]->fw_link_id = IWL_MVM_FW_LINK_ID_INVALID;
mvmvif->link[link_id]->phy_ctxt = NULL;
mvmvif->link[link_id]->active = 0;
+ mvmvif->link[link_id]->igtk = NULL;
}
probe_data = rcu_dereference_protected(mvmvif->deflink.probe_resp_data,
@@ -1233,7 +1243,7 @@ void __iwl_mvm_mac_stop(struct iwl_mvm *mvm)
/* async_handlers_wk is now blocked */
- if (iwl_fw_lookup_cmd_ver(mvm->fw, ADD_STA, 0) < 12)
+ if (!iwl_mvm_has_new_station_api(mvm->fw))
iwl_mvm_rm_aux_sta(mvm);
iwl_mvm_stop_device(mvm);
@@ -1478,21 +1488,37 @@ iwl_mvm_chandef_get_primary_80(struct cfg80211_chan_def *chandef)
return (control_start - data_start) / 80;
}
-/*
- * Returns true if addding the interface is done
- * (either with success or failure)
- *
- * FIXME: remove this again and merge it in
- */
-static bool iwl_mvm_mac_add_interface_common(struct iwl_mvm *mvm,
- struct ieee80211_hw *hw,
- struct ieee80211_vif *vif,
- int *ret)
+static int iwl_mvm_alloc_bcast_mcast_sta(struct iwl_mvm *mvm,
+ struct ieee80211_vif *vif)
{
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
+ int ret;
lockdep_assert_held(&mvm->mutex);
+ ret = iwl_mvm_alloc_bcast_sta(mvm, vif);
+ if (ret) {
+ IWL_ERR(mvm, "Failed to allocate bcast sta\n");
+ return ret;
+ }
+
+ /* Only queue for this station is the mcast queue,
+ * which shouldn't be in TFD mask anyway
+ */
+ return iwl_mvm_allocate_int_sta(mvm, &mvmvif->deflink.mcast_sta, 0,
+ vif->type,
+ IWL_STA_MULTICAST);
+}
+
+static int iwl_mvm_mac_add_interface(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif)
+{
+ struct iwl_mvm *mvm = IWL_MAC80211_GET_MVM(hw);
+ struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
+ int ret;
+
+ mutex_lock(&mvm->mutex);
+
mvmvif->mvm = mvm;
/* the first link always points to the default one */
@@ -1510,12 +1536,18 @@ static bool iwl_mvm_mac_add_interface_common(struct iwl_mvm *mvm,
mvmvif->deflink.beacon_stats.num_beacons;
/* Allocate resources for the MAC context, and add it to the fw */
- *ret = iwl_mvm_mac_ctxt_init(mvm, vif);
- if (*ret)
- return true;
+ ret = iwl_mvm_mac_ctxt_init(mvm, vif);
+ if (ret)
+ goto out;
rcu_assign_pointer(mvm->vif_id_to_mac[mvmvif->id], vif);
+ /* Currently not much to do for NAN */
+ if (vif->type == NL80211_IFTYPE_NAN) {
+ ret = 0;
+ goto out;
+ }
+
/*
* The AP binding flow can be done only after the beacon
* template is configured (which happens only in the mac80211
@@ -1530,50 +1562,12 @@ static bool iwl_mvm_mac_add_interface_common(struct iwl_mvm *mvm,
if (vif->type == NL80211_IFTYPE_AP ||
vif->type == NL80211_IFTYPE_ADHOC) {
iwl_mvm_vif_dbgfs_register(mvm, vif);
- return true;
+ ret = 0;
+ goto out;
}
mvmvif->features |= hw->netdev_features;
- return false;
-}
-
-static int iwl_mvm_alloc_bcast_mcast_sta(struct iwl_mvm *mvm,
- struct ieee80211_vif *vif)
-{
- struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
- int ret;
-
- lockdep_assert_held(&mvm->mutex);
-
- ret = iwl_mvm_alloc_bcast_sta(mvm, vif);
- if (ret) {
- IWL_ERR(mvm, "Failed to allocate bcast sta\n");
- return ret;
- }
-
- /*
- * Only queue for this station is the mcast queue,
- * which shouldn't be in TFD mask anyway
- */
- return iwl_mvm_allocate_int_sta(mvm, &mvmvif->deflink.mcast_sta, 0,
- vif->type,
- IWL_STA_MULTICAST);
-}
-
-static int iwl_mvm_mac_add_interface(struct ieee80211_hw *hw,
- struct ieee80211_vif *vif)
-{
- struct iwl_mvm *mvm = IWL_MAC80211_GET_MVM(hw);
- struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
- int ret;
-
- mutex_lock(&mvm->mutex);
-
- /* Common for MLD and non-MLD API */
- if (iwl_mvm_mac_add_interface_common(mvm, hw, vif, &ret))
- goto out;
-
ret = iwl_mvm_mac_ctxt_add(mvm, vif);
if (ret)
goto out_unlock;
@@ -2246,7 +2240,7 @@ int iwl_mvm_set_sta_pkt_ext(struct iwl_mvm *mvm,
* is enabled or not
*/
bool iwl_mvm_set_fw_mu_edca_params(struct iwl_mvm *mvm,
- struct iwl_mvm_vif *mvmvif,
+ const struct iwl_mvm_vif_link_info *link_info,
struct iwl_he_backoff_conf *trig_based_txf)
{
int i;
@@ -2254,11 +2248,11 @@ bool iwl_mvm_set_fw_mu_edca_params(struct iwl_mvm *mvm,
bool mu_edca_enabled = true;
for (i = 0; i < IEEE80211_NUM_ACS; i++) {
- struct ieee80211_he_mu_edca_param_ac_rec *mu_edca =
- &mvmvif->deflink.queue_params[i].mu_edca_param_rec;
+ const struct ieee80211_he_mu_edca_param_ac_rec *mu_edca =
+ &link_info->queue_params[i].mu_edca_param_rec;
u8 ac = iwl_mvm_mac80211_ac_to_ucode_ac(i);
- if (!mvmvif->deflink.queue_params[i].mu_edca) {
+ if (!link_info->queue_params[i].mu_edca) {
mu_edca_enabled = false;
break;
}
@@ -2285,8 +2279,7 @@ bool iwl_mvm_is_nic_ack_enabled(struct iwl_mvm *mvm, struct ieee80211_vif *vif)
* so take it from one of them.
*/
sband = mvm->hw->wiphy->bands[NL80211_BAND_2GHZ];
- own_he_cap = ieee80211_get_he_iftype_cap(sband,
- ieee80211_vif_type_p2p(vif));
+ own_he_cap = ieee80211_get_he_iftype_cap_vif(sband, vif);
return (own_he_cap && (own_he_cap->he_cap_elem.mac_cap_info[2] &
IEEE80211_HE_MAC_CAP2_ACK_EN));
@@ -2405,7 +2398,7 @@ static void iwl_mvm_cfg_he_sta(struct iwl_mvm *mvm,
rcu_read_unlock();
- if (iwl_mvm_set_fw_mu_edca_params(mvm, mvmvif,
+ if (iwl_mvm_set_fw_mu_edca_params(mvm, &mvmvif->deflink,
&sta_ctxt_cmd.trig_based_txf[0]))
flags |= STA_CTXT_HE_MU_EDCA_CW;
@@ -2898,7 +2891,7 @@ static int iwl_mvm_start_ap_ibss(struct ieee80211_hw *hw,
if (iwl_mvm_phy_ctx_count(mvm) > 1)
iwl_mvm_teardown_tdls_peers(mvm);
- iwl_mvm_ftm_restart_responder(mvm, vif);
+ iwl_mvm_ftm_restart_responder(mvm, vif, &vif->bss_conf);
goto out_unlock;
@@ -3040,7 +3033,7 @@ iwl_mvm_bss_info_changed_ap_ibss(struct iwl_mvm *mvm,
IWL_WARN(mvm, "Failed updating beacon data\n");
if (changes & BSS_CHANGED_FTM_RESPONDER) {
- int ret = iwl_mvm_ftm_start_responder(mvm, vif);
+ int ret = iwl_mvm_ftm_start_responder(mvm, vif, &vif->bss_conf);
if (ret)
IWL_WARN(mvm, "Failed to enable FTM responder (%d)\n",
@@ -3054,7 +3047,7 @@ static void iwl_mvm_bss_info_changed(struct ieee80211_hw *hw,
struct ieee80211_bss_conf *bss_conf,
u64 changes)
{
- struct iwl_mvm_bss_info_changed_ops callbacks = {
+ static const struct iwl_mvm_bss_info_changed_ops callbacks = {
.bss_info_changed_sta = iwl_mvm_bss_info_changed_station,
.bss_info_changed_ap_ibss = iwl_mvm_bss_info_changed_ap_ibss,
};
@@ -3067,7 +3060,7 @@ void
iwl_mvm_bss_info_changed_common(struct ieee80211_hw *hw,
struct ieee80211_vif *vif,
struct ieee80211_bss_conf *bss_conf,
- struct iwl_mvm_bss_info_changed_ops *callbacks,
+ const struct iwl_mvm_bss_info_changed_ops *callbacks,
u64 changes)
{
struct iwl_mvm *mvm = IWL_MAC80211_GET_MVM(hw);
@@ -3468,8 +3461,7 @@ static void iwl_mvm_reset_cca_40mhz_workaround(struct iwl_mvm *mvm,
sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
- he_cap = ieee80211_get_he_iftype_cap(sband,
- ieee80211_vif_type_p2p(vif));
+ he_cap = ieee80211_get_he_iftype_cap_vif(sband, vif);
if (he_cap) {
/* we know that ours is writable */
@@ -3564,7 +3556,7 @@ static int iwl_mvm_mac_sta_state(struct ieee80211_hw *hw,
enum ieee80211_sta_state old_state,
enum ieee80211_sta_state new_state)
{
- struct iwl_mvm_sta_state_ops callbacks = {
+ static const struct iwl_mvm_sta_state_ops callbacks = {
.add_sta = iwl_mvm_add_sta,
.update_sta = iwl_mvm_update_sta,
.rm_sta = iwl_mvm_rm_sta,
@@ -3669,7 +3661,7 @@ static int
iwl_mvm_sta_state_notexist_to_none(struct iwl_mvm *mvm,
struct ieee80211_vif *vif,
struct ieee80211_sta *sta,
- struct iwl_mvm_sta_state_ops *callbacks)
+ const struct iwl_mvm_sta_state_ops *callbacks)
{
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
struct ieee80211_link_sta *link_sta;
@@ -3713,7 +3705,7 @@ iwl_mvm_sta_state_auth_to_assoc(struct ieee80211_hw *hw,
struct iwl_mvm *mvm,
struct ieee80211_vif *vif,
struct ieee80211_sta *sta,
- struct iwl_mvm_sta_state_ops *callbacks)
+ const struct iwl_mvm_sta_state_ops *callbacks)
{
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
struct iwl_mvm_sta *mvm_sta = iwl_mvm_sta_from_mac80211(sta);
@@ -3770,7 +3762,7 @@ static int
iwl_mvm_sta_state_assoc_to_authorized(struct iwl_mvm *mvm,
struct ieee80211_vif *vif,
struct ieee80211_sta *sta,
- struct iwl_mvm_sta_state_ops *callbacks)
+ const struct iwl_mvm_sta_state_ops *callbacks)
{
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
struct iwl_mvm_sta *mvm_sta = iwl_mvm_sta_from_mac80211(sta);
@@ -3805,11 +3797,10 @@ static int
iwl_mvm_sta_state_authorized_to_assoc(struct iwl_mvm *mvm,
struct ieee80211_vif *vif,
struct ieee80211_sta *sta,
- struct iwl_mvm_sta_state_ops *callbacks)
+ const struct iwl_mvm_sta_state_ops *callbacks)
{
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
struct iwl_mvm_sta *mvmsta = iwl_mvm_sta_from_mac80211(sta);
- int ret;
lockdep_assert_held(&mvm->mutex);
@@ -3828,10 +3819,7 @@ iwl_mvm_sta_state_authorized_to_assoc(struct iwl_mvm *mvm,
mvmvif->authorized = 0;
/* disable beacon filtering */
- ret = iwl_mvm_disable_beacon_filter(mvm, vif, 0);
- WARN_ON(ret &&
- !test_bit(IWL_MVM_STATUS_HW_RESTART_REQUESTED,
- &mvm->status));
+ iwl_mvm_disable_beacon_filter(mvm, vif, 0);
}
return 0;
@@ -3843,11 +3831,12 @@ int iwl_mvm_mac_sta_state_common(struct ieee80211_hw *hw,
struct ieee80211_sta *sta,
enum ieee80211_sta_state old_state,
enum ieee80211_sta_state new_state,
- struct iwl_mvm_sta_state_ops *callbacks)
+ const struct iwl_mvm_sta_state_ops *callbacks)
{
struct iwl_mvm *mvm = IWL_MAC80211_GET_MVM(hw);
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
struct iwl_mvm_sta *mvm_sta = iwl_mvm_sta_from_mac80211(sta);
+ struct ieee80211_link_sta *link_sta;
unsigned int link_id;
int ret;
@@ -3889,7 +3878,7 @@ int iwl_mvm_mac_sta_state_common(struct ieee80211_hw *hw,
mutex_lock(&mvm->mutex);
/* this would be a mac80211 bug ... but don't crash */
- for_each_mvm_vif_valid_link(mvmvif, link_id) {
+ for_each_sta_active_link(vif, sta, link_sta, link_id) {
if (WARN_ON_ONCE(!mvmvif->link[link_id]->phy_ctxt)) {
mutex_unlock(&mvm->mutex);
return test_bit(IWL_MVM_STATUS_HW_RESTART_REQUESTED,
@@ -4533,7 +4522,7 @@ static int iwl_mvm_add_aux_sta_for_hs20(struct iwl_mvm *mvm, u32 lmac_id)
return -EINVAL;
}
- if (iwl_fw_lookup_cmd_ver(mvm->fw, ADD_STA, 0) >= 12) {
+ if (iwl_mvm_has_new_station_api(mvm->fw)) {
ret = iwl_mvm_add_aux_sta(mvm, lmac_id);
WARN(ret, "Failed to allocate aux station");
}
@@ -4573,7 +4562,7 @@ static int iwl_mvm_roc(struct ieee80211_hw *hw,
int duration,
enum ieee80211_roc_type type)
{
- struct iwl_mvm_roc_ops ops = {
+ static const struct iwl_mvm_roc_ops ops = {
.add_aux_sta_for_hs20 = iwl_mvm_add_aux_sta_for_hs20,
.switch_phy_ctxt = iwl_mvm_roc_switch_binding,
};
@@ -4585,7 +4574,7 @@ static int iwl_mvm_roc(struct ieee80211_hw *hw,
int iwl_mvm_roc_common(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
struct ieee80211_channel *channel, int duration,
enum ieee80211_roc_type type,
- struct iwl_mvm_roc_ops *ops)
+ const struct iwl_mvm_roc_ops *ops)
{
struct iwl_mvm *mvm = IWL_MAC80211_GET_MVM(hw);
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
@@ -4608,7 +4597,7 @@ int iwl_mvm_roc_common(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
switch (vif->type) {
case NL80211_IFTYPE_STATION:
- lmac_id = iwl_mvm_get_lmac_id(mvm->fw, channel->band);
+ lmac_id = iwl_mvm_get_lmac_id(mvm, channel->band);
/* Use aux roc framework (HS20) */
ret = ops->add_aux_sta_for_hs20(mvm, lmac_id);
@@ -5092,7 +5081,7 @@ static void iwl_mvm_unassign_vif_chanctx(struct ieee80211_hw *hw,
static int
iwl_mvm_switch_vif_chanctx_swap(struct iwl_mvm *mvm,
struct ieee80211_vif_chanctx_switch *vifs,
- struct iwl_mvm_switch_vif_chanctx_ops *ops)
+ const struct iwl_mvm_switch_vif_chanctx_ops *ops)
{
int ret;
@@ -5151,7 +5140,7 @@ out:
static int
iwl_mvm_switch_vif_chanctx_reassign(struct iwl_mvm *mvm,
struct ieee80211_vif_chanctx_switch *vifs,
- struct iwl_mvm_switch_vif_chanctx_ops *ops)
+ const struct iwl_mvm_switch_vif_chanctx_ops *ops)
{
int ret;
@@ -5194,7 +5183,7 @@ iwl_mvm_switch_vif_chanctx_common(struct ieee80211_hw *hw,
struct ieee80211_vif_chanctx_switch *vifs,
int n_vifs,
enum ieee80211_chanctx_switch_mode mode,
- struct iwl_mvm_switch_vif_chanctx_ops *ops)
+ const struct iwl_mvm_switch_vif_chanctx_ops *ops)
{
struct iwl_mvm *mvm = IWL_MAC80211_GET_MVM(hw);
int ret;
@@ -5223,7 +5212,7 @@ static int iwl_mvm_switch_vif_chanctx(struct ieee80211_hw *hw,
int n_vifs,
enum ieee80211_chanctx_switch_mode mode)
{
- struct iwl_mvm_switch_vif_chanctx_ops ops = {
+ static const struct iwl_mvm_switch_vif_chanctx_ops ops = {
.__assign_vif_chanctx = __iwl_mvm_assign_vif_chanctx,
.__unassign_vif_chanctx = __iwl_mvm_unassign_vif_chanctx,
};
@@ -5664,6 +5653,30 @@ void iwl_mvm_mac_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
iwl_trans_wait_tx_queues_empty(mvm->trans, msk);
}
+void iwl_mvm_mac_flush_sta(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
+ struct ieee80211_sta *sta)
+{
+ struct iwl_mvm *mvm = IWL_MAC80211_GET_MVM(hw);
+ int i;
+
+ mutex_lock(&mvm->mutex);
+ for (i = 0; i < mvm->fw->ucode_capa.num_stations; i++) {
+ struct iwl_mvm_sta *mvmsta;
+ struct ieee80211_sta *tmp;
+
+ tmp = rcu_dereference_protected(mvm->fw_id_to_mac_id[i],
+ lockdep_is_held(&mvm->mutex));
+ if (tmp != sta)
+ continue;
+
+ mvmsta = iwl_mvm_sta_from_mac80211(sta);
+
+ if (iwl_mvm_flush_sta(mvm, mvmsta, false))
+ IWL_ERR(mvm, "flush request fail\n");
+ }
+ mutex_unlock(&mvm->mutex);
+}
+
int iwl_mvm_mac_get_survey(struct ieee80211_hw *hw, int idx,
struct survey_info *survey)
{
@@ -6154,10 +6167,6 @@ static bool iwl_mvm_mac_can_aggregate(struct ieee80211_hw *hw,
{
struct iwl_mvm *mvm = IWL_MAC80211_GET_MVM(hw);
- if (iwl_mvm_has_new_tx_csum(mvm))
- return iwl_mvm_tx_csum_bz(mvm, head, true) ==
- iwl_mvm_tx_csum_bz(mvm, skb, true);
-
/* For now don't aggregate IPv6 in AMSDU */
if (skb->protocol != htons(ETH_P_IP))
return false;
@@ -6220,6 +6229,7 @@ const struct ieee80211_ops iwl_mvm_hw_ops = {
.mgd_complete_tx = iwl_mvm_mac_mgd_complete_tx,
.mgd_protect_tdls_discover = iwl_mvm_mac_mgd_protect_tdls_discover,
.flush = iwl_mvm_mac_flush,
+ .flush_sta = iwl_mvm_mac_flush_sta,
.sched_scan_start = iwl_mvm_mac_sched_scan_start,
.sched_scan_stop = iwl_mvm_mac_sched_scan_stop,
.set_key = iwl_mvm_mac_set_key,
@@ -6277,7 +6287,7 @@ const struct ieee80211_ops iwl_mvm_hw_ops = {
.can_aggregate_in_amsdu = iwl_mvm_mac_can_aggregate,
#ifdef CONFIG_IWLWIFI_DEBUGFS
- .sta_add_debugfs = iwl_mvm_sta_add_debugfs,
+ .link_sta_add_debugfs = iwl_mvm_link_sta_add_debugfs,
#endif
.set_hw_timestamp = iwl_mvm_set_hw_timestamp,
};
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/mld-key.c b/drivers/net/wireless/intel/iwlwifi/mvm/mld-key.c
index 8853821b3716..2c9f2f71b083 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/mld-key.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/mld-key.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
- * Copyright (C) 2022 Intel Corporation
+ * Copyright (C) 2022 - 2023 Intel Corporation
*/
#include <linux/kernel.h>
#include <net/mac80211.h>
@@ -42,7 +42,7 @@ static u32 iwl_mvm_get_sec_sta_mask(struct iwl_mvm *mvm,
* Of course the same can be done during add as well, but we must do
* it during remove, since we don't have the mvmvif->ap_sta pointer.
*/
- if (!sta && (keyconf->link_id >= 0 || !vif->valid_links))
+ if (!sta && (keyconf->link_id >= 0 || !ieee80211_vif_is_mld(vif)))
return BIT(link_info->ap_sta_id);
/* STA should be non-NULL now, but iwl_mvm_sta_fw_id_mask() checks */
@@ -51,10 +51,10 @@ static u32 iwl_mvm_get_sec_sta_mask(struct iwl_mvm *mvm,
return iwl_mvm_sta_fw_id_mask(mvm, sta, keyconf->link_id);
}
-static u32 iwl_mvm_get_sec_flags(struct iwl_mvm *mvm,
- struct ieee80211_vif *vif,
- struct ieee80211_sta *sta,
- struct ieee80211_key_conf *keyconf)
+u32 iwl_mvm_get_sec_flags(struct iwl_mvm *mvm,
+ struct ieee80211_vif *vif,
+ struct ieee80211_sta *sta,
+ struct ieee80211_key_conf *keyconf)
{
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
u32 flags = 0;
@@ -164,13 +164,9 @@ static int __iwl_mvm_sec_key_del(struct iwl_mvm *mvm, u32 sta_mask,
return iwl_mvm_send_cmd_pdu(mvm, cmd_id, flags, sizeof(cmd), &cmd);
}
-int iwl_mvm_sec_key_add(struct iwl_mvm *mvm,
- struct ieee80211_vif *vif,
- struct ieee80211_sta *sta,
- struct ieee80211_key_conf *keyconf)
+int iwl_mvm_mld_send_key(struct iwl_mvm *mvm, u32 sta_mask, u32 key_flags,
+ struct ieee80211_key_conf *keyconf)
{
- u32 sta_mask = iwl_mvm_get_sec_sta_mask(mvm, vif, sta, keyconf);
- u32 key_flags = iwl_mvm_get_sec_flags(mvm, vif, sta, keyconf);
u32 cmd_id = WIDE_ID(DATA_PATH_GROUP, SEC_KEY_CMD);
struct iwl_sec_key_cmd cmd = {
.action = cpu_to_le32(FW_CTXT_ACTION_ADD),
@@ -179,9 +175,14 @@ int iwl_mvm_sec_key_add(struct iwl_mvm *mvm,
.u.add.key_flags = cpu_to_le32(key_flags),
.u.add.tx_seq = cpu_to_le64(atomic64_read(&keyconf->tx_pn)),
};
+ int max_key_len = sizeof(cmd.u.add.key);
int ret;
- if (WARN_ON(keyconf->keylen > sizeof(cmd.u.add.key)))
+ if (keyconf->cipher == WLAN_CIPHER_SUITE_WEP40 ||
+ keyconf->cipher == WLAN_CIPHER_SUITE_WEP104)
+ max_key_len -= IWL_SEC_WEP_KEY_OFFSET;
+
+ if (WARN_ON(keyconf->keylen > max_key_len))
return -EINVAL;
if (WARN_ON(!sta_mask))
@@ -223,6 +224,58 @@ int iwl_mvm_sec_key_add(struct iwl_mvm *mvm,
return ret;
}
+int iwl_mvm_sec_key_add(struct iwl_mvm *mvm,
+ struct ieee80211_vif *vif,
+ struct ieee80211_sta *sta,
+ struct ieee80211_key_conf *keyconf)
+{
+ u32 sta_mask = iwl_mvm_get_sec_sta_mask(mvm, vif, sta, keyconf);
+ u32 key_flags = iwl_mvm_get_sec_flags(mvm, vif, sta, keyconf);
+ struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
+ struct iwl_mvm_vif_link_info *mvm_link = NULL;
+ int ret;
+
+ if (keyconf->keyidx == 4 || keyconf->keyidx == 5) {
+ unsigned int link_id = 0;
+
+ /* set to -1 for non-MLO right now */
+ if (keyconf->link_id >= 0)
+ link_id = keyconf->link_id;
+
+ mvm_link = mvmvif->link[link_id];
+ if (WARN_ON(!mvm_link))
+ return -EINVAL;
+
+ if (mvm_link->igtk) {
+ IWL_DEBUG_MAC80211(mvm, "remove old IGTK %d\n",
+ mvm_link->igtk->keyidx);
+ ret = iwl_mvm_sec_key_del(mvm, vif, sta,
+ mvm_link->igtk);
+ if (ret)
+ IWL_ERR(mvm,
+ "failed to remove old IGTK (ret=%d)\n",
+ ret);
+ }
+
+ WARN_ON(mvm_link->igtk);
+ }
+
+ ret = iwl_mvm_mld_send_key(mvm, sta_mask, key_flags, keyconf);
+ if (ret)
+ return ret;
+
+ if (mvm_link)
+ mvm_link->igtk = keyconf;
+
+ /* We don't really need this, but need it to be not invalid,
+ * and if we switch links multiple times it might go to be
+ * invalid when removed.
+ */
+ keyconf->hw_key_idx = 0;
+
+ return 0;
+}
+
static int _iwl_mvm_sec_key_del(struct iwl_mvm *mvm,
struct ieee80211_vif *vif,
struct ieee80211_sta *sta,
@@ -231,11 +284,31 @@ static int _iwl_mvm_sec_key_del(struct iwl_mvm *mvm,
{
u32 sta_mask = iwl_mvm_get_sec_sta_mask(mvm, vif, sta, keyconf);
u32 key_flags = iwl_mvm_get_sec_flags(mvm, vif, sta, keyconf);
+ struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
int ret;
if (WARN_ON(!sta_mask))
return -EINVAL;
+ if (keyconf->keyidx == 4 || keyconf->keyidx == 5) {
+ struct iwl_mvm_vif_link_info *mvm_link;
+ unsigned int link_id = 0;
+
+ /* set to -1 for non-MLO right now */
+ if (keyconf->link_id >= 0)
+ link_id = keyconf->link_id;
+
+ mvm_link = mvmvif->link[link_id];
+ if (WARN_ON(!mvm_link))
+ return -EINVAL;
+
+ if (mvm_link->igtk == keyconf) {
+ /* no longer in HW - mark for later */
+ mvm_link->igtk->hw_key_idx = STA_KEY_IDX_INVALID;
+ mvm_link->igtk = NULL;
+ }
+ }
+
ret = __iwl_mvm_sec_key_del(mvm, sta_mask, key_flags, keyconf->keyidx,
flags);
if (ret)
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/mld-mac.c b/drivers/net/wireless/intel/iwlwifi/mvm/mld-mac.c
index 1717fb52dc12..f313a8d771e4 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/mld-mac.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/mld-mac.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
- * Copyright (C) 2022 Intel Corporation
+ * Copyright (C) 2022 - 2023 Intel Corporation
*/
#include "mvm.h"
@@ -50,7 +50,7 @@ static void iwl_mvm_mld_mac_ctxt_cmd_common(struct iwl_mvm *mvm,
* the association response successfully, so just skip all that
* and enable both when we have MLO.
*/
- if (vif->valid_links) {
+ if (ieee80211_vif_is_mld(vif)) {
iwl_mvm_mld_set_he_support(mvm, vif, cmd);
cmd->eht_support = cpu_to_le32(1);
return;
@@ -96,6 +96,7 @@ static int iwl_mvm_mld_mac_ctxt_cmd_sta(struct iwl_mvm *mvm,
u32 action, bool force_assoc_off)
{
struct iwl_mac_config_cmd cmd = {};
+ u16 esr_transition_timeout;
WARN_ON(vif->type != NL80211_IFTYPE_STATION);
@@ -115,16 +116,16 @@ static int iwl_mvm_mld_mac_ctxt_cmd_sta(struct iwl_mvm *mvm,
if (vif->cfg.assoc && !force_assoc_off) {
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
- cmd.client.is_assoc = cpu_to_le32(1);
+ cmd.client.is_assoc = 1;
if (!mvmvif->authorized &&
fw_has_capa(&mvm->fw->ucode_capa,
IWL_UCODE_TLV_CAPA_COEX_HIGH_PRIO))
cmd.client.data_policy |=
- cpu_to_le32(COEX_HIGH_PRIORITY_ENABLE);
+ cpu_to_le16(COEX_HIGH_PRIORITY_ENABLE);
} else {
- cmd.client.is_assoc = cpu_to_le32(0);
+ cmd.client.is_assoc = 0;
/* Allow beacons to pass through as long as we are not
* associated, or we do not have dtim period information.
@@ -132,14 +133,25 @@ static int iwl_mvm_mld_mac_ctxt_cmd_sta(struct iwl_mvm *mvm,
cmd.filter_flags |= cpu_to_le32(MAC_CFG_FILTER_ACCEPT_BEACON);
}
- cmd.client.assoc_id = cpu_to_le32(vif->cfg.aid);
+ cmd.client.assoc_id = cpu_to_le16(vif->cfg.aid);
+ if (ieee80211_vif_is_mld(vif)) {
+ esr_transition_timeout =
+ u16_get_bits(vif->cfg.eml_cap,
+ IEEE80211_EML_CAP_TRANSITION_TIMEOUT);
+
+ cmd.client.esr_transition_timeout =
+ min_t(u16, IEEE80211_EML_CAP_TRANSITION_TIMEOUT_128TU,
+ esr_transition_timeout);
+ cmd.client.medium_sync_delay =
+ cpu_to_le16(vif->cfg.eml_med_sync_delay);
+ }
if (vif->probe_req_reg && vif->cfg.assoc && vif->p2p)
cmd.filter_flags |= cpu_to_le32(MAC_CFG_FILTER_ACCEPT_PROBE_REQ);
if (vif->bss_conf.he_support && !iwlwifi_mod_params.disable_11ax)
cmd.client.data_policy |=
- iwl_mvm_mac_ctxt_cmd_sta_get_twt_policy(mvm, vif);
+ cpu_to_le16(iwl_mvm_mac_ctxt_cmd_sta_get_twt_policy(mvm, vif));
return iwl_mvm_mld_mac_ctxt_send_cmd(mvm, &cmd);
}
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/mld-mac80211.c b/drivers/net/wireless/intel/iwlwifi/mvm/mld-mac80211.c
index 7fb66c570959..8b6c641772ee 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/mld-mac80211.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/mld-mac80211.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
- * Copyright (C) 2022 Intel Corporation
+ * Copyright (C) 2022-2023 Intel Corporation
*/
#include "mvm.h"
@@ -215,6 +215,53 @@ static void iwl_mvm_mld_mac_remove_interface(struct ieee80211_hw *hw,
mutex_unlock(&mvm->mutex);
}
+static unsigned int iwl_mvm_mld_count_active_links(struct ieee80211_vif *vif)
+{
+ unsigned int n_active = 0;
+ int i;
+
+ for (i = 0; i < IEEE80211_MLD_MAX_NUM_LINKS; i++) {
+ struct ieee80211_bss_conf *link_conf;
+
+ link_conf = link_conf_dereference_protected(vif, i);
+ if (link_conf &&
+ rcu_access_pointer(link_conf->chanctx_conf))
+ n_active++;
+ }
+
+ return n_active;
+}
+
+static int iwl_mvm_esr_mode_active(struct iwl_mvm *mvm,
+ struct ieee80211_vif *vif)
+{
+ struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
+ int link_id, ret = 0;
+
+ mvmvif->esr_active = true;
+
+ /* Disable SMPS overrideing by user */
+ vif->driver_flags |= IEEE80211_VIF_DISABLE_SMPS_OVERRIDE;
+
+ iwl_mvm_update_smps_on_active_links(mvm, vif, IWL_MVM_SMPS_REQ_FW,
+ IEEE80211_SMPS_OFF);
+
+ for_each_mvm_vif_valid_link(mvmvif, link_id) {
+ struct iwl_mvm_vif_link_info *link = mvmvif->link[link_id];
+
+ if (!link->phy_ctxt)
+ continue;
+
+ ret = iwl_mvm_phy_send_rlc(mvm, link->phy_ctxt, 2, 2);
+ if (ret)
+ break;
+
+ link->phy_ctxt->rlc_disabled = true;
+ }
+
+ return ret;
+}
+
static int
__iwl_mvm_mld_assign_vif_chanctx(struct iwl_mvm *mvm,
struct ieee80211_vif *vif,
@@ -224,10 +271,18 @@ __iwl_mvm_mld_assign_vif_chanctx(struct iwl_mvm *mvm,
{
u16 *phy_ctxt_id = (u16 *)ctx->drv_priv;
struct iwl_mvm_phy_ctxt *phy_ctxt = &mvm->phy_ctxts[*phy_ctxt_id];
+ unsigned int n_active = iwl_mvm_mld_count_active_links(vif);
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
unsigned int link_id = link_conf->link_id;
int ret;
+ /* if the assigned one was not counted yet, count it now */
+ if (!rcu_access_pointer(link_conf->chanctx_conf))
+ n_active++;
+
+ if (n_active > iwl_mvm_max_active_links(mvm, vif))
+ return -EOPNOTSUPP;
+
if (WARN_ON_ONCE(!mvmvif->link[link_id]))
return -EINVAL;
@@ -243,6 +298,15 @@ __iwl_mvm_mld_assign_vif_chanctx(struct iwl_mvm *mvm,
}
}
+ if (iwl_mvm_is_esr_supported(mvm->fwrt.trans) && n_active > 1) {
+ mvmvif->link[link_id]->listen_lmac = true;
+ ret = iwl_mvm_esr_mode_active(mvm, vif);
+ if (ret) {
+ IWL_ERR(mvm, "failed to activate ESR mode (%d)\n", ret);
+ return ret;
+ }
+ }
+
mvmvif->link[link_id]->phy_ctxt = phy_ctxt;
if (switching_chanctx) {
@@ -326,14 +390,62 @@ static int iwl_mvm_mld_assign_vif_chanctx(struct ieee80211_hw *hw,
return ret;
}
+static int iwl_mvm_esr_mode_inactive(struct iwl_mvm *mvm,
+ struct ieee80211_vif *vif)
+{
+ struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
+ struct ieee80211_bss_conf *link_conf;
+ int link_id, ret = 0;
+
+ mvmvif->esr_active = false;
+
+ vif->driver_flags &= ~IEEE80211_VIF_DISABLE_SMPS_OVERRIDE;
+
+ iwl_mvm_update_smps_on_active_links(mvm, vif, IWL_MVM_SMPS_REQ_FW,
+ IEEE80211_SMPS_AUTOMATIC);
+
+ for_each_vif_active_link(vif, link_conf, link_id) {
+ struct ieee80211_chanctx_conf *chanctx_conf;
+ struct iwl_mvm_phy_ctxt *phy_ctxt;
+ u8 static_chains, dynamic_chains;
+
+ mvmvif->link[link_id]->listen_lmac = false;
+
+ rcu_read_lock();
+
+ chanctx_conf = rcu_dereference(link_conf->chanctx_conf);
+ phy_ctxt = mvmvif->link[link_id]->phy_ctxt;
+
+ if (!chanctx_conf || !phy_ctxt) {
+ rcu_read_unlock();
+ continue;
+ }
+
+ phy_ctxt->rlc_disabled = false;
+ static_chains = chanctx_conf->rx_chains_static;
+ dynamic_chains = chanctx_conf->rx_chains_dynamic;
+
+ rcu_read_unlock();
+
+ ret = iwl_mvm_phy_send_rlc(mvm, phy_ctxt, static_chains,
+ dynamic_chains);
+ if (ret)
+ break;
+ }
+
+ return ret;
+}
+
static void
__iwl_mvm_mld_unassign_vif_chanctx(struct iwl_mvm *mvm,
struct ieee80211_vif *vif,
struct ieee80211_bss_conf *link_conf,
struct ieee80211_chanctx_conf *ctx,
bool switching_chanctx)
+
{
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
+ unsigned int n_active = iwl_mvm_mld_count_active_links(vif);
unsigned int link_id = link_conf->link_id;
/* shouldn't happen, but verify link_id is valid before accessing */
@@ -352,6 +464,14 @@ __iwl_mvm_mld_unassign_vif_chanctx(struct iwl_mvm *mvm,
mvmvif->ap_ibss_active = false;
}
+ if (iwl_mvm_is_esr_supported(mvm->fwrt.trans) && n_active > 1) {
+ int ret = iwl_mvm_esr_mode_inactive(mvm, vif);
+
+ if (ret)
+ IWL_ERR(mvm, "failed to deactivate ESR mode (%d)\n",
+ ret);
+ }
+
if (vif->type == NL80211_IFTYPE_MONITOR)
iwl_mvm_mld_rm_snif_sta(mvm, vif);
@@ -422,7 +542,7 @@ static int iwl_mvm_mld_start_ap_ibss(struct ieee80211_hw *hw,
if (iwl_mvm_phy_ctx_count(mvm) > 1)
iwl_mvm_teardown_tdls_peers(mvm);
- iwl_mvm_ftm_restart_responder(mvm, vif);
+ iwl_mvm_ftm_restart_responder(mvm, vif, link_conf);
goto out_unlock;
@@ -492,7 +612,7 @@ static int iwl_mvm_mld_mac_sta_state(struct ieee80211_hw *hw,
enum ieee80211_sta_state old_state,
enum ieee80211_sta_state new_state)
{
- struct iwl_mvm_sta_state_ops callbacks = {
+ static const struct iwl_mvm_sta_state_ops callbacks = {
.add_sta = iwl_mvm_mld_add_sta,
.update_sta = iwl_mvm_mld_update_sta,
.rm_sta = iwl_mvm_mld_rm_sta,
@@ -697,7 +817,11 @@ iwl_mvm_mld_link_info_changed_ap_ibss(struct iwl_mvm *mvm,
if (link_conf->he_support)
link_changes |= LINK_CONTEXT_MODIFY_HE_PARAMS;
- if (changes & (BSS_CHANGED_ERP_CTS_PROT | BSS_CHANGED_HT |
+ if (changes & BSS_CHANGED_ERP_SLOT)
+ link_changes |= LINK_CONTEXT_MODIFY_RATES_INFO;
+
+ if (changes & (BSS_CHANGED_ERP_CTS_PROT | BSS_CHANGED_ERP_SLOT |
+ BSS_CHANGED_HT |
BSS_CHANGED_BANDWIDTH | BSS_CHANGED_QOS |
BSS_CHANGED_HE_BSS_COLOR) &&
iwl_mvm_link_changed(mvm, vif, link_conf,
@@ -711,7 +835,7 @@ iwl_mvm_mld_link_info_changed_ap_ibss(struct iwl_mvm *mvm,
/* FIXME: need to decide if we need FTM responder per link */
if (changes & BSS_CHANGED_FTM_RESPONDER) {
- int ret = iwl_mvm_ftm_start_responder(mvm, vif);
+ int ret = iwl_mvm_ftm_start_responder(mvm, vif, link_conf);
if (ret)
IWL_WARN(mvm, "Failed to enable FTM responder (%d)\n",
@@ -779,7 +903,7 @@ iwl_mvm_mld_switch_vif_chanctx(struct ieee80211_hw *hw,
int n_vifs,
enum ieee80211_chanctx_switch_mode mode)
{
- struct iwl_mvm_switch_vif_chanctx_ops ops = {
+ static const struct iwl_mvm_switch_vif_chanctx_ops ops = {
.__assign_vif_chanctx = __iwl_mvm_mld_assign_vif_chanctx,
.__unassign_vif_chanctx = __iwl_mvm_mld_unassign_vif_chanctx,
};
@@ -816,8 +940,12 @@ iwl_mvm_mld_mac_conf_tx(struct ieee80211_hw *hw,
{
struct iwl_mvm *mvm = IWL_MAC80211_GET_MVM(hw);
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
+ struct iwl_mvm_vif_link_info *mvm_link = mvmvif->link[link_id];
- mvmvif->deflink.queue_params[ac] = *params;
+ if (!mvm_link)
+ return -EINVAL;
+
+ mvm_link->queue_params[ac] = *params;
/* No need to update right away, we'll get BSS_CHANGED_QOS
* The exception is P2P_DEVICE interface which needs immediate update.
@@ -871,7 +999,7 @@ static int iwl_mvm_mld_roc(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
struct ieee80211_channel *channel, int duration,
enum ieee80211_roc_type type)
{
- struct iwl_mvm_roc_ops ops = {
+ static const struct iwl_mvm_roc_ops ops = {
.add_aux_sta_for_hs20 = iwl_mvm_mld_add_aux_sta,
.switch_phy_ctxt = iwl_mvm_link_switch_phy_ctx,
};
@@ -886,33 +1014,16 @@ iwl_mvm_mld_change_vif_links(struct ieee80211_hw *hw,
struct ieee80211_bss_conf *old[IEEE80211_MLD_MAX_NUM_LINKS])
{
struct iwl_mvm_vif_link_info *new_link[IEEE80211_MLD_MAX_NUM_LINKS] = {};
+ unsigned int n_active = iwl_mvm_mld_count_active_links(vif);
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
struct iwl_mvm *mvm = IWL_MAC80211_GET_MVM(hw);
u16 removed = old_links & ~new_links;
u16 added = new_links & ~old_links;
int err, i;
- if (hweight16(new_links) > 2) {
+ if (hweight16(new_links) > 1 &&
+ n_active > iwl_mvm_max_active_links(mvm, vif))
return -EOPNOTSUPP;
- } else if (hweight16(new_links) > 1) {
- unsigned int n_active = 0;
-
- for (i = 0; i < IEEE80211_MLD_MAX_NUM_LINKS; i++) {
- struct ieee80211_bss_conf *link_conf;
-
- link_conf = link_conf_dereference_protected(vif, i);
- if (link_conf &&
- rcu_access_pointer(link_conf->chanctx_conf))
- n_active++;
- }
-
- if (vif->type == NL80211_IFTYPE_AP) {
- if (n_active > mvm->fw->ucode_capa.num_beacons)
- return -EOPNOTSUPP;
- } else if (n_active > 1) {
- return -EOPNOTSUPP;
- }
- }
for (i = 0; i < IEEE80211_MLD_MAX_NUM_LINKS; i++) {
int r;
@@ -956,9 +1067,7 @@ iwl_mvm_mld_change_vif_links(struct ieee80211_hw *hw,
goto out_err;
kfree(mvmvif->link[i]);
mvmvif->link[i] = NULL;
- }
-
- if (added & BIT(i)) {
+ } else if (added & BIT(i)) {
struct ieee80211_bss_conf *link_conf;
link_conf = link_conf_dereference_protected(vif, i);
@@ -975,6 +1084,9 @@ iwl_mvm_mld_change_vif_links(struct ieee80211_hw *hw,
}
}
+ if (err)
+ goto out_err;
+
err = 0;
if (new_links == 0) {
mvmvif->link[0] = &mvmvif->deflink;
@@ -1037,6 +1149,7 @@ const struct ieee80211_ops iwl_mvm_mld_hw_ops = {
.mgd_complete_tx = iwl_mvm_mac_mgd_complete_tx,
.mgd_protect_tdls_discover = iwl_mvm_mac_mgd_protect_tdls_discover,
.flush = iwl_mvm_mac_flush,
+ .flush_sta = iwl_mvm_mac_flush_sta,
.sched_scan_start = iwl_mvm_mac_sched_scan_start,
.sched_scan_stop = iwl_mvm_mac_sched_scan_stop,
.set_key = iwl_mvm_mac_set_key,
@@ -1093,7 +1206,7 @@ const struct ieee80211_ops iwl_mvm_mld_hw_ops = {
.abort_pmsr = iwl_mvm_abort_pmsr,
#ifdef CONFIG_IWLWIFI_DEBUGFS
- .sta_add_debugfs = iwl_mvm_sta_add_debugfs,
+ .link_sta_add_debugfs = iwl_mvm_link_sta_add_debugfs,
#endif
.set_hw_timestamp = iwl_mvm_set_hw_timestamp,
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/mld-sta.c b/drivers/net/wireless/intel/iwlwifi/mvm/mld-sta.c
index 85a4ce8449ad..524852cf5cd2 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/mld-sta.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/mld-sta.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
- * Copyright (C) 2022 Intel Corporation
+ * Copyright (C) 2022-2023 Intel Corporation
*/
#include "mvm.h"
#include "time-sync.h"
@@ -71,6 +71,11 @@ static int iwl_mvm_mld_add_int_sta_to_fw(struct iwl_mvm *mvm,
cmd.station_type = cpu_to_le32(sta->type);
+ if (fw_has_capa(&mvm->fw->ucode_capa,
+ IWL_UCODE_TLV_CAPA_STA_EXP_MFP_SUPPORT) &&
+ sta->type == STATION_TYPE_BCAST_MGMT)
+ cmd.mfp = cpu_to_le32(1);
+
if (addr) {
memcpy(cmd.peer_mld_address, addr, ETH_ALEN);
memcpy(cmd.peer_link_address, addr, ETH_ALEN);
@@ -128,11 +133,11 @@ static int iwl_mvm_add_aux_sta_to_fw(struct iwl_mvm *mvm,
/*
* Adds an internal sta to the FW table with its queues
*/
-static int iwl_mvm_mld_add_int_sta_with_queue(struct iwl_mvm *mvm,
- struct iwl_mvm_int_sta *sta,
- const u8 *addr, int link_id,
- u16 *queue, u8 tid,
- unsigned int *_wdg_timeout)
+int iwl_mvm_mld_add_int_sta_with_queue(struct iwl_mvm *mvm,
+ struct iwl_mvm_int_sta *sta,
+ const u8 *addr, int link_id,
+ u16 *queue, u8 tid,
+ unsigned int *_wdg_timeout)
{
int ret, txq;
unsigned int wdg_timeout = _wdg_timeout ? *_wdg_timeout :
@@ -364,6 +369,9 @@ int iwl_mvm_mld_rm_bcast_sta(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
lockdep_assert_held(&mvm->mutex);
+ if (WARN_ON(!link))
+ return -EIO;
+
switch (vif->type) {
case NL80211_IFTYPE_AP:
case NL80211_IFTYPE_ADHOC:
@@ -393,6 +401,9 @@ int iwl_mvm_mld_rm_mcast_sta(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
lockdep_assert_held(&mvm->mutex);
+ if (WARN_ON(!link))
+ return -EIO;
+
return iwl_mvm_mld_rm_int_sta(mvm, &link->mcast_sta, true, 0,
&link->cab_queue);
}
@@ -442,6 +453,11 @@ static int iwl_mvm_mld_cfg_sta(struct iwl_mvm *mvm, struct ieee80211_sta *sta,
if (mvm_sta->sta_state >= IEEE80211_STA_ASSOC)
cmd.assoc_id = cpu_to_le32(sta->aid);
+ if (fw_has_capa(&mvm->fw->ucode_capa,
+ IWL_UCODE_TLV_CAPA_STA_EXP_MFP_SUPPORT) &&
+ (sta->mfp || mvm_sta->sta_state < IEEE80211_STA_AUTHORIZED))
+ cmd.mfp = cpu_to_le32(1);
+
switch (link_sta->rx_nss) {
case 1:
cmd.mimo = cpu_to_le32(0);
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/mvm.h b/drivers/net/wireless/intel/iwlwifi/mvm/mvm.h
index 9e5008e0e47f..b83df0631279 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/mvm.h
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/mvm.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/*
- * Copyright (C) 2012-2014, 2018-2022 Intel Corporation
+ * Copyright (C) 2012-2014, 2018-2023 Intel Corporation
* Copyright (C) 2013-2015 Intel Mobile Communications GmbH
* Copyright (C) 2016-2017 Intel Deutschland GmbH
*/
@@ -104,6 +104,7 @@ struct iwl_mvm_phy_ctxt {
/* track for RLC config command */
u32 center_freq1;
+ bool rlc_disabled;
};
struct iwl_mvm_time_event_data {
@@ -300,6 +301,8 @@ struct iwl_probe_resp_data {
* @he_ru_2mhz_block: 26-tone RU OFDMA transmissions should be blocked
* @queue_params: QoS params for this MAC
* @mgmt_queue: queue number for unbufferable management frames
+ * @igtk: the current IGTK programmed into the firmware
+ * @listen_lmac: indicates this link is allocated to the listen LMAC
*/
struct iwl_mvm_vif_link_info {
u8 bssid[ETH_ALEN];
@@ -317,8 +320,11 @@ struct iwl_mvm_vif_link_info {
enum ieee80211_smps_mode smps_requests[NUM_IWL_MVM_SMPS_REQ];
struct iwl_probe_resp_data __rcu *probe_resp_data;
+ struct ieee80211_key_conf *igtk;
+
bool he_ru_2mhz_block;
bool active;
+ bool listen_lmac;
u16 cab_queue;
/* Assigned while mac80211 has the link in a channel context,
@@ -370,6 +376,7 @@ struct iwl_mvm_vif {
bool ap_ibss_active;
bool pm_enabled;
bool monitor_active;
+ bool esr_active;
u8 low_latency: 6;
u8 low_latency_actual: 1;
@@ -415,7 +422,7 @@ struct iwl_mvm_vif {
#endif
/* FW identified misbehaving AP */
- u8 uapsd_misbehaving_bssid[ETH_ALEN];
+ u8 uapsd_misbehaving_ap_addr[ETH_ALEN] __aligned(2);
struct delayed_work uapsd_nonagg_detected_wk;
bool csa_countdown;
@@ -1003,6 +1010,8 @@ struct iwl_mvm {
struct ieee80211_vif __rcu *vif_id_to_mac[NUM_MAC_INDEX_DRIVER];
+ struct ieee80211_bss_conf __rcu *link_id_to_link_conf[IWL_MVM_FW_MAX_LINK_ID + 1];
+
/* -1 for always, 0 for never, >0 for that many times */
s8 fw_restart;
u8 *error_recovery_buf;
@@ -1174,6 +1183,10 @@ struct iwl_mvm {
__le16 cur_aid;
u8 cur_bssid[ETH_ALEN];
+#ifdef CONFIG_ACPI
+ struct iwl_phy_specific_cfg phy_filters;
+#endif
+
unsigned long last_6ghz_passive_scan_jiffies;
unsigned long last_reset_or_resume_time_jiffies;
@@ -1302,6 +1315,19 @@ iwl_mvm_rcu_dereference_vif_id(struct iwl_mvm *mvm, u8 vif_id, bool rcu)
lockdep_is_held(&mvm->mutex));
}
+static inline struct ieee80211_bss_conf *
+iwl_mvm_rcu_fw_link_id_to_link_conf(struct iwl_mvm *mvm, u8 link_id, bool rcu)
+{
+ if (WARN_ON(link_id >= ARRAY_SIZE(mvm->link_id_to_link_conf)))
+ return NULL;
+
+ if (rcu)
+ return rcu_dereference(mvm->link_id_to_link_conf[link_id]);
+
+ return rcu_dereference_protected(mvm->link_id_to_link_conf[link_id],
+ lockdep_is_held(&mvm->mutex));
+}
+
static inline bool iwl_mvm_is_adaptive_dwell_supported(struct iwl_mvm *mvm)
{
return fw_has_api(&mvm->fw->ucode_capa,
@@ -1415,6 +1441,12 @@ static inline bool iwl_mvm_has_mld_api(const struct iwl_fw *fw)
IWL_UCODE_TLV_CAPA_MLD_API_SUPPORT);
}
+static inline bool iwl_mvm_has_new_station_api(const struct iwl_fw *fw)
+{
+ return iwl_mvm_has_mld_api(fw) ||
+ iwl_fw_lookup_cmd_ver(fw, ADD_STA, 0) >= 12;
+}
+
static inline bool iwl_mvm_has_new_tx_api(struct iwl_mvm *mvm)
{
/* TODO - replace with TLV once defined */
@@ -1516,17 +1548,30 @@ static inline bool iwl_mvm_is_ctdp_supported(struct iwl_mvm *mvm)
IWL_UCODE_TLV_CAPA_CTDP_SUPPORT);
}
-static inline bool iwl_mvm_has_new_tx_csum(struct iwl_mvm *mvm)
+static inline bool iwl_mvm_is_esr_supported(struct iwl_trans *trans)
+{
+ if ((CSR_HW_RFID_TYPE(trans->hw_rf_id) == IWL_CFG_RF_TYPE_FM) &&
+ !CSR_HW_RFID_IS_CDB(trans->hw_rf_id))
+ /* Step A doesn't support eSR */
+ return CSR_HW_RFID_STEP(trans->hw_rf_id);
+
+ return false;
+}
+
+static inline int iwl_mvm_max_active_links(struct iwl_mvm *mvm,
+ struct ieee80211_vif *vif)
{
- if (mvm->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_BZ)
- return false;
+ struct iwl_trans *trans = mvm->fwrt.trans;
+
+ if (vif->type == NL80211_IFTYPE_AP)
+ return mvm->fw->ucode_capa.num_beacons;
- if (mvm->trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_BZ &&
- CSR_HW_REV_TYPE(mvm->trans->hw_rev) == IWL_CFG_MAC_TYPE_GL &&
- mvm->trans->hw_rev_step <= SILICON_B_STEP)
- return false;
+ if (iwl_mvm_is_esr_supported(trans) ||
+ (CSR_HW_RFID_TYPE(trans->hw_rf_id) == IWL_CFG_RF_TYPE_FM &&
+ CSR_HW_RFID_IS_CDB(trans->hw_rf_id)))
+ return IWL_MVM_FW_MAX_ACTIVE_LINKS_NUM;
- return true;
+ return 1;
}
extern const u8 iwl_mvm_ac_to_tx_fifo[];
@@ -1606,7 +1651,6 @@ void iwl_mvm_mac_itxq_xmit(struct ieee80211_hw *hw, struct ieee80211_txq *txq);
unsigned int iwl_mvm_max_amsdu_size(struct iwl_mvm *mvm,
struct ieee80211_sta *sta,
unsigned int tid);
-u32 iwl_mvm_tx_csum_bz(struct iwl_mvm *mvm, struct sk_buff *skb, bool amsdu);
#ifdef CONFIG_IWLWIFI_DEBUG
const char *iwl_mvm_get_tx_fail_reason(u32 status);
@@ -1741,6 +1785,8 @@ void iwl_mvm_phy_ctxt_unref(struct iwl_mvm *mvm,
int iwl_mvm_phy_ctx_count(struct iwl_mvm *mvm);
u8 iwl_mvm_get_channel_width(struct cfg80211_chan_def *chandef);
u8 iwl_mvm_get_ctrl_pos(struct cfg80211_chan_def *chandef);
+int iwl_mvm_phy_send_rlc(struct iwl_mvm *mvm, struct iwl_mvm_phy_ctxt *ctxt,
+ u8 chains_static, u8 chains_dynamic);
/* MAC (virtual interface) programming */
@@ -1758,7 +1804,7 @@ void iwl_mvm_set_fw_qos_params(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
struct ieee80211_bss_conf *link_conf,
struct iwl_ac_qos *ac, __le32 *qos_flags);
bool iwl_mvm_set_fw_mu_edca_params(struct iwl_mvm *mvm,
- struct iwl_mvm_vif *mvmvif,
+ const struct iwl_mvm_vif_link_info *link_info,
struct iwl_he_backoff_conf *trig_based_txf);
void iwl_mvm_set_fw_dtim_tbtt(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
struct ieee80211_bss_conf *link_conf,
@@ -1774,8 +1820,8 @@ void iwl_mvm_mac_ctxt_cmd_ap_set_filter_flags(struct iwl_mvm *mvm,
int iwl_mvm_get_mac_type(struct ieee80211_vif *vif);
__le32 iwl_mvm_mac_ctxt_cmd_p2p_sta_get_oppps_ctwin(struct iwl_mvm *mvm,
struct ieee80211_vif *vif);
-__le32 iwl_mvm_mac_ctxt_cmd_sta_get_twt_policy(struct iwl_mvm *mvm,
- struct ieee80211_vif *vif);
+u32 iwl_mvm_mac_ctxt_cmd_sta_get_twt_policy(struct iwl_mvm *mvm,
+ struct ieee80211_vif *vif);
int iwl_mvm_mld_mac_ctxt_add(struct iwl_mvm *mvm, struct ieee80211_vif *vif);
int iwl_mvm_mld_mac_ctxt_changed(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
bool force_assoc_off);
@@ -1826,6 +1872,7 @@ void iwl_mvm_channel_switch_error_notif(struct iwl_mvm *mvm,
/* Bindings */
int iwl_mvm_binding_add_vif(struct iwl_mvm *mvm, struct ieee80211_vif *vif);
int iwl_mvm_binding_remove_vif(struct iwl_mvm *mvm, struct ieee80211_vif *vif);
+u32 iwl_mvm_get_lmac_id(struct iwl_mvm *mvm, enum nl80211_band band);
/* Links */
int iwl_mvm_add_link(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
@@ -1873,7 +1920,7 @@ void
iwl_mvm_bss_info_changed_common(struct ieee80211_hw *hw,
struct ieee80211_vif *vif,
struct ieee80211_bss_conf *bss_conf,
- struct iwl_mvm_bss_info_changed_ops *callbacks,
+ const struct iwl_mvm_bss_info_changed_ops *callbacks,
u64 changes);
void
iwl_mvm_bss_info_changed_station_common(struct iwl_mvm *mvm,
@@ -1907,7 +1954,7 @@ struct iwl_mvm_roc_ops {
int iwl_mvm_roc_common(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
struct ieee80211_channel *channel, int duration,
enum ieee80211_roc_type type,
- struct iwl_mvm_roc_ops *ops);
+ const struct iwl_mvm_roc_ops *ops);
int iwl_mvm_cancel_roc(struct ieee80211_hw *hw,
struct ieee80211_vif *vif);
/*Session Protection */
@@ -2204,7 +2251,7 @@ static inline void iwl_mvm_vendor_cmds_register(struct iwl_mvm *mvm) {}
#endif
/* Location Aware Regulatory */
-struct iwl_mcc_update_resp *
+struct iwl_mcc_update_resp_v8 *
iwl_mvm_update_mcc(struct iwl_mvm *mvm, const char *alpha2,
enum iwl_mcc_source src_id);
int iwl_mvm_init_mcc(struct iwl_mvm *mvm);
@@ -2224,9 +2271,11 @@ int iwl_mvm_sf_update(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
bool added_vif);
/* FTM responder */
-int iwl_mvm_ftm_start_responder(struct iwl_mvm *mvm, struct ieee80211_vif *vif);
+int iwl_mvm_ftm_start_responder(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
+ struct ieee80211_bss_conf *bss_conf);
void iwl_mvm_ftm_restart_responder(struct iwl_mvm *mvm,
- struct ieee80211_vif *vif);
+ struct ieee80211_vif *vif,
+ struct ieee80211_bss_conf *bss_conf);
void iwl_mvm_ftm_responder_stats(struct iwl_mvm *mvm,
struct iwl_rx_cmd_buffer *rxb);
int iwl_mvm_ftm_resp_remove_pasn_sta(struct iwl_mvm *mvm,
@@ -2322,10 +2371,10 @@ int iwl_mvm_get_sar_geo_profile(struct iwl_mvm *mvm);
int iwl_mvm_ppag_send_cmd(struct iwl_mvm *mvm);
void iwl_mvm_get_acpi_tables(struct iwl_mvm *mvm);
#ifdef CONFIG_IWLWIFI_DEBUGFS
-void iwl_mvm_sta_add_debugfs(struct ieee80211_hw *hw,
- struct ieee80211_vif *vif,
- struct ieee80211_sta *sta,
- struct dentry *dir);
+void iwl_mvm_link_sta_add_debugfs(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif,
+ struct ieee80211_link_sta *link_sta,
+ struct dentry *dir);
#endif
/* new MLD related APIs */
@@ -2346,6 +2395,12 @@ int iwl_mvm_mld_update_sta_keys(struct iwl_mvm *mvm,
struct ieee80211_sta *sta,
u32 old_sta_mask,
u32 new_sta_mask);
+int iwl_mvm_mld_send_key(struct iwl_mvm *mvm, u32 sta_mask, u32 key_flags,
+ struct ieee80211_key_conf *keyconf);
+u32 iwl_mvm_get_sec_flags(struct iwl_mvm *mvm,
+ struct ieee80211_vif *vif,
+ struct ieee80211_sta *sta,
+ struct ieee80211_key_conf *keyconf);
bool iwl_rfi_supported(struct iwl_mvm *mvm);
int iwl_rfi_send_config_cmd(struct iwl_mvm *mvm,
@@ -2406,7 +2461,7 @@ iwl_mvm_switch_vif_chanctx_common(struct ieee80211_hw *hw,
struct ieee80211_vif_chanctx_switch *vifs,
int n_vifs,
enum ieee80211_chanctx_switch_mode mode,
- struct iwl_mvm_switch_vif_chanctx_ops *ops);
+ const struct iwl_mvm_switch_vif_chanctx_ops *ops);
/* Channel info utils */
static inline bool iwl_mvm_has_ultra_hb_channel(struct iwl_mvm *mvm)
@@ -2604,6 +2659,8 @@ void iwl_mvm_mac_mgd_complete_tx(struct ieee80211_hw *hw,
struct ieee80211_prep_tx_info *info);
void iwl_mvm_mac_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
u32 queues, bool drop);
+void iwl_mvm_mac_flush_sta(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
+ struct ieee80211_sta *sta);
int iwl_mvm_mac_sched_scan_start(struct ieee80211_hw *hw,
struct ieee80211_vif *vif,
struct cfg80211_sched_scan_request *req,
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/nvm.c b/drivers/net/wireless/intel/iwlwifi/mvm/nvm.c
index fdf60afb0f3f..f67ab8ee18c2 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/nvm.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/nvm.c
@@ -404,7 +404,7 @@ int iwl_nvm_init(struct iwl_mvm *mvm)
return ret < 0 ? ret : 0;
}
-struct iwl_mcc_update_resp *
+struct iwl_mcc_update_resp_v8 *
iwl_mvm_update_mcc(struct iwl_mvm *mvm, const char *alpha2,
enum iwl_mcc_source src_id)
{
@@ -412,7 +412,7 @@ iwl_mvm_update_mcc(struct iwl_mvm *mvm, const char *alpha2,
.mcc = cpu_to_le16(alpha2[0] << 8 | alpha2[1]),
.source_id = (u8)src_id,
};
- struct iwl_mcc_update_resp *resp_cp;
+ struct iwl_mcc_update_resp_v8 *resp_cp;
struct iwl_rx_packet *pkt;
struct iwl_host_cmd cmd = {
.id = MCC_UPDATE_CMD,
@@ -420,7 +420,7 @@ iwl_mvm_update_mcc(struct iwl_mvm *mvm, const char *alpha2,
.data = { &mcc_update_cmd },
};
- int ret;
+ int ret, resp_ver;
u32 status;
int resp_len, n_channels;
u16 mcc;
@@ -439,24 +439,60 @@ iwl_mvm_update_mcc(struct iwl_mvm *mvm, const char *alpha2,
pkt = cmd.resp_pkt;
+ resp_ver = iwl_fw_lookup_notif_ver(mvm->fw, IWL_ALWAYS_LONG_GROUP,
+ MCC_UPDATE_CMD, 0);
+
/* Extract MCC response */
- if (fw_has_capa(&mvm->fw->ucode_capa,
- IWL_UCODE_TLV_CAPA_MCC_UPDATE_11AX_SUPPORT)) {
- struct iwl_mcc_update_resp *mcc_resp = (void *)pkt->data;
+ if (resp_ver >= 8) {
+ struct iwl_mcc_update_resp_v8 *mcc_resp_v8 = (void *)pkt->data;
+
+ n_channels = __le32_to_cpu(mcc_resp_v8->n_channels);
+ if (iwl_rx_packet_payload_len(pkt) !=
+ struct_size(mcc_resp_v8, channels, n_channels)) {
+ resp_cp = ERR_PTR(-EINVAL);
+ goto exit;
+ }
+ resp_len = struct_size(resp_cp, channels, n_channels);
+ resp_cp = kzalloc(resp_len, GFP_KERNEL);
+ if (!resp_cp) {
+ resp_cp = ERR_PTR(-ENOMEM);
+ goto exit;
+ }
+ resp_cp->status = mcc_resp_v8->status;
+ resp_cp->mcc = mcc_resp_v8->mcc;
+ resp_cp->cap = mcc_resp_v8->cap;
+ resp_cp->source_id = mcc_resp_v8->source_id;
+ resp_cp->time = mcc_resp_v8->time;
+ resp_cp->geo_info = mcc_resp_v8->geo_info;
+ resp_cp->n_channels = mcc_resp_v8->n_channels;
+ memcpy(resp_cp->channels, mcc_resp_v8->channels,
+ n_channels * sizeof(__le32));
+ } else if (fw_has_capa(&mvm->fw->ucode_capa,
+ IWL_UCODE_TLV_CAPA_MCC_UPDATE_11AX_SUPPORT)) {
+ struct iwl_mcc_update_resp_v4 *mcc_resp_v4 = (void *)pkt->data;
- n_channels = __le32_to_cpu(mcc_resp->n_channels);
+ n_channels = __le32_to_cpu(mcc_resp_v4->n_channels);
if (iwl_rx_packet_payload_len(pkt) !=
- struct_size(mcc_resp, channels, n_channels)) {
+ struct_size(mcc_resp_v4, channels, n_channels)) {
resp_cp = ERR_PTR(-EINVAL);
goto exit;
}
- resp_len = sizeof(struct iwl_mcc_update_resp) +
- n_channels * sizeof(__le32);
- resp_cp = kmemdup(mcc_resp, resp_len, GFP_KERNEL);
+ resp_len = struct_size(resp_cp, channels, n_channels);
+ resp_cp = kzalloc(resp_len, GFP_KERNEL);
if (!resp_cp) {
resp_cp = ERR_PTR(-ENOMEM);
goto exit;
}
+
+ resp_cp->status = mcc_resp_v4->status;
+ resp_cp->mcc = mcc_resp_v4->mcc;
+ resp_cp->cap = cpu_to_le32(le16_to_cpu(mcc_resp_v4->cap));
+ resp_cp->source_id = mcc_resp_v4->source_id;
+ resp_cp->time = mcc_resp_v4->time;
+ resp_cp->geo_info = mcc_resp_v4->geo_info;
+ resp_cp->n_channels = mcc_resp_v4->n_channels;
+ memcpy(resp_cp->channels, mcc_resp_v4->channels,
+ n_channels * sizeof(__le32));
} else {
struct iwl_mcc_update_resp_v3 *mcc_resp_v3 = (void *)pkt->data;
@@ -466,8 +502,7 @@ iwl_mvm_update_mcc(struct iwl_mvm *mvm, const char *alpha2,
resp_cp = ERR_PTR(-EINVAL);
goto exit;
}
- resp_len = sizeof(struct iwl_mcc_update_resp) +
- n_channels * sizeof(__le32);
+ resp_len = struct_size(resp_cp, channels, n_channels);
resp_cp = kzalloc(resp_len, GFP_KERNEL);
if (!resp_cp) {
resp_cp = ERR_PTR(-ENOMEM);
@@ -476,7 +511,7 @@ iwl_mvm_update_mcc(struct iwl_mvm *mvm, const char *alpha2,
resp_cp->status = mcc_resp_v3->status;
resp_cp->mcc = mcc_resp_v3->mcc;
- resp_cp->cap = cpu_to_le16(mcc_resp_v3->cap);
+ resp_cp->cap = cpu_to_le32(mcc_resp_v3->cap);
resp_cp->source_id = mcc_resp_v3->source_id;
resp_cp->time = mcc_resp_v3->time;
resp_cp->geo_info = mcc_resp_v3->geo_info;
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/offloading.c b/drivers/net/wireless/intel/iwlwifi/mvm/offloading.c
index a8bd0f5f795c..dfb16ca5b438 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/offloading.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/offloading.c
@@ -198,6 +198,10 @@ int iwl_mvm_send_proto_offload(struct iwl_mvm *mvm,
memcpy(common->arp_mac_addr, vif->addr, ETH_ALEN);
}
+ if (fw_has_capa(&mvm->fw->ucode_capa,
+ IWL_UCODE_TLV_CAPA_OFFLOAD_BTM_SUPPORT))
+ enabled |= IWL_D3_PROTO_OFFLOAD_BTM;
+
if (!disable_offloading)
common->enabled = cpu_to_le32(enabled);
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/ops.c b/drivers/net/wireless/intel/iwlwifi/mvm/ops.c
index 32625bfacaae..5336a4afde4d 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/ops.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/ops.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
- * Copyright (C) 2012-2014, 2018-2020 Intel Corporation
+ * Copyright (C) 2012-2014, 2018-2023 Intel Corporation
* Copyright (C) 2013-2015 Intel Mobile Communications GmbH
* Copyright (C) 2016-2017 Intel Deutschland GmbH
*/
@@ -192,8 +192,7 @@ static void iwl_mvm_rx_monitor_notif(struct iwl_mvm *mvm,
WARN_ON(!(sband->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40));
sband->ht_cap.cap &= ~IEEE80211_HT_CAP_SUP_WIDTH_20_40;
- he_cap = ieee80211_get_he_iftype_cap(sband,
- ieee80211_vif_type_p2p(vif));
+ he_cap = ieee80211_get_he_iftype_cap_vif(sband, vif);
if (he_cap) {
/* we know that ours is writable */
@@ -449,7 +448,6 @@ static const struct iwl_hcmd_names iwl_mvm_legacy_names[] = {
HCMD_NAME(ADD_STA_KEY),
HCMD_NAME(ADD_STA),
HCMD_NAME(REMOVE_STA),
- HCMD_NAME(FW_GET_ITEM_CMD),
HCMD_NAME(TX_CMD),
HCMD_NAME(SCD_QUEUE_CFG),
HCMD_NAME(TXPATH_FLUSH),
@@ -512,7 +510,6 @@ static const struct iwl_hcmd_names iwl_mvm_legacy_names[] = {
HCMD_NAME(REPLY_BEACON_FILTERING_CMD),
HCMD_NAME(D3_CONFIG_CMD),
HCMD_NAME(PROT_OFFLOAD_CONFIG_CMD),
- HCMD_NAME(OFFLOADS_QUERY_CMD),
HCMD_NAME(MATCH_FOUND_NOTIFICATION),
HCMD_NAME(DTS_MEASUREMENT_NOTIFICATION),
HCMD_NAME(WOWLAN_PATTERNS),
@@ -1604,7 +1601,9 @@ static void iwl_mvm_rx_common(struct iwl_mvm *mvm,
if (rx_h->cmd_id != WIDE_ID(pkt->hdr.group_id, pkt->hdr.cmd))
continue;
- if (unlikely(pkt_len < rx_h->min_size))
+ if (IWL_FW_CHECK(mvm, pkt_len < rx_h->min_size,
+ "unexpected notification 0x%04x size %d, need %d\n",
+ rx_h->cmd_id, pkt_len, rx_h->min_size))
return;
if (rx_h->context == RX_HANDLER_SYNC) {
@@ -1743,8 +1742,11 @@ static void iwl_mvm_queue_state_change(struct iwl_op_mode *op_mode,
else
set_bit(IWL_MVM_TXQ_STATE_STOP_FULL, &mvmtxq->state);
- if (start && mvmsta->sta_state != IEEE80211_STA_NOTEXIST)
+ if (start && mvmsta->sta_state != IEEE80211_STA_NOTEXIST) {
+ local_bh_disable();
iwl_mvm_mac_itxq_xmit(mvm->hw, txq);
+ local_bh_enable();
+ }
}
out:
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/phy-ctxt.c b/drivers/net/wireless/intel/iwlwifi/mvm/phy-ctxt.c
index 3ab6fb83a175..a5b432bc9e2f 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/phy-ctxt.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/phy-ctxt.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
- * Copyright (C) 2012-2014, 2018-2022 Intel Corporation
+ * Copyright (C) 2012-2014, 2018-2023 Intel Corporation
* Copyright (C) 2013-2014 Intel Mobile Communications GmbH
* Copyright (C) 2017 Intel Deutschland GmbH
*/
@@ -151,7 +151,7 @@ static void iwl_mvm_phy_ctxt_cmd_data(struct iwl_mvm *mvm,
struct cfg80211_chan_def *chandef,
u8 chains_static, u8 chains_dynamic)
{
- cmd->lmac_id = cpu_to_le32(iwl_mvm_get_lmac_id(mvm->fw,
+ cmd->lmac_id = cpu_to_le32(iwl_mvm_get_lmac_id(mvm,
chandef->chan->band));
/* Set the channel info data */
@@ -163,15 +163,18 @@ static void iwl_mvm_phy_ctxt_cmd_data(struct iwl_mvm *mvm,
chains_static, chains_dynamic);
}
-static int iwl_mvm_phy_send_rlc(struct iwl_mvm *mvm,
- struct iwl_mvm_phy_ctxt *ctxt,
- u8 chains_static, u8 chains_dynamic)
+int iwl_mvm_phy_send_rlc(struct iwl_mvm *mvm, struct iwl_mvm_phy_ctxt *ctxt,
+ u8 chains_static, u8 chains_dynamic)
{
struct iwl_rlc_config_cmd cmd = {
.phy_id = cpu_to_le32(ctxt->id),
};
- if (iwl_fw_lookup_cmd_ver(mvm->fw, WIDE_ID(DATA_PATH_GROUP, RLC_CONFIG_CMD), 0) < 2)
+ if (ctxt->rlc_disabled)
+ return 0;
+
+ if (iwl_fw_lookup_cmd_ver(mvm->fw, WIDE_ID(DATA_PATH_GROUP,
+ RLC_CONFIG_CMD), 0) < 2)
return 0;
BUILD_BUG_ON(IWL_RLC_CHAIN_INFO_DRIVER_FORCE !=
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/power.c b/drivers/net/wireless/intel/iwlwifi/mvm/power.c
index ac1dae52556f..9131b5f1bc76 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/power.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/power.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
- * Copyright (C) 2012-2014, 2018-2019, 2021 Intel Corporation
+ * Copyright (C) 2012-2014, 2018-2019, 2021-2023 Intel Corporation
* Copyright (C) 2013-2014 Intel Mobile Communications GmbH
* Copyright (C) 2015-2017 Intel Deutschland GmbH
*/
@@ -237,8 +237,8 @@ static bool iwl_mvm_power_allow_uapsd(struct iwl_mvm *mvm,
{
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
- if (!memcmp(mvmvif->uapsd_misbehaving_bssid, vif->bss_conf.bssid,
- ETH_ALEN))
+ if (ether_addr_equal(mvmvif->uapsd_misbehaving_ap_addr,
+ vif->cfg.ap_addr))
return false;
/*
@@ -327,12 +327,11 @@ static void iwl_mvm_power_config_skip_dtim(struct iwl_mvm *mvm,
if (WARN_ON(!dtimper_tu))
return;
- /* configure skip over dtim up to 306TU - 314 msec */
- skip = max_t(u8, 1, 306 / dtimper_tu);
+ /* configure skip over dtim up to 900 TU DTIM interval */
+ skip = max_t(u8, 1, 900 / dtimper_tu);
}
- /* the firmware really expects "look at every X DTIMs", so add 1 */
- cmd->skip_dtim_periods = 1 + skip;
+ cmd->skip_dtim_periods = skip;
cmd->flags |= cpu_to_le16(POWER_FLAGS_SKIP_OVER_DTIM_MSK);
}
@@ -502,9 +501,9 @@ void iwl_mvm_power_vif_assoc(struct iwl_mvm *mvm, struct ieee80211_vif *vif)
{
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
- if (memcmp(vif->bss_conf.bssid, mvmvif->uapsd_misbehaving_bssid,
- ETH_ALEN))
- eth_zero_addr(mvmvif->uapsd_misbehaving_bssid);
+ if (!ether_addr_equal(mvmvif->uapsd_misbehaving_ap_addr,
+ vif->cfg.ap_addr))
+ eth_zero_addr(mvmvif->uapsd_misbehaving_ap_addr);
}
static void iwl_mvm_power_uapsd_misbehav_ap_iterator(void *_data, u8 *mac,
@@ -512,14 +511,23 @@ static void iwl_mvm_power_uapsd_misbehav_ap_iterator(void *_data, u8 *mac,
{
u8 *ap_sta_id = _data;
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
+ struct ieee80211_bss_conf *link_conf;
+ unsigned int link_id;
- /* The ap_sta_id is not expected to change during current association
- * so no explicit protection is needed
- */
- if (mvmvif->deflink.ap_sta_id == *ap_sta_id)
- memcpy(mvmvif->uapsd_misbehaving_bssid,
- vif->bss_conf.bssid,
- ETH_ALEN);
+ rcu_read_lock();
+ for_each_vif_active_link(vif, link_conf, link_id) {
+ struct iwl_mvm_vif_link_info *link_info = mvmvif->link[link_id];
+
+ /* The ap_sta_id is not expected to change during current
+ * association so no explicit protection is needed
+ */
+ if (link_info->ap_sta_id == *ap_sta_id) {
+ ether_addr_copy(mvmvif->uapsd_misbehaving_ap_addr,
+ vif->cfg.ap_addr);
+ break;
+ }
+ }
+ rcu_read_unlock();
}
void iwl_mvm_power_uapsd_misbehaving_ap_notif(struct iwl_mvm *mvm,
@@ -647,30 +655,32 @@ static void iwl_mvm_power_set_pm(struct iwl_mvm *mvm,
return;
/* enable PM on bss if bss stand alone */
- if (vifs->bss_active && !vifs->p2p_active && !vifs->ap_active) {
+ if (bss_mvmvif && vifs->bss_active && !vifs->p2p_active &&
+ !vifs->ap_active) {
bss_mvmvif->pm_enabled = true;
return;
}
/* enable PM on p2p if p2p stand alone */
- if (vifs->p2p_active && !vifs->bss_active && !vifs->ap_active) {
+ if (p2p_mvmvif && vifs->p2p_active && !vifs->bss_active &&
+ !vifs->ap_active) {
p2p_mvmvif->pm_enabled = true;
return;
}
- if (vifs->bss_active && vifs->p2p_active)
+ if (p2p_mvmvif && bss_mvmvif && vifs->bss_active && vifs->p2p_active)
client_same_channel =
iwl_mvm_have_links_same_channel(bss_mvmvif, p2p_mvmvif);
- if (vifs->bss_active && vifs->ap_active)
+ if (bss_mvmvif && ap_mvmvif && vifs->bss_active && vifs->ap_active)
ap_same_channel =
iwl_mvm_have_links_same_channel(bss_mvmvif, ap_mvmvif);
/* clients are not stand alone: enable PM if DCM */
if (!(client_same_channel || ap_same_channel)) {
- if (vifs->bss_active)
+ if (bss_mvmvif && vifs->bss_active)
bss_mvmvif->pm_enabled = true;
- if (vifs->p2p_active)
+ if (p2p_mvmvif && vifs->p2p_active)
p2p_mvmvif->pm_enabled = true;
return;
}
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/rs-fw.c b/drivers/net/wireless/intel/iwlwifi/mvm/rs-fw.c
index c3a00bfbeef2..6cba8a353b53 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/rs-fw.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/rs-fw.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
* Copyright (C) 2017 Intel Deutschland GmbH
- * Copyright (C) 2018-2022 Intel Corporation
+ * Copyright (C) 2018-2023 Intel Corporation
*/
#include "rs.h"
#include "fw-api.h"
@@ -63,12 +63,11 @@ static u8 rs_fw_sgi_cw_support(struct ieee80211_link_sta *link_sta)
static u16 rs_fw_get_config_flags(struct iwl_mvm *mvm,
struct ieee80211_vif *vif,
struct ieee80211_link_sta *link_sta,
- struct ieee80211_supported_band *sband)
+ const struct ieee80211_sta_he_cap *sband_he_cap)
{
struct ieee80211_sta_ht_cap *ht_cap = &link_sta->ht_cap;
struct ieee80211_sta_vht_cap *vht_cap = &link_sta->vht_cap;
struct ieee80211_sta_he_cap *he_cap = &link_sta->he_cap;
- const struct ieee80211_sta_he_cap *sband_he_cap;
bool vht_ena = vht_cap->vht_supported;
u16 flags = 0;
@@ -94,8 +93,6 @@ static u16 rs_fw_get_config_flags(struct iwl_mvm *mvm,
IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD))
flags |= IWL_TLC_MNG_CFG_FLAGS_LDPC_MSK;
- sband_he_cap = ieee80211_get_he_iftype_cap(sband,
- ieee80211_vif_type_p2p(vif));
if (sband_he_cap &&
!(sband_he_cap->he_cap_elem.phy_cap_info[1] &
IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD))
@@ -197,16 +194,14 @@ static u16 rs_fw_he_ieee80211_mcs_to_rs_mcs(u16 mcs)
static void
rs_fw_he_set_enabled_rates(const struct ieee80211_link_sta *link_sta,
- struct ieee80211_supported_band *sband,
+ const struct ieee80211_sta_he_cap *sband_he_cap,
struct iwl_tlc_config_cmd_v4 *cmd)
{
const struct ieee80211_sta_he_cap *he_cap = &link_sta->he_cap;
u16 mcs_160 = le16_to_cpu(he_cap->he_mcs_nss_supp.rx_mcs_160);
u16 mcs_80 = le16_to_cpu(he_cap->he_mcs_nss_supp.rx_mcs_80);
- u16 tx_mcs_80 =
- le16_to_cpu(sband->iftype_data->he_cap.he_mcs_nss_supp.tx_mcs_80);
- u16 tx_mcs_160 =
- le16_to_cpu(sband->iftype_data->he_cap.he_mcs_nss_supp.tx_mcs_160);
+ u16 tx_mcs_80 = le16_to_cpu(sband_he_cap->he_mcs_nss_supp.tx_mcs_80);
+ u16 tx_mcs_160 = le16_to_cpu(sband_he_cap->he_mcs_nss_supp.tx_mcs_160);
int i;
u8 nss = link_sta->rx_nss;
@@ -289,7 +284,8 @@ rs_fw_rs_mcs2eht_mcs(enum IWL_TLC_MCS_PER_BW bw,
static void
rs_fw_eht_set_enabled_rates(struct ieee80211_vif *vif,
const struct ieee80211_link_sta *link_sta,
- struct ieee80211_supported_band *sband,
+ const struct ieee80211_sta_he_cap *sband_he_cap,
+ const struct ieee80211_sta_eht_cap *sband_eht_cap,
struct iwl_tlc_config_cmd_v4 *cmd)
{
/* peer RX mcs capa */
@@ -297,7 +293,7 @@ rs_fw_eht_set_enabled_rates(struct ieee80211_vif *vif,
&link_sta->eht_cap.eht_mcs_nss_supp;
/* our TX mcs capa */
const struct ieee80211_eht_mcs_nss_supp *eht_tx_mcs =
- &sband->iftype_data->eht_cap.eht_mcs_nss_supp;
+ &sband_eht_cap->eht_mcs_nss_supp;
enum IWL_TLC_MCS_PER_BW bw;
struct ieee80211_eht_mcs_nss_supp_20mhz_only mcs_rx_20;
@@ -316,7 +312,7 @@ rs_fw_eht_set_enabled_rates(struct ieee80211_vif *vif,
}
/* nic is 20Mhz only */
- if (!(sband->iftype_data->he_cap.he_cap_elem.phy_cap_info[0] &
+ if (!(sband_he_cap->he_cap_elem.phy_cap_info[0] &
IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_MASK_ALL)) {
mcs_tx_20 = eht_tx_mcs->only_20mhz;
} else {
@@ -370,6 +366,8 @@ rs_fw_eht_set_enabled_rates(struct ieee80211_vif *vif,
static void rs_fw_set_supp_rates(struct ieee80211_vif *vif,
struct ieee80211_link_sta *link_sta,
struct ieee80211_supported_band *sband,
+ const struct ieee80211_sta_he_cap *sband_he_cap,
+ const struct ieee80211_sta_eht_cap *sband_eht_cap,
struct iwl_tlc_config_cmd_v4 *cmd)
{
int i;
@@ -388,12 +386,13 @@ static void rs_fw_set_supp_rates(struct ieee80211_vif *vif,
cmd->mode = IWL_TLC_MNG_MODE_NON_HT;
/* HT/VHT rates */
- if (link_sta->eht_cap.has_eht) {
+ if (link_sta->eht_cap.has_eht && sband_he_cap && sband_eht_cap) {
cmd->mode = IWL_TLC_MNG_MODE_EHT;
- rs_fw_eht_set_enabled_rates(vif, link_sta, sband, cmd);
- } else if (he_cap->has_he) {
+ rs_fw_eht_set_enabled_rates(vif, link_sta, sband_he_cap,
+ sband_eht_cap, cmd);
+ } else if (he_cap->has_he && sband_he_cap) {
cmd->mode = IWL_TLC_MNG_MODE_HE;
- rs_fw_he_set_enabled_rates(link_sta, sband, cmd);
+ rs_fw_he_set_enabled_rates(link_sta, sband_he_cap, cmd);
} else if (vht_cap->vht_supported) {
cmd->mode = IWL_TLC_MNG_MODE_VHT;
rs_fw_vht_set_enabled_rates(link_sta, vht_cap, cmd);
@@ -479,7 +478,7 @@ void iwl_mvm_tlc_update_notif(struct iwl_mvm *mvm,
IWL_DEBUG_RATE(mvm, "new rate: %s\n", pretty_rate);
}
- if (flags & IWL_TLC_NOTIF_FLAG_AMSDU && !mvmsta->orig_amsdu_len) {
+ if (flags & IWL_TLC_NOTIF_FLAG_AMSDU && !mvm_link_sta->orig_amsdu_len) {
u16 size = le32_to_cpu(notif->amsdu_size);
int i;
@@ -489,7 +488,7 @@ void iwl_mvm_tlc_update_notif(struct iwl_mvm *mvm,
* so also check with orig_amsdu_len which holds the
* original data before debugfs changed the value
*/
- WARN_ON(mvmsta->orig_amsdu_len < size);
+ WARN_ON(mvm_link_sta->orig_amsdu_len < size);
goto out;
}
@@ -524,6 +523,7 @@ u16 rs_fw_get_max_amsdu_len(struct ieee80211_sta *sta,
{
const struct ieee80211_sta_vht_cap *vht_cap = &link_sta->vht_cap;
const struct ieee80211_sta_ht_cap *ht_cap = &link_sta->ht_cap;
+ const struct ieee80211_sta_eht_cap *eht_cap = &link_sta->eht_cap;
if (WARN_ON_ONCE(!link_conf->chandef.chan))
return IEEE80211_MAX_MPDU_LEN_VHT_3895;
@@ -538,8 +538,18 @@ u16 rs_fw_get_max_amsdu_len(struct ieee80211_sta *sta,
default:
return IEEE80211_MAX_MPDU_LEN_VHT_3895;
}
- } else
- if (vht_cap->vht_supported) {
+ } else if (link_conf->chandef.chan->band == NL80211_BAND_2GHZ &&
+ eht_cap->has_eht) {
+ switch (u8_get_bits(eht_cap->eht_cap_elem.mac_cap_info[0],
+ IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK)) {
+ case IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_11454:
+ return IEEE80211_MAX_MPDU_LEN_VHT_11454;
+ case IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_7991:
+ return IEEE80211_MAX_MPDU_LEN_VHT_7991;
+ default:
+ return IEEE80211_MAX_MPDU_LEN_VHT_3895;
+ }
+ } else if (vht_cap->vht_supported) {
switch (vht_cap->cap & IEEE80211_VHT_CAP_MAX_MPDU_MASK) {
case IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454:
return IEEE80211_MAX_MPDU_LEN_VHT_11454;
@@ -576,13 +586,17 @@ void iwl_mvm_rs_fw_rate_init(struct iwl_mvm *mvm,
u32 cmd_id = WIDE_ID(DATA_PATH_GROUP, TLC_MNG_CONFIG_CMD);
struct ieee80211_supported_band *sband = hw->wiphy->bands[band];
u16 max_amsdu_len = rs_fw_get_max_amsdu_len(sta, link_conf, link_sta);
+ const struct ieee80211_sta_he_cap *sband_he_cap =
+ ieee80211_get_he_iftype_cap_vif(sband, vif);
+ const struct ieee80211_sta_eht_cap *sband_eht_cap =
+ ieee80211_get_eht_iftype_cap_vif(sband, vif);
struct iwl_mvm_link_sta *mvm_link_sta;
struct iwl_lq_sta_rs_fw *lq_sta;
struct iwl_tlc_config_cmd_v4 cfg_cmd = {
.max_ch_width = mvmsta->authorized ?
rs_fw_bw_from_sta_bw(link_sta) : IWL_TLC_MNG_CH_WIDTH_20MHZ,
.flags = cpu_to_le16(rs_fw_get_config_flags(mvm, vif, link_sta,
- sband)),
+ sband_he_cap)),
.chains = rs_fw_set_active_chains(iwl_mvm_get_valid_tx_ant(mvm)),
.sgi_ch_width_supp = rs_fw_sgi_cw_support(link_sta),
.max_mpdu_len = iwl_mvm_is_csum_supported(mvm) ?
@@ -592,6 +606,21 @@ void iwl_mvm_rs_fw_rate_init(struct iwl_mvm *mvm,
int cmd_ver;
int ret;
+ /* Enable external EHT LTF only for GL device and if there's
+ * mutual support by AP and client
+ */
+ if (CSR_HW_REV_TYPE(mvm->trans->hw_rev) == IWL_CFG_MAC_TYPE_GL &&
+ sband_eht_cap &&
+ sband_eht_cap->eht_cap_elem.phy_cap_info[5] &
+ IEEE80211_EHT_PHY_CAP5_SUPP_EXTRA_EHT_LTF &&
+ link_sta->eht_cap.has_eht &&
+ link_sta->eht_cap.eht_cap_elem.phy_cap_info[5] &
+ IEEE80211_EHT_PHY_CAP5_SUPP_EXTRA_EHT_LTF) {
+ IWL_DEBUG_RATE(mvm, "Set support for Extra EHT LTF\n");
+ cfg_cmd.flags |=
+ cpu_to_le16(IWL_TLC_MNG_CFG_FLAGS_EHT_EXTRA_LTF_MSK);
+ }
+
rcu_read_lock();
mvm_link_sta = rcu_dereference(mvmsta->link[link_id]);
if (WARN_ON_ONCE(!mvm_link_sta)) {
@@ -609,7 +638,9 @@ void iwl_mvm_rs_fw_rate_init(struct iwl_mvm *mvm,
#ifdef CONFIG_IWLWIFI_DEBUGFS
iwl_mvm_reset_frame_stats(mvm);
#endif
- rs_fw_set_supp_rates(vif, link_sta, sband, &cfg_cmd);
+ rs_fw_set_supp_rates(vif, link_sta, sband,
+ sband_he_cap, sband_eht_cap,
+ &cfg_cmd);
/*
* since TLC offload works with one mode we can assume
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/rs.c b/drivers/net/wireless/intel/iwlwifi/mvm/rs.c
index 9a20468345e4..481d68cbbbd8 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/rs.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/rs.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/******************************************************************************
*
- * Copyright(c) 2005 - 2014, 2018 - 2022 Intel Corporation. All rights reserved.
+ * Copyright(c) 2005 - 2014, 2018 - 2023 Intel Corporation. All rights reserved.
* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
* Copyright(c) 2016 - 2017 Intel Deutschland GmbH
*****************************************************************************/
@@ -1070,10 +1070,13 @@ static void rs_get_lower_rate_down_column(struct iwl_lq_sta *lq_sta,
rate->bw = RATE_MCS_CHAN_WIDTH_20;
- WARN_ON_ONCE(rate->index < IWL_RATE_MCS_0_INDEX ||
- rate->index > IWL_RATE_MCS_9_INDEX);
+ if (WARN_ON_ONCE(rate->index < IWL_RATE_MCS_0_INDEX))
+ rate->index = rs_ht_to_legacy[IWL_RATE_MCS_0_INDEX];
+ else if (WARN_ON_ONCE(rate->index > IWL_RATE_MCS_9_INDEX))
+ rate->index = rs_ht_to_legacy[IWL_RATE_MCS_9_INDEX];
+ else
+ rate->index = rs_ht_to_legacy[rate->index];
- rate->index = rs_ht_to_legacy[rate->index];
rate->ldpc = false;
} else {
/* Downgrade to SISO with same MCS if in MIMO */
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/rx.c b/drivers/net/wireless/intel/iwlwifi/mvm/rx.c
index b38b24246675..542c192698a4 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/rx.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/rx.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
- * Copyright (C) 2012-2014, 2018-2022 Intel Corporation
+ * Copyright (C) 2012-2014, 2018-2023 Intel Corporation
* Copyright (C) 2013-2015 Intel Mobile Communications GmbH
* Copyright (C) 2016-2017 Intel Deutschland GmbH
*/
@@ -213,8 +213,12 @@ static void iwl_mvm_rx_handle_tcm(struct iwl_mvm *mvm,
};
u16 thr;
- if (ieee80211_is_data_qos(hdr->frame_control))
- ac = tid_to_mac80211_ac[ieee80211_get_tid(hdr)];
+ if (ieee80211_is_data_qos(hdr->frame_control)) {
+ u8 tid = ieee80211_get_tid(hdr);
+
+ if (tid < IWL_MAX_TID_COUNT)
+ ac = tid_to_mac80211_ac[tid];
+ }
mvmsta = iwl_mvm_sta_from_mac80211(sta);
mac = mvmsta->mac_id_n_color & FW_CTXT_ID_MSK;
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c b/drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c
index 6226e4e54a51..8d1e44fd9de7 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c
@@ -279,7 +279,8 @@ static void iwl_mvm_get_signal_strength(struct iwl_mvm *mvm,
static int iwl_mvm_rx_mgmt_prot(struct ieee80211_sta *sta,
struct ieee80211_hdr *hdr,
struct iwl_rx_mpdu_desc *desc,
- u32 status)
+ u32 status,
+ struct ieee80211_rx_status *stats)
{
struct iwl_mvm_sta *mvmsta;
struct iwl_mvm_vif *mvmvif;
@@ -308,8 +309,10 @@ static int iwl_mvm_rx_mgmt_prot(struct ieee80211_sta *sta,
/* good cases */
if (likely(status & IWL_RX_MPDU_STATUS_MIC_OK &&
- !(status & IWL_RX_MPDU_STATUS_REPLAY_ERROR)))
+ !(status & IWL_RX_MPDU_STATUS_REPLAY_ERROR))) {
+ stats->flag |= RX_FLAG_DECRYPTED;
return 0;
+ }
if (!sta)
return -1;
@@ -378,7 +381,7 @@ static int iwl_mvm_rx_crypto(struct iwl_mvm *mvm, struct ieee80211_sta *sta,
if (unlikely(ieee80211_is_mgmt(hdr->frame_control) &&
!ieee80211_has_protected(hdr->frame_control)))
- return iwl_mvm_rx_mgmt_prot(sta, hdr, desc, status);
+ return iwl_mvm_rx_mgmt_prot(sta, hdr, desc, status, stats);
if (!ieee80211_has_protected(hdr->frame_control) ||
(status & IWL_RX_MPDU_STATUS_SEC_MASK) ==
@@ -484,7 +487,7 @@ static void iwl_mvm_rx_csum(struct iwl_mvm *mvm,
}
/*
- * returns true if a packet is a duplicate and should be dropped.
+ * returns true if a packet is a duplicate or invalid tid and should be dropped.
* Updates AMSDU PN tracking info
*/
static bool iwl_mvm_is_dup(struct ieee80211_sta *sta, int queue,
@@ -513,11 +516,14 @@ static bool iwl_mvm_is_dup(struct ieee80211_sta *sta, int queue,
return false;
}
- if (ieee80211_is_data_qos(hdr->frame_control))
+ if (ieee80211_is_data_qos(hdr->frame_control)) {
/* frame has qos control */
tid = ieee80211_get_tid(hdr);
- else
+ if (tid >= IWL_MAX_TID_COUNT)
+ return true;
+ } else {
tid = IWL_MAX_TID_COUNT;
+ }
/* If this wasn't a part of an A-MSDU the sub-frame index will be 0 */
sub_frame_idx = desc->amsdu_info &
@@ -985,10 +991,12 @@ static bool iwl_mvm_reorder(struct iwl_mvm *mvm,
sta_mask = iwl_mvm_sta_fw_id_mask(mvm, sta, -1);
rcu_read_unlock();
- if (WARN(tid != baid_data->tid ||
- !(sta_mask & baid_data->sta_mask),
- "baid 0x%x is mapped to sta_mask:0x%x tid:%d, but was received for sta_mask:0x%x tid:%d\n",
- baid, baid_data->sta_mask, baid_data->tid, sta_mask, tid))
+ if (IWL_FW_CHECK(mvm,
+ tid != baid_data->tid ||
+ !(sta_mask & baid_data->sta_mask),
+ "baid 0x%x is mapped to sta_mask:0x%x tid:%d, but was received for sta_mask:0x%x tid:%d\n",
+ baid, baid_data->sta_mask, baid_data->tid,
+ sta_mask, tid))
return false;
nssn = reorder & IWL_RX_MPDU_REORDER_NSSN_MASK;
@@ -1773,6 +1781,15 @@ static void iwl_mvm_decode_eht_phy_data(struct iwl_mvm *mvm,
IEEE80211_RADIOTAP_EHT_USIG_COMMON_BSS_COLOR);
}
+ if (fw_has_capa(&mvm->fw->ucode_capa,
+ IWL_UCODE_TLV_CAPA_SNIFF_VALIDATE_SUPPORT)) {
+ usig->common |=
+ cpu_to_le32(IEEE80211_RADIOTAP_EHT_USIG_COMMON_VALIDATE_BITS_CHECKED);
+ usig->common |=
+ LE32_DEC_ENC(data0, IWL_RX_PHY_DATA0_EHT_VALIDATE,
+ IEEE80211_RADIOTAP_EHT_USIG_COMMON_VALIDATE_BITS_OK);
+ }
+
eht->known |= cpu_to_le32(IEEE80211_RADIOTAP_EHT_KNOWN_SPATIAL_REUSE);
eht->data[0] |= LE32_DEC_ENC(data0,
IWL_RX_PHY_DATA0_ETH_SPATIAL_REUSE_MASK,
@@ -1782,9 +1799,9 @@ static void iwl_mvm_decode_eht_phy_data(struct iwl_mvm *mvm,
eht->known |= cpu_to_le32(IEEE80211_RADIOTAP_EHT_KNOWN_RU_ALLOC_TB_FMT);
eht->data[8] |= LE32_DEC_ENC(data0, IWL_RX_PHY_DATA0_EHT_PS160,
IEEE80211_RADIOTAP_EHT_DATA8_RU_ALLOC_TB_FMT_PS_160);
- eht->data[8] |= LE32_DEC_ENC(data1, IWL_RX_PHY_DATA1_EHT_B0,
+ eht->data[8] |= LE32_DEC_ENC(data1, IWL_RX_PHY_DATA1_EHT_RU_ALLOC_B0,
IEEE80211_RADIOTAP_EHT_DATA8_RU_ALLOC_TB_FMT_B0);
- eht->data[8] |= LE32_DEC_ENC(data1, IWL_RX_PHY_DATA1_EHT_RU_B1_B7_ALLOC,
+ eht->data[8] |= LE32_DEC_ENC(data1, IWL_RX_PHY_DATA1_EHT_RU_ALLOC_B1_B7,
IEEE80211_RADIOTAP_EHT_DATA8_RU_ALLOC_TB_FMT_B7_B1);
iwl_mvm_decode_eht_ru(mvm, rx_status, eht);
@@ -2633,6 +2650,8 @@ void iwl_mvm_rx_monitor_no_data(struct iwl_mvm *mvm, struct napi_struct *napi,
phy_data.energy_b = u32_get_bits(rssi, RX_NO_DATA_CHAIN_B_MSK);
phy_data.channel = u32_get_bits(rssi, RX_NO_DATA_CHANNEL_MSK);
phy_data.with_data = false;
+ phy_data.rx_vec[0] = desc->rx_vec[0];
+ phy_data.rx_vec[1] = desc->rx_vec[1];
if (iwl_fw_lookup_notif_ver(mvm->fw, DATA_PATH_GROUP,
RX_NO_DATA_NOTIF, 0) < 2) {
@@ -2651,7 +2670,8 @@ void iwl_mvm_rx_monitor_no_data(struct iwl_mvm *mvm, struct napi_struct *napi,
sizeof(struct iwl_rx_no_data_ver_3)))
/* invalid len for ver 3 */
return;
- memcpy(phy_data.rx_vec, desc->rx_vec, sizeof(phy_data.rx_vec));
+ phy_data.rx_vec[2] = desc->rx_vec[2];
+ phy_data.rx_vec[3] = desc->rx_vec[3];
} else {
if (format == RATE_MCS_EHT_MSK)
/* no support for EHT before version 3 API */
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/scan.c b/drivers/net/wireless/intel/iwlwifi/mvm/scan.c
index 175615755d9d..c1d9ce753468 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/scan.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/scan.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
- * Copyright (C) 2012-2014, 2018-2021 Intel Corporation
+ * Copyright (C) 2012-2014, 2018-2023 Intel Corporation
* Copyright (C) 2013-2015 Intel Mobile Communications GmbH
* Copyright (C) 2016-2017 Intel Deutschland GmbH
*/
@@ -647,7 +647,7 @@ static void iwl_mvm_scan_fill_tx_cmd(struct iwl_mvm *mvm,
NL80211_BAND_2GHZ,
no_cck);
- if (iwl_fw_lookup_cmd_ver(mvm->fw, ADD_STA, 0) < 12) {
+ if (!iwl_mvm_has_new_station_api(mvm->fw)) {
tx_cmd[0].sta_id = mvm->aux_sta.sta_id;
tx_cmd[1].sta_id = mvm->aux_sta.sta_id;
@@ -1084,7 +1084,7 @@ static void iwl_mvm_fill_scan_config_v1(struct iwl_mvm *mvm, void *config,
memcpy(&cfg->mac_addr, &mvm->addresses[0].addr, ETH_ALEN);
/* This function should not be called when using ADD_STA ver >=12 */
- WARN_ON_ONCE(iwl_fw_lookup_cmd_ver(mvm->fw, ADD_STA, 0) >= 12);
+ WARN_ON_ONCE(iwl_mvm_has_new_station_api(mvm->fw));
cfg->bcast_sta_id = mvm->aux_sta.sta_id;
cfg->channel_flags = channel_flags;
@@ -1135,7 +1135,7 @@ static void iwl_mvm_fill_scan_config_v2(struct iwl_mvm *mvm, void *config,
memcpy(&cfg->mac_addr, &mvm->addresses[0].addr, ETH_ALEN);
/* This function should not be called when using ADD_STA ver >=12 */
- WARN_ON_ONCE(iwl_fw_lookup_cmd_ver(mvm->fw, ADD_STA, 0) >= 12);
+ WARN_ON_ONCE(iwl_mvm_has_new_station_api(mvm->fw));
cfg->bcast_sta_id = mvm->aux_sta.sta_id;
cfg->channel_flags = channel_flags;
@@ -1250,7 +1250,7 @@ int iwl_mvm_config_scan(struct iwl_mvm *mvm)
memset(&cfg, 0, sizeof(cfg));
- if (iwl_fw_lookup_cmd_ver(mvm->fw, ADD_STA, 0) < 12) {
+ if (!iwl_mvm_has_new_station_api(mvm->fw)) {
cfg.bcast_sta_id = mvm->aux_sta.sta_id;
} else if (iwl_fw_lookup_cmd_ver(mvm->fw, SCAN_CFG_CMD, 0) < 5) {
/*
@@ -1627,11 +1627,11 @@ iwl_mvm_umac_scan_cfg_channels_v4(struct iwl_mvm *mvm,
}
static void
-iwl_mvm_umac_scan_cfg_channels_v6(struct iwl_mvm *mvm,
+iwl_mvm_umac_scan_cfg_channels_v7(struct iwl_mvm *mvm,
struct ieee80211_channel **channels,
- struct iwl_scan_channel_params_v6 *cp,
+ struct iwl_scan_channel_params_v7 *cp,
int n_channels, u32 flags,
- enum nl80211_iftype vif_type)
+ enum nl80211_iftype vif_type, u32 version)
{
int i;
@@ -1641,14 +1641,19 @@ iwl_mvm_umac_scan_cfg_channels_v6(struct iwl_mvm *mvm,
u32 n_aps_flag =
iwl_mvm_scan_ch_n_aps_flag(vif_type,
channels[i]->hw_value);
+ u8 iwl_band = iwl_mvm_phy_band_from_nl80211(band);
cfg->flags = cpu_to_le32(flags | n_aps_flag);
cfg->v2.channel_num = channels[i]->hw_value;
- cfg->v2.band = iwl_mvm_phy_band_from_nl80211(band);
if (cfg80211_channel_is_psc(channels[i]))
cfg->flags = 0;
cfg->v2.iter_count = 1;
cfg->v2.iter_interval = 0;
+ if (version < 17)
+ cfg->v2.band = iwl_band;
+ else
+ cfg->flags |= cpu_to_le32((iwl_band <<
+ IWL_CHAN_CFG_FLAGS_BAND_POS));
}
}
@@ -1723,14 +1728,15 @@ iwl_mvm_umac_scan_fill_6g_chan_list(struct iwl_mvm *mvm,
pp->bssid_num = idex_b;
}
-/* TODO: this function can be merged with iwl_mvm_scan_umac_fill_ch_p_v6 */
+/* TODO: this function can be merged with iwl_mvm_scan_umac_fill_ch_p_v7 */
static u32
-iwl_mvm_umac_scan_cfg_channels_v6_6g(struct iwl_mvm *mvm,
+iwl_mvm_umac_scan_cfg_channels_v7_6g(struct iwl_mvm *mvm,
struct iwl_mvm_scan_params *params,
u32 n_channels,
struct iwl_scan_probe_params_v4 *pp,
- struct iwl_scan_channel_params_v6 *cp,
- enum nl80211_iftype vif_type)
+ struct iwl_scan_channel_params_v7 *cp,
+ enum nl80211_iftype vif_type,
+ u32 version)
{
int i;
struct cfg80211_scan_6ghz_params *scan_6ghz_params =
@@ -1745,6 +1751,7 @@ iwl_mvm_umac_scan_cfg_channels_v6_6g(struct iwl_mvm *mvm,
u8 j, k, s_max = 0, b_max = 0, n_used_bssid_entries;
bool force_passive, found = false, allow_passive = true,
unsolicited_probe_on_chan = false, psc_no_listen = false;
+ s8 psd_20 = IEEE80211_RNR_TBTT_PARAMS_PSD_RESERVED;
/*
* Avoid performing passive scan on non PSC channels unless the
@@ -1756,9 +1763,14 @@ iwl_mvm_umac_scan_cfg_channels_v6_6g(struct iwl_mvm *mvm,
continue;
cfg->v1.channel_num = params->channels[i]->hw_value;
- cfg->v2.band = 2;
- cfg->v2.iter_count = 1;
- cfg->v2.iter_interval = 0;
+ if (version < 17)
+ cfg->v2.band = PHY_BAND_6;
+ else
+ cfg->flags |= cpu_to_le32(PHY_BAND_6 <<
+ IWL_CHAN_CFG_FLAGS_BAND_POS);
+
+ cfg->v5.iter_count = 1;
+ cfg->v5.iter_interval = 0;
/*
* The optimize the scan time, i.e., reduce the scan dwell time
@@ -1769,9 +1781,22 @@ iwl_mvm_umac_scan_cfg_channels_v6_6g(struct iwl_mvm *mvm,
*/
n_used_bssid_entries = 3;
for (j = 0; j < params->n_6ghz_params; j++) {
+ s8 tmp_psd_20;
+
if (!(scan_6ghz_params[j].channel_idx == i))
continue;
+ /* Use the highest PSD value allowed as advertised by
+ * APs for this channel
+ */
+ tmp_psd_20 = scan_6ghz_params[j].psd_20;
+ if (tmp_psd_20 !=
+ IEEE80211_RNR_TBTT_PARAMS_PSD_RESERVED &&
+ (psd_20 ==
+ IEEE80211_RNR_TBTT_PARAMS_PSD_RESERVED ||
+ psd_20 < tmp_psd_20))
+ psd_20 = tmp_psd_20;
+
found = false;
unsolicited_probe_on_chan |=
scan_6ghz_params[j].unsolicited_probe;
@@ -1875,6 +1900,9 @@ iwl_mvm_umac_scan_cfg_channels_v6_6g(struct iwl_mvm *mvm,
flags |= bssid_bitmap | (s_ssid_bitmap << 16);
cfg->flags |= cpu_to_le32(flags);
+ if (version >= 17)
+ cfg->v5.psd_20 = psd_20;
+
ch_cnt++;
}
@@ -2292,11 +2320,12 @@ static int iwl_mvm_scan_umac(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
}
static void
-iwl_mvm_scan_umac_fill_general_p_v11(struct iwl_mvm *mvm,
+iwl_mvm_scan_umac_fill_general_p_v12(struct iwl_mvm *mvm,
struct iwl_mvm_scan_params *params,
struct ieee80211_vif *vif,
struct iwl_scan_general_params_v11 *gp,
- u16 gen_flags, u8 gen_flags2)
+ u16 gen_flags, u8 gen_flags2,
+ u32 version)
{
struct iwl_mvm_vif *scan_vif = iwl_mvm_vif_from_mac80211(vif);
@@ -2313,7 +2342,23 @@ iwl_mvm_scan_umac_fill_general_p_v11(struct iwl_mvm *mvm,
if (gen_flags & IWL_UMAC_SCAN_GEN_FLAGS_V2_FRAGMENTED_LMAC2)
gp->num_of_fragments[SCAN_HB_LMAC_IDX] = IWL_SCAN_NUM_OF_FRAGS;
- gp->scan_start_mac_id = scan_vif->id;
+ if (version < 12) {
+ gp->scan_start_mac_or_link_id = scan_vif->id;
+ } else {
+ struct iwl_mvm_vif_link_info *link_info;
+ u8 link_id = 0;
+
+ /* Use one of the active link (if any). In the future it would
+ * be possible that the link ID would be part of the scan
+ * request coming from upper layers so we would need to use it.
+ */
+ if (vif->active_links)
+ link_id = ffs(vif->active_links) - 1;
+
+ link_info = scan_vif->link[link_id];
+ if (!WARN_ON(!link_info))
+ gp->scan_start_mac_or_link_id = link_info->fw_link_id;
+ }
}
static void
@@ -2352,21 +2397,22 @@ iwl_mvm_scan_umac_fill_ch_p_v4(struct iwl_mvm *mvm,
}
static void
-iwl_mvm_scan_umac_fill_ch_p_v6(struct iwl_mvm *mvm,
+iwl_mvm_scan_umac_fill_ch_p_v7(struct iwl_mvm *mvm,
struct iwl_mvm_scan_params *params,
struct ieee80211_vif *vif,
- struct iwl_scan_channel_params_v6 *cp,
- u32 channel_cfg_flags)
+ struct iwl_scan_channel_params_v7 *cp,
+ u32 channel_cfg_flags,
+ u32 version)
{
cp->flags = iwl_mvm_scan_umac_chan_flags_v2(mvm, params, vif);
cp->count = params->n_channels;
cp->n_aps_override[0] = IWL_SCAN_ADWELL_N_APS_GO_FRIENDLY;
cp->n_aps_override[1] = IWL_SCAN_ADWELL_N_APS_SOCIAL_CHS;
- iwl_mvm_umac_scan_cfg_channels_v6(mvm, params->channels, cp,
+ iwl_mvm_umac_scan_cfg_channels_v7(mvm, params->channels, cp,
params->n_channels,
channel_cfg_flags,
- vif->type);
+ vif->type, version);
if (params->enable_6ghz_passive) {
struct ieee80211_supported_band *sband =
@@ -2383,11 +2429,19 @@ iwl_mvm_scan_umac_fill_ch_p_v6(struct iwl_mvm *mvm,
if (!cfg80211_channel_is_psc(channel))
continue;
- cfg->flags = 0;
- cfg->v2.channel_num = channel->hw_value;
- cfg->v2.band = PHY_BAND_6;
- cfg->v2.iter_count = 1;
- cfg->v2.iter_interval = 0;
+ cfg->v5.channel_num = channel->hw_value;
+ cfg->v5.iter_count = 1;
+ cfg->v5.iter_interval = 0;
+
+ if (version < 17) {
+ cfg->flags = 0;
+ cfg->v2.band = PHY_BAND_6;
+ } else {
+ cfg->flags = cpu_to_le32(PHY_BAND_6 <<
+ IWL_CHAN_CFG_FLAGS_BAND_POS);
+ cfg->v5.psd_20 =
+ IEEE80211_RNR_TBTT_PARAMS_PSD_RESERVED;
+ }
cp->count++;
}
}
@@ -2408,9 +2462,9 @@ static int iwl_mvm_scan_umac_v12(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
cmd->uid = cpu_to_le32(uid);
gen_flags = iwl_mvm_scan_umac_flags_v2(mvm, params, vif, type);
- iwl_mvm_scan_umac_fill_general_p_v11(mvm, params, vif,
+ iwl_mvm_scan_umac_fill_general_p_v12(mvm, params, vif,
&scan_p->general_params,
- gen_flags, 0);
+ gen_flags, 0, 12);
ret = iwl_mvm_fill_scan_sched_params(params,
scan_p->periodic_params.schedule,
@@ -2430,9 +2484,9 @@ static int iwl_mvm_scan_umac_v14_and_above(struct iwl_mvm *mvm,
struct iwl_mvm_scan_params *params,
int type, int uid, u32 version)
{
- struct iwl_scan_req_umac_v15 *cmd = mvm->scan_cmd;
- struct iwl_scan_req_params_v15 *scan_p = &cmd->scan_params;
- struct iwl_scan_channel_params_v6 *cp = &scan_p->channel_params;
+ struct iwl_scan_req_umac_v17 *cmd = mvm->scan_cmd;
+ struct iwl_scan_req_params_v17 *scan_p = &cmd->scan_params;
+ struct iwl_scan_channel_params_v7 *cp = &scan_p->channel_params;
struct iwl_scan_probe_params_v4 *pb = &scan_p->probe_params;
int ret;
u16 gen_flags;
@@ -2451,9 +2505,9 @@ static int iwl_mvm_scan_umac_v14_and_above(struct iwl_mvm *mvm,
else
gen_flags2 = 0;
- iwl_mvm_scan_umac_fill_general_p_v11(mvm, params, vif,
+ iwl_mvm_scan_umac_fill_general_p_v12(mvm, params, vif,
&scan_p->general_params,
- gen_flags, gen_flags2);
+ gen_flags, gen_flags2, version);
ret = iwl_mvm_fill_scan_sched_params(params,
scan_p->periodic_params.schedule,
@@ -2462,11 +2516,13 @@ static int iwl_mvm_scan_umac_v14_and_above(struct iwl_mvm *mvm,
return ret;
if (!params->scan_6ghz) {
- iwl_mvm_scan_umac_fill_probe_p_v4(params, &scan_p->probe_params,
- &bitmap_ssid);
- iwl_mvm_scan_umac_fill_ch_p_v6(mvm, params, vif,
- &scan_p->channel_params, bitmap_ssid);
-
+ iwl_mvm_scan_umac_fill_probe_p_v4(params,
+ &scan_p->probe_params,
+ &bitmap_ssid);
+ iwl_mvm_scan_umac_fill_ch_p_v7(mvm, params, vif,
+ &scan_p->channel_params,
+ bitmap_ssid,
+ version);
return 0;
} else {
pb->preq = params->preq;
@@ -2478,9 +2534,10 @@ static int iwl_mvm_scan_umac_v14_and_above(struct iwl_mvm *mvm,
iwl_mvm_umac_scan_fill_6g_chan_list(mvm, params, pb);
- cp->count = iwl_mvm_umac_scan_cfg_channels_v6_6g(mvm, params,
+ cp->count = iwl_mvm_umac_scan_cfg_channels_v7_6g(mvm, params,
params->n_channels,
- pb, cp, vif->type);
+ pb, cp, vif->type,
+ version);
if (!cp->count) {
mvm->scan_uid_status[uid] = 0;
return -EINVAL;
@@ -2507,6 +2564,20 @@ static int iwl_mvm_scan_umac_v15(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
return iwl_mvm_scan_umac_v14_and_above(mvm, vif, params, type, uid, 15);
}
+static int iwl_mvm_scan_umac_v16(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
+ struct iwl_mvm_scan_params *params, int type,
+ int uid)
+{
+ return iwl_mvm_scan_umac_v14_and_above(mvm, vif, params, type, uid, 16);
+}
+
+static int iwl_mvm_scan_umac_v17(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
+ struct iwl_mvm_scan_params *params, int type,
+ int uid)
+{
+ return iwl_mvm_scan_umac_v14_and_above(mvm, vif, params, type, uid, 17);
+}
+
static int iwl_mvm_num_scans(struct iwl_mvm *mvm)
{
return hweight32(mvm->scan_status & IWL_MVM_SCAN_MASK);
@@ -2622,6 +2693,8 @@ struct iwl_scan_umac_handler {
static const struct iwl_scan_umac_handler iwl_scan_umac_handlers[] = {
/* set the newest version first to shorten the list traverse time */
+ IWL_SCAN_UMAC_HANDLER(17),
+ IWL_SCAN_UMAC_HANDLER(16),
IWL_SCAN_UMAC_HANDLER(15),
IWL_SCAN_UMAC_HANDLER(14),
IWL_SCAN_UMAC_HANDLER(12),
@@ -3210,7 +3283,9 @@ static size_t iwl_scan_req_umac_get_size(u8 scan_ver)
return sizeof(struct iwl_scan_req_umac_v12);
case 14:
case 15:
- return sizeof(struct iwl_scan_req_umac_v15);
+ case 16:
+ case 17:
+ return sizeof(struct iwl_scan_req_umac_v17);
}
return 0;
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/sf.c b/drivers/net/wireless/intel/iwlwifi/mvm/sf.c
index 98f330fcf678..30d4233595e8 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/sf.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/sf.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
- * Copyright (C) 2013-2014, 2018-2019, 2022 Intel Corporation
+ * Copyright (C) 2013-2014, 2018-2019, 2022-2023 Intel Corporation
* Copyright (C) 2013-2014 Intel Mobile Communications GmbH
*/
#include "mvm.h"
@@ -180,9 +180,6 @@ static int iwl_mvm_sf_config(struct iwl_mvm *mvm, struct ieee80211_sta *sta,
};
int ret = 0;
- if (mvm->cfg->disable_dummy_notification)
- sf_cmd.state |= cpu_to_le32(SF_CFG_DUMMY_NOTIF_OFF);
-
/*
* If an associated AP sta changed its antenna configuration, the state
* will remain FULL_ON but SF parameters need to be reconsidered.
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/sta.c b/drivers/net/wireless/intel/iwlwifi/mvm/sta.c
index 05a54a69c135..3b9a343d4f67 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/sta.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/sta.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
- * Copyright (C) 2012-2015, 2018-2022 Intel Corporation
+ * Copyright (C) 2012-2015, 2018-2023 Intel Corporation
* Copyright (C) 2013-2015 Intel Mobile Communications GmbH
* Copyright (C) 2016-2017 Intel Deutschland GmbH
*/
@@ -60,22 +60,27 @@ u32 iwl_mvm_get_sta_ampdu_dens(struct ieee80211_link_sta *link_sta,
if (WARN_ON(!link_sta))
return 0;
- if (link_sta->ht_cap.ht_supported)
+ /* Note that we always use only legacy & highest supported PPDUs, so
+ * of Draft P802.11be D.30 Table 10-12a--Fields used for calculating
+ * the maximum A-MPDU size of various PPDU types in different bands,
+ * we only need to worry about the highest supported PPDU type here.
+ */
+
+ if (link_sta->ht_cap.ht_supported) {
+ agg_size = link_sta->ht_cap.ampdu_factor;
mpdu_dens = link_sta->ht_cap.ampdu_density;
+ }
- if (link_conf->chandef.chan->band ==
- NL80211_BAND_6GHZ) {
+ if (link_conf->chandef.chan->band == NL80211_BAND_6GHZ) {
+ /* overwrite HT values on 6 GHz */
mpdu_dens = le16_get_bits(link_sta->he_6ghz_capa.capa,
IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START);
agg_size = le16_get_bits(link_sta->he_6ghz_capa.capa,
IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP);
} else if (link_sta->vht_cap.vht_supported) {
- agg_size = link_sta->vht_cap.cap &
- IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK;
- agg_size >>=
- IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT;
- } else if (link_sta->ht_cap.ht_supported) {
- agg_size = link_sta->ht_cap.ampdu_factor;
+ /* if VHT supported overwrite HT value */
+ agg_size = u32_get_bits(link_sta->vht_cap.cap,
+ IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK);
}
/* D6.0 10.12.2 A-MPDU length limit rules
@@ -91,10 +96,13 @@ u32 iwl_mvm_get_sta_ampdu_dens(struct ieee80211_link_sta *link_sta,
u8_get_bits(link_sta->he_cap.he_cap_elem.mac_cap_info[3],
IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_MASK);
+ if (link_sta->eht_cap.has_eht)
+ agg_size += u8_get_bits(link_sta->eht_cap.eht_cap_elem.mac_cap_info[1],
+ IEEE80211_EHT_MAC_CAP1_MAX_AMPDU_LEN_MASK);
+
/* Limit to max A-MPDU supported by FW */
- if (agg_size > (STA_FLG_MAX_AGG_SIZE_4M >> STA_FLG_MAX_AGG_SIZE_SHIFT))
- agg_size = (STA_FLG_MAX_AGG_SIZE_4M >>
- STA_FLG_MAX_AGG_SIZE_SHIFT);
+ agg_size = min_t(u32, agg_size,
+ STA_FLG_MAX_AGG_SIZE_4M >> STA_FLG_MAX_AGG_SIZE_SHIFT);
*_agg_size = agg_size;
return mpdu_dens;
@@ -1679,7 +1687,7 @@ static int iwl_mvm_add_int_sta_common(struct iwl_mvm *mvm,
memset(&cmd, 0, sizeof(cmd));
cmd.sta_id = sta->sta_id;
- if (iwl_fw_lookup_cmd_ver(mvm->fw, ADD_STA, 0) >= 12 &&
+ if (iwl_mvm_has_new_station_api(mvm->fw) &&
sta->type == IWL_STA_AUX_ACTIVITY)
cmd.mac_id_n_color = cpu_to_le32(mac_id);
else
@@ -1859,6 +1867,8 @@ int iwl_mvm_add_sta(struct iwl_mvm *mvm,
ret = iwl_mvm_sta_init(mvm, vif, sta, sta_id,
sta->tdls ? IWL_STA_TDLS_LINK : IWL_STA_LINK);
+ if (ret)
+ goto err;
update_fw:
ret = iwl_mvm_sta_send_to_fw(mvm, sta, sta_update, sta_flags);
@@ -2070,13 +2080,6 @@ bool iwl_mvm_sta_del(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
cancel_delayed_work(&mvm->tdls_cs.dwork);
}
- /*
- * Make sure that the tx response code sees the station as -EBUSY and
- * calls the drain worker.
- */
- spin_lock_bh(&mvm_sta->lock);
- spin_unlock_bh(&mvm_sta->lock);
-
return false;
}
@@ -2882,7 +2885,7 @@ int iwl_mvm_sta_rx_agg(struct iwl_mvm *mvm, struct ieee80211_sta *sta,
}
if (iwl_mvm_has_new_rx_api(mvm) && start) {
- u16 reorder_buf_size = buf_size * sizeof(baid_data->entries[0]);
+ u32 reorder_buf_size = buf_size * sizeof(baid_data->entries[0]);
/* sparse doesn't like the __align() so don't check */
#ifndef __CHECKER__
@@ -4306,16 +4309,27 @@ int iwl_mvm_add_pasn_sta(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
u16 queue;
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
struct ieee80211_key_conf *keyconf;
+ unsigned int wdg_timeout =
+ iwl_mvm_get_wd_timeout(mvm, vif, false, false);
+ bool mld = iwl_mvm_has_mld_api(mvm->fw);
+ u32 type = mld ? STATION_TYPE_PEER : IWL_STA_LINK;
ret = iwl_mvm_allocate_int_sta(mvm, sta, 0,
- NL80211_IFTYPE_UNSPECIFIED,
- IWL_STA_LINK);
+ NL80211_IFTYPE_UNSPECIFIED, type);
if (ret)
return ret;
- ret = iwl_mvm_add_int_sta_with_queue(mvm, mvmvif->id, mvmvif->color,
- addr, sta, &queue,
- IWL_MVM_TX_FIFO_BE);
+ if (mld)
+ ret = iwl_mvm_mld_add_int_sta_with_queue(mvm, sta, addr,
+ mvmvif->deflink.fw_link_id,
+ &queue,
+ IWL_MAX_TID_COUNT,
+ &wdg_timeout);
+ else
+ ret = iwl_mvm_add_int_sta_with_queue(mvm, mvmvif->id,
+ mvmvif->color, addr, sta,
+ &queue,
+ IWL_MVM_TX_FIFO_BE);
if (ret)
goto out;
@@ -4328,9 +4342,23 @@ int iwl_mvm_add_pasn_sta(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
keyconf->cipher = cipher;
memcpy(keyconf->key, key, key_len);
keyconf->keylen = key_len;
+ keyconf->flags = IEEE80211_KEY_FLAG_PAIRWISE;
+
+ if (mld) {
+ /* The MFP flag is set according to the station mfp field. Since
+ * we don't have a station, set it manually.
+ */
+ u32 key_flags =
+ iwl_mvm_get_sec_flags(mvm, vif, NULL, keyconf) |
+ IWL_SEC_KEY_FLAG_MFP;
+ u32 sta_mask = BIT(sta->sta_id);
+
+ ret = iwl_mvm_mld_send_key(mvm, sta_mask, key_flags, keyconf);
+ } else {
+ ret = iwl_mvm_send_sta_key(mvm, sta->sta_id, keyconf, false,
+ 0, NULL, 0, 0, true);
+ }
- ret = iwl_mvm_send_sta_key(mvm, sta->sta_id, keyconf, false,
- 0, NULL, 0, 0, true);
kfree(keyconf);
return 0;
out:
@@ -4340,10 +4368,10 @@ out:
void iwl_mvm_cancel_channel_switch(struct iwl_mvm *mvm,
struct ieee80211_vif *vif,
- u32 mac_id)
+ u32 id)
{
struct iwl_cancel_channel_switch_cmd cancel_channel_switch_cmd = {
- .mac_id = cpu_to_le32(mac_id),
+ .id = cpu_to_le32(id),
};
int ret;
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/sta.h b/drivers/net/wireless/intel/iwlwifi/mvm/sta.h
index a61d4f88125f..7364346a1209 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/sta.h
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/sta.h
@@ -336,6 +336,9 @@ struct iwl_mvm_rxq_dup_data {
* @sta_id: the index of the station in the fw
* @lq_sta: holds rate scaling data, either for the case when RS is done in
* the driver - %rs_drv or in the FW - %rs_fw.
+ * @orig_amsdu_len: used to save the original amsdu_len when it is changed via
+ * debugfs. If it's set to 0, it means that it is it's not set via
+ * debugfs.
* @avg_energy: energy as reported by FW statistics notification
*/
struct iwl_mvm_link_sta {
@@ -346,6 +349,8 @@ struct iwl_mvm_link_sta {
struct iwl_lq_sta rs_drv;
} lq_sta;
+ u16 orig_amsdu_len;
+
u8 avg_energy;
};
@@ -365,6 +370,7 @@ struct iwl_mvm_link_sta {
* and from Tx response flow, it needs a spinlock.
* @tid_data: per tid data + mgmt. Look at %iwl_mvm_tid_data.
* @tid_to_baid: a simple map of TID to baid
+ * @vif: a vif pointer
* @reserved_queue: the queue reserved for this STA for DQA purposes
* Every STA has is given one reserved queue to allow it to operate. If no
* such queue can be guaranteed, the STA addition will fail.
@@ -374,10 +380,8 @@ struct iwl_mvm_link_sta {
* @amsdu_enabled: bitmap of TX AMSDU allowed TIDs.
* In case TLC offload is not active it is either 0xFFFF or 0.
* @max_amsdu_len: max AMSDU length
- * @orig_amsdu_len: used to save the original amsdu_len when it is changed via
- * debugfs. If it's set to 0, it means that it is it's not set via
- * debugfs.
* @agg_tids: bitmap of tids whose status is operational aggregated (IWL_AGG_ON)
+ * @sleeping: sta sleep transitions in power management
* @sleep_tx_count: the number of frames that we told the firmware to let out
* even when that station is asleep. This is useful in case the queue
* gets empty before all the frames were sent, which can happen when
@@ -427,7 +431,6 @@ struct iwl_mvm_sta {
bool disable_tx;
u16 amsdu_enabled;
u16 max_amsdu_len;
- u16 orig_amsdu_len;
bool sleeping;
u8 agg_tids;
u8 sleep_tx_count;
@@ -580,7 +583,7 @@ int iwl_mvm_add_pasn_sta(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
u8 *key, u32 key_len);
void iwl_mvm_cancel_channel_switch(struct iwl_mvm *mvm,
struct ieee80211_vif *vif,
- u32 mac_id);
+ u32 id);
/* Queues */
int iwl_mvm_tvqm_enable_txq(struct iwl_mvm *mvm,
struct ieee80211_sta *sta,
@@ -616,7 +619,7 @@ int iwl_mvm_mac_sta_state_common(struct ieee80211_hw *hw,
struct ieee80211_sta *sta,
enum ieee80211_sta_state old_state,
enum ieee80211_sta_state new_state,
- struct iwl_mvm_sta_state_ops *callbacks);
+ const struct iwl_mvm_sta_state_ops *callbacks);
/* New MLD STA related APIs */
/* STA */
@@ -646,6 +649,11 @@ int iwl_mvm_mld_update_sta_links(struct iwl_mvm *mvm,
u16 old_links, u16 new_links);
u32 iwl_mvm_sta_fw_id_mask(struct iwl_mvm *mvm, struct ieee80211_sta *sta,
int filter_link_id);
+int iwl_mvm_mld_add_int_sta_with_queue(struct iwl_mvm *mvm,
+ struct iwl_mvm_int_sta *sta,
+ const u8 *addr, int link_id,
+ u16 *queue, u8 tid,
+ unsigned int *_wdg_timeout);
/* Queues */
void iwl_mvm_mld_modify_all_sta_disable_tx(struct iwl_mvm *mvm,
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/time-event.c b/drivers/net/wireless/intel/iwlwifi/mvm/time-event.c
index 6b7b6250f1bb..5f0e7144a951 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/time-event.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/time-event.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
- * Copyright (C) 2012-2014, 2018-2022 Intel Corporation
+ * Copyright (C) 2012-2014, 2018-2023 Intel Corporation
* Copyright (C) 2013-2015 Intel Mobile Communications GmbH
* Copyright (C) 2017 Intel Deutschland GmbH
*/
@@ -103,7 +103,7 @@ void iwl_mvm_roc_done_wk(struct work_struct *wk)
/* In newer version of this command an aux station is added only
* in cases of dedicated tx queue and need to be removed in end
* of use */
- if (iwl_fw_lookup_cmd_ver(mvm->fw, ADD_STA, 0) >= 12)
+ if (iwl_mvm_has_new_station_api(mvm->fw))
iwl_mvm_rm_aux_sta(mvm);
}
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/tx.c b/drivers/net/wireless/intel/iwlwifi/mvm/tx.c
index 00719e130438..36d70d589aed 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/tx.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/tx.c
@@ -1,12 +1,13 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
- * Copyright (C) 2012-2014, 2018-2022 Intel Corporation
+ * Copyright (C) 2012-2014, 2018-2023 Intel Corporation
* Copyright (C) 2013-2015 Intel Mobile Communications GmbH
* Copyright (C) 2016-2017 Intel Deutschland GmbH
*/
#include <linux/ieee80211.h>
#include <linux/etherdevice.h>
#include <linux/tcp.h>
+#include <net/gso.h>
#include <net/ip.h>
#include <net/ipv6.h>
@@ -40,13 +41,14 @@ iwl_mvm_bar_check_trigger(struct iwl_mvm *mvm, const u8 *addr,
#define OPT_HDR(type, skb, off) \
(type *)(skb_network_header(skb) + (off))
-static u16 iwl_mvm_tx_csum_pre_bz(struct iwl_mvm *mvm, struct sk_buff *skb,
- struct ieee80211_tx_info *info, bool amsdu)
+static u32 iwl_mvm_tx_csum(struct iwl_mvm *mvm, struct sk_buff *skb,
+ struct ieee80211_tx_info *info,
+ bool amsdu)
{
struct ieee80211_hdr *hdr = (void *)skb->data;
+ u16 mh_len = ieee80211_hdrlen(hdr->frame_control);
u16 offload_assist = 0;
#if IS_ENABLED(CONFIG_INET)
- u16 mh_len = ieee80211_hdrlen(hdr->frame_control);
u8 protocol = 0;
/* Do not compute checksum if already computed */
@@ -118,6 +120,8 @@ static u16 iwl_mvm_tx_csum_pre_bz(struct iwl_mvm *mvm, struct sk_buff *skb,
else
udp_hdr(skb)->check = 0;
+out:
+#endif
/*
* mac header len should include IV, size is in words unless
* the IV is added by the firmware like in WEP.
@@ -130,8 +134,6 @@ static u16 iwl_mvm_tx_csum_pre_bz(struct iwl_mvm *mvm, struct sk_buff *skb,
mh_len /= 2;
offload_assist |= mh_len << TX_CMD_OFFLD_MH_SIZE;
-out:
-#endif
if (amsdu)
offload_assist |= BIT(TX_CMD_OFFLD_AMSDU);
else if (ieee80211_hdrlen(hdr->frame_control) % 4)
@@ -141,54 +143,6 @@ out:
return offload_assist;
}
-u32 iwl_mvm_tx_csum_bz(struct iwl_mvm *mvm, struct sk_buff *skb, bool amsdu)
-{
- struct ieee80211_hdr *hdr = (void *)skb->data;
- u32 offload_assist = IWL_TX_CMD_OFFLD_BZ_PARTIAL_CSUM;
- unsigned int hdrlen = ieee80211_hdrlen(hdr->frame_control);
- unsigned int csum_start = skb_checksum_start_offset(skb);
-
- offload_assist |= u32_encode_bits(hdrlen / 2,
- IWL_TX_CMD_OFFLD_BZ_MH_LEN);
- if (amsdu)
- offload_assist |= IWL_TX_CMD_OFFLD_BZ_AMSDU;
- else if (hdrlen % 4)
- /* padding is inserted later in transport */
- offload_assist |= IWL_TX_CMD_OFFLD_BZ_MH_PAD;
-
- if (skb->ip_summed != CHECKSUM_PARTIAL)
- return offload_assist;
-
- offload_assist |= IWL_TX_CMD_OFFLD_BZ_ENABLE_CSUM |
- IWL_TX_CMD_OFFLD_BZ_ZERO2ONES;
-
- /*
- * mac80211 will always calculate checksum in software for
- * non-fast-xmit, and so we can only do offloaded checksum
- * for fast-xmit frames. In this case, we always have the
- * RFC 1042 header present. skb_checksum_start_offset()
- * returns the offset from the beginning, but the hardware
- * needs it from after the header & SNAP header.
- */
- csum_start -= hdrlen + 8;
-
- offload_assist |= u32_encode_bits(csum_start,
- IWL_TX_CMD_OFFLD_BZ_START_OFFS);
- offload_assist |= u32_encode_bits(csum_start + skb->csum_offset,
- IWL_TX_CMD_OFFLD_BZ_RESULT_OFFS);
-
- return offload_assist;
-}
-
-static u32 iwl_mvm_tx_csum(struct iwl_mvm *mvm, struct sk_buff *skb,
- struct ieee80211_tx_info *info,
- bool amsdu)
-{
- if (!iwl_mvm_has_new_tx_csum(mvm))
- return iwl_mvm_tx_csum_pre_bz(mvm, skb, info, amsdu);
- return iwl_mvm_tx_csum_bz(mvm, skb, amsdu);
-}
-
/*
* Sets most of the Tx cmd's fields
*/
@@ -288,7 +242,7 @@ void iwl_mvm_set_tx_cmd(struct iwl_mvm *mvm, struct sk_buff *skb,
tx_cmd->sta_id = sta_id;
tx_cmd->offload_assist =
- cpu_to_le16(iwl_mvm_tx_csum_pre_bz(mvm, skb, info, amsdu));
+ cpu_to_le16(iwl_mvm_tx_csum(mvm, skb, info, amsdu));
}
static u32 iwl_mvm_get_tx_ant(struct iwl_mvm *mvm,
@@ -308,6 +262,54 @@ static u32 iwl_mvm_get_tx_ant(struct iwl_mvm *mvm,
return BIT(mvm->mgmt_last_antenna_idx) << RATE_MCS_ANT_POS;
}
+static u32 iwl_mvm_get_inject_tx_rate(struct iwl_mvm *mvm,
+ struct ieee80211_tx_info *info)
+{
+ struct ieee80211_tx_rate *rate = &info->control.rates[0];
+ u32 result;
+
+ /*
+ * we only care about legacy/HT/VHT so far, so we can
+ * build in v1 and use iwl_new_rate_from_v1()
+ */
+
+ if (rate->flags & IEEE80211_TX_RC_VHT_MCS) {
+ u8 mcs = ieee80211_rate_get_vht_mcs(rate);
+ u8 nss = ieee80211_rate_get_vht_nss(rate);
+
+ result = RATE_MCS_VHT_MSK_V1;
+ result |= u32_encode_bits(mcs, RATE_VHT_MCS_RATE_CODE_MSK);
+ result |= u32_encode_bits(nss, RATE_MCS_NSS_MSK);
+ if (rate->flags & IEEE80211_TX_RC_SHORT_GI)
+ result |= RATE_MCS_SGI_MSK_V1;
+ if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
+ result |= u32_encode_bits(1, RATE_MCS_CHAN_WIDTH_MSK_V1);
+ else if (rate->flags & IEEE80211_TX_RC_80_MHZ_WIDTH)
+ result |= u32_encode_bits(2, RATE_MCS_CHAN_WIDTH_MSK_V1);
+ else if (rate->flags & IEEE80211_TX_RC_160_MHZ_WIDTH)
+ result |= u32_encode_bits(3, RATE_MCS_CHAN_WIDTH_MSK_V1);
+ } else if (rate->flags & IEEE80211_TX_RC_MCS) {
+ result = RATE_MCS_HT_MSK_V1;
+ result |= u32_encode_bits(rate->idx,
+ RATE_HT_MCS_RATE_CODE_MSK_V1 |
+ RATE_HT_MCS_NSS_MSK_V1);
+ if (rate->flags & IEEE80211_TX_RC_SHORT_GI)
+ result |= RATE_MCS_SGI_MSK_V1;
+ if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
+ result |= u32_encode_bits(1, RATE_MCS_CHAN_WIDTH_MSK_V1);
+ if (info->flags & IEEE80211_TX_CTL_LDPC)
+ result |= RATE_MCS_LDPC_MSK_V1;
+ if (u32_get_bits(info->flags, IEEE80211_TX_CTL_STBC))
+ result |= RATE_MCS_STBC_MSK;
+ } else {
+ return 0;
+ }
+
+ if (iwl_fw_lookup_notif_ver(mvm->fw, LONG_GROUP, TX_CMD, 0) > 6)
+ return iwl_new_rate_from_v1(result);
+ return result;
+}
+
static u32 iwl_mvm_get_tx_rate(struct iwl_mvm *mvm,
struct ieee80211_tx_info *info,
struct ieee80211_sta *sta, __le16 fc)
@@ -317,8 +319,15 @@ static u32 iwl_mvm_get_tx_rate(struct iwl_mvm *mvm,
u32 rate_flags = 0;
bool is_cck;
- /* info->control is only relevant for non HW rate control */
- if (!ieee80211_hw_check(mvm->hw, HAS_RATE_CONTROL)) {
+ if (unlikely(info->control.flags & IEEE80211_TX_CTRL_RATE_INJECT)) {
+ u32 result = iwl_mvm_get_inject_tx_rate(mvm, info);
+
+ if (result)
+ return result;
+ rate_idx = info->control.rates[0].idx;
+ } else if (!ieee80211_hw_check(mvm->hw, HAS_RATE_CONTROL)) {
+ /* info->control is only relevant for non HW rate control */
+
/* HT rate doesn't make sense for a non data frame */
WARN_ONCE(info->control.rates[0].flags & IEEE80211_TX_RC_MCS &&
!ieee80211_is_data(fc),
@@ -398,7 +407,8 @@ void iwl_mvm_set_tx_cmd_rate(struct iwl_mvm *mvm, struct iwl_tx_cmd *tx_cmd,
* table is controlled by LINK_QUALITY commands
*/
- if (ieee80211_is_data(fc) && sta) {
+ if (likely(ieee80211_is_data(fc) && sta &&
+ !(info->control.flags & IEEE80211_TX_CTRL_RATE_INJECT))) {
struct iwl_mvm_sta *mvmsta = iwl_mvm_sta_from_mac80211(sta);
if (mvmsta->sta_state >= IEEE80211_STA_AUTHORIZED) {
@@ -556,9 +566,8 @@ iwl_mvm_set_tx_params(struct iwl_mvm *mvm, struct sk_buff *skb,
cmd->rate_n_flags = cpu_to_le32(rate_n_flags);
} else {
struct iwl_tx_cmd_gen2 *cmd = (void *)dev_cmd->payload;
- u16 offload_assist = iwl_mvm_tx_csum_pre_bz(mvm, skb,
- info,
- amsdu);
+ u16 offload_assist = iwl_mvm_tx_csum(mvm, skb,
+ info, amsdu);
cmd->offload_assist = cpu_to_le16(offload_assist);
@@ -749,6 +758,8 @@ int iwl_mvm_tx_skb_non_sta(struct iwl_mvm *mvm, struct sk_buff *skb)
}
link = mvmvif->link[link_id];
+ if (WARN_ON(!link))
+ return -1;
if (!ieee80211_is_data(hdr->frame_control))
sta_id = link->bcast_sta.sta_id;
@@ -840,7 +851,7 @@ unsigned int iwl_mvm_max_amsdu_size(struct iwl_mvm *mvm,
band = mvmsta->vif->bss_conf.chandef.chan->band;
}
- lmac = iwl_mvm_get_lmac_id(mvm->fw, band);
+ lmac = iwl_mvm_get_lmac_id(mvm, band);
} else if (fw_has_capa(&mvm->fw->ucode_capa,
IWL_UCODE_TLV_CAPA_CDB_SUPPORT)) {
/* for real MLO restrict to both LMACs if they exist */
@@ -2065,7 +2076,8 @@ void iwl_mvm_rx_ba_notif(struct iwl_mvm *mvm, struct iwl_rx_cmd_buffer *rxb)
u16 tfd_cnt;
int i;
- if (unlikely(sizeof(*ba_res) > pkt_len))
+ if (IWL_FW_CHECK(mvm, sizeof(*ba_res) > pkt_len,
+ "short BA notification (%d)\n", pkt_len))
return;
sta_id = ba_res->sta_id;
@@ -2077,7 +2089,13 @@ void iwl_mvm_rx_ba_notif(struct iwl_mvm *mvm, struct iwl_rx_cmd_buffer *rxb)
(void *)(uintptr_t)ba_res->reduced_txp;
tfd_cnt = le16_to_cpu(ba_res->tfd_cnt);
- if (!tfd_cnt || struct_size(ba_res, tfd, tfd_cnt) > pkt_len)
+ if (!tfd_cnt)
+ return;
+
+ if (IWL_FW_CHECK(mvm,
+ struct_size(ba_res, tfd, tfd_cnt) > pkt_len,
+ "short BA notification (tfds:%d, size:%d)\n",
+ tfd_cnt, pkt_len))
return;
rcu_read_lock();
@@ -2135,7 +2153,9 @@ void iwl_mvm_rx_ba_notif(struct iwl_mvm *mvm, struct iwl_rx_cmd_buffer *rxb)
rcu_read_lock();
mvmsta = iwl_mvm_sta_from_staid_rcu(mvm, sta_id);
- if (WARN_ON_ONCE(!mvmsta)) {
+ if (IWL_FW_CHECK(mvm, !mvmsta,
+ "invalid STA ID %d in BA notif\n",
+ sta_id)) {
rcu_read_unlock();
return;
}
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/utils.c b/drivers/net/wireless/intel/iwlwifi/mvm/utils.c
index af31b09c3966..48016b4343d2 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/utils.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/utils.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
- * Copyright (C) 2012-2014, 2018-2022 Intel Corporation
+ * Copyright (C) 2012-2014, 2018-2023 Intel Corporation
* Copyright (C) 2013-2014 Intel Mobile Communications GmbH
* Copyright (C) 2015-2017 Intel Deutschland GmbH
*/
@@ -312,6 +312,10 @@ void iwl_mvm_update_smps(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
smps_mode = IEEE80211_SMPS_DYNAMIC;
}
+ /* SMPS is disabled in eSR */
+ if (mvmvif->esr_active)
+ smps_mode = IEEE80211_SMPS_OFF;
+
ieee80211_request_smps(vif, link_id, smps_mode);
}
@@ -413,16 +417,20 @@ static void iwl_mvm_diversity_iter(void *_data, u8 *mac,
{
struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
struct iwl_mvm_diversity_iter_data *data = _data;
- int i;
+ int i, link_id;
- if (mvmvif->deflink.phy_ctxt != data->ctxt)
- return;
+ for_each_mvm_vif_valid_link(mvmvif, link_id) {
+ struct iwl_mvm_vif_link_info *link_info = mvmvif->link[link_id];
- for (i = 0; i < NUM_IWL_MVM_SMPS_REQ; i++) {
- if (mvmvif->deflink.smps_requests[i] == IEEE80211_SMPS_STATIC ||
- mvmvif->deflink.smps_requests[i] == IEEE80211_SMPS_DYNAMIC) {
- data->result = false;
- break;
+ if (link_info->phy_ctxt != data->ctxt)
+ continue;
+
+ for (i = 0; i < NUM_IWL_MVM_SMPS_REQ; i++) {
+ if (link_info->smps_requests[i] == IEEE80211_SMPS_STATIC ||
+ link_info->smps_requests[i] == IEEE80211_SMPS_DYNAMIC) {
+ data->result = false;
+ break;
+ }
}
}
}
diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info-gen3.c b/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info-gen3.c
index cb60ba40fe97..fa4a14546860 100644
--- a/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info-gen3.c
+++ b/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info-gen3.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
- * Copyright (C) 2018-2022 Intel Corporation
+ * Copyright (C) 2018-2023 Intel Corporation
*/
#include "iwl-trans.h"
#include "iwl-fh.h"
@@ -281,70 +281,273 @@ void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans, bool alive)
trans_pcie->prph_info = NULL;
}
-int iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans,
- const void *data, u32 len)
+static int iwl_pcie_load_payloads_continuously(struct iwl_trans *trans,
+ const struct iwl_pnvm_image *pnvm_data,
+ struct iwl_dram_data *dram)
+{
+ u32 len, len0, len1;
+
+ if (pnvm_data->n_chunks != UNFRAGMENTED_PNVM_PAYLOADS_NUMBER) {
+ IWL_DEBUG_FW(trans, "expected 2 payloads, got %d.\n",
+ pnvm_data->n_chunks);
+ return -EINVAL;
+ }
+
+ len0 = pnvm_data->chunks[0].len;
+ len1 = pnvm_data->chunks[1].len;
+ if (len1 > 0xFFFFFFFF - len0) {
+ IWL_DEBUG_FW(trans, "sizes of payloads overflow.\n");
+ return -EINVAL;
+ }
+ len = len0 + len1;
+
+ dram->block = iwl_pcie_ctxt_info_dma_alloc_coherent(trans, len,
+ &dram->physical);
+ if (!dram->block) {
+ IWL_DEBUG_FW(trans, "Failed to allocate PNVM DMA.\n");
+ return -ENOMEM;
+ }
+
+ dram->size = len;
+ memcpy(dram->block, pnvm_data->chunks[0].data, len0);
+ memcpy((u8 *)dram->block + len0, pnvm_data->chunks[1].data, len1);
+
+ return 0;
+}
+
+static int iwl_pcie_load_payloads_segments
+ (struct iwl_trans *trans,
+ struct iwl_dram_regions *dram_regions,
+ const struct iwl_pnvm_image *pnvm_data)
+{
+ struct iwl_dram_data *cur_payload_dram = &dram_regions->drams[0];
+ struct iwl_dram_data *desc_dram = &dram_regions->prph_scratch_mem_desc;
+ struct iwl_prph_scrath_mem_desc_addr_array *addresses;
+ const void *data;
+ u32 len;
+ int i;
+
+ /* allocate and init DRAM descriptors array */
+ len = sizeof(struct iwl_prph_scrath_mem_desc_addr_array);
+ desc_dram->block = iwl_pcie_ctxt_info_dma_alloc_coherent
+ (trans,
+ len,
+ &desc_dram->physical);
+ if (!desc_dram->block) {
+ IWL_DEBUG_FW(trans, "Failed to allocate PNVM DMA.\n");
+ return -ENOMEM;
+ }
+ desc_dram->size = len;
+ memset(desc_dram->block, 0, len);
+
+ /* allocate DRAM region for each payload */
+ dram_regions->n_regions = 0;
+ for (i = 0; i < pnvm_data->n_chunks; i++) {
+ len = pnvm_data->chunks[i].len;
+ data = pnvm_data->chunks[i].data;
+
+ if (iwl_pcie_ctxt_info_alloc_dma(trans,
+ data,
+ len,
+ cur_payload_dram)) {
+ iwl_trans_pcie_free_pnvm_dram_regions(dram_regions,
+ trans->dev);
+ return -ENOMEM;
+ }
+
+ dram_regions->n_regions++;
+ cur_payload_dram++;
+ }
+
+ /* fill desc with the DRAM payloads addresses */
+ addresses = desc_dram->block;
+ for (i = 0; i < pnvm_data->n_chunks; i++) {
+ addresses->mem_descs[i] =
+ cpu_to_le64(dram_regions->drams[i].physical);
+ }
+
+ return 0;
+
+}
+
+int iwl_trans_pcie_ctx_info_gen3_load_pnvm(struct iwl_trans *trans,
+ const struct iwl_pnvm_image *pnvm_payloads,
+ const struct iwl_ucode_capabilities *capa)
{
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl =
&trans_pcie->prph_scratch->ctrl_cfg;
- int ret;
+ struct iwl_dram_regions *dram_regions = &trans_pcie->pnvm_data;
+ int ret = 0;
+
+ /* only allocate the DRAM if not allocated yet */
+ if (trans->pnvm_loaded)
+ return 0;
+
+ if (WARN_ON(prph_sc_ctrl->pnvm_cfg.pnvm_size))
+ return -EBUSY;
if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
return 0;
- /* only allocate the DRAM if not allocated yet */
- if (!trans->pnvm_loaded) {
- if (WARN_ON(prph_sc_ctrl->pnvm_cfg.pnvm_size))
- return -EBUSY;
-
- ret = iwl_pcie_ctxt_info_alloc_dma(trans, data, len,
- &trans_pcie->pnvm_dram);
- if (ret < 0) {
- IWL_DEBUG_FW(trans, "Failed to allocate PNVM DMA %d.\n",
- ret);
- return ret;
+ if (!pnvm_payloads->n_chunks) {
+ IWL_DEBUG_FW(trans, "no payloads\n");
+ return -EINVAL;
+ }
+
+ /* save payloads in several DRAM sections */
+ if (fw_has_capa(capa, IWL_UCODE_TLV_CAPA_FRAGMENTED_PNVM_IMG)) {
+ ret = iwl_pcie_load_payloads_segments(trans,
+ dram_regions,
+ pnvm_payloads);
+ if (!ret)
+ trans->pnvm_loaded = true;
+ } else {
+ /* save only in one DRAM section */
+ ret = iwl_pcie_load_payloads_continuously
+ (trans,
+ pnvm_payloads,
+ &dram_regions->drams[0]);
+ if (!ret) {
+ dram_regions->n_regions = 1;
+ trans->pnvm_loaded = true;
}
}
+ return ret;
+}
+
+static inline size_t
+iwl_dram_regions_size(const struct iwl_dram_regions *dram_regions)
+{
+ size_t total_size = 0;
+ int i;
+
+ for (i = 0; i < dram_regions->n_regions; i++)
+ total_size += dram_regions->drams[i].size;
+
+ return total_size;
+}
+
+static void iwl_pcie_set_pnvm_segments(struct iwl_trans *trans)
+{
+ struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
+ struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl =
+ &trans_pcie->prph_scratch->ctrl_cfg;
+ struct iwl_dram_regions *dram_regions = &trans_pcie->pnvm_data;
+
prph_sc_ctrl->pnvm_cfg.pnvm_base_addr =
- cpu_to_le64(trans_pcie->pnvm_dram.physical);
+ cpu_to_le64(dram_regions->prph_scratch_mem_desc.physical);
prph_sc_ctrl->pnvm_cfg.pnvm_size =
- cpu_to_le32(trans_pcie->pnvm_dram.size);
+ cpu_to_le32(iwl_dram_regions_size(dram_regions));
+}
- return 0;
+static void iwl_pcie_set_continuous_pnvm(struct iwl_trans *trans)
+{
+ struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
+ struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl =
+ &trans_pcie->prph_scratch->ctrl_cfg;
+
+ prph_sc_ctrl->pnvm_cfg.pnvm_base_addr =
+ cpu_to_le64(trans_pcie->pnvm_data.drams[0].physical);
+ prph_sc_ctrl->pnvm_cfg.pnvm_size =
+ cpu_to_le32(trans_pcie->pnvm_data.drams[0].size);
+}
+
+void iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans,
+ const struct iwl_ucode_capabilities *capa)
+{
+ if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
+ return;
+
+ if (fw_has_capa(capa, IWL_UCODE_TLV_CAPA_FRAGMENTED_PNVM_IMG))
+ iwl_pcie_set_pnvm_segments(trans);
+ else
+ iwl_pcie_set_continuous_pnvm(trans);
}
-int iwl_trans_pcie_ctx_info_gen3_set_reduce_power(struct iwl_trans *trans,
- const void *data, u32 len)
+int iwl_trans_pcie_ctx_info_gen3_load_reduce_power(struct iwl_trans *trans,
+ const struct iwl_pnvm_image *payloads,
+ const struct iwl_ucode_capabilities *capa)
{
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl =
&trans_pcie->prph_scratch->ctrl_cfg;
- int ret;
+ struct iwl_dram_regions *dram_regions = &trans_pcie->reduced_tables_data;
+ int ret = 0;
+
+ /* only allocate the DRAM if not allocated yet */
+ if (trans->reduce_power_loaded)
+ return 0;
if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
return 0;
- /* only allocate the DRAM if not allocated yet */
- if (!trans->reduce_power_loaded) {
- if (WARN_ON(prph_sc_ctrl->reduce_power_cfg.size))
- return -EBUSY;
+ if (WARN_ON(prph_sc_ctrl->reduce_power_cfg.size))
+ return -EBUSY;
- ret = iwl_pcie_ctxt_info_alloc_dma(trans, data, len,
- &trans_pcie->reduce_power_dram);
- if (ret < 0) {
- IWL_DEBUG_FW(trans,
- "Failed to allocate reduce power DMA %d.\n",
- ret);
- return ret;
+ if (!payloads->n_chunks) {
+ IWL_DEBUG_FW(trans, "no payloads\n");
+ return -EINVAL;
+ }
+
+ /* save payloads in several DRAM sections */
+ if (fw_has_capa(capa, IWL_UCODE_TLV_CAPA_FRAGMENTED_PNVM_IMG)) {
+ ret = iwl_pcie_load_payloads_segments(trans,
+ dram_regions,
+ payloads);
+ if (!ret)
+ trans->reduce_power_loaded = true;
+ } else {
+ /* save only in one DRAM section */
+ ret = iwl_pcie_load_payloads_continuously
+ (trans,
+ payloads,
+ &dram_regions->drams[0]);
+ if (!ret) {
+ dram_regions->n_regions = 1;
+ trans->reduce_power_loaded = true;
}
}
+ return ret;
+}
+
+static void iwl_pcie_set_reduce_power_segments(struct iwl_trans *trans)
+{
+ struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
+ struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl =
+ &trans_pcie->prph_scratch->ctrl_cfg;
+ struct iwl_dram_regions *dram_regions = &trans_pcie->reduced_tables_data;
+
prph_sc_ctrl->reduce_power_cfg.base_addr =
- cpu_to_le64(trans_pcie->reduce_power_dram.physical);
+ cpu_to_le64(dram_regions->prph_scratch_mem_desc.physical);
prph_sc_ctrl->reduce_power_cfg.size =
- cpu_to_le32(trans_pcie->reduce_power_dram.size);
+ cpu_to_le32(iwl_dram_regions_size(dram_regions));
+}
- return 0;
+static void iwl_pcie_set_continuous_reduce_power(struct iwl_trans *trans)
+{
+ struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
+ struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl =
+ &trans_pcie->prph_scratch->ctrl_cfg;
+
+ prph_sc_ctrl->reduce_power_cfg.base_addr =
+ cpu_to_le64(trans_pcie->reduced_tables_data.drams[0].physical);
+ prph_sc_ctrl->reduce_power_cfg.size =
+ cpu_to_le32(trans_pcie->reduced_tables_data.drams[0].size);
+}
+
+void
+iwl_trans_pcie_ctx_info_gen3_set_reduce_power(struct iwl_trans *trans,
+ const struct iwl_ucode_capabilities *capa)
+{
+ if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
+ return;
+
+ if (fw_has_capa(capa, IWL_UCODE_TLV_CAPA_FRAGMENTED_PNVM_IMG))
+ iwl_pcie_set_reduce_power_segments(trans);
+ else
+ iwl_pcie_set_continuous_reduce_power(trans);
}
diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info.c b/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info.c
index 74ce31fdf45e..5f55efe64bf5 100644
--- a/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info.c
+++ b/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
* Copyright (C) 2017 Intel Deutschland GmbH
- * Copyright (C) 2018-2021 Intel Corporation
+ * Copyright (C) 2018-2022 Intel Corporation
*/
#include "iwl-trans.h"
#include "iwl-fh.h"
@@ -38,9 +38,9 @@ static void *_iwl_pcie_ctxt_info_dma_alloc_coherent(struct iwl_trans *trans,
return result;
}
-static void *iwl_pcie_ctxt_info_dma_alloc_coherent(struct iwl_trans *trans,
- size_t size,
- dma_addr_t *phys)
+void *iwl_pcie_ctxt_info_dma_alloc_coherent(struct iwl_trans *trans,
+ size_t size,
+ dma_addr_t *phys)
{
return _iwl_pcie_ctxt_info_dma_alloc_coherent(trans, size, phys, 0);
}
diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/drv.c b/drivers/net/wireless/intel/iwlwifi/pcie/drv.c
index 79115eb1c285..73c1fb3c0c5e 100644
--- a/drivers/net/wireless/intel/iwlwifi/pcie/drv.c
+++ b/drivers/net/wireless/intel/iwlwifi/pcie/drv.c
@@ -484,17 +484,15 @@ static const struct pci_device_id iwl_hw_card_ids[] = {
{IWL_PCI_DEVICE(0x43F0, PCI_ANY_ID, iwl_qu_long_latency_trans_cfg)},
{IWL_PCI_DEVICE(0xA0F0, PCI_ANY_ID, iwl_qu_long_latency_trans_cfg)},
- {IWL_PCI_DEVICE(0x2720, PCI_ANY_ID, iwl_qnj_trans_cfg)},
-
{IWL_PCI_DEVICE(0x2723, PCI_ANY_ID, iwl_ax200_trans_cfg)},
/* So devices */
{IWL_PCI_DEVICE(0x2725, PCI_ANY_ID, iwl_so_trans_cfg)},
- {IWL_PCI_DEVICE(0x2726, PCI_ANY_ID, iwl_snj_trans_cfg)},
{IWL_PCI_DEVICE(0x7A70, PCI_ANY_ID, iwl_so_long_latency_imr_trans_cfg)},
{IWL_PCI_DEVICE(0x7AF0, PCI_ANY_ID, iwl_so_trans_cfg)},
{IWL_PCI_DEVICE(0x51F0, PCI_ANY_ID, iwl_so_long_latency_trans_cfg)},
{IWL_PCI_DEVICE(0x51F1, PCI_ANY_ID, iwl_so_long_latency_imr_trans_cfg)},
+ {IWL_PCI_DEVICE(0x51F1, PCI_ANY_ID, iwl_so_long_latency_trans_cfg)},
{IWL_PCI_DEVICE(0x54F0, PCI_ANY_ID, iwl_so_long_latency_trans_cfg)},
{IWL_PCI_DEVICE(0x7F70, PCI_ANY_ID, iwl_so_trans_cfg)},
@@ -507,6 +505,9 @@ static const struct pci_device_id iwl_hw_card_ids[] = {
{IWL_PCI_DEVICE(0x272b, PCI_ANY_ID, iwl_bz_trans_cfg)},
{IWL_PCI_DEVICE(0xA840, PCI_ANY_ID, iwl_bz_trans_cfg)},
{IWL_PCI_DEVICE(0x7740, PCI_ANY_ID, iwl_bz_trans_cfg)},
+
+/* Sc devices */
+ {IWL_PCI_DEVICE(0xE440, PCI_ANY_ID, iwl_sc_trans_cfg)},
#endif /* CONFIG_IWLMVM */
{0}
@@ -514,17 +515,16 @@ static const struct pci_device_id iwl_hw_card_ids[] = {
MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
#define _IWL_DEV_INFO(_device, _subdevice, _mac_type, _mac_step, _rf_type, \
- _rf_id, _rf_step, _no_160, _cores, _cdb, _jacket, _cfg, \
- _name) \
+ _rf_id, _rf_step, _no_160, _cores, _cdb, _cfg, _name) \
{ .device = (_device), .subdevice = (_subdevice), .cfg = &(_cfg), \
.name = _name, .mac_type = _mac_type, .rf_type = _rf_type, .rf_step = _rf_step, \
.no_160 = _no_160, .cores = _cores, .rf_id = _rf_id, \
- .mac_step = _mac_step, .cdb = _cdb, .jacket = _jacket }
+ .mac_step = _mac_step, .cdb = _cdb, .jacket = IWL_CFG_ANY }
#define IWL_DEV_INFO(_device, _subdevice, _cfg, _name) \
- _IWL_DEV_INFO(_device, _subdevice, IWL_CFG_ANY, IWL_CFG_ANY, \
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_ANY, \
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_ANY, _cfg, _name)
+ _IWL_DEV_INFO(_device, _subdevice, IWL_CFG_ANY, IWL_CFG_ANY, \
+ IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_ANY, \
+ IWL_CFG_ANY, _cfg, _name)
static const struct iwl_dev_info iwl_dev_info_table[] = {
#if IS_ENABLED(CONFIG_IWLMVM)
@@ -544,6 +544,7 @@ static const struct iwl_dev_info iwl_dev_info_table[] = {
IWL_DEV_INFO(0x51F0, 0x1551, iwl9560_2ac_cfg_soc, iwl9560_killer_1550i_160_name),
IWL_DEV_INFO(0x51F0, 0x1691, iwlax411_2ax_cfg_so_gf4_a0, iwl_ax411_killer_1690s_name),
IWL_DEV_INFO(0x51F0, 0x1692, iwlax411_2ax_cfg_so_gf4_a0, iwl_ax411_killer_1690i_name),
+ IWL_DEV_INFO(0x51F1, 0x1692, iwlax411_2ax_cfg_so_gf4_a0, iwl_ax411_killer_1690i_name),
IWL_DEV_INFO(0x54F0, 0x1691, iwlax411_2ax_cfg_so_gf4_a0, iwl_ax411_killer_1690s_name),
IWL_DEV_INFO(0x54F0, 0x1692, iwlax411_2ax_cfg_so_gf4_a0, iwl_ax411_killer_1690i_name),
IWL_DEV_INFO(0x7A70, 0x1691, iwlax411_2ax_cfg_so_gf4_a0, iwl_ax411_killer_1690s_name),
@@ -552,8 +553,8 @@ static const struct iwl_dev_info iwl_dev_info_table[] = {
IWL_DEV_INFO(0x7AF0, 0x1692, iwlax411_2ax_cfg_so_gf4_a0, iwl_ax411_killer_1690i_name),
IWL_DEV_INFO(0x271C, 0x0214, iwl9260_2ac_cfg, iwl9260_1_name),
- IWL_DEV_INFO(0x7E40, 0x1691, iwl_cfg_ma_a0_gf4_a0, iwl_ax411_killer_1690s_name),
- IWL_DEV_INFO(0x7E40, 0x1692, iwl_cfg_ma_a0_gf4_a0, iwl_ax411_killer_1690i_name),
+ IWL_DEV_INFO(0x7E40, 0x1691, iwl_cfg_ma, iwl_ax411_killer_1690s_name),
+ IWL_DEV_INFO(0x7E40, 0x1692, iwl_cfg_ma, iwl_ax411_killer_1690i_name),
/* AX200 */
IWL_DEV_INFO(0x2723, IWL_CFG_ANY, iwl_ax200_cfg_cc, iwl_ax200_name),
@@ -663,25 +664,13 @@ static const struct iwl_dev_info iwl_dev_info_table[] = {
IWL_DEV_INFO(0x7AF0, 0x1551, iwl9560_2ac_cfg_soc, iwl9560_killer_1550s_160_name),
IWL_DEV_INFO(0x7AF0, 0x1552, iwl9560_2ac_cfg_soc, iwl9560_killer_1550i_160_name),
- /* SnJ with HR */
- IWL_DEV_INFO(0x2725, 0x00B0, iwlax411_2ax_cfg_sosnj_gf4_a0, NULL),
- IWL_DEV_INFO(0x2726, 0x0090, iwlax211_cfg_snj_gf_a0, NULL),
- IWL_DEV_INFO(0x2726, 0x0098, iwlax211_cfg_snj_gf_a0, NULL),
- IWL_DEV_INFO(0x2726, 0x00B0, iwlax411_2ax_cfg_sosnj_gf4_a0, NULL),
- IWL_DEV_INFO(0x2726, 0x00B4, iwlax411_2ax_cfg_sosnj_gf4_a0, NULL),
- IWL_DEV_INFO(0x2726, 0x0510, iwlax211_cfg_snj_gf_a0, NULL),
- IWL_DEV_INFO(0x2726, 0x1651, iwl_cfg_snj_hr_b0, iwl_ax201_killer_1650s_name),
- IWL_DEV_INFO(0x2726, 0x1652, iwl_cfg_snj_hr_b0, iwl_ax201_killer_1650i_name),
- IWL_DEV_INFO(0x2726, 0x1691, iwlax411_2ax_cfg_sosnj_gf4_a0, iwl_ax411_killer_1690s_name),
- IWL_DEV_INFO(0x2726, 0x1692, iwlax411_2ax_cfg_sosnj_gf4_a0, iwl_ax411_killer_1690i_name),
- IWL_DEV_INFO(0x7F70, 0x1691, iwlax411_2ax_cfg_so_gf4_a0, iwl_ax411_killer_1690s_name),
- IWL_DEV_INFO(0x7F70, 0x1692, iwlax411_2ax_cfg_so_gf4_a0, iwl_ax411_killer_1690i_name),
-
/* SO with GF2 */
IWL_DEV_INFO(0x2726, 0x1671, iwlax211_2ax_cfg_so_gf_a0, iwl_ax211_killer_1675s_name),
IWL_DEV_INFO(0x2726, 0x1672, iwlax211_2ax_cfg_so_gf_a0, iwl_ax211_killer_1675i_name),
IWL_DEV_INFO(0x51F0, 0x1671, iwlax211_2ax_cfg_so_gf_a0, iwl_ax211_killer_1675s_name),
IWL_DEV_INFO(0x51F0, 0x1672, iwlax211_2ax_cfg_so_gf_a0, iwl_ax211_killer_1675i_name),
+ IWL_DEV_INFO(0x51F1, 0x1671, iwlax211_2ax_cfg_so_gf_a0, iwl_ax211_killer_1675s_name),
+ IWL_DEV_INFO(0x51F1, 0x1672, iwlax211_2ax_cfg_so_gf_a0, iwl_ax211_killer_1675i_name),
IWL_DEV_INFO(0x54F0, 0x1671, iwlax211_2ax_cfg_so_gf_a0, iwl_ax211_killer_1675s_name),
IWL_DEV_INFO(0x54F0, 0x1672, iwlax211_2ax_cfg_so_gf_a0, iwl_ax211_killer_1675i_name),
IWL_DEV_INFO(0x7A70, 0x1671, iwlax211_2ax_cfg_so_gf_a0, iwl_ax211_killer_1675s_name),
@@ -692,93 +681,72 @@ static const struct iwl_dev_info iwl_dev_info_table[] = {
IWL_DEV_INFO(0x7F70, 0x1672, iwlax211_2ax_cfg_so_gf_a0, iwl_ax211_killer_1675i_name),
/* MA with GF2 */
- IWL_DEV_INFO(0x7E40, 0x1671, iwl_cfg_ma_a0_gf_a0, iwl_ax211_killer_1675s_name),
- IWL_DEV_INFO(0x7E40, 0x1672, iwl_cfg_ma_a0_gf_a0, iwl_ax211_killer_1675i_name),
+ IWL_DEV_INFO(0x7E40, 0x1671, iwl_cfg_ma, iwl_ax211_killer_1675s_name),
+ IWL_DEV_INFO(0x7E40, 0x1672, iwl_cfg_ma, iwl_ax211_killer_1675i_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_PU, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwl9560_2ac_cfg_soc, iwl9461_160_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_PU, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwl9560_2ac_cfg_soc, iwl9461_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_PU, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwl9560_2ac_cfg_soc, iwl9462_160_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_PU, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwl9560_2ac_cfg_soc, iwl9462_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_PU, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwl9560_2ac_cfg_soc, iwl9560_160_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_PU, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwl9560_2ac_cfg_soc, iwl9560_name),
_IWL_DEV_INFO(0x2526, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_PNJ, IWL_CFG_ANY,
- IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl9260_2ac_cfg, iwl9461_160_name),
- _IWL_DEV_INFO(0x2526, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_PNJ, IWL_CFG_ANY,
- IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl9260_2ac_cfg, iwl9461_name),
- _IWL_DEV_INFO(0x2526, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_PNJ, IWL_CFG_ANY,
- IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl9260_2ac_cfg, iwl9462_160_name),
- _IWL_DEV_INFO(0x2526, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_PNJ, IWL_CFG_ANY,
- IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl9260_2ac_cfg, iwl9462_name),
-
- _IWL_DEV_INFO(0x2526, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_TH, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_TH, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_CORES_BT_GNSS, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_160, IWL_CFG_CORES_BT_GNSS, IWL_CFG_NO_CDB,
iwl9260_2ac_cfg, iwl9270_160_name),
_IWL_DEV_INFO(0x2526, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_TH, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_TH, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_CORES_BT_GNSS, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_NO_160, IWL_CFG_CORES_BT_GNSS, IWL_CFG_NO_CDB,
iwl9260_2ac_cfg, iwl9270_name),
_IWL_DEV_INFO(0x271B, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_TH, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_TH1, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwl9260_2ac_cfg, iwl9162_160_name),
_IWL_DEV_INFO(0x271B, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_TH, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_TH1, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwl9260_2ac_cfg, iwl9162_name),
_IWL_DEV_INFO(0x2526, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_TH, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_TH, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwl9260_2ac_cfg, iwl9260_160_name),
_IWL_DEV_INFO(0x2526, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_TH, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_TH, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwl9260_2ac_cfg, iwl9260_name),
/* Qu with Jf */
@@ -786,585 +754,341 @@ static const struct iwl_dev_info iwl_dev_info_table[] = {
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_QU, SILICON_B_STEP,
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwl9560_qu_b0_jf_b0_cfg, iwl9461_160_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_QU, SILICON_B_STEP,
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwl9560_qu_b0_jf_b0_cfg, iwl9461_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_QU, SILICON_B_STEP,
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwl9560_qu_b0_jf_b0_cfg, iwl9462_160_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_QU, SILICON_B_STEP,
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwl9560_qu_b0_jf_b0_cfg, iwl9462_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_QU, SILICON_B_STEP,
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwl9560_qu_b0_jf_b0_cfg, iwl9560_160_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_QU, SILICON_B_STEP,
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwl9560_qu_b0_jf_b0_cfg, iwl9560_name),
_IWL_DEV_INFO(IWL_CFG_ANY, 0x1551,
IWL_CFG_MAC_TYPE_QU, SILICON_B_STEP,
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwl9560_qu_b0_jf_b0_cfg, iwl9560_killer_1550s_name),
_IWL_DEV_INFO(IWL_CFG_ANY, 0x1552,
IWL_CFG_MAC_TYPE_QU, SILICON_B_STEP,
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwl9560_qu_b0_jf_b0_cfg, iwl9560_killer_1550i_name),
/* Qu C step */
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_QU, SILICON_C_STEP,
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwl9560_qu_c0_jf_b0_cfg, iwl9461_160_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_QU, SILICON_C_STEP,
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwl9560_qu_c0_jf_b0_cfg, iwl9461_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_QU, SILICON_C_STEP,
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwl9560_qu_c0_jf_b0_cfg, iwl9462_160_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_QU, SILICON_C_STEP,
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwl9560_qu_c0_jf_b0_cfg, iwl9462_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_QU, SILICON_C_STEP,
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwl9560_qu_c0_jf_b0_cfg, iwl9560_160_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_QU, SILICON_C_STEP,
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwl9560_qu_c0_jf_b0_cfg, iwl9560_name),
_IWL_DEV_INFO(IWL_CFG_ANY, 0x1551,
IWL_CFG_MAC_TYPE_QU, SILICON_C_STEP,
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwl9560_qu_c0_jf_b0_cfg, iwl9560_killer_1550s_name),
_IWL_DEV_INFO(IWL_CFG_ANY, 0x1552,
IWL_CFG_MAC_TYPE_QU, SILICON_C_STEP,
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwl9560_qu_c0_jf_b0_cfg, iwl9560_killer_1550i_name),
/* QuZ */
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_QUZ, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwl9560_quz_a0_jf_b0_cfg, iwl9461_160_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_QUZ, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwl9560_quz_a0_jf_b0_cfg, iwl9461_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_QUZ, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwl9560_quz_a0_jf_b0_cfg, iwl9462_160_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_QUZ, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwl9560_quz_a0_jf_b0_cfg, iwl9462_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_QUZ, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwl9560_quz_a0_jf_b0_cfg, iwl9560_160_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_QUZ, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwl9560_quz_a0_jf_b0_cfg, iwl9560_name),
_IWL_DEV_INFO(IWL_CFG_ANY, 0x1551,
IWL_CFG_MAC_TYPE_QUZ, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwl9560_quz_a0_jf_b0_cfg, iwl9560_killer_1550s_name),
_IWL_DEV_INFO(IWL_CFG_ANY, 0x1552,
IWL_CFG_MAC_TYPE_QUZ, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwl9560_quz_a0_jf_b0_cfg, iwl9560_killer_1550i_name),
- /* QnJ */
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_QNJ, IWL_CFG_ANY,
- IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl9560_qnj_b0_jf_b0_cfg, iwl9461_160_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_QNJ, IWL_CFG_ANY,
- IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl9560_qnj_b0_jf_b0_cfg, iwl9461_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_QNJ, IWL_CFG_ANY,
- IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl9560_qnj_b0_jf_b0_cfg, iwl9462_160_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_QNJ, IWL_CFG_ANY,
- IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl9560_qnj_b0_jf_b0_cfg, iwl9462_name),
-
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_QNJ, IWL_CFG_ANY,
- IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl9560_qnj_b0_jf_b0_cfg, iwl9560_160_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_QNJ, IWL_CFG_ANY,
- IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl9560_qnj_b0_jf_b0_cfg, iwl9560_name),
-
- _IWL_DEV_INFO(IWL_CFG_ANY, 0x1551,
- IWL_CFG_MAC_TYPE_QNJ, IWL_CFG_ANY,
- IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl9560_qnj_b0_jf_b0_cfg, iwl9560_killer_1550s_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, 0x1552,
- IWL_CFG_MAC_TYPE_QNJ, IWL_CFG_ANY,
- IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl9560_qnj_b0_jf_b0_cfg, iwl9560_killer_1550i_name),
-
/* Qu with Hr */
/* Qu B step */
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_QU, SILICON_B_STEP,
IWL_CFG_RF_TYPE_HR1, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB,
iwl_qu_b0_hr1_b0, iwl_ax101_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_QU, SILICON_B_STEP,
IWL_CFG_RF_TYPE_HR2, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_NO_160, IWL_CFG_ANY, IWL_CFG_NO_CDB,
iwl_qu_b0_hr_b0, iwl_ax203_name),
/* Qu C step */
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_QU, SILICON_C_STEP,
IWL_CFG_RF_TYPE_HR1, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB,
iwl_qu_c0_hr1_b0, iwl_ax101_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_QU, SILICON_C_STEP,
IWL_CFG_RF_TYPE_HR2, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_NO_160, IWL_CFG_ANY, IWL_CFG_NO_CDB,
iwl_qu_c0_hr_b0, iwl_ax203_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_QU, SILICON_C_STEP,
IWL_CFG_RF_TYPE_HR2, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_160, IWL_CFG_ANY, IWL_CFG_NO_CDB,
iwl_qu_c0_hr_b0, iwl_ax201_name),
/* QuZ */
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_QUZ, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_HR1, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB,
iwl_quz_a0_hr1_b0, iwl_ax101_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_QUZ, SILICON_B_STEP,
IWL_CFG_RF_TYPE_HR2, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_NO_160, IWL_CFG_ANY, IWL_CFG_NO_CDB,
iwl_cfg_quz_a0_hr_b0, iwl_ax203_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_QUZ, SILICON_B_STEP,
IWL_CFG_RF_TYPE_HR2, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_160, IWL_CFG_ANY, IWL_CFG_NO_CDB,
iwl_cfg_quz_a0_hr_b0, iwl_ax201_name),
-/* QnJ with Hr */
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_QNJ, IWL_CFG_ANY,
- IWL_CFG_RF_TYPE_HR2, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl_qnj_b0_hr_b0_cfg, iwl_ax201_name),
-
-/* SnJ with Jf */
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_SNJ, IWL_CFG_ANY,
- IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl_cfg_snj_a0_jf_b0, iwl9461_160_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_SNJ, IWL_CFG_ANY,
- IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl_cfg_snj_a0_jf_b0, iwl9461_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_SNJ, IWL_CFG_ANY,
- IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl_cfg_snj_a0_jf_b0, iwl9462_160_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_SNJ, IWL_CFG_ANY,
- IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl_cfg_snj_a0_jf_b0, iwl9462_name),
-
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_SNJ, IWL_CFG_ANY,
- IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl_cfg_snj_a0_jf_b0, iwl9560_160_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_SNJ, IWL_CFG_ANY,
- IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl_cfg_snj_a0_jf_b0, iwl9560_name),
-
-/* SnJ with Hr */
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_SNJ, IWL_CFG_ANY,
- IWL_CFG_RF_TYPE_HR1, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl_cfg_snj_hr_b0, iwl_ax101_name),
-
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_SNJ, IWL_CFG_ANY,
- IWL_CFG_RF_TYPE_HR2, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl_cfg_snj_hr_b0, iwl_ax201_name),
-
/* Ma */
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_MA, SILICON_A_STEP,
- IWL_CFG_RF_TYPE_HR2, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl_cfg_ma_a0_hr_b0, iwl_ax201_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_MA, SILICON_A_STEP,
- IWL_CFG_RF_TYPE_GF, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl_cfg_ma_a0_gf_a0, iwl_ax211_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_MA, SILICON_A_STEP,
- IWL_CFG_RF_TYPE_GF, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_CDB, IWL_CFG_ANY,
- iwl_cfg_ma_a0_gf4_a0, iwl_ax211_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_MA, SILICON_A_STEP,
- IWL_CFG_RF_TYPE_MR, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl_cfg_ma_a0_mr_a0, iwl_ax221_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_MA, SILICON_A_STEP,
- IWL_CFG_RF_TYPE_FM, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl_cfg_ma_a0_fm_a0, iwl_ax231_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_SNJ, IWL_CFG_ANY,
- IWL_CFG_RF_TYPE_MR, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl_cfg_snj_a0_mr_a0, iwl_ax221_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_MA, SILICON_B_STEP,
+ IWL_CFG_MAC_TYPE_MA, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_HR2, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl_cfg_ma_b0_hr_b0, iwl_ax201_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_MA, SILICON_B_STEP,
- IWL_CFG_RF_TYPE_GF, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl_cfg_ma_b0_gf_a0, iwl_ax211_name),
+ IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB,
+ iwl_cfg_ma, iwl_ax201_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_MA, SILICON_B_STEP,
+ IWL_CFG_MAC_TYPE_MA, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_GF, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_CDB, IWL_CFG_ANY,
- iwl_cfg_ma_b0_gf4_a0, iwl_ax211_name),
+ IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_ANY,
+ iwl_cfg_ma, iwl_ax211_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_MA, SILICON_B_STEP,
+ IWL_CFG_MAC_TYPE_MA, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_MR, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl_cfg_ma_b0_mr_a0, iwl_ax221_name),
+ IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB,
+ iwl_cfg_ma, iwl_ax221_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_MA, SILICON_B_STEP,
+ IWL_CFG_MAC_TYPE_MA, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_FM, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl_cfg_ma_b0_fm_a0, iwl_ax231_name),
+ IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB,
+ iwl_cfg_ma, iwl_ax231_name),
/* So with Hr */
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_SO, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_HR2, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_NO_160, IWL_CFG_ANY, IWL_CFG_NO_CDB,
iwl_cfg_so_a0_hr_a0, iwl_ax203_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_SO, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_HR1, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_NO_160, IWL_CFG_ANY, IWL_CFG_NO_CDB,
iwl_cfg_so_a0_hr_a0, iwl_ax101_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_SO, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_HR2, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_160, IWL_CFG_ANY, IWL_CFG_NO_CDB,
iwl_cfg_so_a0_hr_a0, iwl_ax201_name),
/* So-F with Hr */
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_SOF, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_HR2, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_NO_160, IWL_CFG_ANY, IWL_CFG_NO_CDB,
iwl_cfg_so_a0_hr_a0, iwl_ax203_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_SOF, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_HR1, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_NO_160, IWL_CFG_ANY, IWL_CFG_NO_CDB,
iwl_cfg_so_a0_hr_a0, iwl_ax101_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_SOF, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_HR2, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_160, IWL_CFG_ANY, IWL_CFG_NO_CDB,
iwl_cfg_so_a0_hr_a0, iwl_ax201_name),
/* So-F with Gf */
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_SOF, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_GF, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_160, IWL_CFG_ANY, IWL_CFG_NO_CDB,
iwlax211_2ax_cfg_so_gf_a0, iwl_ax211_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_SOF, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_GF, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_ANY, IWL_CFG_CDB, IWL_CFG_ANY,
+ IWL_CFG_160, IWL_CFG_ANY, IWL_CFG_CDB,
iwlax411_2ax_cfg_so_gf4_a0, iwl_ax411_name),
/* Bz */
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_BZ, IWL_CFG_ANY,
- IWL_CFG_RF_TYPE_HR1, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl_cfg_bz_a0_hr_a0, iwl_bz_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_BZ, IWL_CFG_ANY,
- IWL_CFG_RF_TYPE_HR2, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl_cfg_bz_a0_hr_b0, iwl_bz_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_BZ, IWL_CFG_ANY,
- IWL_CFG_RF_TYPE_GF, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl_cfg_bz_a0_gf_a0, iwl_bz_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_BZ, IWL_CFG_ANY,
- IWL_CFG_RF_TYPE_GF, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_CDB, IWL_CFG_ANY,
- iwl_cfg_bz_a0_gf4_a0, iwl_bz_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_BZ, IWL_CFG_ANY,
- IWL_CFG_RF_TYPE_MR, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl_cfg_bz_a0_mr_a0, iwl_bz_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_BZ, SILICON_A_STEP,
- IWL_CFG_RF_TYPE_FM, IWL_CFG_ANY, SILICON_A_STEP,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl_cfg_bz_a0_fm_a0, iwl_bz_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_BZ, IWL_CFG_ANY,
- IWL_CFG_RF_TYPE_FM, IWL_CFG_ANY, SILICON_A_STEP,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_CDB, IWL_CFG_NO_JACKET,
- iwl_cfg_bz_a0_fm4_a0, iwl_bz_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_BZ, IWL_CFG_ANY,
- IWL_CFG_RF_TYPE_FM, IWL_CFG_ANY, SILICON_B_STEP,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_IS_JACKET,
- iwl_cfg_bz_a0_fm_b0, iwl_bz_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_BZ, IWL_CFG_ANY,
- IWL_CFG_RF_TYPE_FM, IWL_CFG_ANY, SILICON_B_STEP,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_CDB, IWL_CFG_IS_JACKET,
- iwl_cfg_bz_a0_fm4_b0, iwl_bz_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_GL, SILICON_A_STEP,
- IWL_CFG_RF_TYPE_FM, IWL_CFG_ANY, SILICON_A_STEP,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_NO_JACKET,
- iwl_cfg_gl_a0_fm_a0, iwl_bz_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_GL, SILICON_B_STEP,
- IWL_CFG_RF_TYPE_FM, IWL_CFG_ANY, SILICON_B_STEP,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_NO_JACKET,
- iwl_cfg_gl_b0_fm_b0, iwl_bz_name),
-
-/* BZ Z step */
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_BZ, SILICON_Z_STEP,
- IWL_CFG_RF_TYPE_GF, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl_cfg_bz_z0_gf_a0, iwl_bz_name),
+ IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_ANY,
+ IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_ANY,
+ iwl_cfg_bz, iwl_bz_name),
-/* BNJ */
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_GL, SILICON_A_STEP,
- IWL_CFG_RF_TYPE_FM, IWL_CFG_ANY, SILICON_A_STEP,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_IS_JACKET,
- iwl_cfg_bnj_a0_fm_a0, iwl_bz_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_GL, SILICON_B_STEP,
- IWL_CFG_RF_TYPE_FM, IWL_CFG_ANY, SILICON_B_STEP,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_IS_JACKET,
- iwl_cfg_bnj_b0_fm_b0, iwl_bz_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_GL, SILICON_A_STEP,
- IWL_CFG_RF_TYPE_FM, IWL_CFG_ANY, SILICON_A_STEP,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_CDB, IWL_CFG_IS_JACKET,
- iwl_cfg_bnj_a0_fm4_a0, iwl_bz_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_GL, SILICON_B_STEP,
- IWL_CFG_RF_TYPE_FM, IWL_CFG_ANY, SILICON_B_STEP,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_CDB, IWL_CFG_IS_JACKET,
- iwl_cfg_bnj_b0_fm4_b0, iwl_bz_name),
+/* Ga (Gl) */
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_GL, IWL_CFG_ANY,
- IWL_CFG_RF_TYPE_GF, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_IS_JACKET,
- iwl_cfg_bnj_a0_gf_a0, iwl_bz_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_GL, SILICON_B_STEP,
- IWL_CFG_RF_TYPE_GF, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_IS_JACKET,
- iwl_cfg_bnj_b0_gf_a0, iwl_bz_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_GL, SILICON_A_STEP,
- IWL_CFG_RF_TYPE_GF, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_CDB, IWL_CFG_IS_JACKET,
- iwl_cfg_bnj_a0_gf4_a0, iwl_bz_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_GL, SILICON_B_STEP,
- IWL_CFG_RF_TYPE_GF, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_CDB, IWL_CFG_IS_JACKET,
- iwl_cfg_bnj_b0_gf4_a0, iwl_bz_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_GL, SILICON_A_STEP,
- IWL_CFG_RF_TYPE_HR1, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl_cfg_bnj_a0_hr_a0, iwl_bz_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_GL, SILICON_A_STEP,
- IWL_CFG_RF_TYPE_HR2, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl_cfg_bnj_a0_hr_b0, iwl_bz_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_GL, SILICON_B_STEP,
- IWL_CFG_RF_TYPE_HR1, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl_cfg_bnj_b0_hr_a0, iwl_bz_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_GL, SILICON_B_STEP,
- IWL_CFG_RF_TYPE_HR2, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl_cfg_bnj_b0_hr_b0, iwl_bz_name),
+ IWL_CFG_RF_TYPE_FM, IWL_CFG_ANY, IWL_CFG_ANY,
+ IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_NO_CDB,
+ iwl_cfg_gl, iwl_bz_name),
/* SoF with JF2 */
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_SOF, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwlax210_2ax_cfg_so_jf_b0, iwl9560_160_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_SOF, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwlax210_2ax_cfg_so_jf_b0, iwl9560_name),
/* SoF with JF */
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_SOF, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwlax210_2ax_cfg_so_jf_b0, iwl9461_160_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_SOF, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwlax210_2ax_cfg_so_jf_b0, iwl9462_160_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_SOF, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwlax210_2ax_cfg_so_jf_b0, iwl9461_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_SOF, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwlax210_2ax_cfg_so_jf_b0, iwl9462_name),
/* So with GF */
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_SO, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_GF, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_160, IWL_CFG_ANY, IWL_CFG_NO_CDB,
iwlax211_2ax_cfg_so_gf_a0, iwl_ax211_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_SO, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_GF, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_ANY, IWL_CFG_CDB, IWL_CFG_ANY,
+ IWL_CFG_160, IWL_CFG_ANY, IWL_CFG_CDB,
iwlax411_2ax_cfg_so_gf4_a0, iwl_ax411_name),
/* So with JF2 */
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_SO, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwlax210_2ax_cfg_so_jf_b0, iwl9560_160_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_SO, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_JF2, IWL_CFG_RF_ID_JF, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwlax210_2ax_cfg_so_jf_b0, iwl9560_name),
/* So with JF */
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_SO, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwlax210_2ax_cfg_so_jf_b0, iwl9461_160_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_SO, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwlax210_2ax_cfg_so_jf_b0, iwl9462_160_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_SO, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwlax210_2ax_cfg_so_jf_b0, iwl9461_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_SO, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_JF1, IWL_CFG_RF_ID_JF1_DIV, IWL_CFG_ANY,
- IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_NO_160, IWL_CFG_CORES_BT, IWL_CFG_NO_CDB,
iwlax210_2ax_cfg_so_jf_b0, iwl9462_name),
/* MsP */
@@ -1372,24 +1096,25 @@ static const struct iwl_dev_info iwl_dev_info_table[] = {
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_SO, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_MS, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_160, IWL_CFG_ANY, IWL_CFG_NO_CDB,
iwl_cfg_so_a0_ms_a0, iwl_ax204_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_SOF, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_MS, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
+ IWL_CFG_160, IWL_CFG_ANY, IWL_CFG_NO_CDB,
iwl_cfg_so_a0_ms_a0, iwl_ax204_name),
_IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
IWL_CFG_MAC_TYPE_MA, IWL_CFG_ANY,
IWL_CFG_RF_TYPE_MS, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl_cfg_ma_a0_ms_a0, iwl_ax204_name),
- _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_MAC_TYPE_SNJ, IWL_CFG_ANY,
- IWL_CFG_RF_TYPE_MS, IWL_CFG_ANY, IWL_CFG_ANY,
- IWL_CFG_160, IWL_CFG_ANY, IWL_CFG_NO_CDB, IWL_CFG_ANY,
- iwl_cfg_snj_a0_ms_a0, iwl_ax204_name)
+ IWL_CFG_160, IWL_CFG_ANY, IWL_CFG_NO_CDB,
+ iwl_cfg_ma, iwl_ax204_name),
+/* Sc */
+ _IWL_DEV_INFO(IWL_CFG_ANY, IWL_CFG_ANY,
+ IWL_CFG_MAC_TYPE_SC, IWL_CFG_ANY,
+ IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_ANY,
+ IWL_CFG_ANY, IWL_CFG_ANY, IWL_CFG_ANY,
+ iwl_cfg_sc, iwl_sc_name),
#endif /* CONFIG_IWLMVM */
};
@@ -1669,17 +1394,6 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
}
#if IS_ENABLED(CONFIG_IWLMVM)
-
- /*
- * Workaround for problematic SnJ device: sometimes when
- * certain RF modules are connected to SnJ, the device ID
- * changes to QnJ's ID. So we are using QnJ's trans_cfg until
- * here. But if we detect that the MAC type is actually SnJ,
- * we should switch to it here to avoid problems later.
- */
- if (CSR_HW_REV_TYPE(iwl_trans->hw_rev) == IWL_CFG_MAC_TYPE_SNJ)
- iwl_trans->trans_cfg = &iwl_so_trans_cfg;
-
/*
* special-case 7265D, it has the same PCI IDs.
*
@@ -1752,6 +1466,15 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
trans_pcie->num_rx_bufs = RX_QUEUE_SIZE;
}
+ if (!iwl_trans->trans_cfg->integrated) {
+ u16 link_status;
+
+ pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &link_status);
+
+ iwl_trans->pcie_link_speed =
+ u16_get_bits(link_status, PCI_EXP_LNKSTA_CLS);
+ }
+
ret = iwl_trans_init(iwl_trans);
if (ret)
goto out_free_trans;
diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/internal.h b/drivers/net/wireless/intel/iwlwifi/pcie/internal.h
index 69b95ad5993b..0adcf0e13e85 100644
--- a/drivers/net/wireless/intel/iwlwifi/pcie/internal.h
+++ b/drivers/net/wireless/intel/iwlwifi/pcie/internal.h
@@ -23,6 +23,7 @@
#include "iwl-op-mode.h"
#include "iwl-drv.h"
#include "queue/tx.h"
+#include "iwl-context-info.h"
/*
* RX related structures and functions
@@ -306,7 +307,9 @@ enum iwl_pcie_imr_status {
* @trans: pointer to the generic transport area
* @scd_base_addr: scheduler sram base address in SRAM
* @kw: keep warm address
- * @pnvm_dram: DRAM area that contains the PNVM data
+ * @pnvm_data: holds info about pnvm payloads allocated in DRAM
+ * @reduced_tables_data: holds info about power reduced tablse
+ * payloads allocated in DRAM
* @pci_dev: basic pci-network driver stuff
* @hw_base: pci hardware address support
* @ucode_write_complete: indicates that the ucode has been copied.
@@ -380,8 +383,9 @@ struct iwl_trans_pcie {
u32 scd_base_addr;
struct iwl_dma_ptr kw;
- struct iwl_dram_data pnvm_dram;
- struct iwl_dram_data reduce_power_dram;
+ /* pnvm data */
+ struct iwl_dram_regions pnvm_data;
+ struct iwl_dram_regions reduced_tables_data;
struct iwl_txq *txq_memory;
@@ -478,6 +482,8 @@ struct iwl_trans
const struct pci_device_id *ent,
const struct iwl_cfg_trans_params *cfg_trans);
void iwl_trans_pcie_free(struct iwl_trans *trans);
+void iwl_trans_pcie_free_pnvm_dram_regions(struct iwl_dram_regions *dram_regions,
+ struct device *dev);
bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans);
#define _iwl_trans_pcie_grab_nic_access(trans) \
diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/rx.c b/drivers/net/wireless/intel/iwlwifi/pcie/rx.c
index 0d7890f99a5f..f87b28edc267 100644
--- a/drivers/net/wireless/intel/iwlwifi/pcie/rx.c
+++ b/drivers/net/wireless/intel/iwlwifi/pcie/rx.c
@@ -699,17 +699,25 @@ static void iwl_pcie_free_rxq_dma(struct iwl_trans *trans,
rxq->used_bd = NULL;
}
+static size_t iwl_pcie_rb_stts_size(struct iwl_trans *trans)
+{
+ bool use_rx_td = (trans->trans_cfg->device_family >=
+ IWL_DEVICE_FAMILY_AX210);
+
+ if (use_rx_td)
+ return sizeof(__le16);
+
+ return sizeof(struct iwl_rb_status);
+}
+
static int iwl_pcie_alloc_rxq_dma(struct iwl_trans *trans,
struct iwl_rxq *rxq)
{
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
+ size_t rb_stts_size = iwl_pcie_rb_stts_size(trans);
struct device *dev = trans->dev;
int i;
int free_size;
- bool use_rx_td = (trans->trans_cfg->device_family >=
- IWL_DEVICE_FAMILY_AX210);
- size_t rb_stts_size = use_rx_td ? sizeof(__le16) :
- sizeof(struct iwl_rb_status);
spin_lock_init(&rxq->lock);
if (trans->trans_cfg->mq_rx_supported)
@@ -757,11 +765,9 @@ err:
static int iwl_pcie_rx_alloc(struct iwl_trans *trans)
{
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
+ size_t rb_stts_size = iwl_pcie_rb_stts_size(trans);
struct iwl_rb_allocator *rba = &trans_pcie->rba;
int i, ret;
- size_t rb_stts_size = trans->trans_cfg->device_family >=
- IWL_DEVICE_FAMILY_AX210 ?
- sizeof(__le16) : sizeof(struct iwl_rb_status);
if (WARN_ON(trans_pcie->rxq))
return -EINVAL;
@@ -1193,11 +1199,9 @@ int iwl_pcie_gen2_rx_init(struct iwl_trans *trans)
void iwl_pcie_rx_free(struct iwl_trans *trans)
{
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
+ size_t rb_stts_size = iwl_pcie_rb_stts_size(trans);
struct iwl_rb_allocator *rba = &trans_pcie->rba;
int i;
- size_t rb_stts_size = trans->trans_cfg->device_family >=
- IWL_DEVICE_FAMILY_AX210 ?
- sizeof(__le16) : sizeof(struct iwl_rb_status);
/*
* if rxq is NULL, it means that nothing has been allocated,
@@ -1636,14 +1640,14 @@ irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id)
struct msix_entry *entry = dev_id;
struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry);
struct iwl_trans *trans = trans_pcie->trans;
- struct iwl_rxq *rxq = &trans_pcie->rxq[entry->entry];
+ struct iwl_rxq *rxq;
trace_iwlwifi_dev_irq_msix(trans->dev, entry, false, 0, 0);
if (WARN_ON(entry->entry >= trans->num_rx_queues))
return IRQ_NONE;
- if (!rxq) {
+ if (!trans_pcie->rxq) {
if (net_ratelimit())
IWL_ERR(trans,
"[%d] Got MSI-X interrupt before we have Rx queues\n",
@@ -1651,6 +1655,7 @@ irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id)
return IRQ_NONE;
}
+ rxq = &trans_pcie->rxq[entry->entry];
lock_map_acquire(&trans->sync_cmd_lockdep_map);
IWL_DEBUG_ISR(trans, "[%d] Got interrupt\n", entry->entry);
@@ -1873,7 +1878,7 @@ irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)
return IRQ_NONE;
}
- if (unlikely(inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
+ if (unlikely(inta == 0xFFFFFFFF || iwl_trans_is_hw_error_value(inta))) {
/*
* Hardware disappeared. It might have
* already raised an interrupt.
diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/trans-gen2.c b/drivers/net/wireless/intel/iwlwifi/pcie/trans-gen2.c
index 73b395841ca8..fa46dad5fd68 100644
--- a/drivers/net/wireless/intel/iwlwifi/pcie/trans-gen2.c
+++ b/drivers/net/wireless/intel/iwlwifi/pcie/trans-gen2.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
* Copyright (C) 2017 Intel Deutschland GmbH
- * Copyright (C) 2018-2022 Intel Corporation
+ * Copyright (C) 2018-2023 Intel Corporation
*/
#include "iwl-trans.h"
#include "iwl-prph.h"
@@ -117,9 +117,14 @@ static void iwl_trans_pcie_fw_reset_handshake(struct iwl_trans *trans)
trans_pcie->fw_reset_state != FW_RESET_REQUESTED,
FW_RESET_TIMEOUT);
if (!ret || trans_pcie->fw_reset_state == FW_RESET_ERROR) {
- IWL_INFO(trans,
- "firmware didn't ACK the reset - continue anyway\n");
- iwl_trans_fw_error(trans, true);
+ u32 inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);
+
+ IWL_ERR(trans,
+ "timeout waiting for FW reset ACK (inta_hw=0x%x)\n",
+ inta_hw);
+
+ if (!(inta_hw & MSIX_HW_INT_CAUSES_REG_RESET_DONE))
+ iwl_trans_fw_error(trans, true);
}
trans_pcie->fw_reset_state = FW_RESET_IDLE;
diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/trans.c b/drivers/net/wireless/intel/iwlwifi/pcie/trans.c
index 59e14b398295..eacbbdbffb5e 100644
--- a/drivers/net/wireless/intel/iwlwifi/pcie/trans.c
+++ b/drivers/net/wireless/intel/iwlwifi/pcie/trans.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
- * Copyright (C) 2007-2015, 2018-2022 Intel Corporation
+ * Copyright (C) 2007-2015, 2018-2023 Intel Corporation
* Copyright (C) 2013-2015 Intel Mobile Communications GmbH
* Copyright (C) 2016-2017 Intel Deutschland GmbH
*/
@@ -131,13 +131,15 @@ static int iwl_trans_pcie_sw_reset(struct iwl_trans *trans,
bool retake_ownership)
{
/* Reset entire device - do controller reset (results in SHRD_HW_RST) */
- if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
+ if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
iwl_set_bit(trans, CSR_GP_CNTRL,
CSR_GP_CNTRL_REG_FLAG_SW_RESET);
- else
+ usleep_range(10000, 20000);
+ } else {
iwl_set_bit(trans, CSR_RESET,
CSR_RESET_REG_FLAG_SW_RESET);
- usleep_range(5000, 6000);
+ usleep_range(5000, 6000);
+ }
if (retake_ownership)
return iwl_pcie_prepare_card_hw(trans);
@@ -161,7 +163,7 @@ static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
}
static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans,
- u8 max_power, u8 min_power)
+ u8 max_power)
{
struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
void *block = NULL;
@@ -169,10 +171,13 @@ static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans,
u32 size = 0;
u8 power;
- if (fw_mon->size)
+ if (fw_mon->size) {
+ memset(fw_mon->block, 0, fw_mon->size);
return;
+ }
- for (power = max_power; power >= min_power; power--) {
+ /* need at least 2 KiB, so stop at 11 */
+ for (power = max_power; power >= 11; power--) {
size = BIT(power);
block = dma_alloc_coherent(trans->dev, size, &physical,
GFP_KERNEL | __GFP_NOWARN);
@@ -213,10 +218,7 @@ void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
max_power))
return;
- if (trans->dbg.fw_mon.size)
- return;
-
- iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11);
+ iwl_pcie_alloc_fw_monitor_block(trans, max_power);
}
static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
@@ -475,7 +477,7 @@ void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS,
CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS,
100);
- msleep(100);
+ usleep_range(10000, 20000);
} else {
iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
@@ -1786,7 +1788,7 @@ static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans)
}
hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG);
- if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) {
+ if (!iwl_trans_is_hw_error_value(hpm) && (hpm & PERSISTENCE_BIT)) {
u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot);
if (wprot_val & PREG_WFPM_ACCESS) {
@@ -1993,6 +1995,29 @@ static void iwl_trans_pcie_configure(struct iwl_trans *trans,
trans_pcie->fw_reset_handshake = trans_cfg->fw_reset_handshake;
}
+void iwl_trans_pcie_free_pnvm_dram_regions(struct iwl_dram_regions *dram_regions,
+ struct device *dev)
+{
+ u8 i;
+ struct iwl_dram_data *desc_dram = &dram_regions->prph_scratch_mem_desc;
+
+ /* free DRAM payloads */
+ for (i = 0; i < dram_regions->n_regions; i++) {
+ dma_free_coherent(dev, dram_regions->drams[i].size,
+ dram_regions->drams[i].block,
+ dram_regions->drams[i].physical);
+ }
+ dram_regions->n_regions = 0;
+
+ /* free DRAM addresses array */
+ if (desc_dram->block) {
+ dma_free_coherent(dev, desc_dram->size,
+ desc_dram->block,
+ desc_dram->physical);
+ }
+ memset(desc_dram, 0, sizeof(*desc_dram));
+}
+
void iwl_trans_pcie_free(struct iwl_trans *trans)
{
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
@@ -2025,16 +2050,10 @@ void iwl_trans_pcie_free(struct iwl_trans *trans)
iwl_pcie_free_fw_monitor(trans);
- if (trans_pcie->pnvm_dram.size)
- dma_free_coherent(trans->dev, trans_pcie->pnvm_dram.size,
- trans_pcie->pnvm_dram.block,
- trans_pcie->pnvm_dram.physical);
-
- if (trans_pcie->reduce_power_dram.size)
- dma_free_coherent(trans->dev,
- trans_pcie->reduce_power_dram.size,
- trans_pcie->reduce_power_dram.block,
- trans_pcie->reduce_power_dram.physical);
+ iwl_trans_pcie_free_pnvm_dram_regions(&trans_pcie->pnvm_data,
+ trans->dev);
+ iwl_trans_pcie_free_pnvm_dram_regions(&trans_pcie->reduced_tables_data,
+ trans->dev);
mutex_destroy(&trans_pcie->mutex);
iwl_trans_free(trans);
@@ -3534,7 +3553,9 @@ static const struct iwl_trans_ops trans_ops_pcie_gen2 = {
.txq_free = iwl_txq_dyn_free,
.wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
.rxq_dma_data = iwl_trans_pcie_rxq_dma_data,
+ .load_pnvm = iwl_trans_pcie_ctx_info_gen3_load_pnvm,
.set_pnvm = iwl_trans_pcie_ctx_info_gen3_set_pnvm,
+ .load_reduce_power = iwl_trans_pcie_ctx_info_gen3_load_reduce_power,
.set_reduce_power = iwl_trans_pcie_ctx_info_gen3_set_reduce_power,
#ifdef CONFIG_IWLWIFI_DEBUGFS
.debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/tx.c b/drivers/net/wireless/intel/iwlwifi/pcie/tx.c
index 3546c5269c3b..1337fa95f657 100644
--- a/drivers/net/wireless/intel/iwlwifi/pcie/tx.c
+++ b/drivers/net/wireless/intel/iwlwifi/pcie/tx.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
- * Copyright (C) 2003-2014, 2018-2021 Intel Corporation
+ * Copyright (C) 2003-2014, 2018-2021, 2023 Intel Corporation
* Copyright (C) 2013-2015 Intel Mobile Communications GmbH
* Copyright (C) 2016-2017 Intel Deutschland GmbH
*/
@@ -1547,6 +1547,9 @@ int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
/* there must be data left over for TB1 or this code must be changed */
BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_FIRST_TB_SIZE);
+ BUILD_BUG_ON(sizeof(struct iwl_cmd_header) +
+ offsetofend(struct iwl_tx_cmd, scratch) >
+ IWL_FIRST_TB_SIZE);
/* map the data for TB1 */
tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE;
diff --git a/drivers/net/wireless/intel/iwlwifi/queue/tx.c b/drivers/net/wireless/intel/iwlwifi/queue/tx.c
index d1c39c214f95..fbacbe9ada15 100644
--- a/drivers/net/wireless/intel/iwlwifi/queue/tx.c
+++ b/drivers/net/wireless/intel/iwlwifi/queue/tx.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
- * Copyright (C) 2020-2022 Intel Corporation
+ * Copyright (C) 2020-2023 Intel Corporation
*/
#include <net/tso.h>
#include <linux/tcp.h>
@@ -648,6 +648,13 @@ struct iwl_tfh_tfd *iwl_txq_gen2_build_tfd(struct iwl_trans *trans,
/* There must be data left over for TB1 or this code must be changed */
BUILD_BUG_ON(sizeof(struct iwl_tx_cmd_gen2) < IWL_FIRST_TB_SIZE);
+ BUILD_BUG_ON(sizeof(struct iwl_cmd_header) +
+ offsetofend(struct iwl_tx_cmd_gen2, dram_info) >
+ IWL_FIRST_TB_SIZE);
+ BUILD_BUG_ON(sizeof(struct iwl_tx_cmd_gen3) < IWL_FIRST_TB_SIZE);
+ BUILD_BUG_ON(sizeof(struct iwl_cmd_header) +
+ offsetofend(struct iwl_tx_cmd_gen3, dram_info) >
+ IWL_FIRST_TB_SIZE);
memset(tfd, 0, sizeof(*tfd));
@@ -1027,6 +1034,9 @@ int iwl_txq_alloc(struct iwl_trans *trans, struct iwl_txq *txq, int slots_num,
size_t tb0_buf_sz;
int i;
+ if (WARN_ONCE(slots_num <= 0, "Invalid slots num:%d\n", slots_num))
+ return -EINVAL;
+
if (WARN_ON(txq->entries || txq->tfds))
return -EINVAL;
diff --git a/drivers/net/wireless/intersil/hostap/Kconfig b/drivers/net/wireless/intersil/hostap/Kconfig
index c865d3156cea..2edff8efbcbb 100644
--- a/drivers/net/wireless/intersil/hostap/Kconfig
+++ b/drivers/net/wireless/intersil/hostap/Kconfig
@@ -56,7 +56,7 @@ config HOSTAP_FIRMWARE_NVRAM
config HOSTAP_PLX
tristate "Host AP driver for Prism2/2.5/3 in PLX9052 PCI adaptors"
- depends on PCI && HOSTAP
+ depends on PCI && HOSTAP && HAS_IOPORT
help
Host AP driver's version for Prism2/2.5/3 PC Cards in PLX9052 based
PCI adaptors.
diff --git a/drivers/net/wireless/intersil/hostap/hostap_ioctl.c b/drivers/net/wireless/intersil/hostap/hostap_ioctl.c
index 26287b129d18..b4adfc190ae8 100644
--- a/drivers/net/wireless/intersil/hostap/hostap_ioctl.c
+++ b/drivers/net/wireless/intersil/hostap/hostap_ioctl.c
@@ -3630,7 +3630,7 @@ static int prism2_ioctl_get_encryption(local_info_t *local,
param->u.crypt.key_len = 0;
param->u.crypt.idx = 0xff;
} else {
- strncpy(param->u.crypt.alg, (*crypt)->ops->name,
+ strscpy(param->u.crypt.alg, (*crypt)->ops->name,
HOSTAP_CRYPT_ALG_NAME_LEN);
param->u.crypt.key_len = 0;
diff --git a/drivers/net/wireless/intersil/orinoco/orinoco_cs.c b/drivers/net/wireless/intersil/orinoco/orinoco_cs.c
index a956f965a1e5..03bfd2482656 100644
--- a/drivers/net/wireless/intersil/orinoco/orinoco_cs.c
+++ b/drivers/net/wireless/intersil/orinoco/orinoco_cs.c
@@ -96,6 +96,7 @@ orinoco_cs_probe(struct pcmcia_device *link)
{
struct orinoco_private *priv;
struct orinoco_pccard *card;
+ int ret;
priv = alloc_orinocodev(sizeof(*card), &link->dev,
orinoco_cs_hard_reset, NULL);
@@ -107,8 +108,16 @@ orinoco_cs_probe(struct pcmcia_device *link)
card->p_dev = link;
link->priv = priv;
- return orinoco_cs_config(link);
-} /* orinoco_cs_attach */
+ ret = orinoco_cs_config(link);
+ if (ret)
+ goto err_free_orinocodev;
+
+ return 0;
+
+err_free_orinocodev:
+ free_orinocodev(priv);
+ return ret;
+}
static void orinoco_cs_detach(struct pcmcia_device *link)
{
diff --git a/drivers/net/wireless/intersil/orinoco/spectrum_cs.c b/drivers/net/wireless/intersil/orinoco/spectrum_cs.c
index 291ef97ed45e..841d623c621a 100644
--- a/drivers/net/wireless/intersil/orinoco/spectrum_cs.c
+++ b/drivers/net/wireless/intersil/orinoco/spectrum_cs.c
@@ -157,6 +157,7 @@ spectrum_cs_probe(struct pcmcia_device *link)
{
struct orinoco_private *priv;
struct orinoco_pccard *card;
+ int ret;
priv = alloc_orinocodev(sizeof(*card), &link->dev,
spectrum_cs_hard_reset,
@@ -169,8 +170,16 @@ spectrum_cs_probe(struct pcmcia_device *link)
card->p_dev = link;
link->priv = priv;
- return spectrum_cs_config(link);
-} /* spectrum_cs_attach */
+ ret = spectrum_cs_config(link);
+ if (ret)
+ goto err_free_orinocodev;
+
+ return 0;
+
+err_free_orinocodev:
+ free_orinocodev(priv);
+ return ret;
+}
static void spectrum_cs_detach(struct pcmcia_device *link)
{
diff --git a/drivers/net/wireless/intersil/p54/p54spi.c b/drivers/net/wireless/intersil/p54/p54spi.c
index 19152fd449ba..ce0179b8ab36 100644
--- a/drivers/net/wireless/intersil/p54/p54spi.c
+++ b/drivers/net/wireless/intersil/p54/p54spi.c
@@ -28,6 +28,7 @@
#endif /* CONFIG_P54_SPI_DEFAULT_EEPROM */
MODULE_FIRMWARE("3826.arm");
+MODULE_FIRMWARE("3826.eeprom");
/* gpios should be handled in board files and provided via platform data,
* but because it's currently impossible for p54spi to have a header file
diff --git a/drivers/net/wireless/legacy/ray_cs.c b/drivers/net/wireless/legacy/ray_cs.c
index 1f57a0055bbd..8ace797ce951 100644
--- a/drivers/net/wireless/legacy/ray_cs.c
+++ b/drivers/net/wireless/legacy/ray_cs.c
@@ -270,13 +270,14 @@ static int ray_probe(struct pcmcia_device *p_dev)
{
ray_dev_t *local;
struct net_device *dev;
+ int ret;
dev_dbg(&p_dev->dev, "ray_attach()\n");
/* Allocate space for private device-specific data */
dev = alloc_etherdev(sizeof(ray_dev_t));
if (!dev)
- goto fail_alloc_dev;
+ return -ENOMEM;
local = netdev_priv(dev);
local->finder = p_dev;
@@ -313,16 +314,20 @@ static int ray_probe(struct pcmcia_device *p_dev)
timer_setup(&local->timer, NULL, 0);
this_device = p_dev;
- return ray_config(p_dev);
+ ret = ray_config(p_dev);
+ if (ret)
+ goto err_free_dev;
-fail_alloc_dev:
- return -ENOMEM;
-} /* ray_attach */
+ return 0;
+
+err_free_dev:
+ free_netdev(dev);
+ return ret;
+}
static void ray_detach(struct pcmcia_device *link)
{
struct net_device *dev;
- ray_dev_t *local;
dev_dbg(&link->dev, "ray_detach\n");
@@ -331,9 +336,6 @@ static void ray_detach(struct pcmcia_device *link)
ray_release(link);
- local = netdev_priv(dev);
- del_timer_sync(&local->timer);
-
if (link->priv) {
unregister_netdev(dev);
free_netdev(dev);
@@ -625,7 +627,7 @@ static void init_startup_params(ray_dev_t *local)
local->sparm.b4.a_acting_as_ap_status = TYPE_STA;
if (essid != NULL)
- strncpy(local->sparm.b4.a_current_ess_id, essid, ESSID_SIZE);
+ strscpy(local->sparm.b4.a_current_ess_id, essid, ESSID_SIZE);
} /* init_startup_params */
/*===========================================================================*/
@@ -734,11 +736,14 @@ static void ray_release(struct pcmcia_device *link)
dev_dbg(&link->dev, "ray_release\n");
- del_timer(&local->timer);
+ del_timer_sync(&local->timer);
- iounmap(local->sram);
- iounmap(local->rmem);
- iounmap(local->amem);
+ if (local->sram)
+ iounmap(local->sram);
+ if (local->rmem)
+ iounmap(local->rmem);
+ if (local->amem)
+ iounmap(local->amem);
pcmcia_disable_device(link);
dev_dbg(&link->dev, "ray_release ending\n");
diff --git a/drivers/net/wireless/legacy/wl3501_cs.c b/drivers/net/wireless/legacy/wl3501_cs.c
index 7fb2f9513476..c45c4b7cbbaf 100644
--- a/drivers/net/wireless/legacy/wl3501_cs.c
+++ b/drivers/net/wireless/legacy/wl3501_cs.c
@@ -1862,6 +1862,7 @@ static int wl3501_probe(struct pcmcia_device *p_dev)
{
struct net_device *dev;
struct wl3501_card *this;
+ int ret;
/* The io structure describes IO port mapping */
p_dev->resource[0]->end = 16;
@@ -1873,8 +1874,7 @@ static int wl3501_probe(struct pcmcia_device *p_dev)
dev = alloc_etherdev(sizeof(struct wl3501_card));
if (!dev)
- goto out_link;
-
+ return -ENOMEM;
dev->netdev_ops = &wl3501_netdev_ops;
dev->watchdog_timeo = 5 * HZ;
@@ -1887,9 +1887,15 @@ static int wl3501_probe(struct pcmcia_device *p_dev)
netif_stop_queue(dev);
p_dev->priv = dev;
- return wl3501_config(p_dev);
-out_link:
- return -ENOMEM;
+ ret = wl3501_config(p_dev);
+ if (ret)
+ goto out_free_etherdev;
+
+ return 0;
+
+out_free_etherdev:
+ free_netdev(dev);
+ return ret;
}
static int wl3501_config(struct pcmcia_device *link)
diff --git a/drivers/net/wireless/marvell/mwifiex/11n.h b/drivers/net/wireless/marvell/mwifiex/11n.h
index 94b5e3e4ba08..7738ebe1fec1 100644
--- a/drivers/net/wireless/marvell/mwifiex/11n.h
+++ b/drivers/net/wireless/marvell/mwifiex/11n.h
@@ -102,14 +102,14 @@ static inline u8 mwifiex_space_avail_for_new_ba_stream(
{
struct mwifiex_private *priv;
u8 i;
- u32 ba_stream_num = 0, ba_stream_max;
+ size_t ba_stream_num = 0, ba_stream_max;
ba_stream_max = MWIFIEX_MAX_TX_BASTREAM_SUPPORTED;
for (i = 0; i < adapter->priv_num; i++) {
priv = adapter->priv[i];
if (priv)
- ba_stream_num += mwifiex_wmm_list_len(
+ ba_stream_num += list_count_nodes(
&priv->tx_ba_stream_tbl_ptr);
}
diff --git a/drivers/net/wireless/marvell/mwifiex/cfg80211.c b/drivers/net/wireless/marvell/mwifiex/cfg80211.c
index 5337ee4b6f10..813d1cbebe19 100644
--- a/drivers/net/wireless/marvell/mwifiex/cfg80211.c
+++ b/drivers/net/wireless/marvell/mwifiex/cfg80211.c
@@ -3753,10 +3753,10 @@ static int mwifiex_cfg80211_set_coalesce(struct wiphy *wiphy,
*/
static int
mwifiex_cfg80211_tdls_mgmt(struct wiphy *wiphy, struct net_device *dev,
- const u8 *peer, u8 action_code, u8 dialog_token,
- u16 status_code, u32 peer_capability,
- bool initiator, const u8 *extra_ies,
- size_t extra_ies_len)
+ const u8 *peer, int link_id, u8 action_code,
+ u8 dialog_token, u16 status_code,
+ u32 peer_capability, bool initiator,
+ const u8 *extra_ies, size_t extra_ies_len)
{
struct mwifiex_private *priv = mwifiex_netdev_get_priv(dev);
int ret;
diff --git a/drivers/net/wireless/marvell/mwifiex/scan.c b/drivers/net/wireless/marvell/mwifiex/scan.c
index ac8001c84293..644b1e134b01 100644
--- a/drivers/net/wireless/marvell/mwifiex/scan.c
+++ b/drivers/net/wireless/marvell/mwifiex/scan.c
@@ -2187,9 +2187,9 @@ int mwifiex_ret_802_11_scan(struct mwifiex_private *priv,
if (nd_config) {
adapter->nd_info =
- kzalloc(sizeof(struct cfg80211_wowlan_nd_match) +
- sizeof(struct cfg80211_wowlan_nd_match *) *
- scan_rsp->number_of_sets, GFP_ATOMIC);
+ kzalloc(struct_size(adapter->nd_info, matches,
+ scan_rsp->number_of_sets),
+ GFP_ATOMIC);
if (adapter->nd_info)
adapter->nd_info->n_matches = scan_rsp->number_of_sets;
diff --git a/drivers/net/wireless/marvell/mwifiex/wmm.h b/drivers/net/wireless/marvell/mwifiex/wmm.h
index 4f53a271dae0..d7659e688933 100644
--- a/drivers/net/wireless/marvell/mwifiex/wmm.h
+++ b/drivers/net/wireless/marvell/mwifiex/wmm.h
@@ -39,21 +39,6 @@ mwifiex_get_tid(struct mwifiex_ra_list_tbl *ptr)
}
/*
- * This function gets the length of a list.
- */
-static inline int
-mwifiex_wmm_list_len(struct list_head *head)
-{
- struct list_head *pos;
- int count = 0;
-
- list_for_each(pos, head)
- ++count;
-
- return count;
-}
-
-/*
* This function checks if a RA list is empty or not.
*/
static inline u8
diff --git a/drivers/net/wireless/mediatek/mt7601u/debugfs.c b/drivers/net/wireless/mediatek/mt7601u/debugfs.c
index 230b0e1061a7..dbddf256921b 100644
--- a/drivers/net/wireless/mediatek/mt7601u/debugfs.c
+++ b/drivers/net/wireless/mediatek/mt7601u/debugfs.c
@@ -127,8 +127,6 @@ void mt7601u_init_debugfs(struct mt7601u_dev *dev)
struct dentry *dir;
dir = debugfs_create_dir("mt7601u", dev->hw->wiphy->debugfsdir);
- if (!dir)
- return;
debugfs_create_u8("temperature", 0400, dir, &dev->raw_temp);
debugfs_create_u32("temp_mode", 0400, dir, &dev->temp_mode);
diff --git a/drivers/net/wireless/mediatek/mt7601u/trace.h b/drivers/net/wireless/mediatek/mt7601u/trace.h
index 5a6ba015085f..07696b672161 100644
--- a/drivers/net/wireless/mediatek/mt7601u/trace.h
+++ b/drivers/net/wireless/mediatek/mt7601u/trace.h
@@ -16,7 +16,7 @@
#define MAXNAME 32
#define DEV_ENTRY __array(char, wiphy_name, 32)
-#define DEV_ASSIGN strlcpy(__entry->wiphy_name, \
+#define DEV_ASSIGN strscpy(__entry->wiphy_name, \
wiphy_name(dev->hw->wiphy), MAXNAME)
#define DEV_PR_FMT "%s "
#define DEV_PR_ARG __entry->wiphy_name
diff --git a/drivers/net/wireless/microchip/wilc1000/hif.c b/drivers/net/wireless/microchip/wilc1000/hif.c
index 5adc69d5bcae..a28da5938481 100644
--- a/drivers/net/wireless/microchip/wilc1000/hif.c
+++ b/drivers/net/wireless/microchip/wilc1000/hif.c
@@ -485,6 +485,9 @@ void *wilc_parse_join_bss_param(struct cfg80211_bss *bss,
int rsn_ie_len = sizeof(struct element) + rsn_ie[1];
int offset = 8;
+ param->mode_802_11i = 2;
+ param->rsn_found = true;
+
/* extract RSN capabilities */
if (offset < rsn_ie_len) {
/* skip over pairwise suites */
@@ -494,11 +497,8 @@ void *wilc_parse_join_bss_param(struct cfg80211_bss *bss,
/* skip over authentication suites */
offset += (rsn_ie[offset] * 4) + 2;
- if (offset + 1 < rsn_ie_len) {
- param->mode_802_11i = 2;
- param->rsn_found = true;
+ if (offset + 1 < rsn_ie_len)
memcpy(param->rsn_cap, &rsn_ie[offset], 2);
- }
}
}
}
diff --git a/drivers/net/wireless/microchip/wilc1000/hif.h b/drivers/net/wireless/microchip/wilc1000/hif.h
index baa2881f4465..8e386db72e45 100644
--- a/drivers/net/wireless/microchip/wilc1000/hif.h
+++ b/drivers/net/wireless/microchip/wilc1000/hif.h
@@ -30,8 +30,6 @@ enum {
WILC_GET_CFG
};
-#define WILC_MAX_ASSOC_RESP_FRAME_SIZE 256
-
struct rf_info {
u8 link_speed;
s8 rssi;
diff --git a/drivers/net/wireless/microchip/wilc1000/wlan_cfg.h b/drivers/net/wireless/microchip/wilc1000/wlan_cfg.h
index 614c5673f232..7038b74f8e8f 100644
--- a/drivers/net/wireless/microchip/wilc1000/wlan_cfg.h
+++ b/drivers/net/wireless/microchip/wilc1000/wlan_cfg.h
@@ -30,7 +30,7 @@ struct wilc_cfg_str {
struct wilc_cfg_str_vals {
u8 mac_address[7];
u8 firmware_version[129];
- u8 assoc_rsp[256];
+ u8 assoc_rsp[WILC_MAX_ASSOC_RESP_FRAME_SIZE];
};
struct wilc_cfg {
diff --git a/drivers/net/wireless/microchip/wilc1000/wlan_if.h b/drivers/net/wireless/microchip/wilc1000/wlan_if.h
index df2f5a63bdf6..254a046e3b1b 100644
--- a/drivers/net/wireless/microchip/wilc1000/wlan_if.h
+++ b/drivers/net/wireless/microchip/wilc1000/wlan_if.h
@@ -10,6 +10,8 @@
#include <linux/netdevice.h>
#include "fw.h"
+#define WILC_MAX_ASSOC_RESP_FRAME_SIZE 512
+
/********************************************
*
* Wlan Configuration ID
diff --git a/drivers/net/wireless/ralink/rt2x00/rt2x00link.c b/drivers/net/wireless/ralink/rt2x00/rt2x00link.c
index b052c96347d6..6cf7e7c997c2 100644
--- a/drivers/net/wireless/ralink/rt2x00/rt2x00link.c
+++ b/drivers/net/wireless/ralink/rt2x00/rt2x00link.c
@@ -192,7 +192,7 @@ void rt2x00link_update_stats(struct rt2x00_dev *rt2x00dev,
return;
/*
- * Frame was received successfully since non-succesfull
+ * Frame was received successfully since non-successful
* frames would have been dropped by the hardware.
*/
qual->rx_success++;
diff --git a/drivers/net/wireless/realtek/rtl8xxxu/Kconfig b/drivers/net/wireless/realtek/rtl8xxxu/Kconfig
index 82bcaf44a65f..44ad94757a03 100644
--- a/drivers/net/wireless/realtek/rtl8xxxu/Kconfig
+++ b/drivers/net/wireless/realtek/rtl8xxxu/Kconfig
@@ -11,7 +11,8 @@ config RTL8XXXU
parts written to utilize the Linux mac80211 stack.
The driver is known to work with a number of RTL8723AU,
RL8188CU, RTL8188RU, RTL8191CU, RTL8192CU, RTL8723BU, RTL8192EU,
- RTL8188FU, RTL8188EU, and RTL8710BU (aka RTL8188GU) devices.
+ RTL8188FU, RTL8188EU, RTL8710BU (aka RTL8188GU), and RTL8192FU
+ devices.
This driver is under development and has a limited feature
set. In particular it does not yet support 40MHz channels
diff --git a/drivers/net/wireless/realtek/rtl8xxxu/Makefile b/drivers/net/wireless/realtek/rtl8xxxu/Makefile
index 1bf083c15dcd..fa466589eccb 100644
--- a/drivers/net/wireless/realtek/rtl8xxxu/Makefile
+++ b/drivers/net/wireless/realtek/rtl8xxxu/Makefile
@@ -3,4 +3,4 @@ obj-$(CONFIG_RTL8XXXU) += rtl8xxxu.o
rtl8xxxu-y := rtl8xxxu_core.o rtl8xxxu_8192e.o rtl8xxxu_8723b.o \
rtl8xxxu_8723a.o rtl8xxxu_8192c.o rtl8xxxu_8188f.o \
- rtl8xxxu_8188e.o rtl8xxxu_8710b.o
+ rtl8xxxu_8188e.o rtl8xxxu_8710b.o rtl8xxxu_8192f.o
diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h
index 808c1c895113..4695fb4e2d2d 100644
--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h
+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h
@@ -39,6 +39,7 @@
#define TX_TOTAL_PAGE_NUM_8188E 0xa9
#define TX_TOTAL_PAGE_NUM_8192E 0xf3
#define TX_TOTAL_PAGE_NUM_8723B 0xf7
+#define TX_TOTAL_PAGE_NUM_8192F 0xf7
/* (HPQ + LPQ + NPQ + PUBQ) = TX_TOTAL_PAGE_NUM */
#define TX_PAGE_NUM_PUBQ 0xe7
#define TX_PAGE_NUM_HI_PQ 0x0c
@@ -65,6 +66,11 @@
#define TX_PAGE_NUM_LO_PQ_8723B 0x02
#define TX_PAGE_NUM_NORM_PQ_8723B 0x02
+#define TX_PAGE_NUM_PUBQ_8192F 0xde
+#define TX_PAGE_NUM_HI_PQ_8192F 0x08
+#define TX_PAGE_NUM_LO_PQ_8192F 0x08
+#define TX_PAGE_NUM_NORM_PQ_8192F 0x08
+
#define RTL_FW_PAGE_SIZE 4096
#define RTL8XXXU_FIRMWARE_POLL_MAX 1000
@@ -81,6 +87,7 @@
#define EFUSE_REAL_CONTENT_LEN_8723A 512
#define EFUSE_BT_MAP_LEN_8723A 1024
#define EFUSE_MAX_WORD_UNIT 4
+#define EFUSE_UNDEFINED 0xff
enum rtl8xxxu_rtl_chip {
RTL8192S = 0x81920,
@@ -105,6 +112,7 @@ enum rtl8xxxu_rtl_chip {
RTL8195A = 0x8195a,
RTL8188F = 0x8188f,
RTL8710B = 0x8710b,
+ RTL8192F = 0x8192f,
};
enum rtl8xxxu_rx_type {
@@ -1246,6 +1254,40 @@ struct rtl8710bu_efuse {
u8 res7[0x3c];
} __packed;
+struct rtl8192fu_efuse {
+ __le16 rtl_id;
+ u8 res0[0x0e];
+ struct rtl8192eu_efuse_tx_power tx_power_index_A; /* 0x10 */
+ struct rtl8192eu_efuse_tx_power tx_power_index_B; /* 0x3a */
+ u8 res2[0x54];
+ u8 channel_plan; /* 0xb8 */
+ u8 xtal_k; /* 0xb9 */
+ u8 thermal_meter; /* 0xba */
+ u8 iqk_lck; /* 0xbb */
+ u8 pa_type; /* 0xbc */
+ u8 lna_type_2g; /* 0xbd */
+ u8 res3[1];
+ u8 lna_type_5g; /* 0xbf */
+ u8 res4[1];
+ u8 rf_board_option; /* 0xc1 */
+ u8 rf_feature_option; /* 0xc2 */
+ u8 rf_bt_setting; /* 0xc3 */
+ u8 eeprom_version; /* 0xc4 */
+ u8 eeprom_customer_id; /* 0xc5 */
+ u8 res5[3];
+ u8 rf_antenna_option; /* 0xc9 */
+ u8 rfe_option; /* 0xca */
+ u8 country_code; /* 0xcb */
+ u8 res6[52];
+ u8 vid[2]; /* 0x100 */
+ u8 pid[2]; /* 0x102 */
+ u8 usb_optional_function; /* 0x104 */
+ u8 res7[2];
+ u8 mac_addr[ETH_ALEN]; /* 0x107 */
+ u8 device_info[80]; /* 0x10d */
+ u8 res9[163];
+} __packed;
+
struct rtl8xxxu_reg8val {
u16 reg;
u8 val;
@@ -1280,6 +1322,9 @@ struct rtl8xxxu_rfregs {
#define H2C_JOIN_BSS_DISCONNECT 0
#define H2C_JOIN_BSS_CONNECT 1
+#define H2C_MACID_ROLE_STA 1
+#define H2C_MACID_ROLE_AP 2
+
/*
* H2C (firmware) commands differ between the older generation chips
* 8188[cr]u, 819[12]cu, and 8723au, and the more recent chips 8723bu,
@@ -1727,6 +1772,8 @@ struct rtl8xxxu_cfo_tracking {
};
#define RTL8XXXU_HW_LED_CONTROL 2
+#define RTL8XXXU_MAX_MAC_ID_NUM 128
+#define RTL8XXXU_BC_MC_MACID 0
struct rtl8xxxu_priv {
struct ieee80211_hw *hw;
@@ -1791,6 +1838,7 @@ struct rtl8xxxu_priv {
u32 cck_agc_report_type:1;
u32 cck_new_agc:1;
u8 default_crystal_cap;
+ u8 rfe_type;
unsigned int pipe_interrupt;
unsigned int pipe_in;
unsigned int pipe_out[TXDESC_QUEUE_MAX];
@@ -1831,6 +1879,7 @@ struct rtl8xxxu_priv {
struct rtl8188fu_efuse efuse8188fu;
struct rtl8188eu_efuse efuse8188eu;
struct rtl8710bu_efuse efuse8710bu;
+ struct rtl8192fu_efuse efuse8192fu;
} efuse_wifi;
u32 adda_backup[RTL8XXXU_ADDA_REGS];
u32 mac_backup[RTL8XXXU_MAC_REGS];
@@ -1851,6 +1900,7 @@ struct rtl8xxxu_priv {
struct delayed_work ra_watchdog;
struct work_struct c2hcmd_work;
struct sk_buff_head c2hcmd_queue;
+ struct work_struct update_beacon_work;
struct rtl8xxxu_btcoex bt_coex;
struct rtl8xxxu_ra_report ra_report;
struct rtl8xxxu_cfo_tracking cfo_tracking;
@@ -1859,6 +1909,14 @@ struct rtl8xxxu_priv {
bool led_registered;
char led_name[32];
struct led_classdev led_cdev;
+ DECLARE_BITMAP(mac_id_map, RTL8XXXU_MAX_MAC_ID_NUM);
+};
+
+struct rtl8xxxu_sta_info {
+ struct ieee80211_sta *sta;
+ struct ieee80211_vif *vif;
+
+ u8 macid;
};
struct rtl8xxxu_rx_urb {
@@ -1903,15 +1961,16 @@ struct rtl8xxxu_fileops {
void (*set_tx_power) (struct rtl8xxxu_priv *priv, int channel,
bool ht40);
void (*update_rate_mask) (struct rtl8xxxu_priv *priv,
- u32 ramask, u8 rateid, int sgi, int txbw_40mhz);
+ u32 ramask, u8 rateid, int sgi, int txbw_40mhz,
+ u8 macid);
void (*report_connect) (struct rtl8xxxu_priv *priv,
- u8 macid, bool connect);
+ u8 macid, u8 role, bool connect);
void (*report_rssi) (struct rtl8xxxu_priv *priv, u8 macid, u8 rssi);
void (*fill_txdesc) (struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
struct ieee80211_tx_info *tx_info,
struct rtl8xxxu_txdesc32 *tx_desc, bool sgi,
bool short_preamble, bool ampdu_enable,
- u32 rts_rate);
+ u32 rts_rate, u8 macid);
void (*set_crystal_cap) (struct rtl8xxxu_priv *priv, u8 crystal_cap);
s8 (*cck_rssi) (struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats);
int (*led_classdev_brightness_set) (struct led_classdev *led_cdev,
@@ -1929,6 +1988,9 @@ struct rtl8xxxu_fileops {
u8 init_reg_hmtfr:1;
u8 ampdu_max_time;
u8 ustime_tsf_edca;
+ u16 max_aggr_num;
+ u8 supports_ap:1;
+ u16 max_macid_num;
u32 adda_1t_init;
u32 adda_1t_path_on;
u32 adda_2t_path_on_a;
@@ -2015,6 +2077,7 @@ void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv);
void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv);
void rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv,
int channel, bool ht40);
+void rtl8188f_channel_to_group(int channel, int *group, int *cck_group);
void rtl8188f_set_tx_power(struct rtl8xxxu_priv *priv,
int channel, bool ht40);
void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw);
@@ -2022,13 +2085,13 @@ void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw);
void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv);
void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv);
void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
- u32 ramask, u8 rateid, int sgi, int txbw_40mhz);
+ u32 ramask, u8 rateid, int sgi, int txbw_40mhz, u8 macid);
void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv,
- u32 ramask, u8 rateid, int sgi, int txbw_40mhz);
+ u32 ramask, u8 rateid, int sgi, int txbw_40mhz, u8 macid);
void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv,
- u8 macid, bool connect);
+ u8 macid, u8 role, bool connect);
void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv,
- u8 macid, bool connect);
+ u8 macid, u8 role, bool connect);
void rtl8xxxu_gen1_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi);
void rtl8xxxu_gen2_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi);
void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv);
@@ -2057,17 +2120,17 @@ void rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
struct ieee80211_tx_info *tx_info,
struct rtl8xxxu_txdesc32 *tx_desc, bool sgi,
bool short_preamble, bool ampdu_enable,
- u32 rts_rate);
+ u32 rts_rate, u8 macid);
void rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
struct ieee80211_tx_info *tx_info,
struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi,
bool short_preamble, bool ampdu_enable,
- u32 rts_rate);
+ u32 rts_rate, u8 macid);
void rtl8xxxu_fill_txdesc_v3(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
struct ieee80211_tx_info *tx_info,
struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi,
bool short_preamble, bool ampdu_enable,
- u32 rts_rate);
+ u32 rts_rate, u8 macid);
void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv,
u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5);
void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv);
@@ -2079,6 +2142,7 @@ void rtl8xxxu_update_ra_report(struct rtl8xxxu_ra_report *rarpt,
void rtl8188e_ra_info_init_all(struct rtl8xxxu_ra_info *ra);
void rtl8188e_handle_ra_tx_report2(struct rtl8xxxu_priv *priv, struct sk_buff *skb);
+extern struct rtl8xxxu_fileops rtl8192fu_fops;
extern struct rtl8xxxu_fileops rtl8710bu_fops;
extern struct rtl8xxxu_fileops rtl8188fu_fops;
extern struct rtl8xxxu_fileops rtl8188eu_fops;
diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c
index 8986783ae8fa..6d0f975f891b 100644
--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c
+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c
@@ -1794,7 +1794,8 @@ static void rtl8188e_arfb_refresh(struct rtl8xxxu_ra_info *ra)
static void
rtl8188e_update_rate_mask(struct rtl8xxxu_priv *priv,
- u32 ramask, u8 rateid, int sgi, int txbw_40mhz)
+ u32 ramask, u8 rateid, int sgi, int txbw_40mhz,
+ u8 macid)
{
struct rtl8xxxu_ra_info *ra = &priv->ra_info;
diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188f.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188f.c
index dbdfd7787465..1e1c8fa194cb 100644
--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188f.c
+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188f.c
@@ -351,7 +351,7 @@ out:
return ret;
}
-static void rtl8188f_channel_to_group(int channel, int *group, int *cck_group)
+void rtl8188f_channel_to_group(int channel, int *group, int *cck_group)
{
if (channel < 3)
*group = 0;
@@ -654,7 +654,7 @@ static void rtl8188fu_config_channel(struct ieee80211_hw *hw)
rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RX_BB2, val32);
/* RC Corner */
- rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00140);
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x00140);
rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RX_G2, 0x01c6c);
}
@@ -854,8 +854,8 @@ static int rtl8188fu_iqk_path_a(struct rtl8xxxu_priv *priv, u32 *lok_result)
rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0x07ff7);
/* PA,PAD gain adjust */
- rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x980);
- rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x5102a);
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x980);
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, 0x5102a);
/* enter IQK mode */
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
@@ -886,7 +886,7 @@ static int rtl8188fu_iqk_path_a(struct rtl8xxxu_priv *priv, u32 *lok_result)
val32 &= 0x000000ff;
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
- rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180);
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x180);
/* save LOK result */
*lok_result = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_TXM_IDAC);
@@ -927,8 +927,8 @@ static int rtl8188fu_rx_iqk_path_a(struct rtl8xxxu_priv *priv, u32 lok_result)
rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf1173);
/* PA,PAD gain adjust */
- rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x980);
- rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x5102a);
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x980);
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, 0x5102a);
/*
* Enter IQK mode
@@ -967,7 +967,7 @@ static int rtl8188fu_rx_iqk_path_a(struct rtl8xxxu_priv *priv, u32 lok_result)
val32 &= 0x000000ff;
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
- rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180);
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x180);
/* Check failed */
reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
@@ -1002,8 +1002,8 @@ static int rtl8188fu_rx_iqk_path_a(struct rtl8xxxu_priv *priv, u32 lok_result)
/*
* PA, PAD setting
*/
- rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x980);
- rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x51000);
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x980);
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, 0x51000);
/*
* Enter IQK mode
@@ -1041,7 +1041,7 @@ static int rtl8188fu_rx_iqk_path_a(struct rtl8xxxu_priv *priv, u32 lok_result)
val32 &= 0x000000ff;
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
- rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180);
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x180);
/* reload LOK value */
rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXM_IDAC, lok_result);
@@ -1748,6 +1748,9 @@ struct rtl8xxxu_fileops rtl8188fu_fops = {
.init_reg_hmtfr = 1,
.ampdu_max_time = 0x70,
.ustime_tsf_edca = 0x28,
+ .max_aggr_num = 0x0c14,
+ .supports_ap = 1,
+ .max_macid_num = 16,
.adda_1t_init = 0x03c00014,
.adda_1t_path_on = 0x03c00014,
.trxff_boundary = 0x3f7f,
diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c
index fcc2926ea938..f673aa9ba15a 100644
--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c
+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c
@@ -716,7 +716,7 @@ static int rtl8192eu_iqk_path_a(struct rtl8xxxu_priv *priv)
* PA/PAD controlled by 0x0
*/
rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
- rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00180);
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x00180);
rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0);
rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000);
@@ -776,8 +776,8 @@ static int rtl8192eu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)
rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf1173);
/* PA/PAD control by 0x56, and set = 0x0 */
- rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00980);
- rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x511e0);
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x00980);
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, 0x511e0);
/* Enter IQK mode */
rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
@@ -816,7 +816,7 @@ static int rtl8192eu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)
} else {
/* PA/PAD controlled by 0x0 */
rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
- rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180);
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x180);
goto out;
}
@@ -838,8 +838,8 @@ static int rtl8192eu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)
rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf7ff2);
/* PA/PAD control by 0x56, and set = 0x0 */
- rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00980);
- rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x510e0);
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x00980);
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, 0x510e0);
/* Enter IQK mode */
rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
@@ -869,7 +869,7 @@ static int rtl8192eu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)
reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
- rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180);
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x180);
if (!(reg_eac & BIT(27)) &&
((reg_ea4 & 0x03ff0000) != 0x01320000) &&
@@ -889,7 +889,7 @@ static int rtl8192eu_iqk_path_b(struct rtl8xxxu_priv *priv)
int result = 0;
rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
- rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00180);
+ rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, 0x00180);
rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0);
rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x20000);
@@ -952,8 +952,8 @@ static int rtl8192eu_rx_iqk_path_b(struct rtl8xxxu_priv *priv)
rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf1173);
/* PA/PAD control by 0x56, and set = 0x0 */
- rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00980);
- rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_56, 0x511e0);
+ rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, 0x00980);
+ rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_PAD_TXG, 0x511e0);
/* Enter IQK mode */
rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
@@ -995,7 +995,7 @@ static int rtl8192eu_rx_iqk_path_b(struct rtl8xxxu_priv *priv)
* Vendor driver restores RF_A here which I believe is a bug
*/
rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
- rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x180);
+ rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, 0x180);
goto out;
}
@@ -1017,8 +1017,8 @@ static int rtl8192eu_rx_iqk_path_b(struct rtl8xxxu_priv *priv)
rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ff2);
/* PA/PAD control by 0x56, and set = 0x0 */
- rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00980);
- rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_56, 0x510e0);
+ rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, 0x00980);
+ rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_PAD_TXG, 0x510e0);
/* Enter IQK mode */
rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
@@ -1049,7 +1049,7 @@ static int rtl8192eu_rx_iqk_path_b(struct rtl8xxxu_priv *priv)
reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
- rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x180);
+ rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, 0x180);
if (!(reg_eac & BIT(30)) &&
((reg_ec4 & 0x03ff0000) != 0x01320000) &&
diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192f.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192f.c
new file mode 100644
index 000000000000..18dc5221a9c0
--- /dev/null
+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192f.c
@@ -0,0 +1,2090 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * RTL8XXXU mac80211 USB driver - 8192fu specific subdriver
+ *
+ * Copyright (c) 2023 Bitterblue Smith <rtl8821cerfe2@gmail.com>
+ *
+ * Portions copied from existing rtl8xxxu code:
+ * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
+ *
+ * Portions, notably calibration code:
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/errno.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/list.h>
+#include <linux/usb.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/ethtool.h>
+#include <linux/wireless.h>
+#include <linux/firmware.h>
+#include <linux/moduleparam.h>
+#include <net/mac80211.h>
+#include "rtl8xxxu.h"
+#include "rtl8xxxu_regs.h"
+
+static const struct rtl8xxxu_reg8val rtl8192f_mac_init_table[] = {
+ {0x420, 0x00}, {0x422, 0x78}, {0x428, 0x0a}, {0x429, 0x10},
+ {0x430, 0x00}, {0x431, 0x00}, {0x432, 0x00}, {0x433, 0x01},
+ {0x434, 0x04}, {0x435, 0x05}, {0x436, 0x07}, {0x437, 0x08},
+ {0x43c, 0x04}, {0x43d, 0x05}, {0x43e, 0x07}, {0x43f, 0x08},
+ {0x440, 0x5d}, {0x441, 0x01}, {0x442, 0x00}, {0x444, 0x10},
+ {0x445, 0xf0}, {0x446, 0x0e}, {0x447, 0x1f}, {0x448, 0x00},
+ {0x449, 0x00}, {0x44a, 0x00}, {0x44b, 0x00}, {0x44c, 0x10},
+ {0x44d, 0xf0}, {0x44e, 0x0e}, {0x44f, 0x00}, {0x450, 0x00},
+ {0x451, 0x00}, {0x452, 0x00}, {0x453, 0x00}, {0x480, 0x20},
+ {0x49c, 0x30}, {0x49d, 0xf0}, {0x49e, 0x03}, {0x49f, 0x3e},
+ {0x4a0, 0x00}, {0x4a1, 0x00}, {0x4a2, 0x00}, {0x4a3, 0x00},
+ {0x4a4, 0x15}, {0x4a5, 0xf0}, {0x4a6, 0x01}, {0x4a7, 0x0e},
+ {0x4a8, 0xe0}, {0x4a9, 0x00}, {0x4aa, 0x00}, {0x4ab, 0x00},
+ {0x2448, 0x06}, {0x244a, 0x06}, {0x244c, 0x06}, {0x244e, 0x06},
+ {0x4c7, 0x80}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4ca, 0x3c},
+ {0x4cb, 0x3c}, {0x4cc, 0xff}, {0x4cd, 0xff}, {0x4ce, 0x01},
+ {0x500, 0x26}, {0x501, 0xa2}, {0x502, 0x2f}, {0x503, 0x00},
+ {0x504, 0x28}, {0x505, 0xa3}, {0x506, 0x5e}, {0x507, 0x00},
+ {0x508, 0x2b}, {0x509, 0xa4}, {0x50a, 0x5e}, {0x50b, 0x00},
+ {0x50c, 0x4f}, {0x50d, 0xa4}, {0x50e, 0x00}, {0x50f, 0x00},
+ {0x512, 0x1c}, {0x514, 0x0a}, {0x516, 0x0a}, {0x521, 0x2f},
+ {0x525, 0x0f}, {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02},
+ {0x55c, 0x50}, {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e},
+ {0x609, 0x2a}, {0x60c, 0x18}, {0x620, 0xff}, {0x621, 0xff},
+ {0x622, 0xff}, {0x623, 0xff}, {0x624, 0xff}, {0x625, 0xff},
+ {0x626, 0xff}, {0x627, 0xff}, {0x638, 0x50}, {0x63c, 0x0a},
+ {0x63d, 0x0a}, {0x63e, 0x0e}, {0x63f, 0x0e}, {0x640, 0x40},
+ {0x642, 0x40}, {0x643, 0x00}, {0x652, 0xc8}, {0x66e, 0x05},
+ {0x6a0, 0xff}, {0x6a1, 0xff}, {0x6a2, 0xff}, {0x6a3, 0xff},
+ {0x6a4, 0xff}, {0x6a5, 0xff}, {0x6de, 0x84}, {0x700, 0x21},
+ {0x701, 0x43}, {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21},
+ {0x709, 0x43}, {0x70a, 0x65}, {0x70b, 0x87}, {0x718, 0x40},
+ {0x7c0, 0x38}, {0x7c2, 0x0f}, {0x7c3, 0xc0}, {0x073, 0x04},
+ {0x7c4, 0x77}, {0x024, 0xc7}, {0x7ec, 0xff}, {0x7ed, 0xff},
+ {0x7ee, 0xff}, {0x7ef, 0xff},
+ {0xffff, 0xff},
+};
+
+/* If updating the phy init table, also update rtl8192f_revise_cck_tx_psf(). */
+static const struct rtl8xxxu_reg32val rtl8192fu_phy_init_table[] = {
+ {0x800, 0x80006C00}, {0x804, 0x00004001},
+ {0x808, 0x0000FC00}, {0x80C, 0x00000000},
+ {0x810, 0x20200322}, {0x814, 0x020C3910},
+ {0x818, 0x00000385}, {0x81C, 0x07000000},
+ {0x820, 0x01000100}, {0x824, 0x00390204},
+ {0x828, 0x01000100}, {0x82C, 0x00390204},
+ {0x830, 0x25252525}, {0x834, 0x25252525},
+ {0x838, 0x25252525}, {0x83C, 0x25252525},
+ {0x840, 0x00010000}, {0x844, 0x00010000},
+ {0x848, 0x25252525}, {0x84C, 0x25252525},
+ {0x850, 0x00031FE0}, {0x854, 0x00000000},
+ {0x858, 0x569A569A}, {0x85C, 0x00400040},
+ {0x860, 0x66F60000}, {0x864, 0x061F0000},
+ {0x868, 0x25252525}, {0x86C, 0x25252525},
+ {0x870, 0x00000300}, {0x874, 0x04003400},
+ {0x878, 0x08080808}, {0x87C, 0x004F0201},
+ {0x880, 0xD8001402}, {0x884, 0xC0000120},
+ {0x888, 0x00000000}, {0x88C, 0xCC0000C0},
+ {0x890, 0x00000000}, {0x894, 0xFFFFFFFE},
+ {0x898, 0x40302010}, {0x89C, 0x00706050},
+ {0x900, 0x00000000}, {0x904, 0x00000023},
+ {0x908, 0x00000F00}, {0x90C, 0x81121313},
+ {0x910, 0x024C0000}, {0x914, 0x00000000},
+ {0x918, 0x00000000}, {0x91C, 0x00000000},
+ {0x920, 0x00000000}, {0x924, 0x00000000},
+ {0x928, 0x00000000}, {0x92C, 0x00000000},
+ {0x930, 0x88000000}, {0x934, 0x00000245},
+ {0x938, 0x00024588}, {0x93C, 0x00000000},
+ {0x940, 0x000007FF}, {0x944, 0x3F3F0000},
+ {0x948, 0x000001A3}, {0x94C, 0x20200008},
+ {0x950, 0x00338A98}, {0x954, 0x00000000},
+ {0x958, 0xCBCAD87A}, {0x95C, 0x06EB5735},
+ {0x960, 0x00000000}, {0x964, 0x00000000},
+ {0x968, 0x00000000}, {0x96C, 0x00000003},
+ {0x970, 0x00000000}, {0x974, 0x00000000},
+ {0x978, 0x00000000}, {0x97C, 0x10030000},
+ {0x980, 0x00000000}, {0x984, 0x02800280},
+ {0x988, 0x020A5704}, {0x98C, 0x1461C826},
+ {0x990, 0x0001469E}, {0x994, 0x008858D1},
+ {0x998, 0x400086C9}, {0x99C, 0x44444242},
+ {0x9A0, 0x00000000}, {0x9A4, 0x00000000},
+ {0x9A8, 0x00000000}, {0x9AC, 0xC0000000},
+ {0xA00, 0x00D047C8}, {0xA04, 0xC1FF0008},
+ {0xA08, 0x88838300}, {0xA0C, 0x2E20100F},
+ {0xA10, 0x9500BB78}, {0xA14, 0x11144028},
+ {0xA18, 0x00881117}, {0xA1C, 0x89140F00},
+ {0xA20, 0xE82C0001}, {0xA24, 0x64B80C1C},
+ {0xA28, 0x00158810}, {0xA2C, 0x10BB8000},
+ {0xA70, 0x00008000}, {0xA74, 0x80800100},
+ {0xA78, 0x000089F0}, {0xA7C, 0x225B0606},
+ {0xA80, 0x20803210}, {0xA84, 0x00200200},
+ {0xA88, 0x00000000}, {0xA8C, 0x00000000},
+ {0xA90, 0x00000000}, {0xA94, 0x00000000},
+ {0xA98, 0x00000000}, {0xA9C, 0x00460000},
+ {0xAA0, 0x00000000}, {0xAA4, 0x00020014},
+ {0xAA8, 0xBA0A0008}, {0xAAC, 0x01235667},
+ {0xAB0, 0x00000000}, {0xAB4, 0x00201402},
+ {0xAB8, 0x0000001C}, {0xABC, 0x0000F7FF},
+ {0xAC0, 0xD4C0A742}, {0xAC4, 0x00000000},
+ {0xAC8, 0x00000F08}, {0xACC, 0x00000F07},
+ {0xAD0, 0xA1052A10}, {0xAD4, 0x0D9D8452},
+ {0xAD8, 0x9E024024}, {0xADC, 0x0023C001},
+ {0xAE0, 0x00000391}, {0xB2C, 0x00000000},
+ {0xC00, 0x00000080}, {0xC04, 0x6F005433},
+ {0xC08, 0x000004E4}, {0xC0C, 0x6C6C6C6C},
+ {0xC10, 0x22000000}, {0xC14, 0x40000100},
+ {0xC18, 0x22000000}, {0xC1C, 0x40000100},
+ {0xC20, 0x00000000}, {0xC24, 0x40000100},
+ {0xC28, 0x00000000}, {0xC2C, 0x40000100},
+ {0xC30, 0x0401E809}, {0xC34, 0x30000020},
+ {0xC38, 0x23808080}, {0xC3C, 0x00002F44},
+ {0xC40, 0x1CF8403F}, {0xC44, 0x000100C7},
+ {0xC48, 0xEC060106}, {0xC4C, 0x007F037F},
+ {0xC50, 0x00E48020}, {0xC54, 0x04008017},
+ {0xC58, 0x00000020}, {0xC5C, 0x00708492},
+ {0xC60, 0x09280200}, {0xC64, 0x5014838B},
+ {0xC68, 0x47C006C7}, {0xC6C, 0x00000035},
+ {0xC70, 0x00001007}, {0xC74, 0x02815269},
+ {0xC78, 0x0FE07F1F}, {0xC7C, 0x00B91612},
+ {0xC80, 0x40000100}, {0xC84, 0x32000000},
+ {0xC88, 0x40000100}, {0xC8C, 0xA0240000},
+ {0xC90, 0x400E161E}, {0xC94, 0x00000F00},
+ {0xC98, 0x400E161E}, {0xC9C, 0x0000BDC8},
+ {0xCA0, 0x00000000}, {0xCA4, 0x098300A0},
+ {0xCA8, 0x00006B00}, {0xCAC, 0x87F45B1A},
+ {0xCB0, 0x0000002D}, {0xCB4, 0x00000000},
+ {0xCB8, 0x00000000}, {0xCBC, 0x28100200},
+ {0xCC0, 0x0010A3D0}, {0xCC4, 0x00000F7D},
+ {0xCC8, 0x00000000}, {0xCCC, 0x00000000},
+ {0xCD0, 0x593659AD}, {0xCD4, 0xB7545121},
+ {0xCD8, 0x64B22427}, {0xCDC, 0x00766932},
+ {0xCE0, 0x40201000}, {0xCE4, 0x00000000},
+ {0xCE8, 0x40E04407}, {0xCEC, 0x2E572000},
+ {0xD00, 0x000D8780}, {0xD04, 0x40020403},
+ {0xD08, 0x0002907F}, {0xD0C, 0x20010201},
+ {0xD10, 0x06288888}, {0xD14, 0x8888367B},
+ {0xD18, 0x7D806DB3}, {0xD1C, 0x0000007F},
+ {0xD20, 0x567600B8}, {0xD24, 0x0000018B},
+ {0xD28, 0xD513FF7D}, {0xD2C, 0xCC979975},
+ {0xD30, 0x04928000}, {0xD34, 0x40608000},
+ {0xD38, 0x88DDA000}, {0xD3C, 0x00026EE2},
+ {0xD50, 0x67270001}, {0xD54, 0x20500000},
+ {0xD58, 0x16161616}, {0xD5C, 0x71F20064},
+ {0xD60, 0x4653DA60}, {0xD64, 0x3E718A3C},
+ {0xD68, 0x00000183}, {0xD7C, 0x00000000},
+ {0xD80, 0x50000000}, {0xD84, 0x31310400},
+ {0xD88, 0xF5B50000}, {0xD8C, 0x00000000},
+ {0xD90, 0x00000000}, {0xD94, 0x44BBBB44},
+ {0xD98, 0x44BB44FF}, {0xD9C, 0x06033688},
+ {0xE00, 0x25252525}, {0xE04, 0x25252525},
+ {0xE08, 0x25252525}, {0xE10, 0x25252525},
+ {0xE14, 0x25252525}, {0xE18, 0x25252525},
+ {0xE1C, 0x25252525}, {0xE20, 0x00000000},
+ {0xE24, 0x00200000}, {0xE28, 0x00000000},
+ {0xE2C, 0x00000000}, {0xE30, 0x01007C00},
+ {0xE34, 0x01004800}, {0xE38, 0x10008C0F},
+ {0xE3C, 0x3C008C0F}, {0xE40, 0x01007C00},
+ {0xE44, 0x00000000}, {0xE48, 0x00000000},
+ {0xE4C, 0x00000000}, {0xE50, 0x01007C00},
+ {0xE54, 0x01004800}, {0xE58, 0x10008C0F},
+ {0xE5C, 0x3C008C0F}, {0xE60, 0x02100000},
+ {0xE64, 0xBBBBBBBB}, {0xE68, 0x40404040},
+ {0xE6C, 0x80408040}, {0xE70, 0x80408040},
+ {0xE74, 0x40404040}, {0xE78, 0x00400040},
+ {0xE7C, 0x40404040}, {0xE80, 0x00FF0000},
+ {0xE84, 0x80408040}, {0xE88, 0x40404040},
+ {0xE8C, 0x80408040}, {0xED0, 0x80408040},
+ {0xED4, 0x80408040}, {0xED8, 0x80408040},
+ {0xEDC, 0xC040C040}, {0xEE0, 0xC040C040},
+ {0xEE4, 0x00400040}, {0xEE8, 0xD8001402},
+ {0xEEC, 0xC0000120}, {0xEF0, 0x02000B09},
+ {0xEF4, 0x00000001}, {0xEF8, 0x00000000},
+ {0xF00, 0x00000300}, {0xF04, 0x00000002},
+ {0xF08, 0x00007D0C}, {0xF0C, 0x0000A907},
+ {0xF10, 0x00005807}, {0xF14, 0x00000003},
+ {0xF18, 0x07D003E8}, {0xF1C, 0x8000001F},
+ {0xF20, 0x00000000}, {0xF24, 0x00000000},
+ {0xF28, 0x00000000}, {0xF2C, 0x00000000},
+ {0xF30, 0x00000000}, {0xF34, 0x00000000},
+ {0xF38, 0x00030055}, {0xF3C, 0x0000003A},
+ {0xF40, 0x00000002}, {0xF44, 0x00000000},
+ {0xF48, 0x00000000}, {0xF4C, 0x0B000000},
+ {0xF50, 0x00000000},
+ {0xffff, 0xffffffff},
+};
+
+static const struct rtl8xxxu_reg32val rtl8192f_agc_table[] = {
+ {0xC78, 0x0FA0001F}, {0xC78, 0x0FA0011F},
+ {0xC78, 0x0FA0021F}, {0xC78, 0x0FA0031F},
+ {0xC78, 0x0FA0041F}, {0xC78, 0x0FA0051F},
+ {0xC78, 0x0F90061F}, {0xC78, 0x0F80071F},
+ {0xC78, 0x0F70081F}, {0xC78, 0x0F60091F},
+ {0xC78, 0x0F500A1F}, {0xC78, 0x0F400B1F},
+ {0xC78, 0x0F300C1F}, {0xC78, 0x0F200D1F},
+ {0xC78, 0x0F100E1F}, {0xC78, 0x0F000F1F},
+ {0xC78, 0x0EF0101F}, {0xC78, 0x0EE0111F},
+ {0xC78, 0x0ED0121F}, {0xC78, 0x0EC0131F},
+ {0xC78, 0x0EB0141F}, {0xC78, 0x0EA0151F},
+ {0xC78, 0x0E90161F}, {0xC78, 0x0E80171F},
+ {0xC78, 0x0E70181F}, {0xC78, 0x0E60191F},
+ {0xC78, 0x0E501A1F}, {0xC78, 0x0E401B1F},
+ {0xC78, 0x0E301C1F}, {0xC78, 0x0C701D1F},
+ {0xC78, 0x0C601E1F}, {0xC78, 0x0C501F1F},
+ {0xC78, 0x0C40201F}, {0xC78, 0x0C30211F},
+ {0xC78, 0x0A60221F}, {0xC78, 0x0A50231F},
+ {0xC78, 0x0A40241F}, {0xC78, 0x0A30251F},
+ {0xC78, 0x0860261F}, {0xC78, 0x0850271F},
+ {0xC78, 0x0840281F}, {0xC78, 0x0830291F},
+ {0xC78, 0x06702A1F}, {0xC78, 0x06602B1F},
+ {0xC78, 0x06502C1F}, {0xC78, 0x06402D1F},
+ {0xC78, 0x06302E1F}, {0xC78, 0x04602F1F},
+ {0xC78, 0x0450301F}, {0xC78, 0x0440311F},
+ {0xC78, 0x0430321F}, {0xC78, 0x0260331F},
+ {0xC78, 0x0250341F}, {0xC78, 0x0240351F},
+ {0xC78, 0x0230361F}, {0xC78, 0x0050371F},
+ {0xC78, 0x0040381F}, {0xC78, 0x0030391F},
+ {0xC78, 0x00203A1F}, {0xC78, 0x00103B1F},
+ {0xC78, 0x00003C1F}, {0xC78, 0x00003D1F},
+ {0xC78, 0x00003E1F}, {0xC78, 0x00003F1F},
+
+ {0xC78, 0x0FA0401F}, {0xC78, 0x0FA0411F},
+ {0xC78, 0x0FA0421F}, {0xC78, 0x0FA0431F},
+ {0xC78, 0x0F90441F}, {0xC78, 0x0F80451F},
+ {0xC78, 0x0F70461F}, {0xC78, 0x0F60471F},
+ {0xC78, 0x0F50481F}, {0xC78, 0x0F40491F},
+ {0xC78, 0x0F304A1F}, {0xC78, 0x0F204B1F},
+ {0xC78, 0x0F104C1F}, {0xC78, 0x0F004D1F},
+ {0xC78, 0x0EF04E1F}, {0xC78, 0x0EE04F1F},
+ {0xC78, 0x0ED0501F}, {0xC78, 0x0EC0511F},
+ {0xC78, 0x0EB0521F}, {0xC78, 0x0EA0531F},
+ {0xC78, 0x0E90541F}, {0xC78, 0x0E80551F},
+ {0xC78, 0x0E70561F}, {0xC78, 0x0E60571F},
+ {0xC78, 0x0E50581F}, {0xC78, 0x0E40591F},
+ {0xC78, 0x0E305A1F}, {0xC78, 0x0E205B1F},
+ {0xC78, 0x0E105C1F}, {0xC78, 0x0C505D1F},
+ {0xC78, 0x0C405E1F}, {0xC78, 0x0C305F1F},
+ {0xC78, 0x0C20601F}, {0xC78, 0x0C10611F},
+ {0xC78, 0x0A40621F}, {0xC78, 0x0A30631F},
+ {0xC78, 0x0A20641F}, {0xC78, 0x0A10651F},
+ {0xC78, 0x0840661F}, {0xC78, 0x0830671F},
+ {0xC78, 0x0820681F}, {0xC78, 0x0810691F},
+ {0xC78, 0x06506A1F}, {0xC78, 0x06406B1F},
+ {0xC78, 0x06306C1F}, {0xC78, 0x06206D1F},
+ {0xC78, 0x06106E1F}, {0xC78, 0x04406F1F},
+ {0xC78, 0x0430701F}, {0xC78, 0x0420711F},
+ {0xC78, 0x0410721F}, {0xC78, 0x0240731F},
+ {0xC78, 0x0230741F}, {0xC78, 0x0220751F},
+ {0xC78, 0x0210761F}, {0xC78, 0x0030771F},
+ {0xC78, 0x0020781F}, {0xC78, 0x0010791F},
+ {0xC78, 0x00007A1F}, {0xC78, 0x00007B1F},
+ {0xC78, 0x00007C1F}, {0xC78, 0x00007D1F},
+ {0xC78, 0x00007E1F}, {0xC78, 0x00007F1F},
+
+ {0xC78, 0x0FA0801F}, {0xC78, 0x0FA0811F},
+ {0xC78, 0x0FA0821F}, {0xC78, 0x0FA0831F},
+ {0xC78, 0x0FA0841F}, {0xC78, 0x0FA0851F},
+ {0xC78, 0x0F90861F}, {0xC78, 0x0F80871F},
+ {0xC78, 0x0F70881F}, {0xC78, 0x0F60891F},
+ {0xC78, 0x0F508A1F}, {0xC78, 0x0F408B1F},
+ {0xC78, 0x0F308C1F}, {0xC78, 0x0F208D1F},
+ {0xC78, 0x0F108E1F}, {0xC78, 0x0B908F1F},
+ {0xC78, 0x0B80901F}, {0xC78, 0x0B70911F},
+ {0xC78, 0x0B60921F}, {0xC78, 0x0B50931F},
+ {0xC78, 0x0B40941F}, {0xC78, 0x0B30951F},
+ {0xC78, 0x0B20961F}, {0xC78, 0x0B10971F},
+ {0xC78, 0x0B00981F}, {0xC78, 0x0AF0991F},
+ {0xC78, 0x0AE09A1F}, {0xC78, 0x0AD09B1F},
+ {0xC78, 0x0AC09C1F}, {0xC78, 0x0AB09D1F},
+ {0xC78, 0x0AA09E1F}, {0xC78, 0x0A909F1F},
+ {0xC78, 0x0A80A01F}, {0xC78, 0x0A70A11F},
+ {0xC78, 0x0A60A21F}, {0xC78, 0x0A50A31F},
+ {0xC78, 0x0A40A41F}, {0xC78, 0x0A30A51F},
+ {0xC78, 0x0A20A61F}, {0xC78, 0x0A10A71F},
+ {0xC78, 0x0A00A81F}, {0xC78, 0x0830A91F},
+ {0xC78, 0x0820AA1F}, {0xC78, 0x0810AB1F},
+ {0xC78, 0x0800AC1F}, {0xC78, 0x0640AD1F},
+ {0xC78, 0x0630AE1F}, {0xC78, 0x0620AF1F},
+ {0xC78, 0x0610B01F}, {0xC78, 0x0600B11F},
+ {0xC78, 0x0430B21F}, {0xC78, 0x0420B31F},
+ {0xC78, 0x0410B41F}, {0xC78, 0x0400B51F},
+ {0xC78, 0x0230B61F}, {0xC78, 0x0220B71F},
+ {0xC78, 0x0210B81F}, {0xC78, 0x0200B91F},
+ {0xC78, 0x0000BA1F}, {0xC78, 0x0000BB1F},
+ {0xC78, 0x0000BC1F}, {0xC78, 0x0000BD1F},
+ {0xC78, 0x0000BE1F}, {0xC78, 0x0000BF1F},
+ {0xC50, 0x00E48024}, {0xC50, 0x00E48020},
+ {0xffff, 0xffffffff}
+};
+
+static const struct rtl8xxxu_rfregval rtl8192fu_radioa_init_table[] = {
+ {0x00, 0x30000}, {0x18, 0x0FC07}, {0x81, 0x0FC00}, {0x82, 0x003C0},
+ {0x84, 0x00005}, {0x86, 0xA33A5}, {0x87, 0x00000}, {0x88, 0x58010},
+ {0x8E, 0x64540}, {0x8F, 0x282D8}, {0x51, 0x02C06}, {0x52, 0x7A007},
+ {0x53, 0x10061}, {0x54, 0x60018}, {0x55, 0x82020}, {0x56, 0x08CC6},
+ {0x57, 0x2CC00}, {0x58, 0x00000}, {0x5A, 0x50000}, {0x5B, 0x00006},
+ {0x5C, 0x00015}, {0x65, 0x20000}, {0x6E, 0x38319}, {0xF5, 0x43180},
+ {0xEF, 0x00002}, {0x33, 0x00301}, {0x33, 0x1032A}, {0x33, 0x2032A},
+ {0xEF, 0x00000}, {0xDF, 0x00002}, {0x35, 0x00000}, {0xF0, 0x08008},
+ {0xEF, 0x00800}, {0x33, 0x0040E}, {0x33, 0x04845}, {0x33, 0x08848},
+ {0x33, 0x0C84B}, {0x33, 0x1088A}, {0x33, 0x14C50}, {0x33, 0x18C8E},
+ {0x33, 0x1CCCD}, {0x33, 0x20CD0}, {0x33, 0x24CD3}, {0x33, 0x28CD6},
+ {0x33, 0x4002B}, {0x33, 0x4402E}, {0x33, 0x48846}, {0x33, 0x4C849},
+ {0x33, 0x50888}, {0x33, 0x54CC6}, {0x33, 0x58CC9}, {0x33, 0x5CCCC},
+ {0x33, 0x60CCF}, {0x33, 0x64CD2}, {0x33, 0x68CD5}, {0xEF, 0x00000},
+ {0xEF, 0x00400}, {0x33, 0x01C23}, {0x33, 0x05C23}, {0x33, 0x09D23},
+ {0x33, 0x0DD23}, {0x33, 0x11FA3}, {0x33, 0x15FA3}, {0x33, 0x19FAB},
+ {0x33, 0x1DFAB}, {0xEF, 0x00000}, {0xEF, 0x00200}, {0x33, 0x00030},
+ {0x33, 0x04030}, {0x33, 0x08030}, {0x33, 0x0C030}, {0x33, 0x10030},
+ {0x33, 0x14030}, {0x33, 0x18030}, {0x33, 0x1C030}, {0x33, 0x20030},
+ {0x33, 0x24030}, {0x33, 0x28030}, {0x33, 0x2C030}, {0x33, 0x30030},
+ {0x33, 0x34030}, {0x33, 0x38030}, {0x33, 0x3C030}, {0xEF, 0x00000},
+ {0xEF, 0x00100}, {0x33, 0x44001}, {0x33, 0x48001}, {0x33, 0x4C001},
+ {0x33, 0x50001}, {0x33, 0x54001}, {0x33, 0x58001}, {0x33, 0x5C001},
+ {0x33, 0x60001}, {0x33, 0x64001}, {0x33, 0x68001}, {0x33, 0x6C001},
+ {0x33, 0x70001}, {0x33, 0x74001}, {0x33, 0x78001}, {0x33, 0x04000},
+ {0x33, 0x08000}, {0x33, 0x0C000}, {0x33, 0x10000}, {0x33, 0x14000},
+ {0x33, 0x18001}, {0x33, 0x1C002}, {0x33, 0x20002}, {0x33, 0x24002},
+ {0x33, 0x28002}, {0x33, 0x2C002}, {0x33, 0x30002}, {0x33, 0x34002},
+ {0x33, 0x38002}, {0xEF, 0x00000}, {0x84, 0x00000}, {0xEF, 0x80010},
+ {0x30, 0x20000}, {0x31, 0x0006F}, {0x32, 0x01FF7}, {0xEF, 0x00000},
+ {0x84, 0x00000}, {0xEF, 0x80000}, {0x30, 0x30000}, {0x31, 0x0006F},
+ {0x32, 0xF1DF3}, {0xEF, 0x00000}, {0x84, 0x00000}, {0xEF, 0x80000},
+ {0x30, 0x38000}, {0x31, 0x0006F}, {0x32, 0xF1FF2}, {0xEF, 0x00000},
+ {0x1B, 0x746CE}, {0xEF, 0x20000}, {0x33, 0x30000}, {0x33, 0x38000},
+ {0x33, 0x70000}, {0x33, 0x78000}, {0xEF, 0x00000}, {0xDF, 0x08000},
+ {0xB0, 0xFFBCB}, {0xB3, 0x06000}, {0xB7, 0x18DF0}, {0xB8, 0x38FF0},
+ {0xC9, 0x00600}, {0xDF, 0x00000}, {0xB1, 0x33B8F}, {0xB2, 0x33762},
+ {0xB4, 0x141F0}, {0xB5, 0x14080}, {0xB6, 0x12425}, {0xB9, 0xC0008},
+ {0xBA, 0x40005}, {0xC2, 0x02C01}, {0xC3, 0x0000B}, {0xC4, 0x81E2F},
+ {0xC5, 0x5C28F}, {0xC6, 0x000A0}, {0xCA, 0x02000}, {0xFE, 0x00000},
+ {0x18, 0x08C07}, {0xFE, 0x00000}, {0xFE, 0x00000}, {0xFE, 0x00000},
+ {0x00, 0x31DD5},
+ {0xff, 0xffffffff}
+};
+
+static const struct rtl8xxxu_rfregval rtl8192fu_radiob_init_table[] = {
+ {0x00, 0x30000}, {0x81, 0x0FC00}, {0x82, 0x003C0}, {0x84, 0x00005},
+ {0x86, 0xA33A5}, {0x87, 0x00000}, {0x88, 0x58010}, {0x8E, 0x64540},
+ {0x8F, 0x282D8}, {0x51, 0x02C06}, {0x52, 0x7A007}, {0x53, 0x10061},
+ {0x54, 0x60018}, {0x55, 0x82020}, {0x56, 0x08CC6}, {0x57, 0x2CC00},
+ {0x58, 0x00000}, {0x5A, 0x50000}, {0x5B, 0x00006}, {0x5C, 0x00015},
+ {0x65, 0x20000}, {0x6E, 0x38319}, {0xF5, 0x43180}, {0xEF, 0x00002},
+ {0x33, 0x00301}, {0x33, 0x1032A}, {0x33, 0x2032A}, {0xEF, 0x00000},
+ {0xDF, 0x00002}, {0x35, 0x00000}, {0xF0, 0x08008}, {0xEF, 0x00800},
+ {0x33, 0x0040E}, {0x33, 0x04845}, {0x33, 0x08848}, {0x33, 0x0C84B},
+ {0x33, 0x1088A}, {0x33, 0x14CC8}, {0x33, 0x18CCB}, {0x33, 0x1CCCE},
+ {0x33, 0x20CD1}, {0x33, 0x24CD4}, {0x33, 0x28CD7}, {0x33, 0x4002B},
+ {0x33, 0x4402E}, {0x33, 0x48846}, {0x33, 0x4C849}, {0x33, 0x50888},
+ {0x33, 0x54CC6}, {0x33, 0x58CC9}, {0x33, 0x5CCCC}, {0x33, 0x60CCF},
+ {0x33, 0x64CD2}, {0x33, 0x68CD5}, {0xEF, 0x00000}, {0xEF, 0x00400},
+ {0x33, 0x01D23}, {0x33, 0x05D23}, {0x33, 0x09FA3}, {0x33, 0x0DFA3},
+ {0x33, 0x11D2B}, {0x33, 0x15D2B}, {0x33, 0x19FAB}, {0x33, 0x1DFAB},
+ {0xEF, 0x00000}, {0xEF, 0x00200}, {0x33, 0x00030}, {0x33, 0x04030},
+ {0x33, 0x08030}, {0x33, 0x0C030}, {0x33, 0x10030}, {0x33, 0x14030},
+ {0x33, 0x18030}, {0x33, 0x1C030}, {0x33, 0x20030}, {0x33, 0x24030},
+ {0x33, 0x28030}, {0x33, 0x2C030}, {0x33, 0x30030}, {0x33, 0x34030},
+ {0x33, 0x38030}, {0x33, 0x3C030}, {0xEF, 0x00000}, {0xEF, 0x00100},
+ {0x33, 0x44000}, {0x33, 0x48000}, {0x33, 0x4C000}, {0x33, 0x50000},
+ {0x33, 0x54000}, {0x33, 0x58000}, {0x33, 0x5C000}, {0x33, 0x60000},
+ {0x33, 0x64000}, {0x33, 0x68000}, {0x33, 0x6C000}, {0x33, 0x70000},
+ {0x33, 0x74000}, {0x33, 0x78000}, {0x33, 0x04000}, {0x33, 0x08000},
+ {0x33, 0x0C000}, {0x33, 0x10000}, {0x33, 0x14000}, {0x33, 0x18000},
+ {0x33, 0x1C001}, {0x33, 0x20001}, {0x33, 0x24001}, {0x33, 0x28001},
+ {0x33, 0x2C001}, {0x33, 0x30001}, {0x33, 0x34001}, {0x33, 0x38001},
+ {0xEF, 0x00000}, {0x84, 0x00000}, {0xEF, 0x80010}, {0x30, 0x20000},
+ {0x31, 0x0006F}, {0x32, 0x01FF7}, {0xEF, 0x00000}, {0x84, 0x00000},
+ {0xEF, 0x80000}, {0x30, 0x30000}, {0x31, 0x0006F}, {0x32, 0xF1DF3},
+ {0xEF, 0x00000}, {0x84, 0x00000}, {0xEF, 0x80000}, {0x30, 0x38000},
+ {0x31, 0x0006F}, {0x32, 0xF1FF2}, {0xEF, 0x00000}, {0x1B, 0x746CE},
+ {0xEF, 0x20000}, {0x33, 0x30000}, {0x33, 0x38000}, {0x33, 0x70000},
+ {0x33, 0x78000}, {0xEF, 0x00000}, {0x00, 0x31DD5},
+ {0xff, 0xffffffff}
+};
+
+static int rtl8192fu_identify_chip(struct rtl8xxxu_priv *priv)
+{
+ struct device *dev = &priv->udev->dev;
+ u32 sys_cfg, vendor, val32;
+
+ strscpy(priv->chip_name, "8192FU", sizeof(priv->chip_name));
+ priv->rtl_chip = RTL8192F;
+ priv->rf_paths = 2;
+ priv->rx_paths = 2;
+ priv->tx_paths = 2;
+
+ sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG);
+ priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK);
+ if (sys_cfg & SYS_CFG_TRP_VAUX_EN) {
+ dev_info(dev, "Unsupported test chip\n");
+ return -EOPNOTSUPP;
+ }
+
+ val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
+ priv->has_wifi = u32_get_bits(val32, MULTI_WIFI_FUNC_EN);
+ priv->has_bluetooth = u32_get_bits(val32, MULTI_BT_FUNC_EN);
+ priv->has_gps = u32_get_bits(val32, MULTI_GPS_FUNC_EN);
+ priv->is_multi_func = 1;
+
+ vendor = sys_cfg & SYS_CFG_VENDOR_ID;
+ rtl8xxxu_identify_vendor_1bit(priv, vendor);
+
+ val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
+ priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID);
+
+ return rtl8xxxu_config_endpoints_no_sie(priv);
+}
+
+static void
+rtl8192f_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
+{
+ u8 cck, ofdmbase, mcsbase;
+ u32 val32, ofdm, mcs;
+ int group, cck_group;
+
+ rtl8188f_channel_to_group(channel, &group, &cck_group);
+
+ cck = priv->cck_tx_power_index_A[cck_group];
+
+ rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_CCK1_MCS32, 0x00007f00, cck);
+
+ val32 = (cck << 16) | (cck << 8) | cck;
+ rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_CCK11_A_CCK2_11,
+ 0x7f7f7f00, val32);
+
+ ofdmbase = priv->ht40_1s_tx_power_index_A[group];
+ ofdmbase += priv->ofdm_tx_power_diff[RF_A].a;
+ ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24;
+
+ rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_RATE18_06, 0x7f7f7f7f, ofdm);
+ rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_RATE54_24, 0x7f7f7f7f, ofdm);
+
+ mcsbase = priv->ht40_1s_tx_power_index_A[group];
+ if (ht40)
+ mcsbase += priv->ht40_tx_power_diff[RF_A].a;
+ else
+ mcsbase += priv->ht20_tx_power_diff[RF_A].a;
+ mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24;
+
+ rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_MCS03_MCS00, 0x7f7f7f7f, mcs);
+ rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_MCS07_MCS04, 0x7f7f7f7f, mcs);
+ rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_MCS11_MCS08, 0x7f7f7f7f, mcs);
+ rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_MCS15_MCS12, 0x7f7f7f7f, mcs);
+
+ if (priv->tx_paths == 1)
+ return;
+
+ cck = priv->cck_tx_power_index_B[cck_group];
+
+ val32 = (cck << 16) | (cck << 8) | cck;
+ rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_CCK1_55_MCS32,
+ 0x7f7f7f00, val32);
+
+ rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_CCK11_A_CCK2_11,
+ 0x0000007f, cck);
+
+ ofdmbase = priv->ht40_1s_tx_power_index_B[group];
+ ofdmbase += priv->ofdm_tx_power_diff[RF_B].b;
+ ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24;
+
+ rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_RATE18_06, 0x7f7f7f7f, ofdm);
+ rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_RATE54_24, 0x7f7f7f7f, ofdm);
+
+ mcsbase = priv->ht40_1s_tx_power_index_B[group];
+ if (ht40)
+ mcsbase += priv->ht40_tx_power_diff[RF_B].b;
+ else
+ mcsbase += priv->ht20_tx_power_diff[RF_B].b;
+ mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24;
+
+ rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_MCS03_MCS00, 0x7f7f7f7f, mcs);
+ rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_MCS07_MCS04, 0x7f7f7f7f, mcs);
+ rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_MCS11_MCS08, 0x7f7f7f7f, mcs);
+ rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_MCS15_MCS12, 0x7f7f7f7f, mcs);
+}
+
+static void rtl8192f_revise_cck_tx_psf(struct rtl8xxxu_priv *priv, u8 channel)
+{
+ if (channel == 13) {
+ /* Special value for channel 13 */
+ rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xf8fe0001);
+ /* Normal values */
+ rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x64B80C1C);
+ rtl8xxxu_write16(priv, REG_CCK0_DEBUG_PORT, 0x8810);
+ rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x01235667);
+ } else if (channel == 14) {
+ /* Normal value */
+ rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xE82C0001);
+ /* Special values for channel 14 */
+ rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x0000B81C);
+ rtl8xxxu_write16(priv, REG_CCK0_DEBUG_PORT, 0x0000);
+ rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x00003667);
+ } else {
+ /* Restore normal values from the phy init table */
+ rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xE82C0001);
+ rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x64B80C1C);
+ rtl8xxxu_write16(priv, REG_CCK0_DEBUG_PORT, 0x8810);
+ rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x01235667);
+ }
+}
+
+static void rtl8192fu_config_kfree(struct rtl8xxxu_priv *priv, u8 channel)
+{
+ u8 bb_gain[3] = { EFUSE_UNDEFINED, EFUSE_UNDEFINED, EFUSE_UNDEFINED };
+ u8 bb_gain_path_mask[2] = { 0x0f, 0xf0 };
+ enum rtl8xxxu_rfpath rfpath;
+ u8 bb_gain_for_path;
+ u8 channel_idx = 0;
+
+ if (channel >= 1 && channel <= 3)
+ channel_idx = 0;
+ if (channel >= 4 && channel <= 9)
+ channel_idx = 1;
+ if (channel >= 10 && channel <= 14)
+ channel_idx = 2;
+
+ rtl8xxxu_read_efuse8(priv, 0x1ee, &bb_gain[1]);
+ rtl8xxxu_read_efuse8(priv, 0x1ec, &bb_gain[0]);
+ rtl8xxxu_read_efuse8(priv, 0x1ea, &bb_gain[2]);
+
+ if (bb_gain[1] == EFUSE_UNDEFINED)
+ return;
+
+ if (bb_gain[0] == EFUSE_UNDEFINED)
+ bb_gain[0] = bb_gain[1];
+
+ if (bb_gain[2] == EFUSE_UNDEFINED)
+ bb_gain[2] = bb_gain[1];
+
+ for (rfpath = RF_A; rfpath < priv->rf_paths; rfpath++) {
+ /* power_trim based on 55[19:14] */
+ rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_UNKNOWN_55,
+ BIT(5), 1);
+
+ /* enable 55[14] for 0.5db step */
+ rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_GAIN_CTRL,
+ BIT(18), 1);
+
+ /* enter power_trim debug mode */
+ rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_GAIN_CCA,
+ BIT(7), 1);
+
+ /* write enable */
+ rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_WE_LUT, BIT(7), 1);
+
+ bb_gain_for_path = (bb_gain[channel_idx] & bb_gain_path_mask[rfpath]);
+ bb_gain_for_path >>= __ffs(bb_gain_path_mask[rfpath]);
+
+ rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_TXPA_G3,
+ 0x70000, channel_idx * 2);
+ rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_TXPA_G3,
+ 0x3f, bb_gain_for_path);
+
+ rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_TXPA_G3,
+ 0x70000, channel_idx * 2 + 1);
+ rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_TXPA_G3,
+ 0x3f, bb_gain_for_path);
+
+ /* leave power_trim debug mode */
+ rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_GAIN_CCA,
+ BIT(7), 0);
+
+ /* write disable */
+ rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_WE_LUT, BIT(7), 0);
+ }
+}
+
+static void rtl8192fu_config_channel(struct ieee80211_hw *hw)
+{
+ struct rtl8xxxu_priv *priv = hw->priv;
+ bool ht40 = conf_is_ht40(&hw->conf);
+ u8 channel, subchannel = 0;
+ bool sec_ch_above = 0;
+ u32 val32;
+
+ channel = (u8)hw->conf.chandef.chan->hw_value;
+
+ if (conf_is_ht40_plus(&hw->conf)) {
+ sec_ch_above = 1;
+ channel += 2;
+ subchannel = 2;
+ } else if (conf_is_ht40_minus(&hw->conf)) {
+ sec_ch_above = 0;
+ channel -= 2;
+ subchannel = 1;
+ }
+
+ val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
+
+ rtl8192f_revise_cck_tx_psf(priv, channel);
+
+ /* Set channel */
+ val32 &= ~(BIT(18) | BIT(17)); /* select the 2.4G band(?) */
+ u32p_replace_bits(&val32, channel, 0xff);
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
+ if (priv->rf_paths > 1)
+ rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_MODE_AG, val32);
+
+ rtl8192fu_config_kfree(priv, channel);
+
+ rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel);
+
+ /* small BW */
+ rtl8xxxu_write32_clear(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, GENMASK(31, 30));
+
+ rtl8xxxu_write32_mask(priv, REG_FPGA0_RF_MODE, FPGA_RF_MODE, ht40);
+ rtl8xxxu_write32_mask(priv, REG_FPGA1_RF_MODE, FPGA_RF_MODE, ht40);
+
+ /* ADC clock = 160M */
+ rtl8xxxu_write32_mask(priv, REG_FPGA0_RF_MODE, GENMASK(10, 8), 4);
+
+ /* DAC clock = 80M */
+ rtl8xxxu_write32_mask(priv, REG_FPGA0_RF_MODE, BIT(13) | BIT(12), 2);
+
+ /* ADC buffer clk */
+ rtl8xxxu_write32_mask(priv, REG_ANTDIV_PARA1, BIT(27) | BIT(26), 2);
+
+ if (ht40)
+ /* Set Control channel to upper or lower. */
+ rtl8xxxu_write32_mask(priv, REG_CCK0_SYSTEM,
+ CCK0_SIDEBAND, !sec_ch_above);
+
+ /* Enable CCK */
+ rtl8xxxu_write32_set(priv, REG_FPGA0_RF_MODE, FPGA_RF_MODE_CCK);
+
+ /* RF TRX_BW */
+ val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
+ val32 &= ~MODE_AG_BW_MASK;
+ if (ht40)
+ val32 |= MODE_AG_BW_40MHZ_8723B;
+ else
+ val32 |= MODE_AG_BW_20MHZ_8723B;
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
+ if (priv->rf_paths > 1)
+ rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_MODE_AG, val32);
+
+ /* Modify RX DFIR parameters */
+ rtl8xxxu_write32_mask(priv, REG_TAP_UPD_97F, BIT(21) | BIT(20), 2);
+
+ rtl8xxxu_write32_mask(priv, REG_DOWNSAM_FACTOR, BIT(29) | BIT(28), 2);
+
+ if (ht40)
+ val32 = 0x3;
+ else
+ val32 = 0x1a3;
+ rtl8xxxu_write32_mask(priv, REG_RX_DFIR_MOD_97F, 0x1ff, val32);
+}
+
+static void rtl8192fu_init_aggregation(struct rtl8xxxu_priv *priv)
+{
+ u32 agg_rx;
+ u8 agg_ctrl;
+
+ /* RX aggregation */
+ agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL);
+ agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN;
+
+ agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH);
+ agg_rx &= ~RXDMA_USB_AGG_ENABLE;
+ agg_rx &= ~0xFF0F; /* reset agg size and timeout */
+
+ rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
+ rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx);
+}
+
+static int rtl8192fu_parse_efuse(struct rtl8xxxu_priv *priv)
+{
+ struct rtl8192fu_efuse *efuse = &priv->efuse_wifi.efuse8192fu;
+ int i;
+
+ if (efuse->rtl_id != cpu_to_le16(0x8129))
+ return -EINVAL;
+
+ ether_addr_copy(priv->mac_addr, efuse->mac_addr);
+
+ memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base,
+ sizeof(efuse->tx_power_index_A.cck_base));
+ memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base,
+ sizeof(efuse->tx_power_index_B.cck_base));
+
+ memcpy(priv->ht40_1s_tx_power_index_A,
+ efuse->tx_power_index_A.ht40_base,
+ sizeof(efuse->tx_power_index_A.ht40_base));
+ memcpy(priv->ht40_1s_tx_power_index_B,
+ efuse->tx_power_index_B.ht40_base,
+ sizeof(efuse->tx_power_index_B.ht40_base));
+
+ priv->ht20_tx_power_diff[0].a =
+ efuse->tx_power_index_A.ht20_ofdm_1s_diff.b;
+ priv->ht20_tx_power_diff[0].b =
+ efuse->tx_power_index_B.ht20_ofdm_1s_diff.b;
+
+ priv->ht40_tx_power_diff[0].a = 0;
+ priv->ht40_tx_power_diff[0].b = 0;
+
+ for (i = 1; i < RTL8723B_TX_COUNT; i++) {
+ priv->ofdm_tx_power_diff[i].a =
+ efuse->tx_power_index_A.pwr_diff[i - 1].ofdm;
+ priv->ofdm_tx_power_diff[i].b =
+ efuse->tx_power_index_B.pwr_diff[i - 1].ofdm;
+
+ priv->ht20_tx_power_diff[i].a =
+ efuse->tx_power_index_A.pwr_diff[i - 1].ht20;
+ priv->ht20_tx_power_diff[i].b =
+ efuse->tx_power_index_B.pwr_diff[i - 1].ht20;
+
+ priv->ht40_tx_power_diff[i].a =
+ efuse->tx_power_index_A.pwr_diff[i - 1].ht40;
+ priv->ht40_tx_power_diff[i].b =
+ efuse->tx_power_index_B.pwr_diff[i - 1].ht40;
+ }
+
+ priv->default_crystal_cap = efuse->xtal_k & 0x3f;
+
+ priv->rfe_type = efuse->rfe_option & 0x1f;
+
+ if (priv->rfe_type != 5 && priv->rfe_type != 1)
+ dev_warn(&priv->udev->dev,
+ "%s: RFE type %d was not tested. Please send an email to linux-wireless@vger.kernel.org about this.\n",
+ __func__, priv->rfe_type);
+
+ return 0;
+}
+
+static int rtl8192fu_load_firmware(struct rtl8xxxu_priv *priv)
+{
+ return rtl8xxxu_load_firmware(priv, "rtlwifi/rtl8192fufw.bin");
+}
+
+static void rtl8192fu_init_phy_bb(struct rtl8xxxu_priv *priv)
+{
+ /* Enable BB and RF */
+ rtl8xxxu_write16_set(priv, REG_SYS_FUNC,
+ SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN);
+
+ rtl8xxxu_write8(priv, REG_RF_CTRL, RF_ENABLE | RF_RSTB | RF_SDMRSTB);
+
+ /* To Fix MAC loopback mode fail. */
+ rtl8xxxu_write8(priv, REG_LDOHCI12_CTRL, 0xf);
+ rtl8xxxu_write8(priv, REG_SYS_SWR_CTRL2 + 1, 0xe9);
+
+ rtl8xxxu_init_phy_regs(priv, rtl8192fu_phy_init_table);
+
+ rtl8xxxu_init_phy_regs(priv, rtl8192f_agc_table);
+}
+
+static int rtl8192fu_init_phy_rf(struct rtl8xxxu_priv *priv)
+{
+ int ret;
+
+ ret = rtl8xxxu_init_phy_rf(priv, rtl8192fu_radioa_init_table, RF_A);
+ if (ret)
+ return ret;
+
+ return rtl8xxxu_init_phy_rf(priv, rtl8192fu_radiob_init_table, RF_B);
+}
+
+static void rtl8192f_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
+{
+ u32 backup_mask = BIT(31) | BIT(30);
+ u32 backup;
+ u32 val32;
+
+ /* Aries's NarrowBand */
+ val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);
+ backup = u32_get_bits(val32, backup_mask);
+
+ u32p_replace_bits(&val32, 0, backup_mask);
+ rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32);
+
+ rtl8188f_phy_lc_calibrate(priv);
+
+ /* Aries's NarrowBand */
+ val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);
+ u32p_replace_bits(&val32, backup, backup_mask);
+ rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32);
+
+ /* reset OFDM state */
+ rtl8xxxu_write32_clear(priv, REG_FPGA0_RF_MODE, FPGA_RF_MODE_OFDM);
+ rtl8xxxu_write32_set(priv, REG_FPGA0_RF_MODE, FPGA_RF_MODE_OFDM);
+}
+
+static int rtl8192fu_iqk_path_a(struct rtl8xxxu_priv *priv)
+{
+ u32 reg_eac, reg_e94, reg_e9c, val32;
+ u32 rf_0x58_i, rf_0x58_q;
+ u8 rfe = priv->rfe_type;
+ int result = 0;
+ int ktime, i;
+
+ /* Leave IQK mode */
+ rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);
+
+ rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0);
+ rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44ffbb44);
+ rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00400040);
+ rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005403);
+ rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000804e4);
+ rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400);
+ rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
+
+ rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(4), 1);
+ rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(11), 1);
+ if (rfe == 7 || rfe == 8 || rfe == 9 || rfe == 12)
+ val32 = 0x30;
+ else
+ val32 = 0xe9;
+ rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_PAD_TXG, 0x003ff, val32);
+
+ rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000);
+
+ /* path-A IQK setting */
+ rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
+ rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
+ rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
+ rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
+
+ rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x8214000f);
+ rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28140000);
+
+ rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
+ rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
+
+ /* LO calibration setting */
+ rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00e62911);
+
+ /* One shot, path A LOK & IQK */
+ rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800);
+ rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800);
+
+ mdelay(15);
+
+ ktime = 0;
+ while (rtl8xxxu_read32(priv, REG_IQK_RPT_TXA) == 0 && ktime < 21) {
+ mdelay(5);
+ ktime += 5;
+ }
+
+ /* Check failed */
+ reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
+ reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
+ reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
+
+ /* reload 0xdf and CCK_IND off */
+ rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);
+
+ rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_WE_LUT, BIT(4), 1);
+
+ val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_TXMOD);
+ rf_0x58_i = u32_get_bits(val32, 0xfc000);
+ rf_0x58_q = u32_get_bits(val32, 0x003f0);
+
+ for (i = 0; i < 8; i++) {
+ rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_TXPA_G3,
+ 0x1c000, i);
+ rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_TXPA_G3,
+ 0x00fc0, rf_0x58_i);
+ rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_TXPA_G3,
+ 0x0003f, rf_0x58_q);
+ }
+
+ rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_AC, BIT(14), 0);
+ rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_WE_LUT, BIT(4), 0);
+ rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, 0x00810, 0);
+
+ if (!(reg_eac & BIT(28)) &&
+ ((reg_e94 & 0x03ff0000) != 0x01420000) &&
+ ((reg_e9c & 0x03ff0000) != 0x00420000))
+ result |= 0x01;
+
+ return result;
+}
+
+static int rtl8192fu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)
+{
+ u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32;
+ int result = 0;
+ int ktime;
+
+ /* Leave IQK mode */
+ rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);
+
+ /* PA/PAD control by 0x56, and set = 0x0 */
+ rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(1), 1);
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_P1, 0);
+ rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(11), 1);
+ rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_PAD_TXG, 0x003ff, 0x27);
+
+ /* Enter IQK mode */
+ rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000);
+
+ /* path-A IQK setting */
+ rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
+ rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
+ rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
+ rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
+
+ rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160027);
+ rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160000);
+
+ /* Tx IQK setting */
+ rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
+ rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
+
+ /* LO calibration setting */
+ rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0086a911);
+
+ /* One shot, path A LOK & IQK */
+ rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800);
+ rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800);
+
+ mdelay(15);
+
+ ktime = 0;
+ while (rtl8xxxu_read32(priv, REG_IQK_RPT_TXA) == 0 && ktime < 21) {
+ mdelay(5);
+ ktime += 5;
+ }
+
+ /* Check failed */
+ reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
+ reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
+ reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
+
+ if (!(reg_eac & BIT(28)) &&
+ ((reg_e94 & 0x03ff0000) != 0x01420000) &&
+ ((reg_e9c & 0x03ff0000) != 0x00420000)) {
+ result |= 0x01;
+ } else { /* If TX not OK, ignore RX */
+ /* PA/PAD controlled by 0x0 */
+ rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);
+
+ rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA,
+ BIT(11), 0);
+
+ return result;
+ }
+
+ val32 = 0x80007c00 | (reg_e94 & 0x3ff0000) | ((reg_e9c & 0x3ff0000) >> 16);
+ rtl8xxxu_write32(priv, REG_TX_IQK, val32);
+
+ /* Modify RX IQK mode table */
+ rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);
+
+ /* PA/PAD control by 0x56, and set = 0x0 */
+ rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(1), 1);
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_P1, 0);
+ rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(11), 1);
+ rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_PAD_TXG, 0x003ff, 0x1e0);
+
+ rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0);
+ rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44ffbb44);
+ rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00400040);
+ rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005403);
+ rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000804e4);
+ rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400);
+ rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
+
+ /* Enter IQK mode */
+ rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000);
+
+ /* path-A IQK setting */
+ rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
+ rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c);
+ rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
+ rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
+
+ rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82170000);
+ rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28170000);
+
+ /* RX IQK setting */
+ rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
+
+ /* LO calibration setting */
+ rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1);
+
+ /* One shot, path A LOK & IQK */
+ rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800);
+ rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800);
+
+ mdelay(15);
+
+ ktime = 0;
+ while (rtl8xxxu_read32(priv, REG_IQK_RPT_RXA) == 0 && ktime < 21) {
+ mdelay(5);
+ ktime += 5;
+ }
+
+ /* Check failed */
+ reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
+ reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
+
+ /* Leave IQK mode */
+ rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);
+
+ rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(11), 0);
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_P1, 0x02000);
+
+ if (!(reg_eac & BIT(27)) &&
+ ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
+ ((reg_eac & 0x03ff0000) != 0x00360000))
+ result |= 0x02;
+
+ return result;
+}
+
+static int rtl8192fu_iqk_path_b(struct rtl8xxxu_priv *priv)
+{
+ u32 reg_eac, reg_eb4, reg_ebc, val32;
+ u32 rf_0x58_i, rf_0x58_q;
+ u8 rfe = priv->rfe_type;
+ int result = 0;
+ int ktime, i;
+
+ /* PA/PAD controlled by 0x0 */
+ rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);
+
+ rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0);
+ rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44ffbb44);
+ rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00400040);
+ rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005403);
+ rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000804e4);
+ rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400);
+ rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000000);
+
+ rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(4), 1);
+ rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(11), 1);
+ if (rfe == 7 || rfe == 8 || rfe == 9 || rfe == 12)
+ rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_PAD_TXG,
+ 0x003ff, 0x30);
+ else
+ rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_PAD_TXG,
+ 0x00fff, 0xe9);
+
+ rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000);
+
+ /* Path B IQK setting */
+ rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
+ rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
+ rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c);
+ rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
+
+ rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x8214000F);
+ rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28140000);
+
+ rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
+ rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
+
+ /* LO calibration setting */
+ rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00e62911);
+
+ /* One shot, path B LOK & IQK */
+ rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800);
+ rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800);
+
+ mdelay(15);
+
+ ktime = 0;
+ while (rtl8xxxu_read32(priv, REG_IQK_RPT_TXB) == 0 && ktime < 21) {
+ mdelay(5);
+ ktime += 5;
+ }
+
+ /* Check failed */
+ reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
+ reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
+ reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
+
+ /* reload 0xdf and CCK_IND off */
+ rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);
+
+ rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_WE_LUT, BIT(4), 1);
+
+ val32 = rtl8xxxu_read_rfreg(priv, RF_B, RF6052_REG_TXMOD);
+ rf_0x58_i = u32_get_bits(val32, 0xfc000);
+ rf_0x58_q = u32_get_bits(val32, 0x003f0);
+
+ for (i = 0; i < 8; i++) {
+ rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_TXPA_G3,
+ 0x1c000, i);
+ rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_TXPA_G3,
+ 0x00fc0, rf_0x58_i);
+ rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_TXPA_G3,
+ 0x0003f, rf_0x58_q);
+ }
+
+ rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_AC, BIT(14), 0);
+ rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_WE_LUT, BIT(4), 0);
+ rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, 0x00810, 0);
+
+ if (!(reg_eac & BIT(31)) &&
+ ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
+ ((reg_ebc & 0x03ff0000) != 0x00420000))
+ result |= 0x01;
+ else
+ dev_warn(&priv->udev->dev, "%s: Path B IQK failed!\n",
+ __func__);
+
+ return result;
+}
+
+static int rtl8192fu_rx_iqk_path_b(struct rtl8xxxu_priv *priv)
+{
+ u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc, val32;
+ int result = 0;
+ int ktime;
+
+ /* Leave IQK mode */
+ rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);
+
+ rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(1), 1);
+ rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_P1, 0);
+ rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(11), 1);
+ rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_PAD_TXG, 0x003ff, 0x67);
+
+ rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0);
+ rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44ffbb44);
+ rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00400040);
+ rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005403);
+ rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000804e4);
+ rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400);
+ rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000000);
+
+ rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000);
+
+ /* path-B IQK setting */
+ rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
+ rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
+ rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c);
+ rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
+
+ rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82160027);
+ rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160000);
+
+ /* LO calibration setting */
+ rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0086a911);
+
+ /* One shot, path A LOK & IQK */
+ rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800);
+ rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800);
+
+ mdelay(15);
+
+ ktime = 0;
+ while (rtl8xxxu_read32(priv, REG_IQK_RPT_TXB) == 0 && ktime < 21) {
+ mdelay(5);
+ ktime += 5;
+ }
+
+ /* Check failed */
+ reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
+ reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
+ reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
+
+ if (!(reg_eac & BIT(31)) &&
+ ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
+ ((reg_ebc & 0x03ff0000) != 0x00420000)) {
+ result |= 0x01;
+ } else {
+ /* PA/PAD controlled by 0x0 */
+ rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);
+
+ rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA,
+ BIT(11), 0);
+
+ return result;
+ }
+
+ val32 = 0x80007c00 | (reg_eb4 & 0x03ff0000) | ((reg_ebc >> 16) & 0x03ff);
+ rtl8xxxu_write32(priv, REG_TX_IQK, val32);
+
+ /* Modify RX IQK mode table */
+ rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);
+
+ rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(1), 1);
+ rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_P1, 0);
+ rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(11), 1);
+ rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_PAD_TXG, 0x003ff, 0x1e0);
+
+ rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0);
+ rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44ffbb44);
+ rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00400040);
+ rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005403);
+ rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000804e4);
+ rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400);
+ rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000000);
+
+ rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000);
+
+ /* Path B IQK setting */
+ rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
+ rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
+ rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
+ rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x18008c1c);
+
+ rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82170000);
+ rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28170000);
+
+ /* IQK setting */
+ rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
+
+ /* LO calibration setting */
+ rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
+
+ /* One shot, path A LOK & IQK */
+ rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800);
+ rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800);
+
+ mdelay(15);
+
+ ktime = 0;
+ while (rtl8xxxu_read32(priv, REG_IQK_RPT_RXB) == 0 && ktime < 21) {
+ mdelay(5);
+ ktime += 5;
+ }
+
+ reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
+ reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
+ reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
+
+ rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);
+ rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
+
+ rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(11), 0);
+ rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(1), 0);
+ rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_P1, 0x02000);
+
+ if (!(reg_eac & BIT(30)) &&
+ ((reg_ec4 & 0x03ff0000) != 0x01320000) &&
+ ((reg_ecc & 0x03ff0000) != 0x00360000))
+ result |= 0x02;
+ else
+ dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
+ __func__);
+
+ return result;
+}
+
+static void rtl8192fu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
+ int result[][8], int t)
+{
+ static const u32 adda_regs[2] = {
+ REG_ANAPWR1, REG_RX_WAIT_CCA
+ };
+ static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
+ REG_TXPAUSE, REG_BEACON_CTRL,
+ REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
+ };
+ static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
+ REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
+ REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
+ REG_DPDT_CTRL, REG_RFE_CTRL_ANTA_SRC,
+ REG_RFE_CTRL_ANT_SRC2, REG_CCK0_AFE_SETTING
+ };
+ u32 rx_initial_gain_a, rx_initial_gain_b;
+ struct device *dev = &priv->udev->dev;
+ int path_a_ok, path_b_ok;
+ u8 rfe = priv->rfe_type;
+ int retry = 2;
+ u32 i, val32;
+
+ /*
+ * Note: IQ calibration must be performed after loading
+ * PHY_REG.txt , and radio_a, radio_b.txt
+ */
+
+ rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);
+
+ rx_initial_gain_a = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
+ rx_initial_gain_b = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1);
+
+ if (t == 0) {
+ /* Save ADDA parameters, turn Path A ADDA on */
+ rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
+ ARRAY_SIZE(adda_regs));
+ rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
+ rtl8xxxu_save_regs(priv, iqk_bb_regs,
+ priv->bb_backup, RTL8XXXU_BB_REGS);
+ }
+
+ /* Instead of rtl8xxxu_path_adda_on */
+ rtl8xxxu_write32_set(priv, REG_FPGA0_XCD_RF_PARM, BIT(31));
+
+ /* MAC settings */
+ rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
+ rtl8xxxu_write8_clear(priv, REG_GPIO_MUXCFG, GPIO_MUXCFG_IO_SEL_ENBT);
+
+ if (rfe == 7 || rfe == 8 || rfe == 9 || rfe == 12) {
+ /* in ePA IQK, rfe_func_config & SW both pull down */
+ /* path A */
+ rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANTA_SRC, 0xF, 0x7);
+ rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x1, 0x0);
+
+ rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANTA_SRC, 0xF00, 0x7);
+ rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x4, 0x0);
+
+ rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANTA_SRC, 0xF000, 0x7);
+ rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x8, 0x0);
+
+ /* path B */
+ rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC2, 0xF0, 0x7);
+ rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x20000, 0x0);
+
+ rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC2, 0xF0000, 0x7);
+ rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x100000, 0x0);
+
+ rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC3, 0xF000, 0x7);
+ rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x8000000, 0x0);
+ }
+
+ if (priv->rf_paths > 1) {
+ /* path B standby */
+ rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x000000);
+ rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x10000);
+ rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000);
+ }
+
+ for (i = 0; i < retry; i++) {
+ path_a_ok = rtl8192fu_iqk_path_a(priv);
+
+ if (path_a_ok == 0x01) {
+ val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
+ result[t][0] = (val32 >> 16) & 0x3ff;
+
+ val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
+ result[t][1] = (val32 >> 16) & 0x3ff;
+ break;
+ } else {
+ result[t][0] = 0x100;
+ result[t][1] = 0x0;
+ }
+ }
+
+ for (i = 0; i < retry; i++) {
+ path_a_ok = rtl8192fu_rx_iqk_path_a(priv);
+
+ if (path_a_ok == 0x03) {
+ val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
+ result[t][2] = (val32 >> 16) & 0x3ff;
+
+ val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
+ result[t][3] = (val32 >> 16) & 0x3ff;
+ break;
+ } else {
+ result[t][2] = 0x100;
+ result[t][3] = 0x0;
+ }
+ }
+
+ if (!path_a_ok)
+ dev_warn(dev, "%s: Path A IQK failed!\n", __func__);
+
+ if (priv->rf_paths > 1) {
+ for (i = 0; i < retry; i++) {
+ path_b_ok = rtl8192fu_iqk_path_b(priv);
+
+ if (path_b_ok == 0x01) {
+ val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
+ result[t][4] = (val32 >> 16) & 0x3ff;
+
+ val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
+ result[t][5] = (val32 >> 16) & 0x3ff;
+ break;
+ } else {
+ result[t][4] = 0x100;
+ result[t][5] = 0x0;
+ }
+ }
+
+ for (i = 0; i < retry; i++) {
+ path_b_ok = rtl8192fu_rx_iqk_path_b(priv);
+
+ if (path_b_ok == 0x03) {
+ val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
+ result[t][6] = (val32 >> 16) & 0x3ff;
+
+ val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
+ result[t][7] = (val32 >> 16) & 0x3ff;
+ break;
+ } else {
+ result[t][6] = 0x100;
+ result[t][7] = 0x0;
+ }
+ }
+
+ if (!path_b_ok)
+ dev_warn(dev, "%s: Path B IQK failed!\n", __func__);
+ }
+
+ /* Back to BB mode, load original value */
+ rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);
+
+ rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xcc0000c0);
+
+ rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44bbbb44);
+ rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x80408040);
+ rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005433);
+ rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000004e4);
+ rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04003400);
+ rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
+
+ /* Reload ADDA power saving parameters */
+ rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
+ ARRAY_SIZE(adda_regs));
+
+ /* Reload MAC parameters */
+ rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
+
+ /* Reload BB parameters */
+ rtl8xxxu_restore_regs(priv, iqk_bb_regs, priv->bb_backup, RTL8XXXU_BB_REGS);
+
+ rtl8xxxu_write32_clear(priv, REG_FPGA0_XCD_RF_PARM, BIT(31));
+
+ /* Restore RX initial gain */
+ rtl8xxxu_write32_mask(priv, REG_OFDM0_XA_AGC_CORE1, 0xff, 0x50);
+ rtl8xxxu_write32_mask(priv, REG_OFDM0_XA_AGC_CORE1, 0xff,
+ rx_initial_gain_a & 0xff);
+ if (priv->rf_paths > 1) {
+ rtl8xxxu_write32_mask(priv, REG_OFDM0_XB_AGC_CORE1, 0xff, 0x50);
+ rtl8xxxu_write32_mask(priv, REG_OFDM0_XB_AGC_CORE1, 0xff,
+ rx_initial_gain_b & 0xff);
+ }
+}
+
+static void rtl8192fu_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
+{
+ s32 reg_e94, reg_e9c, reg_ea4, reg_eac;
+ s32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
+ struct device *dev = &priv->udev->dev;
+ u32 path_a_0xdf, path_a_0x35;
+ u32 path_b_0xdf, path_b_0x35;
+ bool path_a_ok, path_b_ok;
+ u8 rfe = priv->rfe_type;
+ u32 rfe_path_select;
+ int result[4][8]; /* last is final result */
+ int i, candidate;
+ s32 reg_tmp = 0;
+ bool simu;
+ u32 val32;
+
+ rfe_path_select = rtl8xxxu_read32(priv, REG_RFE_PATH_SELECT);
+
+ path_a_0xdf = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA);
+ path_a_0x35 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_P1);
+ path_b_0xdf = rtl8xxxu_read_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA);
+ path_b_0x35 = rtl8xxxu_read_rfreg(priv, RF_B, RF6052_REG_GAIN_P1);
+
+ memset(result, 0, sizeof(result));
+ candidate = -1;
+
+ path_a_ok = false;
+ path_b_ok = false;
+
+ for (i = 0; i < 3; i++) {
+ rtl8192fu_phy_iqcalibrate(priv, result, i);
+
+ if (i == 1) {
+ simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 1);
+ if (simu) {
+ candidate = 0;
+ break;
+ }
+ }
+
+ if (i == 2) {
+ simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 2);
+ if (simu) {
+ candidate = 0;
+ break;
+ }
+
+ simu = rtl8xxxu_gen2_simularity_compare(priv, result, 1, 2);
+ if (simu) {
+ candidate = 1;
+ } else {
+ for (i = 0; i < 8; i++)
+ reg_tmp += result[3][i];
+
+ if (reg_tmp)
+ candidate = 3;
+ else
+ candidate = -1;
+ }
+ }
+ }
+
+ if (candidate >= 0) {
+ reg_e94 = result[candidate][0];
+ reg_e9c = result[candidate][1];
+ reg_ea4 = result[candidate][2];
+ reg_eac = result[candidate][3];
+ reg_eb4 = result[candidate][4];
+ reg_ebc = result[candidate][5];
+ reg_ec4 = result[candidate][6];
+ reg_ecc = result[candidate][7];
+
+ dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
+ dev_dbg(dev, "%s: e94=%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%c\n",
+ __func__, reg_e94, reg_e9c, reg_ea4, reg_eac,
+ reg_eb4, reg_ebc, reg_ec4, reg_ecc);
+
+ path_a_ok = true;
+ path_b_ok = true;
+ }
+
+ rtl8xxxu_write32_mask(priv, REG_TX_IQK_TONE_A, 0x3ff00000, 0x100);
+ rtl8xxxu_write32_mask(priv, REG_NP_ANTA, 0x3ff, 0);
+ rtl8xxxu_write32_mask(priv, REG_TX_IQK_TONE_B, 0x3ff00000, 0x100);
+ rtl8xxxu_write32_mask(priv, REG_TAP_UPD_97F, 0x3ff, 0);
+
+ if (candidate >= 0) {
+ if (reg_e94)
+ rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
+ candidate, (reg_ea4 == 0));
+
+ if (reg_eb4)
+ rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
+ candidate, (reg_ec4 == 0));
+ }
+
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, path_a_0xdf);
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_P1, path_a_0x35);
+ rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, path_b_0xdf);
+ rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_P1, path_b_0x35);
+
+ if (rfe == 7 || rfe == 8 || rfe == 9 || rfe == 12) {
+ rtl8xxxu_write32_set(priv, REG_SW_GPIO_SHARE_CTRL_1, 0x70000);
+ rtl8xxxu_write32_clear(priv, REG_LEDCFG0, 0x6c00000);
+ rtl8xxxu_write32_set(priv, REG_PAD_CTRL1, BIT(29) | BIT(28));
+ rtl8xxxu_write32_clear(priv, REG_SW_GPIO_SHARE_CTRL_0,
+ 0x600000 | BIT(4));
+
+ /*
+ * Originally:
+ * odm_set_bb_reg(dm, R_0x944, BIT(11) | 0x1F, 0x3F);
+ *
+ * It clears bit 11 and sets bits 0..4. The mask doesn't cover
+ * bit 5 so it's not modified. Is that what it's supposed to
+ * accomplish?
+ */
+ val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);
+ val32 &= ~BIT(11);
+ val32 |= 0x1f;
+ rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);
+
+ if (rfe == 7) {
+ rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANTA_SRC,
+ 0xfffff, 0x23200);
+ rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC2,
+ 0xfffff, 0x23200);
+ rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC1,
+ 0xf000, 0x3);
+ rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC3,
+ 0xf000, 0x3);
+ } else {
+ rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANTA_SRC,
+ 0xfffff, 0x22200);
+ rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC2,
+ 0xfffff, 0x22200);
+ rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC1,
+ 0xf000, 0x2);
+ rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC3,
+ 0xf000, 0x2);
+ }
+
+ rtl8xxxu_write32_clear(priv, REG_RFE_OPT62, BIT(2));
+
+ if (rfe == 7)
+ rtl8xxxu_write32(priv, REG_RFE_OPT, 0x03000003);
+
+ rtl8xxxu_write32(priv, REG_RFE_PATH_SELECT, rfe_path_select);
+ }
+}
+
+static void rtl8192fu_disabled_to_emu(struct rtl8xxxu_priv *priv)
+{
+ rtl8xxxu_write16_clear(priv, REG_APS_FSMCO,
+ APS_FSMCO_HW_POWERDOWN | APS_FSMCO_HW_SUSPEND);
+
+ rtl8xxxu_write32_clear(priv, REG_GPIO_INTM, BIT(16));
+
+ rtl8xxxu_write16_clear(priv, REG_APS_FSMCO,
+ APS_FSMCO_PCIE | APS_FSMCO_HW_SUSPEND);
+}
+
+static int rtl8192fu_emu_to_active(struct rtl8xxxu_priv *priv)
+{
+ u32 val32;
+ u16 val16;
+ int count;
+
+ /* enable LDOA12 MACRO block for all interface */
+ rtl8xxxu_write8_set(priv, REG_LDOA15_CTRL, LDOA15_ENABLE);
+
+ /* disable BT_GPS_SEL pins */
+ rtl8xxxu_write32_clear(priv, REG_PAD_CTRL1, BIT(28));
+
+ mdelay(1);
+
+ /* release analog Ips to digital */
+ rtl8xxxu_write8_clear(priv, REG_SYS_ISO_CTRL, SYS_ISO_ANALOG_IPS);
+
+ val16 = APS_FSMCO_PCIE | APS_FSMCO_HW_SUSPEND | APS_FSMCO_SW_LPS;
+ rtl8xxxu_write16_clear(priv, REG_APS_FSMCO, val16);
+
+ /* wait till 0x04[17] = 1 power ready */
+ for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
+ val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
+ if (val32 & BIT(17))
+ break;
+
+ udelay(10);
+ }
+
+ if (!count)
+ return -EBUSY;
+
+ rtl8xxxu_write32_set(priv, REG_APS_FSMCO, APS_FSMCO_WLON_RESET);
+
+ for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
+ val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
+ if ((val32 & (APS_FSMCO_MAC_ENABLE | APS_FSMCO_MAC_OFF)) == 0)
+ break;
+
+ udelay(10);
+ }
+
+ if (!count)
+ return -EBUSY;
+
+ /* SWR OCP enable */
+ rtl8xxxu_write32_set(priv, REG_AFE_MISC, BIT(18));
+
+ rtl8xxxu_write16_clear(priv, REG_APS_FSMCO, APS_FSMCO_HW_POWERDOWN);
+
+ rtl8xxxu_write16_clear(priv, REG_APS_FSMCO,
+ APS_FSMCO_PCIE | APS_FSMCO_HW_SUSPEND);
+
+ /* 0x7c[31]=1, LDO has max output capability */
+ rtl8xxxu_write32_set(priv, REG_LDO_SW_CTRL, BIT(31));
+
+ rtl8xxxu_write16_set(priv, REG_APS_FSMCO, APS_FSMCO_MAC_ENABLE);
+
+ for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
+ val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
+ if ((val32 & APS_FSMCO_MAC_ENABLE) == 0)
+ break;
+
+ udelay(10);
+ }
+
+ if (!count)
+ return -EBUSY;
+
+ /* Enable WL control XTAL setting */
+ rtl8xxxu_write8_set(priv, REG_AFE_MISC, AFE_MISC_WL_XTAL_CTRL);
+
+ /* Enable falling edge triggering interrupt */
+ rtl8xxxu_write16_set(priv, REG_GPIO_INTM, GPIO_INTM_EDGE_TRIG_IRQ);
+
+ /* Enable GPIO9 data mode */
+ rtl8xxxu_write16_clear(priv, REG_GPIO_IO_SEL_2, GPIO_IO_SEL_2_GPIO09_IRQ);
+
+ /* Enable GPIO9 input mode */
+ rtl8xxxu_write16_clear(priv, REG_GPIO_IO_SEL_2, GPIO_IO_SEL_2_GPIO09_INPUT);
+
+ /* Enable HSISR GPIO[C:0] interrupt */
+ rtl8xxxu_write8_set(priv, REG_HSIMR, BIT(0));
+
+ /* RF HW ON/OFF Enable */
+ rtl8xxxu_write8_clear(priv, REG_MULTI_FUNC_CTRL, MULTI_WIFI_HW_ROF_EN);
+
+ /* Register Lock Disable */
+ rtl8xxxu_write8_set(priv, REG_RSV_CTRL, BIT(7));
+
+ /* For GPIO9 internal pull high setting */
+ rtl8xxxu_write16_set(priv, REG_MULTI_FUNC_CTRL, BIT(14));
+
+ /* reset RF path S1 */
+ rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
+
+ /* reset RF path S0 */
+ rtl8xxxu_write8(priv, REG_AFE_CTRL4 + 3, 0);
+
+ /* enable RF path S1 */
+ rtl8xxxu_write8(priv, REG_RF_CTRL, RF_SDMRSTB | RF_RSTB | RF_ENABLE);
+
+ /* enable RF path S0 */
+ rtl8xxxu_write8(priv, REG_AFE_CTRL4 + 3, RF_SDMRSTB | RF_RSTB | RF_ENABLE);
+
+ /* AFE_Ctrl */
+ rtl8xxxu_write8_set(priv, REG_RSVD_1, BIT(5));
+
+ /* AFE_Ctrl */
+ rtl8xxxu_write8(priv, REG_RSVD_4, 0xcc);
+
+ /* AFE_Ctrl 0x24[4:3]=00 for xtal gmn */
+ rtl8xxxu_write8_clear(priv, REG_AFE_XTAL_CTRL, BIT(4) | BIT(3));
+
+ /* GPIO_A[31:0] Pull down software register */
+ rtl8xxxu_write32(priv, REG_GPIO_A0, 0xffffffff);
+
+ /* GPIO_B[7:0] Pull down software register */
+ rtl8xxxu_write8(priv, REG_GPIO_B0, 0xff);
+
+ /* Register Lock Enable */
+ rtl8xxxu_write8_clear(priv, REG_RSV_CTRL, BIT(7));
+
+ return 0;
+}
+
+static int rtl8192fu_active_to_emu(struct rtl8xxxu_priv *priv)
+{
+ u32 val32;
+ int count;
+
+ /* Reset BB, RF enter Power Down mode */
+ rtl8xxxu_write8_clear(priv, REG_SYS_FUNC, SYS_FUNC_BBRSTB);
+
+ /* Enable rising edge triggering interrupt */
+ rtl8xxxu_write16_clear(priv, REG_GPIO_INTM, GPIO_INTM_EDGE_TRIG_IRQ);
+
+ /* release WLON reset */
+ rtl8xxxu_write32_set(priv, REG_APS_FSMCO, APS_FSMCO_WLON_RESET);
+
+ /* turn off MAC by HW state machine */
+ rtl8xxxu_write16_set(priv, REG_APS_FSMCO, APS_FSMCO_MAC_OFF);
+
+ for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
+ val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
+ if ((val32 & APS_FSMCO_MAC_OFF) == 0)
+ break;
+
+ udelay(10);
+ }
+
+ if (!count)
+ return -EBUSY;
+
+ /* analog Ips to digital, 1:isolation */
+ rtl8xxxu_write8_set(priv, REG_SYS_ISO_CTRL, SYS_ISO_ANALOG_IPS);
+
+ /* disable LDOA12 MACRO block */
+ rtl8xxxu_write8_clear(priv, REG_LDOA15_CTRL, LDOA15_ENABLE);
+
+ return 0;
+}
+
+static int rtl8192fu_emu_to_disabled(struct rtl8xxxu_priv *priv)
+{
+ u16 val16;
+
+ /* SOP option to disable BG/MB */
+ rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
+
+ /* 0x04[12:11] = 2b'01 enable WL suspend */
+ val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
+ val16 &= ~APS_FSMCO_PCIE;
+ val16 |= APS_FSMCO_HW_SUSPEND;
+ rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
+
+ /* enable GPIO9 as EXT WAKEUP */
+ rtl8xxxu_write32_set(priv, REG_GPIO_INTM, BIT(16));
+
+ return 0;
+}
+
+static int rtl8192fu_active_to_lps(struct rtl8xxxu_priv *priv)
+{
+ struct device *dev = &priv->udev->dev;
+ u16 val16;
+ u32 val32;
+ int retry;
+
+ /* Tx Pause */
+ rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
+
+ retry = 100;
+
+ /* Poll 32 bit wide REG_SCH_TX_CMD for 0 to ensure no TX is pending. */
+ do {
+ val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD);
+ if (!val32)
+ break;
+
+ udelay(10);
+ } while (retry--);
+
+ if (!retry) {
+ dev_warn(dev, "%s: Failed to flush TX queue\n", __func__);
+ return -EBUSY;
+ }
+
+ /* Disable CCK and OFDM, clock gated */
+ rtl8xxxu_write8_clear(priv, REG_SYS_FUNC, SYS_FUNC_BBRSTB);
+
+ udelay(2);
+
+ /* Whole BB is reset */
+ rtl8xxxu_write8_clear(priv, REG_SYS_FUNC, SYS_FUNC_BB_GLB_RSTN);
+
+ /* Reset MAC TRX */
+ val16 = rtl8xxxu_read16(priv, REG_CR);
+ val16 &= 0xff00;
+ val16 |= CR_HCI_RXDMA_ENABLE | CR_HCI_TXDMA_ENABLE;
+ val16 &= ~CR_SECURITY_ENABLE;
+ rtl8xxxu_write16(priv, REG_CR, val16);
+
+ /* Respond TxOK to scheduler */
+ rtl8xxxu_write8_set(priv, REG_DUAL_TSF_RST, DUAL_TSF_TX_OK);
+
+ return 0;
+}
+
+static int rtl8192fu_power_on(struct rtl8xxxu_priv *priv)
+{
+ u16 val16;
+ int ret;
+
+ rtl8xxxu_write8(priv, REG_USB_ACCESS_TIMEOUT, 0x80);
+
+ rtl8192fu_disabled_to_emu(priv);
+
+ ret = rtl8192fu_emu_to_active(priv);
+ if (ret)
+ return ret;
+
+ rtl8xxxu_write16(priv, REG_CR, 0);
+
+ val16 = rtl8xxxu_read16(priv, REG_CR);
+
+ val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
+ CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
+ CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
+ CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE;
+ rtl8xxxu_write16(priv, REG_CR, val16);
+
+ return 0;
+}
+
+static void rtl8192fu_power_off(struct rtl8xxxu_priv *priv)
+{
+ rtl8xxxu_flush_fifo(priv);
+
+ /* Stop Tx Report Timer. 0x4EC[Bit1]=b'0 */
+ rtl8xxxu_write8_clear(priv, REG_TX_REPORT_CTRL,
+ TX_REPORT_CTRL_TIMER_ENABLE);
+
+ /* stop rx */
+ rtl8xxxu_write8(priv, REG_CR, 0x00);
+
+ rtl8192fu_active_to_lps(priv);
+
+ /* Reset Firmware if running in RAM */
+ if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
+ rtl8xxxu_firmware_self_reset(priv);
+
+ /* Reset MCU */
+ rtl8xxxu_write16_clear(priv, REG_SYS_FUNC, SYS_FUNC_CPU_ENABLE);
+
+ /* Reset MCU ready status */
+ rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
+
+ rtl8192fu_active_to_emu(priv);
+ rtl8192fu_emu_to_disabled(priv);
+}
+
+static void rtl8192f_reset_8051(struct rtl8xxxu_priv *priv)
+{
+ rtl8xxxu_write8_clear(priv, REG_RSV_CTRL, BIT(1));
+
+ rtl8xxxu_write8_clear(priv, REG_RSV_CTRL + 1, BIT(0));
+
+ rtl8xxxu_write16_clear(priv, REG_SYS_FUNC, SYS_FUNC_CPU_ENABLE);
+
+ rtl8xxxu_write8_clear(priv, REG_RSV_CTRL, BIT(1));
+
+ rtl8xxxu_write8_set(priv, REG_RSV_CTRL + 1, BIT(0));
+
+ rtl8xxxu_write16_set(priv, REG_SYS_FUNC, SYS_FUNC_CPU_ENABLE);
+}
+
+static void rtl8192f_enable_rf(struct rtl8xxxu_priv *priv)
+{
+ u32 val32;
+
+ rtl8xxxu_write8(priv, REG_RF_CTRL, RF_ENABLE | RF_RSTB | RF_SDMRSTB);
+
+ val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
+ val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
+ val32 |= OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
+ OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
+ rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
+
+ rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
+}
+
+static void rtl8192f_disable_rf(struct rtl8xxxu_priv *priv)
+{
+ u32 val32;
+
+ val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
+ val32 &= ~OFDM_RF_PATH_TX_MASK;
+ rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
+
+ /* Power down RF module */
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
+}
+
+static void rtl8192f_usb_quirks(struct rtl8xxxu_priv *priv)
+{
+ u16 val16;
+
+ rtl8xxxu_gen2_usb_quirks(priv);
+
+ val16 = rtl8xxxu_read16(priv, REG_CR);
+ val16 |= (CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE);
+ rtl8xxxu_write16(priv, REG_CR, val16);
+}
+
+#define XTAL1 GENMASK(6, 1)
+#define XTAL0 GENMASK(30, 25)
+
+static void rtl8192f_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap)
+{
+ struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking;
+ u32 xtal1, xtal0;
+
+ if (crystal_cap == cfo->crystal_cap)
+ return;
+
+ xtal1 = rtl8xxxu_read32(priv, REG_AFE_PLL_CTRL);
+ xtal0 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
+
+ dev_dbg(&priv->udev->dev,
+ "%s: Adjusting crystal cap from 0x%x (actually 0x%x 0x%x) to 0x%x\n",
+ __func__,
+ cfo->crystal_cap,
+ u32_get_bits(xtal1, XTAL1),
+ u32_get_bits(xtal0, XTAL0),
+ crystal_cap);
+
+ u32p_replace_bits(&xtal1, crystal_cap, XTAL1);
+ u32p_replace_bits(&xtal0, crystal_cap, XTAL0);
+ rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, xtal1);
+ rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, xtal0);
+
+ cfo->crystal_cap = crystal_cap;
+}
+
+static s8 rtl8192f_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats)
+{
+ struct jaguar2_phy_stats_type0 *phy_stats0 = (struct jaguar2_phy_stats_type0 *)phy_stats;
+ u8 lna_idx = (phy_stats0->lna_h << 3) | phy_stats0->lna_l;
+ u8 vga_idx = phy_stats0->vga;
+ s8 rx_pwr_all;
+
+ switch (lna_idx) {
+ case 7:
+ rx_pwr_all = -44 - (2 * vga_idx);
+ break;
+ case 5:
+ rx_pwr_all = -28 - (2 * vga_idx);
+ break;
+ case 3:
+ rx_pwr_all = -10 - (2 * vga_idx);
+ break;
+ case 0:
+ rx_pwr_all = 14 - (2 * vga_idx);
+ break;
+ default:
+ rx_pwr_all = 0;
+ break;
+ }
+
+ return rx_pwr_all;
+}
+
+static int rtl8192fu_led_brightness_set(struct led_classdev *led_cdev,
+ enum led_brightness brightness)
+{
+ struct rtl8xxxu_priv *priv = container_of(led_cdev,
+ struct rtl8xxxu_priv,
+ led_cdev);
+ u16 ledcfg;
+
+ /* Values obtained by observing the USB traffic from the Windows driver. */
+ rtl8xxxu_write32(priv, REG_SW_GPIO_SHARE_CTRL_0, 0x20080);
+ rtl8xxxu_write32(priv, REG_SW_GPIO_SHARE_CTRL_1, 0x1b0000);
+
+ ledcfg = rtl8xxxu_read16(priv, REG_LEDCFG0);
+
+ if (brightness == LED_OFF) {
+ /* Value obtained like above. */
+ ledcfg = BIT(1) | BIT(7);
+ } else if (brightness == LED_ON) {
+ /* Value obtained like above. */
+ ledcfg = BIT(1) | BIT(7) | BIT(11);
+ } else if (brightness == RTL8XXXU_HW_LED_CONTROL) {
+ /* Value obtained by brute force. */
+ ledcfg = BIT(8) | BIT(9);
+ }
+
+ rtl8xxxu_write16(priv, REG_LEDCFG0, ledcfg);
+
+ return 0;
+}
+
+struct rtl8xxxu_fileops rtl8192fu_fops = {
+ .identify_chip = rtl8192fu_identify_chip,
+ .parse_efuse = rtl8192fu_parse_efuse,
+ .load_firmware = rtl8192fu_load_firmware,
+ .power_on = rtl8192fu_power_on,
+ .power_off = rtl8192fu_power_off,
+ .read_efuse = rtl8xxxu_read_efuse,
+ .reset_8051 = rtl8192f_reset_8051,
+ .llt_init = rtl8xxxu_auto_llt_table,
+ .init_phy_bb = rtl8192fu_init_phy_bb,
+ .init_phy_rf = rtl8192fu_init_phy_rf,
+ .phy_lc_calibrate = rtl8192f_phy_lc_calibrate,
+ .phy_iq_calibrate = rtl8192fu_phy_iq_calibrate,
+ .config_channel = rtl8192fu_config_channel,
+ .parse_rx_desc = rtl8xxxu_parse_rxdesc24,
+ .parse_phystats = jaguar2_rx_parse_phystats,
+ .init_aggregation = rtl8192fu_init_aggregation,
+ .init_burst = rtl8xxxu_init_burst,
+ .enable_rf = rtl8192f_enable_rf,
+ .disable_rf = rtl8192f_disable_rf,
+ .usb_quirks = rtl8192f_usb_quirks,
+ .set_tx_power = rtl8192f_set_tx_power,
+ .update_rate_mask = rtl8xxxu_gen2_update_rate_mask,
+ .report_connect = rtl8xxxu_gen2_report_connect,
+ .report_rssi = rtl8xxxu_gen2_report_rssi,
+ .fill_txdesc = rtl8xxxu_fill_txdesc_v2,
+ .set_crystal_cap = rtl8192f_set_crystal_cap,
+ .cck_rssi = rtl8192f_cck_rssi,
+ .led_classdev_brightness_set = rtl8192fu_led_brightness_set,
+ .writeN_block_size = 254,
+ .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24),
+ .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40),
+ .has_tx_report = 1,
+ .gen2_thermal_meter = 1,
+ .needs_full_init = 1,
+ .init_reg_rxfltmap = 1,
+ .init_reg_pkt_life_time = 1,
+ .init_reg_hmtfr = 1,
+ .ampdu_max_time = 0x5e,
+ .ustime_tsf_edca = 0x50,
+ .max_aggr_num = 0x1f1f,
+ .trxff_boundary = 0x3f3f,
+ .pbp_rx = PBP_PAGE_SIZE_256,
+ .pbp_tx = PBP_PAGE_SIZE_256,
+ .mactable = rtl8192f_mac_init_table,
+ .total_page_num = TX_TOTAL_PAGE_NUM_8192F,
+ .page_num_hi = TX_PAGE_NUM_HI_PQ_8192F,
+ .page_num_lo = TX_PAGE_NUM_LO_PQ_8192F,
+ .page_num_norm = TX_PAGE_NUM_NORM_PQ_8192F,
+};
diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8710b.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8710b.c
index 22d4704dd31e..f0d17b75c5f1 100644
--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8710b.c
+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8710b.c
@@ -1031,12 +1031,12 @@ static int rtl8710bu_iqk_path_a(struct rtl8xxxu_priv *priv, u32 *lok_result)
rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0x07ff7);
/* PA,PAD gain adjust */
- val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF);
+ val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA);
val32 |= BIT(11);
- rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, val32);
- val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56);
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, val32);
+ val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_PAD_TXG);
u32p_replace_bits(&val32, 0x1ed, 0x00fff);
- rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, val32);
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, val32);
/* enter IQK mode */
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
@@ -1068,9 +1068,9 @@ static int rtl8710bu_iqk_path_a(struct rtl8xxxu_priv *priv, u32 *lok_result)
u32p_replace_bits(&val32, 0, 0xffffff00);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
- val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF);
+ val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA);
val32 &= ~BIT(11);
- rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, val32);
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, val32);
/* save LOK result */
*lok_result = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_TXM_IDAC);
@@ -1113,12 +1113,12 @@ static int rtl8710bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv, u32 lok_result)
rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf1173);
/* PA,PAD gain adjust */
- val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF);
+ val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA);
val32 |= BIT(11);
- rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, val32);
- val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56);
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, val32);
+ val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_PAD_TXG);
u32p_replace_bits(&val32, 0xf, 0x003e0);
- rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, val32);
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, val32);
/*
* Enter IQK mode
@@ -1170,9 +1170,9 @@ static int rtl8710bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv, u32 lok_result)
u32p_replace_bits(&val32, 0, 0xffffff00);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
- val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF);
+ val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA);
val32 &= ~BIT(11);
- rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, val32);
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, val32);
return result;
}
@@ -1197,12 +1197,12 @@ static int rtl8710bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv, u32 lok_result)
/*
* PA, PAD setting
*/
- val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF);
+ val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA);
val32 |= BIT(11);
- rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, val32);
- val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56);
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, val32);
+ val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_PAD_TXG);
u32p_replace_bits(&val32, 0x2a, 0x00fff);
- rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, val32);
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, val32);
/*
* Enter IQK mode
@@ -1241,9 +1241,9 @@ static int rtl8710bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv, u32 lok_result)
u32p_replace_bits(&val32, 0, 0xffffff00);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
- val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF);
+ val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA);
val32 &= ~BIT(11);
- rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, val32);
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, val32);
/* reload LOK value */
rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXM_IDAC, lok_result);
@@ -1874,6 +1874,7 @@ struct rtl8xxxu_fileops rtl8710bu_fops = {
* but in rtl8xxxu 0x50 causes slow upload and random packet loss. Why?
*/
.ustime_tsf_edca = 0x28,
+ .max_aggr_num = 0x0c14,
.adda_1t_init = 0x03c00016,
.adda_1t_path_on = 0x03c00016,
.trxff_boundary = 0x3f7f,
diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c
index abc56c7de6f7..13ad5d5b73f4 100644
--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c
+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c
@@ -824,7 +824,7 @@ static int rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)
/*
* PA, PAD setting
*/
- rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0xf80);
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0xf80);
rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, 0x4021f);
/*
@@ -888,7 +888,7 @@ static int rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)
reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
- rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x780);
+ rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x780);
val32 = (reg_eac >> 16) & 0x3ff;
if (val32 & 0x200)
@@ -1741,6 +1741,7 @@ struct rtl8xxxu_fileops rtl8723bu_fops = {
.init_reg_hmtfr = 1,
.ampdu_max_time = 0x5e,
.ustime_tsf_edca = 0x50,
+ .max_aggr_num = 0x0c14,
.adda_1t_init = 0x01c00014,
.adda_1t_path_on = 0x01c00014,
.adda_2t_path_on_a = 0x01c00014,
diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
index 831639d73657..5d102a1246a3 100644
--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
@@ -56,6 +56,7 @@ MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");
MODULE_FIRMWARE("rtlwifi/rtl8188fufw.bin");
MODULE_FIRMWARE("rtlwifi/rtl8710bufw_SMIC.bin");
MODULE_FIRMWARE("rtlwifi/rtl8710bufw_UMC.bin");
+MODULE_FIRMWARE("rtlwifi/rtl8192fufw.bin");
module_param_named(debug, rtl8xxxu_debug, int, 0600);
MODULE_PARM_DESC(debug, "Set debug mask");
@@ -642,7 +643,7 @@ const u32 rtl8xxxu_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
REG_OFDM0_XA_RX_IQ_IMBALANCE,
REG_OFDM0_XB_RX_IQ_IMBALANCE,
REG_OFDM0_ENERGY_CCA_THRES,
- REG_OFDM0_AGCR_SSI_TABLE,
+ REG_OFDM0_AGC_RSSI_TABLE,
REG_OFDM0_XA_TX_IQ_IMBALANCE,
REG_OFDM0_XB_TX_IQ_IMBALANCE,
REG_OFDM0_XC_TX_AFE,
@@ -1185,6 +1186,20 @@ static void rtl8xxxu_stop_tx_beacon(struct rtl8xxxu_priv *priv)
rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
}
+static void rtl8xxxu_start_tx_beacon(struct rtl8xxxu_priv *priv)
+{
+ u8 val8;
+
+ val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
+ val8 |= EN_BCNQ_DL >> 16;
+ rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
+
+ rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x80);
+ val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
+ val8 &= 0xF0;
+ rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
+}
+
/*
* The rtl8723a has 3 channel groups for it's efuse settings. It only
@@ -2006,12 +2021,18 @@ exit:
static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
{
int pages, remainder, i, ret;
+ u16 reg_fw_start_address;
u16 reg_mcu_fw_dl;
u8 val8;
u16 val16;
u32 val32;
u8 *fwptr;
+ if (priv->rtl_chip == RTL8192F)
+ reg_fw_start_address = REG_FW_START_ADDRESS_8192F;
+ else
+ reg_fw_start_address = REG_FW_START_ADDRESS;
+
if (priv->rtl_chip == RTL8710B) {
reg_mcu_fw_dl = REG_8051FW_CTRL_V1_8710B;
} else {
@@ -2067,7 +2088,7 @@ static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
val8 |= i;
rtl8xxxu_write8(priv, reg_mcu_fw_dl + 2, val8);
- ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
+ ret = rtl8xxxu_writeN(priv, reg_fw_start_address,
fwptr, RTL_FW_PAGE_SIZE);
if (ret != RTL_FW_PAGE_SIZE) {
ret = -EAGAIN;
@@ -2081,7 +2102,7 @@ static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl + 2) & 0xF8;
val8 |= i;
rtl8xxxu_write8(priv, reg_mcu_fw_dl + 2, val8);
- ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
+ ret = rtl8xxxu_writeN(priv, reg_fw_start_address,
fwptr, remainder);
if (ret != remainder) {
ret = -EAGAIN;
@@ -2135,6 +2156,7 @@ int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, const char *fw_name)
case 0x2300:
case 0x88f0:
case 0x10b0:
+ case 0x92f0:
break;
default:
ret = -EINVAL;
@@ -2581,6 +2603,7 @@ static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
u16 hiq, mgq, bkq, beq, viq, voq;
int hip, mgp, bkp, bep, vip, vop;
int ret = 0;
+ u32 val32;
switch (priv->ep_tx_count) {
case 1:
@@ -2663,15 +2686,28 @@ static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
* queue here .... why?
*/
if (!ret) {
- val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
- val16 &= 0x7;
- val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
- (viq << TRXDMA_CTRL_VIQ_SHIFT) |
- (beq << TRXDMA_CTRL_BEQ_SHIFT) |
- (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
- (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
- (hiq << TRXDMA_CTRL_HIQ_SHIFT);
- rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
+ /* Only RTL8192F seems to do it like this. */
+ if (priv->rtl_chip == RTL8192F) {
+ val32 = rtl8xxxu_read32(priv, REG_TRXDMA_CTRL);
+ val32 &= 0x7;
+ val32 |= (voq << TRXDMA_CTRL_VOQ_SHIFT_8192F) |
+ (viq << TRXDMA_CTRL_VIQ_SHIFT_8192F) |
+ (beq << TRXDMA_CTRL_BEQ_SHIFT_8192F) |
+ (bkq << TRXDMA_CTRL_BKQ_SHIFT_8192F) |
+ (mgq << TRXDMA_CTRL_MGQ_SHIFT_8192F) |
+ (hiq << TRXDMA_CTRL_HIQ_SHIFT_8192F);
+ rtl8xxxu_write32(priv, REG_TRXDMA_CTRL, val32);
+ } else {
+ val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
+ val16 &= 0x7;
+ val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
+ (viq << TRXDMA_CTRL_VIQ_SHIFT) |
+ (beq << TRXDMA_CTRL_BEQ_SHIFT) |
+ (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
+ (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
+ (hiq << TRXDMA_CTRL_HIQ_SHIFT);
+ rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
+ }
priv->pipe_out[TXDESC_QUEUE_VO] =
usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
@@ -2842,10 +2878,14 @@ void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok,
reg = (result[candidate][7] >> 6) & 0xf;
- val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
- val32 &= ~0x0000f000;
- val32 |= (reg << 12);
- rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
+ if (priv->rtl_chip == RTL8192F) {
+ rtl8xxxu_write32_mask(priv, REG_RXIQB_EXT, 0x000000f0, reg);
+ } else {
+ val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_RSSI_TABLE);
+ val32 &= ~0x0000f000;
+ val32 |= (reg << 12);
+ rtl8xxxu_write32(priv, REG_OFDM0_AGC_RSSI_TABLE, val32);
+ }
}
#define MAX_TOLERANCE 5
@@ -3944,13 +3984,14 @@ void rtl8xxxu_init_burst(struct rtl8xxxu_priv *priv)
val8 |= HT_SINGLE_AMPDU_ENABLE;
rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8);
- rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0c14);
+ rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, priv->fops->max_aggr_num);
rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B,
priv->fops->ampdu_max_time);
rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff);
rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18);
rtl8xxxu_write8(priv, REG_PIFS, 0x00);
- if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8710B) {
+ if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8710B ||
+ priv->rtl_chip == RTL8192F) {
rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, FWHW_TXQ_CTRL_AMPDU_RETRY);
rtl8xxxu_write32(priv, REG_FAST_EDCA_CTRL, 0x03086666);
}
@@ -3963,6 +4004,34 @@ void rtl8xxxu_init_burst(struct rtl8xxxu_priv *priv)
rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
}
+static u8 rtl8xxxu_acquire_macid(struct rtl8xxxu_priv *priv)
+{
+ u8 macid;
+
+ macid = find_first_zero_bit(priv->mac_id_map, RTL8XXXU_MAX_MAC_ID_NUM);
+ if (macid < RTL8XXXU_MAX_MAC_ID_NUM)
+ set_bit(macid, priv->mac_id_map);
+
+ return macid;
+}
+
+static void rtl8xxxu_release_macid(struct rtl8xxxu_priv *priv, u8 macid)
+{
+ clear_bit(macid, priv->mac_id_map);
+}
+
+static inline u8 rtl8xxxu_get_macid(struct rtl8xxxu_priv *priv,
+ struct ieee80211_sta *sta)
+{
+ struct rtl8xxxu_sta_info *sta_info;
+
+ if (!priv->vif || priv->vif->type == NL80211_IFTYPE_STATION || !sta)
+ return 0;
+
+ sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv;
+ return sta_info->macid;
+}
+
static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
{
struct rtl8xxxu_priv *priv = hw->priv;
@@ -4036,9 +4105,14 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
if (ret)
goto exit;
+ /* Mac APLL Setting */
+ if (priv->rtl_chip == RTL8192F)
+ rtl8xxxu_write16_set(priv, REG_AFE_CTRL4, BIT(4) | BIT(15));
+
/* RFSW Control - clear bit 14 ?? */
if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E &&
- priv->rtl_chip != RTL8188E && priv->rtl_chip != RTL8710B)
+ priv->rtl_chip != RTL8188E && priv->rtl_chip != RTL8710B &&
+ priv->rtl_chip != RTL8192F)
rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
@@ -4052,7 +4126,7 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
/* 0x860[6:5]= 00 - why? - this sets antenna B */
if (priv->rtl_chip != RTL8192E && priv->rtl_chip != RTL8188E &&
- priv->rtl_chip != RTL8710B)
+ priv->rtl_chip != RTL8710B && priv->rtl_chip != RTL8192F)
rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66f60210);
if (!macpower) {
@@ -4126,7 +4200,7 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
rtl8xxxu_write8(priv, 0xa3, val8);
}
- if (priv->rtl_chip == RTL8710B)
+ if (priv->rtl_chip == RTL8710B || priv->rtl_chip == RTL8192F)
rtl8xxxu_write8(priv, REG_EARLY_MODE_CONTROL_8710B, 0);
}
@@ -4153,7 +4227,7 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, val8);
} else if (priv->rtl_chip == RTL8710B) {
rtl8xxxu_write32(priv, REG_HIMR0_8710B, 0);
- } else {
+ } else if (priv->rtl_chip != RTL8192F) {
/*
* Enable all interrupts - not obvious USB needs to do this
*/
@@ -4242,7 +4316,8 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
- if (priv->rtl_chip != RTL8188F && priv->rtl_chip != RTL8710B)
+ if (priv->rtl_chip != RTL8188F && priv->rtl_chip != RTL8710B &&
+ priv->rtl_chip != RTL8192F)
/* Firmware will control REG_DRVERLYINT when power saving is enable, */
/* so don't set this register on STA mode. */
rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
@@ -4293,7 +4368,8 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
/* Disable BAR - not sure if this has any effect on USB */
rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
- if (priv->rtl_chip != RTL8188F && priv->rtl_chip != RTL8188E && priv->rtl_chip != RTL8710B)
+ if (priv->rtl_chip != RTL8188F && priv->rtl_chip != RTL8188E &&
+ priv->rtl_chip != RTL8710B && priv->rtl_chip != RTL8192F)
rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
if (fops->init_statistics)
@@ -4311,9 +4387,10 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
* Reset USB mode switch setting
*/
rtl8xxxu_write8(priv, REG_ACLK_MON, 0x00);
- } else if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8188E) {
+ } else if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8188E ||
+ priv->rtl_chip == RTL8192F) {
/*
- * Init GPIO settings for 8188f, 8188e
+ * Init GPIO settings for 8188f, 8188e, 8192f
*/
val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
val8 &= ~GPIO_MUXCFG_IO_SEL_ENBT;
@@ -4433,6 +4510,8 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
if (priv->rtl_chip == RTL8188E)
rtl8188e_ra_info_init_all(&priv->ra_info);
+ set_bit(RTL8XXXU_BC_MC_MACID, priv->mac_id_map);
+
exit:
return ret;
}
@@ -4490,6 +4569,16 @@ int rtl8xxxu_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
return 0;
}
+static int rtl8xxxu_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
+ bool set)
+{
+ struct rtl8xxxu_priv *priv = hw->priv;
+
+ schedule_work(&priv->update_beacon_work);
+
+ return 0;
+}
+
static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
struct ieee80211_vif *vif, const u8 *mac)
{
@@ -4513,7 +4602,8 @@ static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
}
void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
- u32 ramask, u8 rateid, int sgi, int txbw_40mhz)
+ u32 ramask, u8 rateid, int sgi, int txbw_40mhz,
+ u8 macid)
{
struct h2c_cmd h2c;
@@ -4533,7 +4623,8 @@ void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
}
void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv,
- u32 ramask, u8 rateid, int sgi, int txbw_40mhz)
+ u32 ramask, u8 rateid, int sgi, int txbw_40mhz,
+ u8 macid)
{
struct h2c_cmd h2c;
u8 bw;
@@ -4550,6 +4641,7 @@ void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv,
h2c.b_macid_cfg.ramask1 = (ramask >> 8) & 0xff;
h2c.b_macid_cfg.ramask2 = (ramask >> 16) & 0xff;
h2c.b_macid_cfg.ramask3 = (ramask >> 24) & 0xff;
+ h2c.b_macid_cfg.macid = macid;
h2c.b_macid_cfg.data1 = rateid;
if (sgi)
@@ -4563,7 +4655,7 @@ void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv,
}
void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv,
- u8 macid, bool connect)
+ u8 macid, u8 role, bool connect)
{
struct h2c_cmd h2c;
@@ -4580,7 +4672,7 @@ void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv,
}
void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv,
- u8 macid, bool connect)
+ u8 macid, u8 role, bool connect)
{
/*
* The firmware turns on the rate control when it knows it's
@@ -4596,6 +4688,9 @@ void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv,
else
h2c.media_status_rpt.parm &= ~BIT(0);
+ h2c.media_status_rpt.parm |= ((role << 4) & 0xf0);
+ h2c.media_status_rpt.macid = macid;
+
rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.media_status_rpt));
}
@@ -4912,7 +5007,8 @@ rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
priv->vif = vif;
priv->rssi_level = RTL8XXXU_RATR_STA_INIT;
- priv->fops->update_rate_mask(priv, ramask, 0, sgi, bw == RATE_INFO_BW_40);
+ priv->fops->update_rate_mask(priv, ramask, 0, sgi,
+ bw == RATE_INFO_BW_40, 0);
rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
@@ -4922,13 +5018,13 @@ rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
0xc000 | vif->cfg.aid);
- priv->fops->report_connect(priv, 0, true);
+ priv->fops->report_connect(priv, 0, H2C_MACID_ROLE_AP, true);
} else {
val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
val8 |= BEACON_DISABLE_TSF_UPDATE;
rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
- priv->fops->report_connect(priv, 0, false);
+ priv->fops->report_connect(priv, 0, H2C_MACID_ROLE_AP, false);
}
}
@@ -4965,10 +5061,35 @@ rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
dev_dbg(dev, "Changed BASIC_RATES!\n");
rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
}
+
+ if (changed & BSS_CHANGED_BEACON_ENABLED) {
+ if (bss_conf->enable_beacon)
+ rtl8xxxu_start_tx_beacon(priv);
+ else
+ rtl8xxxu_stop_tx_beacon(priv);
+ }
+
+ if (changed & BSS_CHANGED_BEACON)
+ schedule_work(&priv->update_beacon_work);
+
error:
return;
}
+static int rtl8xxxu_start_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
+ struct ieee80211_bss_conf *link_conf)
+{
+ struct rtl8xxxu_priv *priv = hw->priv;
+ struct device *dev = &priv->udev->dev;
+
+ dev_dbg(dev, "Start AP mode\n");
+ rtl8xxxu_set_bssid(priv, vif->bss_conf.bssid);
+ rtl8xxxu_write16(priv, REG_BCN_INTERVAL, vif->bss_conf.beacon_int);
+ priv->fops->report_connect(priv, RTL8XXXU_BC_MC_MACID, 0, true);
+
+ return 0;
+}
+
static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
{
u32 rtlqueue;
@@ -4997,7 +5118,9 @@ static u32 rtl8xxxu_queue_select(struct ieee80211_hdr *hdr, struct sk_buff *skb)
{
u32 queue;
- if (ieee80211_is_mgmt(hdr->frame_control))
+ if (unlikely(ieee80211_is_beacon(hdr->frame_control)))
+ queue = TXDESC_QUEUE_BEACON;
+ else if (ieee80211_is_mgmt(hdr->frame_control))
queue = TXDESC_QUEUE_MGNT;
else
queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
@@ -5160,23 +5283,16 @@ void
rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
struct ieee80211_tx_info *tx_info,
struct rtl8xxxu_txdesc32 *tx_desc, bool sgi,
- bool short_preamble, bool ampdu_enable, u32 rts_rate)
+ bool short_preamble, bool ampdu_enable, u32 rts_rate,
+ u8 macid)
{
- struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
struct rtl8xxxu_priv *priv = hw->priv;
struct device *dev = &priv->udev->dev;
u8 *qc = ieee80211_get_qos_ctl(hdr);
u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
- u32 rate;
- u16 rate_flags = tx_info->control.rates[0].flags;
+ u32 rate = 0;
u16 seq_number;
- if (rate_flags & IEEE80211_TX_RC_MCS &&
- !ieee80211_is_mgmt(hdr->frame_control))
- rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
- else
- rate = tx_rate->hw_value;
-
if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
dev_info(dev, "%s: TX rate: %d, pkt size %u\n",
__func__, rate, le16_to_cpu(tx_desc->pkt_size));
@@ -5215,10 +5331,10 @@ rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
* rts_rate is zero if RTS/CTS or CTS to SELF are not enabled
*/
tx_desc->txdw4 |= cpu_to_le32(rts_rate << TXDESC32_RTS_RATE_SHIFT);
- if (ampdu_enable || (rate_flags & IEEE80211_TX_RC_USE_RTS_CTS)) {
+ if (ampdu_enable || tx_info->control.use_rts) {
tx_desc->txdw4 |= cpu_to_le32(TXDESC32_RTS_CTS_ENABLE);
tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
- } else if (rate_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
+ } else if (tx_info->control.use_cts_prot) {
tx_desc->txdw4 |= cpu_to_le32(TXDESC32_CTS_SELF_ENABLE);
tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
}
@@ -5232,30 +5348,25 @@ void
rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
struct ieee80211_tx_info *tx_info,
struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi,
- bool short_preamble, bool ampdu_enable, u32 rts_rate)
+ bool short_preamble, bool ampdu_enable, u32 rts_rate,
+ u8 macid)
{
- struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
struct rtl8xxxu_priv *priv = hw->priv;
struct device *dev = &priv->udev->dev;
struct rtl8xxxu_txdesc40 *tx_desc40;
u8 *qc = ieee80211_get_qos_ctl(hdr);
u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
- u32 rate;
- u16 rate_flags = tx_info->control.rates[0].flags;
+ u32 rate = 0;
u16 seq_number;
tx_desc40 = (struct rtl8xxxu_txdesc40 *)tx_desc32;
- if (rate_flags & IEEE80211_TX_RC_MCS &&
- !ieee80211_is_mgmt(hdr->frame_control))
- rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
- else
- rate = tx_rate->hw_value;
-
if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
dev_info(dev, "%s: TX rate: %d, pkt size %u\n",
__func__, rate, le16_to_cpu(tx_desc40->pkt_size));
+ tx_desc40->txdw1 |= cpu_to_le32(macid << TXDESC40_MACID_SHIFT);
+
seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
tx_desc40->txdw4 = cpu_to_le32(rate);
@@ -5279,17 +5390,21 @@ rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
tx_desc40->txdw4 |= cpu_to_le32(TXDESC40_RETRY_LIMIT_ENABLE);
}
+ if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)
+ tx_desc40->txdw8 |= cpu_to_le32(TXDESC40_HW_SEQ_ENABLE);
+
if (short_preamble)
tx_desc40->txdw5 |= cpu_to_le32(TXDESC40_SHORT_PREAMBLE);
tx_desc40->txdw4 |= cpu_to_le32(rts_rate << TXDESC40_RTS_RATE_SHIFT);
+
/*
* rts_rate is zero if RTS/CTS or CTS to SELF are not enabled
*/
- if (ampdu_enable || (rate_flags & IEEE80211_TX_RC_USE_RTS_CTS)) {
+ if (ampdu_enable || tx_info->control.use_rts) {
tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_RTS_CTS_ENABLE);
tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_HW_RTS_ENABLE);
- } else if (rate_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
+ } else if (tx_info->control.use_cts_prot) {
/*
* For some reason the vendor driver doesn't set
* TXDESC40_HW_RTS_ENABLE for CTS to SELF
@@ -5307,24 +5422,17 @@ void
rtl8xxxu_fill_txdesc_v3(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
struct ieee80211_tx_info *tx_info,
struct rtl8xxxu_txdesc32 *tx_desc, bool sgi,
- bool short_preamble, bool ampdu_enable, u32 rts_rate)
+ bool short_preamble, bool ampdu_enable, u32 rts_rate,
+ u8 macid)
{
- struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
struct rtl8xxxu_priv *priv = hw->priv;
struct device *dev = &priv->udev->dev;
struct rtl8xxxu_ra_info *ra = &priv->ra_info;
u8 *qc = ieee80211_get_qos_ctl(hdr);
u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
- u32 rate;
- u16 rate_flags = tx_info->control.rates[0].flags;
+ u32 rate = 0;
u16 seq_number;
- if (rate_flags & IEEE80211_TX_RC_MCS &&
- !ieee80211_is_mgmt(hdr->frame_control))
- rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
- else
- rate = tx_rate->hw_value;
-
seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
if (ieee80211_is_data(hdr->frame_control)) {
@@ -5377,10 +5485,10 @@ rtl8xxxu_fill_txdesc_v3(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
* rts_rate is zero if RTS/CTS or CTS to SELF are not enabled
*/
tx_desc->txdw4 |= cpu_to_le32(rts_rate << TXDESC32_RTS_RATE_SHIFT);
- if (ampdu_enable || (rate_flags & IEEE80211_TX_RC_USE_RTS_CTS)) {
+ if (ampdu_enable || tx_info->control.use_rts) {
tx_desc->txdw4 |= cpu_to_le32(TXDESC32_RTS_CTS_ENABLE);
tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
- } else if (rate_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
+ } else if (tx_info->control.use_cts_prot) {
tx_desc->txdw4 |= cpu_to_le32(TXDESC32_CTS_SELF_ENABLE);
tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
}
@@ -5404,8 +5512,8 @@ static void rtl8xxxu_tx(struct ieee80211_hw *hw,
struct device *dev = &priv->udev->dev;
u32 queue, rts_rate;
u16 pktlen = skb->len;
- u16 rate_flag = tx_info->control.rates[0].flags;
int tx_desc_size = priv->fops->tx_desc_size;
+ u8 macid;
int ret;
bool ampdu_enable, sgi = false, short_preamble = false;
@@ -5444,8 +5552,10 @@ static void rtl8xxxu_tx(struct ieee80211_hw *hw,
tx_desc->pkt_size = cpu_to_le16(pktlen);
tx_desc->pkt_offset = tx_desc_size;
- tx_desc->txdw0 =
- TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
+ /* These bits mean different things to the RTL8192F. */
+ if (priv->rtl_chip != RTL8192F)
+ tx_desc->txdw0 =
+ TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
@@ -5488,31 +5598,34 @@ static void rtl8xxxu_tx(struct ieee80211_hw *hw,
}
}
- if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
- (ieee80211_is_data_qos(hdr->frame_control) &&
- sta && sta->deflink.ht_cap.cap &
- (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20)))
+ if (ieee80211_is_data_qos(hdr->frame_control) &&
+ sta && sta->deflink.ht_cap.cap &
+ (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
sgi = true;
- if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
- (sta && vif && vif->bss_conf.use_short_preamble))
+ if (sta && vif && vif->bss_conf.use_short_preamble)
short_preamble = true;
- if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS)
- rts_rate = ieee80211_get_rts_cts_rate(hw, tx_info)->hw_value;
- else if (rate_flag & IEEE80211_TX_RC_USE_CTS_PROTECT)
- rts_rate = ieee80211_get_rts_cts_rate(hw, tx_info)->hw_value;
+ if (skb->len > hw->wiphy->rts_threshold)
+ tx_info->control.use_rts = true;
+
+ if (sta && vif && vif->bss_conf.use_cts_prot)
+ tx_info->control.use_cts_prot = true;
+
+ if (ampdu_enable || tx_info->control.use_rts ||
+ tx_info->control.use_cts_prot)
+ rts_rate = DESC_RATE_24M;
else
rts_rate = 0;
-
+ macid = rtl8xxxu_get_macid(priv, sta);
priv->fops->fill_txdesc(hw, hdr, tx_info, tx_desc, sgi, short_preamble,
- ampdu_enable, rts_rate);
+ ampdu_enable, rts_rate, macid);
rtl8xxxu_calc_tx_desc_csum(tx_desc);
/* avoid zero checksum make tx hang */
- if (priv->rtl_chip == RTL8710B)
+ if (priv->rtl_chip == RTL8710B || priv->rtl_chip == RTL8192F)
tx_desc->csum = ~tx_desc->csum;
usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
@@ -5530,6 +5643,55 @@ error:
dev_kfree_skb(skb);
}
+static void rtl8xxxu_send_beacon_frame(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif)
+{
+ struct rtl8xxxu_priv *priv = hw->priv;
+ struct sk_buff *skb = ieee80211_beacon_get(hw, vif, 0);
+ struct device *dev = &priv->udev->dev;
+ int retry;
+ u8 val8;
+
+ /* BCN_VALID, write 1 to clear, cleared by SW */
+ val8 = rtl8xxxu_read8(priv, REG_TDECTRL + 2);
+ val8 |= BIT_BCN_VALID >> 16;
+ rtl8xxxu_write8(priv, REG_TDECTRL + 2, val8);
+
+ /* SW_BCN_SEL - Port0 */
+ val8 = rtl8xxxu_read8(priv, REG_DWBCN1_CTRL_8723B + 2);
+ val8 &= ~(BIT_SW_BCN_SEL >> 16);
+ rtl8xxxu_write8(priv, REG_DWBCN1_CTRL_8723B + 2, val8);
+
+ if (skb)
+ rtl8xxxu_tx(hw, NULL, skb);
+
+ retry = 100;
+ do {
+ val8 = rtl8xxxu_read8(priv, REG_TDECTRL + 2);
+ if (val8 & (BIT_BCN_VALID >> 16))
+ break;
+ usleep_range(10, 20);
+ } while (--retry);
+
+ if (!retry)
+ dev_err(dev, "%s: Failed to read beacon valid bit\n", __func__);
+}
+
+static void rtl8xxxu_update_beacon_work_callback(struct work_struct *work)
+{
+ struct rtl8xxxu_priv *priv =
+ container_of(work, struct rtl8xxxu_priv, update_beacon_work);
+ struct ieee80211_hw *hw = priv->hw;
+ struct ieee80211_vif *vif = priv->vif;
+
+ if (!vif) {
+ WARN_ONCE(true, "no vif to update beacon\n");
+ return;
+ }
+
+ rtl8xxxu_send_beacon_frame(hw, vif);
+}
+
void rtl8723au_rx_parse_phystats(struct rtl8xxxu_priv *priv,
struct ieee80211_rx_status *rx_status,
struct rtl8723au_phy_stats *phy_stats,
@@ -6198,61 +6360,98 @@ int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb)
int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb)
{
struct ieee80211_hw *hw = priv->hw;
- struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
- struct rtl8xxxu_rxdesc24 *rx_desc =
- (struct rtl8xxxu_rxdesc24 *)skb->data;
+ struct ieee80211_rx_status *rx_status;
+ struct rtl8xxxu_rxdesc24 *rx_desc;
struct rtl8723au_phy_stats *phy_stats;
- __le32 *_rx_desc_le = (__le32 *)skb->data;
- u32 *_rx_desc = (u32 *)skb->data;
+ struct sk_buff *next_skb = NULL;
+ __le32 *_rx_desc_le;
+ u32 *_rx_desc;
int drvinfo_sz, desc_shift;
- int i;
+ int i, pkt_len, urb_len, pkt_offset;
- for (i = 0; i < (sizeof(struct rtl8xxxu_rxdesc24) / sizeof(u32)); i++)
- _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
+ urb_len = skb->len;
- memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
+ if (urb_len < sizeof(struct rtl8xxxu_rxdesc24)) {
+ kfree_skb(skb);
+ return RX_TYPE_ERROR;
+ }
- skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc24));
+ do {
+ rx_desc = (struct rtl8xxxu_rxdesc24 *)skb->data;
+ _rx_desc_le = (__le32 *)skb->data;
+ _rx_desc = (u32 *)skb->data;
- phy_stats = (struct rtl8723au_phy_stats *)skb->data;
+ for (i = 0; i < (sizeof(struct rtl8xxxu_rxdesc24) / sizeof(u32)); i++)
+ _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
- drvinfo_sz = rx_desc->drvinfo_sz * 8;
- desc_shift = rx_desc->shift;
- skb_pull(skb, drvinfo_sz + desc_shift);
+ pkt_len = rx_desc->pktlen;
- if (rx_desc->rpt_sel) {
- struct device *dev = &priv->udev->dev;
- dev_dbg(dev, "%s: C2H packet\n", __func__);
- rtl8723bu_handle_c2h(priv, skb);
- return RX_TYPE_C2H;
- }
+ drvinfo_sz = rx_desc->drvinfo_sz * 8;
+ desc_shift = rx_desc->shift;
+ pkt_offset = roundup(pkt_len + drvinfo_sz + desc_shift +
+ sizeof(struct rtl8xxxu_rxdesc24), 8);
+
+ /*
+ * Only clone the skb if there's enough data at the end to
+ * at least cover the rx descriptor
+ */
+ if (urb_len >= (pkt_offset + sizeof(struct rtl8xxxu_rxdesc24)))
+ next_skb = skb_clone(skb, GFP_ATOMIC);
- if (rx_desc->phy_stats)
- priv->fops->parse_phystats(priv, rx_status, phy_stats,
- rx_desc->rxmcs, (struct ieee80211_hdr *)skb->data,
- rx_desc->crc32 || rx_desc->icverr);
+ rx_status = IEEE80211_SKB_RXCB(skb);
+ memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
- rx_status->mactime = rx_desc->tsfl;
- rx_status->flag |= RX_FLAG_MACTIME_START;
+ skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc24));
- if (!rx_desc->swdec)
- rx_status->flag |= RX_FLAG_DECRYPTED;
- if (rx_desc->crc32)
- rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
- if (rx_desc->bw)
- rx_status->bw = RATE_INFO_BW_40;
+ phy_stats = (struct rtl8723au_phy_stats *)skb->data;
- if (rx_desc->rxmcs >= DESC_RATE_MCS0) {
- rx_status->encoding = RX_ENC_HT;
- rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
- } else {
- rx_status->rate_idx = rx_desc->rxmcs;
- }
+ skb_pull(skb, drvinfo_sz + desc_shift);
- rx_status->freq = hw->conf.chandef.chan->center_freq;
- rx_status->band = hw->conf.chandef.chan->band;
+ skb_trim(skb, pkt_len);
+
+ if (rx_desc->rpt_sel) {
+ struct device *dev = &priv->udev->dev;
+ dev_dbg(dev, "%s: C2H packet\n", __func__);
+ rtl8723bu_handle_c2h(priv, skb);
+ } else {
+ struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
+
+ if (rx_desc->phy_stats)
+ priv->fops->parse_phystats(priv, rx_status, phy_stats,
+ rx_desc->rxmcs, hdr,
+ rx_desc->crc32 || rx_desc->icverr);
+
+ rx_status->mactime = rx_desc->tsfl;
+ rx_status->flag |= RX_FLAG_MACTIME_START;
+
+ if (!rx_desc->swdec)
+ rx_status->flag |= RX_FLAG_DECRYPTED;
+ if (rx_desc->crc32)
+ rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
+ if (rx_desc->bw)
+ rx_status->bw = RATE_INFO_BW_40;
+
+ if (rx_desc->rxmcs >= DESC_RATE_MCS0) {
+ rx_status->encoding = RX_ENC_HT;
+ rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
+ } else {
+ rx_status->rate_idx = rx_desc->rxmcs;
+ }
+
+ rx_status->freq = hw->conf.chandef.chan->center_freq;
+ rx_status->band = hw->conf.chandef.chan->band;
+
+ ieee80211_rx_irqsafe(hw, skb);
+ }
+
+ skb = next_skb;
+ if (skb)
+ skb_pull(next_skb, pkt_offset);
+
+ urb_len -= pkt_offset;
+ next_skb = NULL;
+ } while (skb && urb_len >= sizeof(struct rtl8xxxu_rxdesc24));
- ieee80211_rx_irqsafe(hw, skb);
return RX_TYPE_DATA_PKT;
}
@@ -6282,7 +6481,6 @@ static void rtl8xxxu_rx_complete(struct urb *urb)
cleanup:
usb_free_urb(urb);
dev_kfree_skb(skb);
- return;
}
static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
@@ -6372,12 +6570,13 @@ static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
int ret;
u8 val8;
+ if (!priv->vif)
+ priv->vif = vif;
+ else
+ return -EOPNOTSUPP;
+
switch (vif->type) {
case NL80211_IFTYPE_STATION:
- if (!priv->vif)
- priv->vif = vif;
- else
- return -EOPNOTSUPP;
rtl8xxxu_stop_tx_beacon(priv);
val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
@@ -6386,11 +6585,33 @@ static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
ret = 0;
break;
+ case NL80211_IFTYPE_AP:
+ rtl8xxxu_write8(priv, REG_BEACON_CTRL,
+ BEACON_DISABLE_TSF_UPDATE | BEACON_CTRL_MBSSID);
+ rtl8xxxu_write8(priv, REG_ATIMWND, 0x0c); /* 12ms */
+ rtl8xxxu_write16(priv, REG_TSFTR_SYN_OFFSET, 0x7fff); /* ~32ms */
+ rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, DUAL_TSF_RESET_TSF0);
+
+ /* enable BCN0 function */
+ rtl8xxxu_write8(priv, REG_BEACON_CTRL,
+ BEACON_DISABLE_TSF_UPDATE |
+ BEACON_FUNCTION_ENABLE | BEACON_CTRL_MBSSID |
+ BEACON_CTRL_TX_BEACON_RPT);
+
+ /* select BCN on port 0 */
+ val8 = rtl8xxxu_read8(priv, REG_CCK_CHECK);
+ val8 &= ~BIT_BCN_PORT_SEL;
+ rtl8xxxu_write8(priv, REG_CCK_CHECK, val8);
+
+ ret = 0;
+ break;
default:
ret = -EOPNOTSUPP;
}
rtl8xxxu_set_linktype(priv, vif->type);
+ ether_addr_copy(priv->mac_addr, vif->addr);
+ rtl8xxxu_set_mac(priv);
return ret;
}
@@ -6521,22 +6742,22 @@ static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
*/
if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
- rcr &= ~RCR_CHECK_BSSID_BEACON;
+ rcr &= ~(RCR_CHECK_BSSID_BEACON | RCR_CHECK_BSSID_MATCH);
else
- rcr |= RCR_CHECK_BSSID_BEACON;
+ rcr |= RCR_CHECK_BSSID_BEACON | RCR_CHECK_BSSID_MATCH;
+
+ if (priv->vif && priv->vif->type == NL80211_IFTYPE_AP)
+ rcr &= ~RCR_CHECK_BSSID_MATCH;
if (*total_flags & FIF_CONTROL)
rcr |= RCR_ACCEPT_CTRL_FRAME;
else
rcr &= ~RCR_ACCEPT_CTRL_FRAME;
- if (*total_flags & FIF_OTHER_BSS) {
+ if (*total_flags & FIF_OTHER_BSS)
rcr |= RCR_ACCEPT_AP;
- rcr &= ~RCR_CHECK_BSSID_MATCH;
- } else {
+ else
rcr &= ~RCR_ACCEPT_AP;
- rcr |= RCR_CHECK_BSSID_MATCH;
- }
if (*total_flags & FIF_PSPOLL)
rcr |= RCR_ACCEPT_PM;
@@ -6557,7 +6778,7 @@ static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
{
- if (rts > 2347)
+ if (rts > 2347 && rts != (u32)-1)
return -EINVAL;
return 0;
@@ -6706,7 +6927,8 @@ static u8 rtl8xxxu_signal_to_snr(int signal)
}
static void rtl8xxxu_refresh_rate_mask(struct rtl8xxxu_priv *priv,
- int signal, struct ieee80211_sta *sta)
+ int signal, struct ieee80211_sta *sta,
+ bool force)
{
struct ieee80211_hw *hw = priv->hw;
u16 wireless_mode;
@@ -6714,6 +6936,7 @@ static void rtl8xxxu_refresh_rate_mask(struct rtl8xxxu_priv *priv,
u8 txbw_40mhz;
u8 snr, snr_thresh_high, snr_thresh_low;
u8 go_up_gap = 5;
+ u8 macid = rtl8xxxu_get_macid(priv, sta);
rssi_level = priv->rssi_level;
snr = rtl8xxxu_signal_to_snr(signal);
@@ -6740,7 +6963,7 @@ static void rtl8xxxu_refresh_rate_mask(struct rtl8xxxu_priv *priv,
else
rssi_level = RTL8XXXU_RATR_STA_LOW;
- if (rssi_level != priv->rssi_level) {
+ if (rssi_level != priv->rssi_level || force) {
int sgi = 0;
u32 rate_bitmap = 0;
@@ -6833,7 +7056,7 @@ static void rtl8xxxu_refresh_rate_mask(struct rtl8xxxu_priv *priv,
}
priv->rssi_level = rssi_level;
- priv->fops->update_rate_mask(priv, rate_bitmap, ratr_idx, sgi, txbw_40mhz);
+ priv->fops->update_rate_mask(priv, rate_bitmap, ratr_idx, sgi, txbw_40mhz, macid);
}
}
@@ -6956,7 +7179,7 @@ static void rtl8xxxu_watchdog_callback(struct work_struct *work)
if (priv->fops->set_crystal_cap)
rtl8xxxu_track_cfo(priv);
- rtl8xxxu_refresh_rate_mask(priv, signal, sta);
+ rtl8xxxu_refresh_rate_mask(priv, signal, sta, false);
}
out:
@@ -7087,6 +7310,38 @@ static void rtl8xxxu_stop(struct ieee80211_hw *hw)
rtl8xxxu_free_tx_resources(priv);
}
+static int rtl8xxxu_sta_add(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif,
+ struct ieee80211_sta *sta)
+{
+ struct rtl8xxxu_sta_info *sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv;
+ struct rtl8xxxu_priv *priv = hw->priv;
+
+ if (vif->type == NL80211_IFTYPE_AP) {
+ sta_info->macid = rtl8xxxu_acquire_macid(priv);
+ if (sta_info->macid >= RTL8XXXU_MAX_MAC_ID_NUM)
+ return -ENOSPC;
+
+ rtl8xxxu_refresh_rate_mask(priv, 0, sta, true);
+ priv->fops->report_connect(priv, sta_info->macid, H2C_MACID_ROLE_STA, true);
+ }
+
+ return 0;
+}
+
+static int rtl8xxxu_sta_remove(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif,
+ struct ieee80211_sta *sta)
+{
+ struct rtl8xxxu_sta_info *sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv;
+ struct rtl8xxxu_priv *priv = hw->priv;
+
+ if (vif->type == NL80211_IFTYPE_AP)
+ rtl8xxxu_release_macid(priv, sta_info->macid);
+
+ return 0;
+}
+
static const struct ieee80211_ops rtl8xxxu_ops = {
.tx = rtl8xxxu_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
@@ -7095,6 +7350,7 @@ static const struct ieee80211_ops rtl8xxxu_ops = {
.config = rtl8xxxu_config,
.conf_tx = rtl8xxxu_conf_tx,
.bss_info_changed = rtl8xxxu_bss_info_changed,
+ .start_ap = rtl8xxxu_start_ap,
.configure_filter = rtl8xxxu_configure_filter,
.set_rts_threshold = rtl8xxxu_set_rts_threshold,
.start = rtl8xxxu_start,
@@ -7105,6 +7361,9 @@ static const struct ieee80211_ops rtl8xxxu_ops = {
.ampdu_action = rtl8xxxu_ampdu_action,
.sta_statistics = rtl8xxxu_sta_statistics,
.get_antenna = rtl8xxxu_get_antenna,
+ .set_tim = rtl8xxxu_set_tim,
+ .sta_add = rtl8xxxu_sta_add,
+ .sta_remove = rtl8xxxu_sta_remove,
};
static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
@@ -7240,6 +7499,7 @@ static int rtl8xxxu_probe(struct usb_interface *interface,
case 0xf179:
case 0x8179:
case 0xb711:
+ case 0xf192:
untested = 0;
break;
}
@@ -7264,6 +7524,10 @@ static int rtl8xxxu_probe(struct usb_interface *interface,
if (id->idProduct == 0x0109)
untested = 0;
break;
+ case 0x0b05:
+ if (id->idProduct == 0x18f1)
+ untested = 0;
+ break;
default:
break;
}
@@ -7296,6 +7560,7 @@ static int rtl8xxxu_probe(struct usb_interface *interface,
spin_lock_init(&priv->rx_urb_lock);
INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
INIT_DELAYED_WORK(&priv->ra_watchdog, rtl8xxxu_watchdog_callback);
+ INIT_WORK(&priv->update_beacon_work, rtl8xxxu_update_beacon_work_callback);
skb_queue_head_init(&priv->c2hcmd_queue);
usb_set_intfdata(interface, hw);
@@ -7347,7 +7612,11 @@ static int rtl8xxxu_probe(struct usb_interface *interface,
hw->wiphy->max_scan_ssids = 1;
hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
+ if (priv->fops->max_macid_num)
+ hw->wiphy->max_ap_assoc_sta = priv->fops->max_macid_num - 1;
hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
+ if (priv->fops->supports_ap)
+ hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP);
hw->queues = 4;
sband = &rtl8xxxu_supported_band;
@@ -7525,6 +7794,16 @@ static const struct usb_device_id dev_table[] = {
/* TOTOLINK N150UA V5 / N150UA-B */
{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2005, 0xff, 0xff, 0xff),
.driver_info = (unsigned long)&rtl8710bu_fops},
+/* Comfast CF-826F */
+{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xf192, 0xff, 0xff, 0xff),
+ .driver_info = (unsigned long)&rtl8192fu_fops},
+/* Asus USB-N13 rev C1 */
+{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x18f1, 0xff, 0xff, 0xff),
+ .driver_info = (unsigned long)&rtl8192fu_fops},
+{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xb722, 0xff, 0xff, 0xff),
+ .driver_info = (unsigned long)&rtl8192fu_fops},
+{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x318b, 0xff, 0xff, 0xff),
+ .driver_info = (unsigned long)&rtl8192fu_fops},
#ifdef CONFIG_RTL8XXXU_UNTESTED
/* Still supported by rtlwifi */
{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h
index 4dffbab494c3..920ee50e2115 100644
--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h
+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h
@@ -67,6 +67,7 @@
#define REG_SPS0_CTRL 0x0011
#define REG_SPS_OCP_CFG 0x0018
#define REG_8192E_LDOV12_CTRL 0x0014
+#define REG_SYS_SWR_CTRL2 0x0014
#define REG_RSV_CTRL 0x001c
#define RSV_CTRL_WLOCK_1C BIT(5)
#define RSV_CTRL_DIS_PRST BIT(6)
@@ -215,6 +216,8 @@
#define REG_HMBOX_EXT_2 0x008c
#define REG_HMBOX_EXT_3 0x008e
+#define REG_RSVD_1 0x0097
+
/* Interrupt registers for 8192e/8723bu/8812 */
#define REG_HIMR0 0x00b0
#define IMR0_TXCCK BIT(30) /* TXRPT interrupt when CCX bit
@@ -283,6 +286,7 @@
#define REG_BIST_SCAN 0x00d0
#define REG_BIST_RPT 0x00d4
#define REG_BIST_ROM_RPT 0x00d8
+#define REG_RSVD_4 0x00dc
#define REG_USB_SIE_INTF 0x00e0
#define REG_PCIE_MIO_INTF 0x00e4
#define REG_PCIE_MIO_INTD 0x00e8
@@ -390,6 +394,12 @@
#define TRXDMA_CTRL_BKQ_SHIFT 10
#define TRXDMA_CTRL_MGQ_SHIFT 12
#define TRXDMA_CTRL_HIQ_SHIFT 14
+#define TRXDMA_CTRL_VOQ_SHIFT_8192F 4
+#define TRXDMA_CTRL_VIQ_SHIFT_8192F 7
+#define TRXDMA_CTRL_BEQ_SHIFT_8192F 10
+#define TRXDMA_CTRL_BKQ_SHIFT_8192F 13
+#define TRXDMA_CTRL_MGQ_SHIFT_8192F 16
+#define TRXDMA_CTRL_HIQ_SHIFT_8192F 19
#define TRXDMA_QUEUE_LOW 1
#define TRXDMA_QUEUE_NORMAL 2
#define TRXDMA_QUEUE_HIGH 3
@@ -439,7 +449,7 @@
#define LLT_OP_READ (0x2 << 30)
#define LLT_OP_MASK (0x3 << 30)
-#define REG_BB_ACCEESS_CTRL 0x01e8
+#define REG_BB_ACCESS_CTRL 0x01e8
#define REG_BB_ACCESS_DATA 0x01ec
#define REG_HMBOX_EXT0_8723B 0x01f0
@@ -456,6 +466,7 @@
#define REG_FIFOPAGE 0x0204
#define REG_TDECTRL 0x0208
+#define BIT_BCN_VALID BIT(16)
#define REG_DWBCN0_CTRL_8188F REG_TDECTRL
@@ -470,6 +481,7 @@
#define AUTO_LLT_INIT_LLT BIT(16)
#define REG_DWBCN1_CTRL_8723B 0x0228
+#define BIT_SW_BCN_SEL BIT(20)
/* 0x0280 ~ 0x02FF RXDMA Configuration */
#define REG_RXDMA_AGG_PG_TH 0x0280 /* 0-7 : USB DMA size bits
@@ -516,6 +528,7 @@
#define REG_FWHW_TXQ_CTRL 0x0420
#define FWHW_TXQ_CTRL_AMPDU_RETRY BIT(7)
#define FWHW_TXQ_CTRL_XMIT_MGMT_ACK BIT(12)
+#define EN_BCNQ_DL BIT(22)
#define REG_HWSEQ_CTRL 0x0423
#define REG_TXPKTBUF_BCNQ_BDNY 0x0424
@@ -572,6 +585,8 @@
#define REG_ARFR1 0x0448
#define REG_ARFR2 0x044c
#define REG_ARFR3 0x0450
+#define REG_CCK_CHECK 0x0454
+#define BIT_BCN_PORT_SEL BIT(5)
#define REG_AMPDU_MAX_TIME_8723B 0x0456
#define REG_AGGLEN_LMT 0x0458
#define REG_AMPDU_MIN_SPACE 0x045c
@@ -968,12 +983,18 @@
#define FPGA1_TX_OFDM_TXSC_MASK 0x30000000
#define REG_ANT_MAPPING1 0x0914
+#define REG_RFE_OPT 0x0920
#define REG_DPDT_CTRL 0x092c /* 8723BU */
#define REG_RFE_CTRL_ANTA_SRC 0x0930 /* 8723BU */
+#define REG_RFE_CTRL_ANT_SRC1 0x0934
+#define REG_RFE_CTRL_ANT_SRC2 0x0938
+#define REG_RFE_CTRL_ANT_SRC3 0x093c
#define REG_RFE_PATH_SELECT 0x0940 /* 8723BU */
#define REG_RFE_BUFFER 0x0944 /* 8723BU */
#define REG_S0S1_PATH_SWITCH 0x0948 /* 8723BU */
+#define REG_RX_DFIR_MOD_97F 0x0948
#define REG_OFDM_RX_DFIR 0x954
+#define REG_RFE_OPT62 0x0968
#define REG_CCK0_SYSTEM 0x0a00
#define CCK0_SIDEBAND BIT(4)
@@ -1033,6 +1054,8 @@
#define REG_OFDM0_FA_RSTC 0x0c0c
+#define REG_DOWNSAM_FACTOR 0x0c10
+
#define REG_OFDM0_XA_RX_AFE 0x0c10
#define REG_OFDM0_XA_RX_IQ_IMBALANCE 0x0c14
#define REG_OFDM0_XB_RX_IQ_IMBALANCE 0x0c1c
@@ -1054,7 +1077,7 @@
#define REG_OFDM0_AGC_PARM1 0x0c70
-#define REG_OFDM0_AGCR_SSI_TABLE 0x0c78
+#define REG_OFDM0_AGC_RSSI_TABLE 0x0c78
#define REG_OFDM0_XA_TX_IQ_IMBALANCE 0x0c80
#define REG_OFDM0_XB_TX_IQ_IMBALANCE 0x0c88
@@ -1069,6 +1092,8 @@
/* 8188eu */
#define REG_ANTDIV_PARA1 0x0ca4
+#define REG_RXIQB_EXT 0x0ca8
+
/* 8723bu */
#define REG_OFDM0_TX_PSDO_NOISE_WEIGHT 0x0ce4
@@ -1088,6 +1113,8 @@
#define REG_OFDM1_CSI_FIX_MASK1 0x0d40
#define REG_OFDM1_CSI_FIX_MASK2 0x0d44
+#define REG_ANAPWR1 0x0d94
+
#define REG_TX_AGC_A_RATE18_06 0x0e00
#define REG_TX_AGC_A_RATE54_24 0x0e04
#define REG_TX_AGC_A_CCK1_MCS32 0x0e08
@@ -1096,6 +1123,10 @@
#define REG_TX_AGC_A_MCS11_MCS08 0x0e18
#define REG_TX_AGC_A_MCS15_MCS12 0x0e1c
+#define REG_NP_ANTA 0x0e20
+
+#define REG_TAP_UPD_97F 0x0e24
+
#define REG_FPGA0_IQK 0x0e28
#define REG_TX_IQK_TONE_A 0x0e30
@@ -1124,19 +1155,23 @@
#define REG_RX_CCK 0x0e8c
#define REG_TX_POWER_BEFORE_IQK_A 0x0e94
+#define REG_IQK_RPT_TXA 0x0e98
#define REG_TX_POWER_AFTER_IQK_A 0x0e9c
#define REG_RX_POWER_BEFORE_IQK_A 0x0ea0
#define REG_RX_POWER_BEFORE_IQK_A_2 0x0ea4
#define REG_RX_POWER_AFTER_IQK_A 0x0ea8
+#define REG_IQK_RPT_RXA 0x0ea8
#define REG_RX_POWER_AFTER_IQK_A_2 0x0eac
#define REG_TX_POWER_BEFORE_IQK_B 0x0eb4
+#define REG_IQK_RPT_TXB 0x0eb8
#define REG_TX_POWER_AFTER_IQK_B 0x0ebc
#define REG_RX_POWER_BEFORE_IQK_B 0x0ec0
#define REG_RX_POWER_BEFORE_IQK_B_2 0x0ec4
#define REG_RX_POWER_AFTER_IQK_B 0x0ec8
+#define REG_IQK_RPT_RXB 0x0ec8
#define REG_RX_POWER_AFTER_IQK_B_2 0x0ecc
#define REG_RX_OFDM 0x0ed0
@@ -1147,6 +1182,12 @@
#define REG_PMPD_ANAEN 0x0eec
#define REG_FW_START_ADDRESS 0x1000
+#define REG_FW_START_ADDRESS_8192F 0x4000
+
+#define REG_SW_GPIO_SHARE_CTRL_0 0x1038
+#define REG_SW_GPIO_SHARE_CTRL_1 0x103c
+#define REG_GPIO_A0 0x1050
+#define REG_GPIO_B0 0x105b
#define REG_USB_INFO 0xfe17
#define REG_USB_HIMR 0xfe38
@@ -1311,12 +1352,15 @@
/*
* NextGen regs: 8723BU
*/
+#define RF6052_REG_GAIN_P1 0x35
#define RF6052_REG_T_METER_8723B 0x42
#define RF6052_REG_UNKNOWN_43 0x43
#define RF6052_REG_UNKNOWN_55 0x55
-#define RF6052_REG_UNKNOWN_56 0x56
+#define RF6052_REG_PAD_TXG 0x56
+#define RF6052_REG_TXMOD 0x58
#define RF6052_REG_RXG_MIX_SWBW 0x87
#define RF6052_REG_S0S1 0xb0
-#define RF6052_REG_UNKNOWN_DF 0xdf
+#define RF6052_REG_GAIN_CCA 0xdf
#define RF6052_REG_UNKNOWN_ED 0xed
#define RF6052_REG_WE_LUT 0xef
+#define RF6052_REG_GAIN_CTRL 0xf5
diff --git a/drivers/net/wireless/realtek/rtlwifi/base.c b/drivers/net/wireless/realtek/rtlwifi/base.c
index 9e7e98b55eff..807a53a97325 100644
--- a/drivers/net/wireless/realtek/rtlwifi/base.c
+++ b/drivers/net/wireless/realtek/rtlwifi/base.c
@@ -452,8 +452,7 @@ static int _rtl_init_deferred_work(struct ieee80211_hw *hw)
/* <1> timer */
timer_setup(&rtlpriv->works.watchdog_timer,
rtl_watch_dog_timer_callback, 0);
- timer_setup(&rtlpriv->works.dualmac_easyconcurrent_retrytimer,
- rtl_easy_concurrent_retrytimer_callback, 0);
+
/* <2> work queue */
rtlpriv->works.hw = hw;
rtlpriv->works.rtl_wq = wq;
@@ -1905,7 +1904,7 @@ EXPORT_SYMBOL(rtl_rx_ampdu_apply);
void rtl_beacon_statistic(struct ieee80211_hw *hw, struct sk_buff *skb)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
+ struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
if (rtlpriv->mac80211.opmode != NL80211_IFTYPE_STATION)
return;
@@ -1991,7 +1990,7 @@ void rtl_scan_list_expire(struct ieee80211_hw *hw)
void rtl_collect_scan_list(struct ieee80211_hw *hw, struct sk_buff *skb)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
+ struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
unsigned long flags;
@@ -2366,19 +2365,6 @@ static void rtl_c2hcmd_wq_callback(struct work_struct *work)
rtl_c2hcmd_launcher(hw, 1);
}
-void rtl_easy_concurrent_retrytimer_callback(struct timer_list *t)
-{
- struct rtl_priv *rtlpriv =
- from_timer(rtlpriv, t, works.dualmac_easyconcurrent_retrytimer);
- struct ieee80211_hw *hw = rtlpriv->hw;
- struct rtl_priv *buddy_priv = rtlpriv->buddy_priv;
-
- if (buddy_priv == NULL)
- return;
-
- rtlpriv->cfg->ops->dualmac_easy_concurrent(hw);
-}
-
/*********************************************************
*
* frame process functions
diff --git a/drivers/net/wireless/realtek/rtlwifi/base.h b/drivers/net/wireless/realtek/rtlwifi/base.h
index 0e4f8a8ae3a5..f081a9a90563 100644
--- a/drivers/net/wireless/realtek/rtlwifi/base.h
+++ b/drivers/net/wireless/realtek/rtlwifi/base.h
@@ -124,7 +124,6 @@ int rtl_send_smps_action(struct ieee80211_hw *hw,
u8 *rtl_find_ie(u8 *data, unsigned int len, u8 ie);
void rtl_recognize_peer(struct ieee80211_hw *hw, u8 *data, unsigned int len);
u8 rtl_tid_to_ac(u8 tid);
-void rtl_easy_concurrent_retrytimer_callback(struct timer_list *t);
extern struct rtl_global_var rtl_global_var;
void rtl_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation);
diff --git a/drivers/net/wireless/realtek/rtlwifi/core.c b/drivers/net/wireless/realtek/rtlwifi/core.c
index 6f10727cdb94..4fb16f5f6f83 100644
--- a/drivers/net/wireless/realtek/rtlwifi/core.c
+++ b/drivers/net/wireless/realtek/rtlwifi/core.c
@@ -1908,6 +1908,16 @@ bool rtl_cmd_send_packet(struct ieee80211_hw *hw, struct sk_buff *skb)
return true;
}
EXPORT_SYMBOL(rtl_cmd_send_packet);
+
+void rtl_init_sw_leds(struct ieee80211_hw *hw)
+{
+ struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+ rtlpriv->ledctl.sw_led0 = LED_PIN_LED0;
+ rtlpriv->ledctl.sw_led1 = LED_PIN_LED1;
+}
+EXPORT_SYMBOL(rtl_init_sw_leds);
+
const struct ieee80211_ops rtl_ops = {
.start = rtl_op_start,
.stop = rtl_op_stop,
diff --git a/drivers/net/wireless/realtek/rtlwifi/core.h b/drivers/net/wireless/realtek/rtlwifi/core.h
index 345161b47442..42c2d9e13bb8 100644
--- a/drivers/net/wireless/realtek/rtlwifi/core.h
+++ b/drivers/net/wireless/realtek/rtlwifi/core.h
@@ -51,6 +51,8 @@ enum dm_dig_connect_e {
};
extern const struct ieee80211_ops rtl_ops;
+
+void rtl_init_sw_leds(struct ieee80211_hw *hw);
void rtl_fw_cb(const struct firmware *firmware, void *context);
void rtl_wowlan_fw_cb(const struct firmware *firmware, void *context);
void rtl_addr_delay(u32 addr);
diff --git a/drivers/net/wireless/realtek/rtlwifi/pci.c b/drivers/net/wireless/realtek/rtlwifi/pci.c
index ca79f652fef3..9886e719739b 100644
--- a/drivers/net/wireless/realtek/rtlwifi/pci.c
+++ b/drivers/net/wireless/realtek/rtlwifi/pci.c
@@ -482,11 +482,6 @@ static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
if (!rtlpriv->rtlhal.earlymode_enable)
return;
- if (rtlpriv->dm.supp_phymode_switch &&
- (rtlpriv->easy_concurrent_ctl.switch_in_process ||
- (rtlpriv->buddy_priv &&
- rtlpriv->buddy_priv->easy_concurrent_ctl.switch_in_process)))
- return;
/* we just use em for BE/BK/VI/VO */
for (tid = 7; tid >= 0; tid--) {
u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)];
@@ -2265,7 +2260,7 @@ int rtl_pci_probe(struct pci_dev *pdev,
err = -ENODEV;
goto fail3;
}
- rtlpriv->cfg->ops->init_sw_leds(hw);
+ rtl_init_sw_leds(hw);
/*aspm */
rtl_pci_init_aspm(hw);
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c
index de61c9c0ddec..58b1a46066b5 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c
@@ -803,17 +803,17 @@ static void _rtl88ee_gen_refresh_led_state(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
+ enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0;
if (rtlpriv->rtlhal.up_first_time)
return;
if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
- rtl88ee_sw_led_on(hw, pled0);
+ rtl88ee_sw_led_on(hw, pin0);
else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
- rtl88ee_sw_led_on(hw, pled0);
+ rtl88ee_sw_led_on(hw, pin0);
else
- rtl88ee_sw_led_off(hw, pled0);
+ rtl88ee_sw_led_off(hw, pin0);
}
static bool _rtl88ee_init_mac(struct ieee80211_hw *hw)
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/led.c b/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/led.c
index 006b979da1c6..b57ba45902f9 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/led.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/led.c
@@ -6,23 +6,15 @@
#include "reg.h"
#include "led.h"
-static void _rtl88ee_init_led(struct ieee80211_hw *hw,
- struct rtl_led *pled, enum rtl_led_pin ledpin)
-{
- pled->hw = hw;
- pled->ledpin = ledpin;
- pled->ledon = false;
-}
-
-void rtl88ee_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
+void rtl88ee_sw_led_on(struct ieee80211_hw *hw, enum rtl_led_pin pin)
{
u8 ledcfg;
struct rtl_priv *rtlpriv = rtl_priv(hw);
rtl_dbg(rtlpriv, COMP_LED, DBG_LOUD,
- "LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin);
+ "LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pin);
- switch (pled->ledpin) {
+ switch (pin) {
case LED_PIN_GPIO0:
break;
case LED_PIN_LED0:
@@ -36,21 +28,20 @@ void rtl88ee_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
break;
default:
rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
- "switch case %#x not processed\n", pled->ledpin);
+ "switch case %#x not processed\n", pin);
break;
}
- pled->ledon = true;
}
-void rtl88ee_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
+void rtl88ee_sw_led_off(struct ieee80211_hw *hw, enum rtl_led_pin pin)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u8 ledcfg;
rtl_dbg(rtlpriv, COMP_LED, DBG_LOUD,
- "LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin);
+ "LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pin);
- switch (pled->ledpin) {
+ switch (pin) {
case LED_PIN_GPIO0:
break;
case LED_PIN_LED0:
@@ -73,34 +64,25 @@ void rtl88ee_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
break;
default:
rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
- "switch case %#x not processed\n", pled->ledpin);
+ "switch case %#x not processed\n", pin);
break;
}
- pled->ledon = false;
-}
-
-void rtl88ee_init_sw_leds(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- _rtl88ee_init_led(hw, &rtlpriv->ledctl.sw_led0, LED_PIN_LED0);
- _rtl88ee_init_led(hw, &rtlpriv->ledctl.sw_led1, LED_PIN_LED1);
}
static void _rtl88ee_sw_led_control(struct ieee80211_hw *hw,
enum led_ctl_mode ledaction)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
+ enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0;
switch (ledaction) {
case LED_CTL_POWER_ON:
case LED_CTL_LINK:
case LED_CTL_NO_LINK:
- rtl88ee_sw_led_on(hw, pled0);
+ rtl88ee_sw_led_on(hw, pin0);
break;
case LED_CTL_POWER_OFF:
- rtl88ee_sw_led_off(hw, pled0);
+ rtl88ee_sw_led_off(hw, pin0);
break;
default:
break;
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/led.h b/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/led.h
index 67d3dc389ba0..e5cc35d4c298 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/led.h
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/led.h
@@ -4,9 +4,8 @@
#ifndef __RTL92CE_LED_H__
#define __RTL92CE_LED_H__
-void rtl88ee_init_sw_leds(struct ieee80211_hw *hw);
-void rtl88ee_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
-void rtl88ee_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
+void rtl88ee_sw_led_on(struct ieee80211_hw *hw, enum rtl_led_pin pin);
+void rtl88ee_sw_led_off(struct ieee80211_hw *hw, enum rtl_led_pin pin);
void rtl88ee_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction);
#endif
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/sw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/sw.c
index 02b77521b5cd..b77937fe2448 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/sw.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/sw.c
@@ -230,7 +230,6 @@ static struct rtl_hal_ops rtl8188ee_hal_ops = {
.tx_polling = rtl88ee_tx_polling,
.enable_hw_sec = rtl88ee_enable_hw_security_config,
.set_key = rtl88ee_set_key,
- .init_sw_leds = rtl88ee_init_sw_leds,
.get_bbreg = rtl88e_phy_query_bb_reg,
.set_bbreg = rtl88e_phy_set_bb_reg,
.get_rfreg = rtl88e_phy_query_rf_reg,
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.c b/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.c
index 6e4741e9483f..65ebe52883d3 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.c
@@ -674,7 +674,7 @@ void rtl88ee_tx_fill_cmddesc(struct ieee80211_hw *hw,
u8 fw_queue = QSLT_BEACON;
__le32 *pdesc = (__le32 *)pdesc8;
- struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
+ struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
__le16 fc = hdr->frame_control;
dma_addr_t mapping = dma_map_single(&rtlpci->pdev->dev, skb->data,
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c
index dc480323c9cb..049c4fe9eeed 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c
@@ -639,17 +639,17 @@ static void _rtl92ce_gen_refresh_led_state(struct ieee80211_hw *hw)
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
+ enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0;
if (rtlpci->up_first_time)
return;
if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
- rtl92ce_sw_led_on(hw, pled0);
+ rtl92ce_sw_led_on(hw, pin0);
else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
- rtl92ce_sw_led_on(hw, pled0);
+ rtl92ce_sw_led_on(hw, pin0);
else
- rtl92ce_sw_led_off(hw, pled0);
+ rtl92ce_sw_led_off(hw, pin0);
}
static bool _rtl92ce_init_mac(struct ieee80211_hw *hw)
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/led.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/led.c
index 57132278eb5c..9d3ffed13ba8 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/led.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/led.c
@@ -6,25 +6,17 @@
#include "reg.h"
#include "led.h"
-static void _rtl92ce_init_led(struct ieee80211_hw *hw,
- struct rtl_led *pled, enum rtl_led_pin ledpin)
-{
- pled->hw = hw;
- pled->ledpin = ledpin;
- pled->ledon = false;
-}
-
-void rtl92ce_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
+void rtl92ce_sw_led_on(struct ieee80211_hw *hw, enum rtl_led_pin pin)
{
u8 ledcfg;
struct rtl_priv *rtlpriv = rtl_priv(hw);
rtl_dbg(rtlpriv, COMP_LED, DBG_LOUD, "LedAddr:%X ledpin=%d\n",
- REG_LEDCFG2, pled->ledpin);
+ REG_LEDCFG2, pin);
ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
- switch (pled->ledpin) {
+ switch (pin) {
case LED_PIN_GPIO0:
break;
case LED_PIN_LED0:
@@ -35,24 +27,22 @@ void rtl92ce_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg & 0x0f) | BIT(5));
break;
default:
- pr_err("switch case %#x not processed\n",
- pled->ledpin);
+ pr_err("switch case %#x not processed\n", pin);
break;
}
- pled->ledon = true;
}
-void rtl92ce_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
+void rtl92ce_sw_led_off(struct ieee80211_hw *hw, enum rtl_led_pin pin)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u8 ledcfg;
rtl_dbg(rtlpriv, COMP_LED, DBG_LOUD, "LedAddr:%X ledpin=%d\n",
- REG_LEDCFG2, pled->ledpin);
+ REG_LEDCFG2, pin);
ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
- switch (pled->ledpin) {
+ switch (pin) {
case LED_PIN_GPIO0:
break;
case LED_PIN_LED0:
@@ -69,34 +59,25 @@ void rtl92ce_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg | BIT(3)));
break;
default:
- pr_info("switch case %#x not processed\n", pled->ledpin);
+ pr_info("switch case %#x not processed\n", pin);
break;
}
- pled->ledon = false;
-}
-
-void rtl92ce_init_sw_leds(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- _rtl92ce_init_led(hw, &rtlpriv->ledctl.sw_led0, LED_PIN_LED0);
- _rtl92ce_init_led(hw, &rtlpriv->ledctl.sw_led1, LED_PIN_LED1);
}
static void _rtl92ce_sw_led_control(struct ieee80211_hw *hw,
enum led_ctl_mode ledaction)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
+ enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0;
switch (ledaction) {
case LED_CTL_POWER_ON:
case LED_CTL_LINK:
case LED_CTL_NO_LINK:
- rtl92ce_sw_led_on(hw, pled0);
+ rtl92ce_sw_led_on(hw, pin0);
break;
case LED_CTL_POWER_OFF:
- rtl92ce_sw_led_off(hw, pled0);
+ rtl92ce_sw_led_off(hw, pin0);
break;
default:
break;
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/led.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/led.h
index 97ab1e00af5f..66dc28d62003 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/led.h
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/led.h
@@ -4,9 +4,8 @@
#ifndef __RTL92CE_LED_H__
#define __RTL92CE_LED_H__
-void rtl92ce_init_sw_leds(struct ieee80211_hw *hw);
-void rtl92ce_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
-void rtl92ce_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
+void rtl92ce_sw_led_on(struct ieee80211_hw *hw, enum rtl_led_pin pin);
+void rtl92ce_sw_led_off(struct ieee80211_hw *hw, enum rtl_led_pin pin);
void rtl92ce_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction);
#endif
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/sw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/sw.c
index ed68c850f9a2..e452275d8789 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/sw.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/sw.c
@@ -207,7 +207,6 @@ static struct rtl_hal_ops rtl8192ce_hal_ops = {
.tx_polling = rtl92ce_tx_polling,
.enable_hw_sec = rtl92ce_enable_hw_security_config,
.set_key = rtl92ce_set_key,
- .init_sw_leds = rtl92ce_init_sw_leds,
.get_bbreg = rtl92c_phy_query_bb_reg,
.set_bbreg = rtl92c_phy_set_bb_reg,
.set_rfreg = rtl92ce_phy_set_rf_reg,
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.c
index 730c7e939bd2..5376bb34251f 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.c
@@ -527,7 +527,7 @@ void rtl92ce_tx_fill_cmddesc(struct ieee80211_hw *hw,
u8 fw_queue = QSLT_BEACON;
__le32 *pdesc = (__le32 *)pdesc8;
- struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
+ struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
__le16 fc = hdr->frame_control;
dma_addr_t mapping = dma_map_single(&rtlpci->pdev->dev, skb->data,
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/led.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/led.c
index 1488f52a2d2f..bfc07efd0eb0 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/led.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/led.c
@@ -6,27 +6,15 @@
#include "reg.h"
#include "led.h"
-static void _rtl92cu_init_led(struct ieee80211_hw *hw,
- struct rtl_led *pled, enum rtl_led_pin ledpin)
-{
- pled->hw = hw;
- pled->ledpin = ledpin;
- pled->ledon = false;
-}
-
-static void rtl92cu_deinit_led(struct rtl_led *pled)
-{
-}
-
-void rtl92cu_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
+void rtl92cu_sw_led_on(struct ieee80211_hw *hw, enum rtl_led_pin pin)
{
u8 ledcfg;
struct rtl_priv *rtlpriv = rtl_priv(hw);
rtl_dbg(rtlpriv, COMP_LED, DBG_LOUD, "LedAddr:%X ledpin=%d\n",
- REG_LEDCFG2, pled->ledpin);
+ REG_LEDCFG2, pin);
ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
- switch (pled->ledpin) {
+ switch (pin) {
case LED_PIN_GPIO0:
break;
case LED_PIN_LED0:
@@ -37,22 +25,20 @@ void rtl92cu_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg & 0x0f) | BIT(5));
break;
default:
- pr_err("switch case %#x not processed\n",
- pled->ledpin);
+ pr_err("switch case %#x not processed\n", pin);
break;
}
- pled->ledon = true;
}
-void rtl92cu_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
+void rtl92cu_sw_led_off(struct ieee80211_hw *hw, enum rtl_led_pin pin)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u8 ledcfg;
rtl_dbg(rtlpriv, COMP_LED, DBG_LOUD, "LedAddr:%X ledpin=%d\n",
- REG_LEDCFG2, pled->ledpin);
+ REG_LEDCFG2, pin);
ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
- switch (pled->ledpin) {
+ switch (pin) {
case LED_PIN_GPIO0:
break;
case LED_PIN_LED0:
@@ -69,36 +55,13 @@ void rtl92cu_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg | BIT(3)));
break;
default:
- pr_err("switch case %#x not processed\n",
- pled->ledpin);
+ pr_err("switch case %#x not processed\n", pin);
break;
}
- pled->ledon = false;
-}
-
-void rtl92cu_init_sw_leds(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- _rtl92cu_init_led(hw, &rtlpriv->ledctl.sw_led0, LED_PIN_LED0);
- _rtl92cu_init_led(hw, &rtlpriv->ledctl.sw_led1, LED_PIN_LED1);
-}
-
-void rtl92cu_deinit_sw_leds(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- rtl92cu_deinit_led(&rtlpriv->ledctl.sw_led0);
- rtl92cu_deinit_led(&rtlpriv->ledctl.sw_led1);
-}
-
-static void _rtl92cu_sw_led_control(struct ieee80211_hw *hw,
- enum led_ctl_mode ledaction)
-{
}
void rtl92cu_led_control(struct ieee80211_hw *hw,
- enum led_ctl_mode ledaction)
+ enum led_ctl_mode ledaction)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
@@ -114,5 +77,4 @@ void rtl92cu_led_control(struct ieee80211_hw *hw,
return;
}
rtl_dbg(rtlpriv, COMP_LED, DBG_LOUD, "ledaction %d\n", ledaction);
- _rtl92cu_sw_led_control(hw, ledaction);
}
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/led.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/led.h
index 3fc1e7c8f78b..8175f8bddd6d 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/led.h
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/led.h
@@ -4,10 +4,8 @@
#ifndef __RTL92CU_LED_H__
#define __RTL92CU_LED_H__
-void rtl92cu_init_sw_leds(struct ieee80211_hw *hw);
-void rtl92cu_deinit_sw_leds(struct ieee80211_hw *hw);
-void rtl92cu_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
-void rtl92cu_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
+void rtl92cu_sw_led_on(struct ieee80211_hw *hw, enum rtl_led_pin pin);
+void rtl92cu_sw_led_off(struct ieee80211_hw *hw, enum rtl_led_pin pin);
void rtl92cu_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction);
#endif
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/sw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/sw.c
index 876c14d46c2f..e6403d4c937c 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/sw.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/sw.c
@@ -115,8 +115,6 @@ static struct rtl_hal_ops rtl8192cu_hal_ops = {
.led_control = rtl92cu_led_control,
.enable_hw_sec = rtl92cu_enable_hw_security_config,
.set_key = rtl92c_set_key,
- .init_sw_leds = rtl92cu_init_sw_leds,
- .deinit_sw_leds = rtl92cu_deinit_sw_leds,
.get_bbreg = rtl92c_phy_query_bb_reg,
.set_bbreg = rtl92c_phy_set_bb_reg,
.get_rfreg = rtl92cu_phy_query_rf_reg,
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.c
index ae3c4f97637e..b70767e72f3d 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.c
@@ -394,7 +394,7 @@ static void _rtl_rx_process(struct ieee80211_hw *hw, struct sk_buff *skb)
(struct rx_desc_92c *)rxdesc, p_drvinfo);
}
skb_pull(skb, (drvinfo_len + RTL_RX_DESC_SIZE));
- hdr = (struct ieee80211_hdr *)(skb->data);
+ hdr = rtl_get_hdr(skb);
fc = hdr->frame_control;
bv = ieee80211_is_probe_resp(fc);
if (bv)
@@ -632,7 +632,7 @@ void rtl92cu_tx_fill_cmddesc(struct ieee80211_hw *hw,
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u8 fw_queue = QSLT_BEACON;
- struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
+ struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
__le16 fc = hdr->frame_control;
__le32 *pdesc = (__le32 *)pdesc8;
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c
index df1e36fbc348..31a18bbface9 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c
@@ -595,16 +595,16 @@ static void _rtl92de_gen_refresh_led_state(struct ieee80211_hw *hw)
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
+ enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0;
if (rtlpci->up_first_time)
return;
if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
- rtl92de_sw_led_on(hw, pled0);
+ rtl92de_sw_led_on(hw, pin0);
else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
- rtl92de_sw_led_on(hw, pled0);
+ rtl92de_sw_led_on(hw, pin0);
else
- rtl92de_sw_led_off(hw, pled0);
+ rtl92de_sw_led_off(hw, pin0);
}
static bool _rtl92de_init_mac(struct ieee80211_hw *hw)
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/led.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/led.c
index 93d1c6a610c3..4bd708570992 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/led.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/led.c
@@ -6,23 +6,15 @@
#include "reg.h"
#include "led.h"
-static void _rtl92ce_init_led(struct ieee80211_hw *hw,
- struct rtl_led *pled, enum rtl_led_pin ledpin)
-{
- pled->hw = hw;
- pled->ledpin = ledpin;
- pled->ledon = false;
-}
-
-void rtl92de_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
+void rtl92de_sw_led_on(struct ieee80211_hw *hw, enum rtl_led_pin pin)
{
u8 ledcfg;
struct rtl_priv *rtlpriv = rtl_priv(hw);
rtl_dbg(rtlpriv, COMP_LED, DBG_LOUD, "LedAddr:%X ledpin=%d\n",
- REG_LEDCFG2, pled->ledpin);
+ REG_LEDCFG2, pin);
- switch (pled->ledpin) {
+ switch (pin) {
case LED_PIN_GPIO0:
break;
case LED_PIN_LED0:
@@ -44,24 +36,22 @@ void rtl92de_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg & 0x0f) | BIT(5));
break;
default:
- pr_err("switch case %#x not processed\n",
- pled->ledpin);
+ pr_err("switch case %#x not processed\n", pin);
break;
}
- pled->ledon = true;
}
-void rtl92de_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
+void rtl92de_sw_led_off(struct ieee80211_hw *hw, enum rtl_led_pin pin)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u8 ledcfg;
rtl_dbg(rtlpriv, COMP_LED, DBG_LOUD, "LedAddr:%X ledpin=%d\n",
- REG_LEDCFG2, pled->ledpin);
+ REG_LEDCFG2, pin);
ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
- switch (pled->ledpin) {
+ switch (pin) {
case LED_PIN_GPIO0:
break;
case LED_PIN_LED0:
@@ -78,35 +68,25 @@ void rtl92de_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg | BIT(3)));
break;
default:
- pr_err("switch case %#x not processed\n",
- pled->ledpin);
+ pr_err("switch case %#x not processed\n", pin);
break;
}
- pled->ledon = false;
-}
-
-void rtl92de_init_sw_leds(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- _rtl92ce_init_led(hw, &rtlpriv->ledctl.sw_led0, LED_PIN_LED0);
- _rtl92ce_init_led(hw, &rtlpriv->ledctl.sw_led1, LED_PIN_LED1);
}
static void _rtl92ce_sw_led_control(struct ieee80211_hw *hw,
enum led_ctl_mode ledaction)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
+ enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0;
switch (ledaction) {
case LED_CTL_POWER_ON:
case LED_CTL_LINK:
case LED_CTL_NO_LINK:
- rtl92de_sw_led_on(hw, pled0);
+ rtl92de_sw_led_on(hw, pin0);
break;
case LED_CTL_POWER_OFF:
- rtl92de_sw_led_off(hw, pled0);
+ rtl92de_sw_led_off(hw, pin0);
break;
default:
break;
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/led.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/led.h
index 7599c7e5ecc3..33e544ad6f99 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/led.h
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/led.h
@@ -4,9 +4,8 @@
#ifndef __RTL92CE_LED_H__
#define __RTL92CE_LED_H__
-void rtl92de_init_sw_leds(struct ieee80211_hw *hw);
-void rtl92de_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
-void rtl92de_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
+void rtl92de_sw_led_on(struct ieee80211_hw *hw, enum rtl_led_pin pin);
+void rtl92de_sw_led_off(struct ieee80211_hw *hw, enum rtl_led_pin pin);
void rtl92de_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction);
#endif
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.c
index a74724c971b9..11f319c97124 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.c
@@ -220,7 +220,6 @@ static struct rtl_hal_ops rtl8192de_hal_ops = {
.tx_polling = rtl92de_tx_polling,
.enable_hw_sec = rtl92de_enable_hw_security_config,
.set_key = rtl92de_set_key,
- .init_sw_leds = rtl92de_init_sw_leds,
.get_bbreg = rtl92d_phy_query_bb_reg,
.set_bbreg = rtl92d_phy_set_bb_reg,
.get_rfreg = rtl92d_phy_query_rf_reg,
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c
index 807b66c16e11..c09c0c312665 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c
@@ -665,7 +665,7 @@ void rtl92de_tx_fill_cmddesc(struct ieee80211_hw *hw,
struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
u8 fw_queue = QSLT_BEACON;
- struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
+ struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
__le16 fc = hdr->frame_control;
__le32 *pdesc = (__le32 *)pdesc8;
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c
index 47d8999e31c0..ebb7abd0c9ad 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c
@@ -714,17 +714,17 @@ static void _rtl92ee_gen_refresh_led_state(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
+ enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0;
if (rtlpriv->rtlhal.up_first_time)
return;
if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
- rtl92ee_sw_led_on(hw, pled0);
+ rtl92ee_sw_led_on(hw, pin0);
else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
- rtl92ee_sw_led_on(hw, pled0);
+ rtl92ee_sw_led_on(hw, pin0);
else
- rtl92ee_sw_led_off(hw, pled0);
+ rtl92ee_sw_led_off(hw, pin0);
}
static bool _rtl92ee_init_mac(struct ieee80211_hw *hw)
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/led.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/led.c
index fb4ea3a8481f..a9b5e3c884ee 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/led.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/led.c
@@ -6,23 +6,15 @@
#include "reg.h"
#include "led.h"
-static void _rtl92ee_init_led(struct ieee80211_hw *hw,
- struct rtl_led *pled, enum rtl_led_pin ledpin)
-{
- pled->hw = hw;
- pled->ledpin = ledpin;
- pled->ledon = false;
-}
-
-void rtl92ee_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
+void rtl92ee_sw_led_on(struct ieee80211_hw *hw, enum rtl_led_pin pin)
{
u32 ledcfg;
struct rtl_priv *rtlpriv = rtl_priv(hw);
rtl_dbg(rtlpriv, COMP_LED, DBG_LOUD,
- "LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin);
+ "LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pin);
- switch (pled->ledpin) {
+ switch (pin) {
case LED_PIN_GPIO0:
break;
case LED_PIN_LED0:
@@ -39,21 +31,20 @@ void rtl92ee_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
break;
default:
rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
- "switch case %#x not processed\n", pled->ledpin);
+ "switch case %#x not processed\n", pin);
break;
}
- pled->ledon = true;
}
-void rtl92ee_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
+void rtl92ee_sw_led_off(struct ieee80211_hw *hw, enum rtl_led_pin pin)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 ledcfg;
rtl_dbg(rtlpriv, COMP_LED, DBG_LOUD,
- "LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin);
+ "LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pin);
- switch (pled->ledpin) {
+ switch (pin) {
case LED_PIN_GPIO0:
break;
case LED_PIN_LED0:
@@ -69,34 +60,25 @@ void rtl92ee_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
break;
default:
rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
- "switch case %#x not processed\n", pled->ledpin);
+ "switch case %#x not processed\n", pin);
break;
}
- pled->ledon = false;
-}
-
-void rtl92ee_init_sw_leds(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- _rtl92ee_init_led(hw, &rtlpriv->ledctl.sw_led0, LED_PIN_LED0);
- _rtl92ee_init_led(hw, &rtlpriv->ledctl.sw_led1, LED_PIN_LED1);
}
static void _rtl92ee_sw_led_control(struct ieee80211_hw *hw,
enum led_ctl_mode ledaction)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
+ enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0;
switch (ledaction) {
case LED_CTL_POWER_ON:
case LED_CTL_LINK:
case LED_CTL_NO_LINK:
- rtl92ee_sw_led_on(hw, pled0);
+ rtl92ee_sw_led_on(hw, pin0);
break;
case LED_CTL_POWER_OFF:
- rtl92ee_sw_led_off(hw, pled0);
+ rtl92ee_sw_led_off(hw, pin0);
break;
default:
break;
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/led.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/led.h
index 6d775e14846f..08b8ff328b63 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/led.h
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/led.h
@@ -4,9 +4,8 @@
#ifndef __RTL92E_LED_H__
#define __RTL92E_LED_H__
-void rtl92ee_init_sw_leds(struct ieee80211_hw *hw);
-void rtl92ee_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
-void rtl92ee_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
+void rtl92ee_sw_led_on(struct ieee80211_hw *hw, enum rtl_led_pin pin);
+void rtl92ee_sw_led_off(struct ieee80211_hw *hw, enum rtl_led_pin pin);
void rtl92ee_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction);
#endif
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/sw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/sw.c
index 7a16563b3a5d..616a47d8d97a 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/sw.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/sw.c
@@ -220,7 +220,6 @@ static struct rtl_hal_ops rtl8192ee_hal_ops = {
.tx_polling = rtl92ee_tx_polling,
.enable_hw_sec = rtl92ee_enable_hw_security_config,
.set_key = rtl92ee_set_key,
- .init_sw_leds = rtl92ee_init_sw_leds,
.get_bbreg = rtl92ee_phy_query_bb_reg,
.set_bbreg = rtl92ee_phy_set_bb_reg,
.get_rfreg = rtl92ee_phy_query_rf_reg,
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c
index a8b5bf45b1bb..e5775b94f04e 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c
@@ -731,12 +731,12 @@ static void _rtl92se_macconfig_before_fwdownload(struct ieee80211_hw *hw)
/* After MACIO reset,we must refresh LED state. */
if ((ppsc->rfoff_reason == RF_CHANGE_BY_IPS) ||
(ppsc->rfoff_reason == 0)) {
- struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
+ enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0;
enum rf_pwrstate rfpwr_state_toset;
rfpwr_state_toset = _rtl92se_rf_onoff_detect(hw);
if (rfpwr_state_toset == ERFON)
- rtl92se_sw_led_on(hw, pled0);
+ rtl92se_sw_led_on(hw, pin0);
}
}
@@ -1302,7 +1302,7 @@ static void _rtl92s_phy_set_rfhalt(struct ieee80211_hw *hw)
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
u8 u1btmp;
- if (rtlhal->driver_going2unload)
+ if (rtlhal->driver_is_goingto_unload)
rtl_write_byte(rtlpriv, 0x560, 0x0);
/* Power save for BB/RF */
@@ -1323,7 +1323,7 @@ static void _rtl92s_phy_set_rfhalt(struct ieee80211_hw *hw)
rtl_write_word(rtlpriv, CMDR, 0x57FC);
rtl_write_word(rtlpriv, CMDR, 0x0000);
- if (rtlhal->driver_going2unload) {
+ if (rtlhal->driver_is_goingto_unload) {
u1btmp = rtl_read_byte(rtlpriv, (REG_SYS_FUNC_EN + 1));
u1btmp &= ~(BIT(0));
rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, u1btmp);
@@ -1345,7 +1345,7 @@ static void _rtl92s_phy_set_rfhalt(struct ieee80211_hw *hw)
/* Power save for MAC */
if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS &&
- !rtlhal->driver_going2unload) {
+ !rtlhal->driver_is_goingto_unload) {
/* enable LED function */
rtl_write_byte(rtlpriv, 0x03, 0xF9);
/* SW/HW radio off or halt adapter!! For example S3/S4 */
@@ -1371,15 +1371,15 @@ static void _rtl92se_gen_refreshledstate(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
+ enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0;
if (rtlpci->up_first_time)
return;
if (rtlpriv->psc.rfoff_reason == RF_CHANGE_BY_IPS)
- rtl92se_sw_led_on(hw, pled0);
+ rtl92se_sw_led_on(hw, pin0);
else
- rtl92se_sw_led_off(hw, pled0);
+ rtl92se_sw_led_off(hw, pin0);
}
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192se/led.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192se/led.c
index ecbf425f679f..db16a325c5e6 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192se/led.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192se/led.c
@@ -6,33 +6,17 @@
#include "reg.h"
#include "led.h"
-static void _rtl92se_init_led(struct ieee80211_hw *hw,
- struct rtl_led *pled, enum rtl_led_pin ledpin)
-{
- pled->hw = hw;
- pled->ledpin = ledpin;
- pled->ledon = false;
-}
-
-void rtl92se_init_sw_leds(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- _rtl92se_init_led(hw, &rtlpriv->ledctl.sw_led0, LED_PIN_LED0);
- _rtl92se_init_led(hw, &rtlpriv->ledctl.sw_led1, LED_PIN_LED1);
-}
-
-void rtl92se_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
+void rtl92se_sw_led_on(struct ieee80211_hw *hw, enum rtl_led_pin pin)
{
u8 ledcfg;
struct rtl_priv *rtlpriv = rtl_priv(hw);
rtl_dbg(rtlpriv, COMP_LED, DBG_LOUD, "LedAddr:%X ledpin=%d\n",
- LEDCFG, pled->ledpin);
+ LEDCFG, pin);
ledcfg = rtl_read_byte(rtlpriv, LEDCFG);
- switch (pled->ledpin) {
+ switch (pin) {
case LED_PIN_GPIO0:
break;
case LED_PIN_LED0:
@@ -42,14 +26,12 @@ void rtl92se_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
rtl_write_byte(rtlpriv, LEDCFG, ledcfg & 0x0f);
break;
default:
- pr_err("switch case %#x not processed\n",
- pled->ledpin);
+ pr_err("switch case %#x not processed\n", pin);
break;
}
- pled->ledon = true;
}
-void rtl92se_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
+void rtl92se_sw_led_off(struct ieee80211_hw *hw, enum rtl_led_pin pin)
{
struct rtl_priv *rtlpriv;
u8 ledcfg;
@@ -58,11 +40,11 @@ void rtl92se_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
if (!rtlpriv || rtlpriv->max_fw_size)
return;
rtl_dbg(rtlpriv, COMP_LED, DBG_LOUD, "LedAddr:%X ledpin=%d\n",
- LEDCFG, pled->ledpin);
+ LEDCFG, pin);
ledcfg = rtl_read_byte(rtlpriv, LEDCFG);
- switch (pled->ledpin) {
+ switch (pin) {
case LED_PIN_GPIO0:
break;
case LED_PIN_LED0:
@@ -77,27 +59,25 @@ void rtl92se_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
rtl_write_byte(rtlpriv, LEDCFG, (ledcfg | BIT(3)));
break;
default:
- pr_err("switch case %#x not processed\n",
- pled->ledpin);
+ pr_err("switch case %#x not processed\n", pin);
break;
}
- pled->ledon = false;
}
static void _rtl92se_sw_led_control(struct ieee80211_hw *hw,
enum led_ctl_mode ledaction)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
+ enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0;
switch (ledaction) {
case LED_CTL_POWER_ON:
case LED_CTL_LINK:
case LED_CTL_NO_LINK:
- rtl92se_sw_led_on(hw, pled0);
+ rtl92se_sw_led_on(hw, pin0);
break;
case LED_CTL_POWER_OFF:
- rtl92se_sw_led_off(hw, pled0);
+ rtl92se_sw_led_off(hw, pin0);
break;
default:
break;
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192se/led.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192se/led.h
index c9e481a8d943..43fcc3c77bc1 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192se/led.h
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192se/led.h
@@ -4,9 +4,8 @@
#ifndef __REALTEK_PCI92SE_LED_H__
#define __REALTEK_PCI92SE_LED_H__
-void rtl92se_init_sw_leds(struct ieee80211_hw *hw);
-void rtl92se_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
-void rtl92se_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
+void rtl92se_sw_led_on(struct ieee80211_hw *hw, enum rtl_led_pin pin);
+void rtl92se_sw_led_off(struct ieee80211_hw *hw, enum rtl_led_pin pin);
void rtl92se_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction);
#endif
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192se/sw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192se/sw.c
index 6d352a3161b8..30bce381c3bb 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192se/sw.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192se/sw.c
@@ -260,7 +260,6 @@ static struct rtl_hal_ops rtl8192se_hal_ops = {
.tx_polling = rtl92se_tx_polling,
.enable_hw_sec = rtl92se_enable_hw_security_config,
.set_key = rtl92se_set_key,
- .init_sw_leds = rtl92se_init_sw_leds,
.get_bbreg = rtl92s_phy_query_bb_reg,
.set_bbreg = rtl92s_phy_set_bb_reg,
.get_rfreg = rtl92s_phy_query_rf_reg,
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c
index 965d98b9b09f..d26d4c4314a3 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c
@@ -643,17 +643,17 @@ static void _rtl8723e_gen_refresh_led_state(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
+ enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0;
if (rtlpriv->rtlhal.up_first_time)
return;
if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
- rtl8723e_sw_led_on(hw, pled0);
+ rtl8723e_sw_led_on(hw, pin0);
else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
- rtl8723e_sw_led_on(hw, pled0);
+ rtl8723e_sw_led_on(hw, pin0);
else
- rtl8723e_sw_led_off(hw, pled0);
+ rtl8723e_sw_led_off(hw, pin0);
}
static bool _rtl8712e_init_mac(struct ieee80211_hw *hw)
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/led.c b/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/led.c
index 7fab02e01a8c..90d3f6ae82d5 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/led.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/led.c
@@ -6,23 +6,15 @@
#include "reg.h"
#include "led.h"
-static void _rtl8723e_init_led(struct ieee80211_hw *hw,
- struct rtl_led *pled, enum rtl_led_pin ledpin)
-{
- pled->hw = hw;
- pled->ledpin = ledpin;
- pled->ledon = false;
-}
-
-void rtl8723e_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
+void rtl8723e_sw_led_on(struct ieee80211_hw *hw, enum rtl_led_pin pin)
{
u8 ledcfg;
struct rtl_priv *rtlpriv = rtl_priv(hw);
rtl_dbg(rtlpriv, COMP_LED, DBG_LOUD,
- "LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin);
+ "LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pin);
- switch (pled->ledpin) {
+ switch (pin) {
case LED_PIN_GPIO0:
break;
case LED_PIN_LED0:
@@ -36,24 +28,22 @@ void rtl8723e_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
rtl_write_byte(rtlpriv, REG_LEDCFG1, ledcfg & 0x10);
break;
default:
- pr_err("switch case %#x not processed\n",
- pled->ledpin);
+ pr_err("switch case %#x not processed\n", pin);
break;
}
- pled->ledon = true;
}
-void rtl8723e_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
+void rtl8723e_sw_led_off(struct ieee80211_hw *hw, enum rtl_led_pin pin)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u8 ledcfg;
rtl_dbg(rtlpriv, COMP_LED, DBG_LOUD,
- "LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin);
+ "LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pin);
ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
- switch (pled->ledpin) {
+ switch (pin) {
case LED_PIN_GPIO0:
break;
case LED_PIN_LED0:
@@ -77,35 +67,25 @@ void rtl8723e_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
break;
default:
- pr_err("switch case %#x not processed\n",
- pled->ledpin);
+ pr_err("switch case %#x not processed\n", pin);
break;
}
- pled->ledon = false;
-}
-
-void rtl8723e_init_sw_leds(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- _rtl8723e_init_led(hw, &rtlpriv->ledctl.sw_led0, LED_PIN_LED0);
- _rtl8723e_init_led(hw, &rtlpriv->ledctl.sw_led1, LED_PIN_LED1);
}
static void _rtl8723e_sw_led_control(struct ieee80211_hw *hw,
enum led_ctl_mode ledaction)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
+ enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0;
switch (ledaction) {
case LED_CTL_POWER_ON:
case LED_CTL_LINK:
case LED_CTL_NO_LINK:
- rtl8723e_sw_led_on(hw, pled0);
+ rtl8723e_sw_led_on(hw, pin0);
break;
case LED_CTL_POWER_OFF:
- rtl8723e_sw_led_off(hw, pled0);
+ rtl8723e_sw_led_off(hw, pin0);
break;
default:
break;
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/led.h b/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/led.h
index 9f85845d23cd..6db5290da806 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/led.h
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/led.h
@@ -4,9 +4,8 @@
#ifndef __RTL92CE_LED_H__
#define __RTL92CE_LED_H__
-void rtl8723e_init_sw_leds(struct ieee80211_hw *hw);
-void rtl8723e_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
-void rtl8723e_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
+void rtl8723e_sw_led_on(struct ieee80211_hw *hw, enum rtl_led_pin pin);
+void rtl8723e_sw_led_off(struct ieee80211_hw *hw, enum rtl_led_pin pin);
void rtl8723e_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction);
#endif
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/sw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/sw.c
index 7828acb1de3f..c821436a1991 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/sw.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/sw.c
@@ -223,7 +223,6 @@ static struct rtl_hal_ops rtl8723e_hal_ops = {
.tx_polling = rtl8723e_tx_polling,
.enable_hw_sec = rtl8723e_enable_hw_security_config,
.set_key = rtl8723e_set_key,
- .init_sw_leds = rtl8723e_init_sw_leds,
.get_bbreg = rtl8723_phy_query_bb_reg,
.set_bbreg = rtl8723_phy_set_bb_reg,
.get_rfreg = rtl8723e_phy_query_rf_reg,
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.c b/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.c
index 27fddbcade32..7f294e698994 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.c
@@ -528,7 +528,7 @@ void rtl8723e_tx_fill_cmddesc(struct ieee80211_hw *hw,
u8 fw_queue = QSLT_BEACON;
__le32 *pdesc = (__le32 *)pdesc8;
- struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
+ struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
__le16 fc = hdr->frame_control;
dma_addr_t mapping = dma_map_single(&rtlpci->pdev->dev, skb->data,
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c
index 0ba3bbed6ed3..15575644551f 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c
@@ -793,17 +793,17 @@ static void _rtl8723be_gen_refresh_led_state(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
+ enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0;
if (rtlpriv->rtlhal.up_first_time)
return;
if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
- rtl8723be_sw_led_on(hw, pled0);
+ rtl8723be_sw_led_on(hw, pin0);
else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
- rtl8723be_sw_led_on(hw, pled0);
+ rtl8723be_sw_led_on(hw, pin0);
else
- rtl8723be_sw_led_off(hw, pled0);
+ rtl8723be_sw_led_off(hw, pin0);
}
static bool _rtl8723be_init_mac(struct ieee80211_hw *hw)
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8723be/led.c b/drivers/net/wireless/realtek/rtlwifi/rtl8723be/led.c
index 3954624ab314..462fe1d0262b 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8723be/led.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8723be/led.c
@@ -6,23 +6,15 @@
#include "reg.h"
#include "led.h"
-static void _rtl8723be_init_led(struct ieee80211_hw *hw, struct rtl_led *pled,
- enum rtl_led_pin ledpin)
-{
- pled->hw = hw;
- pled->ledpin = ledpin;
- pled->ledon = false;
-}
-
-void rtl8723be_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
+void rtl8723be_sw_led_on(struct ieee80211_hw *hw, enum rtl_led_pin pin)
{
u8 ledcfg;
struct rtl_priv *rtlpriv = rtl_priv(hw);
rtl_dbg(rtlpriv, COMP_LED, DBG_LOUD,
- "LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin);
+ "LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pin);
- switch (pled->ledpin) {
+ switch (pin) {
case LED_PIN_GPIO0:
break;
case LED_PIN_LED0:
@@ -35,24 +27,22 @@ void rtl8723be_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
rtl_write_byte(rtlpriv, REG_LEDCFG1, ledcfg & 0x10);
break;
default:
- pr_err("switch case %#x not processed\n",
- pled->ledpin);
+ pr_err("switch case %#x not processed\n", pin);
break;
}
- pled->ledon = true;
}
-void rtl8723be_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
+void rtl8723be_sw_led_off(struct ieee80211_hw *hw, enum rtl_led_pin pin)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u8 ledcfg;
rtl_dbg(rtlpriv, COMP_LED, DBG_LOUD,
- "LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin);
+ "LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pin);
ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
- switch (pled->ledpin) {
+ switch (pin) {
case LED_PIN_GPIO0:
break;
case LED_PIN_LED0:
@@ -76,35 +66,25 @@ void rtl8723be_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
break;
default:
- pr_err("switch case %#x not processed\n",
- pled->ledpin);
+ pr_err("switch case %#x not processed\n", pin);
break;
}
- pled->ledon = false;
-}
-
-void rtl8723be_init_sw_leds(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- _rtl8723be_init_led(hw, &rtlpriv->ledctl.sw_led0, LED_PIN_LED0);
- _rtl8723be_init_led(hw, &rtlpriv->ledctl.sw_led1, LED_PIN_LED1);
}
static void _rtl8723be_sw_led_control(struct ieee80211_hw *hw,
enum led_ctl_mode ledaction)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
+ enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0;
switch (ledaction) {
case LED_CTL_POWER_ON:
case LED_CTL_LINK:
case LED_CTL_NO_LINK:
- rtl8723be_sw_led_on(hw, pled0);
+ rtl8723be_sw_led_on(hw, pin0);
break;
case LED_CTL_POWER_OFF:
- rtl8723be_sw_led_off(hw, pled0);
+ rtl8723be_sw_led_off(hw, pin0);
break;
default:
break;
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8723be/led.h b/drivers/net/wireless/realtek/rtlwifi/rtl8723be/led.h
index 8ac59374b632..3ca9277152f7 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8723be/led.h
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8723be/led.h
@@ -4,9 +4,8 @@
#ifndef __RTL8723BE_LED_H__
#define __RTL8723BE_LED_H__
-void rtl8723be_init_sw_leds(struct ieee80211_hw *hw);
-void rtl8723be_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
-void rtl8723be_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
+void rtl8723be_sw_led_on(struct ieee80211_hw *hw, enum rtl_led_pin pin);
+void rtl8723be_sw_led_off(struct ieee80211_hw *hw, enum rtl_led_pin pin);
void rtl8723be_led_control(struct ieee80211_hw *hw,
enum led_ctl_mode ledaction);
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8723be/sw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8723be/sw.c
index d220e8955e37..43b611d5288d 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8723be/sw.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8723be/sw.c
@@ -227,7 +227,6 @@ static struct rtl_hal_ops rtl8723be_hal_ops = {
.tx_polling = rtl8723be_tx_polling,
.enable_hw_sec = rtl8723be_enable_hw_security_config,
.set_key = rtl8723be_set_key,
- .init_sw_leds = rtl8723be_init_sw_leds,
.get_bbreg = rtl8723_phy_query_bb_reg,
.set_bbreg = rtl8723_phy_set_bb_reg,
.get_rfreg = rtl8723be_phy_query_rf_reg,
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c
index a7e3250957dc..3f8f6da33b12 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c
@@ -869,7 +869,7 @@ static void _rtl8821ae_gen_refresh_led_state(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
+ enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0;
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
if (rtlpriv->rtlhal.up_first_time)
@@ -877,19 +877,19 @@ static void _rtl8821ae_gen_refresh_led_state(struct ieee80211_hw *hw)
if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
- rtl8812ae_sw_led_on(hw, pled0);
+ rtl8812ae_sw_led_on(hw, pin0);
else
- rtl8821ae_sw_led_on(hw, pled0);
+ rtl8821ae_sw_led_on(hw, pin0);
else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
- rtl8812ae_sw_led_on(hw, pled0);
+ rtl8812ae_sw_led_on(hw, pin0);
else
- rtl8821ae_sw_led_on(hw, pled0);
+ rtl8821ae_sw_led_on(hw, pin0);
else
if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
- rtl8812ae_sw_led_off(hw, pled0);
+ rtl8812ae_sw_led_off(hw, pin0);
else
- rtl8821ae_sw_led_off(hw, pled0);
+ rtl8821ae_sw_led_off(hw, pin0);
}
static bool _rtl8821ae_init_mac(struct ieee80211_hw *hw)
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/led.c b/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/led.c
index 7d6fb134c10f..fb003f9ce1ac 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/led.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/led.c
@@ -6,24 +6,15 @@
#include "reg.h"
#include "led.h"
-static void _rtl8821ae_init_led(struct ieee80211_hw *hw,
- struct rtl_led *pled,
- enum rtl_led_pin ledpin)
-{
- pled->hw = hw;
- pled->ledpin = ledpin;
- pled->ledon = false;
-}
-
-void rtl8821ae_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
+void rtl8821ae_sw_led_on(struct ieee80211_hw *hw, enum rtl_led_pin pin)
{
u8 ledcfg;
struct rtl_priv *rtlpriv = rtl_priv(hw);
rtl_dbg(rtlpriv, COMP_LED, DBG_LOUD,
- "LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin);
+ "LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pin);
- switch (pled->ledpin) {
+ switch (pin) {
case LED_PIN_GPIO0:
break;
case LED_PIN_LED0:
@@ -38,19 +29,18 @@ void rtl8821ae_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
break;
default:
rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
- "switch case %#x not processed\n", pled->ledpin);
+ "switch case %#x not processed\n", pin);
break;
}
- pled->ledon = true;
}
-void rtl8812ae_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
+void rtl8812ae_sw_led_on(struct ieee80211_hw *hw, enum rtl_led_pin pin)
{
u16 ledreg = REG_LEDCFG1;
u8 ledcfg = 0;
struct rtl_priv *rtlpriv = rtl_priv(hw);
- switch (pled->ledpin) {
+ switch (pin) {
case LED_PIN_LED0:
ledreg = REG_LEDCFG1;
break;
@@ -66,27 +56,26 @@ void rtl8812ae_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
rtl_dbg(rtlpriv, COMP_LED, DBG_LOUD,
"In SwLedOn, LedAddr:%X LEDPIN=%d\n",
- ledreg, pled->ledpin);
+ ledreg, pin);
ledcfg = rtl_read_byte(rtlpriv, ledreg);
ledcfg |= BIT(5); /*Set 0x4c[21]*/
ledcfg &= ~(BIT(7) | BIT(6) | BIT(3) | BIT(2) | BIT(1) | BIT(0));
/*Clear 0x4c[23:22] and 0x4c[19:16]*/
rtl_write_byte(rtlpriv, ledreg, ledcfg); /*SW control led0 on.*/
- pled->ledon = true;
}
-void rtl8821ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
+void rtl8821ae_sw_led_off(struct ieee80211_hw *hw, enum rtl_led_pin pin)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u8 ledcfg;
rtl_dbg(rtlpriv, COMP_LED, DBG_LOUD,
- "LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin);
+ "LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pin);
ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
- switch (pled->ledpin) {
+ switch (pin) {
case LED_PIN_GPIO0:
break;
case LED_PIN_LED0:
@@ -110,18 +99,17 @@ void rtl8821ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
break;
default:
rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
- "switch case %#x not processed\n", pled->ledpin);
+ "switch case %#x not processed\n", pin);
break;
}
- pled->ledon = false;
}
-void rtl8812ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
+void rtl8812ae_sw_led_off(struct ieee80211_hw *hw, enum rtl_led_pin pin)
{
u16 ledreg = REG_LEDCFG1;
struct rtl_priv *rtlpriv = rtl_priv(hw);
- switch (pled->ledpin) {
+ switch (pin) {
case LED_PIN_LED0:
ledreg = REG_LEDCFG1;
break;
@@ -137,7 +125,7 @@ void rtl8812ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
rtl_dbg(rtlpriv, COMP_LED, DBG_LOUD,
"In SwLedOff,LedAddr:%X LEDPIN=%d\n",
- ledreg, pled->ledpin);
+ ledreg, pin);
/*Open-drain arrangement for controlling the LED*/
if (rtlpriv->ledctl.led_opendrain) {
u8 ledcfg = rtl_read_byte(rtlpriv, ledreg);
@@ -152,23 +140,13 @@ void rtl8812ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
} else {
rtl_write_byte(rtlpriv, ledreg, 0x28);
}
-
- pled->ledon = false;
-}
-
-void rtl8821ae_init_sw_leds(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- _rtl8821ae_init_led(hw, &rtlpriv->ledctl.sw_led0, LED_PIN_LED0);
- _rtl8821ae_init_led(hw, &rtlpriv->ledctl.sw_led1, LED_PIN_LED1);
}
static void _rtl8821ae_sw_led_control(struct ieee80211_hw *hw,
enum led_ctl_mode ledaction)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
+ enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0;
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
switch (ledaction) {
@@ -176,15 +154,15 @@ static void _rtl8821ae_sw_led_control(struct ieee80211_hw *hw,
case LED_CTL_LINK:
case LED_CTL_NO_LINK:
if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
- rtl8812ae_sw_led_on(hw, pled0);
+ rtl8812ae_sw_led_on(hw, pin0);
else
- rtl8821ae_sw_led_on(hw, pled0);
+ rtl8821ae_sw_led_on(hw, pin0);
break;
case LED_CTL_POWER_OFF:
if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
- rtl8812ae_sw_led_off(hw, pled0);
+ rtl8812ae_sw_led_off(hw, pin0);
else
- rtl8821ae_sw_led_off(hw, pled0);
+ rtl8821ae_sw_led_off(hw, pin0);
break;
default:
break;
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/led.h b/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/led.h
index 249a37a8d9db..76d5c0b0e39e 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/led.h
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/led.h
@@ -4,11 +4,10 @@
#ifndef __RTL8821AE_LED_H__
#define __RTL8821AE_LED_H__
-void rtl8821ae_init_sw_leds(struct ieee80211_hw *hw);
-void rtl8821ae_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
-void rtl8812ae_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
-void rtl8821ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
-void rtl8812ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
+void rtl8821ae_sw_led_on(struct ieee80211_hw *hw, enum rtl_led_pin pin);
+void rtl8812ae_sw_led_on(struct ieee80211_hw *hw, enum rtl_led_pin pin);
+void rtl8821ae_sw_led_off(struct ieee80211_hw *hw, enum rtl_led_pin pin);
+void rtl8812ae_sw_led_off(struct ieee80211_hw *hw, enum rtl_led_pin pin);
void rtl8821ae_led_control(struct ieee80211_hw *hw,
enum led_ctl_mode ledaction);
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/sw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/sw.c
index 950542a24e31..0bca542e103f 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/sw.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/sw.c
@@ -269,7 +269,6 @@ static struct rtl_hal_ops rtl8821ae_hal_ops = {
.tx_polling = rtl8821ae_tx_polling,
.enable_hw_sec = rtl8821ae_enable_hw_security_config,
.set_key = rtl8821ae_set_key,
- .init_sw_leds = rtl8821ae_init_sw_leds,
.get_bbreg = rtl8821ae_phy_query_bb_reg,
.set_bbreg = rtl8821ae_phy_set_bb_reg,
.get_rfreg = rtl8821ae_phy_query_rf_reg,
diff --git a/drivers/net/wireless/realtek/rtlwifi/usb.c b/drivers/net/wireless/realtek/rtlwifi/usb.c
index a8eebafb9a7e..30bf2775a335 100644
--- a/drivers/net/wireless/realtek/rtlwifi/usb.c
+++ b/drivers/net/wireless/realtek/rtlwifi/usb.c
@@ -164,13 +164,17 @@ static void _usb_write_async(struct usb_device *udev, u32 addr, u32 val,
u16 wvalue;
u16 index;
__le32 data;
+ int ret;
request = REALTEK_USB_VENQT_CMD_REQ;
index = REALTEK_USB_VENQT_CMD_IDX; /* n/a */
wvalue = (u16)(addr&0x0000ffff);
data = cpu_to_le32(val);
- _usbctrl_vendorreq_async_write(udev, request, wvalue, index, &data,
- len);
+
+ ret = _usbctrl_vendorreq_async_write(udev, request, wvalue,
+ index, &data, len);
+ if (ret < 0)
+ dev_err(&udev->dev, "error %d writing at 0x%x\n", ret, addr);
}
static void _usb_write8_async(struct rtl_priv *rtlpriv, u32 addr, u8 val)
@@ -194,28 +198,6 @@ static void _usb_write32_async(struct rtl_priv *rtlpriv, u32 addr, u32 val)
_usb_write_async(to_usb_device(dev), addr, val, 4);
}
-static void _usb_writen_sync(struct rtl_priv *rtlpriv, u32 addr, void *data,
- u16 len)
-{
- struct device *dev = rtlpriv->io.dev;
- struct usb_device *udev = to_usb_device(dev);
- u8 request = REALTEK_USB_VENQT_CMD_REQ;
- u8 reqtype = REALTEK_USB_VENQT_WRITE;
- u16 wvalue;
- u16 index = REALTEK_USB_VENQT_CMD_IDX;
- int pipe = usb_sndctrlpipe(udev, 0); /* write_out */
- u8 *buffer;
-
- wvalue = (u16)(addr & 0x0000ffff);
- buffer = kmemdup(data, len, GFP_ATOMIC);
- if (!buffer)
- return;
- usb_control_msg(udev, pipe, request, reqtype, wvalue,
- index, buffer, len, 50);
-
- kfree(buffer);
-}
-
static void _rtl_usb_io_handler_init(struct device *dev,
struct ieee80211_hw *hw)
{
@@ -229,7 +211,6 @@ static void _rtl_usb_io_handler_init(struct device *dev,
rtlpriv->io.read8_sync = _usb_read8_sync;
rtlpriv->io.read16_sync = _usb_read16_sync;
rtlpriv->io.read32_sync = _usb_read32_sync;
- rtlpriv->io.writen_sync = _usb_writen_sync;
}
static void _rtl_usb_io_handler_release(struct ieee80211_hw *hw)
@@ -433,7 +414,7 @@ static void _rtl_usb_rx_process_agg(struct ieee80211_hw *hw,
skb_pull(skb, RTL_RX_DESC_SIZE);
rtlpriv->cfg->ops->query_rx_desc(hw, &stats, &rx_status, rxdesc, skb);
skb_pull(skb, (stats.rx_drvinfo_size + stats.rx_bufshift));
- hdr = (struct ieee80211_hdr *)(skb->data);
+ hdr = rtl_get_hdr(skb);
fc = hdr->frame_control;
if (!stats.crc) {
memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
@@ -475,7 +456,7 @@ static void _rtl_usb_rx_process_noagg(struct ieee80211_hw *hw,
skb_pull(skb, RTL_RX_DESC_SIZE);
rtlpriv->cfg->ops->query_rx_desc(hw, &stats, &rx_status, rxdesc, skb);
skb_pull(skb, (stats.rx_drvinfo_size + stats.rx_bufshift));
- hdr = (struct ieee80211_hdr *)(skb->data);
+ hdr = rtl_get_hdr(skb);
fc = hdr->frame_control;
if (!stats.crc) {
memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
@@ -926,7 +907,7 @@ static void _rtl_usb_tx_preprocess(struct ieee80211_hw *hw,
struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
struct rtl_tx_desc *pdesc = NULL;
struct rtl_tcb_desc tcb_desc;
- struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
+ struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
__le16 fc = hdr->frame_control;
u8 *pda_addr = hdr->addr1;
@@ -961,7 +942,7 @@ static int rtl_usb_tx(struct ieee80211_hw *hw,
{
struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
- struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
+ struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
__le16 fc = hdr->frame_control;
u16 hw_queue;
@@ -1068,7 +1049,7 @@ int rtl_usb_probe(struct usb_interface *intf,
pr_err("Can't init_sw_vars\n");
goto error_out;
}
- rtlpriv->cfg->ops->init_sw_leds(hw);
+ rtl_init_sw_leds(hw);
err = ieee80211_register_hw(hw);
if (err) {
@@ -1117,7 +1098,6 @@ void rtl_usb_disconnect(struct usb_interface *intf)
rtl_usb_deinit(hw);
rtl_deinit_core(hw);
kfree(rtlpriv->usb_data);
- rtlpriv->cfg->ops->deinit_sw_leds(hw);
rtlpriv->cfg->ops->deinit_sw_vars(hw);
_rtl_usb_io_handler_release(hw);
usb_put_dev(rtlusb->udev);
diff --git a/drivers/net/wireless/realtek/rtlwifi/wifi.h b/drivers/net/wireless/realtek/rtlwifi/wifi.h
index 082af216760f..2e7e04f91279 100644
--- a/drivers/net/wireless/realtek/rtlwifi/wifi.h
+++ b/drivers/net/wireless/realtek/rtlwifi/wifi.h
@@ -1070,18 +1070,10 @@ struct rtl_probe_rsp {
struct rtl_info_element info_element[];
} __packed;
-/*LED related.*/
-/*ledpin Identify how to implement this SW led.*/
-struct rtl_led {
- void *hw;
- enum rtl_led_pin ledpin;
- bool ledon;
-};
-
struct rtl_led_ctl {
bool led_opendrain;
- struct rtl_led sw_led0;
- struct rtl_led sw_led1;
+ enum rtl_led_pin sw_led0;
+ enum rtl_led_pin sw_led1;
};
struct rtl_qos_parameters {
@@ -1465,8 +1457,6 @@ struct rtl_io {
void (*write8_async)(struct rtl_priv *rtlpriv, u32 addr, u8 val);
void (*write16_async)(struct rtl_priv *rtlpriv, u32 addr, u16 val);
void (*write32_async)(struct rtl_priv *rtlpriv, u32 addr, u32 val);
- void (*writen_sync)(struct rtl_priv *rtlpriv, u32 addr, void *buf,
- u16 len);
u8 (*read8_sync)(struct rtl_priv *rtlpriv, u32 addr);
u16 (*read16_sync)(struct rtl_priv *rtlpriv, u32 addr);
@@ -1673,8 +1663,6 @@ struct rtl_hal {
bool fw_clk_change_in_progress;
bool allow_sw_to_change_hwclc;
u8 fw_ps_state;
- /**/
- bool driver_going2unload;
/*AMPDU init min space*/
u8 minspace_cfg; /*For Min spacing configurations */
@@ -2289,8 +2277,6 @@ struct rtl_hal_ops {
void (*set_key)(struct ieee80211_hw *hw, u32 key_index,
u8 *macaddr, bool is_group, u8 enc_algo,
bool is_wepkey, bool clear_all);
- void (*init_sw_leds)(struct ieee80211_hw *hw);
- void (*deinit_sw_leds)(struct ieee80211_hw *hw);
u32 (*get_bbreg)(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
void (*set_bbreg)(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
u32 data);
@@ -2300,7 +2286,6 @@ struct rtl_hal_ops {
u32 regaddr, u32 bitmask, u32 data);
void (*linked_set_reg)(struct ieee80211_hw *hw);
void (*chk_switch_dmdp)(struct ieee80211_hw *hw);
- void (*dualmac_easy_concurrent)(struct ieee80211_hw *hw);
void (*dualmac_switch_to_dmdp)(struct ieee80211_hw *hw);
bool (*phy_rf6052_config)(struct ieee80211_hw *hw);
void (*phy_rf6052_set_cck_txpower)(struct ieee80211_hw *hw,
@@ -2465,7 +2450,6 @@ struct rtl_works {
/*timer */
struct timer_list watchdog_timer;
- struct timer_list dualmac_easyconcurrent_retrytimer;
struct timer_list fw_clockoff_timer;
struct timer_list fast_antenna_training_timer;
/*task */
@@ -2498,14 +2482,6 @@ struct rtl_debug {
#define MIMO_PS_DYNAMIC 1
#define MIMO_PS_NOLIMIT 3
-struct rtl_dualmac_easy_concurrent_ctl {
- enum band_type currentbandtype_backfordmdp;
- bool close_bbandrf_for_dmsp;
- bool change_to_dmdp;
- bool change_to_dmsp;
- bool switch_in_process;
-};
-
struct rtl_dmsp_ctl {
bool activescan_for_slaveofdmsp;
bool scan_for_anothermac_fordmsp;
@@ -2746,7 +2722,6 @@ struct rtl_priv {
struct list_head list;
struct rtl_priv *buddy_priv;
struct rtl_global_var *glb_var;
- struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl;
struct rtl_dmsp_ctl dmsp_ctl;
struct rtl_locks locks;
struct rtl_works works;
diff --git a/drivers/net/wireless/realtek/rtw88/Kconfig b/drivers/net/wireless/realtek/rtw88/Kconfig
index 29eb2f8e0eb7..cffad1c01249 100644
--- a/drivers/net/wireless/realtek/rtw88/Kconfig
+++ b/drivers/net/wireless/realtek/rtw88/Kconfig
@@ -111,6 +111,17 @@ config RTW88_8723DE
802.11n PCIe wireless network adapter
+config RTW88_8723DS
+ tristate "Realtek 8723DS SDIO wireless network adapter"
+ depends on MMC
+ select RTW88_CORE
+ select RTW88_SDIO
+ select RTW88_8723D
+ help
+ Select this option will enable support for 8723DS chipset
+
+ 802.11n SDIO wireless network adapter
+
config RTW88_8723DU
tristate "Realtek 8723DU USB wireless network adapter"
depends on USB
diff --git a/drivers/net/wireless/realtek/rtw88/Makefile b/drivers/net/wireless/realtek/rtw88/Makefile
index 82979b30ae8d..fd212c09d88a 100644
--- a/drivers/net/wireless/realtek/rtw88/Makefile
+++ b/drivers/net/wireless/realtek/rtw88/Makefile
@@ -50,6 +50,9 @@ rtw88_8723d-objs := rtw8723d.o rtw8723d_table.o
obj-$(CONFIG_RTW88_8723DE) += rtw88_8723de.o
rtw88_8723de-objs := rtw8723de.o
+obj-$(CONFIG_RTW88_8723DS) += rtw88_8723ds.o
+rtw88_8723ds-objs := rtw8723ds.o
+
obj-$(CONFIG_RTW88_8723DU) += rtw88_8723du.o
rtw88_8723du-objs := rtw8723du.o
diff --git a/drivers/net/wireless/realtek/rtw88/debug.c b/drivers/net/wireless/realtek/rtw88/debug.c
index fa3d73b333ba..f8ba133baff0 100644
--- a/drivers/net/wireless/realtek/rtw88/debug.c
+++ b/drivers/net/wireless/realtek/rtw88/debug.c
@@ -183,8 +183,8 @@ static int rtw_debugfs_copy_from_user(char tmp[], int size,
tmp_len = (count > size - 1 ? size - 1 : count);
- if (!buffer || copy_from_user(tmp, buffer, tmp_len))
- return count;
+ if (copy_from_user(tmp, buffer, tmp_len))
+ return -EFAULT;
tmp[tmp_len] = '\0';
@@ -201,13 +201,16 @@ static ssize_t rtw_debugfs_set_read_reg(struct file *filp,
char tmp[32 + 1];
u32 addr, len;
int num;
+ int ret;
- rtw_debugfs_copy_from_user(tmp, sizeof(tmp), buffer, count, 2);
+ ret = rtw_debugfs_copy_from_user(tmp, sizeof(tmp), buffer, count, 2);
+ if (ret)
+ return ret;
num = sscanf(tmp, "%x %x", &addr, &len);
if (num != 2)
- return count;
+ return -EINVAL;
if (len != 1 && len != 2 && len != 4) {
rtw_warn(rtwdev, "read reg setting wrong len\n");
@@ -288,8 +291,11 @@ static ssize_t rtw_debugfs_set_rsvd_page(struct file *filp,
char tmp[32 + 1];
u32 offset, page_num;
int num;
+ int ret;
- rtw_debugfs_copy_from_user(tmp, sizeof(tmp), buffer, count, 2);
+ ret = rtw_debugfs_copy_from_user(tmp, sizeof(tmp), buffer, count, 2);
+ if (ret)
+ return ret;
num = sscanf(tmp, "%d %d", &offset, &page_num);
@@ -314,8 +320,11 @@ static ssize_t rtw_debugfs_set_single_input(struct file *filp,
char tmp[32 + 1];
u32 input;
int num;
+ int ret;
- rtw_debugfs_copy_from_user(tmp, sizeof(tmp), buffer, count, 1);
+ ret = rtw_debugfs_copy_from_user(tmp, sizeof(tmp), buffer, count, 1);
+ if (ret)
+ return ret;
num = kstrtoint(tmp, 0, &input);
@@ -338,14 +347,17 @@ static ssize_t rtw_debugfs_set_write_reg(struct file *filp,
char tmp[32 + 1];
u32 addr, val, len;
int num;
+ int ret;
- rtw_debugfs_copy_from_user(tmp, sizeof(tmp), buffer, count, 3);
+ ret = rtw_debugfs_copy_from_user(tmp, sizeof(tmp), buffer, count, 3);
+ if (ret)
+ return ret;
/* write BB/MAC register */
num = sscanf(tmp, "%x %x %x", &addr, &val, &len);
if (num != 3)
- return count;
+ return -EINVAL;
switch (len) {
case 1:
@@ -381,8 +393,11 @@ static ssize_t rtw_debugfs_set_h2c(struct file *filp,
char tmp[32 + 1];
u8 param[8];
int num;
+ int ret;
- rtw_debugfs_copy_from_user(tmp, sizeof(tmp), buffer, count, 3);
+ ret = rtw_debugfs_copy_from_user(tmp, sizeof(tmp), buffer, count, 3);
+ if (ret)
+ return ret;
num = sscanf(tmp, "%hhx,%hhx,%hhx,%hhx,%hhx,%hhx,%hhx,%hhx",
&param[0], &param[1], &param[2], &param[3],
@@ -408,14 +423,17 @@ static ssize_t rtw_debugfs_set_rf_write(struct file *filp,
char tmp[32 + 1];
u32 path, addr, mask, val;
int num;
+ int ret;
- rtw_debugfs_copy_from_user(tmp, sizeof(tmp), buffer, count, 4);
+ ret = rtw_debugfs_copy_from_user(tmp, sizeof(tmp), buffer, count, 4);
+ if (ret)
+ return ret;
num = sscanf(tmp, "%x %x %x %x", &path, &addr, &mask, &val);
if (num != 4) {
rtw_warn(rtwdev, "invalid args, [path] [addr] [mask] [val]\n");
- return count;
+ return -EINVAL;
}
mutex_lock(&rtwdev->mutex);
@@ -438,14 +456,17 @@ static ssize_t rtw_debugfs_set_rf_read(struct file *filp,
char tmp[32 + 1];
u32 path, addr, mask;
int num;
+ int ret;
- rtw_debugfs_copy_from_user(tmp, sizeof(tmp), buffer, count, 3);
+ ret = rtw_debugfs_copy_from_user(tmp, sizeof(tmp), buffer, count, 3);
+ if (ret)
+ return ret;
num = sscanf(tmp, "%x %x %x", &path, &addr, &mask);
if (num != 3) {
rtw_warn(rtwdev, "invalid args, [path] [addr] [mask] [val]\n");
- return count;
+ return -EINVAL;
}
debugfs_priv->rf_path = path;
@@ -467,7 +488,9 @@ static ssize_t rtw_debugfs_set_fix_rate(struct file *filp,
char tmp[32 + 1];
int ret;
- rtw_debugfs_copy_from_user(tmp, sizeof(tmp), buffer, count, 1);
+ ret = rtw_debugfs_copy_from_user(tmp, sizeof(tmp), buffer, count, 1);
+ if (ret)
+ return ret;
ret = kstrtou8(tmp, 0, &fix_rate);
if (ret) {
@@ -860,7 +883,9 @@ static ssize_t rtw_debugfs_set_coex_enable(struct file *filp,
bool enable;
int ret;
- rtw_debugfs_copy_from_user(tmp, sizeof(tmp), buffer, count, 1);
+ ret = rtw_debugfs_copy_from_user(tmp, sizeof(tmp), buffer, count, 1);
+ if (ret)
+ return ret;
ret = kstrtobool(tmp, &enable);
if (ret) {
@@ -930,7 +955,9 @@ static ssize_t rtw_debugfs_set_fw_crash(struct file *filp,
bool input;
int ret;
- rtw_debugfs_copy_from_user(tmp, sizeof(tmp), buffer, count, 1);
+ ret = rtw_debugfs_copy_from_user(tmp, sizeof(tmp), buffer, count, 1);
+ if (ret)
+ return ret;
ret = kstrtobool(tmp, &input);
if (ret)
diff --git a/drivers/net/wireless/realtek/rtw88/fw.c b/drivers/net/wireless/realtek/rtw88/fw.c
index 2a8ccc8a7f60..567bbedd8ee0 100644
--- a/drivers/net/wireless/realtek/rtw88/fw.c
+++ b/drivers/net/wireless/realtek/rtw88/fw.c
@@ -308,6 +308,57 @@ void rtw_fw_c2h_cmd_isr(struct rtw_dev *rtwdev)
}
EXPORT_SYMBOL(rtw_fw_c2h_cmd_isr);
+static void rtw_fw_send_h2c_command_register(struct rtw_dev *rtwdev,
+ struct rtw_h2c_register *h2c)
+{
+ u32 box_reg, box_ex_reg;
+ u8 box_state, box;
+ int ret;
+
+ rtw_dbg(rtwdev, RTW_DBG_FW, "send H2C content %08x %08x\n", h2c->w0,
+ h2c->w1);
+
+ lockdep_assert_held(&rtwdev->mutex);
+
+ box = rtwdev->h2c.last_box_num;
+ switch (box) {
+ case 0:
+ box_reg = REG_HMEBOX0;
+ box_ex_reg = REG_HMEBOX0_EX;
+ break;
+ case 1:
+ box_reg = REG_HMEBOX1;
+ box_ex_reg = REG_HMEBOX1_EX;
+ break;
+ case 2:
+ box_reg = REG_HMEBOX2;
+ box_ex_reg = REG_HMEBOX2_EX;
+ break;
+ case 3:
+ box_reg = REG_HMEBOX3;
+ box_ex_reg = REG_HMEBOX3_EX;
+ break;
+ default:
+ WARN(1, "invalid h2c mail box number\n");
+ return;
+ }
+
+ ret = read_poll_timeout_atomic(rtw_read8, box_state,
+ !((box_state >> box) & 0x1), 100, 3000,
+ false, rtwdev, REG_HMETFR);
+
+ if (ret) {
+ rtw_err(rtwdev, "failed to send h2c command\n");
+ return;
+ }
+
+ rtw_write32(rtwdev, box_ex_reg, h2c->w1);
+ rtw_write32(rtwdev, box_reg, h2c->w0);
+
+ if (++rtwdev->h2c.last_box_num >= 4)
+ rtwdev->h2c.last_box_num = 0;
+}
+
static void rtw_fw_send_h2c_command(struct rtw_dev *rtwdev,
u8 *h2c)
{
@@ -468,6 +519,23 @@ void rtw_fw_query_bt_info(struct rtw_dev *rtwdev)
rtw_fw_send_h2c_command(rtwdev, h2c_pkt);
}
+void rtw_fw_default_port(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif)
+{
+ struct rtw_h2c_register h2c = {};
+
+ if (rtwvif->net_type != RTW_NET_MGD_LINKED)
+ return;
+
+ /* Leave LPS before default port H2C so FW timer is correct */
+ rtw_leave_lps(rtwdev);
+
+ h2c.w0 = u32_encode_bits(H2C_CMD_DEFAULT_PORT, RTW_H2C_W0_CMDID) |
+ u32_encode_bits(rtwvif->port, RTW_H2C_DEFAULT_PORT_W0_PORTID) |
+ u32_encode_bits(rtwvif->mac_id, RTW_H2C_DEFAULT_PORT_W0_MACID);
+
+ rtw_fw_send_h2c_command_register(rtwdev, &h2c);
+}
+
void rtw_fw_wl_ch_info(struct rtw_dev *rtwdev, u8 link, u8 ch, u8 bw)
{
u8 h2c_pkt[H2C_PKT_SIZE] = {0};
diff --git a/drivers/net/wireless/realtek/rtw88/fw.h b/drivers/net/wireless/realtek/rtw88/fw.h
index 397cbc3f6af6..43ccdf9965ac 100644
--- a/drivers/net/wireless/realtek/rtw88/fw.h
+++ b/drivers/net/wireless/realtek/rtw88/fw.h
@@ -81,6 +81,17 @@ struct rtw_c2h_adaptivity {
u8 option;
} __packed;
+struct rtw_h2c_register {
+ u32 w0;
+ u32 w1;
+} __packed;
+
+#define RTW_H2C_W0_CMDID GENMASK(7, 0)
+
+/* H2C_CMD_DEFAULT_PORT command */
+#define RTW_H2C_DEFAULT_PORT_W0_PORTID GENMASK(15, 8)
+#define RTW_H2C_DEFAULT_PORT_W0_MACID GENMASK(23, 16)
+
struct rtw_h2c_cmd {
__le32 msg;
__le32 msg_ext;
@@ -530,6 +541,7 @@ static inline void rtw_h2c_pkt_set_header(u8 *h2c_pkt, u8 sub_id)
#define H2C_CMD_MEDIA_STATUS_RPT 0x01
#define H2C_CMD_SET_PWR_MODE 0x20
#define H2C_CMD_LPS_PG_INFO 0x2b
+#define H2C_CMD_DEFAULT_PORT 0x2c
#define H2C_CMD_RA_INFO 0x40
#define H2C_CMD_RSSI_MONITOR 0x42
#define H2C_CMD_BCN_FILTER_OFFLOAD_P0 0x56
@@ -801,6 +813,7 @@ void rtw_fw_c2h_cmd_rx_irqsafe(struct rtw_dev *rtwdev, u32 pkt_offset,
void rtw_fw_c2h_cmd_handle(struct rtw_dev *rtwdev, struct sk_buff *skb);
void rtw_fw_send_general_info(struct rtw_dev *rtwdev);
void rtw_fw_send_phydm_info(struct rtw_dev *rtwdev);
+void rtw_fw_default_port(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif);
void rtw_fw_do_iqk(struct rtw_dev *rtwdev, struct rtw_iqk_para *para);
void rtw_fw_inform_rfk_status(struct rtw_dev *rtwdev, bool start);
diff --git a/drivers/net/wireless/realtek/rtw88/mac.c b/drivers/net/wireless/realtek/rtw88/mac.c
index a168f36c38ec..298663b03580 100644
--- a/drivers/net/wireless/realtek/rtw88/mac.c
+++ b/drivers/net/wireless/realtek/rtw88/mac.c
@@ -794,8 +794,10 @@ static int __rtw_download_firmware(struct rtw_dev *rtwdev,
wlan_cpu_enable(rtwdev, true);
- if (!ltecoex_reg_write(rtwdev, 0x38, ltecoex_bckp))
- return -EBUSY;
+ if (!ltecoex_reg_write(rtwdev, 0x38, ltecoex_bckp)) {
+ ret = -EBUSY;
+ goto dlfw_fail;
+ }
ret = download_firmware_validate(rtwdev);
if (ret)
diff --git a/drivers/net/wireless/realtek/rtw88/mac80211.c b/drivers/net/wireless/realtek/rtw88/mac80211.c
index 144618bb94c8..a99b53d44267 100644
--- a/drivers/net/wireless/realtek/rtw88/mac80211.c
+++ b/drivers/net/wireless/realtek/rtw88/mac80211.c
@@ -43,7 +43,11 @@ static void rtw_ops_wake_tx_queue(struct ieee80211_hw *hw,
list_add_tail(&rtwtxq->list, &rtwdev->txqs);
spin_unlock_bh(&rtwdev->txq_lock);
- queue_work(rtwdev->tx_wq, &rtwdev->tx_work);
+ /* ensure to dequeue EAPOL (4/4) at the right time */
+ if (txq->ac == IEEE80211_AC_VO)
+ __rtw_tx_work(rtwdev);
+ else
+ queue_work(rtwdev->tx_wq, &rtwdev->tx_work);
}
static int rtw_ops_start(struct ieee80211_hw *hw)
@@ -164,8 +168,10 @@ static int rtw_ops_add_interface(struct ieee80211_hw *hw,
mutex_lock(&rtwdev->mutex);
port = find_first_zero_bit(rtwdev->hw_port, RTW_PORT_NUM);
- if (port >= RTW_PORT_NUM)
+ if (port >= RTW_PORT_NUM) {
+ mutex_unlock(&rtwdev->mutex);
return -EINVAL;
+ }
set_bit(port, rtwdev->hw_port);
rtwvif->port = port;
@@ -376,6 +382,7 @@ static void rtw_ops_bss_info_changed(struct ieee80211_hw *hw,
rtw_fw_download_rsvd_page(rtwdev);
rtw_send_rsvd_page_h2c(rtwdev);
+ rtw_fw_default_port(rtwdev, rtwvif);
rtw_coex_media_status_notify(rtwdev, vif->cfg.assoc);
if (rtw_bf_support)
rtw_bf_assoc(rtwdev, vif, conf);
@@ -447,6 +454,7 @@ static int rtw_ops_start_ap(struct ieee80211_hw *hw,
const struct rtw_chip_info *chip = rtwdev->chip;
mutex_lock(&rtwdev->mutex);
+ rtw_write32_set(rtwdev, REG_TCR, BIT_TCR_UPDATE_HGQMD);
rtwdev->ap_active = true;
rtw_store_op_chan(rtwdev, true);
chip->ops->phy_calibration(rtwdev);
@@ -462,6 +470,7 @@ static void rtw_ops_stop_ap(struct ieee80211_hw *hw,
struct rtw_dev *rtwdev = hw->priv;
mutex_lock(&rtwdev->mutex);
+ rtw_write32_clr(rtwdev, REG_TCR, BIT_TCR_UPDATE_HGQMD);
rtwdev->ap_active = false;
if (!rtw_core_check_sta_active(rtwdev))
rtw_clear_op_chan(rtwdev);
diff --git a/drivers/net/wireless/realtek/rtw88/main.c b/drivers/net/wireless/realtek/rtw88/main.c
index 9447a3aae3b5..c853e2f2d448 100644
--- a/drivers/net/wireless/realtek/rtw88/main.c
+++ b/drivers/net/wireless/realtek/rtw88/main.c
@@ -334,12 +334,15 @@ int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
struct ieee80211_vif *vif)
{
struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
+ struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
int i;
si->mac_id = rtw_acquire_macid(rtwdev);
if (si->mac_id >= RTW_MAX_MAC_ID_NUM)
return -ENOSPC;
+ if (vif->type == NL80211_IFTYPE_STATION && vif->cfg.assoc == 0)
+ rtwvif->mac_id = si->mac_id;
si->rtwdev = rtwdev;
si->sta = sta;
si->vif = vif;
@@ -2340,6 +2343,9 @@ static void rtw_port_switch_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
rtw_dbg(rtwdev, RTW_DBG_STATE, "AP port switch from %d -> %d\n",
rtwvif_ap->port, rtwvif_target->port);
+ /* Leave LPS so the value swapped are not in PS mode */
+ rtw_leave_lps(rtwdev);
+
reg1 = &rtwvif_ap->conf->net_type;
reg2 = &rtwvif_target->conf->net_type;
rtw_swap_reg_mask(rtwdev, reg1, reg2);
@@ -2358,6 +2364,8 @@ static void rtw_port_switch_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
swap(rtwvif_target->port, rtwvif_ap->port);
swap(rtwvif_target->conf, rtwvif_ap->conf);
+
+ rtw_fw_default_port(rtwdev, rtwvif_target);
}
void rtw_core_port_switch(struct rtw_dev *rtwdev, struct ieee80211_vif *vif)
@@ -2403,10 +2411,13 @@ void rtw_core_enable_beacon(struct rtw_dev *rtwdev, bool enable)
if (!rtwdev->ap_active)
return;
- if (enable)
+ if (enable) {
rtw_write32_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
- else
+ rtw_write32_clr(rtwdev, REG_TXPAUSE, BIT_HIGH_QUEUE);
+ } else {
rtw_write32_clr(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
+ rtw_write32_set(rtwdev, REG_TXPAUSE, BIT_HIGH_QUEUE);
+ }
}
MODULE_AUTHOR("Realtek Corporation");
diff --git a/drivers/net/wireless/realtek/rtw88/main.h b/drivers/net/wireless/realtek/rtw88/main.h
index 9e841f6991a9..f9dd2ab941c8 100644
--- a/drivers/net/wireless/realtek/rtw88/main.h
+++ b/drivers/net/wireless/realtek/rtw88/main.h
@@ -803,6 +803,7 @@ struct rtw_bf_info {
struct rtw_vif {
enum rtw_net_type net_type;
u16 aid;
+ u8 mac_id; /* for STA mode only */
u8 mac_addr[ETH_ALEN];
u8 bssid[ETH_ALEN];
u8 port;
diff --git a/drivers/net/wireless/realtek/rtw88/pci.c b/drivers/net/wireless/realtek/rtw88/pci.c
index 672ddde80816..44a8fff34cdd 100644
--- a/drivers/net/wireless/realtek/rtw88/pci.c
+++ b/drivers/net/wireless/realtek/rtw88/pci.c
@@ -738,8 +738,9 @@ static void __rtw_pci_flush_queues(struct rtw_dev *rtwdev, u32 pci_queues,
u8 q;
for (q = 0; q < RTK_MAX_TX_QUEUE_NUM; q++) {
- /* It may be not necessary to flush BCN and H2C tx queues. */
- if (q == RTW_TX_QUEUE_BCN || q == RTW_TX_QUEUE_H2C)
+ /* Unnecessary to flush BCN, H2C and HI tx queues. */
+ if (q == RTW_TX_QUEUE_BCN || q == RTW_TX_QUEUE_H2C ||
+ q == RTW_TX_QUEUE_HI0)
continue;
if (pci_queues & BIT(q))
diff --git a/drivers/net/wireless/realtek/rtw88/ps.c b/drivers/net/wireless/realtek/rtw88/ps.c
index 53933fb38a33..43e80a3a8136 100644
--- a/drivers/net/wireless/realtek/rtw88/ps.c
+++ b/drivers/net/wireless/realtek/rtw88/ps.c
@@ -18,6 +18,7 @@ static int rtw_ips_pwr_up(struct rtw_dev *rtwdev)
if (ret)
rtw_err(rtwdev, "leave idle state failed\n");
+ rtw_coex_ips_notify(rtwdev, COEX_IPS_LEAVE);
rtw_set_channel(rtwdev);
return ret;
@@ -63,8 +64,6 @@ int rtw_leave_ips(struct rtw_dev *rtwdev)
rtw_iterate_vifs(rtwdev, rtw_restore_port_cfg_iter, rtwdev);
- rtw_coex_ips_notify(rtwdev, COEX_IPS_LEAVE);
-
return 0;
}
diff --git a/drivers/net/wireless/realtek/rtw88/reg.h b/drivers/net/wireless/realtek/rtw88/reg.h
index 2a2ae2081f34..7c6c11d50ff3 100644
--- a/drivers/net/wireless/realtek/rtw88/reg.h
+++ b/drivers/net/wireless/realtek/rtw88/reg.h
@@ -378,6 +378,7 @@
#define BIT_SIFS_BK_EN BIT(12)
#define REG_TXPAUSE 0x0522
#define BIT_AC_QUEUE GENMASK(7, 0)
+#define BIT_HIGH_QUEUE BIT(5)
#define REG_RD_CTRL 0x0524
#define BIT_EDCCA_MSK_CNTDOWN_EN BIT(11)
#define BIT_DIS_TXOP_CFE BIT(10)
@@ -410,6 +411,7 @@
#define REG_TCR 0x0604
#define BIT_PWRMGT_HWDATA_EN BIT(7)
#define BIT_TCR_UPDATE_TIMIE BIT(5)
+#define BIT_TCR_UPDATE_HGQMD BIT(4)
#define REG_RCR 0x0608
#define BIT_APP_FCS BIT(31)
#define BIT_APP_MIC BIT(30)
diff --git a/drivers/net/wireless/realtek/rtw88/rtw8723d.c b/drivers/net/wireless/realtek/rtw88/rtw8723d.c
index 06e7454c9ca6..c575476a0020 100644
--- a/drivers/net/wireless/realtek/rtw88/rtw8723d.c
+++ b/drivers/net/wireless/realtek/rtw88/rtw8723d.c
@@ -216,6 +216,12 @@ static void rtw8723du_efuse_parsing(struct rtw_efuse *efuse,
ether_addr_copy(efuse->addr, map->u.mac_addr);
}
+static void rtw8723ds_efuse_parsing(struct rtw_efuse *efuse,
+ struct rtw8723d_efuse *map)
+{
+ ether_addr_copy(efuse->addr, map->s.mac_addr);
+}
+
static int rtw8723d_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
{
struct rtw_efuse *efuse = &rtwdev->efuse;
@@ -248,6 +254,9 @@ static int rtw8723d_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
case RTW_HCI_TYPE_USB:
rtw8723du_efuse_parsing(efuse, map);
break;
+ case RTW_HCI_TYPE_SDIO:
+ rtw8723ds_efuse_parsing(efuse, map);
+ break;
default:
/* unsupported now */
return -ENOTSUPP;
@@ -1961,15 +1970,17 @@ static void rtw8723d_fill_txdesc_checksum(struct rtw_dev *rtwdev,
size_t words = 32 / 2; /* calculate the first 32 bytes (16 words) */
__le16 chksum = 0;
__le16 *data = (__le16 *)(txdesc);
+ struct rtw_tx_desc *tx_desc = (struct rtw_tx_desc *)txdesc;
- SET_TX_DESC_TXDESC_CHECKSUM(txdesc, 0x0000);
+ le32p_replace_bits(&tx_desc->w7, 0, RTW_TX_DESC_W7_TXDESC_CHECKSUM);
while (words--)
chksum ^= *data++;
chksum = ~chksum;
- SET_TX_DESC_TXDESC_CHECKSUM(txdesc, __le16_to_cpu(chksum));
+ le32p_replace_bits(&tx_desc->w7, __le16_to_cpu(chksum),
+ RTW_TX_DESC_W7_TXDESC_CHECKSUM);
}
static struct rtw_chip_ops rtw8723d_ops = {
diff --git a/drivers/net/wireless/realtek/rtw88/rtw8723d.h b/drivers/net/wireless/realtek/rtw88/rtw8723d.h
index a356318a5c15..3642a2c7f80c 100644
--- a/drivers/net/wireless/realtek/rtw88/rtw8723d.h
+++ b/drivers/net/wireless/realtek/rtw88/rtw8723d.h
@@ -49,6 +49,11 @@ struct rtw8723du_efuse {
u8 mac_addr[ETH_ALEN]; /* 0x107 */
};
+struct rtw8723ds_efuse {
+ u8 res4[0x4a]; /* 0xd0 */
+ u8 mac_addr[ETH_ALEN]; /* 0x11a */
+};
+
struct rtw8723d_efuse {
__le16 rtl_id;
u8 rsvd[2];
@@ -80,6 +85,7 @@ struct rtw8723d_efuse {
union {
struct rtw8723de_efuse e;
struct rtw8723du_efuse u;
+ struct rtw8723ds_efuse s;
};
};
diff --git a/drivers/net/wireless/realtek/rtw88/rtw8723ds.c b/drivers/net/wireless/realtek/rtw88/rtw8723ds.c
new file mode 100644
index 000000000000..e5b6960ba0a0
--- /dev/null
+++ b/drivers/net/wireless/realtek/rtw88/rtw8723ds.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/* Copyright(c) Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ */
+
+#include <linux/mmc/sdio_func.h>
+#include <linux/mmc/sdio_ids.h>
+#include <linux/module.h>
+#include "main.h"
+#include "rtw8723d.h"
+#include "sdio.h"
+
+static const struct sdio_device_id rtw_8723ds_id_table[] = {
+ {
+ SDIO_DEVICE(SDIO_VENDOR_ID_REALTEK,
+ SDIO_DEVICE_ID_REALTEK_RTW8723DS_1ANT),
+ .driver_data = (kernel_ulong_t)&rtw8723d_hw_spec,
+ },
+ {
+ SDIO_DEVICE(SDIO_VENDOR_ID_REALTEK,
+ SDIO_DEVICE_ID_REALTEK_RTW8723DS_2ANT),
+ .driver_data = (kernel_ulong_t)&rtw8723d_hw_spec,
+ },
+ {}
+};
+MODULE_DEVICE_TABLE(sdio, rtw_8723ds_id_table);
+
+static struct sdio_driver rtw_8723ds_driver = {
+ .name = "rtw_8723ds",
+ .probe = rtw_sdio_probe,
+ .remove = rtw_sdio_remove,
+ .id_table = rtw_8723ds_id_table,
+ .drv = {
+ .pm = &rtw_sdio_pm_ops,
+ .shutdown = rtw_sdio_shutdown,
+ }
+};
+module_sdio_driver(rtw_8723ds_driver);
+
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
+MODULE_DESCRIPTION("Realtek 802.11n wireless 8723ds driver");
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/net/wireless/realtek/rtw88/sdio.c b/drivers/net/wireless/realtek/rtw88/sdio.c
index 06fce7c3adda..2c1fb2dabd40 100644
--- a/drivers/net/wireless/realtek/rtw88/sdio.c
+++ b/drivers/net/wireless/realtek/rtw88/sdio.c
@@ -998,9 +998,9 @@ static void rtw_sdio_rxfifo_recv(struct rtw_dev *rtwdev, u32 rx_len)
static void rtw_sdio_rx_isr(struct rtw_dev *rtwdev)
{
- u32 rx_len, total_rx_bytes = 0;
+ u32 rx_len, hisr, total_rx_bytes = 0;
- while (total_rx_bytes < SZ_64K) {
+ do {
if (rtw_chip_wcpu_11n(rtwdev))
rx_len = rtw_read16(rtwdev, REG_SDIO_RX0_REQ_LEN);
else
@@ -1012,7 +1012,25 @@ static void rtw_sdio_rx_isr(struct rtw_dev *rtwdev)
rtw_sdio_rxfifo_recv(rtwdev, rx_len);
total_rx_bytes += rx_len;
- }
+
+ if (rtw_chip_wcpu_11n(rtwdev)) {
+ /* Stop if no more RX requests are pending, even if
+ * rx_len could be greater than zero in the next
+ * iteration. This is needed because the RX buffer may
+ * already contain data while either HW or FW are not
+ * done filling that buffer yet. Still reading the
+ * buffer can result in packets where
+ * rtw_rx_pkt_stat.pkt_len is zero or points beyond the
+ * end of the buffer.
+ */
+ hisr = rtw_read32(rtwdev, REG_SDIO_HISR);
+ } else {
+ /* RTW_WCPU_11AC chips have improved hardware or
+ * firmware and can use rx_len unconditionally.
+ */
+ hisr = REG_SDIO_HISR_RX_REQUEST;
+ }
+ } while (total_rx_bytes < SZ_64K && hisr & REG_SDIO_HISR_RX_REQUEST);
}
static void rtw_sdio_handle_interrupt(struct sdio_func *sdio_func)
diff --git a/drivers/net/wireless/realtek/rtw88/tx.c b/drivers/net/wireless/realtek/rtw88/tx.c
index bb5c7492c98b..2821119dc930 100644
--- a/drivers/net/wireless/realtek/rtw88/tx.c
+++ b/drivers/net/wireless/realtek/rtw88/tx.c
@@ -34,43 +34,57 @@ void rtw_tx_stats(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
void rtw_tx_fill_tx_desc(struct rtw_tx_pkt_info *pkt_info, struct sk_buff *skb)
{
- __le32 *txdesc = (__le32 *)skb->data;
-
- SET_TX_DESC_TXPKTSIZE(txdesc, pkt_info->tx_pkt_size);
- SET_TX_DESC_OFFSET(txdesc, pkt_info->offset);
- SET_TX_DESC_PKT_OFFSET(txdesc, pkt_info->pkt_offset);
- SET_TX_DESC_QSEL(txdesc, pkt_info->qsel);
- SET_TX_DESC_BMC(txdesc, pkt_info->bmc);
- SET_TX_DESC_RATE_ID(txdesc, pkt_info->rate_id);
- SET_TX_DESC_DATARATE(txdesc, pkt_info->rate);
- SET_TX_DESC_DISDATAFB(txdesc, pkt_info->dis_rate_fallback);
- SET_TX_DESC_USE_RATE(txdesc, pkt_info->use_rate);
- SET_TX_DESC_SEC_TYPE(txdesc, pkt_info->sec_type);
- SET_TX_DESC_DATA_BW(txdesc, pkt_info->bw);
- SET_TX_DESC_SW_SEQ(txdesc, pkt_info->seq);
- SET_TX_DESC_MAX_AGG_NUM(txdesc, pkt_info->ampdu_factor);
- SET_TX_DESC_AMPDU_DENSITY(txdesc, pkt_info->ampdu_density);
- SET_TX_DESC_DATA_STBC(txdesc, pkt_info->stbc);
- SET_TX_DESC_DATA_LDPC(txdesc, pkt_info->ldpc);
- SET_TX_DESC_AGG_EN(txdesc, pkt_info->ampdu_en);
- SET_TX_DESC_LS(txdesc, pkt_info->ls);
- SET_TX_DESC_DATA_SHORT(txdesc, pkt_info->short_gi);
- SET_TX_DESC_SPE_RPT(txdesc, pkt_info->report);
- SET_TX_DESC_SW_DEFINE(txdesc, pkt_info->sn);
- SET_TX_DESC_USE_RTS(txdesc, pkt_info->rts);
+ struct rtw_tx_desc *tx_desc = (struct rtw_tx_desc *)skb->data;
+ bool more_data = false;
+
+ if (pkt_info->qsel == TX_DESC_QSEL_HIGH)
+ more_data = true;
+
+ tx_desc->w0 = le32_encode_bits(pkt_info->tx_pkt_size, RTW_TX_DESC_W0_TXPKTSIZE) |
+ le32_encode_bits(pkt_info->offset, RTW_TX_DESC_W0_OFFSET) |
+ le32_encode_bits(pkt_info->bmc, RTW_TX_DESC_W0_BMC) |
+ le32_encode_bits(pkt_info->ls, RTW_TX_DESC_W0_LS) |
+ le32_encode_bits(pkt_info->dis_qselseq, RTW_TX_DESC_W0_DISQSELSEQ);
+
+ tx_desc->w1 = le32_encode_bits(pkt_info->qsel, RTW_TX_DESC_W1_QSEL) |
+ le32_encode_bits(pkt_info->rate_id, RTW_TX_DESC_W1_RATE_ID) |
+ le32_encode_bits(pkt_info->sec_type, RTW_TX_DESC_W1_SEC_TYPE) |
+ le32_encode_bits(pkt_info->pkt_offset, RTW_TX_DESC_W1_PKT_OFFSET) |
+ le32_encode_bits(more_data, RTW_TX_DESC_W1_MORE_DATA);
+
+ tx_desc->w2 = le32_encode_bits(pkt_info->ampdu_en, RTW_TX_DESC_W2_AGG_EN) |
+ le32_encode_bits(pkt_info->report, RTW_TX_DESC_W2_SPE_RPT) |
+ le32_encode_bits(pkt_info->ampdu_density, RTW_TX_DESC_W2_AMPDU_DEN) |
+ le32_encode_bits(pkt_info->bt_null, RTW_TX_DESC_W2_BT_NULL);
+
+ tx_desc->w3 = le32_encode_bits(pkt_info->hw_ssn_sel, RTW_TX_DESC_W3_HW_SSN_SEL) |
+ le32_encode_bits(pkt_info->use_rate, RTW_TX_DESC_W3_USE_RATE) |
+ le32_encode_bits(pkt_info->dis_rate_fallback, RTW_TX_DESC_W3_DISDATAFB) |
+ le32_encode_bits(pkt_info->rts, RTW_TX_DESC_W3_USE_RTS) |
+ le32_encode_bits(pkt_info->nav_use_hdr, RTW_TX_DESC_W3_NAVUSEHDR) |
+ le32_encode_bits(pkt_info->ampdu_factor, RTW_TX_DESC_W3_MAX_AGG_NUM);
+
+ tx_desc->w4 = le32_encode_bits(pkt_info->rate, RTW_TX_DESC_W4_DATARATE);
+
+ tx_desc->w5 = le32_encode_bits(pkt_info->short_gi, RTW_TX_DESC_W5_DATA_SHORT) |
+ le32_encode_bits(pkt_info->bw, RTW_TX_DESC_W5_DATA_BW) |
+ le32_encode_bits(pkt_info->ldpc, RTW_TX_DESC_W5_DATA_LDPC) |
+ le32_encode_bits(pkt_info->stbc, RTW_TX_DESC_W5_DATA_STBC);
+
+ tx_desc->w6 = le32_encode_bits(pkt_info->sn, RTW_TX_DESC_W6_SW_DEFINE);
+
+ tx_desc->w8 = le32_encode_bits(pkt_info->en_hwseq, RTW_TX_DESC_W8_EN_HWSEQ);
+
+ tx_desc->w9 = le32_encode_bits(pkt_info->seq, RTW_TX_DESC_W9_SW_SEQ);
+
if (pkt_info->rts) {
- SET_TX_DESC_RTSRATE(txdesc, DESC_RATE24M);
- SET_TX_DESC_DATA_RTS_SHORT(txdesc, 1);
- }
- SET_TX_DESC_DISQSELSEQ(txdesc, pkt_info->dis_qselseq);
- SET_TX_DESC_EN_HWSEQ(txdesc, pkt_info->en_hwseq);
- SET_TX_DESC_HW_SSN_SEL(txdesc, pkt_info->hw_ssn_sel);
- SET_TX_DESC_NAVUSEHDR(txdesc, pkt_info->nav_use_hdr);
- SET_TX_DESC_BT_NULL(txdesc, pkt_info->bt_null);
- if (pkt_info->tim_offset) {
- SET_TX_DESC_TIM_EN(txdesc, 1);
- SET_TX_DESC_TIM_OFFSET(txdesc, pkt_info->tim_offset);
+ tx_desc->w4 |= le32_encode_bits(DESC_RATE24M, RTW_TX_DESC_W4_RTSRATE);
+ tx_desc->w5 |= le32_encode_bits(1, RTW_TX_DESC_W5_DATA_RTS_SHORT);
}
+
+ if (pkt_info->tim_offset)
+ tx_desc->w9 |= le32_encode_bits(1, RTW_TX_DESC_W9_TIM_EN) |
+ le32_encode_bits(pkt_info->tim_offset, RTW_TX_DESC_W9_TIM_OFFSET);
}
EXPORT_SYMBOL(rtw_tx_fill_tx_desc);
@@ -635,9 +649,8 @@ static void rtw_txq_push(struct rtw_dev *rtwdev,
rcu_read_unlock();
}
-void rtw_tx_work(struct work_struct *w)
+void __rtw_tx_work(struct rtw_dev *rtwdev)
{
- struct rtw_dev *rtwdev = container_of(w, struct rtw_dev, tx_work);
struct rtw_txq *rtwtxq, *tmp;
spin_lock_bh(&rtwdev->txq_lock);
@@ -658,6 +671,13 @@ void rtw_tx_work(struct work_struct *w)
spin_unlock_bh(&rtwdev->txq_lock);
}
+void rtw_tx_work(struct work_struct *w)
+{
+ struct rtw_dev *rtwdev = container_of(w, struct rtw_dev, tx_work);
+
+ __rtw_tx_work(rtwdev);
+}
+
void rtw_txq_init(struct rtw_dev *rtwdev, struct ieee80211_txq *txq)
{
struct rtw_txq *rtwtxq;
diff --git a/drivers/net/wireless/realtek/rtw88/tx.h b/drivers/net/wireless/realtek/rtw88/tx.h
index 197d5868c8ad..324189606257 100644
--- a/drivers/net/wireless/realtek/rtw88/tx.h
+++ b/drivers/net/wireless/realtek/rtw88/tx.h
@@ -9,76 +9,53 @@
#define RTW_TX_PROBE_TIMEOUT msecs_to_jiffies(500)
-#define SET_TX_DESC_TXPKTSIZE(txdesc, value) \
- le32p_replace_bits((__le32 *)(txdesc) + 0x00, value, GENMASK(15, 0))
-#define SET_TX_DESC_OFFSET(txdesc, value) \
- le32p_replace_bits((__le32 *)(txdesc) + 0x00, value, GENMASK(23, 16))
-#define SET_TX_DESC_PKT_OFFSET(txdesc, value) \
- le32p_replace_bits((__le32 *)(txdesc) + 0x01, value, GENMASK(28, 24))
-#define SET_TX_DESC_QSEL(txdesc, value) \
- le32p_replace_bits((__le32 *)(txdesc) + 0x01, value, GENMASK(12, 8))
-#define SET_TX_DESC_BMC(txdesc, value) \
- le32p_replace_bits((__le32 *)(txdesc) + 0x00, value, BIT(24))
-#define SET_TX_DESC_RATE_ID(txdesc, value) \
- le32p_replace_bits((__le32 *)(txdesc) + 0x01, value, GENMASK(20, 16))
-#define SET_TX_DESC_DATARATE(txdesc, value) \
- le32p_replace_bits((__le32 *)(txdesc) + 0x04, value, GENMASK(6, 0))
-#define SET_TX_DESC_DISDATAFB(txdesc, value) \
- le32p_replace_bits((__le32 *)(txdesc) + 0x03, value, BIT(10))
-#define SET_TX_DESC_USE_RATE(txdesc, value) \
- le32p_replace_bits((__le32 *)(txdesc) + 0x03, value, BIT(8))
-#define SET_TX_DESC_SEC_TYPE(txdesc, value) \
- le32p_replace_bits((__le32 *)(txdesc) + 0x01, value, GENMASK(23, 22))
-#define SET_TX_DESC_DATA_BW(txdesc, value) \
- le32p_replace_bits((__le32 *)(txdesc) + 0x05, value, GENMASK(6, 5))
-#define SET_TX_DESC_SW_SEQ(txdesc, value) \
- le32p_replace_bits((__le32 *)(txdesc) + 0x09, value, GENMASK(23, 12))
-#define SET_TX_DESC_TIM_EN(txdesc, value) \
- le32p_replace_bits((__le32 *)(txdesc) + 0x09, value, BIT(7))
-#define SET_TX_DESC_TIM_OFFSET(txdesc, value) \
- le32p_replace_bits((__le32 *)(txdesc) + 0x09, value, GENMASK(6, 0))
-#define SET_TX_DESC_MAX_AGG_NUM(txdesc, value) \
- le32p_replace_bits((__le32 *)(txdesc) + 0x03, value, GENMASK(21, 17))
-#define SET_TX_DESC_USE_RTS(tx_desc, value) \
- le32p_replace_bits((__le32 *)(txdesc) + 0x03, value, BIT(12))
-#define SET_TX_DESC_RTSRATE(txdesc, value) \
- le32p_replace_bits((__le32 *)(txdesc) + 0x04, value, GENMASK(28, 24))
-#define SET_TX_DESC_DATA_RTS_SHORT(txdesc, value) \
- le32p_replace_bits((__le32 *)(txdesc) + 0x05, value, BIT(12))
-#define SET_TX_DESC_AMPDU_DENSITY(txdesc, value) \
- le32p_replace_bits((__le32 *)(txdesc) + 0x02, value, GENMASK(22, 20))
-#define SET_TX_DESC_DATA_STBC(txdesc, value) \
- le32p_replace_bits((__le32 *)(txdesc) + 0x05, value, GENMASK(9, 8))
-#define SET_TX_DESC_DATA_LDPC(txdesc, value) \
- le32p_replace_bits((__le32 *)(txdesc) + 0x05, value, BIT(7))
-#define SET_TX_DESC_AGG_EN(txdesc, value) \
- le32p_replace_bits((__le32 *)(txdesc) + 0x02, value, BIT(12))
-#define SET_TX_DESC_LS(txdesc, value) \
- le32p_replace_bits((__le32 *)(txdesc) + 0x00, value, BIT(26))
-#define SET_TX_DESC_DATA_SHORT(txdesc, value) \
- le32p_replace_bits((__le32 *)(txdesc) + 0x05, value, BIT(4))
-#define SET_TX_DESC_SPE_RPT(tx_desc, value) \
- le32p_replace_bits((__le32 *)(txdesc) + 0x02, value, BIT(19))
-#define SET_TX_DESC_SW_DEFINE(tx_desc, value) \
- le32p_replace_bits((__le32 *)(txdesc) + 0x06, value, GENMASK(11, 0))
-#define SET_TX_DESC_DISQSELSEQ(txdesc, value) \
- le32p_replace_bits((__le32 *)(txdesc) + 0x00, value, BIT(31))
-#define SET_TX_DESC_EN_HWSEQ(txdesc, value) \
- le32p_replace_bits((__le32 *)(txdesc) + 0x08, value, BIT(15))
-#define SET_TX_DESC_HW_SSN_SEL(txdesc, value) \
- le32p_replace_bits((__le32 *)(txdesc) + 0x03, value, GENMASK(7, 6))
-#define SET_TX_DESC_NAVUSEHDR(txdesc, value) \
- le32p_replace_bits((__le32 *)(txdesc) + 0x03, value, BIT(15))
-#define SET_TX_DESC_BT_NULL(txdesc, value) \
- le32p_replace_bits((__le32 *)(txdesc) + 0x02, value, BIT(23))
-#define SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value) \
- le32p_replace_bits((__le32 *)(txdesc) + 0x07, value, GENMASK(15, 0))
-#define SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value) \
- le32p_replace_bits((__le32 *)(txdesc) + 0x07, value, GENMASK(31, 24))
-#define GET_TX_DESC_PKT_OFFSET(txdesc) \
- le32_get_bits(*((__le32 *)(txdesc) + 0x01), GENMASK(28, 24))
-#define GET_TX_DESC_QSEL(txdesc) \
- le32_get_bits(*((__le32 *)(txdesc) + 0x01), GENMASK(12, 8))
+struct rtw_tx_desc {
+ __le32 w0;
+ __le32 w1;
+ __le32 w2;
+ __le32 w3;
+ __le32 w4;
+ __le32 w5;
+ __le32 w6;
+ __le32 w7;
+ __le32 w8;
+ __le32 w9;
+} __packed;
+
+#define RTW_TX_DESC_W0_TXPKTSIZE GENMASK(15, 0)
+#define RTW_TX_DESC_W0_OFFSET GENMASK(23, 16)
+#define RTW_TX_DESC_W0_BMC BIT(24)
+#define RTW_TX_DESC_W0_LS BIT(26)
+#define RTW_TX_DESC_W0_DISQSELSEQ BIT(31)
+#define RTW_TX_DESC_W1_QSEL GENMASK(12, 8)
+#define RTW_TX_DESC_W1_RATE_ID GENMASK(20, 16)
+#define RTW_TX_DESC_W1_SEC_TYPE GENMASK(23, 22)
+#define RTW_TX_DESC_W1_PKT_OFFSET GENMASK(28, 24)
+#define RTW_TX_DESC_W1_MORE_DATA BIT(29)
+#define RTW_TX_DESC_W2_AGG_EN BIT(12)
+#define RTW_TX_DESC_W2_SPE_RPT BIT(19)
+#define RTW_TX_DESC_W2_AMPDU_DEN GENMASK(22, 20)
+#define RTW_TX_DESC_W2_BT_NULL BIT(23)
+#define RTW_TX_DESC_W3_HW_SSN_SEL GENMASK(7, 6)
+#define RTW_TX_DESC_W3_USE_RATE BIT(8)
+#define RTW_TX_DESC_W3_DISDATAFB BIT(10)
+#define RTW_TX_DESC_W3_USE_RTS BIT(12)
+#define RTW_TX_DESC_W3_NAVUSEHDR BIT(15)
+#define RTW_TX_DESC_W3_MAX_AGG_NUM GENMASK(21, 17)
+#define RTW_TX_DESC_W4_DATARATE GENMASK(6, 0)
+#define RTW_TX_DESC_W4_RTSRATE GENMASK(28, 24)
+#define RTW_TX_DESC_W5_DATA_SHORT BIT(4)
+#define RTW_TX_DESC_W5_DATA_BW GENMASK(6, 5)
+#define RTW_TX_DESC_W5_DATA_LDPC BIT(7)
+#define RTW_TX_DESC_W5_DATA_STBC GENMASK(9, 8)
+#define RTW_TX_DESC_W5_DATA_RTS_SHORT BIT(12)
+#define RTW_TX_DESC_W6_SW_DEFINE GENMASK(11, 0)
+#define RTW_TX_DESC_W7_TXDESC_CHECKSUM GENMASK(15, 0)
+#define RTW_TX_DESC_W7_DMA_TXAGG_NUM GENMASK(31, 24)
+#define RTW_TX_DESC_W8_EN_HWSEQ BIT(15)
+#define RTW_TX_DESC_W9_SW_SEQ GENMASK(23, 12)
+#define RTW_TX_DESC_W9_TIM_EN BIT(7)
+#define RTW_TX_DESC_W9_TIM_OFFSET GENMASK(6, 0)
enum rtw_tx_desc_queue_select {
TX_DESC_QSEL_TID0 = 0,
@@ -111,6 +88,7 @@ void rtw_tx(struct rtw_dev *rtwdev,
void rtw_txq_init(struct rtw_dev *rtwdev, struct ieee80211_txq *txq);
void rtw_txq_cleanup(struct rtw_dev *rtwdev, struct ieee80211_txq *txq);
void rtw_tx_work(struct work_struct *w);
+void __rtw_tx_work(struct rtw_dev *rtwdev);
void rtw_tx_pkt_info_update(struct rtw_dev *rtwdev,
struct rtw_tx_pkt_info *pkt_info,
struct ieee80211_sta *sta,
@@ -139,13 +117,15 @@ void fill_txdesc_checksum_common(u8 *txdesc, size_t words)
{
__le16 chksum = 0;
__le16 *data = (__le16 *)(txdesc);
+ struct rtw_tx_desc *tx_desc = (struct rtw_tx_desc *)txdesc;
- SET_TX_DESC_TXDESC_CHECKSUM(txdesc, 0x0000);
+ le32p_replace_bits(&tx_desc->w7, 0, RTW_TX_DESC_W7_TXDESC_CHECKSUM);
while (words--)
chksum ^= *data++;
- SET_TX_DESC_TXDESC_CHECKSUM(txdesc, __le16_to_cpu(chksum));
+ le32p_replace_bits(&tx_desc->w7, __le16_to_cpu(chksum),
+ RTW_TX_DESC_W7_TXDESC_CHECKSUM);
}
static inline void rtw_tx_fill_txdesc_checksum(struct rtw_dev *rtwdev,
diff --git a/drivers/net/wireless/realtek/rtw88/usb.c b/drivers/net/wireless/realtek/rtw88/usb.c
index 44a5fafb9905..4a57efdba97b 100644
--- a/drivers/net/wireless/realtek/rtw88/usb.c
+++ b/drivers/net/wireless/realtek/rtw88/usb.c
@@ -24,11 +24,12 @@ struct rtw_usb_txcb {
static void rtw_usb_fill_tx_checksum(struct rtw_usb *rtwusb,
struct sk_buff *skb, int agg_num)
{
+ struct rtw_tx_desc *tx_desc = (struct rtw_tx_desc *)skb->data;
struct rtw_dev *rtwdev = rtwusb->rtwdev;
struct rtw_tx_pkt_info pkt_info;
- SET_TX_DESC_DMA_TXAGG_NUM(skb->data, agg_num);
- pkt_info.pkt_offset = GET_TX_DESC_PKT_OFFSET(skb->data);
+ le32p_replace_bits(&tx_desc->w7, agg_num, RTW_TX_DESC_W7_DMA_TXAGG_NUM);
+ pkt_info.pkt_offset = le32_get_bits(tx_desc->w1, RTW_TX_DESC_W1_PKT_OFFSET);
rtw_tx_fill_txdesc_checksum(rtwdev, &pkt_info, skb->data);
}
@@ -306,11 +307,13 @@ static int rtw_usb_write_port(struct rtw_dev *rtwdev, u8 qsel, struct sk_buff *s
static bool rtw_usb_tx_agg_skb(struct rtw_usb *rtwusb, struct sk_buff_head *list)
{
struct rtw_dev *rtwdev = rtwusb->rtwdev;
+ struct rtw_tx_desc *tx_desc;
struct rtw_usb_txcb *txcb;
struct sk_buff *skb_head;
struct sk_buff *skb_iter;
int agg_num = 0;
unsigned int align_next = 0;
+ u8 qsel;
if (skb_queue_empty(list))
return false;
@@ -363,9 +366,10 @@ static bool rtw_usb_tx_agg_skb(struct rtw_usb *rtwusb, struct sk_buff_head *list
queue:
skb_queue_tail(&txcb->tx_ack_queue, skb_head);
+ tx_desc = (struct rtw_tx_desc *)skb_head->data;
+ qsel = le32_get_bits(tx_desc->w1, RTW_TX_DESC_W1_QSEL);
- rtw_usb_write_port(rtwdev, GET_TX_DESC_QSEL(skb_head->data), skb_head,
- rtw_usb_write_port_tx_complete, txcb);
+ rtw_usb_write_port(rtwdev, qsel, skb_head, rtw_usb_write_port_tx_complete, txcb);
return true;
}
@@ -465,6 +469,9 @@ static u8 rtw_usb_tx_queue_mapping_to_qsel(struct sk_buff *skb)
if (unlikely(ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc)))
qsel = TX_DESC_QSEL_MGMT;
+ else if (is_broadcast_ether_addr(hdr->addr1) ||
+ is_multicast_ether_addr(hdr->addr1))
+ qsel = TX_DESC_QSEL_HIGH;
else if (skb_get_queue_mapping(skb) <= IEEE80211_AC_BK)
qsel = skb->priority;
else
@@ -535,7 +542,7 @@ static void rtw_usb_rx_handler(struct work_struct *work)
}
if (skb_queue_len(&rtwusb->rx_queue) >= RTW_USB_MAX_RXQ_LEN) {
- rtw_err(rtwdev, "failed to get rx_queue, overflow\n");
+ dev_dbg_ratelimited(rtwdev->dev, "failed to get rx_queue, overflow\n");
dev_kfree_skb_any(skb);
continue;
}
diff --git a/drivers/net/wireless/realtek/rtw89/Kconfig b/drivers/net/wireless/realtek/rtw89/Kconfig
index 2b20cf8bbf3a..90ffbab7cc4c 100644
--- a/drivers/net/wireless/realtek/rtw89/Kconfig
+++ b/drivers/net/wireless/realtek/rtw89/Kconfig
@@ -16,6 +16,9 @@ config RTW89_CORE
config RTW89_PCI
tristate
+config RTW89_8851B
+ tristate
+
config RTW89_8852A
tristate
@@ -25,6 +28,17 @@ config RTW89_8852B
config RTW89_8852C
tristate
+config RTW89_8851BE
+ tristate "Realtek 8851BE PCI wireless network (Wi-Fi 6) adapter"
+ depends on PCI
+ select RTW89_CORE
+ select RTW89_PCI
+ select RTW89_8851B
+ help
+ Select this option will enable support for 8851BE chipset
+
+ 802.11ax PCIe wireless network (Wi-Fi 6) adapter
+
config RTW89_8852AE
tristate "Realtek 8852AE PCI wireless network (Wi-Fi 6) adapter"
depends on PCI
diff --git a/drivers/net/wireless/realtek/rtw89/Makefile b/drivers/net/wireless/realtek/rtw89/Makefile
index 2dc48fa10c6b..41940099af1b 100644
--- a/drivers/net/wireless/realtek/rtw89/Makefile
+++ b/drivers/net/wireless/realtek/rtw89/Makefile
@@ -13,10 +13,20 @@ rtw89_core-y += core.o \
coex.o \
ps.o \
chan.o \
- ser.o
+ ser.o \
+ acpi.o
rtw89_core-$(CONFIG_PM) += wow.o
+obj-$(CONFIG_RTW89_8851B) += rtw89_8851b.o
+rtw89_8851b-objs := rtw8851b.o \
+ rtw8851b_table.o \
+ rtw8851b_rfk.o \
+ rtw8851b_rfk_table.o
+
+obj-$(CONFIG_RTW89_8851BE) += rtw89_8851be.o
+rtw89_8851be-objs := rtw8851be.o
+
obj-$(CONFIG_RTW89_8852A) += rtw89_8852a.o
rtw89_8852a-objs := rtw8852a.o \
rtw8852a_table.o \
diff --git a/drivers/net/wireless/realtek/rtw89/acpi.c b/drivers/net/wireless/realtek/rtw89/acpi.c
new file mode 100644
index 000000000000..8aaf83a2a6b4
--- /dev/null
+++ b/drivers/net/wireless/realtek/rtw89/acpi.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/* Copyright(c) 2021-2023 Realtek Corporation
+ */
+
+#include <linux/acpi.h>
+#include <linux/uuid.h>
+
+#include "acpi.h"
+#include "debug.h"
+
+static const guid_t rtw89_guid = GUID_INIT(0xD2A8C3E8, 0x4B69, 0x4F00,
+ 0x82, 0xBD, 0xFE, 0x86,
+ 0x07, 0x80, 0x3A, 0xA7);
+
+static int rtw89_acpi_dsm_get(struct rtw89_dev *rtwdev, union acpi_object *obj,
+ u8 *value)
+{
+ switch (obj->type) {
+ case ACPI_TYPE_INTEGER:
+ *value = (u8)obj->integer.value;
+ break;
+ case ACPI_TYPE_BUFFER:
+ *value = obj->buffer.pointer[0];
+ break;
+ default:
+ rtw89_debug(rtwdev, RTW89_DBG_UNEXP,
+ "acpi dsm return unhandled type: %d\n", obj->type);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+int rtw89_acpi_evaluate_dsm(struct rtw89_dev *rtwdev,
+ enum rtw89_acpi_dsm_func func, u8 *value)
+{
+ union acpi_object *obj;
+ int ret;
+
+ obj = acpi_evaluate_dsm(ACPI_HANDLE(rtwdev->dev), &rtw89_guid,
+ 0, func, NULL);
+ if (!obj) {
+ rtw89_debug(rtwdev, RTW89_DBG_UNEXP,
+ "acpi dsm fail to evaluate func: %d\n", func);
+ return -ENOENT;
+ }
+
+ ret = rtw89_acpi_dsm_get(rtwdev, obj, value);
+
+ ACPI_FREE(obj);
+ return ret;
+}
diff --git a/drivers/net/wireless/realtek/rtw89/acpi.h b/drivers/net/wireless/realtek/rtw89/acpi.h
new file mode 100644
index 000000000000..ed74d8ceb733
--- /dev/null
+++ b/drivers/net/wireless/realtek/rtw89/acpi.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
+/* Copyright(c) 2021-2023 Realtek Corporation
+ */
+
+#ifndef __RTW89_ACPI_H__
+#define __RTW89_ACPI_H__
+
+#include "core.h"
+
+enum rtw89_acpi_dsm_func {
+ RTW89_ACPI_DSM_FUNC_IDN_BAND_SUP = 2,
+ RTW89_ACPI_DSM_FUNC_6G_DIS = 3,
+ RTW89_ACPI_DSM_FUNC_6G_BP = 4,
+ RTW89_ACPI_DSM_FUNC_TAS_EN = 5,
+ RTW89_ACPI_DSM_FUNC_59G_EN = 6,
+};
+
+int rtw89_acpi_evaluate_dsm(struct rtw89_dev *rtwdev,
+ enum rtw89_acpi_dsm_func func, u8 *value);
+
+#endif
diff --git a/drivers/net/wireless/realtek/rtw89/coex.c b/drivers/net/wireless/realtek/rtw89/coex.c
index acb3fac0c96d..bda0e1e99a8c 100644
--- a/drivers/net/wireless/realtek/rtw89/coex.c
+++ b/drivers/net/wireless/realtek/rtw89/coex.c
@@ -127,6 +127,13 @@ static const u32 cxtbl[] = {
static const struct rtw89_btc_ver rtw89_btc_ver_defs[] = {
/* firmware version must be in decreasing order for each chip */
+ {RTL8851B, RTW89_FW_VER_CODE(0, 29, 29, 0),
+ .fcxbtcrpt = 105, .fcxtdma = 3, .fcxslots = 1, .fcxcysta = 5,
+ .fcxstep = 3, .fcxnullsta = 2, .fcxmreg = 2, .fcxgpiodbg = 1,
+ .fcxbtver = 1, .fcxbtscan = 2, .fcxbtafh = 2, .fcxbtdevinfo = 1,
+ .fwlrole = 1, .frptmap = 3, .fcxctrl = 1,
+ .info_buf = 1800, .max_role_num = 6,
+ },
{RTL8852C, RTW89_FW_VER_CODE(0, 27, 57, 0),
.fcxbtcrpt = 4, .fcxtdma = 3, .fcxslots = 1, .fcxcysta = 3,
.fcxstep = 3, .fcxnullsta = 2, .fcxmreg = 1, .fcxgpiodbg = 1,
@@ -199,7 +206,7 @@ static const struct rtw89_btc_ver rtw89_btc_ver_defs[] = {
struct rtw89_btc_btf_tlv {
u8 type;
u8 len;
- u8 val[1];
+ u8 val[];
} __packed;
enum btc_btf_set_report_en {
diff --git a/drivers/net/wireless/realtek/rtw89/core.c b/drivers/net/wireless/realtek/rtw89/core.c
index bad864d56bd5..69b181fa2966 100644
--- a/drivers/net/wireless/realtek/rtw89/core.c
+++ b/drivers/net/wireless/realtek/rtw89/core.c
@@ -77,6 +77,9 @@ static struct ieee80211_channel rtw89_channels_5ghz[] = {
RTW89_DEF_CHAN_5G(5785, 157),
RTW89_DEF_CHAN_5G(5805, 161),
RTW89_DEF_CHAN_5G_NO_HT40MINUS(5825, 165),
+ RTW89_DEF_CHAN_5G(5845, 169),
+ RTW89_DEF_CHAN_5G(5865, 173),
+ RTW89_DEF_CHAN_5G(5885, 177),
};
static struct ieee80211_channel rtw89_channels_6ghz[] = {
@@ -333,8 +336,7 @@ void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev)
sub_entity_idx = RTW89_SUB_ENTITY_0;
phy_idx = RTW89_PHY_0;
chan = rtw89_chan_get(rtwdev, sub_entity_idx);
- if (chip->ops->set_txpwr)
- chip->ops->set_txpwr(rtwdev, chan, phy_idx);
+ chip->ops->set_txpwr(rtwdev, chan, phy_idx);
}
void rtw89_set_channel(struct rtw89_dev *rtwdev)
@@ -370,7 +372,7 @@ void rtw89_set_channel(struct rtw89_dev *rtwdev)
chip->ops->set_channel(rtwdev, &chan, mac_idx, phy_idx);
- rtw89_core_set_chip_txpwr(rtwdev);
+ chip->ops->set_txpwr(rtwdev, &chan, phy_idx);
rtw89_chip_set_channel_done(rtwdev, &bak, &chan, mac_idx, phy_idx);
@@ -1210,14 +1212,15 @@ static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev,
struct sk_buff *skb,
struct rtw89_rx_phy_ppdu *phy_ppdu)
{
+ const struct rtw89_rxinfo *rxinfo = (const struct rtw89_rxinfo *)skb->data;
bool rx_cnt_valid = false;
u8 plcp_size = 0;
u8 usr_num = 0;
u8 *phy_sts;
- rx_cnt_valid = RTW89_GET_RXINFO_RX_CNT_VLD(skb->data);
- plcp_size = RTW89_GET_RXINFO_PLCP_LEN(skb->data) << 3;
- usr_num = RTW89_GET_RXINFO_USR_NUM(skb->data);
+ rx_cnt_valid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_RX_CNT_VLD);
+ plcp_size = le32_get_bits(rxinfo->w1, RTW89_RXINFO_W1_PLCP_LEN) << 3;
+ usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM);
if (usr_num > RTW89_PPDU_MAX_USR) {
rtw89_warn(rtwdev, "Invalid user number in mac info\n");
return -EINVAL;
@@ -1244,18 +1247,40 @@ static void rtw89_core_rx_process_phy_ppdu_iter(void *data,
struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
struct rtw89_rx_phy_ppdu *phy_ppdu = (struct rtw89_rx_phy_ppdu *)data;
struct rtw89_dev *rtwdev = rtwsta->rtwdev;
+ struct rtw89_hal *hal = &rtwdev->hal;
+ u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num;
+ u8 ant_pos = U8_MAX;
+ u8 evm_pos = 0;
int i;
- if (rtwsta->mac_id == phy_ppdu->mac_id && phy_ppdu->to_self) {
- ewma_rssi_add(&rtwsta->avg_rssi, phy_ppdu->rssi_avg);
+ if (rtwsta->mac_id != phy_ppdu->mac_id || !phy_ppdu->to_self)
+ return;
+
+ if (hal->ant_diversity && hal->antenna_rx) {
+ ant_pos = __ffs(hal->antenna_rx);
+ evm_pos = ant_pos;
+ }
+
+ ewma_rssi_add(&rtwsta->avg_rssi, phy_ppdu->rssi_avg);
+
+ if (ant_pos < ant_num) {
+ ewma_rssi_add(&rtwsta->rssi[ant_pos], phy_ppdu->rssi[0]);
+ } else {
for (i = 0; i < rtwdev->chip->rf_path_num; i++)
ewma_rssi_add(&rtwsta->rssi[i], phy_ppdu->rssi[i]);
}
+
+ if (phy_ppdu->ofdm.has) {
+ ewma_snr_add(&rtwsta->avg_snr, phy_ppdu->ofdm.avg_snr);
+ ewma_evm_add(&rtwsta->evm_min[evm_pos], phy_ppdu->ofdm.evm_min);
+ ewma_evm_add(&rtwsta->evm_max[evm_pos], phy_ppdu->ofdm.evm_max);
+ }
}
#define VAR_LEN 0xff
#define VAR_LEN_UNIT 8
-static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev, u8 *addr)
+static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev,
+ const struct rtw89_phy_sts_iehdr *iehdr)
{
static const u8 physts_ie_len_tab[32] = {
16, 32, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN,
@@ -1265,45 +1290,58 @@ static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev, u8 *addr)
u16 ie_len;
u8 ie;
- ie = RTW89_GET_PHY_STS_IE_TYPE(addr);
+ ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE);
if (physts_ie_len_tab[ie] != VAR_LEN)
ie_len = physts_ie_len_tab[ie];
else
- ie_len = RTW89_GET_PHY_STS_IE_LEN(addr) * VAR_LEN_UNIT;
+ ie_len = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_LEN) * VAR_LEN_UNIT;
return ie_len;
}
-static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev, u8 *addr,
+static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev,
+ const struct rtw89_phy_sts_iehdr *iehdr,
struct rtw89_rx_phy_ppdu *phy_ppdu)
{
+ const struct rtw89_phy_sts_ie0 *ie = (const struct rtw89_phy_sts_ie0 *)iehdr;
s16 cfo;
+ u32 t;
- phy_ppdu->chan_idx = RTW89_GET_PHY_STS_IE01_CH_IDX(addr);
+ phy_ppdu->chan_idx = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_CH_IDX);
if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6)
return;
if (!phy_ppdu->to_self)
return;
+ phy_ppdu->ofdm.avg_snr = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_AVG_SNR);
+ phy_ppdu->ofdm.evm_max = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MAX);
+ phy_ppdu->ofdm.evm_min = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MIN);
+ phy_ppdu->ofdm.has = true;
+
/* sign conversion for S(12,2) */
- if (rtwdev->chip->cfo_src_fd)
- cfo = sign_extend32(RTW89_GET_PHY_STS_IE01_FD_CFO(addr), 11);
- else
- cfo = sign_extend32(RTW89_GET_PHY_STS_IE01_PREMB_CFO(addr), 11);
+ if (rtwdev->chip->cfo_src_fd) {
+ t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_FD_CFO);
+ cfo = sign_extend32(t, 11);
+ } else {
+ t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_PREMB_CFO);
+ cfo = sign_extend32(t, 11);
+ }
rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu);
}
-static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev, u8 *addr,
+static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev,
+ const struct rtw89_phy_sts_iehdr *iehdr,
struct rtw89_rx_phy_ppdu *phy_ppdu)
{
u8 ie;
- ie = RTW89_GET_PHY_STS_IE_TYPE(addr);
+ ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE);
+
switch (ie) {
case RTW89_PHYSTS_IE01_CMN_OFDM:
- rtw89_core_parse_phy_status_ie01(rtwdev, addr, phy_ppdu);
+ rtw89_core_parse_phy_status_ie01(rtwdev, iehdr, phy_ppdu);
break;
default:
break;
@@ -1314,28 +1352,30 @@ static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev, u8 *addr,
static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu)
{
+ const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf;
u8 *rssi = phy_ppdu->rssi;
- u8 *buf = phy_ppdu->buf;
- phy_ppdu->ie = RTW89_GET_PHY_STS_IE_MAP(buf);
- phy_ppdu->rssi_avg = RTW89_GET_PHY_STS_RSSI_AVG(buf);
- rssi[RF_PATH_A] = RTW89_GET_PHY_STS_RSSI_A(buf);
- rssi[RF_PATH_B] = RTW89_GET_PHY_STS_RSSI_B(buf);
- rssi[RF_PATH_C] = RTW89_GET_PHY_STS_RSSI_C(buf);
- rssi[RF_PATH_D] = RTW89_GET_PHY_STS_RSSI_D(buf);
+ phy_ppdu->ie = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_IE_MAP);
+ phy_ppdu->rssi_avg = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_RSSI_AVG);
+ rssi[RF_PATH_A] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_A);
+ rssi[RF_PATH_B] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_B);
+ rssi[RF_PATH_C] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_C);
+ rssi[RF_PATH_D] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_D);
}
static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev,
struct rtw89_rx_phy_ppdu *phy_ppdu)
{
- if (RTW89_GET_PHY_STS_LEN(phy_ppdu->buf) << 3 != phy_ppdu->len) {
+ const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf;
+ u32 len_from_header;
+
+ len_from_header = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_LEN) << 3;
+
+ if (len_from_header != phy_ppdu->len) {
rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "phy ppdu len mismatch\n");
return -EINVAL;
}
rtw89_core_update_phy_ppdu(phy_ppdu);
- ieee80211_iterate_stations_atomic(rtwdev->hw,
- rtw89_core_rx_process_phy_ppdu_iter,
- phy_ppdu);
return 0;
}
@@ -1344,17 +1384,19 @@ static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev,
struct rtw89_rx_phy_ppdu *phy_ppdu)
{
u16 ie_len;
- u8 *pos, *end;
+ void *pos, *end;
/* mark invalid reports and bypass them */
if (phy_ppdu->ie < RTW89_CCK_PKT)
return -EINVAL;
- pos = (u8 *)phy_ppdu->buf + PHY_STS_HDR_LEN;
- end = (u8 *)phy_ppdu->buf + phy_ppdu->len;
+ pos = phy_ppdu->buf + PHY_STS_HDR_LEN;
+ end = phy_ppdu->buf + phy_ppdu->len;
while (pos < end) {
- ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, pos);
- rtw89_core_process_phy_status_ie(rtwdev, pos, phy_ppdu);
+ const struct rtw89_phy_sts_iehdr *iehdr = pos;
+
+ ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, iehdr);
+ rtw89_core_process_phy_status_ie(rtwdev, iehdr, phy_ppdu);
pos += ie_len;
if (pos > end || ie_len == 0) {
rtw89_debug(rtwdev, RTW89_DBG_TXRX,
@@ -1363,6 +1405,8 @@ static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev,
}
}
+ rtw89_phy_antdiv_parse(rtwdev, phy_ppdu);
+
return 0;
}
@@ -1376,6 +1420,10 @@ static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev,
rtw89_debug(rtwdev, RTW89_DBG_TXRX, "parse phy sts failed\n");
else
phy_ppdu->valid = true;
+
+ ieee80211_iterate_stations_atomic(rtwdev->hw,
+ rtw89_core_rx_process_phy_ppdu_iter,
+ phy_ppdu);
}
static u8 rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev *rtwdev,
@@ -1481,6 +1529,34 @@ static void rtw89_stats_trigger_frame(struct rtw89_dev *rtwdev,
}
}
+static void rtw89_cancel_6ghz_probe_work(struct work_struct *work)
+{
+ struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
+ cancel_6ghz_probe_work);
+ struct list_head *pkt_list = rtwdev->scan_info.pkt_list;
+ struct rtw89_pktofld_info *info;
+
+ mutex_lock(&rtwdev->mutex);
+
+ if (!rtwdev->scanning)
+ goto out;
+
+ list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) {
+ if (!info->cancel || !test_bit(info->id, rtwdev->pkt_offload))
+ continue;
+
+ rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id);
+
+ /* Don't delete/free info from pkt_list at this moment. Let it
+ * be deleted/freed in rtw89_release_pkt_list() after scanning,
+ * since if during scanning, pkt_list is accessed in bottom half.
+ */
+ }
+
+out:
+ mutex_unlock(&rtwdev->mutex);
+}
+
static void rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev *rtwdev,
struct sk_buff *skb)
{
@@ -1489,6 +1565,7 @@ static void rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev *rtwdev,
struct list_head *pkt_list = rtwdev->scan_info.pkt_list;
struct rtw89_pktofld_info *info;
const u8 *ies = mgmt->u.beacon.variable, *ssid_ie;
+ bool queue_work = false;
if (rx_status->band != NL80211_BAND_6GHZ)
return;
@@ -1497,16 +1574,22 @@ static void rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev *rtwdev,
list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) {
if (ether_addr_equal(info->bssid, mgmt->bssid)) {
- rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id);
+ info->cancel = true;
+ queue_work = true;
continue;
}
if (!ssid_ie || ssid_ie[1] != info->ssid_len || info->ssid_len == 0)
continue;
- if (memcmp(&ssid_ie[2], info->ssid, info->ssid_len) == 0)
- rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id);
+ if (memcmp(&ssid_ie[2], info->ssid, info->ssid_len) == 0) {
+ info->cancel = true;
+ queue_work = true;
+ }
}
+
+ if (queue_work)
+ ieee80211_queue_work(rtwdev->hw, &rtwdev->cancel_6ghz_probe_work);
}
static void rtw89_vif_rx_stats_iter(void *data, u8 *mac,
@@ -1722,43 +1805,47 @@ void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev,
u8 shift_len, drv_info_len;
rxd_s = (struct rtw89_rxdesc_short *)(data + data_offset);
- desc_info->pkt_size = RTW89_GET_RXWD_PKT_SIZE(rxd_s);
- desc_info->drv_info_size = RTW89_GET_RXWD_DRV_INFO_SIZE(rxd_s);
- desc_info->long_rxdesc = RTW89_GET_RXWD_LONG_RXD(rxd_s);
- desc_info->pkt_type = RTW89_GET_RXWD_RPKT_TYPE(rxd_s);
- desc_info->mac_info_valid = RTW89_GET_RXWD_MAC_INFO_VALID(rxd_s);
+ desc_info->pkt_size = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_LEN_MASK);
+ desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, AX_RXD_DRV_INFO_SIZE_MASK);
+ desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, AX_RXD_LONG_RXD);
+ desc_info->pkt_type = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_TYPE_MASK);
+ desc_info->mac_info_valid = le32_get_bits(rxd_s->dword0, AX_RXD_MAC_INFO_VLD);
if (chip->chip_id == RTL8852C)
- desc_info->bw = RTW89_GET_RXWD_BW_V1(rxd_s);
+ desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_v1_MASK);
else
- desc_info->bw = RTW89_GET_RXWD_BW(rxd_s);
- desc_info->data_rate = RTW89_GET_RXWD_DATA_RATE(rxd_s);
- desc_info->gi_ltf = RTW89_GET_RXWD_GI_LTF(rxd_s);
- desc_info->user_id = RTW89_GET_RXWD_USER_ID(rxd_s);
- desc_info->sr_en = RTW89_GET_RXWD_SR_EN(rxd_s);
- desc_info->ppdu_cnt = RTW89_GET_RXWD_PPDU_CNT(rxd_s);
- desc_info->ppdu_type = RTW89_GET_RXWD_PPDU_TYPE(rxd_s);
- desc_info->free_run_cnt = RTW89_GET_RXWD_FREE_RUN_CNT(rxd_s);
- desc_info->icv_err = RTW89_GET_RXWD_ICV_ERR(rxd_s);
- desc_info->crc32_err = RTW89_GET_RXWD_CRC32_ERR(rxd_s);
- desc_info->hw_dec = RTW89_GET_RXWD_HW_DEC(rxd_s);
- desc_info->sw_dec = RTW89_GET_RXWD_SW_DEC(rxd_s);
- desc_info->addr1_match = RTW89_GET_RXWD_A1_MATCH(rxd_s);
+ desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_MASK);
+ desc_info->data_rate = le32_get_bits(rxd_s->dword1, AX_RXD_RX_DATARATE_MASK);
+ desc_info->gi_ltf = le32_get_bits(rxd_s->dword1, AX_RXD_RX_GI_LTF_MASK);
+ desc_info->user_id = le32_get_bits(rxd_s->dword1, AX_RXD_USER_ID_MASK);
+ desc_info->sr_en = le32_get_bits(rxd_s->dword1, AX_RXD_SR_EN);
+ desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_CNT_MASK);
+ desc_info->ppdu_type = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_TYPE_MASK);
+ desc_info->free_run_cnt = le32_get_bits(rxd_s->dword2, AX_RXD_FREERUN_CNT_MASK);
+ desc_info->icv_err = le32_get_bits(rxd_s->dword3, AX_RXD_ICV_ERR);
+ desc_info->crc32_err = le32_get_bits(rxd_s->dword3, AX_RXD_CRC32_ERR);
+ desc_info->hw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_HW_DEC);
+ desc_info->sw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_SW_DEC);
+ desc_info->addr1_match = le32_get_bits(rxd_s->dword3, AX_RXD_A1_MATCH);
shift_len = desc_info->shift << 1; /* 2-byte unit */
drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */
desc_info->offset = data_offset + shift_len + drv_info_len;
+ if (desc_info->long_rxdesc)
+ desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long);
+ else
+ desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short);
desc_info->ready = true;
if (!desc_info->long_rxdesc)
return;
rxd_l = (struct rtw89_rxdesc_long *)(data + data_offset);
- desc_info->frame_type = RTW89_GET_RXWD_TYPE(rxd_l);
- desc_info->addr_cam_valid = RTW89_GET_RXWD_ADDR_CAM_VLD(rxd_l);
- desc_info->addr_cam_id = RTW89_GET_RXWD_ADDR_CAM_ID(rxd_l);
- desc_info->sec_cam_id = RTW89_GET_RXWD_SEC_CAM_ID(rxd_l);
- desc_info->mac_id = RTW89_GET_RXWD_MAC_ID(rxd_l);
- desc_info->rx_pl_id = RTW89_GET_RXWD_RX_PL_ID(rxd_l);
+ desc_info->frame_type = le32_get_bits(rxd_l->dword4, AX_RXD_TYPE_MASK);
+ desc_info->addr_cam_valid = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_VLD);
+ desc_info->addr_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_MASK);
+ desc_info->sec_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_SEC_CAM_IDX_MASK);
+ desc_info->mac_id = le32_get_bits(rxd_l->dword5, AX_RXD_MAC_ID_MASK);
+ desc_info->rx_pl_id = le32_get_bits(rxd_l->dword5, AX_RXD_RX_PL_ID_MASK);
}
EXPORT_SYMBOL(rtw89_core_query_rxdesc);
@@ -2593,6 +2680,7 @@ static void rtw89_track_work(struct work_struct *work)
rtw89_phy_ra_update(rtwdev);
rtw89_phy_cfo_track(rtwdev);
rtw89_phy_tx_path_div_track(rtwdev);
+ rtw89_phy_antdiv_track(rtwdev);
rtw89_phy_ul_tb_ctrl_track(rtwdev);
if (rtwdev->lps_enabled && !rtwdev->btc.lps)
@@ -2756,6 +2844,8 @@ int rtw89_core_sta_add(struct rtw89_dev *rtwdev,
{
struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
+ struct rtw89_hal *hal = &rtwdev->hal;
+ u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num;
int i;
int ret;
@@ -2769,12 +2859,18 @@ int rtw89_core_sta_add(struct rtw89_dev *rtwdev,
rtw89_core_txq_init(rtwdev, sta->txq[i]);
ewma_rssi_init(&rtwsta->avg_rssi);
- for (i = 0; i < rtwdev->chip->rf_path_num; i++)
+ ewma_snr_init(&rtwsta->avg_snr);
+ for (i = 0; i < ant_num; i++) {
ewma_rssi_init(&rtwsta->rssi[i]);
+ ewma_evm_init(&rtwsta->evm_min[i]);
+ ewma_evm_init(&rtwsta->evm_max[i]);
+ }
if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
/* for station mode, assign the mac_id from itself */
rtwsta->mac_id = rtwvif->mac_id;
+ /* must do rtw89_reg_6ghz_power_recalc() before rfk channel */
+ rtw89_reg_6ghz_power_recalc(rtwdev, rtwvif, true);
rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta,
BTC_ROLE_MSTS_STA_CONN_START);
rtw89_chip_rfk_channel(rtwdev);
@@ -2948,10 +3044,11 @@ int rtw89_core_sta_remove(struct rtw89_dev *rtwdev,
struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
int ret;
- if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls)
+ if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
+ rtw89_reg_6ghz_power_recalc(rtwdev, rtwvif, false);
rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta,
BTC_ROLE_MSTS_STA_DIS_CONN);
- else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) {
+ } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) {
rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwsta->mac_id);
ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta,
@@ -3292,8 +3389,10 @@ static void rtw89_core_clr_supported_band(struct rtw89_dev *rtwdev)
{
struct ieee80211_hw *hw = rtwdev->hw;
- kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]->iftype_data);
- kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]->iftype_data);
+ if (hw->wiphy->bands[NL80211_BAND_2GHZ])
+ kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]->iftype_data);
+ if (hw->wiphy->bands[NL80211_BAND_5GHZ])
+ kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]->iftype_data);
if (hw->wiphy->bands[NL80211_BAND_6GHZ])
kfree(hw->wiphy->bands[NL80211_BAND_6GHZ]->iftype_data);
kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]);
@@ -3430,6 +3529,7 @@ void rtw89_core_stop(struct rtw89_dev *rtwdev)
mutex_unlock(&rtwdev->mutex);
cancel_work_sync(&rtwdev->c2h_work);
+ cancel_work_sync(&rtwdev->cancel_6ghz_probe_work);
cancel_work_sync(&btc->eapol_notify_work);
cancel_work_sync(&btc->arp_notify_work);
cancel_work_sync(&btc->dhcp_notify_work);
@@ -3441,6 +3541,7 @@ void rtw89_core_stop(struct rtw89_dev *rtwdev)
cancel_delayed_work_sync(&rtwdev->coex_rfk_chk_work);
cancel_delayed_work_sync(&rtwdev->cfo_track_work);
cancel_delayed_work_sync(&rtwdev->forbid_ba_work);
+ cancel_delayed_work_sync(&rtwdev->antdiv_work);
mutex_lock(&rtwdev->mutex);
@@ -3476,6 +3577,7 @@ int rtw89_core_init(struct rtw89_dev *rtwdev)
INIT_DELAYED_WORK(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work);
INIT_DELAYED_WORK(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work);
INIT_DELAYED_WORK(&rtwdev->forbid_ba_work, rtw89_forbid_ba_work);
+ INIT_DELAYED_WORK(&rtwdev->antdiv_work, rtw89_phy_antdiv_work);
rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0);
if (!rtwdev->txq_wq)
return -ENOMEM;
@@ -3486,10 +3588,12 @@ int rtw89_core_init(struct rtw89_dev *rtwdev)
rtwdev->total_sta_assoc = 0;
rtw89_init_wait(&rtwdev->mcc.wait);
+ rtw89_init_wait(&rtwdev->mac.fw_ofld_wait);
INIT_WORK(&rtwdev->c2h_work, rtw89_fw_c2h_work);
INIT_WORK(&rtwdev->ips_work, rtw89_ips_work);
INIT_WORK(&rtwdev->load_firmware_work, rtw89_load_firmware_work);
+ INIT_WORK(&rtwdev->cancel_6ghz_probe_work, rtw89_cancel_6ghz_probe_work);
skb_queue_head_init(&rtwdev->c2h_queue);
rtw89_core_ppdu_sts_init(rtwdev);
@@ -3584,7 +3688,7 @@ static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev)
if (chip->chip_id == RTL8852B || chip->chip_id == RTL8851B) {
ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CV, &val);
- if (!ret)
+ if (ret)
return;
rtwdev->hal.acv = u8_get_bits(val, XTAL_SI_ACV_MASK);
@@ -3693,6 +3797,7 @@ static int rtw89_core_register_hw(struct rtw89_dev *rtwdev)
{
struct ieee80211_hw *hw = rtwdev->hw;
struct rtw89_efuse *efuse = &rtwdev->efuse;
+ struct rtw89_hal *hal = &rtwdev->hal;
int ret;
int tx_headroom = IEEE80211_HT_CTL_LEN;
@@ -3731,8 +3836,13 @@ static int rtw89_core_register_hw(struct rtw89_dev *rtwdev)
BIT(NL80211_IFTYPE_P2P_CLIENT) |
BIT(NL80211_IFTYPE_P2P_GO);
- hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1;
- hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1;
+ if (hal->ant_diversity) {
+ hw->wiphy->available_antennas_tx = 0x3;
+ hw->wiphy->available_antennas_rx = 0x3;
+ } else {
+ hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1;
+ hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1;
+ }
hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS |
WIPHY_FLAG_TDLS_EXTERNAL_SETUP |
@@ -3760,7 +3870,12 @@ static int rtw89_core_register_hw(struct rtw89_dev *rtwdev)
return ret;
}
- hw->wiphy->reg_notifier = rtw89_regd_notifier;
+ ret = rtw89_regd_setup(rtwdev);
+ if (ret) {
+ rtw89_err(rtwdev, "failed to set up regd\n");
+ goto err_free_supported_band;
+ }
+
hw->wiphy->sar_capa = &rtw89_sar_capa;
ret = ieee80211_register_hw(hw);
diff --git a/drivers/net/wireless/realtek/rtw89/core.h b/drivers/net/wireless/realtek/rtw89/core.h
index 6df386a38fb4..d2c67db97db1 100644
--- a/drivers/net/wireless/realtek/rtw89/core.h
+++ b/drivers/net/wireless/realtek/rtw89/core.h
@@ -122,6 +122,13 @@ enum rtw89_cv {
CHIP_CV_INVALID = CHIP_CV_MAX,
};
+enum rtw89_bacam_ver {
+ RTW89_BACAM_V0,
+ RTW89_BACAM_V1,
+
+ RTW89_BACAM_V0_EXT = 99,
+};
+
enum rtw89_core_tx_type {
RTW89_CORE_TX_TYPE_DATA,
RTW89_CORE_TX_TYPE_MGMT,
@@ -244,7 +251,7 @@ enum rtw89_band {
RTW89_BAND_2G = 0,
RTW89_BAND_5G = 1,
RTW89_BAND_6G = 2,
- RTW89_BAND_MAX,
+ RTW89_BAND_NUM,
};
enum rtw89_hw_rate {
@@ -427,27 +434,27 @@ enum rtw89_rate_section {
RTW89_RS_MCS, /* for HT/VHT/HE */
RTW89_RS_HEDCM,
RTW89_RS_OFFSET,
- RTW89_RS_MAX,
+ RTW89_RS_NUM,
RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1,
RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1,
};
-enum rtw89_rate_max {
- RTW89_RATE_CCK_MAX = 4,
- RTW89_RATE_OFDM_MAX = 8,
- RTW89_RATE_MCS_MAX = 12,
- RTW89_RATE_HEDCM_MAX = 4, /* for HEDCM MCS0/1/3/4 */
- RTW89_RATE_OFFSET_MAX = 5, /* for HE(HEDCM)/VHT/HT/OFDM/CCK offset */
+enum rtw89_rate_num {
+ RTW89_RATE_CCK_NUM = 4,
+ RTW89_RATE_OFDM_NUM = 8,
+ RTW89_RATE_MCS_NUM = 12,
+ RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */
+ RTW89_RATE_OFFSET_NUM = 5, /* for HE(HEDCM)/VHT/HT/OFDM/CCK offset */
};
enum rtw89_nss {
RTW89_NSS_1 = 0,
RTW89_NSS_2 = 1,
/* HE DCM only support 1ss and 2ss */
- RTW89_NSS_HEDCM_MAX = RTW89_NSS_2 + 1,
+ RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1,
RTW89_NSS_3 = 2,
RTW89_NSS_4 = 3,
- RTW89_NSS_MAX,
+ RTW89_NSS_NUM,
};
enum rtw89_ntx {
@@ -481,6 +488,15 @@ enum rtw89_regulation_type {
RTW89_REGD_NUM,
};
+enum rtw89_reg_6ghz_power {
+ RTW89_REG_6GHZ_POWER_VLP = 0,
+ RTW89_REG_6GHZ_POWER_LPI = 1,
+ RTW89_REG_6GHZ_POWER_STD = 2,
+
+ NUM_OF_RTW89_REG_6GHZ_POWER,
+ RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP,
+};
+
enum rtw89_fw_pkt_ofld_type {
RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0,
RTW89_PKT_OFLD_TYPE_PS_POLL = 1,
@@ -496,11 +512,11 @@ enum rtw89_fw_pkt_ofld_type {
};
struct rtw89_txpwr_byrate {
- s8 cck[RTW89_RATE_CCK_MAX];
- s8 ofdm[RTW89_RATE_OFDM_MAX];
- s8 mcs[RTW89_NSS_MAX][RTW89_RATE_MCS_MAX];
- s8 hedcm[RTW89_NSS_HEDCM_MAX][RTW89_RATE_HEDCM_MAX];
- s8 offset[RTW89_RATE_OFFSET_MAX];
+ s8 cck[RTW89_RATE_CCK_NUM];
+ s8 ofdm[RTW89_RATE_OFDM_NUM];
+ s8 mcs[RTW89_NSS_NUM][RTW89_RATE_MCS_NUM];
+ s8 hedcm[RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM];
+ s8 offset[RTW89_RATE_OFFSET_NUM];
};
enum rtw89_bandwidth_section_num {
@@ -543,7 +559,7 @@ struct rtw89_rate_desc {
#define RF_PATH_MAX 4
#define RTW89_MAX_PPDU_CNT 8
struct rtw89_rx_phy_ppdu {
- u8 *buf;
+ void *buf;
u32 len;
u8 rssi_avg;
u8 rssi[RF_PATH_MAX];
@@ -551,6 +567,12 @@ struct rtw89_rx_phy_ppdu {
u8 chan_idx;
u8 ie;
u16 rate;
+ struct {
+ bool has;
+ u8 avg_snr;
+ u8 evm_max;
+ u8 evm_min;
+ } ofdm;
bool to_self;
bool valid;
};
@@ -763,6 +785,7 @@ struct rtw89_rx_desc_info {
u8 sec_cam_id;
u8 mac_id;
u16 offset;
+ u16 rxd_len;
bool ready;
};
@@ -1382,7 +1405,6 @@ struct rtw89_btc_wl_nhm {
u8 current_status;
u8 refresh;
bool start_flag;
- u8 last_ccx_rpt_stamp;
s8 pwr_max;
s8 pwr_min;
};
@@ -2533,6 +2555,8 @@ struct rtw89_ra_report {
};
DECLARE_EWMA(rssi, 10, 16);
+DECLARE_EWMA(evm, 10, 16);
+DECLARE_EWMA(snr, 10, 16);
struct rtw89_ba_cam_entry {
struct list_head list;
@@ -2595,6 +2619,9 @@ struct rtw89_sta {
u8 prev_rssi;
struct ewma_rssi avg_rssi;
struct ewma_rssi rssi[RF_PATH_MAX];
+ struct ewma_snr avg_snr;
+ struct ewma_evm evm_min[RF_PATH_MAX];
+ struct ewma_evm evm_max[RF_PATH_MAX];
struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS];
struct ieee80211_rx_status rx_status;
u16 rx_hw_rate;
@@ -2663,6 +2690,7 @@ struct rtw89_vif {
struct rtw89_dev *rtwdev;
struct rtw89_roc roc;
enum rtw89_sub_entity_idx sub_entity_idx;
+ enum rtw89_reg_6ghz_power reg_6ghz_power;
u8 mac_id;
u8 port;
@@ -2781,6 +2809,7 @@ struct rtw89_chip_ops {
int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map);
int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map);
void (*fem_setup)(struct rtw89_dev *rtwdev);
+ void (*rfe_gpio)(struct rtw89_dev *rtwdev);
void (*rfk_init)(struct rtw89_dev *rtwdev);
void (*rfk_channel)(struct rtw89_dev *rtwdev);
void (*rfk_band_changed)(struct rtw89_dev *rtwdev,
@@ -2805,6 +2834,9 @@ struct rtw89_chip_ops {
s8 pw_ofst, enum rtw89_mac_idx mac_idx);
int (*pwr_on_func)(struct rtw89_dev *rtwdev);
int (*pwr_off_func)(struct rtw89_dev *rtwdev);
+ void (*query_rxdesc)(struct rtw89_dev *rtwdev,
+ struct rtw89_rx_desc_info *desc_info,
+ u8 *data, u32 data_offset);
void (*fill_txdesc)(struct rtw89_dev *rtwdev,
struct rtw89_tx_desc_info *desc_info,
void *txdesc);
@@ -3013,9 +3045,11 @@ struct rtw89_txpwr_rule_5ghz {
struct rtw89_txpwr_rule_6ghz {
const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM]
[RTW89_RS_LMT_NUM][RTW89_BF_NUM]
- [RTW89_REGD_NUM][RTW89_6G_CH_NUM];
+ [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
+ [RTW89_6G_CH_NUM];
const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
- [RTW89_REGD_NUM][RTW89_6G_CH_NUM];
+ [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
+ [RTW89_6G_CH_NUM];
};
struct rtw89_rfe_parms {
@@ -3090,6 +3124,12 @@ struct rtw89_imr_info {
u32 tmac_imr_set;
};
+struct rtw89_xtal_info {
+ u32 xcap_reg;
+ u32 sc_xo_mask;
+ u32 sc_xi_mask;
+};
+
struct rtw89_rrsr_cfgs {
struct rtw89_reg3_def ref_rate;
struct rtw89_reg3_def rsc;
@@ -3116,6 +3156,25 @@ struct rtw89_phy_ul_tb_info {
u8 def_if_bandedge;
};
+struct rtw89_antdiv_stats {
+ struct ewma_rssi cck_rssi_avg;
+ struct ewma_rssi ofdm_rssi_avg;
+ struct ewma_rssi non_legacy_rssi_avg;
+ u16 pkt_cnt_cck;
+ u16 pkt_cnt_ofdm;
+ u16 pkt_cnt_non_legacy;
+ u32 evm;
+};
+
+struct rtw89_antdiv_info {
+ struct rtw89_antdiv_stats target_stats;
+ struct rtw89_antdiv_stats main_stats;
+ struct rtw89_antdiv_stats aux_stats;
+ u8 training_count;
+ u8 rssi_pre;
+ bool get_stats;
+};
+
struct rtw89_chip_info {
enum rtw89_core_chip_id chip_id;
const struct rtw89_chip_ops *ops;
@@ -3123,6 +3182,7 @@ struct rtw89_chip_info {
u8 fw_format_max;
bool try_ce_fw;
u32 fifo_size;
+ bool small_fifo_size;
u32 dle_scc_rsvd_size;
u16 max_amsdu_limit;
bool dis_2g_40m_ul_ofdma;
@@ -3135,6 +3195,7 @@ struct rtw89_chip_info {
u8 support_chanctx_num;
u8 support_bands;
bool support_bw160;
+ bool support_unii4;
bool support_ul_tb_ctrl;
bool hw_sec_hdr;
u8 rf_path_num;
@@ -3145,7 +3206,7 @@ struct rtw89_chip_info {
u8 scam_num;
u8 bacam_num;
u8 bacam_dynamic_num;
- bool bacam_v1;
+ enum rtw89_bacam_ver bacam_ver;
u8 sec_ctrl_efuse_size;
u32 physical_efuse_size;
@@ -3162,6 +3223,7 @@ struct rtw89_chip_info {
const struct rtw89_phy_table *bb_gain_table;
const struct rtw89_phy_table *rf_table[RF_PATH_MAX];
const struct rtw89_phy_table *nctl_table;
+ const struct rtw89_rfk_tbl *nctl_post_table;
const struct rtw89_txpwr_table *byr_table;
const struct rtw89_phy_dig_gain_table *dig_table;
const struct rtw89_dig_regs *dig_regs;
@@ -3215,6 +3277,7 @@ struct rtw89_chip_info {
u32 dma_ch_mask;
u32 edcca_lvl_reg;
const struct wiphy_wowlan_support *wowlan_stub;
+ const struct rtw89_xtal_info *xtal_info;
};
union rtw89_bus_info {
@@ -3237,7 +3300,6 @@ enum rtw89_hcifc_mode {
struct rtw89_dle_info {
enum rtw89_qta_mode qta_mode;
- u16 wde_pg_size;
u16 ple_pg_size;
u16 c0_rx_qta;
u16 c1_rx_qta;
@@ -3248,14 +3310,6 @@ enum rtw89_host_rpr_mode {
RTW89_RPR_MODE_STF
};
-struct rtw89_mac_info {
- struct rtw89_dle_info dle_info;
- struct rtw89_hfc_param hfc_param;
- enum rtw89_qta_mode qta_mode;
- u8 rpwm_seq_num;
- u8 cpwm_seq_num;
-};
-
#define RTW89_COMPLETION_BUF_SIZE 24
#define RTW89_WAIT_COND_IDLE UINT_MAX
@@ -3278,6 +3332,17 @@ static inline void rtw89_init_wait(struct rtw89_wait_info *wait)
atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE);
}
+struct rtw89_mac_info {
+ struct rtw89_dle_info dle_info;
+ struct rtw89_hfc_param hfc_param;
+ enum rtw89_qta_mode qta_mode;
+ u8 rpwm_seq_num;
+ u8 cpwm_seq_num;
+
+ /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */
+ struct rtw89_wait_info fw_ofld_wait;
+};
+
enum rtw89_fw_type {
RTW89_FW_NORMAL = 1,
RTW89_FW_WOWLAN = 3,
@@ -3322,10 +3387,10 @@ struct rtw89_fw_suit {
(mfw_hdr)->ver.idx)
#define RTW89_FW_HDR_VER_CODE(fw_hdr) \
- RTW89_FW_VER_CODE(GET_FW_HDR_MAJOR_VERSION(fw_hdr), \
- GET_FW_HDR_MINOR_VERSION(fw_hdr), \
- GET_FW_HDR_SUBVERSION(fw_hdr), \
- GET_FW_HDR_SUBINDEX(fw_hdr))
+ RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \
+ le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \
+ le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \
+ le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX))
struct rtw89_fw_req_info {
const struct firmware *firmware;
@@ -3417,12 +3482,13 @@ struct rtw89_hal {
u32 rx_fltr;
u8 cv;
u8 acv;
- u32 sw_amsdu_max_size;
u32 antenna_tx;
u32 antenna_rx;
u8 tx_nss;
u8 rx_nss;
bool tx_path_diversity;
+ bool ant_diversity;
+ bool ant_diversity_fixed;
bool support_cckpd;
bool support_igi;
atomic_t roc_entity_idx;
@@ -3452,6 +3518,7 @@ enum rtw89_flags {
RTW89_FLAG_LOW_POWER_MODE,
RTW89_FLAG_INACTIVE_PS,
RTW89_FLAG_CRASH_SIMULATING,
+ RTW89_FLAG_SER_HANDLING,
RTW89_FLAG_WOWLAN,
RTW89_FLAG_FORBIDDEN_TRACK_WROK,
RTW89_FLAG_CHANGING_INTERFACE,
@@ -3543,7 +3610,6 @@ struct rtw89_iqk_info {
u8 iqk_band[RTW89_IQK_PATH_NR];
u8 iqk_ch[RTW89_IQK_PATH_NR];
u8 iqk_bw[RTW89_IQK_PATH_NR];
- u8 kcount;
u8 iqk_times;
u8 version;
u32 nb_txcfir[RTW89_IQK_PATH_NR];
@@ -3558,8 +3624,6 @@ struct rtw89_iqk_info {
bool iqk_xym_en;
bool iqk_sram_en;
bool iqk_cfir_en;
- u8 thermal[RTW89_IQK_PATH_NR];
- bool thermal_rek_en;
u32 syn1to2;
u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
u8 iqk_table_idx[RTW89_IQK_PATH_NR];
@@ -3749,9 +3813,14 @@ struct rtw89_power_trim_info {
u8 pa_bias_trim[RF_PATH_MAX];
};
-struct rtw89_regulatory {
+struct rtw89_regd {
char alpha2[3];
- u8 txpwr_regd[RTW89_BAND_MAX];
+ u8 txpwr_regd[RTW89_BAND_NUM];
+};
+
+struct rtw89_regulatory_info {
+ const struct rtw89_regd *regd;
+ enum rtw89_reg_6ghz_power reg_6ghz_power;
};
enum rtw89_ifs_clm_application {
@@ -3815,35 +3884,16 @@ enum rtw89_ccx_edcca_opt_bw_idx {
#define RTW89_FAHM_RPT_NUM 12
#define RTW89_IFS_CLM_NUM 4
struct rtw89_env_monitor_info {
- u32 ccx_trigger_time;
- u64 start_time;
- u8 ccx_rpt_stamp;
u8 ccx_watchdog_result;
bool ccx_ongoing;
u8 ccx_rac_lv;
bool ccx_manual_ctrl;
- u8 ccx_pre_rssi;
- u16 clm_mntr_time;
- u16 nhm_mntr_time;
u16 ifs_clm_mntr_time;
enum rtw89_ifs_clm_application ifs_clm_app;
- u16 fahm_mntr_time;
- u16 edcca_clm_mntr_time;
u16 ccx_period;
u8 ccx_unit_idx;
- enum rtw89_ccx_edcca_opt_bw_idx ccx_edcca_opt_bw_idx;
- u8 nhm_th[RTW89_NHM_TH_NUM];
u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM];
u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM];
- u8 fahm_numer_opt;
- u8 fahm_denom_opt;
- u8 fahm_th[RTW89_FAHM_TH_NUM];
- u16 clm_result;
- u16 nhm_result[RTW89_NHM_RPT_NUM];
- u8 nhm_wgt[RTW89_NHM_RPT_NUM];
- u16 nhm_tx_cnt;
- u16 nhm_cca_cnt;
- u16 nhm_idle_cnt;
u16 ifs_clm_tx;
u16 ifs_clm_edcca_excl_cca;
u16 ifs_clm_ofdmfa;
@@ -3854,17 +3904,6 @@ struct rtw89_env_monitor_info {
u8 ifs_clm_his[RTW89_IFS_CLM_NUM];
u16 ifs_clm_avg[RTW89_IFS_CLM_NUM];
u16 ifs_clm_cca[RTW89_IFS_CLM_NUM];
- u16 fahm_result[RTW89_FAHM_RPT_NUM];
- u16 fahm_denom_result;
- u16 edcca_clm_result;
- u8 clm_ratio;
- u8 nhm_rpt[RTW89_NHM_RPT_NUM];
- u8 nhm_tx_ratio;
- u8 nhm_cca_ratio;
- u8 nhm_idle_ratio;
- u8 nhm_ratio;
- u16 nhm_result_sum;
- u8 nhm_pwr;
u8 ifs_clm_tx_ratio;
u8 ifs_clm_edcca_excl_cca_ratio;
u8 ifs_clm_cck_fa_ratio;
@@ -3875,12 +3914,6 @@ struct rtw89_env_monitor_info {
u16 ifs_clm_ofdm_fa_permil;
u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM];
u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM];
- u8 fahm_rpt[RTW89_FAHM_RPT_NUM];
- u16 fahm_result_sum;
- u8 fahm_ratio;
- u8 fahm_denom_ratio;
- u8 fahm_pwr;
- u8 edcca_clm_ratio;
};
enum rtw89_ser_rcvy_step {
@@ -3888,12 +3921,14 @@ enum rtw89_ser_rcvy_step {
RTW89_SER_DRV_STOP_RX,
RTW89_SER_DRV_STOP_RUN,
RTW89_SER_HAL_STOP_DMA,
+ RTW89_SER_SUPPRESS_LOG,
RTW89_NUM_OF_SER_FLAGS
};
struct rtw89_ser {
u8 state;
u8 alarm_event;
+ bool prehandle_l1;
struct work_struct ser_hdl_work;
struct delayed_work ser_alarm_work;
@@ -4054,6 +4089,7 @@ struct rtw89_dev {
struct work_struct c2h_work;
struct work_struct ips_work;
struct work_struct load_firmware_work;
+ struct work_struct cancel_6ghz_probe_work;
struct list_head early_h2c_list;
@@ -4075,7 +4111,7 @@ struct rtw89_dev {
bool is_bt_iqk_timeout;
struct rtw89_fem_info fem;
- struct rtw89_txpwr_byrate byr[RTW89_BAND_MAX];
+ struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM];
struct rtw89_tssi_info tssi;
struct rtw89_power_trim_info pwr_trim;
@@ -4086,6 +4122,7 @@ struct rtw89_dev {
struct rtw89_phy_bb_gain_info bb_gain;
struct rtw89_phy_efuse_gain efuse_gain;
struct rtw89_phy_ul_tb_info ul_tb_info;
+ struct rtw89_antdiv_info antdiv;
struct delayed_work track_work;
struct delayed_work coex_act1_work;
@@ -4094,11 +4131,12 @@ struct rtw89_dev {
struct delayed_work cfo_track_work;
struct delayed_work forbid_ba_work;
struct delayed_work roc_work;
+ struct delayed_work antdiv_work;
struct rtw89_ppdu_sts_info ppdu_sts;
u8 total_sta_assoc;
bool scanning;
- const struct rtw89_regulatory *regd;
+ struct rtw89_regulatory_info regulatory;
struct rtw89_sar_info sar;
struct rtw89_btc btc;
@@ -4643,6 +4681,14 @@ static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev)
chip->ops->fem_setup(rtwdev);
}
+static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev)
+{
+ const struct rtw89_chip_info *chip = rtwdev->chip;
+
+ if (chip->ops->rfe_gpio)
+ chip->ops->rfe_gpio(rtwdev);
+}
+
static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev)
{
const struct rtw89_chip_info *chip = rtwdev->chip;
@@ -4777,7 +4823,9 @@ static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev,
static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band)
{
- return rtwdev->regd->txpwr_regd[band];
+ const struct rtw89_regd *regd = rtwdev->regulatory.regd;
+
+ return regd->txpwr_regd[band];
}
static inline void rtw89_ctrl_btg(struct rtw89_dev *rtwdev, bool btg)
@@ -4789,6 +4837,16 @@ static inline void rtw89_ctrl_btg(struct rtw89_dev *rtwdev, bool btg)
}
static inline
+void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev,
+ struct rtw89_rx_desc_info *desc_info,
+ u8 *data, u32 data_offset)
+{
+ const struct rtw89_chip_info *chip = rtwdev->chip;
+
+ chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset);
+}
+
+static inline
void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev,
struct rtw89_tx_desc_info *desc_info,
void *txdesc)
@@ -4990,6 +5048,7 @@ int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev,
void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc);
int rtw89_chip_info_setup(struct rtw89_dev *rtwdev);
bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate);
+int rtw89_regd_setup(struct rtw89_dev *rtwdev);
int rtw89_regd_init(struct rtw89_dev *rtwdev,
void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request));
void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request);
@@ -5008,5 +5067,7 @@ void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
const u8 *mac_addr, bool hw_scan);
void rtw89_core_scan_complete(struct rtw89_dev *rtwdev,
struct ieee80211_vif *vif, bool hw_scan);
+void rtw89_reg_6ghz_power_recalc(struct rtw89_dev *rtwdev,
+ struct rtw89_vif *rtwvif, bool active);
#endif
diff --git a/drivers/net/wireless/realtek/rtw89/debug.c b/drivers/net/wireless/realtek/rtw89/debug.c
index 1e5b7a998716..1db2d59d33ff 100644
--- a/drivers/net/wireless/realtek/rtw89/debug.c
+++ b/drivers/net/wireless/realtek/rtw89/debug.c
@@ -30,7 +30,7 @@ struct rtw89_debugfs_priv {
u32 cb_data;
struct {
u32 addr;
- u8 len;
+ u32 len;
} read_reg;
struct {
u32 addr;
@@ -164,12 +164,15 @@ static int rtw89_debug_priv_read_reg_get(struct seq_file *m, void *v)
{
struct rtw89_debugfs_priv *debugfs_priv = m->private;
struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
- u32 addr, data;
- u8 len;
+ u32 addr, end, data, k;
+ u32 len;
len = debugfs_priv->read_reg.len;
addr = debugfs_priv->read_reg.addr;
+ if (len > 4)
+ goto ndata;
+
switch (len) {
case 1:
data = rtw89_read8(rtwdev, addr);
@@ -188,6 +191,20 @@ static int rtw89_debug_priv_read_reg_get(struct seq_file *m, void *v)
seq_printf(m, "get %d bytes at 0x%08x=0x%08x\n", len, addr, data);
return 0;
+
+ndata:
+ end = addr + len;
+
+ for (; addr < end; addr += 16) {
+ seq_printf(m, "%08xh : ", 0x18600000 + addr);
+ for (k = 0; k < 16; k += 4) {
+ data = rtw89_read32(rtwdev, addr + k);
+ seq_printf(m, "%08x ", data);
+ }
+ seq_puts(m, "\n");
+ }
+
+ return 0;
}
static ssize_t rtw89_debug_priv_write_reg_set(struct file *filp,
@@ -359,6 +376,7 @@ struct txpwr_map {
u8 size;
u32 addr_from;
u32 addr_to;
+ u32 addr_to_1ss;
};
#define __GEN_TXPWR_ENT2(_t, _e0, _e1) \
@@ -396,6 +414,7 @@ static const struct txpwr_map __txpwr_map_byr = {
.size = ARRAY_SIZE(__txpwr_ent_byr),
.addr_from = R_AX_PWR_BY_RATE,
.addr_to = R_AX_PWR_BY_RATE_MAX,
+ .addr_to_1ss = R_AX_PWR_BY_RATE_1SS_MAX,
};
static const struct txpwr_ent __txpwr_ent_lmt[] = {
@@ -451,6 +470,7 @@ static const struct txpwr_map __txpwr_map_lmt = {
.size = ARRAY_SIZE(__txpwr_ent_lmt),
.addr_from = R_AX_PWR_LMT,
.addr_to = R_AX_PWR_LMT_MAX,
+ .addr_to_1ss = R_AX_PWR_LMT_1SS_MAX,
};
static const struct txpwr_ent __txpwr_ent_lmt_ru[] = {
@@ -478,6 +498,7 @@ static const struct txpwr_map __txpwr_map_lmt_ru = {
.size = ARRAY_SIZE(__txpwr_ent_lmt_ru),
.addr_from = R_AX_PWR_RU_LMT,
.addr_to = R_AX_PWR_RU_LMT_MAX,
+ .addr_to_1ss = R_AX_PWR_RU_LMT_1SS_MAX,
};
static u8 __print_txpwr_ent(struct seq_file *m, const struct txpwr_ent *ent,
@@ -510,6 +531,8 @@ static int __print_txpwr_map(struct seq_file *m, struct rtw89_dev *rtwdev,
const struct txpwr_map *map)
{
u8 fct = rtwdev->chip->txpwr_factor_mac;
+ u8 path_num = rtwdev->chip->rf_path_num;
+ u32 max_valid_addr;
u32 val, addr;
s8 *buf, tmp;
u8 cur, i;
@@ -519,7 +542,12 @@ static int __print_txpwr_map(struct seq_file *m, struct rtw89_dev *rtwdev,
if (!buf)
return -ENOMEM;
- for (addr = map->addr_from; addr <= map->addr_to; addr += 4) {
+ if (path_num == 1)
+ max_valid_addr = map->addr_to_1ss;
+ else
+ max_valid_addr = map->addr_to;
+
+ for (addr = map->addr_from; addr <= max_valid_addr; addr += 4) {
ret = rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, addr, &val);
if (ret)
val = MASKDWORD;
@@ -3206,7 +3234,11 @@ static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta)
struct seq_file *m = (struct seq_file *)data;
struct rtw89_dev *rtwdev = rtwsta->rtwdev;
struct rtw89_hal *hal = &rtwdev->hal;
+ u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num;
+ bool ant_asterisk = hal->tx_path_diversity || hal->ant_diversity;
+ u8 evm_min, evm_max;
u8 rssi;
+ u8 snr;
int i;
seq_printf(m, "TX rate [%d]: ", rtwsta->mac_id);
@@ -3256,13 +3288,27 @@ static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta)
rssi = ewma_rssi_read(&rtwsta->avg_rssi);
seq_printf(m, "RSSI: %d dBm (raw=%d, prev=%d) [",
RTW89_RSSI_RAW_TO_DBM(rssi), rssi, rtwsta->prev_rssi);
- for (i = 0; i < rtwdev->chip->rf_path_num; i++) {
+ for (i = 0; i < ant_num; i++) {
rssi = ewma_rssi_read(&rtwsta->rssi[i]);
seq_printf(m, "%d%s%s", RTW89_RSSI_RAW_TO_DBM(rssi),
- hal->tx_path_diversity && (hal->antenna_tx & BIT(i)) ? "*" : "",
- i + 1 == rtwdev->chip->rf_path_num ? "" : ", ");
+ ant_asterisk && (hal->antenna_tx & BIT(i)) ? "*" : "",
+ i + 1 == ant_num ? "" : ", ");
}
seq_puts(m, "]\n");
+
+ seq_puts(m, "EVM: [");
+ for (i = 0; i < (hal->ant_diversity ? 2 : 1); i++) {
+ evm_min = ewma_evm_read(&rtwsta->evm_min[i]);
+ evm_max = ewma_evm_read(&rtwsta->evm_max[i]);
+
+ seq_printf(m, "%s(%2u.%02u, %2u.%02u)", i == 0 ? "" : " ",
+ evm_min >> 2, (evm_min & 0x3) * 25,
+ evm_max >> 2, (evm_max & 0x3) * 25);
+ }
+ seq_puts(m, "]\t");
+
+ snr = ewma_snr_read(&rtwsta->avg_snr);
+ seq_printf(m, "SNR: %u\n", snr);
}
static void
diff --git a/drivers/net/wireless/realtek/rtw89/efuse.c b/drivers/net/wireless/realtek/rtw89/efuse.c
index 7bd4f8558e03..2aaf4d013e46 100644
--- a/drivers/net/wireless/realtek/rtw89/efuse.c
+++ b/drivers/net/wireless/realtek/rtw89/efuse.c
@@ -7,6 +7,10 @@
#include "mac.h"
#include "reg.h"
+#define EF_FV_OFSET 0x5ea
+#define EF_CV_MASK GENMASK(7, 4)
+#define EF_CV_INV 15
+
enum rtw89_efuse_bank {
RTW89_EFUSE_BANK_WIFI,
RTW89_EFUSE_BANK_BT,
@@ -328,3 +332,20 @@ out_free:
return ret;
}
+
+int rtw89_read_efuse_ver(struct rtw89_dev *rtwdev, u8 *ecv)
+{
+ int ret;
+ u8 val;
+
+ ret = rtw89_dump_physical_efuse_map(rtwdev, &val, EF_FV_OFSET, 1, false);
+ if (ret)
+ return ret;
+
+ *ecv = u8_get_bits(val, EF_CV_MASK);
+ if (*ecv == EF_CV_INV)
+ return -ENOENT;
+
+ return 0;
+}
+EXPORT_SYMBOL(rtw89_read_efuse_ver);
diff --git a/drivers/net/wireless/realtek/rtw89/efuse.h b/drivers/net/wireless/realtek/rtw89/efuse.h
index 622ff95e7476..79071aff28de 100644
--- a/drivers/net/wireless/realtek/rtw89/efuse.h
+++ b/drivers/net/wireless/realtek/rtw89/efuse.h
@@ -9,5 +9,6 @@
int rtw89_parse_efuse_map(struct rtw89_dev *rtwdev);
int rtw89_parse_phycap_map(struct rtw89_dev *rtwdev);
+int rtw89_read_efuse_ver(struct rtw89_dev *rtwdev, u8 *efv);
#endif
diff --git a/drivers/net/wireless/realtek/rtw89/fw.c b/drivers/net/wireless/realtek/rtw89/fw.c
index b9b675bf9d05..9637f5e48d84 100644
--- a/drivers/net/wireless/realtek/rtw89/fw.c
+++ b/drivers/net/wireless/realtek/rtw89/fw.c
@@ -14,6 +14,8 @@
static void rtw89_fw_c2h_cmd_handle(struct rtw89_dev *rtwdev,
struct sk_buff *skb);
+static int rtw89_h2c_tx_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb,
+ struct rtw89_wait_info *wait, unsigned int cond);
static struct sk_buff *rtw89_fw_h2c_alloc_skb(struct rtw89_dev *rtwdev, u32 len,
bool header)
@@ -87,9 +89,11 @@ int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev)
static int rtw89_fw_hdr_parser(struct rtw89_dev *rtwdev, const u8 *fw, u32 len,
struct rtw89_fw_bin_info *info)
{
+ const struct rtw89_fw_hdr *fw_hdr = (const struct rtw89_fw_hdr *)fw;
struct rtw89_fw_hdr_section_info *section_info;
+ const struct rtw89_fw_dynhdr_hdr *fwdynhdr;
+ const struct rtw89_fw_hdr_section *section;
const u8 *fw_end = fw + len;
- const u8 *fwdynhdr;
const u8 *bin;
u32 base_hdr_len;
u32 mssc_len = 0;
@@ -98,16 +102,15 @@ static int rtw89_fw_hdr_parser(struct rtw89_dev *rtwdev, const u8 *fw, u32 len,
if (!info)
return -EINVAL;
- info->section_num = GET_FW_HDR_SEC_NUM(fw);
- base_hdr_len = RTW89_FW_HDR_SIZE +
- info->section_num * RTW89_FW_SECTION_HDR_SIZE;
- info->dynamic_hdr_en = GET_FW_HDR_DYN_HDR(fw);
+ info->section_num = le32_get_bits(fw_hdr->w6, FW_HDR_W6_SEC_NUM);
+ base_hdr_len = struct_size(fw_hdr, sections, info->section_num);
+ info->dynamic_hdr_en = le32_get_bits(fw_hdr->w7, FW_HDR_W7_DYN_HDR);
if (info->dynamic_hdr_en) {
- info->hdr_len = GET_FW_HDR_LEN(fw);
+ info->hdr_len = le32_get_bits(fw_hdr->w3, FW_HDR_W3_LEN);
info->dynamic_hdr_len = info->hdr_len - base_hdr_len;
- fwdynhdr = fw + base_hdr_len;
- if (GET_FW_DYNHDR_LEN(fwdynhdr) != info->dynamic_hdr_len) {
+ fwdynhdr = (const struct rtw89_fw_dynhdr_hdr *)(fw + base_hdr_len);
+ if (le32_to_cpu(fwdynhdr->hdr_len) != info->dynamic_hdr_len) {
rtw89_err(rtwdev, "[ERR]invalid fw dynamic header len\n");
return -EINVAL;
}
@@ -119,26 +122,27 @@ static int rtw89_fw_hdr_parser(struct rtw89_dev *rtwdev, const u8 *fw, u32 len,
bin = fw + info->hdr_len;
/* jump to section header */
- fw += RTW89_FW_HDR_SIZE;
section_info = info->section_info;
for (i = 0; i < info->section_num; i++) {
- section_info->type = GET_FWSECTION_HDR_SECTIONTYPE(fw);
+ section = &fw_hdr->sections[i];
+ section_info->type =
+ le32_get_bits(section->w1, FWSECTION_HDR_W1_SECTIONTYPE);
if (section_info->type == FWDL_SECURITY_SECTION_TYPE) {
- section_info->mssc = GET_FWSECTION_HDR_MSSC(fw);
+ section_info->mssc =
+ le32_get_bits(section->w2, FWSECTION_HDR_W2_MSSC);
mssc_len += section_info->mssc * FWDL_SECURITY_SIGLEN;
} else {
section_info->mssc = 0;
}
- section_info->len = GET_FWSECTION_HDR_SEC_SIZE(fw);
- if (GET_FWSECTION_HDR_CHECKSUM(fw))
+ section_info->len = le32_get_bits(section->w1, FWSECTION_HDR_W1_SEC_SIZE);
+ if (le32_get_bits(section->w1, FWSECTION_HDR_W1_CHECKSUM))
section_info->len += FWDL_SECTION_CHKSUM_LEN;
- section_info->redl = GET_FWSECTION_HDR_REDL(fw);
+ section_info->redl = le32_get_bits(section->w1, FWSECTION_HDR_W1_REDL);
section_info->dladdr =
- GET_FWSECTION_HDR_DL_ADDR(fw) & 0x1fffffff;
+ le32_get_bits(section->w0, FWSECTION_HDR_W0_DL_ADDR) & 0x1fffffff;
section_info->addr = bin;
bin += section_info->len;
- fw += RTW89_FW_SECTION_HDR_SIZE;
section_info++;
}
@@ -193,18 +197,18 @@ static void rtw89_fw_update_ver(struct rtw89_dev *rtwdev,
enum rtw89_fw_type type,
struct rtw89_fw_suit *fw_suit)
{
- const u8 *hdr = fw_suit->data;
-
- fw_suit->major_ver = GET_FW_HDR_MAJOR_VERSION(hdr);
- fw_suit->minor_ver = GET_FW_HDR_MINOR_VERSION(hdr);
- fw_suit->sub_ver = GET_FW_HDR_SUBVERSION(hdr);
- fw_suit->sub_idex = GET_FW_HDR_SUBINDEX(hdr);
- fw_suit->build_year = GET_FW_HDR_YEAR(hdr);
- fw_suit->build_mon = GET_FW_HDR_MONTH(hdr);
- fw_suit->build_date = GET_FW_HDR_DATE(hdr);
- fw_suit->build_hour = GET_FW_HDR_HOUR(hdr);
- fw_suit->build_min = GET_FW_HDR_MIN(hdr);
- fw_suit->cmd_ver = GET_FW_HDR_CMD_VERSERION(hdr);
+ const struct rtw89_fw_hdr *hdr = (const struct rtw89_fw_hdr *)fw_suit->data;
+
+ fw_suit->major_ver = le32_get_bits(hdr->w1, FW_HDR_W1_MAJOR_VERSION);
+ fw_suit->minor_ver = le32_get_bits(hdr->w1, FW_HDR_W1_MINOR_VERSION);
+ fw_suit->sub_ver = le32_get_bits(hdr->w1, FW_HDR_W1_SUBVERSION);
+ fw_suit->sub_idex = le32_get_bits(hdr->w1, FW_HDR_W1_SUBINDEX);
+ fw_suit->build_year = le32_get_bits(hdr->w5, FW_HDR_W5_YEAR);
+ fw_suit->build_mon = le32_get_bits(hdr->w4, FW_HDR_W4_MONTH);
+ fw_suit->build_date = le32_get_bits(hdr->w4, FW_HDR_W4_DATE);
+ fw_suit->build_hour = le32_get_bits(hdr->w4, FW_HDR_W4_HOUR);
+ fw_suit->build_min = le32_get_bits(hdr->w4, FW_HDR_W4_MIN);
+ fw_suit->cmd_ver = le32_get_bits(hdr->w7, FW_HDR_W7_CMD_VERSERION);
rtw89_info(rtwdev,
"Firmware version %u.%u.%u.%u, cmd version %u, type %u\n",
@@ -254,6 +258,9 @@ struct __fw_feat_cfg {
}
static const struct __fw_feat_cfg fw_feat_tbl[] = {
+ __CFG_FW_FEAT(RTL8851B, ge, 0, 29, 37, 1, TX_WAKE),
+ __CFG_FW_FEAT(RTL8851B, ge, 0, 29, 37, 1, SCAN_OFFLOAD),
+ __CFG_FW_FEAT(RTL8851B, ge, 0, 29, 41, 0, CRASH_TRIGGER),
__CFG_FW_FEAT(RTL8852A, le, 0, 13, 29, 0, OLD_HT_RA_FORMAT),
__CFG_FW_FEAT(RTL8852A, ge, 0, 13, 35, 0, SCAN_OFFLOAD),
__CFG_FW_FEAT(RTL8852A, ge, 0, 13, 35, 0, TX_WAKE),
@@ -807,7 +814,7 @@ int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
}
skb_put(skb, H2C_BA_CAM_LEN);
SET_BA_CAM_MACID(skb->data, macid);
- if (chip->bacam_v1)
+ if (chip->bacam_ver == RTW89_BACAM_V0_EXT)
SET_BA_CAM_ENTRY_IDX_V1(skb->data, entry_idx);
else
SET_BA_CAM_ENTRY_IDX(skb->data, entry_idx);
@@ -823,7 +830,7 @@ int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
SET_BA_CAM_INIT_REQ(skb->data, 1);
SET_BA_CAM_SSN(skb->data, params->ssn);
- if (chip->bacam_v1) {
+ if (chip->bacam_ver == RTW89_BACAM_V0_EXT) {
SET_BA_CAM_STD_EN(skb->data, 1);
SET_BA_CAM_BAND(skb->data, rtwvif->mac_idx);
}
@@ -848,8 +855,8 @@ fail:
return ret;
}
-static int rtw89_fw_h2c_init_dynamic_ba_cam_v1(struct rtw89_dev *rtwdev,
- u8 entry_idx, u8 uid)
+static int rtw89_fw_h2c_init_ba_cam_v0_ext(struct rtw89_dev *rtwdev,
+ u8 entry_idx, u8 uid)
{
struct sk_buff *skb;
int ret;
@@ -886,7 +893,7 @@ fail:
return ret;
}
-void rtw89_fw_h2c_init_ba_cam_v1(struct rtw89_dev *rtwdev)
+void rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(struct rtw89_dev *rtwdev)
{
const struct rtw89_chip_info *chip = rtwdev->chip;
u8 entry_idx = chip->bacam_num;
@@ -894,7 +901,7 @@ void rtw89_fw_h2c_init_ba_cam_v1(struct rtw89_dev *rtwdev)
int i;
for (i = 0; i < chip->bacam_dynamic_num; i++) {
- rtw89_fw_h2c_init_dynamic_ba_cam_v1(rtwdev, entry_idx, uid);
+ rtw89_fw_h2c_init_ba_cam_v0_ext(rtwdev, entry_idx, uid);
entry_idx++;
uid++;
}
@@ -997,8 +1004,8 @@ void rtw89_fw_release_general_pkt_list_vif(struct rtw89_dev *rtwdev,
list_for_each_entry_safe(info, tmp, pkt_list, list) {
if (notify_fw)
rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id);
- rtw89_core_release_bit_map(rtwdev->pkt_offload,
- info->id);
+ else
+ rtw89_core_release_bit_map(rtwdev->pkt_offload, info->id);
list_del(&info->list);
kfree(info);
}
@@ -2440,7 +2447,9 @@ fail:
#define H2C_LEN_PKT_OFLD 4
int rtw89_fw_h2c_del_pkt_offload(struct rtw89_dev *rtwdev, u8 id)
{
+ struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait;
struct sk_buff *skb;
+ unsigned int cond;
u8 *cmd;
int ret;
@@ -2460,23 +2469,26 @@ int rtw89_fw_h2c_del_pkt_offload(struct rtw89_dev *rtwdev, u8 id)
H2C_FUNC_PACKET_OFLD, 1, 1,
H2C_LEN_PKT_OFLD);
- ret = rtw89_h2c_tx(rtwdev, skb, false);
- if (ret) {
- rtw89_err(rtwdev, "failed to send h2c\n");
- goto fail;
+ cond = RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(id, RTW89_PKT_OFLD_OP_DEL);
+
+ ret = rtw89_h2c_tx_and_wait(rtwdev, skb, wait, cond);
+ if (ret < 0) {
+ rtw89_debug(rtwdev, RTW89_DBG_FW,
+ "failed to del pkt ofld: id %d, ret %d\n",
+ id, ret);
+ return ret;
}
+ rtw89_core_release_bit_map(rtwdev->pkt_offload, id);
return 0;
-fail:
- dev_kfree_skb_any(skb);
-
- return ret;
}
int rtw89_fw_h2c_add_pkt_offload(struct rtw89_dev *rtwdev, u8 *id,
struct sk_buff *skb_ofld)
{
+ struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait;
struct sk_buff *skb;
+ unsigned int cond;
u8 *cmd;
u8 alloc_id;
int ret;
@@ -2507,27 +2519,29 @@ int rtw89_fw_h2c_add_pkt_offload(struct rtw89_dev *rtwdev, u8 *id,
H2C_FUNC_PACKET_OFLD, 1, 1,
H2C_LEN_PKT_OFLD + skb_ofld->len);
- ret = rtw89_h2c_tx(rtwdev, skb, false);
- if (ret) {
- rtw89_err(rtwdev, "failed to send h2c\n");
+ cond = RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(alloc_id, RTW89_PKT_OFLD_OP_ADD);
+
+ ret = rtw89_h2c_tx_and_wait(rtwdev, skb, wait, cond);
+ if (ret < 0) {
+ rtw89_debug(rtwdev, RTW89_DBG_FW,
+ "failed to add pkt ofld: id %d, ret %d\n",
+ alloc_id, ret);
rtw89_core_release_bit_map(rtwdev->pkt_offload, alloc_id);
- goto fail;
+ return ret;
}
return 0;
-fail:
- dev_kfree_skb_any(skb);
-
- return ret;
}
#define H2C_LEN_SCAN_LIST_OFFLOAD 4
int rtw89_fw_h2c_scan_list_offload(struct rtw89_dev *rtwdev, int len,
struct list_head *chan_list)
{
+ struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait;
struct rtw89_mac_chinfo *ch_info;
struct sk_buff *skb;
int skb_len = H2C_LEN_SCAN_LIST_OFFLOAD + len * RTW89_MAC_CHINFO_SIZE;
+ unsigned int cond;
u8 *cmd;
int ret;
@@ -2574,27 +2588,27 @@ int rtw89_fw_h2c_scan_list_offload(struct rtw89_dev *rtwdev, int len,
H2C_CAT_MAC, H2C_CL_MAC_FW_OFLD,
H2C_FUNC_ADD_SCANOFLD_CH, 1, 1, skb_len);
- ret = rtw89_h2c_tx(rtwdev, skb, false);
+ cond = RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_ADD_SCANOFLD_CH);
+
+ ret = rtw89_h2c_tx_and_wait(rtwdev, skb, wait, cond);
if (ret) {
- rtw89_err(rtwdev, "failed to send h2c\n");
- goto fail;
+ rtw89_debug(rtwdev, RTW89_DBG_FW, "failed to add scan ofld ch\n");
+ return ret;
}
return 0;
-fail:
- dev_kfree_skb_any(skb);
-
- return ret;
}
int rtw89_fw_h2c_scan_offload(struct rtw89_dev *rtwdev,
struct rtw89_scan_option *option,
struct rtw89_vif *rtwvif)
{
+ struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait;
struct rtw89_chan *op = &rtwdev->scan_info.op_chan;
struct rtw89_h2c_scanofld *h2c;
u32 len = sizeof(*h2c);
struct sk_buff *skb;
+ unsigned int cond;
int ret;
skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
@@ -2633,17 +2647,15 @@ int rtw89_fw_h2c_scan_offload(struct rtw89_dev *rtwdev,
H2C_FUNC_SCANOFLD, 1, 1,
len);
- ret = rtw89_h2c_tx(rtwdev, skb, false);
+ cond = RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_SCANOFLD);
+
+ ret = rtw89_h2c_tx_and_wait(rtwdev, skb, wait, cond);
if (ret) {
- rtw89_err(rtwdev, "failed to send h2c\n");
- goto fail;
+ rtw89_debug(rtwdev, RTW89_DBG_FW, "failed to scan ofld\n");
+ return ret;
}
return 0;
-fail:
- dev_kfree_skb_any(skb);
-
- return ret;
}
int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev,
@@ -2909,12 +2921,13 @@ static int rtw89_fw_write_h2c_reg(struct rtw89_dev *rtwdev,
}
len = DIV_ROUND_UP(info->content_len + RTW89_H2CREG_HDR_LEN,
- sizeof(info->h2creg[0]));
+ sizeof(info->u.h2creg[0]));
+
+ u32p_replace_bits(&info->u.hdr.w0, info->id, RTW89_H2CREG_HDR_FUNC_MASK);
+ u32p_replace_bits(&info->u.hdr.w0, len, RTW89_H2CREG_HDR_LEN_MASK);
- RTW89_SET_H2CREG_HDR_FUNC(&info->h2creg[0], info->id);
- RTW89_SET_H2CREG_HDR_LEN(&info->h2creg[0], len);
for (i = 0; i < RTW89_H2CREG_MAX; i++)
- rtw89_write32(rtwdev, h2c_reg[i], info->h2creg[i]);
+ rtw89_write32(rtwdev, h2c_reg[i], info->u.h2creg[i]);
fw_info->h2c_counter++;
rtw89_write8_mask(rtwdev, chip->h2c_counter_reg.addr,
@@ -2944,13 +2957,14 @@ static int rtw89_fw_read_c2h_reg(struct rtw89_dev *rtwdev,
}
for (i = 0; i < RTW89_C2HREG_MAX; i++)
- info->c2hreg[i] = rtw89_read32(rtwdev, c2h_reg[i]);
+ info->u.c2hreg[i] = rtw89_read32(rtwdev, c2h_reg[i]);
rtw89_write8(rtwdev, chip->c2h_ctrl_reg, 0);
- info->id = RTW89_GET_C2H_HDR_FUNC(*info->c2hreg);
- info->content_len = (RTW89_GET_C2H_HDR_LEN(*info->c2hreg) << 2) -
- RTW89_C2HREG_HDR_LEN;
+ info->id = u32_get_bits(info->u.hdr.w0, RTW89_C2HREG_HDR_FUNC_MASK);
+ info->content_len =
+ (u32_get_bits(info->u.hdr.w0, RTW89_C2HREG_HDR_LEN_MASK) << 2) -
+ RTW89_C2HREG_HDR_LEN;
fw_info->c2h_counter++;
rtw89_write8_mask(rtwdev, chip->c2h_counter_reg.addr,
@@ -3019,9 +3033,8 @@ static void rtw89_release_pkt_list(struct rtw89_dev *rtwdev)
continue;
list_for_each_entry_safe(info, tmp, &pkt_list[idx], list) {
- rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id);
- rtw89_core_release_bit_map(rtwdev->pkt_offload,
- info->id);
+ if (test_bit(info->id, rtwdev->pkt_offload))
+ rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id);
list_del(&info->list);
kfree(info);
}
@@ -3786,6 +3799,11 @@ fail:
return ret;
}
+/* Return < 0, if failures happen during waiting for the condition.
+ * Return 0, when waiting for the condition succeeds.
+ * Return > 0, if the wait is considered unreachable due to driver/FW design,
+ * where 1 means during SER.
+ */
static int rtw89_h2c_tx_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb,
struct rtw89_wait_info *wait, unsigned int cond)
{
@@ -3798,6 +3816,9 @@ static int rtw89_h2c_tx_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb,
return -EBUSY;
}
+ if (test_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags))
+ return 1;
+
return rtw89_wait_for_cond(wait, cond);
}
diff --git a/drivers/net/wireless/realtek/rtw89/fw.h b/drivers/net/wireless/realtek/rtw89/fw.h
index 675f85c41471..45f927dc212e 100644
--- a/drivers/net/wireless/realtek/rtw89/fw.h
+++ b/drivers/net/wireless/realtek/rtw89/fw.h
@@ -18,15 +18,51 @@ enum rtw89_fw_dl_status {
RTW89_FWDL_WCPU_FW_INIT_RDY = 7
};
-#define RTW89_GET_C2H_HDR_FUNC(info) \
- u32_get_bits(info, GENMASK(6, 0))
-#define RTW89_GET_C2H_HDR_LEN(info) \
- u32_get_bits(info, GENMASK(11, 8))
+struct rtw89_c2hreg_hdr {
+ u32 w0;
+};
+
+#define RTW89_C2HREG_HDR_FUNC_MASK GENMASK(6, 0)
+#define RTW89_C2HREG_HDR_ACK BIT(7)
+#define RTW89_C2HREG_HDR_LEN_MASK GENMASK(11, 8)
+#define RTW89_C2HREG_HDR_SEQ_MASK GENMASK(15, 12)
+
+struct rtw89_c2hreg_phycap {
+ u32 w0;
+ u32 w1;
+ u32 w2;
+ u32 w3;
+} __packed;
+
+#define RTW89_C2HREG_PHYCAP_W0_FUNC GENMASK(6, 0)
+#define RTW89_C2HREG_PHYCAP_W0_ACK BIT(7)
+#define RTW89_C2HREG_PHYCAP_W0_LEN GENMASK(11, 8)
+#define RTW89_C2HREG_PHYCAP_W0_SEQ GENMASK(15, 12)
+#define RTW89_C2HREG_PHYCAP_W0_RX_NSS GENMASK(23, 16)
+#define RTW89_C2HREG_PHYCAP_W0_BW GENMASK(31, 24)
+#define RTW89_C2HREG_PHYCAP_W1_TX_NSS GENMASK(7, 0)
+#define RTW89_C2HREG_PHYCAP_W1_PROT GENMASK(15, 8)
+#define RTW89_C2HREG_PHYCAP_W1_NIC GENMASK(23, 16)
+#define RTW89_C2HREG_PHYCAP_W1_WL_FUNC GENMASK(31, 24)
+#define RTW89_C2HREG_PHYCAP_W2_HW_TYPE GENMASK(7, 0)
+#define RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM GENMASK(15, 8)
+#define RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM GENMASK(23, 16)
+
+struct rtw89_h2creg_hdr {
+ u32 w0;
+};
+
+#define RTW89_H2CREG_HDR_FUNC_MASK GENMASK(6, 0)
+#define RTW89_H2CREG_HDR_LEN_MASK GENMASK(11, 8)
-#define RTW89_SET_H2CREG_HDR_FUNC(info, val) \
- u32p_replace_bits(info, val, GENMASK(6, 0))
-#define RTW89_SET_H2CREG_HDR_LEN(info, val) \
- u32p_replace_bits(info, val, GENMASK(11, 8))
+struct rtw89_h2creg_sch_tx_en {
+ u32 w0;
+ u32 w1;
+} __packed;
+
+#define RTW89_H2CREG_SCH_TX_EN_W0_EN GENMASK(31, 16)
+#define RTW89_H2CREG_SCH_TX_EN_W1_MASK GENMASK(15, 0)
+#define RTW89_H2CREG_SCH_TX_EN_W1_BAND BIT(16)
#define RTW89_H2CREG_MAX 4
#define RTW89_C2HREG_MAX 4
@@ -36,13 +72,21 @@ enum rtw89_fw_dl_status {
struct rtw89_mac_c2h_info {
u8 id;
u8 content_len;
- u32 c2hreg[RTW89_C2HREG_MAX];
+ union {
+ u32 c2hreg[RTW89_C2HREG_MAX];
+ struct rtw89_c2hreg_hdr hdr;
+ struct rtw89_c2hreg_phycap phycap;
+ } u;
};
struct rtw89_mac_h2c_info {
u8 id;
u8 content_len;
- u32 h2creg[RTW89_H2CREG_MAX];
+ union {
+ u32 h2creg[RTW89_H2CREG_MAX];
+ struct rtw89_h2creg_hdr hdr;
+ struct rtw89_h2creg_sch_tx_en sch_tx_en;
+ } u;
};
enum rtw89_mac_h2c_type {
@@ -63,33 +107,6 @@ enum rtw89_mac_c2h_type {
RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF
};
-#define RTW89_GET_C2H_PHYCAP_FUNC(info) \
- u32_get_bits(*((const u32 *)(info)), GENMASK(6, 0))
-#define RTW89_GET_C2H_PHYCAP_ACK(info) \
- u32_get_bits(*((const u32 *)(info)), BIT(7))
-#define RTW89_GET_C2H_PHYCAP_LEN(info) \
- u32_get_bits(*((const u32 *)(info)), GENMASK(11, 8))
-#define RTW89_GET_C2H_PHYCAP_SEQ(info) \
- u32_get_bits(*((const u32 *)(info)), GENMASK(15, 12))
-#define RTW89_GET_C2H_PHYCAP_RX_NSS(info) \
- u32_get_bits(*((const u32 *)(info)), GENMASK(23, 16))
-#define RTW89_GET_C2H_PHYCAP_BW(info) \
- u32_get_bits(*((const u32 *)(info)), GENMASK(31, 24))
-#define RTW89_GET_C2H_PHYCAP_TX_NSS(info) \
- u32_get_bits(*((const u32 *)(info) + 1), GENMASK(7, 0))
-#define RTW89_GET_C2H_PHYCAP_PROT(info) \
- u32_get_bits(*((const u32 *)(info) + 1), GENMASK(15, 8))
-#define RTW89_GET_C2H_PHYCAP_NIC(info) \
- u32_get_bits(*((const u32 *)(info) + 1), GENMASK(23, 16))
-#define RTW89_GET_C2H_PHYCAP_WL_FUNC(info) \
- u32_get_bits(*((const u32 *)(info) + 1), GENMASK(31, 24))
-#define RTW89_GET_C2H_PHYCAP_HW_TYPE(info) \
- u32_get_bits(*((const u32 *)(info) + 2), GENMASK(7, 0))
-#define RTW89_GET_C2H_PHYCAP_ANT_TX_NUM(info) \
- u32_get_bits(*((const u32 *)(info) + 3), GENMASK(15, 8))
-#define RTW89_GET_C2H_PHYCAP_ANT_RX_NUM(info) \
- u32_get_bits(*((const u32 *)(info) + 3), GENMASK(23, 16))
-
enum rtw89_fw_c2h_category {
RTW89_C2H_CAT_TEST,
RTW89_C2H_CAT_MAC,
@@ -138,8 +155,13 @@ enum rtw89_pkt_offload_op {
RTW89_PKT_OFLD_OP_ADD,
RTW89_PKT_OFLD_OP_DEL,
RTW89_PKT_OFLD_OP_READ,
+
+ NUM_OF_RTW89_PKT_OFFLOAD_OP,
};
+#define RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op) \
+ ((pkt_id) * NUM_OF_RTW89_PKT_OFFLOAD_OP + (pkt_op))
+
enum rtw89_scanofld_notify_reason {
RTW89_SCAN_DWELL_NOTIFY,
RTW89_SCAN_PRE_TX_NOTIFY,
@@ -209,17 +231,6 @@ struct rtw89_fw_macid_pause_grp {
__le32 mask_grp[4];
} __packed;
-struct rtw89_h2creg_sch_tx_en {
- u8 func:7;
- u8 ack:1;
- u8 total_len:4;
- u8 seq_num:4;
- u16 tx_en:16;
- u16 mask:16;
- u8 band:1;
- u16 rsvd:15;
-} __packed;
-
#define RTW89_H2C_MAX_SIZE 2048
#define RTW89_CHANNEL_TIME 45
#define RTW89_CHANNEL_TIME_6G 20
@@ -232,7 +243,7 @@ struct rtw89_h2creg_sch_tx_en {
#define RTW89_SCANOFLD_MAX_IE_LEN 512
#define RTW89_SCANOFLD_PKT_NONE 0xFF
#define RTW89_SCANOFLD_DEBUG_MASK 0x1F
-#define RTW89_MAC_CHINFO_SIZE 24
+#define RTW89_MAC_CHINFO_SIZE 28
#define RTW89_SCAN_LIST_GUARD 4
#define RTW89_SCAN_LIST_LIMIT \
((RTW89_H2C_MAX_SIZE / RTW89_MAC_CHINFO_SIZE) - RTW89_SCAN_LIST_GUARD)
@@ -277,6 +288,7 @@ struct rtw89_pktofld_info {
u8 ssid_len;
u8 bssid[ETH_ALEN];
u16 channel_6ghz;
+ bool cancel;
};
static inline void RTW89_SET_FWCMD_RA_IS_DIS(void *cmd, u32 val)
@@ -516,50 +528,58 @@ static inline void RTW89_SET_EDCA_PARAM(void *cmd, u32 val)
#define FWDL_SECURITY_SECTION_TYPE 9
#define FWDL_SECURITY_SIGLEN 512
-#define GET_FWSECTION_HDR_DL_ADDR(fwhdr) \
- le32_get_bits(*((const __le32 *)(fwhdr)), GENMASK(31, 0))
-#define GET_FWSECTION_HDR_SECTIONTYPE(fwhdr) \
- le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(27, 24))
-#define GET_FWSECTION_HDR_SEC_SIZE(fwhdr) \
- le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(23, 0))
-#define GET_FWSECTION_HDR_CHECKSUM(fwhdr) \
- le32_get_bits(*((const __le32 *)(fwhdr) + 1), BIT(28))
-#define GET_FWSECTION_HDR_REDL(fwhdr) \
- le32_get_bits(*((const __le32 *)(fwhdr) + 1), BIT(29))
-#define GET_FWSECTION_HDR_MSSC(fwhdr) \
- le32_get_bits(*((const __le32 *)(fwhdr) + 2), GENMASK(31, 0))
-
-#define GET_FW_HDR_MAJOR_VERSION(fwhdr) \
- le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(7, 0))
-#define GET_FW_HDR_MINOR_VERSION(fwhdr) \
- le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(15, 8))
-#define GET_FW_HDR_SUBVERSION(fwhdr) \
- le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(23, 16))
-#define GET_FW_HDR_SUBINDEX(fwhdr) \
- le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(31, 24))
-#define GET_FW_HDR_LEN(fwhdr) \
- le32_get_bits(*((const __le32 *)(fwhdr) + 3), GENMASK(23, 16))
-#define GET_FW_HDR_MONTH(fwhdr) \
- le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(7, 0))
-#define GET_FW_HDR_DATE(fwhdr) \
- le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(15, 8))
-#define GET_FW_HDR_HOUR(fwhdr) \
- le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(23, 16))
-#define GET_FW_HDR_MIN(fwhdr) \
- le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(31, 24))
-#define GET_FW_HDR_YEAR(fwhdr) \
- le32_get_bits(*((const __le32 *)(fwhdr) + 5), GENMASK(31, 0))
-#define GET_FW_HDR_SEC_NUM(fwhdr) \
- le32_get_bits(*((const __le32 *)(fwhdr) + 6), GENMASK(15, 8))
-#define GET_FW_HDR_DYN_HDR(fwhdr) \
- le32_get_bits(*((const __le32 *)(fwhdr) + 7), BIT(16))
-#define GET_FW_HDR_CMD_VERSERION(fwhdr) \
- le32_get_bits(*((const __le32 *)(fwhdr) + 7), GENMASK(31, 24))
-
-#define GET_FW_DYNHDR_LEN(fwdynhdr) \
- le32_get_bits(*((const __le32 *)(fwdynhdr)), GENMASK(31, 0))
-#define GET_FW_DYNHDR_COUNT(fwdynhdr) \
- le32_get_bits(*((const __le32 *)(fwdynhdr) + 1), GENMASK(31, 0))
+struct rtw89_fw_dynhdr_sec {
+ __le32 w0;
+ u8 content[];
+} __packed;
+
+struct rtw89_fw_dynhdr_hdr {
+ __le32 hdr_len;
+ __le32 setcion_count;
+ /* struct rtw89_fw_dynhdr_sec (nested flexible structures) */
+} __packed;
+
+struct rtw89_fw_hdr_section {
+ __le32 w0;
+ __le32 w1;
+ __le32 w2;
+ __le32 w3;
+} __packed;
+
+#define FWSECTION_HDR_W0_DL_ADDR GENMASK(31, 0)
+#define FWSECTION_HDR_W1_METADATA GENMASK(31, 24)
+#define FWSECTION_HDR_W1_SECTIONTYPE GENMASK(27, 24)
+#define FWSECTION_HDR_W1_SEC_SIZE GENMASK(23, 0)
+#define FWSECTION_HDR_W1_CHECKSUM BIT(28)
+#define FWSECTION_HDR_W1_REDL BIT(29)
+#define FWSECTION_HDR_W2_MSSC GENMASK(31, 0)
+
+struct rtw89_fw_hdr {
+ __le32 w0;
+ __le32 w1;
+ __le32 w2;
+ __le32 w3;
+ __le32 w4;
+ __le32 w5;
+ __le32 w6;
+ __le32 w7;
+ struct rtw89_fw_hdr_section sections[];
+ /* struct rtw89_fw_dynhdr_hdr (optional) */
+} __packed;
+
+#define FW_HDR_W1_MAJOR_VERSION GENMASK(7, 0)
+#define FW_HDR_W1_MINOR_VERSION GENMASK(15, 8)
+#define FW_HDR_W1_SUBVERSION GENMASK(23, 16)
+#define FW_HDR_W1_SUBINDEX GENMASK(31, 24)
+#define FW_HDR_W3_LEN GENMASK(23, 16)
+#define FW_HDR_W4_MONTH GENMASK(7, 0)
+#define FW_HDR_W4_DATE GENMASK(15, 8)
+#define FW_HDR_W4_HOUR GENMASK(23, 16)
+#define FW_HDR_W4_MIN GENMASK(31, 24)
+#define FW_HDR_W5_YEAR GENMASK(31, 0)
+#define FW_HDR_W6_SEC_NUM GENMASK(15, 8)
+#define FW_HDR_W7_DYN_HDR BIT(16)
+#define FW_HDR_W7_CMD_VERSERION GENMASK(31, 24)
static inline void SET_FW_HDR_PART_SIZE(void *fwhdr, u32 val)
{
@@ -3215,16 +3235,17 @@ static inline struct rtw89_fw_c2h_attr *RTW89_SKB_C2H_CB(struct sk_buff *skb)
#define RTW89_GET_C2H_LOG_SRT_PRT(c2h) (char *)((__le32 *)(c2h) + 2)
#define RTW89_GET_C2H_LOG_LEN(len) ((len) - RTW89_C2H_HEADER_LEN)
-#define RTW89_GET_MAC_C2H_DONE_ACK_CAT(c2h) \
- le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
-#define RTW89_GET_MAC_C2H_DONE_ACK_CLASS(c2h) \
- le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
-#define RTW89_GET_MAC_C2H_DONE_ACK_FUNC(c2h) \
- le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
-#define RTW89_GET_MAC_C2H_DONE_ACK_H2C_RETURN(c2h) \
- le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16))
-#define RTW89_GET_MAC_C2H_DONE_ACK_H2C_SEQ(c2h) \
- le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 24))
+struct rtw89_c2h_done_ack {
+ __le32 w0;
+ __le32 w1;
+ __le32 w2;
+} __packed;
+
+#define RTW89_C2H_DONE_ACK_W2_CAT GENMASK(1, 0)
+#define RTW89_C2H_DONE_ACK_W2_CLASS GENMASK(7, 2)
+#define RTW89_C2H_DONE_ACK_W2_FUNC GENMASK(15, 8)
+#define RTW89_C2H_DONE_ACK_W2_H2C_RETURN GENMASK(23, 16)
+#define RTW89_C2H_DONE_ACK_W2_H2C_SEQ GENMASK(31, 24)
#define RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h) \
le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
@@ -3339,6 +3360,16 @@ static_assert(sizeof(struct rtw89_mac_mcc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE)
#define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h) \
le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
+struct rtw89_c2h_pkt_ofld_rsp {
+ __le32 w0;
+ __le32 w1;
+ __le32 w2;
+} __packed;
+
+#define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID GENMASK(7, 0)
+#define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP GENMASK(10, 8)
+#define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN GENMASK(31, 16)
+
struct rtw89_h2c_bcnfltr {
__le32 w0;
} __packed;
@@ -3369,9 +3400,6 @@ struct rtw89_h2c_ofld {
#define RTW89_H2C_OFLD_W0_TX_TP GENMASK(17, 8)
#define RTW89_H2C_OFLD_W0_RX_TP GENMASK(27, 18)
-#define RTW89_FW_HDR_SIZE 32
-#define RTW89_FW_SECTION_HDR_SIZE 16
-
#define RTW89_MFW_SIG 0xFF
struct rtw89_mfw_info {
@@ -3405,7 +3433,7 @@ struct fwcmd_hdr {
union rtw89_compat_fw_hdr {
struct rtw89_mfw_hdr mfw_hdr;
- u8 fw_hdr[RTW89_FW_HDR_SIZE];
+ struct rtw89_fw_hdr fw_hdr;
};
static inline u32 rtw89_compat_fw_hdr_ver_code(const void *fw_buf)
@@ -3497,17 +3525,28 @@ struct rtw89_fw_h2c_rf_reg_info {
/* CLASS 9 - FW offload */
#define H2C_CL_MAC_FW_OFLD 0x9
-#define H2C_FUNC_PACKET_OFLD 0x1
-#define H2C_FUNC_MAC_MACID_PAUSE 0x8
-#define H2C_FUNC_USR_EDCA 0xF
-#define H2C_FUNC_TSF32_TOGL 0x10
-#define H2C_FUNC_OFLD_CFG 0x14
-#define H2C_FUNC_ADD_SCANOFLD_CH 0x16
-#define H2C_FUNC_SCANOFLD 0x17
-#define H2C_FUNC_PKT_DROP 0x1b
-#define H2C_FUNC_CFG_BCNFLTR 0x1e
-#define H2C_FUNC_OFLD_RSSI 0x1f
-#define H2C_FUNC_OFLD_TP 0x20
+enum rtw89_fw_ofld_h2c_func {
+ H2C_FUNC_PACKET_OFLD = 0x1,
+ H2C_FUNC_MAC_MACID_PAUSE = 0x8,
+ H2C_FUNC_USR_EDCA = 0xF,
+ H2C_FUNC_TSF32_TOGL = 0x10,
+ H2C_FUNC_OFLD_CFG = 0x14,
+ H2C_FUNC_ADD_SCANOFLD_CH = 0x16,
+ H2C_FUNC_SCANOFLD = 0x17,
+ H2C_FUNC_PKT_DROP = 0x1b,
+ H2C_FUNC_CFG_BCNFLTR = 0x1e,
+ H2C_FUNC_OFLD_RSSI = 0x1f,
+ H2C_FUNC_OFLD_TP = 0x20,
+
+ NUM_OF_RTW89_FW_OFLD_H2C_FUNC,
+};
+
+#define RTW89_FW_OFLD_WAIT_COND(tag, func) \
+ ((tag) * NUM_OF_RTW89_FW_OFLD_H2C_FUNC + (func))
+
+#define RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op) \
+ RTW89_FW_OFLD_WAIT_COND(RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op), \
+ H2C_FUNC_PACKET_OFLD)
/* CLASS 10 - Security CAM */
#define H2C_CL_MAC_SEC_CAM 0xa
@@ -3648,7 +3687,7 @@ void rtw89_fw_release_general_pkt_list_vif(struct rtw89_dev *rtwdev,
void rtw89_fw_release_general_pkt_list(struct rtw89_dev *rtwdev, bool notify_fw);
int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
bool valid, struct ieee80211_ampdu_params *params);
-void rtw89_fw_h2c_init_ba_cam_v1(struct rtw89_dev *rtwdev);
+void rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(struct rtw89_dev *rtwdev);
int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev,
struct rtw89_lps_parm *lps_param);
@@ -3711,8 +3750,8 @@ static inline void rtw89_fw_h2c_init_ba_cam(struct rtw89_dev *rtwdev)
{
const struct rtw89_chip_info *chip = rtwdev->chip;
- if (chip->bacam_v1)
- rtw89_fw_h2c_init_ba_cam_v1(rtwdev);
+ if (chip->bacam_ver == RTW89_BACAM_V0_EXT)
+ rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(rtwdev);
}
#endif
diff --git a/drivers/net/wireless/realtek/rtw89/mac.c b/drivers/net/wireless/realtek/rtw89/mac.c
index 512de491a064..b114babec698 100644
--- a/drivers/net/wireless/realtek/rtw89/mac.c
+++ b/drivers/net/wireless/realtek/rtw89/mac.c
@@ -644,6 +644,39 @@ static void rtw89_mac_dump_err_status(struct rtw89_dev *rtwdev,
rtw89_info(rtwdev, "<---\n");
}
+static bool rtw89_mac_suppress_log(struct rtw89_dev *rtwdev, u32 err)
+{
+ struct rtw89_ser *ser = &rtwdev->ser;
+ u32 dmac_err, imr, isr;
+ int ret;
+
+ if (rtwdev->chip->chip_id == RTL8852C) {
+ ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL);
+ if (ret)
+ return true;
+
+ if (err == MAC_AX_ERR_L1_ERR_DMAC) {
+ dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR);
+ imr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR);
+ isr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR);
+
+ if ((dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) &&
+ ((isr & imr) & B_AX_B0_ISR_ERR_CMDPSR_FRZTO)) {
+ set_bit(RTW89_SER_SUPPRESS_LOG, ser->flags);
+ return true;
+ }
+ } else if (err == MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE) {
+ if (test_bit(RTW89_SER_SUPPRESS_LOG, ser->flags))
+ return true;
+ } else if (err == MAC_AX_ERR_L1_RESET_RECOVERY_DONE) {
+ if (test_and_clear_bit(RTW89_SER_SUPPRESS_LOG, ser->flags))
+ return true;
+ }
+ }
+
+ return false;
+}
+
u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev)
{
u32 err, err_scnr;
@@ -667,6 +700,9 @@ u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev)
else if (err_scnr == RTW89_RXI300_ERROR)
err = MAC_AX_ERR_RXI300;
+ if (rtw89_mac_suppress_log(rtwdev, err))
+ return err;
+
rtw89_fw_st_dbg_dump(rtwdev);
rtw89_mac_dump_err_status(rtwdev, err);
@@ -676,6 +712,7 @@ EXPORT_SYMBOL(rtw89_mac_get_err_status);
int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err)
{
+ struct rtw89_ser *ser = &rtwdev->ser;
u32 halt;
int ret = 0;
@@ -692,6 +729,11 @@ int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err)
}
rtw89_write32(rtwdev, R_AX_HALT_H2C, err);
+
+ if (ser->prehandle_l1 &&
+ (err == MAC_AX_ERR_L1_DISABLE_EN || err == MAC_AX_ERR_L1_RCVY_EN))
+ return 0;
+
rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER);
return 0;
@@ -716,11 +758,8 @@ static int hfc_reset_param(struct rtw89_dev *rtwdev)
if (param_ini.pub_cfg)
param->pub_cfg = *param_ini.pub_cfg;
- if (param_ini.prec_cfg) {
+ if (param_ini.prec_cfg)
param->prec_cfg = *param_ini.prec_cfg;
- rtwdev->hal.sw_amsdu_max_size =
- param->prec_cfg.wp_ch07_prec * HFC_PAGE_UNIT;
- }
if (param_ini.ch_cfg)
param->ch_cfg = param_ini.ch_cfg;
@@ -1479,6 +1518,8 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
.ple_qt_52a_wow = {264, 0, 32, 20, 64, 13, 1005, 0, 64, 128, 120,},
/* 8852B PCIE WOW */
.ple_qt_52b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,},
+ /* 8851B PCIE WOW */
+ .ple_qt_51b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,},
};
EXPORT_SYMBOL(rtw89_mac_size);
@@ -1497,7 +1538,6 @@ static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev,
return NULL;
}
- mac->dle_info.wde_pg_size = cfg->wde_size->pge_size;
mac->dle_info.ple_pg_size = cfg->ple_size->pge_size;
mac->dle_info.qta_mode = mode;
mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma;
@@ -2602,9 +2642,11 @@ static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev,
int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev)
{
+ struct rtw89_efuse *efuse = &rtwdev->efuse;
struct rtw89_hal *hal = &rtwdev->hal;
const struct rtw89_chip_info *chip = rtwdev->chip;
struct rtw89_mac_c2h_info c2h_info = {0};
+ const struct rtw89_c2hreg_phycap *phycap;
u8 tx_nss;
u8 rx_nss;
u8 tx_ant;
@@ -2615,10 +2657,12 @@ int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev)
if (ret)
return ret;
- tx_nss = RTW89_GET_C2H_PHYCAP_TX_NSS(c2h_info.c2hreg);
- rx_nss = RTW89_GET_C2H_PHYCAP_RX_NSS(c2h_info.c2hreg);
- tx_ant = RTW89_GET_C2H_PHYCAP_ANT_TX_NUM(c2h_info.c2hreg);
- rx_ant = RTW89_GET_C2H_PHYCAP_ANT_RX_NUM(c2h_info.c2hreg);
+ phycap = &c2h_info.u.phycap;
+
+ tx_nss = u32_get_bits(phycap->w1, RTW89_C2HREG_PHYCAP_W1_TX_NSS);
+ rx_nss = u32_get_bits(phycap->w0, RTW89_C2HREG_PHYCAP_W0_RX_NSS);
+ tx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM);
+ rx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM);
hal->tx_nss = tx_nss ? min_t(u8, tx_nss, chip->tx_nss) : chip->tx_nss;
hal->rx_nss = rx_nss ? min_t(u8, rx_nss, chip->rx_nss) : chip->rx_nss;
@@ -2633,6 +2677,13 @@ int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev)
hal->tx_path_diversity = true;
}
+ if (chip->rf_path_num == 1) {
+ hal->antenna_tx = RF_A;
+ hal->antenna_rx = RF_A;
+ if ((efuse->rfe_type % 3) == 2)
+ hal->ant_diversity = true;
+ }
+
rtw89_debug(rtwdev, RTW89_DBG_FW,
"phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n",
hal->tx_nss, tx_nss, chip->tx_nss,
@@ -2641,6 +2692,7 @@ int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev)
"ant num/bitmap: tx=%d/0x%x rx=%d/0x%x\n",
tx_ant, hal->antenna_tx, rx_ant, hal->antenna_rx);
rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity);
+ rtw89_debug(rtwdev, RTW89_DBG_FW, "Antenna diversity=%d\n", hal->ant_diversity);
return 0;
}
@@ -2651,14 +2703,14 @@ static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band,
u32 ret;
struct rtw89_mac_c2h_info c2h_info = {0};
struct rtw89_mac_h2c_info h2c_info = {0};
- struct rtw89_h2creg_sch_tx_en *h2creg =
- (struct rtw89_h2creg_sch_tx_en *)h2c_info.h2creg;
+ struct rtw89_h2creg_sch_tx_en *sch_tx_en = &h2c_info.u.sch_tx_en;
h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN;
- h2c_info.content_len = sizeof(*h2creg) - RTW89_H2CREG_HDR_LEN;
- h2creg->tx_en = tx_en_u16;
- h2creg->mask = mask_u16;
- h2creg->band = band;
+ h2c_info.content_len = sizeof(*sch_tx_en) - RTW89_H2CREG_HDR_LEN;
+
+ u32p_replace_bits(&sch_tx_en->w0, tx_en_u16, RTW89_H2CREG_SCH_TX_EN_W0_EN);
+ u32p_replace_bits(&sch_tx_en->w1, mask_u16, RTW89_H2CREG_SCH_TX_EN_W1_MASK);
+ u32p_replace_bits(&sch_tx_en->w1, band, RTW89_H2CREG_SCH_TX_EN_W1_BAND);
ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info);
if (ret)
@@ -4331,6 +4383,8 @@ rtw89_mac_c2h_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h,
static void
rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
{
+ /* N.B. This will run in interrupt context. */
+
rtw89_debug(rtwdev, RTW89_DBG_FW,
"C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n",
RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data),
@@ -4340,15 +4394,44 @@ rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
}
static void
-rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
-{
+rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len)
+{
+ /* N.B. This will run in interrupt context. */
+ struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait;
+ const struct rtw89_c2h_done_ack *c2h =
+ (const struct rtw89_c2h_done_ack *)skb_c2h->data;
+ u8 h2c_cat = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CAT);
+ u8 h2c_class = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CLASS);
+ u8 h2c_func = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_FUNC);
+ u8 h2c_return = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_RETURN);
+ u8 h2c_seq = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_SEQ);
+ struct rtw89_completion_data data = {};
+ unsigned int cond;
+
rtw89_debug(rtwdev, RTW89_DBG_FW,
"C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n",
- RTW89_GET_MAC_C2H_DONE_ACK_CAT(c2h->data),
- RTW89_GET_MAC_C2H_DONE_ACK_CLASS(c2h->data),
- RTW89_GET_MAC_C2H_DONE_ACK_FUNC(c2h->data),
- RTW89_GET_MAC_C2H_DONE_ACK_H2C_RETURN(c2h->data),
- RTW89_GET_MAC_C2H_DONE_ACK_H2C_SEQ(c2h->data));
+ h2c_cat, h2c_class, h2c_func, h2c_return, h2c_seq);
+
+ if (h2c_cat != H2C_CAT_MAC)
+ return;
+
+ switch (h2c_class) {
+ default:
+ return;
+ case H2C_CL_MAC_FW_OFLD:
+ switch (h2c_func) {
+ default:
+ return;
+ case H2C_FUNC_ADD_SCANOFLD_CH:
+ case H2C_FUNC_SCANOFLD:
+ cond = RTW89_FW_OFLD_WAIT_COND(0, h2c_func);
+ break;
+ }
+
+ data.err = !!h2c_return;
+ rtw89_complete_cond(fw_ofld_wait, cond, &data);
+ return;
+ }
}
static void
@@ -4364,9 +4447,25 @@ rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
}
static void
-rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *c2h,
+rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h,
u32 len)
{
+ struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait;
+ const struct rtw89_c2h_pkt_ofld_rsp *c2h =
+ (const struct rtw89_c2h_pkt_ofld_rsp *)skb_c2h->data;
+ u16 pkt_len = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN);
+ u8 pkt_id = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID);
+ u8 pkt_op = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP);
+ struct rtw89_completion_data data = {};
+ unsigned int cond;
+
+ rtw89_debug(rtwdev, RTW89_DBG_FW, "pkt ofld rsp: id %d op %d len %d\n",
+ pkt_id, pkt_op, pkt_len);
+
+ data.err = !pkt_len;
+ cond = RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op);
+
+ rtw89_complete_cond(wait, cond, &data);
}
static void
@@ -4574,6 +4673,21 @@ bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func)
switch (class) {
default:
return false;
+ case RTW89_MAC_C2H_CLASS_INFO:
+ switch (func) {
+ default:
+ return false;
+ case RTW89_MAC_C2H_FUNC_REC_ACK:
+ case RTW89_MAC_C2H_FUNC_DONE_ACK:
+ return true;
+ }
+ case RTW89_MAC_C2H_CLASS_OFLD:
+ switch (func) {
+ default:
+ return false;
+ case RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP:
+ return true;
+ }
case RTW89_MAC_C2H_CLASS_MCC:
return true;
}
diff --git a/drivers/net/wireless/realtek/rtw89/mac.h b/drivers/net/wireless/realtek/rtw89/mac.h
index 6ba633ccdd03..0e1570451c2c 100644
--- a/drivers/net/wireless/realtek/rtw89/mac.h
+++ b/drivers/net/wireless/realtek/rtw89/mac.h
@@ -642,6 +642,7 @@ enum mac_ax_err_info {
MAC_AX_ERR_L0_PROMOTE_TO_L1 = 0x0010,
/* L1 */
+ MAC_AX_ERR_L1_PREERR_DMAC = 0x999,
MAC_AX_ERR_L1_ERR_DMAC = 0x1000,
MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE = 0x1001,
MAC_AX_ERR_L1_RESET_RECOVERY_DONE = 0x1002,
@@ -780,6 +781,7 @@ enum mac_ax_err_info {
MAC_AX_ERR_L1_RCVY_EN = 0x0002,
MAC_AX_ERR_L1_RCVY_STOP_REQ = 0x0003,
MAC_AX_ERR_L1_RCVY_START_REQ = 0x0004,
+ MAC_AX_ERR_L1_RESET_START_DMAC = 0x000A,
MAC_AX_ERR_L0_CFG_NOTIFY = 0x0010,
MAC_AX_ERR_L0_CFG_DIS_NOTIFY = 0x0011,
MAC_AX_ERR_L0_CFG_HANDSHAKE = 0x0012,
@@ -819,6 +821,7 @@ struct rtw89_mac_size_set {
const struct rtw89_ple_quota ple_qt58;
const struct rtw89_ple_quota ple_qt_52a_wow;
const struct rtw89_ple_quota ple_qt_52b_wow;
+ const struct rtw89_ple_quota ple_qt_51b_wow;
};
extern const struct rtw89_mac_size_set rtw89_mac_size;
@@ -1115,6 +1118,8 @@ enum rtw89_mac_xtal_si_offset {
XTAL_SI_PWR_CUT = 0x10,
#define XTAL_SI_SMALL_PWR_CUT BIT(0)
#define XTAL_SI_BIG_PWR_CUT BIT(1)
+ XTAL_SI_XTAL_DRV = 0x15,
+#define XTAL_SI_DRV_LATCH BIT(4)
XTAL_SI_XTAL_XMD_2 = 0x24,
#define XTAL_SI_LDO_LPS GENMASK(6, 4)
XTAL_SI_XTAL_XMD_4 = 0x26,
diff --git a/drivers/net/wireless/realtek/rtw89/mac80211.c b/drivers/net/wireless/realtek/rtw89/mac80211.c
index c42e31069035..a66503eb35b8 100644
--- a/drivers/net/wireless/realtek/rtw89/mac80211.c
+++ b/drivers/net/wireless/realtek/rtw89/mac80211.c
@@ -146,6 +146,7 @@ static int rtw89_ops_add_interface(struct ieee80211_hw *hw,
rtwvif->phy_idx = RTW89_PHY_0;
rtwvif->sub_entity_idx = RTW89_SUB_ENTITY_0;
rtwvif->hit_rule = 0;
+ rtwvif->reg_6ghz_power = RTW89_REG_6GHZ_POWER_DFLT;
ether_addr_copy(rtwvif->mac_addr, vif->addr);
INIT_LIST_HEAD(&rtwvif->general_pkt_list);
@@ -457,8 +458,16 @@ static int rtw89_ops_start_ap(struct ieee80211_hw *hw,
{
struct rtw89_dev *rtwdev = hw->priv;
struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
+ const struct rtw89_chan *chan;
mutex_lock(&rtwdev->mutex);
+
+ chan = rtw89_chan_get(rtwdev, rtwvif->sub_entity_idx);
+ if (chan->band_type == RTW89_BAND_6G) {
+ mutex_unlock(&rtwdev->mutex);
+ return -EOPNOTSUPP;
+ }
+
ether_addr_copy(rtwvif->bssid, vif->bss_conf.bssid);
rtw89_cam_bssid_changed(rtwdev, rtwvif);
rtw89_mac_port_update(rtwdev, rtwvif);
@@ -759,13 +768,18 @@ int rtw89_ops_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
struct rtw89_dev *rtwdev = hw->priv;
struct rtw89_hal *hal = &rtwdev->hal;
- if (rx_ant != hw->wiphy->available_antennas_rx && rx_ant != hal->antenna_rx)
+ if (hal->ant_diversity) {
+ if (tx_ant != rx_ant || hweight32(tx_ant) != 1)
+ return -EINVAL;
+ } else if (rx_ant != hw->wiphy->available_antennas_rx && rx_ant != hal->antenna_rx) {
return -EINVAL;
+ }
mutex_lock(&rtwdev->mutex);
hal->antenna_tx = tx_ant;
hal->antenna_rx = rx_ant;
hal->tx_path_diversity = false;
+ hal->ant_diversity_fixed = true;
mutex_unlock(&rtwdev->mutex);
return 0;
diff --git a/drivers/net/wireless/realtek/rtw89/pci.c b/drivers/net/wireless/realtek/rtw89/pci.c
index 70b4754667c9..9402f1a0caea 100644
--- a/drivers/net/wireless/realtek/rtw89/pci.c
+++ b/drivers/net/wireless/realtek/rtw89/pci.c
@@ -265,7 +265,7 @@ static u32 rtw89_pci_rxbd_deliver_skbs(struct rtw89_dev *rtwdev,
goto err_sync_device;
}
- rtw89_core_query_rxdesc(rtwdev, desc_info, skb->data, rxinfo_size);
+ rtw89_chip_query_rxdesc(rtwdev, desc_info, skb->data, rxinfo_size);
new = rtw89_alloc_skb_for_rx(rtwdev, desc_info->pkt_size);
if (!new)
@@ -274,9 +274,7 @@ static u32 rtw89_pci_rxbd_deliver_skbs(struct rtw89_dev *rtwdev,
rx_ring->diliver_skb = new;
/* first segment has RX desc */
- offset = desc_info->offset;
- offset += desc_info->long_rxdesc ? sizeof(struct rtw89_rxdesc_long) :
- sizeof(struct rtw89_rxdesc_short);
+ offset = desc_info->offset + desc_info->rxd_len;
} else {
offset = sizeof(struct rtw89_pci_rxbd_info);
if (!new) {
@@ -546,12 +544,10 @@ static u32 rtw89_pci_release_tx_skbs(struct rtw89_dev *rtwdev,
return cnt;
}
- rtw89_core_query_rxdesc(rtwdev, &desc_info, skb->data, rxinfo_size);
+ rtw89_chip_query_rxdesc(rtwdev, &desc_info, skb->data, rxinfo_size);
/* first segment has RX desc */
- offset = desc_info.offset;
- offset += desc_info.long_rxdesc ? sizeof(struct rtw89_rxdesc_long) :
- sizeof(struct rtw89_rxdesc_short);
+ offset = desc_info.offset + desc_info.rxd_len;
for (; offset + rpp_size <= rx_info->len; offset += rpp_size) {
rpp = (struct rtw89_pci_rpp_fmt *)(skb->data + offset);
rtw89_pci_release_rpp(rtwdev, rpp);
@@ -1003,10 +999,10 @@ static u32 __rtw89_pci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev,
min_cnt = min(bd_cnt, wd_cnt);
if (min_cnt == 0) {
/* This message can be frequently shown in low power mode or
- * high traffic with 8852B, and we have recognized it as normal
+ * high traffic with small FIFO chips, and we have recognized it as normal
* behavior, so print with mask RTW89_DBG_TXRX in these situations.
*/
- if (rtwpci->low_power || chip->chip_id == RTL8852B)
+ if (rtwpci->low_power || chip->small_fifo_size)
debug_mask = RTW89_DBG_TXRX;
else
debug_mask = RTW89_DBG_UNEXP;
@@ -3216,11 +3212,16 @@ static void rtw89_pci_clear_resource(struct rtw89_dev *rtwdev,
void rtw89_pci_config_intr_mask(struct rtw89_dev *rtwdev)
{
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
+ const struct rtw89_chip_info *chip = rtwdev->chip;
+ u32 hs0isr_ind_int_en = B_AX_HS0ISR_IND_INT_EN;
+
+ if (chip->chip_id == RTL8851B)
+ hs0isr_ind_int_en = B_AX_HS0ISR_IND_INT_EN_WKARND;
rtwpci->halt_c2h_intrs = B_AX_HALT_C2H_INT_EN | 0;
if (rtwpci->under_recovery) {
- rtwpci->intrs[0] = B_AX_HS0ISR_IND_INT_EN;
+ rtwpci->intrs[0] = hs0isr_ind_int_en;
rtwpci->intrs[1] = 0;
} else {
rtwpci->intrs[0] = B_AX_TXDMA_STUCK_INT_EN |
@@ -3230,7 +3231,7 @@ void rtw89_pci_config_intr_mask(struct rtw89_dev *rtwdev)
B_AX_RXDMA_STUCK_INT_EN |
B_AX_RDU_INT_EN |
B_AX_RPQBD_FULL_INT_EN |
- B_AX_HS0ISR_IND_INT_EN;
+ hs0isr_ind_int_en;
rtwpci->intrs[1] = B_AX_HC10ISR_IND_INT_EN;
}
diff --git a/drivers/net/wireless/realtek/rtw89/pci.h b/drivers/net/wireless/realtek/rtw89/pci.h
index 0e4bd210b100..2f3d1ad3b0f7 100644
--- a/drivers/net/wireless/realtek/rtw89/pci.h
+++ b/drivers/net/wireless/realtek/rtw89/pci.h
@@ -150,6 +150,7 @@
#define B_AX_HD1ISR_IND_INT_EN BIT(26)
#define B_AX_HD0ISR_IND_INT_EN BIT(25)
#define B_AX_HS0ISR_IND_INT_EN BIT(24)
+#define B_AX_HS0ISR_IND_INT_EN_WKARND BIT(23)
#define B_AX_RETRAIN_INT_EN BIT(21)
#define B_AX_RPQBD_FULL_INT_EN BIT(20)
#define B_AX_RDU_INT_EN BIT(19)
diff --git a/drivers/net/wireless/realtek/rtw89/phy.c b/drivers/net/wireless/realtek/rtw89/phy.c
index c7e906123416..fb15c852fdd4 100644
--- a/drivers/net/wireless/realtek/rtw89/phy.c
+++ b/drivers/net/wireless/realtek/rtw89/phy.c
@@ -10,6 +10,7 @@
#include "ps.h"
#include "reg.h"
#include "sar.h"
+#include "txrx.h"
#include "util.h"
static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev,
@@ -1400,7 +1401,8 @@ static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev)
rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x3);
rtw89_phy_write32_set(rtwdev, R_GNT_BT_WGT_EN, 0x1);
rtw89_phy_write32_set(rtwdev, R_P0_PATH_RST, 0x8000000);
- rtw89_phy_write32_set(rtwdev, R_P1_PATH_RST, 0x8000000);
+ if (chip->chip_id != RTL8851B)
+ rtw89_phy_write32_set(rtwdev, R_P1_PATH_RST, 0x8000000);
if (chip->chip_id == RTL8852B)
rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x2);
@@ -1414,6 +1416,9 @@ static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev)
nctl_table = chip->nctl_table;
rtw89_phy_init_reg(rtwdev, nctl_table, rtw89_phy_config_bb_reg, NULL);
+
+ if (chip->nctl_post_table)
+ rtw89_rfk_parser(rtwdev, chip->nctl_post_table);
}
static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr)
@@ -1489,19 +1494,19 @@ void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev,
}
EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl);
-static const u8 rtw89_rs_idx_max[] = {
- [RTW89_RS_CCK] = RTW89_RATE_CCK_MAX,
- [RTW89_RS_OFDM] = RTW89_RATE_OFDM_MAX,
- [RTW89_RS_MCS] = RTW89_RATE_MCS_MAX,
- [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_MAX,
- [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_MAX,
+static const u8 rtw89_rs_idx_num[] = {
+ [RTW89_RS_CCK] = RTW89_RATE_CCK_NUM,
+ [RTW89_RS_OFDM] = RTW89_RATE_OFDM_NUM,
+ [RTW89_RS_MCS] = RTW89_RATE_MCS_NUM,
+ [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_NUM,
+ [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_NUM,
};
-static const u8 rtw89_rs_nss_max[] = {
+static const u8 rtw89_rs_nss_num[] = {
[RTW89_RS_CCK] = 1,
[RTW89_RS_OFDM] = 1,
- [RTW89_RS_MCS] = RTW89_NSS_MAX,
- [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_MAX,
+ [RTW89_RS_MCS] = RTW89_NSS_NUM,
+ [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_NUM,
[RTW89_RS_OFFSET] = 1,
};
@@ -1514,9 +1519,9 @@ static const u8 _byr_of_rs[] = {
};
#define _byr_seek(rs, raw) ((s8 *)(raw) + _byr_of_rs[rs])
-#define _byr_idx(rs, nss, idx) ((nss) * rtw89_rs_idx_max[rs] + (idx))
+#define _byr_idx(rs, nss, idx) ((nss) * rtw89_rs_idx_num[rs] + (idx))
#define _byr_chk(rs, nss, idx) \
- ((nss) < rtw89_rs_nss_max[rs] && (idx) < rtw89_rs_idx_max[rs])
+ ((nss) < rtw89_rs_nss_num[rs] && (idx) < rtw89_rs_idx_num[rs])
void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev,
const struct rtw89_txpwr_table *tbl)
@@ -1621,8 +1626,10 @@ s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band,
const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz;
const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz;
const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz;
+ struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch);
u8 regd = rtw89_regd_get(rtwdev, band);
+ u8 reg6 = regulatory->reg_6ghz_power;
s8 lmt = 0, sar;
switch (band) {
@@ -1641,11 +1648,13 @@ s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band,
lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx];
break;
case RTW89_BAND_6G:
- lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx];
+ lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][regd][reg6][ch_idx];
if (lmt)
break;
- lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx];
+ lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][RTW89_WW]
+ [RTW89_REG_6GHZ_POWER_DFLT]
+ [ch_idx];
break;
default:
rtw89_warn(rtwdev, "unknown band type: %d\n", band);
@@ -1872,8 +1881,10 @@ static s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band,
const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz;
const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz;
const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz;
+ struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch);
u8 regd = rtw89_regd_get(rtwdev, band);
+ u8 reg6 = regulatory->reg_6ghz_power;
s8 lmt_ru = 0, sar;
switch (band) {
@@ -1892,11 +1903,13 @@ static s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band,
lmt_ru = (*rule_5ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx];
break;
case RTW89_BAND_6G:
- lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][regd][ch_idx];
+ lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][regd][reg6][ch_idx];
if (lmt_ru)
break;
- lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx];
+ lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][RTW89_WW]
+ [RTW89_REG_6GHZ_POWER_DFLT]
+ [ch_idx];
break;
default:
rtw89_warn(rtwdev, "unknown band type: %d\n", band);
@@ -2071,19 +2084,19 @@ void rtw89_phy_set_txpwr_byrate(struct rtw89_dev *rtwdev,
rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
"[TXPWR] set txpwr byrate with ch=%d\n", ch);
- BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_CCK] % 4);
- BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_OFDM] % 4);
- BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_MCS] % 4);
- BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_HEDCM] % 4);
+ BUILD_BUG_ON(rtw89_rs_idx_num[RTW89_RS_CCK] % 4);
+ BUILD_BUG_ON(rtw89_rs_idx_num[RTW89_RS_OFDM] % 4);
+ BUILD_BUG_ON(rtw89_rs_idx_num[RTW89_RS_MCS] % 4);
+ BUILD_BUG_ON(rtw89_rs_idx_num[RTW89_RS_HEDCM] % 4);
addr = R_AX_PWR_BY_RATE;
for (cur.nss = 0; cur.nss < max_nss_num; cur.nss++) {
for (i = 0; i < ARRAY_SIZE(rs); i++) {
- if (cur.nss >= rtw89_rs_nss_max[rs[i]])
+ if (cur.nss >= rtw89_rs_nss_num[rs[i]])
continue;
cur.rs = rs[i];
- for (cur.idx = 0; cur.idx < rtw89_rs_idx_max[rs[i]];
+ for (cur.idx = 0; cur.idx < rtw89_rs_idx_num[rs[i]];
cur.idx++) {
v[cur.idx % 4] =
rtw89_phy_read_txpwr_byrate(rtwdev,
@@ -2116,15 +2129,15 @@ void rtw89_phy_set_txpwr_offset(struct rtw89_dev *rtwdev,
.rs = RTW89_RS_OFFSET,
};
u8 band = chan->band_type;
- s8 v[RTW89_RATE_OFFSET_MAX] = {};
+ s8 v[RTW89_RATE_OFFSET_NUM] = {};
u32 val;
rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n");
- for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_MAX; desc.idx++)
+ for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_NUM; desc.idx++)
v[desc.idx] = rtw89_phy_read_txpwr_byrate(rtwdev, band, &desc);
- BUILD_BUG_ON(RTW89_RATE_OFFSET_MAX != 5);
+ BUILD_BUG_ON(RTW89_RATE_OFFSET_NUM != 5);
val = FIELD_PREP(GENMASK(3, 0), v[0]) |
FIELD_PREP(GENMASK(7, 4), v[1]) |
FIELD_PREP(GENMASK(11, 8), v[2]) |
@@ -2338,27 +2351,29 @@ void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
static u8 rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo)
{
+ const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info;
u32 reg_mask;
if (sc_xo)
- reg_mask = B_AX_XTAL_SC_XO_MASK;
+ reg_mask = xtal->sc_xo_mask;
else
- reg_mask = B_AX_XTAL_SC_XI_MASK;
+ reg_mask = xtal->sc_xi_mask;
- return (u8)rtw89_read32_mask(rtwdev, R_AX_XTAL_ON_CTRL0, reg_mask);
+ return (u8)rtw89_read32_mask(rtwdev, xtal->xcap_reg, reg_mask);
}
static void rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo,
u8 val)
{
+ const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info;
u32 reg_mask;
if (sc_xo)
- reg_mask = B_AX_XTAL_SC_XO_MASK;
+ reg_mask = xtal->sc_xo_mask;
else
- reg_mask = B_AX_XTAL_SC_XI_MASK;
+ reg_mask = xtal->sc_xi_mask;
- rtw89_write32_mask(rtwdev, R_AX_XTAL_ON_CTRL0, reg_mask, val);
+ rtw89_write32_mask(rtwdev, xtal->xcap_reg, reg_mask, val);
}
static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev,
@@ -2371,7 +2386,7 @@ static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev,
if (!force && cfo->crystal_cap == crystal_cap)
return;
crystal_cap = clamp_t(u8, crystal_cap, 0, 127);
- if (chip->chip_id == RTL8852A) {
+ if (chip->chip_id == RTL8852A || chip->chip_id == RTL8851B) {
rtw89_phy_cfo_set_xcap_reg(rtwdev, true, crystal_cap);
rtw89_phy_cfo_set_xcap_reg(rtwdev, false, crystal_cap);
sc_xo_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, true);
@@ -2946,6 +2961,126 @@ static void rtw89_phy_ul_tb_info_init(struct rtw89_dev *rtwdev)
rtw89_phy_read32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN);
}
+static
+void rtw89_phy_antdiv_sts_instance_reset(struct rtw89_antdiv_stats *antdiv_sts)
+{
+ ewma_rssi_init(&antdiv_sts->cck_rssi_avg);
+ ewma_rssi_init(&antdiv_sts->ofdm_rssi_avg);
+ ewma_rssi_init(&antdiv_sts->non_legacy_rssi_avg);
+ antdiv_sts->pkt_cnt_cck = 0;
+ antdiv_sts->pkt_cnt_ofdm = 0;
+ antdiv_sts->pkt_cnt_non_legacy = 0;
+ antdiv_sts->evm = 0;
+}
+
+static void rtw89_phy_antdiv_sts_instance_add(struct rtw89_dev *rtwdev,
+ struct rtw89_rx_phy_ppdu *phy_ppdu,
+ struct rtw89_antdiv_stats *stats)
+{
+ if (GET_DATA_RATE_MODE(phy_ppdu->rate) == DATA_RATE_MODE_NON_HT) {
+ if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) {
+ ewma_rssi_add(&stats->cck_rssi_avg, phy_ppdu->rssi_avg);
+ stats->pkt_cnt_cck++;
+ } else {
+ ewma_rssi_add(&stats->ofdm_rssi_avg, phy_ppdu->rssi_avg);
+ stats->pkt_cnt_ofdm++;
+ stats->evm += phy_ppdu->ofdm.evm_min;
+ }
+ } else {
+ ewma_rssi_add(&stats->non_legacy_rssi_avg, phy_ppdu->rssi_avg);
+ stats->pkt_cnt_non_legacy++;
+ stats->evm += phy_ppdu->ofdm.evm_min;
+ }
+}
+
+static u8 rtw89_phy_antdiv_sts_instance_get_rssi(struct rtw89_antdiv_stats *stats)
+{
+ if (stats->pkt_cnt_non_legacy >= stats->pkt_cnt_cck &&
+ stats->pkt_cnt_non_legacy >= stats->pkt_cnt_ofdm)
+ return ewma_rssi_read(&stats->non_legacy_rssi_avg);
+ else if (stats->pkt_cnt_ofdm >= stats->pkt_cnt_cck &&
+ stats->pkt_cnt_ofdm >= stats->pkt_cnt_non_legacy)
+ return ewma_rssi_read(&stats->ofdm_rssi_avg);
+ else
+ return ewma_rssi_read(&stats->cck_rssi_avg);
+}
+
+static u8 rtw89_phy_antdiv_sts_instance_get_evm(struct rtw89_antdiv_stats *stats)
+{
+ return phy_div(stats->evm, stats->pkt_cnt_non_legacy + stats->pkt_cnt_ofdm);
+}
+
+void rtw89_phy_antdiv_parse(struct rtw89_dev *rtwdev,
+ struct rtw89_rx_phy_ppdu *phy_ppdu)
+{
+ struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
+ struct rtw89_hal *hal = &rtwdev->hal;
+
+ if (!hal->ant_diversity || hal->ant_diversity_fixed)
+ return;
+
+ rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->target_stats);
+
+ if (!antdiv->get_stats)
+ return;
+
+ if (hal->antenna_rx == RF_A)
+ rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->main_stats);
+ else if (hal->antenna_rx == RF_B)
+ rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->aux_stats);
+}
+
+static void rtw89_phy_antdiv_reg_init(struct rtw89_dev *rtwdev)
+{
+ rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_ANT_TRAIN_EN,
+ 0x0, RTW89_PHY_0);
+ rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_TX_ANT_SEL,
+ 0x0, RTW89_PHY_0);
+
+ rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_TRSW_TX_EXTEND,
+ 0x0, RTW89_PHY_0);
+ rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_HW_ANTSW_DIS_BY_GNT_BT,
+ 0x0, RTW89_PHY_0);
+
+ rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_BT_FORCE_ANTIDX_EN,
+ 0x0, RTW89_PHY_0);
+
+ rtw89_phy_write32_idx(rtwdev, R_RFSW_CTRL_ANT0_BASE, B_RFSW_CTRL_ANT_MAPPING,
+ 0x0100, RTW89_PHY_0);
+
+ rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_BTG_TRX,
+ 0x1, RTW89_PHY_0);
+ rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_HW_CTRL,
+ 0x0, RTW89_PHY_0);
+ rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_2G,
+ 0x0, RTW89_PHY_0);
+ rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_5G,
+ 0x0, RTW89_PHY_0);
+}
+
+static void rtw89_phy_antdiv_sts_reset(struct rtw89_dev *rtwdev)
+{
+ struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
+
+ rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats);
+ rtw89_phy_antdiv_sts_instance_reset(&antdiv->main_stats);
+ rtw89_phy_antdiv_sts_instance_reset(&antdiv->aux_stats);
+}
+
+static void rtw89_phy_antdiv_init(struct rtw89_dev *rtwdev)
+{
+ struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
+ struct rtw89_hal *hal = &rtwdev->hal;
+
+ if (!hal->ant_diversity)
+ return;
+
+ antdiv->get_stats = false;
+ antdiv->rssi_pre = 0;
+ rtw89_phy_antdiv_sts_reset(rtwdev);
+ rtw89_phy_antdiv_reg_init(rtwdev);
+}
+
static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev)
{
struct rtw89_phy_stat *phystat = &rtwdev->phystat;
@@ -3053,11 +3188,8 @@ static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev)
env->ccx_manual_ctrl = false;
env->ccx_ongoing = false;
env->ccx_rac_lv = RTW89_RAC_RELEASE;
- env->ccx_rpt_stamp = 0;
env->ccx_period = 0;
env->ccx_unit_idx = RTW89_CCX_32_US;
- env->ccx_trigger_time = 0;
- env->ccx_edcca_opt_bw_idx = RTW89_CCX_EDCCA_BW20_0;
rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EN_MSK, 1);
rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_TRIG_OPT_MSK, 1);
@@ -3265,7 +3397,6 @@ static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev)
rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 1);
rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1);
- env->ccx_rpt_stamp++;
env->ccx_ongoing = true;
}
@@ -4114,6 +4245,144 @@ void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev)
&done);
}
+#define ANTDIV_MAIN 0
+#define ANTDIV_AUX 1
+
+static void rtw89_phy_antdiv_set_ant(struct rtw89_dev *rtwdev)
+{
+ struct rtw89_hal *hal = &rtwdev->hal;
+ u8 default_ant, optional_ant;
+
+ if (!hal->ant_diversity || hal->antenna_tx == 0)
+ return;
+
+ if (hal->antenna_tx == RF_B) {
+ default_ant = ANTDIV_AUX;
+ optional_ant = ANTDIV_MAIN;
+ } else {
+ default_ant = ANTDIV_MAIN;
+ optional_ant = ANTDIV_AUX;
+ }
+
+ rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_CGCS_CTRL,
+ default_ant, RTW89_PHY_0);
+ rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ORI,
+ default_ant, RTW89_PHY_0);
+ rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ALT,
+ optional_ant, RTW89_PHY_0);
+ rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_TX_ORI,
+ default_ant, RTW89_PHY_0);
+}
+
+static void rtw89_phy_swap_hal_antenna(struct rtw89_dev *rtwdev)
+{
+ struct rtw89_hal *hal = &rtwdev->hal;
+
+ hal->antenna_rx = hal->antenna_rx == RF_A ? RF_B : RF_A;
+ hal->antenna_tx = hal->antenna_rx;
+}
+
+static void rtw89_phy_antdiv_decision_state(struct rtw89_dev *rtwdev)
+{
+ struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
+ struct rtw89_hal *hal = &rtwdev->hal;
+ bool no_change = false;
+ u8 main_rssi, aux_rssi;
+ u8 main_evm, aux_evm;
+ u32 candidate;
+
+ antdiv->get_stats = false;
+ antdiv->training_count = 0;
+
+ main_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->main_stats);
+ main_evm = rtw89_phy_antdiv_sts_instance_get_evm(&antdiv->main_stats);
+ aux_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->aux_stats);
+ aux_evm = rtw89_phy_antdiv_sts_instance_get_evm(&antdiv->aux_stats);
+
+ if (main_evm > aux_evm + ANTDIV_EVM_DIFF_TH)
+ candidate = RF_A;
+ else if (aux_evm > main_evm + ANTDIV_EVM_DIFF_TH)
+ candidate = RF_B;
+ else if (main_rssi > aux_rssi + RTW89_TX_DIV_RSSI_RAW_TH)
+ candidate = RF_A;
+ else if (aux_rssi > main_rssi + RTW89_TX_DIV_RSSI_RAW_TH)
+ candidate = RF_B;
+ else
+ no_change = true;
+
+ if (no_change) {
+ /* swap back from training antenna to original */
+ rtw89_phy_swap_hal_antenna(rtwdev);
+ return;
+ }
+
+ hal->antenna_tx = candidate;
+ hal->antenna_rx = candidate;
+}
+
+static void rtw89_phy_antdiv_training_state(struct rtw89_dev *rtwdev)
+{
+ struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
+ u64 state_period;
+
+ if (antdiv->training_count % 2 == 0) {
+ if (antdiv->training_count == 0)
+ rtw89_phy_antdiv_sts_reset(rtwdev);
+
+ antdiv->get_stats = true;
+ state_period = msecs_to_jiffies(ANTDIV_TRAINNING_INTVL);
+ } else {
+ antdiv->get_stats = false;
+ state_period = msecs_to_jiffies(ANTDIV_DELAY);
+
+ rtw89_phy_swap_hal_antenna(rtwdev);
+ rtw89_phy_antdiv_set_ant(rtwdev);
+ }
+
+ antdiv->training_count++;
+ ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->antdiv_work,
+ state_period);
+}
+
+void rtw89_phy_antdiv_work(struct work_struct *work)
+{
+ struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
+ antdiv_work.work);
+ struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
+
+ mutex_lock(&rtwdev->mutex);
+
+ if (antdiv->training_count <= ANTDIV_TRAINNING_CNT) {
+ rtw89_phy_antdiv_training_state(rtwdev);
+ } else {
+ rtw89_phy_antdiv_decision_state(rtwdev);
+ rtw89_phy_antdiv_set_ant(rtwdev);
+ }
+
+ mutex_unlock(&rtwdev->mutex);
+}
+
+void rtw89_phy_antdiv_track(struct rtw89_dev *rtwdev)
+{
+ struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
+ struct rtw89_hal *hal = &rtwdev->hal;
+ u8 rssi, rssi_pre;
+
+ if (!hal->ant_diversity || hal->ant_diversity_fixed)
+ return;
+
+ rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->target_stats);
+ rssi_pre = antdiv->rssi_pre;
+ antdiv->rssi_pre = rssi;
+ rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats);
+
+ if (abs((int)rssi - (int)rssi_pre) < ANTDIV_RSSI_DIFF_TH)
+ return;
+
+ antdiv->training_count = 0;
+ ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->antdiv_work, 0);
+}
+
static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev)
{
rtw89_phy_ccx_top_setting_init(rtwdev);
@@ -4133,6 +4402,9 @@ void rtw89_phy_dm_init(struct rtw89_dev *rtwdev)
rtw89_phy_dig_init(rtwdev);
rtw89_phy_cfo_init(rtwdev);
rtw89_phy_ul_tb_info_init(rtwdev);
+ rtw89_phy_antdiv_init(rtwdev);
+ rtw89_chip_rfe_gpio(rtwdev);
+ rtw89_phy_antdiv_set_ant(rtwdev);
rtw89_phy_init_rf_nctl(rtwdev);
rtw89_chip_rfk_init(rtwdev);
diff --git a/drivers/net/wireless/realtek/rtw89/phy.h b/drivers/net/wireless/realtek/rtw89/phy.h
index 7535867d0f48..ab174a0ba488 100644
--- a/drivers/net/wireless/realtek/rtw89/phy.h
+++ b/drivers/net/wireless/realtek/rtw89/phy.h
@@ -67,6 +67,14 @@
#define UL_TB_TF_CNT_L2H_TH 100
#define UL_TB_TF_CNT_H2L_TH 70
+#define ANTDIV_TRAINNING_CNT 2
+#define ANTDIV_TRAINNING_INTVL 30
+#define ANTDIV_DELAY 110
+#define ANTDIV_TP_DIFF_TH_HIGH 100
+#define ANTDIV_TP_DIFF_TH_LOW 5
+#define ANTDIV_EVM_DIFF_TH 8
+#define ANTDIV_RSSI_DIFF_TH 3
+
#define CCX_MAX_PERIOD 2097
#define CCX_MAX_PERIOD_UNIT 32
#define MS_TO_4US_RATIO 250
@@ -549,6 +557,10 @@ void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev);
void rtw89_phy_dig(struct rtw89_dev *rtwdev);
void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev);
+void rtw89_phy_antdiv_parse(struct rtw89_dev *rtwdev,
+ struct rtw89_rx_phy_ppdu *phy_ppdu);
+void rtw89_phy_antdiv_track(struct rtw89_dev *rtwdev);
+void rtw89_phy_antdiv_work(struct work_struct *work);
void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif);
void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev,
enum rtw89_mac_idx mac_idx,
diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h
index 266e4231b5f3..55595fde7494 100644
--- a/drivers/net/wireless/realtek/rtw89/reg.h
+++ b/drivers/net/wireless/realtek/rtw89/reg.h
@@ -19,6 +19,8 @@
#define B_AX_FEN_BBRSTB BIT(0)
#define R_AX_SYS_PW_CTRL 0x0004
+#define B_AX_SOP_ASWRM BIT(31)
+#define B_AX_SOP_PWMM_DSWR BIT(29)
#define B_AX_XTAL_OFF_A_DIE BIT(22)
#define B_AX_DIS_WLBT_PDNSUSEN_SOPC BIT(18)
#define B_AX_RDY_SYSPWR BIT(17)
@@ -134,6 +136,8 @@
#define B_AX_PLATFORM_EN BIT(0)
#define R_AX_WLLPS_CTRL 0x0090
+#define B_AX_LPSOP_ASWRM BIT(17)
+#define B_AX_LPSOP_DSWRM BIT(9)
#define B_AX_DIS_WLBT_LPSEN_LOPC BIT(1)
#define SW_LPS_OPTION 0x0001A0B2
@@ -222,9 +226,14 @@
#define B_AX_OCP_L1_MASK GENMASK(15, 13)
#define B_AX_VOL_L1_MASK GENMASK(3, 0)
+#define R_AX_SPSLDO_ON_CTRL1 0x0204
+#define B_AX_FPWMDELAY BIT(3)
+
#define R_AX_LDO_AON_CTRL0 0x0218
#define B_AX_PD_REGU_L BIT(16)
+#define R_AX_SPSANA_ON_CTRL1 0x0224
+
#define R_AX_WLAN_XTAL_SI_CTRL 0x0270
#define B_AX_WL_XTAL_SI_CMD_POLL BIT(31)
#define B_AX_BT_XTAL_SI_ERR_FLAG BIT(30)
@@ -237,17 +246,30 @@
#define B_AX_WL_XTAL_SI_DATA_MASK GENMASK(15, 8)
#define B_AX_WL_XTAL_SI_ADDR_MASK GENMASK(7, 0)
+#define R_AX_WLAN_XTAL_SI_CONFIG 0x0274
+#define B_AX_XTAL_SI_ADDR_NOT_CHK BIT(0)
+
#define R_AX_XTAL_ON_CTRL0 0x0280
#define B_AX_XTAL_SC_LPS BIT(31)
#define B_AX_XTAL_SC_XO_MASK GENMASK(23, 17)
#define B_AX_XTAL_SC_XI_MASK GENMASK(16, 10)
#define B_AX_XTAL_SC_MASK GENMASK(6, 0)
+#define R_AX_XTAL_ON_CTRL3 0x028C
+#define B_AX_XTAL_SC_INIT_A_BLOCK_MASK GENMASK(30, 24)
+#define B_AX_XTAL_SC_LPS_A_BLOCK_MASK GENMASK(22, 16)
+#define B_AX_XTAL_SC_XO_A_BLOCK_MASK GENMASK(14, 8)
+#define B_AX_XTAL_SC_XI_A_BLOCK_MASK GENMASK(6, 0)
+
#define R_AX_GPIO0_7_FUNC_SEL 0x02D0
#define R_AX_EECS_EESK_FUNC_SEL 0x02D8
#define B_AX_PINMUX_EESK_FUNC_SEL_MASK GENMASK(7, 4)
+#define R_AX_GPIO16_23_FUNC_SEL 0x02D8
+#define B_AX_PINMUX_GPIO17_FUNC_SEL_MASK GENMASK(7, 4)
+#define B_AX_PINMUX_GPIO16_FUNC_SEL_MASK GENMASK(3, 0)
+
#define R_AX_LED1_FUNC_SEL 0x02DC
#define B_AX_PINMUX_EESK_FUNC_SEL_V1_MASK GENMASK(27, 24)
#define PINMUX_EESK_FUNC_SEL_BT_LOG 0x1
@@ -257,6 +279,10 @@
#define B_AX_EESK_PULL_LOW_EN BIT(17)
#define B_AX_EECS_PULL_LOW_EN BIT(16)
+#define R_AX_GPIO0_16_EECS_EESK_LED1_PULL_LOW_EN 0x02E4
+#define B_AX_GPIO16_PULL_LOW_EN_V1 BIT(19)
+#define B_AX_GPIO10_PULL_LOW_EN BIT(10)
+
#define R_AX_WLRF_CTRL 0x02F0
#define B_AX_AFC_AFEDIG BIT(17)
#define B_AX_WLRF1_CTRL_7 BIT(15)
@@ -3299,10 +3325,36 @@
#define B_AX_TXAGC_BT_EN BIT(1)
#define B_AX_TXAGC_BT_MASK GENMASK(11, 3)
+#define R_AX_PWR_SWING_OTHER_CTRL0 0xD230
+#define R_AX_PWR_SWING_OTHER_CTRL0_C1 0xF230
+#define B_AX_CFIR_BY_RATE_OFF_MASK GENMASK(17, 0)
+
#define R_AX_PWR_UL_CTRL0 0xD240
#define R_AX_PWR_UL_CTRL2 0xD248
#define B_AX_PWR_UL_CFO_MASK GENMASK(2, 0)
#define B_AX_PWR_UL_CTRL2_MASK 0x07700007
+
+#define R_AX_PWR_NORM_FORCE1 0xD260
+#define R_AX_PWR_NORM_FORCE1_C1 0xF260
+#define B_AX_TXAGC_BF_PWR_BOOST_FORCE_VAL_EN BIT(29)
+#define B_AX_TXAGC_BF_PWR_BOOST_FORCE_VAL_MASK GENMASK(28, 24)
+#define B_AX_FORCE_HE_ER_SU_EN_EN BIT(23)
+#define B_AX_FORCE_HE_ER_SU_EN_VALUE BIT(22)
+#define B_AX_FORCE_MACID_CCA_TH_EN_EN BIT(21)
+#define B_AX_FORCE_MACID_CCA_TH_EN_VALUE BIT(20)
+#define B_AX_FORCE_BT_GRANT_EN BIT(19)
+#define B_AX_FORCE_BT_GRANT_VALUE BIT(18)
+#define B_AX_FORCE_RX_LTE_EN BIT(17)
+#define B_AX_FORCE_RX_LTE_VALUE BIT(16)
+#define B_AX_FORCE_TXBF_EN_EN BIT(15)
+#define B_AX_FORCE_TXBF_EN_VALUE BIT(14)
+#define B_AX_FORCE_TXSC_EN BIT(13)
+#define B_AX_FORCE_TXSC_VALUE_MASK GENMASK(12, 9)
+#define B_AX_FORCE_NTX_EN BIT(6)
+#define B_AX_FORCE_NTX_VALUE BIT(5)
+#define B_AX_FORCE_PWR_MODE_EN BIT(3)
+#define B_AX_FORCE_PWR_MODE_VALUE_MASK GENMASK(2, 0)
+
#define R_AX_PWR_UL_TB_CTRL 0xD288
#define B_AX_PWR_UL_TB_CTRL_EN BIT(31)
#define R_AX_PWR_UL_TB_1T 0xD28C
@@ -3312,16 +3364,22 @@
#define B_AX_PWR_UL_TB_2T_MASK GENMASK(4, 0)
#define B_AX_PWR_UL_TB_2T_V1_MASK GENMASK(7, 0)
#define R_AX_PWR_BY_RATE_TABLE0 0xD2C0
+#define R_AX_PWR_BY_RATE_TABLE6 0xD2D8
#define R_AX_PWR_BY_RATE_TABLE10 0xD2E8
#define R_AX_PWR_BY_RATE R_AX_PWR_BY_RATE_TABLE0
+#define R_AX_PWR_BY_RATE_1SS_MAX R_AX_PWR_BY_RATE_TABLE6
#define R_AX_PWR_BY_RATE_MAX R_AX_PWR_BY_RATE_TABLE10
#define R_AX_PWR_LMT_TABLE0 0xD2EC
+#define R_AX_PWR_LMT_TABLE9 0xD310
#define R_AX_PWR_LMT_TABLE19 0xD338
#define R_AX_PWR_LMT R_AX_PWR_LMT_TABLE0
+#define R_AX_PWR_LMT_1SS_MAX R_AX_PWR_LMT_TABLE9
#define R_AX_PWR_LMT_MAX R_AX_PWR_LMT_TABLE19
#define R_AX_PWR_RU_LMT_TABLE0 0xD33C
+#define R_AX_PWR_RU_LMT_TABLE5 0xD350
#define R_AX_PWR_RU_LMT_TABLE11 0xD368
#define R_AX_PWR_RU_LMT R_AX_PWR_RU_LMT_TABLE0
+#define R_AX_PWR_RU_LMT_1SS_MAX R_AX_PWR_RU_LMT_TABLE5
#define R_AX_PWR_RU_LMT_MAX R_AX_PWR_RU_LMT_TABLE11
#define R_AX_PWR_MACID_LMT_TABLE0 0xD36C
#define R_AX_PWR_MACID_LMT_TABLE127 0xD568
@@ -3574,6 +3632,7 @@
#define RR_MOD_MASK GENMASK(19, 16)
#define RR_MOD_DCK GENMASK(14, 10)
#define RR_MOD_RGM GENMASK(13, 4)
+#define RR_MOD_RXB GENMASK(9, 5)
#define RR_MOD_V_DOWN 0x0
#define RR_MOD_V_STANDBY 0x1
#define RR_TXAGC 0x10001
@@ -3713,6 +3772,7 @@
#define RR_RXBB 0x83
#define RR_RXBB_VOBUF GENMASK(15, 12)
#define RR_RXBB_C2G GENMASK(16, 10)
+#define RR_RXBB_C2 GENMASK(11, 8)
#define RR_RXBB_C1G GENMASK(9, 8)
#define RR_RXBB_FATT GENMASK(7, 0)
#define RR_RXBB_ATTR GENMASK(7, 4)
@@ -3727,6 +3787,7 @@
#define RR_RXA_DPK GENMASK(9, 8)
#define RR_RXA_LNA 0x8b
#define RR_RXA2 0x8c
+#define RR_RAA2_SATT GENMASK(15, 13)
#define RR_RAA2_SWATT GENMASK(15, 9)
#define RR_RXA2_C1 GENMASK(12, 10)
#define RR_RXA2_C2 GENMASK(9, 3)
@@ -3776,19 +3837,26 @@
#define RR_LOGEN 0xa3
#define RR_LOGEN_RPT GENMASK(19, 16)
#define RR_SX 0xaf
+#define RR_IBD 0xc9
+#define RR_IBD_VAL GENMASK(4, 0)
#define RR_LDO 0xb1
#define RR_LDO_SEL GENMASK(8, 6)
#define RR_VCO 0xb2
+#define RR_VCO_SEL GENMASK(9, 8)
+#define RR_VCI 0xb3
+#define RR_VCI_ON BIT(7)
#define RR_LPF 0xb7
#define RR_LPF_BUSY BIT(8)
#define RR_XTALX2 0xb8
#define RR_MALSEL 0xbe
#define RR_SYNFB 0xc5
#define RR_SYNFB_LK BIT(15)
+#define RR_AACK 0xca
#define RR_LCKST 0xcf
#define RR_LCKST_BIN BIT(0)
#define RR_LCK_TRG 0xd3
#define RR_LCK_TRGSEL BIT(8)
+#define RR_LCK_ST BIT(4)
#define RR_MMD 0xd5
#define RR_MMD_RST_EN BIT(8)
#define RR_MMD_RST_SYN BIT(6)
@@ -3807,6 +3875,7 @@
#define RR_CAL_RW BIT(19)
#define RR_LUTWE2 0xee
#define RR_LUTWE2_RTXBW BIT(2)
+#define RR_LUTWE2_DIS BIT(6)
#define RR_LUTWE 0xef
#define RR_LUTWE_LOK BIT(2)
#define RR_RFC 0xf0
@@ -3832,6 +3901,7 @@
#define R_RFE_E_A2 0x0334
#define R_RFE_O_SEL_A2 0x0338
#define R_RFE_SEL0_A2 0x033C
+#define B_RFE_SEL0_MASK GENMASK(1, 0)
#define R_RFE_SEL32_A2 0x0340
#define R_CIRST 0x035c
#define B_CIRST_SYN GENMASK(11, 10)
@@ -3852,6 +3922,9 @@
#define B_ENABLE_CCK BIT(5)
#define R_RSTB_ASYNC 0x0704
#define B_RSTB_ASYNC_ALL BIT(1)
+#define R_P0_ANT_SW 0x0728
+#define B_P0_HW_ANTSW_DIS_BY_GNT_BT BIT(12)
+#define B_P0_TRSW_TX_EXTEND GENMASK(3, 0)
#define R_MAC_PIN_SEL 0x0734
#define B_CH_IDX_SEG0 GENMASK(23, 16)
#define R_PLCP_HISTOGRAM 0x0738
@@ -3961,6 +4034,7 @@
#define R_S0_HW_SI_DIS 0x1200
#define B_S0_HW_SI_DIS_W_R_TRIG GENMASK(30, 28)
#define R_P0_RXCK 0x12A0
+#define B_P0_RXCK_ADJ GENMASK(31, 23)
#define B_P0_RXCK_BW3 BIT(30)
#define B_P0_TXCK_ALL GENMASK(19, 12)
#define B_P0_RXCK_ON BIT(19)
@@ -4034,6 +4108,7 @@
#define R_TXAGC_BB 0x1C60
#define B_TXAGC_BB_OFT GENMASK(31, 16)
#define B_TXAGC_BB GENMASK(31, 24)
+#define B_TXAGC_RF GENMASK(5, 0)
#define R_S0_ADDCK 0x1E00
#define B_S0_ADDCK_I GENMASK(9, 0)
#define B_S0_ADDCK_Q GENMASK(19, 10)
@@ -4117,8 +4192,10 @@
#define R_DCFO 0x4264
#define B_DCFO GENMASK(7, 0)
#define R_SEG0CSI 0x42AC
+#define R_SEG0CSI_V1 0x42B0
#define B_SEG0CSI_IDX GENMASK(10, 0)
#define R_SEG0CSI_EN 0x42C4
+#define R_SEG0CSI_EN_V1 0x42C8
#define B_SEG0CSI_EN BIT(23)
#define R_BSS_CLR_MAP 0x43ac
#define R_BSS_CLR_MAP_V1 0x43B0
@@ -4350,6 +4427,14 @@
#define B_PATH0_BT_BACKOFF_V1 GENMASK(23, 0)
#define R_PATH1_BT_BACKOFF_V1 0x4AEC
#define B_PATH1_BT_BACKOFF_V1 GENMASK(23, 0)
+#define R_DCFO_COMP_S0_V2 0x4B20
+#define B_DCFO_COMP_S0_MSK_V2 GENMASK(13, 0)
+#define R_PATH0_TX_CFR 0x4B30
+#define B_PATH0_TX_CFR_LGC1 GENMASK(19, 10)
+#define B_PATH0_TX_CFR_LGC0 GENMASK(9, 0)
+#define R_PATH0_TX_POLAR_CLIPPING 0x4B3C
+#define B_PATH0_TX_POLAR_CLIPPING_LGC1 GENMASK(19, 16)
+#define B_PATH0_TX_POLAR_CLIPPING_LGC0 GENMASK(15, 12)
#define R_PATH0_FRC_FIR_TYPE_V1 0x4C00
#define B_PATH0_FRC_FIR_TYPE_MSK_V1 GENMASK(1, 0)
#define R_PATH0_NOTCH 0x4C14
@@ -4455,10 +4540,29 @@
#define B_P0_RFCTM_VAL GENMASK(25, 20)
#define R_P0_RFCTM_RDY BIT(26)
#define R_P0_TRSW 0x5868
-#define B_P0_TRSW_B BIT(0)
-#define B_P0_TRSW_A BIT(1)
+#define B_P0_BT_FORCE_ANTIDX_EN BIT(12)
#define B_P0_TRSW_X BIT(2)
+#define B_P0_TRSW_A BIT(1)
+#define B_P0_TX_ANT_SEL BIT(1)
+#define B_P0_TRSW_B BIT(0)
+#define B_P0_ANT_TRAIN_EN BIT(0)
#define B_P0_TRSW_SO_A2 GENMASK(7, 5)
+#define R_P0_ANTSEL 0x586C
+#define B_P0_ANTSEL_SW_5G BIT(25)
+#define B_P0_ANTSEL_SW_2G BIT(23)
+#define B_P0_ANTSEL_BTG_TRX BIT(21)
+#define B_P0_ANTSEL_CGCS_CTRL BIT(17)
+#define B_P0_ANTSEL_HW_CTRL BIT(16)
+#define B_P0_ANTSEL_TX_ORI GENMASK(15, 12)
+#define B_P0_ANTSEL_RX_ALT GENMASK(11, 8)
+#define B_P0_ANTSEL_RX_ORI GENMASK(7, 4)
+#define R_RFSW_CTRL_ANT0_BASE 0x5870
+#define B_RFSW_CTRL_ANT_MAPPING GENMASK(15, 0)
+#define R_RFE_SEL0_BASE 0x5880
+#define B_RFE_SEL0_SRC_MASK GENMASK(3, 0)
+#define R_RFE_SEL32_BASE 0x5884
+#define RFE_SEL0_SRC_ANTSEL_0 8
+#define R_RFE_INV0 0x5890
#define R_P0_RFM 0x5894
#define B_P0_RFM_DIS_WL BIT(7)
#define B_P0_RFM_TX_OPT BIT(6)
@@ -4572,12 +4676,15 @@
#define IQK_DF4_TXT_8_25MHZ 0x021
#define R_IQK_CFG 0x8034
#define B_IQK_CFG_SET GENMASK(5, 4)
+#define R_IQK_RXA 0x8044
+#define B_IQK_RXAGC GENMASK(15, 13)
#define R_TPG_SEL 0x8068
#define R_TPG_MOD 0x806C
#define B_TPG_MOD_F GENMASK(2, 1)
#define R_MDPK_SYNC 0x8070
#define B_MDPK_SYNC_SEL BIT(31)
#define B_MDPK_SYNC_MAN GENMASK(31, 28)
+#define B_MDPK_SYNC_DMAN GENMASK(30, 28)
#define R_MDPK_RX_DCK 0x8074
#define B_MDPK_RX_DCK_EN BIT(31)
#define R_KIP_MOD 0x8078
@@ -4586,6 +4693,7 @@
#define R_KIP_SYSCFG 0x8088
#define R_KIP_CLK 0x808C
#define R_DPK_IDL 0x809C
+#define B_DPK_IDL_SEL GENMASK(10, 9)
#define B_DPK_IDL BIT(8)
#define R_LDL_NORM 0x80A0
#define B_LDL_NORM_MA BIT(16)
@@ -4604,6 +4712,10 @@
#define B_KIP_RPT1_SEL GENMASK(21, 16)
#define B_KIP_RPT1_SEL_V1 GENMASK(19, 16)
#define R_SRAM_IQRX 0x80D8
+#define R_IDL_MPA 0x80DC
+#define B_IDL_DN BIT(31)
+#define B_IDL_MD530 BIT(1)
+#define B_IDL_MD500 BIT(0)
#define R_GAPK 0x80E0
#define B_GAPK_ADR BIT(0)
#define R_SRAM_IQRX2 0x80E8
@@ -4619,6 +4731,7 @@
#define B_PRT_COM_SYNERR BIT(30)
#define B_PRT_COM_DCI GENMASK(27, 16)
#define B_PRT_COM_CORV GENMASK(15, 8)
+#define B_RPT_COM_RDY GENMASK(15, 0)
#define B_PRT_COM_DCQ GENMASK(11, 0)
#define B_PRT_COM_RXOV BIT(8)
#define B_PRT_COM_GL GENMASK(7, 4)
@@ -4690,6 +4803,7 @@
#define B_DPK_GL_A0 GENMASK(31, 28)
#define B_DPK_GL_A1 GENMASK(17, 0)
#define R_RPT_PER 0x81FC
+#define B_RPT_PER_KSET GENMASK(31, 29)
#define B_RPT_PER_TSSI GENMASK(28, 16)
#define B_RPT_PER_OF GENMASK(15, 8)
#define B_RPT_PER_TH GENMASK(5, 0)
@@ -4730,11 +4844,15 @@
#define B_IQKINF2_KCNT GENMASK(15, 8)
#define B_IQKINF2_NCTLV GENMASK(7, 0)
#define R_DCOF0 0xC000
+#define B_DCOF0_RST BIT(17)
#define B_DCOF0_V GENMASK(4, 1)
#define R_DCOF1 0xC004
+#define B_DCOF1_RST BIT(17)
#define B_DCOF1_S BIT(0)
#define R_DCOF8 0xC020
#define B_DCOF8_V GENMASK(4, 1)
+#define R_DCOF9 0xC024
+#define B_DCOF9_RST BIT(17)
#define R_DACK_S0P0 0xC040
#define B_DACK_S0P0_OK BIT(31)
#define R_DACK_BIAS00 0xc048
@@ -4779,13 +4897,19 @@
#define R_P0_CFCH_BW1 0xC0D8
#define B_P0_CFCH_EX BIT(13)
#define B_P0_CFCH_BW1 GENMASK(8, 5)
+#define R_WDADC 0xC0E4
+#define B_WDADC_SEL GENMASK(5, 4)
#define R_ADCMOD 0xC0E8
#define B_ADCMOD_LP GENMASK(31, 16)
+#define R_DCIM 0xC0EC
+#define B_DCIM_FR GENMASK(14, 13)
#define R_ADDCK0D 0xC0F0
#define B_ADDCK0D_VAL2 GENMASK(31, 26)
#define B_ADDCK0D_VAL GENMASK(25, 16)
+#define B_ADDCK_DS BIT(16)
#define R_ADDCK0 0xC0F4
#define B_ADDCK0_TRG BIT(11)
+#define B_ADDCK0_IQ BIT(10)
#define B_ADDCK0 GENMASK(9, 8)
#define B_ADDCK0_MAN GENMASK(5, 4)
#define B_ADDCK0_EN BIT(4)
@@ -4797,6 +4921,7 @@
#define B_ADDCK0_RL0 GENMASK(17, 8)
#define R_ADDCKR0 0xC0FC
#define B_ADDCKR0_A0 GENMASK(19, 10)
+#define B_ADDCKR0_DC GENMASK(15, 4)
#define B_ADDCKR0_A1 GENMASK(9, 0)
#define R_DACK10 0xC100
#define B_DACK10 GENMASK(4, 1)
@@ -4847,6 +4972,11 @@
#define R_ADDCKR1 0xC1fC
#define B_ADDCKR1_A0 GENMASK(19, 10)
#define B_ADDCKR1_A1 GENMASK(9, 0)
+#define R_DACKN0_CTL 0xC210
+#define B_DACKN0_EN BIT(0)
+#define B_DACKN0_V GENMASK(21, 14)
+#define R_DACKN1_CTL 0xC224
+#define B_DACKN1_V GENMASK(21, 14)
/* WiFi CPU local domain */
#define R_AX_WDT_CTRL 0x0040
diff --git a/drivers/net/wireless/realtek/rtw89/regd.c b/drivers/net/wireless/realtek/rtw89/regd.c
index 6e5a740b128f..34c4d40cfa02 100644
--- a/drivers/net/wireless/realtek/rtw89/regd.c
+++ b/drivers/net/wireless/realtek/rtw89/regd.c
@@ -2,33 +2,35 @@
/* Copyright(c) 2019-2020 Realtek Corporation
*/
+#include "acpi.h"
#include "debug.h"
#include "ps.h"
+#include "util.h"
#define COUNTRY_REGD(_alpha2, _txpwr_regd...) \
{.alpha2 = (_alpha2), \
.txpwr_regd = {_txpwr_regd}, \
}
-static const struct rtw89_regulatory rtw89_ww_regd =
+static const struct rtw89_regd rtw89_ww_regd =
COUNTRY_REGD("00", RTW89_WW, RTW89_WW);
-static const struct rtw89_regulatory rtw89_regd_map[] = {
+static const struct rtw89_regd rtw89_regd_map[] = {
COUNTRY_REGD("AR", RTW89_MEXICO, RTW89_MEXICO, RTW89_NA),
- COUNTRY_REGD("BO", RTW89_FCC, RTW89_FCC, RTW89_NA),
+ COUNTRY_REGD("BO", RTW89_FCC, RTW89_FCC, RTW89_FCC),
COUNTRY_REGD("BR", RTW89_FCC, RTW89_FCC, RTW89_FCC),
COUNTRY_REGD("CL", RTW89_CHILE, RTW89_CHILE, RTW89_CHILE),
- COUNTRY_REGD("CO", RTW89_FCC, RTW89_FCC, RTW89_NA),
+ COUNTRY_REGD("CO", RTW89_FCC, RTW89_FCC, RTW89_FCC),
COUNTRY_REGD("CR", RTW89_FCC, RTW89_FCC, RTW89_FCC),
COUNTRY_REGD("EC", RTW89_FCC, RTW89_FCC, RTW89_NA),
- COUNTRY_REGD("SV", RTW89_FCC, RTW89_FCC, RTW89_NA),
- COUNTRY_REGD("GT", RTW89_FCC, RTW89_FCC, RTW89_NA),
+ COUNTRY_REGD("SV", RTW89_FCC, RTW89_FCC, RTW89_FCC),
+ COUNTRY_REGD("GT", RTW89_FCC, RTW89_FCC, RTW89_FCC),
COUNTRY_REGD("HN", RTW89_FCC, RTW89_FCC, RTW89_FCC),
COUNTRY_REGD("MX", RTW89_MEXICO, RTW89_MEXICO, RTW89_NA),
COUNTRY_REGD("NI", RTW89_FCC, RTW89_FCC, RTW89_NA),
COUNTRY_REGD("PA", RTW89_FCC, RTW89_FCC, RTW89_NA),
COUNTRY_REGD("PY", RTW89_FCC, RTW89_FCC, RTW89_NA),
- COUNTRY_REGD("PE", RTW89_FCC, RTW89_FCC, RTW89_NA),
+ COUNTRY_REGD("PE", RTW89_FCC, RTW89_FCC, RTW89_FCC),
COUNTRY_REGD("US", RTW89_FCC, RTW89_FCC, RTW89_FCC),
COUNTRY_REGD("UY", RTW89_FCC, RTW89_FCC, RTW89_NA),
COUNTRY_REGD("VE", RTW89_FCC, RTW89_FCC, RTW89_NA),
@@ -65,37 +67,37 @@ static const struct rtw89_regulatory rtw89_regd_map[] = {
COUNTRY_REGD("CH", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
COUNTRY_REGD("GB", RTW89_UK, RTW89_UK, RTW89_UK),
COUNTRY_REGD("AL", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("AZ", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("BH", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
+ COUNTRY_REGD("AZ", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
+ COUNTRY_REGD("BH", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
COUNTRY_REGD("BA", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("BG", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("HR", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
+ COUNTRY_REGD("BG", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
+ COUNTRY_REGD("HR", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
COUNTRY_REGD("EG", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("GH", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
+ COUNTRY_REGD("GH", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
COUNTRY_REGD("IQ", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("IL", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("JO", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
+ COUNTRY_REGD("IL", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
+ COUNTRY_REGD("JO", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
COUNTRY_REGD("KZ", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("KE", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("KW", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("KG", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
+ COUNTRY_REGD("KE", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
+ COUNTRY_REGD("KW", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
+ COUNTRY_REGD("KG", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
COUNTRY_REGD("LB", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("LS", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("MK", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("MA", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
+ COUNTRY_REGD("MA", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
COUNTRY_REGD("MZ", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("NA", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("NG", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("OM", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("QA", RTW89_QATAR, RTW89_QATAR, RTW89_QATAR),
- COUNTRY_REGD("RO", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
+ COUNTRY_REGD("RO", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
COUNTRY_REGD("RU", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("SA", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
+ COUNTRY_REGD("SA", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
COUNTRY_REGD("SN", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("RS", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
+ COUNTRY_REGD("RS", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
COUNTRY_REGD("ME", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("ZA", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("TR", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
+ COUNTRY_REGD("TR", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
COUNTRY_REGD("UA", RTW89_UKRAINE, RTW89_UKRAINE, RTW89_UKRAINE),
COUNTRY_REGD("AE", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
COUNTRY_REGD("YE", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
@@ -103,11 +105,11 @@ static const struct rtw89_regulatory rtw89_regd_map[] = {
COUNTRY_REGD("BD", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("KH", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("CN", RTW89_CN, RTW89_CN, RTW89_CN),
- COUNTRY_REGD("HK", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
+ COUNTRY_REGD("HK", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
COUNTRY_REGD("IN", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("ID", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("KR", RTW89_KCC, RTW89_KCC, RTW89_KCC),
- COUNTRY_REGD("MY", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
+ COUNTRY_REGD("MY", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
COUNTRY_REGD("PK", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("PH", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("SG", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
@@ -115,55 +117,55 @@ static const struct rtw89_regulatory rtw89_regd_map[] = {
COUNTRY_REGD("TW", RTW89_FCC, RTW89_FCC, RTW89_NA),
COUNTRY_REGD("TH", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("VN", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("AU", RTW89_ACMA, RTW89_ACMA, RTW89_NA),
- COUNTRY_REGD("NZ", RTW89_ACMA, RTW89_ACMA, RTW89_NA),
- COUNTRY_REGD("PG", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
+ COUNTRY_REGD("AU", RTW89_ACMA, RTW89_ACMA, RTW89_ACMA),
+ COUNTRY_REGD("NZ", RTW89_ACMA, RTW89_ACMA, RTW89_ACMA),
+ COUNTRY_REGD("PG", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
COUNTRY_REGD("CA", RTW89_IC, RTW89_IC, RTW89_IC),
- COUNTRY_REGD("JP", RTW89_MKK, RTW89_MKK, RTW89_NA),
- COUNTRY_REGD("JM", RTW89_FCC, RTW89_FCC, RTW89_NA),
- COUNTRY_REGD("AN", RTW89_FCC, RTW89_FCC, RTW89_NA),
+ COUNTRY_REGD("JP", RTW89_MKK, RTW89_MKK, RTW89_MKK),
+ COUNTRY_REGD("JM", RTW89_FCC, RTW89_FCC, RTW89_FCC),
+ COUNTRY_REGD("AN", RTW89_FCC, RTW89_FCC, RTW89_FCC),
COUNTRY_REGD("TT", RTW89_FCC, RTW89_FCC, RTW89_NA),
COUNTRY_REGD("TN", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("AF", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("DZ", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
+ COUNTRY_REGD("DZ", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
COUNTRY_REGD("AS", RTW89_FCC, RTW89_FCC, RTW89_NA),
COUNTRY_REGD("AD", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("AO", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("AI", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
+ COUNTRY_REGD("AI", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
COUNTRY_REGD("AQ", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("AG", RTW89_FCC, RTW89_FCC, RTW89_NA),
- COUNTRY_REGD("AM", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("AW", RTW89_FCC, RTW89_FCC, RTW89_NA),
- COUNTRY_REGD("BS", RTW89_FCC, RTW89_FCC, RTW89_NA),
- COUNTRY_REGD("BB", RTW89_FCC, RTW89_FCC, RTW89_NA),
+ COUNTRY_REGD("AG", RTW89_FCC, RTW89_FCC, RTW89_FCC),
+ COUNTRY_REGD("AM", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
+ COUNTRY_REGD("AW", RTW89_FCC, RTW89_FCC, RTW89_FCC),
+ COUNTRY_REGD("BS", RTW89_FCC, RTW89_FCC, RTW89_FCC),
+ COUNTRY_REGD("BB", RTW89_FCC, RTW89_FCC, RTW89_FCC),
COUNTRY_REGD("BY", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("BZ", RTW89_FCC, RTW89_FCC, RTW89_NA),
COUNTRY_REGD("BJ", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("BM", RTW89_FCC, RTW89_FCC, RTW89_NA),
+ COUNTRY_REGD("BM", RTW89_FCC, RTW89_FCC, RTW89_FCC),
COUNTRY_REGD("BT", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("BW", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
+ COUNTRY_REGD("BW", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
COUNTRY_REGD("BV", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("IO", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("VG", RTW89_FCC, RTW89_FCC, RTW89_NA),
+ COUNTRY_REGD("VG", RTW89_FCC, RTW89_FCC, RTW89_FCC),
COUNTRY_REGD("BN", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("BF", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("MM", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("BI", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
+ COUNTRY_REGD("BI", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
COUNTRY_REGD("CM", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("CV", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("KY", RTW89_FCC, RTW89_FCC, RTW89_NA),
+ COUNTRY_REGD("KY", RTW89_FCC, RTW89_FCC, RTW89_FCC),
COUNTRY_REGD("CF", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("TD", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
+ COUNTRY_REGD("TD", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
COUNTRY_REGD("CX", RTW89_ACMA, RTW89_ACMA, RTW89_NA),
- COUNTRY_REGD("CC", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("KM", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
+ COUNTRY_REGD("CC", RTW89_ACMA, RTW89_ACMA, RTW89_NA),
+ COUNTRY_REGD("KM", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
COUNTRY_REGD("CG", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("CD", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("CK", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("CI", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("DJ", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("DM", RTW89_FCC, RTW89_FCC, RTW89_NA),
- COUNTRY_REGD("GQ", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
+ COUNTRY_REGD("DJ", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
+ COUNTRY_REGD("DM", RTW89_FCC, RTW89_FCC, RTW89_FCC),
+ COUNTRY_REGD("GQ", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
COUNTRY_REGD("ER", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("ET", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("FK", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
@@ -173,17 +175,17 @@ static const struct rtw89_regulatory rtw89_regd_map[] = {
COUNTRY_REGD("PF", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("TF", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("GA", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("GM", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
+ COUNTRY_REGD("GM", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
COUNTRY_REGD("GE", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("GI", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("GL", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("GD", RTW89_FCC, RTW89_FCC, RTW89_NA),
+ COUNTRY_REGD("GD", RTW89_FCC, RTW89_FCC, RTW89_FCC),
COUNTRY_REGD("GP", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("GU", RTW89_FCC, RTW89_FCC, RTW89_NA),
COUNTRY_REGD("GG", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("GN", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
+ COUNTRY_REGD("GN", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
COUNTRY_REGD("GW", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("GY", RTW89_NCC, RTW89_NCC, RTW89_NA),
+ COUNTRY_REGD("GY", RTW89_FCC, RTW89_FCC, RTW89_FCC),
COUNTRY_REGD("HT", RTW89_FCC, RTW89_FCC, RTW89_NA),
COUNTRY_REGD("HM", RTW89_ACMA, RTW89_ACMA, RTW89_NA),
COUNTRY_REGD("VA", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
@@ -194,17 +196,17 @@ static const struct rtw89_regulatory rtw89_regd_map[] = {
COUNTRY_REGD("LR", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("LY", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("MO", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("MG", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
+ COUNTRY_REGD("MG", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
COUNTRY_REGD("MW", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("MV", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("ML", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("MH", RTW89_FCC, RTW89_FCC, RTW89_NA),
COUNTRY_REGD("MQ", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("MR", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("MU", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
+ COUNTRY_REGD("MU", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
COUNTRY_REGD("YT", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("FM", RTW89_FCC, RTW89_FCC, RTW89_NA),
- COUNTRY_REGD("MD", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
+ COUNTRY_REGD("MD", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
COUNTRY_REGD("MN", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("MS", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("NR", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
@@ -218,26 +220,26 @@ static const struct rtw89_regulatory rtw89_regd_map[] = {
COUNTRY_REGD("RE", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("RW", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("SH", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("KN", RTW89_FCC, RTW89_FCC, RTW89_NA),
- COUNTRY_REGD("LC", RTW89_FCC, RTW89_FCC, RTW89_NA),
+ COUNTRY_REGD("KN", RTW89_FCC, RTW89_FCC, RTW89_FCC),
+ COUNTRY_REGD("LC", RTW89_FCC, RTW89_FCC, RTW89_FCC),
COUNTRY_REGD("MF", RTW89_FCC, RTW89_FCC, RTW89_NA),
COUNTRY_REGD("SX", RTW89_FCC, RTW89_FCC, RTW89_NA),
COUNTRY_REGD("PM", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("VC", RTW89_FCC, RTW89_FCC, RTW89_NA),
COUNTRY_REGD("WS", RTW89_FCC, RTW89_FCC, RTW89_NA),
COUNTRY_REGD("SM", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("ST", RTW89_FCC, RTW89_FCC, RTW89_NA),
+ COUNTRY_REGD("ST", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("SC", RTW89_FCC, RTW89_FCC, RTW89_NA),
- COUNTRY_REGD("SL", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
+ COUNTRY_REGD("SL", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
COUNTRY_REGD("SB", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("SO", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("GS", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("SR", RTW89_FCC, RTW89_FCC, RTW89_NA),
+ COUNTRY_REGD("SR", RTW89_FCC, RTW89_FCC, RTW89_FCC),
COUNTRY_REGD("SJ", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("SZ", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("TJ", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
+ COUNTRY_REGD("TJ", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
COUNTRY_REGD("TZ", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
- COUNTRY_REGD("TG", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
+ COUNTRY_REGD("TG", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
COUNTRY_REGD("TK", RTW89_ACMA, RTW89_ACMA, RTW89_NA),
COUNTRY_REGD("TO", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("TM", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
@@ -245,7 +247,7 @@ static const struct rtw89_regulatory rtw89_regd_map[] = {
COUNTRY_REGD("TV", RTW89_ETSI, RTW89_NA, RTW89_NA),
COUNTRY_REGD("UG", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("VI", RTW89_FCC, RTW89_FCC, RTW89_NA),
- COUNTRY_REGD("UZ", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
+ COUNTRY_REGD("UZ", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI),
COUNTRY_REGD("VU", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("WF", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
COUNTRY_REGD("EH", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
@@ -254,7 +256,7 @@ static const struct rtw89_regulatory rtw89_regd_map[] = {
COUNTRY_REGD("PS", RTW89_ETSI, RTW89_ETSI, RTW89_NA),
};
-static const struct rtw89_regulatory *rtw89_regd_find_reg_by_name(char *alpha2)
+static const struct rtw89_regd *rtw89_regd_find_reg_by_name(char *alpha2)
{
u32 i;
@@ -266,7 +268,7 @@ static const struct rtw89_regulatory *rtw89_regd_find_reg_by_name(char *alpha2)
return &rtw89_ww_regd;
}
-static bool rtw89_regd_is_ww(const struct rtw89_regulatory *regd)
+static bool rtw89_regd_is_ww(const struct rtw89_regd *regd)
{
return regd == &rtw89_ww_regd;
}
@@ -282,25 +284,139 @@ do { \
__r->txpwr_regd[RTW89_BAND_6G]); \
} while (0)
+static void rtw89_regd_setup_unii4(struct rtw89_dev *rtwdev,
+ struct wiphy *wiphy)
+{
+ const struct rtw89_chip_info *chip = rtwdev->chip;
+ bool regd_allow_unii_4 = chip->support_unii4;
+ struct ieee80211_supported_band *sband;
+ int ret;
+ u8 val;
+
+ if (!chip->support_unii4)
+ goto bottom;
+
+ ret = rtw89_acpi_evaluate_dsm(rtwdev, RTW89_ACPI_DSM_FUNC_59G_EN, &val);
+ if (ret) {
+ rtw89_debug(rtwdev, RTW89_DBG_REGD,
+ "acpi: cannot eval unii 4: %d\n", ret);
+ goto bottom;
+ }
+
+ rtw89_debug(rtwdev, RTW89_DBG_REGD,
+ "acpi: eval if allow unii 4: %d\n", val);
+
+ switch (val) {
+ case 0:
+ regd_allow_unii_4 = false;
+ break;
+ case 1:
+ regd_allow_unii_4 = true;
+ break;
+ default:
+ break;
+ }
+
+bottom:
+ rtw89_debug(rtwdev, RTW89_DBG_REGD, "regd: allow unii 4: %d\n",
+ regd_allow_unii_4);
+
+ if (regd_allow_unii_4)
+ return;
+
+ sband = wiphy->bands[NL80211_BAND_5GHZ];
+ if (!sband)
+ return;
+
+ sband->n_channels -= 3;
+}
+
+static void rtw89_regd_setup_6ghz(struct rtw89_dev *rtwdev, struct wiphy *wiphy)
+{
+ const struct rtw89_chip_info *chip = rtwdev->chip;
+ bool chip_support_6ghz = chip->support_bands & BIT(NL80211_BAND_6GHZ);
+ bool regd_allow_6ghz = chip_support_6ghz;
+ struct ieee80211_supported_band *sband;
+ int ret;
+ u8 val;
+
+ if (!chip_support_6ghz)
+ goto bottom;
+
+ ret = rtw89_acpi_evaluate_dsm(rtwdev, RTW89_ACPI_DSM_FUNC_6G_DIS, &val);
+ if (ret) {
+ rtw89_debug(rtwdev, RTW89_DBG_REGD,
+ "acpi: cannot eval 6ghz: %d\n", ret);
+ goto bottom;
+ }
+
+ rtw89_debug(rtwdev, RTW89_DBG_REGD,
+ "acpi: eval if disallow 6ghz: %d\n", val);
+
+ switch (val) {
+ case 0:
+ regd_allow_6ghz = true;
+ break;
+ case 1:
+ regd_allow_6ghz = false;
+ break;
+ default:
+ break;
+ }
+
+bottom:
+ rtw89_debug(rtwdev, RTW89_DBG_REGD, "regd: allow 6ghz: %d\n",
+ regd_allow_6ghz);
+
+ if (regd_allow_6ghz)
+ return;
+
+ sband = wiphy->bands[NL80211_BAND_6GHZ];
+ if (!sband)
+ return;
+
+ wiphy->bands[NL80211_BAND_6GHZ] = NULL;
+ kfree(sband->iftype_data);
+ kfree(sband);
+}
+
+int rtw89_regd_setup(struct rtw89_dev *rtwdev)
+{
+ struct wiphy *wiphy = rtwdev->hw->wiphy;
+
+ if (!wiphy)
+ return -EINVAL;
+
+ rtw89_regd_setup_unii4(rtwdev, wiphy);
+ rtw89_regd_setup_6ghz(rtwdev, wiphy);
+
+ wiphy->reg_notifier = rtw89_regd_notifier;
+ return 0;
+}
+
int rtw89_regd_init(struct rtw89_dev *rtwdev,
void (*reg_notifier)(struct wiphy *wiphy,
struct regulatory_request *request))
{
- const struct rtw89_regulatory *chip_regd;
+ struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
+ const struct rtw89_regd *chip_regd;
struct wiphy *wiphy = rtwdev->hw->wiphy;
int ret;
+ regulatory->reg_6ghz_power = RTW89_REG_6GHZ_POWER_DFLT;
+
if (!wiphy)
return -EINVAL;
chip_regd = rtw89_regd_find_reg_by_name(rtwdev->efuse.country_code);
if (!rtw89_regd_is_ww(chip_regd)) {
- rtwdev->regd = chip_regd;
+ rtwdev->regulatory.regd = chip_regd;
/* Ignore country ie if there is a country domain programmed in chip */
wiphy->regulatory_flags |= REGULATORY_COUNTRY_IE_IGNORE;
wiphy->regulatory_flags |= REGULATORY_STRICT_REG;
- ret = regulatory_hint(rtwdev->hw->wiphy, rtwdev->regd->alpha2);
+ ret = regulatory_hint(rtwdev->hw->wiphy,
+ rtwdev->regulatory.regd->alpha2);
if (ret)
rtw89_warn(rtwdev, "failed to hint regulatory:%d\n", ret);
@@ -308,7 +424,7 @@ int rtw89_regd_init(struct rtw89_dev *rtwdev,
return 0;
}
- rtw89_debug_regd(rtwdev, rtwdev->regd,
+ rtw89_debug_regd(rtwdev, rtwdev->regulatory.regd,
"worldwide roaming chip, follow the setting of stack");
return 0;
}
@@ -317,13 +433,13 @@ static void rtw89_regd_notifier_apply(struct rtw89_dev *rtwdev,
struct wiphy *wiphy,
struct regulatory_request *request)
{
- rtwdev->regd = rtw89_regd_find_reg_by_name(request->alpha2);
+ rtwdev->regulatory.regd = rtw89_regd_find_reg_by_name(request->alpha2);
/* This notification might be set from the system of distros,
* and it does not expect the regulatory will be modified by
* connecting to an AP (i.e. country ie).
*/
if (request->initiator == NL80211_REGDOM_SET_BY_USER &&
- !rtw89_regd_is_ww(rtwdev->regd))
+ !rtw89_regd_is_ww(rtwdev->regulatory.regd))
wiphy->regulatory_flags |= REGULATORY_COUNTRY_IE_IGNORE;
else
wiphy->regulatory_flags &= ~REGULATORY_COUNTRY_IE_IGNORE;
@@ -343,7 +459,8 @@ void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request
goto exit;
}
rtw89_regd_notifier_apply(rtwdev, wiphy, request);
- rtw89_debug_regd(rtwdev, rtwdev->regd, "get from initiator %d, alpha2",
+ rtw89_debug_regd(rtwdev, rtwdev->regulatory.regd,
+ "get from initiator %d, alpha2",
request->initiator);
rtw89_core_set_chip_txpwr(rtwdev);
@@ -351,3 +468,66 @@ void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request
exit:
mutex_unlock(&rtwdev->mutex);
}
+
+static void __rtw89_reg_6ghz_power_recalc(struct rtw89_dev *rtwdev)
+{
+ struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
+ enum rtw89_reg_6ghz_power sel;
+ const struct rtw89_chan *chan;
+ struct rtw89_vif *rtwvif;
+ int count = 0;
+
+ rtw89_for_each_rtwvif(rtwdev, rtwvif) {
+ chan = rtw89_chan_get(rtwdev, rtwvif->sub_entity_idx);
+ if (chan->band_type != RTW89_BAND_6G)
+ continue;
+
+ if (count != 0 && rtwvif->reg_6ghz_power == sel)
+ continue;
+
+ sel = rtwvif->reg_6ghz_power;
+ count++;
+ }
+
+ if (count != 1)
+ sel = RTW89_REG_6GHZ_POWER_DFLT;
+
+ if (regulatory->reg_6ghz_power == sel)
+ return;
+
+ rtw89_debug(rtwdev, RTW89_DBG_REGD,
+ "recalc 6 GHz reg power type to %d\n", sel);
+
+ regulatory->reg_6ghz_power = sel;
+
+ rtw89_core_set_chip_txpwr(rtwdev);
+}
+
+void rtw89_reg_6ghz_power_recalc(struct rtw89_dev *rtwdev,
+ struct rtw89_vif *rtwvif, bool active)
+{
+ struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
+
+ lockdep_assert_held(&rtwdev->mutex);
+
+ if (active) {
+ switch (vif->bss_conf.power_type) {
+ case IEEE80211_REG_VLP_AP:
+ rtwvif->reg_6ghz_power = RTW89_REG_6GHZ_POWER_VLP;
+ break;
+ case IEEE80211_REG_LPI_AP:
+ rtwvif->reg_6ghz_power = RTW89_REG_6GHZ_POWER_LPI;
+ break;
+ case IEEE80211_REG_SP_AP:
+ rtwvif->reg_6ghz_power = RTW89_REG_6GHZ_POWER_STD;
+ break;
+ default:
+ rtwvif->reg_6ghz_power = RTW89_REG_6GHZ_POWER_DFLT;
+ break;
+ }
+ } else {
+ rtwvif->reg_6ghz_power = RTW89_REG_6GHZ_POWER_DFLT;
+ }
+
+ __rtw89_reg_6ghz_power_recalc(rtwdev);
+}
diff --git a/drivers/net/wireless/realtek/rtw89/rtw8851b.c b/drivers/net/wireless/realtek/rtw89/rtw8851b.c
new file mode 100644
index 000000000000..c3ffcb645ebf
--- /dev/null
+++ b/drivers/net/wireless/realtek/rtw89/rtw8851b.c
@@ -0,0 +1,2442 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/* Copyright(c) 2022-2023 Realtek Corporation
+ */
+
+#include "coex.h"
+#include "efuse.h"
+#include "fw.h"
+#include "mac.h"
+#include "phy.h"
+#include "reg.h"
+#include "rtw8851b.h"
+#include "rtw8851b_rfk.h"
+#include "rtw8851b_rfk_table.h"
+#include "rtw8851b_table.h"
+#include "txrx.h"
+#include "util.h"
+
+#define RTW8851B_FW_FORMAT_MAX 0
+#define RTW8851B_FW_BASENAME "rtw89/rtw8851b_fw"
+#define RTW8851B_MODULE_FIRMWARE \
+ RTW8851B_FW_BASENAME ".bin"
+
+static const struct rtw89_hfc_ch_cfg rtw8851b_hfc_chcfg_pcie[] = {
+ {5, 343, grp_0}, /* ACH 0 */
+ {5, 343, grp_0}, /* ACH 1 */
+ {5, 343, grp_0}, /* ACH 2 */
+ {5, 343, grp_0}, /* ACH 3 */
+ {0, 0, grp_0}, /* ACH 4 */
+ {0, 0, grp_0}, /* ACH 5 */
+ {0, 0, grp_0}, /* ACH 6 */
+ {0, 0, grp_0}, /* ACH 7 */
+ {4, 344, grp_0}, /* B0MGQ */
+ {4, 344, grp_0}, /* B0HIQ */
+ {0, 0, grp_0}, /* B1MGQ */
+ {0, 0, grp_0}, /* B1HIQ */
+ {40, 0, 0} /* FWCMDQ */
+};
+
+static const struct rtw89_hfc_pub_cfg rtw8851b_hfc_pubcfg_pcie = {
+ 448, /* Group 0 */
+ 0, /* Group 1 */
+ 448, /* Public Max */
+ 0 /* WP threshold */
+};
+
+static const struct rtw89_hfc_param_ini rtw8851b_hfc_param_ini_pcie[] = {
+ [RTW89_QTA_SCC] = {rtw8851b_hfc_chcfg_pcie, &rtw8851b_hfc_pubcfg_pcie,
+ &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH},
+ [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie,
+ RTW89_HCIFC_POH},
+ [RTW89_QTA_INVALID] = {NULL},
+};
+
+static const struct rtw89_dle_mem rtw8851b_dle_mem_pcie[] = {
+ [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size6,
+ &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt6,
+ &rtw89_mac_size.wde_qt6, &rtw89_mac_size.ple_qt18,
+ &rtw89_mac_size.ple_qt58},
+ [RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size6,
+ &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt6,
+ &rtw89_mac_size.wde_qt6, &rtw89_mac_size.ple_qt18,
+ &rtw89_mac_size.ple_qt_51b_wow},
+ [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9,
+ &rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4,
+ &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
+ &rtw89_mac_size.ple_qt13},
+ [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
+ NULL},
+};
+
+static const struct rtw89_reg3_def rtw8851b_btc_preagc_en_defs[] = {
+ {0x46D0, GENMASK(1, 0), 0x3},
+ {0x4AD4, GENMASK(31, 0), 0xf},
+ {0x4688, GENMASK(23, 16), 0x80},
+ {0x4688, GENMASK(31, 24), 0x80},
+ {0x4694, GENMASK(7, 0), 0x80},
+ {0x4694, GENMASK(15, 8), 0x80},
+ {0x4AE4, GENMASK(11, 6), 0x34},
+ {0x4AE4, GENMASK(17, 12), 0x0},
+ {0x469C, GENMASK(31, 26), 0x34},
+};
+
+static DECLARE_PHY_REG3_TBL(rtw8851b_btc_preagc_en_defs);
+
+static const struct rtw89_reg3_def rtw8851b_btc_preagc_dis_defs[] = {
+ {0x46D0, GENMASK(1, 0), 0x0},
+ {0x4AD4, GENMASK(31, 0), 0x60},
+ {0x4688, GENMASK(23, 16), 0x10},
+ {0x4690, GENMASK(31, 24), 0x2a},
+ {0x4694, GENMASK(15, 8), 0x2a},
+ {0x4AE4, GENMASK(11, 6), 0x26},
+ {0x4AE4, GENMASK(17, 12), 0x1e},
+ {0x469C, GENMASK(31, 26), 0x26},
+};
+
+static DECLARE_PHY_REG3_TBL(rtw8851b_btc_preagc_dis_defs);
+
+static const u32 rtw8851b_h2c_regs[RTW89_H2CREG_MAX] = {
+ R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2,
+ R_AX_H2CREG_DATA3
+};
+
+static const u32 rtw8851b_c2h_regs[RTW89_C2HREG_MAX] = {
+ R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2,
+ R_AX_C2HREG_DATA3
+};
+
+static const struct rtw89_page_regs rtw8851b_page_regs = {
+ .hci_fc_ctrl = R_AX_HCI_FC_CTRL,
+ .ch_page_ctrl = R_AX_CH_PAGE_CTRL,
+ .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL,
+ .ach_page_info = R_AX_ACH0_PAGE_INFO,
+ .pub_page_info3 = R_AX_PUB_PAGE_INFO3,
+ .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1,
+ .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2,
+ .pub_page_info1 = R_AX_PUB_PAGE_INFO1,
+ .pub_page_info2 = R_AX_PUB_PAGE_INFO2,
+ .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1,
+ .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2,
+ .wp_page_info1 = R_AX_WP_PAGE_INFO1,
+};
+
+static const struct rtw89_reg_def rtw8851b_dcfo_comp = {
+ R_DCFO_COMP_S0_V2, B_DCFO_COMP_S0_MSK_V2
+};
+
+static const struct rtw89_imr_info rtw8851b_imr_info = {
+ .wdrls_imr_set = B_AX_WDRLS_IMR_SET,
+ .wsec_imr_reg = R_AX_SEC_DEBUG,
+ .wsec_imr_set = B_AX_IMR_ERROR,
+ .mpdu_tx_imr_set = 0,
+ .mpdu_rx_imr_set = 0,
+ .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET,
+ .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR,
+ .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR,
+ .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET,
+ .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1,
+ .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR,
+ .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET,
+ .wde_imr_clr = B_AX_WDE_IMR_CLR,
+ .wde_imr_set = B_AX_WDE_IMR_SET,
+ .ple_imr_clr = B_AX_PLE_IMR_CLR,
+ .ple_imr_set = B_AX_PLE_IMR_SET,
+ .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR,
+ .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET,
+ .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR,
+ .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET,
+ .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR,
+ .other_disp_imr_set = 0,
+ .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR_ISR,
+ .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR,
+ .bbrpt_err_imr_set = 0,
+ .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR,
+ .ptcl_imr_clr = B_AX_PTCL_IMR_CLR_ALL,
+ .ptcl_imr_set = B_AX_PTCL_IMR_SET,
+ .cdma_imr_0_reg = R_AX_DLE_CTRL,
+ .cdma_imr_0_clr = B_AX_DLE_IMR_CLR,
+ .cdma_imr_0_set = B_AX_DLE_IMR_SET,
+ .cdma_imr_1_reg = 0,
+ .cdma_imr_1_clr = 0,
+ .cdma_imr_1_set = 0,
+ .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR,
+ .phy_intf_imr_clr = 0,
+ .phy_intf_imr_set = 0,
+ .rmac_imr_reg = R_AX_RMAC_ERR_ISR,
+ .rmac_imr_clr = B_AX_RMAC_IMR_CLR,
+ .rmac_imr_set = B_AX_RMAC_IMR_SET,
+ .tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR,
+ .tmac_imr_clr = B_AX_TMAC_IMR_CLR,
+ .tmac_imr_set = B_AX_TMAC_IMR_SET,
+};
+
+static const struct rtw89_xtal_info rtw8851b_xtal_info = {
+ .xcap_reg = R_AX_XTAL_ON_CTRL3,
+ .sc_xo_mask = B_AX_XTAL_SC_XO_A_BLOCK_MASK,
+ .sc_xi_mask = B_AX_XTAL_SC_XI_A_BLOCK_MASK,
+};
+
+static const struct rtw89_rrsr_cfgs rtw8851b_rrsr_cfgs = {
+ .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0},
+ .rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2},
+};
+
+static const struct rtw89_dig_regs rtw8851b_dig_regs = {
+ .seg0_pd_reg = R_SEG0R_PD_V1,
+ .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
+ .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1,
+ .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK},
+ .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK},
+ .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1},
+ .p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1},
+ .p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1},
+ .p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1},
+ .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V2,
+ B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
+ .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V2,
+ B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
+ .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V2,
+ B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
+ .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V2,
+ B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
+};
+
+static const struct rtw89_btc_rf_trx_para rtw89_btc_8851b_rf_ul[] = {
+ {255, 0, 0, 7}, /* 0 -> original */
+ {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
+ {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
+ {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
+ {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
+ {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
+ {6, 1, 0, 7},
+ {13, 1, 0, 7},
+ {13, 1, 0, 7}
+};
+
+static const struct rtw89_btc_rf_trx_para rtw89_btc_8851b_rf_dl[] = {
+ {255, 0, 0, 7}, /* 0 -> original */
+ {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */
+ {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
+ {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
+ {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
+ {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
+ {255, 1, 0, 7},
+ {255, 1, 0, 7},
+ {255, 1, 0, 7}
+};
+
+static const struct rtw89_btc_fbtc_mreg rtw89_btc_8851b_mon_reg[] = {
+ RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24),
+ RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28),
+ RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c),
+ RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30),
+ RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c),
+ RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10),
+ RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20),
+ RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34),
+ RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4),
+ RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424),
+ RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200),
+ RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220),
+ RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980),
+ RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4738),
+ RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4688),
+ RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4694),
+};
+
+static const u8 rtw89_btc_8851b_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {70, 60, 50, 40};
+static const u8 rtw89_btc_8851b_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {50, 40, 30, 20};
+
+static int rtw8851b_pwr_on_func(struct rtw89_dev *rtwdev)
+{
+ u32 val32;
+ u8 val8;
+ u32 ret;
+
+ rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN |
+ B_AX_AFSM_PCIE_SUS_EN);
+ rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC);
+ rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC);
+ rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN);
+ rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
+
+ ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR,
+ 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
+ if (ret)
+ return ret;
+
+ rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
+ rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC);
+
+ ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC),
+ 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
+ if (ret)
+ return ret;
+
+ rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
+ rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
+ rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
+ rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
+
+ rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
+ rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1);
+
+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI,
+ XTAL_SI_OFF_WEI);
+ if (ret)
+ return ret;
+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI,
+ XTAL_SI_OFF_EI);
+ if (ret)
+ return ret;
+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF);
+ if (ret)
+ return ret;
+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI,
+ XTAL_SI_PON_WEI);
+ if (ret)
+ return ret;
+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI,
+ XTAL_SI_PON_EI);
+ if (ret)
+ return ret;
+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC);
+ if (ret)
+ return ret;
+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_SRAM_CTRL, 0, XTAL_SI_SRAM_DIS);
+ if (ret)
+ return ret;
+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS);
+ if (ret)
+ return ret;
+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP);
+ if (ret)
+ return ret;
+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_DRV, 0, XTAL_SI_DRV_LATCH);
+ if (ret)
+ return ret;
+
+ rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
+ rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE);
+ rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15);
+
+ fsleep(1000);
+
+ rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14);
+ rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
+ rtw89_write32_set(rtwdev, R_AX_GPIO0_16_EECS_EESK_LED1_PULL_LOW_EN,
+ B_AX_GPIO10_PULL_LOW_EN | B_AX_GPIO16_PULL_LOW_EN_V1);
+
+ if (rtwdev->hal.cv == CHIP_CAV) {
+ ret = rtw89_read_efuse_ver(rtwdev, &val8);
+ if (!ret)
+ rtwdev->hal.cv = val8;
+ }
+
+ rtw89_write32_clr(rtwdev, R_AX_WLAN_XTAL_SI_CONFIG,
+ B_AX_XTAL_SI_ADDR_NOT_CHK);
+ if (rtwdev->hal.cv != CHIP_CAV) {
+ rtw89_write32_set(rtwdev, R_AX_SPSLDO_ON_CTRL1, B_AX_FPWMDELAY);
+ rtw89_write32_set(rtwdev, R_AX_SPSANA_ON_CTRL1, B_AX_FPWMDELAY);
+ }
+
+ rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN,
+ B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN |
+ B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN |
+ B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN |
+ B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN |
+ B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN |
+ B_AX_DMACREG_GCKEN);
+ rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN,
+ B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN |
+ B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN |
+ B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN | B_AX_TMAC_EN |
+ B_AX_RMAC_EN);
+
+ rtw89_write32_mask(rtwdev, R_AX_EECS_EESK_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_MASK,
+ PINMUX_EESK_FUNC_SEL_BT_LOG);
+
+ return 0;
+}
+
+static void rtw8851b_patch_swr_pfm2pwm(struct rtw89_dev *rtwdev)
+{
+ rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_SOP_PWMM_DSWR);
+ rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_SOP_ASWRM);
+ rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_LPSOP_DSWRM);
+ rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_LPSOP_ASWRM);
+}
+
+static int rtw8851b_pwr_off_func(struct rtw89_dev *rtwdev)
+{
+ u32 val32;
+ u32 ret;
+
+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF,
+ XTAL_SI_RFC2RF);
+ if (ret)
+ return ret;
+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI);
+ if (ret)
+ return ret;
+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI);
+ if (ret)
+ return ret;
+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00);
+ if (ret)
+ return ret;
+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC,
+ XTAL_SI_SRAM2RFC);
+ if (ret)
+ return ret;
+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI);
+ if (ret)
+ return ret;
+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI);
+ if (ret)
+ return ret;
+
+ rtw89_write32_set(rtwdev, R_AX_WLAN_XTAL_SI_CONFIG,
+ B_AX_XTAL_SI_ADDR_NOT_CHK);
+ rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
+ rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
+ rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB);
+
+ rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC);
+
+ ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC),
+ 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
+ if (ret)
+ return ret;
+
+ rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION);
+
+ if (rtwdev->hal.cv == CHIP_CAV) {
+ rtw8851b_patch_swr_pfm2pwm(rtwdev);
+ } else {
+ rtw89_write32_set(rtwdev, R_AX_SPSLDO_ON_CTRL1, B_AX_FPWMDELAY);
+ rtw89_write32_set(rtwdev, R_AX_SPSANA_ON_CTRL1, B_AX_FPWMDELAY);
+ }
+
+ rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
+
+ return 0;
+}
+
+static void rtw8851b_efuse_parsing(struct rtw89_efuse *efuse,
+ struct rtw8851b_efuse *map)
+{
+ ether_addr_copy(efuse->addr, map->e.mac_addr);
+ efuse->rfe_type = map->rfe_type;
+ efuse->xtal_cap = map->xtal_k;
+}
+
+static void rtw8851b_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
+ struct rtw8851b_efuse *map)
+{
+ struct rtw89_tssi_info *tssi = &rtwdev->tssi;
+ struct rtw8851b_tssi_offset *ofst[] = {&map->path_a_tssi};
+ u8 i, j;
+
+ tssi->thermal[RF_PATH_A] = map->path_a_therm;
+
+ for (i = 0; i < RF_PATH_NUM_8851B; i++) {
+ memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi,
+ sizeof(ofst[i]->cck_tssi));
+
+ for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++)
+ rtw89_debug(rtwdev, RTW89_DBG_TSSI,
+ "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n",
+ i, j, tssi->tssi_cck[i][j]);
+
+ memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi,
+ sizeof(ofst[i]->bw40_tssi));
+ memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM,
+ ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g));
+
+ for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++)
+ rtw89_debug(rtwdev, RTW89_DBG_TSSI,
+ "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n",
+ i, j, tssi->tssi_mcs[i][j]);
+ }
+}
+
+static bool _decode_efuse_gain(u8 data, s8 *high, s8 *low)
+{
+ if (high)
+ *high = sign_extend32(u8_get_bits(data, GENMASK(7, 4)), 3);
+ if (low)
+ *low = sign_extend32(u8_get_bits(data, GENMASK(3, 0)), 3);
+
+ return data != 0xff;
+}
+
+static void rtw8851b_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev,
+ struct rtw8851b_efuse *map)
+{
+ struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
+ bool valid = false;
+
+ valid |= _decode_efuse_gain(map->rx_gain_2g_cck,
+ &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK],
+ NULL);
+ valid |= _decode_efuse_gain(map->rx_gain_2g_ofdm,
+ &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM],
+ NULL);
+ valid |= _decode_efuse_gain(map->rx_gain_5g_low,
+ &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW],
+ NULL);
+ valid |= _decode_efuse_gain(map->rx_gain_5g_mid,
+ &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID],
+ NULL);
+ valid |= _decode_efuse_gain(map->rx_gain_5g_high,
+ &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH],
+ NULL);
+
+ gain->offset_valid = valid;
+}
+
+static int rtw8851b_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map)
+{
+ struct rtw89_efuse *efuse = &rtwdev->efuse;
+ struct rtw8851b_efuse *map;
+
+ map = (struct rtw8851b_efuse *)log_map;
+
+ efuse->country_code[0] = map->country_code[0];
+ efuse->country_code[1] = map->country_code[1];
+ rtw8851b_efuse_parsing_tssi(rtwdev, map);
+ rtw8851b_efuse_parsing_gain_offset(rtwdev, map);
+
+ switch (rtwdev->hci.type) {
+ case RTW89_HCI_TYPE_PCIE:
+ rtw8851b_efuse_parsing(efuse, map);
+ break;
+ default:
+ return -EOPNOTSUPP;
+ }
+
+ rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
+
+ return 0;
+}
+
+static void rtw8851b_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map)
+{
+ struct rtw89_tssi_info *tssi = &rtwdev->tssi;
+ static const u32 tssi_trim_addr[RF_PATH_NUM_8851B] = {0x5D6};
+ u32 addr = rtwdev->chip->phycap_addr;
+ bool pg = false;
+ u32 ofst;
+ u8 i, j;
+
+ for (i = 0; i < RF_PATH_NUM_8851B; i++) {
+ for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) {
+ /* addrs are in decreasing order */
+ ofst = tssi_trim_addr[i] - addr - j;
+ tssi->tssi_trim[i][j] = phycap_map[ofst];
+
+ if (phycap_map[ofst] != 0xff)
+ pg = true;
+ }
+ }
+
+ if (!pg) {
+ memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim));
+ rtw89_debug(rtwdev, RTW89_DBG_TSSI,
+ "[TSSI][TRIM] no PG, set all trim info to 0\n");
+ }
+
+ for (i = 0; i < RF_PATH_NUM_8851B; i++)
+ for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++)
+ rtw89_debug(rtwdev, RTW89_DBG_TSSI,
+ "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n",
+ i, j, tssi->tssi_trim[i][j],
+ tssi_trim_addr[i] - j);
+}
+
+static void rtw8851b_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
+ u8 *phycap_map)
+{
+ struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
+ static const u32 thm_trim_addr[RF_PATH_NUM_8851B] = {0x5DF};
+ u32 addr = rtwdev->chip->phycap_addr;
+ u8 i;
+
+ for (i = 0; i < RF_PATH_NUM_8851B; i++) {
+ info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr];
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n",
+ i, info->thermal_trim[i]);
+
+ if (info->thermal_trim[i] != 0xff)
+ info->pg_thermal_trim = true;
+ }
+}
+
+static void rtw8851b_thermal_trim(struct rtw89_dev *rtwdev)
+{
+#define __thm_setting(raw) \
+({ \
+ u8 __v = (raw); \
+ ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \
+})
+ struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
+ u8 i, val;
+
+ if (!info->pg_thermal_trim) {
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[THERMAL][TRIM] no PG, do nothing\n");
+
+ return;
+ }
+
+ for (i = 0; i < RF_PATH_NUM_8851B; i++) {
+ val = __thm_setting(info->thermal_trim[i]);
+ rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n",
+ i, val);
+ }
+#undef __thm_setting
+}
+
+static void rtw8851b_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
+ u8 *phycap_map)
+{
+ struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
+ static const u32 pabias_trim_addr[] = {0x5DE};
+ u32 addr = rtwdev->chip->phycap_addr;
+ u8 i;
+
+ for (i = 0; i < RF_PATH_NUM_8851B; i++) {
+ info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr];
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n",
+ i, info->pa_bias_trim[i]);
+
+ if (info->pa_bias_trim[i] != 0xff)
+ info->pg_pa_bias_trim = true;
+ }
+}
+
+static void rtw8851b_pa_bias_trim(struct rtw89_dev *rtwdev)
+{
+ struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
+ u8 pabias_2g, pabias_5g;
+ u8 i;
+
+ if (!info->pg_pa_bias_trim) {
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[PA_BIAS][TRIM] no PG, do nothing\n");
+
+ return;
+ }
+
+ for (i = 0; i < RF_PATH_NUM_8851B; i++) {
+ pabias_2g = u8_get_bits(info->pa_bias_trim[i], GENMASK(3, 0));
+ pabias_5g = u8_get_bits(info->pa_bias_trim[i], GENMASK(7, 4));
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
+ i, pabias_2g, pabias_5g);
+
+ rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g);
+ rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g);
+ }
+}
+
+static void rtw8851b_phycap_parsing_gain_comp(struct rtw89_dev *rtwdev, u8 *phycap_map)
+{
+ static const u32 comp_addrs[][RTW89_SUBBAND_2GHZ_5GHZ_NR] = {
+ {0x5BB, 0x5BA, 0, 0x5B9, 0x5B8},
+ };
+ struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
+ u32 phycap_addr = rtwdev->chip->phycap_addr;
+ bool valid = false;
+ int path, i;
+ u8 data;
+
+ for (path = 0; path < BB_PATH_NUM_8851B; path++)
+ for (i = 0; i < RTW89_SUBBAND_2GHZ_5GHZ_NR; i++) {
+ if (comp_addrs[path][i] == 0)
+ continue;
+
+ data = phycap_map[comp_addrs[path][i] - phycap_addr];
+ valid |= _decode_efuse_gain(data, NULL,
+ &gain->comp[path][i]);
+ }
+
+ gain->comp_valid = valid;
+}
+
+static int rtw8851b_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
+{
+ rtw8851b_phycap_parsing_tssi(rtwdev, phycap_map);
+ rtw8851b_phycap_parsing_thermal_trim(rtwdev, phycap_map);
+ rtw8851b_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
+ rtw8851b_phycap_parsing_gain_comp(rtwdev, phycap_map);
+
+ return 0;
+}
+
+static void rtw8851b_set_bb_gpio(struct rtw89_dev *rtwdev, u8 gpio_idx, bool inv,
+ u8 src_sel)
+{
+ u32 addr, mask;
+
+ if (gpio_idx >= 32)
+ return;
+
+ /* 2 continual 32-bit registers for 32 GPIOs, and each GPIO occupies 2 bits */
+ addr = R_RFE_SEL0_A2 + (gpio_idx / 16) * sizeof(u32);
+ mask = B_RFE_SEL0_MASK << (gpio_idx % 16) * 2;
+
+ rtw89_phy_write32_mask(rtwdev, addr, mask, RF_PATH_A);
+ rtw89_phy_write32_mask(rtwdev, R_RFE_INV0, BIT(gpio_idx), inv);
+
+ /* 4 continual 32-bit registers for 32 GPIOs, and each GPIO occupies 4 bits */
+ addr = R_RFE_SEL0_BASE + (gpio_idx / 8) * sizeof(u32);
+ mask = B_RFE_SEL0_SRC_MASK << (gpio_idx % 8) * 4;
+
+ rtw89_phy_write32_mask(rtwdev, addr, mask, src_sel);
+}
+
+static void rtw8851b_set_mac_gpio(struct rtw89_dev *rtwdev, u8 func)
+{
+ static const struct rtw89_reg3_def func16 = {
+ R_AX_GPIO16_23_FUNC_SEL, B_AX_PINMUX_GPIO16_FUNC_SEL_MASK, BIT(3)
+ };
+ static const struct rtw89_reg3_def func17 = {
+ R_AX_GPIO16_23_FUNC_SEL, B_AX_PINMUX_GPIO17_FUNC_SEL_MASK, BIT(7) >> 4,
+ };
+ const struct rtw89_reg3_def *def;
+
+ switch (func) {
+ case 16:
+ def = &func16;
+ break;
+ case 17:
+ def = &func17;
+ break;
+ default:
+ rtw89_warn(rtwdev, "undefined gpio func %d\n", func);
+ return;
+ }
+
+ rtw89_write8_mask(rtwdev, def->addr, def->mask, def->data);
+}
+
+static void rtw8851b_rfe_gpio(struct rtw89_dev *rtwdev)
+{
+ u8 rfe_type = rtwdev->efuse.rfe_type;
+
+ if (rfe_type > 50)
+ return;
+
+ if (rfe_type % 3 == 2) {
+ rtw8851b_set_bb_gpio(rtwdev, 16, true, RFE_SEL0_SRC_ANTSEL_0);
+ rtw8851b_set_bb_gpio(rtwdev, 17, false, RFE_SEL0_SRC_ANTSEL_0);
+
+ rtw8851b_set_mac_gpio(rtwdev, 16);
+ rtw8851b_set_mac_gpio(rtwdev, 17);
+ }
+}
+
+static void rtw8851b_power_trim(struct rtw89_dev *rtwdev)
+{
+ rtw8851b_thermal_trim(rtwdev);
+ rtw8851b_pa_bias_trim(rtwdev);
+}
+
+static void rtw8851b_set_channel_mac(struct rtw89_dev *rtwdev,
+ const struct rtw89_chan *chan,
+ u8 mac_idx)
+{
+ u32 sub_carr = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, mac_idx);
+ u32 chk_rate = rtw89_mac_reg_by_idx(R_AX_TXRATE_CHK, mac_idx);
+ u32 rf_mod = rtw89_mac_reg_by_idx(R_AX_WMAC_RFMOD, mac_idx);
+ u8 txsc20 = 0, txsc40 = 0;
+
+ switch (chan->band_width) {
+ case RTW89_CHANNEL_WIDTH_80:
+ txsc40 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_40);
+ fallthrough;
+ case RTW89_CHANNEL_WIDTH_40:
+ txsc20 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_20);
+ break;
+ default:
+ break;
+ }
+
+ switch (chan->band_width) {
+ case RTW89_CHANNEL_WIDTH_80:
+ rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1));
+ rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4));
+ break;
+ case RTW89_CHANNEL_WIDTH_40:
+ rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0));
+ rtw89_write32(rtwdev, sub_carr, txsc20);
+ break;
+ case RTW89_CHANNEL_WIDTH_20:
+ rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK);
+ rtw89_write32(rtwdev, sub_carr, 0);
+ break;
+ default:
+ break;
+ }
+
+ if (chan->channel > 14) {
+ rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE);
+ rtw89_write8_set(rtwdev, chk_rate,
+ B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
+ } else {
+ rtw89_write8_set(rtwdev, chk_rate, B_AX_BAND_MODE);
+ rtw89_write8_clr(rtwdev, chk_rate,
+ B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
+ }
+}
+
+static const u32 rtw8851b_sco_barker_threshold[14] = {
+ 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6,
+ 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4
+};
+
+static const u32 rtw8851b_sco_cck_threshold[14] = {
+ 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724,
+ 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed
+};
+
+static void rtw8851b_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 primary_ch)
+{
+ u8 ch_element = primary_ch - 1;
+
+ rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH,
+ rtw8851b_sco_barker_threshold[ch_element]);
+ rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH,
+ rtw8851b_sco_cck_threshold[ch_element]);
+}
+
+static u8 rtw8851b_sco_mapping(u8 central_ch)
+{
+ if (central_ch == 1)
+ return 109;
+ else if (central_ch >= 2 && central_ch <= 6)
+ return 108;
+ else if (central_ch >= 7 && central_ch <= 10)
+ return 107;
+ else if (central_ch >= 11 && central_ch <= 14)
+ return 106;
+ else if (central_ch == 36 || central_ch == 38)
+ return 51;
+ else if (central_ch >= 40 && central_ch <= 58)
+ return 50;
+ else if (central_ch >= 60 && central_ch <= 64)
+ return 49;
+ else if (central_ch == 100 || central_ch == 102)
+ return 48;
+ else if (central_ch >= 104 && central_ch <= 126)
+ return 47;
+ else if (central_ch >= 128 && central_ch <= 151)
+ return 46;
+ else if (central_ch >= 153 && central_ch <= 177)
+ return 45;
+ else
+ return 0;
+}
+
+struct rtw8851b_bb_gain {
+ u32 gain_g[BB_PATH_NUM_8851B];
+ u32 gain_a[BB_PATH_NUM_8851B];
+ u32 gain_mask;
+};
+
+static const struct rtw8851b_bb_gain bb_gain_lna[LNA_GAIN_NUM] = {
+ { .gain_g = {0x4678}, .gain_a = {0x45DC},
+ .gain_mask = 0x00ff0000 },
+ { .gain_g = {0x4678}, .gain_a = {0x45DC},
+ .gain_mask = 0xff000000 },
+ { .gain_g = {0x467C}, .gain_a = {0x4660},
+ .gain_mask = 0x000000ff },
+ { .gain_g = {0x467C}, .gain_a = {0x4660},
+ .gain_mask = 0x0000ff00 },
+ { .gain_g = {0x467C}, .gain_a = {0x4660},
+ .gain_mask = 0x00ff0000 },
+ { .gain_g = {0x467C}, .gain_a = {0x4660},
+ .gain_mask = 0xff000000 },
+ { .gain_g = {0x4680}, .gain_a = {0x4664},
+ .gain_mask = 0x000000ff },
+};
+
+static const struct rtw8851b_bb_gain bb_gain_tia[TIA_GAIN_NUM] = {
+ { .gain_g = {0x4680}, .gain_a = {0x4664},
+ .gain_mask = 0x00ff0000 },
+ { .gain_g = {0x4680}, .gain_a = {0x4664},
+ .gain_mask = 0xff000000 },
+};
+
+static void rtw8851b_set_gain_error(struct rtw89_dev *rtwdev,
+ enum rtw89_subband subband,
+ enum rtw89_rf_path path)
+{
+ const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain;
+ u8 gain_band = rtw89_subband_to_bb_gain_band(subband);
+ s32 val;
+ u32 reg;
+ u32 mask;
+ int i;
+
+ for (i = 0; i < LNA_GAIN_NUM; i++) {
+ if (subband == RTW89_CH_2G)
+ reg = bb_gain_lna[i].gain_g[path];
+ else
+ reg = bb_gain_lna[i].gain_a[path];
+
+ mask = bb_gain_lna[i].gain_mask;
+ val = gain->lna_gain[gain_band][path][i];
+ rtw89_phy_write32_mask(rtwdev, reg, mask, val);
+ }
+
+ for (i = 0; i < TIA_GAIN_NUM; i++) {
+ if (subband == RTW89_CH_2G)
+ reg = bb_gain_tia[i].gain_g[path];
+ else
+ reg = bb_gain_tia[i].gain_a[path];
+
+ mask = bb_gain_tia[i].gain_mask;
+ val = gain->tia_gain[gain_band][path][i];
+ rtw89_phy_write32_mask(rtwdev, reg, mask, val);
+ }
+}
+
+static void rtw8851b_set_gain_offset(struct rtw89_dev *rtwdev,
+ enum rtw89_subband subband,
+ enum rtw89_phy_idx phy_idx)
+{
+ static const u32 rssi_ofst_addr[] = {R_PATH0_G_TIA1_LNA6_OP1DB_V1};
+ static const u32 gain_err_addr[] = {R_P0_AGC_RSVD};
+ struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain;
+ enum rtw89_gain_offset gain_ofdm_band;
+ s32 offset_ofdm, offset_cck;
+ s32 offset_a;
+ s32 tmp;
+ u8 path;
+
+ if (!efuse_gain->comp_valid)
+ goto next;
+
+ for (path = RF_PATH_A; path < BB_PATH_NUM_8851B; path++) {
+ tmp = efuse_gain->comp[path][subband];
+ tmp = clamp_t(s32, tmp << 2, S8_MIN, S8_MAX);
+ rtw89_phy_write32_mask(rtwdev, gain_err_addr[path], MASKBYTE0, tmp);
+ }
+
+next:
+ if (!efuse_gain->offset_valid)
+ return;
+
+ gain_ofdm_band = rtw89_subband_to_gain_offset_band_of_ofdm(subband);
+
+ offset_a = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band];
+
+ tmp = -((offset_a << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2));
+ tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
+ rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[RF_PATH_A], B_PATH0_R_G_OFST_MASK, tmp);
+
+ offset_ofdm = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band];
+ offset_cck = -efuse_gain->offset[RF_PATH_A][0];
+
+ tmp = (offset_ofdm << 4) + efuse_gain->offset_base[RTW89_PHY_0];
+ tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
+ rtw89_phy_write32_idx(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx);
+
+ tmp = (offset_ofdm << 4) + efuse_gain->rssi_base[RTW89_PHY_0];
+ tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
+ rtw89_phy_write32_idx(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx);
+
+ if (subband == RTW89_CH_2G) {
+ tmp = (offset_cck << 3) + (efuse_gain->offset_base[RTW89_PHY_0] >> 1);
+ tmp = clamp_t(s32, tmp, S8_MIN >> 1, S8_MAX >> 1);
+ rtw89_phy_write32_mask(rtwdev, R_RX_RPL_OFST,
+ B_RX_RPL_OFST_CCK_MASK, tmp);
+ }
+}
+
+static
+void rtw8851b_set_rxsc_rpl_comp(struct rtw89_dev *rtwdev, enum rtw89_subband subband)
+{
+ const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain;
+ u8 band = rtw89_subband_to_bb_gain_band(subband);
+ u32 val;
+
+ val = u32_encode_bits(gain->rpl_ofst_20[band][RF_PATH_A], B_P0_RPL1_20_MASK) |
+ u32_encode_bits(gain->rpl_ofst_40[band][RF_PATH_A][0], B_P0_RPL1_40_MASK) |
+ u32_encode_bits(gain->rpl_ofst_40[band][RF_PATH_A][1], B_P0_RPL1_41_MASK);
+ val >>= B_P0_RPL1_SHIFT;
+ rtw89_phy_write32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_MASK, val);
+ rtw89_phy_write32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_MASK, val);
+
+ val = u32_encode_bits(gain->rpl_ofst_40[band][RF_PATH_A][2], B_P0_RTL2_42_MASK) |
+ u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][0], B_P0_RTL2_80_MASK) |
+ u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][1], B_P0_RTL2_81_MASK) |
+ u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][10], B_P0_RTL2_8A_MASK);
+ rtw89_phy_write32(rtwdev, R_P0_RPL2, val);
+ rtw89_phy_write32(rtwdev, R_P1_RPL2, val);
+
+ val = u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][2], B_P0_RTL3_82_MASK) |
+ u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][3], B_P0_RTL3_83_MASK) |
+ u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][4], B_P0_RTL3_84_MASK) |
+ u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][9], B_P0_RTL3_89_MASK);
+ rtw89_phy_write32(rtwdev, R_P0_RPL3, val);
+ rtw89_phy_write32(rtwdev, R_P1_RPL3, val);
+}
+
+static void rtw8851b_ctrl_ch(struct rtw89_dev *rtwdev,
+ const struct rtw89_chan *chan,
+ enum rtw89_phy_idx phy_idx)
+{
+ u8 subband = chan->subband_type;
+ u8 central_ch = chan->channel;
+ bool is_2g = central_ch <= 14;
+ u8 sco_comp;
+
+ if (is_2g)
+ rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
+ B_PATH0_BAND_SEL_MSK_V1, 1, phy_idx);
+ else
+ rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
+ B_PATH0_BAND_SEL_MSK_V1, 0, phy_idx);
+ /* SCO compensate FC setting */
+ sco_comp = rtw8851b_sco_mapping(central_ch);
+ rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_INV, sco_comp, phy_idx);
+
+ if (chan->band_type == RTW89_BAND_6G)
+ return;
+
+ /* CCK parameters */
+ if (central_ch == 14) {
+ rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3b13ff);
+ rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x1c42de);
+ rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfdb0ad);
+ rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xf60f6e);
+ rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xfd8f92);
+ rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011);
+ rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c);
+ rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xfff00a);
+ } else {
+ rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3d23ff);
+ rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x29b354);
+ rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8);
+ rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xfdb053);
+ rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xf86f9a);
+ rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0xfaef92);
+ rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0xfe5fcc);
+ rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xffdff5);
+ }
+
+ rtw8851b_set_gain_error(rtwdev, subband, RF_PATH_A);
+ rtw8851b_set_gain_offset(rtwdev, subband, phy_idx);
+ rtw8851b_set_rxsc_rpl_comp(rtwdev, subband);
+}
+
+static void rtw8851b_bw_setting(struct rtw89_dev *rtwdev, u8 bw)
+{
+ rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_CTL, 0x8);
+ rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_EN, 0x2);
+ rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_BW0, 0x2);
+ rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1, B_P0_CFCH_BW1, 0x4);
+ rtw89_phy_write32_mask(rtwdev, R_DRCK, B_DRCK_MUL, 0xf);
+ rtw89_phy_write32_mask(rtwdev, R_ADCMOD, B_ADCMOD_LP, 0xa);
+ rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_ADJ, 0x92);
+
+ switch (bw) {
+ case RTW89_CHANNEL_WIDTH_5:
+ rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x1);
+ break;
+ case RTW89_CHANNEL_WIDTH_10:
+ rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
+ break;
+ case RTW89_CHANNEL_WIDTH_20:
+ rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x2);
+ rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x2);
+ rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
+ break;
+ case RTW89_CHANNEL_WIDTH_40:
+ rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x2);
+ rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x2);
+ rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
+ break;
+ case RTW89_CHANNEL_WIDTH_80:
+ rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x2);
+ rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
+ break;
+ default:
+ rtw89_warn(rtwdev, "Fail to set ADC\n");
+ }
+}
+
+static void rtw8851b_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw,
+ enum rtw89_phy_idx phy_idx)
+{
+ switch (bw) {
+ case RTW89_CHANNEL_WIDTH_5:
+ rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
+ rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x1, phy_idx);
+ rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
+ break;
+ case RTW89_CHANNEL_WIDTH_10:
+ rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
+ rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x2, phy_idx);
+ rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
+ break;
+ case RTW89_CHANNEL_WIDTH_20:
+ rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
+ rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
+ rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
+ break;
+ case RTW89_CHANNEL_WIDTH_40:
+ rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x1, phy_idx);
+ rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
+ rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH,
+ pri_ch, phy_idx);
+ /* CCK primary channel */
+ if (pri_ch == RTW89_SC_20_UPPER)
+ rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1);
+ else
+ rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0);
+
+ break;
+ case RTW89_CHANNEL_WIDTH_80:
+ rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x2, phy_idx);
+ rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
+ rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH,
+ pri_ch, phy_idx);
+ break;
+ default:
+ rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw,
+ pri_ch);
+ }
+
+ rtw8851b_bw_setting(rtwdev, bw);
+}
+
+static void rtw8851b_ctrl_cck_en(struct rtw89_dev *rtwdev, bool cck_en)
+{
+ if (cck_en) {
+ rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0);
+ rtw89_phy_write32_mask(rtwdev, R_PD_ARBITER_OFF,
+ B_PD_ARBITER_OFF, 0);
+ rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1);
+ } else {
+ rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1);
+ rtw89_phy_write32_mask(rtwdev, R_PD_ARBITER_OFF,
+ B_PD_ARBITER_OFF, 1);
+ rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0);
+ }
+}
+
+static u32 rtw8851b_spur_freq(struct rtw89_dev *rtwdev,
+ const struct rtw89_chan *chan)
+{
+ u8 center_chan = chan->channel;
+
+ switch (chan->band_type) {
+ case RTW89_BAND_5G:
+ if (center_chan == 151 || center_chan == 153 ||
+ center_chan == 155 || center_chan == 163)
+ return 5760;
+ else if (center_chan == 54 || center_chan == 58)
+ return 5280;
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+#define CARRIER_SPACING_312_5 312500 /* 312.5 kHz */
+#define CARRIER_SPACING_78_125 78125 /* 78.125 kHz */
+#define MAX_TONE_NUM 2048
+
+static void rtw8851b_set_csi_tone_idx(struct rtw89_dev *rtwdev,
+ const struct rtw89_chan *chan,
+ enum rtw89_phy_idx phy_idx)
+{
+ u32 spur_freq;
+ s32 freq_diff, csi_idx, csi_tone_idx;
+
+ spur_freq = rtw8851b_spur_freq(rtwdev, chan);
+ if (spur_freq == 0) {
+ rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN_V1, B_SEG0CSI_EN,
+ 0, phy_idx);
+ return;
+ }
+
+ freq_diff = (spur_freq - chan->freq) * 1000000;
+ csi_idx = s32_div_u32_round_closest(freq_diff, CARRIER_SPACING_78_125);
+ s32_div_u32_round_down(csi_idx, MAX_TONE_NUM, &csi_tone_idx);
+
+ rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_V1, B_SEG0CSI_IDX,
+ csi_tone_idx, phy_idx);
+ rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN_V1, B_SEG0CSI_EN, 1, phy_idx);
+}
+
+static const struct rtw89_nbi_reg_def rtw8851b_nbi_reg_def = {
+ .notch1_idx = {0x46E4, 0xFF},
+ .notch1_frac_idx = {0x46E4, 0xC00},
+ .notch1_en = {0x46E4, 0x1000},
+ .notch2_idx = {0x47A4, 0xFF},
+ .notch2_frac_idx = {0x47A4, 0xC00},
+ .notch2_en = {0x47A4, 0x1000},
+};
+
+static void rtw8851b_set_nbi_tone_idx(struct rtw89_dev *rtwdev,
+ const struct rtw89_chan *chan)
+{
+ const struct rtw89_nbi_reg_def *nbi = &rtw8851b_nbi_reg_def;
+ s32 nbi_frac_idx, nbi_frac_tone_idx;
+ s32 nbi_idx, nbi_tone_idx;
+ bool notch2_chk = false;
+ u32 spur_freq, fc;
+ s32 freq_diff;
+
+ spur_freq = rtw8851b_spur_freq(rtwdev, chan);
+ if (spur_freq == 0) {
+ rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
+ nbi->notch1_en.mask, 0);
+ rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
+ nbi->notch2_en.mask, 0);
+ return;
+ }
+
+ fc = chan->freq;
+ if (chan->band_width == RTW89_CHANNEL_WIDTH_160) {
+ fc = (spur_freq > fc) ? fc + 40 : fc - 40;
+ if ((fc > spur_freq &&
+ chan->channel < chan->primary_channel) ||
+ (fc < spur_freq &&
+ chan->channel > chan->primary_channel))
+ notch2_chk = true;
+ }
+
+ freq_diff = (spur_freq - fc) * 1000000;
+ nbi_idx = s32_div_u32_round_down(freq_diff, CARRIER_SPACING_312_5,
+ &nbi_frac_idx);
+
+ if (chan->band_width == RTW89_CHANNEL_WIDTH_20) {
+ s32_div_u32_round_down(nbi_idx + 32, 64, &nbi_tone_idx);
+ } else {
+ u16 tone_para = (chan->band_width == RTW89_CHANNEL_WIDTH_40) ?
+ 128 : 256;
+
+ s32_div_u32_round_down(nbi_idx, tone_para, &nbi_tone_idx);
+ }
+ nbi_frac_tone_idx = s32_div_u32_round_closest(nbi_frac_idx,
+ CARRIER_SPACING_78_125);
+
+ if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && notch2_chk) {
+ rtw89_phy_write32_mask(rtwdev, nbi->notch2_idx.addr,
+ nbi->notch2_idx.mask, nbi_tone_idx);
+ rtw89_phy_write32_mask(rtwdev, nbi->notch2_frac_idx.addr,
+ nbi->notch2_frac_idx.mask, nbi_frac_tone_idx);
+ rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
+ nbi->notch2_en.mask, 0);
+ rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
+ nbi->notch2_en.mask, 1);
+ rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
+ nbi->notch1_en.mask, 0);
+ } else {
+ rtw89_phy_write32_mask(rtwdev, nbi->notch1_idx.addr,
+ nbi->notch1_idx.mask, nbi_tone_idx);
+ rtw89_phy_write32_mask(rtwdev, nbi->notch1_frac_idx.addr,
+ nbi->notch1_frac_idx.mask, nbi_frac_tone_idx);
+ rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
+ nbi->notch1_en.mask, 0);
+ rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
+ nbi->notch1_en.mask, 1);
+ rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
+ nbi->notch2_en.mask, 0);
+ }
+}
+
+static void rtw8851b_set_cfr(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan)
+{
+ if (chan->band_type == RTW89_BAND_2G &&
+ chan->band_width == RTW89_CHANNEL_WIDTH_20 &&
+ (chan->channel == 1 || chan->channel == 13)) {
+ rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
+ B_PATH0_TX_CFR_LGC0, 0xf8);
+ rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
+ B_PATH0_TX_CFR_LGC1, 0x120);
+ rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
+ B_PATH0_TX_POLAR_CLIPPING_LGC0, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
+ B_PATH0_TX_POLAR_CLIPPING_LGC1, 0x3);
+ } else {
+ rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
+ B_PATH0_TX_CFR_LGC0, 0x120);
+ rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
+ B_PATH0_TX_CFR_LGC1, 0x3ff);
+ rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
+ B_PATH0_TX_POLAR_CLIPPING_LGC0, 0x3);
+ rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
+ B_PATH0_TX_POLAR_CLIPPING_LGC1, 0x7);
+ }
+}
+
+static void rtw8851b_5m_mask(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
+ enum rtw89_phy_idx phy_idx)
+{
+ u8 pri_ch = chan->pri_ch_idx;
+ bool mask_5m_low;
+ bool mask_5m_en;
+
+ switch (chan->band_width) {
+ case RTW89_CHANNEL_WIDTH_40:
+ /* Prich=1: Mask 5M High, Prich=2: Mask 5M Low */
+ mask_5m_en = true;
+ mask_5m_low = pri_ch == RTW89_SC_20_LOWER;
+ break;
+ case RTW89_CHANNEL_WIDTH_80:
+ /* Prich=3: Mask 5M High, Prich=4: Mask 5M Low, Else: Disable */
+ mask_5m_en = pri_ch == RTW89_SC_20_UPMOST ||
+ pri_ch == RTW89_SC_20_LOWEST;
+ mask_5m_low = pri_ch == RTW89_SC_20_LOWEST;
+ break;
+ default:
+ mask_5m_en = false;
+ break;
+ }
+
+ if (!mask_5m_en) {
+ rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x0);
+ rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1,
+ B_ASSIGN_SBD_OPT_EN_V1, 0x0, phy_idx);
+ return;
+ }
+
+ if (mask_5m_low) {
+ rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x5);
+ rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x1);
+ } else {
+ rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x5);
+ rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x0);
+ }
+ rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1,
+ B_ASSIGN_SBD_OPT_EN_V1, 0x1, phy_idx);
+}
+
+static void rtw8851b_bb_reset_all(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
+{
+ rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
+ fsleep(1);
+ rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
+ rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
+ rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
+ rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
+}
+
+static void rtw8851b_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band,
+ enum rtw89_phy_idx phy_idx, bool en)
+{
+ if (en) {
+ rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
+ B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
+ rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
+ if (band == RTW89_BAND_2G)
+ rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0);
+ } else {
+ rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1);
+ rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
+ B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
+ fsleep(1);
+ rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
+ }
+}
+
+static void rtw8851b_bb_reset(struct rtw89_dev *rtwdev,
+ enum rtw89_phy_idx phy_idx)
+{
+ rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
+ B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI, 0x1);
+ rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
+ rtw8851b_bb_reset_all(rtwdev, phy_idx);
+ rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
+ B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI, 0x3);
+ rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
+}
+
+static
+void rtw8851b_bb_gpio_trsw(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
+ u8 tx_path_en, u8 trsw_tx,
+ u8 trsw_rx, u8 trsw_a, u8 trsw_b)
+{
+ u32 mask_ofst = 16;
+ u32 val;
+
+ if (path != RF_PATH_A)
+ return;
+
+ mask_ofst += (tx_path_en * 4 + trsw_tx * 2 + trsw_rx) * 2;
+ val = u32_encode_bits(trsw_a, B_P0_TRSW_A) |
+ u32_encode_bits(trsw_b, B_P0_TRSW_B);
+
+ rtw89_phy_write32_mask(rtwdev, R_P0_TRSW,
+ (B_P0_TRSW_A | B_P0_TRSW_B) << mask_ofst, val);
+}
+
+static void rtw8851b_bb_gpio_init(struct rtw89_dev *rtwdev)
+{
+ rtw89_phy_write32_set(rtwdev, R_P0_TRSW, B_P0_TRSW_A);
+ rtw89_phy_write32_clr(rtwdev, R_P0_TRSW, B_P0_TRSW_X);
+ rtw89_phy_write32_clr(rtwdev, R_P0_TRSW, B_P0_TRSW_SO_A2);
+ rtw89_phy_write32(rtwdev, R_RFE_SEL0_BASE, 0x77777777);
+ rtw89_phy_write32(rtwdev, R_RFE_SEL32_BASE, 0x77777777);
+
+ rtw89_phy_write32(rtwdev, R_RFE_E_A2, 0xffffffff);
+ rtw89_phy_write32(rtwdev, R_RFE_O_SEL_A2, 0);
+ rtw89_phy_write32(rtwdev, R_RFE_SEL0_A2, 0);
+ rtw89_phy_write32(rtwdev, R_RFE_SEL32_A2, 0);
+
+ rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 0, 0, 1);
+ rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 1, 1, 0);
+ rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 0, 1, 0);
+ rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 1, 1, 0);
+ rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 0, 0, 1);
+ rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 1, 1, 0);
+ rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 0, 1, 0);
+ rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 1, 1, 0);
+}
+
+static void rtw8851b_bb_macid_ctrl_init(struct rtw89_dev *rtwdev,
+ enum rtw89_phy_idx phy_idx)
+{
+ u32 addr;
+
+ for (addr = R_AX_PWR_MACID_LMT_TABLE0;
+ addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4)
+ rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
+}
+
+static void rtw8851b_bb_sethw(struct rtw89_dev *rtwdev)
+{
+ struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
+
+ rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP);
+
+ rtw8851b_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0);
+ rtw8851b_bb_gpio_init(rtwdev);
+
+ rtw89_write32_clr(rtwdev, R_AX_PWR_NORM_FORCE1, B_AX_FORCE_NTX_VALUE);
+ rtw89_write32_set(rtwdev, R_AX_PWR_NORM_FORCE1, B_AX_FORCE_NTX_EN);
+
+ /* read these registers after loading BB parameters */
+ gain->offset_base[RTW89_PHY_0] =
+ rtw89_phy_read32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK);
+ gain->rssi_base[RTW89_PHY_0] =
+ rtw89_phy_read32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK);
+}
+
+static void rtw8851b_set_channel_bb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
+ enum rtw89_phy_idx phy_idx)
+{
+ u8 band = chan->band_type, chan_idx;
+ bool cck_en = chan->channel <= 14;
+ u8 pri_ch_idx = chan->pri_ch_idx;
+
+ if (cck_en)
+ rtw8851b_ctrl_sco_cck(rtwdev, chan->primary_channel);
+
+ rtw8851b_ctrl_ch(rtwdev, chan, phy_idx);
+ rtw8851b_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx);
+ rtw8851b_ctrl_cck_en(rtwdev, cck_en);
+ rtw8851b_set_nbi_tone_idx(rtwdev, chan);
+ rtw8851b_set_csi_tone_idx(rtwdev, chan, phy_idx);
+
+ if (chan->band_type == RTW89_BAND_5G) {
+ rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
+ B_PATH0_BT_SHARE_V1, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
+ B_PATH0_BTG_PATH_V1, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
+ B_BT_DYN_DC_EST_EN_MSK, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0);
+ }
+
+ chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band);
+ rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx);
+ rtw8851b_5m_mask(rtwdev, chan, phy_idx);
+ rtw8851b_set_cfr(rtwdev, chan);
+ rtw8851b_bb_reset_all(rtwdev, phy_idx);
+}
+
+static void rtw8851b_set_channel(struct rtw89_dev *rtwdev,
+ const struct rtw89_chan *chan,
+ enum rtw89_mac_idx mac_idx,
+ enum rtw89_phy_idx phy_idx)
+{
+ rtw8851b_set_channel_mac(rtwdev, chan, mac_idx);
+ rtw8851b_set_channel_bb(rtwdev, chan, phy_idx);
+ rtw8851b_set_channel_rf(rtwdev, chan, phy_idx);
+}
+
+static void rtw8851b_tssi_cont_en(struct rtw89_dev *rtwdev, bool en,
+ enum rtw89_rf_path path)
+{
+ if (en) {
+ rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN, 0x0);
+ } else {
+ rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN, 0x1);
+ }
+}
+
+static void rtw8851b_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en,
+ u8 phy_idx)
+{
+ rtw8851b_tssi_cont_en(rtwdev, en, RF_PATH_A);
+}
+
+static void rtw8851b_adc_en(struct rtw89_dev *rtwdev, bool en)
+{
+ if (en)
+ rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0);
+ else
+ rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0xf);
+}
+
+static void rtw8851b_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
+ struct rtw89_channel_help_params *p,
+ const struct rtw89_chan *chan,
+ enum rtw89_mac_idx mac_idx,
+ enum rtw89_phy_idx phy_idx)
+{
+ if (enter) {
+ rtw89_chip_stop_sch_tx(rtwdev, RTW89_MAC_0, &p->tx_en, RTW89_SCH_TX_SEL_ALL);
+ rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false);
+ rtw8851b_tssi_cont_en_phyidx(rtwdev, false, RTW89_PHY_0);
+ rtw8851b_adc_en(rtwdev, false);
+ fsleep(40);
+ rtw8851b_bb_reset_en(rtwdev, chan->band_type, phy_idx, false);
+ } else {
+ rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
+ rtw8851b_adc_en(rtwdev, true);
+ rtw8851b_tssi_cont_en_phyidx(rtwdev, true, RTW89_PHY_0);
+ rtw8851b_bb_reset_en(rtwdev, chan->band_type, phy_idx, true);
+ rtw89_chip_resume_sch_tx(rtwdev, RTW89_MAC_0, p->tx_en);
+ }
+}
+
+static void rtw8851b_rfk_init(struct rtw89_dev *rtwdev)
+{
+ rtwdev->is_tssi_mode[RF_PATH_A] = false;
+ rtwdev->is_tssi_mode[RF_PATH_B] = false;
+ rtw8851b_lck_init(rtwdev);
+
+ rtw8851b_dpk_init(rtwdev);
+ rtw8851b_aack(rtwdev);
+ rtw8851b_rck(rtwdev);
+ rtw8851b_dack(rtwdev);
+ rtw8851b_rx_dck(rtwdev, RTW89_PHY_0);
+}
+
+static void rtw8851b_rfk_channel(struct rtw89_dev *rtwdev)
+{
+ enum rtw89_phy_idx phy_idx = RTW89_PHY_0;
+
+ rtw8851b_rx_dck(rtwdev, phy_idx);
+ rtw8851b_iqk(rtwdev, phy_idx);
+ rtw8851b_tssi(rtwdev, phy_idx, true);
+ rtw8851b_dpk(rtwdev, phy_idx);
+}
+
+static void rtw8851b_rfk_band_changed(struct rtw89_dev *rtwdev,
+ enum rtw89_phy_idx phy_idx)
+{
+ rtw8851b_tssi_scan(rtwdev, phy_idx);
+}
+
+static void rtw8851b_rfk_scan(struct rtw89_dev *rtwdev, bool start)
+{
+ rtw8851b_wifi_scan_notify(rtwdev, start, RTW89_PHY_0);
+}
+
+static void rtw8851b_rfk_track(struct rtw89_dev *rtwdev)
+{
+ rtw8851b_dpk_track(rtwdev);
+ rtw8851b_lck_track(rtwdev);
+}
+
+static u32 rtw8851b_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev,
+ enum rtw89_phy_idx phy_idx, s16 ref)
+{
+ const u16 tssi_16dbm_cw = 0x12c;
+ const u8 base_cw_0db = 0x27;
+ const s8 ofst_int = 0;
+ s16 pwr_s10_3;
+ s16 rf_pwr_cw;
+ u16 bb_pwr_cw;
+ u32 pwr_cw;
+ u32 tssi_ofst_cw;
+
+ pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3);
+ bb_pwr_cw = u16_get_bits(pwr_s10_3, GENMASK(2, 0));
+ rf_pwr_cw = u16_get_bits(pwr_s10_3, GENMASK(8, 3));
+ rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63);
+ pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw;
+
+ tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3));
+ rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
+ "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n",
+ tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw);
+
+ return u32_encode_bits(tssi_ofst_cw, B_DPD_TSSI_CW) |
+ u32_encode_bits(pwr_cw, B_DPD_PWR_CW) |
+ u32_encode_bits(ref, B_DPD_REF);
+}
+
+static void rtw8851b_set_txpwr_ref(struct rtw89_dev *rtwdev,
+ enum rtw89_phy_idx phy_idx)
+{
+ static const u32 addr[RF_PATH_NUM_8851B] = {0x5800};
+ const u32 mask = B_DPD_TSSI_CW | B_DPD_PWR_CW | B_DPD_REF;
+ const u8 ofst_ofdm = 0x4;
+ const u8 ofst_cck = 0x8;
+ const s16 ref_ofdm = 0;
+ const s16 ref_cck = 0;
+ u32 val;
+ u8 i;
+
+ rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n");
+
+ rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL,
+ B_AX_PWR_REF, 0x0);
+
+ rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n");
+ val = rtw8851b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm);
+
+ for (i = 0; i < RF_PATH_NUM_8851B; i++)
+ rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val,
+ phy_idx);
+
+ rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n");
+ val = rtw8851b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck);
+
+ for (i = 0; i < RF_PATH_NUM_8851B; i++)
+ rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val,
+ phy_idx);
+}
+
+static void rtw8851b_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev,
+ const struct rtw89_chan *chan,
+ u8 tx_shape_idx,
+ enum rtw89_phy_idx phy_idx)
+{
+#define __DFIR_CFG_ADDR(i) (R_TXFIR0 + ((i) << 2))
+#define __DFIR_CFG_MASK 0xffffffff
+#define __DFIR_CFG_NR 8
+#define __DECL_DFIR_PARAM(_name, _val...) \
+ static const u32 param_ ## _name[] = {_val}; \
+ static_assert(ARRAY_SIZE(param_ ## _name) == __DFIR_CFG_NR)
+
+ __DECL_DFIR_PARAM(flat,
+ 0x023D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053,
+ 0x00F86F9A, 0x06FAEF92, 0x00FE5FCC, 0x00FFDFF5);
+ __DECL_DFIR_PARAM(sharp,
+ 0x023D83FF, 0x002C636A, 0x0013F204, 0x00008090,
+ 0x00F87FB0, 0x06F99F83, 0x00FDBFBA, 0x00003FF5);
+ __DECL_DFIR_PARAM(sharp_14,
+ 0x023B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E,
+ 0x00FD8F92, 0x0602D011, 0x0001C02C, 0x00FFF00A);
+ u8 ch = chan->channel;
+ const u32 *param;
+ u32 addr;
+ int i;
+
+ if (ch > 14) {
+ rtw89_warn(rtwdev,
+ "set tx shape dfir by unknown ch: %d on 2G\n", ch);
+ return;
+ }
+
+ if (ch == 14)
+ param = param_sharp_14;
+ else
+ param = tx_shape_idx == 0 ? param_flat : param_sharp;
+
+ for (i = 0; i < __DFIR_CFG_NR; i++) {
+ addr = __DFIR_CFG_ADDR(i);
+ rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
+ "set tx shape dfir: 0x%x: 0x%x\n", addr, param[i]);
+ rtw89_phy_write32_idx(rtwdev, addr, __DFIR_CFG_MASK, param[i],
+ phy_idx);
+ }
+
+#undef __DECL_DFIR_PARAM
+#undef __DFIR_CFG_NR
+#undef __DFIR_CFG_MASK
+#undef __DECL_CFG_ADDR
+}
+
+static void rtw8851b_set_tx_shape(struct rtw89_dev *rtwdev,
+ const struct rtw89_chan *chan,
+ enum rtw89_phy_idx phy_idx)
+{
+ u8 band = chan->band_type;
+ u8 regd = rtw89_regd_get(rtwdev, band);
+ u8 tx_shape_cck = rtw89_8851b_tx_shape[band][RTW89_RS_CCK][regd];
+ u8 tx_shape_ofdm = rtw89_8851b_tx_shape[band][RTW89_RS_OFDM][regd];
+
+ if (band == RTW89_BAND_2G)
+ rtw8851b_bb_set_tx_shape_dfir(rtwdev, chan, tx_shape_cck, phy_idx);
+
+ rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG,
+ tx_shape_ofdm);
+}
+
+static void rtw8851b_set_txpwr(struct rtw89_dev *rtwdev,
+ const struct rtw89_chan *chan,
+ enum rtw89_phy_idx phy_idx)
+{
+ rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
+ rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
+ rtw8851b_set_tx_shape(rtwdev, chan, phy_idx);
+ rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
+ rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
+}
+
+static void rtw8851b_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
+ enum rtw89_phy_idx phy_idx)
+{
+ rtw8851b_set_txpwr_ref(rtwdev, phy_idx);
+}
+
+static
+void rtw8851b_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
+ s8 pw_ofst, enum rtw89_mac_idx mac_idx)
+{
+ u32 reg;
+
+ if (pw_ofst < -16 || pw_ofst > 15) {
+ rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst);
+ return;
+ }
+
+ reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_CTRL, mac_idx);
+ rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN);
+
+ reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_1T, mac_idx);
+ rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, pw_ofst);
+
+ pw_ofst = max_t(s8, pw_ofst - 3, -16);
+ reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_2T, mac_idx);
+ rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, pw_ofst);
+}
+
+static int
+rtw8851b_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
+{
+ int ret;
+
+ ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333);
+ if (ret)
+ return ret;
+
+ ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000);
+ if (ret)
+ return ret;
+
+ ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff);
+ if (ret)
+ return ret;
+
+ rtw8851b_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ?
+ RTW89_MAC_1 : RTW89_MAC_0);
+
+ return 0;
+}
+
+static void rtw8851b_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, bool bt_en)
+{
+ const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
+
+ rtw89_phy_write_reg3_tbl(rtwdev, bt_en ? &rtw8851b_btc_preagc_en_defs_tbl :
+ &rtw8851b_btc_preagc_dis_defs_tbl);
+
+ if (!bt_en) {
+ if (chan->band_type == RTW89_BAND_2G) {
+ rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
+ B_PATH0_G_LNA6_OP1DB_V1, 0x20);
+ rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
+ B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x30);
+ } else {
+ rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
+ B_PATH0_G_LNA6_OP1DB_V1, 0x1a);
+ rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
+ B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x2a);
+ }
+ }
+}
+
+static void rtw8851b_ctrl_btg(struct rtw89_dev *rtwdev, bool btg)
+{
+ const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
+
+ if (btg) {
+ rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
+ B_PATH0_BT_SHARE_V1, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
+ B_PATH0_BTG_PATH_V1, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
+ B_PATH0_G_LNA6_OP1DB_V1, 0x20);
+ rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
+ B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x30);
+ rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
+ B_BT_DYN_DC_EST_EN_MSK, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x1);
+ } else {
+ rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
+ B_PATH0_BT_SHARE_V1, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
+ B_PATH0_BTG_PATH_V1, 0x0);
+ if (chan->band_type == RTW89_BAND_2G) {
+ rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
+ B_PATH0_G_LNA6_OP1DB_V1, 0x80);
+ rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
+ B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x80);
+ } else {
+ rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
+ B_PATH0_G_LNA6_OP1DB_V1, 0x1a);
+ rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
+ B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x2a);
+ }
+ rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xc);
+ rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
+ B_BT_DYN_DC_EST_EN_MSK, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0);
+ }
+}
+
+static void rtw8851b_bb_ctrl_rx_path(struct rtw89_dev *rtwdev,
+ enum rtw89_rf_path_bit rx_path)
+{
+ const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
+ u32 rst_mask0;
+
+ if (rx_path == RF_A) {
+ rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 1);
+ rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 1);
+ rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 1);
+ rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
+ rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
+ rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4);
+ rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
+ rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
+ }
+
+ rtw8851b_set_gain_offset(rtwdev, chan->subband_type, RTW89_PHY_0);
+
+ rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI;
+ if (rx_path == RF_A) {
+ rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1);
+ rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3);
+ }
+}
+
+static void rtw8851b_bb_cfg_txrx_path(struct rtw89_dev *rtwdev)
+{
+ rtw8851b_bb_ctrl_rx_path(rtwdev, RF_A);
+
+ if (rtwdev->hal.rx_nss == 1) {
+ rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
+ rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
+ rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
+ rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
+ }
+
+ rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0);
+}
+
+static u8 rtw8851b_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
+{
+ if (rtwdev->is_tssi_mode[rf_path]) {
+ u32 addr = R_TSSI_THER + (rf_path << 13);
+
+ return rtw89_phy_read32_mask(rtwdev, addr, B_TSSI_THER);
+ }
+
+ rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
+ rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0);
+ rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
+
+ fsleep(200);
+
+ return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL);
+}
+
+static void rtw8851b_btc_set_rfe(struct rtw89_dev *rtwdev)
+{
+ struct rtw89_btc *btc = &rtwdev->btc;
+ struct rtw89_btc_module *module = &btc->mdinfo;
+
+ module->rfe_type = rtwdev->efuse.rfe_type;
+ module->cv = rtwdev->hal.cv;
+ module->bt_solo = 0;
+ module->switch_type = BTC_SWITCH_INTERNAL;
+ module->ant.isolation = 10;
+ module->kt_ver_adie = rtwdev->hal.acv;
+
+ if (module->rfe_type == 0)
+ return;
+
+ /* rfe_type 3*n+1: 1-Ant(shared),
+ * 3*n+2: 2-Ant+Div(non-shared),
+ * 3*n+3: 2-Ant+no-Div(non-shared)
+ */
+ module->ant.num = (module->rfe_type % 3 == 1) ? 1 : 2;
+ /* WL-1ss at S0, btg at s0 (On 1 WL RF) */
+ module->ant.single_pos = RF_PATH_A;
+ module->ant.btg_pos = RF_PATH_A;
+ module->ant.stream_cnt = 1;
+
+ if (module->ant.num == 1) {
+ module->ant.type = BTC_ANT_SHARED;
+ module->bt_pos = BTC_BT_BTG;
+ module->wa_type = 1;
+ module->ant.diversity = 0;
+ } else { /* ant.num == 2 */
+ module->ant.type = BTC_ANT_DEDICATED;
+ module->bt_pos = BTC_BT_ALONE;
+ module->switch_type = BTC_SWITCH_EXTERNAL;
+ module->wa_type = 0;
+ if (module->rfe_type % 3 == 2)
+ module->ant.diversity = 1;
+ }
+}
+
+static
+void rtw8851b_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)
+{
+ if (group > BTC_BT_SS_GROUP)
+ group--; /* Tx-group=1, Rx-group=2 */
+
+ if (rtwdev->btc.mdinfo.ant.type == BTC_ANT_SHARED) /* 1-Ant */
+ group += 3;
+
+ rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group);
+ rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val);
+}
+
+static void rtw8851b_btc_init_cfg(struct rtw89_dev *rtwdev)
+{
+ static const struct rtw89_mac_ax_coex coex_params = {
+ .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE,
+ .direction = RTW89_MAC_AX_COEX_INNER,
+ };
+ const struct rtw89_chip_info *chip = rtwdev->chip;
+ struct rtw89_btc *btc = &rtwdev->btc;
+ struct rtw89_btc_module *module = &btc->mdinfo;
+ struct rtw89_btc_ant_info *ant = &module->ant;
+ u8 path, path_min, path_max;
+
+ /* PTA init */
+ rtw89_mac_coex_init(rtwdev, &coex_params);
+
+ /* set WL Tx response = Hi-Pri */
+ chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true);
+ chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true);
+
+ /* for 1-Ant && 1-ss case: only 1-path */
+ if (ant->stream_cnt == 1) {
+ path_min = ant->single_pos;
+ path_max = path_min;
+ } else {
+ path_min = RF_PATH_A;
+ path_max = RF_PATH_B;
+ }
+
+ for (path = path_min; path <= path_max; path++) {
+ /* set rf gnt-debug off */
+ rtw89_write_rf(rtwdev, path, RR_WLSEL, RFREG_MASK, 0x0);
+
+ /* set DEBUG_LUT_RFMODE_MASK = 1 to start trx-mask-setup */
+ rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, BIT(17));
+
+ /* if GNT_WL=0 && BT=SS_group --> WL Tx/Rx = THRU */
+ rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_SS_GROUP, 0x5ff);
+
+ /* if GNT_WL=0 && BT=Rx_group --> WL-Rx = THRU + WL-Tx = MASK */
+ rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_RX_GROUP, 0x5df);
+
+ /* if GNT_WL = 0 && BT = Tx_group -->
+ * Shared-Ant && BTG-path:WL mask(0x55f), others:WL THRU(0x5ff)
+ */
+ if (ant->type == BTC_ANT_SHARED && ant->btg_pos == path)
+ rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x55f);
+ else
+ rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x5ff);
+
+ /* set DEBUG_LUT_RFMODE_MASK = 0 to stop trx-mask-setup */
+ rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0);
+ }
+
+ /* set PTA break table */
+ rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM);
+
+ /* enable BT counter 0xda40[16,2] = 2b'11 */
+ rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN);
+
+ btc->cx.wl.status.map.init_ok = true;
+}
+
+static
+void rtw8851b_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state)
+{
+ u32 bitmap;
+ u32 reg;
+
+ switch (map) {
+ case BTC_PRI_MASK_TX_RESP:
+ reg = R_BTC_BT_COEX_MSK_TABLE;
+ bitmap = B_BTC_PRI_MASK_TX_RESP_V1;
+ break;
+ case BTC_PRI_MASK_BEACON:
+ reg = R_AX_WL_PRI_MSK;
+ bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ;
+ break;
+ case BTC_PRI_MASK_RX_CCK:
+ reg = R_BTC_BT_COEX_MSK_TABLE;
+ bitmap = B_BTC_PRI_MASK_RXCCK_V1;
+ break;
+ default:
+ return;
+ }
+
+ if (state)
+ rtw89_write32_set(rtwdev, reg, bitmap);
+ else
+ rtw89_write32_clr(rtwdev, reg, bitmap);
+}
+
+union rtw8851b_btc_wl_txpwr_ctrl {
+ u32 txpwr_val;
+ struct {
+ union {
+ u16 ctrl_all_time;
+ struct {
+ s16 data:9;
+ u16 rsvd:6;
+ u16 flag:1;
+ } all_time;
+ };
+ union {
+ u16 ctrl_gnt_bt;
+ struct {
+ s16 data:9;
+ u16 rsvd:7;
+ } gnt_bt;
+ };
+ };
+} __packed;
+
+static void
+rtw8851b_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
+{
+ union rtw8851b_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val };
+ s32 val;
+
+#define __write_ctrl(_reg, _msk, _val, _en, _cond) \
+do { \
+ u32 _wrt = FIELD_PREP(_msk, _val); \
+ BUILD_BUG_ON(!!(_msk & _en)); \
+ if (_cond) \
+ _wrt |= _en; \
+ else \
+ _wrt &= ~_en; \
+ rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \
+ _msk | _en, _wrt); \
+} while (0)
+
+ switch (arg.ctrl_all_time) {
+ case 0xffff:
+ val = 0;
+ break;
+ default:
+ val = arg.all_time.data;
+ break;
+ }
+
+ __write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK,
+ val, B_AX_FORCE_PWR_BY_RATE_EN,
+ arg.ctrl_all_time != 0xffff);
+
+ switch (arg.ctrl_gnt_bt) {
+ case 0xffff:
+ val = 0;
+ break;
+ default:
+ val = arg.gnt_bt.data;
+ break;
+ }
+
+ __write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val,
+ B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff);
+
+#undef __write_ctrl
+}
+
+static
+s8 rtw8851b_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
+{
+ val = clamp_t(s8, val, -100, 0) + 100;
+ val = min(val + 6, 100); /* compensate offset */
+
+ return val;
+}
+
+static
+void rtw8851b_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
+{
+ /* Feature move to firmware */
+}
+
+static void rtw8851b_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
+{
+ struct rtw89_btc *btc = &rtwdev->btc;
+ struct rtw89_btc_ant_info *ant = &btc->mdinfo.ant;
+
+ rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWE, RFREG_MASK, 0x80000);
+ rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWA, RFREG_MASK, 0x1);
+ rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWD1, RFREG_MASK, 0x110);
+
+ /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */
+ if (state)
+ rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWD0, RFREG_MASK, 0x179c);
+ else
+ rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWD0, RFREG_MASK, 0x208);
+
+ rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWE, RFREG_MASK, 0x0);
+}
+
+#define LNA2_51B_MA 0x700
+
+static const struct rtw89_reg2_def btc_8851b_rf_0[] = {{0x2, 0x0}};
+static const struct rtw89_reg2_def btc_8851b_rf_1[] = {{0x2, 0x1}};
+
+static void rtw8851b_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level)
+{
+ /* To improve BT ACI in co-rx
+ * level=0 Default: TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB
+ * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB
+ */
+ struct rtw89_btc *btc = &rtwdev->btc;
+ struct rtw89_btc_ant_info *ant = &btc->mdinfo.ant;
+ const struct rtw89_reg2_def *rf;
+ u32 n, i, val;
+
+ switch (level) {
+ case 0: /* original */
+ default:
+ btc->dm.wl_lna2 = 0;
+ break;
+ case 1: /* for FDD free-run */
+ btc->dm.wl_lna2 = 0;
+ break;
+ case 2: /* for BTG Co-Rx*/
+ btc->dm.wl_lna2 = 1;
+ break;
+ }
+
+ if (btc->dm.wl_lna2 == 0) {
+ rf = btc_8851b_rf_0;
+ n = ARRAY_SIZE(btc_8851b_rf_0);
+ } else {
+ rf = btc_8851b_rf_1;
+ n = ARRAY_SIZE(btc_8851b_rf_1);
+ }
+
+ for (i = 0; i < n; i++, rf++) {
+ val = rf->data;
+ /* bit[10] = 1 if non-shared-ant for 8851b */
+ if (btc->mdinfo.ant.type == BTC_ANT_DEDICATED)
+ val |= 0x4;
+
+ rtw89_write_rf(rtwdev, ant->btg_pos, rf->addr, LNA2_51B_MA, val);
+ }
+}
+
+static void rtw8851b_fill_freq_with_ppdu(struct rtw89_dev *rtwdev,
+ struct rtw89_rx_phy_ppdu *phy_ppdu,
+ struct ieee80211_rx_status *status)
+{
+ u16 chan = phy_ppdu->chan_idx;
+ enum nl80211_band band;
+ u8 ch;
+
+ if (chan == 0)
+ return;
+
+ rtw89_decode_chan_idx(rtwdev, chan, &ch, &band);
+ status->freq = ieee80211_channel_to_frequency(ch, band);
+ status->band = band;
+}
+
+static void rtw8851b_query_ppdu(struct rtw89_dev *rtwdev,
+ struct rtw89_rx_phy_ppdu *phy_ppdu,
+ struct ieee80211_rx_status *status)
+{
+ u8 path;
+ u8 *rx_power = phy_ppdu->rssi;
+
+ status->signal = RTW89_RSSI_RAW_TO_DBM(rx_power[RF_PATH_A]);
+
+ for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
+ status->chains |= BIT(path);
+ status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]);
+ }
+ if (phy_ppdu->valid)
+ rtw8851b_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);
+}
+
+static int rtw8851b_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
+{
+ int ret;
+
+ rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN,
+ B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
+ rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
+ rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
+ rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
+
+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xC7,
+ FULL_BIT_MASK);
+ if (ret)
+ return ret;
+
+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xC7,
+ FULL_BIT_MASK);
+ if (ret)
+ return ret;
+
+ rtw89_write8(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_XYN_CYCLE);
+
+ return 0;
+}
+
+static int rtw8851b_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
+{
+ u8 wl_rfc_s0;
+ u8 wl_rfc_s1;
+ int ret;
+
+ rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN,
+ B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
+
+ ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, &wl_rfc_s0);
+ if (ret)
+ return ret;
+ wl_rfc_s0 &= ~XTAL_SI_RF00S_EN;
+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, wl_rfc_s0,
+ FULL_BIT_MASK);
+ if (ret)
+ return ret;
+
+ ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, &wl_rfc_s1);
+ if (ret)
+ return ret;
+ wl_rfc_s1 &= ~XTAL_SI_RF10S_EN;
+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, wl_rfc_s1,
+ FULL_BIT_MASK);
+ return ret;
+}
+
+static const struct rtw89_chip_ops rtw8851b_chip_ops = {
+ .enable_bb_rf = rtw8851b_mac_enable_bb_rf,
+ .disable_bb_rf = rtw8851b_mac_disable_bb_rf,
+ .bb_reset = rtw8851b_bb_reset,
+ .bb_sethw = rtw8851b_bb_sethw,
+ .read_rf = rtw89_phy_read_rf_v1,
+ .write_rf = rtw89_phy_write_rf_v1,
+ .set_channel = rtw8851b_set_channel,
+ .set_channel_help = rtw8851b_set_channel_help,
+ .read_efuse = rtw8851b_read_efuse,
+ .read_phycap = rtw8851b_read_phycap,
+ .fem_setup = NULL,
+ .rfe_gpio = rtw8851b_rfe_gpio,
+ .rfk_init = rtw8851b_rfk_init,
+ .rfk_channel = rtw8851b_rfk_channel,
+ .rfk_band_changed = rtw8851b_rfk_band_changed,
+ .rfk_scan = rtw8851b_rfk_scan,
+ .rfk_track = rtw8851b_rfk_track,
+ .power_trim = rtw8851b_power_trim,
+ .set_txpwr = rtw8851b_set_txpwr,
+ .set_txpwr_ctrl = rtw8851b_set_txpwr_ctrl,
+ .init_txpwr_unit = rtw8851b_init_txpwr_unit,
+ .get_thermal = rtw8851b_get_thermal,
+ .ctrl_btg = rtw8851b_ctrl_btg,
+ .query_ppdu = rtw8851b_query_ppdu,
+ .bb_ctrl_btc_preagc = rtw8851b_bb_ctrl_btc_preagc,
+ .cfg_txrx_path = rtw8851b_bb_cfg_txrx_path,
+ .set_txpwr_ul_tb_offset = rtw8851b_set_txpwr_ul_tb_offset,
+ .pwr_on_func = rtw8851b_pwr_on_func,
+ .pwr_off_func = rtw8851b_pwr_off_func,
+ .query_rxdesc = rtw89_core_query_rxdesc,
+ .fill_txdesc = rtw89_core_fill_txdesc,
+ .fill_txdesc_fwcmd = rtw89_core_fill_txdesc,
+ .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path,
+ .mac_cfg_gnt = rtw89_mac_cfg_gnt,
+ .stop_sch_tx = rtw89_mac_stop_sch_tx,
+ .resume_sch_tx = rtw89_mac_resume_sch_tx,
+ .h2c_dctl_sec_cam = NULL,
+
+ .btc_set_rfe = rtw8851b_btc_set_rfe,
+ .btc_init_cfg = rtw8851b_btc_init_cfg,
+ .btc_set_wl_pri = rtw8851b_btc_set_wl_pri,
+ .btc_set_wl_txpwr_ctrl = rtw8851b_btc_set_wl_txpwr_ctrl,
+ .btc_get_bt_rssi = rtw8851b_btc_get_bt_rssi,
+ .btc_update_bt_cnt = rtw8851b_btc_update_bt_cnt,
+ .btc_wl_s1_standby = rtw8851b_btc_wl_s1_standby,
+ .btc_set_wl_rx_gain = rtw8851b_btc_set_wl_rx_gain,
+ .btc_set_policy = rtw89_btc_set_policy_v1,
+};
+
+#ifdef CONFIG_PM
+static const struct wiphy_wowlan_support rtw_wowlan_stub_8851b = {
+ .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
+ .n_patterns = RTW89_MAX_PATTERN_NUM,
+ .pattern_max_len = RTW89_MAX_PATTERN_SIZE,
+ .pattern_min_len = 1,
+};
+#endif
+
+const struct rtw89_chip_info rtw8851b_chip_info = {
+ .chip_id = RTL8851B,
+ .ops = &rtw8851b_chip_ops,
+ .fw_basename = RTW8851B_FW_BASENAME,
+ .fw_format_max = RTW8851B_FW_FORMAT_MAX,
+ .try_ce_fw = true,
+ .fifo_size = 196608,
+ .small_fifo_size = true,
+ .dle_scc_rsvd_size = 98304,
+ .max_amsdu_limit = 3500,
+ .dis_2g_40m_ul_ofdma = true,
+ .rsvd_ple_ofst = 0x2f800,
+ .hfc_param_ini = rtw8851b_hfc_param_ini_pcie,
+ .dle_mem = rtw8851b_dle_mem_pcie,
+ .wde_qempty_acq_num = 4,
+ .wde_qempty_mgq_sel = 4,
+ .rf_base_addr = {0xe000},
+ .pwr_on_seq = NULL,
+ .pwr_off_seq = NULL,
+ .bb_table = &rtw89_8851b_phy_bb_table,
+ .bb_gain_table = &rtw89_8851b_phy_bb_gain_table,
+ .rf_table = {&rtw89_8851b_phy_radioa_table,},
+ .nctl_table = &rtw89_8851b_phy_nctl_table,
+ .nctl_post_table = &rtw8851b_nctl_post_defs_tbl,
+ .byr_table = &rtw89_8851b_byr_table,
+ .dflt_parms = &rtw89_8851b_dflt_parms,
+ .rfe_parms_conf = rtw89_8851b_rfe_parms_conf,
+ .txpwr_factor_rf = 2,
+ .txpwr_factor_mac = 1,
+ .dig_table = NULL,
+ .dig_regs = &rtw8851b_dig_regs,
+ .tssi_dbw_table = NULL,
+ .support_chanctx_num = 0,
+ .support_bands = BIT(NL80211_BAND_2GHZ) |
+ BIT(NL80211_BAND_5GHZ),
+ .support_bw160 = false,
+ .support_unii4 = true,
+ .support_ul_tb_ctrl = true,
+ .hw_sec_hdr = false,
+ .rf_path_num = 1,
+ .tx_nss = 1,
+ .rx_nss = 1,
+ .acam_num = 32,
+ .bcam_num = 20,
+ .scam_num = 128,
+ .bacam_num = 2,
+ .bacam_dynamic_num = 4,
+ .bacam_ver = RTW89_BACAM_V0,
+ .sec_ctrl_efuse_size = 4,
+ .physical_efuse_size = 1216,
+ .logical_efuse_size = 2048,
+ .limit_efuse_size = 1280,
+ .dav_phy_efuse_size = 0,
+ .dav_log_efuse_size = 0,
+ .phycap_addr = 0x580,
+ .phycap_size = 128,
+ .para_ver = 0,
+ .wlcx_desired = 0x06000000,
+ .btcx_desired = 0x7,
+ .scbd = 0x1,
+ .mailbox = 0x1,
+
+ .afh_guard_ch = 6,
+ .wl_rssi_thres = rtw89_btc_8851b_wl_rssi_thres,
+ .bt_rssi_thres = rtw89_btc_8851b_bt_rssi_thres,
+ .rssi_tol = 2,
+ .mon_reg_num = ARRAY_SIZE(rtw89_btc_8851b_mon_reg),
+ .mon_reg = rtw89_btc_8851b_mon_reg,
+ .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8851b_rf_ul),
+ .rf_para_ulink = rtw89_btc_8851b_rf_ul,
+ .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8851b_rf_dl),
+ .rf_para_dlink = rtw89_btc_8851b_rf_dl,
+ .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) |
+ BIT(RTW89_PS_MODE_CLK_GATED),
+ .low_power_hci_modes = 0,
+ .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD,
+ .hci_func_en_addr = R_AX_HCI_FUNC_EN,
+ .h2c_desc_size = sizeof(struct rtw89_txwd_body),
+ .txwd_body_size = sizeof(struct rtw89_txwd_body),
+ .h2c_ctrl_reg = R_AX_H2CREG_CTRL,
+ .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8},
+ .h2c_regs = rtw8851b_h2c_regs,
+ .c2h_ctrl_reg = R_AX_C2HREG_CTRL,
+ .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
+ .c2h_regs = rtw8851b_c2h_regs,
+ .page_regs = &rtw8851b_page_regs,
+ .cfo_src_fd = true,
+ .cfo_hw_comp = true,
+ .dcfo_comp = &rtw8851b_dcfo_comp,
+ .dcfo_comp_sft = 12,
+ .imr_info = &rtw8851b_imr_info,
+ .rrsr_cfgs = &rtw8851b_rrsr_cfgs,
+ .bss_clr_map_reg = R_BSS_CLR_MAP_V1,
+ .dma_ch_mask = BIT(RTW89_DMA_ACH4) | BIT(RTW89_DMA_ACH5) |
+ BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) |
+ BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI),
+ .edcca_lvl_reg = R_SEG0R_EDCCA_LVL_V1,
+#ifdef CONFIG_PM
+ .wowlan_stub = &rtw_wowlan_stub_8851b,
+#endif
+ .xtal_info = &rtw8851b_xtal_info,
+};
+EXPORT_SYMBOL(rtw8851b_chip_info);
+
+MODULE_FIRMWARE(RTW8851B_MODULE_FIRMWARE);
+MODULE_AUTHOR("Realtek Corporation");
+MODULE_DESCRIPTION("Realtek 802.11ax wireless 8851B driver");
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/net/wireless/realtek/rtw89/rtw8851b.h b/drivers/net/wireless/realtek/rtw89/rtw8851b.h
new file mode 100644
index 000000000000..1a5c52654d8a
--- /dev/null
+++ b/drivers/net/wireless/realtek/rtw89/rtw8851b.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
+/* Copyright(c) 2022-2023 Realtek Corporation
+ */
+
+#ifndef __RTW89_8851B_H__
+#define __RTW89_8851B_H__
+
+#include "core.h"
+
+#define RF_PATH_NUM_8851B 1
+#define BB_PATH_NUM_8851B 1
+
+struct rtw8851bu_efuse {
+ u8 rsvd[0x88];
+ u8 mac_addr[ETH_ALEN];
+};
+
+struct rtw8851be_efuse {
+ u8 mac_addr[ETH_ALEN];
+};
+
+struct rtw8851b_tssi_offset {
+ u8 cck_tssi[TSSI_CCK_CH_GROUP_NUM];
+ u8 bw40_tssi[TSSI_MCS_2G_CH_GROUP_NUM];
+ u8 rsvd[7];
+ u8 bw40_1s_tssi_5g[TSSI_MCS_5G_CH_GROUP_NUM];
+} __packed;
+
+struct rtw8851b_efuse {
+ u8 rsvd[0x210];
+ struct rtw8851b_tssi_offset path_a_tssi;
+ u8 rsvd1[136];
+ u8 channel_plan;
+ u8 xtal_k;
+ u8 rsvd2;
+ u8 iqk_lck;
+ u8 rsvd3[8];
+ u8 eeprom_version;
+ u8 customer_id;
+ u8 tx_bb_swing_2g;
+ u8 tx_bb_swing_5g;
+ u8 tx_cali_pwr_trk_mode;
+ u8 trx_path_selection;
+ u8 rfe_type;
+ u8 country_code[2];
+ u8 rsvd4[3];
+ u8 path_a_therm;
+ u8 rsvd5[3];
+ u8 rx_gain_2g_ofdm;
+ u8 rsvd6;
+ u8 rx_gain_2g_cck;
+ u8 rsvd7;
+ u8 rx_gain_5g_low;
+ u8 rsvd8;
+ u8 rx_gain_5g_mid;
+ u8 rsvd9;
+ u8 rx_gain_5g_high;
+ u8 rsvd10[35];
+ u8 path_a_cck_pwr_idx[6];
+ u8 path_a_bw40_1tx_pwr_idx[5];
+ u8 path_a_ofdm_1tx_pwr_idx_diff:4;
+ u8 path_a_bw20_1tx_pwr_idx_diff:4;
+ u8 path_a_bw20_2tx_pwr_idx_diff:4;
+ u8 path_a_bw40_2tx_pwr_idx_diff:4;
+ u8 path_a_cck_2tx_pwr_idx_diff:4;
+ u8 path_a_ofdm_2tx_pwr_idx_diff:4;
+ u8 rsvd11[0xf2];
+ union {
+ struct rtw8851bu_efuse u;
+ struct rtw8851be_efuse e;
+ };
+} __packed;
+
+extern const struct rtw89_chip_info rtw8851b_chip_info;
+
+#endif
diff --git a/drivers/net/wireless/realtek/rtw89/rtw8851b_rfk.c b/drivers/net/wireless/realtek/rtw89/rtw8851b_rfk.c
new file mode 100644
index 000000000000..a221f94627f5
--- /dev/null
+++ b/drivers/net/wireless/realtek/rtw89/rtw8851b_rfk.c
@@ -0,0 +1,3621 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/* Copyright(c) 2022-2023 Realtek Corporation
+ */
+
+#include "coex.h"
+#include "debug.h"
+#include "mac.h"
+#include "phy.h"
+#include "reg.h"
+#include "rtw8851b.h"
+#include "rtw8851b_rfk.h"
+#include "rtw8851b_rfk_table.h"
+#include "rtw8851b_table.h"
+
+#define DPK_VER_8851B 0x5
+#define DPK_KIP_REG_NUM_8851B 7
+#define DPK_RF_REG_NUM_8851B 4
+#define DPK_KSET_NUM 4
+#define RTW8851B_RXK_GROUP_NR 4
+#define RTW8851B_RXK_GROUP_IDX_NR 2
+#define RTW8851B_TXK_GROUP_NR 1
+#define RTW8851B_IQK_VER 0x2a
+#define RTW8851B_IQK_SS 1
+#define RTW8851B_LOK_GRAM 10
+#define RTW8851B_TSSI_PATH_NR 1
+
+#define _TSSI_DE_MASK GENMASK(21, 12)
+
+enum dpk_id {
+ LBK_RXIQK = 0x06,
+ SYNC = 0x10,
+ MDPK_IDL = 0x11,
+ MDPK_MPA = 0x12,
+ GAIN_LOSS = 0x13,
+ GAIN_CAL = 0x14,
+ DPK_RXAGC = 0x15,
+ KIP_PRESET = 0x16,
+ KIP_RESTORE = 0x17,
+ DPK_TXAGC = 0x19,
+ D_KIP_PRESET = 0x28,
+ D_TXAGC = 0x29,
+ D_RXAGC = 0x2a,
+ D_SYNC = 0x2b,
+ D_GAIN_LOSS = 0x2c,
+ D_MDPK_IDL = 0x2d,
+ D_MDPK_LDL = 0x2e,
+ D_GAIN_NORM = 0x2f,
+ D_KIP_THERMAL = 0x30,
+ D_KIP_RESTORE = 0x31
+};
+
+enum dpk_agc_step {
+ DPK_AGC_STEP_SYNC_DGAIN,
+ DPK_AGC_STEP_GAIN_LOSS_IDX,
+ DPK_AGC_STEP_GL_GT_CRITERION,
+ DPK_AGC_STEP_GL_LT_CRITERION,
+ DPK_AGC_STEP_SET_TX_GAIN,
+};
+
+enum rtw8851b_iqk_type {
+ ID_TXAGC = 0x0,
+ ID_FLOK_COARSE = 0x1,
+ ID_FLOK_FINE = 0x2,
+ ID_TXK = 0x3,
+ ID_RXAGC = 0x4,
+ ID_RXK = 0x5,
+ ID_NBTXK = 0x6,
+ ID_NBRXK = 0x7,
+ ID_FLOK_VBUFFER = 0x8,
+ ID_A_FLOK_COARSE = 0x9,
+ ID_G_FLOK_COARSE = 0xa,
+ ID_A_FLOK_FINE = 0xb,
+ ID_G_FLOK_FINE = 0xc,
+ ID_IQK_RESTORE = 0x10,
+};
+
+enum rf_mode {
+ RF_SHUT_DOWN = 0x0,
+ RF_STANDBY = 0x1,
+ RF_TX = 0x2,
+ RF_RX = 0x3,
+ RF_TXIQK = 0x4,
+ RF_DPK = 0x5,
+ RF_RXK1 = 0x6,
+ RF_RXK2 = 0x7,
+};
+
+static const u32 _tssi_de_cck_long[RF_PATH_NUM_8851B] = {0x5858};
+static const u32 _tssi_de_cck_short[RF_PATH_NUM_8851B] = {0x5860};
+static const u32 _tssi_de_mcs_20m[RF_PATH_NUM_8851B] = {0x5838};
+static const u32 _tssi_de_mcs_40m[RF_PATH_NUM_8851B] = {0x5840};
+static const u32 _tssi_de_mcs_80m[RF_PATH_NUM_8851B] = {0x5848};
+static const u32 _tssi_de_mcs_80m_80m[RF_PATH_NUM_8851B] = {0x5850};
+static const u32 _tssi_de_mcs_5m[RF_PATH_NUM_8851B] = {0x5828};
+static const u32 _tssi_de_mcs_10m[RF_PATH_NUM_8851B] = {0x5830};
+static const u32 g_idxrxgain[RTW8851B_RXK_GROUP_NR] = {0x10e, 0x116, 0x28e, 0x296};
+static const u32 g_idxattc2[RTW8851B_RXK_GROUP_NR] = {0x0, 0xf, 0x0, 0xf};
+static const u32 g_idxrxagc[RTW8851B_RXK_GROUP_NR] = {0x0, 0x1, 0x2, 0x3};
+static const u32 a_idxrxgain[RTW8851B_RXK_GROUP_IDX_NR] = {0x10C, 0x28c};
+static const u32 a_idxattc2[RTW8851B_RXK_GROUP_IDX_NR] = {0xf, 0xf};
+static const u32 a_idxrxagc[RTW8851B_RXK_GROUP_IDX_NR] = {0x4, 0x6};
+static const u32 a_power_range[RTW8851B_TXK_GROUP_NR] = {0x0};
+static const u32 a_track_range[RTW8851B_TXK_GROUP_NR] = {0x6};
+static const u32 a_gain_bb[RTW8851B_TXK_GROUP_NR] = {0x0a};
+static const u32 a_itqt[RTW8851B_TXK_GROUP_NR] = {0x12};
+static const u32 g_power_range[RTW8851B_TXK_GROUP_NR] = {0x0};
+static const u32 g_track_range[RTW8851B_TXK_GROUP_NR] = {0x6};
+static const u32 g_gain_bb[RTW8851B_TXK_GROUP_NR] = {0x10};
+static const u32 g_itqt[RTW8851B_TXK_GROUP_NR] = {0x12};
+
+static const u32 rtw8851b_backup_bb_regs[] = {0xc0d4, 0xc0d8, 0xc0c4, 0xc0ec, 0xc0e8};
+static const u32 rtw8851b_backup_rf_regs[] = {
+ 0xef, 0xde, 0x0, 0x1e, 0x2, 0x85, 0x90, 0x5};
+
+#define BACKUP_BB_REGS_NR ARRAY_SIZE(rtw8851b_backup_bb_regs)
+#define BACKUP_RF_REGS_NR ARRAY_SIZE(rtw8851b_backup_rf_regs)
+
+static const u32 dpk_kip_reg[DPK_KIP_REG_NUM_8851B] = {
+ 0x813c, 0x8124, 0xc0ec, 0xc0e8, 0xc0c4, 0xc0d4, 0xc0d8};
+static const u32 dpk_rf_reg[DPK_RF_REG_NUM_8851B] = {0xde, 0x8f, 0x5, 0x10005};
+
+static void _set_ch(struct rtw89_dev *rtwdev, u32 val);
+
+static u8 _rxk_5ghz_group_from_idx(u8 idx)
+{
+ /* There are four RXK groups (RTW8851B_RXK_GROUP_NR), but only group 0
+ * and 2 are used in 5 GHz band, so reduce elements to 2.
+ */
+ if (idx < RTW8851B_RXK_GROUP_IDX_NR)
+ return idx * 2;
+
+ return 0;
+}
+
+static u8 _kpath(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
+{
+ return RF_A;
+}
+
+static void _adc_fifo_rst(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
+ u8 path)
+{
+ rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RXK, 0x0101);
+ fsleep(10);
+ rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RXK, 0x1111);
+}
+
+static void _rfk_rf_direct_cntrl(struct rtw89_dev *rtwdev,
+ enum rtw89_rf_path path, bool is_bybb)
+{
+ if (is_bybb)
+ rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1);
+ else
+ rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
+}
+
+static void _rfk_drf_direct_cntrl(struct rtw89_dev *rtwdev,
+ enum rtw89_rf_path path, bool is_bybb)
+{
+ if (is_bybb)
+ rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x1);
+ else
+ rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x0);
+}
+
+static void _wait_rx_mode(struct rtw89_dev *rtwdev, u8 kpath)
+{
+ u32 rf_mode;
+ u8 path;
+ int ret;
+
+ for (path = 0; path < RF_PATH_MAX; path++) {
+ if (!(kpath & BIT(path)))
+ continue;
+
+ ret = read_poll_timeout_atomic(rtw89_read_rf, rf_mode,
+ rf_mode != 2, 2, 5000, false,
+ rtwdev, path, 0x00, RR_MOD_MASK);
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[RFK] Wait S%d to Rx mode!! (ret = %d)\n",
+ path, ret);
+ }
+}
+
+static void _dack_reset(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
+{
+ rtw89_phy_write32_mask(rtwdev, R_DCOF0, B_DCOF0_RST, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_DCOF0, B_DCOF0_RST, 0x1);
+}
+
+static void _drck(struct rtw89_dev *rtwdev)
+{
+ u32 rck_d;
+ u32 val;
+ int ret;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]Ddie RCK start!!!\n");
+
+ rtw89_phy_write32_mask(rtwdev, R_DRCK, B_DRCK_IDLE, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_DRCK, B_DRCK_EN, 0x1);
+
+ ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val,
+ 1, 10000, false,
+ rtwdev, R_DRCK_RES, B_DRCK_POL);
+ if (ret)
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DRCK timeout\n");
+
+ rtw89_phy_write32_mask(rtwdev, R_DRCK, B_DRCK_EN, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_DRCK_FH, B_DRCK_LAT, 0x1);
+ udelay(1);
+ rtw89_phy_write32_mask(rtwdev, R_DRCK_FH, B_DRCK_LAT, 0x0);
+
+ rck_d = rtw89_phy_read32_mask(rtwdev, R_DRCK_RES, 0x7c00);
+ rtw89_phy_write32_mask(rtwdev, R_DRCK, B_DRCK_IDLE, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_DRCK, B_DRCK_VAL, rck_d);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0xc0c4 = 0x%x\n",
+ rtw89_phy_read32_mask(rtwdev, R_DRCK, MASKDWORD));
+}
+
+static void _addck_backup(struct rtw89_dev *rtwdev)
+{
+ struct rtw89_dack_info *dack = &rtwdev->dack;
+
+ rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0, 0x0);
+
+ dack->addck_d[0][0] = rtw89_phy_read32_mask(rtwdev, R_ADDCKR0, B_ADDCKR0_A0);
+ dack->addck_d[0][1] = rtw89_phy_read32_mask(rtwdev, R_ADDCKR0, B_ADDCKR0_A1);
+}
+
+static void _addck_reload(struct rtw89_dev *rtwdev)
+{
+ struct rtw89_dack_info *dack = &rtwdev->dack;
+
+ rtw89_phy_write32_mask(rtwdev, R_ADDCK0_RL, B_ADDCK0_RL1, dack->addck_d[0][0]);
+ rtw89_phy_write32_mask(rtwdev, R_ADDCK0_RL, B_ADDCK0_RL0, dack->addck_d[0][1]);
+ rtw89_phy_write32_mask(rtwdev, R_ADDCK0_RL, B_ADDCK0_RLS, 0x3);
+}
+
+static void _dack_backup_s0(struct rtw89_dev *rtwdev)
+{
+ struct rtw89_dack_info *dack = &rtwdev->dack;
+ u8 i;
+
+ rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x1);
+
+ for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
+ rtw89_phy_write32_mask(rtwdev, R_DCOF0, B_DCOF0_V, i);
+ dack->msbk_d[0][0][i] =
+ rtw89_phy_read32_mask(rtwdev, R_DACK_S0P2, B_DACK_S0M0);
+
+ rtw89_phy_write32_mask(rtwdev, R_DCOF8, B_DCOF8_V, i);
+ dack->msbk_d[0][1][i] =
+ rtw89_phy_read32_mask(rtwdev, R_DACK_S0P3, B_DACK_S0M1);
+ }
+
+ dack->biask_d[0][0] =
+ rtw89_phy_read32_mask(rtwdev, R_DACK_BIAS00, B_DACK_BIAS00);
+ dack->biask_d[0][1] =
+ rtw89_phy_read32_mask(rtwdev, R_DACK_BIAS01, B_DACK_BIAS01);
+ dack->dadck_d[0][0] =
+ rtw89_phy_read32_mask(rtwdev, R_DACK_DADCK00, B_DACK_DADCK00) + 24;
+ dack->dadck_d[0][1] =
+ rtw89_phy_read32_mask(rtwdev, R_DACK_DADCK01, B_DACK_DADCK01) + 24;
+}
+
+static void _dack_reload_by_path(struct rtw89_dev *rtwdev,
+ enum rtw89_rf_path path, u8 index)
+{
+ struct rtw89_dack_info *dack = &rtwdev->dack;
+ u32 idx_offset, path_offset;
+ u32 offset, reg;
+ u32 tmp;
+ u8 i;
+
+ if (index == 0)
+ idx_offset = 0;
+ else
+ idx_offset = 0x14;
+
+ if (path == RF_PATH_A)
+ path_offset = 0;
+ else
+ path_offset = 0x28;
+
+ offset = idx_offset + path_offset;
+
+ rtw89_phy_write32_mask(rtwdev, R_DCOF1, B_DCOF1_RST, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_DCOF9, B_DCOF9_RST, 0x1);
+
+ /* msbk_d: 15/14/13/12 */
+ tmp = 0x0;
+ for (i = 0; i < 4; i++)
+ tmp |= dack->msbk_d[path][index][i + 12] << (i * 8);
+ reg = 0xc200 + offset;
+ rtw89_phy_write32(rtwdev, reg, tmp);
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", reg,
+ rtw89_phy_read32_mask(rtwdev, reg, MASKDWORD));
+
+ /* msbk_d: 11/10/9/8 */
+ tmp = 0x0;
+ for (i = 0; i < 4; i++)
+ tmp |= dack->msbk_d[path][index][i + 8] << (i * 8);
+ reg = 0xc204 + offset;
+ rtw89_phy_write32(rtwdev, reg, tmp);
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", reg,
+ rtw89_phy_read32_mask(rtwdev, reg, MASKDWORD));
+
+ /* msbk_d: 7/6/5/4 */
+ tmp = 0x0;
+ for (i = 0; i < 4; i++)
+ tmp |= dack->msbk_d[path][index][i + 4] << (i * 8);
+ reg = 0xc208 + offset;
+ rtw89_phy_write32(rtwdev, reg, tmp);
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", reg,
+ rtw89_phy_read32_mask(rtwdev, reg, MASKDWORD));
+
+ /* msbk_d: 3/2/1/0 */
+ tmp = 0x0;
+ for (i = 0; i < 4; i++)
+ tmp |= dack->msbk_d[path][index][i] << (i * 8);
+ reg = 0xc20c + offset;
+ rtw89_phy_write32(rtwdev, reg, tmp);
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", reg,
+ rtw89_phy_read32_mask(rtwdev, reg, MASKDWORD));
+
+ /* dadak_d/biask_d */
+ tmp = 0x0;
+ tmp = (dack->biask_d[path][index] << 22) |
+ (dack->dadck_d[path][index] << 14);
+ reg = 0xc210 + offset;
+ rtw89_phy_write32(rtwdev, reg, tmp);
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", reg,
+ rtw89_phy_read32_mask(rtwdev, reg, MASKDWORD));
+
+ rtw89_phy_write32_mask(rtwdev, R_DACKN0_CTL + offset, B_DACKN0_EN, 0x1);
+}
+
+static void _dack_reload(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
+{
+ u8 index;
+
+ for (index = 0; index < 2; index++)
+ _dack_reload_by_path(rtwdev, path, index);
+}
+
+static void _addck(struct rtw89_dev *rtwdev)
+{
+ struct rtw89_dack_info *dack = &rtwdev->dack;
+ u32 val;
+ int ret;
+
+ rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_RST, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_EN, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_EN, 0x0);
+ udelay(1);
+ rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0, 0x1);
+
+ ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val,
+ 1, 10000, false,
+ rtwdev, R_ADDCKR0, BIT(0));
+ if (ret) {
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADDCK timeout\n");
+ dack->addck_timeout[0] = true;
+ }
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]ADDCK ret = %d\n", ret);
+
+ rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_RST, 0x0);
+}
+
+static void _new_dadck(struct rtw89_dev *rtwdev)
+{
+ struct rtw89_dack_info *dack = &rtwdev->dack;
+ u32 i_dc, q_dc, ic, qc;
+ u32 val;
+ int ret;
+
+ rtw89_rfk_parser(rtwdev, &rtw8851b_dadck_setup_defs_tbl);
+
+ ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val,
+ 1, 10000, false,
+ rtwdev, R_ADDCKR0, BIT(0));
+ if (ret) {
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 DADCK timeout\n");
+ dack->addck_timeout[0] = true;
+ }
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DADCK ret = %d\n", ret);
+
+ rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_IQ, 0x0);
+ i_dc = rtw89_phy_read32_mask(rtwdev, R_ADDCKR0, B_ADDCKR0_DC);
+ rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_IQ, 0x1);
+ q_dc = rtw89_phy_read32_mask(rtwdev, R_ADDCKR0, B_ADDCKR0_DC);
+
+ ic = 0x80 - sign_extend32(i_dc, 11) * 6;
+ qc = 0x80 - sign_extend32(q_dc, 11) * 6;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[DACK]before DADCK, i_dc=0x%x, q_dc=0x%x\n", i_dc, q_dc);
+
+ dack->dadck_d[0][0] = ic;
+ dack->dadck_d[0][1] = qc;
+
+ rtw89_phy_write32_mask(rtwdev, R_DACKN0_CTL, B_DACKN0_V, dack->dadck_d[0][0]);
+ rtw89_phy_write32_mask(rtwdev, R_DACKN1_CTL, B_DACKN1_V, dack->dadck_d[0][1]);
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[DACK]after DADCK, 0xc210=0x%x, 0xc224=0x%x\n",
+ rtw89_phy_read32_mask(rtwdev, R_DACKN0_CTL, MASKDWORD),
+ rtw89_phy_read32_mask(rtwdev, R_DACKN1_CTL, MASKDWORD));
+
+ rtw89_rfk_parser(rtwdev, &rtw8851b_dadck_post_defs_tbl);
+}
+
+static bool _dack_s0_poll(struct rtw89_dev *rtwdev)
+{
+ if (rtw89_phy_read32_mask(rtwdev, R_DACK_S0P0, B_DACK_S0P0_OK) == 0 ||
+ rtw89_phy_read32_mask(rtwdev, R_DACK_S0P1, B_DACK_S0P1_OK) == 0 ||
+ rtw89_phy_read32_mask(rtwdev, R_DACK_S0P2, B_DACK_S0P2_OK) == 0 ||
+ rtw89_phy_read32_mask(rtwdev, R_DACK_S0P3, B_DACK_S0P3_OK) == 0)
+ return false;
+
+ return true;
+}
+
+static void _dack_s0(struct rtw89_dev *rtwdev)
+{
+ struct rtw89_dack_info *dack = &rtwdev->dack;
+ bool done;
+ int ret;
+
+ rtw89_rfk_parser(rtwdev, &rtw8851b_dack_s0_1_defs_tbl);
+ _dack_reset(rtwdev, RF_PATH_A);
+ rtw89_phy_write32_mask(rtwdev, R_DCOF1, B_DCOF1_S, 0x1);
+
+ ret = read_poll_timeout_atomic(_dack_s0_poll, done, done,
+ 1, 10000, false, rtwdev);
+ if (ret) {
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 DACK timeout\n");
+ dack->msbk_timeout[0] = true;
+ }
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK ret = %d\n", ret);
+
+ rtw89_rfk_parser(rtwdev, &rtw8851b_dack_s0_2_defs_tbl);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S0 DADCK\n");
+
+ _dack_backup_s0(rtwdev);
+ _dack_reload(rtwdev, RF_PATH_A);
+
+ rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x0);
+}
+
+static void _dack(struct rtw89_dev *rtwdev)
+{
+ _dack_s0(rtwdev);
+}
+
+static void _dack_dump(struct rtw89_dev *rtwdev)
+{
+ struct rtw89_dack_info *dack = &rtwdev->dack;
+ u8 i;
+ u8 t;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_DCK ic = 0x%x, qc = 0x%x\n",
+ dack->addck_d[0][0], dack->addck_d[0][1]);
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 DAC_DCK ic = 0x%x, qc = 0x%x\n",
+ dack->dadck_d[0][0], dack->dadck_d[0][1]);
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 biask ic = 0x%x, qc = 0x%x\n",
+ dack->biask_d[0][0], dack->biask_d[0][1]);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK ic:\n");
+ for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
+ t = dack->msbk_d[0][0][i];
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t);
+ }
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK qc:\n");
+ for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
+ t = dack->msbk_d[0][1][i];
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t);
+ }
+}
+
+static void _dack_manual_off(struct rtw89_dev *rtwdev)
+{
+ rtw89_rfk_parser(rtwdev, &rtw8851b_dack_manual_off_defs_tbl);
+}
+
+static void _dac_cal(struct rtw89_dev *rtwdev, bool force)
+{
+ struct rtw89_dack_info *dack = &rtwdev->dack;
+ u32 rf0_0;
+
+ dack->dack_done = false;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK 0x2\n");
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK start!!!\n");
+ rf0_0 = rtw89_read_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK);
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]RF0=0x%x\n", rf0_0);
+
+ _drck(rtwdev);
+ _dack_manual_off(rtwdev);
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK, 0x337e1);
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RR_RSV1_RST, 0x0);
+
+ _addck(rtwdev);
+ _addck_backup(rtwdev);
+ _addck_reload(rtwdev);
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK, 0x40001);
+
+ _dack(rtwdev);
+ _new_dadck(rtwdev);
+ _dack_dump(rtwdev);
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RR_RSV1_RST, 0x1);
+
+ dack->dack_done = true;
+ dack->dack_cnt++;
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK finish!!!\n");
+}
+
+static void _rx_dck_info(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
+ enum rtw89_rf_path path, bool is_afe)
+{
+ const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[RX_DCK] ==== S%d RX DCK (%s / CH%d / %s / by %s)====\n", path,
+ chan->band_type == RTW89_BAND_2G ? "2G" :
+ chan->band_type == RTW89_BAND_5G ? "5G" : "6G",
+ chan->channel,
+ chan->band_width == RTW89_CHANNEL_WIDTH_20 ? "20M" :
+ chan->band_width == RTW89_CHANNEL_WIDTH_40 ? "40M" : "80M",
+ is_afe ? "AFE" : "RFC");
+}
+
+static void _rxbb_ofst_swap(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 rf_mode)
+{
+ u32 val, val_i, val_q;
+
+ val_i = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_S1);
+ val_q = rtw89_read_rf(rtwdev, path, RR_DCK1, RR_DCK1_S1);
+
+ val = val_q << 4 | val_i;
+
+ rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_DIS, 0x1);
+ rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, rf_mode);
+ rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val);
+ rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_DIS, 0x0);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[RX_DCK] val_i = 0x%x, val_q = 0x%x, 0x3F = 0x%x\n",
+ val_i, val_q, val);
+}
+
+static void _set_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 rf_mode)
+{
+ u32 val;
+ int ret;
+
+ rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0);
+ rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x1);
+
+ ret = read_poll_timeout_atomic(rtw89_read_rf, val, val,
+ 2, 2000, false,
+ rtwdev, path, RR_DCK, BIT(8));
+
+ rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RX_DCK] S%d RXDCK finish (ret = %d)\n",
+ path, ret);
+
+ _rxbb_ofst_swap(rtwdev, path, rf_mode);
+}
+
+static void _rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, bool is_afe)
+{
+ u32 rf_reg5;
+ u8 path;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[RX_DCK] ****** RXDCK Start (Ver: 0x%x, Cv: %d) ******\n",
+ 0x2, rtwdev->hal.cv);
+
+ for (path = 0; path < RF_PATH_NUM_8851B; path++) {
+ _rx_dck_info(rtwdev, phy, path, is_afe);
+
+ rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK);
+
+ if (rtwdev->is_tssi_mode[path])
+ rtw89_phy_write32_mask(rtwdev,
+ R_P0_TSSI_TRK + (path << 13),
+ B_P0_TSSI_TRK_EN, 0x1);
+
+ rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
+ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RF_RX);
+ _set_rx_dck(rtwdev, path, RF_RX);
+ rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5);
+
+ if (rtwdev->is_tssi_mode[path])
+ rtw89_phy_write32_mask(rtwdev,
+ R_P0_TSSI_TRK + (path << 13),
+ B_P0_TSSI_TRK_EN, 0x0);
+ }
+}
+
+static void _iqk_sram(struct rtw89_dev *rtwdev, u8 path)
+{
+ u32 i;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
+
+ rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00020000);
+ rtw89_phy_write32_mask(rtwdev, R_MDPK_RX_DCK, MASKDWORD, 0x80000000);
+ rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX2, MASKDWORD, 0x00000080);
+ rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX, MASKDWORD, 0x00010000);
+ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x009);
+
+ for (i = 0; i <= 0x9f; i++) {
+ rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX, MASKDWORD,
+ 0x00010000 + i);
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]0x%x\n",
+ rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCI));
+ }
+
+ for (i = 0; i <= 0x9f; i++) {
+ rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX, MASKDWORD,
+ 0x00010000 + i);
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]0x%x\n",
+ rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCQ));
+ }
+
+ rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX2, MASKDWORD, 0x00000000);
+ rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX, MASKDWORD, 0x00000000);
+}
+
+static void _iqk_rxk_setting(struct rtw89_dev *rtwdev, u8 path)
+{
+ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc);
+ rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0);
+ rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x1);
+}
+
+static bool _iqk_check_cal(struct rtw89_dev *rtwdev, u8 path)
+{
+ bool fail1 = false, fail2 = false;
+ u32 val;
+ int ret;
+
+ ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x55,
+ 10, 8200, false,
+ rtwdev, 0xbff8, MASKBYTE0);
+ if (ret) {
+ fail1 = true;
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]NCTL1 IQK timeout!!!\n");
+ }
+
+ fsleep(10);
+
+ ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x8000,
+ 10, 200, false,
+ rtwdev, R_RPT_COM, B_RPT_COM_RDY);
+ if (ret) {
+ fail2 = true;
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]NCTL2 IQK timeout!!!\n");
+ }
+
+ fsleep(10);
+ rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, MASKBYTE0, 0x0);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]S%x, ret = %d, notready = %x fail=%d,%d\n",
+ path, ret, fail1 || fail2, fail1, fail2);
+
+ return fail1 || fail2;
+}
+
+static bool _iqk_one_shot(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
+ u8 path, u8 ktype)
+{
+ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
+ bool notready;
+ u32 iqk_cmd;
+
+ switch (ktype) {
+ case ID_A_FLOK_COARSE:
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]============ S%d ID_A_FLOK_COARSE ============\n", path);
+ rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_IQK_RFC_ON, 0x1);
+ iqk_cmd = 0x108 | (1 << (4 + path));
+ break;
+ case ID_G_FLOK_COARSE:
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]============ S%d ID_G_FLOK_COARSE ============\n", path);
+ rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_IQK_RFC_ON, 0x1);
+ iqk_cmd = 0x108 | (1 << (4 + path));
+ break;
+ case ID_A_FLOK_FINE:
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]============ S%d ID_A_FLOK_FINE ============\n", path);
+ rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_IQK_RFC_ON, 0x1);
+ iqk_cmd = 0x308 | (1 << (4 + path));
+ break;
+ case ID_G_FLOK_FINE:
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]============ S%d ID_G_FLOK_FINE ============\n", path);
+ rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_IQK_RFC_ON, 0x1);
+ iqk_cmd = 0x308 | (1 << (4 + path));
+ break;
+ case ID_TXK:
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]============ S%d ID_TXK ============\n", path);
+ rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_IQK_RFC_ON, 0x0);
+ iqk_cmd = 0x008 | (1 << (path + 4)) |
+ (((0x8 + iqk_info->iqk_bw[path]) & 0xf) << 8);
+ break;
+ case ID_RXAGC:
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]============ S%d ID_RXAGC ============\n", path);
+ rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_IQK_RFC_ON, 0x1);
+ iqk_cmd = 0x708 | (1 << (4 + path)) | (path << 1);
+ break;
+ case ID_RXK:
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]============ S%d ID_RXK ============\n", path);
+ rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_IQK_RFC_ON, 0x1);
+ iqk_cmd = 0x008 | (1 << (path + 4)) |
+ (((0xc + iqk_info->iqk_bw[path]) & 0xf) << 8);
+ break;
+ case ID_NBTXK:
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]============ S%d ID_NBTXK ============\n", path);
+ rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_IQK_RFC_ON, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT,
+ 0x00b);
+ iqk_cmd = 0x408 | (1 << (4 + path));
+ break;
+ case ID_NBRXK:
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]============ S%d ID_NBRXK ============\n", path);
+ rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_IQK_RFC_ON, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT,
+ 0x011);
+ iqk_cmd = 0x608 | (1 << (4 + path));
+ break;
+ default:
+ return false;
+ }
+
+ rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, iqk_cmd + 1);
+ notready = _iqk_check_cal(rtwdev, path);
+ if (iqk_info->iqk_sram_en &&
+ (ktype == ID_NBRXK || ktype == ID_RXK))
+ _iqk_sram(rtwdev, path);
+
+ rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_IQK_RFC_ON, 0x0);
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]S%x, ktype= %x, id = %x, notready = %x\n",
+ path, ktype, iqk_cmd + 1, notready);
+
+ return notready;
+}
+
+static bool _rxk_2g_group_sel(struct rtw89_dev *rtwdev,
+ enum rtw89_phy_idx phy_idx, u8 path)
+{
+ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
+ bool kfail = false;
+ bool notready;
+ u32 rf_0;
+ u8 gp;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
+
+ for (gp = 0; gp < RTW8851B_RXK_GROUP_NR; gp++) {
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, gp = %x\n", path, gp);
+
+ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RGM, g_idxrxgain[gp]);
+ rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C2, g_idxattc2[gp]);
+ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_SEL, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G3, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_GP_V1, gp);
+
+ rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80013);
+ fsleep(10);
+ rf_0 = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK);
+ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF2, B_IQK_DIF2_RXPI, rf_0);
+ rtw89_phy_write32_mask(rtwdev, R_IQK_RXA, B_IQK_RXAGC, g_idxrxagc[gp]);
+ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x11);
+
+ notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXAGC);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]S%x, RXAGC 0x8008 = 0x%x, rxbb = %x\n", path,
+ rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, MASKDWORD),
+ rtw89_read_rf(rtwdev, path, RR_MOD, 0x003e0));
+
+ rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_OFF, 0x13);
+ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x011);
+ notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBRXK);
+ iqk_info->nb_rxcfir[path] =
+ rtw89_phy_read32_mask(rtwdev, R_RXIQC, MASKDWORD) | 0x2;
+
+ notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXK);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]S%x, WBRXK 0x8008 = 0x%x\n", path,
+ rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, MASKDWORD));
+ }
+
+ if (!notready)
+ kfail = !!rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, B_NCTL_RPT_FLG);
+
+ if (kfail)
+ _iqk_sram(rtwdev, path);
+
+ if (kfail) {
+ rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8),
+ MASKDWORD, iqk_info->nb_rxcfir[path] | 0x2);
+ iqk_info->is_wb_txiqk[path] = false;
+ } else {
+ rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8),
+ MASKDWORD, 0x40000000);
+ iqk_info->is_wb_txiqk[path] = true;
+ }
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]S%x, kfail = 0x%x, 0x8%x3c = 0x%x\n", path, kfail,
+ 1 << path, iqk_info->nb_rxcfir[path]);
+ return kfail;
+}
+
+static bool _rxk_5g_group_sel(struct rtw89_dev *rtwdev,
+ enum rtw89_phy_idx phy_idx, u8 path)
+{
+ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
+ bool kfail = false;
+ bool notready;
+ u32 rf_0;
+ u8 idx;
+ u8 gp;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
+
+ for (idx = 0; idx < RTW8851B_RXK_GROUP_IDX_NR; idx++) {
+ gp = _rxk_5ghz_group_from_idx(idx);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, gp = %x\n", path, gp);
+
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RR_MOD_RGM, a_idxrxgain[idx]);
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_RXA2, RR_RXA2_ATT, a_idxattc2[idx]);
+
+ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_SEL, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G3, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_GP_V1, gp);
+
+ rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80013);
+ fsleep(100);
+ rf_0 = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK);
+ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF2, B_IQK_DIF2_RXPI, rf_0);
+ rtw89_phy_write32_mask(rtwdev, R_IQK_RXA, B_IQK_RXAGC, a_idxrxagc[idx]);
+ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x11);
+ notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXAGC);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]S%x, RXAGC 0x8008 = 0x%x, rxbb = %x\n", path,
+ rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, MASKDWORD),
+ rtw89_read_rf(rtwdev, path, RR_MOD, RR_MOD_RXB));
+
+ rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_OFF, 0x13);
+ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x011);
+ notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBRXK);
+ iqk_info->nb_rxcfir[path] =
+ rtw89_phy_read32_mask(rtwdev, R_RXIQC, MASKDWORD) | 0x2;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]S%x, NBRXK 0x8008 = 0x%x\n", path,
+ rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, MASKDWORD));
+
+ notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXK);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]S%x, WBRXK 0x8008 = 0x%x\n", path,
+ rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, MASKDWORD));
+ }
+
+ if (!notready)
+ kfail = !!rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, B_NCTL_RPT_FLG);
+
+ if (kfail)
+ _iqk_sram(rtwdev, path);
+
+ if (kfail) {
+ rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD,
+ iqk_info->nb_rxcfir[path] | 0x2);
+ iqk_info->is_wb_txiqk[path] = false;
+ } else {
+ rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD,
+ 0x40000000);
+ iqk_info->is_wb_txiqk[path] = true;
+ }
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]S%x, kfail = 0x%x, 0x8%x3c = 0x%x\n", path, kfail,
+ 1 << path, iqk_info->nb_rxcfir[path]);
+ return kfail;
+}
+
+static bool _iqk_5g_nbrxk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
+ u8 path)
+{
+ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
+ bool kfail = false;
+ bool notready;
+ u8 idx = 0x1;
+ u32 rf_0;
+ u8 gp;
+
+ gp = _rxk_5ghz_group_from_idx(idx);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, gp = %x\n", path, gp);
+
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RR_MOD_RGM, a_idxrxgain[idx]);
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_RXA2, RR_RXA2_ATT, a_idxattc2[idx]);
+
+ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_SEL, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G3, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_GP_V1, gp);
+
+ rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80013);
+ fsleep(100);
+ rf_0 = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK);
+ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF2, B_IQK_DIF2_RXPI, rf_0);
+ rtw89_phy_write32_mask(rtwdev, R_IQK_RXA, B_IQK_RXAGC, a_idxrxagc[idx]);
+ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x11);
+ notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXAGC);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]S%x, RXAGC 0x8008 = 0x%x, rxbb = %x\n", path,
+ rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, MASKDWORD),
+ rtw89_read_rf(rtwdev, path, RR_MOD, 0x003e0));
+
+ rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_OFF, 0x13);
+ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x011);
+ notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBRXK);
+ iqk_info->nb_rxcfir[path] =
+ rtw89_phy_read32_mask(rtwdev, R_RXIQC, MASKDWORD) | 0x2;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]S%x, NBRXK 0x8008 = 0x%x\n", path,
+ rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, MASKDWORD));
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, WBRXK 0x8008 = 0x%x\n",
+ path, rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, MASKDWORD));
+
+ if (!notready)
+ kfail = !!rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, B_NCTL_RPT_FLG);
+
+ if (kfail) {
+ rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8),
+ MASKDWORD, 0x40000002);
+ iqk_info->is_wb_rxiqk[path] = false;
+ } else {
+ iqk_info->is_wb_rxiqk[path] = false;
+ }
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]S%x, kfail = 0x%x, 0x8%x3c = 0x%x\n", path, kfail,
+ 1 << path, iqk_info->nb_rxcfir[path]);
+
+ return kfail;
+}
+
+static bool _iqk_2g_nbrxk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
+ u8 path)
+{
+ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
+ bool kfail = false;
+ bool notready;
+ u8 gp = 0x3;
+ u32 rf_0;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, gp = %x\n", path, gp);
+
+ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RGM, g_idxrxgain[gp]);
+ rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C2, g_idxattc2[gp]);
+ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_SEL, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G3, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_GP_V1, gp);
+
+ rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80013);
+ fsleep(10);
+ rf_0 = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK);
+ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF2, B_IQK_DIF2_RXPI, rf_0);
+ rtw89_phy_write32_mask(rtwdev, R_IQK_RXA, B_IQK_RXAGC, g_idxrxagc[gp]);
+ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x11);
+ notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXAGC);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]S%x, RXAGC 0x8008 = 0x%x, rxbb = %x\n",
+ path, rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, MASKDWORD),
+ rtw89_read_rf(rtwdev, path, RR_MOD, 0x003e0));
+
+ rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_OFF, 0x13);
+ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x011);
+ notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBRXK);
+ iqk_info->nb_rxcfir[path] =
+ rtw89_phy_read32_mask(rtwdev, R_RXIQC, MASKDWORD) | 0x2;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]S%x, NBRXK 0x8008 = 0x%x\n", path,
+ rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, MASKDWORD));
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, WBRXK 0x8008 = 0x%x\n",
+ path, rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, MASKDWORD));
+
+ if (!notready)
+ kfail = !!rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, B_NCTL_RPT_FLG);
+
+ if (kfail) {
+ rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8),
+ MASKDWORD, 0x40000002);
+ iqk_info->is_wb_rxiqk[path] = false;
+ } else {
+ iqk_info->is_wb_rxiqk[path] = false;
+ }
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]S%x, kfail = 0x%x, 0x8%x3c = 0x%x\n", path, kfail,
+ 1 << path, iqk_info->nb_rxcfir[path]);
+ return kfail;
+}
+
+static void _iqk_rxclk_setting(struct rtw89_dev *rtwdev, u8 path)
+{
+ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
+
+ rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_RXBB2_CKT, 0x1);
+
+ if (iqk_info->iqk_bw[path] == RTW89_CHANNEL_WIDTH_80)
+ rtw89_rfk_parser(rtwdev, &rtw8851b_iqk_rxclk_80_defs_tbl);
+ else
+ rtw89_rfk_parser(rtwdev, &rtw8851b_iqk_rxclk_others_defs_tbl);
+}
+
+static bool _txk_5g_group_sel(struct rtw89_dev *rtwdev,
+ enum rtw89_phy_idx phy_idx, u8 path)
+{
+ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
+ bool kfail = false;
+ bool notready;
+ u8 gp;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
+
+ for (gp = 0x0; gp < RTW8851B_TXK_GROUP_NR; gp++) {
+ rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, a_power_range[gp]);
+ rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, a_track_range[gp]);
+ rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, a_gain_bb[gp]);
+
+ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_SEL, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G3, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G2, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_GP, gp);
+ rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00);
+ rtw89_phy_write32_mask(rtwdev, R_KIP_IQP, MASKDWORD, a_itqt[gp]);
+
+ notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK);
+ iqk_info->nb_txcfir[path] =
+ rtw89_phy_read32_mask(rtwdev, R_TXIQC, MASKDWORD) | 0x2;
+
+ rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
+ MASKDWORD, a_itqt[gp]);
+ notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_TXK);
+ }
+
+ if (!notready)
+ kfail = !!rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, B_NCTL_RPT_FLG);
+
+ if (kfail) {
+ rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8),
+ MASKDWORD, iqk_info->nb_txcfir[path] | 0x2);
+ iqk_info->is_wb_txiqk[path] = false;
+ } else {
+ rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8),
+ MASKDWORD, 0x40000000);
+ iqk_info->is_wb_txiqk[path] = true;
+ }
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]S%x, kfail = 0x%x, 0x8%x38 = 0x%x\n", path, kfail,
+ 1 << path, iqk_info->nb_txcfir[path]);
+ return kfail;
+}
+
+static bool _txk_2g_group_sel(struct rtw89_dev *rtwdev,
+ enum rtw89_phy_idx phy_idx, u8 path)
+{
+ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
+ bool kfail = false;
+ bool notready;
+ u8 gp;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
+
+ for (gp = 0x0; gp < RTW8851B_TXK_GROUP_NR; gp++) {
+ rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, g_power_range[gp]);
+ rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, g_track_range[gp]);
+ rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, g_gain_bb[gp]);
+
+ rtw89_phy_write32_mask(rtwdev, R_KIP_IQP, MASKDWORD, g_itqt[gp]);
+ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_SEL, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G3, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G2, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_GP, gp);
+ rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00);
+
+ notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK);
+ iqk_info->nb_txcfir[path] =
+ rtw89_phy_read32_mask(rtwdev, R_TXIQC, MASKDWORD) | 0x2;
+
+ rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
+ MASKDWORD, g_itqt[gp]);
+ notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_TXK);
+ }
+
+ if (!notready)
+ kfail = !!rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, B_NCTL_RPT_FLG);
+
+ if (kfail) {
+ rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8),
+ MASKDWORD, iqk_info->nb_txcfir[path] | 0x2);
+ iqk_info->is_wb_txiqk[path] = false;
+ } else {
+ rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8),
+ MASKDWORD, 0x40000000);
+ iqk_info->is_wb_txiqk[path] = true;
+ }
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]S%x, kfail = 0x%x, 0x8%x38 = 0x%x\n", path, kfail,
+ 1 << path, iqk_info->nb_txcfir[path]);
+ return kfail;
+}
+
+static bool _iqk_5g_nbtxk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
+ u8 path)
+{
+ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
+ bool kfail = false;
+ bool notready;
+ u8 gp;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
+
+ for (gp = 0x0; gp < RTW8851B_TXK_GROUP_NR; gp++) {
+ rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, a_power_range[gp]);
+ rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, a_track_range[gp]);
+ rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, a_gain_bb[gp]);
+
+ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_SEL, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G3, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G2, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_GP, gp);
+ rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00);
+ rtw89_phy_write32_mask(rtwdev, R_KIP_IQP, MASKDWORD, a_itqt[gp]);
+
+ notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK);
+ iqk_info->nb_txcfir[path] =
+ rtw89_phy_read32_mask(rtwdev, R_TXIQC, MASKDWORD) | 0x2;
+ }
+
+ if (!notready)
+ kfail = !!rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, B_NCTL_RPT_FLG);
+
+ if (kfail) {
+ rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8),
+ MASKDWORD, 0x40000002);
+ iqk_info->is_wb_rxiqk[path] = false;
+ } else {
+ iqk_info->is_wb_rxiqk[path] = false;
+ }
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]S%x, kfail = 0x%x, 0x8%x38 = 0x%x\n", path, kfail,
+ 1 << path, iqk_info->nb_txcfir[path]);
+ return kfail;
+}
+
+static bool _iqk_2g_nbtxk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
+ u8 path)
+{
+ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
+ bool kfail = false;
+ bool notready;
+ u8 gp;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
+
+ for (gp = 0x0; gp < RTW8851B_TXK_GROUP_NR; gp++) {
+ rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, g_power_range[gp]);
+ rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, g_track_range[gp]);
+ rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, g_gain_bb[gp]);
+
+ rtw89_phy_write32_mask(rtwdev, R_KIP_IQP, MASKDWORD, g_itqt[gp]);
+ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_SEL, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G3, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G2, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_GP, gp);
+ rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00);
+
+ notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK);
+ iqk_info->nb_txcfir[path] =
+ rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8),
+ MASKDWORD) | 0x2;
+ }
+
+ if (!notready)
+ kfail = !!rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, B_NCTL_RPT_FLG);
+
+ if (kfail) {
+ rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8),
+ MASKDWORD, 0x40000002);
+ iqk_info->is_wb_rxiqk[path] = false;
+ } else {
+ iqk_info->is_wb_rxiqk[path] = false;
+ }
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]S%x, kfail = 0x%x, 0x8%x38 = 0x%x\n", path, kfail,
+ 1 << path, iqk_info->nb_txcfir[path]);
+ return kfail;
+}
+
+static bool _iqk_2g_lok(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
+ u8 path)
+{
+ static const u32 g_txbb[RTW8851B_LOK_GRAM] = {
+ 0x02, 0x06, 0x0a, 0x0c, 0x0e, 0x10, 0x12, 0x14, 0x16, 0x17};
+ static const u32 g_itqt[RTW8851B_LOK_GRAM] = {
+ 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x12, 0x12, 0x12, 0x1b};
+ static const u32 g_wa[RTW8851B_LOK_GRAM] = {
+ 0x00, 0x04, 0x08, 0x0c, 0x0e, 0x10, 0x12, 0x14, 0x16, 0x17};
+ bool fail = false;
+ u8 i;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
+
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTDBG, RR_LUTDBG_LOK, 0x0);
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_TXIG, RR_TXIG_GR0, 0x0);
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_TXIG, RR_TXIG_GR1, 0x6);
+
+ for (i = 0; i < RTW8851B_LOK_GRAM; i++) {
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_TXIG, RR_TXIG_TG, g_txbb[i]);
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWA, RR_LUTWA_M1, g_wa[i]);
+ rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_IQK_RFC_ON, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_KIP_IQP, B_KIP_IQP_IQSW, g_itqt[i]);
+ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x021);
+ rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD,
+ 0x00000109 | (1 << (4 + path)));
+ fail |= _iqk_check_cal(rtwdev, path);
+
+ rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00);
+ rtw89_phy_write32_mask(rtwdev, R_KIP_IQP, B_KIP_IQP_IQSW, g_itqt[i]);
+ rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD,
+ 0x00000309 | (1 << (4 + path)));
+ fail |= _iqk_check_cal(rtwdev, path);
+
+ rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00);
+ rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_IQK_RFC_ON, 0x0);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]S0, i = %x, 0x8[19:15] = 0x%x,0x8[09:05] = 0x%x\n", i,
+ rtw89_read_rf(rtwdev, RF_PATH_A, RR_DTXLOK, 0xf8000),
+ rtw89_read_rf(rtwdev, RF_PATH_A, RR_DTXLOK, 0x003e0));
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]S0, i = %x, 0x9[19:16] = 0x%x,0x9[09:06] = 0x%x\n", i,
+ rtw89_read_rf(rtwdev, RF_PATH_A, RR_RSV2, 0xf0000),
+ rtw89_read_rf(rtwdev, RF_PATH_A, RR_RSV2, 0x003c0));
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]S0, i = %x, 0x58 = %x\n", i,
+ rtw89_read_rf(rtwdev, RF_PATH_A, RR_TXMO, RFREG_MASK));
+ }
+
+ return fail;
+}
+
+static bool _iqk_5g_lok(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
+ u8 path)
+{
+ static const u32 a_txbb[RTW8851B_LOK_GRAM] = {
+ 0x02, 0x06, 0x0a, 0x0c, 0x0e, 0x10, 0x12, 0x14, 0x16, 0x17};
+ static const u32 a_itqt[RTW8851B_LOK_GRAM] = {
+ 0x09, 0x09, 0x09, 0x12, 0x12, 0x12, 0x1b, 0x1b, 0x1b, 0x1b};
+ static const u32 a_wa[RTW8851B_LOK_GRAM] = {
+ 0x80, 0x84, 0x88, 0x8c, 0x8e, 0x90, 0x92, 0x94, 0x96, 0x97};
+ bool fail = false;
+ u8 i;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
+
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTDBG, RR_LUTDBG_LOK, 0x0);
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_TXIG, RR_TXIG_GR0, 0x0);
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_TXIG, RR_TXIG_GR1, 0x7);
+
+ for (i = 0; i < RTW8851B_LOK_GRAM; i++) {
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_TXIG, RR_TXIG_TG, a_txbb[i]);
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWA, RR_LUTWA_M1, a_wa[i]);
+ rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_IQK_RFC_ON, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_KIP_IQP, B_KIP_IQP_IQSW, a_itqt[i]);
+ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x021);
+ rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD,
+ 0x00000109 | (1 << (4 + path)));
+ fail |= _iqk_check_cal(rtwdev, path);
+
+ rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00);
+ rtw89_phy_write32_mask(rtwdev, R_KIP_IQP, B_KIP_IQP_IQSW, a_itqt[i]);
+ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x021);
+ rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD,
+ 0x00000309 | (1 << (4 + path)));
+ fail |= _iqk_check_cal(rtwdev, path);
+
+ rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00);
+ rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_IQK_RFC_ON, 0x0);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]S0, i = %x, 0x8[19:15] = 0x%x,0x8[09:05] = 0x%x\n", i,
+ rtw89_read_rf(rtwdev, RF_PATH_A, RR_DTXLOK, 0xf8000),
+ rtw89_read_rf(rtwdev, RF_PATH_A, RR_DTXLOK, 0x003e0));
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]S0, i = %x, 0x9[19:16] = 0x%x,0x9[09:06] = 0x%x\n", i,
+ rtw89_read_rf(rtwdev, RF_PATH_A, RR_RSV2, 0xf0000),
+ rtw89_read_rf(rtwdev, RF_PATH_A, RR_RSV2, 0x003c0));
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]S0, i = %x, 0x58 = %x\n", i,
+ rtw89_read_rf(rtwdev, RF_PATH_A, RR_TXMO, RFREG_MASK));
+ }
+
+ return fail;
+}
+
+static void _iqk_txk_setting(struct rtw89_dev *rtwdev, u8 path)
+{
+ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
+
+ switch (iqk_info->iqk_band[path]) {
+ case RTW89_BAND_2G:
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]RTW89_BAND_2G\n");
+ rtw89_rfk_parser(rtwdev, &rtw8851b_iqk_txk_2ghz_defs_tbl);
+ break;
+ case RTW89_BAND_5G:
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]RTW89_BAND_5G\n");
+ rtw89_rfk_parser(rtwdev, &rtw8851b_iqk_txk_5ghz_defs_tbl);
+ break;
+ default:
+ break;
+ }
+}
+
+#define IQK_LOK_RETRY 1
+
+static void _iqk_by_path(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
+ u8 path)
+{
+ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
+ bool lok_is_fail;
+ u8 i;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
+
+ for (i = 0; i < IQK_LOK_RETRY; i++) {
+ _iqk_txk_setting(rtwdev, path);
+ if (iqk_info->iqk_band[path] == RTW89_BAND_2G)
+ lok_is_fail = _iqk_2g_lok(rtwdev, phy_idx, path);
+ else
+ lok_is_fail = _iqk_5g_lok(rtwdev, phy_idx, path);
+
+ if (!lok_is_fail)
+ break;
+ }
+
+ if (iqk_info->is_nbiqk) {
+ if (iqk_info->iqk_band[path] == RTW89_BAND_2G)
+ iqk_info->iqk_tx_fail[0][path] =
+ _iqk_2g_nbtxk(rtwdev, phy_idx, path);
+ else
+ iqk_info->iqk_tx_fail[0][path] =
+ _iqk_5g_nbtxk(rtwdev, phy_idx, path);
+ } else {
+ if (iqk_info->iqk_band[path] == RTW89_BAND_2G)
+ iqk_info->iqk_tx_fail[0][path] =
+ _txk_2g_group_sel(rtwdev, phy_idx, path);
+ else
+ iqk_info->iqk_tx_fail[0][path] =
+ _txk_5g_group_sel(rtwdev, phy_idx, path);
+ }
+
+ _iqk_rxclk_setting(rtwdev, path);
+ _iqk_rxk_setting(rtwdev, path);
+ _adc_fifo_rst(rtwdev, phy_idx, path);
+
+ if (iqk_info->is_nbiqk) {
+ if (iqk_info->iqk_band[path] == RTW89_BAND_2G)
+ iqk_info->iqk_rx_fail[0][path] =
+ _iqk_2g_nbrxk(rtwdev, phy_idx, path);
+ else
+ iqk_info->iqk_rx_fail[0][path] =
+ _iqk_5g_nbrxk(rtwdev, phy_idx, path);
+ } else {
+ if (iqk_info->iqk_band[path] == RTW89_BAND_2G)
+ iqk_info->iqk_rx_fail[0][path] =
+ _rxk_2g_group_sel(rtwdev, phy_idx, path);
+ else
+ iqk_info->iqk_rx_fail[0][path] =
+ _rxk_5g_group_sel(rtwdev, phy_idx, path);
+ }
+}
+
+static void _rfk_backup_bb_reg(struct rtw89_dev *rtwdev,
+ u32 backup_bb_reg_val[])
+{
+ u32 i;
+
+ for (i = 0; i < BACKUP_BB_REGS_NR; i++) {
+ backup_bb_reg_val[i] =
+ rtw89_phy_read32_mask(rtwdev, rtw8851b_backup_bb_regs[i],
+ MASKDWORD);
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[RFK]backup bb reg : %x, value =%x\n",
+ rtw8851b_backup_bb_regs[i], backup_bb_reg_val[i]);
+ }
+}
+
+static void _rfk_backup_rf_reg(struct rtw89_dev *rtwdev,
+ u32 backup_rf_reg_val[], u8 rf_path)
+{
+ u32 i;
+
+ for (i = 0; i < BACKUP_RF_REGS_NR; i++) {
+ backup_rf_reg_val[i] =
+ rtw89_read_rf(rtwdev, rf_path,
+ rtw8851b_backup_rf_regs[i], RFREG_MASK);
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[RFK]backup rf S%d reg : %x, value =%x\n", rf_path,
+ rtw8851b_backup_rf_regs[i], backup_rf_reg_val[i]);
+ }
+}
+
+static void _rfk_restore_bb_reg(struct rtw89_dev *rtwdev,
+ const u32 backup_bb_reg_val[])
+{
+ u32 i;
+
+ for (i = 0; i < BACKUP_BB_REGS_NR; i++) {
+ rtw89_phy_write32_mask(rtwdev, rtw8851b_backup_bb_regs[i],
+ MASKDWORD, backup_bb_reg_val[i]);
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[RFK]restore bb reg : %x, value =%x\n",
+ rtw8851b_backup_bb_regs[i], backup_bb_reg_val[i]);
+ }
+}
+
+static void _rfk_restore_rf_reg(struct rtw89_dev *rtwdev,
+ const u32 backup_rf_reg_val[], u8 rf_path)
+{
+ u32 i;
+
+ for (i = 0; i < BACKUP_RF_REGS_NR; i++) {
+ rtw89_write_rf(rtwdev, rf_path, rtw8851b_backup_rf_regs[i],
+ RFREG_MASK, backup_rf_reg_val[i]);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[RFK]restore rf S%d reg: %x, value =%x\n", rf_path,
+ rtw8851b_backup_rf_regs[i], backup_rf_reg_val[i]);
+ }
+}
+
+static void _iqk_get_ch_info(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
+ u8 path)
+{
+ const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
+ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
+ u8 idx = 0;
+
+ iqk_info->iqk_band[path] = chan->band_type;
+ iqk_info->iqk_bw[path] = chan->band_width;
+ iqk_info->iqk_ch[path] = chan->channel;
+ iqk_info->iqk_table_idx[path] = idx;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d (PHY%d): / DBCC %s/ %s/ CH%d/ %s\n",
+ path, phy, rtwdev->dbcc_en ? "on" : "off",
+ iqk_info->iqk_band[path] == 0 ? "2G" :
+ iqk_info->iqk_band[path] == 1 ? "5G" : "6G",
+ iqk_info->iqk_ch[path],
+ iqk_info->iqk_bw[path] == 0 ? "20M" :
+ iqk_info->iqk_bw[path] == 1 ? "40M" : "80M");
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]times = 0x%x, ch =%x\n",
+ iqk_info->iqk_times, idx);
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, iqk_info->syn1to2= 0x%x\n",
+ path, iqk_info->syn1to2);
+}
+
+static void _iqk_start_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
+ u8 path)
+{
+ _iqk_by_path(rtwdev, phy_idx, path);
+}
+
+static void _iqk_restore(struct rtw89_dev *rtwdev, u8 path)
+{
+ bool fail;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
+
+ rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, 0x00001219);
+ fsleep(10);
+ fail = _iqk_check_cal(rtwdev, path);
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] restore fail=%d\n", fail);
+
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RR_LUTWE_LOK, 0x0);
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTDBG, RR_LUTDBG_TIA, 0x0);
+
+ rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00);
+ rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000000);
+ rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x80000000);
+}
+
+static void _iqk_afebb_restore(struct rtw89_dev *rtwdev,
+ enum rtw89_phy_idx phy_idx, u8 path)
+{
+ rtw89_rfk_parser(rtwdev, &rtw8851b_iqk_afebb_restore_defs_tbl);
+}
+
+static void _iqk_preset(struct rtw89_dev *rtwdev, u8 path)
+{
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
+
+ rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000080);
+ rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x81ff010a);
+}
+
+static void _iqk_macbb_setting(struct rtw89_dev *rtwdev,
+ enum rtw89_phy_idx phy_idx, u8 path)
+{
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
+
+ rtw89_rfk_parser(rtwdev, &rtw8851b_iqk_macbb_defs_tbl);
+}
+
+static void _iqk_init(struct rtw89_dev *rtwdev)
+{
+ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
+ u8 idx, path;
+
+ rtw89_phy_write32_mask(rtwdev, R_IQKINF, MASKDWORD, 0x0);
+
+ if (iqk_info->is_iqk_init)
+ return;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
+
+ iqk_info->is_iqk_init = true;
+ iqk_info->is_nbiqk = false;
+ iqk_info->iqk_fft_en = false;
+ iqk_info->iqk_sram_en = false;
+ iqk_info->iqk_cfir_en = false;
+ iqk_info->iqk_xym_en = false;
+ iqk_info->iqk_times = 0x0;
+
+ for (idx = 0; idx < RTW89_IQK_CHS_NR; idx++) {
+ iqk_info->iqk_channel[idx] = 0x0;
+ for (path = 0; path < RF_PATH_NUM_8851B; path++) {
+ iqk_info->lok_cor_fail[idx][path] = false;
+ iqk_info->lok_fin_fail[idx][path] = false;
+ iqk_info->iqk_tx_fail[idx][path] = false;
+ iqk_info->iqk_rx_fail[idx][path] = false;
+ iqk_info->iqk_table_idx[path] = 0x0;
+ }
+ }
+}
+
+static void _doiqk(struct rtw89_dev *rtwdev, bool force,
+ enum rtw89_phy_idx phy_idx, u8 path)
+{
+ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
+ u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, RF_AB);
+ u32 backup_rf_val[RTW8851B_IQK_SS][BACKUP_RF_REGS_NR];
+ u32 backup_bb_val[BACKUP_BB_REGS_NR];
+
+ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK,
+ BTC_WRFK_ONESHOT_START);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[IQK]==========IQK start!!!!!==========\n");
+ iqk_info->iqk_times++;
+ iqk_info->version = RTW8851B_IQK_VER;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]Test Ver 0x%x\n", iqk_info->version);
+ _iqk_get_ch_info(rtwdev, phy_idx, path);
+
+ _rfk_backup_bb_reg(rtwdev, &backup_bb_val[0]);
+ _rfk_backup_rf_reg(rtwdev, &backup_rf_val[path][0], path);
+ _iqk_macbb_setting(rtwdev, phy_idx, path);
+ _iqk_preset(rtwdev, path);
+ _iqk_start_iqk(rtwdev, phy_idx, path);
+ _iqk_restore(rtwdev, path);
+ _iqk_afebb_restore(rtwdev, phy_idx, path);
+ _rfk_restore_bb_reg(rtwdev, &backup_bb_val[0]);
+ _rfk_restore_rf_reg(rtwdev, &backup_rf_val[path][0], path);
+
+ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK,
+ BTC_WRFK_ONESHOT_STOP);
+}
+
+static void _iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, bool force)
+{
+ _doiqk(rtwdev, force, phy_idx, RF_PATH_A);
+}
+
+static void _dpk_bkup_kip(struct rtw89_dev *rtwdev, const u32 *reg,
+ u32 reg_bkup[][DPK_KIP_REG_NUM_8851B], u8 path)
+{
+ u8 i;
+
+ for (i = 0; i < DPK_KIP_REG_NUM_8851B; i++) {
+ reg_bkup[path][i] =
+ rtw89_phy_read32_mask(rtwdev, reg[i] + (path << 8), MASKDWORD);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Backup 0x%x = %x\n",
+ reg[i] + (path << 8), reg_bkup[path][i]);
+ }
+}
+
+static void _dpk_bkup_rf(struct rtw89_dev *rtwdev, const u32 *rf_reg,
+ u32 rf_bkup[][DPK_RF_REG_NUM_8851B], u8 path)
+{
+ u8 i;
+
+ for (i = 0; i < DPK_RF_REG_NUM_8851B; i++) {
+ rf_bkup[path][i] = rtw89_read_rf(rtwdev, path, rf_reg[i], RFREG_MASK);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Backup RF S%d 0x%x = %x\n",
+ path, rf_reg[i], rf_bkup[path][i]);
+ }
+}
+
+static void _dpk_reload_kip(struct rtw89_dev *rtwdev, const u32 *reg,
+ u32 reg_bkup[][DPK_KIP_REG_NUM_8851B], u8 path)
+{
+ u8 i;
+
+ for (i = 0; i < DPK_KIP_REG_NUM_8851B; i++) {
+ rtw89_phy_write32_mask(rtwdev, reg[i] + (path << 8), MASKDWORD,
+ reg_bkup[path][i]);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[DPK] Reload 0x%x = %x\n",
+ reg[i] + (path << 8), reg_bkup[path][i]);
+ }
+}
+
+static void _dpk_reload_rf(struct rtw89_dev *rtwdev, const u32 *rf_reg,
+ u32 rf_bkup[][DPK_RF_REG_NUM_8851B], u8 path)
+{
+ u8 i;
+
+ for (i = 0; i < DPK_RF_REG_NUM_8851B; i++) {
+ rtw89_write_rf(rtwdev, path, rf_reg[i], RFREG_MASK, rf_bkup[path][i]);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[DPK] Reload RF S%d 0x%x = %x\n", path,
+ rf_reg[i], rf_bkup[path][i]);
+ }
+}
+
+static void _dpk_one_shot(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
+ enum rtw89_rf_path path, enum dpk_id id)
+{
+ u16 dpk_cmd;
+ u32 val;
+ int ret;
+
+ dpk_cmd = ((id << 8) | (0x19 + path * 0x12));
+ rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, dpk_cmd);
+
+ ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x55,
+ 10, 20000, false,
+ rtwdev, 0xbff8, MASKBYTE0);
+ if (ret)
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] one-shot 1 timeout\n");
+
+ udelay(1);
+
+ ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x8000,
+ 1, 2000, false,
+ rtwdev, R_RPT_COM, MASKLWORD);
+ if (ret)
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] one-shot 2 timeout\n");
+
+ rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, MASKBYTE0, 0x0);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[DPK] one-shot for %s = 0x%04x\n",
+ id == 0x28 ? "KIP_PRESET" :
+ id == 0x29 ? "DPK_TXAGC" :
+ id == 0x2a ? "DPK_RXAGC" :
+ id == 0x2b ? "SYNC" :
+ id == 0x2c ? "GAIN_LOSS" :
+ id == 0x2d ? "MDPK_IDL" :
+ id == 0x2f ? "DPK_GAIN_NORM" :
+ id == 0x31 ? "KIP_RESTORE" :
+ id == 0x6 ? "LBK_RXIQK" : "Unknown id",
+ dpk_cmd);
+}
+
+static void _dpk_onoff(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
+ bool off)
+{
+ struct rtw89_dpk_info *dpk = &rtwdev->dpk;
+ u8 kidx = dpk->cur_idx[path];
+ u8 off_reverse = off ? 0 : 1;
+ u8 val;
+
+ val = dpk->is_dpk_enable * off_reverse * dpk->bp[path][kidx].path_ok;
+
+ rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
+ 0xf0000000, val);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s !!!\n", path,
+ kidx, val == 0 ? "disable" : "enable");
+}
+
+static void _dpk_init(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
+{
+ struct rtw89_dpk_info *dpk = &rtwdev->dpk;
+
+ u8 kidx = dpk->cur_idx[path];
+
+ dpk->bp[path][kidx].path_ok = 0;
+}
+
+static void _dpk_information(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
+ enum rtw89_rf_path path)
+{
+ const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
+ struct rtw89_dpk_info *dpk = &rtwdev->dpk;
+
+ u8 kidx = dpk->cur_idx[path];
+
+ dpk->bp[path][kidx].band = chan->band_type;
+ dpk->bp[path][kidx].ch = chan->band_width;
+ dpk->bp[path][kidx].bw = chan->channel;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[DPK] S%d[%d] (PHY%d): TSSI %s/ DBCC %s/ %s/ CH%d/ %s\n",
+ path, dpk->cur_idx[path], phy,
+ rtwdev->is_tssi_mode[path] ? "on" : "off",
+ rtwdev->dbcc_en ? "on" : "off",
+ dpk->bp[path][kidx].band == 0 ? "2G" :
+ dpk->bp[path][kidx].band == 1 ? "5G" : "6G",
+ dpk->bp[path][kidx].ch,
+ dpk->bp[path][kidx].bw == 0 ? "20M" :
+ dpk->bp[path][kidx].bw == 1 ? "40M" :
+ dpk->bp[path][kidx].bw == 2 ? "80M" : "160M");
+}
+
+static void _dpk_rxagc_onoff(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
+ bool turn_on)
+{
+ if (path == RF_PATH_A)
+ rtw89_phy_write32_mask(rtwdev, R_P0_AGC_CTL, B_P0_AGC_EN, turn_on);
+ else
+ rtw89_phy_write32_mask(rtwdev, R_P1_AGC_CTL, B_P1_AGC_EN, turn_on);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d RXAGC is %s\n", path,
+ turn_on ? "turn_on" : "turn_off");
+}
+
+static void _dpk_bb_afe_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
+{
+ rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(16 + path), 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(20 + path), 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(24 + path), 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(28 + path), 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13), MASKDWORD, 0xd801dffd);
+
+ rtw89_rfk_parser(rtwdev, &rtw8851b_iqk_bb_afe_defs_tbl);
+
+ rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(20 + path), 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(28 + path), 0x1);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d BB/AFE setting\n", path);
+}
+
+static void _dpk_bb_afe_restore(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
+{
+ rtw89_phy_write32_mask(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(16 + path), 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(20 + path), 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(24 + path), 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(28 + path), 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13), MASKDWORD, 0x00000000);
+ rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13), B_P0_TXCK_ALL, 0x00);
+ rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(16 + path), 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(24 + path), 0x0);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d BB/AFE restore\n", path);
+}
+
+static void _dpk_tssi_pause(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
+ bool is_pause)
+{
+ rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK + (path << 13),
+ B_P0_TSSI_TRK_EN, is_pause);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d TSSI %s\n", path,
+ is_pause ? "pause" : "resume");
+}
+
+static void _dpk_tpg_sel(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx)
+{
+ struct rtw89_dpk_info *dpk = &rtwdev->dpk;
+
+ if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80) {
+ rtw89_phy_write32_mask(rtwdev, R_TPG_MOD, B_TPG_MOD_F, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_TPG_SEL, MASKDWORD, 0xffe0fa00);
+ } else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40) {
+ rtw89_phy_write32_mask(rtwdev, R_TPG_MOD, B_TPG_MOD_F, 0x2);
+ rtw89_phy_write32_mask(rtwdev, R_TPG_SEL, MASKDWORD, 0xff4009e0);
+ } else {
+ rtw89_phy_write32_mask(rtwdev, R_TPG_MOD, B_TPG_MOD_F, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_TPG_SEL, MASKDWORD, 0xf9f007d0);
+ }
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] TPG Select for %s\n",
+ dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80 ? "80M" :
+ dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40 ? "40M" : "20M");
+}
+
+static void _dpk_txpwr_bb_force(struct rtw89_dev *rtwdev,
+ enum rtw89_rf_path path, bool force)
+{
+ rtw89_phy_write32_mask(rtwdev, R_TXPWRB + (path << 13), B_TXPWRB_ON, force);
+ rtw89_phy_write32_mask(rtwdev, R_TXPWRB_H + (path << 13), B_TXPWRB_RDY, force);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d txpwr_bb_force %s\n",
+ path, force ? "on" : "off");
+}
+
+static void _dpk_kip_pwr_clk_onoff(struct rtw89_dev *rtwdev, bool turn_on)
+{
+ if (turn_on) {
+ rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000080);
+ rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x807f030a);
+ } else {
+ rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000000);
+ rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x80000000);
+ rtw89_phy_write32_mask(rtwdev, R_DPK_WR, BIT(18), 0x1);
+ }
+}
+
+static void _dpk_kip_control_rfc(struct rtw89_dev *rtwdev,
+ enum rtw89_rf_path path, bool ctrl_by_kip)
+{
+ rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13),
+ B_IQK_RFC_ON, ctrl_by_kip);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] RFC is controlled by %s\n",
+ ctrl_by_kip ? "KIP" : "BB");
+}
+
+static void _dpk_kip_preset(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
+ enum rtw89_rf_path path, u8 kidx)
+{
+ rtw89_phy_write32_mask(rtwdev, R_KIP_MOD, B_KIP_MOD,
+ rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK));
+ rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
+ B_DPD_SEL, 0x01);
+
+ _dpk_kip_control_rfc(rtwdev, path, true);
+ _dpk_one_shot(rtwdev, phy, path, D_KIP_PRESET);
+}
+
+static void _dpk_kip_restore(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
+ enum rtw89_rf_path path)
+{
+ _dpk_one_shot(rtwdev, phy, path, D_KIP_RESTORE);
+ _dpk_kip_control_rfc(rtwdev, path, false);
+ _dpk_txpwr_bb_force(rtwdev, path, false);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d restore KIP\n", path);
+}
+
+static void _dpk_kset_query(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
+{
+ struct rtw89_dpk_info *dpk = &rtwdev->dpk;
+
+ rtw89_phy_write32_mask(rtwdev, R_KIP_RPT + (path << 8), B_KIP_RPT_SEL, 0x10);
+
+ dpk->cur_k_set =
+ rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8), B_RPT_PER_KSET) - 1;
+}
+
+static void _dpk_para_query(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx)
+{
+ static const u32 reg[RTW89_DPK_BKUP_NUM][DPK_KSET_NUM] = {
+ {0x8190, 0x8194, 0x8198, 0x81a4},
+ {0x81a8, 0x81c4, 0x81c8, 0x81e8}
+ };
+ struct rtw89_dpk_info *dpk = &rtwdev->dpk;
+ u8 cur_k_set = dpk->cur_k_set;
+ u32 para;
+
+ if (cur_k_set >= DPK_KSET_NUM) {
+ rtw89_warn(rtwdev, "DPK cur_k_set = %d\n", cur_k_set);
+ cur_k_set = 2;
+ }
+
+ para = rtw89_phy_read32_mask(rtwdev, reg[kidx][cur_k_set] + (path << 8),
+ MASKDWORD);
+
+ dpk->bp[path][kidx].txagc_dpk = (para >> 10) & 0x3f;
+ dpk->bp[path][kidx].ther_dpk = (para >> 26) & 0x3f;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[DPK] thermal/ txagc_RF (K%d) = 0x%x/ 0x%x\n",
+ dpk->cur_k_set, dpk->bp[path][kidx].ther_dpk,
+ dpk->bp[path][kidx].txagc_dpk);
+}
+
+static bool _dpk_sync_check(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx)
+{
+ struct rtw89_dpk_info *dpk = &rtwdev->dpk;
+ u8 corr_val, corr_idx, rxbb;
+ u16 dc_i, dc_q;
+ u8 rxbb_ov;
+
+ rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x0);
+
+ corr_idx = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_CORI);
+ corr_val = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_CORV);
+ dpk->corr_idx[path][kidx] = corr_idx;
+ dpk->corr_val[path][kidx] = corr_val;
+
+ rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x9);
+
+ dc_i = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCI);
+ dc_q = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCQ);
+
+ dc_i = abs(sign_extend32(dc_i, 11));
+ dc_q = abs(sign_extend32(dc_q, 11));
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[DPK] S%d Corr_idx/ Corr_val /DC I/Q, = %d / %d / %d / %d\n",
+ path, corr_idx, corr_val, dc_i, dc_q);
+
+ dpk->dc_i[path][kidx] = dc_i;
+ dpk->dc_q[path][kidx] = dc_q;
+
+ rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x8);
+ rxbb = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_RXBB);
+
+ rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x31);
+ rxbb_ov = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_RXOV);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[DPK] S%d RXBB/ RXAGC_done /RXBB_ovlmt = %d / %d / %d\n",
+ path, rxbb,
+ rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DONE),
+ rxbb_ov);
+
+ if (dc_i > 200 || dc_q > 200 || corr_val < 170)
+ return true;
+ else
+ return false;
+}
+
+static void _dpk_kip_set_txagc(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
+ enum rtw89_rf_path path, u8 dbm,
+ bool set_from_bb)
+{
+ if (set_from_bb) {
+ dbm = clamp_t(u8, dbm, 7, 24);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[DPK] set S%d txagc to %ddBm\n", path, dbm);
+ rtw89_phy_write32_mask(rtwdev, R_TXPWRB + (path << 13),
+ B_TXPWRB_VAL, dbm << 2);
+ }
+
+ _dpk_one_shot(rtwdev, phy, path, D_TXAGC);
+ _dpk_kset_query(rtwdev, path);
+}
+
+static bool _dpk_kip_set_rxagc(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
+ enum rtw89_rf_path path, u8 kidx)
+{
+ _dpk_kip_control_rfc(rtwdev, path, false);
+ rtw89_phy_write32_mask(rtwdev, R_KIP_MOD, B_KIP_MOD,
+ rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK));
+ _dpk_kip_control_rfc(rtwdev, path, true);
+
+ _dpk_one_shot(rtwdev, phy, path, D_RXAGC);
+ return _dpk_sync_check(rtwdev, path, kidx);
+}
+
+static void _dpk_lbk_rxiqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
+ enum rtw89_rf_path path)
+{
+ u32 rf_11, reg_81cc;
+ u8 cur_rxbb;
+
+ rtw89_phy_write32_mask(rtwdev, R_DPD_V1 + (path << 8), B_DPD_LBK, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_MDPK_RX_DCK, B_MDPK_RX_DCK_EN, 0x1);
+
+ _dpk_kip_control_rfc(rtwdev, path, false);
+
+ cur_rxbb = rtw89_read_rf(rtwdev, path, RR_MOD, RR_MOD_RXB);
+ rf_11 = rtw89_read_rf(rtwdev, path, RR_TXIG, RFREG_MASK);
+ reg_81cc = rtw89_phy_read32_mask(rtwdev, R_KIP_IQP + (path << 8),
+ B_KIP_IQP_SW);
+
+ rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 0x0);
+ rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 0x3);
+ rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0xd);
+ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RXB, 0x1f);
+
+ rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW, 0x12);
+ rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_SW, 0x3);
+
+ _dpk_kip_control_rfc(rtwdev, path, true);
+
+ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, MASKDWORD, 0x00250025);
+
+ _dpk_one_shot(rtwdev, phy, path, LBK_RXIQK);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d LBK RXIQC = 0x%x\n", path,
+ rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD));
+
+ _dpk_kip_control_rfc(rtwdev, path, false);
+
+ rtw89_write_rf(rtwdev, path, RR_TXIG, RFREG_MASK, rf_11);
+ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RXB, cur_rxbb);
+ rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_SW, reg_81cc);
+
+ rtw89_phy_write32_mask(rtwdev, R_MDPK_RX_DCK, B_MDPK_RX_DCK_EN, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_KPATH_CFG, B_KPATH_CFG_ED, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_DI, 0x1);
+
+ _dpk_kip_control_rfc(rtwdev, path, true);
+}
+
+static void _dpk_rf_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx)
+{
+ struct rtw89_dpk_info *dpk = &rtwdev->dpk;
+
+ if (dpk->bp[path][kidx].band == RTW89_BAND_2G) {
+ rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, 0x50521);
+ rtw89_write_rf(rtwdev, path, RR_MOD_V1, RR_MOD_MASK, RF_DPK);
+ rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_ATTC, 0x0);
+ rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_ATTR, 0x7);
+ } else {
+ rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK,
+ 0x50521 | BIT(rtwdev->dbcc_en));
+ rtw89_write_rf(rtwdev, path, RR_MOD_V1, RR_MOD_MASK, RF_DPK);
+ rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RAA2_SATT, 0x3);
+ }
+
+ rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_BW, 0x1);
+ rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_TXBB, dpk->bp[path][kidx].bw + 1);
+ rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_RXBB, 0x0);
+ rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_RXBB2_EBW, 0x0);
+}
+
+static void _dpk_bypass_rxiqc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
+{
+ rtw89_phy_write32_mask(rtwdev, R_DPD_V1 + (path << 8), B_DPD_LBK, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD, 0x40000002);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Bypass RXIQC\n");
+}
+
+static u16 _dpk_dgain_read(struct rtw89_dev *rtwdev)
+{
+ u16 dgain;
+
+ rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x0);
+ dgain = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCI);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] DGain = 0x%x\n", dgain);
+
+ return dgain;
+}
+
+static u8 _dpk_gainloss_read(struct rtw89_dev *rtwdev)
+{
+ u8 result;
+
+ rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x6);
+ rtw89_phy_write32_mask(rtwdev, R_DPK_CFG2, B_DPK_CFG2_ST, 0x1);
+ result = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_GL);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] tmp GL = %d\n", result);
+
+ return result;
+}
+
+static u8 _dpk_gainloss(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
+ enum rtw89_rf_path path, u8 kidx)
+{
+ _dpk_one_shot(rtwdev, phy, path, D_GAIN_LOSS);
+ _dpk_kip_set_txagc(rtwdev, phy, path, 0xff, false);
+
+ rtw89_phy_write32_mask(rtwdev, R_DPK_GL + (path << 8), B_DPK_GL_A1, 0xf078);
+ rtw89_phy_write32_mask(rtwdev, R_DPK_GL + (path << 8), B_DPK_GL_A0, 0x0);
+
+ return _dpk_gainloss_read(rtwdev);
+}
+
+static u8 _dpk_pas_read(struct rtw89_dev *rtwdev, u8 is_check)
+{
+ u32 val1_i = 0, val1_q = 0, val2_i = 0, val2_q = 0;
+ u32 val1_sqrt_sum, val2_sqrt_sum;
+ u8 i;
+
+ rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKBYTE2, 0x06);
+ rtw89_phy_write32_mask(rtwdev, R_DPK_CFG2, B_DPK_CFG2_ST, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE2, 0x08);
+
+ if (is_check) {
+ rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE3, 0x00);
+ val1_i = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKHWORD);
+ val1_i = abs(sign_extend32(val1_i, 11));
+ val1_q = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKLWORD);
+ val1_q = abs(sign_extend32(val1_q, 11));
+
+ rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE3, 0x1f);
+ val2_i = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKHWORD);
+ val2_i = abs(sign_extend32(val2_i, 11));
+ val2_q = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKLWORD);
+ val2_q = abs(sign_extend32(val2_q, 11));
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] PAS_delta = 0x%x\n",
+ phy_div(val1_i * val1_i + val1_q * val1_q,
+ val2_i * val2_i + val2_q * val2_q));
+ } else {
+ for (i = 0; i < 32; i++) {
+ rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE3, i);
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[DPK] PAS_Read[%02d]= 0x%08x\n", i,
+ rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD));
+ }
+ }
+
+ val1_sqrt_sum = val1_i * val1_i + val1_q * val1_q;
+ val2_sqrt_sum = val2_i * val2_i + val2_q * val2_q;
+
+ if (val1_sqrt_sum < val2_sqrt_sum)
+ return 2;
+ else if (val1_sqrt_sum >= val2_sqrt_sum * 8 / 5)
+ return 1;
+ else
+ return 0;
+}
+
+static u8 _dpk_agc(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
+ enum rtw89_rf_path path, u8 kidx, u8 init_xdbm, u8 loss_only)
+{
+ struct rtw89_dpk_info *dpk = &rtwdev->dpk;
+ u8 tmp_dbm = init_xdbm, tmp_gl_idx = 0;
+ u8 step = DPK_AGC_STEP_SYNC_DGAIN;
+ u8 goout = 0, agc_cnt = 0;
+ bool is_fail = false;
+ int limit = 200;
+ u8 tmp_rxbb;
+ u16 dgain;
+
+ do {
+ switch (step) {
+ case DPK_AGC_STEP_SYNC_DGAIN:
+ is_fail = _dpk_kip_set_rxagc(rtwdev, phy, path, kidx);
+
+ if (is_fail) {
+ goout = 1;
+ break;
+ }
+
+ dgain = _dpk_dgain_read(rtwdev);
+
+ if (dgain > 0x5fc || dgain < 0x556) {
+ _dpk_one_shot(rtwdev, phy, path, D_SYNC);
+ dgain = _dpk_dgain_read(rtwdev);
+ }
+
+ if (agc_cnt == 0) {
+ if (dpk->bp[path][kidx].band == RTW89_BAND_2G)
+ _dpk_bypass_rxiqc(rtwdev, path);
+ else
+ _dpk_lbk_rxiqk(rtwdev, phy, path);
+ }
+ step = DPK_AGC_STEP_GAIN_LOSS_IDX;
+ break;
+
+ case DPK_AGC_STEP_GAIN_LOSS_IDX:
+ tmp_gl_idx = _dpk_gainloss(rtwdev, phy, path, kidx);
+
+ if (_dpk_pas_read(rtwdev, true) == 2 && tmp_gl_idx > 0)
+ step = DPK_AGC_STEP_GL_LT_CRITERION;
+ else if ((tmp_gl_idx == 0 && _dpk_pas_read(rtwdev, true) == 1) ||
+ tmp_gl_idx >= 7)
+ step = DPK_AGC_STEP_GL_GT_CRITERION;
+ else if (tmp_gl_idx == 0)
+ step = DPK_AGC_STEP_GL_LT_CRITERION;
+ else
+ step = DPK_AGC_STEP_SET_TX_GAIN;
+ break;
+
+ case DPK_AGC_STEP_GL_GT_CRITERION:
+ if (tmp_dbm <= 7) {
+ goout = 1;
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[DPK] Txagc@lower bound!!\n");
+ } else {
+ tmp_dbm = max_t(u8, tmp_dbm - 3, 7);
+ _dpk_kip_set_txagc(rtwdev, phy, path, tmp_dbm, true);
+ }
+ step = DPK_AGC_STEP_SYNC_DGAIN;
+ agc_cnt++;
+ break;
+
+ case DPK_AGC_STEP_GL_LT_CRITERION:
+ if (tmp_dbm >= 24) {
+ goout = 1;
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[DPK] Txagc@upper bound!!\n");
+ } else {
+ tmp_dbm = min_t(u8, tmp_dbm + 2, 24);
+ _dpk_kip_set_txagc(rtwdev, phy, path, tmp_dbm, true);
+ }
+ step = DPK_AGC_STEP_SYNC_DGAIN;
+ agc_cnt++;
+ break;
+
+ case DPK_AGC_STEP_SET_TX_GAIN:
+ _dpk_kip_control_rfc(rtwdev, path, false);
+ tmp_rxbb = rtw89_read_rf(rtwdev, path, RR_MOD, RR_MOD_RXB);
+ tmp_rxbb = min_t(u8, tmp_rxbb + tmp_gl_idx, 0x1f);
+
+ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RXB, tmp_rxbb);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[DPK] Adjust RXBB (%+d) = 0x%x\n",
+ tmp_gl_idx, tmp_rxbb);
+ _dpk_kip_control_rfc(rtwdev, path, true);
+ goout = 1;
+ break;
+ default:
+ goout = 1;
+ break;
+ }
+ } while (!goout && agc_cnt < 6 && limit-- > 0);
+
+ return is_fail;
+}
+
+static void _dpk_set_mdpd_para(struct rtw89_dev *rtwdev, u8 order)
+{
+ switch (order) {
+ case 0: /* (5,3,1) */
+ rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_OP, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_DPK_IDL, B_DPK_IDL_SEL, 0x2);
+ rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_PN, 0x4);
+ rtw89_phy_write32_mask(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_DMAN, 0x1);
+ break;
+ case 1: /* (5,3,0) */
+ rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_OP, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_DPK_IDL, B_DPK_IDL_SEL, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_PN, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_DMAN, 0x0);
+ break;
+ case 2: /* (5,0,0) */
+ rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_OP, 0x2);
+ rtw89_phy_write32_mask(rtwdev, R_DPK_IDL, B_DPK_IDL_SEL, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_PN, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_DMAN, 0x0);
+ break;
+ case 3: /* (7,3,1) */
+ rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_OP, 0x3);
+ rtw89_phy_write32_mask(rtwdev, R_DPK_IDL, B_DPK_IDL_SEL, 0x3);
+ rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_PN, 0x4);
+ rtw89_phy_write32_mask(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_DMAN, 0x1);
+ break;
+ default:
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[DPK] Wrong MDPD order!!(0x%x)\n", order);
+ break;
+ }
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Set %s for IDL\n",
+ order == 0x0 ? "(5,3,1)" :
+ order == 0x1 ? "(5,3,0)" :
+ order == 0x2 ? "(5,0,0)" : "(7,3,1)");
+}
+
+static void _dpk_idl_mpa(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
+ enum rtw89_rf_path path, u8 kidx)
+{
+ rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_MA, 0x1);
+
+ if (rtw89_phy_read32_mask(rtwdev, R_IDL_MPA, B_IDL_MD500) == 0x1)
+ _dpk_set_mdpd_para(rtwdev, 0x2);
+ else if (rtw89_phy_read32_mask(rtwdev, R_IDL_MPA, B_IDL_MD530) == 0x1)
+ _dpk_set_mdpd_para(rtwdev, 0x1);
+ else
+ _dpk_set_mdpd_para(rtwdev, 0x0);
+
+ rtw89_phy_write32_mask(rtwdev, R_DPK_IDL, B_DPK_IDL, 0x0);
+ fsleep(1000);
+
+ _dpk_one_shot(rtwdev, phy, path, D_MDPK_IDL);
+}
+
+static u8 _dpk_order_convert(struct rtw89_dev *rtwdev)
+{
+ u32 order;
+ u8 val;
+
+ order = rtw89_phy_read32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_OP);
+
+ switch (order) {
+ case 0: /* (5,3,1) */
+ val = 0x6;
+ break;
+ case 1: /* (5,3,0) */
+ val = 0x2;
+ break;
+ case 2: /* (5,0,0) */
+ val = 0x0;
+ break;
+ default:
+ val = 0xff;
+ break;
+ }
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] convert MDPD order to 0x%x\n", val);
+
+ return val;
+}
+
+static void _dpk_gain_normalize(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
+ enum rtw89_rf_path path, u8 kidx, bool is_execute)
+{
+ static const u32 reg[RTW89_DPK_BKUP_NUM][DPK_KSET_NUM] = {
+ {0x8190, 0x8194, 0x8198, 0x81a4},
+ {0x81a8, 0x81c4, 0x81c8, 0x81e8}
+ };
+ struct rtw89_dpk_info *dpk = &rtwdev->dpk;
+ u8 cur_k_set = dpk->cur_k_set;
+
+ if (cur_k_set >= DPK_KSET_NUM) {
+ rtw89_warn(rtwdev, "DPK cur_k_set = %d\n", cur_k_set);
+ cur_k_set = 2;
+ }
+
+ if (is_execute) {
+ rtw89_phy_write32_mask(rtwdev, R_DPK_GN + (path << 8),
+ B_DPK_GN_AG, 0x200);
+ rtw89_phy_write32_mask(rtwdev, R_DPK_GN + (path << 8),
+ B_DPK_GN_EN, 0x3);
+
+ _dpk_one_shot(rtwdev, phy, path, D_GAIN_NORM);
+ } else {
+ rtw89_phy_write32_mask(rtwdev, reg[kidx][cur_k_set] + (path << 8),
+ 0x0000007F, 0x5b);
+ }
+
+ dpk->bp[path][kidx].gs =
+ rtw89_phy_read32_mask(rtwdev, reg[kidx][cur_k_set] + (path << 8),
+ 0x0000007F);
+}
+
+static void _dpk_on(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
+ enum rtw89_rf_path path, u8 kidx)
+{
+ struct rtw89_dpk_info *dpk = &rtwdev->dpk;
+
+ rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
+ B_DPD_ORDER, _dpk_order_convert(rtwdev));
+
+ dpk->bp[path][kidx].path_ok =
+ dpk->bp[path][kidx].path_ok | BIT(dpk->cur_k_set);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] path_ok = 0x%x\n",
+ path, kidx, dpk->bp[path][kidx].path_ok);
+
+ rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
+ B_DPD_MEN, dpk->bp[path][kidx].path_ok);
+
+ _dpk_gain_normalize(rtwdev, phy, path, kidx, false);
+}
+
+static bool _dpk_main(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
+ enum rtw89_rf_path path)
+{
+ struct rtw89_dpk_info *dpk = &rtwdev->dpk;
+ u8 kidx = dpk->cur_idx[path];
+ u8 init_xdbm = 17;
+ bool is_fail;
+
+ if (dpk->bp[path][kidx].band != RTW89_BAND_2G)
+ init_xdbm = 15;
+
+ _dpk_kip_control_rfc(rtwdev, path, false);
+ _rfk_rf_direct_cntrl(rtwdev, path, false);
+ rtw89_write_rf(rtwdev, path, RR_BBDC, RFREG_MASK, 0x03ffd);
+
+ _dpk_rf_setting(rtwdev, path, kidx);
+ _set_rx_dck(rtwdev, path, RF_DPK);
+
+ _dpk_kip_pwr_clk_onoff(rtwdev, true);
+ _dpk_kip_preset(rtwdev, phy, path, kidx);
+ _dpk_txpwr_bb_force(rtwdev, path, true);
+ _dpk_kip_set_txagc(rtwdev, phy, path, init_xdbm, true);
+ _dpk_tpg_sel(rtwdev, path, kidx);
+ is_fail = _dpk_agc(rtwdev, phy, path, kidx, init_xdbm, false);
+ if (is_fail)
+ goto _error;
+
+ _dpk_idl_mpa(rtwdev, phy, path, kidx);
+ _dpk_para_query(rtwdev, path, kidx);
+
+ _dpk_on(rtwdev, phy, path, kidx);
+_error:
+ _dpk_kip_control_rfc(rtwdev, path, false);
+ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RF_RX);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d]_K%d %s\n", path, kidx,
+ dpk->cur_k_set, is_fail ? "need Check" : "is Success");
+
+ return is_fail;
+}
+
+static void _dpk_cal_select(struct rtw89_dev *rtwdev, bool force,
+ enum rtw89_phy_idx phy, u8 kpath)
+{
+ struct rtw89_dpk_info *dpk = &rtwdev->dpk;
+ u32 kip_bkup[RF_PATH_NUM_8851B][DPK_KIP_REG_NUM_8851B] = {};
+ u32 rf_bkup[RF_PATH_NUM_8851B][DPK_RF_REG_NUM_8851B] = {};
+ bool is_fail;
+ u8 path;
+
+ for (path = 0; path < RF_PATH_NUM_8851B; path++)
+ dpk->cur_idx[path] = 0;
+
+ for (path = 0; path < RF_PATH_NUM_8851B; path++) {
+ if (!(kpath & BIT(path)))
+ continue;
+ _dpk_bkup_kip(rtwdev, dpk_kip_reg, kip_bkup, path);
+ _dpk_bkup_rf(rtwdev, dpk_rf_reg, rf_bkup, path);
+ _dpk_information(rtwdev, phy, path);
+ _dpk_init(rtwdev, path);
+
+ if (rtwdev->is_tssi_mode[path])
+ _dpk_tssi_pause(rtwdev, path, true);
+ }
+
+ for (path = 0; path < RF_PATH_NUM_8851B; path++) {
+ if (!(kpath & BIT(path)))
+ continue;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[DPK] ========= S%d[%d] DPK Start =========\n",
+ path, dpk->cur_idx[path]);
+
+ _dpk_rxagc_onoff(rtwdev, path, false);
+ _rfk_drf_direct_cntrl(rtwdev, path, false);
+ _dpk_bb_afe_setting(rtwdev, path);
+
+ is_fail = _dpk_main(rtwdev, phy, path);
+ _dpk_onoff(rtwdev, path, is_fail);
+ }
+
+ for (path = 0; path < RF_PATH_NUM_8851B; path++) {
+ if (!(kpath & BIT(path)))
+ continue;
+
+ _dpk_kip_restore(rtwdev, phy, path);
+ _dpk_reload_kip(rtwdev, dpk_kip_reg, kip_bkup, path);
+ _dpk_reload_rf(rtwdev, dpk_rf_reg, rf_bkup, path);
+ _dpk_bb_afe_restore(rtwdev, path);
+ _dpk_rxagc_onoff(rtwdev, path, true);
+
+ if (rtwdev->is_tssi_mode[path])
+ _dpk_tssi_pause(rtwdev, path, false);
+ }
+
+ _dpk_kip_pwr_clk_onoff(rtwdev, false);
+}
+
+static void _dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, bool force)
+{
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[DPK] ****** 8851B DPK Start (Ver: 0x%x, Cv: %d) ******\n",
+ DPK_VER_8851B, rtwdev->hal.cv);
+
+ _dpk_cal_select(rtwdev, force, phy, _kpath(rtwdev, phy));
+}
+
+static void _dpk_track(struct rtw89_dev *rtwdev)
+{
+ struct rtw89_dpk_info *dpk = &rtwdev->dpk;
+ s8 txagc_bb, txagc_bb_tp, txagc_ofst;
+ s16 pwsf_tssi_ofst;
+ s8 delta_ther = 0;
+ u8 path, kidx;
+ u8 txagc_rf;
+ u8 cur_ther;
+
+ for (path = 0; path < RF_PATH_NUM_8851B; path++) {
+ kidx = dpk->cur_idx[path];
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
+ "[DPK_TRK] ================[S%d[%d] (CH %d)]================\n",
+ path, kidx, dpk->bp[path][kidx].ch);
+
+ txagc_rf = rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13),
+ B_TXAGC_RF);
+ txagc_bb = rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13),
+ MASKBYTE2);
+ txagc_bb_tp = rtw89_phy_read32_mask(rtwdev, R_TXAGC_BTP + (path << 13),
+ B_TXAGC_BTP);
+
+ rtw89_phy_write32_mask(rtwdev, R_KIP_RPT + (path << 8),
+ B_KIP_RPT_SEL, 0xf);
+ cur_ther = rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8),
+ B_RPT_PER_TH);
+ txagc_ofst = rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8),
+ B_RPT_PER_OF);
+ pwsf_tssi_ofst = rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8),
+ B_RPT_PER_TSSI);
+ pwsf_tssi_ofst = sign_extend32(pwsf_tssi_ofst, 12);
+
+ delta_ther = cur_ther - dpk->bp[path][kidx].ther_dpk;
+
+ delta_ther = delta_ther * 2 / 3;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
+ "[DPK_TRK] extra delta_ther = %d (0x%x / 0x%x@k)\n",
+ delta_ther, cur_ther, dpk->bp[path][kidx].ther_dpk);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
+ "[DPK_TRK] delta_txagc = %d (0x%x / 0x%x@k)\n",
+ txagc_rf - dpk->bp[path][kidx].txagc_dpk,
+ txagc_rf, dpk->bp[path][kidx].txagc_dpk);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
+ "[DPK_TRK] txagc_offset / pwsf_tssi_ofst = 0x%x / %+d\n",
+ txagc_ofst, pwsf_tssi_ofst);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
+ "[DPK_TRK] txagc_bb_tp / txagc_bb = 0x%x / 0x%x\n",
+ txagc_bb_tp, txagc_bb);
+
+ if (rtw89_phy_read32_mask(rtwdev, R_IDL_MPA, B_IDL_DN) == 0x0 &&
+ txagc_rf != 0) {
+ rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
+ "[DPK_TRK] New pwsf = 0x%x\n", 0x78 - delta_ther);
+
+ rtw89_phy_write32_mask(rtwdev,
+ R_DPD_BND + (path << 8) + (kidx << 2),
+ 0x07FC0000, 0x78 - delta_ther);
+ }
+ }
+}
+
+static void _rck(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
+{
+ u32 rf_reg5;
+ u32 rck_val;
+ u32 val;
+ int ret;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] ====== S%d RCK ======\n", path);
+
+ rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK);
+
+ rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
+ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] RF0x00 = 0x%05x\n",
+ rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK));
+
+ /* RCK trigger */
+ rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, 0x00240);
+
+ ret = read_poll_timeout_atomic(rtw89_read_rf, val, val, 2, 30,
+ false, rtwdev, path, RR_RCKS, BIT(3));
+
+ rck_val = rtw89_read_rf(rtwdev, path, RR_RCKC, RR_RCKC_CA);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] rck_val = 0x%x, ret = %d\n",
+ rck_val, ret);
+
+ rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, rck_val);
+ rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] RF 0x1b = 0x%x\n",
+ rtw89_read_rf(rtwdev, path, RR_RCKC, RFREG_MASK));
+}
+
+static void _tssi_set_sys(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
+ enum rtw89_rf_path path)
+{
+ const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
+ enum rtw89_band band = chan->band_type;
+
+ rtw89_rfk_parser(rtwdev, &rtw8851b_tssi_sys_defs_tbl);
+
+ rtw89_rfk_parser_by_cond(rtwdev, band == RTW89_BAND_2G,
+ &rtw8851b_tssi_sys_a_defs_2g_tbl,
+ &rtw8851b_tssi_sys_a_defs_5g_tbl);
+}
+
+static void _tssi_ini_txpwr_ctrl_bb(struct rtw89_dev *rtwdev,
+ enum rtw89_phy_idx phy,
+ enum rtw89_rf_path path)
+{
+ rtw89_rfk_parser(rtwdev, &rtw8851b_tssi_init_txpwr_defs_a_tbl);
+}
+
+static void _tssi_ini_txpwr_ctrl_bb_he_tb(struct rtw89_dev *rtwdev,
+ enum rtw89_phy_idx phy,
+ enum rtw89_rf_path path)
+{
+ rtw89_rfk_parser(rtwdev, &rtw8851b_tssi_init_txpwr_he_tb_defs_a_tbl);
+}
+
+static void _tssi_set_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
+ enum rtw89_rf_path path)
+{
+ rtw89_rfk_parser(rtwdev, &rtw8851b_tssi_dck_defs_a_tbl);
+}
+
+static void _tssi_set_tmeter_tbl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
+ enum rtw89_rf_path path)
+{
+#define RTW8851B_TSSI_GET_VAL(ptr, idx) \
+({ \
+ s8 *__ptr = (ptr); \
+ u8 __idx = (idx), __i, __v; \
+ u32 __val = 0; \
+ for (__i = 0; __i < 4; __i++) { \
+ __v = (__ptr[__idx + __i]); \
+ __val |= (__v << (8 * __i)); \
+ } \
+ __val; \
+})
+ struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
+ const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
+ u8 ch = chan->channel;
+ u8 subband = chan->subband_type;
+ const s8 *thm_up_a = NULL;
+ const s8 *thm_down_a = NULL;
+ u8 thermal = 0xff;
+ s8 thm_ofst[64] = {0};
+ u32 tmp = 0;
+ u8 i, j;
+
+ switch (subband) {
+ default:
+ case RTW89_CH_2G:
+ thm_up_a = rtw89_8851b_trk_cfg.delta_swingidx_2ga_p;
+ thm_down_a = rtw89_8851b_trk_cfg.delta_swingidx_2ga_n;
+ break;
+ case RTW89_CH_5G_BAND_1:
+ thm_up_a = rtw89_8851b_trk_cfg.delta_swingidx_5ga_p[0];
+ thm_down_a = rtw89_8851b_trk_cfg.delta_swingidx_5ga_n[0];
+ break;
+ case RTW89_CH_5G_BAND_3:
+ thm_up_a = rtw89_8851b_trk_cfg.delta_swingidx_5ga_p[1];
+ thm_down_a = rtw89_8851b_trk_cfg.delta_swingidx_5ga_n[1];
+ break;
+ case RTW89_CH_5G_BAND_4:
+ thm_up_a = rtw89_8851b_trk_cfg.delta_swingidx_5ga_p[2];
+ thm_down_a = rtw89_8851b_trk_cfg.delta_swingidx_5ga_n[2];
+ break;
+ }
+
+ if (path == RF_PATH_A) {
+ thermal = tssi_info->thermal[RF_PATH_A];
+
+ rtw89_debug(rtwdev, RTW89_DBG_TSSI,
+ "[TSSI] ch=%d thermal_pathA=0x%x\n", ch, thermal);
+
+ rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER_DIS, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER_TRK, 0x1);
+
+ if (thermal == 0xff) {
+ rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER, 32);
+ rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_VAL, 32);
+
+ for (i = 0; i < 64; i += 4) {
+ rtw89_phy_write32(rtwdev, R_P0_TSSI_BASE + i, 0x0);
+
+ rtw89_debug(rtwdev, RTW89_DBG_TSSI,
+ "[TSSI] write 0x%x val=0x%08x\n",
+ R_P0_TSSI_BASE + i, 0x0);
+ }
+
+ } else {
+ rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER,
+ thermal);
+ rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_VAL,
+ thermal);
+
+ i = 0;
+ for (j = 0; j < 32; j++)
+ thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ?
+ -thm_down_a[i++] :
+ -thm_down_a[DELTA_SWINGIDX_SIZE - 1];
+
+ i = 1;
+ for (j = 63; j >= 32; j--)
+ thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ?
+ thm_up_a[i++] :
+ thm_up_a[DELTA_SWINGIDX_SIZE - 1];
+
+ for (i = 0; i < 64; i += 4) {
+ tmp = RTW8851B_TSSI_GET_VAL(thm_ofst, i);
+ rtw89_phy_write32(rtwdev, R_P0_TSSI_BASE + i, tmp);
+
+ rtw89_debug(rtwdev, RTW89_DBG_TSSI,
+ "[TSSI] write 0x%x val=0x%08x\n",
+ 0x5c00 + i, tmp);
+ }
+ }
+ rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, R_P0_RFCTM_RDY, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, R_P0_RFCTM_RDY, 0x0);
+ }
+#undef RTW8851B_TSSI_GET_VAL
+}
+
+static void _tssi_set_dac_gain_tbl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
+ enum rtw89_rf_path path)
+{
+ rtw89_rfk_parser(rtwdev, &rtw8851b_tssi_dac_gain_defs_a_tbl);
+}
+
+static void _tssi_slope_cal_org(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
+ enum rtw89_rf_path path)
+{
+ const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
+ enum rtw89_band band = chan->band_type;
+
+ rtw89_rfk_parser_by_cond(rtwdev, band == RTW89_BAND_2G,
+ &rtw8851b_tssi_slope_a_defs_2g_tbl,
+ &rtw8851b_tssi_slope_a_defs_5g_tbl);
+}
+
+static void _tssi_alignment_default(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
+ enum rtw89_rf_path path, bool all)
+{
+ const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
+ enum rtw89_band band = chan->band_type;
+
+ rtw89_rfk_parser_by_cond(rtwdev, band == RTW89_BAND_2G,
+ &rtw8851b_tssi_align_a_2g_defs_tbl,
+ &rtw8851b_tssi_align_a_5g_defs_tbl);
+}
+
+static void _tssi_set_tssi_slope(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
+ enum rtw89_rf_path path)
+{
+ rtw89_rfk_parser(rtwdev, &rtw8851b_tssi_slope_defs_a_tbl);
+}
+
+static void _tssi_set_tssi_track(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
+ enum rtw89_rf_path path)
+{
+ rtw89_rfk_parser(rtwdev, &rtw8851b_tssi_track_defs_a_tbl);
+}
+
+static void _tssi_set_txagc_offset_mv_avg(struct rtw89_dev *rtwdev,
+ enum rtw89_phy_idx phy,
+ enum rtw89_rf_path path)
+{
+ rtw89_rfk_parser(rtwdev, &rtw8851b_tssi_mv_avg_defs_a_tbl);
+}
+
+static void _tssi_enable(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)
+{
+ _tssi_set_tssi_track(rtwdev, phy, RF_PATH_A);
+ _tssi_set_txagc_offset_mv_avg(rtwdev, phy, RF_PATH_A);
+
+ rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_MV_AVG, B_P0_TSSI_MV_CLR, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_AVG, B_P0_TSSI_EN, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_AVG, B_P0_TSSI_EN, 0x1);
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_TXGA_V1, RR_TXGA_V1_TRK_EN, 0x1);
+
+ rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_RFC, 0x3);
+ rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT, 0xc0);
+ rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x1);
+
+ rtwdev->is_tssi_mode[RF_PATH_A] = true;
+}
+
+static void _tssi_disable(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)
+{
+ rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_AVG, B_P0_TSSI_EN, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x1);
+ rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_MV_AVG, B_P0_TSSI_MV_CLR, 0x1);
+
+ rtwdev->is_tssi_mode[RF_PATH_A] = false;
+}
+
+static u32 _tssi_get_cck_group(struct rtw89_dev *rtwdev, u8 ch)
+{
+ switch (ch) {
+ case 1 ... 2:
+ return 0;
+ case 3 ... 5:
+ return 1;
+ case 6 ... 8:
+ return 2;
+ case 9 ... 11:
+ return 3;
+ case 12 ... 13:
+ return 4;
+ case 14:
+ return 5;
+ }
+
+ return 0;
+}
+
+#define TSSI_EXTRA_GROUP_BIT (BIT(31))
+#define TSSI_EXTRA_GROUP(idx) (TSSI_EXTRA_GROUP_BIT | (idx))
+#define IS_TSSI_EXTRA_GROUP(group) ((group) & TSSI_EXTRA_GROUP_BIT)
+#define TSSI_EXTRA_GET_GROUP_IDX1(group) ((group) & ~TSSI_EXTRA_GROUP_BIT)
+#define TSSI_EXTRA_GET_GROUP_IDX2(group) (TSSI_EXTRA_GET_GROUP_IDX1(group) + 1)
+
+static u32 _tssi_get_ofdm_group(struct rtw89_dev *rtwdev, u8 ch)
+{
+ switch (ch) {
+ case 1 ... 2:
+ return 0;
+ case 3 ... 5:
+ return 1;
+ case 6 ... 8:
+ return 2;
+ case 9 ... 11:
+ return 3;
+ case 12 ... 14:
+ return 4;
+ case 36 ... 40:
+ return 5;
+ case 41 ... 43:
+ return TSSI_EXTRA_GROUP(5);
+ case 44 ... 48:
+ return 6;
+ case 49 ... 51:
+ return TSSI_EXTRA_GROUP(6);
+ case 52 ... 56:
+ return 7;
+ case 57 ... 59:
+ return TSSI_EXTRA_GROUP(7);
+ case 60 ... 64:
+ return 8;
+ case 100 ... 104:
+ return 9;
+ case 105 ... 107:
+ return TSSI_EXTRA_GROUP(9);
+ case 108 ... 112:
+ return 10;
+ case 113 ... 115:
+ return TSSI_EXTRA_GROUP(10);
+ case 116 ... 120:
+ return 11;
+ case 121 ... 123:
+ return TSSI_EXTRA_GROUP(11);
+ case 124 ... 128:
+ return 12;
+ case 129 ... 131:
+ return TSSI_EXTRA_GROUP(12);
+ case 132 ... 136:
+ return 13;
+ case 137 ... 139:
+ return TSSI_EXTRA_GROUP(13);
+ case 140 ... 144:
+ return 14;
+ case 149 ... 153:
+ return 15;
+ case 154 ... 156:
+ return TSSI_EXTRA_GROUP(15);
+ case 157 ... 161:
+ return 16;
+ case 162 ... 164:
+ return TSSI_EXTRA_GROUP(16);
+ case 165 ... 169:
+ return 17;
+ case 170 ... 172:
+ return TSSI_EXTRA_GROUP(17);
+ case 173 ... 177:
+ return 18;
+ }
+
+ return 0;
+}
+
+static u32 _tssi_get_trim_group(struct rtw89_dev *rtwdev, u8 ch)
+{
+ switch (ch) {
+ case 1 ... 8:
+ return 0;
+ case 9 ... 14:
+ return 1;
+ case 36 ... 48:
+ return 2;
+ case 52 ... 64:
+ return 3;
+ case 100 ... 112:
+ return 4;
+ case 116 ... 128:
+ return 5;
+ case 132 ... 144:
+ return 6;
+ case 149 ... 177:
+ return 7;
+ }
+
+ return 0;
+}
+
+static s8 _tssi_get_ofdm_de(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
+ enum rtw89_rf_path path)
+{
+ struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
+ const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
+ u32 gidx, gidx_1st, gidx_2nd;
+ u8 ch = chan->channel;
+ s8 de_1st;
+ s8 de_2nd;
+ s8 val;
+
+ gidx = _tssi_get_ofdm_group(rtwdev, ch);
+
+ rtw89_debug(rtwdev, RTW89_DBG_TSSI,
+ "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n", path, gidx);
+
+ if (IS_TSSI_EXTRA_GROUP(gidx)) {
+ gidx_1st = TSSI_EXTRA_GET_GROUP_IDX1(gidx);
+ gidx_2nd = TSSI_EXTRA_GET_GROUP_IDX2(gidx);
+ de_1st = tssi_info->tssi_mcs[path][gidx_1st];
+ de_2nd = tssi_info->tssi_mcs[path][gidx_2nd];
+ val = (de_1st + de_2nd) / 2;
+
+ rtw89_debug(rtwdev, RTW89_DBG_TSSI,
+ "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n",
+ path, val, de_1st, de_2nd);
+ } else {
+ val = tssi_info->tssi_mcs[path][gidx];
+
+ rtw89_debug(rtwdev, RTW89_DBG_TSSI,
+ "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val);
+ }
+
+ return val;
+}
+
+static s8 _tssi_get_ofdm_trim_de(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
+ enum rtw89_rf_path path)
+{
+ struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
+ const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
+ u32 tgidx, tgidx_1st, tgidx_2nd;
+ u8 ch = chan->channel;
+ s8 tde_1st;
+ s8 tde_2nd;
+ s8 val;
+
+ tgidx = _tssi_get_trim_group(rtwdev, ch);
+
+ rtw89_debug(rtwdev, RTW89_DBG_TSSI,
+ "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n",
+ path, tgidx);
+
+ if (IS_TSSI_EXTRA_GROUP(tgidx)) {
+ tgidx_1st = TSSI_EXTRA_GET_GROUP_IDX1(tgidx);
+ tgidx_2nd = TSSI_EXTRA_GET_GROUP_IDX2(tgidx);
+ tde_1st = tssi_info->tssi_trim[path][tgidx_1st];
+ tde_2nd = tssi_info->tssi_trim[path][tgidx_2nd];
+ val = (tde_1st + tde_2nd) / 2;
+
+ rtw89_debug(rtwdev, RTW89_DBG_TSSI,
+ "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n",
+ path, val, tde_1st, tde_2nd);
+ } else {
+ val = tssi_info->tssi_trim[path][tgidx];
+
+ rtw89_debug(rtwdev, RTW89_DBG_TSSI,
+ "[TSSI][TRIM]: path=%d mcs trim_de=%d\n",
+ path, val);
+ }
+
+ return val;
+}
+
+static void _tssi_set_efuse_to_de(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)
+{
+ struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
+ const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
+ u8 ch = chan->channel;
+ u8 gidx;
+ s8 ofdm_de;
+ s8 trim_de;
+ s32 val;
+ u32 i;
+
+ rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI][TRIM]: phy=%d ch=%d\n",
+ phy, ch);
+
+ for (i = RF_PATH_A; i < RTW8851B_TSSI_PATH_NR; i++) {
+ gidx = _tssi_get_cck_group(rtwdev, ch);
+ trim_de = _tssi_get_ofdm_trim_de(rtwdev, phy, i);
+ val = tssi_info->tssi_cck[i][gidx] + trim_de;
+
+ rtw89_debug(rtwdev, RTW89_DBG_TSSI,
+ "[TSSI][TRIM]: path=%d cck[%d]=0x%x trim=0x%x\n",
+ i, gidx, tssi_info->tssi_cck[i][gidx], trim_de);
+
+ rtw89_phy_write32_mask(rtwdev, _tssi_de_cck_long[i], _TSSI_DE_MASK, val);
+ rtw89_phy_write32_mask(rtwdev, _tssi_de_cck_short[i], _TSSI_DE_MASK, val);
+
+ rtw89_debug(rtwdev, RTW89_DBG_TSSI,
+ "[TSSI] Set TSSI CCK DE 0x%x[21:12]=0x%x\n",
+ _tssi_de_cck_long[i],
+ rtw89_phy_read32_mask(rtwdev, _tssi_de_cck_long[i],
+ _TSSI_DE_MASK));
+
+ ofdm_de = _tssi_get_ofdm_de(rtwdev, phy, i);
+ trim_de = _tssi_get_ofdm_trim_de(rtwdev, phy, i);
+ val = ofdm_de + trim_de;
+
+ rtw89_debug(rtwdev, RTW89_DBG_TSSI,
+ "[TSSI][TRIM]: path=%d mcs=0x%x trim=0x%x\n",
+ i, ofdm_de, trim_de);
+
+ rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_20m[i], _TSSI_DE_MASK, val);
+ rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_40m[i], _TSSI_DE_MASK, val);
+ rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_80m[i], _TSSI_DE_MASK, val);
+ rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_80m_80m[i], _TSSI_DE_MASK, val);
+ rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_5m[i], _TSSI_DE_MASK, val);
+ rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_10m[i], _TSSI_DE_MASK, val);
+
+ rtw89_debug(rtwdev, RTW89_DBG_TSSI,
+ "[TSSI] Set TSSI MCS DE 0x%x[21:12]=0x%x\n",
+ _tssi_de_mcs_20m[i],
+ rtw89_phy_read32_mask(rtwdev, _tssi_de_mcs_20m[i],
+ _TSSI_DE_MASK));
+ }
+}
+
+static void _tssi_alimentk_dump_result(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
+{
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[TSSI PA K]\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n"
+ "0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n",
+ R_TSSI_PA_K1 + (path << 13),
+ rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K1 + (path << 13), MASKDWORD),
+ R_TSSI_PA_K2 + (path << 13),
+ rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K2 + (path << 13), MASKDWORD),
+ R_P0_TSSI_ALIM1 + (path << 13),
+ rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD),
+ R_P0_TSSI_ALIM3 + (path << 13),
+ rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD),
+ R_TSSI_PA_K5 + (path << 13),
+ rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K5 + (path << 13), MASKDWORD),
+ R_P0_TSSI_ALIM2 + (path << 13),
+ rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD),
+ R_P0_TSSI_ALIM4 + (path << 13),
+ rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD),
+ R_TSSI_PA_K8 + (path << 13),
+ rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K8 + (path << 13), MASKDWORD));
+}
+
+static void _tssi_alimentk_done(struct rtw89_dev *rtwdev,
+ enum rtw89_phy_idx phy, enum rtw89_rf_path path)
+{
+ struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
+ const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
+ u8 channel = chan->channel;
+ u8 band;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "======>%s phy=%d path=%d\n", __func__, phy, path);
+
+ if (channel >= 1 && channel <= 14)
+ band = TSSI_ALIMK_2G;
+ else if (channel >= 36 && channel <= 64)
+ band = TSSI_ALIMK_5GL;
+ else if (channel >= 100 && channel <= 144)
+ band = TSSI_ALIMK_5GM;
+ else if (channel >= 149 && channel <= 177)
+ band = TSSI_ALIMK_5GH;
+ else
+ band = TSSI_ALIMK_2G;
+
+ if (tssi_info->alignment_done[path][band]) {
+ rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD,
+ tssi_info->alignment_value[path][band][0]);
+ rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD,
+ tssi_info->alignment_value[path][band][1]);
+ rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD,
+ tssi_info->alignment_value[path][band][2]);
+ rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD,
+ tssi_info->alignment_value[path][band][3]);
+ }
+
+ _tssi_alimentk_dump_result(rtwdev, path);
+}
+
+static void rtw8851b_by_rate_dpd(struct rtw89_dev *rtwdev)
+{
+ rtw89_write32_mask(rtwdev, R_AX_PWR_SWING_OTHER_CTRL0,
+ B_AX_CFIR_BY_RATE_OFF_MASK, 0x21861);
+}
+
+void rtw8851b_dpk_init(struct rtw89_dev *rtwdev)
+{
+ rtw8851b_by_rate_dpd(rtwdev);
+}
+
+void rtw8851b_aack(struct rtw89_dev *rtwdev)
+{
+ u32 tmp05, tmpd3, ib[4];
+ u32 tmp;
+ int ret;
+ int rek;
+ int i;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]DO AACK\n");
+
+ tmp05 = rtw89_read_rf(rtwdev, RF_PATH_A, RR_RSV1, RFREG_MASK);
+ tmpd3 = rtw89_read_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RFREG_MASK);
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RR_MOD_MASK, 0x3);
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RFREG_MASK, 0x0);
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_ST, 0x0);
+
+ for (rek = 0; rek < 4; rek++) {
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_AACK, RFREG_MASK, 0x8201e);
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_AACK, RFREG_MASK, 0x8201f);
+ fsleep(100);
+
+ ret = read_poll_timeout_atomic(rtw89_read_rf, tmp, tmp,
+ 1, 1000, false,
+ rtwdev, RF_PATH_A, 0xd0, BIT(16));
+ if (ret)
+ rtw89_warn(rtwdev, "[LCK]AACK timeout\n");
+
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_VCI, RR_VCI_ON, 0x1);
+ for (i = 0; i < 4; i++) {
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_VCO, RR_VCO_SEL, i);
+ ib[i] = rtw89_read_rf(rtwdev, RF_PATH_A, RR_IBD, RR_IBD_VAL);
+ }
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_VCI, RR_VCI_ON, 0x0);
+
+ if (ib[0] != 0 && ib[1] != 0 && ib[2] != 0 && ib[3] != 0)
+ break;
+ }
+
+ if (rek != 0)
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]AACK rek = %d\n", rek);
+
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RFREG_MASK, tmp05);
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RFREG_MASK, tmpd3);
+}
+
+static void _lck_keep_thermal(struct rtw89_dev *rtwdev)
+{
+ struct rtw89_lck_info *lck = &rtwdev->lck;
+
+ lck->thermal[RF_PATH_A] =
+ ewma_thermal_read(&rtwdev->phystat.avg_thermal[RF_PATH_A]);
+ rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
+ "[LCK] path=%d thermal=0x%x", RF_PATH_A, lck->thermal[RF_PATH_A]);
+}
+
+static void rtw8851b_lck(struct rtw89_dev *rtwdev)
+{
+ u32 tmp05, tmp18, tmpd3;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]DO LCK\n");
+
+ tmp05 = rtw89_read_rf(rtwdev, RF_PATH_A, RR_RSV1, RFREG_MASK);
+ tmp18 = rtw89_read_rf(rtwdev, RF_PATH_A, RR_CFGCH, RFREG_MASK);
+ tmpd3 = rtw89_read_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RFREG_MASK);
+
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RR_MOD_MASK, 0x3);
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RFREG_MASK, 0x0);
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x1);
+
+ _set_ch(rtwdev, tmp18);
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RFREG_MASK, tmpd3);
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RFREG_MASK, tmp05);
+
+ _lck_keep_thermal(rtwdev);
+}
+
+#define RTW8851B_LCK_TH 8
+
+void rtw8851b_lck_track(struct rtw89_dev *rtwdev)
+{
+ struct rtw89_lck_info *lck = &rtwdev->lck;
+ u8 cur_thermal;
+ int delta;
+
+ cur_thermal =
+ ewma_thermal_read(&rtwdev->phystat.avg_thermal[RF_PATH_A]);
+ delta = abs((int)cur_thermal - lck->thermal[RF_PATH_A]);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
+ "[LCK] path=%d current thermal=0x%x delta=0x%x\n",
+ RF_PATH_A, cur_thermal, delta);
+
+ if (delta >= RTW8851B_LCK_TH) {
+ rtw8851b_aack(rtwdev);
+ rtw8851b_lck(rtwdev);
+ }
+}
+
+void rtw8851b_lck_init(struct rtw89_dev *rtwdev)
+{
+ _lck_keep_thermal(rtwdev);
+}
+
+void rtw8851b_rck(struct rtw89_dev *rtwdev)
+{
+ _rck(rtwdev, RF_PATH_A);
+}
+
+void rtw8851b_dack(struct rtw89_dev *rtwdev)
+{
+ _dac_cal(rtwdev, false);
+}
+
+void rtw8851b_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
+{
+ u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0);
+ u32 tx_en;
+
+ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_START);
+ rtw89_chip_stop_sch_tx(rtwdev, phy_idx, &tx_en, RTW89_SCH_TX_SEL_ALL);
+ _wait_rx_mode(rtwdev, _kpath(rtwdev, phy_idx));
+
+ _iqk_init(rtwdev);
+ _iqk(rtwdev, phy_idx, false);
+
+ rtw89_chip_resume_sch_tx(rtwdev, phy_idx, tx_en);
+ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_STOP);
+}
+
+void rtw8851b_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
+{
+ u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0);
+ u32 tx_en;
+
+ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_RXDCK, BTC_WRFK_START);
+ rtw89_chip_stop_sch_tx(rtwdev, phy_idx, &tx_en, RTW89_SCH_TX_SEL_ALL);
+ _wait_rx_mode(rtwdev, _kpath(rtwdev, phy_idx));
+
+ _rx_dck(rtwdev, phy_idx, false);
+
+ rtw89_chip_resume_sch_tx(rtwdev, phy_idx, tx_en);
+ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_RXDCK, BTC_WRFK_STOP);
+}
+
+void rtw8851b_dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
+{
+ u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0);
+ u32 tx_en;
+
+ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DPK, BTC_WRFK_START);
+ rtw89_chip_stop_sch_tx(rtwdev, phy_idx, &tx_en, RTW89_SCH_TX_SEL_ALL);
+ _wait_rx_mode(rtwdev, _kpath(rtwdev, phy_idx));
+
+ rtwdev->dpk.is_dpk_enable = true;
+ rtwdev->dpk.is_dpk_reload_en = false;
+ _dpk(rtwdev, phy_idx, false);
+
+ rtw89_chip_resume_sch_tx(rtwdev, phy_idx, tx_en);
+ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DPK, BTC_WRFK_STOP);
+}
+
+void rtw8851b_dpk_track(struct rtw89_dev *rtwdev)
+{
+ _dpk_track(rtwdev);
+}
+
+void rtw8851b_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, bool hwtx_en)
+{
+ u8 phy_map = rtw89_btc_phymap(rtwdev, phy, RF_A);
+ u8 i;
+
+ rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI] %s: phy=%d\n", __func__, phy);
+ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_START);
+
+ _tssi_disable(rtwdev, phy);
+
+ for (i = RF_PATH_A; i < RF_PATH_NUM_8851B; i++) {
+ _tssi_set_sys(rtwdev, phy, i);
+ _tssi_ini_txpwr_ctrl_bb(rtwdev, phy, i);
+ _tssi_ini_txpwr_ctrl_bb_he_tb(rtwdev, phy, i);
+ _tssi_set_dck(rtwdev, phy, i);
+ _tssi_set_tmeter_tbl(rtwdev, phy, i);
+ _tssi_set_dac_gain_tbl(rtwdev, phy, i);
+ _tssi_slope_cal_org(rtwdev, phy, i);
+ _tssi_alignment_default(rtwdev, phy, i, true);
+ _tssi_set_tssi_slope(rtwdev, phy, i);
+ }
+
+ _tssi_enable(rtwdev, phy);
+ _tssi_set_efuse_to_de(rtwdev, phy);
+
+ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_STOP);
+}
+
+void rtw8851b_tssi_scan(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)
+{
+ const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
+ u8 channel = chan->channel;
+ u32 i;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "======>%s phy=%d channel=%d\n", __func__, phy, channel);
+
+ _tssi_disable(rtwdev, phy);
+
+ for (i = RF_PATH_A; i < RF_PATH_NUM_8851B; i++) {
+ _tssi_set_sys(rtwdev, phy, i);
+ _tssi_set_tmeter_tbl(rtwdev, phy, i);
+ _tssi_slope_cal_org(rtwdev, phy, i);
+ _tssi_alignment_default(rtwdev, phy, i, true);
+ }
+
+ _tssi_enable(rtwdev, phy);
+ _tssi_set_efuse_to_de(rtwdev, phy);
+}
+
+static void rtw8851b_tssi_default_txagc(struct rtw89_dev *rtwdev,
+ enum rtw89_phy_idx phy, bool enable)
+{
+ const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
+ u8 channel = chan->channel;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "======> %s ch=%d\n",
+ __func__, channel);
+
+ if (enable)
+ return;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "======>%s 1 SCAN_END Set 0x5818[7:0]=0x%x\n",
+ __func__,
+ rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT));
+
+ rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT, 0xc0);
+ rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x0);
+ rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x1);
+
+ _tssi_alimentk_done(rtwdev, phy, RF_PATH_A);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "======>%s 2 SCAN_END Set 0x5818[7:0]=0x%x\n",
+ __func__,
+ rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT));
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "======> %s SCAN_END\n", __func__);
+}
+
+void rtw8851b_wifi_scan_notify(struct rtw89_dev *rtwdev, bool scan_start,
+ enum rtw89_phy_idx phy_idx)
+{
+ if (scan_start)
+ rtw8851b_tssi_default_txagc(rtwdev, phy_idx, true);
+ else
+ rtw8851b_tssi_default_txagc(rtwdev, phy_idx, false);
+}
+
+static void _bw_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
+ enum rtw89_bandwidth bw, bool dav)
+{
+ u32 reg18_addr = dav ? RR_CFGCH : RR_CFGCH_V1;
+ u32 rf_reg18;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK]===> %s\n", __func__);
+
+ rf_reg18 = rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK);
+ if (rf_reg18 == INV_RF_DATA) {
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[RFK]Invalid RF_0x18 for Path-%d\n", path);
+ return;
+ }
+ rf_reg18 &= ~RR_CFGCH_BW;
+
+ switch (bw) {
+ case RTW89_CHANNEL_WIDTH_5:
+ case RTW89_CHANNEL_WIDTH_10:
+ case RTW89_CHANNEL_WIDTH_20:
+ rf_reg18 |= FIELD_PREP(RR_CFGCH_BW, CFGCH_BW_20M);
+ break;
+ case RTW89_CHANNEL_WIDTH_40:
+ rf_reg18 |= FIELD_PREP(RR_CFGCH_BW, CFGCH_BW_40M);
+ break;
+ case RTW89_CHANNEL_WIDTH_80:
+ rf_reg18 |= FIELD_PREP(RR_CFGCH_BW, CFGCH_BW_80M);
+ break;
+ default:
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK]Fail to set CH\n");
+ }
+
+ rf_reg18 &= ~(RR_CFGCH_POW_LCK | RR_CFGCH_TRX_AH | RR_CFGCH_BCN |
+ RR_CFGCH_BW2) & RFREG_MASK;
+ rf_reg18 |= RR_CFGCH_BW2;
+ rtw89_write_rf(rtwdev, path, reg18_addr, RFREG_MASK, rf_reg18);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK] set %x at path%d, %x =0x%x\n",
+ bw, path, reg18_addr,
+ rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK));
+}
+
+static void _ctrl_bw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
+ enum rtw89_bandwidth bw)
+{
+ _bw_setting(rtwdev, RF_PATH_A, bw, true);
+ _bw_setting(rtwdev, RF_PATH_A, bw, false);
+}
+
+static bool _set_s0_arfc18(struct rtw89_dev *rtwdev, u32 val)
+{
+ u32 bak;
+ u32 tmp;
+ int ret;
+
+ bak = rtw89_read_rf(rtwdev, RF_PATH_A, RR_LDO, RFREG_MASK);
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_LDO, RR_LDO_SEL, 0x1);
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_CFGCH, RFREG_MASK, val);
+
+ ret = read_poll_timeout_atomic(rtw89_read_rf, tmp, tmp == 0, 1, 1000,
+ false, rtwdev, RF_PATH_A, RR_LPF, RR_LPF_BUSY);
+ if (ret)
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]LCK timeout\n");
+
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_LDO, RFREG_MASK, bak);
+
+ return !!ret;
+}
+
+static void _lck_check(struct rtw89_dev *rtwdev)
+{
+ u32 tmp;
+
+ if (rtw89_read_rf(rtwdev, RF_PATH_A, RR_SYNFB, RR_SYNFB_LK) == 0) {
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]SYN MMD reset\n");
+
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_MMD, RR_MMD_RST_EN, 0x1);
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_MMD, RR_MMD_RST_SYN, 0x0);
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_MMD, RR_MMD_RST_SYN, 0x1);
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_MMD, RR_MMD_RST_EN, 0x0);
+ }
+
+ udelay(10);
+
+ if (rtw89_read_rf(rtwdev, RF_PATH_A, RR_SYNFB, RR_SYNFB_LK) == 0) {
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]re-set RF 0x18\n");
+
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x1);
+ tmp = rtw89_read_rf(rtwdev, RF_PATH_A, RR_CFGCH, RFREG_MASK);
+ _set_s0_arfc18(rtwdev, tmp);
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x0);
+ }
+
+ if (rtw89_read_rf(rtwdev, RF_PATH_A, RR_SYNFB, RR_SYNFB_LK) == 0) {
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]SYN off/on\n");
+
+ tmp = rtw89_read_rf(rtwdev, RF_PATH_A, RR_POW, RFREG_MASK);
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RFREG_MASK, tmp);
+ tmp = rtw89_read_rf(rtwdev, RF_PATH_A, RR_SX, RFREG_MASK);
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_SX, RFREG_MASK, tmp);
+
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_SYNLUT, RR_SYNLUT_MOD, 0x1);
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN, 0x0);
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN, 0x3);
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_SYNLUT, RR_SYNLUT_MOD, 0x0);
+
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x1);
+ tmp = rtw89_read_rf(rtwdev, RF_PATH_A, RR_CFGCH, RFREG_MASK);
+ _set_s0_arfc18(rtwdev, tmp);
+ rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x0);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]0xb2=%x, 0xc5=%x\n",
+ rtw89_read_rf(rtwdev, RF_PATH_A, RR_VCO, RFREG_MASK),
+ rtw89_read_rf(rtwdev, RF_PATH_A, RR_SYNFB, RFREG_MASK));
+ }
+}
+
+static void _set_ch(struct rtw89_dev *rtwdev, u32 val)
+{
+ bool timeout;
+
+ timeout = _set_s0_arfc18(rtwdev, val);
+ if (!timeout)
+ _lck_check(rtwdev);
+}
+
+static void _ch_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
+ u8 central_ch, bool dav)
+{
+ u32 reg18_addr = dav ? RR_CFGCH : RR_CFGCH_V1;
+ bool is_2g_ch = central_ch <= 14;
+ u32 rf_reg18;
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK]===> %s\n", __func__);
+
+ rf_reg18 = rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK);
+ rf_reg18 &= ~(RR_CFGCH_BAND1 | RR_CFGCH_POW_LCK | RR_CFGCH_TRX_AH |
+ RR_CFGCH_BCN | RR_CFGCH_BAND0 | RR_CFGCH_CH);
+ rf_reg18 |= FIELD_PREP(RR_CFGCH_CH, central_ch);
+
+ if (!is_2g_ch)
+ rf_reg18 |= FIELD_PREP(RR_CFGCH_BAND1, CFGCH_BAND1_5G) |
+ FIELD_PREP(RR_CFGCH_BAND0, CFGCH_BAND0_5G);
+
+ rf_reg18 &= ~(RR_CFGCH_POW_LCK | RR_CFGCH_TRX_AH | RR_CFGCH_BCN |
+ RR_CFGCH_BW2) & RFREG_MASK;
+ rf_reg18 |= RR_CFGCH_BW2;
+
+ if (path == RF_PATH_A && dav)
+ _set_ch(rtwdev, rf_reg18);
+ else
+ rtw89_write_rf(rtwdev, path, reg18_addr, RFREG_MASK, rf_reg18);
+
+ rtw89_write_rf(rtwdev, path, RR_LCKST, RR_LCKST_BIN, 0);
+ rtw89_write_rf(rtwdev, path, RR_LCKST, RR_LCKST_BIN, 1);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
+ "[RFK]CH: %d for Path-%d, reg0x%x = 0x%x\n",
+ central_ch, path, reg18_addr,
+ rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK));
+}
+
+static void _ctrl_ch(struct rtw89_dev *rtwdev, u8 central_ch)
+{
+ _ch_setting(rtwdev, RF_PATH_A, central_ch, true);
+ _ch_setting(rtwdev, RF_PATH_A, central_ch, false);
+}
+
+static void _set_rxbb_bw(struct rtw89_dev *rtwdev, enum rtw89_bandwidth bw,
+ enum rtw89_rf_path path)
+{
+ rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x1);
+ rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M2, 0x12);
+
+ if (bw == RTW89_CHANNEL_WIDTH_20)
+ rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x1b);
+ else if (bw == RTW89_CHANNEL_WIDTH_40)
+ rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x13);
+ else if (bw == RTW89_CHANNEL_WIDTH_80)
+ rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0xb);
+ else
+ rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x3);
+
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK] set S%d RXBB BW 0x3F = 0x%x\n", path,
+ rtw89_read_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB));
+
+ rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x0);
+}
+
+static void _rxbb_bw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
+ enum rtw89_bandwidth bw)
+{
+ u8 kpath, path;
+
+ kpath = _kpath(rtwdev, phy);
+
+ for (path = 0; path < RF_PATH_NUM_8851B; path++) {
+ if (!(kpath & BIT(path)))
+ continue;
+
+ _set_rxbb_bw(rtwdev, bw, path);
+ }
+}
+
+static void rtw8851b_ctrl_bw_ch(struct rtw89_dev *rtwdev,
+ enum rtw89_phy_idx phy, u8 central_ch,
+ enum rtw89_band band, enum rtw89_bandwidth bw)
+{
+ _ctrl_ch(rtwdev, central_ch);
+ _ctrl_bw(rtwdev, phy, bw);
+ _rxbb_bw(rtwdev, phy, bw);
+}
+
+void rtw8851b_set_channel_rf(struct rtw89_dev *rtwdev,
+ const struct rtw89_chan *chan,
+ enum rtw89_phy_idx phy_idx)
+{
+ rtw8851b_ctrl_bw_ch(rtwdev, phy_idx, chan->channel, chan->band_type,
+ chan->band_width);
+}
diff --git a/drivers/net/wireless/realtek/rtw89/rtw8851b_rfk.h b/drivers/net/wireless/realtek/rtw89/rtw8851b_rfk.h
new file mode 100644
index 000000000000..b66a23d6d367
--- /dev/null
+++ b/drivers/net/wireless/realtek/rtw89/rtw8851b_rfk.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
+/* Copyright(c) 2022-2023 Realtek Corporation
+ */
+
+#ifndef __RTW89_8851B_RFK_H__
+#define __RTW89_8851B_RFK_H__
+
+#include "core.h"
+
+void rtw8851b_aack(struct rtw89_dev *rtwdev);
+void rtw8851b_lck_init(struct rtw89_dev *rtwdev);
+void rtw8851b_lck_track(struct rtw89_dev *rtwdev);
+void rtw8851b_rck(struct rtw89_dev *rtwdev);
+void rtw8851b_dack(struct rtw89_dev *rtwdev);
+void rtw8851b_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
+void rtw8851b_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
+void rtw8851b_dpk_init(struct rtw89_dev *rtwdev);
+void rtw8851b_dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy);
+void rtw8851b_dpk_track(struct rtw89_dev *rtwdev);
+void rtw8851b_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, bool hwtx_en);
+void rtw8851b_tssi_scan(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy);
+void rtw8851b_wifi_scan_notify(struct rtw89_dev *rtwdev, bool scan_start,
+ enum rtw89_phy_idx phy_idx);
+void rtw8851b_set_channel_rf(struct rtw89_dev *rtwdev,
+ const struct rtw89_chan *chan,
+ enum rtw89_phy_idx phy_idx);
+
+#endif
diff --git a/drivers/net/wireless/realtek/rtw89/rtw8851b_table.c b/drivers/net/wireless/realtek/rtw89/rtw8851b_table.c
index bb724140df4f..c447f91a4bd0 100644
--- a/drivers/net/wireless/realtek/rtw89/rtw8851b_table.c
+++ b/drivers/net/wireless/realtek/rtw89/rtw8851b_table.c
@@ -1273,6 +1273,25 @@ static const struct rtw89_reg2_def rtw89_8851b_phy_radioa_regs[] = {
{0xF0010000, 0x00000000},
{0xF0020000, 0x00000001},
{0xF0030000, 0x00000002},
+ {0xF0010001, 0x00000003},
+ {0xF0020001, 0x00000004},
+ {0xF0030001, 0x00000005},
+ {0xF0040001, 0x00000006},
+ {0xF0050001, 0x00000007},
+ {0xF0060001, 0x00000008},
+ {0x000, 0x00000000},
+ {0x0EF, 0x00080000},
+ {0x033, 0x00000003},
+ {0x03E, 0x00000150},
+ {0x03F, 0x0000D79C},
+ {0x0EF, 0x00000000},
+ {0x052, 0x000C3338},
+ {0x053, 0x000608AF},
+ {0x054, 0x00006C04},
+ {0x063, 0x000FC082},
+ {0x065, 0x00018122},
+ {0x000, 0x00010000},
+ {0x0FE, 0x0000005A},
{0x000, 0x00030000},
{0x018, 0x00013124},
{0x0EF, 0x00080000},
@@ -1834,8 +1853,6 @@ static const struct rtw89_reg2_def rtw89_8851b_phy_radioa_regs[] = {
{0x059, 0x00050033},
{0x061, 0x0005F48A},
{0x062, 0x00077435},
- {0x063, 0x000F80A2},
- {0x065, 0x00018F22},
{0x067, 0x00008060},
{0x07E, 0x0009780B},
{0x0EE, 0x00000004},
@@ -2074,9 +2091,6 @@ static const struct rtw89_reg2_def rtw89_8851b_phy_radioa_regs[] = {
{0x03F, 0x0001C3C3},
{0x0EF, 0x00000000},
{0x051, 0x0003D368},
- {0x052, 0x000A3338},
- {0x053, 0x000688AF},
- {0x054, 0x00012C04},
{0x058, 0x00084221},
{0x05B, 0x000EB000},
{0x100EE, 0x00002000},
@@ -2229,9 +2243,11 @@ static const struct rtw89_reg2_def rtw89_8851b_phy_radioa_regs[] = {
{0x033, 0x00000000},
{0x03F, 0x00000004},
{0x0EF, 0x00000000},
+ {0x000, 0x00010000},
+ {0x0FE, 0x0000005A},
{0x005, 0x00000001},
{0x10005, 0x00000001},
- {0x0FE, 0x00000022},
+ {0x0FE, 0x00000028},
};
static const struct rtw89_reg2_def rtw89_8851b_phy_nctl_regs[] = {
@@ -2306,7 +2322,7 @@ static const struct rtw89_reg2_def rtw89_8851b_phy_nctl_regs[] = {
{0x8144, 0x0b040b03},
{0x8148, 0x07020b04},
{0x814c, 0x07020b04},
- {0x8150, 0xe4e40000},
+ {0x8150, 0xa0a00000},
{0x8158, 0xffffffff},
{0x815c, 0xffffffff},
{0x8160, 0xffffffff},
@@ -3305,7 +3321,7 @@ static const s8 _txpwr_track_delta_swingidx_2g_cck_a_p[] = {
0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4
};
-const u8 rtw89_8851b_tx_shape[RTW89_BAND_MAX][RTW89_RS_TX_SHAPE_NUM]
+const u8 rtw89_8851b_tx_shape[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM]
[RTW89_REGD_NUM] = {
[0][0][RTW89_ACMA] = 0,
[0][0][RTW89_CN] = 0,
@@ -3326,8 +3342,8 @@ const u8 rtw89_8851b_tx_shape[RTW89_BAND_MAX][RTW89_RS_TX_SHAPE_NUM]
[1][1][RTW89_ACMA] = 0,
[1][1][RTW89_CN] = 0,
[1][1][RTW89_ETSI] = 0,
- [1][1][RTW89_FCC] = 3,
- [1][1][RTW89_IC] = 3,
+ [1][1][RTW89_FCC] = 1,
+ [1][1][RTW89_IC] = 1,
[1][1][RTW89_KCC] = 0,
[1][1][RTW89_MKK] = 0,
[1][1][RTW89_UK] = 0,
@@ -4880,9 +4896,9 @@ const s8 rtw89_8851b_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_WW][42] = 30,
[0][0][1][0][RTW89_WW][44] = 30,
[0][0][1][0][RTW89_WW][46] = 30,
- [0][0][1][0][RTW89_WW][48] = 72,
- [0][0][1][0][RTW89_WW][50] = 72,
- [0][0][1][0][RTW89_WW][52] = 72,
+ [0][0][1][0][RTW89_WW][48] = 68,
+ [0][0][1][0][RTW89_WW][50] = 68,
+ [0][0][1][0][RTW89_WW][52] = 68,
[0][1][1][0][RTW89_WW][0] = 0,
[0][1][1][0][RTW89_WW][2] = 0,
[0][1][1][0][RTW89_WW][4] = 0,
@@ -4936,9 +4952,9 @@ const s8 rtw89_8851b_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_WW][42] = 30,
[0][0][2][0][RTW89_WW][44] = 30,
[0][0][2][0][RTW89_WW][46] = 30,
- [0][0][2][0][RTW89_WW][48] = 74,
- [0][0][2][0][RTW89_WW][50] = 76,
- [0][0][2][0][RTW89_WW][52] = 76,
+ [0][0][2][0][RTW89_WW][48] = 70,
+ [0][0][2][0][RTW89_WW][50] = 72,
+ [0][0][2][0][RTW89_WW][52] = 72,
[0][1][2][0][RTW89_WW][0] = 0,
[0][1][2][0][RTW89_WW][2] = 0,
[0][1][2][0][RTW89_WW][4] = 0,
@@ -4995,11 +5011,11 @@ const s8 rtw89_8851b_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_WW][48] = 0,
[0][1][2][1][RTW89_WW][50] = 0,
[0][1][2][1][RTW89_WW][52] = 0,
- [1][0][2][0][RTW89_WW][1] = 64,
+ [1][0][2][0][RTW89_WW][1] = 60,
[1][0][2][0][RTW89_WW][5] = 62,
[1][0][2][0][RTW89_WW][9] = 64,
- [1][0][2][0][RTW89_WW][13] = 64,
- [1][0][2][0][RTW89_WW][16] = 66,
+ [1][0][2][0][RTW89_WW][13] = 60,
+ [1][0][2][0][RTW89_WW][16] = 62,
[1][0][2][0][RTW89_WW][20] = 66,
[1][0][2][0][RTW89_WW][24] = 66,
[1][0][2][0][RTW89_WW][28] = 66,
@@ -5007,8 +5023,8 @@ const s8 rtw89_8851b_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_WW][36] = 76,
[1][0][2][0][RTW89_WW][39] = 30,
[1][0][2][0][RTW89_WW][43] = 30,
- [1][0][2][0][RTW89_WW][47] = 84,
- [1][0][2][0][RTW89_WW][51] = 84,
+ [1][0][2][0][RTW89_WW][47] = 80,
+ [1][0][2][0][RTW89_WW][51] = 80,
[1][1][2][0][RTW89_WW][1] = 0,
[1][1][2][0][RTW89_WW][5] = 0,
[1][1][2][0][RTW89_WW][9] = 0,
@@ -5037,13 +5053,13 @@ const s8 rtw89_8851b_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][1][RTW89_WW][43] = 0,
[1][1][2][1][RTW89_WW][47] = 0,
[1][1][2][1][RTW89_WW][51] = 0,
- [2][0][2][0][RTW89_WW][3] = 62,
- [2][0][2][0][RTW89_WW][11] = 62,
- [2][0][2][0][RTW89_WW][18] = 64,
+ [2][0][2][0][RTW89_WW][3] = 60,
+ [2][0][2][0][RTW89_WW][11] = 58,
+ [2][0][2][0][RTW89_WW][18] = 62,
[2][0][2][0][RTW89_WW][26] = 64,
[2][0][2][0][RTW89_WW][34] = 72,
[2][0][2][0][RTW89_WW][41] = 30,
- [2][0][2][0][RTW89_WW][49] = 74,
+ [2][0][2][0][RTW89_WW][49] = 70,
[2][1][2][0][RTW89_WW][3] = 0,
[2][1][2][0][RTW89_WW][11] = 0,
[2][1][2][0][RTW89_WW][18] = 0,
@@ -5067,7 +5083,7 @@ const s8 rtw89_8851b_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[3][1][2][1][RTW89_WW][7] = 0,
[3][1][2][1][RTW89_WW][22] = 0,
[3][1][2][1][RTW89_WW][45] = 0,
- [0][0][1][0][RTW89_FCC][0] = 80,
+ [0][0][1][0][RTW89_FCC][0] = 76,
[0][0][1][0][RTW89_ETSI][0] = 58,
[0][0][1][0][RTW89_MKK][0] = 60,
[0][0][1][0][RTW89_IC][0] = 62,
@@ -5123,7 +5139,7 @@ const s8 rtw89_8851b_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][12] = 58,
[0][0][1][0][RTW89_CN][12] = 60,
[0][0][1][0][RTW89_UK][12] = 58,
- [0][0][1][0][RTW89_FCC][14] = 78,
+ [0][0][1][0][RTW89_FCC][14] = 74,
[0][0][1][0][RTW89_ETSI][14] = 58,
[0][0][1][0][RTW89_MKK][14] = 60,
[0][0][1][0][RTW89_IC][14] = 64,
@@ -5131,10 +5147,10 @@ const s8 rtw89_8851b_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][14] = 58,
[0][0][1][0][RTW89_CN][14] = 60,
[0][0][1][0][RTW89_UK][14] = 58,
- [0][0][1][0][RTW89_FCC][15] = 78,
+ [0][0][1][0][RTW89_FCC][15] = 74,
[0][0][1][0][RTW89_ETSI][15] = 58,
[0][0][1][0][RTW89_MKK][15] = 78,
- [0][0][1][0][RTW89_IC][15] = 78,
+ [0][0][1][0][RTW89_IC][15] = 74,
[0][0][1][0][RTW89_KCC][15] = 78,
[0][0][1][0][RTW89_ACMA][15] = 58,
[0][0][1][0][RTW89_CN][15] = 127,
@@ -5211,10 +5227,10 @@ const s8 rtw89_8851b_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][33] = 60,
[0][0][1][0][RTW89_CN][33] = 127,
[0][0][1][0][RTW89_UK][33] = 60,
- [0][0][1][0][RTW89_FCC][35] = 72,
+ [0][0][1][0][RTW89_FCC][35] = 68,
[0][0][1][0][RTW89_ETSI][35] = 60,
[0][0][1][0][RTW89_MKK][35] = 78,
- [0][0][1][0][RTW89_IC][35] = 72,
+ [0][0][1][0][RTW89_IC][35] = 68,
[0][0][1][0][RTW89_KCC][35] = 74,
[0][0][1][0][RTW89_ACMA][35] = 60,
[0][0][1][0][RTW89_CN][35] = 127,
@@ -5267,7 +5283,7 @@ const s8 rtw89_8851b_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][46] = 78,
[0][0][1][0][RTW89_CN][46] = 78,
[0][0][1][0][RTW89_UK][46] = 58,
- [0][0][1][0][RTW89_FCC][48] = 72,
+ [0][0][1][0][RTW89_FCC][48] = 68,
[0][0][1][0][RTW89_ETSI][48] = 127,
[0][0][1][0][RTW89_MKK][48] = 127,
[0][0][1][0][RTW89_IC][48] = 127,
@@ -5275,7 +5291,7 @@ const s8 rtw89_8851b_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][48] = 127,
[0][0][1][0][RTW89_CN][48] = 127,
[0][0][1][0][RTW89_UK][48] = 127,
- [0][0][1][0][RTW89_FCC][50] = 72,
+ [0][0][1][0][RTW89_FCC][50] = 68,
[0][0][1][0][RTW89_ETSI][50] = 127,
[0][0][1][0][RTW89_MKK][50] = 127,
[0][0][1][0][RTW89_IC][50] = 127,
@@ -5283,7 +5299,7 @@ const s8 rtw89_8851b_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][50] = 127,
[0][0][1][0][RTW89_CN][50] = 127,
[0][0][1][0][RTW89_UK][50] = 127,
- [0][0][1][0][RTW89_FCC][52] = 72,
+ [0][0][1][0][RTW89_FCC][52] = 68,
[0][0][1][0][RTW89_ETSI][52] = 127,
[0][0][1][0][RTW89_MKK][52] = 127,
[0][0][1][0][RTW89_IC][52] = 127,
@@ -5515,7 +5531,7 @@ const s8 rtw89_8851b_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][52] = 127,
[0][1][1][0][RTW89_CN][52] = 127,
[0][1][1][0][RTW89_UK][52] = 127,
- [0][0][2][0][RTW89_FCC][0] = 78,
+ [0][0][2][0][RTW89_FCC][0] = 74,
[0][0][2][0][RTW89_ETSI][0] = 62,
[0][0][2][0][RTW89_MKK][0] = 62,
[0][0][2][0][RTW89_IC][0] = 64,
@@ -5571,7 +5587,7 @@ const s8 rtw89_8851b_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][12] = 62,
[0][0][2][0][RTW89_CN][12] = 62,
[0][0][2][0][RTW89_UK][12] = 62,
- [0][0][2][0][RTW89_FCC][14] = 76,
+ [0][0][2][0][RTW89_FCC][14] = 72,
[0][0][2][0][RTW89_ETSI][14] = 62,
[0][0][2][0][RTW89_MKK][14] = 62,
[0][0][2][0][RTW89_IC][14] = 64,
@@ -5579,10 +5595,10 @@ const s8 rtw89_8851b_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][14] = 62,
[0][0][2][0][RTW89_CN][14] = 62,
[0][0][2][0][RTW89_UK][14] = 62,
- [0][0][2][0][RTW89_FCC][15] = 76,
+ [0][0][2][0][RTW89_FCC][15] = 72,
[0][0][2][0][RTW89_ETSI][15] = 60,
[0][0][2][0][RTW89_MKK][15] = 78,
- [0][0][2][0][RTW89_IC][15] = 76,
+ [0][0][2][0][RTW89_IC][15] = 72,
[0][0][2][0][RTW89_KCC][15] = 78,
[0][0][2][0][RTW89_ACMA][15] = 60,
[0][0][2][0][RTW89_CN][15] = 127,
@@ -5659,10 +5675,10 @@ const s8 rtw89_8851b_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][33] = 62,
[0][0][2][0][RTW89_CN][33] = 127,
[0][0][2][0][RTW89_UK][33] = 62,
- [0][0][2][0][RTW89_FCC][35] = 72,
+ [0][0][2][0][RTW89_FCC][35] = 68,
[0][0][2][0][RTW89_ETSI][35] = 62,
[0][0][2][0][RTW89_MKK][35] = 78,
- [0][0][2][0][RTW89_IC][35] = 72,
+ [0][0][2][0][RTW89_IC][35] = 68,
[0][0][2][0][RTW89_KCC][35] = 74,
[0][0][2][0][RTW89_ACMA][35] = 62,
[0][0][2][0][RTW89_CN][35] = 127,
@@ -5715,7 +5731,7 @@ const s8 rtw89_8851b_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][46] = 78,
[0][0][2][0][RTW89_CN][46] = 78,
[0][0][2][0][RTW89_UK][46] = 60,
- [0][0][2][0][RTW89_FCC][48] = 74,
+ [0][0][2][0][RTW89_FCC][48] = 70,
[0][0][2][0][RTW89_ETSI][48] = 127,
[0][0][2][0][RTW89_MKK][48] = 127,
[0][0][2][0][RTW89_IC][48] = 127,
@@ -5723,7 +5739,7 @@ const s8 rtw89_8851b_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][48] = 127,
[0][0][2][0][RTW89_CN][48] = 127,
[0][0][2][0][RTW89_UK][48] = 127,
- [0][0][2][0][RTW89_FCC][50] = 76,
+ [0][0][2][0][RTW89_FCC][50] = 72,
[0][0][2][0][RTW89_ETSI][50] = 127,
[0][0][2][0][RTW89_MKK][50] = 127,
[0][0][2][0][RTW89_IC][50] = 127,
@@ -5731,7 +5747,7 @@ const s8 rtw89_8851b_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][50] = 127,
[0][0][2][0][RTW89_CN][50] = 127,
[0][0][2][0][RTW89_UK][50] = 127,
- [0][0][2][0][RTW89_FCC][52] = 76,
+ [0][0][2][0][RTW89_FCC][52] = 72,
[0][0][2][0][RTW89_ETSI][52] = 127,
[0][0][2][0][RTW89_MKK][52] = 127,
[0][0][2][0][RTW89_IC][52] = 127,
@@ -6187,10 +6203,10 @@ const s8 rtw89_8851b_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][52] = 127,
[0][1][2][1][RTW89_CN][52] = 127,
[0][1][2][1][RTW89_UK][52] = 127,
- [1][0][2][0][RTW89_FCC][1] = 68,
+ [1][0][2][0][RTW89_FCC][1] = 64,
[1][0][2][0][RTW89_ETSI][1] = 64,
[1][0][2][0][RTW89_MKK][1] = 64,
- [1][0][2][0][RTW89_IC][1] = 64,
+ [1][0][2][0][RTW89_IC][1] = 60,
[1][0][2][0][RTW89_KCC][1] = 74,
[1][0][2][0][RTW89_ACMA][1] = 64,
[1][0][2][0][RTW89_CN][1] = 64,
@@ -6211,18 +6227,18 @@ const s8 rtw89_8851b_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_ACMA][9] = 64,
[1][0][2][0][RTW89_CN][9] = 64,
[1][0][2][0][RTW89_UK][9] = 64,
- [1][0][2][0][RTW89_FCC][13] = 66,
+ [1][0][2][0][RTW89_FCC][13] = 62,
[1][0][2][0][RTW89_ETSI][13] = 64,
[1][0][2][0][RTW89_MKK][13] = 64,
- [1][0][2][0][RTW89_IC][13] = 64,
+ [1][0][2][0][RTW89_IC][13] = 60,
[1][0][2][0][RTW89_KCC][13] = 72,
[1][0][2][0][RTW89_ACMA][13] = 64,
[1][0][2][0][RTW89_CN][13] = 64,
[1][0][2][0][RTW89_UK][13] = 64,
- [1][0][2][0][RTW89_FCC][16] = 66,
+ [1][0][2][0][RTW89_FCC][16] = 62,
[1][0][2][0][RTW89_ETSI][16] = 66,
[1][0][2][0][RTW89_MKK][16] = 80,
- [1][0][2][0][RTW89_IC][16] = 66,
+ [1][0][2][0][RTW89_IC][16] = 62,
[1][0][2][0][RTW89_KCC][16] = 74,
[1][0][2][0][RTW89_ACMA][16] = 66,
[1][0][2][0][RTW89_CN][16] = 127,
@@ -6230,7 +6246,7 @@ const s8 rtw89_8851b_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_FCC][20] = 80,
[1][0][2][0][RTW89_ETSI][20] = 66,
[1][0][2][0][RTW89_MKK][20] = 80,
- [1][0][2][0][RTW89_IC][20] = 80,
+ [1][0][2][0][RTW89_IC][20] = 76,
[1][0][2][0][RTW89_KCC][20] = 74,
[1][0][2][0][RTW89_ACMA][20] = 66,
[1][0][2][0][RTW89_CN][20] = 127,
@@ -6251,10 +6267,10 @@ const s8 rtw89_8851b_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_ACMA][28] = 127,
[1][0][2][0][RTW89_CN][28] = 127,
[1][0][2][0][RTW89_UK][28] = 66,
- [1][0][2][0][RTW89_FCC][32] = 76,
+ [1][0][2][0][RTW89_FCC][32] = 72,
[1][0][2][0][RTW89_ETSI][32] = 66,
[1][0][2][0][RTW89_MKK][32] = 80,
- [1][0][2][0][RTW89_IC][32] = 76,
+ [1][0][2][0][RTW89_IC][32] = 72,
[1][0][2][0][RTW89_KCC][32] = 78,
[1][0][2][0][RTW89_ACMA][32] = 66,
[1][0][2][0][RTW89_CN][32] = 127,
@@ -6270,7 +6286,7 @@ const s8 rtw89_8851b_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_FCC][39] = 84,
[1][0][2][0][RTW89_ETSI][39] = 30,
[1][0][2][0][RTW89_MKK][39] = 127,
- [1][0][2][0][RTW89_IC][39] = 84,
+ [1][0][2][0][RTW89_IC][39] = 80,
[1][0][2][0][RTW89_KCC][39] = 68,
[1][0][2][0][RTW89_ACMA][39] = 80,
[1][0][2][0][RTW89_CN][39] = 70,
@@ -6283,7 +6299,7 @@ const s8 rtw89_8851b_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_ACMA][43] = 80,
[1][0][2][0][RTW89_CN][43] = 80,
[1][0][2][0][RTW89_UK][43] = 64,
- [1][0][2][0][RTW89_FCC][47] = 84,
+ [1][0][2][0][RTW89_FCC][47] = 80,
[1][0][2][0][RTW89_ETSI][47] = 127,
[1][0][2][0][RTW89_MKK][47] = 127,
[1][0][2][0][RTW89_IC][47] = 127,
@@ -6291,7 +6307,7 @@ const s8 rtw89_8851b_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_ACMA][47] = 127,
[1][0][2][0][RTW89_CN][47] = 127,
[1][0][2][0][RTW89_UK][47] = 127,
- [1][0][2][0][RTW89_FCC][51] = 84,
+ [1][0][2][0][RTW89_FCC][51] = 80,
[1][0][2][0][RTW89_ETSI][51] = 127,
[1][0][2][0][RTW89_MKK][51] = 127,
[1][0][2][0][RTW89_IC][51] = 127,
@@ -6523,26 +6539,26 @@ const s8 rtw89_8851b_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][1][RTW89_ACMA][51] = 127,
[1][1][2][1][RTW89_CN][51] = 127,
[1][1][2][1][RTW89_UK][51] = 127,
- [2][0][2][0][RTW89_FCC][3] = 76,
+ [2][0][2][0][RTW89_FCC][3] = 72,
[2][0][2][0][RTW89_ETSI][3] = 64,
[2][0][2][0][RTW89_MKK][3] = 62,
- [2][0][2][0][RTW89_IC][3] = 64,
+ [2][0][2][0][RTW89_IC][3] = 60,
[2][0][2][0][RTW89_KCC][3] = 72,
[2][0][2][0][RTW89_ACMA][3] = 64,
[2][0][2][0][RTW89_CN][3] = 64,
[2][0][2][0][RTW89_UK][3] = 64,
- [2][0][2][0][RTW89_FCC][11] = 64,
+ [2][0][2][0][RTW89_FCC][11] = 60,
[2][0][2][0][RTW89_ETSI][11] = 64,
[2][0][2][0][RTW89_MKK][11] = 64,
- [2][0][2][0][RTW89_IC][11] = 62,
+ [2][0][2][0][RTW89_IC][11] = 58,
[2][0][2][0][RTW89_KCC][11] = 72,
[2][0][2][0][RTW89_ACMA][11] = 64,
[2][0][2][0][RTW89_CN][11] = 64,
[2][0][2][0][RTW89_UK][11] = 64,
- [2][0][2][0][RTW89_FCC][18] = 66,
+ [2][0][2][0][RTW89_FCC][18] = 62,
[2][0][2][0][RTW89_ETSI][18] = 64,
[2][0][2][0][RTW89_MKK][18] = 72,
- [2][0][2][0][RTW89_IC][18] = 66,
+ [2][0][2][0][RTW89_IC][18] = 62,
[2][0][2][0][RTW89_KCC][18] = 72,
[2][0][2][0][RTW89_ACMA][18] = 64,
[2][0][2][0][RTW89_CN][18] = 127,
@@ -6558,7 +6574,7 @@ const s8 rtw89_8851b_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[2][0][2][0][RTW89_FCC][34] = 76,
[2][0][2][0][RTW89_ETSI][34] = 127,
[2][0][2][0][RTW89_MKK][34] = 72,
- [2][0][2][0][RTW89_IC][34] = 76,
+ [2][0][2][0][RTW89_IC][34] = 72,
[2][0][2][0][RTW89_KCC][34] = 72,
[2][0][2][0][RTW89_ACMA][34] = 72,
[2][0][2][0][RTW89_CN][34] = 127,
@@ -6566,12 +6582,12 @@ const s8 rtw89_8851b_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[2][0][2][0][RTW89_FCC][41] = 76,
[2][0][2][0][RTW89_ETSI][41] = 30,
[2][0][2][0][RTW89_MKK][41] = 127,
- [2][0][2][0][RTW89_IC][41] = 76,
+ [2][0][2][0][RTW89_IC][41] = 72,
[2][0][2][0][RTW89_KCC][41] = 64,
[2][0][2][0][RTW89_ACMA][41] = 72,
[2][0][2][0][RTW89_CN][41] = 72,
[2][0][2][0][RTW89_UK][41] = 64,
- [2][0][2][0][RTW89_FCC][49] = 74,
+ [2][0][2][0][RTW89_FCC][49] = 70,
[2][0][2][0][RTW89_ETSI][49] = 127,
[2][0][2][0][RTW89_MKK][49] = 127,
[2][0][2][0][RTW89_IC][49] = 127,
@@ -10590,9 +10606,9 @@ const s8 rtw89_8851b_txpwr_lmt_5g_type2[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_WW][42] = 30,
[0][0][1][0][RTW89_WW][44] = 30,
[0][0][1][0][RTW89_WW][46] = 30,
- [0][0][1][0][RTW89_WW][48] = 72,
- [0][0][1][0][RTW89_WW][50] = 72,
- [0][0][1][0][RTW89_WW][52] = 72,
+ [0][0][1][0][RTW89_WW][48] = 68,
+ [0][0][1][0][RTW89_WW][50] = 68,
+ [0][0][1][0][RTW89_WW][52] = 68,
[0][1][1][0][RTW89_WW][0] = 0,
[0][1][1][0][RTW89_WW][2] = 0,
[0][1][1][0][RTW89_WW][4] = 0,
@@ -10646,9 +10662,9 @@ const s8 rtw89_8851b_txpwr_lmt_5g_type2[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_WW][42] = 30,
[0][0][2][0][RTW89_WW][44] = 30,
[0][0][2][0][RTW89_WW][46] = 30,
- [0][0][2][0][RTW89_WW][48] = 74,
- [0][0][2][0][RTW89_WW][50] = 74,
- [0][0][2][0][RTW89_WW][52] = 74,
+ [0][0][2][0][RTW89_WW][48] = 70,
+ [0][0][2][0][RTW89_WW][50] = 70,
+ [0][0][2][0][RTW89_WW][52] = 70,
[0][1][2][0][RTW89_WW][0] = 0,
[0][1][2][0][RTW89_WW][2] = 0,
[0][1][2][0][RTW89_WW][4] = 0,
@@ -10705,11 +10721,11 @@ const s8 rtw89_8851b_txpwr_lmt_5g_type2[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_WW][48] = 0,
[0][1][2][1][RTW89_WW][50] = 0,
[0][1][2][1][RTW89_WW][52] = 0,
- [1][0][2][0][RTW89_WW][1] = 64,
+ [1][0][2][0][RTW89_WW][1] = 60,
[1][0][2][0][RTW89_WW][5] = 62,
[1][0][2][0][RTW89_WW][9] = 64,
- [1][0][2][0][RTW89_WW][13] = 64,
- [1][0][2][0][RTW89_WW][16] = 66,
+ [1][0][2][0][RTW89_WW][13] = 60,
+ [1][0][2][0][RTW89_WW][16] = 62,
[1][0][2][0][RTW89_WW][20] = 66,
[1][0][2][0][RTW89_WW][24] = 66,
[1][0][2][0][RTW89_WW][28] = 66,
@@ -10717,8 +10733,8 @@ const s8 rtw89_8851b_txpwr_lmt_5g_type2[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_WW][36] = 76,
[1][0][2][0][RTW89_WW][39] = 30,
[1][0][2][0][RTW89_WW][43] = 30,
- [1][0][2][0][RTW89_WW][47] = 80,
- [1][0][2][0][RTW89_WW][51] = 80,
+ [1][0][2][0][RTW89_WW][47] = 76,
+ [1][0][2][0][RTW89_WW][51] = 76,
[1][1][2][0][RTW89_WW][1] = 0,
[1][1][2][0][RTW89_WW][5] = 0,
[1][1][2][0][RTW89_WW][9] = 0,
@@ -10747,13 +10763,13 @@ const s8 rtw89_8851b_txpwr_lmt_5g_type2[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][1][RTW89_WW][43] = 0,
[1][1][2][1][RTW89_WW][47] = 0,
[1][1][2][1][RTW89_WW][51] = 0,
- [2][0][2][0][RTW89_WW][3] = 62,
- [2][0][2][0][RTW89_WW][11] = 62,
- [2][0][2][0][RTW89_WW][18] = 64,
+ [2][0][2][0][RTW89_WW][3] = 60,
+ [2][0][2][0][RTW89_WW][11] = 58,
+ [2][0][2][0][RTW89_WW][18] = 62,
[2][0][2][0][RTW89_WW][26] = 64,
[2][0][2][0][RTW89_WW][34] = 68,
[2][0][2][0][RTW89_WW][41] = 30,
- [2][0][2][0][RTW89_WW][49] = 72,
+ [2][0][2][0][RTW89_WW][49] = 68,
[2][1][2][0][RTW89_WW][3] = 0,
[2][1][2][0][RTW89_WW][11] = 0,
[2][1][2][0][RTW89_WW][18] = 0,
@@ -10777,7 +10793,7 @@ const s8 rtw89_8851b_txpwr_lmt_5g_type2[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[3][1][2][1][RTW89_WW][7] = 0,
[3][1][2][1][RTW89_WW][22] = 0,
[3][1][2][1][RTW89_WW][45] = 0,
- [0][0][1][0][RTW89_FCC][0] = 78,
+ [0][0][1][0][RTW89_FCC][0] = 74,
[0][0][1][0][RTW89_ETSI][0] = 58,
[0][0][1][0][RTW89_MKK][0] = 60,
[0][0][1][0][RTW89_IC][0] = 62,
@@ -10833,7 +10849,7 @@ const s8 rtw89_8851b_txpwr_lmt_5g_type2[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][12] = 58,
[0][0][1][0][RTW89_CN][12] = 60,
[0][0][1][0][RTW89_UK][12] = 58,
- [0][0][1][0][RTW89_FCC][14] = 76,
+ [0][0][1][0][RTW89_FCC][14] = 72,
[0][0][1][0][RTW89_ETSI][14] = 58,
[0][0][1][0][RTW89_MKK][14] = 60,
[0][0][1][0][RTW89_IC][14] = 62,
@@ -10841,10 +10857,10 @@ const s8 rtw89_8851b_txpwr_lmt_5g_type2[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][14] = 58,
[0][0][1][0][RTW89_CN][14] = 60,
[0][0][1][0][RTW89_UK][14] = 58,
- [0][0][1][0][RTW89_FCC][15] = 76,
+ [0][0][1][0][RTW89_FCC][15] = 72,
[0][0][1][0][RTW89_ETSI][15] = 58,
[0][0][1][0][RTW89_MKK][15] = 74,
- [0][0][1][0][RTW89_IC][15] = 76,
+ [0][0][1][0][RTW89_IC][15] = 72,
[0][0][1][0][RTW89_KCC][15] = 74,
[0][0][1][0][RTW89_ACMA][15] = 58,
[0][0][1][0][RTW89_CN][15] = 127,
@@ -10921,10 +10937,10 @@ const s8 rtw89_8851b_txpwr_lmt_5g_type2[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][33] = 60,
[0][0][1][0][RTW89_CN][33] = 127,
[0][0][1][0][RTW89_UK][33] = 60,
- [0][0][1][0][RTW89_FCC][35] = 70,
+ [0][0][1][0][RTW89_FCC][35] = 66,
[0][0][1][0][RTW89_ETSI][35] = 60,
[0][0][1][0][RTW89_MKK][35] = 74,
- [0][0][1][0][RTW89_IC][35] = 70,
+ [0][0][1][0][RTW89_IC][35] = 66,
[0][0][1][0][RTW89_KCC][35] = 74,
[0][0][1][0][RTW89_ACMA][35] = 60,
[0][0][1][0][RTW89_CN][35] = 127,
@@ -10977,7 +10993,7 @@ const s8 rtw89_8851b_txpwr_lmt_5g_type2[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][46] = 74,
[0][0][1][0][RTW89_CN][46] = 74,
[0][0][1][0][RTW89_UK][46] = 58,
- [0][0][1][0][RTW89_FCC][48] = 72,
+ [0][0][1][0][RTW89_FCC][48] = 68,
[0][0][1][0][RTW89_ETSI][48] = 127,
[0][0][1][0][RTW89_MKK][48] = 127,
[0][0][1][0][RTW89_IC][48] = 127,
@@ -10985,7 +11001,7 @@ const s8 rtw89_8851b_txpwr_lmt_5g_type2[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][48] = 127,
[0][0][1][0][RTW89_CN][48] = 127,
[0][0][1][0][RTW89_UK][48] = 127,
- [0][0][1][0][RTW89_FCC][50] = 72,
+ [0][0][1][0][RTW89_FCC][50] = 68,
[0][0][1][0][RTW89_ETSI][50] = 127,
[0][0][1][0][RTW89_MKK][50] = 127,
[0][0][1][0][RTW89_IC][50] = 127,
@@ -10993,7 +11009,7 @@ const s8 rtw89_8851b_txpwr_lmt_5g_type2[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][50] = 127,
[0][0][1][0][RTW89_CN][50] = 127,
[0][0][1][0][RTW89_UK][50] = 127,
- [0][0][1][0][RTW89_FCC][52] = 72,
+ [0][0][1][0][RTW89_FCC][52] = 68,
[0][0][1][0][RTW89_ETSI][52] = 127,
[0][0][1][0][RTW89_MKK][52] = 127,
[0][0][1][0][RTW89_IC][52] = 127,
@@ -11225,7 +11241,7 @@ const s8 rtw89_8851b_txpwr_lmt_5g_type2[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][52] = 127,
[0][1][1][0][RTW89_CN][52] = 127,
[0][1][1][0][RTW89_UK][52] = 127,
- [0][0][2][0][RTW89_FCC][0] = 76,
+ [0][0][2][0][RTW89_FCC][0] = 72,
[0][0][2][0][RTW89_ETSI][0] = 62,
[0][0][2][0][RTW89_MKK][0] = 62,
[0][0][2][0][RTW89_IC][0] = 64,
@@ -11281,7 +11297,7 @@ const s8 rtw89_8851b_txpwr_lmt_5g_type2[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][12] = 62,
[0][0][2][0][RTW89_CN][12] = 62,
[0][0][2][0][RTW89_UK][12] = 62,
- [0][0][2][0][RTW89_FCC][14] = 74,
+ [0][0][2][0][RTW89_FCC][14] = 70,
[0][0][2][0][RTW89_ETSI][14] = 62,
[0][0][2][0][RTW89_MKK][14] = 62,
[0][0][2][0][RTW89_IC][14] = 64,
@@ -11289,10 +11305,10 @@ const s8 rtw89_8851b_txpwr_lmt_5g_type2[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][14] = 62,
[0][0][2][0][RTW89_CN][14] = 62,
[0][0][2][0][RTW89_UK][14] = 62,
- [0][0][2][0][RTW89_FCC][15] = 74,
+ [0][0][2][0][RTW89_FCC][15] = 70,
[0][0][2][0][RTW89_ETSI][15] = 60,
[0][0][2][0][RTW89_MKK][15] = 74,
- [0][0][2][0][RTW89_IC][15] = 74,
+ [0][0][2][0][RTW89_IC][15] = 70,
[0][0][2][0][RTW89_KCC][15] = 74,
[0][0][2][0][RTW89_ACMA][15] = 60,
[0][0][2][0][RTW89_CN][15] = 127,
@@ -11369,10 +11385,10 @@ const s8 rtw89_8851b_txpwr_lmt_5g_type2[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][33] = 62,
[0][0][2][0][RTW89_CN][33] = 127,
[0][0][2][0][RTW89_UK][33] = 62,
- [0][0][2][0][RTW89_FCC][35] = 72,
+ [0][0][2][0][RTW89_FCC][35] = 68,
[0][0][2][0][RTW89_ETSI][35] = 62,
[0][0][2][0][RTW89_MKK][35] = 74,
- [0][0][2][0][RTW89_IC][35] = 72,
+ [0][0][2][0][RTW89_IC][35] = 68,
[0][0][2][0][RTW89_KCC][35] = 74,
[0][0][2][0][RTW89_ACMA][35] = 62,
[0][0][2][0][RTW89_CN][35] = 127,
@@ -11425,7 +11441,7 @@ const s8 rtw89_8851b_txpwr_lmt_5g_type2[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][46] = 74,
[0][0][2][0][RTW89_CN][46] = 74,
[0][0][2][0][RTW89_UK][46] = 60,
- [0][0][2][0][RTW89_FCC][48] = 74,
+ [0][0][2][0][RTW89_FCC][48] = 70,
[0][0][2][0][RTW89_ETSI][48] = 127,
[0][0][2][0][RTW89_MKK][48] = 127,
[0][0][2][0][RTW89_IC][48] = 127,
@@ -11433,7 +11449,7 @@ const s8 rtw89_8851b_txpwr_lmt_5g_type2[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][48] = 127,
[0][0][2][0][RTW89_CN][48] = 127,
[0][0][2][0][RTW89_UK][48] = 127,
- [0][0][2][0][RTW89_FCC][50] = 74,
+ [0][0][2][0][RTW89_FCC][50] = 70,
[0][0][2][0][RTW89_ETSI][50] = 127,
[0][0][2][0][RTW89_MKK][50] = 127,
[0][0][2][0][RTW89_IC][50] = 127,
@@ -11441,7 +11457,7 @@ const s8 rtw89_8851b_txpwr_lmt_5g_type2[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][50] = 127,
[0][0][2][0][RTW89_CN][50] = 127,
[0][0][2][0][RTW89_UK][50] = 127,
- [0][0][2][0][RTW89_FCC][52] = 74,
+ [0][0][2][0][RTW89_FCC][52] = 70,
[0][0][2][0][RTW89_ETSI][52] = 127,
[0][0][2][0][RTW89_MKK][52] = 127,
[0][0][2][0][RTW89_IC][52] = 127,
@@ -11897,10 +11913,10 @@ const s8 rtw89_8851b_txpwr_lmt_5g_type2[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][52] = 127,
[0][1][2][1][RTW89_CN][52] = 127,
[0][1][2][1][RTW89_UK][52] = 127,
- [1][0][2][0][RTW89_FCC][1] = 66,
+ [1][0][2][0][RTW89_FCC][1] = 62,
[1][0][2][0][RTW89_ETSI][1] = 64,
[1][0][2][0][RTW89_MKK][1] = 64,
- [1][0][2][0][RTW89_IC][1] = 64,
+ [1][0][2][0][RTW89_IC][1] = 60,
[1][0][2][0][RTW89_KCC][1] = 74,
[1][0][2][0][RTW89_ACMA][1] = 64,
[1][0][2][0][RTW89_CN][1] = 64,
@@ -11921,18 +11937,18 @@ const s8 rtw89_8851b_txpwr_lmt_5g_type2[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_ACMA][9] = 64,
[1][0][2][0][RTW89_CN][9] = 64,
[1][0][2][0][RTW89_UK][9] = 64,
- [1][0][2][0][RTW89_FCC][13] = 64,
+ [1][0][2][0][RTW89_FCC][13] = 60,
[1][0][2][0][RTW89_ETSI][13] = 64,
[1][0][2][0][RTW89_MKK][13] = 64,
- [1][0][2][0][RTW89_IC][13] = 64,
+ [1][0][2][0][RTW89_IC][13] = 60,
[1][0][2][0][RTW89_KCC][13] = 72,
[1][0][2][0][RTW89_ACMA][13] = 64,
[1][0][2][0][RTW89_CN][13] = 64,
[1][0][2][0][RTW89_UK][13] = 64,
- [1][0][2][0][RTW89_FCC][16] = 66,
+ [1][0][2][0][RTW89_FCC][16] = 62,
[1][0][2][0][RTW89_ETSI][16] = 66,
[1][0][2][0][RTW89_MKK][16] = 76,
- [1][0][2][0][RTW89_IC][16] = 66,
+ [1][0][2][0][RTW89_IC][16] = 62,
[1][0][2][0][RTW89_KCC][16] = 74,
[1][0][2][0][RTW89_ACMA][16] = 66,
[1][0][2][0][RTW89_CN][16] = 127,
@@ -11940,7 +11956,7 @@ const s8 rtw89_8851b_txpwr_lmt_5g_type2[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_FCC][20] = 80,
[1][0][2][0][RTW89_ETSI][20] = 66,
[1][0][2][0][RTW89_MKK][20] = 76,
- [1][0][2][0][RTW89_IC][20] = 80,
+ [1][0][2][0][RTW89_IC][20] = 76,
[1][0][2][0][RTW89_KCC][20] = 74,
[1][0][2][0][RTW89_ACMA][20] = 66,
[1][0][2][0][RTW89_CN][20] = 127,
@@ -11961,10 +11977,10 @@ const s8 rtw89_8851b_txpwr_lmt_5g_type2[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_ACMA][28] = 127,
[1][0][2][0][RTW89_CN][28] = 127,
[1][0][2][0][RTW89_UK][28] = 66,
- [1][0][2][0][RTW89_FCC][32] = 74,
+ [1][0][2][0][RTW89_FCC][32] = 70,
[1][0][2][0][RTW89_ETSI][32] = 66,
[1][0][2][0][RTW89_MKK][32] = 76,
- [1][0][2][0][RTW89_IC][32] = 74,
+ [1][0][2][0][RTW89_IC][32] = 70,
[1][0][2][0][RTW89_KCC][32] = 76,
[1][0][2][0][RTW89_ACMA][32] = 66,
[1][0][2][0][RTW89_CN][32] = 127,
@@ -11980,7 +11996,7 @@ const s8 rtw89_8851b_txpwr_lmt_5g_type2[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_FCC][39] = 80,
[1][0][2][0][RTW89_ETSI][39] = 30,
[1][0][2][0][RTW89_MKK][39] = 127,
- [1][0][2][0][RTW89_IC][39] = 80,
+ [1][0][2][0][RTW89_IC][39] = 76,
[1][0][2][0][RTW89_KCC][39] = 68,
[1][0][2][0][RTW89_ACMA][39] = 76,
[1][0][2][0][RTW89_CN][39] = 70,
@@ -11993,7 +12009,7 @@ const s8 rtw89_8851b_txpwr_lmt_5g_type2[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_ACMA][43] = 76,
[1][0][2][0][RTW89_CN][43] = 76,
[1][0][2][0][RTW89_UK][43] = 64,
- [1][0][2][0][RTW89_FCC][47] = 80,
+ [1][0][2][0][RTW89_FCC][47] = 76,
[1][0][2][0][RTW89_ETSI][47] = 127,
[1][0][2][0][RTW89_MKK][47] = 127,
[1][0][2][0][RTW89_IC][47] = 127,
@@ -12001,7 +12017,7 @@ const s8 rtw89_8851b_txpwr_lmt_5g_type2[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_ACMA][47] = 127,
[1][0][2][0][RTW89_CN][47] = 127,
[1][0][2][0][RTW89_UK][47] = 127,
- [1][0][2][0][RTW89_FCC][51] = 80,
+ [1][0][2][0][RTW89_FCC][51] = 76,
[1][0][2][0][RTW89_ETSI][51] = 127,
[1][0][2][0][RTW89_MKK][51] = 127,
[1][0][2][0][RTW89_IC][51] = 127,
@@ -12233,26 +12249,26 @@ const s8 rtw89_8851b_txpwr_lmt_5g_type2[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][1][RTW89_ACMA][51] = 127,
[1][1][2][1][RTW89_CN][51] = 127,
[1][1][2][1][RTW89_UK][51] = 127,
- [2][0][2][0][RTW89_FCC][3] = 72,
+ [2][0][2][0][RTW89_FCC][3] = 68,
[2][0][2][0][RTW89_ETSI][3] = 64,
[2][0][2][0][RTW89_MKK][3] = 62,
- [2][0][2][0][RTW89_IC][3] = 64,
+ [2][0][2][0][RTW89_IC][3] = 60,
[2][0][2][0][RTW89_KCC][3] = 68,
[2][0][2][0][RTW89_ACMA][3] = 64,
[2][0][2][0][RTW89_CN][3] = 64,
[2][0][2][0][RTW89_UK][3] = 64,
- [2][0][2][0][RTW89_FCC][11] = 62,
+ [2][0][2][0][RTW89_FCC][11] = 58,
[2][0][2][0][RTW89_ETSI][11] = 64,
[2][0][2][0][RTW89_MKK][11] = 64,
- [2][0][2][0][RTW89_IC][11] = 62,
+ [2][0][2][0][RTW89_IC][11] = 58,
[2][0][2][0][RTW89_KCC][11] = 68,
[2][0][2][0][RTW89_ACMA][11] = 64,
[2][0][2][0][RTW89_CN][11] = 64,
[2][0][2][0][RTW89_UK][11] = 64,
- [2][0][2][0][RTW89_FCC][18] = 66,
+ [2][0][2][0][RTW89_FCC][18] = 62,
[2][0][2][0][RTW89_ETSI][18] = 64,
[2][0][2][0][RTW89_MKK][18] = 68,
- [2][0][2][0][RTW89_IC][18] = 66,
+ [2][0][2][0][RTW89_IC][18] = 62,
[2][0][2][0][RTW89_KCC][18] = 68,
[2][0][2][0][RTW89_ACMA][18] = 64,
[2][0][2][0][RTW89_CN][18] = 127,
@@ -12268,7 +12284,7 @@ const s8 rtw89_8851b_txpwr_lmt_5g_type2[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[2][0][2][0][RTW89_FCC][34] = 72,
[2][0][2][0][RTW89_ETSI][34] = 127,
[2][0][2][0][RTW89_MKK][34] = 68,
- [2][0][2][0][RTW89_IC][34] = 72,
+ [2][0][2][0][RTW89_IC][34] = 68,
[2][0][2][0][RTW89_KCC][34] = 68,
[2][0][2][0][RTW89_ACMA][34] = 68,
[2][0][2][0][RTW89_CN][34] = 127,
@@ -12276,12 +12292,12 @@ const s8 rtw89_8851b_txpwr_lmt_5g_type2[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[2][0][2][0][RTW89_FCC][41] = 72,
[2][0][2][0][RTW89_ETSI][41] = 30,
[2][0][2][0][RTW89_MKK][41] = 127,
- [2][0][2][0][RTW89_IC][41] = 72,
+ [2][0][2][0][RTW89_IC][41] = 68,
[2][0][2][0][RTW89_KCC][41] = 64,
[2][0][2][0][RTW89_ACMA][41] = 68,
[2][0][2][0][RTW89_CN][41] = 68,
[2][0][2][0][RTW89_UK][41] = 64,
- [2][0][2][0][RTW89_FCC][49] = 72,
+ [2][0][2][0][RTW89_FCC][49] = 68,
[2][0][2][0][RTW89_ETSI][49] = 127,
[2][0][2][0][RTW89_MKK][49] = 127,
[2][0][2][0][RTW89_IC][49] = 127,
diff --git a/drivers/net/wireless/realtek/rtw89/rtw8851b_table.h b/drivers/net/wireless/realtek/rtw89/rtw8851b_table.h
index f2e673ba39c8..a8737de02f66 100644
--- a/drivers/net/wireless/realtek/rtw89/rtw8851b_table.h
+++ b/drivers/net/wireless/realtek/rtw89/rtw8851b_table.h
@@ -13,7 +13,7 @@ extern const struct rtw89_phy_table rtw89_8851b_phy_radioa_table;
extern const struct rtw89_phy_table rtw89_8851b_phy_nctl_table;
extern const struct rtw89_txpwr_table rtw89_8851b_byr_table;
extern const struct rtw89_txpwr_track_cfg rtw89_8851b_trk_cfg;
-extern const u8 rtw89_8851b_tx_shape[RTW89_BAND_MAX][RTW89_RS_TX_SHAPE_NUM]
+extern const u8 rtw89_8851b_tx_shape[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM]
[RTW89_REGD_NUM];
extern const struct rtw89_rfe_parms rtw89_8851b_dflt_parms;
extern const struct rtw89_rfe_parms_conf rtw89_8851b_rfe_parms_conf[];
diff --git a/drivers/net/wireless/realtek/rtw89/rtw8851be.c b/drivers/net/wireless/realtek/rtw89/rtw8851be.c
new file mode 100644
index 000000000000..0f7711c50bd1
--- /dev/null
+++ b/drivers/net/wireless/realtek/rtw89/rtw8851be.c
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/* Copyright(c) 2022-2023 Realtek Corporation
+ */
+
+#include <linux/module.h>
+#include <linux/pci.h>
+
+#include "pci.h"
+#include "reg.h"
+#include "rtw8851b.h"
+
+static const struct rtw89_pci_info rtw8851b_pci_info = {
+ .txbd_trunc_mode = MAC_AX_BD_TRUNC,
+ .rxbd_trunc_mode = MAC_AX_BD_TRUNC,
+ .rxbd_mode = MAC_AX_RXBD_PKT,
+ .tag_mode = MAC_AX_TAG_MULTI,
+ .tx_burst = MAC_AX_TX_BURST_2048B,
+ .rx_burst = MAC_AX_RX_BURST_128B,
+ .wd_dma_idle_intvl = MAC_AX_WD_DMA_INTVL_256NS,
+ .wd_dma_act_intvl = MAC_AX_WD_DMA_INTVL_256NS,
+ .multi_tag_num = MAC_AX_TAG_NUM_8,
+ .lbc_en = MAC_AX_PCIE_ENABLE,
+ .lbc_tmr = MAC_AX_LBC_TMR_2MS,
+ .autok_en = MAC_AX_PCIE_DISABLE,
+ .io_rcy_en = MAC_AX_PCIE_DISABLE,
+ .io_rcy_tmr = MAC_AX_IO_RCY_ANA_TMR_6MS,
+
+ .init_cfg_reg = R_AX_PCIE_INIT_CFG1,
+ .txhci_en_bit = B_AX_TXHCI_EN,
+ .rxhci_en_bit = B_AX_RXHCI_EN,
+ .rxbd_mode_bit = B_AX_RXBD_MODE,
+ .exp_ctrl_reg = R_AX_PCIE_EXP_CTRL,
+ .max_tag_num_mask = B_AX_MAX_TAG_NUM,
+ .rxbd_rwptr_clr_reg = R_AX_RXBD_RWPTR_CLR,
+ .txbd_rwptr_clr2_reg = 0,
+ .dma_stop1 = {R_AX_PCIE_DMA_STOP1, B_AX_TX_STOP1_MASK_V1},
+ .dma_stop2 = {0},
+ .dma_busy1 = {R_AX_PCIE_DMA_BUSY1, DMA_BUSY1_CHECK_V1},
+ .dma_busy2_reg = 0,
+ .dma_busy3_reg = R_AX_PCIE_DMA_BUSY1,
+
+ .rpwm_addr = R_AX_PCIE_HRPWM,
+ .cpwm_addr = R_AX_CPWM,
+ .tx_dma_ch_mask = BIT(RTW89_TXCH_ACH4) | BIT(RTW89_TXCH_ACH5) |
+ BIT(RTW89_TXCH_ACH6) | BIT(RTW89_TXCH_ACH7) |
+ BIT(RTW89_TXCH_CH10) | BIT(RTW89_TXCH_CH11),
+ .bd_idx_addr_low_power = NULL,
+ .dma_addr_set = &rtw89_pci_ch_dma_addr_set,
+ .bd_ram_table = &rtw89_bd_ram_table_single,
+
+ .ltr_set = rtw89_pci_ltr_set,
+ .fill_txaddr_info = rtw89_pci_fill_txaddr_info,
+ .config_intr_mask = rtw89_pci_config_intr_mask,
+ .enable_intr = rtw89_pci_enable_intr,
+ .disable_intr = rtw89_pci_disable_intr,
+ .recognize_intrs = rtw89_pci_recognize_intrs,
+};
+
+static const struct rtw89_driver_info rtw89_8851be_info = {
+ .chip = &rtw8851b_chip_info,
+ .bus = {
+ .pci = &rtw8851b_pci_info,
+ },
+};
+
+static const struct pci_device_id rtw89_8851be_id_table[] = {
+ {
+ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0xb851),
+ .driver_data = (kernel_ulong_t)&rtw89_8851be_info,
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(pci, rtw89_8851be_id_table);
+
+static struct pci_driver rtw89_8851be_driver = {
+ .name = "rtw89_8851be",
+ .id_table = rtw89_8851be_id_table,
+ .probe = rtw89_pci_probe,
+ .remove = rtw89_pci_remove,
+ .driver.pm = &rtw89_pm_ops,
+};
+module_pci_driver(rtw89_8851be_driver);
+
+MODULE_AUTHOR("Realtek Corporation");
+MODULE_DESCRIPTION("Realtek 802.11ax wireless 8851BE driver");
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852a.c b/drivers/net/wireless/realtek/rtw89/rtw8852a.c
index d7930efd89b7..6257414a3b4b 100644
--- a/drivers/net/wireless/realtek/rtw89/rtw8852a.c
+++ b/drivers/net/wireless/realtek/rtw89/rtw8852a.c
@@ -463,6 +463,12 @@ static const struct rtw89_imr_info rtw8852a_imr_info = {
.tmac_imr_set = B_AX_TMAC_IMR_SET,
};
+static const struct rtw89_xtal_info rtw8852a_xtal_info = {
+ .xcap_reg = R_AX_XTAL_ON_CTRL0,
+ .sc_xo_mask = B_AX_XTAL_SC_XO_MASK,
+ .sc_xi_mask = B_AX_XTAL_SC_XI_MASK,
+};
+
static const struct rtw89_rrsr_cfgs rtw8852a_rrsr_cfgs = {
.ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0},
.rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2},
@@ -1332,7 +1338,6 @@ static void rtw8852a_rfk_scan(struct rtw89_dev *rtwdev, bool start)
static void rtw8852a_rfk_track(struct rtw89_dev *rtwdev)
{
rtw8852a_dpk_track(rtwdev);
- rtw8852a_iqk_track(rtwdev);
rtw8852a_tssi_track(rtwdev);
}
@@ -2026,6 +2031,7 @@ static const struct rtw89_chip_ops rtw8852a_chip_ops = {
.read_efuse = rtw8852a_read_efuse,
.read_phycap = rtw8852a_read_phycap,
.fem_setup = rtw8852a_fem_setup,
+ .rfe_gpio = NULL,
.rfk_init = rtw8852a_rfk_init,
.rfk_channel = rtw8852a_rfk_channel,
.rfk_band_changed = rtw8852a_rfk_band_changed,
@@ -2043,6 +2049,7 @@ static const struct rtw89_chip_ops rtw8852a_chip_ops = {
.set_txpwr_ul_tb_offset = rtw8852a_set_txpwr_ul_tb_offset,
.pwr_on_func = NULL,
.pwr_off_func = NULL,
+ .query_rxdesc = rtw89_core_query_rxdesc,
.fill_txdesc = rtw89_core_fill_txdesc,
.fill_txdesc_fwcmd = rtw89_core_fill_txdesc,
.cfg_ctrl_path = rtw89_mac_cfg_ctrl_path,
@@ -2069,6 +2076,7 @@ const struct rtw89_chip_info rtw8852a_chip_info = {
.fw_format_max = RTW8852A_FW_FORMAT_MAX,
.try_ce_fw = false,
.fifo_size = 458752,
+ .small_fifo_size = false,
.dle_scc_rsvd_size = 0,
.max_amsdu_limit = 3500,
.dis_2g_40m_ul_ofdma = true,
@@ -2085,6 +2093,7 @@ const struct rtw89_chip_info rtw8852a_chip_info = {
.rf_table = {&rtw89_8852a_phy_radioa_table,
&rtw89_8852a_phy_radiob_table,},
.nctl_table = &rtw89_8852a_phy_nctl_table,
+ .nctl_post_table = NULL,
.byr_table = &rtw89_8852a_byr_table,
.dflt_parms = &rtw89_8852a_dflt_parms,
.rfe_parms_conf = NULL,
@@ -2097,6 +2106,7 @@ const struct rtw89_chip_info rtw8852a_chip_info = {
.support_bands = BIT(NL80211_BAND_2GHZ) |
BIT(NL80211_BAND_5GHZ),
.support_bw160 = false,
+ .support_unii4 = false,
.support_ul_tb_ctrl = false,
.hw_sec_hdr = false,
.rf_path_num = 2,
@@ -2107,7 +2117,7 @@ const struct rtw89_chip_info rtw8852a_chip_info = {
.scam_num = 128,
.bacam_num = 2,
.bacam_dynamic_num = 4,
- .bacam_v1 = false,
+ .bacam_ver = RTW89_BACAM_V0,
.sec_ctrl_efuse_size = 4,
.physical_efuse_size = 1216,
.logical_efuse_size = 1536,
@@ -2159,6 +2169,7 @@ const struct rtw89_chip_info rtw8852a_chip_info = {
#ifdef CONFIG_PM
.wowlan_stub = &rtw_wowlan_stub_8852a,
#endif
+ .xtal_info = &rtw8852a_xtal_info,
};
EXPORT_SYMBOL(rtw8852a_chip_info);
diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk.c b/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk.c
index cd6c39b7f802..d86429e4a35f 100644
--- a/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk.c
+++ b/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk.c
@@ -1284,11 +1284,8 @@ static void _iqk_info_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
u32 tmp = 0x0;
bool flag = 0x0;
- iqk_info->thermal[path] =
- ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]);
- iqk_info->thermal_rek_en = false;
- rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_thermal = %d\n", path,
- iqk_info->thermal[path]);
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_thermal = %lu\n", path,
+ ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]));
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_LOK_COR_fail= %d\n", path,
iqk_info->lok_cor_fail[0][path]);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_LOK_FIN_fail= %d\n", path,
@@ -1536,28 +1533,6 @@ static void _iqk_dbcc(struct rtw89_dev *rtwdev, u8 path)
_iqk_afebb_restore(rtwdev, phy_idx, path);
}
-static void _iqk_track(struct rtw89_dev *rtwdev)
-{
- struct rtw89_iqk_info *iqk = &rtwdev->iqk;
- u8 path = 0x0;
- u8 cur_ther;
-
- if (iqk->iqk_band[0] == RTW89_BAND_2G)
- return;
- if (iqk->iqk_bw[0] < RTW89_CHANNEL_WIDTH_80)
- return;
-
- /* only check path 0 */
- for (path = 0; path < 1; path++) {
- cur_ther = ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]);
-
- if (abs(cur_ther - iqk->thermal[path]) > RTW8852A_IQK_THR_REK)
- iqk->thermal_rek_en = true;
- else
- iqk->thermal_rek_en = false;
- }
-}
-
static void _rck(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
{
u32 rf_reg5, rck_val = 0;
@@ -1616,7 +1591,6 @@ static void _iqk_init(struct rtw89_dev *rtwdev)
iqk_info->iqk_sram_en = false;
iqk_info->iqk_cfir_en = false;
iqk_info->iqk_xym_en = false;
- iqk_info->thermal_rek_en = false;
iqk_info->iqk_times = 0x0;
for (ch = 0; ch < RTW89_IQK_CHS_NR; ch++) {
@@ -1645,7 +1619,6 @@ static void _doiqk(struct rtw89_dev *rtwdev, bool force,
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[IQK]==========IQK start!!!!!==========\n");
iqk_info->iqk_times++;
- iqk_info->kcount = 0;
iqk_info->version = RTW8852A_IQK_VER;
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]Test Ver 0x%x\n", iqk_info->version);
@@ -3655,11 +3628,6 @@ void rtw8852a_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_STOP);
}
-void rtw8852a_iqk_track(struct rtw89_dev *rtwdev)
-{
- _iqk_track(rtwdev);
-}
-
void rtw8852a_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
bool is_afe)
{
diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk.h b/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk.h
index ea36553a76b7..fa058ccc8616 100644
--- a/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk.h
+++ b/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk.h
@@ -10,7 +10,6 @@
void rtw8852a_rck(struct rtw89_dev *rtwdev);
void rtw8852a_dack(struct rtw89_dev *rtwdev);
void rtw8852a_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
-void rtw8852a_iqk_track(struct rtw89_dev *rtwdev);
void rtw8852a_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
bool is_afe);
void rtw8852a_dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy);
diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852b.c b/drivers/net/wireless/realtek/rtw89/rtw8852b.c
index 6da1b603a9a9..718f993da62a 100644
--- a/drivers/net/wireless/realtek/rtw89/rtw8852b.c
+++ b/drivers/net/wireless/realtek/rtw89/rtw8852b.c
@@ -2454,6 +2454,7 @@ static const struct rtw89_chip_ops rtw8852b_chip_ops = {
.read_efuse = rtw8852b_read_efuse,
.read_phycap = rtw8852b_read_phycap,
.fem_setup = NULL,
+ .rfe_gpio = NULL,
.rfk_init = rtw8852b_rfk_init,
.rfk_channel = rtw8852b_rfk_channel,
.rfk_band_changed = rtw8852b_rfk_band_changed,
@@ -2471,6 +2472,7 @@ static const struct rtw89_chip_ops rtw8852b_chip_ops = {
.set_txpwr_ul_tb_offset = rtw8852b_set_txpwr_ul_tb_offset,
.pwr_on_func = rtw8852b_pwr_on_func,
.pwr_off_func = rtw8852b_pwr_off_func,
+ .query_rxdesc = rtw89_core_query_rxdesc,
.fill_txdesc = rtw89_core_fill_txdesc,
.fill_txdesc_fwcmd = rtw89_core_fill_txdesc,
.cfg_ctrl_path = rtw89_mac_cfg_ctrl_path,
@@ -2506,6 +2508,7 @@ const struct rtw89_chip_info rtw8852b_chip_info = {
.fw_format_max = RTW8852B_FW_FORMAT_MAX,
.try_ce_fw = true,
.fifo_size = 196608,
+ .small_fifo_size = true,
.dle_scc_rsvd_size = 98304,
.max_amsdu_limit = 3500,
.dis_2g_40m_ul_ofdma = true,
@@ -2522,6 +2525,7 @@ const struct rtw89_chip_info rtw8852b_chip_info = {
.rf_table = {&rtw89_8852b_phy_radioa_table,
&rtw89_8852b_phy_radiob_table,},
.nctl_table = &rtw89_8852b_phy_nctl_table,
+ .nctl_post_table = NULL,
.byr_table = &rtw89_8852b_byr_table,
.dflt_parms = &rtw89_8852b_dflt_parms,
.rfe_parms_conf = NULL,
@@ -2534,6 +2538,7 @@ const struct rtw89_chip_info rtw8852b_chip_info = {
.support_bands = BIT(NL80211_BAND_2GHZ) |
BIT(NL80211_BAND_5GHZ),
.support_bw160 = false,
+ .support_unii4 = true,
.support_ul_tb_ctrl = true,
.hw_sec_hdr = false,
.rf_path_num = 2,
@@ -2544,7 +2549,7 @@ const struct rtw89_chip_info rtw8852b_chip_info = {
.scam_num = 128,
.bacam_num = 2,
.bacam_dynamic_num = 4,
- .bacam_v1 = false,
+ .bacam_ver = RTW89_BACAM_V0,
.sec_ctrl_efuse_size = 4,
.physical_efuse_size = 1216,
.logical_efuse_size = 2048,
@@ -2598,6 +2603,7 @@ const struct rtw89_chip_info rtw8852b_chip_info = {
#ifdef CONFIG_PM
.wowlan_stub = &rtw_wowlan_stub_8852b,
#endif
+ .xtal_info = NULL,
};
EXPORT_SYMBOL(rtw8852b_chip_info);
diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.c b/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.c
index 722ae34b09c1..fa018e1f499b 100644
--- a/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.c
+++ b/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.c
@@ -1317,10 +1317,6 @@ static void _iqk_info_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
u32 tmp;
bool flag;
- iqk_info->thermal[path] =
- ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]);
- iqk_info->thermal_rek_en = false;
-
flag = iqk_info->lok_cor_fail[0][path];
rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_FCOR << (path * 4), flag);
flag = iqk_info->lok_fin_fail[0][path];
@@ -1568,7 +1564,6 @@ static void _iqk_init(struct rtw89_dev *rtwdev)
iqk_info->iqk_sram_en = false;
iqk_info->iqk_cfir_en = false;
iqk_info->iqk_xym_en = false;
- iqk_info->thermal_rek_en = false;
iqk_info->iqk_times = 0x0;
for (idx = 0; idx < RTW89_IQK_CHS_NR; idx++) {
@@ -1622,9 +1617,8 @@ static void _doiqk(struct rtw89_dev *rtwdev, bool force,
rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_START);
rtw89_debug(rtwdev, RTW89_DBG_RFK,
- "[IQK]==========IQK strat!!!!!==========\n");
+ "[IQK]==========IQK start!!!!!==========\n");
iqk_info->iqk_times++;
- iqk_info->kcount = 0;
iqk_info->version = RTW8852B_IQK_VER;
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]Test Ver 0x%x\n", iqk_info->version);
diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852b_table.c b/drivers/net/wireless/realtek/rtw89/rtw8852b_table.c
index 904cdb9e56fa..17124d851a22 100644
--- a/drivers/net/wireless/realtek/rtw89/rtw8852b_table.c
+++ b/drivers/net/wireless/realtek/rtw89/rtw8852b_table.c
@@ -14666,7 +14666,7 @@ static const s8 _txpwr_track_delta_swingidx_2g_cck_a_p[] = {
0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};
-const u8 rtw89_8852b_tx_shape[RTW89_BAND_MAX][RTW89_RS_TX_SHAPE_NUM]
+const u8 rtw89_8852b_tx_shape[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM]
[RTW89_REGD_NUM] = {
[0][0][RTW89_ACMA] = 0,
[0][0][RTW89_CHILE] = 0,
diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852b_table.h b/drivers/net/wireless/realtek/rtw89/rtw8852b_table.h
index 5f4161496a58..7ef217629f46 100644
--- a/drivers/net/wireless/realtek/rtw89/rtw8852b_table.h
+++ b/drivers/net/wireless/realtek/rtw89/rtw8852b_table.h
@@ -14,7 +14,7 @@ extern const struct rtw89_phy_table rtw89_8852b_phy_radiob_table;
extern const struct rtw89_phy_table rtw89_8852b_phy_nctl_table;
extern const struct rtw89_txpwr_table rtw89_8852b_byr_table;
extern const struct rtw89_txpwr_track_cfg rtw89_8852b_trk_cfg;
-extern const u8 rtw89_8852b_tx_shape[RTW89_BAND_MAX][RTW89_RS_TX_SHAPE_NUM]
+extern const u8 rtw89_8852b_tx_shape[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM]
[RTW89_REGD_NUM];
extern const struct rtw89_rfe_parms rtw89_8852b_dflt_parms;
diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852c.c b/drivers/net/wireless/realtek/rtw89/rtw8852c.c
index ceb819a62efc..9c7c9812d4f4 100644
--- a/drivers/net/wireless/realtek/rtw89/rtw8852c.c
+++ b/drivers/net/wireless/realtek/rtw89/rtw8852c.c
@@ -2762,6 +2762,7 @@ static const struct rtw89_chip_ops rtw8852c_chip_ops = {
.read_efuse = rtw8852c_read_efuse,
.read_phycap = rtw8852c_read_phycap,
.fem_setup = NULL,
+ .rfe_gpio = NULL,
.rfk_init = rtw8852c_rfk_init,
.rfk_channel = rtw8852c_rfk_channel,
.rfk_band_changed = rtw8852c_rfk_band_changed,
@@ -2779,6 +2780,7 @@ static const struct rtw89_chip_ops rtw8852c_chip_ops = {
.set_txpwr_ul_tb_offset = rtw8852c_set_txpwr_ul_tb_offset,
.pwr_on_func = rtw8852c_pwr_on_func,
.pwr_off_func = rtw8852c_pwr_off_func,
+ .query_rxdesc = rtw89_core_query_rxdesc,
.fill_txdesc = rtw89_core_fill_txdesc_v1,
.fill_txdesc_fwcmd = rtw89_core_fill_txdesc_fwcmd_v1,
.cfg_ctrl_path = rtw89_mac_cfg_ctrl_path_v1,
@@ -2805,6 +2807,7 @@ const struct rtw89_chip_info rtw8852c_chip_info = {
.fw_format_max = RTW8852C_FW_FORMAT_MAX,
.try_ce_fw = false,
.fifo_size = 458752,
+ .small_fifo_size = false,
.dle_scc_rsvd_size = 0,
.max_amsdu_limit = 8000,
.dis_2g_40m_ul_ofdma = false,
@@ -2821,6 +2824,7 @@ const struct rtw89_chip_info rtw8852c_chip_info = {
.rf_table = {&rtw89_8852c_phy_radiob_table,
&rtw89_8852c_phy_radioa_table,},
.nctl_table = &rtw89_8852c_phy_nctl_table,
+ .nctl_post_table = NULL,
.byr_table = &rtw89_8852c_byr_table,
.dflt_parms = &rtw89_8852c_dflt_parms,
.rfe_parms_conf = NULL,
@@ -2834,6 +2838,7 @@ const struct rtw89_chip_info rtw8852c_chip_info = {
BIT(NL80211_BAND_5GHZ) |
BIT(NL80211_BAND_6GHZ),
.support_bw160 = true,
+ .support_unii4 = true,
.support_ul_tb_ctrl = false,
.hw_sec_hdr = true,
.rf_path_num = 2,
@@ -2844,7 +2849,7 @@ const struct rtw89_chip_info rtw8852c_chip_info = {
.scam_num = 128,
.bacam_num = 8,
.bacam_dynamic_num = 8,
- .bacam_v1 = true,
+ .bacam_ver = RTW89_BACAM_V0_EXT,
.sec_ctrl_efuse_size = 4,
.physical_efuse_size = 1216,
.logical_efuse_size = 2048,
@@ -2897,6 +2902,7 @@ const struct rtw89_chip_info rtw8852c_chip_info = {
#ifdef CONFIG_PM
.wowlan_stub = &rtw_wowlan_stub_8852c,
#endif
+ .xtal_info = NULL,
};
EXPORT_SYMBOL(rtw8852c_chip_info);
diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852c_rfk.c b/drivers/net/wireless/realtek/rtw89/rtw8852c_rfk.c
index 2c0bc3a4ab3b..de7714f871d5 100644
--- a/drivers/net/wireless/realtek/rtw89/rtw8852c_rfk.c
+++ b/drivers/net/wireless/realtek/rtw89/rtw8852c_rfk.c
@@ -1261,11 +1261,8 @@ static void _iqk_info_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
u32 tmp;
bool flag;
- iqk_info->thermal[path] =
- ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]);
- iqk_info->thermal_rek_en = false;
- rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_thermal = %d\n", path,
- iqk_info->thermal[path]);
+ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_thermal = %lu\n", path,
+ ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]));
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_LOK_COR_fail= %d\n", path,
iqk_info->lok_cor_fail[0][path]);
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_LOK_FIN_fail= %d\n", path,
@@ -1502,7 +1499,6 @@ static void _iqk_init(struct rtw89_dev *rtwdev)
iqk_info->iqk_sram_en = false;
iqk_info->iqk_cfir_en = false;
iqk_info->iqk_xym_en = false;
- iqk_info->thermal_rek_en = false;
iqk_info->iqk_times = 0x0;
for (ch = 0; ch < RTW89_IQK_CHS_NR; ch++) {
@@ -1529,9 +1525,8 @@ static void _doiqk(struct rtw89_dev *rtwdev, bool force,
rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_START);
rtw89_debug(rtwdev, RTW89_DBG_RFK,
- "[IQK]==========IQK strat!!!!!==========\n");
+ "[IQK]==========IQK start!!!!!==========\n");
iqk_info->iqk_times++;
- iqk_info->kcount = 0;
iqk_info->version = RTW8852C_IQK_VER;
rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]Test Ver 0x%x\n", iqk_info->version);
diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852c_table.c b/drivers/net/wireless/realtek/rtw89/rtw8852c_table.c
index 7011e5a6f8fd..4b272fdf1fd7 100644
--- a/drivers/net/wireless/realtek/rtw89/rtw8852c_table.c
+++ b/drivers/net/wireless/realtek/rtw89/rtw8852c_table.c
@@ -2551,19 +2551,27 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0xF0040001, 0x0000000A},
{0xF0050001, 0x0000000B},
{0xF0070001, 0x0000000C},
- {0xF0320001, 0x0000000D},
- {0xF0330001, 0x0000000E},
- {0xF0340001, 0x0000000F},
- {0xF0350001, 0x00000010},
- {0xF0360001, 0x00000011},
- {0xF03F0001, 0x00000012},
- {0xF0400001, 0x00000013},
+ {0xF0150001, 0x0000000D},
+ {0xF0160001, 0x0000000E},
+ {0xF0320001, 0x0000000F},
+ {0xF0330001, 0x00000010},
+ {0xF0340001, 0x00000011},
+ {0xF0350001, 0x00000012},
+ {0xF0360001, 0x00000013},
+ {0xF03F0001, 0x00000014},
+ {0xF0400001, 0x00000015},
{0x005, 0x00000000},
{0x10005, 0x00000000},
{0x000, 0x00030001},
{0x10000, 0x00030000},
{0x018, 0x00011124},
{0x10018, 0x00011124},
+ {0x0A3, 0x000B9204},
+ {0x0AD, 0x00091E0F},
+ {0x05D, 0x00001012},
+ {0x05C, 0x00061C5C},
+ {0x062, 0x00055220},
+ {0x0D3, 0x00000103},
{0x0EF, 0x00080000},
{0x033, 0x00000001},
{0x03E, 0x00000620},
@@ -2636,6 +2644,12 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x067, 0x0000D300},
{0x0DA, 0x000D4000},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x067, 0x0000D300},
+ {0x0DA, 0x000D4000},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x067, 0x0000D300},
+ {0x0DA, 0x000D4000},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x067, 0x0000D300},
{0x0DA, 0x000D4000},
@@ -2716,6 +2730,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000000CC},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000000CC},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000000CC},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000000CC},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000000CC},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -2760,6 +2778,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000000C4},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000000C4},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000000C4},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000000C4},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000000C4},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -2804,6 +2826,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000000BC},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000000BC},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000000BC},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000000BC},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000000BC},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -2848,6 +2874,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000000B4},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000000B4},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000000B4},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000000B4},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000000B4},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -2892,6 +2922,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000000AC},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000000AC},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000000AC},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000000AC},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000000AC},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -2936,6 +2970,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000000A4},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000000A4},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000000A4},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000000A4},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000000A4},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -2980,6 +3018,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x0000009C},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000009C},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000009C},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000009C},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000009C},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -3024,6 +3066,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000094},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000094},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000094},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000094},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000094},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -3068,6 +3114,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x0000008C},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000008C},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000008C},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000008C},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000008C},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -3112,6 +3162,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000084},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000084},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000084},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000084},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000084},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -3156,6 +3210,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000000BC},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000000BC},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000000BC},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000000BC},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000000BC},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -3200,6 +3258,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000000B4},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000000B4},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000000B4},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000000B4},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000000B4},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -3244,6 +3306,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000000AC},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000000AC},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000000AC},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000000AC},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000000AC},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -3288,6 +3354,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000000A4},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000000A4},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000000A4},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000000A4},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000000A4},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -3332,6 +3402,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x0000009C},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000009C},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000009C},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000009C},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000009C},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -3376,6 +3450,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000094},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000094},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000094},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000094},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000094},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -3420,6 +3498,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x0000008C},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000008C},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000008C},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000008C},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000008C},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -3464,6 +3546,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000084},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000084},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000084},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000084},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000084},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -3508,6 +3594,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x0000003C},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000003C},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000003C},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000003C},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000003C},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -3552,6 +3642,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000034},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000034},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000034},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000034},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000034},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -3596,6 +3690,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x0000002C},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000002C},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000002C},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000002C},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000002C},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -3640,6 +3738,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000024},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000024},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000024},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000024},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000024},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -3684,6 +3786,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x0000001C},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000001C},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000001C},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000001C},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000001C},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -3728,6 +3834,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000014},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000014},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000014},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000014},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000014},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -3772,6 +3882,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x0000000C},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000000C},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000000C},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000000C},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000000C},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -3816,6 +3930,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000004},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000004},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000004},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000004},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000004},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -3873,6 +3991,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x08F, 0x000D1352},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x08F, 0x000D1352},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x08F, 0x000D1352},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x08F, 0x000D1352},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x08F, 0x000D1352},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -3936,6 +4058,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000007},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000007},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000017},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000017},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000007},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -4472,6 +4598,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x0000EFFF},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000EFFF},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000EFFF},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000EFFF},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000EFFF},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -4810,6 +4940,32 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x030, 0x00050112},
{0x030, 0x00058101},
{0x030, 0x00060001},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x000085ED},
+ {0x030, 0x000105CC},
+ {0x030, 0x000184AA},
+ {0x030, 0x00020388},
+ {0x030, 0x00028377},
+ {0x030, 0x00030377},
+ {0x030, 0x00038255},
+ {0x030, 0x00040244},
+ {0x030, 0x00048133},
+ {0x030, 0x00050112},
+ {0x030, 0x00058101},
+ {0x030, 0x00060001},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x000085ED},
+ {0x030, 0x000105CC},
+ {0x030, 0x000184AA},
+ {0x030, 0x00020388},
+ {0x030, 0x00028377},
+ {0x030, 0x00030377},
+ {0x030, 0x00038255},
+ {0x030, 0x00040244},
+ {0x030, 0x00048133},
+ {0x030, 0x00050112},
+ {0x030, 0x00058101},
+ {0x030, 0x00060001},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x030, 0x000085ED},
{0x030, 0x000105CC},
@@ -5157,6 +5313,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x030, 0x000300FF},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x030, 0x000300FF},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x000300FF},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x000300FF},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x030, 0x000300FF},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -5178,11 +5338,268 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x0EF, 0x00000000},
{0x06E, 0x00077A18},
{0x06D, 0x00000C31},
+ {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x05E, 0x0000001F},
+ {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
{0x06A, 0x000E0F8A},
{0x06B, 0x000018A0},
{0x06F, 0x000F81FC},
{0x05E, 0x0000001F},
+ {0x90320000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x05E, 0x0000001F},
+ {0x90330000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x05E, 0x0000001F},
+ {0x90340000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x05E, 0x0000001F},
+ {0x90350000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x05E, 0x0000001F},
+ {0x90360000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x05E, 0x0000001F},
+ {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x05E, 0x0000001F},
+ {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x05E, 0x0000001F},
+ {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x05E, 0x0000001F},
+ {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x05E, 0x0000001F},
+ {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x05E, 0x0000001F},
+ {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x05E, 0x0000001F},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0380},
+ {0x06B, 0x00003CA0},
+ {0x06F, 0x000C01FC},
+ {0x05E, 0x0000001F},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0380},
+ {0x06B, 0x00003CA0},
+ {0x06F, 0x000C01FC},
+ {0x05E, 0x0000001F},
+ {0x90320001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x05E, 0x0000001F},
+ {0x90330001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x05E, 0x0000001F},
+ {0x90340001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x05E, 0x0000001F},
+ {0x90350001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x05E, 0x0000001F},
+ {0x90360001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x05E, 0x0000001F},
+ {0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x05E, 0x0000001F},
+ {0x90400001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x05E, 0x0000001F},
+ {0xA0000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x05E, 0x0000001F},
+ {0xB0000000, 0x00000000},
{0x0EF, 0x00000200},
+ {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x90320000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x90330000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x90340000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x90350000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x90360000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003E207},
+ {0x030, 0x0003E207},
+ {0x030, 0x0003E207},
+ {0x030, 0x0003E207},
+ {0x030, 0x0003E207},
+ {0x030, 0x0003E207},
+ {0x030, 0x0003E207},
+ {0x030, 0x0003E207},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003E207},
+ {0x030, 0x0003E207},
+ {0x030, 0x0003E207},
+ {0x030, 0x0003E207},
+ {0x030, 0x0003E207},
+ {0x030, 0x0003E207},
+ {0x030, 0x0003E207},
+ {0x030, 0x0003E207},
+ {0x90320001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x90330001, 0x00000000}, {0x40000000, 0x00000000},
{0x030, 0x0003D407},
{0x030, 0x00035A87},
{0x030, 0x0002CF07},
@@ -5191,14 +5608,225 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x030, 0x00014F07},
{0x030, 0x0000CF07},
{0x030, 0x00004F07},
+ {0x90340001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x90350001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x90360001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x90400001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0xA0000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0xB0000000, 0x00000000},
{0x0EF, 0x00000000},
{0x0EB, 0x00080000},
+ {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
{0x030, 0x00008038},
{0x030, 0x00010038},
{0x030, 0x00018038},
{0x030, 0x00020038},
{0x030, 0x00028038},
{0x030, 0x00030038},
+ {0x90320000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x90330000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x90340000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x90350000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x90360000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0000803C},
+ {0x030, 0x0001003C},
+ {0x030, 0x0001803C},
+ {0x030, 0x0002003C},
+ {0x030, 0x0002803C},
+ {0x030, 0x0003003C},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0000803C},
+ {0x030, 0x0001003C},
+ {0x030, 0x0001803C},
+ {0x030, 0x0002003C},
+ {0x030, 0x0002803C},
+ {0x030, 0x0003003C},
+ {0x90320001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x90330001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x90340001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x90350001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x90360001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x90400001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0xA0000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0xB0000000, 0x00000000},
{0x030, 0x0003803C},
{0x030, 0x0004003C},
{0x030, 0x0004803C},
@@ -5235,6 +5863,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x095, 0x00000008},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x095, 0x00000008},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x095, 0x00000008},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x095, 0x00000008},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x095, 0x00000008},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -5280,6 +5912,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000152},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000152},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000152},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000152},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000152},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -5324,6 +5960,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x0000015A},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000015A},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000015A},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000015A},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000015A},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -5368,6 +6008,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x0000019C},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000019C},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000019C},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000019C},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000019C},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -5412,6 +6056,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000001A4},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001A4},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001A4},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001A4},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001A4},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -5456,6 +6104,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000001E6},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001E6},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001E6},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001E6},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001E6},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -5500,6 +6152,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000002E6},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E6},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E6},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E6},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E6},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -5548,6 +6204,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000152},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000152},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000152},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000152},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000152},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -5592,6 +6252,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x0000015A},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000015A},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000015A},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000015A},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000015A},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -5636,6 +6300,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x0000019C},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000019C},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000019C},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000019C},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000019C},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -5680,6 +6348,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000001A4},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001A4},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001A4},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001A4},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001A4},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -5724,6 +6396,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000001E6},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001E6},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001E6},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001E6},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001E6},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -5768,6 +6444,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000002E6},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E6},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E6},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E6},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E6},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -5812,6 +6492,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000002E7},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E7},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E7},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E7},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E7},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -5856,6 +6540,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000003E7},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000003E7},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000003E7},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000003E7},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000003E7},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -5900,6 +6588,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000152},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000152},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000152},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000152},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000152},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -5944,6 +6636,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x0000015A},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000015A},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000015A},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000015A},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000015A},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -5988,6 +6684,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x0000019C},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000019C},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000019C},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000019C},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000019C},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -6032,6 +6732,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000001A4},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001A4},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001A4},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001A4},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001A4},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -6076,6 +6780,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000001E6},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001E6},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001E6},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001E6},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001E6},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -6120,6 +6828,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000002E6},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E6},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E6},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E6},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E6},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -6164,6 +6876,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000002E7},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E7},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E7},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E7},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E7},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -6208,6 +6924,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000003E7},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000003E7},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000003E7},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000003E7},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000003E7},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -6252,20 +6972,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000152},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000152},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000152},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000152},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000152},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0xA0000000, 0x00000000},
{0x03F, 0x00000052},
{0xB0000000, 0x00000000},
@@ -6296,20 +7020,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x0000015A},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000015A},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000015A},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000015A},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000015A},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0xA0000000, 0x00000000},
{0x03F, 0x0000005A},
{0xB0000000, 0x00000000},
@@ -6340,20 +7068,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x0000019C},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000019C},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000019C},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000019C},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000019C},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0xA0000000, 0x00000000},
{0x03F, 0x0000009C},
{0xB0000000, 0x00000000},
@@ -6384,20 +7116,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000001A4},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001A4},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001A4},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001A4},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001A4},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0xA0000000, 0x00000000},
{0x03F, 0x0000019C},
{0xB0000000, 0x00000000},
@@ -6428,20 +7164,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000001E6},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001E6},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001E6},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001E6},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001E6},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0xA0000000, 0x00000000},
{0x03F, 0x000001A4},
{0xB0000000, 0x00000000},
@@ -6472,20 +7212,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000002E6},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E6},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E6},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E6},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E6},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0xA0000000, 0x00000000},
{0x03F, 0x000001E6},
{0xB0000000, 0x00000000},
@@ -6516,20 +7260,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000002E7},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E7},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E7},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E7},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E7},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0xA0000000, 0x00000000},
{0x03F, 0x000002E6},
{0xB0000000, 0x00000000},
@@ -6560,20 +7308,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000003E7},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000003E7},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000003E7},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000003E7},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000003E7},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0xA0000000, 0x00000000},
{0x03F, 0x000003E6},
{0xB0000000, 0x00000000},
@@ -6604,20 +7356,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000152},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000152},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000152},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000152},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000152},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0xA0000000, 0x00000000},
{0x03F, 0x00000052},
{0xB0000000, 0x00000000},
@@ -6648,20 +7404,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x0000015A},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000015A},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000015A},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000015A},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000015A},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0xA0000000, 0x00000000},
{0x03F, 0x0000005A},
{0xB0000000, 0x00000000},
@@ -6692,20 +7452,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x0000019C},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000019C},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000019C},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000019C},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000019C},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0xA0000000, 0x00000000},
{0x03F, 0x0000009C},
{0xB0000000, 0x00000000},
@@ -6736,20 +7500,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000001A4},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001A4},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001A4},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001A4},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001A4},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0xA0000000, 0x00000000},
{0x03F, 0x0000019C},
{0xB0000000, 0x00000000},
@@ -6780,20 +7548,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000001E6},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001E6},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001E6},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001E6},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001E6},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0xA0000000, 0x00000000},
{0x03F, 0x000001A4},
{0xB0000000, 0x00000000},
@@ -6824,20 +7596,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000002E6},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E6},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E6},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E6},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E6},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0xA0000000, 0x00000000},
{0x03F, 0x000001E6},
{0xB0000000, 0x00000000},
@@ -6868,20 +7644,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000002E7},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E7},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E7},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E7},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E7},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0xA0000000, 0x00000000},
{0x03F, 0x000002E6},
{0xB0000000, 0x00000000},
@@ -6912,20 +7692,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000003E7},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000003E7},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000003E7},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000003E7},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000003E7},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0xA0000000, 0x00000000},
{0x03F, 0x000003E6},
{0xB0000000, 0x00000000},
@@ -6956,20 +7740,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000152},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000152},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000152},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000152},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000152},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0xA0000000, 0x00000000},
{0x03F, 0x00000052},
{0xB0000000, 0x00000000},
@@ -7000,20 +7788,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x0000015A},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000015A},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000015A},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000015A},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000015A},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0xA0000000, 0x00000000},
{0x03F, 0x0000005A},
{0xB0000000, 0x00000000},
@@ -7044,20 +7836,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x0000019C},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000019C},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000019C},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000019C},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000019C},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0xA0000000, 0x00000000},
{0x03F, 0x0000009C},
{0xB0000000, 0x00000000},
@@ -7088,20 +7884,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000001A4},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001A4},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001A4},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001A4},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001A4},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0xA0000000, 0x00000000},
{0x03F, 0x0000019C},
{0xB0000000, 0x00000000},
@@ -7132,20 +7932,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000001E6},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001E6},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001E6},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001E6},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001E6},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0xA0000000, 0x00000000},
{0x03F, 0x000001A4},
{0xB0000000, 0x00000000},
@@ -7176,20 +7980,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000002E6},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E6},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E6},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E6},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E6},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0xA0000000, 0x00000000},
{0x03F, 0x000001E6},
{0xB0000000, 0x00000000},
@@ -7220,20 +8028,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000002E7},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E7},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E7},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E7},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E7},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0xA0000000, 0x00000000},
{0x03F, 0x000002E6},
{0xB0000000, 0x00000000},
@@ -7264,20 +8076,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000003E7},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000003E7},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000003E7},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000003E7},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000003E7},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0xA0000000, 0x00000000},
{0x03F, 0x000003E6},
{0xB0000000, 0x00000000},
@@ -7308,20 +8124,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000152},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000152},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000152},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000152},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000152},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0xA0000000, 0x00000000},
{0x03F, 0x00000052},
{0xB0000000, 0x00000000},
@@ -7352,20 +8172,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x0000015A},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000015A},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000015A},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000015A},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000015A},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0xA0000000, 0x00000000},
{0x03F, 0x0000005A},
{0xB0000000, 0x00000000},
@@ -7396,20 +8220,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x0000019C},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000019C},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000019C},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000019C},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000019C},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0xA0000000, 0x00000000},
{0x03F, 0x0000009C},
{0xB0000000, 0x00000000},
@@ -7440,20 +8268,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000001A4},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001A4},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001A4},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001A4},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001A4},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0xA0000000, 0x00000000},
{0x03F, 0x0000019C},
{0xB0000000, 0x00000000},
@@ -7484,20 +8316,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000001E6},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001E6},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001E6},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001E6},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001E6},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0xA0000000, 0x00000000},
{0x03F, 0x000001A4},
{0xB0000000, 0x00000000},
@@ -7528,20 +8364,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x000002E6},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E6},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E6},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E6},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E6},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0xA0000000, 0x00000000},
{0x03F, 0x000001E6},
{0xB0000000, 0x00000000},
@@ -9436,7 +10276,7 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x10030, 0x0007BC1D},
{0x10030, 0x0007C017},
{0x10030, 0x0007C40F},
- {0x90320001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x000001EF},
{0x10030, 0x000005E9},
{0x10030, 0x000009E3},
@@ -9581,7 +10421,7 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x10030, 0x0007BC1D},
{0x10030, 0x0007C017},
{0x10030, 0x0007C40F},
- {0x90330001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x000001EF},
{0x10030, 0x000005E9},
{0x10030, 0x000009E3},
@@ -9600,60 +10440,60 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x10030, 0x00003C5F},
{0x10030, 0x00004059},
{0x10030, 0x00004453},
- {0x10030, 0x000201A7},
- {0x10030, 0x000205A1},
- {0x10030, 0x0002099B},
- {0x10030, 0x00020D95},
- {0x10030, 0x0002115B},
- {0x10030, 0x00021555},
- {0x10030, 0x00021921},
- {0x10030, 0x00021D1B},
- {0x10030, 0x000220E3},
- {0x10030, 0x000224DD},
+ {0x10030, 0x000201EF},
+ {0x10030, 0x000205E9},
+ {0x10030, 0x000209E3},
+ {0x10030, 0x00020DA3},
+ {0x10030, 0x00021161},
+ {0x10030, 0x0002155B},
+ {0x10030, 0x0002191F},
+ {0x10030, 0x00021D19},
+ {0x10030, 0x000220E1},
+ {0x10030, 0x000224DB},
{0x10030, 0x000228A3},
{0x10030, 0x00022C9D},
{0x10030, 0x00023063},
{0x10030, 0x0002345D},
{0x10030, 0x00023823},
- {0x10030, 0x00023C1D},
- {0x10030, 0x00024017},
- {0x10030, 0x00024411},
- {0x10030, 0x000281A9},
- {0x10030, 0x000285A3},
- {0x10030, 0x0002899D},
- {0x10030, 0x00028D97},
- {0x10030, 0x0002915D},
- {0x10030, 0x00029557},
- {0x10030, 0x0002991F},
- {0x10030, 0x00029D19},
- {0x10030, 0x0002A0E1},
- {0x10030, 0x0002A4DB},
+ {0x10030, 0x00023C1B},
+ {0x10030, 0x00024015},
+ {0x10030, 0x0002440F},
+ {0x10030, 0x000281EF},
+ {0x10030, 0x000285E7},
+ {0x10030, 0x000289A7},
+ {0x10030, 0x00028D65},
+ {0x10030, 0x0002915F},
+ {0x10030, 0x00029523},
+ {0x10030, 0x0002991D},
+ {0x10030, 0x00029CE5},
+ {0x10030, 0x0002A0DF},
+ {0x10030, 0x0002A4A7},
{0x10030, 0x0002A8A1},
- {0x10030, 0x0002AC9B},
+ {0x10030, 0x0002AC67},
{0x10030, 0x0002B061},
- {0x10030, 0x0002B45B},
+ {0x10030, 0x0002B427},
{0x10030, 0x0002B821},
- {0x10030, 0x0002BC1B},
- {0x10030, 0x0002C015},
- {0x10030, 0x0002C40F},
- {0x10030, 0x000301A9},
- {0x10030, 0x000305A3},
- {0x10030, 0x0003099D},
- {0x10030, 0x00030D97},
- {0x10030, 0x0003115D},
- {0x10030, 0x00031557},
+ {0x10030, 0x0002BC19},
+ {0x10030, 0x0002C013},
+ {0x10030, 0x0002C40D},
+ {0x10030, 0x000301EF},
+ {0x10030, 0x000305E7},
+ {0x10030, 0x000309A7},
+ {0x10030, 0x00030D65},
+ {0x10030, 0x0003115F},
+ {0x10030, 0x00031525},
{0x10030, 0x0003191F},
- {0x10030, 0x00031D19},
+ {0x10030, 0x00031CE7},
{0x10030, 0x000320E1},
- {0x10030, 0x000324DB},
- {0x10030, 0x000328A1},
- {0x10030, 0x00032C9B},
- {0x10030, 0x00033061},
- {0x10030, 0x0003345B},
- {0x10030, 0x00033821},
- {0x10030, 0x00033C1B},
- {0x10030, 0x00034015},
- {0x10030, 0x0003440F},
+ {0x10030, 0x000324A9},
+ {0x10030, 0x000328A3},
+ {0x10030, 0x00032C69},
+ {0x10030, 0x00033063},
+ {0x10030, 0x00033429},
+ {0x10030, 0x00033823},
+ {0x10030, 0x00033C1D},
+ {0x10030, 0x00034013},
+ {0x10030, 0x0003440D},
{0x10030, 0x000601F1},
{0x10030, 0x000605E9},
{0x10030, 0x000609A9},
@@ -9697,7 +10537,7 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x10030, 0x0007115B},
{0x10030, 0x00071523},
{0x10030, 0x0007191D},
- {0x10030, 0x00071CE5},
+ {0x10030, 0x00071D17},
{0x10030, 0x000720DF},
{0x10030, 0x000724D9},
{0x10030, 0x000728A1},
@@ -9726,7 +10566,7 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x10030, 0x0007BC1D},
{0x10030, 0x0007C017},
{0x10030, 0x0007C40F},
- {0x90340001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x000001EF},
{0x10030, 0x000005E9},
{0x10030, 0x000009E3},
@@ -9745,60 +10585,60 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x10030, 0x00003C5F},
{0x10030, 0x00004059},
{0x10030, 0x00004453},
- {0x10030, 0x000201A7},
- {0x10030, 0x000205A1},
- {0x10030, 0x0002099B},
- {0x10030, 0x00020D95},
- {0x10030, 0x0002115B},
- {0x10030, 0x00021555},
- {0x10030, 0x00021921},
- {0x10030, 0x00021D1B},
- {0x10030, 0x000220E3},
- {0x10030, 0x000224DD},
+ {0x10030, 0x000201EF},
+ {0x10030, 0x000205E9},
+ {0x10030, 0x000209E3},
+ {0x10030, 0x00020DA3},
+ {0x10030, 0x00021161},
+ {0x10030, 0x0002155B},
+ {0x10030, 0x0002191F},
+ {0x10030, 0x00021D19},
+ {0x10030, 0x000220E1},
+ {0x10030, 0x000224DB},
{0x10030, 0x000228A3},
{0x10030, 0x00022C9D},
{0x10030, 0x00023063},
{0x10030, 0x0002345D},
{0x10030, 0x00023823},
- {0x10030, 0x00023C1D},
- {0x10030, 0x00024017},
- {0x10030, 0x00024411},
- {0x10030, 0x000281A9},
- {0x10030, 0x000285A3},
- {0x10030, 0x0002899D},
- {0x10030, 0x00028D97},
- {0x10030, 0x0002915D},
- {0x10030, 0x00029557},
- {0x10030, 0x0002991F},
- {0x10030, 0x00029D19},
- {0x10030, 0x0002A0E1},
- {0x10030, 0x0002A4DB},
+ {0x10030, 0x00023C1B},
+ {0x10030, 0x00024015},
+ {0x10030, 0x0002440F},
+ {0x10030, 0x000281EF},
+ {0x10030, 0x000285E7},
+ {0x10030, 0x000289A7},
+ {0x10030, 0x00028D65},
+ {0x10030, 0x0002915F},
+ {0x10030, 0x00029523},
+ {0x10030, 0x0002991D},
+ {0x10030, 0x00029CE5},
+ {0x10030, 0x0002A0DF},
+ {0x10030, 0x0002A4A7},
{0x10030, 0x0002A8A1},
- {0x10030, 0x0002AC9B},
+ {0x10030, 0x0002AC67},
{0x10030, 0x0002B061},
- {0x10030, 0x0002B45B},
+ {0x10030, 0x0002B427},
{0x10030, 0x0002B821},
- {0x10030, 0x0002BC1B},
- {0x10030, 0x0002C015},
- {0x10030, 0x0002C40F},
- {0x10030, 0x000301A9},
- {0x10030, 0x000305A3},
- {0x10030, 0x0003099D},
- {0x10030, 0x00030D97},
- {0x10030, 0x0003115D},
- {0x10030, 0x00031557},
+ {0x10030, 0x0002BC19},
+ {0x10030, 0x0002C013},
+ {0x10030, 0x0002C40D},
+ {0x10030, 0x000301EF},
+ {0x10030, 0x000305E7},
+ {0x10030, 0x000309A7},
+ {0x10030, 0x00030D65},
+ {0x10030, 0x0003115F},
+ {0x10030, 0x00031525},
{0x10030, 0x0003191F},
- {0x10030, 0x00031D19},
+ {0x10030, 0x00031CE7},
{0x10030, 0x000320E1},
- {0x10030, 0x000324DB},
- {0x10030, 0x000328A1},
- {0x10030, 0x00032C9B},
- {0x10030, 0x00033061},
- {0x10030, 0x0003345B},
- {0x10030, 0x00033821},
- {0x10030, 0x00033C1B},
- {0x10030, 0x00034015},
- {0x10030, 0x0003440F},
+ {0x10030, 0x000324A9},
+ {0x10030, 0x000328A3},
+ {0x10030, 0x00032C69},
+ {0x10030, 0x00033063},
+ {0x10030, 0x00033429},
+ {0x10030, 0x00033823},
+ {0x10030, 0x00033C1D},
+ {0x10030, 0x00034013},
+ {0x10030, 0x0003440D},
{0x10030, 0x000601F1},
{0x10030, 0x000605E9},
{0x10030, 0x000609A9},
@@ -9842,7 +10682,7 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x10030, 0x0007115B},
{0x10030, 0x00071523},
{0x10030, 0x0007191D},
- {0x10030, 0x00071CE5},
+ {0x10030, 0x00071D17},
{0x10030, 0x000720DF},
{0x10030, 0x000724D9},
{0x10030, 0x000728A1},
@@ -9871,6 +10711,296 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x10030, 0x0007BC1D},
{0x10030, 0x0007C017},
{0x10030, 0x0007C40F},
+ {0x90330001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x000001EF},
+ {0x10030, 0x000005E9},
+ {0x10030, 0x000009E3},
+ {0x10030, 0x00000DDD},
+ {0x10030, 0x000011D7},
+ {0x10030, 0x0000159F},
+ {0x10030, 0x00001999},
+ {0x10030, 0x00001D5F},
+ {0x10030, 0x00002159},
+ {0x10030, 0x0000251F},
+ {0x10030, 0x00002919},
+ {0x10030, 0x00002CDF},
+ {0x10030, 0x000030D9},
+ {0x10030, 0x0000349F},
+ {0x10030, 0x00003899},
+ {0x10030, 0x00003C5F},
+ {0x10030, 0x00004059},
+ {0x10030, 0x00004453},
+ {0x10030, 0x000201A7},
+ {0x10030, 0x000205A1},
+ {0x10030, 0x0002099B},
+ {0x10030, 0x00020D95},
+ {0x10030, 0x0002115B},
+ {0x10030, 0x00021555},
+ {0x10030, 0x00021921},
+ {0x10030, 0x00021D1B},
+ {0x10030, 0x000220E3},
+ {0x10030, 0x000224DD},
+ {0x10030, 0x000228A3},
+ {0x10030, 0x00022C9D},
+ {0x10030, 0x00023063},
+ {0x10030, 0x0002345D},
+ {0x10030, 0x00023823},
+ {0x10030, 0x00023C1D},
+ {0x10030, 0x00024017},
+ {0x10030, 0x00024411},
+ {0x10030, 0x000281A9},
+ {0x10030, 0x000285A3},
+ {0x10030, 0x0002899D},
+ {0x10030, 0x00028D97},
+ {0x10030, 0x0002915D},
+ {0x10030, 0x00029557},
+ {0x10030, 0x0002991F},
+ {0x10030, 0x00029D19},
+ {0x10030, 0x0002A0E1},
+ {0x10030, 0x0002A4DB},
+ {0x10030, 0x0002A8A1},
+ {0x10030, 0x0002AC9B},
+ {0x10030, 0x0002B061},
+ {0x10030, 0x0002B45B},
+ {0x10030, 0x0002B821},
+ {0x10030, 0x0002BC1B},
+ {0x10030, 0x0002C015},
+ {0x10030, 0x0002C40F},
+ {0x10030, 0x000301A9},
+ {0x10030, 0x000305A3},
+ {0x10030, 0x0003099D},
+ {0x10030, 0x00030D97},
+ {0x10030, 0x0003115D},
+ {0x10030, 0x00031557},
+ {0x10030, 0x0003191F},
+ {0x10030, 0x00031D19},
+ {0x10030, 0x000320E1},
+ {0x10030, 0x000324DB},
+ {0x10030, 0x000328A1},
+ {0x10030, 0x00032C9B},
+ {0x10030, 0x00033061},
+ {0x10030, 0x0003345B},
+ {0x10030, 0x00033821},
+ {0x10030, 0x00033C1B},
+ {0x10030, 0x00034015},
+ {0x10030, 0x0003440F},
+ {0x10030, 0x000601F1},
+ {0x10030, 0x000605E9},
+ {0x10030, 0x000609A9},
+ {0x10030, 0x00060D65},
+ {0x10030, 0x0006115F},
+ {0x10030, 0x00061527},
+ {0x10030, 0x00061921},
+ {0x10030, 0x00061CE9},
+ {0x10030, 0x000620E3},
+ {0x10030, 0x000624DD},
+ {0x10030, 0x000628A5},
+ {0x10030, 0x00062C6B},
+ {0x10030, 0x00063065},
+ {0x10030, 0x0006342B},
+ {0x10030, 0x00063825},
+ {0x10030, 0x00063C1F},
+ {0x10030, 0x00064019},
+ {0x10030, 0x00064413},
+ {0x10030, 0x000681EF},
+ {0x10030, 0x000685E7},
+ {0x10030, 0x000689A7},
+ {0x10030, 0x00068D61},
+ {0x10030, 0x0006915B},
+ {0x10030, 0x00069525},
+ {0x10030, 0x0006991F},
+ {0x10030, 0x00069CE7},
+ {0x10030, 0x0006A0E1},
+ {0x10030, 0x0006A4A9},
+ {0x10030, 0x0006A8A3},
+ {0x10030, 0x0006AC69},
+ {0x10030, 0x0006B063},
+ {0x10030, 0x0006B429},
+ {0x10030, 0x0006B823},
+ {0x10030, 0x0006BC1D},
+ {0x10030, 0x0006C017},
+ {0x10030, 0x0006C411},
+ {0x10030, 0x000701EF},
+ {0x10030, 0x000705E9},
+ {0x10030, 0x000709A9},
+ {0x10030, 0x00070D63},
+ {0x10030, 0x0007115D},
+ {0x10030, 0x00071525},
+ {0x10030, 0x0007191F},
+ {0x10030, 0x00071D19},
+ {0x10030, 0x000720E1},
+ {0x10030, 0x000724DB},
+ {0x10030, 0x000728A3},
+ {0x10030, 0x00072C69},
+ {0x10030, 0x00073063},
+ {0x10030, 0x00073429},
+ {0x10030, 0x00073823},
+ {0x10030, 0x00073C1D},
+ {0x10030, 0x00074017},
+ {0x10030, 0x00074411},
+ {0x10030, 0x000781EF},
+ {0x10030, 0x000785E9},
+ {0x10030, 0x000789E3},
+ {0x10030, 0x00078DA1},
+ {0x10030, 0x0007915F},
+ {0x10030, 0x00079559},
+ {0x10030, 0x0007991F},
+ {0x10030, 0x00079D19},
+ {0x10030, 0x0007A0DF},
+ {0x10030, 0x0007A4D9},
+ {0x10030, 0x0007A8D3},
+ {0x10030, 0x0007AC99},
+ {0x10030, 0x0007B05F},
+ {0x10030, 0x0007B459},
+ {0x10030, 0x0007B81F},
+ {0x10030, 0x0007BC19},
+ {0x10030, 0x0007C013},
+ {0x10030, 0x0007C40D},
+ {0x90340001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x000001EF},
+ {0x10030, 0x000005E9},
+ {0x10030, 0x000009E3},
+ {0x10030, 0x00000DDD},
+ {0x10030, 0x000011D7},
+ {0x10030, 0x0000159F},
+ {0x10030, 0x00001999},
+ {0x10030, 0x00001D5F},
+ {0x10030, 0x00002159},
+ {0x10030, 0x0000251F},
+ {0x10030, 0x00002919},
+ {0x10030, 0x00002CDF},
+ {0x10030, 0x000030D9},
+ {0x10030, 0x0000349F},
+ {0x10030, 0x00003899},
+ {0x10030, 0x00003C5F},
+ {0x10030, 0x00004059},
+ {0x10030, 0x00004453},
+ {0x10030, 0x000201A7},
+ {0x10030, 0x000205A1},
+ {0x10030, 0x0002099B},
+ {0x10030, 0x00020D95},
+ {0x10030, 0x0002115B},
+ {0x10030, 0x00021555},
+ {0x10030, 0x00021921},
+ {0x10030, 0x00021D1B},
+ {0x10030, 0x000220E3},
+ {0x10030, 0x000224DD},
+ {0x10030, 0x000228A3},
+ {0x10030, 0x00022C9D},
+ {0x10030, 0x00023063},
+ {0x10030, 0x0002345D},
+ {0x10030, 0x00023823},
+ {0x10030, 0x00023C1D},
+ {0x10030, 0x00024017},
+ {0x10030, 0x00024411},
+ {0x10030, 0x000281A9},
+ {0x10030, 0x000285A3},
+ {0x10030, 0x0002899D},
+ {0x10030, 0x00028D97},
+ {0x10030, 0x0002915D},
+ {0x10030, 0x00029557},
+ {0x10030, 0x0002991F},
+ {0x10030, 0x00029D19},
+ {0x10030, 0x0002A0E1},
+ {0x10030, 0x0002A4DB},
+ {0x10030, 0x0002A8A1},
+ {0x10030, 0x0002AC9B},
+ {0x10030, 0x0002B061},
+ {0x10030, 0x0002B45B},
+ {0x10030, 0x0002B821},
+ {0x10030, 0x0002BC1B},
+ {0x10030, 0x0002C015},
+ {0x10030, 0x0002C40F},
+ {0x10030, 0x000301A9},
+ {0x10030, 0x000305A3},
+ {0x10030, 0x0003099D},
+ {0x10030, 0x00030D97},
+ {0x10030, 0x0003115D},
+ {0x10030, 0x00031557},
+ {0x10030, 0x0003191F},
+ {0x10030, 0x00031D19},
+ {0x10030, 0x000320E1},
+ {0x10030, 0x000324DB},
+ {0x10030, 0x000328A1},
+ {0x10030, 0x00032C9B},
+ {0x10030, 0x00033061},
+ {0x10030, 0x0003345B},
+ {0x10030, 0x00033821},
+ {0x10030, 0x00033C1B},
+ {0x10030, 0x00034015},
+ {0x10030, 0x0003440F},
+ {0x10030, 0x000601F1},
+ {0x10030, 0x000605E9},
+ {0x10030, 0x000609A9},
+ {0x10030, 0x00060D65},
+ {0x10030, 0x0006115F},
+ {0x10030, 0x00061527},
+ {0x10030, 0x00061921},
+ {0x10030, 0x00061CE9},
+ {0x10030, 0x000620E3},
+ {0x10030, 0x000624DD},
+ {0x10030, 0x000628A5},
+ {0x10030, 0x00062C6B},
+ {0x10030, 0x00063065},
+ {0x10030, 0x0006342B},
+ {0x10030, 0x00063825},
+ {0x10030, 0x00063C1F},
+ {0x10030, 0x00064019},
+ {0x10030, 0x00064413},
+ {0x10030, 0x000681EF},
+ {0x10030, 0x000685E7},
+ {0x10030, 0x000689A7},
+ {0x10030, 0x00068D61},
+ {0x10030, 0x0006915B},
+ {0x10030, 0x00069525},
+ {0x10030, 0x0006991F},
+ {0x10030, 0x00069CE7},
+ {0x10030, 0x0006A0E1},
+ {0x10030, 0x0006A4A9},
+ {0x10030, 0x0006A8A3},
+ {0x10030, 0x0006AC69},
+ {0x10030, 0x0006B063},
+ {0x10030, 0x0006B429},
+ {0x10030, 0x0006B823},
+ {0x10030, 0x0006BC1D},
+ {0x10030, 0x0006C017},
+ {0x10030, 0x0006C411},
+ {0x10030, 0x000701EF},
+ {0x10030, 0x000705E9},
+ {0x10030, 0x000709A9},
+ {0x10030, 0x00070D63},
+ {0x10030, 0x0007115D},
+ {0x10030, 0x00071525},
+ {0x10030, 0x0007191F},
+ {0x10030, 0x00071D19},
+ {0x10030, 0x000720E1},
+ {0x10030, 0x000724DB},
+ {0x10030, 0x000728A3},
+ {0x10030, 0x00072C69},
+ {0x10030, 0x00073063},
+ {0x10030, 0x00073429},
+ {0x10030, 0x00073823},
+ {0x10030, 0x00073C1D},
+ {0x10030, 0x00074017},
+ {0x10030, 0x00074411},
+ {0x10030, 0x000781EF},
+ {0x10030, 0x000785E9},
+ {0x10030, 0x000789E3},
+ {0x10030, 0x00078DA1},
+ {0x10030, 0x0007915F},
+ {0x10030, 0x00079559},
+ {0x10030, 0x0007991F},
+ {0x10030, 0x00079D19},
+ {0x10030, 0x0007A0DF},
+ {0x10030, 0x0007A4D9},
+ {0x10030, 0x0007A8D3},
+ {0x10030, 0x0007AC99},
+ {0x10030, 0x0007B05F},
+ {0x10030, 0x0007B459},
+ {0x10030, 0x0007B81F},
+ {0x10030, 0x0007BC19},
+ {0x10030, 0x0007C013},
+ {0x10030, 0x0007C40D},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x000001EF},
{0x10030, 0x000005E9},
@@ -9949,73 +11079,73 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x10030, 0x000609A9},
{0x10030, 0x00060D65},
{0x10030, 0x0006115F},
- {0x10030, 0x00061525},
- {0x10030, 0x0006191F},
- {0x10030, 0x00061CE7},
- {0x10030, 0x000620E1},
- {0x10030, 0x000624DB},
- {0x10030, 0x000628A3},
- {0x10030, 0x00062C69},
- {0x10030, 0x00063063},
- {0x10030, 0x00063429},
- {0x10030, 0x00063823},
- {0x10030, 0x00063C1D},
- {0x10030, 0x00064013},
- {0x10030, 0x0006440D},
+ {0x10030, 0x00061527},
+ {0x10030, 0x00061921},
+ {0x10030, 0x00061CE9},
+ {0x10030, 0x000620E3},
+ {0x10030, 0x000624DD},
+ {0x10030, 0x000628A5},
+ {0x10030, 0x00062C6B},
+ {0x10030, 0x00063065},
+ {0x10030, 0x0006342B},
+ {0x10030, 0x00063825},
+ {0x10030, 0x00063C1F},
+ {0x10030, 0x00064019},
+ {0x10030, 0x00064413},
{0x10030, 0x000681EF},
{0x10030, 0x000685E7},
{0x10030, 0x000689A7},
{0x10030, 0x00068D61},
{0x10030, 0x0006915B},
- {0x10030, 0x00069523},
- {0x10030, 0x0006991D},
- {0x10030, 0x00069CE5},
- {0x10030, 0x0006A0DF},
- {0x10030, 0x0006A4A7},
- {0x10030, 0x0006A8A1},
- {0x10030, 0x0006AC67},
- {0x10030, 0x0006B061},
+ {0x10030, 0x00069525},
+ {0x10030, 0x0006991F},
+ {0x10030, 0x00069CE7},
+ {0x10030, 0x0006A0E1},
+ {0x10030, 0x0006A4A9},
+ {0x10030, 0x0006A8A3},
+ {0x10030, 0x0006AC69},
+ {0x10030, 0x0006B063},
{0x10030, 0x0006B429},
{0x10030, 0x0006B823},
{0x10030, 0x0006BC1D},
{0x10030, 0x0006C017},
- {0x10030, 0x0006C40D},
+ {0x10030, 0x0006C411},
{0x10030, 0x000701EF},
- {0x10030, 0x000705E7},
- {0x10030, 0x000709A7},
- {0x10030, 0x00070D61},
- {0x10030, 0x0007115B},
- {0x10030, 0x00071523},
- {0x10030, 0x0007191D},
- {0x10030, 0x00071CE5},
- {0x10030, 0x000720DF},
- {0x10030, 0x000724D9},
- {0x10030, 0x000728A1},
- {0x10030, 0x00072C67},
- {0x10030, 0x00073061},
- {0x10030, 0x00073427},
- {0x10030, 0x00073821},
- {0x10030, 0x00073C1B},
- {0x10030, 0x00074015},
- {0x10030, 0x0007440D},
+ {0x10030, 0x000705E9},
+ {0x10030, 0x000709A9},
+ {0x10030, 0x00070D63},
+ {0x10030, 0x0007115D},
+ {0x10030, 0x00071525},
+ {0x10030, 0x0007191F},
+ {0x10030, 0x00071D19},
+ {0x10030, 0x000720E1},
+ {0x10030, 0x000724DB},
+ {0x10030, 0x000728A3},
+ {0x10030, 0x00072C69},
+ {0x10030, 0x00073063},
+ {0x10030, 0x00073429},
+ {0x10030, 0x00073823},
+ {0x10030, 0x00073C1D},
+ {0x10030, 0x00074017},
+ {0x10030, 0x00074411},
{0x10030, 0x000781EF},
{0x10030, 0x000785E9},
{0x10030, 0x000789E3},
{0x10030, 0x00078DA1},
{0x10030, 0x0007915F},
{0x10030, 0x00079559},
- {0x10030, 0x00079921},
- {0x10030, 0x00079D1B},
- {0x10030, 0x0007A0E3},
- {0x10030, 0x0007A4DD},
- {0x10030, 0x0007A8D7},
- {0x10030, 0x0007AC9D},
- {0x10030, 0x0007B063},
- {0x10030, 0x0007B45D},
- {0x10030, 0x0007B823},
- {0x10030, 0x0007BC1D},
- {0x10030, 0x0007C017},
- {0x10030, 0x0007C40F},
+ {0x10030, 0x0007991F},
+ {0x10030, 0x00079D19},
+ {0x10030, 0x0007A0DF},
+ {0x10030, 0x0007A4D9},
+ {0x10030, 0x0007A8D3},
+ {0x10030, 0x0007AC99},
+ {0x10030, 0x0007B05F},
+ {0x10030, 0x0007B459},
+ {0x10030, 0x0007B81F},
+ {0x10030, 0x0007BC19},
+ {0x10030, 0x0007C013},
+ {0x10030, 0x0007C40D},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x000001EF},
{0x10030, 0x000005E9},
@@ -10094,73 +11224,73 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x10030, 0x000609A9},
{0x10030, 0x00060D65},
{0x10030, 0x0006115F},
- {0x10030, 0x00061525},
- {0x10030, 0x0006191F},
- {0x10030, 0x00061CE7},
- {0x10030, 0x000620E1},
- {0x10030, 0x000624DB},
- {0x10030, 0x000628A3},
- {0x10030, 0x00062C69},
- {0x10030, 0x00063063},
- {0x10030, 0x00063429},
- {0x10030, 0x00063823},
- {0x10030, 0x00063C1D},
- {0x10030, 0x00064013},
- {0x10030, 0x0006440D},
+ {0x10030, 0x00061527},
+ {0x10030, 0x00061921},
+ {0x10030, 0x00061CE9},
+ {0x10030, 0x000620E3},
+ {0x10030, 0x000624DD},
+ {0x10030, 0x000628A5},
+ {0x10030, 0x00062C6B},
+ {0x10030, 0x00063065},
+ {0x10030, 0x0006342B},
+ {0x10030, 0x00063825},
+ {0x10030, 0x00063C1F},
+ {0x10030, 0x00064019},
+ {0x10030, 0x00064413},
{0x10030, 0x000681EF},
{0x10030, 0x000685E7},
{0x10030, 0x000689A7},
{0x10030, 0x00068D61},
{0x10030, 0x0006915B},
- {0x10030, 0x00069523},
- {0x10030, 0x0006991D},
- {0x10030, 0x00069CE5},
- {0x10030, 0x0006A0DF},
- {0x10030, 0x0006A4A7},
- {0x10030, 0x0006A8A1},
- {0x10030, 0x0006AC67},
- {0x10030, 0x0006B061},
+ {0x10030, 0x00069525},
+ {0x10030, 0x0006991F},
+ {0x10030, 0x00069CE7},
+ {0x10030, 0x0006A0E1},
+ {0x10030, 0x0006A4A9},
+ {0x10030, 0x0006A8A3},
+ {0x10030, 0x0006AC69},
+ {0x10030, 0x0006B063},
{0x10030, 0x0006B429},
{0x10030, 0x0006B823},
{0x10030, 0x0006BC1D},
{0x10030, 0x0006C017},
- {0x10030, 0x0006C40D},
+ {0x10030, 0x0006C411},
{0x10030, 0x000701EF},
- {0x10030, 0x000705E7},
- {0x10030, 0x000709A7},
- {0x10030, 0x00070D61},
- {0x10030, 0x0007115B},
- {0x10030, 0x00071523},
- {0x10030, 0x0007191D},
- {0x10030, 0x00071CE5},
- {0x10030, 0x000720DF},
- {0x10030, 0x000724D9},
- {0x10030, 0x000728A1},
- {0x10030, 0x00072C67},
- {0x10030, 0x00073061},
- {0x10030, 0x00073427},
- {0x10030, 0x00073821},
- {0x10030, 0x00073C1B},
- {0x10030, 0x00074015},
- {0x10030, 0x0007440D},
+ {0x10030, 0x000705E9},
+ {0x10030, 0x000709A9},
+ {0x10030, 0x00070D63},
+ {0x10030, 0x0007115D},
+ {0x10030, 0x00071525},
+ {0x10030, 0x0007191F},
+ {0x10030, 0x00071D19},
+ {0x10030, 0x000720E1},
+ {0x10030, 0x000724DB},
+ {0x10030, 0x000728A3},
+ {0x10030, 0x00072C69},
+ {0x10030, 0x00073063},
+ {0x10030, 0x00073429},
+ {0x10030, 0x00073823},
+ {0x10030, 0x00073C1D},
+ {0x10030, 0x00074017},
+ {0x10030, 0x00074411},
{0x10030, 0x000781EF},
{0x10030, 0x000785E9},
{0x10030, 0x000789E3},
{0x10030, 0x00078DA1},
{0x10030, 0x0007915F},
{0x10030, 0x00079559},
- {0x10030, 0x00079921},
- {0x10030, 0x00079D1B},
- {0x10030, 0x0007A0E3},
- {0x10030, 0x0007A4DD},
- {0x10030, 0x0007A8D7},
- {0x10030, 0x0007AC9D},
- {0x10030, 0x0007B063},
- {0x10030, 0x0007B45D},
- {0x10030, 0x0007B823},
- {0x10030, 0x0007BC1D},
- {0x10030, 0x0007C017},
- {0x10030, 0x0007C40F},
+ {0x10030, 0x0007991F},
+ {0x10030, 0x00079D19},
+ {0x10030, 0x0007A0DF},
+ {0x10030, 0x0007A4D9},
+ {0x10030, 0x0007A8D3},
+ {0x10030, 0x0007AC99},
+ {0x10030, 0x0007B05F},
+ {0x10030, 0x0007B459},
+ {0x10030, 0x0007B81F},
+ {0x10030, 0x0007BC19},
+ {0x10030, 0x0007C013},
+ {0x10030, 0x0007C40D},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x000001EF},
{0x10030, 0x000005E9},
@@ -10239,73 +11369,73 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x10030, 0x000609A9},
{0x10030, 0x00060D65},
{0x10030, 0x0006115F},
- {0x10030, 0x00061525},
- {0x10030, 0x0006191F},
- {0x10030, 0x00061CE7},
- {0x10030, 0x000620E1},
- {0x10030, 0x000624DB},
- {0x10030, 0x000628A3},
- {0x10030, 0x00062C69},
- {0x10030, 0x00063063},
- {0x10030, 0x00063429},
- {0x10030, 0x00063823},
- {0x10030, 0x00063C1D},
- {0x10030, 0x00064013},
- {0x10030, 0x0006440D},
+ {0x10030, 0x00061527},
+ {0x10030, 0x00061921},
+ {0x10030, 0x00061CE9},
+ {0x10030, 0x000620E3},
+ {0x10030, 0x000624DD},
+ {0x10030, 0x000628A5},
+ {0x10030, 0x00062C6B},
+ {0x10030, 0x00063065},
+ {0x10030, 0x0006342B},
+ {0x10030, 0x00063825},
+ {0x10030, 0x00063C1F},
+ {0x10030, 0x00064019},
+ {0x10030, 0x00064413},
{0x10030, 0x000681EF},
{0x10030, 0x000685E7},
{0x10030, 0x000689A7},
{0x10030, 0x00068D61},
{0x10030, 0x0006915B},
- {0x10030, 0x00069523},
- {0x10030, 0x0006991D},
- {0x10030, 0x00069CE5},
- {0x10030, 0x0006A0DF},
- {0x10030, 0x0006A4A7},
- {0x10030, 0x0006A8A1},
- {0x10030, 0x0006AC67},
- {0x10030, 0x0006B061},
+ {0x10030, 0x00069525},
+ {0x10030, 0x0006991F},
+ {0x10030, 0x00069CE7},
+ {0x10030, 0x0006A0E1},
+ {0x10030, 0x0006A4A9},
+ {0x10030, 0x0006A8A3},
+ {0x10030, 0x0006AC69},
+ {0x10030, 0x0006B063},
{0x10030, 0x0006B429},
{0x10030, 0x0006B823},
{0x10030, 0x0006BC1D},
{0x10030, 0x0006C017},
- {0x10030, 0x0006C40D},
+ {0x10030, 0x0006C411},
{0x10030, 0x000701EF},
- {0x10030, 0x000705E7},
- {0x10030, 0x000709A7},
- {0x10030, 0x00070D61},
- {0x10030, 0x0007115B},
- {0x10030, 0x00071523},
- {0x10030, 0x0007191D},
- {0x10030, 0x00071CE5},
- {0x10030, 0x000720DF},
- {0x10030, 0x000724D9},
- {0x10030, 0x000728A1},
- {0x10030, 0x00072C67},
- {0x10030, 0x00073061},
- {0x10030, 0x00073427},
- {0x10030, 0x00073821},
- {0x10030, 0x00073C1B},
- {0x10030, 0x00074015},
- {0x10030, 0x0007440D},
+ {0x10030, 0x000705E9},
+ {0x10030, 0x000709A9},
+ {0x10030, 0x00070D63},
+ {0x10030, 0x0007115D},
+ {0x10030, 0x00071525},
+ {0x10030, 0x0007191F},
+ {0x10030, 0x00071D19},
+ {0x10030, 0x000720E1},
+ {0x10030, 0x000724DB},
+ {0x10030, 0x000728A3},
+ {0x10030, 0x00072C69},
+ {0x10030, 0x00073063},
+ {0x10030, 0x00073429},
+ {0x10030, 0x00073823},
+ {0x10030, 0x00073C1D},
+ {0x10030, 0x00074017},
+ {0x10030, 0x00074411},
{0x10030, 0x000781EF},
{0x10030, 0x000785E9},
{0x10030, 0x000789E3},
{0x10030, 0x00078DA1},
{0x10030, 0x0007915F},
{0x10030, 0x00079559},
- {0x10030, 0x00079921},
- {0x10030, 0x00079D1B},
- {0x10030, 0x0007A0E3},
- {0x10030, 0x0007A4DD},
- {0x10030, 0x0007A8D7},
- {0x10030, 0x0007AC9D},
- {0x10030, 0x0007B063},
- {0x10030, 0x0007B45D},
- {0x10030, 0x0007B823},
- {0x10030, 0x0007BC1D},
- {0x10030, 0x0007C017},
- {0x10030, 0x0007C40F},
+ {0x10030, 0x0007991F},
+ {0x10030, 0x00079D19},
+ {0x10030, 0x0007A0DF},
+ {0x10030, 0x0007A4D9},
+ {0x10030, 0x0007A8D3},
+ {0x10030, 0x0007AC99},
+ {0x10030, 0x0007B05F},
+ {0x10030, 0x0007B459},
+ {0x10030, 0x0007B81F},
+ {0x10030, 0x0007BC19},
+ {0x10030, 0x0007C013},
+ {0x10030, 0x0007C40D},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x000001EF},
{0x10030, 0x000005E9},
@@ -10384,73 +11514,73 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x10030, 0x000609A9},
{0x10030, 0x00060D65},
{0x10030, 0x0006115F},
- {0x10030, 0x00061525},
- {0x10030, 0x0006191F},
- {0x10030, 0x00061CE7},
- {0x10030, 0x000620E1},
- {0x10030, 0x000624DB},
- {0x10030, 0x000628A3},
- {0x10030, 0x00062C69},
- {0x10030, 0x00063063},
- {0x10030, 0x00063429},
- {0x10030, 0x00063823},
- {0x10030, 0x00063C1D},
- {0x10030, 0x00064013},
- {0x10030, 0x0006440D},
+ {0x10030, 0x00061527},
+ {0x10030, 0x00061921},
+ {0x10030, 0x00061CE9},
+ {0x10030, 0x000620E3},
+ {0x10030, 0x000624DD},
+ {0x10030, 0x000628A5},
+ {0x10030, 0x00062C6B},
+ {0x10030, 0x00063065},
+ {0x10030, 0x0006342B},
+ {0x10030, 0x00063825},
+ {0x10030, 0x00063C1F},
+ {0x10030, 0x00064019},
+ {0x10030, 0x00064413},
{0x10030, 0x000681EF},
{0x10030, 0x000685E7},
{0x10030, 0x000689A7},
{0x10030, 0x00068D61},
{0x10030, 0x0006915B},
- {0x10030, 0x00069523},
- {0x10030, 0x0006991D},
- {0x10030, 0x00069CE5},
- {0x10030, 0x0006A0DF},
- {0x10030, 0x0006A4A7},
- {0x10030, 0x0006A8A1},
- {0x10030, 0x0006AC67},
- {0x10030, 0x0006B061},
+ {0x10030, 0x00069525},
+ {0x10030, 0x0006991F},
+ {0x10030, 0x00069CE7},
+ {0x10030, 0x0006A0E1},
+ {0x10030, 0x0006A4A9},
+ {0x10030, 0x0006A8A3},
+ {0x10030, 0x0006AC69},
+ {0x10030, 0x0006B063},
{0x10030, 0x0006B429},
{0x10030, 0x0006B823},
{0x10030, 0x0006BC1D},
{0x10030, 0x0006C017},
- {0x10030, 0x0006C40D},
+ {0x10030, 0x0006C411},
{0x10030, 0x000701EF},
- {0x10030, 0x000705E7},
- {0x10030, 0x000709A7},
- {0x10030, 0x00070D61},
- {0x10030, 0x0007115B},
- {0x10030, 0x00071523},
- {0x10030, 0x0007191D},
- {0x10030, 0x00071CE5},
- {0x10030, 0x000720DF},
- {0x10030, 0x000724D9},
- {0x10030, 0x000728A1},
- {0x10030, 0x00072C67},
- {0x10030, 0x00073061},
- {0x10030, 0x00073427},
- {0x10030, 0x00073821},
- {0x10030, 0x00073C1B},
- {0x10030, 0x00074015},
- {0x10030, 0x0007440D},
+ {0x10030, 0x000705E9},
+ {0x10030, 0x000709A9},
+ {0x10030, 0x00070D63},
+ {0x10030, 0x0007115D},
+ {0x10030, 0x00071525},
+ {0x10030, 0x0007191F},
+ {0x10030, 0x00071D19},
+ {0x10030, 0x000720E1},
+ {0x10030, 0x000724DB},
+ {0x10030, 0x000728A3},
+ {0x10030, 0x00072C69},
+ {0x10030, 0x00073063},
+ {0x10030, 0x00073429},
+ {0x10030, 0x00073823},
+ {0x10030, 0x00073C1D},
+ {0x10030, 0x00074017},
+ {0x10030, 0x00074411},
{0x10030, 0x000781EF},
{0x10030, 0x000785E9},
{0x10030, 0x000789E3},
{0x10030, 0x00078DA1},
{0x10030, 0x0007915F},
{0x10030, 0x00079559},
- {0x10030, 0x00079921},
- {0x10030, 0x00079D1B},
- {0x10030, 0x0007A0E3},
- {0x10030, 0x0007A4DD},
- {0x10030, 0x0007A8D7},
- {0x10030, 0x0007AC9D},
- {0x10030, 0x0007B063},
- {0x10030, 0x0007B45D},
- {0x10030, 0x0007B823},
- {0x10030, 0x0007BC1D},
- {0x10030, 0x0007C017},
- {0x10030, 0x0007C40F},
+ {0x10030, 0x0007991F},
+ {0x10030, 0x00079D19},
+ {0x10030, 0x0007A0DF},
+ {0x10030, 0x0007A4D9},
+ {0x10030, 0x0007A8D3},
+ {0x10030, 0x0007AC99},
+ {0x10030, 0x0007B05F},
+ {0x10030, 0x0007B459},
+ {0x10030, 0x0007B81F},
+ {0x10030, 0x0007BC19},
+ {0x10030, 0x0007C013},
+ {0x10030, 0x0007C40D},
{0xA0000000, 0x00000000},
{0x10030, 0x000001EF},
{0x10030, 0x000005E9},
@@ -11294,6 +12424,110 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x10030, 0x000338CC},
{0x10030, 0x00033C09},
{0x10030, 0x00034006},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x000200E8},
+ {0x10030, 0x000204E5},
+ {0x10030, 0x000208E2},
+ {0x10030, 0x00020CDF},
+ {0x10030, 0x000210DC},
+ {0x10030, 0x000214D9},
+ {0x10030, 0x000218D6},
+ {0x10030, 0x00021CD3},
+ {0x10030, 0x000220D0},
+ {0x10030, 0x0002240D},
+ {0x10030, 0x0002280A},
+ {0x10030, 0x00022C07},
+ {0x10030, 0x00023004},
+ {0x10030, 0x00023401},
+ {0x10030, 0x00023800},
+ {0x10030, 0x00023C00},
+ {0x10030, 0x00024000},
+ {0x10030, 0x000280ED},
+ {0x10030, 0x000284EA},
+ {0x10030, 0x000288E7},
+ {0x10030, 0x00028CE4},
+ {0x10030, 0x000290E1},
+ {0x10030, 0x000294DE},
+ {0x10030, 0x000298DB},
+ {0x10030, 0x00029CD8},
+ {0x10030, 0x0002A0D5},
+ {0x10030, 0x0002A4D2},
+ {0x10030, 0x0002A8CF},
+ {0x10030, 0x0002AC0C},
+ {0x10030, 0x0002B009},
+ {0x10030, 0x0002B406},
+ {0x10030, 0x0002B803},
+ {0x10030, 0x0002BC00},
+ {0x10030, 0x0002C000},
+ {0x10030, 0x000300EE},
+ {0x10030, 0x000304EB},
+ {0x10030, 0x000308E8},
+ {0x10030, 0x00030CE5},
+ {0x10030, 0x000310E2},
+ {0x10030, 0x000314DF},
+ {0x10030, 0x000318DC},
+ {0x10030, 0x00031CD9},
+ {0x10030, 0x000320D6},
+ {0x10030, 0x000324D3},
+ {0x10030, 0x000328D0},
+ {0x10030, 0x00032CCD},
+ {0x10030, 0x0003300A},
+ {0x10030, 0x00033407},
+ {0x10030, 0x00033804},
+ {0x10030, 0x00033C01},
+ {0x10030, 0x00034000},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x000200E8},
+ {0x10030, 0x000204E5},
+ {0x10030, 0x000208E2},
+ {0x10030, 0x00020CDF},
+ {0x10030, 0x000210DC},
+ {0x10030, 0x000214D9},
+ {0x10030, 0x000218D6},
+ {0x10030, 0x00021CD3},
+ {0x10030, 0x000220D0},
+ {0x10030, 0x0002240D},
+ {0x10030, 0x0002280A},
+ {0x10030, 0x00022C07},
+ {0x10030, 0x00023004},
+ {0x10030, 0x00023401},
+ {0x10030, 0x00023800},
+ {0x10030, 0x00023C00},
+ {0x10030, 0x00024000},
+ {0x10030, 0x000280ED},
+ {0x10030, 0x000284EA},
+ {0x10030, 0x000288E7},
+ {0x10030, 0x00028CE4},
+ {0x10030, 0x000290E1},
+ {0x10030, 0x000294DE},
+ {0x10030, 0x000298DB},
+ {0x10030, 0x00029CD8},
+ {0x10030, 0x0002A0D5},
+ {0x10030, 0x0002A4D2},
+ {0x10030, 0x0002A8CF},
+ {0x10030, 0x0002AC0C},
+ {0x10030, 0x0002B009},
+ {0x10030, 0x0002B406},
+ {0x10030, 0x0002B803},
+ {0x10030, 0x0002BC00},
+ {0x10030, 0x0002C000},
+ {0x10030, 0x000300EE},
+ {0x10030, 0x000304EB},
+ {0x10030, 0x000308E8},
+ {0x10030, 0x00030CE5},
+ {0x10030, 0x000310E2},
+ {0x10030, 0x000314DF},
+ {0x10030, 0x000318DC},
+ {0x10030, 0x00031CD9},
+ {0x10030, 0x000320D6},
+ {0x10030, 0x000324D3},
+ {0x10030, 0x000328D0},
+ {0x10030, 0x00032CCD},
+ {0x10030, 0x0003300A},
+ {0x10030, 0x00033407},
+ {0x10030, 0x00033804},
+ {0x10030, 0x00033C01},
+ {0x10030, 0x00034000},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x000200FA},
{0x10030, 0x000204F7},
@@ -11841,6 +13075,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -11885,6 +13123,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -11941,6 +13183,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -11985,6 +13231,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -12041,6 +13291,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -12085,6 +13339,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -12141,6 +13399,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -12185,6 +13447,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -12241,6 +13507,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -12285,6 +13555,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -12305,7 +13579,53 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x033, 0x00000070},
{0x03F, 0x00050002},
{0x033, 0x00000071},
+ {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90320000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90330000, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00060032},
+ {0x90340000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90350000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90360000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90320001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90330001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90340001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90350001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90360001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90400001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0xA0000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0xB0000000, 0x00000000},
{0x033, 0x00000072},
{0x03F, 0x00050042},
{0x033, 0x00000073},
@@ -12341,6 +13661,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -12385,6 +13709,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -12405,7 +13733,53 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x033, 0x00000078},
{0x03F, 0x00050002},
{0x033, 0x00000079},
+ {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90320000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90330000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90340000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90350000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90360000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90320001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90330001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90340001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90350001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90360001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00060032},
+ {0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0x90400001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0xA0000000, 0x00000000},
+ {0x03F, 0x00060032},
+ {0xB0000000, 0x00000000},
{0x033, 0x0000007A},
{0x03F, 0x00050042},
{0x033, 0x0000007B},
@@ -12441,6 +13815,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -12485,6 +13863,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -12541,6 +13923,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -12585,6 +13971,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -12641,6 +14031,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -12685,6 +14079,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -12741,6 +14139,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -12785,6 +14187,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -12841,6 +14247,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -12885,6 +14295,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -12941,6 +14355,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -12985,6 +14403,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -13041,6 +14463,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -13085,6 +14511,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -13141,6 +14571,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -13185,6 +14619,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -13241,6 +14679,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -13285,6 +14727,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -13341,6 +14787,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -13385,6 +14835,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -13441,6 +14895,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -13485,6 +14943,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -13541,6 +15003,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -13585,6 +15051,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -13641,6 +15111,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -13685,6 +15159,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -13741,6 +15219,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -13785,6 +15267,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -13841,6 +15327,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -13885,6 +15375,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -13941,6 +15435,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -13985,6 +15483,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -14041,6 +15543,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -14085,6 +15591,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -14141,6 +15651,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -14185,6 +15699,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -14241,6 +15759,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -14285,6 +15807,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -14341,6 +15867,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -14385,6 +15915,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -14441,6 +15975,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -14485,6 +16023,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -14541,6 +16083,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -14585,6 +16131,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -14669,6 +16219,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x10030, 0x00025003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x00025003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x00025003},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x00025003},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x00025003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -14719,6 +16273,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x10030, 0x0002D003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x0002D003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x0002D003},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x0002D003},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x0002D003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -14769,6 +16327,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x10030, 0x00035003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x00035003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x00035003},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x00035003},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x00035003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -14819,6 +16381,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x10030, 0x0003D003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x0003D003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x0003D003},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x0003D003},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x0003D003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -14882,6 +16448,12 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x00065003},
{0x10030, 0x00066003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x00065003},
+ {0x10030, 0x00066003},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x00065003},
+ {0x10030, 0x00066003},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x00065003},
{0x10030, 0x00066003},
@@ -14952,6 +16524,12 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x0006D003},
{0x10030, 0x0006E003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x0006D003},
+ {0x10030, 0x0006E003},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x0006D003},
+ {0x10030, 0x0006E003},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x0006D003},
{0x10030, 0x0006E003},
@@ -15022,6 +16600,12 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x00075003},
{0x10030, 0x00076003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x00075003},
+ {0x10030, 0x00076003},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x00075003},
+ {0x10030, 0x00076003},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x00075003},
{0x10030, 0x00076003},
@@ -15092,6 +16676,12 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x0007D003},
{0x10030, 0x0007E003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x0007D003},
+ {0x10030, 0x0007E003},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x0007D003},
+ {0x10030, 0x0007E003},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x0007D003},
{0x10030, 0x0007E003},
@@ -15119,7 +16709,7 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
{0xB0000000, 0x00000000},
{0x10030, 0x0007F003},
{0x100EE, 0x00000000},
- {0x0FE, 0x00000048},
+ {0x0FE, 0x00000063},
};
static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
@@ -15136,13 +16726,15 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0xF0040001, 0x0000000A},
{0xF0050001, 0x0000000B},
{0xF0070001, 0x0000000C},
- {0xF0320001, 0x0000000D},
- {0xF0330001, 0x0000000E},
- {0xF0340001, 0x0000000F},
- {0xF0350001, 0x00000010},
- {0xF0360001, 0x00000011},
- {0xF03F0001, 0x00000012},
- {0xF0400001, 0x00000013},
+ {0xF0150001, 0x0000000D},
+ {0xF0160001, 0x0000000E},
+ {0xF0320001, 0x0000000F},
+ {0xF0330001, 0x00000010},
+ {0xF0340001, 0x00000011},
+ {0xF0350001, 0x00000012},
+ {0xF0360001, 0x00000013},
+ {0xF03F0001, 0x00000014},
+ {0xF0400001, 0x00000015},
{0x005, 0x00000000},
{0x10005, 0x00000000},
{0x0B9, 0x00020440},
@@ -15150,6 +16742,12 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x10000, 0x00030000},
{0x018, 0x00011124},
{0x10018, 0x00011124},
+ {0x0A3, 0x000B9204},
+ {0x0AD, 0x00091E0F},
+ {0x05D, 0x00001012},
+ {0x05C, 0x00079C5C},
+ {0x062, 0x00055220},
+ {0x0D3, 0x00000103},
{0x05F, 0x00000038},
{0x097, 0x00043200},
{0x0A6, 0x00066DB7},
@@ -15253,6 +16851,12 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x067, 0x0000D300},
{0x0DA, 0x000D4000},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x067, 0x0000D300},
+ {0x0DA, 0x000D4000},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x067, 0x0000D300},
+ {0x0DA, 0x000D4000},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x067, 0x0000D300},
{0x0DA, 0x000D4000},
@@ -15319,6 +16923,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x08F, 0x000D1352},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x08F, 0x000D1352},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x08F, 0x000D1352},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x08F, 0x000D1352},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x08F, 0x000D1352},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -15382,6 +16990,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000007},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000007},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000017},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000017},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000007},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -15918,6 +17530,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x0000EFFF},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000EFFF},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000EFFF},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000EFFF},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000EFFF},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -16256,6 +17872,32 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x030, 0x00050112},
{0x030, 0x00058101},
{0x030, 0x00060001},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x000085ED},
+ {0x030, 0x000105CC},
+ {0x030, 0x000184AA},
+ {0x030, 0x00020388},
+ {0x030, 0x00028377},
+ {0x030, 0x00030377},
+ {0x030, 0x00038255},
+ {0x030, 0x00040244},
+ {0x030, 0x00048133},
+ {0x030, 0x00050112},
+ {0x030, 0x00058101},
+ {0x030, 0x00060001},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x000085ED},
+ {0x030, 0x000105CC},
+ {0x030, 0x000184AA},
+ {0x030, 0x00020388},
+ {0x030, 0x00028377},
+ {0x030, 0x00030377},
+ {0x030, 0x00038255},
+ {0x030, 0x00040244},
+ {0x030, 0x00048133},
+ {0x030, 0x00050112},
+ {0x030, 0x00058101},
+ {0x030, 0x00060001},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x030, 0x000085ED},
{0x030, 0x000105CC},
@@ -16582,11 +18224,291 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x0EF, 0x00000000},
{0x06E, 0x00077A18},
{0x06D, 0x00000C31},
+ {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x90320000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x90330000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x90340000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x90350000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x90360000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x06A, 0x000E0F8A},
{0x06B, 0x000018A0},
{0x06F, 0x000F81FC},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0380},
+ {0x06B, 0x00003CA0},
+ {0x06F, 0x000C01FC},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0380},
+ {0x06B, 0x00003CA0},
+ {0x06F, 0x000C01FC},
+ {0x90320001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x90330001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x90340001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x90350001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x90360001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0x90400001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0xA0000000, 0x00000000},
+ {0x06A, 0x000E0F8A},
+ {0x06B, 0x000018A0},
+ {0x06F, 0x000F81FC},
+ {0xB0000000, 0x00000000},
{0x05E, 0x0000001F},
{0x0EF, 0x00000200},
+ {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x90320000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x90330000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x90340000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x90350000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x90360000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003E207},
+ {0x030, 0x0003E207},
+ {0x030, 0x0003E207},
+ {0x030, 0x0003E207},
+ {0x030, 0x0003E207},
+ {0x030, 0x0003E207},
+ {0x030, 0x0003E207},
+ {0x030, 0x0003E207},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003E207},
+ {0x030, 0x0003E207},
+ {0x030, 0x0003E207},
+ {0x030, 0x0003E207},
+ {0x030, 0x0003E207},
+ {0x030, 0x0003E207},
+ {0x030, 0x0003E207},
+ {0x030, 0x0003E207},
+ {0x90320001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x90330001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x90340001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x90350001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x90360001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0x90400001, 0x00000000}, {0x40000000, 0x00000000},
{0x030, 0x0003D407},
{0x030, 0x00035A87},
{0x030, 0x0002CF07},
@@ -16595,14 +18517,180 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x030, 0x00014F07},
{0x030, 0x0000CF07},
{0x030, 0x00004F07},
+ {0xA0000000, 0x00000000},
+ {0x030, 0x0003D407},
+ {0x030, 0x00035A87},
+ {0x030, 0x0002CF07},
+ {0x030, 0x00024F07},
+ {0x030, 0x0001CF07},
+ {0x030, 0x00014F07},
+ {0x030, 0x0000CF07},
+ {0x030, 0x00004F07},
+ {0xB0000000, 0x00000000},
{0x0EF, 0x00000000},
{0x0EB, 0x00080000},
+ {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x90320000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x90330000, 0x00000000}, {0x40000000, 0x00000000},
{0x030, 0x00008038},
{0x030, 0x00010038},
{0x030, 0x00018038},
{0x030, 0x00020038},
{0x030, 0x00028038},
{0x030, 0x00030038},
+ {0x90340000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x90350000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x90360000, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0000803C},
+ {0x030, 0x0001003C},
+ {0x030, 0x0001803C},
+ {0x030, 0x0002003C},
+ {0x030, 0x0002803C},
+ {0x030, 0x0003003C},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x0000803C},
+ {0x030, 0x0001003C},
+ {0x030, 0x0001803C},
+ {0x030, 0x0002003C},
+ {0x030, 0x0002803C},
+ {0x030, 0x0003003C},
+ {0x90320001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x90330001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x90340001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x90350001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x90360001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0x90400001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0xA0000000, 0x00000000},
+ {0x030, 0x00008038},
+ {0x030, 0x00010038},
+ {0x030, 0x00018038},
+ {0x030, 0x00020038},
+ {0x030, 0x00028038},
+ {0x030, 0x00030038},
+ {0xB0000000, 0x00000000},
{0x030, 0x0003803C},
{0x030, 0x0004003C},
{0x030, 0x0004803C},
@@ -16639,6 +18727,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x095, 0x00000008},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x095, 0x00000008},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x095, 0x00000008},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x095, 0x00000008},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x095, 0x00000008},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -16684,6 +18776,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000152},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000152},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000152},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000152},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000152},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -16728,6 +18824,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x0000015A},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000015A},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000015A},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000015A},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000015A},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -16772,6 +18872,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x0000019C},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000019C},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000019C},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000019C},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000019C},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -16816,6 +18920,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x000001A4},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001A4},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001A4},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001A4},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001A4},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -16860,6 +18968,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x000001E6},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001E6},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001E6},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001E6},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001E6},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -16904,6 +19016,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x000002E6},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E6},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E6},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E6},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E6},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -16948,6 +19064,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x000002E7},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E7},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E7},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E7},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E7},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -16992,6 +19112,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x000003E7},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000003E7},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000003E7},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000003E7},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000003E7},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -17036,6 +19160,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000152},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000152},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000152},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000152},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000152},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -17080,6 +19208,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x0000015A},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000015A},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000015A},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000015A},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000015A},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -17124,6 +19256,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x0000019C},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000019C},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000019C},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000019C},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000019C},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -17168,6 +19304,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x000001A4},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001A4},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001A4},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001A4},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001A4},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -17212,6 +19352,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x000001E6},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001E6},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001E6},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001E6},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001E6},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -17256,6 +19400,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x000002E6},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E6},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E6},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E6},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E6},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -17300,6 +19448,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x000002E7},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E7},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E7},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E7},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E7},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -17344,6 +19496,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x000003E7},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000003E7},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000003E7},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000003E7},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000003E7},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -17388,6 +19544,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000152},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000152},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000152},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000152},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000152},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -17432,6 +19592,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x0000015A},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000015A},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000015A},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000015A},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000015A},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -17476,6 +19640,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x0000019C},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000019C},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000019C},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000019C},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000019C},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -17520,6 +19688,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x000001A4},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001A4},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001A4},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001A4},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001A4},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -17564,6 +19736,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x000001E6},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001E6},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001E6},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001E6},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001E6},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -17608,6 +19784,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x000002E6},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E6},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E6},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E6},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E6},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -17652,6 +19832,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x000002E7},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E7},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E7},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E7},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E7},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -17696,6 +19880,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x000003E7},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000003E7},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000003E7},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000003E7},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000003E7},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -17740,20 +19928,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000152},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000152},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000152},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000152},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000152},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0xA0000000, 0x00000000},
{0x03F, 0x00000052},
{0xB0000000, 0x00000000},
@@ -17784,20 +19976,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x0000015A},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000015A},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000015A},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000015A},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000015A},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0xA0000000, 0x00000000},
{0x03F, 0x0000005A},
{0xB0000000, 0x00000000},
@@ -17828,20 +20024,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x0000019C},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000019C},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000019C},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000019C},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000019C},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0xA0000000, 0x00000000},
{0x03F, 0x0000009C},
{0xB0000000, 0x00000000},
@@ -17872,20 +20072,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x000001A4},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001A4},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001A4},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001A4},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001A4},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0xA0000000, 0x00000000},
{0x03F, 0x0000019C},
{0xB0000000, 0x00000000},
@@ -17916,20 +20120,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x000001E6},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001E6},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001E6},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001E6},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001E6},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0xA0000000, 0x00000000},
{0x03F, 0x000001A4},
{0xB0000000, 0x00000000},
@@ -17960,20 +20168,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x000002E6},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E6},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E6},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E6},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E6},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0xA0000000, 0x00000000},
{0x03F, 0x000001E6},
{0xB0000000, 0x00000000},
@@ -18004,20 +20216,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x000002E7},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E7},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E7},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E7},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E7},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0xA0000000, 0x00000000},
{0x03F, 0x000002E6},
{0xB0000000, 0x00000000},
@@ -18048,20 +20264,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x000003E7},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000003E7},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000003E7},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000003E7},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000003E7},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0xA0000000, 0x00000000},
{0x03F, 0x000003E6},
{0xB0000000, 0x00000000},
@@ -18092,20 +20312,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000152},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000152},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000152},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000152},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000152},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0xA0000000, 0x00000000},
{0x03F, 0x00000052},
{0xB0000000, 0x00000000},
@@ -18136,20 +20360,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x0000015A},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000015A},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000015A},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000015A},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000015A},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0xA0000000, 0x00000000},
{0x03F, 0x0000005A},
{0xB0000000, 0x00000000},
@@ -18180,20 +20408,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x0000019C},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000019C},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000019C},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000019C},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000019C},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0xA0000000, 0x00000000},
{0x03F, 0x0000009C},
{0xB0000000, 0x00000000},
@@ -18224,20 +20456,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x000001A4},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001A4},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001A4},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001A4},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001A4},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0xA0000000, 0x00000000},
{0x03F, 0x0000019C},
{0xB0000000, 0x00000000},
@@ -18268,20 +20504,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x000001E6},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001E6},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001E6},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001E6},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001E6},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0xA0000000, 0x00000000},
{0x03F, 0x000001A4},
{0xB0000000, 0x00000000},
@@ -18312,20 +20552,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x000002E6},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E6},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E6},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E6},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E6},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0xA0000000, 0x00000000},
{0x03F, 0x000001E6},
{0xB0000000, 0x00000000},
@@ -18356,20 +20600,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x000002E7},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E7},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E7},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E7},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E7},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0xA0000000, 0x00000000},
{0x03F, 0x000002E6},
{0xB0000000, 0x00000000},
@@ -18400,20 +20648,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x000003E7},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000003E7},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000003E7},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000003E7},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000003E7},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0xA0000000, 0x00000000},
{0x03F, 0x000003E6},
{0xB0000000, 0x00000000},
@@ -18444,20 +20696,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000152},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000152},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000152},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000152},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000152},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0xA0000000, 0x00000000},
{0x03F, 0x00000052},
{0xB0000000, 0x00000000},
@@ -18488,20 +20744,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x0000015A},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000015A},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000015A},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000015A},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000015A},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0xA0000000, 0x00000000},
{0x03F, 0x0000005A},
{0xB0000000, 0x00000000},
@@ -18532,20 +20792,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x0000019C},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000019C},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000019C},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000019C},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000019C},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0xA0000000, 0x00000000},
{0x03F, 0x0000009C},
{0xB0000000, 0x00000000},
@@ -18576,20 +20840,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x000001A4},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001A4},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001A4},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001A4},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001A4},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0xA0000000, 0x00000000},
{0x03F, 0x0000019C},
{0xB0000000, 0x00000000},
@@ -18620,20 +20888,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x000001E6},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001E6},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001E6},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001E6},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001E6},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0xA0000000, 0x00000000},
{0x03F, 0x000001A4},
{0xB0000000, 0x00000000},
@@ -18664,20 +20936,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x000002E6},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E6},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E6},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E6},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E6},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0xA0000000, 0x00000000},
{0x03F, 0x000001E6},
{0xB0000000, 0x00000000},
@@ -18708,20 +20984,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x000002E7},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E7},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E7},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E7},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E7},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000002E6},
+ {0x03F, 0x000002E7},
{0xA0000000, 0x00000000},
{0x03F, 0x000002E6},
{0xB0000000, 0x00000000},
@@ -18752,20 +21032,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x000003E7},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000003E7},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000003E7},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000003E7},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000003E7},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000003E6},
+ {0x03F, 0x000003E7},
{0xA0000000, 0x00000000},
{0x03F, 0x000003E6},
{0xB0000000, 0x00000000},
@@ -18796,20 +21080,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000152},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000152},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000152},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00000152},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000152},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x00000052},
+ {0x03F, 0x00000152},
{0xA0000000, 0x00000000},
{0x03F, 0x00000052},
{0xB0000000, 0x00000000},
@@ -18840,20 +21128,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x0000015A},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000015A},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000015A},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000015A},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000015A},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000005A},
+ {0x03F, 0x0000015A},
{0xA0000000, 0x00000000},
{0x03F, 0x0000005A},
{0xB0000000, 0x00000000},
@@ -18884,20 +21176,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x0000019C},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000019C},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000019C},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x0000019C},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x0000019C},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000009C},
+ {0x03F, 0x0000019C},
{0xA0000000, 0x00000000},
{0x03F, 0x0000009C},
{0xB0000000, 0x00000000},
@@ -18928,20 +21224,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x000001A4},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001A4},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001A4},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001A4},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001A4},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x0000019C},
+ {0x03F, 0x000001A4},
{0xA0000000, 0x00000000},
{0x03F, 0x0000019C},
{0xB0000000, 0x00000000},
@@ -18972,20 +21272,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x000001E6},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001E6},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001E6},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000001E6},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000001E6},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001A4},
+ {0x03F, 0x000001E6},
{0xA0000000, 0x00000000},
{0x03F, 0x000001A4},
{0xB0000000, 0x00000000},
@@ -19016,20 +21320,24 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x000002E6},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E6},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E6},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x000002E6},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x000002E6},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x90340001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
- {0x03F, 0x000001E6},
+ {0x03F, 0x000002E6},
{0xA0000000, 0x00000000},
{0x03F, 0x000001E6},
{0xB0000000, 0x00000000},
@@ -20924,7 +23232,7 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x10030, 0x0007BC1D},
{0x10030, 0x0007C017},
{0x10030, 0x0007C40F},
- {0x90320001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x000001EF},
{0x10030, 0x000005E9},
{0x10030, 0x000009E3},
@@ -21069,7 +23377,7 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x10030, 0x0007BC1D},
{0x10030, 0x0007C017},
{0x10030, 0x0007C40F},
- {0x90330001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x000001EF},
{0x10030, 0x000005E9},
{0x10030, 0x000009E3},
@@ -21088,60 +23396,60 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x10030, 0x00003C5F},
{0x10030, 0x00004059},
{0x10030, 0x00004453},
- {0x10030, 0x000201A7},
- {0x10030, 0x000205A1},
- {0x10030, 0x0002099B},
- {0x10030, 0x00020D95},
- {0x10030, 0x0002115B},
- {0x10030, 0x00021555},
- {0x10030, 0x00021921},
- {0x10030, 0x00021D1B},
- {0x10030, 0x000220E3},
- {0x10030, 0x000224DD},
+ {0x10030, 0x000201EF},
+ {0x10030, 0x000205E9},
+ {0x10030, 0x000209E3},
+ {0x10030, 0x00020DA3},
+ {0x10030, 0x00021161},
+ {0x10030, 0x0002155B},
+ {0x10030, 0x0002191F},
+ {0x10030, 0x00021D19},
+ {0x10030, 0x000220E1},
+ {0x10030, 0x000224DB},
{0x10030, 0x000228A3},
{0x10030, 0x00022C9D},
{0x10030, 0x00023063},
{0x10030, 0x0002345D},
{0x10030, 0x00023823},
- {0x10030, 0x00023C1D},
- {0x10030, 0x00024017},
- {0x10030, 0x00024411},
- {0x10030, 0x000281A9},
- {0x10030, 0x000285A3},
- {0x10030, 0x0002899D},
- {0x10030, 0x00028D97},
- {0x10030, 0x0002915D},
- {0x10030, 0x00029557},
- {0x10030, 0x0002991F},
- {0x10030, 0x00029D19},
- {0x10030, 0x0002A0E1},
- {0x10030, 0x0002A4DB},
+ {0x10030, 0x00023C1B},
+ {0x10030, 0x00024015},
+ {0x10030, 0x0002440F},
+ {0x10030, 0x000281EF},
+ {0x10030, 0x000285E7},
+ {0x10030, 0x000289A7},
+ {0x10030, 0x00028D65},
+ {0x10030, 0x0002915F},
+ {0x10030, 0x00029523},
+ {0x10030, 0x0002991D},
+ {0x10030, 0x00029CE5},
+ {0x10030, 0x0002A0DF},
+ {0x10030, 0x0002A4A7},
{0x10030, 0x0002A8A1},
- {0x10030, 0x0002AC9B},
+ {0x10030, 0x0002AC67},
{0x10030, 0x0002B061},
- {0x10030, 0x0002B45B},
+ {0x10030, 0x0002B427},
{0x10030, 0x0002B821},
- {0x10030, 0x0002BC1B},
- {0x10030, 0x0002C015},
- {0x10030, 0x0002C40F},
- {0x10030, 0x000301A9},
- {0x10030, 0x000305A3},
- {0x10030, 0x0003099D},
- {0x10030, 0x00030D97},
- {0x10030, 0x0003115D},
- {0x10030, 0x00031557},
+ {0x10030, 0x0002BC19},
+ {0x10030, 0x0002C013},
+ {0x10030, 0x0002C40D},
+ {0x10030, 0x000301EF},
+ {0x10030, 0x000305E7},
+ {0x10030, 0x000309A7},
+ {0x10030, 0x00030D65},
+ {0x10030, 0x0003115F},
+ {0x10030, 0x00031525},
{0x10030, 0x0003191F},
- {0x10030, 0x00031D19},
+ {0x10030, 0x00031CE7},
{0x10030, 0x000320E1},
- {0x10030, 0x000324DB},
- {0x10030, 0x000328A1},
- {0x10030, 0x00032C9B},
- {0x10030, 0x00033061},
- {0x10030, 0x0003345B},
- {0x10030, 0x00033821},
- {0x10030, 0x00033C1B},
- {0x10030, 0x00034015},
- {0x10030, 0x0003440F},
+ {0x10030, 0x000324A9},
+ {0x10030, 0x000328A3},
+ {0x10030, 0x00032C69},
+ {0x10030, 0x00033063},
+ {0x10030, 0x00033429},
+ {0x10030, 0x00033823},
+ {0x10030, 0x00033C1D},
+ {0x10030, 0x00034013},
+ {0x10030, 0x0003440D},
{0x10030, 0x000601F1},
{0x10030, 0x000605E9},
{0x10030, 0x000609A9},
@@ -21186,7 +23494,7 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x10030, 0x00071523},
{0x10030, 0x0007191D},
{0x10030, 0x00071D17},
- {0x10030, 0x000720DF},
+ {0x10030, 0x00072111},
{0x10030, 0x000724D9},
{0x10030, 0x000728D3},
{0x10030, 0x00072C67},
@@ -21214,7 +23522,7 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x10030, 0x0007BC1D},
{0x10030, 0x0007C017},
{0x10030, 0x0007C40F},
- {0x90340001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x000001EF},
{0x10030, 0x000005E9},
{0x10030, 0x000009E3},
@@ -21233,60 +23541,60 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x10030, 0x00003C5F},
{0x10030, 0x00004059},
{0x10030, 0x00004453},
- {0x10030, 0x000201A7},
- {0x10030, 0x000205A1},
- {0x10030, 0x0002099B},
- {0x10030, 0x00020D95},
- {0x10030, 0x0002115B},
- {0x10030, 0x00021555},
- {0x10030, 0x00021921},
- {0x10030, 0x00021D1B},
- {0x10030, 0x000220E3},
- {0x10030, 0x000224DD},
+ {0x10030, 0x000201EF},
+ {0x10030, 0x000205E9},
+ {0x10030, 0x000209E3},
+ {0x10030, 0x00020DA3},
+ {0x10030, 0x00021161},
+ {0x10030, 0x0002155B},
+ {0x10030, 0x0002191F},
+ {0x10030, 0x00021D19},
+ {0x10030, 0x000220E1},
+ {0x10030, 0x000224DB},
{0x10030, 0x000228A3},
{0x10030, 0x00022C9D},
{0x10030, 0x00023063},
{0x10030, 0x0002345D},
{0x10030, 0x00023823},
- {0x10030, 0x00023C1D},
- {0x10030, 0x00024017},
- {0x10030, 0x00024411},
- {0x10030, 0x000281A9},
- {0x10030, 0x000285A3},
- {0x10030, 0x0002899D},
- {0x10030, 0x00028D97},
- {0x10030, 0x0002915D},
- {0x10030, 0x00029557},
- {0x10030, 0x0002991F},
- {0x10030, 0x00029D19},
- {0x10030, 0x0002A0E1},
- {0x10030, 0x0002A4DB},
+ {0x10030, 0x00023C1B},
+ {0x10030, 0x00024015},
+ {0x10030, 0x0002440F},
+ {0x10030, 0x000281EF},
+ {0x10030, 0x000285E7},
+ {0x10030, 0x000289A7},
+ {0x10030, 0x00028D65},
+ {0x10030, 0x0002915F},
+ {0x10030, 0x00029523},
+ {0x10030, 0x0002991D},
+ {0x10030, 0x00029CE5},
+ {0x10030, 0x0002A0DF},
+ {0x10030, 0x0002A4A7},
{0x10030, 0x0002A8A1},
- {0x10030, 0x0002AC9B},
+ {0x10030, 0x0002AC67},
{0x10030, 0x0002B061},
- {0x10030, 0x0002B45B},
+ {0x10030, 0x0002B427},
{0x10030, 0x0002B821},
- {0x10030, 0x0002BC1B},
- {0x10030, 0x0002C015},
- {0x10030, 0x0002C40F},
- {0x10030, 0x000301A9},
- {0x10030, 0x000305A3},
- {0x10030, 0x0003099D},
- {0x10030, 0x00030D97},
- {0x10030, 0x0003115D},
- {0x10030, 0x00031557},
+ {0x10030, 0x0002BC19},
+ {0x10030, 0x0002C013},
+ {0x10030, 0x0002C40D},
+ {0x10030, 0x000301EF},
+ {0x10030, 0x000305E7},
+ {0x10030, 0x000309A7},
+ {0x10030, 0x00030D65},
+ {0x10030, 0x0003115F},
+ {0x10030, 0x00031525},
{0x10030, 0x0003191F},
- {0x10030, 0x00031D19},
+ {0x10030, 0x00031CE7},
{0x10030, 0x000320E1},
- {0x10030, 0x000324DB},
- {0x10030, 0x000328A1},
- {0x10030, 0x00032C9B},
- {0x10030, 0x00033061},
- {0x10030, 0x0003345B},
- {0x10030, 0x00033821},
- {0x10030, 0x00033C1B},
- {0x10030, 0x00034015},
- {0x10030, 0x0003440F},
+ {0x10030, 0x000324A9},
+ {0x10030, 0x000328A3},
+ {0x10030, 0x00032C69},
+ {0x10030, 0x00033063},
+ {0x10030, 0x00033429},
+ {0x10030, 0x00033823},
+ {0x10030, 0x00033C1D},
+ {0x10030, 0x00034013},
+ {0x10030, 0x0003440D},
{0x10030, 0x000601F1},
{0x10030, 0x000605E9},
{0x10030, 0x000609A9},
@@ -21331,7 +23639,7 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x10030, 0x00071523},
{0x10030, 0x0007191D},
{0x10030, 0x00071D17},
- {0x10030, 0x000720DF},
+ {0x10030, 0x00072111},
{0x10030, 0x000724D9},
{0x10030, 0x000728D3},
{0x10030, 0x00072C67},
@@ -21359,6 +23667,296 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x10030, 0x0007BC1D},
{0x10030, 0x0007C017},
{0x10030, 0x0007C40F},
+ {0x90330001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x000001EF},
+ {0x10030, 0x000005E9},
+ {0x10030, 0x000009E3},
+ {0x10030, 0x00000DDD},
+ {0x10030, 0x000011D7},
+ {0x10030, 0x0000159F},
+ {0x10030, 0x00001999},
+ {0x10030, 0x00001D5F},
+ {0x10030, 0x00002159},
+ {0x10030, 0x0000251F},
+ {0x10030, 0x00002919},
+ {0x10030, 0x00002CDF},
+ {0x10030, 0x000030D9},
+ {0x10030, 0x0000349F},
+ {0x10030, 0x00003899},
+ {0x10030, 0x00003C5F},
+ {0x10030, 0x00004059},
+ {0x10030, 0x00004453},
+ {0x10030, 0x000201A7},
+ {0x10030, 0x000205A1},
+ {0x10030, 0x0002099B},
+ {0x10030, 0x00020D95},
+ {0x10030, 0x0002115B},
+ {0x10030, 0x00021555},
+ {0x10030, 0x00021921},
+ {0x10030, 0x00021D1B},
+ {0x10030, 0x000220E3},
+ {0x10030, 0x000224DD},
+ {0x10030, 0x000228A3},
+ {0x10030, 0x00022C9D},
+ {0x10030, 0x00023063},
+ {0x10030, 0x0002345D},
+ {0x10030, 0x00023823},
+ {0x10030, 0x00023C1D},
+ {0x10030, 0x00024017},
+ {0x10030, 0x00024411},
+ {0x10030, 0x000281A9},
+ {0x10030, 0x000285A3},
+ {0x10030, 0x0002899D},
+ {0x10030, 0x00028D97},
+ {0x10030, 0x0002915D},
+ {0x10030, 0x00029557},
+ {0x10030, 0x0002991F},
+ {0x10030, 0x00029D19},
+ {0x10030, 0x0002A0E1},
+ {0x10030, 0x0002A4DB},
+ {0x10030, 0x0002A8A1},
+ {0x10030, 0x0002AC9B},
+ {0x10030, 0x0002B061},
+ {0x10030, 0x0002B45B},
+ {0x10030, 0x0002B821},
+ {0x10030, 0x0002BC1B},
+ {0x10030, 0x0002C015},
+ {0x10030, 0x0002C40F},
+ {0x10030, 0x000301A9},
+ {0x10030, 0x000305A3},
+ {0x10030, 0x0003099D},
+ {0x10030, 0x00030D97},
+ {0x10030, 0x0003115D},
+ {0x10030, 0x00031557},
+ {0x10030, 0x0003191F},
+ {0x10030, 0x00031D19},
+ {0x10030, 0x000320E1},
+ {0x10030, 0x000324DB},
+ {0x10030, 0x000328A1},
+ {0x10030, 0x00032C9B},
+ {0x10030, 0x00033061},
+ {0x10030, 0x0003345B},
+ {0x10030, 0x00033821},
+ {0x10030, 0x00033C1B},
+ {0x10030, 0x00034015},
+ {0x10030, 0x0003440F},
+ {0x10030, 0x000601F1},
+ {0x10030, 0x000605E9},
+ {0x10030, 0x000609A9},
+ {0x10030, 0x00060D65},
+ {0x10030, 0x0006115F},
+ {0x10030, 0x00061527},
+ {0x10030, 0x00061921},
+ {0x10030, 0x00061CE9},
+ {0x10030, 0x000620E3},
+ {0x10030, 0x000624DD},
+ {0x10030, 0x000628A5},
+ {0x10030, 0x00062C6B},
+ {0x10030, 0x00063065},
+ {0x10030, 0x0006342B},
+ {0x10030, 0x00063825},
+ {0x10030, 0x00063C1F},
+ {0x10030, 0x00064019},
+ {0x10030, 0x00064413},
+ {0x10030, 0x000681EF},
+ {0x10030, 0x000685E7},
+ {0x10030, 0x000689A7},
+ {0x10030, 0x00068D61},
+ {0x10030, 0x0006915B},
+ {0x10030, 0x00069525},
+ {0x10030, 0x0006991F},
+ {0x10030, 0x00069CE7},
+ {0x10030, 0x0006A0E1},
+ {0x10030, 0x0006A4A9},
+ {0x10030, 0x0006A8A3},
+ {0x10030, 0x0006AC69},
+ {0x10030, 0x0006B063},
+ {0x10030, 0x0006B429},
+ {0x10030, 0x0006B823},
+ {0x10030, 0x0006BC1D},
+ {0x10030, 0x0006C017},
+ {0x10030, 0x0006C411},
+ {0x10030, 0x000701EF},
+ {0x10030, 0x000705E9},
+ {0x10030, 0x000709A9},
+ {0x10030, 0x00070D63},
+ {0x10030, 0x0007115D},
+ {0x10030, 0x00071525},
+ {0x10030, 0x0007191F},
+ {0x10030, 0x00071D19},
+ {0x10030, 0x000720E1},
+ {0x10030, 0x000724DB},
+ {0x10030, 0x000728A3},
+ {0x10030, 0x00072C69},
+ {0x10030, 0x00073063},
+ {0x10030, 0x00073429},
+ {0x10030, 0x00073823},
+ {0x10030, 0x00073C1D},
+ {0x10030, 0x00074017},
+ {0x10030, 0x00074411},
+ {0x10030, 0x000781EF},
+ {0x10030, 0x000785E9},
+ {0x10030, 0x000789E3},
+ {0x10030, 0x00078DA1},
+ {0x10030, 0x0007915F},
+ {0x10030, 0x00079559},
+ {0x10030, 0x0007991F},
+ {0x10030, 0x00079D19},
+ {0x10030, 0x0007A0DF},
+ {0x10030, 0x0007A4D9},
+ {0x10030, 0x0007A8D3},
+ {0x10030, 0x0007AC99},
+ {0x10030, 0x0007B05F},
+ {0x10030, 0x0007B459},
+ {0x10030, 0x0007B81F},
+ {0x10030, 0x0007BC19},
+ {0x10030, 0x0007C013},
+ {0x10030, 0x0007C40D},
+ {0x90340001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x000001EF},
+ {0x10030, 0x000005E9},
+ {0x10030, 0x000009E3},
+ {0x10030, 0x00000DDD},
+ {0x10030, 0x000011D7},
+ {0x10030, 0x0000159F},
+ {0x10030, 0x00001999},
+ {0x10030, 0x00001D5F},
+ {0x10030, 0x00002159},
+ {0x10030, 0x0000251F},
+ {0x10030, 0x00002919},
+ {0x10030, 0x00002CDF},
+ {0x10030, 0x000030D9},
+ {0x10030, 0x0000349F},
+ {0x10030, 0x00003899},
+ {0x10030, 0x00003C5F},
+ {0x10030, 0x00004059},
+ {0x10030, 0x00004453},
+ {0x10030, 0x000201A7},
+ {0x10030, 0x000205A1},
+ {0x10030, 0x0002099B},
+ {0x10030, 0x00020D95},
+ {0x10030, 0x0002115B},
+ {0x10030, 0x00021555},
+ {0x10030, 0x00021921},
+ {0x10030, 0x00021D1B},
+ {0x10030, 0x000220E3},
+ {0x10030, 0x000224DD},
+ {0x10030, 0x000228A3},
+ {0x10030, 0x00022C9D},
+ {0x10030, 0x00023063},
+ {0x10030, 0x0002345D},
+ {0x10030, 0x00023823},
+ {0x10030, 0x00023C1D},
+ {0x10030, 0x00024017},
+ {0x10030, 0x00024411},
+ {0x10030, 0x000281A9},
+ {0x10030, 0x000285A3},
+ {0x10030, 0x0002899D},
+ {0x10030, 0x00028D97},
+ {0x10030, 0x0002915D},
+ {0x10030, 0x00029557},
+ {0x10030, 0x0002991F},
+ {0x10030, 0x00029D19},
+ {0x10030, 0x0002A0E1},
+ {0x10030, 0x0002A4DB},
+ {0x10030, 0x0002A8A1},
+ {0x10030, 0x0002AC9B},
+ {0x10030, 0x0002B061},
+ {0x10030, 0x0002B45B},
+ {0x10030, 0x0002B821},
+ {0x10030, 0x0002BC1B},
+ {0x10030, 0x0002C015},
+ {0x10030, 0x0002C40F},
+ {0x10030, 0x000301A9},
+ {0x10030, 0x000305A3},
+ {0x10030, 0x0003099D},
+ {0x10030, 0x00030D97},
+ {0x10030, 0x0003115D},
+ {0x10030, 0x00031557},
+ {0x10030, 0x0003191F},
+ {0x10030, 0x00031D19},
+ {0x10030, 0x000320E1},
+ {0x10030, 0x000324DB},
+ {0x10030, 0x000328A1},
+ {0x10030, 0x00032C9B},
+ {0x10030, 0x00033061},
+ {0x10030, 0x0003345B},
+ {0x10030, 0x00033821},
+ {0x10030, 0x00033C1B},
+ {0x10030, 0x00034015},
+ {0x10030, 0x0003440F},
+ {0x10030, 0x000601F1},
+ {0x10030, 0x000605E9},
+ {0x10030, 0x000609A9},
+ {0x10030, 0x00060D65},
+ {0x10030, 0x0006115F},
+ {0x10030, 0x00061527},
+ {0x10030, 0x00061921},
+ {0x10030, 0x00061CE9},
+ {0x10030, 0x000620E3},
+ {0x10030, 0x000624DD},
+ {0x10030, 0x000628A5},
+ {0x10030, 0x00062C6B},
+ {0x10030, 0x00063065},
+ {0x10030, 0x0006342B},
+ {0x10030, 0x00063825},
+ {0x10030, 0x00063C1F},
+ {0x10030, 0x00064019},
+ {0x10030, 0x00064413},
+ {0x10030, 0x000681EF},
+ {0x10030, 0x000685E7},
+ {0x10030, 0x000689A7},
+ {0x10030, 0x00068D61},
+ {0x10030, 0x0006915B},
+ {0x10030, 0x00069525},
+ {0x10030, 0x0006991F},
+ {0x10030, 0x00069CE7},
+ {0x10030, 0x0006A0E1},
+ {0x10030, 0x0006A4A9},
+ {0x10030, 0x0006A8A3},
+ {0x10030, 0x0006AC69},
+ {0x10030, 0x0006B063},
+ {0x10030, 0x0006B429},
+ {0x10030, 0x0006B823},
+ {0x10030, 0x0006BC1D},
+ {0x10030, 0x0006C017},
+ {0x10030, 0x0006C411},
+ {0x10030, 0x000701EF},
+ {0x10030, 0x000705E9},
+ {0x10030, 0x000709A9},
+ {0x10030, 0x00070D63},
+ {0x10030, 0x0007115D},
+ {0x10030, 0x00071525},
+ {0x10030, 0x0007191F},
+ {0x10030, 0x00071D19},
+ {0x10030, 0x000720E1},
+ {0x10030, 0x000724DB},
+ {0x10030, 0x000728A3},
+ {0x10030, 0x00072C69},
+ {0x10030, 0x00073063},
+ {0x10030, 0x00073429},
+ {0x10030, 0x00073823},
+ {0x10030, 0x00073C1D},
+ {0x10030, 0x00074017},
+ {0x10030, 0x00074411},
+ {0x10030, 0x000781EF},
+ {0x10030, 0x000785E9},
+ {0x10030, 0x000789E3},
+ {0x10030, 0x00078DA1},
+ {0x10030, 0x0007915F},
+ {0x10030, 0x00079559},
+ {0x10030, 0x0007991F},
+ {0x10030, 0x00079D19},
+ {0x10030, 0x0007A0DF},
+ {0x10030, 0x0007A4D9},
+ {0x10030, 0x0007A8D3},
+ {0x10030, 0x0007AC99},
+ {0x10030, 0x0007B05F},
+ {0x10030, 0x0007B459},
+ {0x10030, 0x0007B81F},
+ {0x10030, 0x0007BC19},
+ {0x10030, 0x0007C013},
+ {0x10030, 0x0007C40D},
{0x90350001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x000001EF},
{0x10030, 0x000005E9},
@@ -21437,73 +24035,73 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x10030, 0x000609A9},
{0x10030, 0x00060D65},
{0x10030, 0x0006115F},
- {0x10030, 0x00061525},
- {0x10030, 0x0006191F},
- {0x10030, 0x00061CE7},
- {0x10030, 0x000620E1},
- {0x10030, 0x000624DB},
- {0x10030, 0x000628A3},
- {0x10030, 0x00062C69},
- {0x10030, 0x00063063},
- {0x10030, 0x00063429},
- {0x10030, 0x00063823},
- {0x10030, 0x00063C1D},
- {0x10030, 0x00064013},
- {0x10030, 0x0006440D},
+ {0x10030, 0x00061527},
+ {0x10030, 0x00061921},
+ {0x10030, 0x00061CE9},
+ {0x10030, 0x000620E3},
+ {0x10030, 0x000624DD},
+ {0x10030, 0x000628A5},
+ {0x10030, 0x00062C6B},
+ {0x10030, 0x00063065},
+ {0x10030, 0x0006342B},
+ {0x10030, 0x00063825},
+ {0x10030, 0x00063C1F},
+ {0x10030, 0x00064019},
+ {0x10030, 0x00064413},
{0x10030, 0x000681EF},
{0x10030, 0x000685E7},
{0x10030, 0x000689A7},
{0x10030, 0x00068D61},
{0x10030, 0x0006915B},
- {0x10030, 0x00069523},
- {0x10030, 0x0006991D},
- {0x10030, 0x00069CE5},
- {0x10030, 0x0006A0DF},
- {0x10030, 0x0006A4A7},
- {0x10030, 0x0006A8A1},
- {0x10030, 0x0006AC67},
- {0x10030, 0x0006B061},
+ {0x10030, 0x00069525},
+ {0x10030, 0x0006991F},
+ {0x10030, 0x00069CE7},
+ {0x10030, 0x0006A0E1},
+ {0x10030, 0x0006A4A9},
+ {0x10030, 0x0006A8A3},
+ {0x10030, 0x0006AC69},
+ {0x10030, 0x0006B063},
{0x10030, 0x0006B429},
{0x10030, 0x0006B823},
{0x10030, 0x0006BC1D},
{0x10030, 0x0006C017},
- {0x10030, 0x0006C40D},
- {0x10030, 0x000701F1},
+ {0x10030, 0x0006C411},
+ {0x10030, 0x000701EF},
{0x10030, 0x000705E9},
{0x10030, 0x000709A9},
{0x10030, 0x00070D63},
{0x10030, 0x0007115D},
- {0x10030, 0x00071523},
- {0x10030, 0x0007191D},
- {0x10030, 0x00071D17},
- {0x10030, 0x000720DF},
- {0x10030, 0x000724D9},
- {0x10030, 0x000728D3},
- {0x10030, 0x00072C67},
- {0x10030, 0x00073061},
- {0x10030, 0x00073427},
- {0x10030, 0x00073821},
- {0x10030, 0x00073C1B},
- {0x10030, 0x00074015},
- {0x10030, 0x0007440D},
- {0x10030, 0x000781F1},
- {0x10030, 0x000785EB},
- {0x10030, 0x000789E5},
- {0x10030, 0x00078DA3},
- {0x10030, 0x00079161},
- {0x10030, 0x0007955B},
- {0x10030, 0x00079923},
- {0x10030, 0x00079D1D},
- {0x10030, 0x0007A117},
- {0x10030, 0x0007A4DD},
- {0x10030, 0x0007A8D7},
- {0x10030, 0x0007AC9D},
- {0x10030, 0x0007B063},
- {0x10030, 0x0007B45D},
- {0x10030, 0x0007B857},
- {0x10030, 0x0007BC1D},
- {0x10030, 0x0007C017},
- {0x10030, 0x0007C40F},
+ {0x10030, 0x00071525},
+ {0x10030, 0x0007191F},
+ {0x10030, 0x00071D19},
+ {0x10030, 0x000720E1},
+ {0x10030, 0x000724DB},
+ {0x10030, 0x000728A3},
+ {0x10030, 0x00072C69},
+ {0x10030, 0x00073063},
+ {0x10030, 0x00073429},
+ {0x10030, 0x00073823},
+ {0x10030, 0x00073C1D},
+ {0x10030, 0x00074017},
+ {0x10030, 0x00074411},
+ {0x10030, 0x000781EF},
+ {0x10030, 0x000785E9},
+ {0x10030, 0x000789E3},
+ {0x10030, 0x00078DA1},
+ {0x10030, 0x0007915F},
+ {0x10030, 0x00079559},
+ {0x10030, 0x0007991F},
+ {0x10030, 0x00079D19},
+ {0x10030, 0x0007A0DF},
+ {0x10030, 0x0007A4D9},
+ {0x10030, 0x0007A8D3},
+ {0x10030, 0x0007AC99},
+ {0x10030, 0x0007B05F},
+ {0x10030, 0x0007B459},
+ {0x10030, 0x0007B81F},
+ {0x10030, 0x0007BC19},
+ {0x10030, 0x0007C013},
+ {0x10030, 0x0007C40D},
{0x90360001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x000001EF},
{0x10030, 0x000005E9},
@@ -21582,73 +24180,73 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x10030, 0x000609A9},
{0x10030, 0x00060D65},
{0x10030, 0x0006115F},
- {0x10030, 0x00061525},
- {0x10030, 0x0006191F},
- {0x10030, 0x00061CE7},
- {0x10030, 0x000620E1},
- {0x10030, 0x000624DB},
- {0x10030, 0x000628A3},
- {0x10030, 0x00062C69},
- {0x10030, 0x00063063},
- {0x10030, 0x00063429},
- {0x10030, 0x00063823},
- {0x10030, 0x00063C1D},
- {0x10030, 0x00064013},
- {0x10030, 0x0006440D},
+ {0x10030, 0x00061527},
+ {0x10030, 0x00061921},
+ {0x10030, 0x00061CE9},
+ {0x10030, 0x000620E3},
+ {0x10030, 0x000624DD},
+ {0x10030, 0x000628A5},
+ {0x10030, 0x00062C6B},
+ {0x10030, 0x00063065},
+ {0x10030, 0x0006342B},
+ {0x10030, 0x00063825},
+ {0x10030, 0x00063C1F},
+ {0x10030, 0x00064019},
+ {0x10030, 0x00064413},
{0x10030, 0x000681EF},
{0x10030, 0x000685E7},
{0x10030, 0x000689A7},
{0x10030, 0x00068D61},
{0x10030, 0x0006915B},
- {0x10030, 0x00069523},
- {0x10030, 0x0006991D},
- {0x10030, 0x00069CE5},
- {0x10030, 0x0006A0DF},
- {0x10030, 0x0006A4A7},
- {0x10030, 0x0006A8A1},
- {0x10030, 0x0006AC67},
- {0x10030, 0x0006B061},
+ {0x10030, 0x00069525},
+ {0x10030, 0x0006991F},
+ {0x10030, 0x00069CE7},
+ {0x10030, 0x0006A0E1},
+ {0x10030, 0x0006A4A9},
+ {0x10030, 0x0006A8A3},
+ {0x10030, 0x0006AC69},
+ {0x10030, 0x0006B063},
{0x10030, 0x0006B429},
{0x10030, 0x0006B823},
{0x10030, 0x0006BC1D},
{0x10030, 0x0006C017},
- {0x10030, 0x0006C40D},
- {0x10030, 0x000701F1},
+ {0x10030, 0x0006C411},
+ {0x10030, 0x000701EF},
{0x10030, 0x000705E9},
{0x10030, 0x000709A9},
{0x10030, 0x00070D63},
{0x10030, 0x0007115D},
- {0x10030, 0x00071523},
- {0x10030, 0x0007191D},
- {0x10030, 0x00071D17},
- {0x10030, 0x000720DF},
- {0x10030, 0x000724D9},
- {0x10030, 0x000728D3},
- {0x10030, 0x00072C67},
- {0x10030, 0x00073061},
- {0x10030, 0x00073427},
- {0x10030, 0x00073821},
- {0x10030, 0x00073C1B},
- {0x10030, 0x00074015},
- {0x10030, 0x0007440D},
- {0x10030, 0x000781F1},
- {0x10030, 0x000785EB},
- {0x10030, 0x000789E5},
- {0x10030, 0x00078DA3},
- {0x10030, 0x00079161},
- {0x10030, 0x0007955B},
- {0x10030, 0x00079923},
- {0x10030, 0x00079D1D},
- {0x10030, 0x0007A117},
- {0x10030, 0x0007A4DD},
- {0x10030, 0x0007A8D7},
- {0x10030, 0x0007AC9D},
- {0x10030, 0x0007B063},
- {0x10030, 0x0007B45D},
- {0x10030, 0x0007B857},
- {0x10030, 0x0007BC1D},
- {0x10030, 0x0007C017},
- {0x10030, 0x0007C40F},
+ {0x10030, 0x00071525},
+ {0x10030, 0x0007191F},
+ {0x10030, 0x00071D19},
+ {0x10030, 0x000720E1},
+ {0x10030, 0x000724DB},
+ {0x10030, 0x000728A3},
+ {0x10030, 0x00072C69},
+ {0x10030, 0x00073063},
+ {0x10030, 0x00073429},
+ {0x10030, 0x00073823},
+ {0x10030, 0x00073C1D},
+ {0x10030, 0x00074017},
+ {0x10030, 0x00074411},
+ {0x10030, 0x000781EF},
+ {0x10030, 0x000785E9},
+ {0x10030, 0x000789E3},
+ {0x10030, 0x00078DA1},
+ {0x10030, 0x0007915F},
+ {0x10030, 0x00079559},
+ {0x10030, 0x0007991F},
+ {0x10030, 0x00079D19},
+ {0x10030, 0x0007A0DF},
+ {0x10030, 0x0007A4D9},
+ {0x10030, 0x0007A8D3},
+ {0x10030, 0x0007AC99},
+ {0x10030, 0x0007B05F},
+ {0x10030, 0x0007B459},
+ {0x10030, 0x0007B81F},
+ {0x10030, 0x0007BC19},
+ {0x10030, 0x0007C013},
+ {0x10030, 0x0007C40D},
{0x903f0001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x000001EF},
{0x10030, 0x000005E9},
@@ -21727,73 +24325,73 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x10030, 0x000609A9},
{0x10030, 0x00060D65},
{0x10030, 0x0006115F},
- {0x10030, 0x00061525},
- {0x10030, 0x0006191F},
- {0x10030, 0x00061CE7},
- {0x10030, 0x000620E1},
- {0x10030, 0x000624DB},
- {0x10030, 0x000628A3},
- {0x10030, 0x00062C69},
- {0x10030, 0x00063063},
- {0x10030, 0x00063429},
- {0x10030, 0x00063823},
- {0x10030, 0x00063C1D},
- {0x10030, 0x00064013},
- {0x10030, 0x0006440D},
+ {0x10030, 0x00061527},
+ {0x10030, 0x00061921},
+ {0x10030, 0x00061CE9},
+ {0x10030, 0x000620E3},
+ {0x10030, 0x000624DD},
+ {0x10030, 0x000628A5},
+ {0x10030, 0x00062C6B},
+ {0x10030, 0x00063065},
+ {0x10030, 0x0006342B},
+ {0x10030, 0x00063825},
+ {0x10030, 0x00063C1F},
+ {0x10030, 0x00064019},
+ {0x10030, 0x00064413},
{0x10030, 0x000681EF},
{0x10030, 0x000685E7},
{0x10030, 0x000689A7},
{0x10030, 0x00068D61},
{0x10030, 0x0006915B},
- {0x10030, 0x00069523},
- {0x10030, 0x0006991D},
- {0x10030, 0x00069CE5},
- {0x10030, 0x0006A0DF},
- {0x10030, 0x0006A4A7},
- {0x10030, 0x0006A8A1},
- {0x10030, 0x0006AC67},
- {0x10030, 0x0006B061},
+ {0x10030, 0x00069525},
+ {0x10030, 0x0006991F},
+ {0x10030, 0x00069CE7},
+ {0x10030, 0x0006A0E1},
+ {0x10030, 0x0006A4A9},
+ {0x10030, 0x0006A8A3},
+ {0x10030, 0x0006AC69},
+ {0x10030, 0x0006B063},
{0x10030, 0x0006B429},
{0x10030, 0x0006B823},
{0x10030, 0x0006BC1D},
{0x10030, 0x0006C017},
- {0x10030, 0x0006C40D},
- {0x10030, 0x000701F1},
+ {0x10030, 0x0006C411},
+ {0x10030, 0x000701EF},
{0x10030, 0x000705E9},
{0x10030, 0x000709A9},
{0x10030, 0x00070D63},
{0x10030, 0x0007115D},
- {0x10030, 0x00071523},
- {0x10030, 0x0007191D},
- {0x10030, 0x00071D17},
- {0x10030, 0x000720DF},
- {0x10030, 0x000724D9},
- {0x10030, 0x000728D3},
- {0x10030, 0x00072C67},
- {0x10030, 0x00073061},
- {0x10030, 0x00073427},
- {0x10030, 0x00073821},
- {0x10030, 0x00073C1B},
- {0x10030, 0x00074015},
- {0x10030, 0x0007440D},
- {0x10030, 0x000781F1},
- {0x10030, 0x000785EB},
- {0x10030, 0x000789E5},
- {0x10030, 0x00078DA3},
- {0x10030, 0x00079161},
- {0x10030, 0x0007955B},
- {0x10030, 0x00079923},
- {0x10030, 0x00079D1D},
- {0x10030, 0x0007A117},
- {0x10030, 0x0007A4DD},
- {0x10030, 0x0007A8D7},
- {0x10030, 0x0007AC9D},
- {0x10030, 0x0007B063},
- {0x10030, 0x0007B45D},
- {0x10030, 0x0007B857},
- {0x10030, 0x0007BC1D},
- {0x10030, 0x0007C017},
- {0x10030, 0x0007C40F},
+ {0x10030, 0x00071525},
+ {0x10030, 0x0007191F},
+ {0x10030, 0x00071D19},
+ {0x10030, 0x000720E1},
+ {0x10030, 0x000724DB},
+ {0x10030, 0x000728A3},
+ {0x10030, 0x00072C69},
+ {0x10030, 0x00073063},
+ {0x10030, 0x00073429},
+ {0x10030, 0x00073823},
+ {0x10030, 0x00073C1D},
+ {0x10030, 0x00074017},
+ {0x10030, 0x00074411},
+ {0x10030, 0x000781EF},
+ {0x10030, 0x000785E9},
+ {0x10030, 0x000789E3},
+ {0x10030, 0x00078DA1},
+ {0x10030, 0x0007915F},
+ {0x10030, 0x00079559},
+ {0x10030, 0x0007991F},
+ {0x10030, 0x00079D19},
+ {0x10030, 0x0007A0DF},
+ {0x10030, 0x0007A4D9},
+ {0x10030, 0x0007A8D3},
+ {0x10030, 0x0007AC99},
+ {0x10030, 0x0007B05F},
+ {0x10030, 0x0007B459},
+ {0x10030, 0x0007B81F},
+ {0x10030, 0x0007BC19},
+ {0x10030, 0x0007C013},
+ {0x10030, 0x0007C40D},
{0x90400001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x000001EF},
{0x10030, 0x000005E9},
@@ -21872,73 +24470,73 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x10030, 0x000609A9},
{0x10030, 0x00060D65},
{0x10030, 0x0006115F},
- {0x10030, 0x00061525},
- {0x10030, 0x0006191F},
- {0x10030, 0x00061CE7},
- {0x10030, 0x000620E1},
- {0x10030, 0x000624DB},
- {0x10030, 0x000628A3},
- {0x10030, 0x00062C69},
- {0x10030, 0x00063063},
- {0x10030, 0x00063429},
- {0x10030, 0x00063823},
- {0x10030, 0x00063C1D},
- {0x10030, 0x00064013},
- {0x10030, 0x0006440D},
+ {0x10030, 0x00061527},
+ {0x10030, 0x00061921},
+ {0x10030, 0x00061CE9},
+ {0x10030, 0x000620E3},
+ {0x10030, 0x000624DD},
+ {0x10030, 0x000628A5},
+ {0x10030, 0x00062C6B},
+ {0x10030, 0x00063065},
+ {0x10030, 0x0006342B},
+ {0x10030, 0x00063825},
+ {0x10030, 0x00063C1F},
+ {0x10030, 0x00064019},
+ {0x10030, 0x00064413},
{0x10030, 0x000681EF},
{0x10030, 0x000685E7},
{0x10030, 0x000689A7},
{0x10030, 0x00068D61},
{0x10030, 0x0006915B},
- {0x10030, 0x00069523},
- {0x10030, 0x0006991D},
- {0x10030, 0x00069CE5},
- {0x10030, 0x0006A0DF},
- {0x10030, 0x0006A4A7},
- {0x10030, 0x0006A8A1},
- {0x10030, 0x0006AC67},
- {0x10030, 0x0006B061},
+ {0x10030, 0x00069525},
+ {0x10030, 0x0006991F},
+ {0x10030, 0x00069CE7},
+ {0x10030, 0x0006A0E1},
+ {0x10030, 0x0006A4A9},
+ {0x10030, 0x0006A8A3},
+ {0x10030, 0x0006AC69},
+ {0x10030, 0x0006B063},
{0x10030, 0x0006B429},
{0x10030, 0x0006B823},
{0x10030, 0x0006BC1D},
{0x10030, 0x0006C017},
- {0x10030, 0x0006C40D},
- {0x10030, 0x000701F1},
+ {0x10030, 0x0006C411},
+ {0x10030, 0x000701EF},
{0x10030, 0x000705E9},
{0x10030, 0x000709A9},
{0x10030, 0x00070D63},
{0x10030, 0x0007115D},
- {0x10030, 0x00071523},
- {0x10030, 0x0007191D},
- {0x10030, 0x00071D17},
- {0x10030, 0x000720DF},
- {0x10030, 0x000724D9},
- {0x10030, 0x000728D3},
- {0x10030, 0x00072C67},
- {0x10030, 0x00073061},
- {0x10030, 0x00073427},
- {0x10030, 0x00073821},
- {0x10030, 0x00073C1B},
- {0x10030, 0x00074015},
- {0x10030, 0x0007440D},
- {0x10030, 0x000781F1},
- {0x10030, 0x000785EB},
- {0x10030, 0x000789E5},
- {0x10030, 0x00078DA3},
- {0x10030, 0x00079161},
- {0x10030, 0x0007955B},
- {0x10030, 0x00079923},
- {0x10030, 0x00079D1D},
- {0x10030, 0x0007A117},
- {0x10030, 0x0007A4DD},
- {0x10030, 0x0007A8D7},
- {0x10030, 0x0007AC9D},
- {0x10030, 0x0007B063},
- {0x10030, 0x0007B45D},
- {0x10030, 0x0007B857},
- {0x10030, 0x0007BC1D},
- {0x10030, 0x0007C017},
- {0x10030, 0x0007C40F},
+ {0x10030, 0x00071525},
+ {0x10030, 0x0007191F},
+ {0x10030, 0x00071D19},
+ {0x10030, 0x000720E1},
+ {0x10030, 0x000724DB},
+ {0x10030, 0x000728A3},
+ {0x10030, 0x00072C69},
+ {0x10030, 0x00073063},
+ {0x10030, 0x00073429},
+ {0x10030, 0x00073823},
+ {0x10030, 0x00073C1D},
+ {0x10030, 0x00074017},
+ {0x10030, 0x00074411},
+ {0x10030, 0x000781EF},
+ {0x10030, 0x000785E9},
+ {0x10030, 0x000789E3},
+ {0x10030, 0x00078DA1},
+ {0x10030, 0x0007915F},
+ {0x10030, 0x00079559},
+ {0x10030, 0x0007991F},
+ {0x10030, 0x00079D19},
+ {0x10030, 0x0007A0DF},
+ {0x10030, 0x0007A4D9},
+ {0x10030, 0x0007A8D3},
+ {0x10030, 0x0007AC99},
+ {0x10030, 0x0007B05F},
+ {0x10030, 0x0007B459},
+ {0x10030, 0x0007B81F},
+ {0x10030, 0x0007BC19},
+ {0x10030, 0x0007C013},
+ {0x10030, 0x0007C40D},
{0xA0000000, 0x00000000},
{0x10030, 0x000001EF},
{0x10030, 0x000005E9},
@@ -22782,6 +25380,110 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x10030, 0x000338CC},
{0x10030, 0x00033C09},
{0x10030, 0x00034006},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x000200E8},
+ {0x10030, 0x000204E5},
+ {0x10030, 0x000208E2},
+ {0x10030, 0x00020CDF},
+ {0x10030, 0x000210DC},
+ {0x10030, 0x000214D9},
+ {0x10030, 0x000218D6},
+ {0x10030, 0x00021CD3},
+ {0x10030, 0x000220D0},
+ {0x10030, 0x0002240D},
+ {0x10030, 0x0002280A},
+ {0x10030, 0x00022C07},
+ {0x10030, 0x00023004},
+ {0x10030, 0x00023401},
+ {0x10030, 0x00023800},
+ {0x10030, 0x00023C00},
+ {0x10030, 0x00024000},
+ {0x10030, 0x000280E7},
+ {0x10030, 0x000284E4},
+ {0x10030, 0x000288E1},
+ {0x10030, 0x00028CDE},
+ {0x10030, 0x000290DB},
+ {0x10030, 0x000294D8},
+ {0x10030, 0x000298D5},
+ {0x10030, 0x00029CD2},
+ {0x10030, 0x0002A0CF},
+ {0x10030, 0x0002A40C},
+ {0x10030, 0x0002A809},
+ {0x10030, 0x0002AC06},
+ {0x10030, 0x0002B003},
+ {0x10030, 0x0002B400},
+ {0x10030, 0x0002B800},
+ {0x10030, 0x0002BC00},
+ {0x10030, 0x0002C000},
+ {0x10030, 0x000300E7},
+ {0x10030, 0x000304E4},
+ {0x10030, 0x000308E1},
+ {0x10030, 0x00030CDE},
+ {0x10030, 0x000310DB},
+ {0x10030, 0x000314D8},
+ {0x10030, 0x000318D5},
+ {0x10030, 0x00031CD2},
+ {0x10030, 0x000320CF},
+ {0x10030, 0x000324CC},
+ {0x10030, 0x00032809},
+ {0x10030, 0x00032C06},
+ {0x10030, 0x00033003},
+ {0x10030, 0x00033400},
+ {0x10030, 0x00033800},
+ {0x10030, 0x00033C00},
+ {0x10030, 0x00034000},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x000200E8},
+ {0x10030, 0x000204E5},
+ {0x10030, 0x000208E2},
+ {0x10030, 0x00020CDF},
+ {0x10030, 0x000210DC},
+ {0x10030, 0x000214D9},
+ {0x10030, 0x000218D6},
+ {0x10030, 0x00021CD3},
+ {0x10030, 0x000220D0},
+ {0x10030, 0x0002240D},
+ {0x10030, 0x0002280A},
+ {0x10030, 0x00022C07},
+ {0x10030, 0x00023004},
+ {0x10030, 0x00023401},
+ {0x10030, 0x00023800},
+ {0x10030, 0x00023C00},
+ {0x10030, 0x00024000},
+ {0x10030, 0x000280E7},
+ {0x10030, 0x000284E4},
+ {0x10030, 0x000288E1},
+ {0x10030, 0x00028CDE},
+ {0x10030, 0x000290DB},
+ {0x10030, 0x000294D8},
+ {0x10030, 0x000298D5},
+ {0x10030, 0x00029CD2},
+ {0x10030, 0x0002A0CF},
+ {0x10030, 0x0002A40C},
+ {0x10030, 0x0002A809},
+ {0x10030, 0x0002AC06},
+ {0x10030, 0x0002B003},
+ {0x10030, 0x0002B400},
+ {0x10030, 0x0002B800},
+ {0x10030, 0x0002BC00},
+ {0x10030, 0x0002C000},
+ {0x10030, 0x000300E7},
+ {0x10030, 0x000304E4},
+ {0x10030, 0x000308E1},
+ {0x10030, 0x00030CDE},
+ {0x10030, 0x000310DB},
+ {0x10030, 0x000314D8},
+ {0x10030, 0x000318D5},
+ {0x10030, 0x00031CD2},
+ {0x10030, 0x000320CF},
+ {0x10030, 0x000324CC},
+ {0x10030, 0x00032809},
+ {0x10030, 0x00032C06},
+ {0x10030, 0x00033003},
+ {0x10030, 0x00033400},
+ {0x10030, 0x00033800},
+ {0x10030, 0x00033C00},
+ {0x10030, 0x00034000},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x000200FA},
{0x10030, 0x000204F7},
@@ -23329,6 +26031,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -23373,6 +26079,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -23429,6 +26139,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -23473,6 +26187,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -23529,6 +26247,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -23573,6 +26295,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -23629,6 +26355,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -23673,6 +26403,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -23729,6 +26463,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -23773,6 +26511,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -23829,6 +26571,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -23873,6 +26619,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -23929,6 +26679,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -23973,6 +26727,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -24029,6 +26787,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -24073,6 +26835,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -24129,6 +26895,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -24173,6 +26943,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -24229,6 +27003,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -24273,6 +27051,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -24329,6 +27111,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -24373,6 +27159,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -24429,6 +27219,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -24473,6 +27267,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -24529,6 +27327,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -24573,6 +27375,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -24629,6 +27435,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -24673,6 +27483,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -24729,6 +27543,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -24773,6 +27591,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -24829,6 +27651,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -24873,6 +27699,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -24929,6 +27759,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -24973,6 +27807,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -25029,6 +27867,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -25073,6 +27915,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -25129,6 +27975,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -25173,6 +28023,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -25229,6 +28083,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -25273,6 +28131,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -25329,6 +28191,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -25373,6 +28239,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -25429,6 +28299,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -25473,6 +28347,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -25529,6 +28407,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -25573,6 +28455,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -25629,6 +28515,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -25673,6 +28563,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -25729,6 +28623,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -25773,6 +28671,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -25829,6 +28731,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -25873,6 +28779,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -25929,6 +28839,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -25973,6 +28887,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -26029,6 +28947,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -26073,6 +28995,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x00000003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x03F, 0x00008002},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x03F, 0x00000003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -26157,6 +29083,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x10030, 0x00025003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x00025003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x00025003},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x00025003},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x00025003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -26207,6 +29137,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x10030, 0x0002D003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x0002D003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x0002D003},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x0002D003},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x0002D003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -26257,6 +29191,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x10030, 0x00035003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x00035003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x00035003},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x00035003},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x00035003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -26307,6 +29245,10 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x10030, 0x0003D003},
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x0003D003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x0003D003},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x0003D003},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x0003D003},
{0x90330001, 0x00000000}, {0x40000000, 0x00000000},
@@ -26370,6 +29312,12 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x00065003},
{0x10030, 0x00066003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x00065003},
+ {0x10030, 0x00066003},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x00065003},
+ {0x10030, 0x00066003},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x00065003},
{0x10030, 0x00066003},
@@ -26440,6 +29388,12 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x0006D003},
{0x10030, 0x0006E003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x0006D003},
+ {0x10030, 0x0006E003},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x0006D003},
+ {0x10030, 0x0006E003},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x0006D003},
{0x10030, 0x0006E003},
@@ -26510,6 +29464,12 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x00075003},
{0x10030, 0x00076003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x00075003},
+ {0x10030, 0x00076003},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x00075003},
+ {0x10030, 0x00076003},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x00075003},
{0x10030, 0x00076003},
@@ -26580,6 +29540,12 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x90070001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x0007D003},
{0x10030, 0x0007E003},
+ {0x90150001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x0007D003},
+ {0x10030, 0x0007E003},
+ {0x90160001, 0x00000000}, {0x40000000, 0x00000000},
+ {0x10030, 0x0007D003},
+ {0x10030, 0x0007E003},
{0x90320001, 0x00000000}, {0x40000000, 0x00000000},
{0x10030, 0x0007D003},
{0x10030, 0x0007E003},
@@ -26621,7 +29587,7 @@ static const struct rtw89_reg2_def rtw89_8852c_phy_radiob_regs[] = {
{0x03F, 0x0000000A},
{0x0ED, 0x00000000},
{0x100EE, 0x00000000},
- {0x0FE, 0x00000048},
+ {0x0FE, 0x00000063},
};
static const struct rtw89_reg2_def rtw89_8852c_phy_nctl_regs[] = {
@@ -28430,11 +31396,11 @@ static const struct rtw89_txpwr_byrate_cfg rtw89_8852c_txpwr_byrate[] = {
{ 2, 0, 1, 4, 4, 0x383c4040, },
{ 2, 0, 2, 0, 4, 0x40404040, },
{ 2, 0, 2, 4, 4, 0x34383c40, },
- { 2, 0, 2, 8, 4, 0x24282c30, },
+ { 2, 0, 2, 8, 4, 0x20282c30, },
{ 2, 0, 3, 0, 4, 0x40404040, },
{ 2, 1, 2, 0, 4, 0x40404040, },
{ 2, 1, 2, 4, 4, 0x34383c40, },
- { 2, 1, 2, 8, 4, 0x24282c30, },
+ { 2, 1, 2, 8, 4, 0x20282c30, },
{ 2, 1, 3, 0, 4, 0x40404040, },
{ 2, 0, 4, 0, 4, 0x00000000, },
};
@@ -28559,35 +31525,53 @@ static const s8 _txpwr_track_delta_swingidx_2g_cck_a_p[] = {
3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 5, 5, 5
};
-const u8 rtw89_8852c_tx_shape[RTW89_BAND_MAX][RTW89_RS_TX_SHAPE_NUM]
+const u8 rtw89_8852c_tx_shape[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM]
[RTW89_REGD_NUM] = {
[0][0][RTW89_ACMA] = 0,
+ [0][0][RTW89_CHILE] = 0,
[0][0][RTW89_CN] = 0,
[0][0][RTW89_ETSI] = 0,
[0][0][RTW89_FCC] = 1,
[0][0][RTW89_IC] = 1,
[0][0][RTW89_KCC] = 0,
+ [0][0][RTW89_MEXICO] = 1,
[0][0][RTW89_MKK] = 0,
+ [0][0][RTW89_QATAR] = 0,
[0][0][RTW89_UK] = 0,
+ [0][0][RTW89_UKRAINE] = 0,
[0][1][RTW89_ACMA] = 0,
+ [0][1][RTW89_CHILE] = 0,
[0][1][RTW89_CN] = 0,
[0][1][RTW89_ETSI] = 0,
[0][1][RTW89_FCC] = 3,
[0][1][RTW89_IC] = 3,
[0][1][RTW89_KCC] = 0,
+ [0][1][RTW89_MEXICO] = 3,
[0][1][RTW89_MKK] = 0,
+ [0][1][RTW89_QATAR] = 0,
[0][1][RTW89_UK] = 0,
+ [0][1][RTW89_UKRAINE] = 0,
[1][1][RTW89_ACMA] = 0,
+ [1][1][RTW89_CHILE] = 0,
[1][1][RTW89_CN] = 0,
[1][1][RTW89_ETSI] = 0,
[1][1][RTW89_FCC] = 3,
[1][1][RTW89_IC] = 3,
[1][1][RTW89_KCC] = 0,
+ [1][1][RTW89_MEXICO] = 3,
[1][1][RTW89_MKK] = 0,
+ [1][1][RTW89_QATAR] = 0,
[1][1][RTW89_UK] = 0,
+ [1][1][RTW89_UKRAINE] = 0,
+ [2][1][RTW89_ACMA] = 0,
+ [2][1][RTW89_CHILE] = 0,
[2][1][RTW89_ETSI] = 0,
[2][1][RTW89_FCC] = 0,
+ [2][1][RTW89_IC] = 0,
[2][1][RTW89_KCC] = 0,
+ [2][1][RTW89_MKK] = 0,
+ [2][1][RTW89_QATAR] = 0,
+ [2][1][RTW89_UK] = 0,
};
static
@@ -28770,6 +31754,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][0][0][RTW89_ACMA][0] = 60,
[0][0][0][0][RTW89_CN][0] = 58,
[0][0][0][0][RTW89_UK][0] = 60,
+ [0][0][0][0][RTW89_MEXICO][0] = 76,
+ [0][0][0][0][RTW89_UKRAINE][0] = 60,
+ [0][0][0][0][RTW89_CHILE][0] = 76,
+ [0][0][0][0][RTW89_QATAR][0] = 60,
[0][0][0][0][RTW89_FCC][1] = 76,
[0][0][0][0][RTW89_ETSI][1] = 60,
[0][0][0][0][RTW89_MKK][1] = 68,
@@ -28778,6 +31766,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][0][0][RTW89_ACMA][1] = 60,
[0][0][0][0][RTW89_CN][1] = 58,
[0][0][0][0][RTW89_UK][1] = 60,
+ [0][0][0][0][RTW89_MEXICO][1] = 76,
+ [0][0][0][0][RTW89_UKRAINE][1] = 60,
+ [0][0][0][0][RTW89_CHILE][1] = 68,
+ [0][0][0][0][RTW89_QATAR][1] = 60,
[0][0][0][0][RTW89_FCC][2] = 76,
[0][0][0][0][RTW89_ETSI][2] = 60,
[0][0][0][0][RTW89_MKK][2] = 68,
@@ -28786,6 +31778,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][0][0][RTW89_ACMA][2] = 60,
[0][0][0][0][RTW89_CN][2] = 58,
[0][0][0][0][RTW89_UK][2] = 60,
+ [0][0][0][0][RTW89_MEXICO][2] = 76,
+ [0][0][0][0][RTW89_UKRAINE][2] = 60,
+ [0][0][0][0][RTW89_CHILE][2] = 68,
+ [0][0][0][0][RTW89_QATAR][2] = 60,
[0][0][0][0][RTW89_FCC][3] = 76,
[0][0][0][0][RTW89_ETSI][3] = 60,
[0][0][0][0][RTW89_MKK][3] = 68,
@@ -28794,6 +31790,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][0][0][RTW89_ACMA][3] = 60,
[0][0][0][0][RTW89_CN][3] = 58,
[0][0][0][0][RTW89_UK][3] = 60,
+ [0][0][0][0][RTW89_MEXICO][3] = 76,
+ [0][0][0][0][RTW89_UKRAINE][3] = 60,
+ [0][0][0][0][RTW89_CHILE][3] = 68,
+ [0][0][0][0][RTW89_QATAR][3] = 60,
[0][0][0][0][RTW89_FCC][4] = 76,
[0][0][0][0][RTW89_ETSI][4] = 60,
[0][0][0][0][RTW89_MKK][4] = 68,
@@ -28802,6 +31802,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][0][0][RTW89_ACMA][4] = 60,
[0][0][0][0][RTW89_CN][4] = 58,
[0][0][0][0][RTW89_UK][4] = 60,
+ [0][0][0][0][RTW89_MEXICO][4] = 76,
+ [0][0][0][0][RTW89_UKRAINE][4] = 60,
+ [0][0][0][0][RTW89_CHILE][4] = 68,
+ [0][0][0][0][RTW89_QATAR][4] = 60,
[0][0][0][0][RTW89_FCC][5] = 76,
[0][0][0][0][RTW89_ETSI][5] = 60,
[0][0][0][0][RTW89_MKK][5] = 68,
@@ -28810,6 +31814,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][0][0][RTW89_ACMA][5] = 60,
[0][0][0][0][RTW89_CN][5] = 58,
[0][0][0][0][RTW89_UK][5] = 60,
+ [0][0][0][0][RTW89_MEXICO][5] = 76,
+ [0][0][0][0][RTW89_UKRAINE][5] = 60,
+ [0][0][0][0][RTW89_CHILE][5] = 76,
+ [0][0][0][0][RTW89_QATAR][5] = 60,
[0][0][0][0][RTW89_FCC][6] = 76,
[0][0][0][0][RTW89_ETSI][6] = 60,
[0][0][0][0][RTW89_MKK][6] = 68,
@@ -28818,6 +31826,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][0][0][RTW89_ACMA][6] = 60,
[0][0][0][0][RTW89_CN][6] = 58,
[0][0][0][0][RTW89_UK][6] = 60,
+ [0][0][0][0][RTW89_MEXICO][6] = 76,
+ [0][0][0][0][RTW89_UKRAINE][6] = 60,
+ [0][0][0][0][RTW89_CHILE][6] = 76,
+ [0][0][0][0][RTW89_QATAR][6] = 60,
[0][0][0][0][RTW89_FCC][7] = 76,
[0][0][0][0][RTW89_ETSI][7] = 60,
[0][0][0][0][RTW89_MKK][7] = 68,
@@ -28826,6 +31838,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][0][0][RTW89_ACMA][7] = 60,
[0][0][0][0][RTW89_CN][7] = 58,
[0][0][0][0][RTW89_UK][7] = 60,
+ [0][0][0][0][RTW89_MEXICO][7] = 76,
+ [0][0][0][0][RTW89_UKRAINE][7] = 60,
+ [0][0][0][0][RTW89_CHILE][7] = 76,
+ [0][0][0][0][RTW89_QATAR][7] = 60,
[0][0][0][0][RTW89_FCC][8] = 76,
[0][0][0][0][RTW89_ETSI][8] = 60,
[0][0][0][0][RTW89_MKK][8] = 68,
@@ -28834,6 +31850,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][0][0][RTW89_ACMA][8] = 60,
[0][0][0][0][RTW89_CN][8] = 58,
[0][0][0][0][RTW89_UK][8] = 60,
+ [0][0][0][0][RTW89_MEXICO][8] = 76,
+ [0][0][0][0][RTW89_UKRAINE][8] = 60,
+ [0][0][0][0][RTW89_CHILE][8] = 76,
+ [0][0][0][0][RTW89_QATAR][8] = 60,
[0][0][0][0][RTW89_FCC][9] = 76,
[0][0][0][0][RTW89_ETSI][9] = 60,
[0][0][0][0][RTW89_MKK][9] = 68,
@@ -28842,6 +31862,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][0][0][RTW89_ACMA][9] = 60,
[0][0][0][0][RTW89_CN][9] = 58,
[0][0][0][0][RTW89_UK][9] = 60,
+ [0][0][0][0][RTW89_MEXICO][9] = 76,
+ [0][0][0][0][RTW89_UKRAINE][9] = 60,
+ [0][0][0][0][RTW89_CHILE][9] = 76,
+ [0][0][0][0][RTW89_QATAR][9] = 60,
[0][0][0][0][RTW89_FCC][10] = 76,
[0][0][0][0][RTW89_ETSI][10] = 60,
[0][0][0][0][RTW89_MKK][10] = 68,
@@ -28850,6 +31874,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][0][0][RTW89_ACMA][10] = 60,
[0][0][0][0][RTW89_CN][10] = 58,
[0][0][0][0][RTW89_UK][10] = 60,
+ [0][0][0][0][RTW89_MEXICO][10] = 76,
+ [0][0][0][0][RTW89_UKRAINE][10] = 60,
+ [0][0][0][0][RTW89_CHILE][10] = 76,
+ [0][0][0][0][RTW89_QATAR][10] = 60,
[0][0][0][0][RTW89_FCC][11] = 58,
[0][0][0][0][RTW89_ETSI][11] = 60,
[0][0][0][0][RTW89_MKK][11] = 68,
@@ -28858,6 +31886,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][0][0][RTW89_ACMA][11] = 60,
[0][0][0][0][RTW89_CN][11] = 58,
[0][0][0][0][RTW89_UK][11] = 60,
+ [0][0][0][0][RTW89_MEXICO][11] = 58,
+ [0][0][0][0][RTW89_UKRAINE][11] = 60,
+ [0][0][0][0][RTW89_CHILE][11] = 58,
+ [0][0][0][0][RTW89_QATAR][11] = 60,
[0][0][0][0][RTW89_FCC][12] = 46,
[0][0][0][0][RTW89_ETSI][12] = 60,
[0][0][0][0][RTW89_MKK][12] = 68,
@@ -28866,6 +31898,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][0][0][RTW89_ACMA][12] = 60,
[0][0][0][0][RTW89_CN][12] = 58,
[0][0][0][0][RTW89_UK][12] = 60,
+ [0][0][0][0][RTW89_MEXICO][12] = 46,
+ [0][0][0][0][RTW89_UKRAINE][12] = 60,
+ [0][0][0][0][RTW89_CHILE][12] = 46,
+ [0][0][0][0][RTW89_QATAR][12] = 60,
[0][0][0][0][RTW89_FCC][13] = 127,
[0][0][0][0][RTW89_ETSI][13] = 127,
[0][0][0][0][RTW89_MKK][13] = 72,
@@ -28874,6 +31910,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][0][0][RTW89_ACMA][13] = 127,
[0][0][0][0][RTW89_CN][13] = 127,
[0][0][0][0][RTW89_UK][13] = 127,
+ [0][0][0][0][RTW89_MEXICO][13] = 127,
+ [0][0][0][0][RTW89_UKRAINE][13] = 127,
+ [0][0][0][0][RTW89_CHILE][13] = 127,
+ [0][0][0][0][RTW89_QATAR][13] = 127,
[0][1][0][0][RTW89_FCC][0] = 76,
[0][1][0][0][RTW89_ETSI][0] = 48,
[0][1][0][0][RTW89_MKK][0] = 58,
@@ -28882,6 +31922,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][0][0][RTW89_ACMA][0] = 48,
[0][1][0][0][RTW89_CN][0] = 42,
[0][1][0][0][RTW89_UK][0] = 48,
+ [0][1][0][0][RTW89_MEXICO][0] = 76,
+ [0][1][0][0][RTW89_UKRAINE][0] = 48,
+ [0][1][0][0][RTW89_CHILE][0] = 76,
+ [0][1][0][0][RTW89_QATAR][0] = 48,
[0][1][0][0][RTW89_FCC][1] = 76,
[0][1][0][0][RTW89_ETSI][1] = 48,
[0][1][0][0][RTW89_MKK][1] = 58,
@@ -28890,6 +31934,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][0][0][RTW89_ACMA][1] = 48,
[0][1][0][0][RTW89_CN][1] = 42,
[0][1][0][0][RTW89_UK][1] = 48,
+ [0][1][0][0][RTW89_MEXICO][1] = 76,
+ [0][1][0][0][RTW89_UKRAINE][1] = 48,
+ [0][1][0][0][RTW89_CHILE][1] = 54,
+ [0][1][0][0][RTW89_QATAR][1] = 48,
[0][1][0][0][RTW89_FCC][2] = 76,
[0][1][0][0][RTW89_ETSI][2] = 48,
[0][1][0][0][RTW89_MKK][2] = 58,
@@ -28898,6 +31946,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][0][0][RTW89_ACMA][2] = 48,
[0][1][0][0][RTW89_CN][2] = 42,
[0][1][0][0][RTW89_UK][2] = 48,
+ [0][1][0][0][RTW89_MEXICO][2] = 76,
+ [0][1][0][0][RTW89_UKRAINE][2] = 48,
+ [0][1][0][0][RTW89_CHILE][2] = 54,
+ [0][1][0][0][RTW89_QATAR][2] = 48,
[0][1][0][0][RTW89_FCC][3] = 76,
[0][1][0][0][RTW89_ETSI][3] = 48,
[0][1][0][0][RTW89_MKK][3] = 58,
@@ -28906,6 +31958,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][0][0][RTW89_ACMA][3] = 48,
[0][1][0][0][RTW89_CN][3] = 42,
[0][1][0][0][RTW89_UK][3] = 48,
+ [0][1][0][0][RTW89_MEXICO][3] = 76,
+ [0][1][0][0][RTW89_UKRAINE][3] = 48,
+ [0][1][0][0][RTW89_CHILE][3] = 54,
+ [0][1][0][0][RTW89_QATAR][3] = 48,
[0][1][0][0][RTW89_FCC][4] = 76,
[0][1][0][0][RTW89_ETSI][4] = 48,
[0][1][0][0][RTW89_MKK][4] = 58,
@@ -28914,6 +31970,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][0][0][RTW89_ACMA][4] = 48,
[0][1][0][0][RTW89_CN][4] = 42,
[0][1][0][0][RTW89_UK][4] = 48,
+ [0][1][0][0][RTW89_MEXICO][4] = 76,
+ [0][1][0][0][RTW89_UKRAINE][4] = 48,
+ [0][1][0][0][RTW89_CHILE][4] = 54,
+ [0][1][0][0][RTW89_QATAR][4] = 48,
[0][1][0][0][RTW89_FCC][5] = 76,
[0][1][0][0][RTW89_ETSI][5] = 48,
[0][1][0][0][RTW89_MKK][5] = 58,
@@ -28922,6 +31982,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][0][0][RTW89_ACMA][5] = 48,
[0][1][0][0][RTW89_CN][5] = 42,
[0][1][0][0][RTW89_UK][5] = 48,
+ [0][1][0][0][RTW89_MEXICO][5] = 76,
+ [0][1][0][0][RTW89_UKRAINE][5] = 48,
+ [0][1][0][0][RTW89_CHILE][5] = 76,
+ [0][1][0][0][RTW89_QATAR][5] = 48,
[0][1][0][0][RTW89_FCC][6] = 76,
[0][1][0][0][RTW89_ETSI][6] = 48,
[0][1][0][0][RTW89_MKK][6] = 58,
@@ -28930,6 +31994,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][0][0][RTW89_ACMA][6] = 48,
[0][1][0][0][RTW89_CN][6] = 42,
[0][1][0][0][RTW89_UK][6] = 48,
+ [0][1][0][0][RTW89_MEXICO][6] = 76,
+ [0][1][0][0][RTW89_UKRAINE][6] = 48,
+ [0][1][0][0][RTW89_CHILE][6] = 76,
+ [0][1][0][0][RTW89_QATAR][6] = 48,
[0][1][0][0][RTW89_FCC][7] = 76,
[0][1][0][0][RTW89_ETSI][7] = 48,
[0][1][0][0][RTW89_MKK][7] = 58,
@@ -28938,6 +32006,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][0][0][RTW89_ACMA][7] = 48,
[0][1][0][0][RTW89_CN][7] = 42,
[0][1][0][0][RTW89_UK][7] = 48,
+ [0][1][0][0][RTW89_MEXICO][7] = 76,
+ [0][1][0][0][RTW89_UKRAINE][7] = 48,
+ [0][1][0][0][RTW89_CHILE][7] = 76,
+ [0][1][0][0][RTW89_QATAR][7] = 48,
[0][1][0][0][RTW89_FCC][8] = 76,
[0][1][0][0][RTW89_ETSI][8] = 48,
[0][1][0][0][RTW89_MKK][8] = 58,
@@ -28946,6 +32018,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][0][0][RTW89_ACMA][8] = 48,
[0][1][0][0][RTW89_CN][8] = 42,
[0][1][0][0][RTW89_UK][8] = 48,
+ [0][1][0][0][RTW89_MEXICO][8] = 76,
+ [0][1][0][0][RTW89_UKRAINE][8] = 48,
+ [0][1][0][0][RTW89_CHILE][8] = 76,
+ [0][1][0][0][RTW89_QATAR][8] = 48,
[0][1][0][0][RTW89_FCC][9] = 70,
[0][1][0][0][RTW89_ETSI][9] = 48,
[0][1][0][0][RTW89_MKK][9] = 58,
@@ -28954,6 +32030,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][0][0][RTW89_ACMA][9] = 48,
[0][1][0][0][RTW89_CN][9] = 42,
[0][1][0][0][RTW89_UK][9] = 48,
+ [0][1][0][0][RTW89_MEXICO][9] = 70,
+ [0][1][0][0][RTW89_UKRAINE][9] = 48,
+ [0][1][0][0][RTW89_CHILE][9] = 70,
+ [0][1][0][0][RTW89_QATAR][9] = 48,
[0][1][0][0][RTW89_FCC][10] = 72,
[0][1][0][0][RTW89_ETSI][10] = 48,
[0][1][0][0][RTW89_MKK][10] = 58,
@@ -28962,6 +32042,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][0][0][RTW89_ACMA][10] = 48,
[0][1][0][0][RTW89_CN][10] = 42,
[0][1][0][0][RTW89_UK][10] = 48,
+ [0][1][0][0][RTW89_MEXICO][10] = 72,
+ [0][1][0][0][RTW89_UKRAINE][10] = 48,
+ [0][1][0][0][RTW89_CHILE][10] = 72,
+ [0][1][0][0][RTW89_QATAR][10] = 48,
[0][1][0][0][RTW89_FCC][11] = 44,
[0][1][0][0][RTW89_ETSI][11] = 48,
[0][1][0][0][RTW89_MKK][11] = 58,
@@ -28970,6 +32054,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][0][0][RTW89_ACMA][11] = 48,
[0][1][0][0][RTW89_CN][11] = 42,
[0][1][0][0][RTW89_UK][11] = 48,
+ [0][1][0][0][RTW89_MEXICO][11] = 44,
+ [0][1][0][0][RTW89_UKRAINE][11] = 48,
+ [0][1][0][0][RTW89_CHILE][11] = 44,
+ [0][1][0][0][RTW89_QATAR][11] = 48,
[0][1][0][0][RTW89_FCC][12] = 18,
[0][1][0][0][RTW89_ETSI][12] = 48,
[0][1][0][0][RTW89_MKK][12] = 58,
@@ -28978,6 +32066,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][0][0][RTW89_ACMA][12] = 48,
[0][1][0][0][RTW89_CN][12] = 42,
[0][1][0][0][RTW89_UK][12] = 48,
+ [0][1][0][0][RTW89_MEXICO][12] = 18,
+ [0][1][0][0][RTW89_UKRAINE][12] = 48,
+ [0][1][0][0][RTW89_CHILE][12] = 18,
+ [0][1][0][0][RTW89_QATAR][12] = 48,
[0][1][0][0][RTW89_FCC][13] = 127,
[0][1][0][0][RTW89_ETSI][13] = 127,
[0][1][0][0][RTW89_MKK][13] = 60,
@@ -28986,6 +32078,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][0][0][RTW89_ACMA][13] = 127,
[0][1][0][0][RTW89_CN][13] = 127,
[0][1][0][0][RTW89_UK][13] = 127,
+ [0][1][0][0][RTW89_MEXICO][13] = 127,
+ [0][1][0][0][RTW89_UKRAINE][13] = 127,
+ [0][1][0][0][RTW89_CHILE][13] = 127,
+ [0][1][0][0][RTW89_QATAR][13] = 127,
[1][0][0][0][RTW89_FCC][0] = 127,
[1][0][0][0][RTW89_ETSI][0] = 127,
[1][0][0][0][RTW89_MKK][0] = 127,
@@ -28994,6 +32090,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][0][0][0][RTW89_ACMA][0] = 127,
[1][0][0][0][RTW89_CN][0] = 127,
[1][0][0][0][RTW89_UK][0] = 127,
+ [1][0][0][0][RTW89_MEXICO][0] = 127,
+ [1][0][0][0][RTW89_UKRAINE][0] = 127,
+ [1][0][0][0][RTW89_CHILE][0] = 127,
+ [1][0][0][0][RTW89_QATAR][0] = 127,
[1][0][0][0][RTW89_FCC][1] = 127,
[1][0][0][0][RTW89_ETSI][1] = 127,
[1][0][0][0][RTW89_MKK][1] = 127,
@@ -29002,6 +32102,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][0][0][0][RTW89_ACMA][1] = 127,
[1][0][0][0][RTW89_CN][1] = 127,
[1][0][0][0][RTW89_UK][1] = 127,
+ [1][0][0][0][RTW89_MEXICO][1] = 127,
+ [1][0][0][0][RTW89_UKRAINE][1] = 127,
+ [1][0][0][0][RTW89_CHILE][1] = 127,
+ [1][0][0][0][RTW89_QATAR][1] = 127,
[1][0][0][0][RTW89_FCC][2] = 44,
[1][0][0][0][RTW89_ETSI][2] = 60,
[1][0][0][0][RTW89_MKK][2] = 66,
@@ -29010,6 +32114,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][0][0][0][RTW89_ACMA][2] = 60,
[1][0][0][0][RTW89_CN][2] = 58,
[1][0][0][0][RTW89_UK][2] = 60,
+ [1][0][0][0][RTW89_MEXICO][2] = 44,
+ [1][0][0][0][RTW89_UKRAINE][2] = 60,
+ [1][0][0][0][RTW89_CHILE][2] = 44,
+ [1][0][0][0][RTW89_QATAR][2] = 60,
[1][0][0][0][RTW89_FCC][3] = 60,
[1][0][0][0][RTW89_ETSI][3] = 60,
[1][0][0][0][RTW89_MKK][3] = 66,
@@ -29018,6 +32126,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][0][0][0][RTW89_ACMA][3] = 60,
[1][0][0][0][RTW89_CN][3] = 58,
[1][0][0][0][RTW89_UK][3] = 60,
+ [1][0][0][0][RTW89_MEXICO][3] = 60,
+ [1][0][0][0][RTW89_UKRAINE][3] = 60,
+ [1][0][0][0][RTW89_CHILE][3] = 60,
+ [1][0][0][0][RTW89_QATAR][3] = 60,
[1][0][0][0][RTW89_FCC][4] = 60,
[1][0][0][0][RTW89_ETSI][4] = 60,
[1][0][0][0][RTW89_MKK][4] = 66,
@@ -29026,6 +32138,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][0][0][0][RTW89_ACMA][4] = 60,
[1][0][0][0][RTW89_CN][4] = 58,
[1][0][0][0][RTW89_UK][4] = 60,
+ [1][0][0][0][RTW89_MEXICO][4] = 60,
+ [1][0][0][0][RTW89_UKRAINE][4] = 60,
+ [1][0][0][0][RTW89_CHILE][4] = 60,
+ [1][0][0][0][RTW89_QATAR][4] = 60,
[1][0][0][0][RTW89_FCC][5] = 62,
[1][0][0][0][RTW89_ETSI][5] = 60,
[1][0][0][0][RTW89_MKK][5] = 66,
@@ -29034,6 +32150,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][0][0][0][RTW89_ACMA][5] = 60,
[1][0][0][0][RTW89_CN][5] = 58,
[1][0][0][0][RTW89_UK][5] = 60,
+ [1][0][0][0][RTW89_MEXICO][5] = 62,
+ [1][0][0][0][RTW89_UKRAINE][5] = 60,
+ [1][0][0][0][RTW89_CHILE][5] = 62,
+ [1][0][0][0][RTW89_QATAR][5] = 60,
[1][0][0][0][RTW89_FCC][6] = 46,
[1][0][0][0][RTW89_ETSI][6] = 60,
[1][0][0][0][RTW89_MKK][6] = 66,
@@ -29042,6 +32162,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][0][0][0][RTW89_ACMA][6] = 60,
[1][0][0][0][RTW89_CN][6] = 58,
[1][0][0][0][RTW89_UK][6] = 60,
+ [1][0][0][0][RTW89_MEXICO][6] = 46,
+ [1][0][0][0][RTW89_UKRAINE][6] = 60,
+ [1][0][0][0][RTW89_CHILE][6] = 46,
+ [1][0][0][0][RTW89_QATAR][6] = 60,
[1][0][0][0][RTW89_FCC][7] = 46,
[1][0][0][0][RTW89_ETSI][7] = 60,
[1][0][0][0][RTW89_MKK][7] = 66,
@@ -29050,6 +32174,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][0][0][0][RTW89_ACMA][7] = 60,
[1][0][0][0][RTW89_CN][7] = 58,
[1][0][0][0][RTW89_UK][7] = 60,
+ [1][0][0][0][RTW89_MEXICO][7] = 46,
+ [1][0][0][0][RTW89_UKRAINE][7] = 60,
+ [1][0][0][0][RTW89_CHILE][7] = 46,
+ [1][0][0][0][RTW89_QATAR][7] = 60,
[1][0][0][0][RTW89_FCC][8] = 28,
[1][0][0][0][RTW89_ETSI][8] = 60,
[1][0][0][0][RTW89_MKK][8] = 66,
@@ -29058,6 +32186,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][0][0][0][RTW89_ACMA][8] = 60,
[1][0][0][0][RTW89_CN][8] = 58,
[1][0][0][0][RTW89_UK][8] = 60,
+ [1][0][0][0][RTW89_MEXICO][8] = 28,
+ [1][0][0][0][RTW89_UKRAINE][8] = 60,
+ [1][0][0][0][RTW89_CHILE][8] = 28,
+ [1][0][0][0][RTW89_QATAR][8] = 60,
[1][0][0][0][RTW89_FCC][9] = 26,
[1][0][0][0][RTW89_ETSI][9] = 60,
[1][0][0][0][RTW89_MKK][9] = 66,
@@ -29066,6 +32198,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][0][0][0][RTW89_ACMA][9] = 60,
[1][0][0][0][RTW89_CN][9] = 58,
[1][0][0][0][RTW89_UK][9] = 60,
+ [1][0][0][0][RTW89_MEXICO][9] = 26,
+ [1][0][0][0][RTW89_UKRAINE][9] = 60,
+ [1][0][0][0][RTW89_CHILE][9] = 26,
+ [1][0][0][0][RTW89_QATAR][9] = 60,
[1][0][0][0][RTW89_FCC][10] = 26,
[1][0][0][0][RTW89_ETSI][10] = 60,
[1][0][0][0][RTW89_MKK][10] = 66,
@@ -29074,6 +32210,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][0][0][0][RTW89_ACMA][10] = 60,
[1][0][0][0][RTW89_CN][10] = 58,
[1][0][0][0][RTW89_UK][10] = 60,
+ [1][0][0][0][RTW89_MEXICO][10] = 26,
+ [1][0][0][0][RTW89_UKRAINE][10] = 60,
+ [1][0][0][0][RTW89_CHILE][10] = 26,
+ [1][0][0][0][RTW89_QATAR][10] = 60,
[1][0][0][0][RTW89_FCC][11] = 127,
[1][0][0][0][RTW89_ETSI][11] = 127,
[1][0][0][0][RTW89_MKK][11] = 127,
@@ -29082,6 +32222,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][0][0][0][RTW89_ACMA][11] = 127,
[1][0][0][0][RTW89_CN][11] = 127,
[1][0][0][0][RTW89_UK][11] = 127,
+ [1][0][0][0][RTW89_MEXICO][11] = 127,
+ [1][0][0][0][RTW89_UKRAINE][11] = 127,
+ [1][0][0][0][RTW89_CHILE][11] = 127,
+ [1][0][0][0][RTW89_QATAR][11] = 127,
[1][0][0][0][RTW89_FCC][12] = 127,
[1][0][0][0][RTW89_ETSI][12] = 127,
[1][0][0][0][RTW89_MKK][12] = 127,
@@ -29090,6 +32234,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][0][0][0][RTW89_ACMA][12] = 127,
[1][0][0][0][RTW89_CN][12] = 127,
[1][0][0][0][RTW89_UK][12] = 127,
+ [1][0][0][0][RTW89_MEXICO][12] = 127,
+ [1][0][0][0][RTW89_UKRAINE][12] = 127,
+ [1][0][0][0][RTW89_CHILE][12] = 127,
+ [1][0][0][0][RTW89_QATAR][12] = 127,
[1][0][0][0][RTW89_FCC][13] = 127,
[1][0][0][0][RTW89_ETSI][13] = 127,
[1][0][0][0][RTW89_MKK][13] = 127,
@@ -29098,6 +32246,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][0][0][0][RTW89_ACMA][13] = 127,
[1][0][0][0][RTW89_CN][13] = 127,
[1][0][0][0][RTW89_UK][13] = 127,
+ [1][0][0][0][RTW89_MEXICO][13] = 127,
+ [1][0][0][0][RTW89_UKRAINE][13] = 127,
+ [1][0][0][0][RTW89_CHILE][13] = 127,
+ [1][0][0][0][RTW89_QATAR][13] = 127,
[1][1][0][0][RTW89_FCC][0] = 127,
[1][1][0][0][RTW89_ETSI][0] = 127,
[1][1][0][0][RTW89_MKK][0] = 127,
@@ -29106,6 +32258,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][0][0][RTW89_ACMA][0] = 127,
[1][1][0][0][RTW89_CN][0] = 127,
[1][1][0][0][RTW89_UK][0] = 127,
+ [1][1][0][0][RTW89_MEXICO][0] = 127,
+ [1][1][0][0][RTW89_UKRAINE][0] = 127,
+ [1][1][0][0][RTW89_CHILE][0] = 127,
+ [1][1][0][0][RTW89_QATAR][0] = 127,
[1][1][0][0][RTW89_FCC][1] = 127,
[1][1][0][0][RTW89_ETSI][1] = 127,
[1][1][0][0][RTW89_MKK][1] = 127,
@@ -29114,6 +32270,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][0][0][RTW89_ACMA][1] = 127,
[1][1][0][0][RTW89_CN][1] = 127,
[1][1][0][0][RTW89_UK][1] = 127,
+ [1][1][0][0][RTW89_MEXICO][1] = 127,
+ [1][1][0][0][RTW89_UKRAINE][1] = 127,
+ [1][1][0][0][RTW89_CHILE][1] = 127,
+ [1][1][0][0][RTW89_QATAR][1] = 127,
[1][1][0][0][RTW89_FCC][2] = 46,
[1][1][0][0][RTW89_ETSI][2] = 48,
[1][1][0][0][RTW89_MKK][2] = 58,
@@ -29122,6 +32282,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][0][0][RTW89_ACMA][2] = 48,
[1][1][0][0][RTW89_CN][2] = 46,
[1][1][0][0][RTW89_UK][2] = 48,
+ [1][1][0][0][RTW89_MEXICO][2] = 46,
+ [1][1][0][0][RTW89_UKRAINE][2] = 48,
+ [1][1][0][0][RTW89_CHILE][2] = 46,
+ [1][1][0][0][RTW89_QATAR][2] = 48,
[1][1][0][0][RTW89_FCC][3] = 46,
[1][1][0][0][RTW89_ETSI][3] = 48,
[1][1][0][0][RTW89_MKK][3] = 58,
@@ -29130,6 +32294,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][0][0][RTW89_ACMA][3] = 48,
[1][1][0][0][RTW89_CN][3] = 46,
[1][1][0][0][RTW89_UK][3] = 48,
+ [1][1][0][0][RTW89_MEXICO][3] = 46,
+ [1][1][0][0][RTW89_UKRAINE][3] = 48,
+ [1][1][0][0][RTW89_CHILE][3] = 46,
+ [1][1][0][0][RTW89_QATAR][3] = 48,
[1][1][0][0][RTW89_FCC][4] = 46,
[1][1][0][0][RTW89_ETSI][4] = 48,
[1][1][0][0][RTW89_MKK][4] = 58,
@@ -29138,6 +32306,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][0][0][RTW89_ACMA][4] = 48,
[1][1][0][0][RTW89_CN][4] = 46,
[1][1][0][0][RTW89_UK][4] = 48,
+ [1][1][0][0][RTW89_MEXICO][4] = 46,
+ [1][1][0][0][RTW89_UKRAINE][4] = 48,
+ [1][1][0][0][RTW89_CHILE][4] = 46,
+ [1][1][0][0][RTW89_QATAR][4] = 48,
[1][1][0][0][RTW89_FCC][5] = 48,
[1][1][0][0][RTW89_ETSI][5] = 48,
[1][1][0][0][RTW89_MKK][5] = 58,
@@ -29146,6 +32318,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][0][0][RTW89_ACMA][5] = 48,
[1][1][0][0][RTW89_CN][5] = 46,
[1][1][0][0][RTW89_UK][5] = 48,
+ [1][1][0][0][RTW89_MEXICO][5] = 48,
+ [1][1][0][0][RTW89_UKRAINE][5] = 48,
+ [1][1][0][0][RTW89_CHILE][5] = 48,
+ [1][1][0][0][RTW89_QATAR][5] = 48,
[1][1][0][0][RTW89_FCC][6] = 40,
[1][1][0][0][RTW89_ETSI][6] = 48,
[1][1][0][0][RTW89_MKK][6] = 58,
@@ -29154,6 +32330,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][0][0][RTW89_ACMA][6] = 48,
[1][1][0][0][RTW89_CN][6] = 46,
[1][1][0][0][RTW89_UK][6] = 48,
+ [1][1][0][0][RTW89_MEXICO][6] = 40,
+ [1][1][0][0][RTW89_UKRAINE][6] = 48,
+ [1][1][0][0][RTW89_CHILE][6] = 40,
+ [1][1][0][0][RTW89_QATAR][6] = 48,
[1][1][0][0][RTW89_FCC][7] = 40,
[1][1][0][0][RTW89_ETSI][7] = 48,
[1][1][0][0][RTW89_MKK][7] = 58,
@@ -29162,6 +32342,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][0][0][RTW89_ACMA][7] = 48,
[1][1][0][0][RTW89_CN][7] = 46,
[1][1][0][0][RTW89_UK][7] = 48,
+ [1][1][0][0][RTW89_MEXICO][7] = 40,
+ [1][1][0][0][RTW89_UKRAINE][7] = 48,
+ [1][1][0][0][RTW89_CHILE][7] = 40,
+ [1][1][0][0][RTW89_QATAR][7] = 48,
[1][1][0][0][RTW89_FCC][8] = 14,
[1][1][0][0][RTW89_ETSI][8] = 48,
[1][1][0][0][RTW89_MKK][8] = 58,
@@ -29170,6 +32354,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][0][0][RTW89_ACMA][8] = 48,
[1][1][0][0][RTW89_CN][8] = 46,
[1][1][0][0][RTW89_UK][8] = 48,
+ [1][1][0][0][RTW89_MEXICO][8] = 14,
+ [1][1][0][0][RTW89_UKRAINE][8] = 48,
+ [1][1][0][0][RTW89_CHILE][8] = 14,
+ [1][1][0][0][RTW89_QATAR][8] = 48,
[1][1][0][0][RTW89_FCC][9] = 14,
[1][1][0][0][RTW89_ETSI][9] = 48,
[1][1][0][0][RTW89_MKK][9] = 58,
@@ -29178,6 +32366,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][0][0][RTW89_ACMA][9] = 48,
[1][1][0][0][RTW89_CN][9] = 46,
[1][1][0][0][RTW89_UK][9] = 48,
+ [1][1][0][0][RTW89_MEXICO][9] = 14,
+ [1][1][0][0][RTW89_UKRAINE][9] = 48,
+ [1][1][0][0][RTW89_CHILE][9] = 14,
+ [1][1][0][0][RTW89_QATAR][9] = 48,
[1][1][0][0][RTW89_FCC][10] = 12,
[1][1][0][0][RTW89_ETSI][10] = 48,
[1][1][0][0][RTW89_MKK][10] = 56,
@@ -29186,6 +32378,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][0][0][RTW89_ACMA][10] = 48,
[1][1][0][0][RTW89_CN][10] = 46,
[1][1][0][0][RTW89_UK][10] = 48,
+ [1][1][0][0][RTW89_MEXICO][10] = 12,
+ [1][1][0][0][RTW89_UKRAINE][10] = 48,
+ [1][1][0][0][RTW89_CHILE][10] = 12,
+ [1][1][0][0][RTW89_QATAR][10] = 48,
[1][1][0][0][RTW89_FCC][11] = 127,
[1][1][0][0][RTW89_ETSI][11] = 127,
[1][1][0][0][RTW89_MKK][11] = 127,
@@ -29194,6 +32390,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][0][0][RTW89_ACMA][11] = 127,
[1][1][0][0][RTW89_CN][11] = 127,
[1][1][0][0][RTW89_UK][11] = 127,
+ [1][1][0][0][RTW89_MEXICO][11] = 127,
+ [1][1][0][0][RTW89_UKRAINE][11] = 127,
+ [1][1][0][0][RTW89_CHILE][11] = 127,
+ [1][1][0][0][RTW89_QATAR][11] = 127,
[1][1][0][0][RTW89_FCC][12] = 127,
[1][1][0][0][RTW89_ETSI][12] = 127,
[1][1][0][0][RTW89_MKK][12] = 127,
@@ -29202,6 +32402,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][0][0][RTW89_ACMA][12] = 127,
[1][1][0][0][RTW89_CN][12] = 127,
[1][1][0][0][RTW89_UK][12] = 127,
+ [1][1][0][0][RTW89_MEXICO][12] = 127,
+ [1][1][0][0][RTW89_UKRAINE][12] = 127,
+ [1][1][0][0][RTW89_CHILE][12] = 127,
+ [1][1][0][0][RTW89_QATAR][12] = 127,
[1][1][0][0][RTW89_FCC][13] = 127,
[1][1][0][0][RTW89_ETSI][13] = 127,
[1][1][0][0][RTW89_MKK][13] = 127,
@@ -29210,6 +32414,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][0][0][RTW89_ACMA][13] = 127,
[1][1][0][0][RTW89_CN][13] = 127,
[1][1][0][0][RTW89_UK][13] = 127,
+ [1][1][0][0][RTW89_MEXICO][13] = 127,
+ [1][1][0][0][RTW89_UKRAINE][13] = 127,
+ [1][1][0][0][RTW89_CHILE][13] = 127,
+ [1][1][0][0][RTW89_QATAR][13] = 127,
[0][0][1][0][RTW89_FCC][0] = 66,
[0][0][1][0][RTW89_ETSI][0] = 60,
[0][0][1][0][RTW89_MKK][0] = 76,
@@ -29218,6 +32426,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][0] = 60,
[0][0][1][0][RTW89_CN][0] = 58,
[0][0][1][0][RTW89_UK][0] = 60,
+ [0][0][1][0][RTW89_MEXICO][0] = 66,
+ [0][0][1][0][RTW89_UKRAINE][0] = 60,
+ [0][0][1][0][RTW89_CHILE][0] = 66,
+ [0][0][1][0][RTW89_QATAR][0] = 60,
[0][0][1][0][RTW89_FCC][1] = 68,
[0][0][1][0][RTW89_ETSI][1] = 60,
[0][0][1][0][RTW89_MKK][1] = 78,
@@ -29226,6 +32438,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][1] = 60,
[0][0][1][0][RTW89_CN][1] = 58,
[0][0][1][0][RTW89_UK][1] = 60,
+ [0][0][1][0][RTW89_MEXICO][1] = 68,
+ [0][0][1][0][RTW89_UKRAINE][1] = 60,
+ [0][0][1][0][RTW89_CHILE][1] = 68,
+ [0][0][1][0][RTW89_QATAR][1] = 60,
[0][0][1][0][RTW89_FCC][2] = 72,
[0][0][1][0][RTW89_ETSI][2] = 60,
[0][0][1][0][RTW89_MKK][2] = 78,
@@ -29234,6 +32450,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][2] = 60,
[0][0][1][0][RTW89_CN][2] = 58,
[0][0][1][0][RTW89_UK][2] = 60,
+ [0][0][1][0][RTW89_MEXICO][2] = 72,
+ [0][0][1][0][RTW89_UKRAINE][2] = 60,
+ [0][0][1][0][RTW89_CHILE][2] = 62,
+ [0][0][1][0][RTW89_QATAR][2] = 60,
[0][0][1][0][RTW89_FCC][3] = 76,
[0][0][1][0][RTW89_ETSI][3] = 60,
[0][0][1][0][RTW89_MKK][3] = 78,
@@ -29242,6 +32462,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][3] = 60,
[0][0][1][0][RTW89_CN][3] = 58,
[0][0][1][0][RTW89_UK][3] = 60,
+ [0][0][1][0][RTW89_MEXICO][3] = 76,
+ [0][0][1][0][RTW89_UKRAINE][3] = 60,
+ [0][0][1][0][RTW89_CHILE][3] = 62,
+ [0][0][1][0][RTW89_QATAR][3] = 60,
[0][0][1][0][RTW89_FCC][4] = 80,
[0][0][1][0][RTW89_ETSI][4] = 60,
[0][0][1][0][RTW89_MKK][4] = 78,
@@ -29250,6 +32474,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][4] = 60,
[0][0][1][0][RTW89_CN][4] = 58,
[0][0][1][0][RTW89_UK][4] = 60,
+ [0][0][1][0][RTW89_MEXICO][4] = 80,
+ [0][0][1][0][RTW89_UKRAINE][4] = 60,
+ [0][0][1][0][RTW89_CHILE][4] = 62,
+ [0][0][1][0][RTW89_QATAR][4] = 60,
[0][0][1][0][RTW89_FCC][5] = 80,
[0][0][1][0][RTW89_ETSI][5] = 60,
[0][0][1][0][RTW89_MKK][5] = 78,
@@ -29258,6 +32486,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][5] = 60,
[0][0][1][0][RTW89_CN][5] = 58,
[0][0][1][0][RTW89_UK][5] = 60,
+ [0][0][1][0][RTW89_MEXICO][5] = 80,
+ [0][0][1][0][RTW89_UKRAINE][5] = 60,
+ [0][0][1][0][RTW89_CHILE][5] = 80,
+ [0][0][1][0][RTW89_QATAR][5] = 60,
[0][0][1][0][RTW89_FCC][6] = 80,
[0][0][1][0][RTW89_ETSI][6] = 60,
[0][0][1][0][RTW89_MKK][6] = 76,
@@ -29266,6 +32498,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][6] = 60,
[0][0][1][0][RTW89_CN][6] = 58,
[0][0][1][0][RTW89_UK][6] = 60,
+ [0][0][1][0][RTW89_MEXICO][6] = 80,
+ [0][0][1][0][RTW89_UKRAINE][6] = 60,
+ [0][0][1][0][RTW89_CHILE][6] = 70,
+ [0][0][1][0][RTW89_QATAR][6] = 60,
[0][0][1][0][RTW89_FCC][7] = 80,
[0][0][1][0][RTW89_ETSI][7] = 60,
[0][0][1][0][RTW89_MKK][7] = 78,
@@ -29274,6 +32510,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][7] = 60,
[0][0][1][0][RTW89_CN][7] = 58,
[0][0][1][0][RTW89_UK][7] = 60,
+ [0][0][1][0][RTW89_MEXICO][7] = 80,
+ [0][0][1][0][RTW89_UKRAINE][7] = 60,
+ [0][0][1][0][RTW89_CHILE][7] = 70,
+ [0][0][1][0][RTW89_QATAR][7] = 60,
[0][0][1][0][RTW89_FCC][8] = 80,
[0][0][1][0][RTW89_ETSI][8] = 60,
[0][0][1][0][RTW89_MKK][8] = 78,
@@ -29282,6 +32522,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][8] = 60,
[0][0][1][0][RTW89_CN][8] = 58,
[0][0][1][0][RTW89_UK][8] = 60,
+ [0][0][1][0][RTW89_MEXICO][8] = 80,
+ [0][0][1][0][RTW89_UKRAINE][8] = 60,
+ [0][0][1][0][RTW89_CHILE][8] = 70,
+ [0][0][1][0][RTW89_QATAR][8] = 60,
[0][0][1][0][RTW89_FCC][9] = 76,
[0][0][1][0][RTW89_ETSI][9] = 60,
[0][0][1][0][RTW89_MKK][9] = 78,
@@ -29290,6 +32534,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][9] = 60,
[0][0][1][0][RTW89_CN][9] = 58,
[0][0][1][0][RTW89_UK][9] = 60,
+ [0][0][1][0][RTW89_MEXICO][9] = 76,
+ [0][0][1][0][RTW89_UKRAINE][9] = 60,
+ [0][0][1][0][RTW89_CHILE][9] = 76,
+ [0][0][1][0][RTW89_QATAR][9] = 60,
[0][0][1][0][RTW89_FCC][10] = 66,
[0][0][1][0][RTW89_ETSI][10] = 60,
[0][0][1][0][RTW89_MKK][10] = 78,
@@ -29298,6 +32546,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][10] = 60,
[0][0][1][0][RTW89_CN][10] = 58,
[0][0][1][0][RTW89_UK][10] = 60,
+ [0][0][1][0][RTW89_MEXICO][10] = 66,
+ [0][0][1][0][RTW89_UKRAINE][10] = 60,
+ [0][0][1][0][RTW89_CHILE][10] = 66,
+ [0][0][1][0][RTW89_QATAR][10] = 60,
[0][0][1][0][RTW89_FCC][11] = 62,
[0][0][1][0][RTW89_ETSI][11] = 60,
[0][0][1][0][RTW89_MKK][11] = 78,
@@ -29306,6 +32558,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][11] = 60,
[0][0][1][0][RTW89_CN][11] = 58,
[0][0][1][0][RTW89_UK][11] = 60,
+ [0][0][1][0][RTW89_MEXICO][11] = 62,
+ [0][0][1][0][RTW89_UKRAINE][11] = 60,
+ [0][0][1][0][RTW89_CHILE][11] = 62,
+ [0][0][1][0][RTW89_QATAR][11] = 60,
[0][0][1][0][RTW89_FCC][12] = 60,
[0][0][1][0][RTW89_ETSI][12] = 60,
[0][0][1][0][RTW89_MKK][12] = 78,
@@ -29314,6 +32570,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][12] = 60,
[0][0][1][0][RTW89_CN][12] = 58,
[0][0][1][0][RTW89_UK][12] = 60,
+ [0][0][1][0][RTW89_MEXICO][12] = 60,
+ [0][0][1][0][RTW89_UKRAINE][12] = 60,
+ [0][0][1][0][RTW89_CHILE][12] = 60,
+ [0][0][1][0][RTW89_QATAR][12] = 60,
[0][0][1][0][RTW89_FCC][13] = 127,
[0][0][1][0][RTW89_ETSI][13] = 127,
[0][0][1][0][RTW89_MKK][13] = 127,
@@ -29322,6 +32582,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][13] = 127,
[0][0][1][0][RTW89_CN][13] = 127,
[0][0][1][0][RTW89_UK][13] = 127,
+ [0][0][1][0][RTW89_MEXICO][13] = 127,
+ [0][0][1][0][RTW89_UKRAINE][13] = 127,
+ [0][0][1][0][RTW89_CHILE][13] = 127,
+ [0][0][1][0][RTW89_QATAR][13] = 127,
[0][1][1][0][RTW89_FCC][0] = 66,
[0][1][1][0][RTW89_ETSI][0] = 48,
[0][1][1][0][RTW89_MKK][0] = 66,
@@ -29330,6 +32594,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][0] = 48,
[0][1][1][0][RTW89_CN][0] = 46,
[0][1][1][0][RTW89_UK][0] = 48,
+ [0][1][1][0][RTW89_MEXICO][0] = 66,
+ [0][1][1][0][RTW89_UKRAINE][0] = 48,
+ [0][1][1][0][RTW89_CHILE][0] = 66,
+ [0][1][1][0][RTW89_QATAR][0] = 48,
[0][1][1][0][RTW89_FCC][1] = 68,
[0][1][1][0][RTW89_ETSI][1] = 48,
[0][1][1][0][RTW89_MKK][1] = 66,
@@ -29338,6 +32606,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][1] = 48,
[0][1][1][0][RTW89_CN][1] = 46,
[0][1][1][0][RTW89_UK][1] = 48,
+ [0][1][1][0][RTW89_MEXICO][1] = 68,
+ [0][1][1][0][RTW89_UKRAINE][1] = 48,
+ [0][1][1][0][RTW89_CHILE][1] = 68,
+ [0][1][1][0][RTW89_QATAR][1] = 48,
[0][1][1][0][RTW89_FCC][2] = 72,
[0][1][1][0][RTW89_ETSI][2] = 48,
[0][1][1][0][RTW89_MKK][2] = 66,
@@ -29346,6 +32618,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][2] = 48,
[0][1][1][0][RTW89_CN][2] = 46,
[0][1][1][0][RTW89_UK][2] = 48,
+ [0][1][1][0][RTW89_MEXICO][2] = 72,
+ [0][1][1][0][RTW89_UKRAINE][2] = 48,
+ [0][1][1][0][RTW89_CHILE][2] = 54,
+ [0][1][1][0][RTW89_QATAR][2] = 48,
[0][1][1][0][RTW89_FCC][3] = 76,
[0][1][1][0][RTW89_ETSI][3] = 48,
[0][1][1][0][RTW89_MKK][3] = 66,
@@ -29354,6 +32630,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][3] = 48,
[0][1][1][0][RTW89_CN][3] = 46,
[0][1][1][0][RTW89_UK][3] = 48,
+ [0][1][1][0][RTW89_MEXICO][3] = 76,
+ [0][1][1][0][RTW89_UKRAINE][3] = 48,
+ [0][1][1][0][RTW89_CHILE][3] = 54,
+ [0][1][1][0][RTW89_QATAR][3] = 48,
[0][1][1][0][RTW89_FCC][4] = 80,
[0][1][1][0][RTW89_ETSI][4] = 48,
[0][1][1][0][RTW89_MKK][4] = 66,
@@ -29362,6 +32642,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][4] = 48,
[0][1][1][0][RTW89_CN][4] = 46,
[0][1][1][0][RTW89_UK][4] = 48,
+ [0][1][1][0][RTW89_MEXICO][4] = 80,
+ [0][1][1][0][RTW89_UKRAINE][4] = 48,
+ [0][1][1][0][RTW89_CHILE][4] = 54,
+ [0][1][1][0][RTW89_QATAR][4] = 48,
[0][1][1][0][RTW89_FCC][5] = 80,
[0][1][1][0][RTW89_ETSI][5] = 48,
[0][1][1][0][RTW89_MKK][5] = 66,
@@ -29370,6 +32654,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][5] = 48,
[0][1][1][0][RTW89_CN][5] = 46,
[0][1][1][0][RTW89_UK][5] = 48,
+ [0][1][1][0][RTW89_MEXICO][5] = 80,
+ [0][1][1][0][RTW89_UKRAINE][5] = 48,
+ [0][1][1][0][RTW89_CHILE][5] = 80,
+ [0][1][1][0][RTW89_QATAR][5] = 48,
[0][1][1][0][RTW89_FCC][6] = 80,
[0][1][1][0][RTW89_ETSI][6] = 48,
[0][1][1][0][RTW89_MKK][6] = 66,
@@ -29378,6 +32666,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][6] = 48,
[0][1][1][0][RTW89_CN][6] = 46,
[0][1][1][0][RTW89_UK][6] = 48,
+ [0][1][1][0][RTW89_MEXICO][6] = 80,
+ [0][1][1][0][RTW89_UKRAINE][6] = 48,
+ [0][1][1][0][RTW89_CHILE][6] = 56,
+ [0][1][1][0][RTW89_QATAR][6] = 48,
[0][1][1][0][RTW89_FCC][7] = 78,
[0][1][1][0][RTW89_ETSI][7] = 48,
[0][1][1][0][RTW89_MKK][7] = 66,
@@ -29386,6 +32678,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][7] = 48,
[0][1][1][0][RTW89_CN][7] = 46,
[0][1][1][0][RTW89_UK][7] = 48,
+ [0][1][1][0][RTW89_MEXICO][7] = 78,
+ [0][1][1][0][RTW89_UKRAINE][7] = 48,
+ [0][1][1][0][RTW89_CHILE][7] = 56,
+ [0][1][1][0][RTW89_QATAR][7] = 48,
[0][1][1][0][RTW89_FCC][8] = 74,
[0][1][1][0][RTW89_ETSI][8] = 48,
[0][1][1][0][RTW89_MKK][8] = 66,
@@ -29394,6 +32690,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][8] = 48,
[0][1][1][0][RTW89_CN][8] = 46,
[0][1][1][0][RTW89_UK][8] = 48,
+ [0][1][1][0][RTW89_MEXICO][8] = 74,
+ [0][1][1][0][RTW89_UKRAINE][8] = 48,
+ [0][1][1][0][RTW89_CHILE][8] = 56,
+ [0][1][1][0][RTW89_QATAR][8] = 48,
[0][1][1][0][RTW89_FCC][9] = 70,
[0][1][1][0][RTW89_ETSI][9] = 48,
[0][1][1][0][RTW89_MKK][9] = 66,
@@ -29402,6 +32702,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][9] = 48,
[0][1][1][0][RTW89_CN][9] = 46,
[0][1][1][0][RTW89_UK][9] = 48,
+ [0][1][1][0][RTW89_MEXICO][9] = 70,
+ [0][1][1][0][RTW89_UKRAINE][9] = 48,
+ [0][1][1][0][RTW89_CHILE][9] = 70,
+ [0][1][1][0][RTW89_QATAR][9] = 48,
[0][1][1][0][RTW89_FCC][10] = 62,
[0][1][1][0][RTW89_ETSI][10] = 48,
[0][1][1][0][RTW89_MKK][10] = 66,
@@ -29410,6 +32714,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][10] = 48,
[0][1][1][0][RTW89_CN][10] = 46,
[0][1][1][0][RTW89_UK][10] = 48,
+ [0][1][1][0][RTW89_MEXICO][10] = 62,
+ [0][1][1][0][RTW89_UKRAINE][10] = 48,
+ [0][1][1][0][RTW89_CHILE][10] = 62,
+ [0][1][1][0][RTW89_QATAR][10] = 48,
[0][1][1][0][RTW89_FCC][11] = 60,
[0][1][1][0][RTW89_ETSI][11] = 48,
[0][1][1][0][RTW89_MKK][11] = 66,
@@ -29418,6 +32726,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][11] = 48,
[0][1][1][0][RTW89_CN][11] = 46,
[0][1][1][0][RTW89_UK][11] = 48,
+ [0][1][1][0][RTW89_MEXICO][11] = 60,
+ [0][1][1][0][RTW89_UKRAINE][11] = 48,
+ [0][1][1][0][RTW89_CHILE][11] = 60,
+ [0][1][1][0][RTW89_QATAR][11] = 48,
[0][1][1][0][RTW89_FCC][12] = 36,
[0][1][1][0][RTW89_ETSI][12] = 48,
[0][1][1][0][RTW89_MKK][12] = 66,
@@ -29426,6 +32738,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][12] = 48,
[0][1][1][0][RTW89_CN][12] = 46,
[0][1][1][0][RTW89_UK][12] = 48,
+ [0][1][1][0][RTW89_MEXICO][12] = 36,
+ [0][1][1][0][RTW89_UKRAINE][12] = 48,
+ [0][1][1][0][RTW89_CHILE][12] = 36,
+ [0][1][1][0][RTW89_QATAR][12] = 48,
[0][1][1][0][RTW89_FCC][13] = 127,
[0][1][1][0][RTW89_ETSI][13] = 127,
[0][1][1][0][RTW89_MKK][13] = 127,
@@ -29434,6 +32750,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][13] = 127,
[0][1][1][0][RTW89_CN][13] = 127,
[0][1][1][0][RTW89_UK][13] = 127,
+ [0][1][1][0][RTW89_MEXICO][13] = 127,
+ [0][1][1][0][RTW89_UKRAINE][13] = 127,
+ [0][1][1][0][RTW89_CHILE][13] = 127,
+ [0][1][1][0][RTW89_QATAR][13] = 127,
[0][0][2][0][RTW89_FCC][0] = 66,
[0][0][2][0][RTW89_ETSI][0] = 60,
[0][0][2][0][RTW89_MKK][0] = 78,
@@ -29442,6 +32762,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][0] = 60,
[0][0][2][0][RTW89_CN][0] = 58,
[0][0][2][0][RTW89_UK][0] = 60,
+ [0][0][2][0][RTW89_MEXICO][0] = 66,
+ [0][0][2][0][RTW89_UKRAINE][0] = 60,
+ [0][0][2][0][RTW89_CHILE][0] = 66,
+ [0][0][2][0][RTW89_QATAR][0] = 60,
[0][0][2][0][RTW89_FCC][1] = 70,
[0][0][2][0][RTW89_ETSI][1] = 60,
[0][0][2][0][RTW89_MKK][1] = 78,
@@ -29450,6 +32774,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][1] = 60,
[0][0][2][0][RTW89_CN][1] = 58,
[0][0][2][0][RTW89_UK][1] = 60,
+ [0][0][2][0][RTW89_MEXICO][1] = 70,
+ [0][0][2][0][RTW89_UKRAINE][1] = 60,
+ [0][0][2][0][RTW89_CHILE][1] = 70,
+ [0][0][2][0][RTW89_QATAR][1] = 60,
[0][0][2][0][RTW89_FCC][2] = 74,
[0][0][2][0][RTW89_ETSI][2] = 60,
[0][0][2][0][RTW89_MKK][2] = 78,
@@ -29458,6 +32786,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][2] = 60,
[0][0][2][0][RTW89_CN][2] = 58,
[0][0][2][0][RTW89_UK][2] = 60,
+ [0][0][2][0][RTW89_MEXICO][2] = 74,
+ [0][0][2][0][RTW89_UKRAINE][2] = 60,
+ [0][0][2][0][RTW89_CHILE][2] = 64,
+ [0][0][2][0][RTW89_QATAR][2] = 60,
[0][0][2][0][RTW89_FCC][3] = 78,
[0][0][2][0][RTW89_ETSI][3] = 60,
[0][0][2][0][RTW89_MKK][3] = 78,
@@ -29466,6 +32798,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][3] = 60,
[0][0][2][0][RTW89_CN][3] = 58,
[0][0][2][0][RTW89_UK][3] = 60,
+ [0][0][2][0][RTW89_MEXICO][3] = 78,
+ [0][0][2][0][RTW89_UKRAINE][3] = 60,
+ [0][0][2][0][RTW89_CHILE][3] = 64,
+ [0][0][2][0][RTW89_QATAR][3] = 60,
[0][0][2][0][RTW89_FCC][4] = 80,
[0][0][2][0][RTW89_ETSI][4] = 60,
[0][0][2][0][RTW89_MKK][4] = 78,
@@ -29474,6 +32810,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][4] = 60,
[0][0][2][0][RTW89_CN][4] = 58,
[0][0][2][0][RTW89_UK][4] = 60,
+ [0][0][2][0][RTW89_MEXICO][4] = 80,
+ [0][0][2][0][RTW89_UKRAINE][4] = 60,
+ [0][0][2][0][RTW89_CHILE][4] = 64,
+ [0][0][2][0][RTW89_QATAR][4] = 60,
[0][0][2][0][RTW89_FCC][5] = 80,
[0][0][2][0][RTW89_ETSI][5] = 60,
[0][0][2][0][RTW89_MKK][5] = 78,
@@ -29482,6 +32822,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][5] = 60,
[0][0][2][0][RTW89_CN][5] = 58,
[0][0][2][0][RTW89_UK][5] = 60,
+ [0][0][2][0][RTW89_MEXICO][5] = 80,
+ [0][0][2][0][RTW89_UKRAINE][5] = 60,
+ [0][0][2][0][RTW89_CHILE][5] = 80,
+ [0][0][2][0][RTW89_QATAR][5] = 60,
[0][0][2][0][RTW89_FCC][6] = 80,
[0][0][2][0][RTW89_ETSI][6] = 60,
[0][0][2][0][RTW89_MKK][6] = 78,
@@ -29490,6 +32834,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][6] = 60,
[0][0][2][0][RTW89_CN][6] = 58,
[0][0][2][0][RTW89_UK][6] = 60,
+ [0][0][2][0][RTW89_MEXICO][6] = 80,
+ [0][0][2][0][RTW89_UKRAINE][6] = 60,
+ [0][0][2][0][RTW89_CHILE][6] = 68,
+ [0][0][2][0][RTW89_QATAR][6] = 60,
[0][0][2][0][RTW89_FCC][7] = 80,
[0][0][2][0][RTW89_ETSI][7] = 60,
[0][0][2][0][RTW89_MKK][7] = 78,
@@ -29498,6 +32846,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][7] = 60,
[0][0][2][0][RTW89_CN][7] = 58,
[0][0][2][0][RTW89_UK][7] = 60,
+ [0][0][2][0][RTW89_MEXICO][7] = 80,
+ [0][0][2][0][RTW89_UKRAINE][7] = 60,
+ [0][0][2][0][RTW89_CHILE][7] = 68,
+ [0][0][2][0][RTW89_QATAR][7] = 60,
[0][0][2][0][RTW89_FCC][8] = 78,
[0][0][2][0][RTW89_ETSI][8] = 60,
[0][0][2][0][RTW89_MKK][8] = 78,
@@ -29506,6 +32858,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][8] = 60,
[0][0][2][0][RTW89_CN][8] = 58,
[0][0][2][0][RTW89_UK][8] = 60,
+ [0][0][2][0][RTW89_MEXICO][8] = 78,
+ [0][0][2][0][RTW89_UKRAINE][8] = 60,
+ [0][0][2][0][RTW89_CHILE][8] = 68,
+ [0][0][2][0][RTW89_QATAR][8] = 60,
[0][0][2][0][RTW89_FCC][9] = 74,
[0][0][2][0][RTW89_ETSI][9] = 60,
[0][0][2][0][RTW89_MKK][9] = 78,
@@ -29514,6 +32870,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][9] = 60,
[0][0][2][0][RTW89_CN][9] = 58,
[0][0][2][0][RTW89_UK][9] = 60,
+ [0][0][2][0][RTW89_MEXICO][9] = 74,
+ [0][0][2][0][RTW89_UKRAINE][9] = 60,
+ [0][0][2][0][RTW89_CHILE][9] = 74,
+ [0][0][2][0][RTW89_QATAR][9] = 60,
[0][0][2][0][RTW89_FCC][10] = 62,
[0][0][2][0][RTW89_ETSI][10] = 60,
[0][0][2][0][RTW89_MKK][10] = 78,
@@ -29522,6 +32882,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][10] = 60,
[0][0][2][0][RTW89_CN][10] = 58,
[0][0][2][0][RTW89_UK][10] = 60,
+ [0][0][2][0][RTW89_MEXICO][10] = 62,
+ [0][0][2][0][RTW89_UKRAINE][10] = 60,
+ [0][0][2][0][RTW89_CHILE][10] = 62,
+ [0][0][2][0][RTW89_QATAR][10] = 60,
[0][0][2][0][RTW89_FCC][11] = 60,
[0][0][2][0][RTW89_ETSI][11] = 60,
[0][0][2][0][RTW89_MKK][11] = 78,
@@ -29530,6 +32894,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][11] = 60,
[0][0][2][0][RTW89_CN][11] = 58,
[0][0][2][0][RTW89_UK][11] = 60,
+ [0][0][2][0][RTW89_MEXICO][11] = 60,
+ [0][0][2][0][RTW89_UKRAINE][11] = 60,
+ [0][0][2][0][RTW89_CHILE][11] = 60,
+ [0][0][2][0][RTW89_QATAR][11] = 60,
[0][0][2][0][RTW89_FCC][12] = 38,
[0][0][2][0][RTW89_ETSI][12] = 60,
[0][0][2][0][RTW89_MKK][12] = 78,
@@ -29538,6 +32906,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][12] = 60,
[0][0][2][0][RTW89_CN][12] = 58,
[0][0][2][0][RTW89_UK][12] = 60,
+ [0][0][2][0][RTW89_MEXICO][12] = 38,
+ [0][0][2][0][RTW89_UKRAINE][12] = 60,
+ [0][0][2][0][RTW89_CHILE][12] = 38,
+ [0][0][2][0][RTW89_QATAR][12] = 60,
[0][0][2][0][RTW89_FCC][13] = 127,
[0][0][2][0][RTW89_ETSI][13] = 127,
[0][0][2][0][RTW89_MKK][13] = 127,
@@ -29546,6 +32918,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][13] = 127,
[0][0][2][0][RTW89_CN][13] = 127,
[0][0][2][0][RTW89_UK][13] = 127,
+ [0][0][2][0][RTW89_MEXICO][13] = 127,
+ [0][0][2][0][RTW89_UKRAINE][13] = 127,
+ [0][0][2][0][RTW89_CHILE][13] = 127,
+ [0][0][2][0][RTW89_QATAR][13] = 127,
[0][1][2][0][RTW89_FCC][0] = 64,
[0][1][2][0][RTW89_ETSI][0] = 48,
[0][1][2][0][RTW89_MKK][0] = 68,
@@ -29554,6 +32930,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][0] = 48,
[0][1][2][0][RTW89_CN][0] = 46,
[0][1][2][0][RTW89_UK][0] = 48,
+ [0][1][2][0][RTW89_MEXICO][0] = 64,
+ [0][1][2][0][RTW89_UKRAINE][0] = 48,
+ [0][1][2][0][RTW89_CHILE][0] = 64,
+ [0][1][2][0][RTW89_QATAR][0] = 48,
[0][1][2][0][RTW89_FCC][1] = 70,
[0][1][2][0][RTW89_ETSI][1] = 48,
[0][1][2][0][RTW89_MKK][1] = 68,
@@ -29562,6 +32942,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][1] = 48,
[0][1][2][0][RTW89_CN][1] = 46,
[0][1][2][0][RTW89_UK][1] = 48,
+ [0][1][2][0][RTW89_MEXICO][1] = 70,
+ [0][1][2][0][RTW89_UKRAINE][1] = 48,
+ [0][1][2][0][RTW89_CHILE][1] = 70,
+ [0][1][2][0][RTW89_QATAR][1] = 48,
[0][1][2][0][RTW89_FCC][2] = 74,
[0][1][2][0][RTW89_ETSI][2] = 48,
[0][1][2][0][RTW89_MKK][2] = 68,
@@ -29570,6 +32954,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][2] = 48,
[0][1][2][0][RTW89_CN][2] = 46,
[0][1][2][0][RTW89_UK][2] = 48,
+ [0][1][2][0][RTW89_MEXICO][2] = 74,
+ [0][1][2][0][RTW89_UKRAINE][2] = 48,
+ [0][1][2][0][RTW89_CHILE][2] = 56,
+ [0][1][2][0][RTW89_QATAR][2] = 48,
[0][1][2][0][RTW89_FCC][3] = 78,
[0][1][2][0][RTW89_ETSI][3] = 48,
[0][1][2][0][RTW89_MKK][3] = 68,
@@ -29578,6 +32966,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][3] = 48,
[0][1][2][0][RTW89_CN][3] = 46,
[0][1][2][0][RTW89_UK][3] = 48,
+ [0][1][2][0][RTW89_MEXICO][3] = 78,
+ [0][1][2][0][RTW89_UKRAINE][3] = 48,
+ [0][1][2][0][RTW89_CHILE][3] = 56,
+ [0][1][2][0][RTW89_QATAR][3] = 48,
[0][1][2][0][RTW89_FCC][4] = 80,
[0][1][2][0][RTW89_ETSI][4] = 48,
[0][1][2][0][RTW89_MKK][4] = 68,
@@ -29586,6 +32978,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][4] = 48,
[0][1][2][0][RTW89_CN][4] = 46,
[0][1][2][0][RTW89_UK][4] = 48,
+ [0][1][2][0][RTW89_MEXICO][4] = 80,
+ [0][1][2][0][RTW89_UKRAINE][4] = 48,
+ [0][1][2][0][RTW89_CHILE][4] = 56,
+ [0][1][2][0][RTW89_QATAR][4] = 48,
[0][1][2][0][RTW89_FCC][5] = 80,
[0][1][2][0][RTW89_ETSI][5] = 48,
[0][1][2][0][RTW89_MKK][5] = 68,
@@ -29594,6 +32990,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][5] = 48,
[0][1][2][0][RTW89_CN][5] = 46,
[0][1][2][0][RTW89_UK][5] = 48,
+ [0][1][2][0][RTW89_MEXICO][5] = 80,
+ [0][1][2][0][RTW89_UKRAINE][5] = 48,
+ [0][1][2][0][RTW89_CHILE][5] = 78,
+ [0][1][2][0][RTW89_QATAR][5] = 48,
[0][1][2][0][RTW89_FCC][6] = 80,
[0][1][2][0][RTW89_ETSI][6] = 48,
[0][1][2][0][RTW89_MKK][6] = 68,
@@ -29602,6 +33002,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][6] = 48,
[0][1][2][0][RTW89_CN][6] = 46,
[0][1][2][0][RTW89_UK][6] = 48,
+ [0][1][2][0][RTW89_MEXICO][6] = 80,
+ [0][1][2][0][RTW89_UKRAINE][6] = 48,
+ [0][1][2][0][RTW89_CHILE][6] = 54,
+ [0][1][2][0][RTW89_QATAR][6] = 48,
[0][1][2][0][RTW89_FCC][7] = 74,
[0][1][2][0][RTW89_ETSI][7] = 48,
[0][1][2][0][RTW89_MKK][7] = 68,
@@ -29610,6 +33014,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][7] = 48,
[0][1][2][0][RTW89_CN][7] = 46,
[0][1][2][0][RTW89_UK][7] = 48,
+ [0][1][2][0][RTW89_MEXICO][7] = 74,
+ [0][1][2][0][RTW89_UKRAINE][7] = 48,
+ [0][1][2][0][RTW89_CHILE][7] = 54,
+ [0][1][2][0][RTW89_QATAR][7] = 48,
[0][1][2][0][RTW89_FCC][8] = 70,
[0][1][2][0][RTW89_ETSI][8] = 48,
[0][1][2][0][RTW89_MKK][8] = 68,
@@ -29618,6 +33026,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][8] = 48,
[0][1][2][0][RTW89_CN][8] = 46,
[0][1][2][0][RTW89_UK][8] = 48,
+ [0][1][2][0][RTW89_MEXICO][8] = 70,
+ [0][1][2][0][RTW89_UKRAINE][8] = 48,
+ [0][1][2][0][RTW89_CHILE][8] = 54,
+ [0][1][2][0][RTW89_QATAR][8] = 48,
[0][1][2][0][RTW89_FCC][9] = 66,
[0][1][2][0][RTW89_ETSI][9] = 48,
[0][1][2][0][RTW89_MKK][9] = 68,
@@ -29626,6 +33038,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][9] = 48,
[0][1][2][0][RTW89_CN][9] = 46,
[0][1][2][0][RTW89_UK][9] = 48,
+ [0][1][2][0][RTW89_MEXICO][9] = 66,
+ [0][1][2][0][RTW89_UKRAINE][9] = 48,
+ [0][1][2][0][RTW89_CHILE][9] = 66,
+ [0][1][2][0][RTW89_QATAR][9] = 48,
[0][1][2][0][RTW89_FCC][10] = 58,
[0][1][2][0][RTW89_ETSI][10] = 48,
[0][1][2][0][RTW89_MKK][10] = 68,
@@ -29634,6 +33050,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][10] = 48,
[0][1][2][0][RTW89_CN][10] = 46,
[0][1][2][0][RTW89_UK][10] = 48,
+ [0][1][2][0][RTW89_MEXICO][10] = 58,
+ [0][1][2][0][RTW89_UKRAINE][10] = 48,
+ [0][1][2][0][RTW89_CHILE][10] = 58,
+ [0][1][2][0][RTW89_QATAR][10] = 48,
[0][1][2][0][RTW89_FCC][11] = 58,
[0][1][2][0][RTW89_ETSI][11] = 48,
[0][1][2][0][RTW89_MKK][11] = 68,
@@ -29642,6 +33062,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][11] = 48,
[0][1][2][0][RTW89_CN][11] = 46,
[0][1][2][0][RTW89_UK][11] = 48,
+ [0][1][2][0][RTW89_MEXICO][11] = 58,
+ [0][1][2][0][RTW89_UKRAINE][11] = 48,
+ [0][1][2][0][RTW89_CHILE][11] = 58,
+ [0][1][2][0][RTW89_QATAR][11] = 48,
[0][1][2][0][RTW89_FCC][12] = 16,
[0][1][2][0][RTW89_ETSI][12] = 48,
[0][1][2][0][RTW89_MKK][12] = 68,
@@ -29650,6 +33074,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][12] = 48,
[0][1][2][0][RTW89_CN][12] = 46,
[0][1][2][0][RTW89_UK][12] = 48,
+ [0][1][2][0][RTW89_MEXICO][12] = 16,
+ [0][1][2][0][RTW89_UKRAINE][12] = 48,
+ [0][1][2][0][RTW89_CHILE][12] = 16,
+ [0][1][2][0][RTW89_QATAR][12] = 48,
[0][1][2][0][RTW89_FCC][13] = 127,
[0][1][2][0][RTW89_ETSI][13] = 127,
[0][1][2][0][RTW89_MKK][13] = 127,
@@ -29658,6 +33086,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][13] = 127,
[0][1][2][0][RTW89_CN][13] = 127,
[0][1][2][0][RTW89_UK][13] = 127,
+ [0][1][2][0][RTW89_MEXICO][13] = 127,
+ [0][1][2][0][RTW89_UKRAINE][13] = 127,
+ [0][1][2][0][RTW89_CHILE][13] = 127,
+ [0][1][2][0][RTW89_QATAR][13] = 127,
[0][1][2][1][RTW89_FCC][0] = 64,
[0][1][2][1][RTW89_ETSI][0] = 36,
[0][1][2][1][RTW89_MKK][0] = 68,
@@ -29666,6 +33098,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][0] = 36,
[0][1][2][1][RTW89_CN][0] = 36,
[0][1][2][1][RTW89_UK][0] = 36,
+ [0][1][2][1][RTW89_MEXICO][0] = 64,
+ [0][1][2][1][RTW89_UKRAINE][0] = 36,
+ [0][1][2][1][RTW89_CHILE][0] = 64,
+ [0][1][2][1][RTW89_QATAR][0] = 36,
[0][1][2][1][RTW89_FCC][1] = 70,
[0][1][2][1][RTW89_ETSI][1] = 36,
[0][1][2][1][RTW89_MKK][1] = 68,
@@ -29674,6 +33110,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][1] = 36,
[0][1][2][1][RTW89_CN][1] = 34,
[0][1][2][1][RTW89_UK][1] = 36,
+ [0][1][2][1][RTW89_MEXICO][1] = 70,
+ [0][1][2][1][RTW89_UKRAINE][1] = 36,
+ [0][1][2][1][RTW89_CHILE][1] = 70,
+ [0][1][2][1][RTW89_QATAR][1] = 36,
[0][1][2][1][RTW89_FCC][2] = 74,
[0][1][2][1][RTW89_ETSI][2] = 36,
[0][1][2][1][RTW89_MKK][2] = 68,
@@ -29682,6 +33122,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][2] = 36,
[0][1][2][1][RTW89_CN][2] = 34,
[0][1][2][1][RTW89_UK][2] = 36,
+ [0][1][2][1][RTW89_MEXICO][2] = 74,
+ [0][1][2][1][RTW89_UKRAINE][2] = 36,
+ [0][1][2][1][RTW89_CHILE][2] = 44,
+ [0][1][2][1][RTW89_QATAR][2] = 36,
[0][1][2][1][RTW89_FCC][3] = 78,
[0][1][2][1][RTW89_ETSI][3] = 36,
[0][1][2][1][RTW89_MKK][3] = 68,
@@ -29690,6 +33134,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][3] = 36,
[0][1][2][1][RTW89_CN][3] = 34,
[0][1][2][1][RTW89_UK][3] = 36,
+ [0][1][2][1][RTW89_MEXICO][3] = 78,
+ [0][1][2][1][RTW89_UKRAINE][3] = 36,
+ [0][1][2][1][RTW89_CHILE][3] = 44,
+ [0][1][2][1][RTW89_QATAR][3] = 36,
[0][1][2][1][RTW89_FCC][4] = 80,
[0][1][2][1][RTW89_ETSI][4] = 36,
[0][1][2][1][RTW89_MKK][4] = 68,
@@ -29698,6 +33146,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][4] = 36,
[0][1][2][1][RTW89_CN][4] = 34,
[0][1][2][1][RTW89_UK][4] = 36,
+ [0][1][2][1][RTW89_MEXICO][4] = 80,
+ [0][1][2][1][RTW89_UKRAINE][4] = 36,
+ [0][1][2][1][RTW89_CHILE][4] = 44,
+ [0][1][2][1][RTW89_QATAR][4] = 36,
[0][1][2][1][RTW89_FCC][5] = 80,
[0][1][2][1][RTW89_ETSI][5] = 36,
[0][1][2][1][RTW89_MKK][5] = 68,
@@ -29706,6 +33158,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][5] = 36,
[0][1][2][1][RTW89_CN][5] = 34,
[0][1][2][1][RTW89_UK][5] = 36,
+ [0][1][2][1][RTW89_MEXICO][5] = 80,
+ [0][1][2][1][RTW89_UKRAINE][5] = 36,
+ [0][1][2][1][RTW89_CHILE][5] = 74,
+ [0][1][2][1][RTW89_QATAR][5] = 36,
[0][1][2][1][RTW89_FCC][6] = 80,
[0][1][2][1][RTW89_ETSI][6] = 36,
[0][1][2][1][RTW89_MKK][6] = 68,
@@ -29714,6 +33170,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][6] = 36,
[0][1][2][1][RTW89_CN][6] = 34,
[0][1][2][1][RTW89_UK][6] = 36,
+ [0][1][2][1][RTW89_MEXICO][6] = 80,
+ [0][1][2][1][RTW89_UKRAINE][6] = 36,
+ [0][1][2][1][RTW89_CHILE][6] = 42,
+ [0][1][2][1][RTW89_QATAR][6] = 36,
[0][1][2][1][RTW89_FCC][7] = 74,
[0][1][2][1][RTW89_ETSI][7] = 36,
[0][1][2][1][RTW89_MKK][7] = 68,
@@ -29722,6 +33182,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][7] = 36,
[0][1][2][1][RTW89_CN][7] = 34,
[0][1][2][1][RTW89_UK][7] = 36,
+ [0][1][2][1][RTW89_MEXICO][7] = 74,
+ [0][1][2][1][RTW89_UKRAINE][7] = 36,
+ [0][1][2][1][RTW89_CHILE][7] = 42,
+ [0][1][2][1][RTW89_QATAR][7] = 36,
[0][1][2][1][RTW89_FCC][8] = 70,
[0][1][2][1][RTW89_ETSI][8] = 36,
[0][1][2][1][RTW89_MKK][8] = 68,
@@ -29730,6 +33194,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][8] = 36,
[0][1][2][1][RTW89_CN][8] = 34,
[0][1][2][1][RTW89_UK][8] = 36,
+ [0][1][2][1][RTW89_MEXICO][8] = 70,
+ [0][1][2][1][RTW89_UKRAINE][8] = 36,
+ [0][1][2][1][RTW89_CHILE][8] = 42,
+ [0][1][2][1][RTW89_QATAR][8] = 36,
[0][1][2][1][RTW89_FCC][9] = 66,
[0][1][2][1][RTW89_ETSI][9] = 36,
[0][1][2][1][RTW89_MKK][9] = 68,
@@ -29738,6 +33206,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][9] = 36,
[0][1][2][1][RTW89_CN][9] = 34,
[0][1][2][1][RTW89_UK][9] = 36,
+ [0][1][2][1][RTW89_MEXICO][9] = 66,
+ [0][1][2][1][RTW89_UKRAINE][9] = 36,
+ [0][1][2][1][RTW89_CHILE][9] = 66,
+ [0][1][2][1][RTW89_QATAR][9] = 36,
[0][1][2][1][RTW89_FCC][10] = 58,
[0][1][2][1][RTW89_ETSI][10] = 36,
[0][1][2][1][RTW89_MKK][10] = 68,
@@ -29746,6 +33218,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][10] = 36,
[0][1][2][1][RTW89_CN][10] = 34,
[0][1][2][1][RTW89_UK][10] = 36,
+ [0][1][2][1][RTW89_MEXICO][10] = 58,
+ [0][1][2][1][RTW89_UKRAINE][10] = 36,
+ [0][1][2][1][RTW89_CHILE][10] = 58,
+ [0][1][2][1][RTW89_QATAR][10] = 36,
[0][1][2][1][RTW89_FCC][11] = 58,
[0][1][2][1][RTW89_ETSI][11] = 36,
[0][1][2][1][RTW89_MKK][11] = 68,
@@ -29754,6 +33230,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][11] = 36,
[0][1][2][1][RTW89_CN][11] = 34,
[0][1][2][1][RTW89_UK][11] = 36,
+ [0][1][2][1][RTW89_MEXICO][11] = 58,
+ [0][1][2][1][RTW89_UKRAINE][11] = 36,
+ [0][1][2][1][RTW89_CHILE][11] = 58,
+ [0][1][2][1][RTW89_QATAR][11] = 36,
[0][1][2][1][RTW89_FCC][12] = 16,
[0][1][2][1][RTW89_ETSI][12] = 36,
[0][1][2][1][RTW89_MKK][12] = 68,
@@ -29762,6 +33242,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][12] = 36,
[0][1][2][1][RTW89_CN][12] = 34,
[0][1][2][1][RTW89_UK][12] = 36,
+ [0][1][2][1][RTW89_MEXICO][12] = 16,
+ [0][1][2][1][RTW89_UKRAINE][12] = 36,
+ [0][1][2][1][RTW89_CHILE][12] = 16,
+ [0][1][2][1][RTW89_QATAR][12] = 36,
[0][1][2][1][RTW89_FCC][13] = 127,
[0][1][2][1][RTW89_ETSI][13] = 127,
[0][1][2][1][RTW89_MKK][13] = 127,
@@ -29770,6 +33254,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][13] = 127,
[0][1][2][1][RTW89_CN][13] = 127,
[0][1][2][1][RTW89_UK][13] = 127,
+ [0][1][2][1][RTW89_MEXICO][13] = 127,
+ [0][1][2][1][RTW89_UKRAINE][13] = 127,
+ [0][1][2][1][RTW89_CHILE][13] = 127,
+ [0][1][2][1][RTW89_QATAR][13] = 127,
[1][0][2][0][RTW89_FCC][0] = 127,
[1][0][2][0][RTW89_ETSI][0] = 127,
[1][0][2][0][RTW89_MKK][0] = 127,
@@ -29778,6 +33266,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_ACMA][0] = 127,
[1][0][2][0][RTW89_CN][0] = 127,
[1][0][2][0][RTW89_UK][0] = 127,
+ [1][0][2][0][RTW89_MEXICO][0] = 127,
+ [1][0][2][0][RTW89_UKRAINE][0] = 127,
+ [1][0][2][0][RTW89_CHILE][0] = 127,
+ [1][0][2][0][RTW89_QATAR][0] = 127,
[1][0][2][0][RTW89_FCC][1] = 127,
[1][0][2][0][RTW89_ETSI][1] = 127,
[1][0][2][0][RTW89_MKK][1] = 127,
@@ -29786,6 +33278,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_ACMA][1] = 127,
[1][0][2][0][RTW89_CN][1] = 127,
[1][0][2][0][RTW89_UK][1] = 127,
+ [1][0][2][0][RTW89_MEXICO][1] = 127,
+ [1][0][2][0][RTW89_UKRAINE][1] = 127,
+ [1][0][2][0][RTW89_CHILE][1] = 127,
+ [1][0][2][0][RTW89_QATAR][1] = 127,
[1][0][2][0][RTW89_FCC][2] = 64,
[1][0][2][0][RTW89_ETSI][2] = 60,
[1][0][2][0][RTW89_MKK][2] = 74,
@@ -29794,6 +33290,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_ACMA][2] = 60,
[1][0][2][0][RTW89_CN][2] = 58,
[1][0][2][0][RTW89_UK][2] = 60,
+ [1][0][2][0][RTW89_MEXICO][2] = 64,
+ [1][0][2][0][RTW89_UKRAINE][2] = 60,
+ [1][0][2][0][RTW89_CHILE][2] = 64,
+ [1][0][2][0][RTW89_QATAR][2] = 60,
[1][0][2][0][RTW89_FCC][3] = 64,
[1][0][2][0][RTW89_ETSI][3] = 60,
[1][0][2][0][RTW89_MKK][3] = 74,
@@ -29802,6 +33302,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_ACMA][3] = 60,
[1][0][2][0][RTW89_CN][3] = 58,
[1][0][2][0][RTW89_UK][3] = 60,
+ [1][0][2][0][RTW89_MEXICO][3] = 64,
+ [1][0][2][0][RTW89_UKRAINE][3] = 60,
+ [1][0][2][0][RTW89_CHILE][3] = 64,
+ [1][0][2][0][RTW89_QATAR][3] = 60,
[1][0][2][0][RTW89_FCC][4] = 68,
[1][0][2][0][RTW89_ETSI][4] = 60,
[1][0][2][0][RTW89_MKK][4] = 74,
@@ -29810,6 +33314,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_ACMA][4] = 60,
[1][0][2][0][RTW89_CN][4] = 58,
[1][0][2][0][RTW89_UK][4] = 60,
+ [1][0][2][0][RTW89_MEXICO][4] = 68,
+ [1][0][2][0][RTW89_UKRAINE][4] = 60,
+ [1][0][2][0][RTW89_CHILE][4] = 68,
+ [1][0][2][0][RTW89_QATAR][4] = 60,
[1][0][2][0][RTW89_FCC][5] = 68,
[1][0][2][0][RTW89_ETSI][5] = 60,
[1][0][2][0][RTW89_MKK][5] = 74,
@@ -29818,6 +33326,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_ACMA][5] = 60,
[1][0][2][0][RTW89_CN][5] = 58,
[1][0][2][0][RTW89_UK][5] = 60,
+ [1][0][2][0][RTW89_MEXICO][5] = 68,
+ [1][0][2][0][RTW89_UKRAINE][5] = 60,
+ [1][0][2][0][RTW89_CHILE][5] = 68,
+ [1][0][2][0][RTW89_QATAR][5] = 60,
[1][0][2][0][RTW89_FCC][6] = 66,
[1][0][2][0][RTW89_ETSI][6] = 60,
[1][0][2][0][RTW89_MKK][6] = 74,
@@ -29826,6 +33338,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_ACMA][6] = 60,
[1][0][2][0][RTW89_CN][6] = 58,
[1][0][2][0][RTW89_UK][6] = 60,
+ [1][0][2][0][RTW89_MEXICO][6] = 66,
+ [1][0][2][0][RTW89_UKRAINE][6] = 60,
+ [1][0][2][0][RTW89_CHILE][6] = 66,
+ [1][0][2][0][RTW89_QATAR][6] = 60,
[1][0][2][0][RTW89_FCC][7] = 62,
[1][0][2][0][RTW89_ETSI][7] = 60,
[1][0][2][0][RTW89_MKK][7] = 74,
@@ -29834,6 +33350,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_ACMA][7] = 60,
[1][0][2][0][RTW89_CN][7] = 58,
[1][0][2][0][RTW89_UK][7] = 60,
+ [1][0][2][0][RTW89_MEXICO][7] = 62,
+ [1][0][2][0][RTW89_UKRAINE][7] = 60,
+ [1][0][2][0][RTW89_CHILE][7] = 62,
+ [1][0][2][0][RTW89_QATAR][7] = 60,
[1][0][2][0][RTW89_FCC][8] = 62,
[1][0][2][0][RTW89_ETSI][8] = 60,
[1][0][2][0][RTW89_MKK][8] = 74,
@@ -29842,6 +33362,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_ACMA][8] = 60,
[1][0][2][0][RTW89_CN][8] = 58,
[1][0][2][0][RTW89_UK][8] = 60,
+ [1][0][2][0][RTW89_MEXICO][8] = 62,
+ [1][0][2][0][RTW89_UKRAINE][8] = 60,
+ [1][0][2][0][RTW89_CHILE][8] = 62,
+ [1][0][2][0][RTW89_QATAR][8] = 60,
[1][0][2][0][RTW89_FCC][9] = 60,
[1][0][2][0][RTW89_ETSI][9] = 60,
[1][0][2][0][RTW89_MKK][9] = 74,
@@ -29850,6 +33374,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_ACMA][9] = 60,
[1][0][2][0][RTW89_CN][9] = 58,
[1][0][2][0][RTW89_UK][9] = 60,
+ [1][0][2][0][RTW89_MEXICO][9] = 60,
+ [1][0][2][0][RTW89_UKRAINE][9] = 60,
+ [1][0][2][0][RTW89_CHILE][9] = 60,
+ [1][0][2][0][RTW89_QATAR][9] = 60,
[1][0][2][0][RTW89_FCC][10] = 56,
[1][0][2][0][RTW89_ETSI][10] = 60,
[1][0][2][0][RTW89_MKK][10] = 74,
@@ -29858,6 +33386,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_ACMA][10] = 60,
[1][0][2][0][RTW89_CN][10] = 58,
[1][0][2][0][RTW89_UK][10] = 60,
+ [1][0][2][0][RTW89_MEXICO][10] = 56,
+ [1][0][2][0][RTW89_UKRAINE][10] = 60,
+ [1][0][2][0][RTW89_CHILE][10] = 56,
+ [1][0][2][0][RTW89_QATAR][10] = 60,
[1][0][2][0][RTW89_FCC][11] = 127,
[1][0][2][0][RTW89_ETSI][11] = 127,
[1][0][2][0][RTW89_MKK][11] = 127,
@@ -29866,6 +33398,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_ACMA][11] = 127,
[1][0][2][0][RTW89_CN][11] = 127,
[1][0][2][0][RTW89_UK][11] = 127,
+ [1][0][2][0][RTW89_MEXICO][11] = 127,
+ [1][0][2][0][RTW89_UKRAINE][11] = 127,
+ [1][0][2][0][RTW89_CHILE][11] = 127,
+ [1][0][2][0][RTW89_QATAR][11] = 127,
[1][0][2][0][RTW89_FCC][12] = 127,
[1][0][2][0][RTW89_ETSI][12] = 127,
[1][0][2][0][RTW89_MKK][12] = 127,
@@ -29874,6 +33410,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_ACMA][12] = 127,
[1][0][2][0][RTW89_CN][12] = 127,
[1][0][2][0][RTW89_UK][12] = 127,
+ [1][0][2][0][RTW89_MEXICO][12] = 127,
+ [1][0][2][0][RTW89_UKRAINE][12] = 127,
+ [1][0][2][0][RTW89_CHILE][12] = 127,
+ [1][0][2][0][RTW89_QATAR][12] = 127,
[1][0][2][0][RTW89_FCC][13] = 127,
[1][0][2][0][RTW89_ETSI][13] = 127,
[1][0][2][0][RTW89_MKK][13] = 127,
@@ -29882,6 +33422,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_ACMA][13] = 127,
[1][0][2][0][RTW89_CN][13] = 127,
[1][0][2][0][RTW89_UK][13] = 127,
+ [1][0][2][0][RTW89_MEXICO][13] = 127,
+ [1][0][2][0][RTW89_UKRAINE][13] = 127,
+ [1][0][2][0][RTW89_CHILE][13] = 127,
+ [1][0][2][0][RTW89_QATAR][13] = 127,
[1][1][2][0][RTW89_FCC][0] = 127,
[1][1][2][0][RTW89_ETSI][0] = 127,
[1][1][2][0][RTW89_MKK][0] = 127,
@@ -29890,6 +33434,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][0][RTW89_ACMA][0] = 127,
[1][1][2][0][RTW89_CN][0] = 127,
[1][1][2][0][RTW89_UK][0] = 127,
+ [1][1][2][0][RTW89_MEXICO][0] = 127,
+ [1][1][2][0][RTW89_UKRAINE][0] = 127,
+ [1][1][2][0][RTW89_CHILE][0] = 127,
+ [1][1][2][0][RTW89_QATAR][0] = 127,
[1][1][2][0][RTW89_FCC][1] = 127,
[1][1][2][0][RTW89_ETSI][1] = 127,
[1][1][2][0][RTW89_MKK][1] = 127,
@@ -29898,6 +33446,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][0][RTW89_ACMA][1] = 127,
[1][1][2][0][RTW89_CN][1] = 127,
[1][1][2][0][RTW89_UK][1] = 127,
+ [1][1][2][0][RTW89_MEXICO][1] = 127,
+ [1][1][2][0][RTW89_UKRAINE][1] = 127,
+ [1][1][2][0][RTW89_CHILE][1] = 127,
+ [1][1][2][0][RTW89_QATAR][1] = 127,
[1][1][2][0][RTW89_FCC][2] = 60,
[1][1][2][0][RTW89_ETSI][2] = 48,
[1][1][2][0][RTW89_MKK][2] = 68,
@@ -29906,6 +33458,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][0][RTW89_ACMA][2] = 48,
[1][1][2][0][RTW89_CN][2] = 34,
[1][1][2][0][RTW89_UK][2] = 48,
+ [1][1][2][0][RTW89_MEXICO][2] = 60,
+ [1][1][2][0][RTW89_UKRAINE][2] = 48,
+ [1][1][2][0][RTW89_CHILE][2] = 60,
+ [1][1][2][0][RTW89_QATAR][2] = 48,
[1][1][2][0][RTW89_FCC][3] = 60,
[1][1][2][0][RTW89_ETSI][3] = 48,
[1][1][2][0][RTW89_MKK][3] = 68,
@@ -29914,6 +33470,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][0][RTW89_ACMA][3] = 48,
[1][1][2][0][RTW89_CN][3] = 34,
[1][1][2][0][RTW89_UK][3] = 48,
+ [1][1][2][0][RTW89_MEXICO][3] = 60,
+ [1][1][2][0][RTW89_UKRAINE][3] = 48,
+ [1][1][2][0][RTW89_CHILE][3] = 56,
+ [1][1][2][0][RTW89_QATAR][3] = 48,
[1][1][2][0][RTW89_FCC][4] = 60,
[1][1][2][0][RTW89_ETSI][4] = 48,
[1][1][2][0][RTW89_MKK][4] = 68,
@@ -29922,6 +33482,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][0][RTW89_ACMA][4] = 48,
[1][1][2][0][RTW89_CN][4] = 34,
[1][1][2][0][RTW89_UK][4] = 48,
+ [1][1][2][0][RTW89_MEXICO][4] = 60,
+ [1][1][2][0][RTW89_UKRAINE][4] = 48,
+ [1][1][2][0][RTW89_CHILE][4] = 56,
+ [1][1][2][0][RTW89_QATAR][4] = 48,
[1][1][2][0][RTW89_FCC][5] = 60,
[1][1][2][0][RTW89_ETSI][5] = 48,
[1][1][2][0][RTW89_MKK][5] = 68,
@@ -29930,6 +33494,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][0][RTW89_ACMA][5] = 48,
[1][1][2][0][RTW89_CN][5] = 34,
[1][1][2][0][RTW89_UK][5] = 48,
+ [1][1][2][0][RTW89_MEXICO][5] = 60,
+ [1][1][2][0][RTW89_UKRAINE][5] = 48,
+ [1][1][2][0][RTW89_CHILE][5] = 60,
+ [1][1][2][0][RTW89_QATAR][5] = 48,
[1][1][2][0][RTW89_FCC][6] = 58,
[1][1][2][0][RTW89_ETSI][6] = 48,
[1][1][2][0][RTW89_MKK][6] = 68,
@@ -29938,6 +33506,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][0][RTW89_ACMA][6] = 48,
[1][1][2][0][RTW89_CN][6] = 34,
[1][1][2][0][RTW89_UK][6] = 48,
+ [1][1][2][0][RTW89_MEXICO][6] = 58,
+ [1][1][2][0][RTW89_UKRAINE][6] = 48,
+ [1][1][2][0][RTW89_CHILE][6] = 52,
+ [1][1][2][0][RTW89_QATAR][6] = 48,
[1][1][2][0][RTW89_FCC][7] = 54,
[1][1][2][0][RTW89_ETSI][7] = 48,
[1][1][2][0][RTW89_MKK][7] = 68,
@@ -29946,6 +33518,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][0][RTW89_ACMA][7] = 48,
[1][1][2][0][RTW89_CN][7] = 34,
[1][1][2][0][RTW89_UK][7] = 48,
+ [1][1][2][0][RTW89_MEXICO][7] = 54,
+ [1][1][2][0][RTW89_UKRAINE][7] = 48,
+ [1][1][2][0][RTW89_CHILE][7] = 52,
+ [1][1][2][0][RTW89_QATAR][7] = 48,
[1][1][2][0][RTW89_FCC][8] = 54,
[1][1][2][0][RTW89_ETSI][8] = 48,
[1][1][2][0][RTW89_MKK][8] = 68,
@@ -29954,6 +33530,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][0][RTW89_ACMA][8] = 48,
[1][1][2][0][RTW89_CN][8] = 34,
[1][1][2][0][RTW89_UK][8] = 48,
+ [1][1][2][0][RTW89_MEXICO][8] = 54,
+ [1][1][2][0][RTW89_UKRAINE][8] = 48,
+ [1][1][2][0][RTW89_CHILE][8] = 54,
+ [1][1][2][0][RTW89_QATAR][8] = 48,
[1][1][2][0][RTW89_FCC][9] = 54,
[1][1][2][0][RTW89_ETSI][9] = 48,
[1][1][2][0][RTW89_MKK][9] = 68,
@@ -29962,6 +33542,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][0][RTW89_ACMA][9] = 48,
[1][1][2][0][RTW89_CN][9] = 34,
[1][1][2][0][RTW89_UK][9] = 48,
+ [1][1][2][0][RTW89_MEXICO][9] = 54,
+ [1][1][2][0][RTW89_UKRAINE][9] = 48,
+ [1][1][2][0][RTW89_CHILE][9] = 54,
+ [1][1][2][0][RTW89_QATAR][9] = 48,
[1][1][2][0][RTW89_FCC][10] = 46,
[1][1][2][0][RTW89_ETSI][10] = 48,
[1][1][2][0][RTW89_MKK][10] = 68,
@@ -29970,6 +33554,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][0][RTW89_ACMA][10] = 48,
[1][1][2][0][RTW89_CN][10] = 34,
[1][1][2][0][RTW89_UK][10] = 48,
+ [1][1][2][0][RTW89_MEXICO][10] = 46,
+ [1][1][2][0][RTW89_UKRAINE][10] = 48,
+ [1][1][2][0][RTW89_CHILE][10] = 46,
+ [1][1][2][0][RTW89_QATAR][10] = 48,
[1][1][2][0][RTW89_FCC][11] = 127,
[1][1][2][0][RTW89_ETSI][11] = 127,
[1][1][2][0][RTW89_MKK][11] = 127,
@@ -29978,6 +33566,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][0][RTW89_ACMA][11] = 127,
[1][1][2][0][RTW89_CN][11] = 127,
[1][1][2][0][RTW89_UK][11] = 127,
+ [1][1][2][0][RTW89_MEXICO][11] = 127,
+ [1][1][2][0][RTW89_UKRAINE][11] = 127,
+ [1][1][2][0][RTW89_CHILE][11] = 127,
+ [1][1][2][0][RTW89_QATAR][11] = 127,
[1][1][2][0][RTW89_FCC][12] = 127,
[1][1][2][0][RTW89_ETSI][12] = 127,
[1][1][2][0][RTW89_MKK][12] = 127,
@@ -29986,6 +33578,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][0][RTW89_ACMA][12] = 127,
[1][1][2][0][RTW89_CN][12] = 127,
[1][1][2][0][RTW89_UK][12] = 127,
+ [1][1][2][0][RTW89_MEXICO][12] = 127,
+ [1][1][2][0][RTW89_UKRAINE][12] = 127,
+ [1][1][2][0][RTW89_CHILE][12] = 127,
+ [1][1][2][0][RTW89_QATAR][12] = 127,
[1][1][2][0][RTW89_FCC][13] = 127,
[1][1][2][0][RTW89_ETSI][13] = 127,
[1][1][2][0][RTW89_MKK][13] = 127,
@@ -29994,6 +33590,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][0][RTW89_ACMA][13] = 127,
[1][1][2][0][RTW89_CN][13] = 127,
[1][1][2][0][RTW89_UK][13] = 127,
+ [1][1][2][0][RTW89_MEXICO][13] = 127,
+ [1][1][2][0][RTW89_UKRAINE][13] = 127,
+ [1][1][2][0][RTW89_CHILE][13] = 127,
+ [1][1][2][0][RTW89_QATAR][13] = 127,
[1][1][2][1][RTW89_FCC][0] = 127,
[1][1][2][1][RTW89_ETSI][0] = 127,
[1][1][2][1][RTW89_MKK][0] = 127,
@@ -30002,6 +33602,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][1][RTW89_ACMA][0] = 127,
[1][1][2][1][RTW89_CN][0] = 127,
[1][1][2][1][RTW89_UK][0] = 127,
+ [1][1][2][1][RTW89_MEXICO][0] = 127,
+ [1][1][2][1][RTW89_UKRAINE][0] = 127,
+ [1][1][2][1][RTW89_CHILE][0] = 127,
+ [1][1][2][1][RTW89_QATAR][0] = 127,
[1][1][2][1][RTW89_FCC][1] = 127,
[1][1][2][1][RTW89_ETSI][1] = 127,
[1][1][2][1][RTW89_MKK][1] = 127,
@@ -30010,6 +33614,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][1][RTW89_ACMA][1] = 127,
[1][1][2][1][RTW89_CN][1] = 127,
[1][1][2][1][RTW89_UK][1] = 127,
+ [1][1][2][1][RTW89_MEXICO][1] = 127,
+ [1][1][2][1][RTW89_UKRAINE][1] = 127,
+ [1][1][2][1][RTW89_CHILE][1] = 127,
+ [1][1][2][1][RTW89_QATAR][1] = 127,
[1][1][2][1][RTW89_FCC][2] = 60,
[1][1][2][1][RTW89_ETSI][2] = 36,
[1][1][2][1][RTW89_MKK][2] = 68,
@@ -30018,6 +33626,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][1][RTW89_ACMA][2] = 36,
[1][1][2][1][RTW89_CN][2] = 34,
[1][1][2][1][RTW89_UK][2] = 36,
+ [1][1][2][1][RTW89_MEXICO][2] = 60,
+ [1][1][2][1][RTW89_UKRAINE][2] = 36,
+ [1][1][2][1][RTW89_CHILE][2] = 60,
+ [1][1][2][1][RTW89_QATAR][2] = 36,
[1][1][2][1][RTW89_FCC][3] = 60,
[1][1][2][1][RTW89_ETSI][3] = 36,
[1][1][2][1][RTW89_MKK][3] = 68,
@@ -30026,6 +33638,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][1][RTW89_ACMA][3] = 36,
[1][1][2][1][RTW89_CN][3] = 34,
[1][1][2][1][RTW89_UK][3] = 36,
+ [1][1][2][1][RTW89_MEXICO][3] = 60,
+ [1][1][2][1][RTW89_UKRAINE][3] = 36,
+ [1][1][2][1][RTW89_CHILE][3] = 44,
+ [1][1][2][1][RTW89_QATAR][3] = 36,
[1][1][2][1][RTW89_FCC][4] = 60,
[1][1][2][1][RTW89_ETSI][4] = 36,
[1][1][2][1][RTW89_MKK][4] = 68,
@@ -30034,6 +33650,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][1][RTW89_ACMA][4] = 36,
[1][1][2][1][RTW89_CN][4] = 34,
[1][1][2][1][RTW89_UK][4] = 36,
+ [1][1][2][1][RTW89_MEXICO][4] = 60,
+ [1][1][2][1][RTW89_UKRAINE][4] = 36,
+ [1][1][2][1][RTW89_CHILE][4] = 44,
+ [1][1][2][1][RTW89_QATAR][4] = 36,
[1][1][2][1][RTW89_FCC][5] = 60,
[1][1][2][1][RTW89_ETSI][5] = 36,
[1][1][2][1][RTW89_MKK][5] = 68,
@@ -30042,6 +33662,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][1][RTW89_ACMA][5] = 36,
[1][1][2][1][RTW89_CN][5] = 34,
[1][1][2][1][RTW89_UK][5] = 36,
+ [1][1][2][1][RTW89_MEXICO][5] = 60,
+ [1][1][2][1][RTW89_UKRAINE][5] = 36,
+ [1][1][2][1][RTW89_CHILE][5] = 60,
+ [1][1][2][1][RTW89_QATAR][5] = 36,
[1][1][2][1][RTW89_FCC][6] = 58,
[1][1][2][1][RTW89_ETSI][6] = 36,
[1][1][2][1][RTW89_MKK][6] = 68,
@@ -30050,6 +33674,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][1][RTW89_ACMA][6] = 36,
[1][1][2][1][RTW89_CN][6] = 34,
[1][1][2][1][RTW89_UK][6] = 36,
+ [1][1][2][1][RTW89_MEXICO][6] = 58,
+ [1][1][2][1][RTW89_UKRAINE][6] = 36,
+ [1][1][2][1][RTW89_CHILE][6] = 40,
+ [1][1][2][1][RTW89_QATAR][6] = 36,
[1][1][2][1][RTW89_FCC][7] = 54,
[1][1][2][1][RTW89_ETSI][7] = 36,
[1][1][2][1][RTW89_MKK][7] = 68,
@@ -30058,6 +33686,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][1][RTW89_ACMA][7] = 36,
[1][1][2][1][RTW89_CN][7] = 34,
[1][1][2][1][RTW89_UK][7] = 36,
+ [1][1][2][1][RTW89_MEXICO][7] = 54,
+ [1][1][2][1][RTW89_UKRAINE][7] = 36,
+ [1][1][2][1][RTW89_CHILE][7] = 40,
+ [1][1][2][1][RTW89_QATAR][7] = 36,
[1][1][2][1][RTW89_FCC][8] = 54,
[1][1][2][1][RTW89_ETSI][8] = 36,
[1][1][2][1][RTW89_MKK][8] = 68,
@@ -30066,6 +33698,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][1][RTW89_ACMA][8] = 36,
[1][1][2][1][RTW89_CN][8] = 34,
[1][1][2][1][RTW89_UK][8] = 36,
+ [1][1][2][1][RTW89_MEXICO][8] = 54,
+ [1][1][2][1][RTW89_UKRAINE][8] = 36,
+ [1][1][2][1][RTW89_CHILE][8] = 54,
+ [1][1][2][1][RTW89_QATAR][8] = 36,
[1][1][2][1][RTW89_FCC][9] = 54,
[1][1][2][1][RTW89_ETSI][9] = 36,
[1][1][2][1][RTW89_MKK][9] = 68,
@@ -30074,6 +33710,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][1][RTW89_ACMA][9] = 36,
[1][1][2][1][RTW89_CN][9] = 34,
[1][1][2][1][RTW89_UK][9] = 36,
+ [1][1][2][1][RTW89_MEXICO][9] = 54,
+ [1][1][2][1][RTW89_UKRAINE][9] = 36,
+ [1][1][2][1][RTW89_CHILE][9] = 54,
+ [1][1][2][1][RTW89_QATAR][9] = 36,
[1][1][2][1][RTW89_FCC][10] = 46,
[1][1][2][1][RTW89_ETSI][10] = 36,
[1][1][2][1][RTW89_MKK][10] = 68,
@@ -30082,6 +33722,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][1][RTW89_ACMA][10] = 36,
[1][1][2][1][RTW89_CN][10] = 36,
[1][1][2][1][RTW89_UK][10] = 36,
+ [1][1][2][1][RTW89_MEXICO][10] = 46,
+ [1][1][2][1][RTW89_UKRAINE][10] = 36,
+ [1][1][2][1][RTW89_CHILE][10] = 46,
+ [1][1][2][1][RTW89_QATAR][10] = 36,
[1][1][2][1][RTW89_FCC][11] = 127,
[1][1][2][1][RTW89_ETSI][11] = 127,
[1][1][2][1][RTW89_MKK][11] = 127,
@@ -30090,6 +33734,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][1][RTW89_ACMA][11] = 127,
[1][1][2][1][RTW89_CN][11] = 127,
[1][1][2][1][RTW89_UK][11] = 127,
+ [1][1][2][1][RTW89_MEXICO][11] = 127,
+ [1][1][2][1][RTW89_UKRAINE][11] = 127,
+ [1][1][2][1][RTW89_CHILE][11] = 127,
+ [1][1][2][1][RTW89_QATAR][11] = 127,
[1][1][2][1][RTW89_FCC][12] = 127,
[1][1][2][1][RTW89_ETSI][12] = 127,
[1][1][2][1][RTW89_MKK][12] = 127,
@@ -30098,6 +33746,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][1][RTW89_ACMA][12] = 127,
[1][1][2][1][RTW89_CN][12] = 127,
[1][1][2][1][RTW89_UK][12] = 127,
+ [1][1][2][1][RTW89_MEXICO][12] = 127,
+ [1][1][2][1][RTW89_UKRAINE][12] = 127,
+ [1][1][2][1][RTW89_CHILE][12] = 127,
+ [1][1][2][1][RTW89_QATAR][12] = 127,
[1][1][2][1][RTW89_FCC][13] = 127,
[1][1][2][1][RTW89_ETSI][13] = 127,
[1][1][2][1][RTW89_MKK][13] = 127,
@@ -30106,6 +33758,10 @@ const s8 rtw89_8852c_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][1][RTW89_ACMA][13] = 127,
[1][1][2][1][RTW89_CN][13] = 127,
[1][1][2][1][RTW89_UK][13] = 127,
+ [1][1][2][1][RTW89_MEXICO][13] = 127,
+ [1][1][2][1][RTW89_UKRAINE][13] = 127,
+ [1][1][2][1][RTW89_CHILE][13] = 127,
+ [1][1][2][1][RTW89_QATAR][13] = 127,
};
static
@@ -30120,17 +33776,17 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_WW][10] = 50,
[0][0][1][0][RTW89_WW][12] = 50,
[0][0][1][0][RTW89_WW][14] = 50,
- [0][0][1][0][RTW89_WW][15] = 66,
- [0][0][1][0][RTW89_WW][17] = 66,
- [0][0][1][0][RTW89_WW][19] = 66,
- [0][0][1][0][RTW89_WW][21] = 66,
- [0][0][1][0][RTW89_WW][23] = 66,
- [0][0][1][0][RTW89_WW][25] = 66,
- [0][0][1][0][RTW89_WW][27] = 66,
- [0][0][1][0][RTW89_WW][29] = 66,
- [0][0][1][0][RTW89_WW][31] = 66,
- [0][0][1][0][RTW89_WW][33] = 66,
- [0][0][1][0][RTW89_WW][35] = 60,
+ [0][0][1][0][RTW89_WW][15] = 54,
+ [0][0][1][0][RTW89_WW][17] = 54,
+ [0][0][1][0][RTW89_WW][19] = 54,
+ [0][0][1][0][RTW89_WW][21] = 54,
+ [0][0][1][0][RTW89_WW][23] = 54,
+ [0][0][1][0][RTW89_WW][25] = 54,
+ [0][0][1][0][RTW89_WW][27] = 54,
+ [0][0][1][0][RTW89_WW][29] = 54,
+ [0][0][1][0][RTW89_WW][31] = 54,
+ [0][0][1][0][RTW89_WW][33] = 54,
+ [0][0][1][0][RTW89_WW][35] = 54,
[0][0][1][0][RTW89_WW][37] = 64,
[0][0][1][0][RTW89_WW][38] = 30,
[0][0][1][0][RTW89_WW][40] = 30,
@@ -30144,21 +33800,21 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_WW][2] = 34,
[0][1][1][0][RTW89_WW][4] = 34,
[0][1][1][0][RTW89_WW][6] = 36,
- [0][1][1][0][RTW89_WW][8] = 46,
- [0][1][1][0][RTW89_WW][10] = 46,
- [0][1][1][0][RTW89_WW][12] = 46,
- [0][1][1][0][RTW89_WW][14] = 46,
- [0][1][1][0][RTW89_WW][15] = 54,
- [0][1][1][0][RTW89_WW][17] = 54,
- [0][1][1][0][RTW89_WW][19] = 54,
- [0][1][1][0][RTW89_WW][21] = 54,
- [0][1][1][0][RTW89_WW][23] = 54,
- [0][1][1][0][RTW89_WW][25] = 54,
- [0][1][1][0][RTW89_WW][27] = 54,
- [0][1][1][0][RTW89_WW][29] = 54,
- [0][1][1][0][RTW89_WW][31] = 54,
- [0][1][1][0][RTW89_WW][33] = 54,
- [0][1][1][0][RTW89_WW][35] = 52,
+ [0][1][1][0][RTW89_WW][8] = 42,
+ [0][1][1][0][RTW89_WW][10] = 42,
+ [0][1][1][0][RTW89_WW][12] = 42,
+ [0][1][1][0][RTW89_WW][14] = 42,
+ [0][1][1][0][RTW89_WW][15] = 42,
+ [0][1][1][0][RTW89_WW][17] = 42,
+ [0][1][1][0][RTW89_WW][19] = 42,
+ [0][1][1][0][RTW89_WW][21] = 42,
+ [0][1][1][0][RTW89_WW][23] = 42,
+ [0][1][1][0][RTW89_WW][25] = 42,
+ [0][1][1][0][RTW89_WW][27] = 42,
+ [0][1][1][0][RTW89_WW][29] = 42,
+ [0][1][1][0][RTW89_WW][31] = 42,
+ [0][1][1][0][RTW89_WW][33] = 42,
+ [0][1][1][0][RTW89_WW][35] = 42,
[0][1][1][0][RTW89_WW][37] = 52,
[0][1][1][0][RTW89_WW][38] = 18,
[0][1][1][0][RTW89_WW][40] = 18,
@@ -30176,17 +33832,17 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_WW][10] = 52,
[0][0][2][0][RTW89_WW][12] = 52,
[0][0][2][0][RTW89_WW][14] = 52,
- [0][0][2][0][RTW89_WW][15] = 66,
- [0][0][2][0][RTW89_WW][17] = 66,
- [0][0][2][0][RTW89_WW][19] = 66,
- [0][0][2][0][RTW89_WW][21] = 66,
- [0][0][2][0][RTW89_WW][23] = 66,
- [0][0][2][0][RTW89_WW][25] = 66,
- [0][0][2][0][RTW89_WW][27] = 66,
- [0][0][2][0][RTW89_WW][29] = 66,
- [0][0][2][0][RTW89_WW][31] = 66,
- [0][0][2][0][RTW89_WW][33] = 66,
- [0][0][2][0][RTW89_WW][35] = 56,
+ [0][0][2][0][RTW89_WW][15] = 54,
+ [0][0][2][0][RTW89_WW][17] = 54,
+ [0][0][2][0][RTW89_WW][19] = 54,
+ [0][0][2][0][RTW89_WW][21] = 54,
+ [0][0][2][0][RTW89_WW][23] = 54,
+ [0][0][2][0][RTW89_WW][25] = 54,
+ [0][0][2][0][RTW89_WW][27] = 54,
+ [0][0][2][0][RTW89_WW][29] = 54,
+ [0][0][2][0][RTW89_WW][31] = 54,
+ [0][0][2][0][RTW89_WW][33] = 54,
+ [0][0][2][0][RTW89_WW][35] = 54,
[0][0][2][0][RTW89_WW][37] = 64,
[0][0][2][0][RTW89_WW][38] = 30,
[0][0][2][0][RTW89_WW][40] = 30,
@@ -30204,17 +33860,17 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_WW][10] = 40,
[0][1][2][0][RTW89_WW][12] = 40,
[0][1][2][0][RTW89_WW][14] = 40,
- [0][1][2][0][RTW89_WW][15] = 54,
- [0][1][2][0][RTW89_WW][17] = 54,
- [0][1][2][0][RTW89_WW][19] = 54,
- [0][1][2][0][RTW89_WW][21] = 54,
- [0][1][2][0][RTW89_WW][23] = 54,
- [0][1][2][0][RTW89_WW][25] = 54,
- [0][1][2][0][RTW89_WW][27] = 54,
- [0][1][2][0][RTW89_WW][29] = 54,
- [0][1][2][0][RTW89_WW][31] = 54,
- [0][1][2][0][RTW89_WW][33] = 54,
- [0][1][2][0][RTW89_WW][35] = 46,
+ [0][1][2][0][RTW89_WW][15] = 42,
+ [0][1][2][0][RTW89_WW][17] = 42,
+ [0][1][2][0][RTW89_WW][19] = 42,
+ [0][1][2][0][RTW89_WW][21] = 42,
+ [0][1][2][0][RTW89_WW][23] = 42,
+ [0][1][2][0][RTW89_WW][25] = 42,
+ [0][1][2][0][RTW89_WW][27] = 42,
+ [0][1][2][0][RTW89_WW][29] = 42,
+ [0][1][2][0][RTW89_WW][31] = 42,
+ [0][1][2][0][RTW89_WW][33] = 42,
+ [0][1][2][0][RTW89_WW][35] = 42,
[0][1][2][0][RTW89_WW][37] = 52,
[0][1][2][0][RTW89_WW][38] = 18,
[0][1][2][0][RTW89_WW][40] = 18,
@@ -30224,25 +33880,25 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_WW][48] = 48,
[0][1][2][0][RTW89_WW][50] = 50,
[0][1][2][0][RTW89_WW][52] = 48,
- [0][1][2][1][RTW89_WW][0] = 36,
- [0][1][2][1][RTW89_WW][2] = 36,
- [0][1][2][1][RTW89_WW][4] = 36,
- [0][1][2][1][RTW89_WW][6] = 36,
- [0][1][2][1][RTW89_WW][8] = 36,
- [0][1][2][1][RTW89_WW][10] = 36,
- [0][1][2][1][RTW89_WW][12] = 36,
- [0][1][2][1][RTW89_WW][14] = 36,
- [0][1][2][1][RTW89_WW][15] = 40,
- [0][1][2][1][RTW89_WW][17] = 40,
- [0][1][2][1][RTW89_WW][19] = 40,
- [0][1][2][1][RTW89_WW][21] = 40,
- [0][1][2][1][RTW89_WW][23] = 40,
- [0][1][2][1][RTW89_WW][25] = 40,
- [0][1][2][1][RTW89_WW][27] = 40,
- [0][1][2][1][RTW89_WW][29] = 40,
- [0][1][2][1][RTW89_WW][31] = 40,
- [0][1][2][1][RTW89_WW][33] = 40,
- [0][1][2][1][RTW89_WW][35] = 40,
+ [0][1][2][1][RTW89_WW][0] = 30,
+ [0][1][2][1][RTW89_WW][2] = 30,
+ [0][1][2][1][RTW89_WW][4] = 30,
+ [0][1][2][1][RTW89_WW][6] = 30,
+ [0][1][2][1][RTW89_WW][8] = 30,
+ [0][1][2][1][RTW89_WW][10] = 30,
+ [0][1][2][1][RTW89_WW][12] = 30,
+ [0][1][2][1][RTW89_WW][14] = 30,
+ [0][1][2][1][RTW89_WW][15] = 30,
+ [0][1][2][1][RTW89_WW][17] = 30,
+ [0][1][2][1][RTW89_WW][19] = 30,
+ [0][1][2][1][RTW89_WW][21] = 30,
+ [0][1][2][1][RTW89_WW][23] = 30,
+ [0][1][2][1][RTW89_WW][25] = 30,
+ [0][1][2][1][RTW89_WW][27] = 30,
+ [0][1][2][1][RTW89_WW][29] = 30,
+ [0][1][2][1][RTW89_WW][31] = 30,
+ [0][1][2][1][RTW89_WW][33] = 30,
+ [0][1][2][1][RTW89_WW][35] = 30,
[0][1][2][1][RTW89_WW][37] = 40,
[0][1][2][1][RTW89_WW][38] = 6,
[0][1][2][1][RTW89_WW][40] = 6,
@@ -30256,11 +33912,11 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_WW][5] = 54,
[1][0][2][0][RTW89_WW][9] = 54,
[1][0][2][0][RTW89_WW][13] = 52,
- [1][0][2][0][RTW89_WW][16] = 56,
- [1][0][2][0][RTW89_WW][20] = 56,
- [1][0][2][0][RTW89_WW][24] = 56,
- [1][0][2][0][RTW89_WW][28] = 66,
- [1][0][2][0][RTW89_WW][32] = 62,
+ [1][0][2][0][RTW89_WW][16] = 54,
+ [1][0][2][0][RTW89_WW][20] = 54,
+ [1][0][2][0][RTW89_WW][24] = 54,
+ [1][0][2][0][RTW89_WW][28] = 54,
+ [1][0][2][0][RTW89_WW][32] = 54,
[1][0][2][0][RTW89_WW][36] = 64,
[1][0][2][0][RTW89_WW][39] = 30,
[1][0][2][0][RTW89_WW][43] = 30,
@@ -30270,25 +33926,25 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][0][RTW89_WW][5] = 42,
[1][1][2][0][RTW89_WW][9] = 42,
[1][1][2][0][RTW89_WW][13] = 42,
- [1][1][2][0][RTW89_WW][16] = 54,
- [1][1][2][0][RTW89_WW][20] = 54,
- [1][1][2][0][RTW89_WW][24] = 54,
- [1][1][2][0][RTW89_WW][28] = 54,
- [1][1][2][0][RTW89_WW][32] = 54,
+ [1][1][2][0][RTW89_WW][16] = 42,
+ [1][1][2][0][RTW89_WW][20] = 42,
+ [1][1][2][0][RTW89_WW][24] = 42,
+ [1][1][2][0][RTW89_WW][28] = 42,
+ [1][1][2][0][RTW89_WW][32] = 42,
[1][1][2][0][RTW89_WW][36] = 52,
[1][1][2][0][RTW89_WW][39] = 18,
[1][1][2][0][RTW89_WW][43] = 18,
[1][1][2][0][RTW89_WW][47] = 62,
[1][1][2][0][RTW89_WW][51] = 60,
- [1][1][2][1][RTW89_WW][1] = 40,
- [1][1][2][1][RTW89_WW][5] = 40,
- [1][1][2][1][RTW89_WW][9] = 40,
- [1][1][2][1][RTW89_WW][13] = 40,
- [1][1][2][1][RTW89_WW][16] = 40,
- [1][1][2][1][RTW89_WW][20] = 40,
- [1][1][2][1][RTW89_WW][24] = 40,
- [1][1][2][1][RTW89_WW][28] = 40,
- [1][1][2][1][RTW89_WW][32] = 40,
+ [1][1][2][1][RTW89_WW][1] = 30,
+ [1][1][2][1][RTW89_WW][5] = 30,
+ [1][1][2][1][RTW89_WW][9] = 30,
+ [1][1][2][1][RTW89_WW][13] = 30,
+ [1][1][2][1][RTW89_WW][16] = 30,
+ [1][1][2][1][RTW89_WW][20] = 30,
+ [1][1][2][1][RTW89_WW][24] = 30,
+ [1][1][2][1][RTW89_WW][28] = 30,
+ [1][1][2][1][RTW89_WW][32] = 30,
[1][1][2][1][RTW89_WW][36] = 40,
[1][1][2][1][RTW89_WW][39] = 6,
[1][1][2][1][RTW89_WW][43] = 6,
@@ -30296,22 +33952,22 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][1][RTW89_WW][51] = 60,
[2][0][2][0][RTW89_WW][3] = 54,
[2][0][2][0][RTW89_WW][11] = 50,
- [2][0][2][0][RTW89_WW][18] = 56,
- [2][0][2][0][RTW89_WW][26] = 60,
+ [2][0][2][0][RTW89_WW][18] = 54,
+ [2][0][2][0][RTW89_WW][26] = 54,
[2][0][2][0][RTW89_WW][34] = 60,
[2][0][2][0][RTW89_WW][41] = 30,
[2][0][2][0][RTW89_WW][49] = 62,
- [2][1][2][0][RTW89_WW][3] = 46,
+ [2][1][2][0][RTW89_WW][3] = 42,
[2][1][2][0][RTW89_WW][11] = 38,
- [2][1][2][0][RTW89_WW][18] = 50,
- [2][1][2][0][RTW89_WW][26] = 52,
+ [2][1][2][0][RTW89_WW][18] = 42,
+ [2][1][2][0][RTW89_WW][26] = 42,
[2][1][2][0][RTW89_WW][34] = 52,
[2][1][2][0][RTW89_WW][41] = 18,
[2][1][2][0][RTW89_WW][49] = 62,
- [2][1][2][1][RTW89_WW][3] = 40,
- [2][1][2][1][RTW89_WW][11] = 38,
- [2][1][2][1][RTW89_WW][18] = 40,
- [2][1][2][1][RTW89_WW][26] = 42,
+ [2][1][2][1][RTW89_WW][3] = 30,
+ [2][1][2][1][RTW89_WW][11] = 30,
+ [2][1][2][1][RTW89_WW][18] = 30,
+ [2][1][2][1][RTW89_WW][26] = 30,
[2][1][2][1][RTW89_WW][34] = 40,
[2][1][2][1][RTW89_WW][41] = 6,
[2][1][2][1][RTW89_WW][49] = 62,
@@ -30328,34 +33984,50 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ETSI][0] = 66,
[0][0][1][0][RTW89_MKK][0] = 66,
[0][0][1][0][RTW89_IC][0] = 60,
- [0][0][1][0][RTW89_KCC][0] = 52,
+ [0][0][1][0][RTW89_KCC][0] = 62,
[0][0][1][0][RTW89_ACMA][0] = 66,
[0][0][1][0][RTW89_CN][0] = 50,
[0][0][1][0][RTW89_UK][0] = 66,
+ [0][0][1][0][RTW89_MEXICO][0] = 62,
+ [0][0][1][0][RTW89_UKRAINE][0] = 54,
+ [0][0][1][0][RTW89_CHILE][0] = 70,
+ [0][0][1][0][RTW89_QATAR][0] = 66,
[0][0][1][0][RTW89_FCC][2] = 72,
[0][0][1][0][RTW89_ETSI][2] = 66,
[0][0][1][0][RTW89_MKK][2] = 66,
[0][0][1][0][RTW89_IC][2] = 60,
- [0][0][1][0][RTW89_KCC][2] = 52,
+ [0][0][1][0][RTW89_KCC][2] = 62,
[0][0][1][0][RTW89_ACMA][2] = 66,
[0][0][1][0][RTW89_CN][2] = 50,
[0][0][1][0][RTW89_UK][2] = 66,
+ [0][0][1][0][RTW89_MEXICO][2] = 62,
+ [0][0][1][0][RTW89_UKRAINE][2] = 54,
+ [0][0][1][0][RTW89_CHILE][2] = 70,
+ [0][0][1][0][RTW89_QATAR][2] = 66,
[0][0][1][0][RTW89_FCC][4] = 72,
[0][0][1][0][RTW89_ETSI][4] = 66,
[0][0][1][0][RTW89_MKK][4] = 66,
[0][0][1][0][RTW89_IC][4] = 60,
- [0][0][1][0][RTW89_KCC][4] = 52,
+ [0][0][1][0][RTW89_KCC][4] = 62,
[0][0][1][0][RTW89_ACMA][4] = 66,
[0][0][1][0][RTW89_CN][4] = 50,
[0][0][1][0][RTW89_UK][4] = 66,
+ [0][0][1][0][RTW89_MEXICO][4] = 62,
+ [0][0][1][0][RTW89_UKRAINE][4] = 54,
+ [0][0][1][0][RTW89_CHILE][4] = 70,
+ [0][0][1][0][RTW89_QATAR][4] = 66,
[0][0][1][0][RTW89_FCC][6] = 72,
[0][0][1][0][RTW89_ETSI][6] = 66,
[0][0][1][0][RTW89_MKK][6] = 66,
[0][0][1][0][RTW89_IC][6] = 58,
- [0][0][1][0][RTW89_KCC][6] = 62,
+ [0][0][1][0][RTW89_KCC][6] = 52,
[0][0][1][0][RTW89_ACMA][6] = 66,
[0][0][1][0][RTW89_CN][6] = 50,
[0][0][1][0][RTW89_UK][6] = 66,
+ [0][0][1][0][RTW89_MEXICO][6] = 62,
+ [0][0][1][0][RTW89_UKRAINE][6] = 54,
+ [0][0][1][0][RTW89_CHILE][6] = 70,
+ [0][0][1][0][RTW89_QATAR][6] = 66,
[0][0][1][0][RTW89_FCC][8] = 72,
[0][0][1][0][RTW89_ETSI][8] = 66,
[0][0][1][0][RTW89_MKK][8] = 66,
@@ -30364,6 +34036,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][8] = 66,
[0][0][1][0][RTW89_CN][8] = 50,
[0][0][1][0][RTW89_UK][8] = 66,
+ [0][0][1][0][RTW89_MEXICO][8] = 72,
+ [0][0][1][0][RTW89_UKRAINE][8] = 54,
+ [0][0][1][0][RTW89_CHILE][8] = 70,
+ [0][0][1][0][RTW89_QATAR][8] = 66,
[0][0][1][0][RTW89_FCC][10] = 72,
[0][0][1][0][RTW89_ETSI][10] = 66,
[0][0][1][0][RTW89_MKK][10] = 66,
@@ -30372,6 +34048,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][10] = 66,
[0][0][1][0][RTW89_CN][10] = 50,
[0][0][1][0][RTW89_UK][10] = 66,
+ [0][0][1][0][RTW89_MEXICO][10] = 72,
+ [0][0][1][0][RTW89_UKRAINE][10] = 54,
+ [0][0][1][0][RTW89_CHILE][10] = 70,
+ [0][0][1][0][RTW89_QATAR][10] = 66,
[0][0][1][0][RTW89_FCC][12] = 72,
[0][0][1][0][RTW89_ETSI][12] = 66,
[0][0][1][0][RTW89_MKK][12] = 66,
@@ -30380,6 +34060,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][12] = 66,
[0][0][1][0][RTW89_CN][12] = 50,
[0][0][1][0][RTW89_UK][12] = 66,
+ [0][0][1][0][RTW89_MEXICO][12] = 72,
+ [0][0][1][0][RTW89_UKRAINE][12] = 54,
+ [0][0][1][0][RTW89_CHILE][12] = 70,
+ [0][0][1][0][RTW89_QATAR][12] = 66,
[0][0][1][0][RTW89_FCC][14] = 70,
[0][0][1][0][RTW89_ETSI][14] = 66,
[0][0][1][0][RTW89_MKK][14] = 66,
@@ -30388,6 +34072,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][14] = 66,
[0][0][1][0][RTW89_CN][14] = 50,
[0][0][1][0][RTW89_UK][14] = 66,
+ [0][0][1][0][RTW89_MEXICO][14] = 70,
+ [0][0][1][0][RTW89_UKRAINE][14] = 54,
+ [0][0][1][0][RTW89_CHILE][14] = 68,
+ [0][0][1][0][RTW89_QATAR][14] = 66,
[0][0][1][0][RTW89_FCC][15] = 72,
[0][0][1][0][RTW89_ETSI][15] = 66,
[0][0][1][0][RTW89_MKK][15] = 70,
@@ -30396,6 +34084,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][15] = 66,
[0][0][1][0][RTW89_CN][15] = 127,
[0][0][1][0][RTW89_UK][15] = 66,
+ [0][0][1][0][RTW89_MEXICO][15] = 72,
+ [0][0][1][0][RTW89_UKRAINE][15] = 54,
+ [0][0][1][0][RTW89_CHILE][15] = 70,
+ [0][0][1][0][RTW89_QATAR][15] = 66,
[0][0][1][0][RTW89_FCC][17] = 72,
[0][0][1][0][RTW89_ETSI][17] = 66,
[0][0][1][0][RTW89_MKK][17] = 70,
@@ -30404,6 +34096,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][17] = 66,
[0][0][1][0][RTW89_CN][17] = 127,
[0][0][1][0][RTW89_UK][17] = 66,
+ [0][0][1][0][RTW89_MEXICO][17] = 72,
+ [0][0][1][0][RTW89_UKRAINE][17] = 54,
+ [0][0][1][0][RTW89_CHILE][17] = 70,
+ [0][0][1][0][RTW89_QATAR][17] = 66,
[0][0][1][0][RTW89_FCC][19] = 72,
[0][0][1][0][RTW89_ETSI][19] = 66,
[0][0][1][0][RTW89_MKK][19] = 70,
@@ -30412,6 +34108,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][19] = 66,
[0][0][1][0][RTW89_CN][19] = 127,
[0][0][1][0][RTW89_UK][19] = 66,
+ [0][0][1][0][RTW89_MEXICO][19] = 72,
+ [0][0][1][0][RTW89_UKRAINE][19] = 54,
+ [0][0][1][0][RTW89_CHILE][19] = 70,
+ [0][0][1][0][RTW89_QATAR][19] = 66,
[0][0][1][0][RTW89_FCC][21] = 72,
[0][0][1][0][RTW89_ETSI][21] = 66,
[0][0][1][0][RTW89_MKK][21] = 70,
@@ -30420,6 +34120,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][21] = 66,
[0][0][1][0][RTW89_CN][21] = 127,
[0][0][1][0][RTW89_UK][21] = 66,
+ [0][0][1][0][RTW89_MEXICO][21] = 72,
+ [0][0][1][0][RTW89_UKRAINE][21] = 54,
+ [0][0][1][0][RTW89_CHILE][21] = 70,
+ [0][0][1][0][RTW89_QATAR][21] = 66,
[0][0][1][0][RTW89_FCC][23] = 72,
[0][0][1][0][RTW89_ETSI][23] = 66,
[0][0][1][0][RTW89_MKK][23] = 70,
@@ -30428,6 +34132,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][23] = 66,
[0][0][1][0][RTW89_CN][23] = 127,
[0][0][1][0][RTW89_UK][23] = 66,
+ [0][0][1][0][RTW89_MEXICO][23] = 72,
+ [0][0][1][0][RTW89_UKRAINE][23] = 54,
+ [0][0][1][0][RTW89_CHILE][23] = 70,
+ [0][0][1][0][RTW89_QATAR][23] = 66,
[0][0][1][0][RTW89_FCC][25] = 72,
[0][0][1][0][RTW89_ETSI][25] = 66,
[0][0][1][0][RTW89_MKK][25] = 70,
@@ -30436,6 +34144,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][25] = 127,
[0][0][1][0][RTW89_CN][25] = 127,
[0][0][1][0][RTW89_UK][25] = 66,
+ [0][0][1][0][RTW89_MEXICO][25] = 72,
+ [0][0][1][0][RTW89_UKRAINE][25] = 54,
+ [0][0][1][0][RTW89_CHILE][25] = 70,
+ [0][0][1][0][RTW89_QATAR][25] = 66,
[0][0][1][0][RTW89_FCC][27] = 72,
[0][0][1][0][RTW89_ETSI][27] = 66,
[0][0][1][0][RTW89_MKK][27] = 70,
@@ -30444,6 +34156,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][27] = 127,
[0][0][1][0][RTW89_CN][27] = 127,
[0][0][1][0][RTW89_UK][27] = 66,
+ [0][0][1][0][RTW89_MEXICO][27] = 72,
+ [0][0][1][0][RTW89_UKRAINE][27] = 54,
+ [0][0][1][0][RTW89_CHILE][27] = 58,
+ [0][0][1][0][RTW89_QATAR][27] = 66,
[0][0][1][0][RTW89_FCC][29] = 72,
[0][0][1][0][RTW89_ETSI][29] = 66,
[0][0][1][0][RTW89_MKK][29] = 70,
@@ -30452,6 +34168,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][29] = 127,
[0][0][1][0][RTW89_CN][29] = 127,
[0][0][1][0][RTW89_UK][29] = 66,
+ [0][0][1][0][RTW89_MEXICO][29] = 72,
+ [0][0][1][0][RTW89_UKRAINE][29] = 54,
+ [0][0][1][0][RTW89_CHILE][29] = 58,
+ [0][0][1][0][RTW89_QATAR][29] = 66,
[0][0][1][0][RTW89_FCC][31] = 72,
[0][0][1][0][RTW89_ETSI][31] = 66,
[0][0][1][0][RTW89_MKK][31] = 70,
@@ -30460,6 +34180,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][31] = 66,
[0][0][1][0][RTW89_CN][31] = 127,
[0][0][1][0][RTW89_UK][31] = 66,
+ [0][0][1][0][RTW89_MEXICO][31] = 72,
+ [0][0][1][0][RTW89_UKRAINE][31] = 54,
+ [0][0][1][0][RTW89_CHILE][31] = 58,
+ [0][0][1][0][RTW89_QATAR][31] = 66,
[0][0][1][0][RTW89_FCC][33] = 72,
[0][0][1][0][RTW89_ETSI][33] = 66,
[0][0][1][0][RTW89_MKK][33] = 70,
@@ -30468,6 +34192,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][33] = 66,
[0][0][1][0][RTW89_CN][33] = 127,
[0][0][1][0][RTW89_UK][33] = 66,
+ [0][0][1][0][RTW89_MEXICO][33] = 72,
+ [0][0][1][0][RTW89_UKRAINE][33] = 54,
+ [0][0][1][0][RTW89_CHILE][33] = 58,
+ [0][0][1][0][RTW89_QATAR][33] = 66,
[0][0][1][0][RTW89_FCC][35] = 60,
[0][0][1][0][RTW89_ETSI][35] = 66,
[0][0][1][0][RTW89_MKK][35] = 70,
@@ -30476,6 +34204,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][35] = 66,
[0][0][1][0][RTW89_CN][35] = 127,
[0][0][1][0][RTW89_UK][35] = 66,
+ [0][0][1][0][RTW89_MEXICO][35] = 60,
+ [0][0][1][0][RTW89_UKRAINE][35] = 54,
+ [0][0][1][0][RTW89_CHILE][35] = 58,
+ [0][0][1][0][RTW89_QATAR][35] = 66,
[0][0][1][0][RTW89_FCC][37] = 72,
[0][0][1][0][RTW89_ETSI][37] = 127,
[0][0][1][0][RTW89_MKK][37] = 70,
@@ -30484,6 +34216,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][37] = 70,
[0][0][1][0][RTW89_CN][37] = 127,
[0][0][1][0][RTW89_UK][37] = 64,
+ [0][0][1][0][RTW89_MEXICO][37] = 72,
+ [0][0][1][0][RTW89_UKRAINE][37] = 127,
+ [0][0][1][0][RTW89_CHILE][37] = 70,
+ [0][0][1][0][RTW89_QATAR][37] = 127,
[0][0][1][0][RTW89_FCC][38] = 72,
[0][0][1][0][RTW89_ETSI][38] = 30,
[0][0][1][0][RTW89_MKK][38] = 127,
@@ -30492,6 +34228,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][38] = 70,
[0][0][1][0][RTW89_CN][38] = 68,
[0][0][1][0][RTW89_UK][38] = 64,
+ [0][0][1][0][RTW89_MEXICO][38] = 72,
+ [0][0][1][0][RTW89_UKRAINE][38] = 30,
+ [0][0][1][0][RTW89_CHILE][38] = 70,
+ [0][0][1][0][RTW89_QATAR][38] = 30,
[0][0][1][0][RTW89_FCC][40] = 72,
[0][0][1][0][RTW89_ETSI][40] = 30,
[0][0][1][0][RTW89_MKK][40] = 127,
@@ -30500,6 +34240,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][40] = 70,
[0][0][1][0][RTW89_CN][40] = 68,
[0][0][1][0][RTW89_UK][40] = 64,
+ [0][0][1][0][RTW89_MEXICO][40] = 72,
+ [0][0][1][0][RTW89_UKRAINE][40] = 30,
+ [0][0][1][0][RTW89_CHILE][40] = 70,
+ [0][0][1][0][RTW89_QATAR][40] = 30,
[0][0][1][0][RTW89_FCC][42] = 72,
[0][0][1][0][RTW89_ETSI][42] = 30,
[0][0][1][0][RTW89_MKK][42] = 127,
@@ -30508,6 +34252,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][42] = 70,
[0][0][1][0][RTW89_CN][42] = 68,
[0][0][1][0][RTW89_UK][42] = 64,
+ [0][0][1][0][RTW89_MEXICO][42] = 72,
+ [0][0][1][0][RTW89_UKRAINE][42] = 30,
+ [0][0][1][0][RTW89_CHILE][42] = 70,
+ [0][0][1][0][RTW89_QATAR][42] = 30,
[0][0][1][0][RTW89_FCC][44] = 72,
[0][0][1][0][RTW89_ETSI][44] = 30,
[0][0][1][0][RTW89_MKK][44] = 127,
@@ -30516,6 +34264,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][44] = 70,
[0][0][1][0][RTW89_CN][44] = 68,
[0][0][1][0][RTW89_UK][44] = 64,
+ [0][0][1][0][RTW89_MEXICO][44] = 72,
+ [0][0][1][0][RTW89_UKRAINE][44] = 30,
+ [0][0][1][0][RTW89_CHILE][44] = 70,
+ [0][0][1][0][RTW89_QATAR][44] = 30,
[0][0][1][0][RTW89_FCC][46] = 72,
[0][0][1][0][RTW89_ETSI][46] = 30,
[0][0][1][0][RTW89_MKK][46] = 127,
@@ -30524,6 +34276,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][46] = 70,
[0][0][1][0][RTW89_CN][46] = 68,
[0][0][1][0][RTW89_UK][46] = 64,
+ [0][0][1][0][RTW89_MEXICO][46] = 72,
+ [0][0][1][0][RTW89_UKRAINE][46] = 30,
+ [0][0][1][0][RTW89_CHILE][46] = 70,
+ [0][0][1][0][RTW89_QATAR][46] = 30,
[0][0][1][0][RTW89_FCC][48] = 72,
[0][0][1][0][RTW89_ETSI][48] = 127,
[0][0][1][0][RTW89_MKK][48] = 127,
@@ -30532,6 +34288,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][48] = 127,
[0][0][1][0][RTW89_CN][48] = 127,
[0][0][1][0][RTW89_UK][48] = 127,
+ [0][0][1][0][RTW89_MEXICO][48] = 127,
+ [0][0][1][0][RTW89_UKRAINE][48] = 127,
+ [0][0][1][0][RTW89_CHILE][48] = 127,
+ [0][0][1][0][RTW89_QATAR][48] = 127,
[0][0][1][0][RTW89_FCC][50] = 72,
[0][0][1][0][RTW89_ETSI][50] = 127,
[0][0][1][0][RTW89_MKK][50] = 127,
@@ -30540,6 +34300,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][50] = 127,
[0][0][1][0][RTW89_CN][50] = 127,
[0][0][1][0][RTW89_UK][50] = 127,
+ [0][0][1][0][RTW89_MEXICO][50] = 127,
+ [0][0][1][0][RTW89_UKRAINE][50] = 127,
+ [0][0][1][0][RTW89_CHILE][50] = 127,
+ [0][0][1][0][RTW89_QATAR][50] = 127,
[0][0][1][0][RTW89_FCC][52] = 72,
[0][0][1][0][RTW89_ETSI][52] = 127,
[0][0][1][0][RTW89_MKK][52] = 127,
@@ -30548,38 +34312,58 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][1][0][RTW89_ACMA][52] = 127,
[0][0][1][0][RTW89_CN][52] = 127,
[0][0][1][0][RTW89_UK][52] = 127,
+ [0][0][1][0][RTW89_MEXICO][52] = 127,
+ [0][0][1][0][RTW89_UKRAINE][52] = 127,
+ [0][0][1][0][RTW89_CHILE][52] = 127,
+ [0][0][1][0][RTW89_QATAR][52] = 127,
[0][1][1][0][RTW89_FCC][0] = 60,
[0][1][1][0][RTW89_ETSI][0] = 54,
[0][1][1][0][RTW89_MKK][0] = 54,
[0][1][1][0][RTW89_IC][0] = 34,
- [0][1][1][0][RTW89_KCC][0] = 40,
+ [0][1][1][0][RTW89_KCC][0] = 60,
[0][1][1][0][RTW89_ACMA][0] = 54,
[0][1][1][0][RTW89_CN][0] = 46,
[0][1][1][0][RTW89_UK][0] = 54,
+ [0][1][1][0][RTW89_MEXICO][0] = 50,
+ [0][1][1][0][RTW89_UKRAINE][0] = 42,
+ [0][1][1][0][RTW89_CHILE][0] = 60,
+ [0][1][1][0][RTW89_QATAR][0] = 54,
[0][1][1][0][RTW89_FCC][2] = 60,
[0][1][1][0][RTW89_ETSI][2] = 54,
[0][1][1][0][RTW89_MKK][2] = 54,
[0][1][1][0][RTW89_IC][2] = 34,
- [0][1][1][0][RTW89_KCC][2] = 40,
+ [0][1][1][0][RTW89_KCC][2] = 60,
[0][1][1][0][RTW89_ACMA][2] = 54,
[0][1][1][0][RTW89_CN][2] = 46,
[0][1][1][0][RTW89_UK][2] = 54,
+ [0][1][1][0][RTW89_MEXICO][2] = 50,
+ [0][1][1][0][RTW89_UKRAINE][2] = 42,
+ [0][1][1][0][RTW89_CHILE][2] = 60,
+ [0][1][1][0][RTW89_QATAR][2] = 54,
[0][1][1][0][RTW89_FCC][4] = 60,
[0][1][1][0][RTW89_ETSI][4] = 54,
[0][1][1][0][RTW89_MKK][4] = 54,
[0][1][1][0][RTW89_IC][4] = 34,
- [0][1][1][0][RTW89_KCC][4] = 40,
+ [0][1][1][0][RTW89_KCC][4] = 60,
[0][1][1][0][RTW89_ACMA][4] = 54,
[0][1][1][0][RTW89_CN][4] = 46,
[0][1][1][0][RTW89_UK][4] = 54,
+ [0][1][1][0][RTW89_MEXICO][4] = 50,
+ [0][1][1][0][RTW89_UKRAINE][4] = 42,
+ [0][1][1][0][RTW89_CHILE][4] = 60,
+ [0][1][1][0][RTW89_QATAR][4] = 54,
[0][1][1][0][RTW89_FCC][6] = 60,
[0][1][1][0][RTW89_ETSI][6] = 54,
[0][1][1][0][RTW89_MKK][6] = 54,
[0][1][1][0][RTW89_IC][6] = 36,
- [0][1][1][0][RTW89_KCC][6] = 60,
+ [0][1][1][0][RTW89_KCC][6] = 40,
[0][1][1][0][RTW89_ACMA][6] = 54,
[0][1][1][0][RTW89_CN][6] = 46,
[0][1][1][0][RTW89_UK][6] = 54,
+ [0][1][1][0][RTW89_MEXICO][6] = 50,
+ [0][1][1][0][RTW89_UKRAINE][6] = 42,
+ [0][1][1][0][RTW89_CHILE][6] = 60,
+ [0][1][1][0][RTW89_QATAR][6] = 54,
[0][1][1][0][RTW89_FCC][8] = 62,
[0][1][1][0][RTW89_ETSI][8] = 54,
[0][1][1][0][RTW89_MKK][8] = 52,
@@ -30588,6 +34372,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][8] = 54,
[0][1][1][0][RTW89_CN][8] = 46,
[0][1][1][0][RTW89_UK][8] = 54,
+ [0][1][1][0][RTW89_MEXICO][8] = 62,
+ [0][1][1][0][RTW89_UKRAINE][8] = 42,
+ [0][1][1][0][RTW89_CHILE][8] = 62,
+ [0][1][1][0][RTW89_QATAR][8] = 54,
[0][1][1][0][RTW89_FCC][10] = 62,
[0][1][1][0][RTW89_ETSI][10] = 54,
[0][1][1][0][RTW89_MKK][10] = 54,
@@ -30596,6 +34384,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][10] = 54,
[0][1][1][0][RTW89_CN][10] = 46,
[0][1][1][0][RTW89_UK][10] = 54,
+ [0][1][1][0][RTW89_MEXICO][10] = 62,
+ [0][1][1][0][RTW89_UKRAINE][10] = 42,
+ [0][1][1][0][RTW89_CHILE][10] = 62,
+ [0][1][1][0][RTW89_QATAR][10] = 54,
[0][1][1][0][RTW89_FCC][12] = 62,
[0][1][1][0][RTW89_ETSI][12] = 54,
[0][1][1][0][RTW89_MKK][12] = 54,
@@ -30604,6 +34396,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][12] = 54,
[0][1][1][0][RTW89_CN][12] = 46,
[0][1][1][0][RTW89_UK][12] = 54,
+ [0][1][1][0][RTW89_MEXICO][12] = 62,
+ [0][1][1][0][RTW89_UKRAINE][12] = 42,
+ [0][1][1][0][RTW89_CHILE][12] = 62,
+ [0][1][1][0][RTW89_QATAR][12] = 54,
[0][1][1][0][RTW89_FCC][14] = 60,
[0][1][1][0][RTW89_ETSI][14] = 54,
[0][1][1][0][RTW89_MKK][14] = 54,
@@ -30612,6 +34408,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][14] = 54,
[0][1][1][0][RTW89_CN][14] = 46,
[0][1][1][0][RTW89_UK][14] = 54,
+ [0][1][1][0][RTW89_MEXICO][14] = 60,
+ [0][1][1][0][RTW89_UKRAINE][14] = 42,
+ [0][1][1][0][RTW89_CHILE][14] = 60,
+ [0][1][1][0][RTW89_QATAR][14] = 54,
[0][1][1][0][RTW89_FCC][15] = 60,
[0][1][1][0][RTW89_ETSI][15] = 54,
[0][1][1][0][RTW89_MKK][15] = 70,
@@ -30620,6 +34420,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][15] = 54,
[0][1][1][0][RTW89_CN][15] = 127,
[0][1][1][0][RTW89_UK][15] = 54,
+ [0][1][1][0][RTW89_MEXICO][15] = 60,
+ [0][1][1][0][RTW89_UKRAINE][15] = 42,
+ [0][1][1][0][RTW89_CHILE][15] = 60,
+ [0][1][1][0][RTW89_QATAR][15] = 54,
[0][1][1][0][RTW89_FCC][17] = 60,
[0][1][1][0][RTW89_ETSI][17] = 54,
[0][1][1][0][RTW89_MKK][17] = 70,
@@ -30628,6 +34432,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][17] = 54,
[0][1][1][0][RTW89_CN][17] = 127,
[0][1][1][0][RTW89_UK][17] = 54,
+ [0][1][1][0][RTW89_MEXICO][17] = 60,
+ [0][1][1][0][RTW89_UKRAINE][17] = 42,
+ [0][1][1][0][RTW89_CHILE][17] = 60,
+ [0][1][1][0][RTW89_QATAR][17] = 54,
[0][1][1][0][RTW89_FCC][19] = 60,
[0][1][1][0][RTW89_ETSI][19] = 54,
[0][1][1][0][RTW89_MKK][19] = 70,
@@ -30636,6 +34444,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][19] = 54,
[0][1][1][0][RTW89_CN][19] = 127,
[0][1][1][0][RTW89_UK][19] = 54,
+ [0][1][1][0][RTW89_MEXICO][19] = 60,
+ [0][1][1][0][RTW89_UKRAINE][19] = 42,
+ [0][1][1][0][RTW89_CHILE][19] = 60,
+ [0][1][1][0][RTW89_QATAR][19] = 54,
[0][1][1][0][RTW89_FCC][21] = 60,
[0][1][1][0][RTW89_ETSI][21] = 54,
[0][1][1][0][RTW89_MKK][21] = 70,
@@ -30644,6 +34456,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][21] = 54,
[0][1][1][0][RTW89_CN][21] = 127,
[0][1][1][0][RTW89_UK][21] = 54,
+ [0][1][1][0][RTW89_MEXICO][21] = 60,
+ [0][1][1][0][RTW89_UKRAINE][21] = 42,
+ [0][1][1][0][RTW89_CHILE][21] = 60,
+ [0][1][1][0][RTW89_QATAR][21] = 54,
[0][1][1][0][RTW89_FCC][23] = 60,
[0][1][1][0][RTW89_ETSI][23] = 54,
[0][1][1][0][RTW89_MKK][23] = 70,
@@ -30652,6 +34468,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][23] = 54,
[0][1][1][0][RTW89_CN][23] = 127,
[0][1][1][0][RTW89_UK][23] = 54,
+ [0][1][1][0][RTW89_MEXICO][23] = 60,
+ [0][1][1][0][RTW89_UKRAINE][23] = 42,
+ [0][1][1][0][RTW89_CHILE][23] = 60,
+ [0][1][1][0][RTW89_QATAR][23] = 54,
[0][1][1][0][RTW89_FCC][25] = 60,
[0][1][1][0][RTW89_ETSI][25] = 54,
[0][1][1][0][RTW89_MKK][25] = 70,
@@ -30660,6 +34480,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][25] = 127,
[0][1][1][0][RTW89_CN][25] = 127,
[0][1][1][0][RTW89_UK][25] = 54,
+ [0][1][1][0][RTW89_MEXICO][25] = 60,
+ [0][1][1][0][RTW89_UKRAINE][25] = 42,
+ [0][1][1][0][RTW89_CHILE][25] = 60,
+ [0][1][1][0][RTW89_QATAR][25] = 54,
[0][1][1][0][RTW89_FCC][27] = 60,
[0][1][1][0][RTW89_ETSI][27] = 54,
[0][1][1][0][RTW89_MKK][27] = 70,
@@ -30668,6 +34492,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][27] = 127,
[0][1][1][0][RTW89_CN][27] = 127,
[0][1][1][0][RTW89_UK][27] = 54,
+ [0][1][1][0][RTW89_MEXICO][27] = 60,
+ [0][1][1][0][RTW89_UKRAINE][27] = 42,
+ [0][1][1][0][RTW89_CHILE][27] = 52,
+ [0][1][1][0][RTW89_QATAR][27] = 54,
[0][1][1][0][RTW89_FCC][29] = 60,
[0][1][1][0][RTW89_ETSI][29] = 54,
[0][1][1][0][RTW89_MKK][29] = 70,
@@ -30676,6 +34504,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][29] = 127,
[0][1][1][0][RTW89_CN][29] = 127,
[0][1][1][0][RTW89_UK][29] = 54,
+ [0][1][1][0][RTW89_MEXICO][29] = 60,
+ [0][1][1][0][RTW89_UKRAINE][29] = 42,
+ [0][1][1][0][RTW89_CHILE][29] = 52,
+ [0][1][1][0][RTW89_QATAR][29] = 54,
[0][1][1][0][RTW89_FCC][31] = 60,
[0][1][1][0][RTW89_ETSI][31] = 54,
[0][1][1][0][RTW89_MKK][31] = 70,
@@ -30684,6 +34516,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][31] = 54,
[0][1][1][0][RTW89_CN][31] = 127,
[0][1][1][0][RTW89_UK][31] = 54,
+ [0][1][1][0][RTW89_MEXICO][31] = 60,
+ [0][1][1][0][RTW89_UKRAINE][31] = 42,
+ [0][1][1][0][RTW89_CHILE][31] = 52,
+ [0][1][1][0][RTW89_QATAR][31] = 54,
[0][1][1][0][RTW89_FCC][33] = 60,
[0][1][1][0][RTW89_ETSI][33] = 54,
[0][1][1][0][RTW89_MKK][33] = 70,
@@ -30692,6 +34528,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][33] = 54,
[0][1][1][0][RTW89_CN][33] = 127,
[0][1][1][0][RTW89_UK][33] = 54,
+ [0][1][1][0][RTW89_MEXICO][33] = 60,
+ [0][1][1][0][RTW89_UKRAINE][33] = 42,
+ [0][1][1][0][RTW89_CHILE][33] = 52,
+ [0][1][1][0][RTW89_QATAR][33] = 54,
[0][1][1][0][RTW89_FCC][35] = 52,
[0][1][1][0][RTW89_ETSI][35] = 54,
[0][1][1][0][RTW89_MKK][35] = 70,
@@ -30700,6 +34540,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][35] = 54,
[0][1][1][0][RTW89_CN][35] = 127,
[0][1][1][0][RTW89_UK][35] = 54,
+ [0][1][1][0][RTW89_MEXICO][35] = 52,
+ [0][1][1][0][RTW89_UKRAINE][35] = 42,
+ [0][1][1][0][RTW89_CHILE][35] = 52,
+ [0][1][1][0][RTW89_QATAR][35] = 54,
[0][1][1][0][RTW89_FCC][37] = 62,
[0][1][1][0][RTW89_ETSI][37] = 127,
[0][1][1][0][RTW89_MKK][37] = 70,
@@ -30708,6 +34552,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][37] = 64,
[0][1][1][0][RTW89_CN][37] = 127,
[0][1][1][0][RTW89_UK][37] = 52,
+ [0][1][1][0][RTW89_MEXICO][37] = 62,
+ [0][1][1][0][RTW89_UKRAINE][37] = 127,
+ [0][1][1][0][RTW89_CHILE][37] = 62,
+ [0][1][1][0][RTW89_QATAR][37] = 127,
[0][1][1][0][RTW89_FCC][38] = 72,
[0][1][1][0][RTW89_ETSI][38] = 18,
[0][1][1][0][RTW89_MKK][38] = 127,
@@ -30716,6 +34564,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][38] = 70,
[0][1][1][0][RTW89_CN][38] = 64,
[0][1][1][0][RTW89_UK][38] = 52,
+ [0][1][1][0][RTW89_MEXICO][38] = 72,
+ [0][1][1][0][RTW89_UKRAINE][38] = 18,
+ [0][1][1][0][RTW89_CHILE][38] = 70,
+ [0][1][1][0][RTW89_QATAR][38] = 18,
[0][1][1][0][RTW89_FCC][40] = 72,
[0][1][1][0][RTW89_ETSI][40] = 18,
[0][1][1][0][RTW89_MKK][40] = 127,
@@ -30724,6 +34576,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][40] = 70,
[0][1][1][0][RTW89_CN][40] = 64,
[0][1][1][0][RTW89_UK][40] = 52,
+ [0][1][1][0][RTW89_MEXICO][40] = 72,
+ [0][1][1][0][RTW89_UKRAINE][40] = 18,
+ [0][1][1][0][RTW89_CHILE][40] = 70,
+ [0][1][1][0][RTW89_QATAR][40] = 18,
[0][1][1][0][RTW89_FCC][42] = 72,
[0][1][1][0][RTW89_ETSI][42] = 18,
[0][1][1][0][RTW89_MKK][42] = 127,
@@ -30732,6 +34588,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][42] = 70,
[0][1][1][0][RTW89_CN][42] = 64,
[0][1][1][0][RTW89_UK][42] = 52,
+ [0][1][1][0][RTW89_MEXICO][42] = 72,
+ [0][1][1][0][RTW89_UKRAINE][42] = 18,
+ [0][1][1][0][RTW89_CHILE][42] = 70,
+ [0][1][1][0][RTW89_QATAR][42] = 18,
[0][1][1][0][RTW89_FCC][44] = 72,
[0][1][1][0][RTW89_ETSI][44] = 18,
[0][1][1][0][RTW89_MKK][44] = 127,
@@ -30740,6 +34600,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][44] = 70,
[0][1][1][0][RTW89_CN][44] = 60,
[0][1][1][0][RTW89_UK][44] = 52,
+ [0][1][1][0][RTW89_MEXICO][44] = 72,
+ [0][1][1][0][RTW89_UKRAINE][44] = 18,
+ [0][1][1][0][RTW89_CHILE][44] = 70,
+ [0][1][1][0][RTW89_QATAR][44] = 18,
[0][1][1][0][RTW89_FCC][46] = 72,
[0][1][1][0][RTW89_ETSI][46] = 18,
[0][1][1][0][RTW89_MKK][46] = 127,
@@ -30748,6 +34612,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][46] = 70,
[0][1][1][0][RTW89_CN][46] = 60,
[0][1][1][0][RTW89_UK][46] = 52,
+ [0][1][1][0][RTW89_MEXICO][46] = 72,
+ [0][1][1][0][RTW89_UKRAINE][46] = 18,
+ [0][1][1][0][RTW89_CHILE][46] = 70,
+ [0][1][1][0][RTW89_QATAR][46] = 18,
[0][1][1][0][RTW89_FCC][48] = 48,
[0][1][1][0][RTW89_ETSI][48] = 127,
[0][1][1][0][RTW89_MKK][48] = 127,
@@ -30756,6 +34624,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][48] = 127,
[0][1][1][0][RTW89_CN][48] = 127,
[0][1][1][0][RTW89_UK][48] = 127,
+ [0][1][1][0][RTW89_MEXICO][48] = 127,
+ [0][1][1][0][RTW89_UKRAINE][48] = 127,
+ [0][1][1][0][RTW89_CHILE][48] = 127,
+ [0][1][1][0][RTW89_QATAR][48] = 127,
[0][1][1][0][RTW89_FCC][50] = 48,
[0][1][1][0][RTW89_ETSI][50] = 127,
[0][1][1][0][RTW89_MKK][50] = 127,
@@ -30764,6 +34636,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][50] = 127,
[0][1][1][0][RTW89_CN][50] = 127,
[0][1][1][0][RTW89_UK][50] = 127,
+ [0][1][1][0][RTW89_MEXICO][50] = 127,
+ [0][1][1][0][RTW89_UKRAINE][50] = 127,
+ [0][1][1][0][RTW89_CHILE][50] = 127,
+ [0][1][1][0][RTW89_QATAR][50] = 127,
[0][1][1][0][RTW89_FCC][52] = 48,
[0][1][1][0][RTW89_ETSI][52] = 127,
[0][1][1][0][RTW89_MKK][52] = 127,
@@ -30772,38 +34648,58 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][1][0][RTW89_ACMA][52] = 127,
[0][1][1][0][RTW89_CN][52] = 127,
[0][1][1][0][RTW89_UK][52] = 127,
+ [0][1][1][0][RTW89_MEXICO][52] = 127,
+ [0][1][1][0][RTW89_UKRAINE][52] = 127,
+ [0][1][1][0][RTW89_CHILE][52] = 127,
+ [0][1][1][0][RTW89_QATAR][52] = 127,
[0][0][2][0][RTW89_FCC][0] = 70,
[0][0][2][0][RTW89_ETSI][0] = 66,
[0][0][2][0][RTW89_MKK][0] = 68,
[0][0][2][0][RTW89_IC][0] = 60,
- [0][0][2][0][RTW89_KCC][0] = 54,
+ [0][0][2][0][RTW89_KCC][0] = 68,
[0][0][2][0][RTW89_ACMA][0] = 66,
[0][0][2][0][RTW89_CN][0] = 52,
[0][0][2][0][RTW89_UK][0] = 66,
+ [0][0][2][0][RTW89_MEXICO][0] = 62,
+ [0][0][2][0][RTW89_UKRAINE][0] = 54,
+ [0][0][2][0][RTW89_CHILE][0] = 68,
+ [0][0][2][0][RTW89_QATAR][0] = 66,
[0][0][2][0][RTW89_FCC][2] = 72,
[0][0][2][0][RTW89_ETSI][2] = 66,
[0][0][2][0][RTW89_MKK][2] = 68,
[0][0][2][0][RTW89_IC][2] = 60,
- [0][0][2][0][RTW89_KCC][2] = 54,
+ [0][0][2][0][RTW89_KCC][2] = 68,
[0][0][2][0][RTW89_ACMA][2] = 66,
[0][0][2][0][RTW89_CN][2] = 52,
[0][0][2][0][RTW89_UK][2] = 66,
+ [0][0][2][0][RTW89_MEXICO][2] = 62,
+ [0][0][2][0][RTW89_UKRAINE][2] = 54,
+ [0][0][2][0][RTW89_CHILE][2] = 70,
+ [0][0][2][0][RTW89_QATAR][2] = 66,
[0][0][2][0][RTW89_FCC][4] = 72,
[0][0][2][0][RTW89_ETSI][4] = 66,
[0][0][2][0][RTW89_MKK][4] = 68,
[0][0][2][0][RTW89_IC][4] = 60,
- [0][0][2][0][RTW89_KCC][4] = 54,
+ [0][0][2][0][RTW89_KCC][4] = 68,
[0][0][2][0][RTW89_ACMA][4] = 66,
[0][0][2][0][RTW89_CN][4] = 52,
[0][0][2][0][RTW89_UK][4] = 66,
+ [0][0][2][0][RTW89_MEXICO][4] = 62,
+ [0][0][2][0][RTW89_UKRAINE][4] = 54,
+ [0][0][2][0][RTW89_CHILE][4] = 70,
+ [0][0][2][0][RTW89_QATAR][4] = 66,
[0][0][2][0][RTW89_FCC][6] = 72,
[0][0][2][0][RTW89_ETSI][6] = 66,
[0][0][2][0][RTW89_MKK][6] = 60,
[0][0][2][0][RTW89_IC][6] = 60,
- [0][0][2][0][RTW89_KCC][6] = 68,
+ [0][0][2][0][RTW89_KCC][6] = 54,
[0][0][2][0][RTW89_ACMA][6] = 66,
[0][0][2][0][RTW89_CN][6] = 52,
[0][0][2][0][RTW89_UK][6] = 66,
+ [0][0][2][0][RTW89_MEXICO][6] = 62,
+ [0][0][2][0][RTW89_UKRAINE][6] = 54,
+ [0][0][2][0][RTW89_CHILE][6] = 70,
+ [0][0][2][0][RTW89_QATAR][6] = 66,
[0][0][2][0][RTW89_FCC][8] = 72,
[0][0][2][0][RTW89_ETSI][8] = 66,
[0][0][2][0][RTW89_MKK][8] = 58,
@@ -30812,6 +34708,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][8] = 66,
[0][0][2][0][RTW89_CN][8] = 52,
[0][0][2][0][RTW89_UK][8] = 66,
+ [0][0][2][0][RTW89_MEXICO][8] = 72,
+ [0][0][2][0][RTW89_UKRAINE][8] = 54,
+ [0][0][2][0][RTW89_CHILE][8] = 70,
+ [0][0][2][0][RTW89_QATAR][8] = 66,
[0][0][2][0][RTW89_FCC][10] = 72,
[0][0][2][0][RTW89_ETSI][10] = 66,
[0][0][2][0][RTW89_MKK][10] = 70,
@@ -30820,6 +34720,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][10] = 66,
[0][0][2][0][RTW89_CN][10] = 52,
[0][0][2][0][RTW89_UK][10] = 66,
+ [0][0][2][0][RTW89_MEXICO][10] = 72,
+ [0][0][2][0][RTW89_UKRAINE][10] = 54,
+ [0][0][2][0][RTW89_CHILE][10] = 70,
+ [0][0][2][0][RTW89_QATAR][10] = 66,
[0][0][2][0][RTW89_FCC][12] = 72,
[0][0][2][0][RTW89_ETSI][12] = 66,
[0][0][2][0][RTW89_MKK][12] = 70,
@@ -30828,6 +34732,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][12] = 66,
[0][0][2][0][RTW89_CN][12] = 52,
[0][0][2][0][RTW89_UK][12] = 66,
+ [0][0][2][0][RTW89_MEXICO][12] = 72,
+ [0][0][2][0][RTW89_UKRAINE][12] = 54,
+ [0][0][2][0][RTW89_CHILE][12] = 70,
+ [0][0][2][0][RTW89_QATAR][12] = 66,
[0][0][2][0][RTW89_FCC][14] = 68,
[0][0][2][0][RTW89_ETSI][14] = 66,
[0][0][2][0][RTW89_MKK][14] = 70,
@@ -30836,6 +34744,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][14] = 66,
[0][0][2][0][RTW89_CN][14] = 52,
[0][0][2][0][RTW89_UK][14] = 66,
+ [0][0][2][0][RTW89_MEXICO][14] = 68,
+ [0][0][2][0][RTW89_UKRAINE][14] = 54,
+ [0][0][2][0][RTW89_CHILE][14] = 66,
+ [0][0][2][0][RTW89_QATAR][14] = 66,
[0][0][2][0][RTW89_FCC][15] = 70,
[0][0][2][0][RTW89_ETSI][15] = 66,
[0][0][2][0][RTW89_MKK][15] = 70,
@@ -30844,6 +34756,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][15] = 66,
[0][0][2][0][RTW89_CN][15] = 127,
[0][0][2][0][RTW89_UK][15] = 66,
+ [0][0][2][0][RTW89_MEXICO][15] = 70,
+ [0][0][2][0][RTW89_UKRAINE][15] = 54,
+ [0][0][2][0][RTW89_CHILE][15] = 68,
+ [0][0][2][0][RTW89_QATAR][15] = 66,
[0][0][2][0][RTW89_FCC][17] = 72,
[0][0][2][0][RTW89_ETSI][17] = 66,
[0][0][2][0][RTW89_MKK][17] = 70,
@@ -30852,6 +34768,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][17] = 66,
[0][0][2][0][RTW89_CN][17] = 127,
[0][0][2][0][RTW89_UK][17] = 66,
+ [0][0][2][0][RTW89_MEXICO][17] = 72,
+ [0][0][2][0][RTW89_UKRAINE][17] = 54,
+ [0][0][2][0][RTW89_CHILE][17] = 68,
+ [0][0][2][0][RTW89_QATAR][17] = 66,
[0][0][2][0][RTW89_FCC][19] = 72,
[0][0][2][0][RTW89_ETSI][19] = 66,
[0][0][2][0][RTW89_MKK][19] = 70,
@@ -30860,6 +34780,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][19] = 66,
[0][0][2][0][RTW89_CN][19] = 127,
[0][0][2][0][RTW89_UK][19] = 66,
+ [0][0][2][0][RTW89_MEXICO][19] = 72,
+ [0][0][2][0][RTW89_UKRAINE][19] = 54,
+ [0][0][2][0][RTW89_CHILE][19] = 68,
+ [0][0][2][0][RTW89_QATAR][19] = 66,
[0][0][2][0][RTW89_FCC][21] = 72,
[0][0][2][0][RTW89_ETSI][21] = 66,
[0][0][2][0][RTW89_MKK][21] = 70,
@@ -30868,6 +34792,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][21] = 66,
[0][0][2][0][RTW89_CN][21] = 127,
[0][0][2][0][RTW89_UK][21] = 66,
+ [0][0][2][0][RTW89_MEXICO][21] = 72,
+ [0][0][2][0][RTW89_UKRAINE][21] = 54,
+ [0][0][2][0][RTW89_CHILE][21] = 70,
+ [0][0][2][0][RTW89_QATAR][21] = 66,
[0][0][2][0][RTW89_FCC][23] = 72,
[0][0][2][0][RTW89_ETSI][23] = 66,
[0][0][2][0][RTW89_MKK][23] = 70,
@@ -30876,6 +34804,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][23] = 66,
[0][0][2][0][RTW89_CN][23] = 127,
[0][0][2][0][RTW89_UK][23] = 66,
+ [0][0][2][0][RTW89_MEXICO][23] = 72,
+ [0][0][2][0][RTW89_UKRAINE][23] = 54,
+ [0][0][2][0][RTW89_CHILE][23] = 70,
+ [0][0][2][0][RTW89_QATAR][23] = 66,
[0][0][2][0][RTW89_FCC][25] = 72,
[0][0][2][0][RTW89_ETSI][25] = 66,
[0][0][2][0][RTW89_MKK][25] = 70,
@@ -30884,6 +34816,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][25] = 127,
[0][0][2][0][RTW89_CN][25] = 127,
[0][0][2][0][RTW89_UK][25] = 66,
+ [0][0][2][0][RTW89_MEXICO][25] = 72,
+ [0][0][2][0][RTW89_UKRAINE][25] = 54,
+ [0][0][2][0][RTW89_CHILE][25] = 70,
+ [0][0][2][0][RTW89_QATAR][25] = 66,
[0][0][2][0][RTW89_FCC][27] = 72,
[0][0][2][0][RTW89_ETSI][27] = 66,
[0][0][2][0][RTW89_MKK][27] = 70,
@@ -30892,6 +34828,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][27] = 127,
[0][0][2][0][RTW89_CN][27] = 127,
[0][0][2][0][RTW89_UK][27] = 66,
+ [0][0][2][0][RTW89_MEXICO][27] = 72,
+ [0][0][2][0][RTW89_UKRAINE][27] = 54,
+ [0][0][2][0][RTW89_CHILE][27] = 56,
+ [0][0][2][0][RTW89_QATAR][27] = 66,
[0][0][2][0][RTW89_FCC][29] = 72,
[0][0][2][0][RTW89_ETSI][29] = 66,
[0][0][2][0][RTW89_MKK][29] = 70,
@@ -30900,6 +34840,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][29] = 127,
[0][0][2][0][RTW89_CN][29] = 127,
[0][0][2][0][RTW89_UK][29] = 66,
+ [0][0][2][0][RTW89_MEXICO][29] = 72,
+ [0][0][2][0][RTW89_UKRAINE][29] = 54,
+ [0][0][2][0][RTW89_CHILE][29] = 56,
+ [0][0][2][0][RTW89_QATAR][29] = 66,
[0][0][2][0][RTW89_FCC][31] = 72,
[0][0][2][0][RTW89_ETSI][31] = 66,
[0][0][2][0][RTW89_MKK][31] = 70,
@@ -30908,6 +34852,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][31] = 66,
[0][0][2][0][RTW89_CN][31] = 127,
[0][0][2][0][RTW89_UK][31] = 66,
+ [0][0][2][0][RTW89_MEXICO][31] = 72,
+ [0][0][2][0][RTW89_UKRAINE][31] = 54,
+ [0][0][2][0][RTW89_CHILE][31] = 56,
+ [0][0][2][0][RTW89_QATAR][31] = 66,
[0][0][2][0][RTW89_FCC][33] = 72,
[0][0][2][0][RTW89_ETSI][33] = 66,
[0][0][2][0][RTW89_MKK][33] = 70,
@@ -30916,6 +34864,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][33] = 66,
[0][0][2][0][RTW89_CN][33] = 127,
[0][0][2][0][RTW89_UK][33] = 66,
+ [0][0][2][0][RTW89_MEXICO][33] = 72,
+ [0][0][2][0][RTW89_UKRAINE][33] = 54,
+ [0][0][2][0][RTW89_CHILE][33] = 56,
+ [0][0][2][0][RTW89_QATAR][33] = 66,
[0][0][2][0][RTW89_FCC][35] = 56,
[0][0][2][0][RTW89_ETSI][35] = 66,
[0][0][2][0][RTW89_MKK][35] = 70,
@@ -30924,6 +34876,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][35] = 66,
[0][0][2][0][RTW89_CN][35] = 127,
[0][0][2][0][RTW89_UK][35] = 66,
+ [0][0][2][0][RTW89_MEXICO][35] = 56,
+ [0][0][2][0][RTW89_UKRAINE][35] = 54,
+ [0][0][2][0][RTW89_CHILE][35] = 56,
+ [0][0][2][0][RTW89_QATAR][35] = 66,
[0][0][2][0][RTW89_FCC][37] = 72,
[0][0][2][0][RTW89_ETSI][37] = 127,
[0][0][2][0][RTW89_MKK][37] = 70,
@@ -30932,6 +34888,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][37] = 70,
[0][0][2][0][RTW89_CN][37] = 127,
[0][0][2][0][RTW89_UK][37] = 64,
+ [0][0][2][0][RTW89_MEXICO][37] = 72,
+ [0][0][2][0][RTW89_UKRAINE][37] = 127,
+ [0][0][2][0][RTW89_CHILE][37] = 70,
+ [0][0][2][0][RTW89_QATAR][37] = 127,
[0][0][2][0][RTW89_FCC][38] = 72,
[0][0][2][0][RTW89_ETSI][38] = 30,
[0][0][2][0][RTW89_MKK][38] = 127,
@@ -30940,6 +34900,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][38] = 70,
[0][0][2][0][RTW89_CN][38] = 68,
[0][0][2][0][RTW89_UK][38] = 64,
+ [0][0][2][0][RTW89_MEXICO][38] = 72,
+ [0][0][2][0][RTW89_UKRAINE][38] = 30,
+ [0][0][2][0][RTW89_CHILE][38] = 70,
+ [0][0][2][0][RTW89_QATAR][38] = 30,
[0][0][2][0][RTW89_FCC][40] = 72,
[0][0][2][0][RTW89_ETSI][40] = 30,
[0][0][2][0][RTW89_MKK][40] = 127,
@@ -30948,6 +34912,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][40] = 70,
[0][0][2][0][RTW89_CN][40] = 68,
[0][0][2][0][RTW89_UK][40] = 64,
+ [0][0][2][0][RTW89_MEXICO][40] = 72,
+ [0][0][2][0][RTW89_UKRAINE][40] = 30,
+ [0][0][2][0][RTW89_CHILE][40] = 70,
+ [0][0][2][0][RTW89_QATAR][40] = 30,
[0][0][2][0][RTW89_FCC][42] = 72,
[0][0][2][0][RTW89_ETSI][42] = 30,
[0][0][2][0][RTW89_MKK][42] = 127,
@@ -30956,6 +34924,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][42] = 70,
[0][0][2][0][RTW89_CN][42] = 68,
[0][0][2][0][RTW89_UK][42] = 64,
+ [0][0][2][0][RTW89_MEXICO][42] = 72,
+ [0][0][2][0][RTW89_UKRAINE][42] = 30,
+ [0][0][2][0][RTW89_CHILE][42] = 70,
+ [0][0][2][0][RTW89_QATAR][42] = 30,
[0][0][2][0][RTW89_FCC][44] = 72,
[0][0][2][0][RTW89_ETSI][44] = 30,
[0][0][2][0][RTW89_MKK][44] = 127,
@@ -30964,6 +34936,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][44] = 70,
[0][0][2][0][RTW89_CN][44] = 68,
[0][0][2][0][RTW89_UK][44] = 64,
+ [0][0][2][0][RTW89_MEXICO][44] = 72,
+ [0][0][2][0][RTW89_UKRAINE][44] = 30,
+ [0][0][2][0][RTW89_CHILE][44] = 70,
+ [0][0][2][0][RTW89_QATAR][44] = 30,
[0][0][2][0][RTW89_FCC][46] = 72,
[0][0][2][0][RTW89_ETSI][46] = 30,
[0][0][2][0][RTW89_MKK][46] = 127,
@@ -30972,6 +34948,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][46] = 70,
[0][0][2][0][RTW89_CN][46] = 68,
[0][0][2][0][RTW89_UK][46] = 64,
+ [0][0][2][0][RTW89_MEXICO][46] = 72,
+ [0][0][2][0][RTW89_UKRAINE][46] = 30,
+ [0][0][2][0][RTW89_CHILE][46] = 70,
+ [0][0][2][0][RTW89_QATAR][46] = 30,
[0][0][2][0][RTW89_FCC][48] = 72,
[0][0][2][0][RTW89_ETSI][48] = 127,
[0][0][2][0][RTW89_MKK][48] = 127,
@@ -30980,6 +34960,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][48] = 127,
[0][0][2][0][RTW89_CN][48] = 127,
[0][0][2][0][RTW89_UK][48] = 127,
+ [0][0][2][0][RTW89_MEXICO][48] = 127,
+ [0][0][2][0][RTW89_UKRAINE][48] = 127,
+ [0][0][2][0][RTW89_CHILE][48] = 127,
+ [0][0][2][0][RTW89_QATAR][48] = 127,
[0][0][2][0][RTW89_FCC][50] = 72,
[0][0][2][0][RTW89_ETSI][50] = 127,
[0][0][2][0][RTW89_MKK][50] = 127,
@@ -30988,6 +34972,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][50] = 127,
[0][0][2][0][RTW89_CN][50] = 127,
[0][0][2][0][RTW89_UK][50] = 127,
+ [0][0][2][0][RTW89_MEXICO][50] = 127,
+ [0][0][2][0][RTW89_UKRAINE][50] = 127,
+ [0][0][2][0][RTW89_CHILE][50] = 127,
+ [0][0][2][0][RTW89_QATAR][50] = 127,
[0][0][2][0][RTW89_FCC][52] = 72,
[0][0][2][0][RTW89_ETSI][52] = 127,
[0][0][2][0][RTW89_MKK][52] = 127,
@@ -30996,38 +34984,58 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][0][2][0][RTW89_ACMA][52] = 127,
[0][0][2][0][RTW89_CN][52] = 127,
[0][0][2][0][RTW89_UK][52] = 127,
+ [0][0][2][0][RTW89_MEXICO][52] = 127,
+ [0][0][2][0][RTW89_UKRAINE][52] = 127,
+ [0][0][2][0][RTW89_CHILE][52] = 127,
+ [0][0][2][0][RTW89_QATAR][52] = 127,
[0][1][2][0][RTW89_FCC][0] = 60,
[0][1][2][0][RTW89_ETSI][0] = 54,
[0][1][2][0][RTW89_MKK][0] = 54,
[0][1][2][0][RTW89_IC][0] = 36,
- [0][1][2][0][RTW89_KCC][0] = 40,
+ [0][1][2][0][RTW89_KCC][0] = 64,
[0][1][2][0][RTW89_ACMA][0] = 54,
[0][1][2][0][RTW89_CN][0] = 40,
[0][1][2][0][RTW89_UK][0] = 54,
+ [0][1][2][0][RTW89_MEXICO][0] = 50,
+ [0][1][2][0][RTW89_UKRAINE][0] = 42,
+ [0][1][2][0][RTW89_CHILE][0] = 60,
+ [0][1][2][0][RTW89_QATAR][0] = 54,
[0][1][2][0][RTW89_FCC][2] = 62,
[0][1][2][0][RTW89_ETSI][2] = 54,
[0][1][2][0][RTW89_MKK][2] = 54,
[0][1][2][0][RTW89_IC][2] = 36,
- [0][1][2][0][RTW89_KCC][2] = 40,
+ [0][1][2][0][RTW89_KCC][2] = 64,
[0][1][2][0][RTW89_ACMA][2] = 54,
[0][1][2][0][RTW89_CN][2] = 40,
[0][1][2][0][RTW89_UK][2] = 54,
+ [0][1][2][0][RTW89_MEXICO][2] = 50,
+ [0][1][2][0][RTW89_UKRAINE][2] = 42,
+ [0][1][2][0][RTW89_CHILE][2] = 62,
+ [0][1][2][0][RTW89_QATAR][2] = 54,
[0][1][2][0][RTW89_FCC][4] = 62,
[0][1][2][0][RTW89_ETSI][4] = 54,
[0][1][2][0][RTW89_MKK][4] = 54,
[0][1][2][0][RTW89_IC][4] = 36,
- [0][1][2][0][RTW89_KCC][4] = 40,
+ [0][1][2][0][RTW89_KCC][4] = 64,
[0][1][2][0][RTW89_ACMA][4] = 54,
[0][1][2][0][RTW89_CN][4] = 40,
[0][1][2][0][RTW89_UK][4] = 54,
+ [0][1][2][0][RTW89_MEXICO][4] = 50,
+ [0][1][2][0][RTW89_UKRAINE][4] = 42,
+ [0][1][2][0][RTW89_CHILE][4] = 62,
+ [0][1][2][0][RTW89_QATAR][4] = 54,
[0][1][2][0][RTW89_FCC][6] = 62,
[0][1][2][0][RTW89_ETSI][6] = 54,
[0][1][2][0][RTW89_MKK][6] = 50,
[0][1][2][0][RTW89_IC][6] = 38,
- [0][1][2][0][RTW89_KCC][6] = 64,
+ [0][1][2][0][RTW89_KCC][6] = 40,
[0][1][2][0][RTW89_ACMA][6] = 54,
[0][1][2][0][RTW89_CN][6] = 40,
[0][1][2][0][RTW89_UK][6] = 54,
+ [0][1][2][0][RTW89_MEXICO][6] = 50,
+ [0][1][2][0][RTW89_UKRAINE][6] = 42,
+ [0][1][2][0][RTW89_CHILE][6] = 62,
+ [0][1][2][0][RTW89_QATAR][6] = 54,
[0][1][2][0][RTW89_FCC][8] = 62,
[0][1][2][0][RTW89_ETSI][8] = 54,
[0][1][2][0][RTW89_MKK][8] = 42,
@@ -31036,6 +35044,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][8] = 54,
[0][1][2][0][RTW89_CN][8] = 40,
[0][1][2][0][RTW89_UK][8] = 54,
+ [0][1][2][0][RTW89_MEXICO][8] = 62,
+ [0][1][2][0][RTW89_UKRAINE][8] = 42,
+ [0][1][2][0][RTW89_CHILE][8] = 62,
+ [0][1][2][0][RTW89_QATAR][8] = 54,
[0][1][2][0][RTW89_FCC][10] = 62,
[0][1][2][0][RTW89_ETSI][10] = 54,
[0][1][2][0][RTW89_MKK][10] = 54,
@@ -31044,6 +35056,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][10] = 54,
[0][1][2][0][RTW89_CN][10] = 40,
[0][1][2][0][RTW89_UK][10] = 54,
+ [0][1][2][0][RTW89_MEXICO][10] = 62,
+ [0][1][2][0][RTW89_UKRAINE][10] = 42,
+ [0][1][2][0][RTW89_CHILE][10] = 62,
+ [0][1][2][0][RTW89_QATAR][10] = 54,
[0][1][2][0][RTW89_FCC][12] = 62,
[0][1][2][0][RTW89_ETSI][12] = 54,
[0][1][2][0][RTW89_MKK][12] = 54,
@@ -31052,6 +35068,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][12] = 54,
[0][1][2][0][RTW89_CN][12] = 40,
[0][1][2][0][RTW89_UK][12] = 54,
+ [0][1][2][0][RTW89_MEXICO][12] = 62,
+ [0][1][2][0][RTW89_UKRAINE][12] = 42,
+ [0][1][2][0][RTW89_CHILE][12] = 62,
+ [0][1][2][0][RTW89_QATAR][12] = 54,
[0][1][2][0][RTW89_FCC][14] = 62,
[0][1][2][0][RTW89_ETSI][14] = 54,
[0][1][2][0][RTW89_MKK][14] = 54,
@@ -31060,6 +35080,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][14] = 54,
[0][1][2][0][RTW89_CN][14] = 40,
[0][1][2][0][RTW89_UK][14] = 54,
+ [0][1][2][0][RTW89_MEXICO][14] = 62,
+ [0][1][2][0][RTW89_UKRAINE][14] = 42,
+ [0][1][2][0][RTW89_CHILE][14] = 62,
+ [0][1][2][0][RTW89_QATAR][14] = 54,
[0][1][2][0][RTW89_FCC][15] = 60,
[0][1][2][0][RTW89_ETSI][15] = 54,
[0][1][2][0][RTW89_MKK][15] = 68,
@@ -31068,6 +35092,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][15] = 54,
[0][1][2][0][RTW89_CN][15] = 127,
[0][1][2][0][RTW89_UK][15] = 54,
+ [0][1][2][0][RTW89_MEXICO][15] = 60,
+ [0][1][2][0][RTW89_UKRAINE][15] = 42,
+ [0][1][2][0][RTW89_CHILE][15] = 60,
+ [0][1][2][0][RTW89_QATAR][15] = 54,
[0][1][2][0][RTW89_FCC][17] = 62,
[0][1][2][0][RTW89_ETSI][17] = 54,
[0][1][2][0][RTW89_MKK][17] = 68,
@@ -31076,6 +35104,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][17] = 54,
[0][1][2][0][RTW89_CN][17] = 127,
[0][1][2][0][RTW89_UK][17] = 54,
+ [0][1][2][0][RTW89_MEXICO][17] = 62,
+ [0][1][2][0][RTW89_UKRAINE][17] = 42,
+ [0][1][2][0][RTW89_CHILE][17] = 60,
+ [0][1][2][0][RTW89_QATAR][17] = 54,
[0][1][2][0][RTW89_FCC][19] = 62,
[0][1][2][0][RTW89_ETSI][19] = 54,
[0][1][2][0][RTW89_MKK][19] = 68,
@@ -31084,6 +35116,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][19] = 54,
[0][1][2][0][RTW89_CN][19] = 127,
[0][1][2][0][RTW89_UK][19] = 54,
+ [0][1][2][0][RTW89_MEXICO][19] = 62,
+ [0][1][2][0][RTW89_UKRAINE][19] = 42,
+ [0][1][2][0][RTW89_CHILE][19] = 62,
+ [0][1][2][0][RTW89_QATAR][19] = 54,
[0][1][2][0][RTW89_FCC][21] = 62,
[0][1][2][0][RTW89_ETSI][21] = 54,
[0][1][2][0][RTW89_MKK][21] = 68,
@@ -31092,6 +35128,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][21] = 54,
[0][1][2][0][RTW89_CN][21] = 127,
[0][1][2][0][RTW89_UK][21] = 54,
+ [0][1][2][0][RTW89_MEXICO][21] = 62,
+ [0][1][2][0][RTW89_UKRAINE][21] = 42,
+ [0][1][2][0][RTW89_CHILE][21] = 62,
+ [0][1][2][0][RTW89_QATAR][21] = 54,
[0][1][2][0][RTW89_FCC][23] = 62,
[0][1][2][0][RTW89_ETSI][23] = 54,
[0][1][2][0][RTW89_MKK][23] = 68,
@@ -31100,6 +35140,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][23] = 54,
[0][1][2][0][RTW89_CN][23] = 127,
[0][1][2][0][RTW89_UK][23] = 54,
+ [0][1][2][0][RTW89_MEXICO][23] = 62,
+ [0][1][2][0][RTW89_UKRAINE][23] = 42,
+ [0][1][2][0][RTW89_CHILE][23] = 62,
+ [0][1][2][0][RTW89_QATAR][23] = 54,
[0][1][2][0][RTW89_FCC][25] = 62,
[0][1][2][0][RTW89_ETSI][25] = 54,
[0][1][2][0][RTW89_MKK][25] = 68,
@@ -31108,6 +35152,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][25] = 127,
[0][1][2][0][RTW89_CN][25] = 127,
[0][1][2][0][RTW89_UK][25] = 54,
+ [0][1][2][0][RTW89_MEXICO][25] = 62,
+ [0][1][2][0][RTW89_UKRAINE][25] = 42,
+ [0][1][2][0][RTW89_CHILE][25] = 62,
+ [0][1][2][0][RTW89_QATAR][25] = 54,
[0][1][2][0][RTW89_FCC][27] = 62,
[0][1][2][0][RTW89_ETSI][27] = 54,
[0][1][2][0][RTW89_MKK][27] = 68,
@@ -31116,6 +35164,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][27] = 127,
[0][1][2][0][RTW89_CN][27] = 127,
[0][1][2][0][RTW89_UK][27] = 54,
+ [0][1][2][0][RTW89_MEXICO][27] = 62,
+ [0][1][2][0][RTW89_UKRAINE][27] = 42,
+ [0][1][2][0][RTW89_CHILE][27] = 46,
+ [0][1][2][0][RTW89_QATAR][27] = 54,
[0][1][2][0][RTW89_FCC][29] = 62,
[0][1][2][0][RTW89_ETSI][29] = 54,
[0][1][2][0][RTW89_MKK][29] = 68,
@@ -31124,6 +35176,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][29] = 127,
[0][1][2][0][RTW89_CN][29] = 127,
[0][1][2][0][RTW89_UK][29] = 54,
+ [0][1][2][0][RTW89_MEXICO][29] = 62,
+ [0][1][2][0][RTW89_UKRAINE][29] = 42,
+ [0][1][2][0][RTW89_CHILE][29] = 46,
+ [0][1][2][0][RTW89_QATAR][29] = 54,
[0][1][2][0][RTW89_FCC][31] = 62,
[0][1][2][0][RTW89_ETSI][31] = 54,
[0][1][2][0][RTW89_MKK][31] = 68,
@@ -31132,6 +35188,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][31] = 54,
[0][1][2][0][RTW89_CN][31] = 127,
[0][1][2][0][RTW89_UK][31] = 54,
+ [0][1][2][0][RTW89_MEXICO][31] = 62,
+ [0][1][2][0][RTW89_UKRAINE][31] = 42,
+ [0][1][2][0][RTW89_CHILE][31] = 46,
+ [0][1][2][0][RTW89_QATAR][31] = 54,
[0][1][2][0][RTW89_FCC][33] = 62,
[0][1][2][0][RTW89_ETSI][33] = 54,
[0][1][2][0][RTW89_MKK][33] = 68,
@@ -31140,6 +35200,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][33] = 54,
[0][1][2][0][RTW89_CN][33] = 127,
[0][1][2][0][RTW89_UK][33] = 54,
+ [0][1][2][0][RTW89_MEXICO][33] = 62,
+ [0][1][2][0][RTW89_UKRAINE][33] = 42,
+ [0][1][2][0][RTW89_CHILE][33] = 46,
+ [0][1][2][0][RTW89_QATAR][33] = 54,
[0][1][2][0][RTW89_FCC][35] = 46,
[0][1][2][0][RTW89_ETSI][35] = 54,
[0][1][2][0][RTW89_MKK][35] = 68,
@@ -31148,6 +35212,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][35] = 54,
[0][1][2][0][RTW89_CN][35] = 127,
[0][1][2][0][RTW89_UK][35] = 54,
+ [0][1][2][0][RTW89_MEXICO][35] = 46,
+ [0][1][2][0][RTW89_UKRAINE][35] = 42,
+ [0][1][2][0][RTW89_CHILE][35] = 46,
+ [0][1][2][0][RTW89_QATAR][35] = 54,
[0][1][2][0][RTW89_FCC][37] = 64,
[0][1][2][0][RTW89_ETSI][37] = 127,
[0][1][2][0][RTW89_MKK][37] = 68,
@@ -31156,6 +35224,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][37] = 64,
[0][1][2][0][RTW89_CN][37] = 127,
[0][1][2][0][RTW89_UK][37] = 52,
+ [0][1][2][0][RTW89_MEXICO][37] = 64,
+ [0][1][2][0][RTW89_UKRAINE][37] = 127,
+ [0][1][2][0][RTW89_CHILE][37] = 64,
+ [0][1][2][0][RTW89_QATAR][37] = 127,
[0][1][2][0][RTW89_FCC][38] = 72,
[0][1][2][0][RTW89_ETSI][38] = 18,
[0][1][2][0][RTW89_MKK][38] = 127,
@@ -31164,6 +35236,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][38] = 70,
[0][1][2][0][RTW89_CN][38] = 68,
[0][1][2][0][RTW89_UK][38] = 52,
+ [0][1][2][0][RTW89_MEXICO][38] = 72,
+ [0][1][2][0][RTW89_UKRAINE][38] = 18,
+ [0][1][2][0][RTW89_CHILE][38] = 70,
+ [0][1][2][0][RTW89_QATAR][38] = 18,
[0][1][2][0][RTW89_FCC][40] = 72,
[0][1][2][0][RTW89_ETSI][40] = 18,
[0][1][2][0][RTW89_MKK][40] = 127,
@@ -31172,6 +35248,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][40] = 70,
[0][1][2][0][RTW89_CN][40] = 68,
[0][1][2][0][RTW89_UK][40] = 52,
+ [0][1][2][0][RTW89_MEXICO][40] = 72,
+ [0][1][2][0][RTW89_UKRAINE][40] = 18,
+ [0][1][2][0][RTW89_CHILE][40] = 70,
+ [0][1][2][0][RTW89_QATAR][40] = 18,
[0][1][2][0][RTW89_FCC][42] = 72,
[0][1][2][0][RTW89_ETSI][42] = 18,
[0][1][2][0][RTW89_MKK][42] = 127,
@@ -31180,6 +35260,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][42] = 70,
[0][1][2][0][RTW89_CN][42] = 68,
[0][1][2][0][RTW89_UK][42] = 52,
+ [0][1][2][0][RTW89_MEXICO][42] = 72,
+ [0][1][2][0][RTW89_UKRAINE][42] = 18,
+ [0][1][2][0][RTW89_CHILE][42] = 70,
+ [0][1][2][0][RTW89_QATAR][42] = 18,
[0][1][2][0][RTW89_FCC][44] = 72,
[0][1][2][0][RTW89_ETSI][44] = 18,
[0][1][2][0][RTW89_MKK][44] = 127,
@@ -31188,6 +35272,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][44] = 70,
[0][1][2][0][RTW89_CN][44] = 68,
[0][1][2][0][RTW89_UK][44] = 52,
+ [0][1][2][0][RTW89_MEXICO][44] = 72,
+ [0][1][2][0][RTW89_UKRAINE][44] = 18,
+ [0][1][2][0][RTW89_CHILE][44] = 70,
+ [0][1][2][0][RTW89_QATAR][44] = 18,
[0][1][2][0][RTW89_FCC][46] = 72,
[0][1][2][0][RTW89_ETSI][46] = 18,
[0][1][2][0][RTW89_MKK][46] = 127,
@@ -31196,6 +35284,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][46] = 70,
[0][1][2][0][RTW89_CN][46] = 68,
[0][1][2][0][RTW89_UK][46] = 52,
+ [0][1][2][0][RTW89_MEXICO][46] = 72,
+ [0][1][2][0][RTW89_UKRAINE][46] = 18,
+ [0][1][2][0][RTW89_CHILE][46] = 70,
+ [0][1][2][0][RTW89_QATAR][46] = 18,
[0][1][2][0][RTW89_FCC][48] = 48,
[0][1][2][0][RTW89_ETSI][48] = 127,
[0][1][2][0][RTW89_MKK][48] = 127,
@@ -31204,6 +35296,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][48] = 127,
[0][1][2][0][RTW89_CN][48] = 127,
[0][1][2][0][RTW89_UK][48] = 127,
+ [0][1][2][0][RTW89_MEXICO][48] = 127,
+ [0][1][2][0][RTW89_UKRAINE][48] = 127,
+ [0][1][2][0][RTW89_CHILE][48] = 127,
+ [0][1][2][0][RTW89_QATAR][48] = 127,
[0][1][2][0][RTW89_FCC][50] = 50,
[0][1][2][0][RTW89_ETSI][50] = 127,
[0][1][2][0][RTW89_MKK][50] = 127,
@@ -31212,6 +35308,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][50] = 127,
[0][1][2][0][RTW89_CN][50] = 127,
[0][1][2][0][RTW89_UK][50] = 127,
+ [0][1][2][0][RTW89_MEXICO][50] = 127,
+ [0][1][2][0][RTW89_UKRAINE][50] = 127,
+ [0][1][2][0][RTW89_CHILE][50] = 127,
+ [0][1][2][0][RTW89_QATAR][50] = 127,
[0][1][2][0][RTW89_FCC][52] = 48,
[0][1][2][0][RTW89_ETSI][52] = 127,
[0][1][2][0][RTW89_MKK][52] = 127,
@@ -31220,38 +35320,58 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][0][RTW89_ACMA][52] = 127,
[0][1][2][0][RTW89_CN][52] = 127,
[0][1][2][0][RTW89_UK][52] = 127,
+ [0][1][2][0][RTW89_MEXICO][52] = 127,
+ [0][1][2][0][RTW89_UKRAINE][52] = 127,
+ [0][1][2][0][RTW89_CHILE][52] = 127,
+ [0][1][2][0][RTW89_QATAR][52] = 127,
[0][1][2][1][RTW89_FCC][0] = 60,
[0][1][2][1][RTW89_ETSI][0] = 40,
[0][1][2][1][RTW89_MKK][0] = 54,
[0][1][2][1][RTW89_IC][0] = 40,
- [0][1][2][1][RTW89_KCC][0] = 40,
+ [0][1][2][1][RTW89_KCC][0] = 64,
[0][1][2][1][RTW89_ACMA][0] = 40,
[0][1][2][1][RTW89_CN][0] = 36,
[0][1][2][1][RTW89_UK][0] = 40,
+ [0][1][2][1][RTW89_MEXICO][0] = 50,
+ [0][1][2][1][RTW89_UKRAINE][0] = 30,
+ [0][1][2][1][RTW89_CHILE][0] = 60,
+ [0][1][2][1][RTW89_QATAR][0] = 40,
[0][1][2][1][RTW89_FCC][2] = 62,
[0][1][2][1][RTW89_ETSI][2] = 40,
[0][1][2][1][RTW89_MKK][2] = 54,
[0][1][2][1][RTW89_IC][2] = 40,
- [0][1][2][1][RTW89_KCC][2] = 40,
+ [0][1][2][1][RTW89_KCC][2] = 64,
[0][1][2][1][RTW89_ACMA][2] = 40,
[0][1][2][1][RTW89_CN][2] = 36,
[0][1][2][1][RTW89_UK][2] = 40,
+ [0][1][2][1][RTW89_MEXICO][2] = 50,
+ [0][1][2][1][RTW89_UKRAINE][2] = 30,
+ [0][1][2][1][RTW89_CHILE][2] = 60,
+ [0][1][2][1][RTW89_QATAR][2] = 40,
[0][1][2][1][RTW89_FCC][4] = 62,
[0][1][2][1][RTW89_ETSI][4] = 40,
[0][1][2][1][RTW89_MKK][4] = 54,
[0][1][2][1][RTW89_IC][4] = 40,
- [0][1][2][1][RTW89_KCC][4] = 40,
+ [0][1][2][1][RTW89_KCC][4] = 64,
[0][1][2][1][RTW89_ACMA][4] = 40,
[0][1][2][1][RTW89_CN][4] = 36,
[0][1][2][1][RTW89_UK][4] = 40,
+ [0][1][2][1][RTW89_MEXICO][4] = 50,
+ [0][1][2][1][RTW89_UKRAINE][4] = 30,
+ [0][1][2][1][RTW89_CHILE][4] = 60,
+ [0][1][2][1][RTW89_QATAR][4] = 40,
[0][1][2][1][RTW89_FCC][6] = 62,
[0][1][2][1][RTW89_ETSI][6] = 40,
[0][1][2][1][RTW89_MKK][6] = 50,
[0][1][2][1][RTW89_IC][6] = 40,
- [0][1][2][1][RTW89_KCC][6] = 64,
+ [0][1][2][1][RTW89_KCC][6] = 40,
[0][1][2][1][RTW89_ACMA][6] = 40,
[0][1][2][1][RTW89_CN][6] = 36,
[0][1][2][1][RTW89_UK][6] = 40,
+ [0][1][2][1][RTW89_MEXICO][6] = 50,
+ [0][1][2][1][RTW89_UKRAINE][6] = 30,
+ [0][1][2][1][RTW89_CHILE][6] = 60,
+ [0][1][2][1][RTW89_QATAR][6] = 40,
[0][1][2][1][RTW89_FCC][8] = 62,
[0][1][2][1][RTW89_ETSI][8] = 40,
[0][1][2][1][RTW89_MKK][8] = 42,
@@ -31260,6 +35380,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][8] = 40,
[0][1][2][1][RTW89_CN][8] = 36,
[0][1][2][1][RTW89_UK][8] = 40,
+ [0][1][2][1][RTW89_MEXICO][8] = 62,
+ [0][1][2][1][RTW89_UKRAINE][8] = 30,
+ [0][1][2][1][RTW89_CHILE][8] = 60,
+ [0][1][2][1][RTW89_QATAR][8] = 40,
[0][1][2][1][RTW89_FCC][10] = 62,
[0][1][2][1][RTW89_ETSI][10] = 40,
[0][1][2][1][RTW89_MKK][10] = 54,
@@ -31268,6 +35392,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][10] = 40,
[0][1][2][1][RTW89_CN][10] = 36,
[0][1][2][1][RTW89_UK][10] = 40,
+ [0][1][2][1][RTW89_MEXICO][10] = 62,
+ [0][1][2][1][RTW89_UKRAINE][10] = 30,
+ [0][1][2][1][RTW89_CHILE][10] = 60,
+ [0][1][2][1][RTW89_QATAR][10] = 40,
[0][1][2][1][RTW89_FCC][12] = 62,
[0][1][2][1][RTW89_ETSI][12] = 40,
[0][1][2][1][RTW89_MKK][12] = 54,
@@ -31276,6 +35404,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][12] = 40,
[0][1][2][1][RTW89_CN][12] = 36,
[0][1][2][1][RTW89_UK][12] = 40,
+ [0][1][2][1][RTW89_MEXICO][12] = 62,
+ [0][1][2][1][RTW89_UKRAINE][12] = 30,
+ [0][1][2][1][RTW89_CHILE][12] = 60,
+ [0][1][2][1][RTW89_QATAR][12] = 40,
[0][1][2][1][RTW89_FCC][14] = 62,
[0][1][2][1][RTW89_ETSI][14] = 40,
[0][1][2][1][RTW89_MKK][14] = 54,
@@ -31284,6 +35416,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][14] = 40,
[0][1][2][1][RTW89_CN][14] = 36,
[0][1][2][1][RTW89_UK][14] = 40,
+ [0][1][2][1][RTW89_MEXICO][14] = 62,
+ [0][1][2][1][RTW89_UKRAINE][14] = 30,
+ [0][1][2][1][RTW89_CHILE][14] = 60,
+ [0][1][2][1][RTW89_QATAR][14] = 40,
[0][1][2][1][RTW89_FCC][15] = 60,
[0][1][2][1][RTW89_ETSI][15] = 40,
[0][1][2][1][RTW89_MKK][15] = 68,
@@ -31292,6 +35428,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][15] = 40,
[0][1][2][1][RTW89_CN][15] = 127,
[0][1][2][1][RTW89_UK][15] = 40,
+ [0][1][2][1][RTW89_MEXICO][15] = 60,
+ [0][1][2][1][RTW89_UKRAINE][15] = 30,
+ [0][1][2][1][RTW89_CHILE][15] = 60,
+ [0][1][2][1][RTW89_QATAR][15] = 40,
[0][1][2][1][RTW89_FCC][17] = 62,
[0][1][2][1][RTW89_ETSI][17] = 40,
[0][1][2][1][RTW89_MKK][17] = 68,
@@ -31300,6 +35440,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][17] = 40,
[0][1][2][1][RTW89_CN][17] = 127,
[0][1][2][1][RTW89_UK][17] = 40,
+ [0][1][2][1][RTW89_MEXICO][17] = 62,
+ [0][1][2][1][RTW89_UKRAINE][17] = 30,
+ [0][1][2][1][RTW89_CHILE][17] = 60,
+ [0][1][2][1][RTW89_QATAR][17] = 40,
[0][1][2][1][RTW89_FCC][19] = 62,
[0][1][2][1][RTW89_ETSI][19] = 40,
[0][1][2][1][RTW89_MKK][19] = 68,
@@ -31308,6 +35452,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][19] = 40,
[0][1][2][1][RTW89_CN][19] = 127,
[0][1][2][1][RTW89_UK][19] = 40,
+ [0][1][2][1][RTW89_MEXICO][19] = 62,
+ [0][1][2][1][RTW89_UKRAINE][19] = 30,
+ [0][1][2][1][RTW89_CHILE][19] = 60,
+ [0][1][2][1][RTW89_QATAR][19] = 40,
[0][1][2][1][RTW89_FCC][21] = 62,
[0][1][2][1][RTW89_ETSI][21] = 40,
[0][1][2][1][RTW89_MKK][21] = 68,
@@ -31316,6 +35464,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][21] = 40,
[0][1][2][1][RTW89_CN][21] = 127,
[0][1][2][1][RTW89_UK][21] = 40,
+ [0][1][2][1][RTW89_MEXICO][21] = 62,
+ [0][1][2][1][RTW89_UKRAINE][21] = 30,
+ [0][1][2][1][RTW89_CHILE][21] = 60,
+ [0][1][2][1][RTW89_QATAR][21] = 40,
[0][1][2][1][RTW89_FCC][23] = 62,
[0][1][2][1][RTW89_ETSI][23] = 40,
[0][1][2][1][RTW89_MKK][23] = 68,
@@ -31324,6 +35476,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][23] = 40,
[0][1][2][1][RTW89_CN][23] = 127,
[0][1][2][1][RTW89_UK][23] = 40,
+ [0][1][2][1][RTW89_MEXICO][23] = 62,
+ [0][1][2][1][RTW89_UKRAINE][23] = 30,
+ [0][1][2][1][RTW89_CHILE][23] = 60,
+ [0][1][2][1][RTW89_QATAR][23] = 40,
[0][1][2][1][RTW89_FCC][25] = 46,
[0][1][2][1][RTW89_ETSI][25] = 40,
[0][1][2][1][RTW89_MKK][25] = 68,
@@ -31332,6 +35488,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][25] = 127,
[0][1][2][1][RTW89_CN][25] = 127,
[0][1][2][1][RTW89_UK][25] = 40,
+ [0][1][2][1][RTW89_MEXICO][25] = 46,
+ [0][1][2][1][RTW89_UKRAINE][25] = 30,
+ [0][1][2][1][RTW89_CHILE][25] = 60,
+ [0][1][2][1][RTW89_QATAR][25] = 40,
[0][1][2][1][RTW89_FCC][27] = 46,
[0][1][2][1][RTW89_ETSI][27] = 40,
[0][1][2][1][RTW89_MKK][27] = 68,
@@ -31340,6 +35500,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][27] = 127,
[0][1][2][1][RTW89_CN][27] = 127,
[0][1][2][1][RTW89_UK][27] = 40,
+ [0][1][2][1][RTW89_MEXICO][27] = 46,
+ [0][1][2][1][RTW89_UKRAINE][27] = 30,
+ [0][1][2][1][RTW89_CHILE][27] = 46,
+ [0][1][2][1][RTW89_QATAR][27] = 40,
[0][1][2][1][RTW89_FCC][29] = 46,
[0][1][2][1][RTW89_ETSI][29] = 40,
[0][1][2][1][RTW89_MKK][29] = 68,
@@ -31348,6 +35512,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][29] = 127,
[0][1][2][1][RTW89_CN][29] = 127,
[0][1][2][1][RTW89_UK][29] = 40,
+ [0][1][2][1][RTW89_MEXICO][29] = 46,
+ [0][1][2][1][RTW89_UKRAINE][29] = 30,
+ [0][1][2][1][RTW89_CHILE][29] = 46,
+ [0][1][2][1][RTW89_QATAR][29] = 40,
[0][1][2][1][RTW89_FCC][31] = 46,
[0][1][2][1][RTW89_ETSI][31] = 40,
[0][1][2][1][RTW89_MKK][31] = 68,
@@ -31356,6 +35524,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][31] = 40,
[0][1][2][1][RTW89_CN][31] = 127,
[0][1][2][1][RTW89_UK][31] = 40,
+ [0][1][2][1][RTW89_MEXICO][31] = 46,
+ [0][1][2][1][RTW89_UKRAINE][31] = 30,
+ [0][1][2][1][RTW89_CHILE][31] = 46,
+ [0][1][2][1][RTW89_QATAR][31] = 40,
[0][1][2][1][RTW89_FCC][33] = 46,
[0][1][2][1][RTW89_ETSI][33] = 40,
[0][1][2][1][RTW89_MKK][33] = 68,
@@ -31364,6 +35536,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][33] = 40,
[0][1][2][1][RTW89_CN][33] = 127,
[0][1][2][1][RTW89_UK][33] = 40,
+ [0][1][2][1][RTW89_MEXICO][33] = 46,
+ [0][1][2][1][RTW89_UKRAINE][33] = 30,
+ [0][1][2][1][RTW89_CHILE][33] = 46,
+ [0][1][2][1][RTW89_QATAR][33] = 40,
[0][1][2][1][RTW89_FCC][35] = 46,
[0][1][2][1][RTW89_ETSI][35] = 40,
[0][1][2][1][RTW89_MKK][35] = 68,
@@ -31372,6 +35548,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][35] = 40,
[0][1][2][1][RTW89_CN][35] = 127,
[0][1][2][1][RTW89_UK][35] = 40,
+ [0][1][2][1][RTW89_MEXICO][35] = 46,
+ [0][1][2][1][RTW89_UKRAINE][35] = 30,
+ [0][1][2][1][RTW89_CHILE][35] = 46,
+ [0][1][2][1][RTW89_QATAR][35] = 40,
[0][1][2][1][RTW89_FCC][37] = 64,
[0][1][2][1][RTW89_ETSI][37] = 127,
[0][1][2][1][RTW89_MKK][37] = 68,
@@ -31380,6 +35560,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][37] = 64,
[0][1][2][1][RTW89_CN][37] = 127,
[0][1][2][1][RTW89_UK][37] = 40,
+ [0][1][2][1][RTW89_MEXICO][37] = 64,
+ [0][1][2][1][RTW89_UKRAINE][37] = 127,
+ [0][1][2][1][RTW89_CHILE][37] = 64,
+ [0][1][2][1][RTW89_QATAR][37] = 127,
[0][1][2][1][RTW89_FCC][38] = 72,
[0][1][2][1][RTW89_ETSI][38] = 6,
[0][1][2][1][RTW89_MKK][38] = 127,
@@ -31388,6 +35572,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][38] = 70,
[0][1][2][1][RTW89_CN][38] = 60,
[0][1][2][1][RTW89_UK][38] = 40,
+ [0][1][2][1][RTW89_MEXICO][38] = 72,
+ [0][1][2][1][RTW89_UKRAINE][38] = 6,
+ [0][1][2][1][RTW89_CHILE][38] = 60,
+ [0][1][2][1][RTW89_QATAR][38] = 6,
[0][1][2][1][RTW89_FCC][40] = 72,
[0][1][2][1][RTW89_ETSI][40] = 6,
[0][1][2][1][RTW89_MKK][40] = 127,
@@ -31396,6 +35584,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][40] = 70,
[0][1][2][1][RTW89_CN][40] = 60,
[0][1][2][1][RTW89_UK][40] = 40,
+ [0][1][2][1][RTW89_MEXICO][40] = 72,
+ [0][1][2][1][RTW89_UKRAINE][40] = 6,
+ [0][1][2][1][RTW89_CHILE][40] = 60,
+ [0][1][2][1][RTW89_QATAR][40] = 6,
[0][1][2][1][RTW89_FCC][42] = 72,
[0][1][2][1][RTW89_ETSI][42] = 6,
[0][1][2][1][RTW89_MKK][42] = 127,
@@ -31404,6 +35596,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][42] = 70,
[0][1][2][1][RTW89_CN][42] = 60,
[0][1][2][1][RTW89_UK][42] = 40,
+ [0][1][2][1][RTW89_MEXICO][42] = 72,
+ [0][1][2][1][RTW89_UKRAINE][42] = 6,
+ [0][1][2][1][RTW89_CHILE][42] = 60,
+ [0][1][2][1][RTW89_QATAR][42] = 6,
[0][1][2][1][RTW89_FCC][44] = 72,
[0][1][2][1][RTW89_ETSI][44] = 6,
[0][1][2][1][RTW89_MKK][44] = 127,
@@ -31412,6 +35608,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][44] = 70,
[0][1][2][1][RTW89_CN][44] = 54,
[0][1][2][1][RTW89_UK][44] = 40,
+ [0][1][2][1][RTW89_MEXICO][44] = 72,
+ [0][1][2][1][RTW89_UKRAINE][44] = 6,
+ [0][1][2][1][RTW89_CHILE][44] = 60,
+ [0][1][2][1][RTW89_QATAR][44] = 6,
[0][1][2][1][RTW89_FCC][46] = 72,
[0][1][2][1][RTW89_ETSI][46] = 6,
[0][1][2][1][RTW89_MKK][46] = 127,
@@ -31420,6 +35620,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][46] = 70,
[0][1][2][1][RTW89_CN][46] = 54,
[0][1][2][1][RTW89_UK][46] = 40,
+ [0][1][2][1][RTW89_MEXICO][46] = 72,
+ [0][1][2][1][RTW89_UKRAINE][46] = 6,
+ [0][1][2][1][RTW89_CHILE][46] = 60,
+ [0][1][2][1][RTW89_QATAR][46] = 6,
[0][1][2][1][RTW89_FCC][48] = 48,
[0][1][2][1][RTW89_ETSI][48] = 127,
[0][1][2][1][RTW89_MKK][48] = 127,
@@ -31428,6 +35632,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][48] = 127,
[0][1][2][1][RTW89_CN][48] = 127,
[0][1][2][1][RTW89_UK][48] = 127,
+ [0][1][2][1][RTW89_MEXICO][48] = 127,
+ [0][1][2][1][RTW89_UKRAINE][48] = 127,
+ [0][1][2][1][RTW89_CHILE][48] = 127,
+ [0][1][2][1][RTW89_QATAR][48] = 127,
[0][1][2][1][RTW89_FCC][50] = 50,
[0][1][2][1][RTW89_ETSI][50] = 127,
[0][1][2][1][RTW89_MKK][50] = 127,
@@ -31436,6 +35644,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][50] = 127,
[0][1][2][1][RTW89_CN][50] = 127,
[0][1][2][1][RTW89_UK][50] = 127,
+ [0][1][2][1][RTW89_MEXICO][50] = 127,
+ [0][1][2][1][RTW89_UKRAINE][50] = 127,
+ [0][1][2][1][RTW89_CHILE][50] = 127,
+ [0][1][2][1][RTW89_QATAR][50] = 127,
[0][1][2][1][RTW89_FCC][52] = 48,
[0][1][2][1][RTW89_ETSI][52] = 127,
[0][1][2][1][RTW89_MKK][52] = 127,
@@ -31444,22 +35656,34 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[0][1][2][1][RTW89_ACMA][52] = 127,
[0][1][2][1][RTW89_CN][52] = 127,
[0][1][2][1][RTW89_UK][52] = 127,
+ [0][1][2][1][RTW89_MEXICO][52] = 127,
+ [0][1][2][1][RTW89_UKRAINE][52] = 127,
+ [0][1][2][1][RTW89_CHILE][52] = 127,
+ [0][1][2][1][RTW89_QATAR][52] = 127,
[1][0][2][0][RTW89_FCC][1] = 64,
[1][0][2][0][RTW89_ETSI][1] = 66,
[1][0][2][0][RTW89_MKK][1] = 66,
[1][0][2][0][RTW89_IC][1] = 62,
- [1][0][2][0][RTW89_KCC][1] = 66,
+ [1][0][2][0][RTW89_KCC][1] = 54,
[1][0][2][0][RTW89_ACMA][1] = 66,
[1][0][2][0][RTW89_CN][1] = 54,
[1][0][2][0][RTW89_UK][1] = 66,
+ [1][0][2][0][RTW89_MEXICO][1] = 62,
+ [1][0][2][0][RTW89_UKRAINE][1] = 54,
+ [1][0][2][0][RTW89_CHILE][1] = 62,
+ [1][0][2][0][RTW89_QATAR][1] = 66,
[1][0][2][0][RTW89_FCC][5] = 68,
[1][0][2][0][RTW89_ETSI][5] = 66,
[1][0][2][0][RTW89_MKK][5] = 66,
[1][0][2][0][RTW89_IC][5] = 64,
- [1][0][2][0][RTW89_KCC][5] = 54,
+ [1][0][2][0][RTW89_KCC][5] = 66,
[1][0][2][0][RTW89_ACMA][5] = 66,
[1][0][2][0][RTW89_CN][5] = 54,
[1][0][2][0][RTW89_UK][5] = 66,
+ [1][0][2][0][RTW89_MEXICO][5] = 62,
+ [1][0][2][0][RTW89_UKRAINE][5] = 54,
+ [1][0][2][0][RTW89_CHILE][5] = 66,
+ [1][0][2][0][RTW89_QATAR][5] = 66,
[1][0][2][0][RTW89_FCC][9] = 68,
[1][0][2][0][RTW89_ETSI][9] = 66,
[1][0][2][0][RTW89_MKK][9] = 66,
@@ -31468,6 +35692,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_ACMA][9] = 66,
[1][0][2][0][RTW89_CN][9] = 54,
[1][0][2][0][RTW89_UK][9] = 66,
+ [1][0][2][0][RTW89_MEXICO][9] = 68,
+ [1][0][2][0][RTW89_UKRAINE][9] = 54,
+ [1][0][2][0][RTW89_CHILE][9] = 66,
+ [1][0][2][0][RTW89_QATAR][9] = 66,
[1][0][2][0][RTW89_FCC][13] = 60,
[1][0][2][0][RTW89_ETSI][13] = 66,
[1][0][2][0][RTW89_MKK][13] = 66,
@@ -31476,6 +35704,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_ACMA][13] = 66,
[1][0][2][0][RTW89_CN][13] = 54,
[1][0][2][0][RTW89_UK][13] = 66,
+ [1][0][2][0][RTW89_MEXICO][13] = 60,
+ [1][0][2][0][RTW89_UKRAINE][13] = 54,
+ [1][0][2][0][RTW89_CHILE][13] = 60,
+ [1][0][2][0][RTW89_QATAR][13] = 66,
[1][0][2][0][RTW89_FCC][16] = 64,
[1][0][2][0][RTW89_ETSI][16] = 66,
[1][0][2][0][RTW89_MKK][16] = 66,
@@ -31484,6 +35716,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_ACMA][16] = 66,
[1][0][2][0][RTW89_CN][16] = 127,
[1][0][2][0][RTW89_UK][16] = 66,
+ [1][0][2][0][RTW89_MEXICO][16] = 64,
+ [1][0][2][0][RTW89_UKRAINE][16] = 54,
+ [1][0][2][0][RTW89_CHILE][16] = 64,
+ [1][0][2][0][RTW89_QATAR][16] = 66,
[1][0][2][0][RTW89_FCC][20] = 68,
[1][0][2][0][RTW89_ETSI][20] = 66,
[1][0][2][0][RTW89_MKK][20] = 66,
@@ -31492,6 +35728,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_ACMA][20] = 66,
[1][0][2][0][RTW89_CN][20] = 127,
[1][0][2][0][RTW89_UK][20] = 66,
+ [1][0][2][0][RTW89_MEXICO][20] = 68,
+ [1][0][2][0][RTW89_UKRAINE][20] = 54,
+ [1][0][2][0][RTW89_CHILE][20] = 66,
+ [1][0][2][0][RTW89_QATAR][20] = 66,
[1][0][2][0][RTW89_FCC][24] = 68,
[1][0][2][0][RTW89_ETSI][24] = 66,
[1][0][2][0][RTW89_MKK][24] = 66,
@@ -31500,6 +35740,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_ACMA][24] = 127,
[1][0][2][0][RTW89_CN][24] = 127,
[1][0][2][0][RTW89_UK][24] = 66,
+ [1][0][2][0][RTW89_MEXICO][24] = 68,
+ [1][0][2][0][RTW89_UKRAINE][24] = 54,
+ [1][0][2][0][RTW89_CHILE][24] = 66,
+ [1][0][2][0][RTW89_QATAR][24] = 66,
[1][0][2][0][RTW89_FCC][28] = 68,
[1][0][2][0][RTW89_ETSI][28] = 66,
[1][0][2][0][RTW89_MKK][28] = 66,
@@ -31508,6 +35752,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_ACMA][28] = 127,
[1][0][2][0][RTW89_CN][28] = 127,
[1][0][2][0][RTW89_UK][28] = 66,
+ [1][0][2][0][RTW89_MEXICO][28] = 68,
+ [1][0][2][0][RTW89_UKRAINE][28] = 54,
+ [1][0][2][0][RTW89_CHILE][28] = 62,
+ [1][0][2][0][RTW89_QATAR][28] = 66,
[1][0][2][0][RTW89_FCC][32] = 62,
[1][0][2][0][RTW89_ETSI][32] = 66,
[1][0][2][0][RTW89_MKK][32] = 66,
@@ -31516,6 +35764,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_ACMA][32] = 66,
[1][0][2][0][RTW89_CN][32] = 127,
[1][0][2][0][RTW89_UK][32] = 66,
+ [1][0][2][0][RTW89_MEXICO][32] = 62,
+ [1][0][2][0][RTW89_UKRAINE][32] = 54,
+ [1][0][2][0][RTW89_CHILE][32] = 62,
+ [1][0][2][0][RTW89_QATAR][32] = 66,
[1][0][2][0][RTW89_FCC][36] = 68,
[1][0][2][0][RTW89_ETSI][36] = 127,
[1][0][2][0][RTW89_MKK][36] = 66,
@@ -31524,6 +35776,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_ACMA][36] = 66,
[1][0][2][0][RTW89_CN][36] = 127,
[1][0][2][0][RTW89_UK][36] = 64,
+ [1][0][2][0][RTW89_MEXICO][36] = 68,
+ [1][0][2][0][RTW89_UKRAINE][36] = 127,
+ [1][0][2][0][RTW89_CHILE][36] = 66,
+ [1][0][2][0][RTW89_QATAR][36] = 127,
[1][0][2][0][RTW89_FCC][39] = 68,
[1][0][2][0][RTW89_ETSI][39] = 30,
[1][0][2][0][RTW89_MKK][39] = 127,
@@ -31532,6 +35788,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_ACMA][39] = 66,
[1][0][2][0][RTW89_CN][39] = 62,
[1][0][2][0][RTW89_UK][39] = 64,
+ [1][0][2][0][RTW89_MEXICO][39] = 68,
+ [1][0][2][0][RTW89_UKRAINE][39] = 30,
+ [1][0][2][0][RTW89_CHILE][39] = 66,
+ [1][0][2][0][RTW89_QATAR][39] = 30,
[1][0][2][0][RTW89_FCC][43] = 68,
[1][0][2][0][RTW89_ETSI][43] = 30,
[1][0][2][0][RTW89_MKK][43] = 127,
@@ -31540,6 +35800,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_ACMA][43] = 66,
[1][0][2][0][RTW89_CN][43] = 66,
[1][0][2][0][RTW89_UK][43] = 64,
+ [1][0][2][0][RTW89_MEXICO][43] = 68,
+ [1][0][2][0][RTW89_UKRAINE][43] = 30,
+ [1][0][2][0][RTW89_CHILE][43] = 66,
+ [1][0][2][0][RTW89_QATAR][43] = 30,
[1][0][2][0][RTW89_FCC][47] = 68,
[1][0][2][0][RTW89_ETSI][47] = 127,
[1][0][2][0][RTW89_MKK][47] = 127,
@@ -31548,6 +35812,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_ACMA][47] = 127,
[1][0][2][0][RTW89_CN][47] = 127,
[1][0][2][0][RTW89_UK][47] = 127,
+ [1][0][2][0][RTW89_MEXICO][47] = 127,
+ [1][0][2][0][RTW89_UKRAINE][47] = 127,
+ [1][0][2][0][RTW89_CHILE][47] = 127,
+ [1][0][2][0][RTW89_QATAR][47] = 127,
[1][0][2][0][RTW89_FCC][51] = 68,
[1][0][2][0][RTW89_ETSI][51] = 127,
[1][0][2][0][RTW89_MKK][51] = 127,
@@ -31556,6 +35824,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][0][2][0][RTW89_ACMA][51] = 127,
[1][0][2][0][RTW89_CN][51] = 127,
[1][0][2][0][RTW89_UK][51] = 127,
+ [1][0][2][0][RTW89_MEXICO][51] = 127,
+ [1][0][2][0][RTW89_UKRAINE][51] = 127,
+ [1][0][2][0][RTW89_CHILE][51] = 127,
+ [1][0][2][0][RTW89_QATAR][51] = 127,
[1][1][2][0][RTW89_FCC][1] = 54,
[1][1][2][0][RTW89_ETSI][1] = 54,
[1][1][2][0][RTW89_MKK][1] = 48,
@@ -31564,6 +35836,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][0][RTW89_ACMA][1] = 54,
[1][1][2][0][RTW89_CN][1] = 42,
[1][1][2][0][RTW89_UK][1] = 54,
+ [1][1][2][0][RTW89_MEXICO][1] = 50,
+ [1][1][2][0][RTW89_UKRAINE][1] = 42,
+ [1][1][2][0][RTW89_CHILE][1] = 54,
+ [1][1][2][0][RTW89_QATAR][1] = 54,
[1][1][2][0][RTW89_FCC][5] = 68,
[1][1][2][0][RTW89_ETSI][5] = 54,
[1][1][2][0][RTW89_MKK][5] = 52,
@@ -31572,6 +35848,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][0][RTW89_ACMA][5] = 54,
[1][1][2][0][RTW89_CN][5] = 42,
[1][1][2][0][RTW89_UK][5] = 54,
+ [1][1][2][0][RTW89_MEXICO][5] = 50,
+ [1][1][2][0][RTW89_UKRAINE][5] = 42,
+ [1][1][2][0][RTW89_CHILE][5] = 66,
+ [1][1][2][0][RTW89_QATAR][5] = 54,
[1][1][2][0][RTW89_FCC][9] = 68,
[1][1][2][0][RTW89_ETSI][9] = 54,
[1][1][2][0][RTW89_MKK][9] = 52,
@@ -31580,6 +35860,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][0][RTW89_ACMA][9] = 54,
[1][1][2][0][RTW89_CN][9] = 42,
[1][1][2][0][RTW89_UK][9] = 54,
+ [1][1][2][0][RTW89_MEXICO][9] = 68,
+ [1][1][2][0][RTW89_UKRAINE][9] = 42,
+ [1][1][2][0][RTW89_CHILE][9] = 66,
+ [1][1][2][0][RTW89_QATAR][9] = 54,
[1][1][2][0][RTW89_FCC][13] = 54,
[1][1][2][0][RTW89_ETSI][13] = 54,
[1][1][2][0][RTW89_MKK][13] = 52,
@@ -31588,6 +35872,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][0][RTW89_ACMA][13] = 54,
[1][1][2][0][RTW89_CN][13] = 42,
[1][1][2][0][RTW89_UK][13] = 54,
+ [1][1][2][0][RTW89_MEXICO][13] = 54,
+ [1][1][2][0][RTW89_UKRAINE][13] = 42,
+ [1][1][2][0][RTW89_CHILE][13] = 54,
+ [1][1][2][0][RTW89_QATAR][13] = 54,
[1][1][2][0][RTW89_FCC][16] = 56,
[1][1][2][0][RTW89_ETSI][16] = 54,
[1][1][2][0][RTW89_MKK][16] = 66,
@@ -31596,6 +35884,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][0][RTW89_ACMA][16] = 54,
[1][1][2][0][RTW89_CN][16] = 127,
[1][1][2][0][RTW89_UK][16] = 54,
+ [1][1][2][0][RTW89_MEXICO][16] = 56,
+ [1][1][2][0][RTW89_UKRAINE][16] = 42,
+ [1][1][2][0][RTW89_CHILE][16] = 54,
+ [1][1][2][0][RTW89_QATAR][16] = 54,
[1][1][2][0][RTW89_FCC][20] = 68,
[1][1][2][0][RTW89_ETSI][20] = 54,
[1][1][2][0][RTW89_MKK][20] = 66,
@@ -31604,6 +35896,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][0][RTW89_ACMA][20] = 54,
[1][1][2][0][RTW89_CN][20] = 127,
[1][1][2][0][RTW89_UK][20] = 54,
+ [1][1][2][0][RTW89_MEXICO][20] = 68,
+ [1][1][2][0][RTW89_UKRAINE][20] = 42,
+ [1][1][2][0][RTW89_CHILE][20] = 66,
+ [1][1][2][0][RTW89_QATAR][20] = 54,
[1][1][2][0][RTW89_FCC][24] = 68,
[1][1][2][0][RTW89_ETSI][24] = 54,
[1][1][2][0][RTW89_MKK][24] = 66,
@@ -31612,6 +35908,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][0][RTW89_ACMA][24] = 127,
[1][1][2][0][RTW89_CN][24] = 127,
[1][1][2][0][RTW89_UK][24] = 54,
+ [1][1][2][0][RTW89_MEXICO][24] = 68,
+ [1][1][2][0][RTW89_UKRAINE][24] = 42,
+ [1][1][2][0][RTW89_CHILE][24] = 66,
+ [1][1][2][0][RTW89_QATAR][24] = 54,
[1][1][2][0][RTW89_FCC][28] = 68,
[1][1][2][0][RTW89_ETSI][28] = 54,
[1][1][2][0][RTW89_MKK][28] = 66,
@@ -31620,6 +35920,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][0][RTW89_ACMA][28] = 127,
[1][1][2][0][RTW89_CN][28] = 127,
[1][1][2][0][RTW89_UK][28] = 54,
+ [1][1][2][0][RTW89_MEXICO][28] = 68,
+ [1][1][2][0][RTW89_UKRAINE][28] = 42,
+ [1][1][2][0][RTW89_CHILE][28] = 54,
+ [1][1][2][0][RTW89_QATAR][28] = 54,
[1][1][2][0][RTW89_FCC][32] = 56,
[1][1][2][0][RTW89_ETSI][32] = 54,
[1][1][2][0][RTW89_MKK][32] = 66,
@@ -31628,6 +35932,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][0][RTW89_ACMA][32] = 54,
[1][1][2][0][RTW89_CN][32] = 127,
[1][1][2][0][RTW89_UK][32] = 54,
+ [1][1][2][0][RTW89_MEXICO][32] = 56,
+ [1][1][2][0][RTW89_UKRAINE][32] = 42,
+ [1][1][2][0][RTW89_CHILE][32] = 54,
+ [1][1][2][0][RTW89_QATAR][32] = 54,
[1][1][2][0][RTW89_FCC][36] = 68,
[1][1][2][0][RTW89_ETSI][36] = 127,
[1][1][2][0][RTW89_MKK][36] = 66,
@@ -31636,6 +35944,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][0][RTW89_ACMA][36] = 66,
[1][1][2][0][RTW89_CN][36] = 127,
[1][1][2][0][RTW89_UK][36] = 52,
+ [1][1][2][0][RTW89_MEXICO][36] = 68,
+ [1][1][2][0][RTW89_UKRAINE][36] = 127,
+ [1][1][2][0][RTW89_CHILE][36] = 66,
+ [1][1][2][0][RTW89_QATAR][36] = 127,
[1][1][2][0][RTW89_FCC][39] = 68,
[1][1][2][0][RTW89_ETSI][39] = 18,
[1][1][2][0][RTW89_MKK][39] = 127,
@@ -31644,6 +35956,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][0][RTW89_ACMA][39] = 66,
[1][1][2][0][RTW89_CN][39] = 62,
[1][1][2][0][RTW89_UK][39] = 52,
+ [1][1][2][0][RTW89_MEXICO][39] = 68,
+ [1][1][2][0][RTW89_UKRAINE][39] = 18,
+ [1][1][2][0][RTW89_CHILE][39] = 66,
+ [1][1][2][0][RTW89_QATAR][39] = 18,
[1][1][2][0][RTW89_FCC][43] = 68,
[1][1][2][0][RTW89_ETSI][43] = 18,
[1][1][2][0][RTW89_MKK][43] = 127,
@@ -31652,6 +35968,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][0][RTW89_ACMA][43] = 66,
[1][1][2][0][RTW89_CN][43] = 66,
[1][1][2][0][RTW89_UK][43] = 52,
+ [1][1][2][0][RTW89_MEXICO][43] = 68,
+ [1][1][2][0][RTW89_UKRAINE][43] = 18,
+ [1][1][2][0][RTW89_CHILE][43] = 66,
+ [1][1][2][0][RTW89_QATAR][43] = 18,
[1][1][2][0][RTW89_FCC][47] = 62,
[1][1][2][0][RTW89_ETSI][47] = 127,
[1][1][2][0][RTW89_MKK][47] = 127,
@@ -31660,6 +35980,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][0][RTW89_ACMA][47] = 127,
[1][1][2][0][RTW89_CN][47] = 127,
[1][1][2][0][RTW89_UK][47] = 127,
+ [1][1][2][0][RTW89_MEXICO][47] = 127,
+ [1][1][2][0][RTW89_UKRAINE][47] = 127,
+ [1][1][2][0][RTW89_CHILE][47] = 127,
+ [1][1][2][0][RTW89_QATAR][47] = 127,
[1][1][2][0][RTW89_FCC][51] = 60,
[1][1][2][0][RTW89_ETSI][51] = 127,
[1][1][2][0][RTW89_MKK][51] = 127,
@@ -31668,6 +35992,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][0][RTW89_ACMA][51] = 127,
[1][1][2][0][RTW89_CN][51] = 127,
[1][1][2][0][RTW89_UK][51] = 127,
+ [1][1][2][0][RTW89_MEXICO][51] = 127,
+ [1][1][2][0][RTW89_UKRAINE][51] = 127,
+ [1][1][2][0][RTW89_CHILE][51] = 127,
+ [1][1][2][0][RTW89_QATAR][51] = 127,
[1][1][2][1][RTW89_FCC][1] = 54,
[1][1][2][1][RTW89_ETSI][1] = 40,
[1][1][2][1][RTW89_MKK][1] = 48,
@@ -31676,6 +36004,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][1][RTW89_ACMA][1] = 40,
[1][1][2][1][RTW89_CN][1] = 42,
[1][1][2][1][RTW89_UK][1] = 40,
+ [1][1][2][1][RTW89_MEXICO][1] = 50,
+ [1][1][2][1][RTW89_UKRAINE][1] = 30,
+ [1][1][2][1][RTW89_CHILE][1] = 54,
+ [1][1][2][1][RTW89_QATAR][1] = 40,
[1][1][2][1][RTW89_FCC][5] = 68,
[1][1][2][1][RTW89_ETSI][5] = 40,
[1][1][2][1][RTW89_MKK][5] = 52,
@@ -31684,6 +36016,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][1][RTW89_ACMA][5] = 40,
[1][1][2][1][RTW89_CN][5] = 42,
[1][1][2][1][RTW89_UK][5] = 40,
+ [1][1][2][1][RTW89_MEXICO][5] = 50,
+ [1][1][2][1][RTW89_UKRAINE][5] = 30,
+ [1][1][2][1][RTW89_CHILE][5] = 60,
+ [1][1][2][1][RTW89_QATAR][5] = 40,
[1][1][2][1][RTW89_FCC][9] = 68,
[1][1][2][1][RTW89_ETSI][9] = 40,
[1][1][2][1][RTW89_MKK][9] = 52,
@@ -31692,6 +36028,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][1][RTW89_ACMA][9] = 40,
[1][1][2][1][RTW89_CN][9] = 42,
[1][1][2][1][RTW89_UK][9] = 40,
+ [1][1][2][1][RTW89_MEXICO][9] = 68,
+ [1][1][2][1][RTW89_UKRAINE][9] = 30,
+ [1][1][2][1][RTW89_CHILE][9] = 60,
+ [1][1][2][1][RTW89_QATAR][9] = 40,
[1][1][2][1][RTW89_FCC][13] = 54,
[1][1][2][1][RTW89_ETSI][13] = 40,
[1][1][2][1][RTW89_MKK][13] = 52,
@@ -31700,6 +36040,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][1][RTW89_ACMA][13] = 40,
[1][1][2][1][RTW89_CN][13] = 42,
[1][1][2][1][RTW89_UK][13] = 40,
+ [1][1][2][1][RTW89_MEXICO][13] = 54,
+ [1][1][2][1][RTW89_UKRAINE][13] = 30,
+ [1][1][2][1][RTW89_CHILE][13] = 54,
+ [1][1][2][1][RTW89_QATAR][13] = 40,
[1][1][2][1][RTW89_FCC][16] = 56,
[1][1][2][1][RTW89_ETSI][16] = 40,
[1][1][2][1][RTW89_MKK][16] = 66,
@@ -31708,6 +36052,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][1][RTW89_ACMA][16] = 40,
[1][1][2][1][RTW89_CN][16] = 127,
[1][1][2][1][RTW89_UK][16] = 40,
+ [1][1][2][1][RTW89_MEXICO][16] = 56,
+ [1][1][2][1][RTW89_UKRAINE][16] = 30,
+ [1][1][2][1][RTW89_CHILE][16] = 54,
+ [1][1][2][1][RTW89_QATAR][16] = 40,
[1][1][2][1][RTW89_FCC][20] = 68,
[1][1][2][1][RTW89_ETSI][20] = 40,
[1][1][2][1][RTW89_MKK][20] = 66,
@@ -31716,6 +36064,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][1][RTW89_ACMA][20] = 40,
[1][1][2][1][RTW89_CN][20] = 127,
[1][1][2][1][RTW89_UK][20] = 40,
+ [1][1][2][1][RTW89_MEXICO][20] = 68,
+ [1][1][2][1][RTW89_UKRAINE][20] = 30,
+ [1][1][2][1][RTW89_CHILE][20] = 60,
+ [1][1][2][1][RTW89_QATAR][20] = 40,
[1][1][2][1][RTW89_FCC][24] = 68,
[1][1][2][1][RTW89_ETSI][24] = 40,
[1][1][2][1][RTW89_MKK][24] = 66,
@@ -31724,6 +36076,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][1][RTW89_ACMA][24] = 127,
[1][1][2][1][RTW89_CN][24] = 127,
[1][1][2][1][RTW89_UK][24] = 40,
+ [1][1][2][1][RTW89_MEXICO][24] = 68,
+ [1][1][2][1][RTW89_UKRAINE][24] = 30,
+ [1][1][2][1][RTW89_CHILE][24] = 60,
+ [1][1][2][1][RTW89_QATAR][24] = 40,
[1][1][2][1][RTW89_FCC][28] = 68,
[1][1][2][1][RTW89_ETSI][28] = 40,
[1][1][2][1][RTW89_MKK][28] = 66,
@@ -31732,6 +36088,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][1][RTW89_ACMA][28] = 127,
[1][1][2][1][RTW89_CN][28] = 127,
[1][1][2][1][RTW89_UK][28] = 40,
+ [1][1][2][1][RTW89_MEXICO][28] = 68,
+ [1][1][2][1][RTW89_UKRAINE][28] = 30,
+ [1][1][2][1][RTW89_CHILE][28] = 54,
+ [1][1][2][1][RTW89_QATAR][28] = 40,
[1][1][2][1][RTW89_FCC][32] = 56,
[1][1][2][1][RTW89_ETSI][32] = 40,
[1][1][2][1][RTW89_MKK][32] = 66,
@@ -31740,6 +36100,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][1][RTW89_ACMA][32] = 40,
[1][1][2][1][RTW89_CN][32] = 127,
[1][1][2][1][RTW89_UK][32] = 40,
+ [1][1][2][1][RTW89_MEXICO][32] = 56,
+ [1][1][2][1][RTW89_UKRAINE][32] = 30,
+ [1][1][2][1][RTW89_CHILE][32] = 54,
+ [1][1][2][1][RTW89_QATAR][32] = 40,
[1][1][2][1][RTW89_FCC][36] = 68,
[1][1][2][1][RTW89_ETSI][36] = 127,
[1][1][2][1][RTW89_MKK][36] = 66,
@@ -31748,6 +36112,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][1][RTW89_ACMA][36] = 66,
[1][1][2][1][RTW89_CN][36] = 127,
[1][1][2][1][RTW89_UK][36] = 40,
+ [1][1][2][1][RTW89_MEXICO][36] = 68,
+ [1][1][2][1][RTW89_UKRAINE][36] = 127,
+ [1][1][2][1][RTW89_CHILE][36] = 66,
+ [1][1][2][1][RTW89_QATAR][36] = 127,
[1][1][2][1][RTW89_FCC][39] = 68,
[1][1][2][1][RTW89_ETSI][39] = 6,
[1][1][2][1][RTW89_MKK][39] = 127,
@@ -31756,6 +36124,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][1][RTW89_ACMA][39] = 66,
[1][1][2][1][RTW89_CN][39] = 60,
[1][1][2][1][RTW89_UK][39] = 40,
+ [1][1][2][1][RTW89_MEXICO][39] = 68,
+ [1][1][2][1][RTW89_UKRAINE][39] = 6,
+ [1][1][2][1][RTW89_CHILE][39] = 60,
+ [1][1][2][1][RTW89_QATAR][39] = 6,
[1][1][2][1][RTW89_FCC][43] = 68,
[1][1][2][1][RTW89_ETSI][43] = 6,
[1][1][2][1][RTW89_MKK][43] = 127,
@@ -31764,6 +36136,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][1][RTW89_ACMA][43] = 66,
[1][1][2][1][RTW89_CN][43] = 52,
[1][1][2][1][RTW89_UK][43] = 40,
+ [1][1][2][1][RTW89_MEXICO][43] = 68,
+ [1][1][2][1][RTW89_UKRAINE][43] = 6,
+ [1][1][2][1][RTW89_CHILE][43] = 60,
+ [1][1][2][1][RTW89_QATAR][43] = 6,
[1][1][2][1][RTW89_FCC][47] = 62,
[1][1][2][1][RTW89_ETSI][47] = 127,
[1][1][2][1][RTW89_MKK][47] = 127,
@@ -31772,6 +36148,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][1][RTW89_ACMA][47] = 127,
[1][1][2][1][RTW89_CN][47] = 127,
[1][1][2][1][RTW89_UK][47] = 127,
+ [1][1][2][1][RTW89_MEXICO][47] = 127,
+ [1][1][2][1][RTW89_UKRAINE][47] = 127,
+ [1][1][2][1][RTW89_CHILE][47] = 127,
+ [1][1][2][1][RTW89_QATAR][47] = 127,
[1][1][2][1][RTW89_FCC][51] = 60,
[1][1][2][1][RTW89_ETSI][51] = 127,
[1][1][2][1][RTW89_MKK][51] = 127,
@@ -31780,6 +36160,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[1][1][2][1][RTW89_ACMA][51] = 127,
[1][1][2][1][RTW89_CN][51] = 127,
[1][1][2][1][RTW89_UK][51] = 127,
+ [1][1][2][1][RTW89_MEXICO][51] = 127,
+ [1][1][2][1][RTW89_UKRAINE][51] = 127,
+ [1][1][2][1][RTW89_CHILE][51] = 127,
+ [1][1][2][1][RTW89_QATAR][51] = 127,
[2][0][2][0][RTW89_FCC][3] = 58,
[2][0][2][0][RTW89_ETSI][3] = 60,
[2][0][2][0][RTW89_MKK][3] = 60,
@@ -31788,6 +36172,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[2][0][2][0][RTW89_ACMA][3] = 60,
[2][0][2][0][RTW89_CN][3] = 54,
[2][0][2][0][RTW89_UK][3] = 60,
+ [2][0][2][0][RTW89_MEXICO][3] = 58,
+ [2][0][2][0][RTW89_UKRAINE][3] = 54,
+ [2][0][2][0][RTW89_CHILE][3] = 58,
+ [2][0][2][0][RTW89_QATAR][3] = 60,
[2][0][2][0][RTW89_FCC][11] = 50,
[2][0][2][0][RTW89_ETSI][11] = 60,
[2][0][2][0][RTW89_MKK][11] = 60,
@@ -31796,6 +36184,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[2][0][2][0][RTW89_ACMA][11] = 60,
[2][0][2][0][RTW89_CN][11] = 54,
[2][0][2][0][RTW89_UK][11] = 60,
+ [2][0][2][0][RTW89_MEXICO][11] = 50,
+ [2][0][2][0][RTW89_UKRAINE][11] = 54,
+ [2][0][2][0][RTW89_CHILE][11] = 50,
+ [2][0][2][0][RTW89_QATAR][11] = 60,
[2][0][2][0][RTW89_FCC][18] = 60,
[2][0][2][0][RTW89_ETSI][18] = 60,
[2][0][2][0][RTW89_MKK][18] = 60,
@@ -31804,6 +36196,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[2][0][2][0][RTW89_ACMA][18] = 60,
[2][0][2][0][RTW89_CN][18] = 127,
[2][0][2][0][RTW89_UK][18] = 60,
+ [2][0][2][0][RTW89_MEXICO][18] = 60,
+ [2][0][2][0][RTW89_UKRAINE][18] = 54,
+ [2][0][2][0][RTW89_CHILE][18] = 60,
+ [2][0][2][0][RTW89_QATAR][18] = 60,
[2][0][2][0][RTW89_FCC][26] = 62,
[2][0][2][0][RTW89_ETSI][26] = 60,
[2][0][2][0][RTW89_MKK][26] = 60,
@@ -31812,6 +36208,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[2][0][2][0][RTW89_ACMA][26] = 127,
[2][0][2][0][RTW89_CN][26] = 127,
[2][0][2][0][RTW89_UK][26] = 60,
+ [2][0][2][0][RTW89_MEXICO][26] = 62,
+ [2][0][2][0][RTW89_UKRAINE][26] = 54,
+ [2][0][2][0][RTW89_CHILE][26] = 60,
+ [2][0][2][0][RTW89_QATAR][26] = 60,
[2][0][2][0][RTW89_FCC][34] = 62,
[2][0][2][0][RTW89_ETSI][34] = 127,
[2][0][2][0][RTW89_MKK][34] = 60,
@@ -31820,6 +36220,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[2][0][2][0][RTW89_ACMA][34] = 60,
[2][0][2][0][RTW89_CN][34] = 127,
[2][0][2][0][RTW89_UK][34] = 60,
+ [2][0][2][0][RTW89_MEXICO][34] = 62,
+ [2][0][2][0][RTW89_UKRAINE][34] = 127,
+ [2][0][2][0][RTW89_CHILE][34] = 60,
+ [2][0][2][0][RTW89_QATAR][34] = 127,
[2][0][2][0][RTW89_FCC][41] = 62,
[2][0][2][0][RTW89_ETSI][41] = 30,
[2][0][2][0][RTW89_MKK][41] = 127,
@@ -31828,6 +36232,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[2][0][2][0][RTW89_ACMA][41] = 60,
[2][0][2][0][RTW89_CN][41] = 62,
[2][0][2][0][RTW89_UK][41] = 60,
+ [2][0][2][0][RTW89_MEXICO][41] = 62,
+ [2][0][2][0][RTW89_UKRAINE][41] = 30,
+ [2][0][2][0][RTW89_CHILE][41] = 60,
+ [2][0][2][0][RTW89_QATAR][41] = 30,
[2][0][2][0][RTW89_FCC][49] = 62,
[2][0][2][0][RTW89_ETSI][49] = 127,
[2][0][2][0][RTW89_MKK][49] = 127,
@@ -31836,6 +36244,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[2][0][2][0][RTW89_ACMA][49] = 127,
[2][0][2][0][RTW89_CN][49] = 127,
[2][0][2][0][RTW89_UK][49] = 127,
+ [2][0][2][0][RTW89_MEXICO][49] = 127,
+ [2][0][2][0][RTW89_UKRAINE][49] = 127,
+ [2][0][2][0][RTW89_CHILE][49] = 127,
+ [2][0][2][0][RTW89_QATAR][49] = 127,
[2][1][2][0][RTW89_FCC][3] = 48,
[2][1][2][0][RTW89_ETSI][3] = 54,
[2][1][2][0][RTW89_MKK][3] = 56,
@@ -31844,6 +36256,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[2][1][2][0][RTW89_ACMA][3] = 54,
[2][1][2][0][RTW89_CN][3] = 52,
[2][1][2][0][RTW89_UK][3] = 54,
+ [2][1][2][0][RTW89_MEXICO][3] = 48,
+ [2][1][2][0][RTW89_UKRAINE][3] = 42,
+ [2][1][2][0][RTW89_CHILE][3] = 46,
+ [2][1][2][0][RTW89_QATAR][3] = 54,
[2][1][2][0][RTW89_FCC][11] = 38,
[2][1][2][0][RTW89_ETSI][11] = 54,
[2][1][2][0][RTW89_MKK][11] = 54,
@@ -31852,6 +36268,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[2][1][2][0][RTW89_ACMA][11] = 54,
[2][1][2][0][RTW89_CN][11] = 52,
[2][1][2][0][RTW89_UK][11] = 54,
+ [2][1][2][0][RTW89_MEXICO][11] = 38,
+ [2][1][2][0][RTW89_UKRAINE][11] = 42,
+ [2][1][2][0][RTW89_CHILE][11] = 38,
+ [2][1][2][0][RTW89_QATAR][11] = 54,
[2][1][2][0][RTW89_FCC][18] = 50,
[2][1][2][0][RTW89_ETSI][18] = 54,
[2][1][2][0][RTW89_MKK][18] = 60,
@@ -31860,6 +36280,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[2][1][2][0][RTW89_ACMA][18] = 54,
[2][1][2][0][RTW89_CN][18] = 127,
[2][1][2][0][RTW89_UK][18] = 54,
+ [2][1][2][0][RTW89_MEXICO][18] = 50,
+ [2][1][2][0][RTW89_UKRAINE][18] = 42,
+ [2][1][2][0][RTW89_CHILE][18] = 50,
+ [2][1][2][0][RTW89_QATAR][18] = 54,
[2][1][2][0][RTW89_FCC][26] = 52,
[2][1][2][0][RTW89_ETSI][26] = 54,
[2][1][2][0][RTW89_MKK][26] = 56,
@@ -31868,6 +36292,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[2][1][2][0][RTW89_ACMA][26] = 127,
[2][1][2][0][RTW89_CN][26] = 127,
[2][1][2][0][RTW89_UK][26] = 54,
+ [2][1][2][0][RTW89_MEXICO][26] = 52,
+ [2][1][2][0][RTW89_UKRAINE][26] = 42,
+ [2][1][2][0][RTW89_CHILE][26] = 52,
+ [2][1][2][0][RTW89_QATAR][26] = 54,
[2][1][2][0][RTW89_FCC][34] = 62,
[2][1][2][0][RTW89_ETSI][34] = 127,
[2][1][2][0][RTW89_MKK][34] = 60,
@@ -31876,6 +36304,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[2][1][2][0][RTW89_ACMA][34] = 60,
[2][1][2][0][RTW89_CN][34] = 127,
[2][1][2][0][RTW89_UK][34] = 52,
+ [2][1][2][0][RTW89_MEXICO][34] = 62,
+ [2][1][2][0][RTW89_UKRAINE][34] = 127,
+ [2][1][2][0][RTW89_CHILE][34] = 60,
+ [2][1][2][0][RTW89_QATAR][34] = 127,
[2][1][2][0][RTW89_FCC][41] = 60,
[2][1][2][0][RTW89_ETSI][41] = 18,
[2][1][2][0][RTW89_MKK][41] = 127,
@@ -31884,6 +36316,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[2][1][2][0][RTW89_ACMA][41] = 58,
[2][1][2][0][RTW89_CN][41] = 62,
[2][1][2][0][RTW89_UK][41] = 52,
+ [2][1][2][0][RTW89_MEXICO][41] = 60,
+ [2][1][2][0][RTW89_UKRAINE][41] = 18,
+ [2][1][2][0][RTW89_CHILE][41] = 58,
+ [2][1][2][0][RTW89_QATAR][41] = 18,
[2][1][2][0][RTW89_FCC][49] = 62,
[2][1][2][0][RTW89_ETSI][49] = 127,
[2][1][2][0][RTW89_MKK][49] = 127,
@@ -31892,6 +36328,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[2][1][2][0][RTW89_ACMA][49] = 127,
[2][1][2][0][RTW89_CN][49] = 127,
[2][1][2][0][RTW89_UK][49] = 127,
+ [2][1][2][0][RTW89_MEXICO][49] = 127,
+ [2][1][2][0][RTW89_UKRAINE][49] = 127,
+ [2][1][2][0][RTW89_CHILE][49] = 127,
+ [2][1][2][0][RTW89_QATAR][49] = 127,
[2][1][2][1][RTW89_FCC][3] = 48,
[2][1][2][1][RTW89_ETSI][3] = 40,
[2][1][2][1][RTW89_MKK][3] = 56,
@@ -31900,6 +36340,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[2][1][2][1][RTW89_ACMA][3] = 40,
[2][1][2][1][RTW89_CN][3] = 42,
[2][1][2][1][RTW89_UK][3] = 40,
+ [2][1][2][1][RTW89_MEXICO][3] = 48,
+ [2][1][2][1][RTW89_UKRAINE][3] = 30,
+ [2][1][2][1][RTW89_CHILE][3] = 46,
+ [2][1][2][1][RTW89_QATAR][3] = 40,
[2][1][2][1][RTW89_FCC][11] = 38,
[2][1][2][1][RTW89_ETSI][11] = 40,
[2][1][2][1][RTW89_MKK][11] = 54,
@@ -31908,6 +36352,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[2][1][2][1][RTW89_ACMA][11] = 40,
[2][1][2][1][RTW89_CN][11] = 42,
[2][1][2][1][RTW89_UK][11] = 40,
+ [2][1][2][1][RTW89_MEXICO][11] = 38,
+ [2][1][2][1][RTW89_UKRAINE][11] = 30,
+ [2][1][2][1][RTW89_CHILE][11] = 38,
+ [2][1][2][1][RTW89_QATAR][11] = 40,
[2][1][2][1][RTW89_FCC][18] = 50,
[2][1][2][1][RTW89_ETSI][18] = 40,
[2][1][2][1][RTW89_MKK][18] = 60,
@@ -31916,6 +36364,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[2][1][2][1][RTW89_ACMA][18] = 40,
[2][1][2][1][RTW89_CN][18] = 127,
[2][1][2][1][RTW89_UK][18] = 40,
+ [2][1][2][1][RTW89_MEXICO][18] = 50,
+ [2][1][2][1][RTW89_UKRAINE][18] = 30,
+ [2][1][2][1][RTW89_CHILE][18] = 50,
+ [2][1][2][1][RTW89_QATAR][18] = 40,
[2][1][2][1][RTW89_FCC][26] = 52,
[2][1][2][1][RTW89_ETSI][26] = 42,
[2][1][2][1][RTW89_MKK][26] = 56,
@@ -31924,6 +36376,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[2][1][2][1][RTW89_ACMA][26] = 127,
[2][1][2][1][RTW89_CN][26] = 127,
[2][1][2][1][RTW89_UK][26] = 42,
+ [2][1][2][1][RTW89_MEXICO][26] = 52,
+ [2][1][2][1][RTW89_UKRAINE][26] = 30,
+ [2][1][2][1][RTW89_CHILE][26] = 52,
+ [2][1][2][1][RTW89_QATAR][26] = 42,
[2][1][2][1][RTW89_FCC][34] = 62,
[2][1][2][1][RTW89_ETSI][34] = 127,
[2][1][2][1][RTW89_MKK][34] = 60,
@@ -31932,6 +36388,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[2][1][2][1][RTW89_ACMA][34] = 60,
[2][1][2][1][RTW89_CN][34] = 127,
[2][1][2][1][RTW89_UK][34] = 40,
+ [2][1][2][1][RTW89_MEXICO][34] = 62,
+ [2][1][2][1][RTW89_UKRAINE][34] = 127,
+ [2][1][2][1][RTW89_CHILE][34] = 60,
+ [2][1][2][1][RTW89_QATAR][34] = 127,
[2][1][2][1][RTW89_FCC][41] = 60,
[2][1][2][1][RTW89_ETSI][41] = 6,
[2][1][2][1][RTW89_MKK][41] = 127,
@@ -31940,6 +36400,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[2][1][2][1][RTW89_ACMA][41] = 58,
[2][1][2][1][RTW89_CN][41] = 40,
[2][1][2][1][RTW89_UK][41] = 40,
+ [2][1][2][1][RTW89_MEXICO][41] = 60,
+ [2][1][2][1][RTW89_UKRAINE][41] = 6,
+ [2][1][2][1][RTW89_CHILE][41] = 58,
+ [2][1][2][1][RTW89_QATAR][41] = 6,
[2][1][2][1][RTW89_FCC][49] = 62,
[2][1][2][1][RTW89_ETSI][49] = 127,
[2][1][2][1][RTW89_MKK][49] = 127,
@@ -31948,6 +36412,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[2][1][2][1][RTW89_ACMA][49] = 127,
[2][1][2][1][RTW89_CN][49] = 127,
[2][1][2][1][RTW89_UK][49] = 127,
+ [2][1][2][1][RTW89_MEXICO][49] = 127,
+ [2][1][2][1][RTW89_UKRAINE][49] = 127,
+ [2][1][2][1][RTW89_CHILE][49] = 127,
+ [2][1][2][1][RTW89_QATAR][49] = 127,
[3][0][2][0][RTW89_FCC][7] = 40,
[3][0][2][0][RTW89_ETSI][7] = 50,
[3][0][2][0][RTW89_MKK][7] = 50,
@@ -31956,6 +36424,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[3][0][2][0][RTW89_ACMA][7] = 127,
[3][0][2][0][RTW89_CN][7] = 66,
[3][0][2][0][RTW89_UK][7] = 127,
+ [3][0][2][0][RTW89_MEXICO][7] = 127,
+ [3][0][2][0][RTW89_UKRAINE][7] = 50,
+ [3][0][2][0][RTW89_CHILE][7] = 40,
+ [3][0][2][0][RTW89_QATAR][7] = 50,
[3][0][2][0][RTW89_FCC][22] = 42,
[3][0][2][0][RTW89_ETSI][22] = 50,
[3][0][2][0][RTW89_MKK][22] = 50,
@@ -31964,6 +36436,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[3][0][2][0][RTW89_ACMA][22] = 127,
[3][0][2][0][RTW89_CN][22] = 66,
[3][0][2][0][RTW89_UK][22] = 127,
+ [3][0][2][0][RTW89_MEXICO][22] = 127,
+ [3][0][2][0][RTW89_UKRAINE][22] = 50,
+ [3][0][2][0][RTW89_CHILE][22] = 42,
+ [3][0][2][0][RTW89_QATAR][22] = 50,
[3][0][2][0][RTW89_FCC][45] = 52,
[3][0][2][0][RTW89_ETSI][45] = 127,
[3][0][2][0][RTW89_MKK][45] = 127,
@@ -31972,6 +36448,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[3][0][2][0][RTW89_ACMA][45] = 127,
[3][0][2][0][RTW89_CN][45] = 127,
[3][0][2][0][RTW89_UK][45] = 127,
+ [3][0][2][0][RTW89_MEXICO][45] = 127,
+ [3][0][2][0][RTW89_UKRAINE][45] = 127,
+ [3][0][2][0][RTW89_CHILE][45] = 127,
+ [3][0][2][0][RTW89_QATAR][45] = 127,
[3][1][2][0][RTW89_FCC][7] = 32,
[3][1][2][0][RTW89_ETSI][7] = 50,
[3][1][2][0][RTW89_MKK][7] = 36,
@@ -31980,6 +36460,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[3][1][2][0][RTW89_ACMA][7] = 127,
[3][1][2][0][RTW89_CN][7] = 54,
[3][1][2][0][RTW89_UK][7] = 127,
+ [3][1][2][0][RTW89_MEXICO][7] = 127,
+ [3][1][2][0][RTW89_UKRAINE][7] = 50,
+ [3][1][2][0][RTW89_CHILE][7] = 32,
+ [3][1][2][0][RTW89_QATAR][7] = 50,
[3][1][2][0][RTW89_FCC][22] = 36,
[3][1][2][0][RTW89_ETSI][22] = 50,
[3][1][2][0][RTW89_MKK][22] = 48,
@@ -31988,6 +36472,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[3][1][2][0][RTW89_ACMA][22] = 127,
[3][1][2][0][RTW89_CN][22] = 54,
[3][1][2][0][RTW89_UK][22] = 127,
+ [3][1][2][0][RTW89_MEXICO][22] = 127,
+ [3][1][2][0][RTW89_UKRAINE][22] = 50,
+ [3][1][2][0][RTW89_CHILE][22] = 36,
+ [3][1][2][0][RTW89_QATAR][22] = 50,
[3][1][2][0][RTW89_FCC][45] = 46,
[3][1][2][0][RTW89_ETSI][45] = 127,
[3][1][2][0][RTW89_MKK][45] = 127,
@@ -31996,6 +36484,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[3][1][2][0][RTW89_ACMA][45] = 127,
[3][1][2][0][RTW89_CN][45] = 127,
[3][1][2][0][RTW89_UK][45] = 127,
+ [3][1][2][0][RTW89_MEXICO][45] = 127,
+ [3][1][2][0][RTW89_UKRAINE][45] = 127,
+ [3][1][2][0][RTW89_CHILE][45] = 127,
+ [3][1][2][0][RTW89_QATAR][45] = 127,
[3][1][2][1][RTW89_FCC][7] = 32,
[3][1][2][1][RTW89_ETSI][7] = 42,
[3][1][2][1][RTW89_MKK][7] = 36,
@@ -32004,6 +36496,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[3][1][2][1][RTW89_ACMA][7] = 127,
[3][1][2][1][RTW89_CN][7] = 42,
[3][1][2][1][RTW89_UK][7] = 127,
+ [3][1][2][1][RTW89_MEXICO][7] = 127,
+ [3][1][2][1][RTW89_UKRAINE][7] = 42,
+ [3][1][2][1][RTW89_CHILE][7] = 32,
+ [3][1][2][1][RTW89_QATAR][7] = 42,
[3][1][2][1][RTW89_FCC][22] = 36,
[3][1][2][1][RTW89_ETSI][22] = 42,
[3][1][2][1][RTW89_MKK][22] = 48,
@@ -32012,6 +36508,10 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[3][1][2][1][RTW89_ACMA][22] = 127,
[3][1][2][1][RTW89_CN][22] = 42,
[3][1][2][1][RTW89_UK][22] = 127,
+ [3][1][2][1][RTW89_MEXICO][22] = 127,
+ [3][1][2][1][RTW89_UKRAINE][22] = 42,
+ [3][1][2][1][RTW89_CHILE][22] = 36,
+ [3][1][2][1][RTW89_QATAR][22] = 42,
[3][1][2][1][RTW89_FCC][45] = 46,
[3][1][2][1][RTW89_ETSI][45] = 127,
[3][1][2][1][RTW89_MKK][45] = 127,
@@ -32020,1964 +36520,9289 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[3][1][2][1][RTW89_ACMA][45] = 127,
[3][1][2][1][RTW89_CN][45] = 127,
[3][1][2][1][RTW89_UK][45] = 127,
+ [3][1][2][1][RTW89_MEXICO][45] = 127,
+ [3][1][2][1][RTW89_UKRAINE][45] = 127,
+ [3][1][2][1][RTW89_CHILE][45] = 127,
+ [3][1][2][1][RTW89_QATAR][45] = 127,
};
static
const s8 rtw89_8852c_txpwr_lmt_6g[RTW89_6G_BW_NUM][RTW89_NTX_NUM]
[RTW89_RS_LMT_NUM][RTW89_BF_NUM]
- [RTW89_REGD_NUM][RTW89_6G_CH_NUM] = {
- [0][0][1][0][RTW89_WW][0] = 24,
- [0][0][1][0][RTW89_WW][2] = 22,
- [0][0][1][0][RTW89_WW][4] = 22,
- [0][0][1][0][RTW89_WW][6] = 22,
- [0][0][1][0][RTW89_WW][8] = 22,
- [0][0][1][0][RTW89_WW][10] = 22,
- [0][0][1][0][RTW89_WW][12] = 22,
- [0][0][1][0][RTW89_WW][14] = 22,
- [0][0][1][0][RTW89_WW][15] = 22,
- [0][0][1][0][RTW89_WW][17] = 22,
- [0][0][1][0][RTW89_WW][19] = 22,
- [0][0][1][0][RTW89_WW][21] = 22,
- [0][0][1][0][RTW89_WW][23] = 22,
- [0][0][1][0][RTW89_WW][25] = 22,
- [0][0][1][0][RTW89_WW][27] = 22,
- [0][0][1][0][RTW89_WW][29] = 22,
- [0][0][1][0][RTW89_WW][30] = 22,
- [0][0][1][0][RTW89_WW][32] = 22,
- [0][0][1][0][RTW89_WW][34] = 22,
- [0][0][1][0][RTW89_WW][36] = 22,
- [0][0][1][0][RTW89_WW][38] = 22,
- [0][0][1][0][RTW89_WW][40] = 22,
- [0][0][1][0][RTW89_WW][42] = 22,
- [0][0][1][0][RTW89_WW][44] = 22,
- [0][0][1][0][RTW89_WW][45] = 22,
- [0][0][1][0][RTW89_WW][47] = 22,
- [0][0][1][0][RTW89_WW][49] = 24,
- [0][0][1][0][RTW89_WW][51] = 22,
- [0][0][1][0][RTW89_WW][53] = 22,
- [0][0][1][0][RTW89_WW][55] = 22,
- [0][0][1][0][RTW89_WW][57] = 22,
- [0][0][1][0][RTW89_WW][59] = 22,
- [0][0][1][0][RTW89_WW][60] = 22,
- [0][0][1][0][RTW89_WW][62] = 22,
- [0][0][1][0][RTW89_WW][64] = 22,
- [0][0][1][0][RTW89_WW][66] = 22,
- [0][0][1][0][RTW89_WW][68] = 22,
- [0][0][1][0][RTW89_WW][70] = 24,
- [0][0][1][0][RTW89_WW][72] = 22,
- [0][0][1][0][RTW89_WW][74] = 22,
- [0][0][1][0][RTW89_WW][75] = 22,
- [0][0][1][0][RTW89_WW][77] = 22,
- [0][0][1][0][RTW89_WW][79] = 22,
- [0][0][1][0][RTW89_WW][81] = 22,
- [0][0][1][0][RTW89_WW][83] = 22,
- [0][0][1][0][RTW89_WW][85] = 22,
- [0][0][1][0][RTW89_WW][87] = 22,
- [0][0][1][0][RTW89_WW][89] = 22,
- [0][0][1][0][RTW89_WW][90] = 22,
- [0][0][1][0][RTW89_WW][92] = 22,
- [0][0][1][0][RTW89_WW][94] = 22,
- [0][0][1][0][RTW89_WW][96] = 22,
- [0][0][1][0][RTW89_WW][98] = 22,
- [0][0][1][0][RTW89_WW][100] = 22,
- [0][0][1][0][RTW89_WW][102] = 22,
- [0][0][1][0][RTW89_WW][104] = 22,
- [0][0][1][0][RTW89_WW][105] = 22,
- [0][0][1][0][RTW89_WW][107] = 24,
- [0][0][1][0][RTW89_WW][109] = 24,
- [0][0][1][0][RTW89_WW][111] = 0,
- [0][0][1][0][RTW89_WW][113] = 0,
- [0][0][1][0][RTW89_WW][115] = 0,
- [0][0][1][0][RTW89_WW][117] = 0,
- [0][0][1][0][RTW89_WW][119] = 0,
- [0][1][1][0][RTW89_WW][0] = -2,
- [0][1][1][0][RTW89_WW][2] = -4,
- [0][1][1][0][RTW89_WW][4] = -4,
- [0][1][1][0][RTW89_WW][6] = -4,
- [0][1][1][0][RTW89_WW][8] = -4,
- [0][1][1][0][RTW89_WW][10] = -4,
- [0][1][1][0][RTW89_WW][12] = -4,
- [0][1][1][0][RTW89_WW][14] = -4,
- [0][1][1][0][RTW89_WW][15] = -4,
- [0][1][1][0][RTW89_WW][17] = -4,
- [0][1][1][0][RTW89_WW][19] = -4,
- [0][1][1][0][RTW89_WW][21] = -4,
- [0][1][1][0][RTW89_WW][23] = -4,
- [0][1][1][0][RTW89_WW][25] = -4,
- [0][1][1][0][RTW89_WW][27] = -4,
- [0][1][1][0][RTW89_WW][29] = -4,
- [0][1][1][0][RTW89_WW][30] = -4,
- [0][1][1][0][RTW89_WW][32] = -4,
- [0][1][1][0][RTW89_WW][34] = -4,
- [0][1][1][0][RTW89_WW][36] = -4,
- [0][1][1][0][RTW89_WW][38] = -4,
- [0][1][1][0][RTW89_WW][40] = -4,
- [0][1][1][0][RTW89_WW][42] = -4,
- [0][1][1][0][RTW89_WW][44] = -2,
- [0][1][1][0][RTW89_WW][45] = -2,
- [0][1][1][0][RTW89_WW][47] = -2,
- [0][1][1][0][RTW89_WW][49] = -2,
- [0][1][1][0][RTW89_WW][51] = -2,
- [0][1][1][0][RTW89_WW][53] = -2,
- [0][1][1][0][RTW89_WW][55] = -2,
- [0][1][1][0][RTW89_WW][57] = -2,
- [0][1][1][0][RTW89_WW][59] = -2,
- [0][1][1][0][RTW89_WW][60] = -2,
- [0][1][1][0][RTW89_WW][62] = -2,
- [0][1][1][0][RTW89_WW][64] = -2,
- [0][1][1][0][RTW89_WW][66] = -2,
- [0][1][1][0][RTW89_WW][68] = -2,
- [0][1][1][0][RTW89_WW][70] = -2,
- [0][1][1][0][RTW89_WW][72] = -2,
- [0][1][1][0][RTW89_WW][74] = -2,
- [0][1][1][0][RTW89_WW][75] = -2,
- [0][1][1][0][RTW89_WW][77] = -2,
- [0][1][1][0][RTW89_WW][79] = -2,
- [0][1][1][0][RTW89_WW][81] = -2,
- [0][1][1][0][RTW89_WW][83] = -2,
- [0][1][1][0][RTW89_WW][85] = -2,
- [0][1][1][0][RTW89_WW][87] = -2,
- [0][1][1][0][RTW89_WW][89] = -2,
- [0][1][1][0][RTW89_WW][90] = -2,
- [0][1][1][0][RTW89_WW][92] = -2,
- [0][1][1][0][RTW89_WW][94] = -2,
- [0][1][1][0][RTW89_WW][96] = -2,
- [0][1][1][0][RTW89_WW][98] = -2,
- [0][1][1][0][RTW89_WW][100] = -2,
- [0][1][1][0][RTW89_WW][102] = -2,
- [0][1][1][0][RTW89_WW][104] = -2,
- [0][1][1][0][RTW89_WW][105] = -2,
- [0][1][1][0][RTW89_WW][107] = 1,
- [0][1][1][0][RTW89_WW][109] = 1,
- [0][1][1][0][RTW89_WW][111] = 0,
- [0][1][1][0][RTW89_WW][113] = 0,
- [0][1][1][0][RTW89_WW][115] = 0,
- [0][1][1][0][RTW89_WW][117] = 0,
- [0][1][1][0][RTW89_WW][119] = 0,
- [0][0][2][0][RTW89_WW][0] = 24,
- [0][0][2][0][RTW89_WW][2] = 22,
- [0][0][2][0][RTW89_WW][4] = 22,
- [0][0][2][0][RTW89_WW][6] = 22,
- [0][0][2][0][RTW89_WW][8] = 22,
- [0][0][2][0][RTW89_WW][10] = 22,
- [0][0][2][0][RTW89_WW][12] = 22,
- [0][0][2][0][RTW89_WW][14] = 22,
- [0][0][2][0][RTW89_WW][15] = 22,
- [0][0][2][0][RTW89_WW][17] = 22,
- [0][0][2][0][RTW89_WW][19] = 22,
- [0][0][2][0][RTW89_WW][21] = 22,
- [0][0][2][0][RTW89_WW][23] = 22,
- [0][0][2][0][RTW89_WW][25] = 22,
- [0][0][2][0][RTW89_WW][27] = 22,
- [0][0][2][0][RTW89_WW][29] = 22,
- [0][0][2][0][RTW89_WW][30] = 22,
- [0][0][2][0][RTW89_WW][32] = 22,
- [0][0][2][0][RTW89_WW][34] = 22,
- [0][0][2][0][RTW89_WW][36] = 22,
- [0][0][2][0][RTW89_WW][38] = 22,
- [0][0][2][0][RTW89_WW][40] = 22,
- [0][0][2][0][RTW89_WW][42] = 22,
- [0][0][2][0][RTW89_WW][44] = 22,
- [0][0][2][0][RTW89_WW][45] = 22,
- [0][0][2][0][RTW89_WW][47] = 22,
- [0][0][2][0][RTW89_WW][49] = 24,
- [0][0][2][0][RTW89_WW][51] = 22,
- [0][0][2][0][RTW89_WW][53] = 22,
- [0][0][2][0][RTW89_WW][55] = 22,
- [0][0][2][0][RTW89_WW][57] = 22,
- [0][0][2][0][RTW89_WW][59] = 22,
- [0][0][2][0][RTW89_WW][60] = 22,
- [0][0][2][0][RTW89_WW][62] = 22,
- [0][0][2][0][RTW89_WW][64] = 22,
- [0][0][2][0][RTW89_WW][66] = 22,
- [0][0][2][0][RTW89_WW][68] = 22,
- [0][0][2][0][RTW89_WW][70] = 24,
- [0][0][2][0][RTW89_WW][72] = 22,
- [0][0][2][0][RTW89_WW][74] = 22,
- [0][0][2][0][RTW89_WW][75] = 22,
- [0][0][2][0][RTW89_WW][77] = 22,
- [0][0][2][0][RTW89_WW][79] = 22,
- [0][0][2][0][RTW89_WW][81] = 22,
- [0][0][2][0][RTW89_WW][83] = 22,
- [0][0][2][0][RTW89_WW][85] = 22,
- [0][0][2][0][RTW89_WW][87] = 22,
- [0][0][2][0][RTW89_WW][89] = 22,
- [0][0][2][0][RTW89_WW][90] = 22,
- [0][0][2][0][RTW89_WW][92] = 22,
- [0][0][2][0][RTW89_WW][94] = 22,
- [0][0][2][0][RTW89_WW][96] = 22,
- [0][0][2][0][RTW89_WW][98] = 22,
- [0][0][2][0][RTW89_WW][100] = 22,
- [0][0][2][0][RTW89_WW][102] = 22,
- [0][0][2][0][RTW89_WW][104] = 22,
- [0][0][2][0][RTW89_WW][105] = 22,
- [0][0][2][0][RTW89_WW][107] = 24,
- [0][0][2][0][RTW89_WW][109] = 24,
- [0][0][2][0][RTW89_WW][111] = 0,
- [0][0][2][0][RTW89_WW][113] = 0,
- [0][0][2][0][RTW89_WW][115] = 0,
- [0][0][2][0][RTW89_WW][117] = 0,
- [0][0][2][0][RTW89_WW][119] = 0,
- [0][1][2][0][RTW89_WW][0] = -2,
- [0][1][2][0][RTW89_WW][2] = -4,
- [0][1][2][0][RTW89_WW][4] = -4,
- [0][1][2][0][RTW89_WW][6] = -4,
- [0][1][2][0][RTW89_WW][8] = -4,
- [0][1][2][0][RTW89_WW][10] = -4,
- [0][1][2][0][RTW89_WW][12] = -4,
- [0][1][2][0][RTW89_WW][14] = -4,
- [0][1][2][0][RTW89_WW][15] = -4,
- [0][1][2][0][RTW89_WW][17] = -4,
- [0][1][2][0][RTW89_WW][19] = -4,
- [0][1][2][0][RTW89_WW][21] = -4,
- [0][1][2][0][RTW89_WW][23] = -4,
- [0][1][2][0][RTW89_WW][25] = -4,
- [0][1][2][0][RTW89_WW][27] = -4,
- [0][1][2][0][RTW89_WW][29] = -4,
- [0][1][2][0][RTW89_WW][30] = -4,
- [0][1][2][0][RTW89_WW][32] = -4,
- [0][1][2][0][RTW89_WW][34] = -4,
- [0][1][2][0][RTW89_WW][36] = -4,
- [0][1][2][0][RTW89_WW][38] = -4,
- [0][1][2][0][RTW89_WW][40] = -4,
- [0][1][2][0][RTW89_WW][42] = -4,
- [0][1][2][0][RTW89_WW][44] = -2,
- [0][1][2][0][RTW89_WW][45] = -2,
- [0][1][2][0][RTW89_WW][47] = -2,
- [0][1][2][0][RTW89_WW][49] = -2,
- [0][1][2][0][RTW89_WW][51] = -2,
- [0][1][2][0][RTW89_WW][53] = -2,
- [0][1][2][0][RTW89_WW][55] = -2,
- [0][1][2][0][RTW89_WW][57] = -2,
- [0][1][2][0][RTW89_WW][59] = -2,
- [0][1][2][0][RTW89_WW][60] = -2,
- [0][1][2][0][RTW89_WW][62] = -2,
- [0][1][2][0][RTW89_WW][64] = -2,
- [0][1][2][0][RTW89_WW][66] = -2,
- [0][1][2][0][RTW89_WW][68] = -2,
- [0][1][2][0][RTW89_WW][70] = -2,
- [0][1][2][0][RTW89_WW][72] = -2,
- [0][1][2][0][RTW89_WW][74] = -2,
- [0][1][2][0][RTW89_WW][75] = -2,
- [0][1][2][0][RTW89_WW][77] = -2,
- [0][1][2][0][RTW89_WW][79] = -2,
- [0][1][2][0][RTW89_WW][81] = -2,
- [0][1][2][0][RTW89_WW][83] = -2,
- [0][1][2][0][RTW89_WW][85] = -2,
- [0][1][2][0][RTW89_WW][87] = -2,
- [0][1][2][0][RTW89_WW][89] = -2,
- [0][1][2][0][RTW89_WW][90] = -2,
- [0][1][2][0][RTW89_WW][92] = -2,
- [0][1][2][0][RTW89_WW][94] = -2,
- [0][1][2][0][RTW89_WW][96] = -2,
- [0][1][2][0][RTW89_WW][98] = -2,
- [0][1][2][0][RTW89_WW][100] = -2,
- [0][1][2][0][RTW89_WW][102] = -2,
- [0][1][2][0][RTW89_WW][104] = -2,
- [0][1][2][0][RTW89_WW][105] = -2,
- [0][1][2][0][RTW89_WW][107] = 1,
- [0][1][2][0][RTW89_WW][109] = 1,
- [0][1][2][0][RTW89_WW][111] = 0,
- [0][1][2][0][RTW89_WW][113] = 0,
- [0][1][2][0][RTW89_WW][115] = 0,
- [0][1][2][0][RTW89_WW][117] = 0,
- [0][1][2][0][RTW89_WW][119] = 0,
- [0][1][2][1][RTW89_WW][0] = -2,
- [0][1][2][1][RTW89_WW][2] = -4,
- [0][1][2][1][RTW89_WW][4] = -4,
- [0][1][2][1][RTW89_WW][6] = -4,
- [0][1][2][1][RTW89_WW][8] = -4,
- [0][1][2][1][RTW89_WW][10] = -4,
- [0][1][2][1][RTW89_WW][12] = -4,
- [0][1][2][1][RTW89_WW][14] = -4,
- [0][1][2][1][RTW89_WW][15] = -4,
- [0][1][2][1][RTW89_WW][17] = -4,
- [0][1][2][1][RTW89_WW][19] = -4,
- [0][1][2][1][RTW89_WW][21] = -4,
- [0][1][2][1][RTW89_WW][23] = -4,
- [0][1][2][1][RTW89_WW][25] = -4,
- [0][1][2][1][RTW89_WW][27] = -4,
- [0][1][2][1][RTW89_WW][29] = -4,
- [0][1][2][1][RTW89_WW][30] = -4,
- [0][1][2][1][RTW89_WW][32] = -4,
- [0][1][2][1][RTW89_WW][34] = -4,
- [0][1][2][1][RTW89_WW][36] = -4,
- [0][1][2][1][RTW89_WW][38] = -4,
- [0][1][2][1][RTW89_WW][40] = -4,
- [0][1][2][1][RTW89_WW][42] = -4,
- [0][1][2][1][RTW89_WW][44] = -2,
- [0][1][2][1][RTW89_WW][45] = -2,
- [0][1][2][1][RTW89_WW][47] = -2,
- [0][1][2][1][RTW89_WW][49] = -2,
- [0][1][2][1][RTW89_WW][51] = -2,
- [0][1][2][1][RTW89_WW][53] = -2,
- [0][1][2][1][RTW89_WW][55] = -2,
- [0][1][2][1][RTW89_WW][57] = -2,
- [0][1][2][1][RTW89_WW][59] = -2,
- [0][1][2][1][RTW89_WW][60] = -2,
- [0][1][2][1][RTW89_WW][62] = -2,
- [0][1][2][1][RTW89_WW][64] = -2,
- [0][1][2][1][RTW89_WW][66] = -2,
- [0][1][2][1][RTW89_WW][68] = -2,
- [0][1][2][1][RTW89_WW][70] = -2,
- [0][1][2][1][RTW89_WW][72] = -2,
- [0][1][2][1][RTW89_WW][74] = -2,
- [0][1][2][1][RTW89_WW][75] = -2,
- [0][1][2][1][RTW89_WW][77] = -2,
- [0][1][2][1][RTW89_WW][79] = -2,
- [0][1][2][1][RTW89_WW][81] = -2,
- [0][1][2][1][RTW89_WW][83] = -2,
- [0][1][2][1][RTW89_WW][85] = -2,
- [0][1][2][1][RTW89_WW][87] = -2,
- [0][1][2][1][RTW89_WW][89] = -2,
- [0][1][2][1][RTW89_WW][90] = -2,
- [0][1][2][1][RTW89_WW][92] = -2,
- [0][1][2][1][RTW89_WW][94] = -2,
- [0][1][2][1][RTW89_WW][96] = -2,
- [0][1][2][1][RTW89_WW][98] = -2,
- [0][1][2][1][RTW89_WW][100] = -2,
- [0][1][2][1][RTW89_WW][102] = -2,
- [0][1][2][1][RTW89_WW][104] = -2,
- [0][1][2][1][RTW89_WW][105] = -2,
- [0][1][2][1][RTW89_WW][107] = 1,
- [0][1][2][1][RTW89_WW][109] = 1,
- [0][1][2][1][RTW89_WW][111] = 0,
- [0][1][2][1][RTW89_WW][113] = 0,
- [0][1][2][1][RTW89_WW][115] = 0,
- [0][1][2][1][RTW89_WW][117] = 0,
- [0][1][2][1][RTW89_WW][119] = 0,
- [1][0][2][0][RTW89_WW][1] = 34,
- [1][0][2][0][RTW89_WW][5] = 34,
- [1][0][2][0][RTW89_WW][9] = 34,
- [1][0][2][0][RTW89_WW][13] = 34,
- [1][0][2][0][RTW89_WW][16] = 34,
- [1][0][2][0][RTW89_WW][20] = 34,
- [1][0][2][0][RTW89_WW][24] = 36,
- [1][0][2][0][RTW89_WW][28] = 34,
- [1][0][2][0][RTW89_WW][31] = 34,
- [1][0][2][0][RTW89_WW][35] = 34,
- [1][0][2][0][RTW89_WW][39] = 34,
- [1][0][2][0][RTW89_WW][43] = 34,
- [1][0][2][0][RTW89_WW][46] = 34,
- [1][0][2][0][RTW89_WW][50] = 34,
- [1][0][2][0][RTW89_WW][54] = 36,
- [1][0][2][0][RTW89_WW][58] = 36,
- [1][0][2][0][RTW89_WW][61] = 34,
- [1][0][2][0][RTW89_WW][65] = 34,
- [1][0][2][0][RTW89_WW][69] = 34,
- [1][0][2][0][RTW89_WW][73] = 34,
- [1][0][2][0][RTW89_WW][76] = 34,
- [1][0][2][0][RTW89_WW][80] = 34,
- [1][0][2][0][RTW89_WW][84] = 34,
- [1][0][2][0][RTW89_WW][88] = 34,
- [1][0][2][0][RTW89_WW][91] = 36,
- [1][0][2][0][RTW89_WW][95] = 34,
- [1][0][2][0][RTW89_WW][99] = 34,
- [1][0][2][0][RTW89_WW][103] = 34,
- [1][0][2][0][RTW89_WW][106] = 36,
- [1][0][2][0][RTW89_WW][110] = 0,
- [1][0][2][0][RTW89_WW][114] = 0,
- [1][0][2][0][RTW89_WW][118] = 0,
- [1][1][2][0][RTW89_WW][1] = 10,
- [1][1][2][0][RTW89_WW][5] = 10,
- [1][1][2][0][RTW89_WW][9] = 10,
- [1][1][2][0][RTW89_WW][13] = 10,
- [1][1][2][0][RTW89_WW][16] = 10,
- [1][1][2][0][RTW89_WW][20] = 10,
- [1][1][2][0][RTW89_WW][24] = 10,
- [1][1][2][0][RTW89_WW][28] = 10,
- [1][1][2][0][RTW89_WW][31] = 10,
- [1][1][2][0][RTW89_WW][35] = 10,
- [1][1][2][0][RTW89_WW][39] = 10,
- [1][1][2][0][RTW89_WW][43] = 10,
- [1][1][2][0][RTW89_WW][46] = 12,
- [1][1][2][0][RTW89_WW][50] = 12,
- [1][1][2][0][RTW89_WW][54] = 10,
- [1][1][2][0][RTW89_WW][58] = 10,
- [1][1][2][0][RTW89_WW][61] = 10,
- [1][1][2][0][RTW89_WW][65] = 10,
- [1][1][2][0][RTW89_WW][69] = 10,
- [1][1][2][0][RTW89_WW][73] = 10,
- [1][1][2][0][RTW89_WW][76] = 10,
- [1][1][2][0][RTW89_WW][80] = 10,
- [1][1][2][0][RTW89_WW][84] = 10,
- [1][1][2][0][RTW89_WW][88] = 10,
- [1][1][2][0][RTW89_WW][91] = 12,
- [1][1][2][0][RTW89_WW][95] = 10,
- [1][1][2][0][RTW89_WW][99] = 10,
- [1][1][2][0][RTW89_WW][103] = 10,
- [1][1][2][0][RTW89_WW][106] = 12,
- [1][1][2][0][RTW89_WW][110] = 0,
- [1][1][2][0][RTW89_WW][114] = 0,
- [1][1][2][0][RTW89_WW][118] = 0,
- [1][1][2][1][RTW89_WW][1] = 10,
- [1][1][2][1][RTW89_WW][5] = 10,
- [1][1][2][1][RTW89_WW][9] = 10,
- [1][1][2][1][RTW89_WW][13] = 10,
- [1][1][2][1][RTW89_WW][16] = 10,
- [1][1][2][1][RTW89_WW][20] = 10,
- [1][1][2][1][RTW89_WW][24] = 10,
- [1][1][2][1][RTW89_WW][28] = 10,
- [1][1][2][1][RTW89_WW][31] = 10,
- [1][1][2][1][RTW89_WW][35] = 10,
- [1][1][2][1][RTW89_WW][39] = 10,
- [1][1][2][1][RTW89_WW][43] = 10,
- [1][1][2][1][RTW89_WW][46] = 12,
- [1][1][2][1][RTW89_WW][50] = 12,
- [1][1][2][1][RTW89_WW][54] = 10,
- [1][1][2][1][RTW89_WW][58] = 10,
- [1][1][2][1][RTW89_WW][61] = 10,
- [1][1][2][1][RTW89_WW][65] = 10,
- [1][1][2][1][RTW89_WW][69] = 10,
- [1][1][2][1][RTW89_WW][73] = 10,
- [1][1][2][1][RTW89_WW][76] = 10,
- [1][1][2][1][RTW89_WW][80] = 10,
- [1][1][2][1][RTW89_WW][84] = 10,
- [1][1][2][1][RTW89_WW][88] = 10,
- [1][1][2][1][RTW89_WW][91] = 12,
- [1][1][2][1][RTW89_WW][95] = 10,
- [1][1][2][1][RTW89_WW][99] = 10,
- [1][1][2][1][RTW89_WW][103] = 10,
- [1][1][2][1][RTW89_WW][106] = 12,
- [1][1][2][1][RTW89_WW][110] = 0,
- [1][1][2][1][RTW89_WW][114] = 0,
- [1][1][2][1][RTW89_WW][118] = 0,
- [2][0][2][0][RTW89_WW][3] = 46,
- [2][0][2][0][RTW89_WW][11] = 46,
- [2][0][2][0][RTW89_WW][18] = 46,
- [2][0][2][0][RTW89_WW][26] = 46,
- [2][0][2][0][RTW89_WW][33] = 46,
- [2][0][2][0][RTW89_WW][41] = 46,
- [2][0][2][0][RTW89_WW][48] = 46,
- [2][0][2][0][RTW89_WW][56] = 46,
- [2][0][2][0][RTW89_WW][63] = 46,
- [2][0][2][0][RTW89_WW][71] = 46,
- [2][0][2][0][RTW89_WW][78] = 46,
- [2][0][2][0][RTW89_WW][86] = 46,
- [2][0][2][0][RTW89_WW][93] = 46,
- [2][0][2][0][RTW89_WW][101] = 44,
- [2][0][2][0][RTW89_WW][108] = 0,
- [2][0][2][0][RTW89_WW][116] = 0,
- [2][1][2][0][RTW89_WW][3] = 22,
- [2][1][2][0][RTW89_WW][11] = 20,
- [2][1][2][0][RTW89_WW][18] = 20,
- [2][1][2][0][RTW89_WW][26] = 20,
- [2][1][2][0][RTW89_WW][33] = 20,
- [2][1][2][0][RTW89_WW][41] = 22,
- [2][1][2][0][RTW89_WW][48] = 22,
- [2][1][2][0][RTW89_WW][56] = 20,
- [2][1][2][0][RTW89_WW][63] = 22,
- [2][1][2][0][RTW89_WW][71] = 20,
- [2][1][2][0][RTW89_WW][78] = 20,
- [2][1][2][0][RTW89_WW][86] = 20,
- [2][1][2][0][RTW89_WW][93] = 22,
- [2][1][2][0][RTW89_WW][101] = 22,
- [2][1][2][0][RTW89_WW][108] = 0,
- [2][1][2][0][RTW89_WW][116] = 0,
- [2][1][2][1][RTW89_WW][3] = 22,
- [2][1][2][1][RTW89_WW][11] = 20,
- [2][1][2][1][RTW89_WW][18] = 20,
- [2][1][2][1][RTW89_WW][26] = 20,
- [2][1][2][1][RTW89_WW][33] = 20,
- [2][1][2][1][RTW89_WW][41] = 22,
- [2][1][2][1][RTW89_WW][48] = 22,
- [2][1][2][1][RTW89_WW][56] = 20,
- [2][1][2][1][RTW89_WW][63] = 22,
- [2][1][2][1][RTW89_WW][71] = 20,
- [2][1][2][1][RTW89_WW][78] = 20,
- [2][1][2][1][RTW89_WW][86] = 20,
- [2][1][2][1][RTW89_WW][93] = 22,
- [2][1][2][1][RTW89_WW][101] = 22,
- [2][1][2][1][RTW89_WW][108] = 0,
- [2][1][2][1][RTW89_WW][116] = 0,
- [3][0][2][0][RTW89_WW][7] = 38,
- [3][0][2][0][RTW89_WW][22] = 38,
- [3][0][2][0][RTW89_WW][37] = 38,
- [3][0][2][0][RTW89_WW][52] = 54,
- [3][0][2][0][RTW89_WW][67] = 54,
- [3][0][2][0][RTW89_WW][82] = 26,
- [3][0][2][0][RTW89_WW][97] = 26,
- [3][0][2][0][RTW89_WW][112] = 0,
- [3][1][2][0][RTW89_WW][7] = 32,
- [3][1][2][0][RTW89_WW][22] = 30,
- [3][1][2][0][RTW89_WW][37] = 30,
- [3][1][2][0][RTW89_WW][52] = 30,
- [3][1][2][0][RTW89_WW][67] = 32,
- [3][1][2][0][RTW89_WW][82] = 24,
- [3][1][2][0][RTW89_WW][97] = 14,
- [3][1][2][0][RTW89_WW][112] = 0,
- [3][1][2][1][RTW89_WW][7] = 32,
- [3][1][2][1][RTW89_WW][22] = 30,
- [3][1][2][1][RTW89_WW][37] = 30,
- [3][1][2][1][RTW89_WW][52] = 30,
- [3][1][2][1][RTW89_WW][67] = 32,
- [3][1][2][1][RTW89_WW][82] = 24,
- [3][1][2][1][RTW89_WW][97] = 14,
- [3][1][2][1][RTW89_WW][112] = 0,
- [0][0][1][0][RTW89_FCC][0] = 24,
- [0][0][1][0][RTW89_ETSI][0] = 66,
- [0][0][1][0][RTW89_KCC][0] = 24,
- [0][0][1][0][RTW89_FCC][2] = 22,
- [0][0][1][0][RTW89_ETSI][2] = 66,
- [0][0][1][0][RTW89_KCC][2] = 24,
- [0][0][1][0][RTW89_FCC][4] = 22,
- [0][0][1][0][RTW89_ETSI][4] = 66,
- [0][0][1][0][RTW89_KCC][4] = 24,
- [0][0][1][0][RTW89_FCC][6] = 22,
- [0][0][1][0][RTW89_ETSI][6] = 66,
- [0][0][1][0][RTW89_KCC][6] = 24,
- [0][0][1][0][RTW89_FCC][8] = 22,
- [0][0][1][0][RTW89_ETSI][8] = 66,
- [0][0][1][0][RTW89_KCC][8] = 24,
- [0][0][1][0][RTW89_FCC][10] = 22,
- [0][0][1][0][RTW89_ETSI][10] = 66,
- [0][0][1][0][RTW89_KCC][10] = 24,
- [0][0][1][0][RTW89_FCC][12] = 22,
- [0][0][1][0][RTW89_ETSI][12] = 66,
- [0][0][1][0][RTW89_KCC][12] = 24,
- [0][0][1][0][RTW89_FCC][14] = 22,
- [0][0][1][0][RTW89_ETSI][14] = 66,
- [0][0][1][0][RTW89_KCC][14] = 24,
- [0][0][1][0][RTW89_FCC][15] = 22,
- [0][0][1][0][RTW89_ETSI][15] = 66,
- [0][0][1][0][RTW89_KCC][15] = 24,
- [0][0][1][0][RTW89_FCC][17] = 22,
- [0][0][1][0][RTW89_ETSI][17] = 66,
- [0][0][1][0][RTW89_KCC][17] = 24,
- [0][0][1][0][RTW89_FCC][19] = 22,
- [0][0][1][0][RTW89_ETSI][19] = 66,
- [0][0][1][0][RTW89_KCC][19] = 24,
- [0][0][1][0][RTW89_FCC][21] = 22,
- [0][0][1][0][RTW89_ETSI][21] = 66,
- [0][0][1][0][RTW89_KCC][21] = 24,
- [0][0][1][0][RTW89_FCC][23] = 22,
- [0][0][1][0][RTW89_ETSI][23] = 66,
- [0][0][1][0][RTW89_KCC][23] = 24,
- [0][0][1][0][RTW89_FCC][25] = 22,
- [0][0][1][0][RTW89_ETSI][25] = 66,
- [0][0][1][0][RTW89_KCC][25] = 24,
- [0][0][1][0][RTW89_FCC][27] = 22,
- [0][0][1][0][RTW89_ETSI][27] = 66,
- [0][0][1][0][RTW89_KCC][27] = 24,
- [0][0][1][0][RTW89_FCC][29] = 22,
- [0][0][1][0][RTW89_ETSI][29] = 66,
- [0][0][1][0][RTW89_KCC][29] = 24,
- [0][0][1][0][RTW89_FCC][30] = 22,
- [0][0][1][0][RTW89_ETSI][30] = 66,
- [0][0][1][0][RTW89_KCC][30] = 24,
- [0][0][1][0][RTW89_FCC][32] = 22,
- [0][0][1][0][RTW89_ETSI][32] = 66,
- [0][0][1][0][RTW89_KCC][32] = 24,
- [0][0][1][0][RTW89_FCC][34] = 22,
- [0][0][1][0][RTW89_ETSI][34] = 66,
- [0][0][1][0][RTW89_KCC][34] = 24,
- [0][0][1][0][RTW89_FCC][36] = 22,
- [0][0][1][0][RTW89_ETSI][36] = 66,
- [0][0][1][0][RTW89_KCC][36] = 24,
- [0][0][1][0][RTW89_FCC][38] = 22,
- [0][0][1][0][RTW89_ETSI][38] = 66,
- [0][0][1][0][RTW89_KCC][38] = 24,
- [0][0][1][0][RTW89_FCC][40] = 22,
- [0][0][1][0][RTW89_ETSI][40] = 66,
- [0][0][1][0][RTW89_KCC][40] = 24,
- [0][0][1][0][RTW89_FCC][42] = 22,
- [0][0][1][0][RTW89_ETSI][42] = 66,
- [0][0][1][0][RTW89_KCC][42] = 24,
- [0][0][1][0][RTW89_FCC][44] = 22,
- [0][0][1][0][RTW89_ETSI][44] = 66,
- [0][0][1][0][RTW89_KCC][44] = 24,
- [0][0][1][0][RTW89_FCC][45] = 22,
- [0][0][1][0][RTW89_ETSI][45] = 127,
- [0][0][1][0][RTW89_KCC][45] = 24,
- [0][0][1][0][RTW89_FCC][47] = 22,
- [0][0][1][0][RTW89_ETSI][47] = 127,
- [0][0][1][0][RTW89_KCC][47] = 24,
- [0][0][1][0][RTW89_FCC][49] = 24,
- [0][0][1][0][RTW89_ETSI][49] = 127,
- [0][0][1][0][RTW89_KCC][49] = 24,
- [0][0][1][0][RTW89_FCC][51] = 22,
- [0][0][1][0][RTW89_ETSI][51] = 127,
- [0][0][1][0][RTW89_KCC][51] = 24,
- [0][0][1][0][RTW89_FCC][53] = 22,
- [0][0][1][0][RTW89_ETSI][53] = 127,
- [0][0][1][0][RTW89_KCC][53] = 24,
- [0][0][1][0][RTW89_FCC][55] = 22,
- [0][0][1][0][RTW89_ETSI][55] = 127,
- [0][0][1][0][RTW89_KCC][55] = 26,
- [0][0][1][0][RTW89_FCC][57] = 22,
- [0][0][1][0][RTW89_ETSI][57] = 127,
- [0][0][1][0][RTW89_KCC][57] = 26,
- [0][0][1][0][RTW89_FCC][59] = 22,
- [0][0][1][0][RTW89_ETSI][59] = 127,
- [0][0][1][0][RTW89_KCC][59] = 26,
- [0][0][1][0][RTW89_FCC][60] = 22,
- [0][0][1][0][RTW89_ETSI][60] = 127,
- [0][0][1][0][RTW89_KCC][60] = 26,
- [0][0][1][0][RTW89_FCC][62] = 22,
- [0][0][1][0][RTW89_ETSI][62] = 127,
- [0][0][1][0][RTW89_KCC][62] = 26,
- [0][0][1][0][RTW89_FCC][64] = 22,
- [0][0][1][0][RTW89_ETSI][64] = 127,
- [0][0][1][0][RTW89_KCC][64] = 26,
- [0][0][1][0][RTW89_FCC][66] = 22,
- [0][0][1][0][RTW89_ETSI][66] = 127,
- [0][0][1][0][RTW89_KCC][66] = 26,
- [0][0][1][0][RTW89_FCC][68] = 22,
- [0][0][1][0][RTW89_ETSI][68] = 127,
- [0][0][1][0][RTW89_KCC][68] = 26,
- [0][0][1][0][RTW89_FCC][70] = 24,
- [0][0][1][0][RTW89_ETSI][70] = 127,
- [0][0][1][0][RTW89_KCC][70] = 26,
- [0][0][1][0][RTW89_FCC][72] = 22,
- [0][0][1][0][RTW89_ETSI][72] = 127,
- [0][0][1][0][RTW89_KCC][72] = 26,
- [0][0][1][0][RTW89_FCC][74] = 22,
- [0][0][1][0][RTW89_ETSI][74] = 127,
- [0][0][1][0][RTW89_KCC][74] = 26,
- [0][0][1][0][RTW89_FCC][75] = 22,
- [0][0][1][0][RTW89_ETSI][75] = 127,
- [0][0][1][0][RTW89_KCC][75] = 26,
- [0][0][1][0][RTW89_FCC][77] = 22,
- [0][0][1][0][RTW89_ETSI][77] = 127,
- [0][0][1][0][RTW89_KCC][77] = 26,
- [0][0][1][0][RTW89_FCC][79] = 22,
- [0][0][1][0][RTW89_ETSI][79] = 127,
- [0][0][1][0][RTW89_KCC][79] = 26,
- [0][0][1][0][RTW89_FCC][81] = 22,
- [0][0][1][0][RTW89_ETSI][81] = 127,
- [0][0][1][0][RTW89_KCC][81] = 26,
- [0][0][1][0][RTW89_FCC][83] = 22,
- [0][0][1][0][RTW89_ETSI][83] = 127,
- [0][0][1][0][RTW89_KCC][83] = 32,
- [0][0][1][0][RTW89_FCC][85] = 22,
- [0][0][1][0][RTW89_ETSI][85] = 127,
- [0][0][1][0][RTW89_KCC][85] = 32,
- [0][0][1][0][RTW89_FCC][87] = 22,
- [0][0][1][0][RTW89_ETSI][87] = 127,
- [0][0][1][0][RTW89_KCC][87] = 32,
- [0][0][1][0][RTW89_FCC][89] = 22,
- [0][0][1][0][RTW89_ETSI][89] = 127,
- [0][0][1][0][RTW89_KCC][89] = 32,
- [0][0][1][0][RTW89_FCC][90] = 22,
- [0][0][1][0][RTW89_ETSI][90] = 127,
- [0][0][1][0][RTW89_KCC][90] = 32,
- [0][0][1][0][RTW89_FCC][92] = 22,
- [0][0][1][0][RTW89_ETSI][92] = 127,
- [0][0][1][0][RTW89_KCC][92] = 32,
- [0][0][1][0][RTW89_FCC][94] = 22,
- [0][0][1][0][RTW89_ETSI][94] = 127,
- [0][0][1][0][RTW89_KCC][94] = 32,
- [0][0][1][0][RTW89_FCC][96] = 22,
- [0][0][1][0][RTW89_ETSI][96] = 127,
- [0][0][1][0][RTW89_KCC][96] = 32,
- [0][0][1][0][RTW89_FCC][98] = 22,
- [0][0][1][0][RTW89_ETSI][98] = 127,
- [0][0][1][0][RTW89_KCC][98] = 32,
- [0][0][1][0][RTW89_FCC][100] = 22,
- [0][0][1][0][RTW89_ETSI][100] = 127,
- [0][0][1][0][RTW89_KCC][100] = 32,
- [0][0][1][0][RTW89_FCC][102] = 22,
- [0][0][1][0][RTW89_ETSI][102] = 127,
- [0][0][1][0][RTW89_KCC][102] = 32,
- [0][0][1][0][RTW89_FCC][104] = 22,
- [0][0][1][0][RTW89_ETSI][104] = 127,
- [0][0][1][0][RTW89_KCC][104] = 32,
- [0][0][1][0][RTW89_FCC][105] = 22,
- [0][0][1][0][RTW89_ETSI][105] = 127,
- [0][0][1][0][RTW89_KCC][105] = 32,
- [0][0][1][0][RTW89_FCC][107] = 24,
- [0][0][1][0][RTW89_ETSI][107] = 127,
- [0][0][1][0][RTW89_KCC][107] = 32,
- [0][0][1][0][RTW89_FCC][109] = 24,
- [0][0][1][0][RTW89_ETSI][109] = 127,
- [0][0][1][0][RTW89_KCC][109] = 32,
- [0][0][1][0][RTW89_FCC][111] = 127,
- [0][0][1][0][RTW89_ETSI][111] = 127,
- [0][0][1][0][RTW89_KCC][111] = 127,
- [0][0][1][0][RTW89_FCC][113] = 127,
- [0][0][1][0][RTW89_ETSI][113] = 127,
- [0][0][1][0][RTW89_KCC][113] = 127,
- [0][0][1][0][RTW89_FCC][115] = 127,
- [0][0][1][0][RTW89_ETSI][115] = 127,
- [0][0][1][0][RTW89_KCC][115] = 127,
- [0][0][1][0][RTW89_FCC][117] = 127,
- [0][0][1][0][RTW89_ETSI][117] = 127,
- [0][0][1][0][RTW89_KCC][117] = 127,
- [0][0][1][0][RTW89_FCC][119] = 127,
- [0][0][1][0][RTW89_ETSI][119] = 127,
- [0][0][1][0][RTW89_KCC][119] = 127,
- [0][1][1][0][RTW89_FCC][0] = -2,
- [0][1][1][0][RTW89_ETSI][0] = 54,
- [0][1][1][0][RTW89_KCC][0] = 12,
- [0][1][1][0][RTW89_FCC][2] = -4,
- [0][1][1][0][RTW89_ETSI][2] = 54,
- [0][1][1][0][RTW89_KCC][2] = 12,
- [0][1][1][0][RTW89_FCC][4] = -4,
- [0][1][1][0][RTW89_ETSI][4] = 54,
- [0][1][1][0][RTW89_KCC][4] = 12,
- [0][1][1][0][RTW89_FCC][6] = -4,
- [0][1][1][0][RTW89_ETSI][6] = 54,
- [0][1][1][0][RTW89_KCC][6] = 12,
- [0][1][1][0][RTW89_FCC][8] = -4,
- [0][1][1][0][RTW89_ETSI][8] = 54,
- [0][1][1][0][RTW89_KCC][8] = 12,
- [0][1][1][0][RTW89_FCC][10] = -4,
- [0][1][1][0][RTW89_ETSI][10] = 54,
- [0][1][1][0][RTW89_KCC][10] = 12,
- [0][1][1][0][RTW89_FCC][12] = -4,
- [0][1][1][0][RTW89_ETSI][12] = 54,
- [0][1][1][0][RTW89_KCC][12] = 12,
- [0][1][1][0][RTW89_FCC][14] = -4,
- [0][1][1][0][RTW89_ETSI][14] = 54,
- [0][1][1][0][RTW89_KCC][14] = 12,
- [0][1][1][0][RTW89_FCC][15] = -4,
- [0][1][1][0][RTW89_ETSI][15] = 54,
- [0][1][1][0][RTW89_KCC][15] = 12,
- [0][1][1][0][RTW89_FCC][17] = -4,
- [0][1][1][0][RTW89_ETSI][17] = 54,
- [0][1][1][0][RTW89_KCC][17] = 12,
- [0][1][1][0][RTW89_FCC][19] = -4,
- [0][1][1][0][RTW89_ETSI][19] = 54,
- [0][1][1][0][RTW89_KCC][19] = 12,
- [0][1][1][0][RTW89_FCC][21] = -4,
- [0][1][1][0][RTW89_ETSI][21] = 54,
- [0][1][1][0][RTW89_KCC][21] = 12,
- [0][1][1][0][RTW89_FCC][23] = -4,
- [0][1][1][0][RTW89_ETSI][23] = 54,
- [0][1][1][0][RTW89_KCC][23] = 12,
- [0][1][1][0][RTW89_FCC][25] = -4,
- [0][1][1][0][RTW89_ETSI][25] = 54,
- [0][1][1][0][RTW89_KCC][25] = 12,
- [0][1][1][0][RTW89_FCC][27] = -4,
- [0][1][1][0][RTW89_ETSI][27] = 54,
- [0][1][1][0][RTW89_KCC][27] = 12,
- [0][1][1][0][RTW89_FCC][29] = -4,
- [0][1][1][0][RTW89_ETSI][29] = 54,
- [0][1][1][0][RTW89_KCC][29] = 12,
- [0][1][1][0][RTW89_FCC][30] = -4,
- [0][1][1][0][RTW89_ETSI][30] = 54,
- [0][1][1][0][RTW89_KCC][30] = 12,
- [0][1][1][0][RTW89_FCC][32] = -4,
- [0][1][1][0][RTW89_ETSI][32] = 54,
- [0][1][1][0][RTW89_KCC][32] = 12,
- [0][1][1][0][RTW89_FCC][34] = -4,
- [0][1][1][0][RTW89_ETSI][34] = 54,
- [0][1][1][0][RTW89_KCC][34] = 12,
- [0][1][1][0][RTW89_FCC][36] = -4,
- [0][1][1][0][RTW89_ETSI][36] = 54,
- [0][1][1][0][RTW89_KCC][36] = 12,
- [0][1][1][0][RTW89_FCC][38] = -4,
- [0][1][1][0][RTW89_ETSI][38] = 54,
- [0][1][1][0][RTW89_KCC][38] = 12,
- [0][1][1][0][RTW89_FCC][40] = -4,
- [0][1][1][0][RTW89_ETSI][40] = 54,
- [0][1][1][0][RTW89_KCC][40] = 12,
- [0][1][1][0][RTW89_FCC][42] = -4,
- [0][1][1][0][RTW89_ETSI][42] = 54,
- [0][1][1][0][RTW89_KCC][42] = 12,
- [0][1][1][0][RTW89_FCC][44] = -2,
- [0][1][1][0][RTW89_ETSI][44] = 54,
- [0][1][1][0][RTW89_KCC][44] = 12,
- [0][1][1][0][RTW89_FCC][45] = -2,
- [0][1][1][0][RTW89_ETSI][45] = 127,
- [0][1][1][0][RTW89_KCC][45] = 12,
- [0][1][1][0][RTW89_FCC][47] = -2,
- [0][1][1][0][RTW89_ETSI][47] = 127,
- [0][1][1][0][RTW89_KCC][47] = 12,
- [0][1][1][0][RTW89_FCC][49] = -2,
- [0][1][1][0][RTW89_ETSI][49] = 127,
- [0][1][1][0][RTW89_KCC][49] = 12,
- [0][1][1][0][RTW89_FCC][51] = -2,
- [0][1][1][0][RTW89_ETSI][51] = 127,
- [0][1][1][0][RTW89_KCC][51] = 12,
- [0][1][1][0][RTW89_FCC][53] = -2,
- [0][1][1][0][RTW89_ETSI][53] = 127,
- [0][1][1][0][RTW89_KCC][53] = 12,
- [0][1][1][0][RTW89_FCC][55] = -2,
- [0][1][1][0][RTW89_ETSI][55] = 127,
- [0][1][1][0][RTW89_KCC][55] = 12,
- [0][1][1][0][RTW89_FCC][57] = -2,
- [0][1][1][0][RTW89_ETSI][57] = 127,
- [0][1][1][0][RTW89_KCC][57] = 12,
- [0][1][1][0][RTW89_FCC][59] = -2,
- [0][1][1][0][RTW89_ETSI][59] = 127,
- [0][1][1][0][RTW89_KCC][59] = 12,
- [0][1][1][0][RTW89_FCC][60] = -2,
- [0][1][1][0][RTW89_ETSI][60] = 127,
- [0][1][1][0][RTW89_KCC][60] = 12,
- [0][1][1][0][RTW89_FCC][62] = -2,
- [0][1][1][0][RTW89_ETSI][62] = 127,
- [0][1][1][0][RTW89_KCC][62] = 12,
- [0][1][1][0][RTW89_FCC][64] = -2,
- [0][1][1][0][RTW89_ETSI][64] = 127,
- [0][1][1][0][RTW89_KCC][64] = 12,
- [0][1][1][0][RTW89_FCC][66] = -2,
- [0][1][1][0][RTW89_ETSI][66] = 127,
- [0][1][1][0][RTW89_KCC][66] = 12,
- [0][1][1][0][RTW89_FCC][68] = -2,
- [0][1][1][0][RTW89_ETSI][68] = 127,
- [0][1][1][0][RTW89_KCC][68] = 12,
- [0][1][1][0][RTW89_FCC][70] = -2,
- [0][1][1][0][RTW89_ETSI][70] = 127,
- [0][1][1][0][RTW89_KCC][70] = 12,
- [0][1][1][0][RTW89_FCC][72] = -2,
- [0][1][1][0][RTW89_ETSI][72] = 127,
- [0][1][1][0][RTW89_KCC][72] = 12,
- [0][1][1][0][RTW89_FCC][74] = -2,
- [0][1][1][0][RTW89_ETSI][74] = 127,
- [0][1][1][0][RTW89_KCC][74] = 12,
- [0][1][1][0][RTW89_FCC][75] = -2,
- [0][1][1][0][RTW89_ETSI][75] = 127,
- [0][1][1][0][RTW89_KCC][75] = 12,
- [0][1][1][0][RTW89_FCC][77] = -2,
- [0][1][1][0][RTW89_ETSI][77] = 127,
- [0][1][1][0][RTW89_KCC][77] = 12,
- [0][1][1][0][RTW89_FCC][79] = -2,
- [0][1][1][0][RTW89_ETSI][79] = 127,
- [0][1][1][0][RTW89_KCC][79] = 12,
- [0][1][1][0][RTW89_FCC][81] = -2,
- [0][1][1][0][RTW89_ETSI][81] = 127,
- [0][1][1][0][RTW89_KCC][81] = 12,
- [0][1][1][0][RTW89_FCC][83] = -2,
- [0][1][1][0][RTW89_ETSI][83] = 127,
- [0][1][1][0][RTW89_KCC][83] = 20,
- [0][1][1][0][RTW89_FCC][85] = -2,
- [0][1][1][0][RTW89_ETSI][85] = 127,
- [0][1][1][0][RTW89_KCC][85] = 20,
- [0][1][1][0][RTW89_FCC][87] = -2,
- [0][1][1][0][RTW89_ETSI][87] = 127,
- [0][1][1][0][RTW89_KCC][87] = 20,
- [0][1][1][0][RTW89_FCC][89] = -2,
- [0][1][1][0][RTW89_ETSI][89] = 127,
- [0][1][1][0][RTW89_KCC][89] = 20,
- [0][1][1][0][RTW89_FCC][90] = -2,
- [0][1][1][0][RTW89_ETSI][90] = 127,
- [0][1][1][0][RTW89_KCC][90] = 20,
- [0][1][1][0][RTW89_FCC][92] = -2,
- [0][1][1][0][RTW89_ETSI][92] = 127,
- [0][1][1][0][RTW89_KCC][92] = 20,
- [0][1][1][0][RTW89_FCC][94] = -2,
- [0][1][1][0][RTW89_ETSI][94] = 127,
- [0][1][1][0][RTW89_KCC][94] = 20,
- [0][1][1][0][RTW89_FCC][96] = -2,
- [0][1][1][0][RTW89_ETSI][96] = 127,
- [0][1][1][0][RTW89_KCC][96] = 20,
- [0][1][1][0][RTW89_FCC][98] = -2,
- [0][1][1][0][RTW89_ETSI][98] = 127,
- [0][1][1][0][RTW89_KCC][98] = 20,
- [0][1][1][0][RTW89_FCC][100] = -2,
- [0][1][1][0][RTW89_ETSI][100] = 127,
- [0][1][1][0][RTW89_KCC][100] = 20,
- [0][1][1][0][RTW89_FCC][102] = -2,
- [0][1][1][0][RTW89_ETSI][102] = 127,
- [0][1][1][0][RTW89_KCC][102] = 20,
- [0][1][1][0][RTW89_FCC][104] = -2,
- [0][1][1][0][RTW89_ETSI][104] = 127,
- [0][1][1][0][RTW89_KCC][104] = 20,
- [0][1][1][0][RTW89_FCC][105] = -2,
- [0][1][1][0][RTW89_ETSI][105] = 127,
- [0][1][1][0][RTW89_KCC][105] = 20,
- [0][1][1][0][RTW89_FCC][107] = 0,
- [0][1][1][0][RTW89_ETSI][107] = 127,
- [0][1][1][0][RTW89_KCC][107] = 20,
- [0][1][1][0][RTW89_FCC][109] = 0,
- [0][1][1][0][RTW89_ETSI][109] = 127,
- [0][1][1][0][RTW89_KCC][109] = 20,
- [0][1][1][0][RTW89_FCC][111] = 127,
- [0][1][1][0][RTW89_ETSI][111] = 127,
- [0][1][1][0][RTW89_KCC][111] = 127,
- [0][1][1][0][RTW89_FCC][113] = 127,
- [0][1][1][0][RTW89_ETSI][113] = 127,
- [0][1][1][0][RTW89_KCC][113] = 127,
- [0][1][1][0][RTW89_FCC][115] = 127,
- [0][1][1][0][RTW89_ETSI][115] = 127,
- [0][1][1][0][RTW89_KCC][115] = 127,
- [0][1][1][0][RTW89_FCC][117] = 127,
- [0][1][1][0][RTW89_ETSI][117] = 127,
- [0][1][1][0][RTW89_KCC][117] = 127,
- [0][1][1][0][RTW89_FCC][119] = 127,
- [0][1][1][0][RTW89_ETSI][119] = 127,
- [0][1][1][0][RTW89_KCC][119] = 127,
- [0][0][2][0][RTW89_FCC][0] = 24,
- [0][0][2][0][RTW89_ETSI][0] = 66,
- [0][0][2][0][RTW89_KCC][0] = 24,
- [0][0][2][0][RTW89_FCC][2] = 22,
- [0][0][2][0][RTW89_ETSI][2] = 66,
- [0][0][2][0][RTW89_KCC][2] = 24,
- [0][0][2][0][RTW89_FCC][4] = 22,
- [0][0][2][0][RTW89_ETSI][4] = 66,
- [0][0][2][0][RTW89_KCC][4] = 24,
- [0][0][2][0][RTW89_FCC][6] = 22,
- [0][0][2][0][RTW89_ETSI][6] = 66,
- [0][0][2][0][RTW89_KCC][6] = 24,
- [0][0][2][0][RTW89_FCC][8] = 22,
- [0][0][2][0][RTW89_ETSI][8] = 66,
- [0][0][2][0][RTW89_KCC][8] = 24,
- [0][0][2][0][RTW89_FCC][10] = 22,
- [0][0][2][0][RTW89_ETSI][10] = 66,
- [0][0][2][0][RTW89_KCC][10] = 24,
- [0][0][2][0][RTW89_FCC][12] = 22,
- [0][0][2][0][RTW89_ETSI][12] = 66,
- [0][0][2][0][RTW89_KCC][12] = 24,
- [0][0][2][0][RTW89_FCC][14] = 22,
- [0][0][2][0][RTW89_ETSI][14] = 66,
- [0][0][2][0][RTW89_KCC][14] = 24,
- [0][0][2][0][RTW89_FCC][15] = 22,
- [0][0][2][0][RTW89_ETSI][15] = 66,
- [0][0][2][0][RTW89_KCC][15] = 24,
- [0][0][2][0][RTW89_FCC][17] = 22,
- [0][0][2][0][RTW89_ETSI][17] = 66,
- [0][0][2][0][RTW89_KCC][17] = 24,
- [0][0][2][0][RTW89_FCC][19] = 22,
- [0][0][2][0][RTW89_ETSI][19] = 66,
- [0][0][2][0][RTW89_KCC][19] = 24,
- [0][0][2][0][RTW89_FCC][21] = 22,
- [0][0][2][0][RTW89_ETSI][21] = 66,
- [0][0][2][0][RTW89_KCC][21] = 24,
- [0][0][2][0][RTW89_FCC][23] = 22,
- [0][0][2][0][RTW89_ETSI][23] = 66,
- [0][0][2][0][RTW89_KCC][23] = 24,
- [0][0][2][0][RTW89_FCC][25] = 22,
- [0][0][2][0][RTW89_ETSI][25] = 66,
- [0][0][2][0][RTW89_KCC][25] = 24,
- [0][0][2][0][RTW89_FCC][27] = 22,
- [0][0][2][0][RTW89_ETSI][27] = 66,
- [0][0][2][0][RTW89_KCC][27] = 24,
- [0][0][2][0][RTW89_FCC][29] = 22,
- [0][0][2][0][RTW89_ETSI][29] = 66,
- [0][0][2][0][RTW89_KCC][29] = 24,
- [0][0][2][0][RTW89_FCC][30] = 22,
- [0][0][2][0][RTW89_ETSI][30] = 66,
- [0][0][2][0][RTW89_KCC][30] = 24,
- [0][0][2][0][RTW89_FCC][32] = 22,
- [0][0][2][0][RTW89_ETSI][32] = 66,
- [0][0][2][0][RTW89_KCC][32] = 24,
- [0][0][2][0][RTW89_FCC][34] = 22,
- [0][0][2][0][RTW89_ETSI][34] = 66,
- [0][0][2][0][RTW89_KCC][34] = 24,
- [0][0][2][0][RTW89_FCC][36] = 22,
- [0][0][2][0][RTW89_ETSI][36] = 66,
- [0][0][2][0][RTW89_KCC][36] = 24,
- [0][0][2][0][RTW89_FCC][38] = 22,
- [0][0][2][0][RTW89_ETSI][38] = 66,
- [0][0][2][0][RTW89_KCC][38] = 24,
- [0][0][2][0][RTW89_FCC][40] = 22,
- [0][0][2][0][RTW89_ETSI][40] = 66,
- [0][0][2][0][RTW89_KCC][40] = 24,
- [0][0][2][0][RTW89_FCC][42] = 22,
- [0][0][2][0][RTW89_ETSI][42] = 66,
- [0][0][2][0][RTW89_KCC][42] = 24,
- [0][0][2][0][RTW89_FCC][44] = 22,
- [0][0][2][0][RTW89_ETSI][44] = 66,
- [0][0][2][0][RTW89_KCC][44] = 24,
- [0][0][2][0][RTW89_FCC][45] = 22,
- [0][0][2][0][RTW89_ETSI][45] = 127,
- [0][0][2][0][RTW89_KCC][45] = 24,
- [0][0][2][0][RTW89_FCC][47] = 22,
- [0][0][2][0][RTW89_ETSI][47] = 127,
- [0][0][2][0][RTW89_KCC][47] = 24,
- [0][0][2][0][RTW89_FCC][49] = 24,
- [0][0][2][0][RTW89_ETSI][49] = 127,
- [0][0][2][0][RTW89_KCC][49] = 24,
- [0][0][2][0][RTW89_FCC][51] = 22,
- [0][0][2][0][RTW89_ETSI][51] = 127,
- [0][0][2][0][RTW89_KCC][51] = 24,
- [0][0][2][0][RTW89_FCC][53] = 22,
- [0][0][2][0][RTW89_ETSI][53] = 127,
- [0][0][2][0][RTW89_KCC][53] = 24,
- [0][0][2][0][RTW89_FCC][55] = 22,
- [0][0][2][0][RTW89_ETSI][55] = 127,
- [0][0][2][0][RTW89_KCC][55] = 26,
- [0][0][2][0][RTW89_FCC][57] = 22,
- [0][0][2][0][RTW89_ETSI][57] = 127,
- [0][0][2][0][RTW89_KCC][57] = 26,
- [0][0][2][0][RTW89_FCC][59] = 22,
- [0][0][2][0][RTW89_ETSI][59] = 127,
- [0][0][2][0][RTW89_KCC][59] = 26,
- [0][0][2][0][RTW89_FCC][60] = 22,
- [0][0][2][0][RTW89_ETSI][60] = 127,
- [0][0][2][0][RTW89_KCC][60] = 26,
- [0][0][2][0][RTW89_FCC][62] = 22,
- [0][0][2][0][RTW89_ETSI][62] = 127,
- [0][0][2][0][RTW89_KCC][62] = 26,
- [0][0][2][0][RTW89_FCC][64] = 22,
- [0][0][2][0][RTW89_ETSI][64] = 127,
- [0][0][2][0][RTW89_KCC][64] = 26,
- [0][0][2][0][RTW89_FCC][66] = 22,
- [0][0][2][0][RTW89_ETSI][66] = 127,
- [0][0][2][0][RTW89_KCC][66] = 26,
- [0][0][2][0][RTW89_FCC][68] = 22,
- [0][0][2][0][RTW89_ETSI][68] = 127,
- [0][0][2][0][RTW89_KCC][68] = 26,
- [0][0][2][0][RTW89_FCC][70] = 24,
- [0][0][2][0][RTW89_ETSI][70] = 127,
- [0][0][2][0][RTW89_KCC][70] = 26,
- [0][0][2][0][RTW89_FCC][72] = 22,
- [0][0][2][0][RTW89_ETSI][72] = 127,
- [0][0][2][0][RTW89_KCC][72] = 26,
- [0][0][2][0][RTW89_FCC][74] = 22,
- [0][0][2][0][RTW89_ETSI][74] = 127,
- [0][0][2][0][RTW89_KCC][74] = 26,
- [0][0][2][0][RTW89_FCC][75] = 22,
- [0][0][2][0][RTW89_ETSI][75] = 127,
- [0][0][2][0][RTW89_KCC][75] = 26,
- [0][0][2][0][RTW89_FCC][77] = 22,
- [0][0][2][0][RTW89_ETSI][77] = 127,
- [0][0][2][0][RTW89_KCC][77] = 26,
- [0][0][2][0][RTW89_FCC][79] = 22,
- [0][0][2][0][RTW89_ETSI][79] = 127,
- [0][0][2][0][RTW89_KCC][79] = 26,
- [0][0][2][0][RTW89_FCC][81] = 22,
- [0][0][2][0][RTW89_ETSI][81] = 127,
- [0][0][2][0][RTW89_KCC][81] = 26,
- [0][0][2][0][RTW89_FCC][83] = 22,
- [0][0][2][0][RTW89_ETSI][83] = 127,
- [0][0][2][0][RTW89_KCC][83] = 32,
- [0][0][2][0][RTW89_FCC][85] = 22,
- [0][0][2][0][RTW89_ETSI][85] = 127,
- [0][0][2][0][RTW89_KCC][85] = 32,
- [0][0][2][0][RTW89_FCC][87] = 22,
- [0][0][2][0][RTW89_ETSI][87] = 127,
- [0][0][2][0][RTW89_KCC][87] = 32,
- [0][0][2][0][RTW89_FCC][89] = 22,
- [0][0][2][0][RTW89_ETSI][89] = 127,
- [0][0][2][0][RTW89_KCC][89] = 32,
- [0][0][2][0][RTW89_FCC][90] = 22,
- [0][0][2][0][RTW89_ETSI][90] = 127,
- [0][0][2][0][RTW89_KCC][90] = 32,
- [0][0][2][0][RTW89_FCC][92] = 22,
- [0][0][2][0][RTW89_ETSI][92] = 127,
- [0][0][2][0][RTW89_KCC][92] = 32,
- [0][0][2][0][RTW89_FCC][94] = 22,
- [0][0][2][0][RTW89_ETSI][94] = 127,
- [0][0][2][0][RTW89_KCC][94] = 32,
- [0][0][2][0][RTW89_FCC][96] = 22,
- [0][0][2][0][RTW89_ETSI][96] = 127,
- [0][0][2][0][RTW89_KCC][96] = 32,
- [0][0][2][0][RTW89_FCC][98] = 22,
- [0][0][2][0][RTW89_ETSI][98] = 127,
- [0][0][2][0][RTW89_KCC][98] = 32,
- [0][0][2][0][RTW89_FCC][100] = 22,
- [0][0][2][0][RTW89_ETSI][100] = 127,
- [0][0][2][0][RTW89_KCC][100] = 32,
- [0][0][2][0][RTW89_FCC][102] = 22,
- [0][0][2][0][RTW89_ETSI][102] = 127,
- [0][0][2][0][RTW89_KCC][102] = 32,
- [0][0][2][0][RTW89_FCC][104] = 22,
- [0][0][2][0][RTW89_ETSI][104] = 127,
- [0][0][2][0][RTW89_KCC][104] = 32,
- [0][0][2][0][RTW89_FCC][105] = 22,
- [0][0][2][0][RTW89_ETSI][105] = 127,
- [0][0][2][0][RTW89_KCC][105] = 32,
- [0][0][2][0][RTW89_FCC][107] = 24,
- [0][0][2][0][RTW89_ETSI][107] = 127,
- [0][0][2][0][RTW89_KCC][107] = 32,
- [0][0][2][0][RTW89_FCC][109] = 24,
- [0][0][2][0][RTW89_ETSI][109] = 127,
- [0][0][2][0][RTW89_KCC][109] = 32,
- [0][0][2][0][RTW89_FCC][111] = 127,
- [0][0][2][0][RTW89_ETSI][111] = 127,
- [0][0][2][0][RTW89_KCC][111] = 127,
- [0][0][2][0][RTW89_FCC][113] = 127,
- [0][0][2][0][RTW89_ETSI][113] = 127,
- [0][0][2][0][RTW89_KCC][113] = 127,
- [0][0][2][0][RTW89_FCC][115] = 127,
- [0][0][2][0][RTW89_ETSI][115] = 127,
- [0][0][2][0][RTW89_KCC][115] = 127,
- [0][0][2][0][RTW89_FCC][117] = 127,
- [0][0][2][0][RTW89_ETSI][117] = 127,
- [0][0][2][0][RTW89_KCC][117] = 127,
- [0][0][2][0][RTW89_FCC][119] = 127,
- [0][0][2][0][RTW89_ETSI][119] = 127,
- [0][0][2][0][RTW89_KCC][119] = 127,
- [0][1][2][0][RTW89_FCC][0] = -2,
- [0][1][2][0][RTW89_ETSI][0] = 54,
- [0][1][2][0][RTW89_KCC][0] = 12,
- [0][1][2][0][RTW89_FCC][2] = -4,
- [0][1][2][0][RTW89_ETSI][2] = 54,
- [0][1][2][0][RTW89_KCC][2] = 12,
- [0][1][2][0][RTW89_FCC][4] = -4,
- [0][1][2][0][RTW89_ETSI][4] = 54,
- [0][1][2][0][RTW89_KCC][4] = 12,
- [0][1][2][0][RTW89_FCC][6] = -4,
- [0][1][2][0][RTW89_ETSI][6] = 54,
- [0][1][2][0][RTW89_KCC][6] = 12,
- [0][1][2][0][RTW89_FCC][8] = -4,
- [0][1][2][0][RTW89_ETSI][8] = 54,
- [0][1][2][0][RTW89_KCC][8] = 12,
- [0][1][2][0][RTW89_FCC][10] = -4,
- [0][1][2][0][RTW89_ETSI][10] = 54,
- [0][1][2][0][RTW89_KCC][10] = 12,
- [0][1][2][0][RTW89_FCC][12] = -4,
- [0][1][2][0][RTW89_ETSI][12] = 54,
- [0][1][2][0][RTW89_KCC][12] = 12,
- [0][1][2][0][RTW89_FCC][14] = -4,
- [0][1][2][0][RTW89_ETSI][14] = 54,
- [0][1][2][0][RTW89_KCC][14] = 12,
- [0][1][2][0][RTW89_FCC][15] = -4,
- [0][1][2][0][RTW89_ETSI][15] = 54,
- [0][1][2][0][RTW89_KCC][15] = 12,
- [0][1][2][0][RTW89_FCC][17] = -4,
- [0][1][2][0][RTW89_ETSI][17] = 54,
- [0][1][2][0][RTW89_KCC][17] = 12,
- [0][1][2][0][RTW89_FCC][19] = -4,
- [0][1][2][0][RTW89_ETSI][19] = 54,
- [0][1][2][0][RTW89_KCC][19] = 12,
- [0][1][2][0][RTW89_FCC][21] = -4,
- [0][1][2][0][RTW89_ETSI][21] = 54,
- [0][1][2][0][RTW89_KCC][21] = 12,
- [0][1][2][0][RTW89_FCC][23] = -4,
- [0][1][2][0][RTW89_ETSI][23] = 54,
- [0][1][2][0][RTW89_KCC][23] = 12,
- [0][1][2][0][RTW89_FCC][25] = -4,
- [0][1][2][0][RTW89_ETSI][25] = 54,
- [0][1][2][0][RTW89_KCC][25] = 12,
- [0][1][2][0][RTW89_FCC][27] = -4,
- [0][1][2][0][RTW89_ETSI][27] = 54,
- [0][1][2][0][RTW89_KCC][27] = 12,
- [0][1][2][0][RTW89_FCC][29] = -4,
- [0][1][2][0][RTW89_ETSI][29] = 54,
- [0][1][2][0][RTW89_KCC][29] = 12,
- [0][1][2][0][RTW89_FCC][30] = -4,
- [0][1][2][0][RTW89_ETSI][30] = 54,
- [0][1][2][0][RTW89_KCC][30] = 12,
- [0][1][2][0][RTW89_FCC][32] = -4,
- [0][1][2][0][RTW89_ETSI][32] = 54,
- [0][1][2][0][RTW89_KCC][32] = 12,
- [0][1][2][0][RTW89_FCC][34] = -4,
- [0][1][2][0][RTW89_ETSI][34] = 54,
- [0][1][2][0][RTW89_KCC][34] = 12,
- [0][1][2][0][RTW89_FCC][36] = -4,
- [0][1][2][0][RTW89_ETSI][36] = 54,
- [0][1][2][0][RTW89_KCC][36] = 12,
- [0][1][2][0][RTW89_FCC][38] = -4,
- [0][1][2][0][RTW89_ETSI][38] = 54,
- [0][1][2][0][RTW89_KCC][38] = 12,
- [0][1][2][0][RTW89_FCC][40] = -4,
- [0][1][2][0][RTW89_ETSI][40] = 54,
- [0][1][2][0][RTW89_KCC][40] = 12,
- [0][1][2][0][RTW89_FCC][42] = -4,
- [0][1][2][0][RTW89_ETSI][42] = 54,
- [0][1][2][0][RTW89_KCC][42] = 12,
- [0][1][2][0][RTW89_FCC][44] = -2,
- [0][1][2][0][RTW89_ETSI][44] = 54,
- [0][1][2][0][RTW89_KCC][44] = 12,
- [0][1][2][0][RTW89_FCC][45] = -2,
- [0][1][2][0][RTW89_ETSI][45] = 127,
- [0][1][2][0][RTW89_KCC][45] = 12,
- [0][1][2][0][RTW89_FCC][47] = -2,
- [0][1][2][0][RTW89_ETSI][47] = 127,
- [0][1][2][0][RTW89_KCC][47] = 12,
- [0][1][2][0][RTW89_FCC][49] = -2,
- [0][1][2][0][RTW89_ETSI][49] = 127,
- [0][1][2][0][RTW89_KCC][49] = 12,
- [0][1][2][0][RTW89_FCC][51] = -2,
- [0][1][2][0][RTW89_ETSI][51] = 127,
- [0][1][2][0][RTW89_KCC][51] = 12,
- [0][1][2][0][RTW89_FCC][53] = -2,
- [0][1][2][0][RTW89_ETSI][53] = 127,
- [0][1][2][0][RTW89_KCC][53] = 12,
- [0][1][2][0][RTW89_FCC][55] = -2,
- [0][1][2][0][RTW89_ETSI][55] = 127,
- [0][1][2][0][RTW89_KCC][55] = 12,
- [0][1][2][0][RTW89_FCC][57] = -2,
- [0][1][2][0][RTW89_ETSI][57] = 127,
- [0][1][2][0][RTW89_KCC][57] = 12,
- [0][1][2][0][RTW89_FCC][59] = -2,
- [0][1][2][0][RTW89_ETSI][59] = 127,
- [0][1][2][0][RTW89_KCC][59] = 12,
- [0][1][2][0][RTW89_FCC][60] = -2,
- [0][1][2][0][RTW89_ETSI][60] = 127,
- [0][1][2][0][RTW89_KCC][60] = 12,
- [0][1][2][0][RTW89_FCC][62] = -2,
- [0][1][2][0][RTW89_ETSI][62] = 127,
- [0][1][2][0][RTW89_KCC][62] = 12,
- [0][1][2][0][RTW89_FCC][64] = -2,
- [0][1][2][0][RTW89_ETSI][64] = 127,
- [0][1][2][0][RTW89_KCC][64] = 12,
- [0][1][2][0][RTW89_FCC][66] = -2,
- [0][1][2][0][RTW89_ETSI][66] = 127,
- [0][1][2][0][RTW89_KCC][66] = 12,
- [0][1][2][0][RTW89_FCC][68] = -2,
- [0][1][2][0][RTW89_ETSI][68] = 127,
- [0][1][2][0][RTW89_KCC][68] = 12,
- [0][1][2][0][RTW89_FCC][70] = -2,
- [0][1][2][0][RTW89_ETSI][70] = 127,
- [0][1][2][0][RTW89_KCC][70] = 12,
- [0][1][2][0][RTW89_FCC][72] = -2,
- [0][1][2][0][RTW89_ETSI][72] = 127,
- [0][1][2][0][RTW89_KCC][72] = 12,
- [0][1][2][0][RTW89_FCC][74] = -2,
- [0][1][2][0][RTW89_ETSI][74] = 127,
- [0][1][2][0][RTW89_KCC][74] = 12,
- [0][1][2][0][RTW89_FCC][75] = -2,
- [0][1][2][0][RTW89_ETSI][75] = 127,
- [0][1][2][0][RTW89_KCC][75] = 12,
- [0][1][2][0][RTW89_FCC][77] = -2,
- [0][1][2][0][RTW89_ETSI][77] = 127,
- [0][1][2][0][RTW89_KCC][77] = 12,
- [0][1][2][0][RTW89_FCC][79] = -2,
- [0][1][2][0][RTW89_ETSI][79] = 127,
- [0][1][2][0][RTW89_KCC][79] = 12,
- [0][1][2][0][RTW89_FCC][81] = -2,
- [0][1][2][0][RTW89_ETSI][81] = 127,
- [0][1][2][0][RTW89_KCC][81] = 12,
- [0][1][2][0][RTW89_FCC][83] = -2,
- [0][1][2][0][RTW89_ETSI][83] = 127,
- [0][1][2][0][RTW89_KCC][83] = 20,
- [0][1][2][0][RTW89_FCC][85] = -2,
- [0][1][2][0][RTW89_ETSI][85] = 127,
- [0][1][2][0][RTW89_KCC][85] = 20,
- [0][1][2][0][RTW89_FCC][87] = -2,
- [0][1][2][0][RTW89_ETSI][87] = 127,
- [0][1][2][0][RTW89_KCC][87] = 20,
- [0][1][2][0][RTW89_FCC][89] = -2,
- [0][1][2][0][RTW89_ETSI][89] = 127,
- [0][1][2][0][RTW89_KCC][89] = 20,
- [0][1][2][0][RTW89_FCC][90] = -2,
- [0][1][2][0][RTW89_ETSI][90] = 127,
- [0][1][2][0][RTW89_KCC][90] = 20,
- [0][1][2][0][RTW89_FCC][92] = -2,
- [0][1][2][0][RTW89_ETSI][92] = 127,
- [0][1][2][0][RTW89_KCC][92] = 20,
- [0][1][2][0][RTW89_FCC][94] = -2,
- [0][1][2][0][RTW89_ETSI][94] = 127,
- [0][1][2][0][RTW89_KCC][94] = 20,
- [0][1][2][0][RTW89_FCC][96] = -2,
- [0][1][2][0][RTW89_ETSI][96] = 127,
- [0][1][2][0][RTW89_KCC][96] = 20,
- [0][1][2][0][RTW89_FCC][98] = -2,
- [0][1][2][0][RTW89_ETSI][98] = 127,
- [0][1][2][0][RTW89_KCC][98] = 20,
- [0][1][2][0][RTW89_FCC][100] = -2,
- [0][1][2][0][RTW89_ETSI][100] = 127,
- [0][1][2][0][RTW89_KCC][100] = 20,
- [0][1][2][0][RTW89_FCC][102] = -2,
- [0][1][2][0][RTW89_ETSI][102] = 127,
- [0][1][2][0][RTW89_KCC][102] = 20,
- [0][1][2][0][RTW89_FCC][104] = -2,
- [0][1][2][0][RTW89_ETSI][104] = 127,
- [0][1][2][0][RTW89_KCC][104] = 20,
- [0][1][2][0][RTW89_FCC][105] = -2,
- [0][1][2][0][RTW89_ETSI][105] = 127,
- [0][1][2][0][RTW89_KCC][105] = 20,
- [0][1][2][0][RTW89_FCC][107] = 0,
- [0][1][2][0][RTW89_ETSI][107] = 127,
- [0][1][2][0][RTW89_KCC][107] = 20,
- [0][1][2][0][RTW89_FCC][109] = 0,
- [0][1][2][0][RTW89_ETSI][109] = 127,
- [0][1][2][0][RTW89_KCC][109] = 20,
- [0][1][2][0][RTW89_FCC][111] = 127,
- [0][1][2][0][RTW89_ETSI][111] = 127,
- [0][1][2][0][RTW89_KCC][111] = 127,
- [0][1][2][0][RTW89_FCC][113] = 127,
- [0][1][2][0][RTW89_ETSI][113] = 127,
- [0][1][2][0][RTW89_KCC][113] = 127,
- [0][1][2][0][RTW89_FCC][115] = 127,
- [0][1][2][0][RTW89_ETSI][115] = 127,
- [0][1][2][0][RTW89_KCC][115] = 127,
- [0][1][2][0][RTW89_FCC][117] = 127,
- [0][1][2][0][RTW89_ETSI][117] = 127,
- [0][1][2][0][RTW89_KCC][117] = 127,
- [0][1][2][0][RTW89_FCC][119] = 127,
- [0][1][2][0][RTW89_ETSI][119] = 127,
- [0][1][2][0][RTW89_KCC][119] = 127,
- [0][1][2][1][RTW89_FCC][0] = -2,
- [0][1][2][1][RTW89_ETSI][0] = 42,
- [0][1][2][1][RTW89_KCC][0] = 12,
- [0][1][2][1][RTW89_FCC][2] = -4,
- [0][1][2][1][RTW89_ETSI][2] = 42,
- [0][1][2][1][RTW89_KCC][2] = 12,
- [0][1][2][1][RTW89_FCC][4] = -4,
- [0][1][2][1][RTW89_ETSI][4] = 42,
- [0][1][2][1][RTW89_KCC][4] = 12,
- [0][1][2][1][RTW89_FCC][6] = -4,
- [0][1][2][1][RTW89_ETSI][6] = 42,
- [0][1][2][1][RTW89_KCC][6] = 12,
- [0][1][2][1][RTW89_FCC][8] = -4,
- [0][1][2][1][RTW89_ETSI][8] = 42,
- [0][1][2][1][RTW89_KCC][8] = 12,
- [0][1][2][1][RTW89_FCC][10] = -4,
- [0][1][2][1][RTW89_ETSI][10] = 42,
- [0][1][2][1][RTW89_KCC][10] = 12,
- [0][1][2][1][RTW89_FCC][12] = -4,
- [0][1][2][1][RTW89_ETSI][12] = 42,
- [0][1][2][1][RTW89_KCC][12] = 12,
- [0][1][2][1][RTW89_FCC][14] = -4,
- [0][1][2][1][RTW89_ETSI][14] = 42,
- [0][1][2][1][RTW89_KCC][14] = 12,
- [0][1][2][1][RTW89_FCC][15] = -4,
- [0][1][2][1][RTW89_ETSI][15] = 42,
- [0][1][2][1][RTW89_KCC][15] = 12,
- [0][1][2][1][RTW89_FCC][17] = -4,
- [0][1][2][1][RTW89_ETSI][17] = 42,
- [0][1][2][1][RTW89_KCC][17] = 12,
- [0][1][2][1][RTW89_FCC][19] = -4,
- [0][1][2][1][RTW89_ETSI][19] = 42,
- [0][1][2][1][RTW89_KCC][19] = 12,
- [0][1][2][1][RTW89_FCC][21] = -4,
- [0][1][2][1][RTW89_ETSI][21] = 42,
- [0][1][2][1][RTW89_KCC][21] = 12,
- [0][1][2][1][RTW89_FCC][23] = -4,
- [0][1][2][1][RTW89_ETSI][23] = 42,
- [0][1][2][1][RTW89_KCC][23] = 12,
- [0][1][2][1][RTW89_FCC][25] = -4,
- [0][1][2][1][RTW89_ETSI][25] = 42,
- [0][1][2][1][RTW89_KCC][25] = 12,
- [0][1][2][1][RTW89_FCC][27] = -4,
- [0][1][2][1][RTW89_ETSI][27] = 42,
- [0][1][2][1][RTW89_KCC][27] = 12,
- [0][1][2][1][RTW89_FCC][29] = -4,
- [0][1][2][1][RTW89_ETSI][29] = 42,
- [0][1][2][1][RTW89_KCC][29] = 12,
- [0][1][2][1][RTW89_FCC][30] = -4,
- [0][1][2][1][RTW89_ETSI][30] = 42,
- [0][1][2][1][RTW89_KCC][30] = 12,
- [0][1][2][1][RTW89_FCC][32] = -4,
- [0][1][2][1][RTW89_ETSI][32] = 42,
- [0][1][2][1][RTW89_KCC][32] = 12,
- [0][1][2][1][RTW89_FCC][34] = -4,
- [0][1][2][1][RTW89_ETSI][34] = 42,
- [0][1][2][1][RTW89_KCC][34] = 12,
- [0][1][2][1][RTW89_FCC][36] = -4,
- [0][1][2][1][RTW89_ETSI][36] = 42,
- [0][1][2][1][RTW89_KCC][36] = 12,
- [0][1][2][1][RTW89_FCC][38] = -4,
- [0][1][2][1][RTW89_ETSI][38] = 42,
- [0][1][2][1][RTW89_KCC][38] = 12,
- [0][1][2][1][RTW89_FCC][40] = -4,
- [0][1][2][1][RTW89_ETSI][40] = 42,
- [0][1][2][1][RTW89_KCC][40] = 12,
- [0][1][2][1][RTW89_FCC][42] = -4,
- [0][1][2][1][RTW89_ETSI][42] = 42,
- [0][1][2][1][RTW89_KCC][42] = 12,
- [0][1][2][1][RTW89_FCC][44] = -2,
- [0][1][2][1][RTW89_ETSI][44] = 42,
- [0][1][2][1][RTW89_KCC][44] = 12,
- [0][1][2][1][RTW89_FCC][45] = -2,
- [0][1][2][1][RTW89_ETSI][45] = 127,
- [0][1][2][1][RTW89_KCC][45] = 12,
- [0][1][2][1][RTW89_FCC][47] = -2,
- [0][1][2][1][RTW89_ETSI][47] = 127,
- [0][1][2][1][RTW89_KCC][47] = 12,
- [0][1][2][1][RTW89_FCC][49] = -2,
- [0][1][2][1][RTW89_ETSI][49] = 127,
- [0][1][2][1][RTW89_KCC][49] = 12,
- [0][1][2][1][RTW89_FCC][51] = -2,
- [0][1][2][1][RTW89_ETSI][51] = 127,
- [0][1][2][1][RTW89_KCC][51] = 12,
- [0][1][2][1][RTW89_FCC][53] = -2,
- [0][1][2][1][RTW89_ETSI][53] = 127,
- [0][1][2][1][RTW89_KCC][53] = 12,
- [0][1][2][1][RTW89_FCC][55] = -2,
- [0][1][2][1][RTW89_ETSI][55] = 127,
- [0][1][2][1][RTW89_KCC][55] = 12,
- [0][1][2][1][RTW89_FCC][57] = -2,
- [0][1][2][1][RTW89_ETSI][57] = 127,
- [0][1][2][1][RTW89_KCC][57] = 12,
- [0][1][2][1][RTW89_FCC][59] = -2,
- [0][1][2][1][RTW89_ETSI][59] = 127,
- [0][1][2][1][RTW89_KCC][59] = 12,
- [0][1][2][1][RTW89_FCC][60] = -2,
- [0][1][2][1][RTW89_ETSI][60] = 127,
- [0][1][2][1][RTW89_KCC][60] = 12,
- [0][1][2][1][RTW89_FCC][62] = -2,
- [0][1][2][1][RTW89_ETSI][62] = 127,
- [0][1][2][1][RTW89_KCC][62] = 12,
- [0][1][2][1][RTW89_FCC][64] = -2,
- [0][1][2][1][RTW89_ETSI][64] = 127,
- [0][1][2][1][RTW89_KCC][64] = 12,
- [0][1][2][1][RTW89_FCC][66] = -2,
- [0][1][2][1][RTW89_ETSI][66] = 127,
- [0][1][2][1][RTW89_KCC][66] = 12,
- [0][1][2][1][RTW89_FCC][68] = -2,
- [0][1][2][1][RTW89_ETSI][68] = 127,
- [0][1][2][1][RTW89_KCC][68] = 12,
- [0][1][2][1][RTW89_FCC][70] = -2,
- [0][1][2][1][RTW89_ETSI][70] = 127,
- [0][1][2][1][RTW89_KCC][70] = 12,
- [0][1][2][1][RTW89_FCC][72] = -2,
- [0][1][2][1][RTW89_ETSI][72] = 127,
- [0][1][2][1][RTW89_KCC][72] = 12,
- [0][1][2][1][RTW89_FCC][74] = -2,
- [0][1][2][1][RTW89_ETSI][74] = 127,
- [0][1][2][1][RTW89_KCC][74] = 12,
- [0][1][2][1][RTW89_FCC][75] = -2,
- [0][1][2][1][RTW89_ETSI][75] = 127,
- [0][1][2][1][RTW89_KCC][75] = 12,
- [0][1][2][1][RTW89_FCC][77] = -2,
- [0][1][2][1][RTW89_ETSI][77] = 127,
- [0][1][2][1][RTW89_KCC][77] = 12,
- [0][1][2][1][RTW89_FCC][79] = -2,
- [0][1][2][1][RTW89_ETSI][79] = 127,
- [0][1][2][1][RTW89_KCC][79] = 12,
- [0][1][2][1][RTW89_FCC][81] = -2,
- [0][1][2][1][RTW89_ETSI][81] = 127,
- [0][1][2][1][RTW89_KCC][81] = 12,
- [0][1][2][1][RTW89_FCC][83] = -2,
- [0][1][2][1][RTW89_ETSI][83] = 127,
- [0][1][2][1][RTW89_KCC][83] = 20,
- [0][1][2][1][RTW89_FCC][85] = -2,
- [0][1][2][1][RTW89_ETSI][85] = 127,
- [0][1][2][1][RTW89_KCC][85] = 20,
- [0][1][2][1][RTW89_FCC][87] = -2,
- [0][1][2][1][RTW89_ETSI][87] = 127,
- [0][1][2][1][RTW89_KCC][87] = 20,
- [0][1][2][1][RTW89_FCC][89] = -2,
- [0][1][2][1][RTW89_ETSI][89] = 127,
- [0][1][2][1][RTW89_KCC][89] = 20,
- [0][1][2][1][RTW89_FCC][90] = -2,
- [0][1][2][1][RTW89_ETSI][90] = 127,
- [0][1][2][1][RTW89_KCC][90] = 20,
- [0][1][2][1][RTW89_FCC][92] = -2,
- [0][1][2][1][RTW89_ETSI][92] = 127,
- [0][1][2][1][RTW89_KCC][92] = 20,
- [0][1][2][1][RTW89_FCC][94] = -2,
- [0][1][2][1][RTW89_ETSI][94] = 127,
- [0][1][2][1][RTW89_KCC][94] = 20,
- [0][1][2][1][RTW89_FCC][96] = -2,
- [0][1][2][1][RTW89_ETSI][96] = 127,
- [0][1][2][1][RTW89_KCC][96] = 20,
- [0][1][2][1][RTW89_FCC][98] = -2,
- [0][1][2][1][RTW89_ETSI][98] = 127,
- [0][1][2][1][RTW89_KCC][98] = 20,
- [0][1][2][1][RTW89_FCC][100] = -2,
- [0][1][2][1][RTW89_ETSI][100] = 127,
- [0][1][2][1][RTW89_KCC][100] = 20,
- [0][1][2][1][RTW89_FCC][102] = -2,
- [0][1][2][1][RTW89_ETSI][102] = 127,
- [0][1][2][1][RTW89_KCC][102] = 20,
- [0][1][2][1][RTW89_FCC][104] = -2,
- [0][1][2][1][RTW89_ETSI][104] = 127,
- [0][1][2][1][RTW89_KCC][104] = 20,
- [0][1][2][1][RTW89_FCC][105] = -2,
- [0][1][2][1][RTW89_ETSI][105] = 127,
- [0][1][2][1][RTW89_KCC][105] = 20,
- [0][1][2][1][RTW89_FCC][107] = 0,
- [0][1][2][1][RTW89_ETSI][107] = 127,
- [0][1][2][1][RTW89_KCC][107] = 20,
- [0][1][2][1][RTW89_FCC][109] = 0,
- [0][1][2][1][RTW89_ETSI][109] = 127,
- [0][1][2][1][RTW89_KCC][109] = 20,
- [0][1][2][1][RTW89_FCC][111] = 127,
- [0][1][2][1][RTW89_ETSI][111] = 127,
- [0][1][2][1][RTW89_KCC][111] = 127,
- [0][1][2][1][RTW89_FCC][113] = 127,
- [0][1][2][1][RTW89_ETSI][113] = 127,
- [0][1][2][1][RTW89_KCC][113] = 127,
- [0][1][2][1][RTW89_FCC][115] = 127,
- [0][1][2][1][RTW89_ETSI][115] = 127,
- [0][1][2][1][RTW89_KCC][115] = 127,
- [0][1][2][1][RTW89_FCC][117] = 127,
- [0][1][2][1][RTW89_ETSI][117] = 127,
- [0][1][2][1][RTW89_KCC][117] = 127,
- [0][1][2][1][RTW89_FCC][119] = 127,
- [0][1][2][1][RTW89_ETSI][119] = 127,
- [0][1][2][1][RTW89_KCC][119] = 127,
- [1][0][2][0][RTW89_FCC][1] = 34,
- [1][0][2][0][RTW89_ETSI][1] = 66,
- [1][0][2][0][RTW89_KCC][1] = 40,
- [1][0][2][0][RTW89_FCC][5] = 34,
- [1][0][2][0][RTW89_ETSI][5] = 66,
- [1][0][2][0][RTW89_KCC][5] = 40,
- [1][0][2][0][RTW89_FCC][9] = 34,
- [1][0][2][0][RTW89_ETSI][9] = 66,
- [1][0][2][0][RTW89_KCC][9] = 40,
- [1][0][2][0][RTW89_FCC][13] = 34,
- [1][0][2][0][RTW89_ETSI][13] = 66,
- [1][0][2][0][RTW89_KCC][13] = 40,
- [1][0][2][0][RTW89_FCC][16] = 34,
- [1][0][2][0][RTW89_ETSI][16] = 66,
- [1][0][2][0][RTW89_KCC][16] = 40,
- [1][0][2][0][RTW89_FCC][20] = 34,
- [1][0][2][0][RTW89_ETSI][20] = 66,
- [1][0][2][0][RTW89_KCC][20] = 40,
- [1][0][2][0][RTW89_FCC][24] = 36,
- [1][0][2][0][RTW89_ETSI][24] = 66,
- [1][0][2][0][RTW89_KCC][24] = 40,
- [1][0][2][0][RTW89_FCC][28] = 34,
- [1][0][2][0][RTW89_ETSI][28] = 66,
- [1][0][2][0][RTW89_KCC][28] = 40,
- [1][0][2][0][RTW89_FCC][31] = 34,
- [1][0][2][0][RTW89_ETSI][31] = 66,
- [1][0][2][0][RTW89_KCC][31] = 40,
- [1][0][2][0][RTW89_FCC][35] = 34,
- [1][0][2][0][RTW89_ETSI][35] = 66,
- [1][0][2][0][RTW89_KCC][35] = 40,
- [1][0][2][0][RTW89_FCC][39] = 34,
- [1][0][2][0][RTW89_ETSI][39] = 66,
- [1][0][2][0][RTW89_KCC][39] = 40,
- [1][0][2][0][RTW89_FCC][43] = 34,
- [1][0][2][0][RTW89_ETSI][43] = 66,
- [1][0][2][0][RTW89_KCC][43] = 40,
- [1][0][2][0][RTW89_FCC][46] = 34,
- [1][0][2][0][RTW89_ETSI][46] = 127,
- [1][0][2][0][RTW89_KCC][46] = 40,
- [1][0][2][0][RTW89_FCC][50] = 34,
- [1][0][2][0][RTW89_ETSI][50] = 127,
- [1][0][2][0][RTW89_KCC][50] = 40,
- [1][0][2][0][RTW89_FCC][54] = 36,
- [1][0][2][0][RTW89_ETSI][54] = 127,
- [1][0][2][0][RTW89_KCC][54] = 40,
- [1][0][2][0][RTW89_FCC][58] = 36,
- [1][0][2][0][RTW89_ETSI][58] = 127,
- [1][0][2][0][RTW89_KCC][58] = 40,
- [1][0][2][0][RTW89_FCC][61] = 34,
- [1][0][2][0][RTW89_ETSI][61] = 127,
- [1][0][2][0][RTW89_KCC][61] = 40,
- [1][0][2][0][RTW89_FCC][65] = 34,
- [1][0][2][0][RTW89_ETSI][65] = 127,
- [1][0][2][0][RTW89_KCC][65] = 40,
- [1][0][2][0][RTW89_FCC][69] = 34,
- [1][0][2][0][RTW89_ETSI][69] = 127,
- [1][0][2][0][RTW89_KCC][69] = 40,
- [1][0][2][0][RTW89_FCC][73] = 34,
- [1][0][2][0][RTW89_ETSI][73] = 127,
- [1][0][2][0][RTW89_KCC][73] = 40,
- [1][0][2][0][RTW89_FCC][76] = 34,
- [1][0][2][0][RTW89_ETSI][76] = 127,
- [1][0][2][0][RTW89_KCC][76] = 40,
- [1][0][2][0][RTW89_FCC][80] = 34,
- [1][0][2][0][RTW89_ETSI][80] = 127,
- [1][0][2][0][RTW89_KCC][80] = 42,
- [1][0][2][0][RTW89_FCC][84] = 34,
- [1][0][2][0][RTW89_ETSI][84] = 127,
- [1][0][2][0][RTW89_KCC][84] = 42,
- [1][0][2][0][RTW89_FCC][88] = 34,
- [1][0][2][0][RTW89_ETSI][88] = 127,
- [1][0][2][0][RTW89_KCC][88] = 42,
- [1][0][2][0][RTW89_FCC][91] = 36,
- [1][0][2][0][RTW89_ETSI][91] = 127,
- [1][0][2][0][RTW89_KCC][91] = 42,
- [1][0][2][0][RTW89_FCC][95] = 34,
- [1][0][2][0][RTW89_ETSI][95] = 127,
- [1][0][2][0][RTW89_KCC][95] = 42,
- [1][0][2][0][RTW89_FCC][99] = 34,
- [1][0][2][0][RTW89_ETSI][99] = 127,
- [1][0][2][0][RTW89_KCC][99] = 42,
- [1][0][2][0][RTW89_FCC][103] = 34,
- [1][0][2][0][RTW89_ETSI][103] = 127,
- [1][0][2][0][RTW89_KCC][103] = 42,
- [1][0][2][0][RTW89_FCC][106] = 36,
- [1][0][2][0][RTW89_ETSI][106] = 127,
- [1][0][2][0][RTW89_KCC][106] = 42,
- [1][0][2][0][RTW89_FCC][110] = 127,
- [1][0][2][0][RTW89_ETSI][110] = 127,
- [1][0][2][0][RTW89_KCC][110] = 127,
- [1][0][2][0][RTW89_FCC][114] = 127,
- [1][0][2][0][RTW89_ETSI][114] = 127,
- [1][0][2][0][RTW89_KCC][114] = 127,
- [1][0][2][0][RTW89_FCC][118] = 127,
- [1][0][2][0][RTW89_ETSI][118] = 127,
- [1][0][2][0][RTW89_KCC][118] = 127,
- [1][1][2][0][RTW89_FCC][1] = 10,
- [1][1][2][0][RTW89_ETSI][1] = 54,
- [1][1][2][0][RTW89_KCC][1] = 28,
- [1][1][2][0][RTW89_FCC][5] = 10,
- [1][1][2][0][RTW89_ETSI][5] = 54,
- [1][1][2][0][RTW89_KCC][5] = 28,
- [1][1][2][0][RTW89_FCC][9] = 10,
- [1][1][2][0][RTW89_ETSI][9] = 54,
- [1][1][2][0][RTW89_KCC][9] = 28,
- [1][1][2][0][RTW89_FCC][13] = 10,
- [1][1][2][0][RTW89_ETSI][13] = 54,
- [1][1][2][0][RTW89_KCC][13] = 28,
- [1][1][2][0][RTW89_FCC][16] = 10,
- [1][1][2][0][RTW89_ETSI][16] = 54,
- [1][1][2][0][RTW89_KCC][16] = 28,
- [1][1][2][0][RTW89_FCC][20] = 10,
- [1][1][2][0][RTW89_ETSI][20] = 54,
- [1][1][2][0][RTW89_KCC][20] = 28,
- [1][1][2][0][RTW89_FCC][24] = 10,
- [1][1][2][0][RTW89_ETSI][24] = 54,
- [1][1][2][0][RTW89_KCC][24] = 28,
- [1][1][2][0][RTW89_FCC][28] = 10,
- [1][1][2][0][RTW89_ETSI][28] = 54,
- [1][1][2][0][RTW89_KCC][28] = 28,
- [1][1][2][0][RTW89_FCC][31] = 10,
- [1][1][2][0][RTW89_ETSI][31] = 54,
- [1][1][2][0][RTW89_KCC][31] = 28,
- [1][1][2][0][RTW89_FCC][35] = 10,
- [1][1][2][0][RTW89_ETSI][35] = 54,
- [1][1][2][0][RTW89_KCC][35] = 28,
- [1][1][2][0][RTW89_FCC][39] = 10,
- [1][1][2][0][RTW89_ETSI][39] = 54,
- [1][1][2][0][RTW89_KCC][39] = 28,
- [1][1][2][0][RTW89_FCC][43] = 10,
- [1][1][2][0][RTW89_ETSI][43] = 54,
- [1][1][2][0][RTW89_KCC][43] = 28,
- [1][1][2][0][RTW89_FCC][46] = 12,
- [1][1][2][0][RTW89_ETSI][46] = 127,
- [1][1][2][0][RTW89_KCC][46] = 28,
- [1][1][2][0][RTW89_FCC][50] = 12,
- [1][1][2][0][RTW89_ETSI][50] = 127,
- [1][1][2][0][RTW89_KCC][50] = 28,
- [1][1][2][0][RTW89_FCC][54] = 10,
- [1][1][2][0][RTW89_ETSI][54] = 127,
- [1][1][2][0][RTW89_KCC][54] = 28,
- [1][1][2][0][RTW89_FCC][58] = 10,
- [1][1][2][0][RTW89_ETSI][58] = 127,
- [1][1][2][0][RTW89_KCC][58] = 28,
- [1][1][2][0][RTW89_FCC][61] = 10,
- [1][1][2][0][RTW89_ETSI][61] = 127,
- [1][1][2][0][RTW89_KCC][61] = 28,
- [1][1][2][0][RTW89_FCC][65] = 10,
- [1][1][2][0][RTW89_ETSI][65] = 127,
- [1][1][2][0][RTW89_KCC][65] = 28,
- [1][1][2][0][RTW89_FCC][69] = 10,
- [1][1][2][0][RTW89_ETSI][69] = 127,
- [1][1][2][0][RTW89_KCC][69] = 28,
- [1][1][2][0][RTW89_FCC][73] = 10,
- [1][1][2][0][RTW89_ETSI][73] = 127,
- [1][1][2][0][RTW89_KCC][73] = 28,
- [1][1][2][0][RTW89_FCC][76] = 10,
- [1][1][2][0][RTW89_ETSI][76] = 127,
- [1][1][2][0][RTW89_KCC][76] = 28,
- [1][1][2][0][RTW89_FCC][80] = 10,
- [1][1][2][0][RTW89_ETSI][80] = 127,
- [1][1][2][0][RTW89_KCC][80] = 32,
- [1][1][2][0][RTW89_FCC][84] = 10,
- [1][1][2][0][RTW89_ETSI][84] = 127,
- [1][1][2][0][RTW89_KCC][84] = 32,
- [1][1][2][0][RTW89_FCC][88] = 10,
- [1][1][2][0][RTW89_ETSI][88] = 127,
- [1][1][2][0][RTW89_KCC][88] = 32,
- [1][1][2][0][RTW89_FCC][91] = 12,
- [1][1][2][0][RTW89_ETSI][91] = 127,
- [1][1][2][0][RTW89_KCC][91] = 32,
- [1][1][2][0][RTW89_FCC][95] = 10,
- [1][1][2][0][RTW89_ETSI][95] = 127,
- [1][1][2][0][RTW89_KCC][95] = 32,
- [1][1][2][0][RTW89_FCC][99] = 10,
- [1][1][2][0][RTW89_ETSI][99] = 127,
- [1][1][2][0][RTW89_KCC][99] = 32,
- [1][1][2][0][RTW89_FCC][103] = 10,
- [1][1][2][0][RTW89_ETSI][103] = 127,
- [1][1][2][0][RTW89_KCC][103] = 32,
- [1][1][2][0][RTW89_FCC][106] = 12,
- [1][1][2][0][RTW89_ETSI][106] = 127,
- [1][1][2][0][RTW89_KCC][106] = 32,
- [1][1][2][0][RTW89_FCC][110] = 127,
- [1][1][2][0][RTW89_ETSI][110] = 127,
- [1][1][2][0][RTW89_KCC][110] = 127,
- [1][1][2][0][RTW89_FCC][114] = 127,
- [1][1][2][0][RTW89_ETSI][114] = 127,
- [1][1][2][0][RTW89_KCC][114] = 127,
- [1][1][2][0][RTW89_FCC][118] = 127,
- [1][1][2][0][RTW89_ETSI][118] = 127,
- [1][1][2][0][RTW89_KCC][118] = 127,
- [1][1][2][1][RTW89_FCC][1] = 10,
- [1][1][2][1][RTW89_ETSI][1] = 42,
- [1][1][2][1][RTW89_KCC][1] = 28,
- [1][1][2][1][RTW89_FCC][5] = 10,
- [1][1][2][1][RTW89_ETSI][5] = 42,
- [1][1][2][1][RTW89_KCC][5] = 28,
- [1][1][2][1][RTW89_FCC][9] = 10,
- [1][1][2][1][RTW89_ETSI][9] = 42,
- [1][1][2][1][RTW89_KCC][9] = 28,
- [1][1][2][1][RTW89_FCC][13] = 10,
- [1][1][2][1][RTW89_ETSI][13] = 42,
- [1][1][2][1][RTW89_KCC][13] = 28,
- [1][1][2][1][RTW89_FCC][16] = 10,
- [1][1][2][1][RTW89_ETSI][16] = 42,
- [1][1][2][1][RTW89_KCC][16] = 28,
- [1][1][2][1][RTW89_FCC][20] = 10,
- [1][1][2][1][RTW89_ETSI][20] = 42,
- [1][1][2][1][RTW89_KCC][20] = 28,
- [1][1][2][1][RTW89_FCC][24] = 10,
- [1][1][2][1][RTW89_ETSI][24] = 42,
- [1][1][2][1][RTW89_KCC][24] = 28,
- [1][1][2][1][RTW89_FCC][28] = 10,
- [1][1][2][1][RTW89_ETSI][28] = 42,
- [1][1][2][1][RTW89_KCC][28] = 28,
- [1][1][2][1][RTW89_FCC][31] = 10,
- [1][1][2][1][RTW89_ETSI][31] = 42,
- [1][1][2][1][RTW89_KCC][31] = 28,
- [1][1][2][1][RTW89_FCC][35] = 10,
- [1][1][2][1][RTW89_ETSI][35] = 42,
- [1][1][2][1][RTW89_KCC][35] = 28,
- [1][1][2][1][RTW89_FCC][39] = 10,
- [1][1][2][1][RTW89_ETSI][39] = 42,
- [1][1][2][1][RTW89_KCC][39] = 28,
- [1][1][2][1][RTW89_FCC][43] = 10,
- [1][1][2][1][RTW89_ETSI][43] = 42,
- [1][1][2][1][RTW89_KCC][43] = 28,
- [1][1][2][1][RTW89_FCC][46] = 12,
- [1][1][2][1][RTW89_ETSI][46] = 127,
- [1][1][2][1][RTW89_KCC][46] = 28,
- [1][1][2][1][RTW89_FCC][50] = 12,
- [1][1][2][1][RTW89_ETSI][50] = 127,
- [1][1][2][1][RTW89_KCC][50] = 28,
- [1][1][2][1][RTW89_FCC][54] = 10,
- [1][1][2][1][RTW89_ETSI][54] = 127,
- [1][1][2][1][RTW89_KCC][54] = 28,
- [1][1][2][1][RTW89_FCC][58] = 10,
- [1][1][2][1][RTW89_ETSI][58] = 127,
- [1][1][2][1][RTW89_KCC][58] = 28,
- [1][1][2][1][RTW89_FCC][61] = 10,
- [1][1][2][1][RTW89_ETSI][61] = 127,
- [1][1][2][1][RTW89_KCC][61] = 28,
- [1][1][2][1][RTW89_FCC][65] = 10,
- [1][1][2][1][RTW89_ETSI][65] = 127,
- [1][1][2][1][RTW89_KCC][65] = 28,
- [1][1][2][1][RTW89_FCC][69] = 10,
- [1][1][2][1][RTW89_ETSI][69] = 127,
- [1][1][2][1][RTW89_KCC][69] = 28,
- [1][1][2][1][RTW89_FCC][73] = 10,
- [1][1][2][1][RTW89_ETSI][73] = 127,
- [1][1][2][1][RTW89_KCC][73] = 28,
- [1][1][2][1][RTW89_FCC][76] = 10,
- [1][1][2][1][RTW89_ETSI][76] = 127,
- [1][1][2][1][RTW89_KCC][76] = 28,
- [1][1][2][1][RTW89_FCC][80] = 10,
- [1][1][2][1][RTW89_ETSI][80] = 127,
- [1][1][2][1][RTW89_KCC][80] = 32,
- [1][1][2][1][RTW89_FCC][84] = 10,
- [1][1][2][1][RTW89_ETSI][84] = 127,
- [1][1][2][1][RTW89_KCC][84] = 32,
- [1][1][2][1][RTW89_FCC][88] = 10,
- [1][1][2][1][RTW89_ETSI][88] = 127,
- [1][1][2][1][RTW89_KCC][88] = 32,
- [1][1][2][1][RTW89_FCC][91] = 12,
- [1][1][2][1][RTW89_ETSI][91] = 127,
- [1][1][2][1][RTW89_KCC][91] = 32,
- [1][1][2][1][RTW89_FCC][95] = 10,
- [1][1][2][1][RTW89_ETSI][95] = 127,
- [1][1][2][1][RTW89_KCC][95] = 32,
- [1][1][2][1][RTW89_FCC][99] = 10,
- [1][1][2][1][RTW89_ETSI][99] = 127,
- [1][1][2][1][RTW89_KCC][99] = 32,
- [1][1][2][1][RTW89_FCC][103] = 10,
- [1][1][2][1][RTW89_ETSI][103] = 127,
- [1][1][2][1][RTW89_KCC][103] = 32,
- [1][1][2][1][RTW89_FCC][106] = 12,
- [1][1][2][1][RTW89_ETSI][106] = 127,
- [1][1][2][1][RTW89_KCC][106] = 32,
- [1][1][2][1][RTW89_FCC][110] = 127,
- [1][1][2][1][RTW89_ETSI][110] = 127,
- [1][1][2][1][RTW89_KCC][110] = 127,
- [1][1][2][1][RTW89_FCC][114] = 127,
- [1][1][2][1][RTW89_ETSI][114] = 127,
- [1][1][2][1][RTW89_KCC][114] = 127,
- [1][1][2][1][RTW89_FCC][118] = 127,
- [1][1][2][1][RTW89_ETSI][118] = 127,
- [1][1][2][1][RTW89_KCC][118] = 127,
- [2][0][2][0][RTW89_FCC][3] = 46,
- [2][0][2][0][RTW89_ETSI][3] = 48,
- [2][0][2][0][RTW89_KCC][3] = 50,
- [2][0][2][0][RTW89_FCC][11] = 46,
- [2][0][2][0][RTW89_ETSI][11] = 48,
- [2][0][2][0][RTW89_KCC][11] = 50,
- [2][0][2][0][RTW89_FCC][18] = 46,
- [2][0][2][0][RTW89_ETSI][18] = 48,
- [2][0][2][0][RTW89_KCC][18] = 50,
- [2][0][2][0][RTW89_FCC][26] = 46,
- [2][0][2][0][RTW89_ETSI][26] = 48,
- [2][0][2][0][RTW89_KCC][26] = 50,
- [2][0][2][0][RTW89_FCC][33] = 46,
- [2][0][2][0][RTW89_ETSI][33] = 48,
- [2][0][2][0][RTW89_KCC][33] = 50,
- [2][0][2][0][RTW89_FCC][41] = 46,
- [2][0][2][0][RTW89_ETSI][41] = 48,
- [2][0][2][0][RTW89_KCC][41] = 50,
- [2][0][2][0][RTW89_FCC][48] = 46,
- [2][0][2][0][RTW89_ETSI][48] = 127,
- [2][0][2][0][RTW89_KCC][48] = 48,
- [2][0][2][0][RTW89_FCC][56] = 46,
- [2][0][2][0][RTW89_ETSI][56] = 127,
- [2][0][2][0][RTW89_KCC][56] = 48,
- [2][0][2][0][RTW89_FCC][63] = 46,
- [2][0][2][0][RTW89_ETSI][63] = 127,
- [2][0][2][0][RTW89_KCC][63] = 48,
- [2][0][2][0][RTW89_FCC][71] = 46,
- [2][0][2][0][RTW89_ETSI][71] = 127,
- [2][0][2][0][RTW89_KCC][71] = 48,
- [2][0][2][0][RTW89_FCC][78] = 46,
- [2][0][2][0][RTW89_ETSI][78] = 127,
- [2][0][2][0][RTW89_KCC][78] = 52,
- [2][0][2][0][RTW89_FCC][86] = 46,
- [2][0][2][0][RTW89_ETSI][86] = 127,
- [2][0][2][0][RTW89_KCC][86] = 52,
- [2][0][2][0][RTW89_FCC][93] = 46,
- [2][0][2][0][RTW89_ETSI][93] = 127,
- [2][0][2][0][RTW89_KCC][93] = 50,
- [2][0][2][0][RTW89_FCC][101] = 44,
- [2][0][2][0][RTW89_ETSI][101] = 127,
- [2][0][2][0][RTW89_KCC][101] = 50,
- [2][0][2][0][RTW89_FCC][108] = 127,
- [2][0][2][0][RTW89_ETSI][108] = 127,
- [2][0][2][0][RTW89_KCC][108] = 127,
- [2][0][2][0][RTW89_FCC][116] = 127,
- [2][0][2][0][RTW89_ETSI][116] = 127,
- [2][0][2][0][RTW89_KCC][116] = 127,
- [2][1][2][0][RTW89_FCC][3] = 22,
- [2][1][2][0][RTW89_ETSI][3] = 48,
- [2][1][2][0][RTW89_KCC][3] = 38,
- [2][1][2][0][RTW89_FCC][11] = 20,
- [2][1][2][0][RTW89_ETSI][11] = 48,
- [2][1][2][0][RTW89_KCC][11] = 38,
- [2][1][2][0][RTW89_FCC][18] = 20,
- [2][1][2][0][RTW89_ETSI][18] = 48,
- [2][1][2][0][RTW89_KCC][18] = 38,
- [2][1][2][0][RTW89_FCC][26] = 20,
- [2][1][2][0][RTW89_ETSI][26] = 48,
- [2][1][2][0][RTW89_KCC][26] = 38,
- [2][1][2][0][RTW89_FCC][33] = 20,
- [2][1][2][0][RTW89_ETSI][33] = 48,
- [2][1][2][0][RTW89_KCC][33] = 38,
- [2][1][2][0][RTW89_FCC][41] = 22,
- [2][1][2][0][RTW89_ETSI][41] = 48,
- [2][1][2][0][RTW89_KCC][41] = 38,
- [2][1][2][0][RTW89_FCC][48] = 22,
- [2][1][2][0][RTW89_ETSI][48] = 127,
- [2][1][2][0][RTW89_KCC][48] = 38,
- [2][1][2][0][RTW89_FCC][56] = 20,
- [2][1][2][0][RTW89_ETSI][56] = 127,
- [2][1][2][0][RTW89_KCC][56] = 38,
- [2][1][2][0][RTW89_FCC][63] = 22,
- [2][1][2][0][RTW89_ETSI][63] = 127,
- [2][1][2][0][RTW89_KCC][63] = 38,
- [2][1][2][0][RTW89_FCC][71] = 20,
- [2][1][2][0][RTW89_ETSI][71] = 127,
- [2][1][2][0][RTW89_KCC][71] = 38,
- [2][1][2][0][RTW89_FCC][78] = 20,
- [2][1][2][0][RTW89_ETSI][78] = 127,
- [2][1][2][0][RTW89_KCC][78] = 38,
- [2][1][2][0][RTW89_FCC][86] = 20,
- [2][1][2][0][RTW89_ETSI][86] = 127,
- [2][1][2][0][RTW89_KCC][86] = 38,
- [2][1][2][0][RTW89_FCC][93] = 22,
- [2][1][2][0][RTW89_ETSI][93] = 127,
- [2][1][2][0][RTW89_KCC][93] = 38,
- [2][1][2][0][RTW89_FCC][101] = 22,
- [2][1][2][0][RTW89_ETSI][101] = 127,
- [2][1][2][0][RTW89_KCC][101] = 38,
- [2][1][2][0][RTW89_FCC][108] = 127,
- [2][1][2][0][RTW89_ETSI][108] = 127,
- [2][1][2][0][RTW89_KCC][108] = 127,
- [2][1][2][0][RTW89_FCC][116] = 127,
- [2][1][2][0][RTW89_ETSI][116] = 127,
- [2][1][2][0][RTW89_KCC][116] = 127,
- [2][1][2][1][RTW89_FCC][3] = 22,
- [2][1][2][1][RTW89_ETSI][3] = 42,
- [2][1][2][1][RTW89_KCC][3] = 38,
- [2][1][2][1][RTW89_FCC][11] = 20,
- [2][1][2][1][RTW89_ETSI][11] = 42,
- [2][1][2][1][RTW89_KCC][11] = 38,
- [2][1][2][1][RTW89_FCC][18] = 20,
- [2][1][2][1][RTW89_ETSI][18] = 42,
- [2][1][2][1][RTW89_KCC][18] = 38,
- [2][1][2][1][RTW89_FCC][26] = 20,
- [2][1][2][1][RTW89_ETSI][26] = 42,
- [2][1][2][1][RTW89_KCC][26] = 38,
- [2][1][2][1][RTW89_FCC][33] = 20,
- [2][1][2][1][RTW89_ETSI][33] = 42,
- [2][1][2][1][RTW89_KCC][33] = 38,
- [2][1][2][1][RTW89_FCC][41] = 22,
- [2][1][2][1][RTW89_ETSI][41] = 42,
- [2][1][2][1][RTW89_KCC][41] = 38,
- [2][1][2][1][RTW89_FCC][48] = 22,
- [2][1][2][1][RTW89_ETSI][48] = 127,
- [2][1][2][1][RTW89_KCC][48] = 38,
- [2][1][2][1][RTW89_FCC][56] = 20,
- [2][1][2][1][RTW89_ETSI][56] = 127,
- [2][1][2][1][RTW89_KCC][56] = 38,
- [2][1][2][1][RTW89_FCC][63] = 22,
- [2][1][2][1][RTW89_ETSI][63] = 127,
- [2][1][2][1][RTW89_KCC][63] = 38,
- [2][1][2][1][RTW89_FCC][71] = 20,
- [2][1][2][1][RTW89_ETSI][71] = 127,
- [2][1][2][1][RTW89_KCC][71] = 38,
- [2][1][2][1][RTW89_FCC][78] = 20,
- [2][1][2][1][RTW89_ETSI][78] = 127,
- [2][1][2][1][RTW89_KCC][78] = 38,
- [2][1][2][1][RTW89_FCC][86] = 20,
- [2][1][2][1][RTW89_ETSI][86] = 127,
- [2][1][2][1][RTW89_KCC][86] = 38,
- [2][1][2][1][RTW89_FCC][93] = 22,
- [2][1][2][1][RTW89_ETSI][93] = 127,
- [2][1][2][1][RTW89_KCC][93] = 38,
- [2][1][2][1][RTW89_FCC][101] = 22,
- [2][1][2][1][RTW89_ETSI][101] = 127,
- [2][1][2][1][RTW89_KCC][101] = 38,
- [2][1][2][1][RTW89_FCC][108] = 127,
- [2][1][2][1][RTW89_ETSI][108] = 127,
- [2][1][2][1][RTW89_KCC][108] = 127,
- [2][1][2][1][RTW89_FCC][116] = 127,
- [2][1][2][1][RTW89_ETSI][116] = 127,
- [2][1][2][1][RTW89_KCC][116] = 127,
- [3][0][2][0][RTW89_FCC][7] = 52,
- [3][0][2][0][RTW89_ETSI][7] = 38,
- [3][0][2][0][RTW89_KCC][7] = 42,
- [3][0][2][0][RTW89_FCC][22] = 52,
- [3][0][2][0][RTW89_ETSI][22] = 38,
- [3][0][2][0][RTW89_KCC][22] = 42,
- [3][0][2][0][RTW89_FCC][37] = 52,
- [3][0][2][0][RTW89_ETSI][37] = 38,
- [3][0][2][0][RTW89_KCC][37] = 42,
- [3][0][2][0][RTW89_FCC][52] = 54,
- [3][0][2][0][RTW89_ETSI][52] = 127,
- [3][0][2][0][RTW89_KCC][52] = 56,
- [3][0][2][0][RTW89_FCC][67] = 54,
- [3][0][2][0][RTW89_ETSI][67] = 127,
- [3][0][2][0][RTW89_KCC][67] = 54,
- [3][0][2][0][RTW89_FCC][82] = 54,
- [3][0][2][0][RTW89_ETSI][82] = 127,
- [3][0][2][0][RTW89_KCC][82] = 26,
- [3][0][2][0][RTW89_FCC][97] = 40,
- [3][0][2][0][RTW89_ETSI][97] = 127,
- [3][0][2][0][RTW89_KCC][97] = 26,
- [3][0][2][0][RTW89_FCC][112] = 127,
- [3][0][2][0][RTW89_ETSI][112] = 127,
- [3][0][2][0][RTW89_KCC][112] = 127,
- [3][1][2][0][RTW89_FCC][7] = 32,
- [3][1][2][0][RTW89_ETSI][7] = 38,
- [3][1][2][0][RTW89_KCC][7] = 40,
- [3][1][2][0][RTW89_FCC][22] = 30,
- [3][1][2][0][RTW89_ETSI][22] = 38,
- [3][1][2][0][RTW89_KCC][22] = 40,
- [3][1][2][0][RTW89_FCC][37] = 30,
- [3][1][2][0][RTW89_ETSI][37] = 38,
- [3][1][2][0][RTW89_KCC][37] = 40,
- [3][1][2][0][RTW89_FCC][52] = 30,
- [3][1][2][0][RTW89_ETSI][52] = 127,
- [3][1][2][0][RTW89_KCC][52] = 48,
- [3][1][2][0][RTW89_FCC][67] = 32,
- [3][1][2][0][RTW89_ETSI][67] = 127,
- [3][1][2][0][RTW89_KCC][67] = 48,
- [3][1][2][0][RTW89_FCC][82] = 32,
- [3][1][2][0][RTW89_ETSI][82] = 127,
- [3][1][2][0][RTW89_KCC][82] = 24,
- [3][1][2][0][RTW89_FCC][97] = 14,
- [3][1][2][0][RTW89_ETSI][97] = 127,
- [3][1][2][0][RTW89_KCC][97] = 24,
- [3][1][2][0][RTW89_FCC][112] = 127,
- [3][1][2][0][RTW89_ETSI][112] = 127,
- [3][1][2][0][RTW89_KCC][112] = 127,
- [3][1][2][1][RTW89_FCC][7] = 32,
- [3][1][2][1][RTW89_ETSI][7] = 38,
- [3][1][2][1][RTW89_KCC][7] = 40,
- [3][1][2][1][RTW89_FCC][22] = 30,
- [3][1][2][1][RTW89_ETSI][22] = 38,
- [3][1][2][1][RTW89_KCC][22] = 40,
- [3][1][2][1][RTW89_FCC][37] = 30,
- [3][1][2][1][RTW89_ETSI][37] = 38,
- [3][1][2][1][RTW89_KCC][37] = 40,
- [3][1][2][1][RTW89_FCC][52] = 30,
- [3][1][2][1][RTW89_ETSI][52] = 127,
- [3][1][2][1][RTW89_KCC][52] = 48,
- [3][1][2][1][RTW89_FCC][67] = 32,
- [3][1][2][1][RTW89_ETSI][67] = 127,
- [3][1][2][1][RTW89_KCC][67] = 48,
- [3][1][2][1][RTW89_FCC][82] = 32,
- [3][1][2][1][RTW89_ETSI][82] = 127,
- [3][1][2][1][RTW89_KCC][82] = 24,
- [3][1][2][1][RTW89_FCC][97] = 14,
- [3][1][2][1][RTW89_ETSI][97] = 127,
- [3][1][2][1][RTW89_KCC][97] = 24,
- [3][1][2][1][RTW89_FCC][112] = 127,
- [3][1][2][1][RTW89_ETSI][112] = 127,
- [3][1][2][1][RTW89_KCC][112] = 127,
+ [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
+ [RTW89_6G_CH_NUM] = {
+ [0][0][1][0][RTW89_WW][0][0] = 24,
+ [0][0][1][0][RTW89_WW][1][0] = 24,
+ [0][0][1][0][RTW89_WW][2][0] = 56,
+ [0][0][1][0][RTW89_WW][0][2] = 22,
+ [0][0][1][0][RTW89_WW][1][2] = 22,
+ [0][0][1][0][RTW89_WW][2][2] = 56,
+ [0][0][1][0][RTW89_WW][0][4] = 22,
+ [0][0][1][0][RTW89_WW][1][4] = 22,
+ [0][0][1][0][RTW89_WW][2][4] = 56,
+ [0][0][1][0][RTW89_WW][0][6] = 22,
+ [0][0][1][0][RTW89_WW][1][6] = 22,
+ [0][0][1][0][RTW89_WW][2][6] = 56,
+ [0][0][1][0][RTW89_WW][0][8] = 22,
+ [0][0][1][0][RTW89_WW][1][8] = 22,
+ [0][0][1][0][RTW89_WW][2][8] = 56,
+ [0][0][1][0][RTW89_WW][0][10] = 22,
+ [0][0][1][0][RTW89_WW][1][10] = 22,
+ [0][0][1][0][RTW89_WW][2][10] = 56,
+ [0][0][1][0][RTW89_WW][0][12] = 22,
+ [0][0][1][0][RTW89_WW][1][12] = 22,
+ [0][0][1][0][RTW89_WW][2][12] = 56,
+ [0][0][1][0][RTW89_WW][0][14] = 22,
+ [0][0][1][0][RTW89_WW][1][14] = 22,
+ [0][0][1][0][RTW89_WW][2][14] = 56,
+ [0][0][1][0][RTW89_WW][0][15] = 22,
+ [0][0][1][0][RTW89_WW][1][15] = 22,
+ [0][0][1][0][RTW89_WW][2][15] = 56,
+ [0][0][1][0][RTW89_WW][0][17] = 22,
+ [0][0][1][0][RTW89_WW][1][17] = 22,
+ [0][0][1][0][RTW89_WW][2][17] = 56,
+ [0][0][1][0][RTW89_WW][0][19] = 22,
+ [0][0][1][0][RTW89_WW][1][19] = 22,
+ [0][0][1][0][RTW89_WW][2][19] = 56,
+ [0][0][1][0][RTW89_WW][0][21] = 22,
+ [0][0][1][0][RTW89_WW][1][21] = 22,
+ [0][0][1][0][RTW89_WW][2][21] = 56,
+ [0][0][1][0][RTW89_WW][0][23] = 22,
+ [0][0][1][0][RTW89_WW][1][23] = 22,
+ [0][0][1][0][RTW89_WW][2][23] = 70,
+ [0][0][1][0][RTW89_WW][0][25] = 22,
+ [0][0][1][0][RTW89_WW][1][25] = 22,
+ [0][0][1][0][RTW89_WW][2][25] = 70,
+ [0][0][1][0][RTW89_WW][0][27] = 22,
+ [0][0][1][0][RTW89_WW][1][27] = 22,
+ [0][0][1][0][RTW89_WW][2][27] = 70,
+ [0][0][1][0][RTW89_WW][0][29] = 22,
+ [0][0][1][0][RTW89_WW][1][29] = 22,
+ [0][0][1][0][RTW89_WW][2][29] = 70,
+ [0][0][1][0][RTW89_WW][0][30] = 22,
+ [0][0][1][0][RTW89_WW][1][30] = 22,
+ [0][0][1][0][RTW89_WW][2][30] = 70,
+ [0][0][1][0][RTW89_WW][0][32] = 22,
+ [0][0][1][0][RTW89_WW][1][32] = 22,
+ [0][0][1][0][RTW89_WW][2][32] = 70,
+ [0][0][1][0][RTW89_WW][0][34] = 22,
+ [0][0][1][0][RTW89_WW][1][34] = 22,
+ [0][0][1][0][RTW89_WW][2][34] = 70,
+ [0][0][1][0][RTW89_WW][0][36] = 22,
+ [0][0][1][0][RTW89_WW][1][36] = 22,
+ [0][0][1][0][RTW89_WW][2][36] = 70,
+ [0][0][1][0][RTW89_WW][0][38] = 22,
+ [0][0][1][0][RTW89_WW][1][38] = 22,
+ [0][0][1][0][RTW89_WW][2][38] = 70,
+ [0][0][1][0][RTW89_WW][0][40] = 22,
+ [0][0][1][0][RTW89_WW][1][40] = 22,
+ [0][0][1][0][RTW89_WW][2][40] = 70,
+ [0][0][1][0][RTW89_WW][0][42] = 22,
+ [0][0][1][0][RTW89_WW][1][42] = 22,
+ [0][0][1][0][RTW89_WW][2][42] = 70,
+ [0][0][1][0][RTW89_WW][0][44] = 22,
+ [0][0][1][0][RTW89_WW][1][44] = 22,
+ [0][0][1][0][RTW89_WW][2][44] = 70,
+ [0][0][1][0][RTW89_WW][0][45] = 22,
+ [0][0][1][0][RTW89_WW][1][45] = 22,
+ [0][0][1][0][RTW89_WW][2][45] = 0,
+ [0][0][1][0][RTW89_WW][0][47] = 22,
+ [0][0][1][0][RTW89_WW][1][47] = 22,
+ [0][0][1][0][RTW89_WW][2][47] = 0,
+ [0][0][1][0][RTW89_WW][0][49] = 24,
+ [0][0][1][0][RTW89_WW][1][49] = 24,
+ [0][0][1][0][RTW89_WW][2][49] = 0,
+ [0][0][1][0][RTW89_WW][0][51] = 22,
+ [0][0][1][0][RTW89_WW][1][51] = 22,
+ [0][0][1][0][RTW89_WW][2][51] = 0,
+ [0][0][1][0][RTW89_WW][0][53] = 22,
+ [0][0][1][0][RTW89_WW][1][53] = 22,
+ [0][0][1][0][RTW89_WW][2][53] = 0,
+ [0][0][1][0][RTW89_WW][0][55] = 22,
+ [0][0][1][0][RTW89_WW][1][55] = 22,
+ [0][0][1][0][RTW89_WW][2][55] = 68,
+ [0][0][1][0][RTW89_WW][0][57] = 22,
+ [0][0][1][0][RTW89_WW][1][57] = 22,
+ [0][0][1][0][RTW89_WW][2][57] = 68,
+ [0][0][1][0][RTW89_WW][0][59] = 22,
+ [0][0][1][0][RTW89_WW][1][59] = 22,
+ [0][0][1][0][RTW89_WW][2][59] = 68,
+ [0][0][1][0][RTW89_WW][0][60] = 22,
+ [0][0][1][0][RTW89_WW][1][60] = 22,
+ [0][0][1][0][RTW89_WW][2][60] = 68,
+ [0][0][1][0][RTW89_WW][0][62] = 22,
+ [0][0][1][0][RTW89_WW][1][62] = 22,
+ [0][0][1][0][RTW89_WW][2][62] = 68,
+ [0][0][1][0][RTW89_WW][0][64] = 22,
+ [0][0][1][0][RTW89_WW][1][64] = 22,
+ [0][0][1][0][RTW89_WW][2][64] = 68,
+ [0][0][1][0][RTW89_WW][0][66] = 22,
+ [0][0][1][0][RTW89_WW][1][66] = 22,
+ [0][0][1][0][RTW89_WW][2][66] = 68,
+ [0][0][1][0][RTW89_WW][0][68] = 22,
+ [0][0][1][0][RTW89_WW][1][68] = 22,
+ [0][0][1][0][RTW89_WW][2][68] = 68,
+ [0][0][1][0][RTW89_WW][0][70] = 24,
+ [0][0][1][0][RTW89_WW][1][70] = 24,
+ [0][0][1][0][RTW89_WW][2][70] = 68,
+ [0][0][1][0][RTW89_WW][0][72] = 22,
+ [0][0][1][0][RTW89_WW][1][72] = 22,
+ [0][0][1][0][RTW89_WW][2][72] = 68,
+ [0][0][1][0][RTW89_WW][0][74] = 22,
+ [0][0][1][0][RTW89_WW][1][74] = 22,
+ [0][0][1][0][RTW89_WW][2][74] = 68,
+ [0][0][1][0][RTW89_WW][0][75] = 22,
+ [0][0][1][0][RTW89_WW][1][75] = 22,
+ [0][0][1][0][RTW89_WW][2][75] = 68,
+ [0][0][1][0][RTW89_WW][0][77] = 22,
+ [0][0][1][0][RTW89_WW][1][77] = 22,
+ [0][0][1][0][RTW89_WW][2][77] = 68,
+ [0][0][1][0][RTW89_WW][0][79] = 22,
+ [0][0][1][0][RTW89_WW][1][79] = 22,
+ [0][0][1][0][RTW89_WW][2][79] = 68,
+ [0][0][1][0][RTW89_WW][0][81] = 22,
+ [0][0][1][0][RTW89_WW][1][81] = 22,
+ [0][0][1][0][RTW89_WW][2][81] = 68,
+ [0][0][1][0][RTW89_WW][0][83] = 22,
+ [0][0][1][0][RTW89_WW][1][83] = 22,
+ [0][0][1][0][RTW89_WW][2][83] = 68,
+ [0][0][1][0][RTW89_WW][0][85] = 22,
+ [0][0][1][0][RTW89_WW][1][85] = 22,
+ [0][0][1][0][RTW89_WW][2][85] = 68,
+ [0][0][1][0][RTW89_WW][0][87] = 22,
+ [0][0][1][0][RTW89_WW][1][87] = 22,
+ [0][0][1][0][RTW89_WW][2][87] = 0,
+ [0][0][1][0][RTW89_WW][0][89] = 22,
+ [0][0][1][0][RTW89_WW][1][89] = 22,
+ [0][0][1][0][RTW89_WW][2][89] = 0,
+ [0][0][1][0][RTW89_WW][0][90] = 22,
+ [0][0][1][0][RTW89_WW][1][90] = 22,
+ [0][0][1][0][RTW89_WW][2][90] = 0,
+ [0][0][1][0][RTW89_WW][0][92] = 22,
+ [0][0][1][0][RTW89_WW][1][92] = 22,
+ [0][0][1][0][RTW89_WW][2][92] = 0,
+ [0][0][1][0][RTW89_WW][0][94] = 22,
+ [0][0][1][0][RTW89_WW][1][94] = 22,
+ [0][0][1][0][RTW89_WW][2][94] = 0,
+ [0][0][1][0][RTW89_WW][0][96] = 22,
+ [0][0][1][0][RTW89_WW][1][96] = 22,
+ [0][0][1][0][RTW89_WW][2][96] = 0,
+ [0][0][1][0][RTW89_WW][0][98] = 22,
+ [0][0][1][0][RTW89_WW][1][98] = 22,
+ [0][0][1][0][RTW89_WW][2][98] = 0,
+ [0][0][1][0][RTW89_WW][0][100] = 22,
+ [0][0][1][0][RTW89_WW][1][100] = 22,
+ [0][0][1][0][RTW89_WW][2][100] = 0,
+ [0][0][1][0][RTW89_WW][0][102] = 22,
+ [0][0][1][0][RTW89_WW][1][102] = 22,
+ [0][0][1][0][RTW89_WW][2][102] = 0,
+ [0][0][1][0][RTW89_WW][0][104] = 22,
+ [0][0][1][0][RTW89_WW][1][104] = 22,
+ [0][0][1][0][RTW89_WW][2][104] = 0,
+ [0][0][1][0][RTW89_WW][0][105] = 22,
+ [0][0][1][0][RTW89_WW][1][105] = 22,
+ [0][0][1][0][RTW89_WW][2][105] = 0,
+ [0][0][1][0][RTW89_WW][0][107] = 24,
+ [0][0][1][0][RTW89_WW][1][107] = 24,
+ [0][0][1][0][RTW89_WW][2][107] = 0,
+ [0][0][1][0][RTW89_WW][0][109] = 24,
+ [0][0][1][0][RTW89_WW][1][109] = 24,
+ [0][0][1][0][RTW89_WW][2][109] = 0,
+ [0][0][1][0][RTW89_WW][0][111] = 0,
+ [0][0][1][0][RTW89_WW][1][111] = 0,
+ [0][0][1][0][RTW89_WW][2][111] = 0,
+ [0][0][1][0][RTW89_WW][0][113] = 0,
+ [0][0][1][0][RTW89_WW][1][113] = 0,
+ [0][0][1][0][RTW89_WW][2][113] = 0,
+ [0][0][1][0][RTW89_WW][0][115] = 0,
+ [0][0][1][0][RTW89_WW][1][115] = 0,
+ [0][0][1][0][RTW89_WW][2][115] = 0,
+ [0][0][1][0][RTW89_WW][0][117] = 0,
+ [0][0][1][0][RTW89_WW][1][117] = 0,
+ [0][0][1][0][RTW89_WW][2][117] = 0,
+ [0][0][1][0][RTW89_WW][0][119] = 0,
+ [0][0][1][0][RTW89_WW][1][119] = 0,
+ [0][0][1][0][RTW89_WW][2][119] = 0,
+ [0][1][1][0][RTW89_WW][0][0] = -2,
+ [0][1][1][0][RTW89_WW][1][0] = -2,
+ [0][1][1][0][RTW89_WW][2][0] = 54,
+ [0][1][1][0][RTW89_WW][0][2] = -4,
+ [0][1][1][0][RTW89_WW][1][2] = -4,
+ [0][1][1][0][RTW89_WW][2][2] = 54,
+ [0][1][1][0][RTW89_WW][0][4] = -4,
+ [0][1][1][0][RTW89_WW][1][4] = -4,
+ [0][1][1][0][RTW89_WW][2][4] = 54,
+ [0][1][1][0][RTW89_WW][0][6] = -4,
+ [0][1][1][0][RTW89_WW][1][6] = -4,
+ [0][1][1][0][RTW89_WW][2][6] = 54,
+ [0][1][1][0][RTW89_WW][0][8] = -4,
+ [0][1][1][0][RTW89_WW][1][8] = -4,
+ [0][1][1][0][RTW89_WW][2][8] = 54,
+ [0][1][1][0][RTW89_WW][0][10] = -4,
+ [0][1][1][0][RTW89_WW][1][10] = -4,
+ [0][1][1][0][RTW89_WW][2][10] = 54,
+ [0][1][1][0][RTW89_WW][0][12] = -4,
+ [0][1][1][0][RTW89_WW][1][12] = -4,
+ [0][1][1][0][RTW89_WW][2][12] = 54,
+ [0][1][1][0][RTW89_WW][0][14] = -4,
+ [0][1][1][0][RTW89_WW][1][14] = -4,
+ [0][1][1][0][RTW89_WW][2][14] = 54,
+ [0][1][1][0][RTW89_WW][0][15] = -4,
+ [0][1][1][0][RTW89_WW][1][15] = -4,
+ [0][1][1][0][RTW89_WW][2][15] = 54,
+ [0][1][1][0][RTW89_WW][0][17] = -4,
+ [0][1][1][0][RTW89_WW][1][17] = -4,
+ [0][1][1][0][RTW89_WW][2][17] = 54,
+ [0][1][1][0][RTW89_WW][0][19] = -4,
+ [0][1][1][0][RTW89_WW][1][19] = -4,
+ [0][1][1][0][RTW89_WW][2][19] = 54,
+ [0][1][1][0][RTW89_WW][0][21] = -4,
+ [0][1][1][0][RTW89_WW][1][21] = -4,
+ [0][1][1][0][RTW89_WW][2][21] = 54,
+ [0][1][1][0][RTW89_WW][0][23] = -4,
+ [0][1][1][0][RTW89_WW][1][23] = -4,
+ [0][1][1][0][RTW89_WW][2][23] = 68,
+ [0][1][1][0][RTW89_WW][0][25] = -4,
+ [0][1][1][0][RTW89_WW][1][25] = -4,
+ [0][1][1][0][RTW89_WW][2][25] = 68,
+ [0][1][1][0][RTW89_WW][0][27] = -4,
+ [0][1][1][0][RTW89_WW][1][27] = -4,
+ [0][1][1][0][RTW89_WW][2][27] = 68,
+ [0][1][1][0][RTW89_WW][0][29] = -4,
+ [0][1][1][0][RTW89_WW][1][29] = -4,
+ [0][1][1][0][RTW89_WW][2][29] = 68,
+ [0][1][1][0][RTW89_WW][0][30] = -4,
+ [0][1][1][0][RTW89_WW][1][30] = -4,
+ [0][1][1][0][RTW89_WW][2][30] = 68,
+ [0][1][1][0][RTW89_WW][0][32] = -4,
+ [0][1][1][0][RTW89_WW][1][32] = -4,
+ [0][1][1][0][RTW89_WW][2][32] = 68,
+ [0][1][1][0][RTW89_WW][0][34] = -4,
+ [0][1][1][0][RTW89_WW][1][34] = -4,
+ [0][1][1][0][RTW89_WW][2][34] = 68,
+ [0][1][1][0][RTW89_WW][0][36] = -4,
+ [0][1][1][0][RTW89_WW][1][36] = -4,
+ [0][1][1][0][RTW89_WW][2][36] = 68,
+ [0][1][1][0][RTW89_WW][0][38] = -4,
+ [0][1][1][0][RTW89_WW][1][38] = -4,
+ [0][1][1][0][RTW89_WW][2][38] = 68,
+ [0][1][1][0][RTW89_WW][0][40] = -4,
+ [0][1][1][0][RTW89_WW][1][40] = -4,
+ [0][1][1][0][RTW89_WW][2][40] = 68,
+ [0][1][1][0][RTW89_WW][0][42] = -4,
+ [0][1][1][0][RTW89_WW][1][42] = -4,
+ [0][1][1][0][RTW89_WW][2][42] = 68,
+ [0][1][1][0][RTW89_WW][0][44] = -2,
+ [0][1][1][0][RTW89_WW][1][44] = -2,
+ [0][1][1][0][RTW89_WW][2][44] = 68,
+ [0][1][1][0][RTW89_WW][0][45] = -2,
+ [0][1][1][0][RTW89_WW][1][45] = -2,
+ [0][1][1][0][RTW89_WW][2][45] = 0,
+ [0][1][1][0][RTW89_WW][0][47] = -2,
+ [0][1][1][0][RTW89_WW][1][47] = -2,
+ [0][1][1][0][RTW89_WW][2][47] = 0,
+ [0][1][1][0][RTW89_WW][0][49] = -2,
+ [0][1][1][0][RTW89_WW][1][49] = -2,
+ [0][1][1][0][RTW89_WW][2][49] = 0,
+ [0][1][1][0][RTW89_WW][0][51] = -2,
+ [0][1][1][0][RTW89_WW][1][51] = -2,
+ [0][1][1][0][RTW89_WW][2][51] = 0,
+ [0][1][1][0][RTW89_WW][0][53] = -2,
+ [0][1][1][0][RTW89_WW][1][53] = -2,
+ [0][1][1][0][RTW89_WW][2][53] = 0,
+ [0][1][1][0][RTW89_WW][0][55] = -2,
+ [0][1][1][0][RTW89_WW][1][55] = -2,
+ [0][1][1][0][RTW89_WW][2][55] = 68,
+ [0][1][1][0][RTW89_WW][0][57] = -2,
+ [0][1][1][0][RTW89_WW][1][57] = -2,
+ [0][1][1][0][RTW89_WW][2][57] = 68,
+ [0][1][1][0][RTW89_WW][0][59] = -2,
+ [0][1][1][0][RTW89_WW][1][59] = -2,
+ [0][1][1][0][RTW89_WW][2][59] = 68,
+ [0][1][1][0][RTW89_WW][0][60] = -2,
+ [0][1][1][0][RTW89_WW][1][60] = -2,
+ [0][1][1][0][RTW89_WW][2][60] = 68,
+ [0][1][1][0][RTW89_WW][0][62] = -2,
+ [0][1][1][0][RTW89_WW][1][62] = -2,
+ [0][1][1][0][RTW89_WW][2][62] = 68,
+ [0][1][1][0][RTW89_WW][0][64] = -2,
+ [0][1][1][0][RTW89_WW][1][64] = -2,
+ [0][1][1][0][RTW89_WW][2][64] = 68,
+ [0][1][1][0][RTW89_WW][0][66] = -2,
+ [0][1][1][0][RTW89_WW][1][66] = -2,
+ [0][1][1][0][RTW89_WW][2][66] = 68,
+ [0][1][1][0][RTW89_WW][0][68] = -2,
+ [0][1][1][0][RTW89_WW][1][68] = -2,
+ [0][1][1][0][RTW89_WW][2][68] = 68,
+ [0][1][1][0][RTW89_WW][0][70] = -2,
+ [0][1][1][0][RTW89_WW][1][70] = -2,
+ [0][1][1][0][RTW89_WW][2][70] = 68,
+ [0][1][1][0][RTW89_WW][0][72] = -2,
+ [0][1][1][0][RTW89_WW][1][72] = -2,
+ [0][1][1][0][RTW89_WW][2][72] = 68,
+ [0][1][1][0][RTW89_WW][0][74] = -2,
+ [0][1][1][0][RTW89_WW][1][74] = -2,
+ [0][1][1][0][RTW89_WW][2][74] = 68,
+ [0][1][1][0][RTW89_WW][0][75] = -2,
+ [0][1][1][0][RTW89_WW][1][75] = -2,
+ [0][1][1][0][RTW89_WW][2][75] = 68,
+ [0][1][1][0][RTW89_WW][0][77] = -2,
+ [0][1][1][0][RTW89_WW][1][77] = -2,
+ [0][1][1][0][RTW89_WW][2][77] = 68,
+ [0][1][1][0][RTW89_WW][0][79] = -2,
+ [0][1][1][0][RTW89_WW][1][79] = -2,
+ [0][1][1][0][RTW89_WW][2][79] = 68,
+ [0][1][1][0][RTW89_WW][0][81] = -2,
+ [0][1][1][0][RTW89_WW][1][81] = -2,
+ [0][1][1][0][RTW89_WW][2][81] = 68,
+ [0][1][1][0][RTW89_WW][0][83] = -2,
+ [0][1][1][0][RTW89_WW][1][83] = -2,
+ [0][1][1][0][RTW89_WW][2][83] = 68,
+ [0][1][1][0][RTW89_WW][0][85] = -2,
+ [0][1][1][0][RTW89_WW][1][85] = -2,
+ [0][1][1][0][RTW89_WW][2][85] = 68,
+ [0][1][1][0][RTW89_WW][0][87] = -2,
+ [0][1][1][0][RTW89_WW][1][87] = -2,
+ [0][1][1][0][RTW89_WW][2][87] = 0,
+ [0][1][1][0][RTW89_WW][0][89] = -2,
+ [0][1][1][0][RTW89_WW][1][89] = -2,
+ [0][1][1][0][RTW89_WW][2][89] = 0,
+ [0][1][1][0][RTW89_WW][0][90] = -2,
+ [0][1][1][0][RTW89_WW][1][90] = -2,
+ [0][1][1][0][RTW89_WW][2][90] = 0,
+ [0][1][1][0][RTW89_WW][0][92] = -2,
+ [0][1][1][0][RTW89_WW][1][92] = -2,
+ [0][1][1][0][RTW89_WW][2][92] = 0,
+ [0][1][1][0][RTW89_WW][0][94] = -2,
+ [0][1][1][0][RTW89_WW][1][94] = -2,
+ [0][1][1][0][RTW89_WW][2][94] = 0,
+ [0][1][1][0][RTW89_WW][0][96] = -2,
+ [0][1][1][0][RTW89_WW][1][96] = -2,
+ [0][1][1][0][RTW89_WW][2][96] = 0,
+ [0][1][1][0][RTW89_WW][0][98] = -2,
+ [0][1][1][0][RTW89_WW][1][98] = -2,
+ [0][1][1][0][RTW89_WW][2][98] = 0,
+ [0][1][1][0][RTW89_WW][0][100] = -2,
+ [0][1][1][0][RTW89_WW][1][100] = -2,
+ [0][1][1][0][RTW89_WW][2][100] = 0,
+ [0][1][1][0][RTW89_WW][0][102] = -2,
+ [0][1][1][0][RTW89_WW][1][102] = -2,
+ [0][1][1][0][RTW89_WW][2][102] = 0,
+ [0][1][1][0][RTW89_WW][0][104] = -2,
+ [0][1][1][0][RTW89_WW][1][104] = -2,
+ [0][1][1][0][RTW89_WW][2][104] = 0,
+ [0][1][1][0][RTW89_WW][0][105] = -2,
+ [0][1][1][0][RTW89_WW][1][105] = -2,
+ [0][1][1][0][RTW89_WW][2][105] = 0,
+ [0][1][1][0][RTW89_WW][0][107] = 1,
+ [0][1][1][0][RTW89_WW][1][107] = 1,
+ [0][1][1][0][RTW89_WW][2][107] = 0,
+ [0][1][1][0][RTW89_WW][0][109] = 1,
+ [0][1][1][0][RTW89_WW][1][109] = 1,
+ [0][1][1][0][RTW89_WW][2][109] = 0,
+ [0][1][1][0][RTW89_WW][0][111] = 0,
+ [0][1][1][0][RTW89_WW][1][111] = 0,
+ [0][1][1][0][RTW89_WW][2][111] = 0,
+ [0][1][1][0][RTW89_WW][0][113] = 0,
+ [0][1][1][0][RTW89_WW][1][113] = 0,
+ [0][1][1][0][RTW89_WW][2][113] = 0,
+ [0][1][1][0][RTW89_WW][0][115] = 0,
+ [0][1][1][0][RTW89_WW][1][115] = 0,
+ [0][1][1][0][RTW89_WW][2][115] = 0,
+ [0][1][1][0][RTW89_WW][0][117] = 0,
+ [0][1][1][0][RTW89_WW][1][117] = 0,
+ [0][1][1][0][RTW89_WW][2][117] = 0,
+ [0][1][1][0][RTW89_WW][0][119] = 0,
+ [0][1][1][0][RTW89_WW][1][119] = 0,
+ [0][1][1][0][RTW89_WW][2][119] = 0,
+ [0][0][2][0][RTW89_WW][0][0] = 24,
+ [0][0][2][0][RTW89_WW][1][0] = 24,
+ [0][0][2][0][RTW89_WW][2][0] = 56,
+ [0][0][2][0][RTW89_WW][0][2] = 22,
+ [0][0][2][0][RTW89_WW][1][2] = 22,
+ [0][0][2][0][RTW89_WW][2][2] = 56,
+ [0][0][2][0][RTW89_WW][0][4] = 22,
+ [0][0][2][0][RTW89_WW][1][4] = 22,
+ [0][0][2][0][RTW89_WW][2][4] = 56,
+ [0][0][2][0][RTW89_WW][0][6] = 22,
+ [0][0][2][0][RTW89_WW][1][6] = 22,
+ [0][0][2][0][RTW89_WW][2][6] = 56,
+ [0][0][2][0][RTW89_WW][0][8] = 22,
+ [0][0][2][0][RTW89_WW][1][8] = 22,
+ [0][0][2][0][RTW89_WW][2][8] = 56,
+ [0][0][2][0][RTW89_WW][0][10] = 22,
+ [0][0][2][0][RTW89_WW][1][10] = 22,
+ [0][0][2][0][RTW89_WW][2][10] = 56,
+ [0][0][2][0][RTW89_WW][0][12] = 22,
+ [0][0][2][0][RTW89_WW][1][12] = 22,
+ [0][0][2][0][RTW89_WW][2][12] = 56,
+ [0][0][2][0][RTW89_WW][0][14] = 22,
+ [0][0][2][0][RTW89_WW][1][14] = 22,
+ [0][0][2][0][RTW89_WW][2][14] = 56,
+ [0][0][2][0][RTW89_WW][0][15] = 22,
+ [0][0][2][0][RTW89_WW][1][15] = 22,
+ [0][0][2][0][RTW89_WW][2][15] = 56,
+ [0][0][2][0][RTW89_WW][0][17] = 22,
+ [0][0][2][0][RTW89_WW][1][17] = 22,
+ [0][0][2][0][RTW89_WW][2][17] = 56,
+ [0][0][2][0][RTW89_WW][0][19] = 22,
+ [0][0][2][0][RTW89_WW][1][19] = 22,
+ [0][0][2][0][RTW89_WW][2][19] = 56,
+ [0][0][2][0][RTW89_WW][0][21] = 22,
+ [0][0][2][0][RTW89_WW][1][21] = 22,
+ [0][0][2][0][RTW89_WW][2][21] = 56,
+ [0][0][2][0][RTW89_WW][0][23] = 22,
+ [0][0][2][0][RTW89_WW][1][23] = 22,
+ [0][0][2][0][RTW89_WW][2][23] = 70,
+ [0][0][2][0][RTW89_WW][0][25] = 22,
+ [0][0][2][0][RTW89_WW][1][25] = 22,
+ [0][0][2][0][RTW89_WW][2][25] = 70,
+ [0][0][2][0][RTW89_WW][0][27] = 22,
+ [0][0][2][0][RTW89_WW][1][27] = 22,
+ [0][0][2][0][RTW89_WW][2][27] = 70,
+ [0][0][2][0][RTW89_WW][0][29] = 22,
+ [0][0][2][0][RTW89_WW][1][29] = 22,
+ [0][0][2][0][RTW89_WW][2][29] = 70,
+ [0][0][2][0][RTW89_WW][0][30] = 22,
+ [0][0][2][0][RTW89_WW][1][30] = 22,
+ [0][0][2][0][RTW89_WW][2][30] = 70,
+ [0][0][2][0][RTW89_WW][0][32] = 22,
+ [0][0][2][0][RTW89_WW][1][32] = 22,
+ [0][0][2][0][RTW89_WW][2][32] = 70,
+ [0][0][2][0][RTW89_WW][0][34] = 22,
+ [0][0][2][0][RTW89_WW][1][34] = 22,
+ [0][0][2][0][RTW89_WW][2][34] = 70,
+ [0][0][2][0][RTW89_WW][0][36] = 22,
+ [0][0][2][0][RTW89_WW][1][36] = 22,
+ [0][0][2][0][RTW89_WW][2][36] = 70,
+ [0][0][2][0][RTW89_WW][0][38] = 22,
+ [0][0][2][0][RTW89_WW][1][38] = 22,
+ [0][0][2][0][RTW89_WW][2][38] = 70,
+ [0][0][2][0][RTW89_WW][0][40] = 22,
+ [0][0][2][0][RTW89_WW][1][40] = 22,
+ [0][0][2][0][RTW89_WW][2][40] = 70,
+ [0][0][2][0][RTW89_WW][0][42] = 22,
+ [0][0][2][0][RTW89_WW][1][42] = 22,
+ [0][0][2][0][RTW89_WW][2][42] = 70,
+ [0][0][2][0][RTW89_WW][0][44] = 22,
+ [0][0][2][0][RTW89_WW][1][44] = 22,
+ [0][0][2][0][RTW89_WW][2][44] = 70,
+ [0][0][2][0][RTW89_WW][0][45] = 22,
+ [0][0][2][0][RTW89_WW][1][45] = 22,
+ [0][0][2][0][RTW89_WW][2][45] = 0,
+ [0][0][2][0][RTW89_WW][0][47] = 22,
+ [0][0][2][0][RTW89_WW][1][47] = 22,
+ [0][0][2][0][RTW89_WW][2][47] = 0,
+ [0][0][2][0][RTW89_WW][0][49] = 24,
+ [0][0][2][0][RTW89_WW][1][49] = 24,
+ [0][0][2][0][RTW89_WW][2][49] = 0,
+ [0][0][2][0][RTW89_WW][0][51] = 22,
+ [0][0][2][0][RTW89_WW][1][51] = 22,
+ [0][0][2][0][RTW89_WW][2][51] = 0,
+ [0][0][2][0][RTW89_WW][0][53] = 22,
+ [0][0][2][0][RTW89_WW][1][53] = 22,
+ [0][0][2][0][RTW89_WW][2][53] = 0,
+ [0][0][2][0][RTW89_WW][0][55] = 22,
+ [0][0][2][0][RTW89_WW][1][55] = 22,
+ [0][0][2][0][RTW89_WW][2][55] = 68,
+ [0][0][2][0][RTW89_WW][0][57] = 22,
+ [0][0][2][0][RTW89_WW][1][57] = 22,
+ [0][0][2][0][RTW89_WW][2][57] = 68,
+ [0][0][2][0][RTW89_WW][0][59] = 22,
+ [0][0][2][0][RTW89_WW][1][59] = 22,
+ [0][0][2][0][RTW89_WW][2][59] = 68,
+ [0][0][2][0][RTW89_WW][0][60] = 22,
+ [0][0][2][0][RTW89_WW][1][60] = 22,
+ [0][0][2][0][RTW89_WW][2][60] = 68,
+ [0][0][2][0][RTW89_WW][0][62] = 22,
+ [0][0][2][0][RTW89_WW][1][62] = 22,
+ [0][0][2][0][RTW89_WW][2][62] = 68,
+ [0][0][2][0][RTW89_WW][0][64] = 22,
+ [0][0][2][0][RTW89_WW][1][64] = 22,
+ [0][0][2][0][RTW89_WW][2][64] = 68,
+ [0][0][2][0][RTW89_WW][0][66] = 22,
+ [0][0][2][0][RTW89_WW][1][66] = 22,
+ [0][0][2][0][RTW89_WW][2][66] = 68,
+ [0][0][2][0][RTW89_WW][0][68] = 22,
+ [0][0][2][0][RTW89_WW][1][68] = 22,
+ [0][0][2][0][RTW89_WW][2][68] = 68,
+ [0][0][2][0][RTW89_WW][0][70] = 24,
+ [0][0][2][0][RTW89_WW][1][70] = 24,
+ [0][0][2][0][RTW89_WW][2][70] = 68,
+ [0][0][2][0][RTW89_WW][0][72] = 22,
+ [0][0][2][0][RTW89_WW][1][72] = 22,
+ [0][0][2][0][RTW89_WW][2][72] = 68,
+ [0][0][2][0][RTW89_WW][0][74] = 22,
+ [0][0][2][0][RTW89_WW][1][74] = 22,
+ [0][0][2][0][RTW89_WW][2][74] = 68,
+ [0][0][2][0][RTW89_WW][0][75] = 22,
+ [0][0][2][0][RTW89_WW][1][75] = 22,
+ [0][0][2][0][RTW89_WW][2][75] = 68,
+ [0][0][2][0][RTW89_WW][0][77] = 22,
+ [0][0][2][0][RTW89_WW][1][77] = 22,
+ [0][0][2][0][RTW89_WW][2][77] = 68,
+ [0][0][2][0][RTW89_WW][0][79] = 22,
+ [0][0][2][0][RTW89_WW][1][79] = 22,
+ [0][0][2][0][RTW89_WW][2][79] = 68,
+ [0][0][2][0][RTW89_WW][0][81] = 22,
+ [0][0][2][0][RTW89_WW][1][81] = 22,
+ [0][0][2][0][RTW89_WW][2][81] = 68,
+ [0][0][2][0][RTW89_WW][0][83] = 22,
+ [0][0][2][0][RTW89_WW][1][83] = 22,
+ [0][0][2][0][RTW89_WW][2][83] = 68,
+ [0][0][2][0][RTW89_WW][0][85] = 22,
+ [0][0][2][0][RTW89_WW][1][85] = 22,
+ [0][0][2][0][RTW89_WW][2][85] = 68,
+ [0][0][2][0][RTW89_WW][0][87] = 22,
+ [0][0][2][0][RTW89_WW][1][87] = 22,
+ [0][0][2][0][RTW89_WW][2][87] = 0,
+ [0][0][2][0][RTW89_WW][0][89] = 22,
+ [0][0][2][0][RTW89_WW][1][89] = 22,
+ [0][0][2][0][RTW89_WW][2][89] = 0,
+ [0][0][2][0][RTW89_WW][0][90] = 22,
+ [0][0][2][0][RTW89_WW][1][90] = 22,
+ [0][0][2][0][RTW89_WW][2][90] = 0,
+ [0][0][2][0][RTW89_WW][0][92] = 22,
+ [0][0][2][0][RTW89_WW][1][92] = 22,
+ [0][0][2][0][RTW89_WW][2][92] = 0,
+ [0][0][2][0][RTW89_WW][0][94] = 22,
+ [0][0][2][0][RTW89_WW][1][94] = 22,
+ [0][0][2][0][RTW89_WW][2][94] = 0,
+ [0][0][2][0][RTW89_WW][0][96] = 22,
+ [0][0][2][0][RTW89_WW][1][96] = 22,
+ [0][0][2][0][RTW89_WW][2][96] = 0,
+ [0][0][2][0][RTW89_WW][0][98] = 22,
+ [0][0][2][0][RTW89_WW][1][98] = 22,
+ [0][0][2][0][RTW89_WW][2][98] = 0,
+ [0][0][2][0][RTW89_WW][0][100] = 22,
+ [0][0][2][0][RTW89_WW][1][100] = 22,
+ [0][0][2][0][RTW89_WW][2][100] = 0,
+ [0][0][2][0][RTW89_WW][0][102] = 22,
+ [0][0][2][0][RTW89_WW][1][102] = 22,
+ [0][0][2][0][RTW89_WW][2][102] = 0,
+ [0][0][2][0][RTW89_WW][0][104] = 22,
+ [0][0][2][0][RTW89_WW][1][104] = 22,
+ [0][0][2][0][RTW89_WW][2][104] = 0,
+ [0][0][2][0][RTW89_WW][0][105] = 22,
+ [0][0][2][0][RTW89_WW][1][105] = 22,
+ [0][0][2][0][RTW89_WW][2][105] = 0,
+ [0][0][2][0][RTW89_WW][0][107] = 24,
+ [0][0][2][0][RTW89_WW][1][107] = 24,
+ [0][0][2][0][RTW89_WW][2][107] = 0,
+ [0][0][2][0][RTW89_WW][0][109] = 24,
+ [0][0][2][0][RTW89_WW][1][109] = 24,
+ [0][0][2][0][RTW89_WW][2][109] = 0,
+ [0][0][2][0][RTW89_WW][0][111] = 0,
+ [0][0][2][0][RTW89_WW][1][111] = 0,
+ [0][0][2][0][RTW89_WW][2][111] = 0,
+ [0][0][2][0][RTW89_WW][0][113] = 0,
+ [0][0][2][0][RTW89_WW][1][113] = 0,
+ [0][0][2][0][RTW89_WW][2][113] = 0,
+ [0][0][2][0][RTW89_WW][0][115] = 0,
+ [0][0][2][0][RTW89_WW][1][115] = 0,
+ [0][0][2][0][RTW89_WW][2][115] = 0,
+ [0][0][2][0][RTW89_WW][0][117] = 0,
+ [0][0][2][0][RTW89_WW][1][117] = 0,
+ [0][0][2][0][RTW89_WW][2][117] = 0,
+ [0][0][2][0][RTW89_WW][0][119] = 0,
+ [0][0][2][0][RTW89_WW][1][119] = 0,
+ [0][0][2][0][RTW89_WW][2][119] = 0,
+ [0][1][2][0][RTW89_WW][0][0] = -2,
+ [0][1][2][0][RTW89_WW][1][0] = -2,
+ [0][1][2][0][RTW89_WW][2][0] = 54,
+ [0][1][2][0][RTW89_WW][0][2] = -4,
+ [0][1][2][0][RTW89_WW][1][2] = -4,
+ [0][1][2][0][RTW89_WW][2][2] = 54,
+ [0][1][2][0][RTW89_WW][0][4] = -4,
+ [0][1][2][0][RTW89_WW][1][4] = -4,
+ [0][1][2][0][RTW89_WW][2][4] = 54,
+ [0][1][2][0][RTW89_WW][0][6] = -4,
+ [0][1][2][0][RTW89_WW][1][6] = -4,
+ [0][1][2][0][RTW89_WW][2][6] = 54,
+ [0][1][2][0][RTW89_WW][0][8] = -4,
+ [0][1][2][0][RTW89_WW][1][8] = -4,
+ [0][1][2][0][RTW89_WW][2][8] = 54,
+ [0][1][2][0][RTW89_WW][0][10] = -4,
+ [0][1][2][0][RTW89_WW][1][10] = -4,
+ [0][1][2][0][RTW89_WW][2][10] = 54,
+ [0][1][2][0][RTW89_WW][0][12] = -4,
+ [0][1][2][0][RTW89_WW][1][12] = -4,
+ [0][1][2][0][RTW89_WW][2][12] = 54,
+ [0][1][2][0][RTW89_WW][0][14] = -4,
+ [0][1][2][0][RTW89_WW][1][14] = -4,
+ [0][1][2][0][RTW89_WW][2][14] = 54,
+ [0][1][2][0][RTW89_WW][0][15] = -4,
+ [0][1][2][0][RTW89_WW][1][15] = -4,
+ [0][1][2][0][RTW89_WW][2][15] = 54,
+ [0][1][2][0][RTW89_WW][0][17] = -4,
+ [0][1][2][0][RTW89_WW][1][17] = -4,
+ [0][1][2][0][RTW89_WW][2][17] = 54,
+ [0][1][2][0][RTW89_WW][0][19] = -4,
+ [0][1][2][0][RTW89_WW][1][19] = -4,
+ [0][1][2][0][RTW89_WW][2][19] = 54,
+ [0][1][2][0][RTW89_WW][0][21] = -4,
+ [0][1][2][0][RTW89_WW][1][21] = -4,
+ [0][1][2][0][RTW89_WW][2][21] = 54,
+ [0][1][2][0][RTW89_WW][0][23] = -4,
+ [0][1][2][0][RTW89_WW][1][23] = -4,
+ [0][1][2][0][RTW89_WW][2][23] = 68,
+ [0][1][2][0][RTW89_WW][0][25] = -4,
+ [0][1][2][0][RTW89_WW][1][25] = -4,
+ [0][1][2][0][RTW89_WW][2][25] = 68,
+ [0][1][2][0][RTW89_WW][0][27] = -4,
+ [0][1][2][0][RTW89_WW][1][27] = -4,
+ [0][1][2][0][RTW89_WW][2][27] = 68,
+ [0][1][2][0][RTW89_WW][0][29] = -4,
+ [0][1][2][0][RTW89_WW][1][29] = -4,
+ [0][1][2][0][RTW89_WW][2][29] = 68,
+ [0][1][2][0][RTW89_WW][0][30] = -4,
+ [0][1][2][0][RTW89_WW][1][30] = -4,
+ [0][1][2][0][RTW89_WW][2][30] = 68,
+ [0][1][2][0][RTW89_WW][0][32] = -4,
+ [0][1][2][0][RTW89_WW][1][32] = -4,
+ [0][1][2][0][RTW89_WW][2][32] = 68,
+ [0][1][2][0][RTW89_WW][0][34] = -4,
+ [0][1][2][0][RTW89_WW][1][34] = -4,
+ [0][1][2][0][RTW89_WW][2][34] = 68,
+ [0][1][2][0][RTW89_WW][0][36] = -4,
+ [0][1][2][0][RTW89_WW][1][36] = -4,
+ [0][1][2][0][RTW89_WW][2][36] = 68,
+ [0][1][2][0][RTW89_WW][0][38] = -4,
+ [0][1][2][0][RTW89_WW][1][38] = -4,
+ [0][1][2][0][RTW89_WW][2][38] = 68,
+ [0][1][2][0][RTW89_WW][0][40] = -4,
+ [0][1][2][0][RTW89_WW][1][40] = -4,
+ [0][1][2][0][RTW89_WW][2][40] = 68,
+ [0][1][2][0][RTW89_WW][0][42] = -4,
+ [0][1][2][0][RTW89_WW][1][42] = -4,
+ [0][1][2][0][RTW89_WW][2][42] = 68,
+ [0][1][2][0][RTW89_WW][0][44] = -2,
+ [0][1][2][0][RTW89_WW][1][44] = -2,
+ [0][1][2][0][RTW89_WW][2][44] = 68,
+ [0][1][2][0][RTW89_WW][0][45] = -2,
+ [0][1][2][0][RTW89_WW][1][45] = -2,
+ [0][1][2][0][RTW89_WW][2][45] = 0,
+ [0][1][2][0][RTW89_WW][0][47] = -2,
+ [0][1][2][0][RTW89_WW][1][47] = -2,
+ [0][1][2][0][RTW89_WW][2][47] = 0,
+ [0][1][2][0][RTW89_WW][0][49] = -2,
+ [0][1][2][0][RTW89_WW][1][49] = -2,
+ [0][1][2][0][RTW89_WW][2][49] = 0,
+ [0][1][2][0][RTW89_WW][0][51] = -2,
+ [0][1][2][0][RTW89_WW][1][51] = -2,
+ [0][1][2][0][RTW89_WW][2][51] = 0,
+ [0][1][2][0][RTW89_WW][0][53] = -2,
+ [0][1][2][0][RTW89_WW][1][53] = -2,
+ [0][1][2][0][RTW89_WW][2][53] = 0,
+ [0][1][2][0][RTW89_WW][0][55] = -2,
+ [0][1][2][0][RTW89_WW][1][55] = -2,
+ [0][1][2][0][RTW89_WW][2][55] = 68,
+ [0][1][2][0][RTW89_WW][0][57] = -2,
+ [0][1][2][0][RTW89_WW][1][57] = -2,
+ [0][1][2][0][RTW89_WW][2][57] = 68,
+ [0][1][2][0][RTW89_WW][0][59] = -2,
+ [0][1][2][0][RTW89_WW][1][59] = -2,
+ [0][1][2][0][RTW89_WW][2][59] = 68,
+ [0][1][2][0][RTW89_WW][0][60] = -2,
+ [0][1][2][0][RTW89_WW][1][60] = -2,
+ [0][1][2][0][RTW89_WW][2][60] = 68,
+ [0][1][2][0][RTW89_WW][0][62] = -2,
+ [0][1][2][0][RTW89_WW][1][62] = -2,
+ [0][1][2][0][RTW89_WW][2][62] = 68,
+ [0][1][2][0][RTW89_WW][0][64] = -2,
+ [0][1][2][0][RTW89_WW][1][64] = -2,
+ [0][1][2][0][RTW89_WW][2][64] = 68,
+ [0][1][2][0][RTW89_WW][0][66] = -2,
+ [0][1][2][0][RTW89_WW][1][66] = -2,
+ [0][1][2][0][RTW89_WW][2][66] = 68,
+ [0][1][2][0][RTW89_WW][0][68] = -2,
+ [0][1][2][0][RTW89_WW][1][68] = -2,
+ [0][1][2][0][RTW89_WW][2][68] = 68,
+ [0][1][2][0][RTW89_WW][0][70] = -2,
+ [0][1][2][0][RTW89_WW][1][70] = -2,
+ [0][1][2][0][RTW89_WW][2][70] = 68,
+ [0][1][2][0][RTW89_WW][0][72] = -2,
+ [0][1][2][0][RTW89_WW][1][72] = -2,
+ [0][1][2][0][RTW89_WW][2][72] = 68,
+ [0][1][2][0][RTW89_WW][0][74] = -2,
+ [0][1][2][0][RTW89_WW][1][74] = -2,
+ [0][1][2][0][RTW89_WW][2][74] = 68,
+ [0][1][2][0][RTW89_WW][0][75] = -2,
+ [0][1][2][0][RTW89_WW][1][75] = -2,
+ [0][1][2][0][RTW89_WW][2][75] = 68,
+ [0][1][2][0][RTW89_WW][0][77] = -2,
+ [0][1][2][0][RTW89_WW][1][77] = -2,
+ [0][1][2][0][RTW89_WW][2][77] = 68,
+ [0][1][2][0][RTW89_WW][0][79] = -2,
+ [0][1][2][0][RTW89_WW][1][79] = -2,
+ [0][1][2][0][RTW89_WW][2][79] = 68,
+ [0][1][2][0][RTW89_WW][0][81] = -2,
+ [0][1][2][0][RTW89_WW][1][81] = -2,
+ [0][1][2][0][RTW89_WW][2][81] = 68,
+ [0][1][2][0][RTW89_WW][0][83] = -2,
+ [0][1][2][0][RTW89_WW][1][83] = -2,
+ [0][1][2][0][RTW89_WW][2][83] = 68,
+ [0][1][2][0][RTW89_WW][0][85] = -2,
+ [0][1][2][0][RTW89_WW][1][85] = -2,
+ [0][1][2][0][RTW89_WW][2][85] = 68,
+ [0][1][2][0][RTW89_WW][0][87] = -2,
+ [0][1][2][0][RTW89_WW][1][87] = -2,
+ [0][1][2][0][RTW89_WW][2][87] = 0,
+ [0][1][2][0][RTW89_WW][0][89] = -2,
+ [0][1][2][0][RTW89_WW][1][89] = -2,
+ [0][1][2][0][RTW89_WW][2][89] = 0,
+ [0][1][2][0][RTW89_WW][0][90] = -2,
+ [0][1][2][0][RTW89_WW][1][90] = -2,
+ [0][1][2][0][RTW89_WW][2][90] = 0,
+ [0][1][2][0][RTW89_WW][0][92] = -2,
+ [0][1][2][0][RTW89_WW][1][92] = -2,
+ [0][1][2][0][RTW89_WW][2][92] = 0,
+ [0][1][2][0][RTW89_WW][0][94] = -2,
+ [0][1][2][0][RTW89_WW][1][94] = -2,
+ [0][1][2][0][RTW89_WW][2][94] = 0,
+ [0][1][2][0][RTW89_WW][0][96] = -2,
+ [0][1][2][0][RTW89_WW][1][96] = -2,
+ [0][1][2][0][RTW89_WW][2][96] = 0,
+ [0][1][2][0][RTW89_WW][0][98] = -2,
+ [0][1][2][0][RTW89_WW][1][98] = -2,
+ [0][1][2][0][RTW89_WW][2][98] = 0,
+ [0][1][2][0][RTW89_WW][0][100] = -2,
+ [0][1][2][0][RTW89_WW][1][100] = -2,
+ [0][1][2][0][RTW89_WW][2][100] = 0,
+ [0][1][2][0][RTW89_WW][0][102] = -2,
+ [0][1][2][0][RTW89_WW][1][102] = -2,
+ [0][1][2][0][RTW89_WW][2][102] = 0,
+ [0][1][2][0][RTW89_WW][0][104] = -2,
+ [0][1][2][0][RTW89_WW][1][104] = -2,
+ [0][1][2][0][RTW89_WW][2][104] = 0,
+ [0][1][2][0][RTW89_WW][0][105] = -2,
+ [0][1][2][0][RTW89_WW][1][105] = -2,
+ [0][1][2][0][RTW89_WW][2][105] = 0,
+ [0][1][2][0][RTW89_WW][0][107] = 1,
+ [0][1][2][0][RTW89_WW][1][107] = 1,
+ [0][1][2][0][RTW89_WW][2][107] = 0,
+ [0][1][2][0][RTW89_WW][0][109] = 1,
+ [0][1][2][0][RTW89_WW][1][109] = 1,
+ [0][1][2][0][RTW89_WW][2][109] = 0,
+ [0][1][2][0][RTW89_WW][0][111] = 0,
+ [0][1][2][0][RTW89_WW][1][111] = 0,
+ [0][1][2][0][RTW89_WW][2][111] = 0,
+ [0][1][2][0][RTW89_WW][0][113] = 0,
+ [0][1][2][0][RTW89_WW][1][113] = 0,
+ [0][1][2][0][RTW89_WW][2][113] = 0,
+ [0][1][2][0][RTW89_WW][0][115] = 0,
+ [0][1][2][0][RTW89_WW][1][115] = 0,
+ [0][1][2][0][RTW89_WW][2][115] = 0,
+ [0][1][2][0][RTW89_WW][0][117] = 0,
+ [0][1][2][0][RTW89_WW][1][117] = 0,
+ [0][1][2][0][RTW89_WW][2][117] = 0,
+ [0][1][2][0][RTW89_WW][0][119] = 0,
+ [0][1][2][0][RTW89_WW][1][119] = 0,
+ [0][1][2][0][RTW89_WW][2][119] = 0,
+ [0][1][2][1][RTW89_WW][0][0] = -2,
+ [0][1][2][1][RTW89_WW][1][0] = -2,
+ [0][1][2][1][RTW89_WW][2][0] = 54,
+ [0][1][2][1][RTW89_WW][0][2] = -4,
+ [0][1][2][1][RTW89_WW][1][2] = -4,
+ [0][1][2][1][RTW89_WW][2][2] = 54,
+ [0][1][2][1][RTW89_WW][0][4] = -4,
+ [0][1][2][1][RTW89_WW][1][4] = -4,
+ [0][1][2][1][RTW89_WW][2][4] = 54,
+ [0][1][2][1][RTW89_WW][0][6] = -4,
+ [0][1][2][1][RTW89_WW][1][6] = -4,
+ [0][1][2][1][RTW89_WW][2][6] = 54,
+ [0][1][2][1][RTW89_WW][0][8] = -4,
+ [0][1][2][1][RTW89_WW][1][8] = -4,
+ [0][1][2][1][RTW89_WW][2][8] = 54,
+ [0][1][2][1][RTW89_WW][0][10] = -4,
+ [0][1][2][1][RTW89_WW][1][10] = -4,
+ [0][1][2][1][RTW89_WW][2][10] = 54,
+ [0][1][2][1][RTW89_WW][0][12] = -4,
+ [0][1][2][1][RTW89_WW][1][12] = -4,
+ [0][1][2][1][RTW89_WW][2][12] = 54,
+ [0][1][2][1][RTW89_WW][0][14] = -4,
+ [0][1][2][1][RTW89_WW][1][14] = -4,
+ [0][1][2][1][RTW89_WW][2][14] = 54,
+ [0][1][2][1][RTW89_WW][0][15] = -4,
+ [0][1][2][1][RTW89_WW][1][15] = -4,
+ [0][1][2][1][RTW89_WW][2][15] = 54,
+ [0][1][2][1][RTW89_WW][0][17] = -4,
+ [0][1][2][1][RTW89_WW][1][17] = -4,
+ [0][1][2][1][RTW89_WW][2][17] = 54,
+ [0][1][2][1][RTW89_WW][0][19] = -4,
+ [0][1][2][1][RTW89_WW][1][19] = -4,
+ [0][1][2][1][RTW89_WW][2][19] = 54,
+ [0][1][2][1][RTW89_WW][0][21] = -4,
+ [0][1][2][1][RTW89_WW][1][21] = -4,
+ [0][1][2][1][RTW89_WW][2][21] = 54,
+ [0][1][2][1][RTW89_WW][0][23] = -4,
+ [0][1][2][1][RTW89_WW][1][23] = -4,
+ [0][1][2][1][RTW89_WW][2][23] = 68,
+ [0][1][2][1][RTW89_WW][0][25] = -4,
+ [0][1][2][1][RTW89_WW][1][25] = -4,
+ [0][1][2][1][RTW89_WW][2][25] = 68,
+ [0][1][2][1][RTW89_WW][0][27] = -4,
+ [0][1][2][1][RTW89_WW][1][27] = -4,
+ [0][1][2][1][RTW89_WW][2][27] = 68,
+ [0][1][2][1][RTW89_WW][0][29] = -4,
+ [0][1][2][1][RTW89_WW][1][29] = -4,
+ [0][1][2][1][RTW89_WW][2][29] = 68,
+ [0][1][2][1][RTW89_WW][0][30] = -4,
+ [0][1][2][1][RTW89_WW][1][30] = -4,
+ [0][1][2][1][RTW89_WW][2][30] = 68,
+ [0][1][2][1][RTW89_WW][0][32] = -4,
+ [0][1][2][1][RTW89_WW][1][32] = -4,
+ [0][1][2][1][RTW89_WW][2][32] = 68,
+ [0][1][2][1][RTW89_WW][0][34] = -4,
+ [0][1][2][1][RTW89_WW][1][34] = -4,
+ [0][1][2][1][RTW89_WW][2][34] = 68,
+ [0][1][2][1][RTW89_WW][0][36] = -4,
+ [0][1][2][1][RTW89_WW][1][36] = -4,
+ [0][1][2][1][RTW89_WW][2][36] = 68,
+ [0][1][2][1][RTW89_WW][0][38] = -4,
+ [0][1][2][1][RTW89_WW][1][38] = -4,
+ [0][1][2][1][RTW89_WW][2][38] = 68,
+ [0][1][2][1][RTW89_WW][0][40] = -4,
+ [0][1][2][1][RTW89_WW][1][40] = -4,
+ [0][1][2][1][RTW89_WW][2][40] = 68,
+ [0][1][2][1][RTW89_WW][0][42] = -4,
+ [0][1][2][1][RTW89_WW][1][42] = -4,
+ [0][1][2][1][RTW89_WW][2][42] = 68,
+ [0][1][2][1][RTW89_WW][0][44] = -2,
+ [0][1][2][1][RTW89_WW][1][44] = -2,
+ [0][1][2][1][RTW89_WW][2][44] = 68,
+ [0][1][2][1][RTW89_WW][0][45] = -2,
+ [0][1][2][1][RTW89_WW][1][45] = -2,
+ [0][1][2][1][RTW89_WW][2][45] = 0,
+ [0][1][2][1][RTW89_WW][0][47] = -2,
+ [0][1][2][1][RTW89_WW][1][47] = -2,
+ [0][1][2][1][RTW89_WW][2][47] = 0,
+ [0][1][2][1][RTW89_WW][0][49] = -2,
+ [0][1][2][1][RTW89_WW][1][49] = -2,
+ [0][1][2][1][RTW89_WW][2][49] = 0,
+ [0][1][2][1][RTW89_WW][0][51] = -2,
+ [0][1][2][1][RTW89_WW][1][51] = -2,
+ [0][1][2][1][RTW89_WW][2][51] = 0,
+ [0][1][2][1][RTW89_WW][0][53] = -2,
+ [0][1][2][1][RTW89_WW][1][53] = -2,
+ [0][1][2][1][RTW89_WW][2][53] = 0,
+ [0][1][2][1][RTW89_WW][0][55] = -2,
+ [0][1][2][1][RTW89_WW][1][55] = -2,
+ [0][1][2][1][RTW89_WW][2][55] = 68,
+ [0][1][2][1][RTW89_WW][0][57] = -2,
+ [0][1][2][1][RTW89_WW][1][57] = -2,
+ [0][1][2][1][RTW89_WW][2][57] = 68,
+ [0][1][2][1][RTW89_WW][0][59] = -2,
+ [0][1][2][1][RTW89_WW][1][59] = -2,
+ [0][1][2][1][RTW89_WW][2][59] = 68,
+ [0][1][2][1][RTW89_WW][0][60] = -2,
+ [0][1][2][1][RTW89_WW][1][60] = -2,
+ [0][1][2][1][RTW89_WW][2][60] = 68,
+ [0][1][2][1][RTW89_WW][0][62] = -2,
+ [0][1][2][1][RTW89_WW][1][62] = -2,
+ [0][1][2][1][RTW89_WW][2][62] = 68,
+ [0][1][2][1][RTW89_WW][0][64] = -2,
+ [0][1][2][1][RTW89_WW][1][64] = -2,
+ [0][1][2][1][RTW89_WW][2][64] = 68,
+ [0][1][2][1][RTW89_WW][0][66] = -2,
+ [0][1][2][1][RTW89_WW][1][66] = -2,
+ [0][1][2][1][RTW89_WW][2][66] = 68,
+ [0][1][2][1][RTW89_WW][0][68] = -2,
+ [0][1][2][1][RTW89_WW][1][68] = -2,
+ [0][1][2][1][RTW89_WW][2][68] = 68,
+ [0][1][2][1][RTW89_WW][0][70] = -2,
+ [0][1][2][1][RTW89_WW][1][70] = -2,
+ [0][1][2][1][RTW89_WW][2][70] = 68,
+ [0][1][2][1][RTW89_WW][0][72] = -2,
+ [0][1][2][1][RTW89_WW][1][72] = -2,
+ [0][1][2][1][RTW89_WW][2][72] = 68,
+ [0][1][2][1][RTW89_WW][0][74] = -2,
+ [0][1][2][1][RTW89_WW][1][74] = -2,
+ [0][1][2][1][RTW89_WW][2][74] = 68,
+ [0][1][2][1][RTW89_WW][0][75] = -2,
+ [0][1][2][1][RTW89_WW][1][75] = -2,
+ [0][1][2][1][RTW89_WW][2][75] = 68,
+ [0][1][2][1][RTW89_WW][0][77] = -2,
+ [0][1][2][1][RTW89_WW][1][77] = -2,
+ [0][1][2][1][RTW89_WW][2][77] = 68,
+ [0][1][2][1][RTW89_WW][0][79] = -2,
+ [0][1][2][1][RTW89_WW][1][79] = -2,
+ [0][1][2][1][RTW89_WW][2][79] = 68,
+ [0][1][2][1][RTW89_WW][0][81] = -2,
+ [0][1][2][1][RTW89_WW][1][81] = -2,
+ [0][1][2][1][RTW89_WW][2][81] = 68,
+ [0][1][2][1][RTW89_WW][0][83] = -2,
+ [0][1][2][1][RTW89_WW][1][83] = -2,
+ [0][1][2][1][RTW89_WW][2][83] = 68,
+ [0][1][2][1][RTW89_WW][0][85] = -2,
+ [0][1][2][1][RTW89_WW][1][85] = -2,
+ [0][1][2][1][RTW89_WW][2][85] = 68,
+ [0][1][2][1][RTW89_WW][0][87] = -2,
+ [0][1][2][1][RTW89_WW][1][87] = -2,
+ [0][1][2][1][RTW89_WW][2][87] = 0,
+ [0][1][2][1][RTW89_WW][0][89] = -2,
+ [0][1][2][1][RTW89_WW][1][89] = -2,
+ [0][1][2][1][RTW89_WW][2][89] = 0,
+ [0][1][2][1][RTW89_WW][0][90] = -2,
+ [0][1][2][1][RTW89_WW][1][90] = -2,
+ [0][1][2][1][RTW89_WW][2][90] = 0,
+ [0][1][2][1][RTW89_WW][0][92] = -2,
+ [0][1][2][1][RTW89_WW][1][92] = -2,
+ [0][1][2][1][RTW89_WW][2][92] = 0,
+ [0][1][2][1][RTW89_WW][0][94] = -2,
+ [0][1][2][1][RTW89_WW][1][94] = -2,
+ [0][1][2][1][RTW89_WW][2][94] = 0,
+ [0][1][2][1][RTW89_WW][0][96] = -2,
+ [0][1][2][1][RTW89_WW][1][96] = -2,
+ [0][1][2][1][RTW89_WW][2][96] = 0,
+ [0][1][2][1][RTW89_WW][0][98] = -2,
+ [0][1][2][1][RTW89_WW][1][98] = -2,
+ [0][1][2][1][RTW89_WW][2][98] = 0,
+ [0][1][2][1][RTW89_WW][0][100] = -2,
+ [0][1][2][1][RTW89_WW][1][100] = -2,
+ [0][1][2][1][RTW89_WW][2][100] = 0,
+ [0][1][2][1][RTW89_WW][0][102] = -2,
+ [0][1][2][1][RTW89_WW][1][102] = -2,
+ [0][1][2][1][RTW89_WW][2][102] = 0,
+ [0][1][2][1][RTW89_WW][0][104] = -2,
+ [0][1][2][1][RTW89_WW][1][104] = -2,
+ [0][1][2][1][RTW89_WW][2][104] = 0,
+ [0][1][2][1][RTW89_WW][0][105] = -2,
+ [0][1][2][1][RTW89_WW][1][105] = -2,
+ [0][1][2][1][RTW89_WW][2][105] = 0,
+ [0][1][2][1][RTW89_WW][0][107] = 1,
+ [0][1][2][1][RTW89_WW][1][107] = 1,
+ [0][1][2][1][RTW89_WW][2][107] = 0,
+ [0][1][2][1][RTW89_WW][0][109] = 1,
+ [0][1][2][1][RTW89_WW][1][109] = 1,
+ [0][1][2][1][RTW89_WW][2][109] = 0,
+ [0][1][2][1][RTW89_WW][0][111] = 0,
+ [0][1][2][1][RTW89_WW][1][111] = 0,
+ [0][1][2][1][RTW89_WW][2][111] = 0,
+ [0][1][2][1][RTW89_WW][0][113] = 0,
+ [0][1][2][1][RTW89_WW][1][113] = 0,
+ [0][1][2][1][RTW89_WW][2][113] = 0,
+ [0][1][2][1][RTW89_WW][0][115] = 0,
+ [0][1][2][1][RTW89_WW][1][115] = 0,
+ [0][1][2][1][RTW89_WW][2][115] = 0,
+ [0][1][2][1][RTW89_WW][0][117] = 0,
+ [0][1][2][1][RTW89_WW][1][117] = 0,
+ [0][1][2][1][RTW89_WW][2][117] = 0,
+ [0][1][2][1][RTW89_WW][0][119] = 0,
+ [0][1][2][1][RTW89_WW][1][119] = 0,
+ [0][1][2][1][RTW89_WW][2][119] = 0,
+ [1][0][2][0][RTW89_WW][0][1] = 24,
+ [1][0][2][0][RTW89_WW][1][1] = 34,
+ [1][0][2][0][RTW89_WW][2][1] = 70,
+ [1][0][2][0][RTW89_WW][0][5] = 24,
+ [1][0][2][0][RTW89_WW][1][5] = 34,
+ [1][0][2][0][RTW89_WW][2][5] = 70,
+ [1][0][2][0][RTW89_WW][0][9] = 24,
+ [1][0][2][0][RTW89_WW][1][9] = 34,
+ [1][0][2][0][RTW89_WW][2][9] = 70,
+ [1][0][2][0][RTW89_WW][0][13] = 24,
+ [1][0][2][0][RTW89_WW][1][13] = 34,
+ [1][0][2][0][RTW89_WW][2][13] = 70,
+ [1][0][2][0][RTW89_WW][0][16] = 24,
+ [1][0][2][0][RTW89_WW][1][16] = 34,
+ [1][0][2][0][RTW89_WW][2][16] = 70,
+ [1][0][2][0][RTW89_WW][0][20] = 24,
+ [1][0][2][0][RTW89_WW][1][20] = 34,
+ [1][0][2][0][RTW89_WW][2][20] = 70,
+ [1][0][2][0][RTW89_WW][0][24] = 26,
+ [1][0][2][0][RTW89_WW][1][24] = 36,
+ [1][0][2][0][RTW89_WW][2][24] = 70,
+ [1][0][2][0][RTW89_WW][0][28] = 26,
+ [1][0][2][0][RTW89_WW][1][28] = 34,
+ [1][0][2][0][RTW89_WW][2][28] = 70,
+ [1][0][2][0][RTW89_WW][0][31] = 26,
+ [1][0][2][0][RTW89_WW][1][31] = 34,
+ [1][0][2][0][RTW89_WW][2][31] = 70,
+ [1][0][2][0][RTW89_WW][0][35] = 26,
+ [1][0][2][0][RTW89_WW][1][35] = 34,
+ [1][0][2][0][RTW89_WW][2][35] = 70,
+ [1][0][2][0][RTW89_WW][0][39] = 26,
+ [1][0][2][0][RTW89_WW][1][39] = 34,
+ [1][0][2][0][RTW89_WW][2][39] = 70,
+ [1][0][2][0][RTW89_WW][0][43] = 26,
+ [1][0][2][0][RTW89_WW][1][43] = 34,
+ [1][0][2][0][RTW89_WW][2][43] = 70,
+ [1][0][2][0][RTW89_WW][0][46] = 34,
+ [1][0][2][0][RTW89_WW][1][46] = 34,
+ [1][0][2][0][RTW89_WW][2][46] = 0,
+ [1][0][2][0][RTW89_WW][0][50] = 34,
+ [1][0][2][0][RTW89_WW][1][50] = 34,
+ [1][0][2][0][RTW89_WW][2][50] = 0,
+ [1][0][2][0][RTW89_WW][0][54] = 36,
+ [1][0][2][0][RTW89_WW][1][54] = 36,
+ [1][0][2][0][RTW89_WW][2][54] = 0,
+ [1][0][2][0][RTW89_WW][0][58] = 36,
+ [1][0][2][0][RTW89_WW][1][58] = 36,
+ [1][0][2][0][RTW89_WW][2][58] = 66,
+ [1][0][2][0][RTW89_WW][0][61] = 34,
+ [1][0][2][0][RTW89_WW][1][61] = 34,
+ [1][0][2][0][RTW89_WW][2][61] = 66,
+ [1][0][2][0][RTW89_WW][0][65] = 34,
+ [1][0][2][0][RTW89_WW][1][65] = 34,
+ [1][0][2][0][RTW89_WW][2][65] = 66,
+ [1][0][2][0][RTW89_WW][0][69] = 34,
+ [1][0][2][0][RTW89_WW][1][69] = 34,
+ [1][0][2][0][RTW89_WW][2][69] = 66,
+ [1][0][2][0][RTW89_WW][0][73] = 34,
+ [1][0][2][0][RTW89_WW][1][73] = 34,
+ [1][0][2][0][RTW89_WW][2][73] = 66,
+ [1][0][2][0][RTW89_WW][0][76] = 34,
+ [1][0][2][0][RTW89_WW][1][76] = 34,
+ [1][0][2][0][RTW89_WW][2][76] = 66,
+ [1][0][2][0][RTW89_WW][0][80] = 34,
+ [1][0][2][0][RTW89_WW][1][80] = 34,
+ [1][0][2][0][RTW89_WW][2][80] = 66,
+ [1][0][2][0][RTW89_WW][0][84] = 34,
+ [1][0][2][0][RTW89_WW][1][84] = 34,
+ [1][0][2][0][RTW89_WW][2][84] = 66,
+ [1][0][2][0][RTW89_WW][0][88] = 34,
+ [1][0][2][0][RTW89_WW][1][88] = 34,
+ [1][0][2][0][RTW89_WW][2][88] = 0,
+ [1][0][2][0][RTW89_WW][0][91] = 36,
+ [1][0][2][0][RTW89_WW][1][91] = 36,
+ [1][0][2][0][RTW89_WW][2][91] = 0,
+ [1][0][2][0][RTW89_WW][0][95] = 34,
+ [1][0][2][0][RTW89_WW][1][95] = 34,
+ [1][0][2][0][RTW89_WW][2][95] = 0,
+ [1][0][2][0][RTW89_WW][0][99] = 34,
+ [1][0][2][0][RTW89_WW][1][99] = 34,
+ [1][0][2][0][RTW89_WW][2][99] = 0,
+ [1][0][2][0][RTW89_WW][0][103] = 34,
+ [1][0][2][0][RTW89_WW][1][103] = 34,
+ [1][0][2][0][RTW89_WW][2][103] = 0,
+ [1][0][2][0][RTW89_WW][0][106] = 36,
+ [1][0][2][0][RTW89_WW][1][106] = 36,
+ [1][0][2][0][RTW89_WW][2][106] = 0,
+ [1][0][2][0][RTW89_WW][0][110] = 0,
+ [1][0][2][0][RTW89_WW][1][110] = 0,
+ [1][0][2][0][RTW89_WW][2][110] = 0,
+ [1][0][2][0][RTW89_WW][0][114] = 0,
+ [1][0][2][0][RTW89_WW][1][114] = 0,
+ [1][0][2][0][RTW89_WW][2][114] = 0,
+ [1][0][2][0][RTW89_WW][0][118] = 0,
+ [1][0][2][0][RTW89_WW][1][118] = 0,
+ [1][0][2][0][RTW89_WW][2][118] = 0,
+ [1][1][2][0][RTW89_WW][0][1] = 10,
+ [1][1][2][0][RTW89_WW][1][1] = 10,
+ [1][1][2][0][RTW89_WW][2][1] = 58,
+ [1][1][2][0][RTW89_WW][0][5] = 10,
+ [1][1][2][0][RTW89_WW][1][5] = 10,
+ [1][1][2][0][RTW89_WW][2][5] = 58,
+ [1][1][2][0][RTW89_WW][0][9] = 10,
+ [1][1][2][0][RTW89_WW][1][9] = 10,
+ [1][1][2][0][RTW89_WW][2][9] = 58,
+ [1][1][2][0][RTW89_WW][0][13] = 10,
+ [1][1][2][0][RTW89_WW][1][13] = 10,
+ [1][1][2][0][RTW89_WW][2][13] = 58,
+ [1][1][2][0][RTW89_WW][0][16] = 10,
+ [1][1][2][0][RTW89_WW][1][16] = 10,
+ [1][1][2][0][RTW89_WW][2][16] = 58,
+ [1][1][2][0][RTW89_WW][0][20] = 10,
+ [1][1][2][0][RTW89_WW][1][20] = 10,
+ [1][1][2][0][RTW89_WW][2][20] = 58,
+ [1][1][2][0][RTW89_WW][0][24] = 10,
+ [1][1][2][0][RTW89_WW][1][24] = 10,
+ [1][1][2][0][RTW89_WW][2][24] = 70,
+ [1][1][2][0][RTW89_WW][0][28] = 10,
+ [1][1][2][0][RTW89_WW][1][28] = 10,
+ [1][1][2][0][RTW89_WW][2][28] = 70,
+ [1][1][2][0][RTW89_WW][0][31] = 10,
+ [1][1][2][0][RTW89_WW][1][31] = 10,
+ [1][1][2][0][RTW89_WW][2][31] = 70,
+ [1][1][2][0][RTW89_WW][0][35] = 10,
+ [1][1][2][0][RTW89_WW][1][35] = 10,
+ [1][1][2][0][RTW89_WW][2][35] = 70,
+ [1][1][2][0][RTW89_WW][0][39] = 10,
+ [1][1][2][0][RTW89_WW][1][39] = 10,
+ [1][1][2][0][RTW89_WW][2][39] = 70,
+ [1][1][2][0][RTW89_WW][0][43] = 10,
+ [1][1][2][0][RTW89_WW][1][43] = 10,
+ [1][1][2][0][RTW89_WW][2][43] = 70,
+ [1][1][2][0][RTW89_WW][0][46] = 12,
+ [1][1][2][0][RTW89_WW][1][46] = 12,
+ [1][1][2][0][RTW89_WW][2][46] = 0,
+ [1][1][2][0][RTW89_WW][0][50] = 12,
+ [1][1][2][0][RTW89_WW][1][50] = 12,
+ [1][1][2][0][RTW89_WW][2][50] = 0,
+ [1][1][2][0][RTW89_WW][0][54] = 10,
+ [1][1][2][0][RTW89_WW][1][54] = 10,
+ [1][1][2][0][RTW89_WW][2][54] = 0,
+ [1][1][2][0][RTW89_WW][0][58] = 10,
+ [1][1][2][0][RTW89_WW][1][58] = 10,
+ [1][1][2][0][RTW89_WW][2][58] = 66,
+ [1][1][2][0][RTW89_WW][0][61] = 10,
+ [1][1][2][0][RTW89_WW][1][61] = 10,
+ [1][1][2][0][RTW89_WW][2][61] = 66,
+ [1][1][2][0][RTW89_WW][0][65] = 10,
+ [1][1][2][0][RTW89_WW][1][65] = 10,
+ [1][1][2][0][RTW89_WW][2][65] = 66,
+ [1][1][2][0][RTW89_WW][0][69] = 10,
+ [1][1][2][0][RTW89_WW][1][69] = 10,
+ [1][1][2][0][RTW89_WW][2][69] = 66,
+ [1][1][2][0][RTW89_WW][0][73] = 10,
+ [1][1][2][0][RTW89_WW][1][73] = 10,
+ [1][1][2][0][RTW89_WW][2][73] = 66,
+ [1][1][2][0][RTW89_WW][0][76] = 10,
+ [1][1][2][0][RTW89_WW][1][76] = 10,
+ [1][1][2][0][RTW89_WW][2][76] = 66,
+ [1][1][2][0][RTW89_WW][0][80] = 10,
+ [1][1][2][0][RTW89_WW][1][80] = 10,
+ [1][1][2][0][RTW89_WW][2][80] = 66,
+ [1][1][2][0][RTW89_WW][0][84] = 10,
+ [1][1][2][0][RTW89_WW][1][84] = 10,
+ [1][1][2][0][RTW89_WW][2][84] = 66,
+ [1][1][2][0][RTW89_WW][0][88] = 10,
+ [1][1][2][0][RTW89_WW][1][88] = 10,
+ [1][1][2][0][RTW89_WW][2][88] = 0,
+ [1][1][2][0][RTW89_WW][0][91] = 12,
+ [1][1][2][0][RTW89_WW][1][91] = 12,
+ [1][1][2][0][RTW89_WW][2][91] = 0,
+ [1][1][2][0][RTW89_WW][0][95] = 10,
+ [1][1][2][0][RTW89_WW][1][95] = 10,
+ [1][1][2][0][RTW89_WW][2][95] = 0,
+ [1][1][2][0][RTW89_WW][0][99] = 10,
+ [1][1][2][0][RTW89_WW][1][99] = 10,
+ [1][1][2][0][RTW89_WW][2][99] = 0,
+ [1][1][2][0][RTW89_WW][0][103] = 10,
+ [1][1][2][0][RTW89_WW][1][103] = 10,
+ [1][1][2][0][RTW89_WW][2][103] = 0,
+ [1][1][2][0][RTW89_WW][0][106] = 12,
+ [1][1][2][0][RTW89_WW][1][106] = 12,
+ [1][1][2][0][RTW89_WW][2][106] = 0,
+ [1][1][2][0][RTW89_WW][0][110] = 0,
+ [1][1][2][0][RTW89_WW][1][110] = 0,
+ [1][1][2][0][RTW89_WW][2][110] = 0,
+ [1][1][2][0][RTW89_WW][0][114] = 0,
+ [1][1][2][0][RTW89_WW][1][114] = 0,
+ [1][1][2][0][RTW89_WW][2][114] = 0,
+ [1][1][2][0][RTW89_WW][0][118] = 0,
+ [1][1][2][0][RTW89_WW][1][118] = 0,
+ [1][1][2][0][RTW89_WW][2][118] = 0,
+ [1][1][2][1][RTW89_WW][0][1] = 6,
+ [1][1][2][1][RTW89_WW][1][1] = 10,
+ [1][1][2][1][RTW89_WW][2][1] = 58,
+ [1][1][2][1][RTW89_WW][0][5] = 6,
+ [1][1][2][1][RTW89_WW][1][5] = 10,
+ [1][1][2][1][RTW89_WW][2][5] = 58,
+ [1][1][2][1][RTW89_WW][0][9] = 6,
+ [1][1][2][1][RTW89_WW][1][9] = 10,
+ [1][1][2][1][RTW89_WW][2][9] = 58,
+ [1][1][2][1][RTW89_WW][0][13] = 6,
+ [1][1][2][1][RTW89_WW][1][13] = 10,
+ [1][1][2][1][RTW89_WW][2][13] = 58,
+ [1][1][2][1][RTW89_WW][0][16] = 6,
+ [1][1][2][1][RTW89_WW][1][16] = 10,
+ [1][1][2][1][RTW89_WW][2][16] = 58,
+ [1][1][2][1][RTW89_WW][0][20] = 6,
+ [1][1][2][1][RTW89_WW][1][20] = 10,
+ [1][1][2][1][RTW89_WW][2][20] = 58,
+ [1][1][2][1][RTW89_WW][0][24] = 6,
+ [1][1][2][1][RTW89_WW][1][24] = 10,
+ [1][1][2][1][RTW89_WW][2][24] = 70,
+ [1][1][2][1][RTW89_WW][0][28] = 6,
+ [1][1][2][1][RTW89_WW][1][28] = 10,
+ [1][1][2][1][RTW89_WW][2][28] = 70,
+ [1][1][2][1][RTW89_WW][0][31] = 6,
+ [1][1][2][1][RTW89_WW][1][31] = 10,
+ [1][1][2][1][RTW89_WW][2][31] = 70,
+ [1][1][2][1][RTW89_WW][0][35] = 6,
+ [1][1][2][1][RTW89_WW][1][35] = 10,
+ [1][1][2][1][RTW89_WW][2][35] = 70,
+ [1][1][2][1][RTW89_WW][0][39] = 6,
+ [1][1][2][1][RTW89_WW][1][39] = 10,
+ [1][1][2][1][RTW89_WW][2][39] = 70,
+ [1][1][2][1][RTW89_WW][0][43] = 6,
+ [1][1][2][1][RTW89_WW][1][43] = 10,
+ [1][1][2][1][RTW89_WW][2][43] = 70,
+ [1][1][2][1][RTW89_WW][0][46] = 12,
+ [1][1][2][1][RTW89_WW][1][46] = 12,
+ [1][1][2][1][RTW89_WW][2][46] = 0,
+ [1][1][2][1][RTW89_WW][0][50] = 12,
+ [1][1][2][1][RTW89_WW][1][50] = 12,
+ [1][1][2][1][RTW89_WW][2][50] = 0,
+ [1][1][2][1][RTW89_WW][0][54] = 10,
+ [1][1][2][1][RTW89_WW][1][54] = 10,
+ [1][1][2][1][RTW89_WW][2][54] = 0,
+ [1][1][2][1][RTW89_WW][0][58] = 10,
+ [1][1][2][1][RTW89_WW][1][58] = 10,
+ [1][1][2][1][RTW89_WW][2][58] = 66,
+ [1][1][2][1][RTW89_WW][0][61] = 10,
+ [1][1][2][1][RTW89_WW][1][61] = 10,
+ [1][1][2][1][RTW89_WW][2][61] = 66,
+ [1][1][2][1][RTW89_WW][0][65] = 10,
+ [1][1][2][1][RTW89_WW][1][65] = 10,
+ [1][1][2][1][RTW89_WW][2][65] = 66,
+ [1][1][2][1][RTW89_WW][0][69] = 10,
+ [1][1][2][1][RTW89_WW][1][69] = 10,
+ [1][1][2][1][RTW89_WW][2][69] = 66,
+ [1][1][2][1][RTW89_WW][0][73] = 10,
+ [1][1][2][1][RTW89_WW][1][73] = 10,
+ [1][1][2][1][RTW89_WW][2][73] = 66,
+ [1][1][2][1][RTW89_WW][0][76] = 10,
+ [1][1][2][1][RTW89_WW][1][76] = 10,
+ [1][1][2][1][RTW89_WW][2][76] = 66,
+ [1][1][2][1][RTW89_WW][0][80] = 10,
+ [1][1][2][1][RTW89_WW][1][80] = 10,
+ [1][1][2][1][RTW89_WW][2][80] = 66,
+ [1][1][2][1][RTW89_WW][0][84] = 10,
+ [1][1][2][1][RTW89_WW][1][84] = 10,
+ [1][1][2][1][RTW89_WW][2][84] = 66,
+ [1][1][2][1][RTW89_WW][0][88] = 10,
+ [1][1][2][1][RTW89_WW][1][88] = 10,
+ [1][1][2][1][RTW89_WW][2][88] = 0,
+ [1][1][2][1][RTW89_WW][0][91] = 12,
+ [1][1][2][1][RTW89_WW][1][91] = 12,
+ [1][1][2][1][RTW89_WW][2][91] = 0,
+ [1][1][2][1][RTW89_WW][0][95] = 10,
+ [1][1][2][1][RTW89_WW][1][95] = 10,
+ [1][1][2][1][RTW89_WW][2][95] = 0,
+ [1][1][2][1][RTW89_WW][0][99] = 10,
+ [1][1][2][1][RTW89_WW][1][99] = 10,
+ [1][1][2][1][RTW89_WW][2][99] = 0,
+ [1][1][2][1][RTW89_WW][0][103] = 10,
+ [1][1][2][1][RTW89_WW][1][103] = 10,
+ [1][1][2][1][RTW89_WW][2][103] = 0,
+ [1][1][2][1][RTW89_WW][0][106] = 12,
+ [1][1][2][1][RTW89_WW][1][106] = 12,
+ [1][1][2][1][RTW89_WW][2][106] = 0,
+ [1][1][2][1][RTW89_WW][0][110] = 0,
+ [1][1][2][1][RTW89_WW][1][110] = 0,
+ [1][1][2][1][RTW89_WW][2][110] = 0,
+ [1][1][2][1][RTW89_WW][0][114] = 0,
+ [1][1][2][1][RTW89_WW][1][114] = 0,
+ [1][1][2][1][RTW89_WW][2][114] = 0,
+ [1][1][2][1][RTW89_WW][0][118] = 0,
+ [1][1][2][1][RTW89_WW][1][118] = 0,
+ [1][1][2][1][RTW89_WW][2][118] = 0,
+ [2][0][2][0][RTW89_WW][0][3] = 24,
+ [2][0][2][0][RTW89_WW][1][3] = 46,
+ [2][0][2][0][RTW89_WW][2][3] = 60,
+ [2][0][2][0][RTW89_WW][0][11] = 24,
+ [2][0][2][0][RTW89_WW][1][11] = 46,
+ [2][0][2][0][RTW89_WW][2][11] = 60,
+ [2][0][2][0][RTW89_WW][0][18] = 24,
+ [2][0][2][0][RTW89_WW][1][18] = 46,
+ [2][0][2][0][RTW89_WW][2][18] = 60,
+ [2][0][2][0][RTW89_WW][0][26] = 24,
+ [2][0][2][0][RTW89_WW][1][26] = 46,
+ [2][0][2][0][RTW89_WW][2][26] = 60,
+ [2][0][2][0][RTW89_WW][0][33] = 24,
+ [2][0][2][0][RTW89_WW][1][33] = 46,
+ [2][0][2][0][RTW89_WW][2][33] = 60,
+ [2][0][2][0][RTW89_WW][0][41] = 24,
+ [2][0][2][0][RTW89_WW][1][41] = 46,
+ [2][0][2][0][RTW89_WW][2][41] = 60,
+ [2][0][2][0][RTW89_WW][0][48] = 46,
+ [2][0][2][0][RTW89_WW][1][48] = 46,
+ [2][0][2][0][RTW89_WW][2][48] = 0,
+ [2][0][2][0][RTW89_WW][0][56] = 46,
+ [2][0][2][0][RTW89_WW][1][56] = 46,
+ [2][0][2][0][RTW89_WW][2][56] = 0,
+ [2][0][2][0][RTW89_WW][0][63] = 46,
+ [2][0][2][0][RTW89_WW][1][63] = 46,
+ [2][0][2][0][RTW89_WW][2][63] = 58,
+ [2][0][2][0][RTW89_WW][0][71] = 46,
+ [2][0][2][0][RTW89_WW][1][71] = 46,
+ [2][0][2][0][RTW89_WW][2][71] = 58,
+ [2][0][2][0][RTW89_WW][0][78] = 46,
+ [2][0][2][0][RTW89_WW][1][78] = 46,
+ [2][0][2][0][RTW89_WW][2][78] = 58,
+ [2][0][2][0][RTW89_WW][0][86] = 46,
+ [2][0][2][0][RTW89_WW][1][86] = 46,
+ [2][0][2][0][RTW89_WW][2][86] = 0,
+ [2][0][2][0][RTW89_WW][0][93] = 46,
+ [2][0][2][0][RTW89_WW][1][93] = 46,
+ [2][0][2][0][RTW89_WW][2][93] = 0,
+ [2][0][2][0][RTW89_WW][0][101] = 44,
+ [2][0][2][0][RTW89_WW][1][101] = 44,
+ [2][0][2][0][RTW89_WW][2][101] = 0,
+ [2][0][2][0][RTW89_WW][0][108] = 0,
+ [2][0][2][0][RTW89_WW][1][108] = 0,
+ [2][0][2][0][RTW89_WW][2][108] = 0,
+ [2][0][2][0][RTW89_WW][0][116] = 0,
+ [2][0][2][0][RTW89_WW][1][116] = 0,
+ [2][0][2][0][RTW89_WW][2][116] = 0,
+ [2][1][2][0][RTW89_WW][0][3] = 12,
+ [2][1][2][0][RTW89_WW][1][3] = 22,
+ [2][1][2][0][RTW89_WW][2][3] = 50,
+ [2][1][2][0][RTW89_WW][0][11] = 12,
+ [2][1][2][0][RTW89_WW][1][11] = 20,
+ [2][1][2][0][RTW89_WW][2][11] = 50,
+ [2][1][2][0][RTW89_WW][0][18] = 12,
+ [2][1][2][0][RTW89_WW][1][18] = 20,
+ [2][1][2][0][RTW89_WW][2][18] = 50,
+ [2][1][2][0][RTW89_WW][0][26] = 12,
+ [2][1][2][0][RTW89_WW][1][26] = 20,
+ [2][1][2][0][RTW89_WW][2][26] = 60,
+ [2][1][2][0][RTW89_WW][0][33] = 12,
+ [2][1][2][0][RTW89_WW][1][33] = 20,
+ [2][1][2][0][RTW89_WW][2][33] = 60,
+ [2][1][2][0][RTW89_WW][0][41] = 12,
+ [2][1][2][0][RTW89_WW][1][41] = 22,
+ [2][1][2][0][RTW89_WW][2][41] = 60,
+ [2][1][2][0][RTW89_WW][0][48] = 22,
+ [2][1][2][0][RTW89_WW][1][48] = 22,
+ [2][1][2][0][RTW89_WW][2][48] = 0,
+ [2][1][2][0][RTW89_WW][0][56] = 20,
+ [2][1][2][0][RTW89_WW][1][56] = 20,
+ [2][1][2][0][RTW89_WW][2][56] = 0,
+ [2][1][2][0][RTW89_WW][0][63] = 22,
+ [2][1][2][0][RTW89_WW][1][63] = 22,
+ [2][1][2][0][RTW89_WW][2][63] = 58,
+ [2][1][2][0][RTW89_WW][0][71] = 20,
+ [2][1][2][0][RTW89_WW][1][71] = 20,
+ [2][1][2][0][RTW89_WW][2][71] = 58,
+ [2][1][2][0][RTW89_WW][0][78] = 20,
+ [2][1][2][0][RTW89_WW][1][78] = 20,
+ [2][1][2][0][RTW89_WW][2][78] = 58,
+ [2][1][2][0][RTW89_WW][0][86] = 20,
+ [2][1][2][0][RTW89_WW][1][86] = 20,
+ [2][1][2][0][RTW89_WW][2][86] = 0,
+ [2][1][2][0][RTW89_WW][0][93] = 22,
+ [2][1][2][0][RTW89_WW][1][93] = 22,
+ [2][1][2][0][RTW89_WW][2][93] = 0,
+ [2][1][2][0][RTW89_WW][0][101] = 22,
+ [2][1][2][0][RTW89_WW][1][101] = 22,
+ [2][1][2][0][RTW89_WW][2][101] = 0,
+ [2][1][2][0][RTW89_WW][0][108] = 0,
+ [2][1][2][0][RTW89_WW][1][108] = 0,
+ [2][1][2][0][RTW89_WW][2][108] = 0,
+ [2][1][2][0][RTW89_WW][0][116] = 0,
+ [2][1][2][0][RTW89_WW][1][116] = 0,
+ [2][1][2][0][RTW89_WW][2][116] = 0,
+ [2][1][2][1][RTW89_WW][0][3] = 6,
+ [2][1][2][1][RTW89_WW][1][3] = 22,
+ [2][1][2][1][RTW89_WW][2][3] = 50,
+ [2][1][2][1][RTW89_WW][0][11] = 6,
+ [2][1][2][1][RTW89_WW][1][11] = 20,
+ [2][1][2][1][RTW89_WW][2][11] = 50,
+ [2][1][2][1][RTW89_WW][0][18] = 6,
+ [2][1][2][1][RTW89_WW][1][18] = 20,
+ [2][1][2][1][RTW89_WW][2][18] = 50,
+ [2][1][2][1][RTW89_WW][0][26] = 6,
+ [2][1][2][1][RTW89_WW][1][26] = 20,
+ [2][1][2][1][RTW89_WW][2][26] = 60,
+ [2][1][2][1][RTW89_WW][0][33] = 6,
+ [2][1][2][1][RTW89_WW][1][33] = 20,
+ [2][1][2][1][RTW89_WW][2][33] = 60,
+ [2][1][2][1][RTW89_WW][0][41] = 6,
+ [2][1][2][1][RTW89_WW][1][41] = 22,
+ [2][1][2][1][RTW89_WW][2][41] = 60,
+ [2][1][2][1][RTW89_WW][0][48] = 22,
+ [2][1][2][1][RTW89_WW][1][48] = 22,
+ [2][1][2][1][RTW89_WW][2][48] = 0,
+ [2][1][2][1][RTW89_WW][0][56] = 20,
+ [2][1][2][1][RTW89_WW][1][56] = 20,
+ [2][1][2][1][RTW89_WW][2][56] = 0,
+ [2][1][2][1][RTW89_WW][0][63] = 22,
+ [2][1][2][1][RTW89_WW][1][63] = 22,
+ [2][1][2][1][RTW89_WW][2][63] = 58,
+ [2][1][2][1][RTW89_WW][0][71] = 20,
+ [2][1][2][1][RTW89_WW][1][71] = 20,
+ [2][1][2][1][RTW89_WW][2][71] = 58,
+ [2][1][2][1][RTW89_WW][0][78] = 20,
+ [2][1][2][1][RTW89_WW][1][78] = 20,
+ [2][1][2][1][RTW89_WW][2][78] = 58,
+ [2][1][2][1][RTW89_WW][0][86] = 20,
+ [2][1][2][1][RTW89_WW][1][86] = 20,
+ [2][1][2][1][RTW89_WW][2][86] = 0,
+ [2][1][2][1][RTW89_WW][0][93] = 22,
+ [2][1][2][1][RTW89_WW][1][93] = 22,
+ [2][1][2][1][RTW89_WW][2][93] = 0,
+ [2][1][2][1][RTW89_WW][0][101] = 22,
+ [2][1][2][1][RTW89_WW][1][101] = 22,
+ [2][1][2][1][RTW89_WW][2][101] = 0,
+ [2][1][2][1][RTW89_WW][0][108] = 0,
+ [2][1][2][1][RTW89_WW][1][108] = 0,
+ [2][1][2][1][RTW89_WW][2][108] = 0,
+ [2][1][2][1][RTW89_WW][0][116] = 0,
+ [2][1][2][1][RTW89_WW][1][116] = 0,
+ [2][1][2][1][RTW89_WW][2][116] = 0,
+ [3][0][2][0][RTW89_WW][0][7] = 22,
+ [3][0][2][0][RTW89_WW][1][7] = 42,
+ [3][0][2][0][RTW89_WW][2][7] = 52,
+ [3][0][2][0][RTW89_WW][0][22] = 20,
+ [3][0][2][0][RTW89_WW][1][22] = 42,
+ [3][0][2][0][RTW89_WW][2][22] = 52,
+ [3][0][2][0][RTW89_WW][0][37] = 20,
+ [3][0][2][0][RTW89_WW][1][37] = 42,
+ [3][0][2][0][RTW89_WW][2][37] = 52,
+ [3][0][2][0][RTW89_WW][0][52] = 54,
+ [3][0][2][0][RTW89_WW][1][52] = 54,
+ [3][0][2][0][RTW89_WW][2][52] = 0,
+ [3][0][2][0][RTW89_WW][0][67] = 54,
+ [3][0][2][0][RTW89_WW][1][67] = 54,
+ [3][0][2][0][RTW89_WW][2][67] = 54,
+ [3][0][2][0][RTW89_WW][0][82] = 26,
+ [3][0][2][0][RTW89_WW][1][82] = 26,
+ [3][0][2][0][RTW89_WW][2][82] = 0,
+ [3][0][2][0][RTW89_WW][0][97] = 26,
+ [3][0][2][0][RTW89_WW][1][97] = 26,
+ [3][0][2][0][RTW89_WW][2][97] = 0,
+ [3][0][2][0][RTW89_WW][0][112] = 0,
+ [3][0][2][0][RTW89_WW][1][112] = 0,
+ [3][0][2][0][RTW89_WW][2][112] = 0,
+ [3][1][2][0][RTW89_WW][0][7] = 10,
+ [3][1][2][0][RTW89_WW][1][7] = 32,
+ [3][1][2][0][RTW89_WW][2][7] = 46,
+ [3][1][2][0][RTW89_WW][0][22] = 8,
+ [3][1][2][0][RTW89_WW][1][22] = 30,
+ [3][1][2][0][RTW89_WW][2][22] = 52,
+ [3][1][2][0][RTW89_WW][0][37] = 8,
+ [3][1][2][0][RTW89_WW][1][37] = 30,
+ [3][1][2][0][RTW89_WW][2][37] = 52,
+ [3][1][2][0][RTW89_WW][0][52] = 30,
+ [3][1][2][0][RTW89_WW][1][52] = 30,
+ [3][1][2][0][RTW89_WW][2][52] = 0,
+ [3][1][2][0][RTW89_WW][0][67] = 32,
+ [3][1][2][0][RTW89_WW][1][67] = 32,
+ [3][1][2][0][RTW89_WW][2][67] = 54,
+ [3][1][2][0][RTW89_WW][0][82] = 24,
+ [3][1][2][0][RTW89_WW][1][82] = 24,
+ [3][1][2][0][RTW89_WW][2][82] = 0,
+ [3][1][2][0][RTW89_WW][0][97] = 24,
+ [3][1][2][0][RTW89_WW][1][97] = 24,
+ [3][1][2][0][RTW89_WW][2][97] = 0,
+ [3][1][2][0][RTW89_WW][0][112] = 0,
+ [3][1][2][0][RTW89_WW][1][112] = 0,
+ [3][1][2][0][RTW89_WW][2][112] = 0,
+ [3][1][2][1][RTW89_WW][0][7] = 6,
+ [3][1][2][1][RTW89_WW][1][7] = 32,
+ [3][1][2][1][RTW89_WW][2][7] = 46,
+ [3][1][2][1][RTW89_WW][0][22] = 6,
+ [3][1][2][1][RTW89_WW][1][22] = 30,
+ [3][1][2][1][RTW89_WW][2][22] = 52,
+ [3][1][2][1][RTW89_WW][0][37] = 6,
+ [3][1][2][1][RTW89_WW][1][37] = 30,
+ [3][1][2][1][RTW89_WW][2][37] = 52,
+ [3][1][2][1][RTW89_WW][0][52] = 30,
+ [3][1][2][1][RTW89_WW][1][52] = 30,
+ [3][1][2][1][RTW89_WW][2][52] = 0,
+ [3][1][2][1][RTW89_WW][0][67] = 32,
+ [3][1][2][1][RTW89_WW][1][67] = 32,
+ [3][1][2][1][RTW89_WW][2][67] = 54,
+ [3][1][2][1][RTW89_WW][0][82] = 24,
+ [3][1][2][1][RTW89_WW][1][82] = 24,
+ [3][1][2][1][RTW89_WW][2][82] = 0,
+ [3][1][2][1][RTW89_WW][0][97] = 24,
+ [3][1][2][1][RTW89_WW][1][97] = 24,
+ [3][1][2][1][RTW89_WW][2][97] = 0,
+ [3][1][2][1][RTW89_WW][0][112] = 0,
+ [3][1][2][1][RTW89_WW][1][112] = 0,
+ [3][1][2][1][RTW89_WW][2][112] = 0,
+ [0][0][1][0][RTW89_FCC][1][0] = 24,
+ [0][0][1][0][RTW89_FCC][2][0] = 56,
+ [0][0][1][0][RTW89_ETSI][1][0] = 66,
+ [0][0][1][0][RTW89_ETSI][0][0] = 28,
+ [0][0][1][0][RTW89_MKK][1][0] = 66,
+ [0][0][1][0][RTW89_MKK][0][0] = 26,
+ [0][0][1][0][RTW89_IC][1][0] = 24,
+ [0][0][1][0][RTW89_KCC][1][0] = 24,
+ [0][0][1][0][RTW89_KCC][0][0] = 24,
+ [0][0][1][0][RTW89_ACMA][1][0] = 66,
+ [0][0][1][0][RTW89_ACMA][0][0] = 28,
+ [0][0][1][0][RTW89_CHILE][1][0] = 24,
+ [0][0][1][0][RTW89_QATAR][1][0] = 66,
+ [0][0][1][0][RTW89_QATAR][0][0] = 28,
+ [0][0][1][0][RTW89_UK][1][0] = 66,
+ [0][0][1][0][RTW89_UK][0][0] = 28,
+ [0][0][1][0][RTW89_FCC][1][2] = 22,
+ [0][0][1][0][RTW89_FCC][2][2] = 56,
+ [0][0][1][0][RTW89_ETSI][1][2] = 66,
+ [0][0][1][0][RTW89_ETSI][0][2] = 28,
+ [0][0][1][0][RTW89_MKK][1][2] = 66,
+ [0][0][1][0][RTW89_MKK][0][2] = 26,
+ [0][0][1][0][RTW89_IC][1][2] = 22,
+ [0][0][1][0][RTW89_KCC][1][2] = 24,
+ [0][0][1][0][RTW89_KCC][0][2] = 24,
+ [0][0][1][0][RTW89_ACMA][1][2] = 66,
+ [0][0][1][0][RTW89_ACMA][0][2] = 28,
+ [0][0][1][0][RTW89_CHILE][1][2] = 22,
+ [0][0][1][0][RTW89_QATAR][1][2] = 66,
+ [0][0][1][0][RTW89_QATAR][0][2] = 28,
+ [0][0][1][0][RTW89_UK][1][2] = 66,
+ [0][0][1][0][RTW89_UK][0][2] = 28,
+ [0][0][1][0][RTW89_FCC][1][4] = 22,
+ [0][0][1][0][RTW89_FCC][2][4] = 56,
+ [0][0][1][0][RTW89_ETSI][1][4] = 66,
+ [0][0][1][0][RTW89_ETSI][0][4] = 28,
+ [0][0][1][0][RTW89_MKK][1][4] = 66,
+ [0][0][1][0][RTW89_MKK][0][4] = 26,
+ [0][0][1][0][RTW89_IC][1][4] = 22,
+ [0][0][1][0][RTW89_KCC][1][4] = 24,
+ [0][0][1][0][RTW89_KCC][0][4] = 24,
+ [0][0][1][0][RTW89_ACMA][1][4] = 66,
+ [0][0][1][0][RTW89_ACMA][0][4] = 28,
+ [0][0][1][0][RTW89_CHILE][1][4] = 22,
+ [0][0][1][0][RTW89_QATAR][1][4] = 66,
+ [0][0][1][0][RTW89_QATAR][0][4] = 28,
+ [0][0][1][0][RTW89_UK][1][4] = 66,
+ [0][0][1][0][RTW89_UK][0][4] = 28,
+ [0][0][1][0][RTW89_FCC][1][6] = 22,
+ [0][0][1][0][RTW89_FCC][2][6] = 56,
+ [0][0][1][0][RTW89_ETSI][1][6] = 66,
+ [0][0][1][0][RTW89_ETSI][0][6] = 28,
+ [0][0][1][0][RTW89_MKK][1][6] = 66,
+ [0][0][1][0][RTW89_MKK][0][6] = 26,
+ [0][0][1][0][RTW89_IC][1][6] = 22,
+ [0][0][1][0][RTW89_KCC][1][6] = 24,
+ [0][0][1][0][RTW89_KCC][0][6] = 24,
+ [0][0][1][0][RTW89_ACMA][1][6] = 66,
+ [0][0][1][0][RTW89_ACMA][0][6] = 28,
+ [0][0][1][0][RTW89_CHILE][1][6] = 22,
+ [0][0][1][0][RTW89_QATAR][1][6] = 66,
+ [0][0][1][0][RTW89_QATAR][0][6] = 28,
+ [0][0][1][0][RTW89_UK][1][6] = 66,
+ [0][0][1][0][RTW89_UK][0][6] = 28,
+ [0][0][1][0][RTW89_FCC][1][8] = 22,
+ [0][0][1][0][RTW89_FCC][2][8] = 56,
+ [0][0][1][0][RTW89_ETSI][1][8] = 66,
+ [0][0][1][0][RTW89_ETSI][0][8] = 28,
+ [0][0][1][0][RTW89_MKK][1][8] = 66,
+ [0][0][1][0][RTW89_MKK][0][8] = 26,
+ [0][0][1][0][RTW89_IC][1][8] = 22,
+ [0][0][1][0][RTW89_KCC][1][8] = 24,
+ [0][0][1][0][RTW89_KCC][0][8] = 24,
+ [0][0][1][0][RTW89_ACMA][1][8] = 66,
+ [0][0][1][0][RTW89_ACMA][0][8] = 28,
+ [0][0][1][0][RTW89_CHILE][1][8] = 22,
+ [0][0][1][0][RTW89_QATAR][1][8] = 66,
+ [0][0][1][0][RTW89_QATAR][0][8] = 28,
+ [0][0][1][0][RTW89_UK][1][8] = 66,
+ [0][0][1][0][RTW89_UK][0][8] = 28,
+ [0][0][1][0][RTW89_FCC][1][10] = 22,
+ [0][0][1][0][RTW89_FCC][2][10] = 56,
+ [0][0][1][0][RTW89_ETSI][1][10] = 66,
+ [0][0][1][0][RTW89_ETSI][0][10] = 28,
+ [0][0][1][0][RTW89_MKK][1][10] = 66,
+ [0][0][1][0][RTW89_MKK][0][10] = 26,
+ [0][0][1][0][RTW89_IC][1][10] = 22,
+ [0][0][1][0][RTW89_KCC][1][10] = 24,
+ [0][0][1][0][RTW89_KCC][0][10] = 24,
+ [0][0][1][0][RTW89_ACMA][1][10] = 66,
+ [0][0][1][0][RTW89_ACMA][0][10] = 28,
+ [0][0][1][0][RTW89_CHILE][1][10] = 22,
+ [0][0][1][0][RTW89_QATAR][1][10] = 66,
+ [0][0][1][0][RTW89_QATAR][0][10] = 28,
+ [0][0][1][0][RTW89_UK][1][10] = 66,
+ [0][0][1][0][RTW89_UK][0][10] = 28,
+ [0][0][1][0][RTW89_FCC][1][12] = 22,
+ [0][0][1][0][RTW89_FCC][2][12] = 56,
+ [0][0][1][0][RTW89_ETSI][1][12] = 66,
+ [0][0][1][0][RTW89_ETSI][0][12] = 28,
+ [0][0][1][0][RTW89_MKK][1][12] = 66,
+ [0][0][1][0][RTW89_MKK][0][12] = 26,
+ [0][0][1][0][RTW89_IC][1][12] = 22,
+ [0][0][1][0][RTW89_KCC][1][12] = 24,
+ [0][0][1][0][RTW89_KCC][0][12] = 24,
+ [0][0][1][0][RTW89_ACMA][1][12] = 66,
+ [0][0][1][0][RTW89_ACMA][0][12] = 28,
+ [0][0][1][0][RTW89_CHILE][1][12] = 22,
+ [0][0][1][0][RTW89_QATAR][1][12] = 66,
+ [0][0][1][0][RTW89_QATAR][0][12] = 28,
+ [0][0][1][0][RTW89_UK][1][12] = 66,
+ [0][0][1][0][RTW89_UK][0][12] = 28,
+ [0][0][1][0][RTW89_FCC][1][14] = 22,
+ [0][0][1][0][RTW89_FCC][2][14] = 56,
+ [0][0][1][0][RTW89_ETSI][1][14] = 66,
+ [0][0][1][0][RTW89_ETSI][0][14] = 28,
+ [0][0][1][0][RTW89_MKK][1][14] = 66,
+ [0][0][1][0][RTW89_MKK][0][14] = 26,
+ [0][0][1][0][RTW89_IC][1][14] = 22,
+ [0][0][1][0][RTW89_KCC][1][14] = 24,
+ [0][0][1][0][RTW89_KCC][0][14] = 24,
+ [0][0][1][0][RTW89_ACMA][1][14] = 66,
+ [0][0][1][0][RTW89_ACMA][0][14] = 28,
+ [0][0][1][0][RTW89_CHILE][1][14] = 22,
+ [0][0][1][0][RTW89_QATAR][1][14] = 66,
+ [0][0][1][0][RTW89_QATAR][0][14] = 28,
+ [0][0][1][0][RTW89_UK][1][14] = 66,
+ [0][0][1][0][RTW89_UK][0][14] = 28,
+ [0][0][1][0][RTW89_FCC][1][15] = 22,
+ [0][0][1][0][RTW89_FCC][2][15] = 56,
+ [0][0][1][0][RTW89_ETSI][1][15] = 66,
+ [0][0][1][0][RTW89_ETSI][0][15] = 28,
+ [0][0][1][0][RTW89_MKK][1][15] = 66,
+ [0][0][1][0][RTW89_MKK][0][15] = 26,
+ [0][0][1][0][RTW89_IC][1][15] = 22,
+ [0][0][1][0][RTW89_KCC][1][15] = 24,
+ [0][0][1][0][RTW89_KCC][0][15] = 24,
+ [0][0][1][0][RTW89_ACMA][1][15] = 66,
+ [0][0][1][0][RTW89_ACMA][0][15] = 28,
+ [0][0][1][0][RTW89_CHILE][1][15] = 22,
+ [0][0][1][0][RTW89_QATAR][1][15] = 66,
+ [0][0][1][0][RTW89_QATAR][0][15] = 28,
+ [0][0][1][0][RTW89_UK][1][15] = 66,
+ [0][0][1][0][RTW89_UK][0][15] = 28,
+ [0][0][1][0][RTW89_FCC][1][17] = 22,
+ [0][0][1][0][RTW89_FCC][2][17] = 56,
+ [0][0][1][0][RTW89_ETSI][1][17] = 66,
+ [0][0][1][0][RTW89_ETSI][0][17] = 28,
+ [0][0][1][0][RTW89_MKK][1][17] = 66,
+ [0][0][1][0][RTW89_MKK][0][17] = 26,
+ [0][0][1][0][RTW89_IC][1][17] = 22,
+ [0][0][1][0][RTW89_KCC][1][17] = 24,
+ [0][0][1][0][RTW89_KCC][0][17] = 24,
+ [0][0][1][0][RTW89_ACMA][1][17] = 66,
+ [0][0][1][0][RTW89_ACMA][0][17] = 28,
+ [0][0][1][0][RTW89_CHILE][1][17] = 22,
+ [0][0][1][0][RTW89_QATAR][1][17] = 66,
+ [0][0][1][0][RTW89_QATAR][0][17] = 28,
+ [0][0][1][0][RTW89_UK][1][17] = 66,
+ [0][0][1][0][RTW89_UK][0][17] = 28,
+ [0][0][1][0][RTW89_FCC][1][19] = 22,
+ [0][0][1][0][RTW89_FCC][2][19] = 56,
+ [0][0][1][0][RTW89_ETSI][1][19] = 66,
+ [0][0][1][0][RTW89_ETSI][0][19] = 28,
+ [0][0][1][0][RTW89_MKK][1][19] = 66,
+ [0][0][1][0][RTW89_MKK][0][19] = 26,
+ [0][0][1][0][RTW89_IC][1][19] = 22,
+ [0][0][1][0][RTW89_KCC][1][19] = 24,
+ [0][0][1][0][RTW89_KCC][0][19] = 24,
+ [0][0][1][0][RTW89_ACMA][1][19] = 66,
+ [0][0][1][0][RTW89_ACMA][0][19] = 28,
+ [0][0][1][0][RTW89_CHILE][1][19] = 22,
+ [0][0][1][0][RTW89_QATAR][1][19] = 66,
+ [0][0][1][0][RTW89_QATAR][0][19] = 28,
+ [0][0][1][0][RTW89_UK][1][19] = 66,
+ [0][0][1][0][RTW89_UK][0][19] = 28,
+ [0][0][1][0][RTW89_FCC][1][21] = 22,
+ [0][0][1][0][RTW89_FCC][2][21] = 56,
+ [0][0][1][0][RTW89_ETSI][1][21] = 66,
+ [0][0][1][0][RTW89_ETSI][0][21] = 28,
+ [0][0][1][0][RTW89_MKK][1][21] = 66,
+ [0][0][1][0][RTW89_MKK][0][21] = 26,
+ [0][0][1][0][RTW89_IC][1][21] = 22,
+ [0][0][1][0][RTW89_KCC][1][21] = 24,
+ [0][0][1][0][RTW89_KCC][0][21] = 24,
+ [0][0][1][0][RTW89_ACMA][1][21] = 66,
+ [0][0][1][0][RTW89_ACMA][0][21] = 28,
+ [0][0][1][0][RTW89_CHILE][1][21] = 22,
+ [0][0][1][0][RTW89_QATAR][1][21] = 66,
+ [0][0][1][0][RTW89_QATAR][0][21] = 28,
+ [0][0][1][0][RTW89_UK][1][21] = 66,
+ [0][0][1][0][RTW89_UK][0][21] = 28,
+ [0][0][1][0][RTW89_FCC][1][23] = 22,
+ [0][0][1][0][RTW89_FCC][2][23] = 70,
+ [0][0][1][0][RTW89_ETSI][1][23] = 66,
+ [0][0][1][0][RTW89_ETSI][0][23] = 28,
+ [0][0][1][0][RTW89_MKK][1][23] = 66,
+ [0][0][1][0][RTW89_MKK][0][23] = 26,
+ [0][0][1][0][RTW89_IC][1][23] = 22,
+ [0][0][1][0][RTW89_KCC][1][23] = 24,
+ [0][0][1][0][RTW89_KCC][0][23] = 26,
+ [0][0][1][0][RTW89_ACMA][1][23] = 66,
+ [0][0][1][0][RTW89_ACMA][0][23] = 28,
+ [0][0][1][0][RTW89_CHILE][1][23] = 22,
+ [0][0][1][0][RTW89_QATAR][1][23] = 66,
+ [0][0][1][0][RTW89_QATAR][0][23] = 28,
+ [0][0][1][0][RTW89_UK][1][23] = 66,
+ [0][0][1][0][RTW89_UK][0][23] = 28,
+ [0][0][1][0][RTW89_FCC][1][25] = 22,
+ [0][0][1][0][RTW89_FCC][2][25] = 70,
+ [0][0][1][0][RTW89_ETSI][1][25] = 66,
+ [0][0][1][0][RTW89_ETSI][0][25] = 28,
+ [0][0][1][0][RTW89_MKK][1][25] = 66,
+ [0][0][1][0][RTW89_MKK][0][25] = 26,
+ [0][0][1][0][RTW89_IC][1][25] = 22,
+ [0][0][1][0][RTW89_KCC][1][25] = 24,
+ [0][0][1][0][RTW89_KCC][0][25] = 26,
+ [0][0][1][0][RTW89_ACMA][1][25] = 66,
+ [0][0][1][0][RTW89_ACMA][0][25] = 28,
+ [0][0][1][0][RTW89_CHILE][1][25] = 22,
+ [0][0][1][0][RTW89_QATAR][1][25] = 66,
+ [0][0][1][0][RTW89_QATAR][0][25] = 28,
+ [0][0][1][0][RTW89_UK][1][25] = 66,
+ [0][0][1][0][RTW89_UK][0][25] = 28,
+ [0][0][1][0][RTW89_FCC][1][27] = 22,
+ [0][0][1][0][RTW89_FCC][2][27] = 70,
+ [0][0][1][0][RTW89_ETSI][1][27] = 66,
+ [0][0][1][0][RTW89_ETSI][0][27] = 28,
+ [0][0][1][0][RTW89_MKK][1][27] = 66,
+ [0][0][1][0][RTW89_MKK][0][27] = 26,
+ [0][0][1][0][RTW89_IC][1][27] = 22,
+ [0][0][1][0][RTW89_KCC][1][27] = 24,
+ [0][0][1][0][RTW89_KCC][0][27] = 26,
+ [0][0][1][0][RTW89_ACMA][1][27] = 66,
+ [0][0][1][0][RTW89_ACMA][0][27] = 28,
+ [0][0][1][0][RTW89_CHILE][1][27] = 22,
+ [0][0][1][0][RTW89_QATAR][1][27] = 66,
+ [0][0][1][0][RTW89_QATAR][0][27] = 28,
+ [0][0][1][0][RTW89_UK][1][27] = 66,
+ [0][0][1][0][RTW89_UK][0][27] = 28,
+ [0][0][1][0][RTW89_FCC][1][29] = 22,
+ [0][0][1][0][RTW89_FCC][2][29] = 70,
+ [0][0][1][0][RTW89_ETSI][1][29] = 66,
+ [0][0][1][0][RTW89_ETSI][0][29] = 28,
+ [0][0][1][0][RTW89_MKK][1][29] = 66,
+ [0][0][1][0][RTW89_MKK][0][29] = 26,
+ [0][0][1][0][RTW89_IC][1][29] = 22,
+ [0][0][1][0][RTW89_KCC][1][29] = 24,
+ [0][0][1][0][RTW89_KCC][0][29] = 26,
+ [0][0][1][0][RTW89_ACMA][1][29] = 66,
+ [0][0][1][0][RTW89_ACMA][0][29] = 28,
+ [0][0][1][0][RTW89_CHILE][1][29] = 22,
+ [0][0][1][0][RTW89_QATAR][1][29] = 66,
+ [0][0][1][0][RTW89_QATAR][0][29] = 28,
+ [0][0][1][0][RTW89_UK][1][29] = 66,
+ [0][0][1][0][RTW89_UK][0][29] = 28,
+ [0][0][1][0][RTW89_FCC][1][30] = 22,
+ [0][0][1][0][RTW89_FCC][2][30] = 70,
+ [0][0][1][0][RTW89_ETSI][1][30] = 66,
+ [0][0][1][0][RTW89_ETSI][0][30] = 28,
+ [0][0][1][0][RTW89_MKK][1][30] = 66,
+ [0][0][1][0][RTW89_MKK][0][30] = 26,
+ [0][0][1][0][RTW89_IC][1][30] = 22,
+ [0][0][1][0][RTW89_KCC][1][30] = 24,
+ [0][0][1][0][RTW89_KCC][0][30] = 26,
+ [0][0][1][0][RTW89_ACMA][1][30] = 66,
+ [0][0][1][0][RTW89_ACMA][0][30] = 28,
+ [0][0][1][0][RTW89_CHILE][1][30] = 22,
+ [0][0][1][0][RTW89_QATAR][1][30] = 66,
+ [0][0][1][0][RTW89_QATAR][0][30] = 28,
+ [0][0][1][0][RTW89_UK][1][30] = 66,
+ [0][0][1][0][RTW89_UK][0][30] = 28,
+ [0][0][1][0][RTW89_FCC][1][32] = 22,
+ [0][0][1][0][RTW89_FCC][2][32] = 70,
+ [0][0][1][0][RTW89_ETSI][1][32] = 66,
+ [0][0][1][0][RTW89_ETSI][0][32] = 28,
+ [0][0][1][0][RTW89_MKK][1][32] = 66,
+ [0][0][1][0][RTW89_MKK][0][32] = 26,
+ [0][0][1][0][RTW89_IC][1][32] = 22,
+ [0][0][1][0][RTW89_KCC][1][32] = 24,
+ [0][0][1][0][RTW89_KCC][0][32] = 26,
+ [0][0][1][0][RTW89_ACMA][1][32] = 66,
+ [0][0][1][0][RTW89_ACMA][0][32] = 28,
+ [0][0][1][0][RTW89_CHILE][1][32] = 22,
+ [0][0][1][0][RTW89_QATAR][1][32] = 66,
+ [0][0][1][0][RTW89_QATAR][0][32] = 28,
+ [0][0][1][0][RTW89_UK][1][32] = 66,
+ [0][0][1][0][RTW89_UK][0][32] = 28,
+ [0][0][1][0][RTW89_FCC][1][34] = 22,
+ [0][0][1][0][RTW89_FCC][2][34] = 70,
+ [0][0][1][0][RTW89_ETSI][1][34] = 66,
+ [0][0][1][0][RTW89_ETSI][0][34] = 28,
+ [0][0][1][0][RTW89_MKK][1][34] = 66,
+ [0][0][1][0][RTW89_MKK][0][34] = 26,
+ [0][0][1][0][RTW89_IC][1][34] = 22,
+ [0][0][1][0][RTW89_KCC][1][34] = 24,
+ [0][0][1][0][RTW89_KCC][0][34] = 26,
+ [0][0][1][0][RTW89_ACMA][1][34] = 66,
+ [0][0][1][0][RTW89_ACMA][0][34] = 28,
+ [0][0][1][0][RTW89_CHILE][1][34] = 22,
+ [0][0][1][0][RTW89_QATAR][1][34] = 66,
+ [0][0][1][0][RTW89_QATAR][0][34] = 28,
+ [0][0][1][0][RTW89_UK][1][34] = 66,
+ [0][0][1][0][RTW89_UK][0][34] = 28,
+ [0][0][1][0][RTW89_FCC][1][36] = 22,
+ [0][0][1][0][RTW89_FCC][2][36] = 70,
+ [0][0][1][0][RTW89_ETSI][1][36] = 66,
+ [0][0][1][0][RTW89_ETSI][0][36] = 28,
+ [0][0][1][0][RTW89_MKK][1][36] = 66,
+ [0][0][1][0][RTW89_MKK][0][36] = 26,
+ [0][0][1][0][RTW89_IC][1][36] = 22,
+ [0][0][1][0][RTW89_KCC][1][36] = 24,
+ [0][0][1][0][RTW89_KCC][0][36] = 26,
+ [0][0][1][0][RTW89_ACMA][1][36] = 66,
+ [0][0][1][0][RTW89_ACMA][0][36] = 28,
+ [0][0][1][0][RTW89_CHILE][1][36] = 22,
+ [0][0][1][0][RTW89_QATAR][1][36] = 66,
+ [0][0][1][0][RTW89_QATAR][0][36] = 28,
+ [0][0][1][0][RTW89_UK][1][36] = 66,
+ [0][0][1][0][RTW89_UK][0][36] = 28,
+ [0][0][1][0][RTW89_FCC][1][38] = 22,
+ [0][0][1][0][RTW89_FCC][2][38] = 70,
+ [0][0][1][0][RTW89_ETSI][1][38] = 66,
+ [0][0][1][0][RTW89_ETSI][0][38] = 28,
+ [0][0][1][0][RTW89_MKK][1][38] = 66,
+ [0][0][1][0][RTW89_MKK][0][38] = 26,
+ [0][0][1][0][RTW89_IC][1][38] = 22,
+ [0][0][1][0][RTW89_KCC][1][38] = 24,
+ [0][0][1][0][RTW89_KCC][0][38] = 26,
+ [0][0][1][0][RTW89_ACMA][1][38] = 66,
+ [0][0][1][0][RTW89_ACMA][0][38] = 28,
+ [0][0][1][0][RTW89_CHILE][1][38] = 22,
+ [0][0][1][0][RTW89_QATAR][1][38] = 66,
+ [0][0][1][0][RTW89_QATAR][0][38] = 28,
+ [0][0][1][0][RTW89_UK][1][38] = 66,
+ [0][0][1][0][RTW89_UK][0][38] = 28,
+ [0][0][1][0][RTW89_FCC][1][40] = 22,
+ [0][0][1][0][RTW89_FCC][2][40] = 70,
+ [0][0][1][0][RTW89_ETSI][1][40] = 66,
+ [0][0][1][0][RTW89_ETSI][0][40] = 28,
+ [0][0][1][0][RTW89_MKK][1][40] = 66,
+ [0][0][1][0][RTW89_MKK][0][40] = 26,
+ [0][0][1][0][RTW89_IC][1][40] = 22,
+ [0][0][1][0][RTW89_KCC][1][40] = 24,
+ [0][0][1][0][RTW89_KCC][0][40] = 26,
+ [0][0][1][0][RTW89_ACMA][1][40] = 66,
+ [0][0][1][0][RTW89_ACMA][0][40] = 28,
+ [0][0][1][0][RTW89_CHILE][1][40] = 22,
+ [0][0][1][0][RTW89_QATAR][1][40] = 66,
+ [0][0][1][0][RTW89_QATAR][0][40] = 28,
+ [0][0][1][0][RTW89_UK][1][40] = 66,
+ [0][0][1][0][RTW89_UK][0][40] = 28,
+ [0][0][1][0][RTW89_FCC][1][42] = 22,
+ [0][0][1][0][RTW89_FCC][2][42] = 70,
+ [0][0][1][0][RTW89_ETSI][1][42] = 66,
+ [0][0][1][0][RTW89_ETSI][0][42] = 28,
+ [0][0][1][0][RTW89_MKK][1][42] = 66,
+ [0][0][1][0][RTW89_MKK][0][42] = 26,
+ [0][0][1][0][RTW89_IC][1][42] = 22,
+ [0][0][1][0][RTW89_KCC][1][42] = 24,
+ [0][0][1][0][RTW89_KCC][0][42] = 26,
+ [0][0][1][0][RTW89_ACMA][1][42] = 66,
+ [0][0][1][0][RTW89_ACMA][0][42] = 28,
+ [0][0][1][0][RTW89_CHILE][1][42] = 22,
+ [0][0][1][0][RTW89_QATAR][1][42] = 66,
+ [0][0][1][0][RTW89_QATAR][0][42] = 28,
+ [0][0][1][0][RTW89_UK][1][42] = 66,
+ [0][0][1][0][RTW89_UK][0][42] = 28,
+ [0][0][1][0][RTW89_FCC][1][44] = 22,
+ [0][0][1][0][RTW89_FCC][2][44] = 70,
+ [0][0][1][0][RTW89_ETSI][1][44] = 66,
+ [0][0][1][0][RTW89_ETSI][0][44] = 30,
+ [0][0][1][0][RTW89_MKK][1][44] = 44,
+ [0][0][1][0][RTW89_MKK][0][44] = 28,
+ [0][0][1][0][RTW89_IC][1][44] = 22,
+ [0][0][1][0][RTW89_KCC][1][44] = 24,
+ [0][0][1][0][RTW89_KCC][0][44] = 26,
+ [0][0][1][0][RTW89_ACMA][1][44] = 66,
+ [0][0][1][0][RTW89_ACMA][0][44] = 30,
+ [0][0][1][0][RTW89_CHILE][1][44] = 22,
+ [0][0][1][0][RTW89_QATAR][1][44] = 66,
+ [0][0][1][0][RTW89_QATAR][0][44] = 30,
+ [0][0][1][0][RTW89_UK][1][44] = 66,
+ [0][0][1][0][RTW89_UK][0][44] = 30,
+ [0][0][1][0][RTW89_FCC][1][45] = 22,
+ [0][0][1][0][RTW89_FCC][2][45] = 127,
+ [0][0][1][0][RTW89_ETSI][1][45] = 127,
+ [0][0][1][0][RTW89_ETSI][0][45] = 127,
+ [0][0][1][0][RTW89_MKK][1][45] = 127,
+ [0][0][1][0][RTW89_MKK][0][45] = 127,
+ [0][0][1][0][RTW89_IC][1][45] = 22,
+ [0][0][1][0][RTW89_KCC][1][45] = 24,
+ [0][0][1][0][RTW89_KCC][0][45] = 127,
+ [0][0][1][0][RTW89_ACMA][1][45] = 127,
+ [0][0][1][0][RTW89_ACMA][0][45] = 127,
+ [0][0][1][0][RTW89_CHILE][1][45] = 22,
+ [0][0][1][0][RTW89_QATAR][1][45] = 127,
+ [0][0][1][0][RTW89_QATAR][0][45] = 127,
+ [0][0][1][0][RTW89_UK][1][45] = 127,
+ [0][0][1][0][RTW89_UK][0][45] = 127,
+ [0][0][1][0][RTW89_FCC][1][47] = 22,
+ [0][0][1][0][RTW89_FCC][2][47] = 127,
+ [0][0][1][0][RTW89_ETSI][1][47] = 127,
+ [0][0][1][0][RTW89_ETSI][0][47] = 127,
+ [0][0][1][0][RTW89_MKK][1][47] = 127,
+ [0][0][1][0][RTW89_MKK][0][47] = 127,
+ [0][0][1][0][RTW89_IC][1][47] = 22,
+ [0][0][1][0][RTW89_KCC][1][47] = 24,
+ [0][0][1][0][RTW89_KCC][0][47] = 127,
+ [0][0][1][0][RTW89_ACMA][1][47] = 127,
+ [0][0][1][0][RTW89_ACMA][0][47] = 127,
+ [0][0][1][0][RTW89_CHILE][1][47] = 22,
+ [0][0][1][0][RTW89_QATAR][1][47] = 127,
+ [0][0][1][0][RTW89_QATAR][0][47] = 127,
+ [0][0][1][0][RTW89_UK][1][47] = 127,
+ [0][0][1][0][RTW89_UK][0][47] = 127,
+ [0][0][1][0][RTW89_FCC][1][49] = 24,
+ [0][0][1][0][RTW89_FCC][2][49] = 127,
+ [0][0][1][0][RTW89_ETSI][1][49] = 127,
+ [0][0][1][0][RTW89_ETSI][0][49] = 127,
+ [0][0][1][0][RTW89_MKK][1][49] = 127,
+ [0][0][1][0][RTW89_MKK][0][49] = 127,
+ [0][0][1][0][RTW89_IC][1][49] = 24,
+ [0][0][1][0][RTW89_KCC][1][49] = 24,
+ [0][0][1][0][RTW89_KCC][0][49] = 127,
+ [0][0][1][0][RTW89_ACMA][1][49] = 127,
+ [0][0][1][0][RTW89_ACMA][0][49] = 127,
+ [0][0][1][0][RTW89_CHILE][1][49] = 24,
+ [0][0][1][0][RTW89_QATAR][1][49] = 127,
+ [0][0][1][0][RTW89_QATAR][0][49] = 127,
+ [0][0][1][0][RTW89_UK][1][49] = 127,
+ [0][0][1][0][RTW89_UK][0][49] = 127,
+ [0][0][1][0][RTW89_FCC][1][51] = 22,
+ [0][0][1][0][RTW89_FCC][2][51] = 127,
+ [0][0][1][0][RTW89_ETSI][1][51] = 127,
+ [0][0][1][0][RTW89_ETSI][0][51] = 127,
+ [0][0][1][0][RTW89_MKK][1][51] = 127,
+ [0][0][1][0][RTW89_MKK][0][51] = 127,
+ [0][0][1][0][RTW89_IC][1][51] = 22,
+ [0][0][1][0][RTW89_KCC][1][51] = 24,
+ [0][0][1][0][RTW89_KCC][0][51] = 127,
+ [0][0][1][0][RTW89_ACMA][1][51] = 127,
+ [0][0][1][0][RTW89_ACMA][0][51] = 127,
+ [0][0][1][0][RTW89_CHILE][1][51] = 22,
+ [0][0][1][0][RTW89_QATAR][1][51] = 127,
+ [0][0][1][0][RTW89_QATAR][0][51] = 127,
+ [0][0][1][0][RTW89_UK][1][51] = 127,
+ [0][0][1][0][RTW89_UK][0][51] = 127,
+ [0][0][1][0][RTW89_FCC][1][53] = 22,
+ [0][0][1][0][RTW89_FCC][2][53] = 127,
+ [0][0][1][0][RTW89_ETSI][1][53] = 127,
+ [0][0][1][0][RTW89_ETSI][0][53] = 127,
+ [0][0][1][0][RTW89_MKK][1][53] = 127,
+ [0][0][1][0][RTW89_MKK][0][53] = 127,
+ [0][0][1][0][RTW89_IC][1][53] = 22,
+ [0][0][1][0][RTW89_KCC][1][53] = 24,
+ [0][0][1][0][RTW89_KCC][0][53] = 127,
+ [0][0][1][0][RTW89_ACMA][1][53] = 127,
+ [0][0][1][0][RTW89_ACMA][0][53] = 127,
+ [0][0][1][0][RTW89_CHILE][1][53] = 22,
+ [0][0][1][0][RTW89_QATAR][1][53] = 127,
+ [0][0][1][0][RTW89_QATAR][0][53] = 127,
+ [0][0][1][0][RTW89_UK][1][53] = 127,
+ [0][0][1][0][RTW89_UK][0][53] = 127,
+ [0][0][1][0][RTW89_FCC][1][55] = 22,
+ [0][0][1][0][RTW89_FCC][2][55] = 68,
+ [0][0][1][0][RTW89_ETSI][1][55] = 127,
+ [0][0][1][0][RTW89_ETSI][0][55] = 127,
+ [0][0][1][0][RTW89_MKK][1][55] = 127,
+ [0][0][1][0][RTW89_MKK][0][55] = 127,
+ [0][0][1][0][RTW89_IC][1][55] = 22,
+ [0][0][1][0][RTW89_KCC][1][55] = 26,
+ [0][0][1][0][RTW89_KCC][0][55] = 127,
+ [0][0][1][0][RTW89_ACMA][1][55] = 127,
+ [0][0][1][0][RTW89_ACMA][0][55] = 127,
+ [0][0][1][0][RTW89_CHILE][1][55] = 22,
+ [0][0][1][0][RTW89_QATAR][1][55] = 127,
+ [0][0][1][0][RTW89_QATAR][0][55] = 127,
+ [0][0][1][0][RTW89_UK][1][55] = 127,
+ [0][0][1][0][RTW89_UK][0][55] = 127,
+ [0][0][1][0][RTW89_FCC][1][57] = 22,
+ [0][0][1][0][RTW89_FCC][2][57] = 68,
+ [0][0][1][0][RTW89_ETSI][1][57] = 127,
+ [0][0][1][0][RTW89_ETSI][0][57] = 127,
+ [0][0][1][0][RTW89_MKK][1][57] = 127,
+ [0][0][1][0][RTW89_MKK][0][57] = 127,
+ [0][0][1][0][RTW89_IC][1][57] = 22,
+ [0][0][1][0][RTW89_KCC][1][57] = 26,
+ [0][0][1][0][RTW89_KCC][0][57] = 127,
+ [0][0][1][0][RTW89_ACMA][1][57] = 127,
+ [0][0][1][0][RTW89_ACMA][0][57] = 127,
+ [0][0][1][0][RTW89_CHILE][1][57] = 22,
+ [0][0][1][0][RTW89_QATAR][1][57] = 127,
+ [0][0][1][0][RTW89_QATAR][0][57] = 127,
+ [0][0][1][0][RTW89_UK][1][57] = 127,
+ [0][0][1][0][RTW89_UK][0][57] = 127,
+ [0][0][1][0][RTW89_FCC][1][59] = 22,
+ [0][0][1][0][RTW89_FCC][2][59] = 68,
+ [0][0][1][0][RTW89_ETSI][1][59] = 127,
+ [0][0][1][0][RTW89_ETSI][0][59] = 127,
+ [0][0][1][0][RTW89_MKK][1][59] = 127,
+ [0][0][1][0][RTW89_MKK][0][59] = 127,
+ [0][0][1][0][RTW89_IC][1][59] = 22,
+ [0][0][1][0][RTW89_KCC][1][59] = 26,
+ [0][0][1][0][RTW89_KCC][0][59] = 127,
+ [0][0][1][0][RTW89_ACMA][1][59] = 127,
+ [0][0][1][0][RTW89_ACMA][0][59] = 127,
+ [0][0][1][0][RTW89_CHILE][1][59] = 22,
+ [0][0][1][0][RTW89_QATAR][1][59] = 127,
+ [0][0][1][0][RTW89_QATAR][0][59] = 127,
+ [0][0][1][0][RTW89_UK][1][59] = 127,
+ [0][0][1][0][RTW89_UK][0][59] = 127,
+ [0][0][1][0][RTW89_FCC][1][60] = 22,
+ [0][0][1][0][RTW89_FCC][2][60] = 68,
+ [0][0][1][0][RTW89_ETSI][1][60] = 127,
+ [0][0][1][0][RTW89_ETSI][0][60] = 127,
+ [0][0][1][0][RTW89_MKK][1][60] = 127,
+ [0][0][1][0][RTW89_MKK][0][60] = 127,
+ [0][0][1][0][RTW89_IC][1][60] = 22,
+ [0][0][1][0][RTW89_KCC][1][60] = 26,
+ [0][0][1][0][RTW89_KCC][0][60] = 127,
+ [0][0][1][0][RTW89_ACMA][1][60] = 127,
+ [0][0][1][0][RTW89_ACMA][0][60] = 127,
+ [0][0][1][0][RTW89_CHILE][1][60] = 22,
+ [0][0][1][0][RTW89_QATAR][1][60] = 127,
+ [0][0][1][0][RTW89_QATAR][0][60] = 127,
+ [0][0][1][0][RTW89_UK][1][60] = 127,
+ [0][0][1][0][RTW89_UK][0][60] = 127,
+ [0][0][1][0][RTW89_FCC][1][62] = 22,
+ [0][0][1][0][RTW89_FCC][2][62] = 68,
+ [0][0][1][0][RTW89_ETSI][1][62] = 127,
+ [0][0][1][0][RTW89_ETSI][0][62] = 127,
+ [0][0][1][0][RTW89_MKK][1][62] = 127,
+ [0][0][1][0][RTW89_MKK][0][62] = 127,
+ [0][0][1][0][RTW89_IC][1][62] = 22,
+ [0][0][1][0][RTW89_KCC][1][62] = 26,
+ [0][0][1][0][RTW89_KCC][0][62] = 127,
+ [0][0][1][0][RTW89_ACMA][1][62] = 127,
+ [0][0][1][0][RTW89_ACMA][0][62] = 127,
+ [0][0][1][0][RTW89_CHILE][1][62] = 22,
+ [0][0][1][0][RTW89_QATAR][1][62] = 127,
+ [0][0][1][0][RTW89_QATAR][0][62] = 127,
+ [0][0][1][0][RTW89_UK][1][62] = 127,
+ [0][0][1][0][RTW89_UK][0][62] = 127,
+ [0][0][1][0][RTW89_FCC][1][64] = 22,
+ [0][0][1][0][RTW89_FCC][2][64] = 68,
+ [0][0][1][0][RTW89_ETSI][1][64] = 127,
+ [0][0][1][0][RTW89_ETSI][0][64] = 127,
+ [0][0][1][0][RTW89_MKK][1][64] = 127,
+ [0][0][1][0][RTW89_MKK][0][64] = 127,
+ [0][0][1][0][RTW89_IC][1][64] = 22,
+ [0][0][1][0][RTW89_KCC][1][64] = 26,
+ [0][0][1][0][RTW89_KCC][0][64] = 127,
+ [0][0][1][0][RTW89_ACMA][1][64] = 127,
+ [0][0][1][0][RTW89_ACMA][0][64] = 127,
+ [0][0][1][0][RTW89_CHILE][1][64] = 22,
+ [0][0][1][0][RTW89_QATAR][1][64] = 127,
+ [0][0][1][0][RTW89_QATAR][0][64] = 127,
+ [0][0][1][0][RTW89_UK][1][64] = 127,
+ [0][0][1][0][RTW89_UK][0][64] = 127,
+ [0][0][1][0][RTW89_FCC][1][66] = 22,
+ [0][0][1][0][RTW89_FCC][2][66] = 68,
+ [0][0][1][0][RTW89_ETSI][1][66] = 127,
+ [0][0][1][0][RTW89_ETSI][0][66] = 127,
+ [0][0][1][0][RTW89_MKK][1][66] = 127,
+ [0][0][1][0][RTW89_MKK][0][66] = 127,
+ [0][0][1][0][RTW89_IC][1][66] = 22,
+ [0][0][1][0][RTW89_KCC][1][66] = 26,
+ [0][0][1][0][RTW89_KCC][0][66] = 127,
+ [0][0][1][0][RTW89_ACMA][1][66] = 127,
+ [0][0][1][0][RTW89_ACMA][0][66] = 127,
+ [0][0][1][0][RTW89_CHILE][1][66] = 22,
+ [0][0][1][0][RTW89_QATAR][1][66] = 127,
+ [0][0][1][0][RTW89_QATAR][0][66] = 127,
+ [0][0][1][0][RTW89_UK][1][66] = 127,
+ [0][0][1][0][RTW89_UK][0][66] = 127,
+ [0][0][1][0][RTW89_FCC][1][68] = 22,
+ [0][0][1][0][RTW89_FCC][2][68] = 68,
+ [0][0][1][0][RTW89_ETSI][1][68] = 127,
+ [0][0][1][0][RTW89_ETSI][0][68] = 127,
+ [0][0][1][0][RTW89_MKK][1][68] = 127,
+ [0][0][1][0][RTW89_MKK][0][68] = 127,
+ [0][0][1][0][RTW89_IC][1][68] = 22,
+ [0][0][1][0][RTW89_KCC][1][68] = 26,
+ [0][0][1][0][RTW89_KCC][0][68] = 127,
+ [0][0][1][0][RTW89_ACMA][1][68] = 127,
+ [0][0][1][0][RTW89_ACMA][0][68] = 127,
+ [0][0][1][0][RTW89_CHILE][1][68] = 22,
+ [0][0][1][0][RTW89_QATAR][1][68] = 127,
+ [0][0][1][0][RTW89_QATAR][0][68] = 127,
+ [0][0][1][0][RTW89_UK][1][68] = 127,
+ [0][0][1][0][RTW89_UK][0][68] = 127,
+ [0][0][1][0][RTW89_FCC][1][70] = 24,
+ [0][0][1][0][RTW89_FCC][2][70] = 68,
+ [0][0][1][0][RTW89_ETSI][1][70] = 127,
+ [0][0][1][0][RTW89_ETSI][0][70] = 127,
+ [0][0][1][0][RTW89_MKK][1][70] = 127,
+ [0][0][1][0][RTW89_MKK][0][70] = 127,
+ [0][0][1][0][RTW89_IC][1][70] = 24,
+ [0][0][1][0][RTW89_KCC][1][70] = 26,
+ [0][0][1][0][RTW89_KCC][0][70] = 127,
+ [0][0][1][0][RTW89_ACMA][1][70] = 127,
+ [0][0][1][0][RTW89_ACMA][0][70] = 127,
+ [0][0][1][0][RTW89_CHILE][1][70] = 24,
+ [0][0][1][0][RTW89_QATAR][1][70] = 127,
+ [0][0][1][0][RTW89_QATAR][0][70] = 127,
+ [0][0][1][0][RTW89_UK][1][70] = 127,
+ [0][0][1][0][RTW89_UK][0][70] = 127,
+ [0][0][1][0][RTW89_FCC][1][72] = 22,
+ [0][0][1][0][RTW89_FCC][2][72] = 68,
+ [0][0][1][0][RTW89_ETSI][1][72] = 127,
+ [0][0][1][0][RTW89_ETSI][0][72] = 127,
+ [0][0][1][0][RTW89_MKK][1][72] = 127,
+ [0][0][1][0][RTW89_MKK][0][72] = 127,
+ [0][0][1][0][RTW89_IC][1][72] = 22,
+ [0][0][1][0][RTW89_KCC][1][72] = 26,
+ [0][0][1][0][RTW89_KCC][0][72] = 127,
+ [0][0][1][0][RTW89_ACMA][1][72] = 127,
+ [0][0][1][0][RTW89_ACMA][0][72] = 127,
+ [0][0][1][0][RTW89_CHILE][1][72] = 22,
+ [0][0][1][0][RTW89_QATAR][1][72] = 127,
+ [0][0][1][0][RTW89_QATAR][0][72] = 127,
+ [0][0][1][0][RTW89_UK][1][72] = 127,
+ [0][0][1][0][RTW89_UK][0][72] = 127,
+ [0][0][1][0][RTW89_FCC][1][74] = 22,
+ [0][0][1][0][RTW89_FCC][2][74] = 68,
+ [0][0][1][0][RTW89_ETSI][1][74] = 127,
+ [0][0][1][0][RTW89_ETSI][0][74] = 127,
+ [0][0][1][0][RTW89_MKK][1][74] = 127,
+ [0][0][1][0][RTW89_MKK][0][74] = 127,
+ [0][0][1][0][RTW89_IC][1][74] = 22,
+ [0][0][1][0][RTW89_KCC][1][74] = 26,
+ [0][0][1][0][RTW89_KCC][0][74] = 127,
+ [0][0][1][0][RTW89_ACMA][1][74] = 127,
+ [0][0][1][0][RTW89_ACMA][0][74] = 127,
+ [0][0][1][0][RTW89_CHILE][1][74] = 22,
+ [0][0][1][0][RTW89_QATAR][1][74] = 127,
+ [0][0][1][0][RTW89_QATAR][0][74] = 127,
+ [0][0][1][0][RTW89_UK][1][74] = 127,
+ [0][0][1][0][RTW89_UK][0][74] = 127,
+ [0][0][1][0][RTW89_FCC][1][75] = 22,
+ [0][0][1][0][RTW89_FCC][2][75] = 68,
+ [0][0][1][0][RTW89_ETSI][1][75] = 127,
+ [0][0][1][0][RTW89_ETSI][0][75] = 127,
+ [0][0][1][0][RTW89_MKK][1][75] = 127,
+ [0][0][1][0][RTW89_MKK][0][75] = 127,
+ [0][0][1][0][RTW89_IC][1][75] = 22,
+ [0][0][1][0][RTW89_KCC][1][75] = 26,
+ [0][0][1][0][RTW89_KCC][0][75] = 127,
+ [0][0][1][0][RTW89_ACMA][1][75] = 127,
+ [0][0][1][0][RTW89_ACMA][0][75] = 127,
+ [0][0][1][0][RTW89_CHILE][1][75] = 22,
+ [0][0][1][0][RTW89_QATAR][1][75] = 127,
+ [0][0][1][0][RTW89_QATAR][0][75] = 127,
+ [0][0][1][0][RTW89_UK][1][75] = 127,
+ [0][0][1][0][RTW89_UK][0][75] = 127,
+ [0][0][1][0][RTW89_FCC][1][77] = 22,
+ [0][0][1][0][RTW89_FCC][2][77] = 68,
+ [0][0][1][0][RTW89_ETSI][1][77] = 127,
+ [0][0][1][0][RTW89_ETSI][0][77] = 127,
+ [0][0][1][0][RTW89_MKK][1][77] = 127,
+ [0][0][1][0][RTW89_MKK][0][77] = 127,
+ [0][0][1][0][RTW89_IC][1][77] = 22,
+ [0][0][1][0][RTW89_KCC][1][77] = 26,
+ [0][0][1][0][RTW89_KCC][0][77] = 127,
+ [0][0][1][0][RTW89_ACMA][1][77] = 127,
+ [0][0][1][0][RTW89_ACMA][0][77] = 127,
+ [0][0][1][0][RTW89_CHILE][1][77] = 22,
+ [0][0][1][0][RTW89_QATAR][1][77] = 127,
+ [0][0][1][0][RTW89_QATAR][0][77] = 127,
+ [0][0][1][0][RTW89_UK][1][77] = 127,
+ [0][0][1][0][RTW89_UK][0][77] = 127,
+ [0][0][1][0][RTW89_FCC][1][79] = 22,
+ [0][0][1][0][RTW89_FCC][2][79] = 68,
+ [0][0][1][0][RTW89_ETSI][1][79] = 127,
+ [0][0][1][0][RTW89_ETSI][0][79] = 127,
+ [0][0][1][0][RTW89_MKK][1][79] = 127,
+ [0][0][1][0][RTW89_MKK][0][79] = 127,
+ [0][0][1][0][RTW89_IC][1][79] = 22,
+ [0][0][1][0][RTW89_KCC][1][79] = 26,
+ [0][0][1][0][RTW89_KCC][0][79] = 127,
+ [0][0][1][0][RTW89_ACMA][1][79] = 127,
+ [0][0][1][0][RTW89_ACMA][0][79] = 127,
+ [0][0][1][0][RTW89_CHILE][1][79] = 22,
+ [0][0][1][0][RTW89_QATAR][1][79] = 127,
+ [0][0][1][0][RTW89_QATAR][0][79] = 127,
+ [0][0][1][0][RTW89_UK][1][79] = 127,
+ [0][0][1][0][RTW89_UK][0][79] = 127,
+ [0][0][1][0][RTW89_FCC][1][81] = 22,
+ [0][0][1][0][RTW89_FCC][2][81] = 68,
+ [0][0][1][0][RTW89_ETSI][1][81] = 127,
+ [0][0][1][0][RTW89_ETSI][0][81] = 127,
+ [0][0][1][0][RTW89_MKK][1][81] = 127,
+ [0][0][1][0][RTW89_MKK][0][81] = 127,
+ [0][0][1][0][RTW89_IC][1][81] = 22,
+ [0][0][1][0][RTW89_KCC][1][81] = 26,
+ [0][0][1][0][RTW89_KCC][0][81] = 127,
+ [0][0][1][0][RTW89_ACMA][1][81] = 127,
+ [0][0][1][0][RTW89_ACMA][0][81] = 127,
+ [0][0][1][0][RTW89_CHILE][1][81] = 22,
+ [0][0][1][0][RTW89_QATAR][1][81] = 127,
+ [0][0][1][0][RTW89_QATAR][0][81] = 127,
+ [0][0][1][0][RTW89_UK][1][81] = 127,
+ [0][0][1][0][RTW89_UK][0][81] = 127,
+ [0][0][1][0][RTW89_FCC][1][83] = 22,
+ [0][0][1][0][RTW89_FCC][2][83] = 68,
+ [0][0][1][0][RTW89_ETSI][1][83] = 127,
+ [0][0][1][0][RTW89_ETSI][0][83] = 127,
+ [0][0][1][0][RTW89_MKK][1][83] = 127,
+ [0][0][1][0][RTW89_MKK][0][83] = 127,
+ [0][0][1][0][RTW89_IC][1][83] = 22,
+ [0][0][1][0][RTW89_KCC][1][83] = 32,
+ [0][0][1][0][RTW89_KCC][0][83] = 127,
+ [0][0][1][0][RTW89_ACMA][1][83] = 127,
+ [0][0][1][0][RTW89_ACMA][0][83] = 127,
+ [0][0][1][0][RTW89_CHILE][1][83] = 22,
+ [0][0][1][0][RTW89_QATAR][1][83] = 127,
+ [0][0][1][0][RTW89_QATAR][0][83] = 127,
+ [0][0][1][0][RTW89_UK][1][83] = 127,
+ [0][0][1][0][RTW89_UK][0][83] = 127,
+ [0][0][1][0][RTW89_FCC][1][85] = 22,
+ [0][0][1][0][RTW89_FCC][2][85] = 68,
+ [0][0][1][0][RTW89_ETSI][1][85] = 127,
+ [0][0][1][0][RTW89_ETSI][0][85] = 127,
+ [0][0][1][0][RTW89_MKK][1][85] = 127,
+ [0][0][1][0][RTW89_MKK][0][85] = 127,
+ [0][0][1][0][RTW89_IC][1][85] = 22,
+ [0][0][1][0][RTW89_KCC][1][85] = 32,
+ [0][0][1][0][RTW89_KCC][0][85] = 127,
+ [0][0][1][0][RTW89_ACMA][1][85] = 127,
+ [0][0][1][0][RTW89_ACMA][0][85] = 127,
+ [0][0][1][0][RTW89_CHILE][1][85] = 22,
+ [0][0][1][0][RTW89_QATAR][1][85] = 127,
+ [0][0][1][0][RTW89_QATAR][0][85] = 127,
+ [0][0][1][0][RTW89_UK][1][85] = 127,
+ [0][0][1][0][RTW89_UK][0][85] = 127,
+ [0][0][1][0][RTW89_FCC][1][87] = 22,
+ [0][0][1][0][RTW89_FCC][2][87] = 127,
+ [0][0][1][0][RTW89_ETSI][1][87] = 127,
+ [0][0][1][0][RTW89_ETSI][0][87] = 127,
+ [0][0][1][0][RTW89_MKK][1][87] = 127,
+ [0][0][1][0][RTW89_MKK][0][87] = 127,
+ [0][0][1][0][RTW89_IC][1][87] = 22,
+ [0][0][1][0][RTW89_KCC][1][87] = 32,
+ [0][0][1][0][RTW89_KCC][0][87] = 127,
+ [0][0][1][0][RTW89_ACMA][1][87] = 127,
+ [0][0][1][0][RTW89_ACMA][0][87] = 127,
+ [0][0][1][0][RTW89_CHILE][1][87] = 22,
+ [0][0][1][0][RTW89_QATAR][1][87] = 127,
+ [0][0][1][0][RTW89_QATAR][0][87] = 127,
+ [0][0][1][0][RTW89_UK][1][87] = 127,
+ [0][0][1][0][RTW89_UK][0][87] = 127,
+ [0][0][1][0][RTW89_FCC][1][89] = 22,
+ [0][0][1][0][RTW89_FCC][2][89] = 127,
+ [0][0][1][0][RTW89_ETSI][1][89] = 127,
+ [0][0][1][0][RTW89_ETSI][0][89] = 127,
+ [0][0][1][0][RTW89_MKK][1][89] = 127,
+ [0][0][1][0][RTW89_MKK][0][89] = 127,
+ [0][0][1][0][RTW89_IC][1][89] = 22,
+ [0][0][1][0][RTW89_KCC][1][89] = 32,
+ [0][0][1][0][RTW89_KCC][0][89] = 127,
+ [0][0][1][0][RTW89_ACMA][1][89] = 127,
+ [0][0][1][0][RTW89_ACMA][0][89] = 127,
+ [0][0][1][0][RTW89_CHILE][1][89] = 22,
+ [0][0][1][0][RTW89_QATAR][1][89] = 127,
+ [0][0][1][0][RTW89_QATAR][0][89] = 127,
+ [0][0][1][0][RTW89_UK][1][89] = 127,
+ [0][0][1][0][RTW89_UK][0][89] = 127,
+ [0][0][1][0][RTW89_FCC][1][90] = 22,
+ [0][0][1][0][RTW89_FCC][2][90] = 127,
+ [0][0][1][0][RTW89_ETSI][1][90] = 127,
+ [0][0][1][0][RTW89_ETSI][0][90] = 127,
+ [0][0][1][0][RTW89_MKK][1][90] = 127,
+ [0][0][1][0][RTW89_MKK][0][90] = 127,
+ [0][0][1][0][RTW89_IC][1][90] = 22,
+ [0][0][1][0][RTW89_KCC][1][90] = 32,
+ [0][0][1][0][RTW89_KCC][0][90] = 127,
+ [0][0][1][0][RTW89_ACMA][1][90] = 127,
+ [0][0][1][0][RTW89_ACMA][0][90] = 127,
+ [0][0][1][0][RTW89_CHILE][1][90] = 22,
+ [0][0][1][0][RTW89_QATAR][1][90] = 127,
+ [0][0][1][0][RTW89_QATAR][0][90] = 127,
+ [0][0][1][0][RTW89_UK][1][90] = 127,
+ [0][0][1][0][RTW89_UK][0][90] = 127,
+ [0][0][1][0][RTW89_FCC][1][92] = 22,
+ [0][0][1][0][RTW89_FCC][2][92] = 127,
+ [0][0][1][0][RTW89_ETSI][1][92] = 127,
+ [0][0][1][0][RTW89_ETSI][0][92] = 127,
+ [0][0][1][0][RTW89_MKK][1][92] = 127,
+ [0][0][1][0][RTW89_MKK][0][92] = 127,
+ [0][0][1][0][RTW89_IC][1][92] = 22,
+ [0][0][1][0][RTW89_KCC][1][92] = 32,
+ [0][0][1][0][RTW89_KCC][0][92] = 127,
+ [0][0][1][0][RTW89_ACMA][1][92] = 127,
+ [0][0][1][0][RTW89_ACMA][0][92] = 127,
+ [0][0][1][0][RTW89_CHILE][1][92] = 22,
+ [0][0][1][0][RTW89_QATAR][1][92] = 127,
+ [0][0][1][0][RTW89_QATAR][0][92] = 127,
+ [0][0][1][0][RTW89_UK][1][92] = 127,
+ [0][0][1][0][RTW89_UK][0][92] = 127,
+ [0][0][1][0][RTW89_FCC][1][94] = 22,
+ [0][0][1][0][RTW89_FCC][2][94] = 127,
+ [0][0][1][0][RTW89_ETSI][1][94] = 127,
+ [0][0][1][0][RTW89_ETSI][0][94] = 127,
+ [0][0][1][0][RTW89_MKK][1][94] = 127,
+ [0][0][1][0][RTW89_MKK][0][94] = 127,
+ [0][0][1][0][RTW89_IC][1][94] = 22,
+ [0][0][1][0][RTW89_KCC][1][94] = 32,
+ [0][0][1][0][RTW89_KCC][0][94] = 127,
+ [0][0][1][0][RTW89_ACMA][1][94] = 127,
+ [0][0][1][0][RTW89_ACMA][0][94] = 127,
+ [0][0][1][0][RTW89_CHILE][1][94] = 22,
+ [0][0][1][0][RTW89_QATAR][1][94] = 127,
+ [0][0][1][0][RTW89_QATAR][0][94] = 127,
+ [0][0][1][0][RTW89_UK][1][94] = 127,
+ [0][0][1][0][RTW89_UK][0][94] = 127,
+ [0][0][1][0][RTW89_FCC][1][96] = 22,
+ [0][0][1][0][RTW89_FCC][2][96] = 127,
+ [0][0][1][0][RTW89_ETSI][1][96] = 127,
+ [0][0][1][0][RTW89_ETSI][0][96] = 127,
+ [0][0][1][0][RTW89_MKK][1][96] = 127,
+ [0][0][1][0][RTW89_MKK][0][96] = 127,
+ [0][0][1][0][RTW89_IC][1][96] = 22,
+ [0][0][1][0][RTW89_KCC][1][96] = 32,
+ [0][0][1][0][RTW89_KCC][0][96] = 127,
+ [0][0][1][0][RTW89_ACMA][1][96] = 127,
+ [0][0][1][0][RTW89_ACMA][0][96] = 127,
+ [0][0][1][0][RTW89_CHILE][1][96] = 22,
+ [0][0][1][0][RTW89_QATAR][1][96] = 127,
+ [0][0][1][0][RTW89_QATAR][0][96] = 127,
+ [0][0][1][0][RTW89_UK][1][96] = 127,
+ [0][0][1][0][RTW89_UK][0][96] = 127,
+ [0][0][1][0][RTW89_FCC][1][98] = 22,
+ [0][0][1][0][RTW89_FCC][2][98] = 127,
+ [0][0][1][0][RTW89_ETSI][1][98] = 127,
+ [0][0][1][0][RTW89_ETSI][0][98] = 127,
+ [0][0][1][0][RTW89_MKK][1][98] = 127,
+ [0][0][1][0][RTW89_MKK][0][98] = 127,
+ [0][0][1][0][RTW89_IC][1][98] = 22,
+ [0][0][1][0][RTW89_KCC][1][98] = 32,
+ [0][0][1][0][RTW89_KCC][0][98] = 127,
+ [0][0][1][0][RTW89_ACMA][1][98] = 127,
+ [0][0][1][0][RTW89_ACMA][0][98] = 127,
+ [0][0][1][0][RTW89_CHILE][1][98] = 22,
+ [0][0][1][0][RTW89_QATAR][1][98] = 127,
+ [0][0][1][0][RTW89_QATAR][0][98] = 127,
+ [0][0][1][0][RTW89_UK][1][98] = 127,
+ [0][0][1][0][RTW89_UK][0][98] = 127,
+ [0][0][1][0][RTW89_FCC][1][100] = 22,
+ [0][0][1][0][RTW89_FCC][2][100] = 127,
+ [0][0][1][0][RTW89_ETSI][1][100] = 127,
+ [0][0][1][0][RTW89_ETSI][0][100] = 127,
+ [0][0][1][0][RTW89_MKK][1][100] = 127,
+ [0][0][1][0][RTW89_MKK][0][100] = 127,
+ [0][0][1][0][RTW89_IC][1][100] = 22,
+ [0][0][1][0][RTW89_KCC][1][100] = 32,
+ [0][0][1][0][RTW89_KCC][0][100] = 127,
+ [0][0][1][0][RTW89_ACMA][1][100] = 127,
+ [0][0][1][0][RTW89_ACMA][0][100] = 127,
+ [0][0][1][0][RTW89_CHILE][1][100] = 22,
+ [0][0][1][0][RTW89_QATAR][1][100] = 127,
+ [0][0][1][0][RTW89_QATAR][0][100] = 127,
+ [0][0][1][0][RTW89_UK][1][100] = 127,
+ [0][0][1][0][RTW89_UK][0][100] = 127,
+ [0][0][1][0][RTW89_FCC][1][102] = 22,
+ [0][0][1][0][RTW89_FCC][2][102] = 127,
+ [0][0][1][0][RTW89_ETSI][1][102] = 127,
+ [0][0][1][0][RTW89_ETSI][0][102] = 127,
+ [0][0][1][0][RTW89_MKK][1][102] = 127,
+ [0][0][1][0][RTW89_MKK][0][102] = 127,
+ [0][0][1][0][RTW89_IC][1][102] = 22,
+ [0][0][1][0][RTW89_KCC][1][102] = 32,
+ [0][0][1][0][RTW89_KCC][0][102] = 127,
+ [0][0][1][0][RTW89_ACMA][1][102] = 127,
+ [0][0][1][0][RTW89_ACMA][0][102] = 127,
+ [0][0][1][0][RTW89_CHILE][1][102] = 22,
+ [0][0][1][0][RTW89_QATAR][1][102] = 127,
+ [0][0][1][0][RTW89_QATAR][0][102] = 127,
+ [0][0][1][0][RTW89_UK][1][102] = 127,
+ [0][0][1][0][RTW89_UK][0][102] = 127,
+ [0][0][1][0][RTW89_FCC][1][104] = 22,
+ [0][0][1][0][RTW89_FCC][2][104] = 127,
+ [0][0][1][0][RTW89_ETSI][1][104] = 127,
+ [0][0][1][0][RTW89_ETSI][0][104] = 127,
+ [0][0][1][0][RTW89_MKK][1][104] = 127,
+ [0][0][1][0][RTW89_MKK][0][104] = 127,
+ [0][0][1][0][RTW89_IC][1][104] = 22,
+ [0][0][1][0][RTW89_KCC][1][104] = 32,
+ [0][0][1][0][RTW89_KCC][0][104] = 127,
+ [0][0][1][0][RTW89_ACMA][1][104] = 127,
+ [0][0][1][0][RTW89_ACMA][0][104] = 127,
+ [0][0][1][0][RTW89_CHILE][1][104] = 22,
+ [0][0][1][0][RTW89_QATAR][1][104] = 127,
+ [0][0][1][0][RTW89_QATAR][0][104] = 127,
+ [0][0][1][0][RTW89_UK][1][104] = 127,
+ [0][0][1][0][RTW89_UK][0][104] = 127,
+ [0][0][1][0][RTW89_FCC][1][105] = 22,
+ [0][0][1][0][RTW89_FCC][2][105] = 127,
+ [0][0][1][0][RTW89_ETSI][1][105] = 127,
+ [0][0][1][0][RTW89_ETSI][0][105] = 127,
+ [0][0][1][0][RTW89_MKK][1][105] = 127,
+ [0][0][1][0][RTW89_MKK][0][105] = 127,
+ [0][0][1][0][RTW89_IC][1][105] = 22,
+ [0][0][1][0][RTW89_KCC][1][105] = 32,
+ [0][0][1][0][RTW89_KCC][0][105] = 127,
+ [0][0][1][0][RTW89_ACMA][1][105] = 127,
+ [0][0][1][0][RTW89_ACMA][0][105] = 127,
+ [0][0][1][0][RTW89_CHILE][1][105] = 22,
+ [0][0][1][0][RTW89_QATAR][1][105] = 127,
+ [0][0][1][0][RTW89_QATAR][0][105] = 127,
+ [0][0][1][0][RTW89_UK][1][105] = 127,
+ [0][0][1][0][RTW89_UK][0][105] = 127,
+ [0][0][1][0][RTW89_FCC][1][107] = 24,
+ [0][0][1][0][RTW89_FCC][2][107] = 127,
+ [0][0][1][0][RTW89_ETSI][1][107] = 127,
+ [0][0][1][0][RTW89_ETSI][0][107] = 127,
+ [0][0][1][0][RTW89_MKK][1][107] = 127,
+ [0][0][1][0][RTW89_MKK][0][107] = 127,
+ [0][0][1][0][RTW89_IC][1][107] = 24,
+ [0][0][1][0][RTW89_KCC][1][107] = 32,
+ [0][0][1][0][RTW89_KCC][0][107] = 127,
+ [0][0][1][0][RTW89_ACMA][1][107] = 127,
+ [0][0][1][0][RTW89_ACMA][0][107] = 127,
+ [0][0][1][0][RTW89_CHILE][1][107] = 24,
+ [0][0][1][0][RTW89_QATAR][1][107] = 127,
+ [0][0][1][0][RTW89_QATAR][0][107] = 127,
+ [0][0][1][0][RTW89_UK][1][107] = 127,
+ [0][0][1][0][RTW89_UK][0][107] = 127,
+ [0][0][1][0][RTW89_FCC][1][109] = 24,
+ [0][0][1][0][RTW89_FCC][2][109] = 127,
+ [0][0][1][0][RTW89_ETSI][1][109] = 127,
+ [0][0][1][0][RTW89_ETSI][0][109] = 127,
+ [0][0][1][0][RTW89_MKK][1][109] = 127,
+ [0][0][1][0][RTW89_MKK][0][109] = 127,
+ [0][0][1][0][RTW89_IC][1][109] = 24,
+ [0][0][1][0][RTW89_KCC][1][109] = 32,
+ [0][0][1][0][RTW89_KCC][0][109] = 127,
+ [0][0][1][0][RTW89_ACMA][1][109] = 127,
+ [0][0][1][0][RTW89_ACMA][0][109] = 127,
+ [0][0][1][0][RTW89_CHILE][1][109] = 24,
+ [0][0][1][0][RTW89_QATAR][1][109] = 127,
+ [0][0][1][0][RTW89_QATAR][0][109] = 127,
+ [0][0][1][0][RTW89_UK][1][109] = 127,
+ [0][0][1][0][RTW89_UK][0][109] = 127,
+ [0][0][1][0][RTW89_FCC][1][111] = 127,
+ [0][0][1][0][RTW89_FCC][2][111] = 127,
+ [0][0][1][0][RTW89_ETSI][1][111] = 127,
+ [0][0][1][0][RTW89_ETSI][0][111] = 127,
+ [0][0][1][0][RTW89_MKK][1][111] = 127,
+ [0][0][1][0][RTW89_MKK][0][111] = 127,
+ [0][0][1][0][RTW89_IC][1][111] = 127,
+ [0][0][1][0][RTW89_KCC][1][111] = 127,
+ [0][0][1][0][RTW89_KCC][0][111] = 127,
+ [0][0][1][0][RTW89_ACMA][1][111] = 127,
+ [0][0][1][0][RTW89_ACMA][0][111] = 127,
+ [0][0][1][0][RTW89_CHILE][1][111] = 127,
+ [0][0][1][0][RTW89_QATAR][1][111] = 127,
+ [0][0][1][0][RTW89_QATAR][0][111] = 127,
+ [0][0][1][0][RTW89_UK][1][111] = 127,
+ [0][0][1][0][RTW89_UK][0][111] = 127,
+ [0][0][1][0][RTW89_FCC][1][113] = 127,
+ [0][0][1][0][RTW89_FCC][2][113] = 127,
+ [0][0][1][0][RTW89_ETSI][1][113] = 127,
+ [0][0][1][0][RTW89_ETSI][0][113] = 127,
+ [0][0][1][0][RTW89_MKK][1][113] = 127,
+ [0][0][1][0][RTW89_MKK][0][113] = 127,
+ [0][0][1][0][RTW89_IC][1][113] = 127,
+ [0][0][1][0][RTW89_KCC][1][113] = 127,
+ [0][0][1][0][RTW89_KCC][0][113] = 127,
+ [0][0][1][0][RTW89_ACMA][1][113] = 127,
+ [0][0][1][0][RTW89_ACMA][0][113] = 127,
+ [0][0][1][0][RTW89_CHILE][1][113] = 127,
+ [0][0][1][0][RTW89_QATAR][1][113] = 127,
+ [0][0][1][0][RTW89_QATAR][0][113] = 127,
+ [0][0][1][0][RTW89_UK][1][113] = 127,
+ [0][0][1][0][RTW89_UK][0][113] = 127,
+ [0][0][1][0][RTW89_FCC][1][115] = 127,
+ [0][0][1][0][RTW89_FCC][2][115] = 127,
+ [0][0][1][0][RTW89_ETSI][1][115] = 127,
+ [0][0][1][0][RTW89_ETSI][0][115] = 127,
+ [0][0][1][0][RTW89_MKK][1][115] = 127,
+ [0][0][1][0][RTW89_MKK][0][115] = 127,
+ [0][0][1][0][RTW89_IC][1][115] = 127,
+ [0][0][1][0][RTW89_KCC][1][115] = 127,
+ [0][0][1][0][RTW89_KCC][0][115] = 127,
+ [0][0][1][0][RTW89_ACMA][1][115] = 127,
+ [0][0][1][0][RTW89_ACMA][0][115] = 127,
+ [0][0][1][0][RTW89_CHILE][1][115] = 127,
+ [0][0][1][0][RTW89_QATAR][1][115] = 127,
+ [0][0][1][0][RTW89_QATAR][0][115] = 127,
+ [0][0][1][0][RTW89_UK][1][115] = 127,
+ [0][0][1][0][RTW89_UK][0][115] = 127,
+ [0][0][1][0][RTW89_FCC][1][117] = 127,
+ [0][0][1][0][RTW89_FCC][2][117] = 127,
+ [0][0][1][0][RTW89_ETSI][1][117] = 127,
+ [0][0][1][0][RTW89_ETSI][0][117] = 127,
+ [0][0][1][0][RTW89_MKK][1][117] = 127,
+ [0][0][1][0][RTW89_MKK][0][117] = 127,
+ [0][0][1][0][RTW89_IC][1][117] = 127,
+ [0][0][1][0][RTW89_KCC][1][117] = 127,
+ [0][0][1][0][RTW89_KCC][0][117] = 127,
+ [0][0][1][0][RTW89_ACMA][1][117] = 127,
+ [0][0][1][0][RTW89_ACMA][0][117] = 127,
+ [0][0][1][0][RTW89_CHILE][1][117] = 127,
+ [0][0][1][0][RTW89_QATAR][1][117] = 127,
+ [0][0][1][0][RTW89_QATAR][0][117] = 127,
+ [0][0][1][0][RTW89_UK][1][117] = 127,
+ [0][0][1][0][RTW89_UK][0][117] = 127,
+ [0][0][1][0][RTW89_FCC][1][119] = 127,
+ [0][0][1][0][RTW89_FCC][2][119] = 127,
+ [0][0][1][0][RTW89_ETSI][1][119] = 127,
+ [0][0][1][0][RTW89_ETSI][0][119] = 127,
+ [0][0][1][0][RTW89_MKK][1][119] = 127,
+ [0][0][1][0][RTW89_MKK][0][119] = 127,
+ [0][0][1][0][RTW89_IC][1][119] = 127,
+ [0][0][1][0][RTW89_KCC][1][119] = 127,
+ [0][0][1][0][RTW89_KCC][0][119] = 127,
+ [0][0][1][0][RTW89_ACMA][1][119] = 127,
+ [0][0][1][0][RTW89_ACMA][0][119] = 127,
+ [0][0][1][0][RTW89_CHILE][1][119] = 127,
+ [0][0][1][0][RTW89_QATAR][1][119] = 127,
+ [0][0][1][0][RTW89_QATAR][0][119] = 127,
+ [0][0][1][0][RTW89_UK][1][119] = 127,
+ [0][0][1][0][RTW89_UK][0][119] = 127,
+ [0][1][1][0][RTW89_FCC][1][0] = -2,
+ [0][1][1][0][RTW89_FCC][2][0] = 54,
+ [0][1][1][0][RTW89_ETSI][1][0] = 54,
+ [0][1][1][0][RTW89_ETSI][0][0] = 18,
+ [0][1][1][0][RTW89_MKK][1][0] = 56,
+ [0][1][1][0][RTW89_MKK][0][0] = 16,
+ [0][1][1][0][RTW89_IC][1][0] = -2,
+ [0][1][1][0][RTW89_KCC][1][0] = 12,
+ [0][1][1][0][RTW89_KCC][0][0] = 10,
+ [0][1][1][0][RTW89_ACMA][1][0] = 54,
+ [0][1][1][0][RTW89_ACMA][0][0] = 18,
+ [0][1][1][0][RTW89_CHILE][1][0] = -2,
+ [0][1][1][0][RTW89_QATAR][1][0] = 54,
+ [0][1][1][0][RTW89_QATAR][0][0] = 18,
+ [0][1][1][0][RTW89_UK][1][0] = 54,
+ [0][1][1][0][RTW89_UK][0][0] = 18,
+ [0][1][1][0][RTW89_FCC][1][2] = -4,
+ [0][1][1][0][RTW89_FCC][2][2] = 54,
+ [0][1][1][0][RTW89_ETSI][1][2] = 54,
+ [0][1][1][0][RTW89_ETSI][0][2] = 18,
+ [0][1][1][0][RTW89_MKK][1][2] = 54,
+ [0][1][1][0][RTW89_MKK][0][2] = 16,
+ [0][1][1][0][RTW89_IC][1][2] = -4,
+ [0][1][1][0][RTW89_KCC][1][2] = 12,
+ [0][1][1][0][RTW89_KCC][0][2] = 12,
+ [0][1][1][0][RTW89_ACMA][1][2] = 54,
+ [0][1][1][0][RTW89_ACMA][0][2] = 18,
+ [0][1][1][0][RTW89_CHILE][1][2] = -4,
+ [0][1][1][0][RTW89_QATAR][1][2] = 54,
+ [0][1][1][0][RTW89_QATAR][0][2] = 18,
+ [0][1][1][0][RTW89_UK][1][2] = 54,
+ [0][1][1][0][RTW89_UK][0][2] = 18,
+ [0][1][1][0][RTW89_FCC][1][4] = -4,
+ [0][1][1][0][RTW89_FCC][2][4] = 54,
+ [0][1][1][0][RTW89_ETSI][1][4] = 54,
+ [0][1][1][0][RTW89_ETSI][0][4] = 18,
+ [0][1][1][0][RTW89_MKK][1][4] = 54,
+ [0][1][1][0][RTW89_MKK][0][4] = 16,
+ [0][1][1][0][RTW89_IC][1][4] = -4,
+ [0][1][1][0][RTW89_KCC][1][4] = 12,
+ [0][1][1][0][RTW89_KCC][0][4] = 12,
+ [0][1][1][0][RTW89_ACMA][1][4] = 54,
+ [0][1][1][0][RTW89_ACMA][0][4] = 18,
+ [0][1][1][0][RTW89_CHILE][1][4] = -4,
+ [0][1][1][0][RTW89_QATAR][1][4] = 54,
+ [0][1][1][0][RTW89_QATAR][0][4] = 18,
+ [0][1][1][0][RTW89_UK][1][4] = 54,
+ [0][1][1][0][RTW89_UK][0][4] = 18,
+ [0][1][1][0][RTW89_FCC][1][6] = -4,
+ [0][1][1][0][RTW89_FCC][2][6] = 54,
+ [0][1][1][0][RTW89_ETSI][1][6] = 54,
+ [0][1][1][0][RTW89_ETSI][0][6] = 18,
+ [0][1][1][0][RTW89_MKK][1][6] = 54,
+ [0][1][1][0][RTW89_MKK][0][6] = 16,
+ [0][1][1][0][RTW89_IC][1][6] = -4,
+ [0][1][1][0][RTW89_KCC][1][6] = 12,
+ [0][1][1][0][RTW89_KCC][0][6] = 12,
+ [0][1][1][0][RTW89_ACMA][1][6] = 54,
+ [0][1][1][0][RTW89_ACMA][0][6] = 18,
+ [0][1][1][0][RTW89_CHILE][1][6] = -4,
+ [0][1][1][0][RTW89_QATAR][1][6] = 54,
+ [0][1][1][0][RTW89_QATAR][0][6] = 18,
+ [0][1][1][0][RTW89_UK][1][6] = 54,
+ [0][1][1][0][RTW89_UK][0][6] = 18,
+ [0][1][1][0][RTW89_FCC][1][8] = -4,
+ [0][1][1][0][RTW89_FCC][2][8] = 54,
+ [0][1][1][0][RTW89_ETSI][1][8] = 54,
+ [0][1][1][0][RTW89_ETSI][0][8] = 18,
+ [0][1][1][0][RTW89_MKK][1][8] = 54,
+ [0][1][1][0][RTW89_MKK][0][8] = 16,
+ [0][1][1][0][RTW89_IC][1][8] = -4,
+ [0][1][1][0][RTW89_KCC][1][8] = 12,
+ [0][1][1][0][RTW89_KCC][0][8] = 12,
+ [0][1][1][0][RTW89_ACMA][1][8] = 54,
+ [0][1][1][0][RTW89_ACMA][0][8] = 18,
+ [0][1][1][0][RTW89_CHILE][1][8] = -4,
+ [0][1][1][0][RTW89_QATAR][1][8] = 54,
+ [0][1][1][0][RTW89_QATAR][0][8] = 18,
+ [0][1][1][0][RTW89_UK][1][8] = 54,
+ [0][1][1][0][RTW89_UK][0][8] = 18,
+ [0][1][1][0][RTW89_FCC][1][10] = -4,
+ [0][1][1][0][RTW89_FCC][2][10] = 54,
+ [0][1][1][0][RTW89_ETSI][1][10] = 54,
+ [0][1][1][0][RTW89_ETSI][0][10] = 18,
+ [0][1][1][0][RTW89_MKK][1][10] = 54,
+ [0][1][1][0][RTW89_MKK][0][10] = 16,
+ [0][1][1][0][RTW89_IC][1][10] = -4,
+ [0][1][1][0][RTW89_KCC][1][10] = 12,
+ [0][1][1][0][RTW89_KCC][0][10] = 12,
+ [0][1][1][0][RTW89_ACMA][1][10] = 54,
+ [0][1][1][0][RTW89_ACMA][0][10] = 18,
+ [0][1][1][0][RTW89_CHILE][1][10] = -4,
+ [0][1][1][0][RTW89_QATAR][1][10] = 54,
+ [0][1][1][0][RTW89_QATAR][0][10] = 18,
+ [0][1][1][0][RTW89_UK][1][10] = 54,
+ [0][1][1][0][RTW89_UK][0][10] = 18,
+ [0][1][1][0][RTW89_FCC][1][12] = -4,
+ [0][1][1][0][RTW89_FCC][2][12] = 54,
+ [0][1][1][0][RTW89_ETSI][1][12] = 54,
+ [0][1][1][0][RTW89_ETSI][0][12] = 18,
+ [0][1][1][0][RTW89_MKK][1][12] = 54,
+ [0][1][1][0][RTW89_MKK][0][12] = 16,
+ [0][1][1][0][RTW89_IC][1][12] = -4,
+ [0][1][1][0][RTW89_KCC][1][12] = 12,
+ [0][1][1][0][RTW89_KCC][0][12] = 12,
+ [0][1][1][0][RTW89_ACMA][1][12] = 54,
+ [0][1][1][0][RTW89_ACMA][0][12] = 18,
+ [0][1][1][0][RTW89_CHILE][1][12] = -4,
+ [0][1][1][0][RTW89_QATAR][1][12] = 54,
+ [0][1][1][0][RTW89_QATAR][0][12] = 18,
+ [0][1][1][0][RTW89_UK][1][12] = 54,
+ [0][1][1][0][RTW89_UK][0][12] = 18,
+ [0][1][1][0][RTW89_FCC][1][14] = -4,
+ [0][1][1][0][RTW89_FCC][2][14] = 54,
+ [0][1][1][0][RTW89_ETSI][1][14] = 54,
+ [0][1][1][0][RTW89_ETSI][0][14] = 18,
+ [0][1][1][0][RTW89_MKK][1][14] = 54,
+ [0][1][1][0][RTW89_MKK][0][14] = 16,
+ [0][1][1][0][RTW89_IC][1][14] = -4,
+ [0][1][1][0][RTW89_KCC][1][14] = 12,
+ [0][1][1][0][RTW89_KCC][0][14] = 12,
+ [0][1][1][0][RTW89_ACMA][1][14] = 54,
+ [0][1][1][0][RTW89_ACMA][0][14] = 18,
+ [0][1][1][0][RTW89_CHILE][1][14] = -4,
+ [0][1][1][0][RTW89_QATAR][1][14] = 54,
+ [0][1][1][0][RTW89_QATAR][0][14] = 18,
+ [0][1][1][0][RTW89_UK][1][14] = 54,
+ [0][1][1][0][RTW89_UK][0][14] = 18,
+ [0][1][1][0][RTW89_FCC][1][15] = -4,
+ [0][1][1][0][RTW89_FCC][2][15] = 54,
+ [0][1][1][0][RTW89_ETSI][1][15] = 54,
+ [0][1][1][0][RTW89_ETSI][0][15] = 18,
+ [0][1][1][0][RTW89_MKK][1][15] = 54,
+ [0][1][1][0][RTW89_MKK][0][15] = 16,
+ [0][1][1][0][RTW89_IC][1][15] = -4,
+ [0][1][1][0][RTW89_KCC][1][15] = 12,
+ [0][1][1][0][RTW89_KCC][0][15] = 12,
+ [0][1][1][0][RTW89_ACMA][1][15] = 54,
+ [0][1][1][0][RTW89_ACMA][0][15] = 18,
+ [0][1][1][0][RTW89_CHILE][1][15] = -4,
+ [0][1][1][0][RTW89_QATAR][1][15] = 54,
+ [0][1][1][0][RTW89_QATAR][0][15] = 18,
+ [0][1][1][0][RTW89_UK][1][15] = 54,
+ [0][1][1][0][RTW89_UK][0][15] = 18,
+ [0][1][1][0][RTW89_FCC][1][17] = -4,
+ [0][1][1][0][RTW89_FCC][2][17] = 54,
+ [0][1][1][0][RTW89_ETSI][1][17] = 54,
+ [0][1][1][0][RTW89_ETSI][0][17] = 18,
+ [0][1][1][0][RTW89_MKK][1][17] = 54,
+ [0][1][1][0][RTW89_MKK][0][17] = 16,
+ [0][1][1][0][RTW89_IC][1][17] = -4,
+ [0][1][1][0][RTW89_KCC][1][17] = 12,
+ [0][1][1][0][RTW89_KCC][0][17] = 12,
+ [0][1][1][0][RTW89_ACMA][1][17] = 54,
+ [0][1][1][0][RTW89_ACMA][0][17] = 18,
+ [0][1][1][0][RTW89_CHILE][1][17] = -4,
+ [0][1][1][0][RTW89_QATAR][1][17] = 54,
+ [0][1][1][0][RTW89_QATAR][0][17] = 18,
+ [0][1][1][0][RTW89_UK][1][17] = 54,
+ [0][1][1][0][RTW89_UK][0][17] = 18,
+ [0][1][1][0][RTW89_FCC][1][19] = -4,
+ [0][1][1][0][RTW89_FCC][2][19] = 54,
+ [0][1][1][0][RTW89_ETSI][1][19] = 54,
+ [0][1][1][0][RTW89_ETSI][0][19] = 18,
+ [0][1][1][0][RTW89_MKK][1][19] = 54,
+ [0][1][1][0][RTW89_MKK][0][19] = 16,
+ [0][1][1][0][RTW89_IC][1][19] = -4,
+ [0][1][1][0][RTW89_KCC][1][19] = 12,
+ [0][1][1][0][RTW89_KCC][0][19] = 12,
+ [0][1][1][0][RTW89_ACMA][1][19] = 54,
+ [0][1][1][0][RTW89_ACMA][0][19] = 18,
+ [0][1][1][0][RTW89_CHILE][1][19] = -4,
+ [0][1][1][0][RTW89_QATAR][1][19] = 54,
+ [0][1][1][0][RTW89_QATAR][0][19] = 18,
+ [0][1][1][0][RTW89_UK][1][19] = 54,
+ [0][1][1][0][RTW89_UK][0][19] = 18,
+ [0][1][1][0][RTW89_FCC][1][21] = -4,
+ [0][1][1][0][RTW89_FCC][2][21] = 54,
+ [0][1][1][0][RTW89_ETSI][1][21] = 54,
+ [0][1][1][0][RTW89_ETSI][0][21] = 18,
+ [0][1][1][0][RTW89_MKK][1][21] = 54,
+ [0][1][1][0][RTW89_MKK][0][21] = 16,
+ [0][1][1][0][RTW89_IC][1][21] = -4,
+ [0][1][1][0][RTW89_KCC][1][21] = 12,
+ [0][1][1][0][RTW89_KCC][0][21] = 12,
+ [0][1][1][0][RTW89_ACMA][1][21] = 54,
+ [0][1][1][0][RTW89_ACMA][0][21] = 18,
+ [0][1][1][0][RTW89_CHILE][1][21] = -4,
+ [0][1][1][0][RTW89_QATAR][1][21] = 54,
+ [0][1][1][0][RTW89_QATAR][0][21] = 18,
+ [0][1][1][0][RTW89_UK][1][21] = 54,
+ [0][1][1][0][RTW89_UK][0][21] = 18,
+ [0][1][1][0][RTW89_FCC][1][23] = -4,
+ [0][1][1][0][RTW89_FCC][2][23] = 68,
+ [0][1][1][0][RTW89_ETSI][1][23] = 54,
+ [0][1][1][0][RTW89_ETSI][0][23] = 18,
+ [0][1][1][0][RTW89_MKK][1][23] = 54,
+ [0][1][1][0][RTW89_MKK][0][23] = 16,
+ [0][1][1][0][RTW89_IC][1][23] = -4,
+ [0][1][1][0][RTW89_KCC][1][23] = 12,
+ [0][1][1][0][RTW89_KCC][0][23] = 10,
+ [0][1][1][0][RTW89_ACMA][1][23] = 54,
+ [0][1][1][0][RTW89_ACMA][0][23] = 18,
+ [0][1][1][0][RTW89_CHILE][1][23] = -4,
+ [0][1][1][0][RTW89_QATAR][1][23] = 54,
+ [0][1][1][0][RTW89_QATAR][0][23] = 18,
+ [0][1][1][0][RTW89_UK][1][23] = 54,
+ [0][1][1][0][RTW89_UK][0][23] = 18,
+ [0][1][1][0][RTW89_FCC][1][25] = -4,
+ [0][1][1][0][RTW89_FCC][2][25] = 68,
+ [0][1][1][0][RTW89_ETSI][1][25] = 54,
+ [0][1][1][0][RTW89_ETSI][0][25] = 18,
+ [0][1][1][0][RTW89_MKK][1][25] = 54,
+ [0][1][1][0][RTW89_MKK][0][25] = 16,
+ [0][1][1][0][RTW89_IC][1][25] = -4,
+ [0][1][1][0][RTW89_KCC][1][25] = 12,
+ [0][1][1][0][RTW89_KCC][0][25] = 14,
+ [0][1][1][0][RTW89_ACMA][1][25] = 54,
+ [0][1][1][0][RTW89_ACMA][0][25] = 18,
+ [0][1][1][0][RTW89_CHILE][1][25] = -4,
+ [0][1][1][0][RTW89_QATAR][1][25] = 54,
+ [0][1][1][0][RTW89_QATAR][0][25] = 18,
+ [0][1][1][0][RTW89_UK][1][25] = 54,
+ [0][1][1][0][RTW89_UK][0][25] = 18,
+ [0][1][1][0][RTW89_FCC][1][27] = -4,
+ [0][1][1][0][RTW89_FCC][2][27] = 68,
+ [0][1][1][0][RTW89_ETSI][1][27] = 54,
+ [0][1][1][0][RTW89_ETSI][0][27] = 18,
+ [0][1][1][0][RTW89_MKK][1][27] = 54,
+ [0][1][1][0][RTW89_MKK][0][27] = 16,
+ [0][1][1][0][RTW89_IC][1][27] = -4,
+ [0][1][1][0][RTW89_KCC][1][27] = 12,
+ [0][1][1][0][RTW89_KCC][0][27] = 14,
+ [0][1][1][0][RTW89_ACMA][1][27] = 54,
+ [0][1][1][0][RTW89_ACMA][0][27] = 18,
+ [0][1][1][0][RTW89_CHILE][1][27] = -4,
+ [0][1][1][0][RTW89_QATAR][1][27] = 54,
+ [0][1][1][0][RTW89_QATAR][0][27] = 18,
+ [0][1][1][0][RTW89_UK][1][27] = 54,
+ [0][1][1][0][RTW89_UK][0][27] = 18,
+ [0][1][1][0][RTW89_FCC][1][29] = -4,
+ [0][1][1][0][RTW89_FCC][2][29] = 68,
+ [0][1][1][0][RTW89_ETSI][1][29] = 54,
+ [0][1][1][0][RTW89_ETSI][0][29] = 18,
+ [0][1][1][0][RTW89_MKK][1][29] = 54,
+ [0][1][1][0][RTW89_MKK][0][29] = 16,
+ [0][1][1][0][RTW89_IC][1][29] = -4,
+ [0][1][1][0][RTW89_KCC][1][29] = 12,
+ [0][1][1][0][RTW89_KCC][0][29] = 14,
+ [0][1][1][0][RTW89_ACMA][1][29] = 54,
+ [0][1][1][0][RTW89_ACMA][0][29] = 18,
+ [0][1][1][0][RTW89_CHILE][1][29] = -4,
+ [0][1][1][0][RTW89_QATAR][1][29] = 54,
+ [0][1][1][0][RTW89_QATAR][0][29] = 18,
+ [0][1][1][0][RTW89_UK][1][29] = 54,
+ [0][1][1][0][RTW89_UK][0][29] = 18,
+ [0][1][1][0][RTW89_FCC][1][30] = -4,
+ [0][1][1][0][RTW89_FCC][2][30] = 68,
+ [0][1][1][0][RTW89_ETSI][1][30] = 54,
+ [0][1][1][0][RTW89_ETSI][0][30] = 18,
+ [0][1][1][0][RTW89_MKK][1][30] = 54,
+ [0][1][1][0][RTW89_MKK][0][30] = 16,
+ [0][1][1][0][RTW89_IC][1][30] = -4,
+ [0][1][1][0][RTW89_KCC][1][30] = 12,
+ [0][1][1][0][RTW89_KCC][0][30] = 14,
+ [0][1][1][0][RTW89_ACMA][1][30] = 54,
+ [0][1][1][0][RTW89_ACMA][0][30] = 18,
+ [0][1][1][0][RTW89_CHILE][1][30] = -4,
+ [0][1][1][0][RTW89_QATAR][1][30] = 54,
+ [0][1][1][0][RTW89_QATAR][0][30] = 18,
+ [0][1][1][0][RTW89_UK][1][30] = 54,
+ [0][1][1][0][RTW89_UK][0][30] = 18,
+ [0][1][1][0][RTW89_FCC][1][32] = -4,
+ [0][1][1][0][RTW89_FCC][2][32] = 68,
+ [0][1][1][0][RTW89_ETSI][1][32] = 54,
+ [0][1][1][0][RTW89_ETSI][0][32] = 18,
+ [0][1][1][0][RTW89_MKK][1][32] = 54,
+ [0][1][1][0][RTW89_MKK][0][32] = 16,
+ [0][1][1][0][RTW89_IC][1][32] = -4,
+ [0][1][1][0][RTW89_KCC][1][32] = 12,
+ [0][1][1][0][RTW89_KCC][0][32] = 14,
+ [0][1][1][0][RTW89_ACMA][1][32] = 54,
+ [0][1][1][0][RTW89_ACMA][0][32] = 18,
+ [0][1][1][0][RTW89_CHILE][1][32] = -4,
+ [0][1][1][0][RTW89_QATAR][1][32] = 54,
+ [0][1][1][0][RTW89_QATAR][0][32] = 18,
+ [0][1][1][0][RTW89_UK][1][32] = 54,
+ [0][1][1][0][RTW89_UK][0][32] = 18,
+ [0][1][1][0][RTW89_FCC][1][34] = -4,
+ [0][1][1][0][RTW89_FCC][2][34] = 68,
+ [0][1][1][0][RTW89_ETSI][1][34] = 54,
+ [0][1][1][0][RTW89_ETSI][0][34] = 18,
+ [0][1][1][0][RTW89_MKK][1][34] = 54,
+ [0][1][1][0][RTW89_MKK][0][34] = 16,
+ [0][1][1][0][RTW89_IC][1][34] = -4,
+ [0][1][1][0][RTW89_KCC][1][34] = 12,
+ [0][1][1][0][RTW89_KCC][0][34] = 14,
+ [0][1][1][0][RTW89_ACMA][1][34] = 54,
+ [0][1][1][0][RTW89_ACMA][0][34] = 18,
+ [0][1][1][0][RTW89_CHILE][1][34] = -4,
+ [0][1][1][0][RTW89_QATAR][1][34] = 54,
+ [0][1][1][0][RTW89_QATAR][0][34] = 18,
+ [0][1][1][0][RTW89_UK][1][34] = 54,
+ [0][1][1][0][RTW89_UK][0][34] = 18,
+ [0][1][1][0][RTW89_FCC][1][36] = -4,
+ [0][1][1][0][RTW89_FCC][2][36] = 68,
+ [0][1][1][0][RTW89_ETSI][1][36] = 54,
+ [0][1][1][0][RTW89_ETSI][0][36] = 18,
+ [0][1][1][0][RTW89_MKK][1][36] = 54,
+ [0][1][1][0][RTW89_MKK][0][36] = 16,
+ [0][1][1][0][RTW89_IC][1][36] = -4,
+ [0][1][1][0][RTW89_KCC][1][36] = 12,
+ [0][1][1][0][RTW89_KCC][0][36] = 14,
+ [0][1][1][0][RTW89_ACMA][1][36] = 54,
+ [0][1][1][0][RTW89_ACMA][0][36] = 18,
+ [0][1][1][0][RTW89_CHILE][1][36] = -4,
+ [0][1][1][0][RTW89_QATAR][1][36] = 54,
+ [0][1][1][0][RTW89_QATAR][0][36] = 18,
+ [0][1][1][0][RTW89_UK][1][36] = 54,
+ [0][1][1][0][RTW89_UK][0][36] = 18,
+ [0][1][1][0][RTW89_FCC][1][38] = -4,
+ [0][1][1][0][RTW89_FCC][2][38] = 68,
+ [0][1][1][0][RTW89_ETSI][1][38] = 54,
+ [0][1][1][0][RTW89_ETSI][0][38] = 18,
+ [0][1][1][0][RTW89_MKK][1][38] = 54,
+ [0][1][1][0][RTW89_MKK][0][38] = 16,
+ [0][1][1][0][RTW89_IC][1][38] = -4,
+ [0][1][1][0][RTW89_KCC][1][38] = 12,
+ [0][1][1][0][RTW89_KCC][0][38] = 14,
+ [0][1][1][0][RTW89_ACMA][1][38] = 54,
+ [0][1][1][0][RTW89_ACMA][0][38] = 18,
+ [0][1][1][0][RTW89_CHILE][1][38] = -4,
+ [0][1][1][0][RTW89_QATAR][1][38] = 54,
+ [0][1][1][0][RTW89_QATAR][0][38] = 18,
+ [0][1][1][0][RTW89_UK][1][38] = 54,
+ [0][1][1][0][RTW89_UK][0][38] = 18,
+ [0][1][1][0][RTW89_FCC][1][40] = -4,
+ [0][1][1][0][RTW89_FCC][2][40] = 68,
+ [0][1][1][0][RTW89_ETSI][1][40] = 54,
+ [0][1][1][0][RTW89_ETSI][0][40] = 18,
+ [0][1][1][0][RTW89_MKK][1][40] = 54,
+ [0][1][1][0][RTW89_MKK][0][40] = 16,
+ [0][1][1][0][RTW89_IC][1][40] = -4,
+ [0][1][1][0][RTW89_KCC][1][40] = 12,
+ [0][1][1][0][RTW89_KCC][0][40] = 14,
+ [0][1][1][0][RTW89_ACMA][1][40] = 54,
+ [0][1][1][0][RTW89_ACMA][0][40] = 18,
+ [0][1][1][0][RTW89_CHILE][1][40] = -4,
+ [0][1][1][0][RTW89_QATAR][1][40] = 54,
+ [0][1][1][0][RTW89_QATAR][0][40] = 18,
+ [0][1][1][0][RTW89_UK][1][40] = 54,
+ [0][1][1][0][RTW89_UK][0][40] = 18,
+ [0][1][1][0][RTW89_FCC][1][42] = -4,
+ [0][1][1][0][RTW89_FCC][2][42] = 68,
+ [0][1][1][0][RTW89_ETSI][1][42] = 54,
+ [0][1][1][0][RTW89_ETSI][0][42] = 18,
+ [0][1][1][0][RTW89_MKK][1][42] = 54,
+ [0][1][1][0][RTW89_MKK][0][42] = 16,
+ [0][1][1][0][RTW89_IC][1][42] = -4,
+ [0][1][1][0][RTW89_KCC][1][42] = 12,
+ [0][1][1][0][RTW89_KCC][0][42] = 14,
+ [0][1][1][0][RTW89_ACMA][1][42] = 54,
+ [0][1][1][0][RTW89_ACMA][0][42] = 18,
+ [0][1][1][0][RTW89_CHILE][1][42] = -4,
+ [0][1][1][0][RTW89_QATAR][1][42] = 54,
+ [0][1][1][0][RTW89_QATAR][0][42] = 18,
+ [0][1][1][0][RTW89_UK][1][42] = 54,
+ [0][1][1][0][RTW89_UK][0][42] = 18,
+ [0][1][1][0][RTW89_FCC][1][44] = -2,
+ [0][1][1][0][RTW89_FCC][2][44] = 68,
+ [0][1][1][0][RTW89_ETSI][1][44] = 54,
+ [0][1][1][0][RTW89_ETSI][0][44] = 18,
+ [0][1][1][0][RTW89_MKK][1][44] = 34,
+ [0][1][1][0][RTW89_MKK][0][44] = 16,
+ [0][1][1][0][RTW89_IC][1][44] = -2,
+ [0][1][1][0][RTW89_KCC][1][44] = 12,
+ [0][1][1][0][RTW89_KCC][0][44] = 12,
+ [0][1][1][0][RTW89_ACMA][1][44] = 54,
+ [0][1][1][0][RTW89_ACMA][0][44] = 18,
+ [0][1][1][0][RTW89_CHILE][1][44] = -2,
+ [0][1][1][0][RTW89_QATAR][1][44] = 54,
+ [0][1][1][0][RTW89_QATAR][0][44] = 18,
+ [0][1][1][0][RTW89_UK][1][44] = 54,
+ [0][1][1][0][RTW89_UK][0][44] = 18,
+ [0][1][1][0][RTW89_FCC][1][45] = -2,
+ [0][1][1][0][RTW89_FCC][2][45] = 127,
+ [0][1][1][0][RTW89_ETSI][1][45] = 127,
+ [0][1][1][0][RTW89_ETSI][0][45] = 127,
+ [0][1][1][0][RTW89_MKK][1][45] = 127,
+ [0][1][1][0][RTW89_MKK][0][45] = 127,
+ [0][1][1][0][RTW89_IC][1][45] = -2,
+ [0][1][1][0][RTW89_KCC][1][45] = 12,
+ [0][1][1][0][RTW89_KCC][0][45] = 127,
+ [0][1][1][0][RTW89_ACMA][1][45] = 127,
+ [0][1][1][0][RTW89_ACMA][0][45] = 127,
+ [0][1][1][0][RTW89_CHILE][1][45] = -2,
+ [0][1][1][0][RTW89_QATAR][1][45] = 127,
+ [0][1][1][0][RTW89_QATAR][0][45] = 127,
+ [0][1][1][0][RTW89_UK][1][45] = 127,
+ [0][1][1][0][RTW89_UK][0][45] = 127,
+ [0][1][1][0][RTW89_FCC][1][47] = -2,
+ [0][1][1][0][RTW89_FCC][2][47] = 127,
+ [0][1][1][0][RTW89_ETSI][1][47] = 127,
+ [0][1][1][0][RTW89_ETSI][0][47] = 127,
+ [0][1][1][0][RTW89_MKK][1][47] = 127,
+ [0][1][1][0][RTW89_MKK][0][47] = 127,
+ [0][1][1][0][RTW89_IC][1][47] = -2,
+ [0][1][1][0][RTW89_KCC][1][47] = 12,
+ [0][1][1][0][RTW89_KCC][0][47] = 127,
+ [0][1][1][0][RTW89_ACMA][1][47] = 127,
+ [0][1][1][0][RTW89_ACMA][0][47] = 127,
+ [0][1][1][0][RTW89_CHILE][1][47] = -2,
+ [0][1][1][0][RTW89_QATAR][1][47] = 127,
+ [0][1][1][0][RTW89_QATAR][0][47] = 127,
+ [0][1][1][0][RTW89_UK][1][47] = 127,
+ [0][1][1][0][RTW89_UK][0][47] = 127,
+ [0][1][1][0][RTW89_FCC][1][49] = -2,
+ [0][1][1][0][RTW89_FCC][2][49] = 127,
+ [0][1][1][0][RTW89_ETSI][1][49] = 127,
+ [0][1][1][0][RTW89_ETSI][0][49] = 127,
+ [0][1][1][0][RTW89_MKK][1][49] = 127,
+ [0][1][1][0][RTW89_MKK][0][49] = 127,
+ [0][1][1][0][RTW89_IC][1][49] = -2,
+ [0][1][1][0][RTW89_KCC][1][49] = 12,
+ [0][1][1][0][RTW89_KCC][0][49] = 127,
+ [0][1][1][0][RTW89_ACMA][1][49] = 127,
+ [0][1][1][0][RTW89_ACMA][0][49] = 127,
+ [0][1][1][0][RTW89_CHILE][1][49] = -2,
+ [0][1][1][0][RTW89_QATAR][1][49] = 127,
+ [0][1][1][0][RTW89_QATAR][0][49] = 127,
+ [0][1][1][0][RTW89_UK][1][49] = 127,
+ [0][1][1][0][RTW89_UK][0][49] = 127,
+ [0][1][1][0][RTW89_FCC][1][51] = -2,
+ [0][1][1][0][RTW89_FCC][2][51] = 127,
+ [0][1][1][0][RTW89_ETSI][1][51] = 127,
+ [0][1][1][0][RTW89_ETSI][0][51] = 127,
+ [0][1][1][0][RTW89_MKK][1][51] = 127,
+ [0][1][1][0][RTW89_MKK][0][51] = 127,
+ [0][1][1][0][RTW89_IC][1][51] = -2,
+ [0][1][1][0][RTW89_KCC][1][51] = 12,
+ [0][1][1][0][RTW89_KCC][0][51] = 127,
+ [0][1][1][0][RTW89_ACMA][1][51] = 127,
+ [0][1][1][0][RTW89_ACMA][0][51] = 127,
+ [0][1][1][0][RTW89_CHILE][1][51] = -2,
+ [0][1][1][0][RTW89_QATAR][1][51] = 127,
+ [0][1][1][0][RTW89_QATAR][0][51] = 127,
+ [0][1][1][0][RTW89_UK][1][51] = 127,
+ [0][1][1][0][RTW89_UK][0][51] = 127,
+ [0][1][1][0][RTW89_FCC][1][53] = -2,
+ [0][1][1][0][RTW89_FCC][2][53] = 127,
+ [0][1][1][0][RTW89_ETSI][1][53] = 127,
+ [0][1][1][0][RTW89_ETSI][0][53] = 127,
+ [0][1][1][0][RTW89_MKK][1][53] = 127,
+ [0][1][1][0][RTW89_MKK][0][53] = 127,
+ [0][1][1][0][RTW89_IC][1][53] = -2,
+ [0][1][1][0][RTW89_KCC][1][53] = 12,
+ [0][1][1][0][RTW89_KCC][0][53] = 127,
+ [0][1][1][0][RTW89_ACMA][1][53] = 127,
+ [0][1][1][0][RTW89_ACMA][0][53] = 127,
+ [0][1][1][0][RTW89_CHILE][1][53] = -2,
+ [0][1][1][0][RTW89_QATAR][1][53] = 127,
+ [0][1][1][0][RTW89_QATAR][0][53] = 127,
+ [0][1][1][0][RTW89_UK][1][53] = 127,
+ [0][1][1][0][RTW89_UK][0][53] = 127,
+ [0][1][1][0][RTW89_FCC][1][55] = -2,
+ [0][1][1][0][RTW89_FCC][2][55] = 68,
+ [0][1][1][0][RTW89_ETSI][1][55] = 127,
+ [0][1][1][0][RTW89_ETSI][0][55] = 127,
+ [0][1][1][0][RTW89_MKK][1][55] = 127,
+ [0][1][1][0][RTW89_MKK][0][55] = 127,
+ [0][1][1][0][RTW89_IC][1][55] = -2,
+ [0][1][1][0][RTW89_KCC][1][55] = 12,
+ [0][1][1][0][RTW89_KCC][0][55] = 127,
+ [0][1][1][0][RTW89_ACMA][1][55] = 127,
+ [0][1][1][0][RTW89_ACMA][0][55] = 127,
+ [0][1][1][0][RTW89_CHILE][1][55] = -2,
+ [0][1][1][0][RTW89_QATAR][1][55] = 127,
+ [0][1][1][0][RTW89_QATAR][0][55] = 127,
+ [0][1][1][0][RTW89_UK][1][55] = 127,
+ [0][1][1][0][RTW89_UK][0][55] = 127,
+ [0][1][1][0][RTW89_FCC][1][57] = -2,
+ [0][1][1][0][RTW89_FCC][2][57] = 68,
+ [0][1][1][0][RTW89_ETSI][1][57] = 127,
+ [0][1][1][0][RTW89_ETSI][0][57] = 127,
+ [0][1][1][0][RTW89_MKK][1][57] = 127,
+ [0][1][1][0][RTW89_MKK][0][57] = 127,
+ [0][1][1][0][RTW89_IC][1][57] = -2,
+ [0][1][1][0][RTW89_KCC][1][57] = 12,
+ [0][1][1][0][RTW89_KCC][0][57] = 127,
+ [0][1][1][0][RTW89_ACMA][1][57] = 127,
+ [0][1][1][0][RTW89_ACMA][0][57] = 127,
+ [0][1][1][0][RTW89_CHILE][1][57] = -2,
+ [0][1][1][0][RTW89_QATAR][1][57] = 127,
+ [0][1][1][0][RTW89_QATAR][0][57] = 127,
+ [0][1][1][0][RTW89_UK][1][57] = 127,
+ [0][1][1][0][RTW89_UK][0][57] = 127,
+ [0][1][1][0][RTW89_FCC][1][59] = -2,
+ [0][1][1][0][RTW89_FCC][2][59] = 68,
+ [0][1][1][0][RTW89_ETSI][1][59] = 127,
+ [0][1][1][0][RTW89_ETSI][0][59] = 127,
+ [0][1][1][0][RTW89_MKK][1][59] = 127,
+ [0][1][1][0][RTW89_MKK][0][59] = 127,
+ [0][1][1][0][RTW89_IC][1][59] = -2,
+ [0][1][1][0][RTW89_KCC][1][59] = 12,
+ [0][1][1][0][RTW89_KCC][0][59] = 127,
+ [0][1][1][0][RTW89_ACMA][1][59] = 127,
+ [0][1][1][0][RTW89_ACMA][0][59] = 127,
+ [0][1][1][0][RTW89_CHILE][1][59] = -2,
+ [0][1][1][0][RTW89_QATAR][1][59] = 127,
+ [0][1][1][0][RTW89_QATAR][0][59] = 127,
+ [0][1][1][0][RTW89_UK][1][59] = 127,
+ [0][1][1][0][RTW89_UK][0][59] = 127,
+ [0][1][1][0][RTW89_FCC][1][60] = -2,
+ [0][1][1][0][RTW89_FCC][2][60] = 68,
+ [0][1][1][0][RTW89_ETSI][1][60] = 127,
+ [0][1][1][0][RTW89_ETSI][0][60] = 127,
+ [0][1][1][0][RTW89_MKK][1][60] = 127,
+ [0][1][1][0][RTW89_MKK][0][60] = 127,
+ [0][1][1][0][RTW89_IC][1][60] = -2,
+ [0][1][1][0][RTW89_KCC][1][60] = 12,
+ [0][1][1][0][RTW89_KCC][0][60] = 127,
+ [0][1][1][0][RTW89_ACMA][1][60] = 127,
+ [0][1][1][0][RTW89_ACMA][0][60] = 127,
+ [0][1][1][0][RTW89_CHILE][1][60] = -2,
+ [0][1][1][0][RTW89_QATAR][1][60] = 127,
+ [0][1][1][0][RTW89_QATAR][0][60] = 127,
+ [0][1][1][0][RTW89_UK][1][60] = 127,
+ [0][1][1][0][RTW89_UK][0][60] = 127,
+ [0][1][1][0][RTW89_FCC][1][62] = -2,
+ [0][1][1][0][RTW89_FCC][2][62] = 68,
+ [0][1][1][0][RTW89_ETSI][1][62] = 127,
+ [0][1][1][0][RTW89_ETSI][0][62] = 127,
+ [0][1][1][0][RTW89_MKK][1][62] = 127,
+ [0][1][1][0][RTW89_MKK][0][62] = 127,
+ [0][1][1][0][RTW89_IC][1][62] = -2,
+ [0][1][1][0][RTW89_KCC][1][62] = 12,
+ [0][1][1][0][RTW89_KCC][0][62] = 127,
+ [0][1][1][0][RTW89_ACMA][1][62] = 127,
+ [0][1][1][0][RTW89_ACMA][0][62] = 127,
+ [0][1][1][0][RTW89_CHILE][1][62] = -2,
+ [0][1][1][0][RTW89_QATAR][1][62] = 127,
+ [0][1][1][0][RTW89_QATAR][0][62] = 127,
+ [0][1][1][0][RTW89_UK][1][62] = 127,
+ [0][1][1][0][RTW89_UK][0][62] = 127,
+ [0][1][1][0][RTW89_FCC][1][64] = -2,
+ [0][1][1][0][RTW89_FCC][2][64] = 68,
+ [0][1][1][0][RTW89_ETSI][1][64] = 127,
+ [0][1][1][0][RTW89_ETSI][0][64] = 127,
+ [0][1][1][0][RTW89_MKK][1][64] = 127,
+ [0][1][1][0][RTW89_MKK][0][64] = 127,
+ [0][1][1][0][RTW89_IC][1][64] = -2,
+ [0][1][1][0][RTW89_KCC][1][64] = 12,
+ [0][1][1][0][RTW89_KCC][0][64] = 127,
+ [0][1][1][0][RTW89_ACMA][1][64] = 127,
+ [0][1][1][0][RTW89_ACMA][0][64] = 127,
+ [0][1][1][0][RTW89_CHILE][1][64] = -2,
+ [0][1][1][0][RTW89_QATAR][1][64] = 127,
+ [0][1][1][0][RTW89_QATAR][0][64] = 127,
+ [0][1][1][0][RTW89_UK][1][64] = 127,
+ [0][1][1][0][RTW89_UK][0][64] = 127,
+ [0][1][1][0][RTW89_FCC][1][66] = -2,
+ [0][1][1][0][RTW89_FCC][2][66] = 68,
+ [0][1][1][0][RTW89_ETSI][1][66] = 127,
+ [0][1][1][0][RTW89_ETSI][0][66] = 127,
+ [0][1][1][0][RTW89_MKK][1][66] = 127,
+ [0][1][1][0][RTW89_MKK][0][66] = 127,
+ [0][1][1][0][RTW89_IC][1][66] = -2,
+ [0][1][1][0][RTW89_KCC][1][66] = 12,
+ [0][1][1][0][RTW89_KCC][0][66] = 127,
+ [0][1][1][0][RTW89_ACMA][1][66] = 127,
+ [0][1][1][0][RTW89_ACMA][0][66] = 127,
+ [0][1][1][0][RTW89_CHILE][1][66] = -2,
+ [0][1][1][0][RTW89_QATAR][1][66] = 127,
+ [0][1][1][0][RTW89_QATAR][0][66] = 127,
+ [0][1][1][0][RTW89_UK][1][66] = 127,
+ [0][1][1][0][RTW89_UK][0][66] = 127,
+ [0][1][1][0][RTW89_FCC][1][68] = -2,
+ [0][1][1][0][RTW89_FCC][2][68] = 68,
+ [0][1][1][0][RTW89_ETSI][1][68] = 127,
+ [0][1][1][0][RTW89_ETSI][0][68] = 127,
+ [0][1][1][0][RTW89_MKK][1][68] = 127,
+ [0][1][1][0][RTW89_MKK][0][68] = 127,
+ [0][1][1][0][RTW89_IC][1][68] = -2,
+ [0][1][1][0][RTW89_KCC][1][68] = 12,
+ [0][1][1][0][RTW89_KCC][0][68] = 127,
+ [0][1][1][0][RTW89_ACMA][1][68] = 127,
+ [0][1][1][0][RTW89_ACMA][0][68] = 127,
+ [0][1][1][0][RTW89_CHILE][1][68] = -2,
+ [0][1][1][0][RTW89_QATAR][1][68] = 127,
+ [0][1][1][0][RTW89_QATAR][0][68] = 127,
+ [0][1][1][0][RTW89_UK][1][68] = 127,
+ [0][1][1][0][RTW89_UK][0][68] = 127,
+ [0][1][1][0][RTW89_FCC][1][70] = -2,
+ [0][1][1][0][RTW89_FCC][2][70] = 68,
+ [0][1][1][0][RTW89_ETSI][1][70] = 127,
+ [0][1][1][0][RTW89_ETSI][0][70] = 127,
+ [0][1][1][0][RTW89_MKK][1][70] = 127,
+ [0][1][1][0][RTW89_MKK][0][70] = 127,
+ [0][1][1][0][RTW89_IC][1][70] = -2,
+ [0][1][1][0][RTW89_KCC][1][70] = 12,
+ [0][1][1][0][RTW89_KCC][0][70] = 127,
+ [0][1][1][0][RTW89_ACMA][1][70] = 127,
+ [0][1][1][0][RTW89_ACMA][0][70] = 127,
+ [0][1][1][0][RTW89_CHILE][1][70] = -2,
+ [0][1][1][0][RTW89_QATAR][1][70] = 127,
+ [0][1][1][0][RTW89_QATAR][0][70] = 127,
+ [0][1][1][0][RTW89_UK][1][70] = 127,
+ [0][1][1][0][RTW89_UK][0][70] = 127,
+ [0][1][1][0][RTW89_FCC][1][72] = -2,
+ [0][1][1][0][RTW89_FCC][2][72] = 68,
+ [0][1][1][0][RTW89_ETSI][1][72] = 127,
+ [0][1][1][0][RTW89_ETSI][0][72] = 127,
+ [0][1][1][0][RTW89_MKK][1][72] = 127,
+ [0][1][1][0][RTW89_MKK][0][72] = 127,
+ [0][1][1][0][RTW89_IC][1][72] = -2,
+ [0][1][1][0][RTW89_KCC][1][72] = 12,
+ [0][1][1][0][RTW89_KCC][0][72] = 127,
+ [0][1][1][0][RTW89_ACMA][1][72] = 127,
+ [0][1][1][0][RTW89_ACMA][0][72] = 127,
+ [0][1][1][0][RTW89_CHILE][1][72] = -2,
+ [0][1][1][0][RTW89_QATAR][1][72] = 127,
+ [0][1][1][0][RTW89_QATAR][0][72] = 127,
+ [0][1][1][0][RTW89_UK][1][72] = 127,
+ [0][1][1][0][RTW89_UK][0][72] = 127,
+ [0][1][1][0][RTW89_FCC][1][74] = -2,
+ [0][1][1][0][RTW89_FCC][2][74] = 68,
+ [0][1][1][0][RTW89_ETSI][1][74] = 127,
+ [0][1][1][0][RTW89_ETSI][0][74] = 127,
+ [0][1][1][0][RTW89_MKK][1][74] = 127,
+ [0][1][1][0][RTW89_MKK][0][74] = 127,
+ [0][1][1][0][RTW89_IC][1][74] = -2,
+ [0][1][1][0][RTW89_KCC][1][74] = 12,
+ [0][1][1][0][RTW89_KCC][0][74] = 127,
+ [0][1][1][0][RTW89_ACMA][1][74] = 127,
+ [0][1][1][0][RTW89_ACMA][0][74] = 127,
+ [0][1][1][0][RTW89_CHILE][1][74] = -2,
+ [0][1][1][0][RTW89_QATAR][1][74] = 127,
+ [0][1][1][0][RTW89_QATAR][0][74] = 127,
+ [0][1][1][0][RTW89_UK][1][74] = 127,
+ [0][1][1][0][RTW89_UK][0][74] = 127,
+ [0][1][1][0][RTW89_FCC][1][75] = -2,
+ [0][1][1][0][RTW89_FCC][2][75] = 68,
+ [0][1][1][0][RTW89_ETSI][1][75] = 127,
+ [0][1][1][0][RTW89_ETSI][0][75] = 127,
+ [0][1][1][0][RTW89_MKK][1][75] = 127,
+ [0][1][1][0][RTW89_MKK][0][75] = 127,
+ [0][1][1][0][RTW89_IC][1][75] = -2,
+ [0][1][1][0][RTW89_KCC][1][75] = 12,
+ [0][1][1][0][RTW89_KCC][0][75] = 127,
+ [0][1][1][0][RTW89_ACMA][1][75] = 127,
+ [0][1][1][0][RTW89_ACMA][0][75] = 127,
+ [0][1][1][0][RTW89_CHILE][1][75] = -2,
+ [0][1][1][0][RTW89_QATAR][1][75] = 127,
+ [0][1][1][0][RTW89_QATAR][0][75] = 127,
+ [0][1][1][0][RTW89_UK][1][75] = 127,
+ [0][1][1][0][RTW89_UK][0][75] = 127,
+ [0][1][1][0][RTW89_FCC][1][77] = -2,
+ [0][1][1][0][RTW89_FCC][2][77] = 68,
+ [0][1][1][0][RTW89_ETSI][1][77] = 127,
+ [0][1][1][0][RTW89_ETSI][0][77] = 127,
+ [0][1][1][0][RTW89_MKK][1][77] = 127,
+ [0][1][1][0][RTW89_MKK][0][77] = 127,
+ [0][1][1][0][RTW89_IC][1][77] = -2,
+ [0][1][1][0][RTW89_KCC][1][77] = 12,
+ [0][1][1][0][RTW89_KCC][0][77] = 127,
+ [0][1][1][0][RTW89_ACMA][1][77] = 127,
+ [0][1][1][0][RTW89_ACMA][0][77] = 127,
+ [0][1][1][0][RTW89_CHILE][1][77] = -2,
+ [0][1][1][0][RTW89_QATAR][1][77] = 127,
+ [0][1][1][0][RTW89_QATAR][0][77] = 127,
+ [0][1][1][0][RTW89_UK][1][77] = 127,
+ [0][1][1][0][RTW89_UK][0][77] = 127,
+ [0][1][1][0][RTW89_FCC][1][79] = -2,
+ [0][1][1][0][RTW89_FCC][2][79] = 68,
+ [0][1][1][0][RTW89_ETSI][1][79] = 127,
+ [0][1][1][0][RTW89_ETSI][0][79] = 127,
+ [0][1][1][0][RTW89_MKK][1][79] = 127,
+ [0][1][1][0][RTW89_MKK][0][79] = 127,
+ [0][1][1][0][RTW89_IC][1][79] = -2,
+ [0][1][1][0][RTW89_KCC][1][79] = 12,
+ [0][1][1][0][RTW89_KCC][0][79] = 127,
+ [0][1][1][0][RTW89_ACMA][1][79] = 127,
+ [0][1][1][0][RTW89_ACMA][0][79] = 127,
+ [0][1][1][0][RTW89_CHILE][1][79] = -2,
+ [0][1][1][0][RTW89_QATAR][1][79] = 127,
+ [0][1][1][0][RTW89_QATAR][0][79] = 127,
+ [0][1][1][0][RTW89_UK][1][79] = 127,
+ [0][1][1][0][RTW89_UK][0][79] = 127,
+ [0][1][1][0][RTW89_FCC][1][81] = -2,
+ [0][1][1][0][RTW89_FCC][2][81] = 68,
+ [0][1][1][0][RTW89_ETSI][1][81] = 127,
+ [0][1][1][0][RTW89_ETSI][0][81] = 127,
+ [0][1][1][0][RTW89_MKK][1][81] = 127,
+ [0][1][1][0][RTW89_MKK][0][81] = 127,
+ [0][1][1][0][RTW89_IC][1][81] = -2,
+ [0][1][1][0][RTW89_KCC][1][81] = 12,
+ [0][1][1][0][RTW89_KCC][0][81] = 127,
+ [0][1][1][0][RTW89_ACMA][1][81] = 127,
+ [0][1][1][0][RTW89_ACMA][0][81] = 127,
+ [0][1][1][0][RTW89_CHILE][1][81] = -2,
+ [0][1][1][0][RTW89_QATAR][1][81] = 127,
+ [0][1][1][0][RTW89_QATAR][0][81] = 127,
+ [0][1][1][0][RTW89_UK][1][81] = 127,
+ [0][1][1][0][RTW89_UK][0][81] = 127,
+ [0][1][1][0][RTW89_FCC][1][83] = -2,
+ [0][1][1][0][RTW89_FCC][2][83] = 68,
+ [0][1][1][0][RTW89_ETSI][1][83] = 127,
+ [0][1][1][0][RTW89_ETSI][0][83] = 127,
+ [0][1][1][0][RTW89_MKK][1][83] = 127,
+ [0][1][1][0][RTW89_MKK][0][83] = 127,
+ [0][1][1][0][RTW89_IC][1][83] = -2,
+ [0][1][1][0][RTW89_KCC][1][83] = 20,
+ [0][1][1][0][RTW89_KCC][0][83] = 127,
+ [0][1][1][0][RTW89_ACMA][1][83] = 127,
+ [0][1][1][0][RTW89_ACMA][0][83] = 127,
+ [0][1][1][0][RTW89_CHILE][1][83] = -2,
+ [0][1][1][0][RTW89_QATAR][1][83] = 127,
+ [0][1][1][0][RTW89_QATAR][0][83] = 127,
+ [0][1][1][0][RTW89_UK][1][83] = 127,
+ [0][1][1][0][RTW89_UK][0][83] = 127,
+ [0][1][1][0][RTW89_FCC][1][85] = -2,
+ [0][1][1][0][RTW89_FCC][2][85] = 68,
+ [0][1][1][0][RTW89_ETSI][1][85] = 127,
+ [0][1][1][0][RTW89_ETSI][0][85] = 127,
+ [0][1][1][0][RTW89_MKK][1][85] = 127,
+ [0][1][1][0][RTW89_MKK][0][85] = 127,
+ [0][1][1][0][RTW89_IC][1][85] = -2,
+ [0][1][1][0][RTW89_KCC][1][85] = 20,
+ [0][1][1][0][RTW89_KCC][0][85] = 127,
+ [0][1][1][0][RTW89_ACMA][1][85] = 127,
+ [0][1][1][0][RTW89_ACMA][0][85] = 127,
+ [0][1][1][0][RTW89_CHILE][1][85] = -2,
+ [0][1][1][0][RTW89_QATAR][1][85] = 127,
+ [0][1][1][0][RTW89_QATAR][0][85] = 127,
+ [0][1][1][0][RTW89_UK][1][85] = 127,
+ [0][1][1][0][RTW89_UK][0][85] = 127,
+ [0][1][1][0][RTW89_FCC][1][87] = -2,
+ [0][1][1][0][RTW89_FCC][2][87] = 127,
+ [0][1][1][0][RTW89_ETSI][1][87] = 127,
+ [0][1][1][0][RTW89_ETSI][0][87] = 127,
+ [0][1][1][0][RTW89_MKK][1][87] = 127,
+ [0][1][1][0][RTW89_MKK][0][87] = 127,
+ [0][1][1][0][RTW89_IC][1][87] = -2,
+ [0][1][1][0][RTW89_KCC][1][87] = 20,
+ [0][1][1][0][RTW89_KCC][0][87] = 127,
+ [0][1][1][0][RTW89_ACMA][1][87] = 127,
+ [0][1][1][0][RTW89_ACMA][0][87] = 127,
+ [0][1][1][0][RTW89_CHILE][1][87] = -2,
+ [0][1][1][0][RTW89_QATAR][1][87] = 127,
+ [0][1][1][0][RTW89_QATAR][0][87] = 127,
+ [0][1][1][0][RTW89_UK][1][87] = 127,
+ [0][1][1][0][RTW89_UK][0][87] = 127,
+ [0][1][1][0][RTW89_FCC][1][89] = -2,
+ [0][1][1][0][RTW89_FCC][2][89] = 127,
+ [0][1][1][0][RTW89_ETSI][1][89] = 127,
+ [0][1][1][0][RTW89_ETSI][0][89] = 127,
+ [0][1][1][0][RTW89_MKK][1][89] = 127,
+ [0][1][1][0][RTW89_MKK][0][89] = 127,
+ [0][1][1][0][RTW89_IC][1][89] = -2,
+ [0][1][1][0][RTW89_KCC][1][89] = 20,
+ [0][1][1][0][RTW89_KCC][0][89] = 127,
+ [0][1][1][0][RTW89_ACMA][1][89] = 127,
+ [0][1][1][0][RTW89_ACMA][0][89] = 127,
+ [0][1][1][0][RTW89_CHILE][1][89] = -2,
+ [0][1][1][0][RTW89_QATAR][1][89] = 127,
+ [0][1][1][0][RTW89_QATAR][0][89] = 127,
+ [0][1][1][0][RTW89_UK][1][89] = 127,
+ [0][1][1][0][RTW89_UK][0][89] = 127,
+ [0][1][1][0][RTW89_FCC][1][90] = -2,
+ [0][1][1][0][RTW89_FCC][2][90] = 127,
+ [0][1][1][0][RTW89_ETSI][1][90] = 127,
+ [0][1][1][0][RTW89_ETSI][0][90] = 127,
+ [0][1][1][0][RTW89_MKK][1][90] = 127,
+ [0][1][1][0][RTW89_MKK][0][90] = 127,
+ [0][1][1][0][RTW89_IC][1][90] = -2,
+ [0][1][1][0][RTW89_KCC][1][90] = 20,
+ [0][1][1][0][RTW89_KCC][0][90] = 127,
+ [0][1][1][0][RTW89_ACMA][1][90] = 127,
+ [0][1][1][0][RTW89_ACMA][0][90] = 127,
+ [0][1][1][0][RTW89_CHILE][1][90] = -2,
+ [0][1][1][0][RTW89_QATAR][1][90] = 127,
+ [0][1][1][0][RTW89_QATAR][0][90] = 127,
+ [0][1][1][0][RTW89_UK][1][90] = 127,
+ [0][1][1][0][RTW89_UK][0][90] = 127,
+ [0][1][1][0][RTW89_FCC][1][92] = -2,
+ [0][1][1][0][RTW89_FCC][2][92] = 127,
+ [0][1][1][0][RTW89_ETSI][1][92] = 127,
+ [0][1][1][0][RTW89_ETSI][0][92] = 127,
+ [0][1][1][0][RTW89_MKK][1][92] = 127,
+ [0][1][1][0][RTW89_MKK][0][92] = 127,
+ [0][1][1][0][RTW89_IC][1][92] = -2,
+ [0][1][1][0][RTW89_KCC][1][92] = 20,
+ [0][1][1][0][RTW89_KCC][0][92] = 127,
+ [0][1][1][0][RTW89_ACMA][1][92] = 127,
+ [0][1][1][0][RTW89_ACMA][0][92] = 127,
+ [0][1][1][0][RTW89_CHILE][1][92] = -2,
+ [0][1][1][0][RTW89_QATAR][1][92] = 127,
+ [0][1][1][0][RTW89_QATAR][0][92] = 127,
+ [0][1][1][0][RTW89_UK][1][92] = 127,
+ [0][1][1][0][RTW89_UK][0][92] = 127,
+ [0][1][1][0][RTW89_FCC][1][94] = -2,
+ [0][1][1][0][RTW89_FCC][2][94] = 127,
+ [0][1][1][0][RTW89_ETSI][1][94] = 127,
+ [0][1][1][0][RTW89_ETSI][0][94] = 127,
+ [0][1][1][0][RTW89_MKK][1][94] = 127,
+ [0][1][1][0][RTW89_MKK][0][94] = 127,
+ [0][1][1][0][RTW89_IC][1][94] = -2,
+ [0][1][1][0][RTW89_KCC][1][94] = 20,
+ [0][1][1][0][RTW89_KCC][0][94] = 127,
+ [0][1][1][0][RTW89_ACMA][1][94] = 127,
+ [0][1][1][0][RTW89_ACMA][0][94] = 127,
+ [0][1][1][0][RTW89_CHILE][1][94] = -2,
+ [0][1][1][0][RTW89_QATAR][1][94] = 127,
+ [0][1][1][0][RTW89_QATAR][0][94] = 127,
+ [0][1][1][0][RTW89_UK][1][94] = 127,
+ [0][1][1][0][RTW89_UK][0][94] = 127,
+ [0][1][1][0][RTW89_FCC][1][96] = -2,
+ [0][1][1][0][RTW89_FCC][2][96] = 127,
+ [0][1][1][0][RTW89_ETSI][1][96] = 127,
+ [0][1][1][0][RTW89_ETSI][0][96] = 127,
+ [0][1][1][0][RTW89_MKK][1][96] = 127,
+ [0][1][1][0][RTW89_MKK][0][96] = 127,
+ [0][1][1][0][RTW89_IC][1][96] = -2,
+ [0][1][1][0][RTW89_KCC][1][96] = 20,
+ [0][1][1][0][RTW89_KCC][0][96] = 127,
+ [0][1][1][0][RTW89_ACMA][1][96] = 127,
+ [0][1][1][0][RTW89_ACMA][0][96] = 127,
+ [0][1][1][0][RTW89_CHILE][1][96] = -2,
+ [0][1][1][0][RTW89_QATAR][1][96] = 127,
+ [0][1][1][0][RTW89_QATAR][0][96] = 127,
+ [0][1][1][0][RTW89_UK][1][96] = 127,
+ [0][1][1][0][RTW89_UK][0][96] = 127,
+ [0][1][1][0][RTW89_FCC][1][98] = -2,
+ [0][1][1][0][RTW89_FCC][2][98] = 127,
+ [0][1][1][0][RTW89_ETSI][1][98] = 127,
+ [0][1][1][0][RTW89_ETSI][0][98] = 127,
+ [0][1][1][0][RTW89_MKK][1][98] = 127,
+ [0][1][1][0][RTW89_MKK][0][98] = 127,
+ [0][1][1][0][RTW89_IC][1][98] = -2,
+ [0][1][1][0][RTW89_KCC][1][98] = 20,
+ [0][1][1][0][RTW89_KCC][0][98] = 127,
+ [0][1][1][0][RTW89_ACMA][1][98] = 127,
+ [0][1][1][0][RTW89_ACMA][0][98] = 127,
+ [0][1][1][0][RTW89_CHILE][1][98] = -2,
+ [0][1][1][0][RTW89_QATAR][1][98] = 127,
+ [0][1][1][0][RTW89_QATAR][0][98] = 127,
+ [0][1][1][0][RTW89_UK][1][98] = 127,
+ [0][1][1][0][RTW89_UK][0][98] = 127,
+ [0][1][1][0][RTW89_FCC][1][100] = -2,
+ [0][1][1][0][RTW89_FCC][2][100] = 127,
+ [0][1][1][0][RTW89_ETSI][1][100] = 127,
+ [0][1][1][0][RTW89_ETSI][0][100] = 127,
+ [0][1][1][0][RTW89_MKK][1][100] = 127,
+ [0][1][1][0][RTW89_MKK][0][100] = 127,
+ [0][1][1][0][RTW89_IC][1][100] = -2,
+ [0][1][1][0][RTW89_KCC][1][100] = 20,
+ [0][1][1][0][RTW89_KCC][0][100] = 127,
+ [0][1][1][0][RTW89_ACMA][1][100] = 127,
+ [0][1][1][0][RTW89_ACMA][0][100] = 127,
+ [0][1][1][0][RTW89_CHILE][1][100] = -2,
+ [0][1][1][0][RTW89_QATAR][1][100] = 127,
+ [0][1][1][0][RTW89_QATAR][0][100] = 127,
+ [0][1][1][0][RTW89_UK][1][100] = 127,
+ [0][1][1][0][RTW89_UK][0][100] = 127,
+ [0][1][1][0][RTW89_FCC][1][102] = -2,
+ [0][1][1][0][RTW89_FCC][2][102] = 127,
+ [0][1][1][0][RTW89_ETSI][1][102] = 127,
+ [0][1][1][0][RTW89_ETSI][0][102] = 127,
+ [0][1][1][0][RTW89_MKK][1][102] = 127,
+ [0][1][1][0][RTW89_MKK][0][102] = 127,
+ [0][1][1][0][RTW89_IC][1][102] = -2,
+ [0][1][1][0][RTW89_KCC][1][102] = 20,
+ [0][1][1][0][RTW89_KCC][0][102] = 127,
+ [0][1][1][0][RTW89_ACMA][1][102] = 127,
+ [0][1][1][0][RTW89_ACMA][0][102] = 127,
+ [0][1][1][0][RTW89_CHILE][1][102] = -2,
+ [0][1][1][0][RTW89_QATAR][1][102] = 127,
+ [0][1][1][0][RTW89_QATAR][0][102] = 127,
+ [0][1][1][0][RTW89_UK][1][102] = 127,
+ [0][1][1][0][RTW89_UK][0][102] = 127,
+ [0][1][1][0][RTW89_FCC][1][104] = -2,
+ [0][1][1][0][RTW89_FCC][2][104] = 127,
+ [0][1][1][0][RTW89_ETSI][1][104] = 127,
+ [0][1][1][0][RTW89_ETSI][0][104] = 127,
+ [0][1][1][0][RTW89_MKK][1][104] = 127,
+ [0][1][1][0][RTW89_MKK][0][104] = 127,
+ [0][1][1][0][RTW89_IC][1][104] = -2,
+ [0][1][1][0][RTW89_KCC][1][104] = 20,
+ [0][1][1][0][RTW89_KCC][0][104] = 127,
+ [0][1][1][0][RTW89_ACMA][1][104] = 127,
+ [0][1][1][0][RTW89_ACMA][0][104] = 127,
+ [0][1][1][0][RTW89_CHILE][1][104] = -2,
+ [0][1][1][0][RTW89_QATAR][1][104] = 127,
+ [0][1][1][0][RTW89_QATAR][0][104] = 127,
+ [0][1][1][0][RTW89_UK][1][104] = 127,
+ [0][1][1][0][RTW89_UK][0][104] = 127,
+ [0][1][1][0][RTW89_FCC][1][105] = -2,
+ [0][1][1][0][RTW89_FCC][2][105] = 127,
+ [0][1][1][0][RTW89_ETSI][1][105] = 127,
+ [0][1][1][0][RTW89_ETSI][0][105] = 127,
+ [0][1][1][0][RTW89_MKK][1][105] = 127,
+ [0][1][1][0][RTW89_MKK][0][105] = 127,
+ [0][1][1][0][RTW89_IC][1][105] = -2,
+ [0][1][1][0][RTW89_KCC][1][105] = 20,
+ [0][1][1][0][RTW89_KCC][0][105] = 127,
+ [0][1][1][0][RTW89_ACMA][1][105] = 127,
+ [0][1][1][0][RTW89_ACMA][0][105] = 127,
+ [0][1][1][0][RTW89_CHILE][1][105] = -2,
+ [0][1][1][0][RTW89_QATAR][1][105] = 127,
+ [0][1][1][0][RTW89_QATAR][0][105] = 127,
+ [0][1][1][0][RTW89_UK][1][105] = 127,
+ [0][1][1][0][RTW89_UK][0][105] = 127,
+ [0][1][1][0][RTW89_FCC][1][107] = 1,
+ [0][1][1][0][RTW89_FCC][2][107] = 127,
+ [0][1][1][0][RTW89_ETSI][1][107] = 127,
+ [0][1][1][0][RTW89_ETSI][0][107] = 127,
+ [0][1][1][0][RTW89_MKK][1][107] = 127,
+ [0][1][1][0][RTW89_MKK][0][107] = 127,
+ [0][1][1][0][RTW89_IC][1][107] = 1,
+ [0][1][1][0][RTW89_KCC][1][107] = 20,
+ [0][1][1][0][RTW89_KCC][0][107] = 127,
+ [0][1][1][0][RTW89_ACMA][1][107] = 127,
+ [0][1][1][0][RTW89_ACMA][0][107] = 127,
+ [0][1][1][0][RTW89_CHILE][1][107] = 1,
+ [0][1][1][0][RTW89_QATAR][1][107] = 127,
+ [0][1][1][0][RTW89_QATAR][0][107] = 127,
+ [0][1][1][0][RTW89_UK][1][107] = 127,
+ [0][1][1][0][RTW89_UK][0][107] = 127,
+ [0][1][1][0][RTW89_FCC][1][109] = 1,
+ [0][1][1][0][RTW89_FCC][2][109] = 127,
+ [0][1][1][0][RTW89_ETSI][1][109] = 127,
+ [0][1][1][0][RTW89_ETSI][0][109] = 127,
+ [0][1][1][0][RTW89_MKK][1][109] = 127,
+ [0][1][1][0][RTW89_MKK][0][109] = 127,
+ [0][1][1][0][RTW89_IC][1][109] = 1,
+ [0][1][1][0][RTW89_KCC][1][109] = 20,
+ [0][1][1][0][RTW89_KCC][0][109] = 127,
+ [0][1][1][0][RTW89_ACMA][1][109] = 127,
+ [0][1][1][0][RTW89_ACMA][0][109] = 127,
+ [0][1][1][0][RTW89_CHILE][1][109] = 1,
+ [0][1][1][0][RTW89_QATAR][1][109] = 127,
+ [0][1][1][0][RTW89_QATAR][0][109] = 127,
+ [0][1][1][0][RTW89_UK][1][109] = 127,
+ [0][1][1][0][RTW89_UK][0][109] = 127,
+ [0][1][1][0][RTW89_FCC][1][111] = 127,
+ [0][1][1][0][RTW89_FCC][2][111] = 127,
+ [0][1][1][0][RTW89_ETSI][1][111] = 127,
+ [0][1][1][0][RTW89_ETSI][0][111] = 127,
+ [0][1][1][0][RTW89_MKK][1][111] = 127,
+ [0][1][1][0][RTW89_MKK][0][111] = 127,
+ [0][1][1][0][RTW89_IC][1][111] = 127,
+ [0][1][1][0][RTW89_KCC][1][111] = 127,
+ [0][1][1][0][RTW89_KCC][0][111] = 127,
+ [0][1][1][0][RTW89_ACMA][1][111] = 127,
+ [0][1][1][0][RTW89_ACMA][0][111] = 127,
+ [0][1][1][0][RTW89_CHILE][1][111] = 127,
+ [0][1][1][0][RTW89_QATAR][1][111] = 127,
+ [0][1][1][0][RTW89_QATAR][0][111] = 127,
+ [0][1][1][0][RTW89_UK][1][111] = 127,
+ [0][1][1][0][RTW89_UK][0][111] = 127,
+ [0][1][1][0][RTW89_FCC][1][113] = 127,
+ [0][1][1][0][RTW89_FCC][2][113] = 127,
+ [0][1][1][0][RTW89_ETSI][1][113] = 127,
+ [0][1][1][0][RTW89_ETSI][0][113] = 127,
+ [0][1][1][0][RTW89_MKK][1][113] = 127,
+ [0][1][1][0][RTW89_MKK][0][113] = 127,
+ [0][1][1][0][RTW89_IC][1][113] = 127,
+ [0][1][1][0][RTW89_KCC][1][113] = 127,
+ [0][1][1][0][RTW89_KCC][0][113] = 127,
+ [0][1][1][0][RTW89_ACMA][1][113] = 127,
+ [0][1][1][0][RTW89_ACMA][0][113] = 127,
+ [0][1][1][0][RTW89_CHILE][1][113] = 127,
+ [0][1][1][0][RTW89_QATAR][1][113] = 127,
+ [0][1][1][0][RTW89_QATAR][0][113] = 127,
+ [0][1][1][0][RTW89_UK][1][113] = 127,
+ [0][1][1][0][RTW89_UK][0][113] = 127,
+ [0][1][1][0][RTW89_FCC][1][115] = 127,
+ [0][1][1][0][RTW89_FCC][2][115] = 127,
+ [0][1][1][0][RTW89_ETSI][1][115] = 127,
+ [0][1][1][0][RTW89_ETSI][0][115] = 127,
+ [0][1][1][0][RTW89_MKK][1][115] = 127,
+ [0][1][1][0][RTW89_MKK][0][115] = 127,
+ [0][1][1][0][RTW89_IC][1][115] = 127,
+ [0][1][1][0][RTW89_KCC][1][115] = 127,
+ [0][1][1][0][RTW89_KCC][0][115] = 127,
+ [0][1][1][0][RTW89_ACMA][1][115] = 127,
+ [0][1][1][0][RTW89_ACMA][0][115] = 127,
+ [0][1][1][0][RTW89_CHILE][1][115] = 127,
+ [0][1][1][0][RTW89_QATAR][1][115] = 127,
+ [0][1][1][0][RTW89_QATAR][0][115] = 127,
+ [0][1][1][0][RTW89_UK][1][115] = 127,
+ [0][1][1][0][RTW89_UK][0][115] = 127,
+ [0][1][1][0][RTW89_FCC][1][117] = 127,
+ [0][1][1][0][RTW89_FCC][2][117] = 127,
+ [0][1][1][0][RTW89_ETSI][1][117] = 127,
+ [0][1][1][0][RTW89_ETSI][0][117] = 127,
+ [0][1][1][0][RTW89_MKK][1][117] = 127,
+ [0][1][1][0][RTW89_MKK][0][117] = 127,
+ [0][1][1][0][RTW89_IC][1][117] = 127,
+ [0][1][1][0][RTW89_KCC][1][117] = 127,
+ [0][1][1][0][RTW89_KCC][0][117] = 127,
+ [0][1][1][0][RTW89_ACMA][1][117] = 127,
+ [0][1][1][0][RTW89_ACMA][0][117] = 127,
+ [0][1][1][0][RTW89_CHILE][1][117] = 127,
+ [0][1][1][0][RTW89_QATAR][1][117] = 127,
+ [0][1][1][0][RTW89_QATAR][0][117] = 127,
+ [0][1][1][0][RTW89_UK][1][117] = 127,
+ [0][1][1][0][RTW89_UK][0][117] = 127,
+ [0][1][1][0][RTW89_FCC][1][119] = 127,
+ [0][1][1][0][RTW89_FCC][2][119] = 127,
+ [0][1][1][0][RTW89_ETSI][1][119] = 127,
+ [0][1][1][0][RTW89_ETSI][0][119] = 127,
+ [0][1][1][0][RTW89_MKK][1][119] = 127,
+ [0][1][1][0][RTW89_MKK][0][119] = 127,
+ [0][1][1][0][RTW89_IC][1][119] = 127,
+ [0][1][1][0][RTW89_KCC][1][119] = 127,
+ [0][1][1][0][RTW89_KCC][0][119] = 127,
+ [0][1][1][0][RTW89_ACMA][1][119] = 127,
+ [0][1][1][0][RTW89_ACMA][0][119] = 127,
+ [0][1][1][0][RTW89_CHILE][1][119] = 127,
+ [0][1][1][0][RTW89_QATAR][1][119] = 127,
+ [0][1][1][0][RTW89_QATAR][0][119] = 127,
+ [0][1][1][0][RTW89_UK][1][119] = 127,
+ [0][1][1][0][RTW89_UK][0][119] = 127,
+ [0][0][2][0][RTW89_FCC][1][0] = 24,
+ [0][0][2][0][RTW89_FCC][2][0] = 56,
+ [0][0][2][0][RTW89_ETSI][1][0] = 66,
+ [0][0][2][0][RTW89_ETSI][0][0] = 28,
+ [0][0][2][0][RTW89_MKK][1][0] = 66,
+ [0][0][2][0][RTW89_MKK][0][0] = 26,
+ [0][0][2][0][RTW89_IC][1][0] = 24,
+ [0][0][2][0][RTW89_KCC][1][0] = 24,
+ [0][0][2][0][RTW89_KCC][0][0] = 24,
+ [0][0][2][0][RTW89_ACMA][1][0] = 66,
+ [0][0][2][0][RTW89_ACMA][0][0] = 28,
+ [0][0][2][0][RTW89_CHILE][1][0] = 24,
+ [0][0][2][0][RTW89_QATAR][1][0] = 66,
+ [0][0][2][0][RTW89_QATAR][0][0] = 28,
+ [0][0][2][0][RTW89_UK][1][0] = 66,
+ [0][0][2][0][RTW89_UK][0][0] = 28,
+ [0][0][2][0][RTW89_FCC][1][2] = 22,
+ [0][0][2][0][RTW89_FCC][2][2] = 56,
+ [0][0][2][0][RTW89_ETSI][1][2] = 66,
+ [0][0][2][0][RTW89_ETSI][0][2] = 28,
+ [0][0][2][0][RTW89_MKK][1][2] = 66,
+ [0][0][2][0][RTW89_MKK][0][2] = 26,
+ [0][0][2][0][RTW89_IC][1][2] = 22,
+ [0][0][2][0][RTW89_KCC][1][2] = 24,
+ [0][0][2][0][RTW89_KCC][0][2] = 24,
+ [0][0][2][0][RTW89_ACMA][1][2] = 66,
+ [0][0][2][0][RTW89_ACMA][0][2] = 28,
+ [0][0][2][0][RTW89_CHILE][1][2] = 22,
+ [0][0][2][0][RTW89_QATAR][1][2] = 66,
+ [0][0][2][0][RTW89_QATAR][0][2] = 28,
+ [0][0][2][0][RTW89_UK][1][2] = 66,
+ [0][0][2][0][RTW89_UK][0][2] = 28,
+ [0][0][2][0][RTW89_FCC][1][4] = 22,
+ [0][0][2][0][RTW89_FCC][2][4] = 56,
+ [0][0][2][0][RTW89_ETSI][1][4] = 66,
+ [0][0][2][0][RTW89_ETSI][0][4] = 28,
+ [0][0][2][0][RTW89_MKK][1][4] = 66,
+ [0][0][2][0][RTW89_MKK][0][4] = 26,
+ [0][0][2][0][RTW89_IC][1][4] = 22,
+ [0][0][2][0][RTW89_KCC][1][4] = 24,
+ [0][0][2][0][RTW89_KCC][0][4] = 24,
+ [0][0][2][0][RTW89_ACMA][1][4] = 66,
+ [0][0][2][0][RTW89_ACMA][0][4] = 28,
+ [0][0][2][0][RTW89_CHILE][1][4] = 22,
+ [0][0][2][0][RTW89_QATAR][1][4] = 66,
+ [0][0][2][0][RTW89_QATAR][0][4] = 28,
+ [0][0][2][0][RTW89_UK][1][4] = 66,
+ [0][0][2][0][RTW89_UK][0][4] = 28,
+ [0][0][2][0][RTW89_FCC][1][6] = 22,
+ [0][0][2][0][RTW89_FCC][2][6] = 56,
+ [0][0][2][0][RTW89_ETSI][1][6] = 66,
+ [0][0][2][0][RTW89_ETSI][0][6] = 28,
+ [0][0][2][0][RTW89_MKK][1][6] = 66,
+ [0][0][2][0][RTW89_MKK][0][6] = 26,
+ [0][0][2][0][RTW89_IC][1][6] = 22,
+ [0][0][2][0][RTW89_KCC][1][6] = 24,
+ [0][0][2][0][RTW89_KCC][0][6] = 24,
+ [0][0][2][0][RTW89_ACMA][1][6] = 66,
+ [0][0][2][0][RTW89_ACMA][0][6] = 28,
+ [0][0][2][0][RTW89_CHILE][1][6] = 22,
+ [0][0][2][0][RTW89_QATAR][1][6] = 66,
+ [0][0][2][0][RTW89_QATAR][0][6] = 28,
+ [0][0][2][0][RTW89_UK][1][6] = 66,
+ [0][0][2][0][RTW89_UK][0][6] = 28,
+ [0][0][2][0][RTW89_FCC][1][8] = 22,
+ [0][0][2][0][RTW89_FCC][2][8] = 56,
+ [0][0][2][0][RTW89_ETSI][1][8] = 66,
+ [0][0][2][0][RTW89_ETSI][0][8] = 28,
+ [0][0][2][0][RTW89_MKK][1][8] = 66,
+ [0][0][2][0][RTW89_MKK][0][8] = 26,
+ [0][0][2][0][RTW89_IC][1][8] = 22,
+ [0][0][2][0][RTW89_KCC][1][8] = 24,
+ [0][0][2][0][RTW89_KCC][0][8] = 24,
+ [0][0][2][0][RTW89_ACMA][1][8] = 66,
+ [0][0][2][0][RTW89_ACMA][0][8] = 28,
+ [0][0][2][0][RTW89_CHILE][1][8] = 22,
+ [0][0][2][0][RTW89_QATAR][1][8] = 66,
+ [0][0][2][0][RTW89_QATAR][0][8] = 28,
+ [0][0][2][0][RTW89_UK][1][8] = 66,
+ [0][0][2][0][RTW89_UK][0][8] = 28,
+ [0][0][2][0][RTW89_FCC][1][10] = 22,
+ [0][0][2][0][RTW89_FCC][2][10] = 56,
+ [0][0][2][0][RTW89_ETSI][1][10] = 66,
+ [0][0][2][0][RTW89_ETSI][0][10] = 28,
+ [0][0][2][0][RTW89_MKK][1][10] = 66,
+ [0][0][2][0][RTW89_MKK][0][10] = 26,
+ [0][0][2][0][RTW89_IC][1][10] = 22,
+ [0][0][2][0][RTW89_KCC][1][10] = 24,
+ [0][0][2][0][RTW89_KCC][0][10] = 24,
+ [0][0][2][0][RTW89_ACMA][1][10] = 66,
+ [0][0][2][0][RTW89_ACMA][0][10] = 28,
+ [0][0][2][0][RTW89_CHILE][1][10] = 22,
+ [0][0][2][0][RTW89_QATAR][1][10] = 66,
+ [0][0][2][0][RTW89_QATAR][0][10] = 28,
+ [0][0][2][0][RTW89_UK][1][10] = 66,
+ [0][0][2][0][RTW89_UK][0][10] = 28,
+ [0][0][2][0][RTW89_FCC][1][12] = 22,
+ [0][0][2][0][RTW89_FCC][2][12] = 56,
+ [0][0][2][0][RTW89_ETSI][1][12] = 66,
+ [0][0][2][0][RTW89_ETSI][0][12] = 28,
+ [0][0][2][0][RTW89_MKK][1][12] = 66,
+ [0][0][2][0][RTW89_MKK][0][12] = 26,
+ [0][0][2][0][RTW89_IC][1][12] = 22,
+ [0][0][2][0][RTW89_KCC][1][12] = 24,
+ [0][0][2][0][RTW89_KCC][0][12] = 24,
+ [0][0][2][0][RTW89_ACMA][1][12] = 66,
+ [0][0][2][0][RTW89_ACMA][0][12] = 28,
+ [0][0][2][0][RTW89_CHILE][1][12] = 22,
+ [0][0][2][0][RTW89_QATAR][1][12] = 66,
+ [0][0][2][0][RTW89_QATAR][0][12] = 28,
+ [0][0][2][0][RTW89_UK][1][12] = 66,
+ [0][0][2][0][RTW89_UK][0][12] = 28,
+ [0][0][2][0][RTW89_FCC][1][14] = 22,
+ [0][0][2][0][RTW89_FCC][2][14] = 56,
+ [0][0][2][0][RTW89_ETSI][1][14] = 66,
+ [0][0][2][0][RTW89_ETSI][0][14] = 28,
+ [0][0][2][0][RTW89_MKK][1][14] = 66,
+ [0][0][2][0][RTW89_MKK][0][14] = 26,
+ [0][0][2][0][RTW89_IC][1][14] = 22,
+ [0][0][2][0][RTW89_KCC][1][14] = 24,
+ [0][0][2][0][RTW89_KCC][0][14] = 24,
+ [0][0][2][0][RTW89_ACMA][1][14] = 66,
+ [0][0][2][0][RTW89_ACMA][0][14] = 28,
+ [0][0][2][0][RTW89_CHILE][1][14] = 22,
+ [0][0][2][0][RTW89_QATAR][1][14] = 66,
+ [0][0][2][0][RTW89_QATAR][0][14] = 28,
+ [0][0][2][0][RTW89_UK][1][14] = 66,
+ [0][0][2][0][RTW89_UK][0][14] = 28,
+ [0][0][2][0][RTW89_FCC][1][15] = 22,
+ [0][0][2][0][RTW89_FCC][2][15] = 56,
+ [0][0][2][0][RTW89_ETSI][1][15] = 66,
+ [0][0][2][0][RTW89_ETSI][0][15] = 28,
+ [0][0][2][0][RTW89_MKK][1][15] = 66,
+ [0][0][2][0][RTW89_MKK][0][15] = 26,
+ [0][0][2][0][RTW89_IC][1][15] = 22,
+ [0][0][2][0][RTW89_KCC][1][15] = 24,
+ [0][0][2][0][RTW89_KCC][0][15] = 24,
+ [0][0][2][0][RTW89_ACMA][1][15] = 66,
+ [0][0][2][0][RTW89_ACMA][0][15] = 28,
+ [0][0][2][0][RTW89_CHILE][1][15] = 22,
+ [0][0][2][0][RTW89_QATAR][1][15] = 66,
+ [0][0][2][0][RTW89_QATAR][0][15] = 28,
+ [0][0][2][0][RTW89_UK][1][15] = 66,
+ [0][0][2][0][RTW89_UK][0][15] = 28,
+ [0][0][2][0][RTW89_FCC][1][17] = 22,
+ [0][0][2][0][RTW89_FCC][2][17] = 56,
+ [0][0][2][0][RTW89_ETSI][1][17] = 66,
+ [0][0][2][0][RTW89_ETSI][0][17] = 28,
+ [0][0][2][0][RTW89_MKK][1][17] = 66,
+ [0][0][2][0][RTW89_MKK][0][17] = 26,
+ [0][0][2][0][RTW89_IC][1][17] = 22,
+ [0][0][2][0][RTW89_KCC][1][17] = 24,
+ [0][0][2][0][RTW89_KCC][0][17] = 24,
+ [0][0][2][0][RTW89_ACMA][1][17] = 66,
+ [0][0][2][0][RTW89_ACMA][0][17] = 28,
+ [0][0][2][0][RTW89_CHILE][1][17] = 22,
+ [0][0][2][0][RTW89_QATAR][1][17] = 66,
+ [0][0][2][0][RTW89_QATAR][0][17] = 28,
+ [0][0][2][0][RTW89_UK][1][17] = 66,
+ [0][0][2][0][RTW89_UK][0][17] = 28,
+ [0][0][2][0][RTW89_FCC][1][19] = 22,
+ [0][0][2][0][RTW89_FCC][2][19] = 56,
+ [0][0][2][0][RTW89_ETSI][1][19] = 66,
+ [0][0][2][0][RTW89_ETSI][0][19] = 28,
+ [0][0][2][0][RTW89_MKK][1][19] = 66,
+ [0][0][2][0][RTW89_MKK][0][19] = 26,
+ [0][0][2][0][RTW89_IC][1][19] = 22,
+ [0][0][2][0][RTW89_KCC][1][19] = 24,
+ [0][0][2][0][RTW89_KCC][0][19] = 24,
+ [0][0][2][0][RTW89_ACMA][1][19] = 66,
+ [0][0][2][0][RTW89_ACMA][0][19] = 28,
+ [0][0][2][0][RTW89_CHILE][1][19] = 22,
+ [0][0][2][0][RTW89_QATAR][1][19] = 66,
+ [0][0][2][0][RTW89_QATAR][0][19] = 28,
+ [0][0][2][0][RTW89_UK][1][19] = 66,
+ [0][0][2][0][RTW89_UK][0][19] = 28,
+ [0][0][2][0][RTW89_FCC][1][21] = 22,
+ [0][0][2][0][RTW89_FCC][2][21] = 56,
+ [0][0][2][0][RTW89_ETSI][1][21] = 66,
+ [0][0][2][0][RTW89_ETSI][0][21] = 28,
+ [0][0][2][0][RTW89_MKK][1][21] = 66,
+ [0][0][2][0][RTW89_MKK][0][21] = 26,
+ [0][0][2][0][RTW89_IC][1][21] = 22,
+ [0][0][2][0][RTW89_KCC][1][21] = 24,
+ [0][0][2][0][RTW89_KCC][0][21] = 24,
+ [0][0][2][0][RTW89_ACMA][1][21] = 66,
+ [0][0][2][0][RTW89_ACMA][0][21] = 28,
+ [0][0][2][0][RTW89_CHILE][1][21] = 22,
+ [0][0][2][0][RTW89_QATAR][1][21] = 66,
+ [0][0][2][0][RTW89_QATAR][0][21] = 28,
+ [0][0][2][0][RTW89_UK][1][21] = 66,
+ [0][0][2][0][RTW89_UK][0][21] = 28,
+ [0][0][2][0][RTW89_FCC][1][23] = 22,
+ [0][0][2][0][RTW89_FCC][2][23] = 70,
+ [0][0][2][0][RTW89_ETSI][1][23] = 66,
+ [0][0][2][0][RTW89_ETSI][0][23] = 28,
+ [0][0][2][0][RTW89_MKK][1][23] = 66,
+ [0][0][2][0][RTW89_MKK][0][23] = 26,
+ [0][0][2][0][RTW89_IC][1][23] = 22,
+ [0][0][2][0][RTW89_KCC][1][23] = 24,
+ [0][0][2][0][RTW89_KCC][0][23] = 26,
+ [0][0][2][0][RTW89_ACMA][1][23] = 66,
+ [0][0][2][0][RTW89_ACMA][0][23] = 28,
+ [0][0][2][0][RTW89_CHILE][1][23] = 22,
+ [0][0][2][0][RTW89_QATAR][1][23] = 66,
+ [0][0][2][0][RTW89_QATAR][0][23] = 28,
+ [0][0][2][0][RTW89_UK][1][23] = 66,
+ [0][0][2][0][RTW89_UK][0][23] = 28,
+ [0][0][2][0][RTW89_FCC][1][25] = 22,
+ [0][0][2][0][RTW89_FCC][2][25] = 70,
+ [0][0][2][0][RTW89_ETSI][1][25] = 66,
+ [0][0][2][0][RTW89_ETSI][0][25] = 28,
+ [0][0][2][0][RTW89_MKK][1][25] = 66,
+ [0][0][2][0][RTW89_MKK][0][25] = 26,
+ [0][0][2][0][RTW89_IC][1][25] = 22,
+ [0][0][2][0][RTW89_KCC][1][25] = 24,
+ [0][0][2][0][RTW89_KCC][0][25] = 26,
+ [0][0][2][0][RTW89_ACMA][1][25] = 66,
+ [0][0][2][0][RTW89_ACMA][0][25] = 28,
+ [0][0][2][0][RTW89_CHILE][1][25] = 22,
+ [0][0][2][0][RTW89_QATAR][1][25] = 66,
+ [0][0][2][0][RTW89_QATAR][0][25] = 28,
+ [0][0][2][0][RTW89_UK][1][25] = 66,
+ [0][0][2][0][RTW89_UK][0][25] = 28,
+ [0][0][2][0][RTW89_FCC][1][27] = 22,
+ [0][0][2][0][RTW89_FCC][2][27] = 70,
+ [0][0][2][0][RTW89_ETSI][1][27] = 66,
+ [0][0][2][0][RTW89_ETSI][0][27] = 28,
+ [0][0][2][0][RTW89_MKK][1][27] = 66,
+ [0][0][2][0][RTW89_MKK][0][27] = 26,
+ [0][0][2][0][RTW89_IC][1][27] = 22,
+ [0][0][2][0][RTW89_KCC][1][27] = 24,
+ [0][0][2][0][RTW89_KCC][0][27] = 26,
+ [0][0][2][0][RTW89_ACMA][1][27] = 66,
+ [0][0][2][0][RTW89_ACMA][0][27] = 28,
+ [0][0][2][0][RTW89_CHILE][1][27] = 22,
+ [0][0][2][0][RTW89_QATAR][1][27] = 66,
+ [0][0][2][0][RTW89_QATAR][0][27] = 28,
+ [0][0][2][0][RTW89_UK][1][27] = 66,
+ [0][0][2][0][RTW89_UK][0][27] = 28,
+ [0][0][2][0][RTW89_FCC][1][29] = 22,
+ [0][0][2][0][RTW89_FCC][2][29] = 70,
+ [0][0][2][0][RTW89_ETSI][1][29] = 66,
+ [0][0][2][0][RTW89_ETSI][0][29] = 28,
+ [0][0][2][0][RTW89_MKK][1][29] = 66,
+ [0][0][2][0][RTW89_MKK][0][29] = 26,
+ [0][0][2][0][RTW89_IC][1][29] = 22,
+ [0][0][2][0][RTW89_KCC][1][29] = 24,
+ [0][0][2][0][RTW89_KCC][0][29] = 26,
+ [0][0][2][0][RTW89_ACMA][1][29] = 66,
+ [0][0][2][0][RTW89_ACMA][0][29] = 28,
+ [0][0][2][0][RTW89_CHILE][1][29] = 22,
+ [0][0][2][0][RTW89_QATAR][1][29] = 66,
+ [0][0][2][0][RTW89_QATAR][0][29] = 28,
+ [0][0][2][0][RTW89_UK][1][29] = 66,
+ [0][0][2][0][RTW89_UK][0][29] = 28,
+ [0][0][2][0][RTW89_FCC][1][30] = 22,
+ [0][0][2][0][RTW89_FCC][2][30] = 70,
+ [0][0][2][0][RTW89_ETSI][1][30] = 66,
+ [0][0][2][0][RTW89_ETSI][0][30] = 28,
+ [0][0][2][0][RTW89_MKK][1][30] = 66,
+ [0][0][2][0][RTW89_MKK][0][30] = 26,
+ [0][0][2][0][RTW89_IC][1][30] = 22,
+ [0][0][2][0][RTW89_KCC][1][30] = 24,
+ [0][0][2][0][RTW89_KCC][0][30] = 26,
+ [0][0][2][0][RTW89_ACMA][1][30] = 66,
+ [0][0][2][0][RTW89_ACMA][0][30] = 28,
+ [0][0][2][0][RTW89_CHILE][1][30] = 22,
+ [0][0][2][0][RTW89_QATAR][1][30] = 66,
+ [0][0][2][0][RTW89_QATAR][0][30] = 28,
+ [0][0][2][0][RTW89_UK][1][30] = 66,
+ [0][0][2][0][RTW89_UK][0][30] = 28,
+ [0][0][2][0][RTW89_FCC][1][32] = 22,
+ [0][0][2][0][RTW89_FCC][2][32] = 70,
+ [0][0][2][0][RTW89_ETSI][1][32] = 66,
+ [0][0][2][0][RTW89_ETSI][0][32] = 28,
+ [0][0][2][0][RTW89_MKK][1][32] = 66,
+ [0][0][2][0][RTW89_MKK][0][32] = 26,
+ [0][0][2][0][RTW89_IC][1][32] = 22,
+ [0][0][2][0][RTW89_KCC][1][32] = 24,
+ [0][0][2][0][RTW89_KCC][0][32] = 26,
+ [0][0][2][0][RTW89_ACMA][1][32] = 66,
+ [0][0][2][0][RTW89_ACMA][0][32] = 28,
+ [0][0][2][0][RTW89_CHILE][1][32] = 22,
+ [0][0][2][0][RTW89_QATAR][1][32] = 66,
+ [0][0][2][0][RTW89_QATAR][0][32] = 28,
+ [0][0][2][0][RTW89_UK][1][32] = 66,
+ [0][0][2][0][RTW89_UK][0][32] = 28,
+ [0][0][2][0][RTW89_FCC][1][34] = 22,
+ [0][0][2][0][RTW89_FCC][2][34] = 70,
+ [0][0][2][0][RTW89_ETSI][1][34] = 66,
+ [0][0][2][0][RTW89_ETSI][0][34] = 28,
+ [0][0][2][0][RTW89_MKK][1][34] = 66,
+ [0][0][2][0][RTW89_MKK][0][34] = 26,
+ [0][0][2][0][RTW89_IC][1][34] = 22,
+ [0][0][2][0][RTW89_KCC][1][34] = 24,
+ [0][0][2][0][RTW89_KCC][0][34] = 26,
+ [0][0][2][0][RTW89_ACMA][1][34] = 66,
+ [0][0][2][0][RTW89_ACMA][0][34] = 28,
+ [0][0][2][0][RTW89_CHILE][1][34] = 22,
+ [0][0][2][0][RTW89_QATAR][1][34] = 66,
+ [0][0][2][0][RTW89_QATAR][0][34] = 28,
+ [0][0][2][0][RTW89_UK][1][34] = 66,
+ [0][0][2][0][RTW89_UK][0][34] = 28,
+ [0][0][2][0][RTW89_FCC][1][36] = 22,
+ [0][0][2][0][RTW89_FCC][2][36] = 70,
+ [0][0][2][0][RTW89_ETSI][1][36] = 66,
+ [0][0][2][0][RTW89_ETSI][0][36] = 28,
+ [0][0][2][0][RTW89_MKK][1][36] = 66,
+ [0][0][2][0][RTW89_MKK][0][36] = 26,
+ [0][0][2][0][RTW89_IC][1][36] = 22,
+ [0][0][2][0][RTW89_KCC][1][36] = 24,
+ [0][0][2][0][RTW89_KCC][0][36] = 26,
+ [0][0][2][0][RTW89_ACMA][1][36] = 66,
+ [0][0][2][0][RTW89_ACMA][0][36] = 28,
+ [0][0][2][0][RTW89_CHILE][1][36] = 22,
+ [0][0][2][0][RTW89_QATAR][1][36] = 66,
+ [0][0][2][0][RTW89_QATAR][0][36] = 28,
+ [0][0][2][0][RTW89_UK][1][36] = 66,
+ [0][0][2][0][RTW89_UK][0][36] = 28,
+ [0][0][2][0][RTW89_FCC][1][38] = 22,
+ [0][0][2][0][RTW89_FCC][2][38] = 70,
+ [0][0][2][0][RTW89_ETSI][1][38] = 66,
+ [0][0][2][0][RTW89_ETSI][0][38] = 28,
+ [0][0][2][0][RTW89_MKK][1][38] = 66,
+ [0][0][2][0][RTW89_MKK][0][38] = 26,
+ [0][0][2][0][RTW89_IC][1][38] = 22,
+ [0][0][2][0][RTW89_KCC][1][38] = 24,
+ [0][0][2][0][RTW89_KCC][0][38] = 26,
+ [0][0][2][0][RTW89_ACMA][1][38] = 66,
+ [0][0][2][0][RTW89_ACMA][0][38] = 28,
+ [0][0][2][0][RTW89_CHILE][1][38] = 22,
+ [0][0][2][0][RTW89_QATAR][1][38] = 66,
+ [0][0][2][0][RTW89_QATAR][0][38] = 28,
+ [0][0][2][0][RTW89_UK][1][38] = 66,
+ [0][0][2][0][RTW89_UK][0][38] = 28,
+ [0][0][2][0][RTW89_FCC][1][40] = 22,
+ [0][0][2][0][RTW89_FCC][2][40] = 70,
+ [0][0][2][0][RTW89_ETSI][1][40] = 66,
+ [0][0][2][0][RTW89_ETSI][0][40] = 28,
+ [0][0][2][0][RTW89_MKK][1][40] = 66,
+ [0][0][2][0][RTW89_MKK][0][40] = 26,
+ [0][0][2][0][RTW89_IC][1][40] = 22,
+ [0][0][2][0][RTW89_KCC][1][40] = 24,
+ [0][0][2][0][RTW89_KCC][0][40] = 26,
+ [0][0][2][0][RTW89_ACMA][1][40] = 66,
+ [0][0][2][0][RTW89_ACMA][0][40] = 28,
+ [0][0][2][0][RTW89_CHILE][1][40] = 22,
+ [0][0][2][0][RTW89_QATAR][1][40] = 66,
+ [0][0][2][0][RTW89_QATAR][0][40] = 28,
+ [0][0][2][0][RTW89_UK][1][40] = 66,
+ [0][0][2][0][RTW89_UK][0][40] = 28,
+ [0][0][2][0][RTW89_FCC][1][42] = 22,
+ [0][0][2][0][RTW89_FCC][2][42] = 70,
+ [0][0][2][0][RTW89_ETSI][1][42] = 66,
+ [0][0][2][0][RTW89_ETSI][0][42] = 28,
+ [0][0][2][0][RTW89_MKK][1][42] = 66,
+ [0][0][2][0][RTW89_MKK][0][42] = 26,
+ [0][0][2][0][RTW89_IC][1][42] = 22,
+ [0][0][2][0][RTW89_KCC][1][42] = 24,
+ [0][0][2][0][RTW89_KCC][0][42] = 26,
+ [0][0][2][0][RTW89_ACMA][1][42] = 66,
+ [0][0][2][0][RTW89_ACMA][0][42] = 28,
+ [0][0][2][0][RTW89_CHILE][1][42] = 22,
+ [0][0][2][0][RTW89_QATAR][1][42] = 66,
+ [0][0][2][0][RTW89_QATAR][0][42] = 28,
+ [0][0][2][0][RTW89_UK][1][42] = 66,
+ [0][0][2][0][RTW89_UK][0][42] = 28,
+ [0][0][2][0][RTW89_FCC][1][44] = 22,
+ [0][0][2][0][RTW89_FCC][2][44] = 70,
+ [0][0][2][0][RTW89_ETSI][1][44] = 66,
+ [0][0][2][0][RTW89_ETSI][0][44] = 30,
+ [0][0][2][0][RTW89_MKK][1][44] = 44,
+ [0][0][2][0][RTW89_MKK][0][44] = 28,
+ [0][0][2][0][RTW89_IC][1][44] = 22,
+ [0][0][2][0][RTW89_KCC][1][44] = 24,
+ [0][0][2][0][RTW89_KCC][0][44] = 26,
+ [0][0][2][0][RTW89_ACMA][1][44] = 66,
+ [0][0][2][0][RTW89_ACMA][0][44] = 30,
+ [0][0][2][0][RTW89_CHILE][1][44] = 22,
+ [0][0][2][0][RTW89_QATAR][1][44] = 66,
+ [0][0][2][0][RTW89_QATAR][0][44] = 30,
+ [0][0][2][0][RTW89_UK][1][44] = 66,
+ [0][0][2][0][RTW89_UK][0][44] = 30,
+ [0][0][2][0][RTW89_FCC][1][45] = 22,
+ [0][0][2][0][RTW89_FCC][2][45] = 127,
+ [0][0][2][0][RTW89_ETSI][1][45] = 127,
+ [0][0][2][0][RTW89_ETSI][0][45] = 127,
+ [0][0][2][0][RTW89_MKK][1][45] = 127,
+ [0][0][2][0][RTW89_MKK][0][45] = 127,
+ [0][0][2][0][RTW89_IC][1][45] = 22,
+ [0][0][2][0][RTW89_KCC][1][45] = 24,
+ [0][0][2][0][RTW89_KCC][0][45] = 127,
+ [0][0][2][0][RTW89_ACMA][1][45] = 127,
+ [0][0][2][0][RTW89_ACMA][0][45] = 127,
+ [0][0][2][0][RTW89_CHILE][1][45] = 22,
+ [0][0][2][0][RTW89_QATAR][1][45] = 127,
+ [0][0][2][0][RTW89_QATAR][0][45] = 127,
+ [0][0][2][0][RTW89_UK][1][45] = 127,
+ [0][0][2][0][RTW89_UK][0][45] = 127,
+ [0][0][2][0][RTW89_FCC][1][47] = 22,
+ [0][0][2][0][RTW89_FCC][2][47] = 127,
+ [0][0][2][0][RTW89_ETSI][1][47] = 127,
+ [0][0][2][0][RTW89_ETSI][0][47] = 127,
+ [0][0][2][0][RTW89_MKK][1][47] = 127,
+ [0][0][2][0][RTW89_MKK][0][47] = 127,
+ [0][0][2][0][RTW89_IC][1][47] = 22,
+ [0][0][2][0][RTW89_KCC][1][47] = 24,
+ [0][0][2][0][RTW89_KCC][0][47] = 127,
+ [0][0][2][0][RTW89_ACMA][1][47] = 127,
+ [0][0][2][0][RTW89_ACMA][0][47] = 127,
+ [0][0][2][0][RTW89_CHILE][1][47] = 22,
+ [0][0][2][0][RTW89_QATAR][1][47] = 127,
+ [0][0][2][0][RTW89_QATAR][0][47] = 127,
+ [0][0][2][0][RTW89_UK][1][47] = 127,
+ [0][0][2][0][RTW89_UK][0][47] = 127,
+ [0][0][2][0][RTW89_FCC][1][49] = 24,
+ [0][0][2][0][RTW89_FCC][2][49] = 127,
+ [0][0][2][0][RTW89_ETSI][1][49] = 127,
+ [0][0][2][0][RTW89_ETSI][0][49] = 127,
+ [0][0][2][0][RTW89_MKK][1][49] = 127,
+ [0][0][2][0][RTW89_MKK][0][49] = 127,
+ [0][0][2][0][RTW89_IC][1][49] = 24,
+ [0][0][2][0][RTW89_KCC][1][49] = 24,
+ [0][0][2][0][RTW89_KCC][0][49] = 127,
+ [0][0][2][0][RTW89_ACMA][1][49] = 127,
+ [0][0][2][0][RTW89_ACMA][0][49] = 127,
+ [0][0][2][0][RTW89_CHILE][1][49] = 24,
+ [0][0][2][0][RTW89_QATAR][1][49] = 127,
+ [0][0][2][0][RTW89_QATAR][0][49] = 127,
+ [0][0][2][0][RTW89_UK][1][49] = 127,
+ [0][0][2][0][RTW89_UK][0][49] = 127,
+ [0][0][2][0][RTW89_FCC][1][51] = 22,
+ [0][0][2][0][RTW89_FCC][2][51] = 127,
+ [0][0][2][0][RTW89_ETSI][1][51] = 127,
+ [0][0][2][0][RTW89_ETSI][0][51] = 127,
+ [0][0][2][0][RTW89_MKK][1][51] = 127,
+ [0][0][2][0][RTW89_MKK][0][51] = 127,
+ [0][0][2][0][RTW89_IC][1][51] = 22,
+ [0][0][2][0][RTW89_KCC][1][51] = 24,
+ [0][0][2][0][RTW89_KCC][0][51] = 127,
+ [0][0][2][0][RTW89_ACMA][1][51] = 127,
+ [0][0][2][0][RTW89_ACMA][0][51] = 127,
+ [0][0][2][0][RTW89_CHILE][1][51] = 22,
+ [0][0][2][0][RTW89_QATAR][1][51] = 127,
+ [0][0][2][0][RTW89_QATAR][0][51] = 127,
+ [0][0][2][0][RTW89_UK][1][51] = 127,
+ [0][0][2][0][RTW89_UK][0][51] = 127,
+ [0][0][2][0][RTW89_FCC][1][53] = 22,
+ [0][0][2][0][RTW89_FCC][2][53] = 127,
+ [0][0][2][0][RTW89_ETSI][1][53] = 127,
+ [0][0][2][0][RTW89_ETSI][0][53] = 127,
+ [0][0][2][0][RTW89_MKK][1][53] = 127,
+ [0][0][2][0][RTW89_MKK][0][53] = 127,
+ [0][0][2][0][RTW89_IC][1][53] = 22,
+ [0][0][2][0][RTW89_KCC][1][53] = 24,
+ [0][0][2][0][RTW89_KCC][0][53] = 127,
+ [0][0][2][0][RTW89_ACMA][1][53] = 127,
+ [0][0][2][0][RTW89_ACMA][0][53] = 127,
+ [0][0][2][0][RTW89_CHILE][1][53] = 22,
+ [0][0][2][0][RTW89_QATAR][1][53] = 127,
+ [0][0][2][0][RTW89_QATAR][0][53] = 127,
+ [0][0][2][0][RTW89_UK][1][53] = 127,
+ [0][0][2][0][RTW89_UK][0][53] = 127,
+ [0][0][2][0][RTW89_FCC][1][55] = 22,
+ [0][0][2][0][RTW89_FCC][2][55] = 68,
+ [0][0][2][0][RTW89_ETSI][1][55] = 127,
+ [0][0][2][0][RTW89_ETSI][0][55] = 127,
+ [0][0][2][0][RTW89_MKK][1][55] = 127,
+ [0][0][2][0][RTW89_MKK][0][55] = 127,
+ [0][0][2][0][RTW89_IC][1][55] = 22,
+ [0][0][2][0][RTW89_KCC][1][55] = 26,
+ [0][0][2][0][RTW89_KCC][0][55] = 127,
+ [0][0][2][0][RTW89_ACMA][1][55] = 127,
+ [0][0][2][0][RTW89_ACMA][0][55] = 127,
+ [0][0][2][0][RTW89_CHILE][1][55] = 22,
+ [0][0][2][0][RTW89_QATAR][1][55] = 127,
+ [0][0][2][0][RTW89_QATAR][0][55] = 127,
+ [0][0][2][0][RTW89_UK][1][55] = 127,
+ [0][0][2][0][RTW89_UK][0][55] = 127,
+ [0][0][2][0][RTW89_FCC][1][57] = 22,
+ [0][0][2][0][RTW89_FCC][2][57] = 68,
+ [0][0][2][0][RTW89_ETSI][1][57] = 127,
+ [0][0][2][0][RTW89_ETSI][0][57] = 127,
+ [0][0][2][0][RTW89_MKK][1][57] = 127,
+ [0][0][2][0][RTW89_MKK][0][57] = 127,
+ [0][0][2][0][RTW89_IC][1][57] = 22,
+ [0][0][2][0][RTW89_KCC][1][57] = 26,
+ [0][0][2][0][RTW89_KCC][0][57] = 127,
+ [0][0][2][0][RTW89_ACMA][1][57] = 127,
+ [0][0][2][0][RTW89_ACMA][0][57] = 127,
+ [0][0][2][0][RTW89_CHILE][1][57] = 22,
+ [0][0][2][0][RTW89_QATAR][1][57] = 127,
+ [0][0][2][0][RTW89_QATAR][0][57] = 127,
+ [0][0][2][0][RTW89_UK][1][57] = 127,
+ [0][0][2][0][RTW89_UK][0][57] = 127,
+ [0][0][2][0][RTW89_FCC][1][59] = 22,
+ [0][0][2][0][RTW89_FCC][2][59] = 68,
+ [0][0][2][0][RTW89_ETSI][1][59] = 127,
+ [0][0][2][0][RTW89_ETSI][0][59] = 127,
+ [0][0][2][0][RTW89_MKK][1][59] = 127,
+ [0][0][2][0][RTW89_MKK][0][59] = 127,
+ [0][0][2][0][RTW89_IC][1][59] = 22,
+ [0][0][2][0][RTW89_KCC][1][59] = 26,
+ [0][0][2][0][RTW89_KCC][0][59] = 127,
+ [0][0][2][0][RTW89_ACMA][1][59] = 127,
+ [0][0][2][0][RTW89_ACMA][0][59] = 127,
+ [0][0][2][0][RTW89_CHILE][1][59] = 22,
+ [0][0][2][0][RTW89_QATAR][1][59] = 127,
+ [0][0][2][0][RTW89_QATAR][0][59] = 127,
+ [0][0][2][0][RTW89_UK][1][59] = 127,
+ [0][0][2][0][RTW89_UK][0][59] = 127,
+ [0][0][2][0][RTW89_FCC][1][60] = 22,
+ [0][0][2][0][RTW89_FCC][2][60] = 68,
+ [0][0][2][0][RTW89_ETSI][1][60] = 127,
+ [0][0][2][0][RTW89_ETSI][0][60] = 127,
+ [0][0][2][0][RTW89_MKK][1][60] = 127,
+ [0][0][2][0][RTW89_MKK][0][60] = 127,
+ [0][0][2][0][RTW89_IC][1][60] = 22,
+ [0][0][2][0][RTW89_KCC][1][60] = 26,
+ [0][0][2][0][RTW89_KCC][0][60] = 127,
+ [0][0][2][0][RTW89_ACMA][1][60] = 127,
+ [0][0][2][0][RTW89_ACMA][0][60] = 127,
+ [0][0][2][0][RTW89_CHILE][1][60] = 22,
+ [0][0][2][0][RTW89_QATAR][1][60] = 127,
+ [0][0][2][0][RTW89_QATAR][0][60] = 127,
+ [0][0][2][0][RTW89_UK][1][60] = 127,
+ [0][0][2][0][RTW89_UK][0][60] = 127,
+ [0][0][2][0][RTW89_FCC][1][62] = 22,
+ [0][0][2][0][RTW89_FCC][2][62] = 68,
+ [0][0][2][0][RTW89_ETSI][1][62] = 127,
+ [0][0][2][0][RTW89_ETSI][0][62] = 127,
+ [0][0][2][0][RTW89_MKK][1][62] = 127,
+ [0][0][2][0][RTW89_MKK][0][62] = 127,
+ [0][0][2][0][RTW89_IC][1][62] = 22,
+ [0][0][2][0][RTW89_KCC][1][62] = 26,
+ [0][0][2][0][RTW89_KCC][0][62] = 127,
+ [0][0][2][0][RTW89_ACMA][1][62] = 127,
+ [0][0][2][0][RTW89_ACMA][0][62] = 127,
+ [0][0][2][0][RTW89_CHILE][1][62] = 22,
+ [0][0][2][0][RTW89_QATAR][1][62] = 127,
+ [0][0][2][0][RTW89_QATAR][0][62] = 127,
+ [0][0][2][0][RTW89_UK][1][62] = 127,
+ [0][0][2][0][RTW89_UK][0][62] = 127,
+ [0][0][2][0][RTW89_FCC][1][64] = 22,
+ [0][0][2][0][RTW89_FCC][2][64] = 68,
+ [0][0][2][0][RTW89_ETSI][1][64] = 127,
+ [0][0][2][0][RTW89_ETSI][0][64] = 127,
+ [0][0][2][0][RTW89_MKK][1][64] = 127,
+ [0][0][2][0][RTW89_MKK][0][64] = 127,
+ [0][0][2][0][RTW89_IC][1][64] = 22,
+ [0][0][2][0][RTW89_KCC][1][64] = 26,
+ [0][0][2][0][RTW89_KCC][0][64] = 127,
+ [0][0][2][0][RTW89_ACMA][1][64] = 127,
+ [0][0][2][0][RTW89_ACMA][0][64] = 127,
+ [0][0][2][0][RTW89_CHILE][1][64] = 22,
+ [0][0][2][0][RTW89_QATAR][1][64] = 127,
+ [0][0][2][0][RTW89_QATAR][0][64] = 127,
+ [0][0][2][0][RTW89_UK][1][64] = 127,
+ [0][0][2][0][RTW89_UK][0][64] = 127,
+ [0][0][2][0][RTW89_FCC][1][66] = 22,
+ [0][0][2][0][RTW89_FCC][2][66] = 68,
+ [0][0][2][0][RTW89_ETSI][1][66] = 127,
+ [0][0][2][0][RTW89_ETSI][0][66] = 127,
+ [0][0][2][0][RTW89_MKK][1][66] = 127,
+ [0][0][2][0][RTW89_MKK][0][66] = 127,
+ [0][0][2][0][RTW89_IC][1][66] = 22,
+ [0][0][2][0][RTW89_KCC][1][66] = 26,
+ [0][0][2][0][RTW89_KCC][0][66] = 127,
+ [0][0][2][0][RTW89_ACMA][1][66] = 127,
+ [0][0][2][0][RTW89_ACMA][0][66] = 127,
+ [0][0][2][0][RTW89_CHILE][1][66] = 22,
+ [0][0][2][0][RTW89_QATAR][1][66] = 127,
+ [0][0][2][0][RTW89_QATAR][0][66] = 127,
+ [0][0][2][0][RTW89_UK][1][66] = 127,
+ [0][0][2][0][RTW89_UK][0][66] = 127,
+ [0][0][2][0][RTW89_FCC][1][68] = 22,
+ [0][0][2][0][RTW89_FCC][2][68] = 68,
+ [0][0][2][0][RTW89_ETSI][1][68] = 127,
+ [0][0][2][0][RTW89_ETSI][0][68] = 127,
+ [0][0][2][0][RTW89_MKK][1][68] = 127,
+ [0][0][2][0][RTW89_MKK][0][68] = 127,
+ [0][0][2][0][RTW89_IC][1][68] = 22,
+ [0][0][2][0][RTW89_KCC][1][68] = 26,
+ [0][0][2][0][RTW89_KCC][0][68] = 127,
+ [0][0][2][0][RTW89_ACMA][1][68] = 127,
+ [0][0][2][0][RTW89_ACMA][0][68] = 127,
+ [0][0][2][0][RTW89_CHILE][1][68] = 22,
+ [0][0][2][0][RTW89_QATAR][1][68] = 127,
+ [0][0][2][0][RTW89_QATAR][0][68] = 127,
+ [0][0][2][0][RTW89_UK][1][68] = 127,
+ [0][0][2][0][RTW89_UK][0][68] = 127,
+ [0][0][2][0][RTW89_FCC][1][70] = 24,
+ [0][0][2][0][RTW89_FCC][2][70] = 68,
+ [0][0][2][0][RTW89_ETSI][1][70] = 127,
+ [0][0][2][0][RTW89_ETSI][0][70] = 127,
+ [0][0][2][0][RTW89_MKK][1][70] = 127,
+ [0][0][2][0][RTW89_MKK][0][70] = 127,
+ [0][0][2][0][RTW89_IC][1][70] = 24,
+ [0][0][2][0][RTW89_KCC][1][70] = 26,
+ [0][0][2][0][RTW89_KCC][0][70] = 127,
+ [0][0][2][0][RTW89_ACMA][1][70] = 127,
+ [0][0][2][0][RTW89_ACMA][0][70] = 127,
+ [0][0][2][0][RTW89_CHILE][1][70] = 24,
+ [0][0][2][0][RTW89_QATAR][1][70] = 127,
+ [0][0][2][0][RTW89_QATAR][0][70] = 127,
+ [0][0][2][0][RTW89_UK][1][70] = 127,
+ [0][0][2][0][RTW89_UK][0][70] = 127,
+ [0][0][2][0][RTW89_FCC][1][72] = 22,
+ [0][0][2][0][RTW89_FCC][2][72] = 68,
+ [0][0][2][0][RTW89_ETSI][1][72] = 127,
+ [0][0][2][0][RTW89_ETSI][0][72] = 127,
+ [0][0][2][0][RTW89_MKK][1][72] = 127,
+ [0][0][2][0][RTW89_MKK][0][72] = 127,
+ [0][0][2][0][RTW89_IC][1][72] = 22,
+ [0][0][2][0][RTW89_KCC][1][72] = 26,
+ [0][0][2][0][RTW89_KCC][0][72] = 127,
+ [0][0][2][0][RTW89_ACMA][1][72] = 127,
+ [0][0][2][0][RTW89_ACMA][0][72] = 127,
+ [0][0][2][0][RTW89_CHILE][1][72] = 22,
+ [0][0][2][0][RTW89_QATAR][1][72] = 127,
+ [0][0][2][0][RTW89_QATAR][0][72] = 127,
+ [0][0][2][0][RTW89_UK][1][72] = 127,
+ [0][0][2][0][RTW89_UK][0][72] = 127,
+ [0][0][2][0][RTW89_FCC][1][74] = 22,
+ [0][0][2][0][RTW89_FCC][2][74] = 68,
+ [0][0][2][0][RTW89_ETSI][1][74] = 127,
+ [0][0][2][0][RTW89_ETSI][0][74] = 127,
+ [0][0][2][0][RTW89_MKK][1][74] = 127,
+ [0][0][2][0][RTW89_MKK][0][74] = 127,
+ [0][0][2][0][RTW89_IC][1][74] = 22,
+ [0][0][2][0][RTW89_KCC][1][74] = 26,
+ [0][0][2][0][RTW89_KCC][0][74] = 127,
+ [0][0][2][0][RTW89_ACMA][1][74] = 127,
+ [0][0][2][0][RTW89_ACMA][0][74] = 127,
+ [0][0][2][0][RTW89_CHILE][1][74] = 22,
+ [0][0][2][0][RTW89_QATAR][1][74] = 127,
+ [0][0][2][0][RTW89_QATAR][0][74] = 127,
+ [0][0][2][0][RTW89_UK][1][74] = 127,
+ [0][0][2][0][RTW89_UK][0][74] = 127,
+ [0][0][2][0][RTW89_FCC][1][75] = 22,
+ [0][0][2][0][RTW89_FCC][2][75] = 68,
+ [0][0][2][0][RTW89_ETSI][1][75] = 127,
+ [0][0][2][0][RTW89_ETSI][0][75] = 127,
+ [0][0][2][0][RTW89_MKK][1][75] = 127,
+ [0][0][2][0][RTW89_MKK][0][75] = 127,
+ [0][0][2][0][RTW89_IC][1][75] = 22,
+ [0][0][2][0][RTW89_KCC][1][75] = 26,
+ [0][0][2][0][RTW89_KCC][0][75] = 127,
+ [0][0][2][0][RTW89_ACMA][1][75] = 127,
+ [0][0][2][0][RTW89_ACMA][0][75] = 127,
+ [0][0][2][0][RTW89_CHILE][1][75] = 22,
+ [0][0][2][0][RTW89_QATAR][1][75] = 127,
+ [0][0][2][0][RTW89_QATAR][0][75] = 127,
+ [0][0][2][0][RTW89_UK][1][75] = 127,
+ [0][0][2][0][RTW89_UK][0][75] = 127,
+ [0][0][2][0][RTW89_FCC][1][77] = 22,
+ [0][0][2][0][RTW89_FCC][2][77] = 68,
+ [0][0][2][0][RTW89_ETSI][1][77] = 127,
+ [0][0][2][0][RTW89_ETSI][0][77] = 127,
+ [0][0][2][0][RTW89_MKK][1][77] = 127,
+ [0][0][2][0][RTW89_MKK][0][77] = 127,
+ [0][0][2][0][RTW89_IC][1][77] = 22,
+ [0][0][2][0][RTW89_KCC][1][77] = 26,
+ [0][0][2][0][RTW89_KCC][0][77] = 127,
+ [0][0][2][0][RTW89_ACMA][1][77] = 127,
+ [0][0][2][0][RTW89_ACMA][0][77] = 127,
+ [0][0][2][0][RTW89_CHILE][1][77] = 22,
+ [0][0][2][0][RTW89_QATAR][1][77] = 127,
+ [0][0][2][0][RTW89_QATAR][0][77] = 127,
+ [0][0][2][0][RTW89_UK][1][77] = 127,
+ [0][0][2][0][RTW89_UK][0][77] = 127,
+ [0][0][2][0][RTW89_FCC][1][79] = 22,
+ [0][0][2][0][RTW89_FCC][2][79] = 68,
+ [0][0][2][0][RTW89_ETSI][1][79] = 127,
+ [0][0][2][0][RTW89_ETSI][0][79] = 127,
+ [0][0][2][0][RTW89_MKK][1][79] = 127,
+ [0][0][2][0][RTW89_MKK][0][79] = 127,
+ [0][0][2][0][RTW89_IC][1][79] = 22,
+ [0][0][2][0][RTW89_KCC][1][79] = 26,
+ [0][0][2][0][RTW89_KCC][0][79] = 127,
+ [0][0][2][0][RTW89_ACMA][1][79] = 127,
+ [0][0][2][0][RTW89_ACMA][0][79] = 127,
+ [0][0][2][0][RTW89_CHILE][1][79] = 22,
+ [0][0][2][0][RTW89_QATAR][1][79] = 127,
+ [0][0][2][0][RTW89_QATAR][0][79] = 127,
+ [0][0][2][0][RTW89_UK][1][79] = 127,
+ [0][0][2][0][RTW89_UK][0][79] = 127,
+ [0][0][2][0][RTW89_FCC][1][81] = 22,
+ [0][0][2][0][RTW89_FCC][2][81] = 68,
+ [0][0][2][0][RTW89_ETSI][1][81] = 127,
+ [0][0][2][0][RTW89_ETSI][0][81] = 127,
+ [0][0][2][0][RTW89_MKK][1][81] = 127,
+ [0][0][2][0][RTW89_MKK][0][81] = 127,
+ [0][0][2][0][RTW89_IC][1][81] = 22,
+ [0][0][2][0][RTW89_KCC][1][81] = 26,
+ [0][0][2][0][RTW89_KCC][0][81] = 127,
+ [0][0][2][0][RTW89_ACMA][1][81] = 127,
+ [0][0][2][0][RTW89_ACMA][0][81] = 127,
+ [0][0][2][0][RTW89_CHILE][1][81] = 22,
+ [0][0][2][0][RTW89_QATAR][1][81] = 127,
+ [0][0][2][0][RTW89_QATAR][0][81] = 127,
+ [0][0][2][0][RTW89_UK][1][81] = 127,
+ [0][0][2][0][RTW89_UK][0][81] = 127,
+ [0][0][2][0][RTW89_FCC][1][83] = 22,
+ [0][0][2][0][RTW89_FCC][2][83] = 68,
+ [0][0][2][0][RTW89_ETSI][1][83] = 127,
+ [0][0][2][0][RTW89_ETSI][0][83] = 127,
+ [0][0][2][0][RTW89_MKK][1][83] = 127,
+ [0][0][2][0][RTW89_MKK][0][83] = 127,
+ [0][0][2][0][RTW89_IC][1][83] = 22,
+ [0][0][2][0][RTW89_KCC][1][83] = 32,
+ [0][0][2][0][RTW89_KCC][0][83] = 127,
+ [0][0][2][0][RTW89_ACMA][1][83] = 127,
+ [0][0][2][0][RTW89_ACMA][0][83] = 127,
+ [0][0][2][0][RTW89_CHILE][1][83] = 22,
+ [0][0][2][0][RTW89_QATAR][1][83] = 127,
+ [0][0][2][0][RTW89_QATAR][0][83] = 127,
+ [0][0][2][0][RTW89_UK][1][83] = 127,
+ [0][0][2][0][RTW89_UK][0][83] = 127,
+ [0][0][2][0][RTW89_FCC][1][85] = 22,
+ [0][0][2][0][RTW89_FCC][2][85] = 68,
+ [0][0][2][0][RTW89_ETSI][1][85] = 127,
+ [0][0][2][0][RTW89_ETSI][0][85] = 127,
+ [0][0][2][0][RTW89_MKK][1][85] = 127,
+ [0][0][2][0][RTW89_MKK][0][85] = 127,
+ [0][0][2][0][RTW89_IC][1][85] = 22,
+ [0][0][2][0][RTW89_KCC][1][85] = 32,
+ [0][0][2][0][RTW89_KCC][0][85] = 127,
+ [0][0][2][0][RTW89_ACMA][1][85] = 127,
+ [0][0][2][0][RTW89_ACMA][0][85] = 127,
+ [0][0][2][0][RTW89_CHILE][1][85] = 22,
+ [0][0][2][0][RTW89_QATAR][1][85] = 127,
+ [0][0][2][0][RTW89_QATAR][0][85] = 127,
+ [0][0][2][0][RTW89_UK][1][85] = 127,
+ [0][0][2][0][RTW89_UK][0][85] = 127,
+ [0][0][2][0][RTW89_FCC][1][87] = 22,
+ [0][0][2][0][RTW89_FCC][2][87] = 127,
+ [0][0][2][0][RTW89_ETSI][1][87] = 127,
+ [0][0][2][0][RTW89_ETSI][0][87] = 127,
+ [0][0][2][0][RTW89_MKK][1][87] = 127,
+ [0][0][2][0][RTW89_MKK][0][87] = 127,
+ [0][0][2][0][RTW89_IC][1][87] = 22,
+ [0][0][2][0][RTW89_KCC][1][87] = 32,
+ [0][0][2][0][RTW89_KCC][0][87] = 127,
+ [0][0][2][0][RTW89_ACMA][1][87] = 127,
+ [0][0][2][0][RTW89_ACMA][0][87] = 127,
+ [0][0][2][0][RTW89_CHILE][1][87] = 22,
+ [0][0][2][0][RTW89_QATAR][1][87] = 127,
+ [0][0][2][0][RTW89_QATAR][0][87] = 127,
+ [0][0][2][0][RTW89_UK][1][87] = 127,
+ [0][0][2][0][RTW89_UK][0][87] = 127,
+ [0][0][2][0][RTW89_FCC][1][89] = 22,
+ [0][0][2][0][RTW89_FCC][2][89] = 127,
+ [0][0][2][0][RTW89_ETSI][1][89] = 127,
+ [0][0][2][0][RTW89_ETSI][0][89] = 127,
+ [0][0][2][0][RTW89_MKK][1][89] = 127,
+ [0][0][2][0][RTW89_MKK][0][89] = 127,
+ [0][0][2][0][RTW89_IC][1][89] = 22,
+ [0][0][2][0][RTW89_KCC][1][89] = 32,
+ [0][0][2][0][RTW89_KCC][0][89] = 127,
+ [0][0][2][0][RTW89_ACMA][1][89] = 127,
+ [0][0][2][0][RTW89_ACMA][0][89] = 127,
+ [0][0][2][0][RTW89_CHILE][1][89] = 22,
+ [0][0][2][0][RTW89_QATAR][1][89] = 127,
+ [0][0][2][0][RTW89_QATAR][0][89] = 127,
+ [0][0][2][0][RTW89_UK][1][89] = 127,
+ [0][0][2][0][RTW89_UK][0][89] = 127,
+ [0][0][2][0][RTW89_FCC][1][90] = 22,
+ [0][0][2][0][RTW89_FCC][2][90] = 127,
+ [0][0][2][0][RTW89_ETSI][1][90] = 127,
+ [0][0][2][0][RTW89_ETSI][0][90] = 127,
+ [0][0][2][0][RTW89_MKK][1][90] = 127,
+ [0][0][2][0][RTW89_MKK][0][90] = 127,
+ [0][0][2][0][RTW89_IC][1][90] = 22,
+ [0][0][2][0][RTW89_KCC][1][90] = 32,
+ [0][0][2][0][RTW89_KCC][0][90] = 127,
+ [0][0][2][0][RTW89_ACMA][1][90] = 127,
+ [0][0][2][0][RTW89_ACMA][0][90] = 127,
+ [0][0][2][0][RTW89_CHILE][1][90] = 22,
+ [0][0][2][0][RTW89_QATAR][1][90] = 127,
+ [0][0][2][0][RTW89_QATAR][0][90] = 127,
+ [0][0][2][0][RTW89_UK][1][90] = 127,
+ [0][0][2][0][RTW89_UK][0][90] = 127,
+ [0][0][2][0][RTW89_FCC][1][92] = 22,
+ [0][0][2][0][RTW89_FCC][2][92] = 127,
+ [0][0][2][0][RTW89_ETSI][1][92] = 127,
+ [0][0][2][0][RTW89_ETSI][0][92] = 127,
+ [0][0][2][0][RTW89_MKK][1][92] = 127,
+ [0][0][2][0][RTW89_MKK][0][92] = 127,
+ [0][0][2][0][RTW89_IC][1][92] = 22,
+ [0][0][2][0][RTW89_KCC][1][92] = 32,
+ [0][0][2][0][RTW89_KCC][0][92] = 127,
+ [0][0][2][0][RTW89_ACMA][1][92] = 127,
+ [0][0][2][0][RTW89_ACMA][0][92] = 127,
+ [0][0][2][0][RTW89_CHILE][1][92] = 22,
+ [0][0][2][0][RTW89_QATAR][1][92] = 127,
+ [0][0][2][0][RTW89_QATAR][0][92] = 127,
+ [0][0][2][0][RTW89_UK][1][92] = 127,
+ [0][0][2][0][RTW89_UK][0][92] = 127,
+ [0][0][2][0][RTW89_FCC][1][94] = 22,
+ [0][0][2][0][RTW89_FCC][2][94] = 127,
+ [0][0][2][0][RTW89_ETSI][1][94] = 127,
+ [0][0][2][0][RTW89_ETSI][0][94] = 127,
+ [0][0][2][0][RTW89_MKK][1][94] = 127,
+ [0][0][2][0][RTW89_MKK][0][94] = 127,
+ [0][0][2][0][RTW89_IC][1][94] = 22,
+ [0][0][2][0][RTW89_KCC][1][94] = 32,
+ [0][0][2][0][RTW89_KCC][0][94] = 127,
+ [0][0][2][0][RTW89_ACMA][1][94] = 127,
+ [0][0][2][0][RTW89_ACMA][0][94] = 127,
+ [0][0][2][0][RTW89_CHILE][1][94] = 22,
+ [0][0][2][0][RTW89_QATAR][1][94] = 127,
+ [0][0][2][0][RTW89_QATAR][0][94] = 127,
+ [0][0][2][0][RTW89_UK][1][94] = 127,
+ [0][0][2][0][RTW89_UK][0][94] = 127,
+ [0][0][2][0][RTW89_FCC][1][96] = 22,
+ [0][0][2][0][RTW89_FCC][2][96] = 127,
+ [0][0][2][0][RTW89_ETSI][1][96] = 127,
+ [0][0][2][0][RTW89_ETSI][0][96] = 127,
+ [0][0][2][0][RTW89_MKK][1][96] = 127,
+ [0][0][2][0][RTW89_MKK][0][96] = 127,
+ [0][0][2][0][RTW89_IC][1][96] = 22,
+ [0][0][2][0][RTW89_KCC][1][96] = 32,
+ [0][0][2][0][RTW89_KCC][0][96] = 127,
+ [0][0][2][0][RTW89_ACMA][1][96] = 127,
+ [0][0][2][0][RTW89_ACMA][0][96] = 127,
+ [0][0][2][0][RTW89_CHILE][1][96] = 22,
+ [0][0][2][0][RTW89_QATAR][1][96] = 127,
+ [0][0][2][0][RTW89_QATAR][0][96] = 127,
+ [0][0][2][0][RTW89_UK][1][96] = 127,
+ [0][0][2][0][RTW89_UK][0][96] = 127,
+ [0][0][2][0][RTW89_FCC][1][98] = 22,
+ [0][0][2][0][RTW89_FCC][2][98] = 127,
+ [0][0][2][0][RTW89_ETSI][1][98] = 127,
+ [0][0][2][0][RTW89_ETSI][0][98] = 127,
+ [0][0][2][0][RTW89_MKK][1][98] = 127,
+ [0][0][2][0][RTW89_MKK][0][98] = 127,
+ [0][0][2][0][RTW89_IC][1][98] = 22,
+ [0][0][2][0][RTW89_KCC][1][98] = 32,
+ [0][0][2][0][RTW89_KCC][0][98] = 127,
+ [0][0][2][0][RTW89_ACMA][1][98] = 127,
+ [0][0][2][0][RTW89_ACMA][0][98] = 127,
+ [0][0][2][0][RTW89_CHILE][1][98] = 22,
+ [0][0][2][0][RTW89_QATAR][1][98] = 127,
+ [0][0][2][0][RTW89_QATAR][0][98] = 127,
+ [0][0][2][0][RTW89_UK][1][98] = 127,
+ [0][0][2][0][RTW89_UK][0][98] = 127,
+ [0][0][2][0][RTW89_FCC][1][100] = 22,
+ [0][0][2][0][RTW89_FCC][2][100] = 127,
+ [0][0][2][0][RTW89_ETSI][1][100] = 127,
+ [0][0][2][0][RTW89_ETSI][0][100] = 127,
+ [0][0][2][0][RTW89_MKK][1][100] = 127,
+ [0][0][2][0][RTW89_MKK][0][100] = 127,
+ [0][0][2][0][RTW89_IC][1][100] = 22,
+ [0][0][2][0][RTW89_KCC][1][100] = 32,
+ [0][0][2][0][RTW89_KCC][0][100] = 127,
+ [0][0][2][0][RTW89_ACMA][1][100] = 127,
+ [0][0][2][0][RTW89_ACMA][0][100] = 127,
+ [0][0][2][0][RTW89_CHILE][1][100] = 22,
+ [0][0][2][0][RTW89_QATAR][1][100] = 127,
+ [0][0][2][0][RTW89_QATAR][0][100] = 127,
+ [0][0][2][0][RTW89_UK][1][100] = 127,
+ [0][0][2][0][RTW89_UK][0][100] = 127,
+ [0][0][2][0][RTW89_FCC][1][102] = 22,
+ [0][0][2][0][RTW89_FCC][2][102] = 127,
+ [0][0][2][0][RTW89_ETSI][1][102] = 127,
+ [0][0][2][0][RTW89_ETSI][0][102] = 127,
+ [0][0][2][0][RTW89_MKK][1][102] = 127,
+ [0][0][2][0][RTW89_MKK][0][102] = 127,
+ [0][0][2][0][RTW89_IC][1][102] = 22,
+ [0][0][2][0][RTW89_KCC][1][102] = 32,
+ [0][0][2][0][RTW89_KCC][0][102] = 127,
+ [0][0][2][0][RTW89_ACMA][1][102] = 127,
+ [0][0][2][0][RTW89_ACMA][0][102] = 127,
+ [0][0][2][0][RTW89_CHILE][1][102] = 22,
+ [0][0][2][0][RTW89_QATAR][1][102] = 127,
+ [0][0][2][0][RTW89_QATAR][0][102] = 127,
+ [0][0][2][0][RTW89_UK][1][102] = 127,
+ [0][0][2][0][RTW89_UK][0][102] = 127,
+ [0][0][2][0][RTW89_FCC][1][104] = 22,
+ [0][0][2][0][RTW89_FCC][2][104] = 127,
+ [0][0][2][0][RTW89_ETSI][1][104] = 127,
+ [0][0][2][0][RTW89_ETSI][0][104] = 127,
+ [0][0][2][0][RTW89_MKK][1][104] = 127,
+ [0][0][2][0][RTW89_MKK][0][104] = 127,
+ [0][0][2][0][RTW89_IC][1][104] = 22,
+ [0][0][2][0][RTW89_KCC][1][104] = 32,
+ [0][0][2][0][RTW89_KCC][0][104] = 127,
+ [0][0][2][0][RTW89_ACMA][1][104] = 127,
+ [0][0][2][0][RTW89_ACMA][0][104] = 127,
+ [0][0][2][0][RTW89_CHILE][1][104] = 22,
+ [0][0][2][0][RTW89_QATAR][1][104] = 127,
+ [0][0][2][0][RTW89_QATAR][0][104] = 127,
+ [0][0][2][0][RTW89_UK][1][104] = 127,
+ [0][0][2][0][RTW89_UK][0][104] = 127,
+ [0][0][2][0][RTW89_FCC][1][105] = 22,
+ [0][0][2][0][RTW89_FCC][2][105] = 127,
+ [0][0][2][0][RTW89_ETSI][1][105] = 127,
+ [0][0][2][0][RTW89_ETSI][0][105] = 127,
+ [0][0][2][0][RTW89_MKK][1][105] = 127,
+ [0][0][2][0][RTW89_MKK][0][105] = 127,
+ [0][0][2][0][RTW89_IC][1][105] = 22,
+ [0][0][2][0][RTW89_KCC][1][105] = 32,
+ [0][0][2][0][RTW89_KCC][0][105] = 127,
+ [0][0][2][0][RTW89_ACMA][1][105] = 127,
+ [0][0][2][0][RTW89_ACMA][0][105] = 127,
+ [0][0][2][0][RTW89_CHILE][1][105] = 22,
+ [0][0][2][0][RTW89_QATAR][1][105] = 127,
+ [0][0][2][0][RTW89_QATAR][0][105] = 127,
+ [0][0][2][0][RTW89_UK][1][105] = 127,
+ [0][0][2][0][RTW89_UK][0][105] = 127,
+ [0][0][2][0][RTW89_FCC][1][107] = 24,
+ [0][0][2][0][RTW89_FCC][2][107] = 127,
+ [0][0][2][0][RTW89_ETSI][1][107] = 127,
+ [0][0][2][0][RTW89_ETSI][0][107] = 127,
+ [0][0][2][0][RTW89_MKK][1][107] = 127,
+ [0][0][2][0][RTW89_MKK][0][107] = 127,
+ [0][0][2][0][RTW89_IC][1][107] = 24,
+ [0][0][2][0][RTW89_KCC][1][107] = 32,
+ [0][0][2][0][RTW89_KCC][0][107] = 127,
+ [0][0][2][0][RTW89_ACMA][1][107] = 127,
+ [0][0][2][0][RTW89_ACMA][0][107] = 127,
+ [0][0][2][0][RTW89_CHILE][1][107] = 24,
+ [0][0][2][0][RTW89_QATAR][1][107] = 127,
+ [0][0][2][0][RTW89_QATAR][0][107] = 127,
+ [0][0][2][0][RTW89_UK][1][107] = 127,
+ [0][0][2][0][RTW89_UK][0][107] = 127,
+ [0][0][2][0][RTW89_FCC][1][109] = 24,
+ [0][0][2][0][RTW89_FCC][2][109] = 127,
+ [0][0][2][0][RTW89_ETSI][1][109] = 127,
+ [0][0][2][0][RTW89_ETSI][0][109] = 127,
+ [0][0][2][0][RTW89_MKK][1][109] = 127,
+ [0][0][2][0][RTW89_MKK][0][109] = 127,
+ [0][0][2][0][RTW89_IC][1][109] = 24,
+ [0][0][2][0][RTW89_KCC][1][109] = 32,
+ [0][0][2][0][RTW89_KCC][0][109] = 127,
+ [0][0][2][0][RTW89_ACMA][1][109] = 127,
+ [0][0][2][0][RTW89_ACMA][0][109] = 127,
+ [0][0][2][0][RTW89_CHILE][1][109] = 24,
+ [0][0][2][0][RTW89_QATAR][1][109] = 127,
+ [0][0][2][0][RTW89_QATAR][0][109] = 127,
+ [0][0][2][0][RTW89_UK][1][109] = 127,
+ [0][0][2][0][RTW89_UK][0][109] = 127,
+ [0][0][2][0][RTW89_FCC][1][111] = 127,
+ [0][0][2][0][RTW89_FCC][2][111] = 127,
+ [0][0][2][0][RTW89_ETSI][1][111] = 127,
+ [0][0][2][0][RTW89_ETSI][0][111] = 127,
+ [0][0][2][0][RTW89_MKK][1][111] = 127,
+ [0][0][2][0][RTW89_MKK][0][111] = 127,
+ [0][0][2][0][RTW89_IC][1][111] = 127,
+ [0][0][2][0][RTW89_KCC][1][111] = 127,
+ [0][0][2][0][RTW89_KCC][0][111] = 127,
+ [0][0][2][0][RTW89_ACMA][1][111] = 127,
+ [0][0][2][0][RTW89_ACMA][0][111] = 127,
+ [0][0][2][0][RTW89_CHILE][1][111] = 127,
+ [0][0][2][0][RTW89_QATAR][1][111] = 127,
+ [0][0][2][0][RTW89_QATAR][0][111] = 127,
+ [0][0][2][0][RTW89_UK][1][111] = 127,
+ [0][0][2][0][RTW89_UK][0][111] = 127,
+ [0][0][2][0][RTW89_FCC][1][113] = 127,
+ [0][0][2][0][RTW89_FCC][2][113] = 127,
+ [0][0][2][0][RTW89_ETSI][1][113] = 127,
+ [0][0][2][0][RTW89_ETSI][0][113] = 127,
+ [0][0][2][0][RTW89_MKK][1][113] = 127,
+ [0][0][2][0][RTW89_MKK][0][113] = 127,
+ [0][0][2][0][RTW89_IC][1][113] = 127,
+ [0][0][2][0][RTW89_KCC][1][113] = 127,
+ [0][0][2][0][RTW89_KCC][0][113] = 127,
+ [0][0][2][0][RTW89_ACMA][1][113] = 127,
+ [0][0][2][0][RTW89_ACMA][0][113] = 127,
+ [0][0][2][0][RTW89_CHILE][1][113] = 127,
+ [0][0][2][0][RTW89_QATAR][1][113] = 127,
+ [0][0][2][0][RTW89_QATAR][0][113] = 127,
+ [0][0][2][0][RTW89_UK][1][113] = 127,
+ [0][0][2][0][RTW89_UK][0][113] = 127,
+ [0][0][2][0][RTW89_FCC][1][115] = 127,
+ [0][0][2][0][RTW89_FCC][2][115] = 127,
+ [0][0][2][0][RTW89_ETSI][1][115] = 127,
+ [0][0][2][0][RTW89_ETSI][0][115] = 127,
+ [0][0][2][0][RTW89_MKK][1][115] = 127,
+ [0][0][2][0][RTW89_MKK][0][115] = 127,
+ [0][0][2][0][RTW89_IC][1][115] = 127,
+ [0][0][2][0][RTW89_KCC][1][115] = 127,
+ [0][0][2][0][RTW89_KCC][0][115] = 127,
+ [0][0][2][0][RTW89_ACMA][1][115] = 127,
+ [0][0][2][0][RTW89_ACMA][0][115] = 127,
+ [0][0][2][0][RTW89_CHILE][1][115] = 127,
+ [0][0][2][0][RTW89_QATAR][1][115] = 127,
+ [0][0][2][0][RTW89_QATAR][0][115] = 127,
+ [0][0][2][0][RTW89_UK][1][115] = 127,
+ [0][0][2][0][RTW89_UK][0][115] = 127,
+ [0][0][2][0][RTW89_FCC][1][117] = 127,
+ [0][0][2][0][RTW89_FCC][2][117] = 127,
+ [0][0][2][0][RTW89_ETSI][1][117] = 127,
+ [0][0][2][0][RTW89_ETSI][0][117] = 127,
+ [0][0][2][0][RTW89_MKK][1][117] = 127,
+ [0][0][2][0][RTW89_MKK][0][117] = 127,
+ [0][0][2][0][RTW89_IC][1][117] = 127,
+ [0][0][2][0][RTW89_KCC][1][117] = 127,
+ [0][0][2][0][RTW89_KCC][0][117] = 127,
+ [0][0][2][0][RTW89_ACMA][1][117] = 127,
+ [0][0][2][0][RTW89_ACMA][0][117] = 127,
+ [0][0][2][0][RTW89_CHILE][1][117] = 127,
+ [0][0][2][0][RTW89_QATAR][1][117] = 127,
+ [0][0][2][0][RTW89_QATAR][0][117] = 127,
+ [0][0][2][0][RTW89_UK][1][117] = 127,
+ [0][0][2][0][RTW89_UK][0][117] = 127,
+ [0][0][2][0][RTW89_FCC][1][119] = 127,
+ [0][0][2][0][RTW89_FCC][2][119] = 127,
+ [0][0][2][0][RTW89_ETSI][1][119] = 127,
+ [0][0][2][0][RTW89_ETSI][0][119] = 127,
+ [0][0][2][0][RTW89_MKK][1][119] = 127,
+ [0][0][2][0][RTW89_MKK][0][119] = 127,
+ [0][0][2][0][RTW89_IC][1][119] = 127,
+ [0][0][2][0][RTW89_KCC][1][119] = 127,
+ [0][0][2][0][RTW89_KCC][0][119] = 127,
+ [0][0][2][0][RTW89_ACMA][1][119] = 127,
+ [0][0][2][0][RTW89_ACMA][0][119] = 127,
+ [0][0][2][0][RTW89_CHILE][1][119] = 127,
+ [0][0][2][0][RTW89_QATAR][1][119] = 127,
+ [0][0][2][0][RTW89_QATAR][0][119] = 127,
+ [0][0][2][0][RTW89_UK][1][119] = 127,
+ [0][0][2][0][RTW89_UK][0][119] = 127,
+ [0][1][2][0][RTW89_FCC][1][0] = -2,
+ [0][1][2][0][RTW89_FCC][2][0] = 54,
+ [0][1][2][0][RTW89_ETSI][1][0] = 54,
+ [0][1][2][0][RTW89_ETSI][0][0] = 18,
+ [0][1][2][0][RTW89_MKK][1][0] = 56,
+ [0][1][2][0][RTW89_MKK][0][0] = 16,
+ [0][1][2][0][RTW89_IC][1][0] = -2,
+ [0][1][2][0][RTW89_KCC][1][0] = 12,
+ [0][1][2][0][RTW89_KCC][0][0] = 10,
+ [0][1][2][0][RTW89_ACMA][1][0] = 54,
+ [0][1][2][0][RTW89_ACMA][0][0] = 18,
+ [0][1][2][0][RTW89_CHILE][1][0] = -2,
+ [0][1][2][0][RTW89_QATAR][1][0] = 54,
+ [0][1][2][0][RTW89_QATAR][0][0] = 18,
+ [0][1][2][0][RTW89_UK][1][0] = 54,
+ [0][1][2][0][RTW89_UK][0][0] = 18,
+ [0][1][2][0][RTW89_FCC][1][2] = -4,
+ [0][1][2][0][RTW89_FCC][2][2] = 54,
+ [0][1][2][0][RTW89_ETSI][1][2] = 54,
+ [0][1][2][0][RTW89_ETSI][0][2] = 18,
+ [0][1][2][0][RTW89_MKK][1][2] = 54,
+ [0][1][2][0][RTW89_MKK][0][2] = 16,
+ [0][1][2][0][RTW89_IC][1][2] = -4,
+ [0][1][2][0][RTW89_KCC][1][2] = 12,
+ [0][1][2][0][RTW89_KCC][0][2] = 12,
+ [0][1][2][0][RTW89_ACMA][1][2] = 54,
+ [0][1][2][0][RTW89_ACMA][0][2] = 18,
+ [0][1][2][0][RTW89_CHILE][1][2] = -4,
+ [0][1][2][0][RTW89_QATAR][1][2] = 54,
+ [0][1][2][0][RTW89_QATAR][0][2] = 18,
+ [0][1][2][0][RTW89_UK][1][2] = 54,
+ [0][1][2][0][RTW89_UK][0][2] = 18,
+ [0][1][2][0][RTW89_FCC][1][4] = -4,
+ [0][1][2][0][RTW89_FCC][2][4] = 54,
+ [0][1][2][0][RTW89_ETSI][1][4] = 54,
+ [0][1][2][0][RTW89_ETSI][0][4] = 18,
+ [0][1][2][0][RTW89_MKK][1][4] = 54,
+ [0][1][2][0][RTW89_MKK][0][4] = 16,
+ [0][1][2][0][RTW89_IC][1][4] = -4,
+ [0][1][2][0][RTW89_KCC][1][4] = 12,
+ [0][1][2][0][RTW89_KCC][0][4] = 12,
+ [0][1][2][0][RTW89_ACMA][1][4] = 54,
+ [0][1][2][0][RTW89_ACMA][0][4] = 18,
+ [0][1][2][0][RTW89_CHILE][1][4] = -4,
+ [0][1][2][0][RTW89_QATAR][1][4] = 54,
+ [0][1][2][0][RTW89_QATAR][0][4] = 18,
+ [0][1][2][0][RTW89_UK][1][4] = 54,
+ [0][1][2][0][RTW89_UK][0][4] = 18,
+ [0][1][2][0][RTW89_FCC][1][6] = -4,
+ [0][1][2][0][RTW89_FCC][2][6] = 54,
+ [0][1][2][0][RTW89_ETSI][1][6] = 54,
+ [0][1][2][0][RTW89_ETSI][0][6] = 18,
+ [0][1][2][0][RTW89_MKK][1][6] = 54,
+ [0][1][2][0][RTW89_MKK][0][6] = 16,
+ [0][1][2][0][RTW89_IC][1][6] = -4,
+ [0][1][2][0][RTW89_KCC][1][6] = 12,
+ [0][1][2][0][RTW89_KCC][0][6] = 12,
+ [0][1][2][0][RTW89_ACMA][1][6] = 54,
+ [0][1][2][0][RTW89_ACMA][0][6] = 18,
+ [0][1][2][0][RTW89_CHILE][1][6] = -4,
+ [0][1][2][0][RTW89_QATAR][1][6] = 54,
+ [0][1][2][0][RTW89_QATAR][0][6] = 18,
+ [0][1][2][0][RTW89_UK][1][6] = 54,
+ [0][1][2][0][RTW89_UK][0][6] = 18,
+ [0][1][2][0][RTW89_FCC][1][8] = -4,
+ [0][1][2][0][RTW89_FCC][2][8] = 54,
+ [0][1][2][0][RTW89_ETSI][1][8] = 54,
+ [0][1][2][0][RTW89_ETSI][0][8] = 18,
+ [0][1][2][0][RTW89_MKK][1][8] = 54,
+ [0][1][2][0][RTW89_MKK][0][8] = 16,
+ [0][1][2][0][RTW89_IC][1][8] = -4,
+ [0][1][2][0][RTW89_KCC][1][8] = 12,
+ [0][1][2][0][RTW89_KCC][0][8] = 12,
+ [0][1][2][0][RTW89_ACMA][1][8] = 54,
+ [0][1][2][0][RTW89_ACMA][0][8] = 18,
+ [0][1][2][0][RTW89_CHILE][1][8] = -4,
+ [0][1][2][0][RTW89_QATAR][1][8] = 54,
+ [0][1][2][0][RTW89_QATAR][0][8] = 18,
+ [0][1][2][0][RTW89_UK][1][8] = 54,
+ [0][1][2][0][RTW89_UK][0][8] = 18,
+ [0][1][2][0][RTW89_FCC][1][10] = -4,
+ [0][1][2][0][RTW89_FCC][2][10] = 54,
+ [0][1][2][0][RTW89_ETSI][1][10] = 54,
+ [0][1][2][0][RTW89_ETSI][0][10] = 18,
+ [0][1][2][0][RTW89_MKK][1][10] = 54,
+ [0][1][2][0][RTW89_MKK][0][10] = 16,
+ [0][1][2][0][RTW89_IC][1][10] = -4,
+ [0][1][2][0][RTW89_KCC][1][10] = 12,
+ [0][1][2][0][RTW89_KCC][0][10] = 12,
+ [0][1][2][0][RTW89_ACMA][1][10] = 54,
+ [0][1][2][0][RTW89_ACMA][0][10] = 18,
+ [0][1][2][0][RTW89_CHILE][1][10] = -4,
+ [0][1][2][0][RTW89_QATAR][1][10] = 54,
+ [0][1][2][0][RTW89_QATAR][0][10] = 18,
+ [0][1][2][0][RTW89_UK][1][10] = 54,
+ [0][1][2][0][RTW89_UK][0][10] = 18,
+ [0][1][2][0][RTW89_FCC][1][12] = -4,
+ [0][1][2][0][RTW89_FCC][2][12] = 54,
+ [0][1][2][0][RTW89_ETSI][1][12] = 54,
+ [0][1][2][0][RTW89_ETSI][0][12] = 18,
+ [0][1][2][0][RTW89_MKK][1][12] = 54,
+ [0][1][2][0][RTW89_MKK][0][12] = 16,
+ [0][1][2][0][RTW89_IC][1][12] = -4,
+ [0][1][2][0][RTW89_KCC][1][12] = 12,
+ [0][1][2][0][RTW89_KCC][0][12] = 12,
+ [0][1][2][0][RTW89_ACMA][1][12] = 54,
+ [0][1][2][0][RTW89_ACMA][0][12] = 18,
+ [0][1][2][0][RTW89_CHILE][1][12] = -4,
+ [0][1][2][0][RTW89_QATAR][1][12] = 54,
+ [0][1][2][0][RTW89_QATAR][0][12] = 18,
+ [0][1][2][0][RTW89_UK][1][12] = 54,
+ [0][1][2][0][RTW89_UK][0][12] = 18,
+ [0][1][2][0][RTW89_FCC][1][14] = -4,
+ [0][1][2][0][RTW89_FCC][2][14] = 54,
+ [0][1][2][0][RTW89_ETSI][1][14] = 54,
+ [0][1][2][0][RTW89_ETSI][0][14] = 18,
+ [0][1][2][0][RTW89_MKK][1][14] = 54,
+ [0][1][2][0][RTW89_MKK][0][14] = 16,
+ [0][1][2][0][RTW89_IC][1][14] = -4,
+ [0][1][2][0][RTW89_KCC][1][14] = 12,
+ [0][1][2][0][RTW89_KCC][0][14] = 12,
+ [0][1][2][0][RTW89_ACMA][1][14] = 54,
+ [0][1][2][0][RTW89_ACMA][0][14] = 18,
+ [0][1][2][0][RTW89_CHILE][1][14] = -4,
+ [0][1][2][0][RTW89_QATAR][1][14] = 54,
+ [0][1][2][0][RTW89_QATAR][0][14] = 18,
+ [0][1][2][0][RTW89_UK][1][14] = 54,
+ [0][1][2][0][RTW89_UK][0][14] = 18,
+ [0][1][2][0][RTW89_FCC][1][15] = -4,
+ [0][1][2][0][RTW89_FCC][2][15] = 54,
+ [0][1][2][0][RTW89_ETSI][1][15] = 54,
+ [0][1][2][0][RTW89_ETSI][0][15] = 18,
+ [0][1][2][0][RTW89_MKK][1][15] = 54,
+ [0][1][2][0][RTW89_MKK][0][15] = 16,
+ [0][1][2][0][RTW89_IC][1][15] = -4,
+ [0][1][2][0][RTW89_KCC][1][15] = 12,
+ [0][1][2][0][RTW89_KCC][0][15] = 12,
+ [0][1][2][0][RTW89_ACMA][1][15] = 54,
+ [0][1][2][0][RTW89_ACMA][0][15] = 18,
+ [0][1][2][0][RTW89_CHILE][1][15] = -4,
+ [0][1][2][0][RTW89_QATAR][1][15] = 54,
+ [0][1][2][0][RTW89_QATAR][0][15] = 18,
+ [0][1][2][0][RTW89_UK][1][15] = 54,
+ [0][1][2][0][RTW89_UK][0][15] = 18,
+ [0][1][2][0][RTW89_FCC][1][17] = -4,
+ [0][1][2][0][RTW89_FCC][2][17] = 54,
+ [0][1][2][0][RTW89_ETSI][1][17] = 54,
+ [0][1][2][0][RTW89_ETSI][0][17] = 18,
+ [0][1][2][0][RTW89_MKK][1][17] = 54,
+ [0][1][2][0][RTW89_MKK][0][17] = 16,
+ [0][1][2][0][RTW89_IC][1][17] = -4,
+ [0][1][2][0][RTW89_KCC][1][17] = 12,
+ [0][1][2][0][RTW89_KCC][0][17] = 12,
+ [0][1][2][0][RTW89_ACMA][1][17] = 54,
+ [0][1][2][0][RTW89_ACMA][0][17] = 18,
+ [0][1][2][0][RTW89_CHILE][1][17] = -4,
+ [0][1][2][0][RTW89_QATAR][1][17] = 54,
+ [0][1][2][0][RTW89_QATAR][0][17] = 18,
+ [0][1][2][0][RTW89_UK][1][17] = 54,
+ [0][1][2][0][RTW89_UK][0][17] = 18,
+ [0][1][2][0][RTW89_FCC][1][19] = -4,
+ [0][1][2][0][RTW89_FCC][2][19] = 54,
+ [0][1][2][0][RTW89_ETSI][1][19] = 54,
+ [0][1][2][0][RTW89_ETSI][0][19] = 18,
+ [0][1][2][0][RTW89_MKK][1][19] = 54,
+ [0][1][2][0][RTW89_MKK][0][19] = 16,
+ [0][1][2][0][RTW89_IC][1][19] = -4,
+ [0][1][2][0][RTW89_KCC][1][19] = 12,
+ [0][1][2][0][RTW89_KCC][0][19] = 12,
+ [0][1][2][0][RTW89_ACMA][1][19] = 54,
+ [0][1][2][0][RTW89_ACMA][0][19] = 18,
+ [0][1][2][0][RTW89_CHILE][1][19] = -4,
+ [0][1][2][0][RTW89_QATAR][1][19] = 54,
+ [0][1][2][0][RTW89_QATAR][0][19] = 18,
+ [0][1][2][0][RTW89_UK][1][19] = 54,
+ [0][1][2][0][RTW89_UK][0][19] = 18,
+ [0][1][2][0][RTW89_FCC][1][21] = -4,
+ [0][1][2][0][RTW89_FCC][2][21] = 54,
+ [0][1][2][0][RTW89_ETSI][1][21] = 54,
+ [0][1][2][0][RTW89_ETSI][0][21] = 18,
+ [0][1][2][0][RTW89_MKK][1][21] = 54,
+ [0][1][2][0][RTW89_MKK][0][21] = 16,
+ [0][1][2][0][RTW89_IC][1][21] = -4,
+ [0][1][2][0][RTW89_KCC][1][21] = 12,
+ [0][1][2][0][RTW89_KCC][0][21] = 12,
+ [0][1][2][0][RTW89_ACMA][1][21] = 54,
+ [0][1][2][0][RTW89_ACMA][0][21] = 18,
+ [0][1][2][0][RTW89_CHILE][1][21] = -4,
+ [0][1][2][0][RTW89_QATAR][1][21] = 54,
+ [0][1][2][0][RTW89_QATAR][0][21] = 18,
+ [0][1][2][0][RTW89_UK][1][21] = 54,
+ [0][1][2][0][RTW89_UK][0][21] = 18,
+ [0][1][2][0][RTW89_FCC][1][23] = -4,
+ [0][1][2][0][RTW89_FCC][2][23] = 68,
+ [0][1][2][0][RTW89_ETSI][1][23] = 54,
+ [0][1][2][0][RTW89_ETSI][0][23] = 18,
+ [0][1][2][0][RTW89_MKK][1][23] = 54,
+ [0][1][2][0][RTW89_MKK][0][23] = 16,
+ [0][1][2][0][RTW89_IC][1][23] = -4,
+ [0][1][2][0][RTW89_KCC][1][23] = 12,
+ [0][1][2][0][RTW89_KCC][0][23] = 10,
+ [0][1][2][0][RTW89_ACMA][1][23] = 54,
+ [0][1][2][0][RTW89_ACMA][0][23] = 18,
+ [0][1][2][0][RTW89_CHILE][1][23] = -4,
+ [0][1][2][0][RTW89_QATAR][1][23] = 54,
+ [0][1][2][0][RTW89_QATAR][0][23] = 18,
+ [0][1][2][0][RTW89_UK][1][23] = 54,
+ [0][1][2][0][RTW89_UK][0][23] = 18,
+ [0][1][2][0][RTW89_FCC][1][25] = -4,
+ [0][1][2][0][RTW89_FCC][2][25] = 68,
+ [0][1][2][0][RTW89_ETSI][1][25] = 54,
+ [0][1][2][0][RTW89_ETSI][0][25] = 18,
+ [0][1][2][0][RTW89_MKK][1][25] = 54,
+ [0][1][2][0][RTW89_MKK][0][25] = 16,
+ [0][1][2][0][RTW89_IC][1][25] = -4,
+ [0][1][2][0][RTW89_KCC][1][25] = 12,
+ [0][1][2][0][RTW89_KCC][0][25] = 14,
+ [0][1][2][0][RTW89_ACMA][1][25] = 54,
+ [0][1][2][0][RTW89_ACMA][0][25] = 18,
+ [0][1][2][0][RTW89_CHILE][1][25] = -4,
+ [0][1][2][0][RTW89_QATAR][1][25] = 54,
+ [0][1][2][0][RTW89_QATAR][0][25] = 18,
+ [0][1][2][0][RTW89_UK][1][25] = 54,
+ [0][1][2][0][RTW89_UK][0][25] = 18,
+ [0][1][2][0][RTW89_FCC][1][27] = -4,
+ [0][1][2][0][RTW89_FCC][2][27] = 68,
+ [0][1][2][0][RTW89_ETSI][1][27] = 54,
+ [0][1][2][0][RTW89_ETSI][0][27] = 18,
+ [0][1][2][0][RTW89_MKK][1][27] = 54,
+ [0][1][2][0][RTW89_MKK][0][27] = 16,
+ [0][1][2][0][RTW89_IC][1][27] = -4,
+ [0][1][2][0][RTW89_KCC][1][27] = 12,
+ [0][1][2][0][RTW89_KCC][0][27] = 14,
+ [0][1][2][0][RTW89_ACMA][1][27] = 54,
+ [0][1][2][0][RTW89_ACMA][0][27] = 18,
+ [0][1][2][0][RTW89_CHILE][1][27] = -4,
+ [0][1][2][0][RTW89_QATAR][1][27] = 54,
+ [0][1][2][0][RTW89_QATAR][0][27] = 18,
+ [0][1][2][0][RTW89_UK][1][27] = 54,
+ [0][1][2][0][RTW89_UK][0][27] = 18,
+ [0][1][2][0][RTW89_FCC][1][29] = -4,
+ [0][1][2][0][RTW89_FCC][2][29] = 68,
+ [0][1][2][0][RTW89_ETSI][1][29] = 54,
+ [0][1][2][0][RTW89_ETSI][0][29] = 18,
+ [0][1][2][0][RTW89_MKK][1][29] = 54,
+ [0][1][2][0][RTW89_MKK][0][29] = 16,
+ [0][1][2][0][RTW89_IC][1][29] = -4,
+ [0][1][2][0][RTW89_KCC][1][29] = 12,
+ [0][1][2][0][RTW89_KCC][0][29] = 14,
+ [0][1][2][0][RTW89_ACMA][1][29] = 54,
+ [0][1][2][0][RTW89_ACMA][0][29] = 18,
+ [0][1][2][0][RTW89_CHILE][1][29] = -4,
+ [0][1][2][0][RTW89_QATAR][1][29] = 54,
+ [0][1][2][0][RTW89_QATAR][0][29] = 18,
+ [0][1][2][0][RTW89_UK][1][29] = 54,
+ [0][1][2][0][RTW89_UK][0][29] = 18,
+ [0][1][2][0][RTW89_FCC][1][30] = -4,
+ [0][1][2][0][RTW89_FCC][2][30] = 68,
+ [0][1][2][0][RTW89_ETSI][1][30] = 54,
+ [0][1][2][0][RTW89_ETSI][0][30] = 18,
+ [0][1][2][0][RTW89_MKK][1][30] = 54,
+ [0][1][2][0][RTW89_MKK][0][30] = 16,
+ [0][1][2][0][RTW89_IC][1][30] = -4,
+ [0][1][2][0][RTW89_KCC][1][30] = 12,
+ [0][1][2][0][RTW89_KCC][0][30] = 14,
+ [0][1][2][0][RTW89_ACMA][1][30] = 54,
+ [0][1][2][0][RTW89_ACMA][0][30] = 18,
+ [0][1][2][0][RTW89_CHILE][1][30] = -4,
+ [0][1][2][0][RTW89_QATAR][1][30] = 54,
+ [0][1][2][0][RTW89_QATAR][0][30] = 18,
+ [0][1][2][0][RTW89_UK][1][30] = 54,
+ [0][1][2][0][RTW89_UK][0][30] = 18,
+ [0][1][2][0][RTW89_FCC][1][32] = -4,
+ [0][1][2][0][RTW89_FCC][2][32] = 68,
+ [0][1][2][0][RTW89_ETSI][1][32] = 54,
+ [0][1][2][0][RTW89_ETSI][0][32] = 18,
+ [0][1][2][0][RTW89_MKK][1][32] = 54,
+ [0][1][2][0][RTW89_MKK][0][32] = 16,
+ [0][1][2][0][RTW89_IC][1][32] = -4,
+ [0][1][2][0][RTW89_KCC][1][32] = 12,
+ [0][1][2][0][RTW89_KCC][0][32] = 14,
+ [0][1][2][0][RTW89_ACMA][1][32] = 54,
+ [0][1][2][0][RTW89_ACMA][0][32] = 18,
+ [0][1][2][0][RTW89_CHILE][1][32] = -4,
+ [0][1][2][0][RTW89_QATAR][1][32] = 54,
+ [0][1][2][0][RTW89_QATAR][0][32] = 18,
+ [0][1][2][0][RTW89_UK][1][32] = 54,
+ [0][1][2][0][RTW89_UK][0][32] = 18,
+ [0][1][2][0][RTW89_FCC][1][34] = -4,
+ [0][1][2][0][RTW89_FCC][2][34] = 68,
+ [0][1][2][0][RTW89_ETSI][1][34] = 54,
+ [0][1][2][0][RTW89_ETSI][0][34] = 18,
+ [0][1][2][0][RTW89_MKK][1][34] = 54,
+ [0][1][2][0][RTW89_MKK][0][34] = 16,
+ [0][1][2][0][RTW89_IC][1][34] = -4,
+ [0][1][2][0][RTW89_KCC][1][34] = 12,
+ [0][1][2][0][RTW89_KCC][0][34] = 14,
+ [0][1][2][0][RTW89_ACMA][1][34] = 54,
+ [0][1][2][0][RTW89_ACMA][0][34] = 18,
+ [0][1][2][0][RTW89_CHILE][1][34] = -4,
+ [0][1][2][0][RTW89_QATAR][1][34] = 54,
+ [0][1][2][0][RTW89_QATAR][0][34] = 18,
+ [0][1][2][0][RTW89_UK][1][34] = 54,
+ [0][1][2][0][RTW89_UK][0][34] = 18,
+ [0][1][2][0][RTW89_FCC][1][36] = -4,
+ [0][1][2][0][RTW89_FCC][2][36] = 68,
+ [0][1][2][0][RTW89_ETSI][1][36] = 54,
+ [0][1][2][0][RTW89_ETSI][0][36] = 18,
+ [0][1][2][0][RTW89_MKK][1][36] = 54,
+ [0][1][2][0][RTW89_MKK][0][36] = 16,
+ [0][1][2][0][RTW89_IC][1][36] = -4,
+ [0][1][2][0][RTW89_KCC][1][36] = 12,
+ [0][1][2][0][RTW89_KCC][0][36] = 14,
+ [0][1][2][0][RTW89_ACMA][1][36] = 54,
+ [0][1][2][0][RTW89_ACMA][0][36] = 18,
+ [0][1][2][0][RTW89_CHILE][1][36] = -4,
+ [0][1][2][0][RTW89_QATAR][1][36] = 54,
+ [0][1][2][0][RTW89_QATAR][0][36] = 18,
+ [0][1][2][0][RTW89_UK][1][36] = 54,
+ [0][1][2][0][RTW89_UK][0][36] = 18,
+ [0][1][2][0][RTW89_FCC][1][38] = -4,
+ [0][1][2][0][RTW89_FCC][2][38] = 68,
+ [0][1][2][0][RTW89_ETSI][1][38] = 54,
+ [0][1][2][0][RTW89_ETSI][0][38] = 18,
+ [0][1][2][0][RTW89_MKK][1][38] = 54,
+ [0][1][2][0][RTW89_MKK][0][38] = 16,
+ [0][1][2][0][RTW89_IC][1][38] = -4,
+ [0][1][2][0][RTW89_KCC][1][38] = 12,
+ [0][1][2][0][RTW89_KCC][0][38] = 14,
+ [0][1][2][0][RTW89_ACMA][1][38] = 54,
+ [0][1][2][0][RTW89_ACMA][0][38] = 18,
+ [0][1][2][0][RTW89_CHILE][1][38] = -4,
+ [0][1][2][0][RTW89_QATAR][1][38] = 54,
+ [0][1][2][0][RTW89_QATAR][0][38] = 18,
+ [0][1][2][0][RTW89_UK][1][38] = 54,
+ [0][1][2][0][RTW89_UK][0][38] = 18,
+ [0][1][2][0][RTW89_FCC][1][40] = -4,
+ [0][1][2][0][RTW89_FCC][2][40] = 68,
+ [0][1][2][0][RTW89_ETSI][1][40] = 54,
+ [0][1][2][0][RTW89_ETSI][0][40] = 18,
+ [0][1][2][0][RTW89_MKK][1][40] = 54,
+ [0][1][2][0][RTW89_MKK][0][40] = 16,
+ [0][1][2][0][RTW89_IC][1][40] = -4,
+ [0][1][2][0][RTW89_KCC][1][40] = 12,
+ [0][1][2][0][RTW89_KCC][0][40] = 14,
+ [0][1][2][0][RTW89_ACMA][1][40] = 54,
+ [0][1][2][0][RTW89_ACMA][0][40] = 18,
+ [0][1][2][0][RTW89_CHILE][1][40] = -4,
+ [0][1][2][0][RTW89_QATAR][1][40] = 54,
+ [0][1][2][0][RTW89_QATAR][0][40] = 18,
+ [0][1][2][0][RTW89_UK][1][40] = 54,
+ [0][1][2][0][RTW89_UK][0][40] = 18,
+ [0][1][2][0][RTW89_FCC][1][42] = -4,
+ [0][1][2][0][RTW89_FCC][2][42] = 68,
+ [0][1][2][0][RTW89_ETSI][1][42] = 54,
+ [0][1][2][0][RTW89_ETSI][0][42] = 18,
+ [0][1][2][0][RTW89_MKK][1][42] = 54,
+ [0][1][2][0][RTW89_MKK][0][42] = 16,
+ [0][1][2][0][RTW89_IC][1][42] = -4,
+ [0][1][2][0][RTW89_KCC][1][42] = 12,
+ [0][1][2][0][RTW89_KCC][0][42] = 14,
+ [0][1][2][0][RTW89_ACMA][1][42] = 54,
+ [0][1][2][0][RTW89_ACMA][0][42] = 18,
+ [0][1][2][0][RTW89_CHILE][1][42] = -4,
+ [0][1][2][0][RTW89_QATAR][1][42] = 54,
+ [0][1][2][0][RTW89_QATAR][0][42] = 18,
+ [0][1][2][0][RTW89_UK][1][42] = 54,
+ [0][1][2][0][RTW89_UK][0][42] = 18,
+ [0][1][2][0][RTW89_FCC][1][44] = -2,
+ [0][1][2][0][RTW89_FCC][2][44] = 68,
+ [0][1][2][0][RTW89_ETSI][1][44] = 54,
+ [0][1][2][0][RTW89_ETSI][0][44] = 18,
+ [0][1][2][0][RTW89_MKK][1][44] = 34,
+ [0][1][2][0][RTW89_MKK][0][44] = 16,
+ [0][1][2][0][RTW89_IC][1][44] = -2,
+ [0][1][2][0][RTW89_KCC][1][44] = 12,
+ [0][1][2][0][RTW89_KCC][0][44] = 12,
+ [0][1][2][0][RTW89_ACMA][1][44] = 54,
+ [0][1][2][0][RTW89_ACMA][0][44] = 18,
+ [0][1][2][0][RTW89_CHILE][1][44] = -2,
+ [0][1][2][0][RTW89_QATAR][1][44] = 54,
+ [0][1][2][0][RTW89_QATAR][0][44] = 18,
+ [0][1][2][0][RTW89_UK][1][44] = 54,
+ [0][1][2][0][RTW89_UK][0][44] = 18,
+ [0][1][2][0][RTW89_FCC][1][45] = -2,
+ [0][1][2][0][RTW89_FCC][2][45] = 127,
+ [0][1][2][0][RTW89_ETSI][1][45] = 127,
+ [0][1][2][0][RTW89_ETSI][0][45] = 127,
+ [0][1][2][0][RTW89_MKK][1][45] = 127,
+ [0][1][2][0][RTW89_MKK][0][45] = 127,
+ [0][1][2][0][RTW89_IC][1][45] = -2,
+ [0][1][2][0][RTW89_KCC][1][45] = 12,
+ [0][1][2][0][RTW89_KCC][0][45] = 127,
+ [0][1][2][0][RTW89_ACMA][1][45] = 127,
+ [0][1][2][0][RTW89_ACMA][0][45] = 127,
+ [0][1][2][0][RTW89_CHILE][1][45] = -2,
+ [0][1][2][0][RTW89_QATAR][1][45] = 127,
+ [0][1][2][0][RTW89_QATAR][0][45] = 127,
+ [0][1][2][0][RTW89_UK][1][45] = 127,
+ [0][1][2][0][RTW89_UK][0][45] = 127,
+ [0][1][2][0][RTW89_FCC][1][47] = -2,
+ [0][1][2][0][RTW89_FCC][2][47] = 127,
+ [0][1][2][0][RTW89_ETSI][1][47] = 127,
+ [0][1][2][0][RTW89_ETSI][0][47] = 127,
+ [0][1][2][0][RTW89_MKK][1][47] = 127,
+ [0][1][2][0][RTW89_MKK][0][47] = 127,
+ [0][1][2][0][RTW89_IC][1][47] = -2,
+ [0][1][2][0][RTW89_KCC][1][47] = 12,
+ [0][1][2][0][RTW89_KCC][0][47] = 127,
+ [0][1][2][0][RTW89_ACMA][1][47] = 127,
+ [0][1][2][0][RTW89_ACMA][0][47] = 127,
+ [0][1][2][0][RTW89_CHILE][1][47] = -2,
+ [0][1][2][0][RTW89_QATAR][1][47] = 127,
+ [0][1][2][0][RTW89_QATAR][0][47] = 127,
+ [0][1][2][0][RTW89_UK][1][47] = 127,
+ [0][1][2][0][RTW89_UK][0][47] = 127,
+ [0][1][2][0][RTW89_FCC][1][49] = -2,
+ [0][1][2][0][RTW89_FCC][2][49] = 127,
+ [0][1][2][0][RTW89_ETSI][1][49] = 127,
+ [0][1][2][0][RTW89_ETSI][0][49] = 127,
+ [0][1][2][0][RTW89_MKK][1][49] = 127,
+ [0][1][2][0][RTW89_MKK][0][49] = 127,
+ [0][1][2][0][RTW89_IC][1][49] = -2,
+ [0][1][2][0][RTW89_KCC][1][49] = 12,
+ [0][1][2][0][RTW89_KCC][0][49] = 127,
+ [0][1][2][0][RTW89_ACMA][1][49] = 127,
+ [0][1][2][0][RTW89_ACMA][0][49] = 127,
+ [0][1][2][0][RTW89_CHILE][1][49] = -2,
+ [0][1][2][0][RTW89_QATAR][1][49] = 127,
+ [0][1][2][0][RTW89_QATAR][0][49] = 127,
+ [0][1][2][0][RTW89_UK][1][49] = 127,
+ [0][1][2][0][RTW89_UK][0][49] = 127,
+ [0][1][2][0][RTW89_FCC][1][51] = -2,
+ [0][1][2][0][RTW89_FCC][2][51] = 127,
+ [0][1][2][0][RTW89_ETSI][1][51] = 127,
+ [0][1][2][0][RTW89_ETSI][0][51] = 127,
+ [0][1][2][0][RTW89_MKK][1][51] = 127,
+ [0][1][2][0][RTW89_MKK][0][51] = 127,
+ [0][1][2][0][RTW89_IC][1][51] = -2,
+ [0][1][2][0][RTW89_KCC][1][51] = 12,
+ [0][1][2][0][RTW89_KCC][0][51] = 127,
+ [0][1][2][0][RTW89_ACMA][1][51] = 127,
+ [0][1][2][0][RTW89_ACMA][0][51] = 127,
+ [0][1][2][0][RTW89_CHILE][1][51] = -2,
+ [0][1][2][0][RTW89_QATAR][1][51] = 127,
+ [0][1][2][0][RTW89_QATAR][0][51] = 127,
+ [0][1][2][0][RTW89_UK][1][51] = 127,
+ [0][1][2][0][RTW89_UK][0][51] = 127,
+ [0][1][2][0][RTW89_FCC][1][53] = -2,
+ [0][1][2][0][RTW89_FCC][2][53] = 127,
+ [0][1][2][0][RTW89_ETSI][1][53] = 127,
+ [0][1][2][0][RTW89_ETSI][0][53] = 127,
+ [0][1][2][0][RTW89_MKK][1][53] = 127,
+ [0][1][2][0][RTW89_MKK][0][53] = 127,
+ [0][1][2][0][RTW89_IC][1][53] = -2,
+ [0][1][2][0][RTW89_KCC][1][53] = 12,
+ [0][1][2][0][RTW89_KCC][0][53] = 127,
+ [0][1][2][0][RTW89_ACMA][1][53] = 127,
+ [0][1][2][0][RTW89_ACMA][0][53] = 127,
+ [0][1][2][0][RTW89_CHILE][1][53] = -2,
+ [0][1][2][0][RTW89_QATAR][1][53] = 127,
+ [0][1][2][0][RTW89_QATAR][0][53] = 127,
+ [0][1][2][0][RTW89_UK][1][53] = 127,
+ [0][1][2][0][RTW89_UK][0][53] = 127,
+ [0][1][2][0][RTW89_FCC][1][55] = -2,
+ [0][1][2][0][RTW89_FCC][2][55] = 68,
+ [0][1][2][0][RTW89_ETSI][1][55] = 127,
+ [0][1][2][0][RTW89_ETSI][0][55] = 127,
+ [0][1][2][0][RTW89_MKK][1][55] = 127,
+ [0][1][2][0][RTW89_MKK][0][55] = 127,
+ [0][1][2][0][RTW89_IC][1][55] = -2,
+ [0][1][2][0][RTW89_KCC][1][55] = 12,
+ [0][1][2][0][RTW89_KCC][0][55] = 127,
+ [0][1][2][0][RTW89_ACMA][1][55] = 127,
+ [0][1][2][0][RTW89_ACMA][0][55] = 127,
+ [0][1][2][0][RTW89_CHILE][1][55] = -2,
+ [0][1][2][0][RTW89_QATAR][1][55] = 127,
+ [0][1][2][0][RTW89_QATAR][0][55] = 127,
+ [0][1][2][0][RTW89_UK][1][55] = 127,
+ [0][1][2][0][RTW89_UK][0][55] = 127,
+ [0][1][2][0][RTW89_FCC][1][57] = -2,
+ [0][1][2][0][RTW89_FCC][2][57] = 68,
+ [0][1][2][0][RTW89_ETSI][1][57] = 127,
+ [0][1][2][0][RTW89_ETSI][0][57] = 127,
+ [0][1][2][0][RTW89_MKK][1][57] = 127,
+ [0][1][2][0][RTW89_MKK][0][57] = 127,
+ [0][1][2][0][RTW89_IC][1][57] = -2,
+ [0][1][2][0][RTW89_KCC][1][57] = 12,
+ [0][1][2][0][RTW89_KCC][0][57] = 127,
+ [0][1][2][0][RTW89_ACMA][1][57] = 127,
+ [0][1][2][0][RTW89_ACMA][0][57] = 127,
+ [0][1][2][0][RTW89_CHILE][1][57] = -2,
+ [0][1][2][0][RTW89_QATAR][1][57] = 127,
+ [0][1][2][0][RTW89_QATAR][0][57] = 127,
+ [0][1][2][0][RTW89_UK][1][57] = 127,
+ [0][1][2][0][RTW89_UK][0][57] = 127,
+ [0][1][2][0][RTW89_FCC][1][59] = -2,
+ [0][1][2][0][RTW89_FCC][2][59] = 68,
+ [0][1][2][0][RTW89_ETSI][1][59] = 127,
+ [0][1][2][0][RTW89_ETSI][0][59] = 127,
+ [0][1][2][0][RTW89_MKK][1][59] = 127,
+ [0][1][2][0][RTW89_MKK][0][59] = 127,
+ [0][1][2][0][RTW89_IC][1][59] = -2,
+ [0][1][2][0][RTW89_KCC][1][59] = 12,
+ [0][1][2][0][RTW89_KCC][0][59] = 127,
+ [0][1][2][0][RTW89_ACMA][1][59] = 127,
+ [0][1][2][0][RTW89_ACMA][0][59] = 127,
+ [0][1][2][0][RTW89_CHILE][1][59] = -2,
+ [0][1][2][0][RTW89_QATAR][1][59] = 127,
+ [0][1][2][0][RTW89_QATAR][0][59] = 127,
+ [0][1][2][0][RTW89_UK][1][59] = 127,
+ [0][1][2][0][RTW89_UK][0][59] = 127,
+ [0][1][2][0][RTW89_FCC][1][60] = -2,
+ [0][1][2][0][RTW89_FCC][2][60] = 68,
+ [0][1][2][0][RTW89_ETSI][1][60] = 127,
+ [0][1][2][0][RTW89_ETSI][0][60] = 127,
+ [0][1][2][0][RTW89_MKK][1][60] = 127,
+ [0][1][2][0][RTW89_MKK][0][60] = 127,
+ [0][1][2][0][RTW89_IC][1][60] = -2,
+ [0][1][2][0][RTW89_KCC][1][60] = 12,
+ [0][1][2][0][RTW89_KCC][0][60] = 127,
+ [0][1][2][0][RTW89_ACMA][1][60] = 127,
+ [0][1][2][0][RTW89_ACMA][0][60] = 127,
+ [0][1][2][0][RTW89_CHILE][1][60] = -2,
+ [0][1][2][0][RTW89_QATAR][1][60] = 127,
+ [0][1][2][0][RTW89_QATAR][0][60] = 127,
+ [0][1][2][0][RTW89_UK][1][60] = 127,
+ [0][1][2][0][RTW89_UK][0][60] = 127,
+ [0][1][2][0][RTW89_FCC][1][62] = -2,
+ [0][1][2][0][RTW89_FCC][2][62] = 68,
+ [0][1][2][0][RTW89_ETSI][1][62] = 127,
+ [0][1][2][0][RTW89_ETSI][0][62] = 127,
+ [0][1][2][0][RTW89_MKK][1][62] = 127,
+ [0][1][2][0][RTW89_MKK][0][62] = 127,
+ [0][1][2][0][RTW89_IC][1][62] = -2,
+ [0][1][2][0][RTW89_KCC][1][62] = 12,
+ [0][1][2][0][RTW89_KCC][0][62] = 127,
+ [0][1][2][0][RTW89_ACMA][1][62] = 127,
+ [0][1][2][0][RTW89_ACMA][0][62] = 127,
+ [0][1][2][0][RTW89_CHILE][1][62] = -2,
+ [0][1][2][0][RTW89_QATAR][1][62] = 127,
+ [0][1][2][0][RTW89_QATAR][0][62] = 127,
+ [0][1][2][0][RTW89_UK][1][62] = 127,
+ [0][1][2][0][RTW89_UK][0][62] = 127,
+ [0][1][2][0][RTW89_FCC][1][64] = -2,
+ [0][1][2][0][RTW89_FCC][2][64] = 68,
+ [0][1][2][0][RTW89_ETSI][1][64] = 127,
+ [0][1][2][0][RTW89_ETSI][0][64] = 127,
+ [0][1][2][0][RTW89_MKK][1][64] = 127,
+ [0][1][2][0][RTW89_MKK][0][64] = 127,
+ [0][1][2][0][RTW89_IC][1][64] = -2,
+ [0][1][2][0][RTW89_KCC][1][64] = 12,
+ [0][1][2][0][RTW89_KCC][0][64] = 127,
+ [0][1][2][0][RTW89_ACMA][1][64] = 127,
+ [0][1][2][0][RTW89_ACMA][0][64] = 127,
+ [0][1][2][0][RTW89_CHILE][1][64] = -2,
+ [0][1][2][0][RTW89_QATAR][1][64] = 127,
+ [0][1][2][0][RTW89_QATAR][0][64] = 127,
+ [0][1][2][0][RTW89_UK][1][64] = 127,
+ [0][1][2][0][RTW89_UK][0][64] = 127,
+ [0][1][2][0][RTW89_FCC][1][66] = -2,
+ [0][1][2][0][RTW89_FCC][2][66] = 68,
+ [0][1][2][0][RTW89_ETSI][1][66] = 127,
+ [0][1][2][0][RTW89_ETSI][0][66] = 127,
+ [0][1][2][0][RTW89_MKK][1][66] = 127,
+ [0][1][2][0][RTW89_MKK][0][66] = 127,
+ [0][1][2][0][RTW89_IC][1][66] = -2,
+ [0][1][2][0][RTW89_KCC][1][66] = 12,
+ [0][1][2][0][RTW89_KCC][0][66] = 127,
+ [0][1][2][0][RTW89_ACMA][1][66] = 127,
+ [0][1][2][0][RTW89_ACMA][0][66] = 127,
+ [0][1][2][0][RTW89_CHILE][1][66] = -2,
+ [0][1][2][0][RTW89_QATAR][1][66] = 127,
+ [0][1][2][0][RTW89_QATAR][0][66] = 127,
+ [0][1][2][0][RTW89_UK][1][66] = 127,
+ [0][1][2][0][RTW89_UK][0][66] = 127,
+ [0][1][2][0][RTW89_FCC][1][68] = -2,
+ [0][1][2][0][RTW89_FCC][2][68] = 68,
+ [0][1][2][0][RTW89_ETSI][1][68] = 127,
+ [0][1][2][0][RTW89_ETSI][0][68] = 127,
+ [0][1][2][0][RTW89_MKK][1][68] = 127,
+ [0][1][2][0][RTW89_MKK][0][68] = 127,
+ [0][1][2][0][RTW89_IC][1][68] = -2,
+ [0][1][2][0][RTW89_KCC][1][68] = 12,
+ [0][1][2][0][RTW89_KCC][0][68] = 127,
+ [0][1][2][0][RTW89_ACMA][1][68] = 127,
+ [0][1][2][0][RTW89_ACMA][0][68] = 127,
+ [0][1][2][0][RTW89_CHILE][1][68] = -2,
+ [0][1][2][0][RTW89_QATAR][1][68] = 127,
+ [0][1][2][0][RTW89_QATAR][0][68] = 127,
+ [0][1][2][0][RTW89_UK][1][68] = 127,
+ [0][1][2][0][RTW89_UK][0][68] = 127,
+ [0][1][2][0][RTW89_FCC][1][70] = -2,
+ [0][1][2][0][RTW89_FCC][2][70] = 68,
+ [0][1][2][0][RTW89_ETSI][1][70] = 127,
+ [0][1][2][0][RTW89_ETSI][0][70] = 127,
+ [0][1][2][0][RTW89_MKK][1][70] = 127,
+ [0][1][2][0][RTW89_MKK][0][70] = 127,
+ [0][1][2][0][RTW89_IC][1][70] = -2,
+ [0][1][2][0][RTW89_KCC][1][70] = 12,
+ [0][1][2][0][RTW89_KCC][0][70] = 127,
+ [0][1][2][0][RTW89_ACMA][1][70] = 127,
+ [0][1][2][0][RTW89_ACMA][0][70] = 127,
+ [0][1][2][0][RTW89_CHILE][1][70] = -2,
+ [0][1][2][0][RTW89_QATAR][1][70] = 127,
+ [0][1][2][0][RTW89_QATAR][0][70] = 127,
+ [0][1][2][0][RTW89_UK][1][70] = 127,
+ [0][1][2][0][RTW89_UK][0][70] = 127,
+ [0][1][2][0][RTW89_FCC][1][72] = -2,
+ [0][1][2][0][RTW89_FCC][2][72] = 68,
+ [0][1][2][0][RTW89_ETSI][1][72] = 127,
+ [0][1][2][0][RTW89_ETSI][0][72] = 127,
+ [0][1][2][0][RTW89_MKK][1][72] = 127,
+ [0][1][2][0][RTW89_MKK][0][72] = 127,
+ [0][1][2][0][RTW89_IC][1][72] = -2,
+ [0][1][2][0][RTW89_KCC][1][72] = 12,
+ [0][1][2][0][RTW89_KCC][0][72] = 127,
+ [0][1][2][0][RTW89_ACMA][1][72] = 127,
+ [0][1][2][0][RTW89_ACMA][0][72] = 127,
+ [0][1][2][0][RTW89_CHILE][1][72] = -2,
+ [0][1][2][0][RTW89_QATAR][1][72] = 127,
+ [0][1][2][0][RTW89_QATAR][0][72] = 127,
+ [0][1][2][0][RTW89_UK][1][72] = 127,
+ [0][1][2][0][RTW89_UK][0][72] = 127,
+ [0][1][2][0][RTW89_FCC][1][74] = -2,
+ [0][1][2][0][RTW89_FCC][2][74] = 68,
+ [0][1][2][0][RTW89_ETSI][1][74] = 127,
+ [0][1][2][0][RTW89_ETSI][0][74] = 127,
+ [0][1][2][0][RTW89_MKK][1][74] = 127,
+ [0][1][2][0][RTW89_MKK][0][74] = 127,
+ [0][1][2][0][RTW89_IC][1][74] = -2,
+ [0][1][2][0][RTW89_KCC][1][74] = 12,
+ [0][1][2][0][RTW89_KCC][0][74] = 127,
+ [0][1][2][0][RTW89_ACMA][1][74] = 127,
+ [0][1][2][0][RTW89_ACMA][0][74] = 127,
+ [0][1][2][0][RTW89_CHILE][1][74] = -2,
+ [0][1][2][0][RTW89_QATAR][1][74] = 127,
+ [0][1][2][0][RTW89_QATAR][0][74] = 127,
+ [0][1][2][0][RTW89_UK][1][74] = 127,
+ [0][1][2][0][RTW89_UK][0][74] = 127,
+ [0][1][2][0][RTW89_FCC][1][75] = -2,
+ [0][1][2][0][RTW89_FCC][2][75] = 68,
+ [0][1][2][0][RTW89_ETSI][1][75] = 127,
+ [0][1][2][0][RTW89_ETSI][0][75] = 127,
+ [0][1][2][0][RTW89_MKK][1][75] = 127,
+ [0][1][2][0][RTW89_MKK][0][75] = 127,
+ [0][1][2][0][RTW89_IC][1][75] = -2,
+ [0][1][2][0][RTW89_KCC][1][75] = 12,
+ [0][1][2][0][RTW89_KCC][0][75] = 127,
+ [0][1][2][0][RTW89_ACMA][1][75] = 127,
+ [0][1][2][0][RTW89_ACMA][0][75] = 127,
+ [0][1][2][0][RTW89_CHILE][1][75] = -2,
+ [0][1][2][0][RTW89_QATAR][1][75] = 127,
+ [0][1][2][0][RTW89_QATAR][0][75] = 127,
+ [0][1][2][0][RTW89_UK][1][75] = 127,
+ [0][1][2][0][RTW89_UK][0][75] = 127,
+ [0][1][2][0][RTW89_FCC][1][77] = -2,
+ [0][1][2][0][RTW89_FCC][2][77] = 68,
+ [0][1][2][0][RTW89_ETSI][1][77] = 127,
+ [0][1][2][0][RTW89_ETSI][0][77] = 127,
+ [0][1][2][0][RTW89_MKK][1][77] = 127,
+ [0][1][2][0][RTW89_MKK][0][77] = 127,
+ [0][1][2][0][RTW89_IC][1][77] = -2,
+ [0][1][2][0][RTW89_KCC][1][77] = 12,
+ [0][1][2][0][RTW89_KCC][0][77] = 127,
+ [0][1][2][0][RTW89_ACMA][1][77] = 127,
+ [0][1][2][0][RTW89_ACMA][0][77] = 127,
+ [0][1][2][0][RTW89_CHILE][1][77] = -2,
+ [0][1][2][0][RTW89_QATAR][1][77] = 127,
+ [0][1][2][0][RTW89_QATAR][0][77] = 127,
+ [0][1][2][0][RTW89_UK][1][77] = 127,
+ [0][1][2][0][RTW89_UK][0][77] = 127,
+ [0][1][2][0][RTW89_FCC][1][79] = -2,
+ [0][1][2][0][RTW89_FCC][2][79] = 68,
+ [0][1][2][0][RTW89_ETSI][1][79] = 127,
+ [0][1][2][0][RTW89_ETSI][0][79] = 127,
+ [0][1][2][0][RTW89_MKK][1][79] = 127,
+ [0][1][2][0][RTW89_MKK][0][79] = 127,
+ [0][1][2][0][RTW89_IC][1][79] = -2,
+ [0][1][2][0][RTW89_KCC][1][79] = 12,
+ [0][1][2][0][RTW89_KCC][0][79] = 127,
+ [0][1][2][0][RTW89_ACMA][1][79] = 127,
+ [0][1][2][0][RTW89_ACMA][0][79] = 127,
+ [0][1][2][0][RTW89_CHILE][1][79] = -2,
+ [0][1][2][0][RTW89_QATAR][1][79] = 127,
+ [0][1][2][0][RTW89_QATAR][0][79] = 127,
+ [0][1][2][0][RTW89_UK][1][79] = 127,
+ [0][1][2][0][RTW89_UK][0][79] = 127,
+ [0][1][2][0][RTW89_FCC][1][81] = -2,
+ [0][1][2][0][RTW89_FCC][2][81] = 68,
+ [0][1][2][0][RTW89_ETSI][1][81] = 127,
+ [0][1][2][0][RTW89_ETSI][0][81] = 127,
+ [0][1][2][0][RTW89_MKK][1][81] = 127,
+ [0][1][2][0][RTW89_MKK][0][81] = 127,
+ [0][1][2][0][RTW89_IC][1][81] = -2,
+ [0][1][2][0][RTW89_KCC][1][81] = 12,
+ [0][1][2][0][RTW89_KCC][0][81] = 127,
+ [0][1][2][0][RTW89_ACMA][1][81] = 127,
+ [0][1][2][0][RTW89_ACMA][0][81] = 127,
+ [0][1][2][0][RTW89_CHILE][1][81] = -2,
+ [0][1][2][0][RTW89_QATAR][1][81] = 127,
+ [0][1][2][0][RTW89_QATAR][0][81] = 127,
+ [0][1][2][0][RTW89_UK][1][81] = 127,
+ [0][1][2][0][RTW89_UK][0][81] = 127,
+ [0][1][2][0][RTW89_FCC][1][83] = -2,
+ [0][1][2][0][RTW89_FCC][2][83] = 68,
+ [0][1][2][0][RTW89_ETSI][1][83] = 127,
+ [0][1][2][0][RTW89_ETSI][0][83] = 127,
+ [0][1][2][0][RTW89_MKK][1][83] = 127,
+ [0][1][2][0][RTW89_MKK][0][83] = 127,
+ [0][1][2][0][RTW89_IC][1][83] = -2,
+ [0][1][2][0][RTW89_KCC][1][83] = 20,
+ [0][1][2][0][RTW89_KCC][0][83] = 127,
+ [0][1][2][0][RTW89_ACMA][1][83] = 127,
+ [0][1][2][0][RTW89_ACMA][0][83] = 127,
+ [0][1][2][0][RTW89_CHILE][1][83] = -2,
+ [0][1][2][0][RTW89_QATAR][1][83] = 127,
+ [0][1][2][0][RTW89_QATAR][0][83] = 127,
+ [0][1][2][0][RTW89_UK][1][83] = 127,
+ [0][1][2][0][RTW89_UK][0][83] = 127,
+ [0][1][2][0][RTW89_FCC][1][85] = -2,
+ [0][1][2][0][RTW89_FCC][2][85] = 68,
+ [0][1][2][0][RTW89_ETSI][1][85] = 127,
+ [0][1][2][0][RTW89_ETSI][0][85] = 127,
+ [0][1][2][0][RTW89_MKK][1][85] = 127,
+ [0][1][2][0][RTW89_MKK][0][85] = 127,
+ [0][1][2][0][RTW89_IC][1][85] = -2,
+ [0][1][2][0][RTW89_KCC][1][85] = 20,
+ [0][1][2][0][RTW89_KCC][0][85] = 127,
+ [0][1][2][0][RTW89_ACMA][1][85] = 127,
+ [0][1][2][0][RTW89_ACMA][0][85] = 127,
+ [0][1][2][0][RTW89_CHILE][1][85] = -2,
+ [0][1][2][0][RTW89_QATAR][1][85] = 127,
+ [0][1][2][0][RTW89_QATAR][0][85] = 127,
+ [0][1][2][0][RTW89_UK][1][85] = 127,
+ [0][1][2][0][RTW89_UK][0][85] = 127,
+ [0][1][2][0][RTW89_FCC][1][87] = -2,
+ [0][1][2][0][RTW89_FCC][2][87] = 127,
+ [0][1][2][0][RTW89_ETSI][1][87] = 127,
+ [0][1][2][0][RTW89_ETSI][0][87] = 127,
+ [0][1][2][0][RTW89_MKK][1][87] = 127,
+ [0][1][2][0][RTW89_MKK][0][87] = 127,
+ [0][1][2][0][RTW89_IC][1][87] = -2,
+ [0][1][2][0][RTW89_KCC][1][87] = 20,
+ [0][1][2][0][RTW89_KCC][0][87] = 127,
+ [0][1][2][0][RTW89_ACMA][1][87] = 127,
+ [0][1][2][0][RTW89_ACMA][0][87] = 127,
+ [0][1][2][0][RTW89_CHILE][1][87] = -2,
+ [0][1][2][0][RTW89_QATAR][1][87] = 127,
+ [0][1][2][0][RTW89_QATAR][0][87] = 127,
+ [0][1][2][0][RTW89_UK][1][87] = 127,
+ [0][1][2][0][RTW89_UK][0][87] = 127,
+ [0][1][2][0][RTW89_FCC][1][89] = -2,
+ [0][1][2][0][RTW89_FCC][2][89] = 127,
+ [0][1][2][0][RTW89_ETSI][1][89] = 127,
+ [0][1][2][0][RTW89_ETSI][0][89] = 127,
+ [0][1][2][0][RTW89_MKK][1][89] = 127,
+ [0][1][2][0][RTW89_MKK][0][89] = 127,
+ [0][1][2][0][RTW89_IC][1][89] = -2,
+ [0][1][2][0][RTW89_KCC][1][89] = 20,
+ [0][1][2][0][RTW89_KCC][0][89] = 127,
+ [0][1][2][0][RTW89_ACMA][1][89] = 127,
+ [0][1][2][0][RTW89_ACMA][0][89] = 127,
+ [0][1][2][0][RTW89_CHILE][1][89] = -2,
+ [0][1][2][0][RTW89_QATAR][1][89] = 127,
+ [0][1][2][0][RTW89_QATAR][0][89] = 127,
+ [0][1][2][0][RTW89_UK][1][89] = 127,
+ [0][1][2][0][RTW89_UK][0][89] = 127,
+ [0][1][2][0][RTW89_FCC][1][90] = -2,
+ [0][1][2][0][RTW89_FCC][2][90] = 127,
+ [0][1][2][0][RTW89_ETSI][1][90] = 127,
+ [0][1][2][0][RTW89_ETSI][0][90] = 127,
+ [0][1][2][0][RTW89_MKK][1][90] = 127,
+ [0][1][2][0][RTW89_MKK][0][90] = 127,
+ [0][1][2][0][RTW89_IC][1][90] = -2,
+ [0][1][2][0][RTW89_KCC][1][90] = 20,
+ [0][1][2][0][RTW89_KCC][0][90] = 127,
+ [0][1][2][0][RTW89_ACMA][1][90] = 127,
+ [0][1][2][0][RTW89_ACMA][0][90] = 127,
+ [0][1][2][0][RTW89_CHILE][1][90] = -2,
+ [0][1][2][0][RTW89_QATAR][1][90] = 127,
+ [0][1][2][0][RTW89_QATAR][0][90] = 127,
+ [0][1][2][0][RTW89_UK][1][90] = 127,
+ [0][1][2][0][RTW89_UK][0][90] = 127,
+ [0][1][2][0][RTW89_FCC][1][92] = -2,
+ [0][1][2][0][RTW89_FCC][2][92] = 127,
+ [0][1][2][0][RTW89_ETSI][1][92] = 127,
+ [0][1][2][0][RTW89_ETSI][0][92] = 127,
+ [0][1][2][0][RTW89_MKK][1][92] = 127,
+ [0][1][2][0][RTW89_MKK][0][92] = 127,
+ [0][1][2][0][RTW89_IC][1][92] = -2,
+ [0][1][2][0][RTW89_KCC][1][92] = 20,
+ [0][1][2][0][RTW89_KCC][0][92] = 127,
+ [0][1][2][0][RTW89_ACMA][1][92] = 127,
+ [0][1][2][0][RTW89_ACMA][0][92] = 127,
+ [0][1][2][0][RTW89_CHILE][1][92] = -2,
+ [0][1][2][0][RTW89_QATAR][1][92] = 127,
+ [0][1][2][0][RTW89_QATAR][0][92] = 127,
+ [0][1][2][0][RTW89_UK][1][92] = 127,
+ [0][1][2][0][RTW89_UK][0][92] = 127,
+ [0][1][2][0][RTW89_FCC][1][94] = -2,
+ [0][1][2][0][RTW89_FCC][2][94] = 127,
+ [0][1][2][0][RTW89_ETSI][1][94] = 127,
+ [0][1][2][0][RTW89_ETSI][0][94] = 127,
+ [0][1][2][0][RTW89_MKK][1][94] = 127,
+ [0][1][2][0][RTW89_MKK][0][94] = 127,
+ [0][1][2][0][RTW89_IC][1][94] = -2,
+ [0][1][2][0][RTW89_KCC][1][94] = 20,
+ [0][1][2][0][RTW89_KCC][0][94] = 127,
+ [0][1][2][0][RTW89_ACMA][1][94] = 127,
+ [0][1][2][0][RTW89_ACMA][0][94] = 127,
+ [0][1][2][0][RTW89_CHILE][1][94] = -2,
+ [0][1][2][0][RTW89_QATAR][1][94] = 127,
+ [0][1][2][0][RTW89_QATAR][0][94] = 127,
+ [0][1][2][0][RTW89_UK][1][94] = 127,
+ [0][1][2][0][RTW89_UK][0][94] = 127,
+ [0][1][2][0][RTW89_FCC][1][96] = -2,
+ [0][1][2][0][RTW89_FCC][2][96] = 127,
+ [0][1][2][0][RTW89_ETSI][1][96] = 127,
+ [0][1][2][0][RTW89_ETSI][0][96] = 127,
+ [0][1][2][0][RTW89_MKK][1][96] = 127,
+ [0][1][2][0][RTW89_MKK][0][96] = 127,
+ [0][1][2][0][RTW89_IC][1][96] = -2,
+ [0][1][2][0][RTW89_KCC][1][96] = 20,
+ [0][1][2][0][RTW89_KCC][0][96] = 127,
+ [0][1][2][0][RTW89_ACMA][1][96] = 127,
+ [0][1][2][0][RTW89_ACMA][0][96] = 127,
+ [0][1][2][0][RTW89_CHILE][1][96] = -2,
+ [0][1][2][0][RTW89_QATAR][1][96] = 127,
+ [0][1][2][0][RTW89_QATAR][0][96] = 127,
+ [0][1][2][0][RTW89_UK][1][96] = 127,
+ [0][1][2][0][RTW89_UK][0][96] = 127,
+ [0][1][2][0][RTW89_FCC][1][98] = -2,
+ [0][1][2][0][RTW89_FCC][2][98] = 127,
+ [0][1][2][0][RTW89_ETSI][1][98] = 127,
+ [0][1][2][0][RTW89_ETSI][0][98] = 127,
+ [0][1][2][0][RTW89_MKK][1][98] = 127,
+ [0][1][2][0][RTW89_MKK][0][98] = 127,
+ [0][1][2][0][RTW89_IC][1][98] = -2,
+ [0][1][2][0][RTW89_KCC][1][98] = 20,
+ [0][1][2][0][RTW89_KCC][0][98] = 127,
+ [0][1][2][0][RTW89_ACMA][1][98] = 127,
+ [0][1][2][0][RTW89_ACMA][0][98] = 127,
+ [0][1][2][0][RTW89_CHILE][1][98] = -2,
+ [0][1][2][0][RTW89_QATAR][1][98] = 127,
+ [0][1][2][0][RTW89_QATAR][0][98] = 127,
+ [0][1][2][0][RTW89_UK][1][98] = 127,
+ [0][1][2][0][RTW89_UK][0][98] = 127,
+ [0][1][2][0][RTW89_FCC][1][100] = -2,
+ [0][1][2][0][RTW89_FCC][2][100] = 127,
+ [0][1][2][0][RTW89_ETSI][1][100] = 127,
+ [0][1][2][0][RTW89_ETSI][0][100] = 127,
+ [0][1][2][0][RTW89_MKK][1][100] = 127,
+ [0][1][2][0][RTW89_MKK][0][100] = 127,
+ [0][1][2][0][RTW89_IC][1][100] = -2,
+ [0][1][2][0][RTW89_KCC][1][100] = 20,
+ [0][1][2][0][RTW89_KCC][0][100] = 127,
+ [0][1][2][0][RTW89_ACMA][1][100] = 127,
+ [0][1][2][0][RTW89_ACMA][0][100] = 127,
+ [0][1][2][0][RTW89_CHILE][1][100] = -2,
+ [0][1][2][0][RTW89_QATAR][1][100] = 127,
+ [0][1][2][0][RTW89_QATAR][0][100] = 127,
+ [0][1][2][0][RTW89_UK][1][100] = 127,
+ [0][1][2][0][RTW89_UK][0][100] = 127,
+ [0][1][2][0][RTW89_FCC][1][102] = -2,
+ [0][1][2][0][RTW89_FCC][2][102] = 127,
+ [0][1][2][0][RTW89_ETSI][1][102] = 127,
+ [0][1][2][0][RTW89_ETSI][0][102] = 127,
+ [0][1][2][0][RTW89_MKK][1][102] = 127,
+ [0][1][2][0][RTW89_MKK][0][102] = 127,
+ [0][1][2][0][RTW89_IC][1][102] = -2,
+ [0][1][2][0][RTW89_KCC][1][102] = 20,
+ [0][1][2][0][RTW89_KCC][0][102] = 127,
+ [0][1][2][0][RTW89_ACMA][1][102] = 127,
+ [0][1][2][0][RTW89_ACMA][0][102] = 127,
+ [0][1][2][0][RTW89_CHILE][1][102] = -2,
+ [0][1][2][0][RTW89_QATAR][1][102] = 127,
+ [0][1][2][0][RTW89_QATAR][0][102] = 127,
+ [0][1][2][0][RTW89_UK][1][102] = 127,
+ [0][1][2][0][RTW89_UK][0][102] = 127,
+ [0][1][2][0][RTW89_FCC][1][104] = -2,
+ [0][1][2][0][RTW89_FCC][2][104] = 127,
+ [0][1][2][0][RTW89_ETSI][1][104] = 127,
+ [0][1][2][0][RTW89_ETSI][0][104] = 127,
+ [0][1][2][0][RTW89_MKK][1][104] = 127,
+ [0][1][2][0][RTW89_MKK][0][104] = 127,
+ [0][1][2][0][RTW89_IC][1][104] = -2,
+ [0][1][2][0][RTW89_KCC][1][104] = 20,
+ [0][1][2][0][RTW89_KCC][0][104] = 127,
+ [0][1][2][0][RTW89_ACMA][1][104] = 127,
+ [0][1][2][0][RTW89_ACMA][0][104] = 127,
+ [0][1][2][0][RTW89_CHILE][1][104] = -2,
+ [0][1][2][0][RTW89_QATAR][1][104] = 127,
+ [0][1][2][0][RTW89_QATAR][0][104] = 127,
+ [0][1][2][0][RTW89_UK][1][104] = 127,
+ [0][1][2][0][RTW89_UK][0][104] = 127,
+ [0][1][2][0][RTW89_FCC][1][105] = -2,
+ [0][1][2][0][RTW89_FCC][2][105] = 127,
+ [0][1][2][0][RTW89_ETSI][1][105] = 127,
+ [0][1][2][0][RTW89_ETSI][0][105] = 127,
+ [0][1][2][0][RTW89_MKK][1][105] = 127,
+ [0][1][2][0][RTW89_MKK][0][105] = 127,
+ [0][1][2][0][RTW89_IC][1][105] = -2,
+ [0][1][2][0][RTW89_KCC][1][105] = 20,
+ [0][1][2][0][RTW89_KCC][0][105] = 127,
+ [0][1][2][0][RTW89_ACMA][1][105] = 127,
+ [0][1][2][0][RTW89_ACMA][0][105] = 127,
+ [0][1][2][0][RTW89_CHILE][1][105] = -2,
+ [0][1][2][0][RTW89_QATAR][1][105] = 127,
+ [0][1][2][0][RTW89_QATAR][0][105] = 127,
+ [0][1][2][0][RTW89_UK][1][105] = 127,
+ [0][1][2][0][RTW89_UK][0][105] = 127,
+ [0][1][2][0][RTW89_FCC][1][107] = 1,
+ [0][1][2][0][RTW89_FCC][2][107] = 127,
+ [0][1][2][0][RTW89_ETSI][1][107] = 127,
+ [0][1][2][0][RTW89_ETSI][0][107] = 127,
+ [0][1][2][0][RTW89_MKK][1][107] = 127,
+ [0][1][2][0][RTW89_MKK][0][107] = 127,
+ [0][1][2][0][RTW89_IC][1][107] = 1,
+ [0][1][2][0][RTW89_KCC][1][107] = 20,
+ [0][1][2][0][RTW89_KCC][0][107] = 127,
+ [0][1][2][0][RTW89_ACMA][1][107] = 127,
+ [0][1][2][0][RTW89_ACMA][0][107] = 127,
+ [0][1][2][0][RTW89_CHILE][1][107] = 1,
+ [0][1][2][0][RTW89_QATAR][1][107] = 127,
+ [0][1][2][0][RTW89_QATAR][0][107] = 127,
+ [0][1][2][0][RTW89_UK][1][107] = 127,
+ [0][1][2][0][RTW89_UK][0][107] = 127,
+ [0][1][2][0][RTW89_FCC][1][109] = 1,
+ [0][1][2][0][RTW89_FCC][2][109] = 127,
+ [0][1][2][0][RTW89_ETSI][1][109] = 127,
+ [0][1][2][0][RTW89_ETSI][0][109] = 127,
+ [0][1][2][0][RTW89_MKK][1][109] = 127,
+ [0][1][2][0][RTW89_MKK][0][109] = 127,
+ [0][1][2][0][RTW89_IC][1][109] = 1,
+ [0][1][2][0][RTW89_KCC][1][109] = 20,
+ [0][1][2][0][RTW89_KCC][0][109] = 127,
+ [0][1][2][0][RTW89_ACMA][1][109] = 127,
+ [0][1][2][0][RTW89_ACMA][0][109] = 127,
+ [0][1][2][0][RTW89_CHILE][1][109] = 1,
+ [0][1][2][0][RTW89_QATAR][1][109] = 127,
+ [0][1][2][0][RTW89_QATAR][0][109] = 127,
+ [0][1][2][0][RTW89_UK][1][109] = 127,
+ [0][1][2][0][RTW89_UK][0][109] = 127,
+ [0][1][2][0][RTW89_FCC][1][111] = 127,
+ [0][1][2][0][RTW89_FCC][2][111] = 127,
+ [0][1][2][0][RTW89_ETSI][1][111] = 127,
+ [0][1][2][0][RTW89_ETSI][0][111] = 127,
+ [0][1][2][0][RTW89_MKK][1][111] = 127,
+ [0][1][2][0][RTW89_MKK][0][111] = 127,
+ [0][1][2][0][RTW89_IC][1][111] = 127,
+ [0][1][2][0][RTW89_KCC][1][111] = 127,
+ [0][1][2][0][RTW89_KCC][0][111] = 127,
+ [0][1][2][0][RTW89_ACMA][1][111] = 127,
+ [0][1][2][0][RTW89_ACMA][0][111] = 127,
+ [0][1][2][0][RTW89_CHILE][1][111] = 127,
+ [0][1][2][0][RTW89_QATAR][1][111] = 127,
+ [0][1][2][0][RTW89_QATAR][0][111] = 127,
+ [0][1][2][0][RTW89_UK][1][111] = 127,
+ [0][1][2][0][RTW89_UK][0][111] = 127,
+ [0][1][2][0][RTW89_FCC][1][113] = 127,
+ [0][1][2][0][RTW89_FCC][2][113] = 127,
+ [0][1][2][0][RTW89_ETSI][1][113] = 127,
+ [0][1][2][0][RTW89_ETSI][0][113] = 127,
+ [0][1][2][0][RTW89_MKK][1][113] = 127,
+ [0][1][2][0][RTW89_MKK][0][113] = 127,
+ [0][1][2][0][RTW89_IC][1][113] = 127,
+ [0][1][2][0][RTW89_KCC][1][113] = 127,
+ [0][1][2][0][RTW89_KCC][0][113] = 127,
+ [0][1][2][0][RTW89_ACMA][1][113] = 127,
+ [0][1][2][0][RTW89_ACMA][0][113] = 127,
+ [0][1][2][0][RTW89_CHILE][1][113] = 127,
+ [0][1][2][0][RTW89_QATAR][1][113] = 127,
+ [0][1][2][0][RTW89_QATAR][0][113] = 127,
+ [0][1][2][0][RTW89_UK][1][113] = 127,
+ [0][1][2][0][RTW89_UK][0][113] = 127,
+ [0][1][2][0][RTW89_FCC][1][115] = 127,
+ [0][1][2][0][RTW89_FCC][2][115] = 127,
+ [0][1][2][0][RTW89_ETSI][1][115] = 127,
+ [0][1][2][0][RTW89_ETSI][0][115] = 127,
+ [0][1][2][0][RTW89_MKK][1][115] = 127,
+ [0][1][2][0][RTW89_MKK][0][115] = 127,
+ [0][1][2][0][RTW89_IC][1][115] = 127,
+ [0][1][2][0][RTW89_KCC][1][115] = 127,
+ [0][1][2][0][RTW89_KCC][0][115] = 127,
+ [0][1][2][0][RTW89_ACMA][1][115] = 127,
+ [0][1][2][0][RTW89_ACMA][0][115] = 127,
+ [0][1][2][0][RTW89_CHILE][1][115] = 127,
+ [0][1][2][0][RTW89_QATAR][1][115] = 127,
+ [0][1][2][0][RTW89_QATAR][0][115] = 127,
+ [0][1][2][0][RTW89_UK][1][115] = 127,
+ [0][1][2][0][RTW89_UK][0][115] = 127,
+ [0][1][2][0][RTW89_FCC][1][117] = 127,
+ [0][1][2][0][RTW89_FCC][2][117] = 127,
+ [0][1][2][0][RTW89_ETSI][1][117] = 127,
+ [0][1][2][0][RTW89_ETSI][0][117] = 127,
+ [0][1][2][0][RTW89_MKK][1][117] = 127,
+ [0][1][2][0][RTW89_MKK][0][117] = 127,
+ [0][1][2][0][RTW89_IC][1][117] = 127,
+ [0][1][2][0][RTW89_KCC][1][117] = 127,
+ [0][1][2][0][RTW89_KCC][0][117] = 127,
+ [0][1][2][0][RTW89_ACMA][1][117] = 127,
+ [0][1][2][0][RTW89_ACMA][0][117] = 127,
+ [0][1][2][0][RTW89_CHILE][1][117] = 127,
+ [0][1][2][0][RTW89_QATAR][1][117] = 127,
+ [0][1][2][0][RTW89_QATAR][0][117] = 127,
+ [0][1][2][0][RTW89_UK][1][117] = 127,
+ [0][1][2][0][RTW89_UK][0][117] = 127,
+ [0][1][2][0][RTW89_FCC][1][119] = 127,
+ [0][1][2][0][RTW89_FCC][2][119] = 127,
+ [0][1][2][0][RTW89_ETSI][1][119] = 127,
+ [0][1][2][0][RTW89_ETSI][0][119] = 127,
+ [0][1][2][0][RTW89_MKK][1][119] = 127,
+ [0][1][2][0][RTW89_MKK][0][119] = 127,
+ [0][1][2][0][RTW89_IC][1][119] = 127,
+ [0][1][2][0][RTW89_KCC][1][119] = 127,
+ [0][1][2][0][RTW89_KCC][0][119] = 127,
+ [0][1][2][0][RTW89_ACMA][1][119] = 127,
+ [0][1][2][0][RTW89_ACMA][0][119] = 127,
+ [0][1][2][0][RTW89_CHILE][1][119] = 127,
+ [0][1][2][0][RTW89_QATAR][1][119] = 127,
+ [0][1][2][0][RTW89_QATAR][0][119] = 127,
+ [0][1][2][0][RTW89_UK][1][119] = 127,
+ [0][1][2][0][RTW89_UK][0][119] = 127,
+ [0][1][2][1][RTW89_FCC][1][0] = -2,
+ [0][1][2][1][RTW89_FCC][2][0] = 54,
+ [0][1][2][1][RTW89_ETSI][1][0] = 42,
+ [0][1][2][1][RTW89_ETSI][0][0] = 6,
+ [0][1][2][1][RTW89_MKK][1][0] = 56,
+ [0][1][2][1][RTW89_MKK][0][0] = 16,
+ [0][1][2][1][RTW89_IC][1][0] = -2,
+ [0][1][2][1][RTW89_KCC][1][0] = 12,
+ [0][1][2][1][RTW89_KCC][0][0] = 10,
+ [0][1][2][1][RTW89_ACMA][1][0] = 42,
+ [0][1][2][1][RTW89_ACMA][0][0] = 6,
+ [0][1][2][1][RTW89_CHILE][1][0] = -2,
+ [0][1][2][1][RTW89_QATAR][1][0] = 42,
+ [0][1][2][1][RTW89_QATAR][0][0] = 6,
+ [0][1][2][1][RTW89_UK][1][0] = 42,
+ [0][1][2][1][RTW89_UK][0][0] = 6,
+ [0][1][2][1][RTW89_FCC][1][2] = -4,
+ [0][1][2][1][RTW89_FCC][2][2] = 54,
+ [0][1][2][1][RTW89_ETSI][1][2] = 42,
+ [0][1][2][1][RTW89_ETSI][0][2] = 6,
+ [0][1][2][1][RTW89_MKK][1][2] = 54,
+ [0][1][2][1][RTW89_MKK][0][2] = 16,
+ [0][1][2][1][RTW89_IC][1][2] = -4,
+ [0][1][2][1][RTW89_KCC][1][2] = 12,
+ [0][1][2][1][RTW89_KCC][0][2] = 12,
+ [0][1][2][1][RTW89_ACMA][1][2] = 42,
+ [0][1][2][1][RTW89_ACMA][0][2] = 6,
+ [0][1][2][1][RTW89_CHILE][1][2] = -4,
+ [0][1][2][1][RTW89_QATAR][1][2] = 42,
+ [0][1][2][1][RTW89_QATAR][0][2] = 6,
+ [0][1][2][1][RTW89_UK][1][2] = 42,
+ [0][1][2][1][RTW89_UK][0][2] = 6,
+ [0][1][2][1][RTW89_FCC][1][4] = -4,
+ [0][1][2][1][RTW89_FCC][2][4] = 54,
+ [0][1][2][1][RTW89_ETSI][1][4] = 42,
+ [0][1][2][1][RTW89_ETSI][0][4] = 6,
+ [0][1][2][1][RTW89_MKK][1][4] = 54,
+ [0][1][2][1][RTW89_MKK][0][4] = 16,
+ [0][1][2][1][RTW89_IC][1][4] = -4,
+ [0][1][2][1][RTW89_KCC][1][4] = 12,
+ [0][1][2][1][RTW89_KCC][0][4] = 12,
+ [0][1][2][1][RTW89_ACMA][1][4] = 42,
+ [0][1][2][1][RTW89_ACMA][0][4] = 6,
+ [0][1][2][1][RTW89_CHILE][1][4] = -4,
+ [0][1][2][1][RTW89_QATAR][1][4] = 42,
+ [0][1][2][1][RTW89_QATAR][0][4] = 6,
+ [0][1][2][1][RTW89_UK][1][4] = 42,
+ [0][1][2][1][RTW89_UK][0][4] = 6,
+ [0][1][2][1][RTW89_FCC][1][6] = -4,
+ [0][1][2][1][RTW89_FCC][2][6] = 54,
+ [0][1][2][1][RTW89_ETSI][1][6] = 42,
+ [0][1][2][1][RTW89_ETSI][0][6] = 6,
+ [0][1][2][1][RTW89_MKK][1][6] = 54,
+ [0][1][2][1][RTW89_MKK][0][6] = 16,
+ [0][1][2][1][RTW89_IC][1][6] = -4,
+ [0][1][2][1][RTW89_KCC][1][6] = 12,
+ [0][1][2][1][RTW89_KCC][0][6] = 12,
+ [0][1][2][1][RTW89_ACMA][1][6] = 42,
+ [0][1][2][1][RTW89_ACMA][0][6] = 6,
+ [0][1][2][1][RTW89_CHILE][1][6] = -4,
+ [0][1][2][1][RTW89_QATAR][1][6] = 42,
+ [0][1][2][1][RTW89_QATAR][0][6] = 6,
+ [0][1][2][1][RTW89_UK][1][6] = 42,
+ [0][1][2][1][RTW89_UK][0][6] = 6,
+ [0][1][2][1][RTW89_FCC][1][8] = -4,
+ [0][1][2][1][RTW89_FCC][2][8] = 54,
+ [0][1][2][1][RTW89_ETSI][1][8] = 42,
+ [0][1][2][1][RTW89_ETSI][0][8] = 6,
+ [0][1][2][1][RTW89_MKK][1][8] = 54,
+ [0][1][2][1][RTW89_MKK][0][8] = 16,
+ [0][1][2][1][RTW89_IC][1][8] = -4,
+ [0][1][2][1][RTW89_KCC][1][8] = 12,
+ [0][1][2][1][RTW89_KCC][0][8] = 12,
+ [0][1][2][1][RTW89_ACMA][1][8] = 42,
+ [0][1][2][1][RTW89_ACMA][0][8] = 6,
+ [0][1][2][1][RTW89_CHILE][1][8] = -4,
+ [0][1][2][1][RTW89_QATAR][1][8] = 42,
+ [0][1][2][1][RTW89_QATAR][0][8] = 6,
+ [0][1][2][1][RTW89_UK][1][8] = 42,
+ [0][1][2][1][RTW89_UK][0][8] = 6,
+ [0][1][2][1][RTW89_FCC][1][10] = -4,
+ [0][1][2][1][RTW89_FCC][2][10] = 54,
+ [0][1][2][1][RTW89_ETSI][1][10] = 42,
+ [0][1][2][1][RTW89_ETSI][0][10] = 6,
+ [0][1][2][1][RTW89_MKK][1][10] = 54,
+ [0][1][2][1][RTW89_MKK][0][10] = 16,
+ [0][1][2][1][RTW89_IC][1][10] = -4,
+ [0][1][2][1][RTW89_KCC][1][10] = 12,
+ [0][1][2][1][RTW89_KCC][0][10] = 12,
+ [0][1][2][1][RTW89_ACMA][1][10] = 42,
+ [0][1][2][1][RTW89_ACMA][0][10] = 6,
+ [0][1][2][1][RTW89_CHILE][1][10] = -4,
+ [0][1][2][1][RTW89_QATAR][1][10] = 42,
+ [0][1][2][1][RTW89_QATAR][0][10] = 6,
+ [0][1][2][1][RTW89_UK][1][10] = 42,
+ [0][1][2][1][RTW89_UK][0][10] = 6,
+ [0][1][2][1][RTW89_FCC][1][12] = -4,
+ [0][1][2][1][RTW89_FCC][2][12] = 54,
+ [0][1][2][1][RTW89_ETSI][1][12] = 42,
+ [0][1][2][1][RTW89_ETSI][0][12] = 6,
+ [0][1][2][1][RTW89_MKK][1][12] = 54,
+ [0][1][2][1][RTW89_MKK][0][12] = 16,
+ [0][1][2][1][RTW89_IC][1][12] = -4,
+ [0][1][2][1][RTW89_KCC][1][12] = 12,
+ [0][1][2][1][RTW89_KCC][0][12] = 12,
+ [0][1][2][1][RTW89_ACMA][1][12] = 42,
+ [0][1][2][1][RTW89_ACMA][0][12] = 6,
+ [0][1][2][1][RTW89_CHILE][1][12] = -4,
+ [0][1][2][1][RTW89_QATAR][1][12] = 42,
+ [0][1][2][1][RTW89_QATAR][0][12] = 6,
+ [0][1][2][1][RTW89_UK][1][12] = 42,
+ [0][1][2][1][RTW89_UK][0][12] = 6,
+ [0][1][2][1][RTW89_FCC][1][14] = -4,
+ [0][1][2][1][RTW89_FCC][2][14] = 54,
+ [0][1][2][1][RTW89_ETSI][1][14] = 42,
+ [0][1][2][1][RTW89_ETSI][0][14] = 6,
+ [0][1][2][1][RTW89_MKK][1][14] = 54,
+ [0][1][2][1][RTW89_MKK][0][14] = 16,
+ [0][1][2][1][RTW89_IC][1][14] = -4,
+ [0][1][2][1][RTW89_KCC][1][14] = 12,
+ [0][1][2][1][RTW89_KCC][0][14] = 12,
+ [0][1][2][1][RTW89_ACMA][1][14] = 42,
+ [0][1][2][1][RTW89_ACMA][0][14] = 6,
+ [0][1][2][1][RTW89_CHILE][1][14] = -4,
+ [0][1][2][1][RTW89_QATAR][1][14] = 42,
+ [0][1][2][1][RTW89_QATAR][0][14] = 6,
+ [0][1][2][1][RTW89_UK][1][14] = 42,
+ [0][1][2][1][RTW89_UK][0][14] = 6,
+ [0][1][2][1][RTW89_FCC][1][15] = -4,
+ [0][1][2][1][RTW89_FCC][2][15] = 54,
+ [0][1][2][1][RTW89_ETSI][1][15] = 42,
+ [0][1][2][1][RTW89_ETSI][0][15] = 6,
+ [0][1][2][1][RTW89_MKK][1][15] = 54,
+ [0][1][2][1][RTW89_MKK][0][15] = 16,
+ [0][1][2][1][RTW89_IC][1][15] = -4,
+ [0][1][2][1][RTW89_KCC][1][15] = 12,
+ [0][1][2][1][RTW89_KCC][0][15] = 12,
+ [0][1][2][1][RTW89_ACMA][1][15] = 42,
+ [0][1][2][1][RTW89_ACMA][0][15] = 6,
+ [0][1][2][1][RTW89_CHILE][1][15] = -4,
+ [0][1][2][1][RTW89_QATAR][1][15] = 42,
+ [0][1][2][1][RTW89_QATAR][0][15] = 6,
+ [0][1][2][1][RTW89_UK][1][15] = 42,
+ [0][1][2][1][RTW89_UK][0][15] = 6,
+ [0][1][2][1][RTW89_FCC][1][17] = -4,
+ [0][1][2][1][RTW89_FCC][2][17] = 54,
+ [0][1][2][1][RTW89_ETSI][1][17] = 42,
+ [0][1][2][1][RTW89_ETSI][0][17] = 6,
+ [0][1][2][1][RTW89_MKK][1][17] = 54,
+ [0][1][2][1][RTW89_MKK][0][17] = 16,
+ [0][1][2][1][RTW89_IC][1][17] = -4,
+ [0][1][2][1][RTW89_KCC][1][17] = 12,
+ [0][1][2][1][RTW89_KCC][0][17] = 12,
+ [0][1][2][1][RTW89_ACMA][1][17] = 42,
+ [0][1][2][1][RTW89_ACMA][0][17] = 6,
+ [0][1][2][1][RTW89_CHILE][1][17] = -4,
+ [0][1][2][1][RTW89_QATAR][1][17] = 42,
+ [0][1][2][1][RTW89_QATAR][0][17] = 6,
+ [0][1][2][1][RTW89_UK][1][17] = 42,
+ [0][1][2][1][RTW89_UK][0][17] = 6,
+ [0][1][2][1][RTW89_FCC][1][19] = -4,
+ [0][1][2][1][RTW89_FCC][2][19] = 54,
+ [0][1][2][1][RTW89_ETSI][1][19] = 42,
+ [0][1][2][1][RTW89_ETSI][0][19] = 6,
+ [0][1][2][1][RTW89_MKK][1][19] = 54,
+ [0][1][2][1][RTW89_MKK][0][19] = 16,
+ [0][1][2][1][RTW89_IC][1][19] = -4,
+ [0][1][2][1][RTW89_KCC][1][19] = 12,
+ [0][1][2][1][RTW89_KCC][0][19] = 12,
+ [0][1][2][1][RTW89_ACMA][1][19] = 42,
+ [0][1][2][1][RTW89_ACMA][0][19] = 6,
+ [0][1][2][1][RTW89_CHILE][1][19] = -4,
+ [0][1][2][1][RTW89_QATAR][1][19] = 42,
+ [0][1][2][1][RTW89_QATAR][0][19] = 6,
+ [0][1][2][1][RTW89_UK][1][19] = 42,
+ [0][1][2][1][RTW89_UK][0][19] = 6,
+ [0][1][2][1][RTW89_FCC][1][21] = -4,
+ [0][1][2][1][RTW89_FCC][2][21] = 54,
+ [0][1][2][1][RTW89_ETSI][1][21] = 42,
+ [0][1][2][1][RTW89_ETSI][0][21] = 6,
+ [0][1][2][1][RTW89_MKK][1][21] = 54,
+ [0][1][2][1][RTW89_MKK][0][21] = 16,
+ [0][1][2][1][RTW89_IC][1][21] = -4,
+ [0][1][2][1][RTW89_KCC][1][21] = 12,
+ [0][1][2][1][RTW89_KCC][0][21] = 12,
+ [0][1][2][1][RTW89_ACMA][1][21] = 42,
+ [0][1][2][1][RTW89_ACMA][0][21] = 6,
+ [0][1][2][1][RTW89_CHILE][1][21] = -4,
+ [0][1][2][1][RTW89_QATAR][1][21] = 42,
+ [0][1][2][1][RTW89_QATAR][0][21] = 6,
+ [0][1][2][1][RTW89_UK][1][21] = 42,
+ [0][1][2][1][RTW89_UK][0][21] = 6,
+ [0][1][2][1][RTW89_FCC][1][23] = -4,
+ [0][1][2][1][RTW89_FCC][2][23] = 68,
+ [0][1][2][1][RTW89_ETSI][1][23] = 42,
+ [0][1][2][1][RTW89_ETSI][0][23] = 6,
+ [0][1][2][1][RTW89_MKK][1][23] = 54,
+ [0][1][2][1][RTW89_MKK][0][23] = 16,
+ [0][1][2][1][RTW89_IC][1][23] = -4,
+ [0][1][2][1][RTW89_KCC][1][23] = 12,
+ [0][1][2][1][RTW89_KCC][0][23] = 10,
+ [0][1][2][1][RTW89_ACMA][1][23] = 42,
+ [0][1][2][1][RTW89_ACMA][0][23] = 6,
+ [0][1][2][1][RTW89_CHILE][1][23] = -4,
+ [0][1][2][1][RTW89_QATAR][1][23] = 42,
+ [0][1][2][1][RTW89_QATAR][0][23] = 6,
+ [0][1][2][1][RTW89_UK][1][23] = 42,
+ [0][1][2][1][RTW89_UK][0][23] = 6,
+ [0][1][2][1][RTW89_FCC][1][25] = -4,
+ [0][1][2][1][RTW89_FCC][2][25] = 68,
+ [0][1][2][1][RTW89_ETSI][1][25] = 42,
+ [0][1][2][1][RTW89_ETSI][0][25] = 6,
+ [0][1][2][1][RTW89_MKK][1][25] = 54,
+ [0][1][2][1][RTW89_MKK][0][25] = 16,
+ [0][1][2][1][RTW89_IC][1][25] = -4,
+ [0][1][2][1][RTW89_KCC][1][25] = 12,
+ [0][1][2][1][RTW89_KCC][0][25] = 14,
+ [0][1][2][1][RTW89_ACMA][1][25] = 42,
+ [0][1][2][1][RTW89_ACMA][0][25] = 6,
+ [0][1][2][1][RTW89_CHILE][1][25] = -4,
+ [0][1][2][1][RTW89_QATAR][1][25] = 42,
+ [0][1][2][1][RTW89_QATAR][0][25] = 6,
+ [0][1][2][1][RTW89_UK][1][25] = 42,
+ [0][1][2][1][RTW89_UK][0][25] = 6,
+ [0][1][2][1][RTW89_FCC][1][27] = -4,
+ [0][1][2][1][RTW89_FCC][2][27] = 68,
+ [0][1][2][1][RTW89_ETSI][1][27] = 42,
+ [0][1][2][1][RTW89_ETSI][0][27] = 6,
+ [0][1][2][1][RTW89_MKK][1][27] = 54,
+ [0][1][2][1][RTW89_MKK][0][27] = 16,
+ [0][1][2][1][RTW89_IC][1][27] = -4,
+ [0][1][2][1][RTW89_KCC][1][27] = 12,
+ [0][1][2][1][RTW89_KCC][0][27] = 14,
+ [0][1][2][1][RTW89_ACMA][1][27] = 42,
+ [0][1][2][1][RTW89_ACMA][0][27] = 6,
+ [0][1][2][1][RTW89_CHILE][1][27] = -4,
+ [0][1][2][1][RTW89_QATAR][1][27] = 42,
+ [0][1][2][1][RTW89_QATAR][0][27] = 6,
+ [0][1][2][1][RTW89_UK][1][27] = 42,
+ [0][1][2][1][RTW89_UK][0][27] = 6,
+ [0][1][2][1][RTW89_FCC][1][29] = -4,
+ [0][1][2][1][RTW89_FCC][2][29] = 68,
+ [0][1][2][1][RTW89_ETSI][1][29] = 42,
+ [0][1][2][1][RTW89_ETSI][0][29] = 6,
+ [0][1][2][1][RTW89_MKK][1][29] = 54,
+ [0][1][2][1][RTW89_MKK][0][29] = 16,
+ [0][1][2][1][RTW89_IC][1][29] = -4,
+ [0][1][2][1][RTW89_KCC][1][29] = 12,
+ [0][1][2][1][RTW89_KCC][0][29] = 14,
+ [0][1][2][1][RTW89_ACMA][1][29] = 42,
+ [0][1][2][1][RTW89_ACMA][0][29] = 6,
+ [0][1][2][1][RTW89_CHILE][1][29] = -4,
+ [0][1][2][1][RTW89_QATAR][1][29] = 42,
+ [0][1][2][1][RTW89_QATAR][0][29] = 6,
+ [0][1][2][1][RTW89_UK][1][29] = 42,
+ [0][1][2][1][RTW89_UK][0][29] = 6,
+ [0][1][2][1][RTW89_FCC][1][30] = -4,
+ [0][1][2][1][RTW89_FCC][2][30] = 68,
+ [0][1][2][1][RTW89_ETSI][1][30] = 42,
+ [0][1][2][1][RTW89_ETSI][0][30] = 6,
+ [0][1][2][1][RTW89_MKK][1][30] = 54,
+ [0][1][2][1][RTW89_MKK][0][30] = 16,
+ [0][1][2][1][RTW89_IC][1][30] = -4,
+ [0][1][2][1][RTW89_KCC][1][30] = 12,
+ [0][1][2][1][RTW89_KCC][0][30] = 14,
+ [0][1][2][1][RTW89_ACMA][1][30] = 42,
+ [0][1][2][1][RTW89_ACMA][0][30] = 6,
+ [0][1][2][1][RTW89_CHILE][1][30] = -4,
+ [0][1][2][1][RTW89_QATAR][1][30] = 42,
+ [0][1][2][1][RTW89_QATAR][0][30] = 6,
+ [0][1][2][1][RTW89_UK][1][30] = 42,
+ [0][1][2][1][RTW89_UK][0][30] = 6,
+ [0][1][2][1][RTW89_FCC][1][32] = -4,
+ [0][1][2][1][RTW89_FCC][2][32] = 68,
+ [0][1][2][1][RTW89_ETSI][1][32] = 42,
+ [0][1][2][1][RTW89_ETSI][0][32] = 6,
+ [0][1][2][1][RTW89_MKK][1][32] = 54,
+ [0][1][2][1][RTW89_MKK][0][32] = 16,
+ [0][1][2][1][RTW89_IC][1][32] = -4,
+ [0][1][2][1][RTW89_KCC][1][32] = 12,
+ [0][1][2][1][RTW89_KCC][0][32] = 14,
+ [0][1][2][1][RTW89_ACMA][1][32] = 42,
+ [0][1][2][1][RTW89_ACMA][0][32] = 6,
+ [0][1][2][1][RTW89_CHILE][1][32] = -4,
+ [0][1][2][1][RTW89_QATAR][1][32] = 42,
+ [0][1][2][1][RTW89_QATAR][0][32] = 6,
+ [0][1][2][1][RTW89_UK][1][32] = 42,
+ [0][1][2][1][RTW89_UK][0][32] = 6,
+ [0][1][2][1][RTW89_FCC][1][34] = -4,
+ [0][1][2][1][RTW89_FCC][2][34] = 68,
+ [0][1][2][1][RTW89_ETSI][1][34] = 42,
+ [0][1][2][1][RTW89_ETSI][0][34] = 6,
+ [0][1][2][1][RTW89_MKK][1][34] = 54,
+ [0][1][2][1][RTW89_MKK][0][34] = 16,
+ [0][1][2][1][RTW89_IC][1][34] = -4,
+ [0][1][2][1][RTW89_KCC][1][34] = 12,
+ [0][1][2][1][RTW89_KCC][0][34] = 14,
+ [0][1][2][1][RTW89_ACMA][1][34] = 42,
+ [0][1][2][1][RTW89_ACMA][0][34] = 6,
+ [0][1][2][1][RTW89_CHILE][1][34] = -4,
+ [0][1][2][1][RTW89_QATAR][1][34] = 42,
+ [0][1][2][1][RTW89_QATAR][0][34] = 6,
+ [0][1][2][1][RTW89_UK][1][34] = 42,
+ [0][1][2][1][RTW89_UK][0][34] = 6,
+ [0][1][2][1][RTW89_FCC][1][36] = -4,
+ [0][1][2][1][RTW89_FCC][2][36] = 68,
+ [0][1][2][1][RTW89_ETSI][1][36] = 42,
+ [0][1][2][1][RTW89_ETSI][0][36] = 6,
+ [0][1][2][1][RTW89_MKK][1][36] = 54,
+ [0][1][2][1][RTW89_MKK][0][36] = 16,
+ [0][1][2][1][RTW89_IC][1][36] = -4,
+ [0][1][2][1][RTW89_KCC][1][36] = 12,
+ [0][1][2][1][RTW89_KCC][0][36] = 14,
+ [0][1][2][1][RTW89_ACMA][1][36] = 42,
+ [0][1][2][1][RTW89_ACMA][0][36] = 6,
+ [0][1][2][1][RTW89_CHILE][1][36] = -4,
+ [0][1][2][1][RTW89_QATAR][1][36] = 42,
+ [0][1][2][1][RTW89_QATAR][0][36] = 6,
+ [0][1][2][1][RTW89_UK][1][36] = 42,
+ [0][1][2][1][RTW89_UK][0][36] = 6,
+ [0][1][2][1][RTW89_FCC][1][38] = -4,
+ [0][1][2][1][RTW89_FCC][2][38] = 68,
+ [0][1][2][1][RTW89_ETSI][1][38] = 42,
+ [0][1][2][1][RTW89_ETSI][0][38] = 6,
+ [0][1][2][1][RTW89_MKK][1][38] = 54,
+ [0][1][2][1][RTW89_MKK][0][38] = 16,
+ [0][1][2][1][RTW89_IC][1][38] = -4,
+ [0][1][2][1][RTW89_KCC][1][38] = 12,
+ [0][1][2][1][RTW89_KCC][0][38] = 14,
+ [0][1][2][1][RTW89_ACMA][1][38] = 42,
+ [0][1][2][1][RTW89_ACMA][0][38] = 6,
+ [0][1][2][1][RTW89_CHILE][1][38] = -4,
+ [0][1][2][1][RTW89_QATAR][1][38] = 42,
+ [0][1][2][1][RTW89_QATAR][0][38] = 6,
+ [0][1][2][1][RTW89_UK][1][38] = 42,
+ [0][1][2][1][RTW89_UK][0][38] = 6,
+ [0][1][2][1][RTW89_FCC][1][40] = -4,
+ [0][1][2][1][RTW89_FCC][2][40] = 68,
+ [0][1][2][1][RTW89_ETSI][1][40] = 42,
+ [0][1][2][1][RTW89_ETSI][0][40] = 6,
+ [0][1][2][1][RTW89_MKK][1][40] = 54,
+ [0][1][2][1][RTW89_MKK][0][40] = 16,
+ [0][1][2][1][RTW89_IC][1][40] = -4,
+ [0][1][2][1][RTW89_KCC][1][40] = 12,
+ [0][1][2][1][RTW89_KCC][0][40] = 14,
+ [0][1][2][1][RTW89_ACMA][1][40] = 42,
+ [0][1][2][1][RTW89_ACMA][0][40] = 6,
+ [0][1][2][1][RTW89_CHILE][1][40] = -4,
+ [0][1][2][1][RTW89_QATAR][1][40] = 42,
+ [0][1][2][1][RTW89_QATAR][0][40] = 6,
+ [0][1][2][1][RTW89_UK][1][40] = 42,
+ [0][1][2][1][RTW89_UK][0][40] = 6,
+ [0][1][2][1][RTW89_FCC][1][42] = -4,
+ [0][1][2][1][RTW89_FCC][2][42] = 68,
+ [0][1][2][1][RTW89_ETSI][1][42] = 42,
+ [0][1][2][1][RTW89_ETSI][0][42] = 6,
+ [0][1][2][1][RTW89_MKK][1][42] = 54,
+ [0][1][2][1][RTW89_MKK][0][42] = 16,
+ [0][1][2][1][RTW89_IC][1][42] = -4,
+ [0][1][2][1][RTW89_KCC][1][42] = 12,
+ [0][1][2][1][RTW89_KCC][0][42] = 14,
+ [0][1][2][1][RTW89_ACMA][1][42] = 42,
+ [0][1][2][1][RTW89_ACMA][0][42] = 6,
+ [0][1][2][1][RTW89_CHILE][1][42] = -4,
+ [0][1][2][1][RTW89_QATAR][1][42] = 42,
+ [0][1][2][1][RTW89_QATAR][0][42] = 6,
+ [0][1][2][1][RTW89_UK][1][42] = 42,
+ [0][1][2][1][RTW89_UK][0][42] = 6,
+ [0][1][2][1][RTW89_FCC][1][44] = -2,
+ [0][1][2][1][RTW89_FCC][2][44] = 68,
+ [0][1][2][1][RTW89_ETSI][1][44] = 42,
+ [0][1][2][1][RTW89_ETSI][0][44] = 6,
+ [0][1][2][1][RTW89_MKK][1][44] = 34,
+ [0][1][2][1][RTW89_MKK][0][44] = 16,
+ [0][1][2][1][RTW89_IC][1][44] = -2,
+ [0][1][2][1][RTW89_KCC][1][44] = 12,
+ [0][1][2][1][RTW89_KCC][0][44] = 12,
+ [0][1][2][1][RTW89_ACMA][1][44] = 42,
+ [0][1][2][1][RTW89_ACMA][0][44] = 6,
+ [0][1][2][1][RTW89_CHILE][1][44] = -2,
+ [0][1][2][1][RTW89_QATAR][1][44] = 42,
+ [0][1][2][1][RTW89_QATAR][0][44] = 6,
+ [0][1][2][1][RTW89_UK][1][44] = 42,
+ [0][1][2][1][RTW89_UK][0][44] = 6,
+ [0][1][2][1][RTW89_FCC][1][45] = -2,
+ [0][1][2][1][RTW89_FCC][2][45] = 127,
+ [0][1][2][1][RTW89_ETSI][1][45] = 127,
+ [0][1][2][1][RTW89_ETSI][0][45] = 127,
+ [0][1][2][1][RTW89_MKK][1][45] = 127,
+ [0][1][2][1][RTW89_MKK][0][45] = 127,
+ [0][1][2][1][RTW89_IC][1][45] = -2,
+ [0][1][2][1][RTW89_KCC][1][45] = 12,
+ [0][1][2][1][RTW89_KCC][0][45] = 127,
+ [0][1][2][1][RTW89_ACMA][1][45] = 127,
+ [0][1][2][1][RTW89_ACMA][0][45] = 127,
+ [0][1][2][1][RTW89_CHILE][1][45] = -2,
+ [0][1][2][1][RTW89_QATAR][1][45] = 127,
+ [0][1][2][1][RTW89_QATAR][0][45] = 127,
+ [0][1][2][1][RTW89_UK][1][45] = 127,
+ [0][1][2][1][RTW89_UK][0][45] = 127,
+ [0][1][2][1][RTW89_FCC][1][47] = -2,
+ [0][1][2][1][RTW89_FCC][2][47] = 127,
+ [0][1][2][1][RTW89_ETSI][1][47] = 127,
+ [0][1][2][1][RTW89_ETSI][0][47] = 127,
+ [0][1][2][1][RTW89_MKK][1][47] = 127,
+ [0][1][2][1][RTW89_MKK][0][47] = 127,
+ [0][1][2][1][RTW89_IC][1][47] = -2,
+ [0][1][2][1][RTW89_KCC][1][47] = 12,
+ [0][1][2][1][RTW89_KCC][0][47] = 127,
+ [0][1][2][1][RTW89_ACMA][1][47] = 127,
+ [0][1][2][1][RTW89_ACMA][0][47] = 127,
+ [0][1][2][1][RTW89_CHILE][1][47] = -2,
+ [0][1][2][1][RTW89_QATAR][1][47] = 127,
+ [0][1][2][1][RTW89_QATAR][0][47] = 127,
+ [0][1][2][1][RTW89_UK][1][47] = 127,
+ [0][1][2][1][RTW89_UK][0][47] = 127,
+ [0][1][2][1][RTW89_FCC][1][49] = -2,
+ [0][1][2][1][RTW89_FCC][2][49] = 127,
+ [0][1][2][1][RTW89_ETSI][1][49] = 127,
+ [0][1][2][1][RTW89_ETSI][0][49] = 127,
+ [0][1][2][1][RTW89_MKK][1][49] = 127,
+ [0][1][2][1][RTW89_MKK][0][49] = 127,
+ [0][1][2][1][RTW89_IC][1][49] = -2,
+ [0][1][2][1][RTW89_KCC][1][49] = 12,
+ [0][1][2][1][RTW89_KCC][0][49] = 127,
+ [0][1][2][1][RTW89_ACMA][1][49] = 127,
+ [0][1][2][1][RTW89_ACMA][0][49] = 127,
+ [0][1][2][1][RTW89_CHILE][1][49] = -2,
+ [0][1][2][1][RTW89_QATAR][1][49] = 127,
+ [0][1][2][1][RTW89_QATAR][0][49] = 127,
+ [0][1][2][1][RTW89_UK][1][49] = 127,
+ [0][1][2][1][RTW89_UK][0][49] = 127,
+ [0][1][2][1][RTW89_FCC][1][51] = -2,
+ [0][1][2][1][RTW89_FCC][2][51] = 127,
+ [0][1][2][1][RTW89_ETSI][1][51] = 127,
+ [0][1][2][1][RTW89_ETSI][0][51] = 127,
+ [0][1][2][1][RTW89_MKK][1][51] = 127,
+ [0][1][2][1][RTW89_MKK][0][51] = 127,
+ [0][1][2][1][RTW89_IC][1][51] = -2,
+ [0][1][2][1][RTW89_KCC][1][51] = 12,
+ [0][1][2][1][RTW89_KCC][0][51] = 127,
+ [0][1][2][1][RTW89_ACMA][1][51] = 127,
+ [0][1][2][1][RTW89_ACMA][0][51] = 127,
+ [0][1][2][1][RTW89_CHILE][1][51] = -2,
+ [0][1][2][1][RTW89_QATAR][1][51] = 127,
+ [0][1][2][1][RTW89_QATAR][0][51] = 127,
+ [0][1][2][1][RTW89_UK][1][51] = 127,
+ [0][1][2][1][RTW89_UK][0][51] = 127,
+ [0][1][2][1][RTW89_FCC][1][53] = -2,
+ [0][1][2][1][RTW89_FCC][2][53] = 127,
+ [0][1][2][1][RTW89_ETSI][1][53] = 127,
+ [0][1][2][1][RTW89_ETSI][0][53] = 127,
+ [0][1][2][1][RTW89_MKK][1][53] = 127,
+ [0][1][2][1][RTW89_MKK][0][53] = 127,
+ [0][1][2][1][RTW89_IC][1][53] = -2,
+ [0][1][2][1][RTW89_KCC][1][53] = 12,
+ [0][1][2][1][RTW89_KCC][0][53] = 127,
+ [0][1][2][1][RTW89_ACMA][1][53] = 127,
+ [0][1][2][1][RTW89_ACMA][0][53] = 127,
+ [0][1][2][1][RTW89_CHILE][1][53] = -2,
+ [0][1][2][1][RTW89_QATAR][1][53] = 127,
+ [0][1][2][1][RTW89_QATAR][0][53] = 127,
+ [0][1][2][1][RTW89_UK][1][53] = 127,
+ [0][1][2][1][RTW89_UK][0][53] = 127,
+ [0][1][2][1][RTW89_FCC][1][55] = -2,
+ [0][1][2][1][RTW89_FCC][2][55] = 68,
+ [0][1][2][1][RTW89_ETSI][1][55] = 127,
+ [0][1][2][1][RTW89_ETSI][0][55] = 127,
+ [0][1][2][1][RTW89_MKK][1][55] = 127,
+ [0][1][2][1][RTW89_MKK][0][55] = 127,
+ [0][1][2][1][RTW89_IC][1][55] = -2,
+ [0][1][2][1][RTW89_KCC][1][55] = 12,
+ [0][1][2][1][RTW89_KCC][0][55] = 127,
+ [0][1][2][1][RTW89_ACMA][1][55] = 127,
+ [0][1][2][1][RTW89_ACMA][0][55] = 127,
+ [0][1][2][1][RTW89_CHILE][1][55] = -2,
+ [0][1][2][1][RTW89_QATAR][1][55] = 127,
+ [0][1][2][1][RTW89_QATAR][0][55] = 127,
+ [0][1][2][1][RTW89_UK][1][55] = 127,
+ [0][1][2][1][RTW89_UK][0][55] = 127,
+ [0][1][2][1][RTW89_FCC][1][57] = -2,
+ [0][1][2][1][RTW89_FCC][2][57] = 68,
+ [0][1][2][1][RTW89_ETSI][1][57] = 127,
+ [0][1][2][1][RTW89_ETSI][0][57] = 127,
+ [0][1][2][1][RTW89_MKK][1][57] = 127,
+ [0][1][2][1][RTW89_MKK][0][57] = 127,
+ [0][1][2][1][RTW89_IC][1][57] = -2,
+ [0][1][2][1][RTW89_KCC][1][57] = 12,
+ [0][1][2][1][RTW89_KCC][0][57] = 127,
+ [0][1][2][1][RTW89_ACMA][1][57] = 127,
+ [0][1][2][1][RTW89_ACMA][0][57] = 127,
+ [0][1][2][1][RTW89_CHILE][1][57] = -2,
+ [0][1][2][1][RTW89_QATAR][1][57] = 127,
+ [0][1][2][1][RTW89_QATAR][0][57] = 127,
+ [0][1][2][1][RTW89_UK][1][57] = 127,
+ [0][1][2][1][RTW89_UK][0][57] = 127,
+ [0][1][2][1][RTW89_FCC][1][59] = -2,
+ [0][1][2][1][RTW89_FCC][2][59] = 68,
+ [0][1][2][1][RTW89_ETSI][1][59] = 127,
+ [0][1][2][1][RTW89_ETSI][0][59] = 127,
+ [0][1][2][1][RTW89_MKK][1][59] = 127,
+ [0][1][2][1][RTW89_MKK][0][59] = 127,
+ [0][1][2][1][RTW89_IC][1][59] = -2,
+ [0][1][2][1][RTW89_KCC][1][59] = 12,
+ [0][1][2][1][RTW89_KCC][0][59] = 127,
+ [0][1][2][1][RTW89_ACMA][1][59] = 127,
+ [0][1][2][1][RTW89_ACMA][0][59] = 127,
+ [0][1][2][1][RTW89_CHILE][1][59] = -2,
+ [0][1][2][1][RTW89_QATAR][1][59] = 127,
+ [0][1][2][1][RTW89_QATAR][0][59] = 127,
+ [0][1][2][1][RTW89_UK][1][59] = 127,
+ [0][1][2][1][RTW89_UK][0][59] = 127,
+ [0][1][2][1][RTW89_FCC][1][60] = -2,
+ [0][1][2][1][RTW89_FCC][2][60] = 68,
+ [0][1][2][1][RTW89_ETSI][1][60] = 127,
+ [0][1][2][1][RTW89_ETSI][0][60] = 127,
+ [0][1][2][1][RTW89_MKK][1][60] = 127,
+ [0][1][2][1][RTW89_MKK][0][60] = 127,
+ [0][1][2][1][RTW89_IC][1][60] = -2,
+ [0][1][2][1][RTW89_KCC][1][60] = 12,
+ [0][1][2][1][RTW89_KCC][0][60] = 127,
+ [0][1][2][1][RTW89_ACMA][1][60] = 127,
+ [0][1][2][1][RTW89_ACMA][0][60] = 127,
+ [0][1][2][1][RTW89_CHILE][1][60] = -2,
+ [0][1][2][1][RTW89_QATAR][1][60] = 127,
+ [0][1][2][1][RTW89_QATAR][0][60] = 127,
+ [0][1][2][1][RTW89_UK][1][60] = 127,
+ [0][1][2][1][RTW89_UK][0][60] = 127,
+ [0][1][2][1][RTW89_FCC][1][62] = -2,
+ [0][1][2][1][RTW89_FCC][2][62] = 68,
+ [0][1][2][1][RTW89_ETSI][1][62] = 127,
+ [0][1][2][1][RTW89_ETSI][0][62] = 127,
+ [0][1][2][1][RTW89_MKK][1][62] = 127,
+ [0][1][2][1][RTW89_MKK][0][62] = 127,
+ [0][1][2][1][RTW89_IC][1][62] = -2,
+ [0][1][2][1][RTW89_KCC][1][62] = 12,
+ [0][1][2][1][RTW89_KCC][0][62] = 127,
+ [0][1][2][1][RTW89_ACMA][1][62] = 127,
+ [0][1][2][1][RTW89_ACMA][0][62] = 127,
+ [0][1][2][1][RTW89_CHILE][1][62] = -2,
+ [0][1][2][1][RTW89_QATAR][1][62] = 127,
+ [0][1][2][1][RTW89_QATAR][0][62] = 127,
+ [0][1][2][1][RTW89_UK][1][62] = 127,
+ [0][1][2][1][RTW89_UK][0][62] = 127,
+ [0][1][2][1][RTW89_FCC][1][64] = -2,
+ [0][1][2][1][RTW89_FCC][2][64] = 68,
+ [0][1][2][1][RTW89_ETSI][1][64] = 127,
+ [0][1][2][1][RTW89_ETSI][0][64] = 127,
+ [0][1][2][1][RTW89_MKK][1][64] = 127,
+ [0][1][2][1][RTW89_MKK][0][64] = 127,
+ [0][1][2][1][RTW89_IC][1][64] = -2,
+ [0][1][2][1][RTW89_KCC][1][64] = 12,
+ [0][1][2][1][RTW89_KCC][0][64] = 127,
+ [0][1][2][1][RTW89_ACMA][1][64] = 127,
+ [0][1][2][1][RTW89_ACMA][0][64] = 127,
+ [0][1][2][1][RTW89_CHILE][1][64] = -2,
+ [0][1][2][1][RTW89_QATAR][1][64] = 127,
+ [0][1][2][1][RTW89_QATAR][0][64] = 127,
+ [0][1][2][1][RTW89_UK][1][64] = 127,
+ [0][1][2][1][RTW89_UK][0][64] = 127,
+ [0][1][2][1][RTW89_FCC][1][66] = -2,
+ [0][1][2][1][RTW89_FCC][2][66] = 68,
+ [0][1][2][1][RTW89_ETSI][1][66] = 127,
+ [0][1][2][1][RTW89_ETSI][0][66] = 127,
+ [0][1][2][1][RTW89_MKK][1][66] = 127,
+ [0][1][2][1][RTW89_MKK][0][66] = 127,
+ [0][1][2][1][RTW89_IC][1][66] = -2,
+ [0][1][2][1][RTW89_KCC][1][66] = 12,
+ [0][1][2][1][RTW89_KCC][0][66] = 127,
+ [0][1][2][1][RTW89_ACMA][1][66] = 127,
+ [0][1][2][1][RTW89_ACMA][0][66] = 127,
+ [0][1][2][1][RTW89_CHILE][1][66] = -2,
+ [0][1][2][1][RTW89_QATAR][1][66] = 127,
+ [0][1][2][1][RTW89_QATAR][0][66] = 127,
+ [0][1][2][1][RTW89_UK][1][66] = 127,
+ [0][1][2][1][RTW89_UK][0][66] = 127,
+ [0][1][2][1][RTW89_FCC][1][68] = -2,
+ [0][1][2][1][RTW89_FCC][2][68] = 68,
+ [0][1][2][1][RTW89_ETSI][1][68] = 127,
+ [0][1][2][1][RTW89_ETSI][0][68] = 127,
+ [0][1][2][1][RTW89_MKK][1][68] = 127,
+ [0][1][2][1][RTW89_MKK][0][68] = 127,
+ [0][1][2][1][RTW89_IC][1][68] = -2,
+ [0][1][2][1][RTW89_KCC][1][68] = 12,
+ [0][1][2][1][RTW89_KCC][0][68] = 127,
+ [0][1][2][1][RTW89_ACMA][1][68] = 127,
+ [0][1][2][1][RTW89_ACMA][0][68] = 127,
+ [0][1][2][1][RTW89_CHILE][1][68] = -2,
+ [0][1][2][1][RTW89_QATAR][1][68] = 127,
+ [0][1][2][1][RTW89_QATAR][0][68] = 127,
+ [0][1][2][1][RTW89_UK][1][68] = 127,
+ [0][1][2][1][RTW89_UK][0][68] = 127,
+ [0][1][2][1][RTW89_FCC][1][70] = -2,
+ [0][1][2][1][RTW89_FCC][2][70] = 68,
+ [0][1][2][1][RTW89_ETSI][1][70] = 127,
+ [0][1][2][1][RTW89_ETSI][0][70] = 127,
+ [0][1][2][1][RTW89_MKK][1][70] = 127,
+ [0][1][2][1][RTW89_MKK][0][70] = 127,
+ [0][1][2][1][RTW89_IC][1][70] = -2,
+ [0][1][2][1][RTW89_KCC][1][70] = 12,
+ [0][1][2][1][RTW89_KCC][0][70] = 127,
+ [0][1][2][1][RTW89_ACMA][1][70] = 127,
+ [0][1][2][1][RTW89_ACMA][0][70] = 127,
+ [0][1][2][1][RTW89_CHILE][1][70] = -2,
+ [0][1][2][1][RTW89_QATAR][1][70] = 127,
+ [0][1][2][1][RTW89_QATAR][0][70] = 127,
+ [0][1][2][1][RTW89_UK][1][70] = 127,
+ [0][1][2][1][RTW89_UK][0][70] = 127,
+ [0][1][2][1][RTW89_FCC][1][72] = -2,
+ [0][1][2][1][RTW89_FCC][2][72] = 68,
+ [0][1][2][1][RTW89_ETSI][1][72] = 127,
+ [0][1][2][1][RTW89_ETSI][0][72] = 127,
+ [0][1][2][1][RTW89_MKK][1][72] = 127,
+ [0][1][2][1][RTW89_MKK][0][72] = 127,
+ [0][1][2][1][RTW89_IC][1][72] = -2,
+ [0][1][2][1][RTW89_KCC][1][72] = 12,
+ [0][1][2][1][RTW89_KCC][0][72] = 127,
+ [0][1][2][1][RTW89_ACMA][1][72] = 127,
+ [0][1][2][1][RTW89_ACMA][0][72] = 127,
+ [0][1][2][1][RTW89_CHILE][1][72] = -2,
+ [0][1][2][1][RTW89_QATAR][1][72] = 127,
+ [0][1][2][1][RTW89_QATAR][0][72] = 127,
+ [0][1][2][1][RTW89_UK][1][72] = 127,
+ [0][1][2][1][RTW89_UK][0][72] = 127,
+ [0][1][2][1][RTW89_FCC][1][74] = -2,
+ [0][1][2][1][RTW89_FCC][2][74] = 68,
+ [0][1][2][1][RTW89_ETSI][1][74] = 127,
+ [0][1][2][1][RTW89_ETSI][0][74] = 127,
+ [0][1][2][1][RTW89_MKK][1][74] = 127,
+ [0][1][2][1][RTW89_MKK][0][74] = 127,
+ [0][1][2][1][RTW89_IC][1][74] = -2,
+ [0][1][2][1][RTW89_KCC][1][74] = 12,
+ [0][1][2][1][RTW89_KCC][0][74] = 127,
+ [0][1][2][1][RTW89_ACMA][1][74] = 127,
+ [0][1][2][1][RTW89_ACMA][0][74] = 127,
+ [0][1][2][1][RTW89_CHILE][1][74] = -2,
+ [0][1][2][1][RTW89_QATAR][1][74] = 127,
+ [0][1][2][1][RTW89_QATAR][0][74] = 127,
+ [0][1][2][1][RTW89_UK][1][74] = 127,
+ [0][1][2][1][RTW89_UK][0][74] = 127,
+ [0][1][2][1][RTW89_FCC][1][75] = -2,
+ [0][1][2][1][RTW89_FCC][2][75] = 68,
+ [0][1][2][1][RTW89_ETSI][1][75] = 127,
+ [0][1][2][1][RTW89_ETSI][0][75] = 127,
+ [0][1][2][1][RTW89_MKK][1][75] = 127,
+ [0][1][2][1][RTW89_MKK][0][75] = 127,
+ [0][1][2][1][RTW89_IC][1][75] = -2,
+ [0][1][2][1][RTW89_KCC][1][75] = 12,
+ [0][1][2][1][RTW89_KCC][0][75] = 127,
+ [0][1][2][1][RTW89_ACMA][1][75] = 127,
+ [0][1][2][1][RTW89_ACMA][0][75] = 127,
+ [0][1][2][1][RTW89_CHILE][1][75] = -2,
+ [0][1][2][1][RTW89_QATAR][1][75] = 127,
+ [0][1][2][1][RTW89_QATAR][0][75] = 127,
+ [0][1][2][1][RTW89_UK][1][75] = 127,
+ [0][1][2][1][RTW89_UK][0][75] = 127,
+ [0][1][2][1][RTW89_FCC][1][77] = -2,
+ [0][1][2][1][RTW89_FCC][2][77] = 68,
+ [0][1][2][1][RTW89_ETSI][1][77] = 127,
+ [0][1][2][1][RTW89_ETSI][0][77] = 127,
+ [0][1][2][1][RTW89_MKK][1][77] = 127,
+ [0][1][2][1][RTW89_MKK][0][77] = 127,
+ [0][1][2][1][RTW89_IC][1][77] = -2,
+ [0][1][2][1][RTW89_KCC][1][77] = 12,
+ [0][1][2][1][RTW89_KCC][0][77] = 127,
+ [0][1][2][1][RTW89_ACMA][1][77] = 127,
+ [0][1][2][1][RTW89_ACMA][0][77] = 127,
+ [0][1][2][1][RTW89_CHILE][1][77] = -2,
+ [0][1][2][1][RTW89_QATAR][1][77] = 127,
+ [0][1][2][1][RTW89_QATAR][0][77] = 127,
+ [0][1][2][1][RTW89_UK][1][77] = 127,
+ [0][1][2][1][RTW89_UK][0][77] = 127,
+ [0][1][2][1][RTW89_FCC][1][79] = -2,
+ [0][1][2][1][RTW89_FCC][2][79] = 68,
+ [0][1][2][1][RTW89_ETSI][1][79] = 127,
+ [0][1][2][1][RTW89_ETSI][0][79] = 127,
+ [0][1][2][1][RTW89_MKK][1][79] = 127,
+ [0][1][2][1][RTW89_MKK][0][79] = 127,
+ [0][1][2][1][RTW89_IC][1][79] = -2,
+ [0][1][2][1][RTW89_KCC][1][79] = 12,
+ [0][1][2][1][RTW89_KCC][0][79] = 127,
+ [0][1][2][1][RTW89_ACMA][1][79] = 127,
+ [0][1][2][1][RTW89_ACMA][0][79] = 127,
+ [0][1][2][1][RTW89_CHILE][1][79] = -2,
+ [0][1][2][1][RTW89_QATAR][1][79] = 127,
+ [0][1][2][1][RTW89_QATAR][0][79] = 127,
+ [0][1][2][1][RTW89_UK][1][79] = 127,
+ [0][1][2][1][RTW89_UK][0][79] = 127,
+ [0][1][2][1][RTW89_FCC][1][81] = -2,
+ [0][1][2][1][RTW89_FCC][2][81] = 68,
+ [0][1][2][1][RTW89_ETSI][1][81] = 127,
+ [0][1][2][1][RTW89_ETSI][0][81] = 127,
+ [0][1][2][1][RTW89_MKK][1][81] = 127,
+ [0][1][2][1][RTW89_MKK][0][81] = 127,
+ [0][1][2][1][RTW89_IC][1][81] = -2,
+ [0][1][2][1][RTW89_KCC][1][81] = 12,
+ [0][1][2][1][RTW89_KCC][0][81] = 127,
+ [0][1][2][1][RTW89_ACMA][1][81] = 127,
+ [0][1][2][1][RTW89_ACMA][0][81] = 127,
+ [0][1][2][1][RTW89_CHILE][1][81] = -2,
+ [0][1][2][1][RTW89_QATAR][1][81] = 127,
+ [0][1][2][1][RTW89_QATAR][0][81] = 127,
+ [0][1][2][1][RTW89_UK][1][81] = 127,
+ [0][1][2][1][RTW89_UK][0][81] = 127,
+ [0][1][2][1][RTW89_FCC][1][83] = -2,
+ [0][1][2][1][RTW89_FCC][2][83] = 68,
+ [0][1][2][1][RTW89_ETSI][1][83] = 127,
+ [0][1][2][1][RTW89_ETSI][0][83] = 127,
+ [0][1][2][1][RTW89_MKK][1][83] = 127,
+ [0][1][2][1][RTW89_MKK][0][83] = 127,
+ [0][1][2][1][RTW89_IC][1][83] = -2,
+ [0][1][2][1][RTW89_KCC][1][83] = 20,
+ [0][1][2][1][RTW89_KCC][0][83] = 127,
+ [0][1][2][1][RTW89_ACMA][1][83] = 127,
+ [0][1][2][1][RTW89_ACMA][0][83] = 127,
+ [0][1][2][1][RTW89_CHILE][1][83] = -2,
+ [0][1][2][1][RTW89_QATAR][1][83] = 127,
+ [0][1][2][1][RTW89_QATAR][0][83] = 127,
+ [0][1][2][1][RTW89_UK][1][83] = 127,
+ [0][1][2][1][RTW89_UK][0][83] = 127,
+ [0][1][2][1][RTW89_FCC][1][85] = -2,
+ [0][1][2][1][RTW89_FCC][2][85] = 68,
+ [0][1][2][1][RTW89_ETSI][1][85] = 127,
+ [0][1][2][1][RTW89_ETSI][0][85] = 127,
+ [0][1][2][1][RTW89_MKK][1][85] = 127,
+ [0][1][2][1][RTW89_MKK][0][85] = 127,
+ [0][1][2][1][RTW89_IC][1][85] = -2,
+ [0][1][2][1][RTW89_KCC][1][85] = 20,
+ [0][1][2][1][RTW89_KCC][0][85] = 127,
+ [0][1][2][1][RTW89_ACMA][1][85] = 127,
+ [0][1][2][1][RTW89_ACMA][0][85] = 127,
+ [0][1][2][1][RTW89_CHILE][1][85] = -2,
+ [0][1][2][1][RTW89_QATAR][1][85] = 127,
+ [0][1][2][1][RTW89_QATAR][0][85] = 127,
+ [0][1][2][1][RTW89_UK][1][85] = 127,
+ [0][1][2][1][RTW89_UK][0][85] = 127,
+ [0][1][2][1][RTW89_FCC][1][87] = -2,
+ [0][1][2][1][RTW89_FCC][2][87] = 127,
+ [0][1][2][1][RTW89_ETSI][1][87] = 127,
+ [0][1][2][1][RTW89_ETSI][0][87] = 127,
+ [0][1][2][1][RTW89_MKK][1][87] = 127,
+ [0][1][2][1][RTW89_MKK][0][87] = 127,
+ [0][1][2][1][RTW89_IC][1][87] = -2,
+ [0][1][2][1][RTW89_KCC][1][87] = 20,
+ [0][1][2][1][RTW89_KCC][0][87] = 127,
+ [0][1][2][1][RTW89_ACMA][1][87] = 127,
+ [0][1][2][1][RTW89_ACMA][0][87] = 127,
+ [0][1][2][1][RTW89_CHILE][1][87] = -2,
+ [0][1][2][1][RTW89_QATAR][1][87] = 127,
+ [0][1][2][1][RTW89_QATAR][0][87] = 127,
+ [0][1][2][1][RTW89_UK][1][87] = 127,
+ [0][1][2][1][RTW89_UK][0][87] = 127,
+ [0][1][2][1][RTW89_FCC][1][89] = -2,
+ [0][1][2][1][RTW89_FCC][2][89] = 127,
+ [0][1][2][1][RTW89_ETSI][1][89] = 127,
+ [0][1][2][1][RTW89_ETSI][0][89] = 127,
+ [0][1][2][1][RTW89_MKK][1][89] = 127,
+ [0][1][2][1][RTW89_MKK][0][89] = 127,
+ [0][1][2][1][RTW89_IC][1][89] = -2,
+ [0][1][2][1][RTW89_KCC][1][89] = 20,
+ [0][1][2][1][RTW89_KCC][0][89] = 127,
+ [0][1][2][1][RTW89_ACMA][1][89] = 127,
+ [0][1][2][1][RTW89_ACMA][0][89] = 127,
+ [0][1][2][1][RTW89_CHILE][1][89] = -2,
+ [0][1][2][1][RTW89_QATAR][1][89] = 127,
+ [0][1][2][1][RTW89_QATAR][0][89] = 127,
+ [0][1][2][1][RTW89_UK][1][89] = 127,
+ [0][1][2][1][RTW89_UK][0][89] = 127,
+ [0][1][2][1][RTW89_FCC][1][90] = -2,
+ [0][1][2][1][RTW89_FCC][2][90] = 127,
+ [0][1][2][1][RTW89_ETSI][1][90] = 127,
+ [0][1][2][1][RTW89_ETSI][0][90] = 127,
+ [0][1][2][1][RTW89_MKK][1][90] = 127,
+ [0][1][2][1][RTW89_MKK][0][90] = 127,
+ [0][1][2][1][RTW89_IC][1][90] = -2,
+ [0][1][2][1][RTW89_KCC][1][90] = 20,
+ [0][1][2][1][RTW89_KCC][0][90] = 127,
+ [0][1][2][1][RTW89_ACMA][1][90] = 127,
+ [0][1][2][1][RTW89_ACMA][0][90] = 127,
+ [0][1][2][1][RTW89_CHILE][1][90] = -2,
+ [0][1][2][1][RTW89_QATAR][1][90] = 127,
+ [0][1][2][1][RTW89_QATAR][0][90] = 127,
+ [0][1][2][1][RTW89_UK][1][90] = 127,
+ [0][1][2][1][RTW89_UK][0][90] = 127,
+ [0][1][2][1][RTW89_FCC][1][92] = -2,
+ [0][1][2][1][RTW89_FCC][2][92] = 127,
+ [0][1][2][1][RTW89_ETSI][1][92] = 127,
+ [0][1][2][1][RTW89_ETSI][0][92] = 127,
+ [0][1][2][1][RTW89_MKK][1][92] = 127,
+ [0][1][2][1][RTW89_MKK][0][92] = 127,
+ [0][1][2][1][RTW89_IC][1][92] = -2,
+ [0][1][2][1][RTW89_KCC][1][92] = 20,
+ [0][1][2][1][RTW89_KCC][0][92] = 127,
+ [0][1][2][1][RTW89_ACMA][1][92] = 127,
+ [0][1][2][1][RTW89_ACMA][0][92] = 127,
+ [0][1][2][1][RTW89_CHILE][1][92] = -2,
+ [0][1][2][1][RTW89_QATAR][1][92] = 127,
+ [0][1][2][1][RTW89_QATAR][0][92] = 127,
+ [0][1][2][1][RTW89_UK][1][92] = 127,
+ [0][1][2][1][RTW89_UK][0][92] = 127,
+ [0][1][2][1][RTW89_FCC][1][94] = -2,
+ [0][1][2][1][RTW89_FCC][2][94] = 127,
+ [0][1][2][1][RTW89_ETSI][1][94] = 127,
+ [0][1][2][1][RTW89_ETSI][0][94] = 127,
+ [0][1][2][1][RTW89_MKK][1][94] = 127,
+ [0][1][2][1][RTW89_MKK][0][94] = 127,
+ [0][1][2][1][RTW89_IC][1][94] = -2,
+ [0][1][2][1][RTW89_KCC][1][94] = 20,
+ [0][1][2][1][RTW89_KCC][0][94] = 127,
+ [0][1][2][1][RTW89_ACMA][1][94] = 127,
+ [0][1][2][1][RTW89_ACMA][0][94] = 127,
+ [0][1][2][1][RTW89_CHILE][1][94] = -2,
+ [0][1][2][1][RTW89_QATAR][1][94] = 127,
+ [0][1][2][1][RTW89_QATAR][0][94] = 127,
+ [0][1][2][1][RTW89_UK][1][94] = 127,
+ [0][1][2][1][RTW89_UK][0][94] = 127,
+ [0][1][2][1][RTW89_FCC][1][96] = -2,
+ [0][1][2][1][RTW89_FCC][2][96] = 127,
+ [0][1][2][1][RTW89_ETSI][1][96] = 127,
+ [0][1][2][1][RTW89_ETSI][0][96] = 127,
+ [0][1][2][1][RTW89_MKK][1][96] = 127,
+ [0][1][2][1][RTW89_MKK][0][96] = 127,
+ [0][1][2][1][RTW89_IC][1][96] = -2,
+ [0][1][2][1][RTW89_KCC][1][96] = 20,
+ [0][1][2][1][RTW89_KCC][0][96] = 127,
+ [0][1][2][1][RTW89_ACMA][1][96] = 127,
+ [0][1][2][1][RTW89_ACMA][0][96] = 127,
+ [0][1][2][1][RTW89_CHILE][1][96] = -2,
+ [0][1][2][1][RTW89_QATAR][1][96] = 127,
+ [0][1][2][1][RTW89_QATAR][0][96] = 127,
+ [0][1][2][1][RTW89_UK][1][96] = 127,
+ [0][1][2][1][RTW89_UK][0][96] = 127,
+ [0][1][2][1][RTW89_FCC][1][98] = -2,
+ [0][1][2][1][RTW89_FCC][2][98] = 127,
+ [0][1][2][1][RTW89_ETSI][1][98] = 127,
+ [0][1][2][1][RTW89_ETSI][0][98] = 127,
+ [0][1][2][1][RTW89_MKK][1][98] = 127,
+ [0][1][2][1][RTW89_MKK][0][98] = 127,
+ [0][1][2][1][RTW89_IC][1][98] = -2,
+ [0][1][2][1][RTW89_KCC][1][98] = 20,
+ [0][1][2][1][RTW89_KCC][0][98] = 127,
+ [0][1][2][1][RTW89_ACMA][1][98] = 127,
+ [0][1][2][1][RTW89_ACMA][0][98] = 127,
+ [0][1][2][1][RTW89_CHILE][1][98] = -2,
+ [0][1][2][1][RTW89_QATAR][1][98] = 127,
+ [0][1][2][1][RTW89_QATAR][0][98] = 127,
+ [0][1][2][1][RTW89_UK][1][98] = 127,
+ [0][1][2][1][RTW89_UK][0][98] = 127,
+ [0][1][2][1][RTW89_FCC][1][100] = -2,
+ [0][1][2][1][RTW89_FCC][2][100] = 127,
+ [0][1][2][1][RTW89_ETSI][1][100] = 127,
+ [0][1][2][1][RTW89_ETSI][0][100] = 127,
+ [0][1][2][1][RTW89_MKK][1][100] = 127,
+ [0][1][2][1][RTW89_MKK][0][100] = 127,
+ [0][1][2][1][RTW89_IC][1][100] = -2,
+ [0][1][2][1][RTW89_KCC][1][100] = 20,
+ [0][1][2][1][RTW89_KCC][0][100] = 127,
+ [0][1][2][1][RTW89_ACMA][1][100] = 127,
+ [0][1][2][1][RTW89_ACMA][0][100] = 127,
+ [0][1][2][1][RTW89_CHILE][1][100] = -2,
+ [0][1][2][1][RTW89_QATAR][1][100] = 127,
+ [0][1][2][1][RTW89_QATAR][0][100] = 127,
+ [0][1][2][1][RTW89_UK][1][100] = 127,
+ [0][1][2][1][RTW89_UK][0][100] = 127,
+ [0][1][2][1][RTW89_FCC][1][102] = -2,
+ [0][1][2][1][RTW89_FCC][2][102] = 127,
+ [0][1][2][1][RTW89_ETSI][1][102] = 127,
+ [0][1][2][1][RTW89_ETSI][0][102] = 127,
+ [0][1][2][1][RTW89_MKK][1][102] = 127,
+ [0][1][2][1][RTW89_MKK][0][102] = 127,
+ [0][1][2][1][RTW89_IC][1][102] = -2,
+ [0][1][2][1][RTW89_KCC][1][102] = 20,
+ [0][1][2][1][RTW89_KCC][0][102] = 127,
+ [0][1][2][1][RTW89_ACMA][1][102] = 127,
+ [0][1][2][1][RTW89_ACMA][0][102] = 127,
+ [0][1][2][1][RTW89_CHILE][1][102] = -2,
+ [0][1][2][1][RTW89_QATAR][1][102] = 127,
+ [0][1][2][1][RTW89_QATAR][0][102] = 127,
+ [0][1][2][1][RTW89_UK][1][102] = 127,
+ [0][1][2][1][RTW89_UK][0][102] = 127,
+ [0][1][2][1][RTW89_FCC][1][104] = -2,
+ [0][1][2][1][RTW89_FCC][2][104] = 127,
+ [0][1][2][1][RTW89_ETSI][1][104] = 127,
+ [0][1][2][1][RTW89_ETSI][0][104] = 127,
+ [0][1][2][1][RTW89_MKK][1][104] = 127,
+ [0][1][2][1][RTW89_MKK][0][104] = 127,
+ [0][1][2][1][RTW89_IC][1][104] = -2,
+ [0][1][2][1][RTW89_KCC][1][104] = 20,
+ [0][1][2][1][RTW89_KCC][0][104] = 127,
+ [0][1][2][1][RTW89_ACMA][1][104] = 127,
+ [0][1][2][1][RTW89_ACMA][0][104] = 127,
+ [0][1][2][1][RTW89_CHILE][1][104] = -2,
+ [0][1][2][1][RTW89_QATAR][1][104] = 127,
+ [0][1][2][1][RTW89_QATAR][0][104] = 127,
+ [0][1][2][1][RTW89_UK][1][104] = 127,
+ [0][1][2][1][RTW89_UK][0][104] = 127,
+ [0][1][2][1][RTW89_FCC][1][105] = -2,
+ [0][1][2][1][RTW89_FCC][2][105] = 127,
+ [0][1][2][1][RTW89_ETSI][1][105] = 127,
+ [0][1][2][1][RTW89_ETSI][0][105] = 127,
+ [0][1][2][1][RTW89_MKK][1][105] = 127,
+ [0][1][2][1][RTW89_MKK][0][105] = 127,
+ [0][1][2][1][RTW89_IC][1][105] = -2,
+ [0][1][2][1][RTW89_KCC][1][105] = 20,
+ [0][1][2][1][RTW89_KCC][0][105] = 127,
+ [0][1][2][1][RTW89_ACMA][1][105] = 127,
+ [0][1][2][1][RTW89_ACMA][0][105] = 127,
+ [0][1][2][1][RTW89_CHILE][1][105] = -2,
+ [0][1][2][1][RTW89_QATAR][1][105] = 127,
+ [0][1][2][1][RTW89_QATAR][0][105] = 127,
+ [0][1][2][1][RTW89_UK][1][105] = 127,
+ [0][1][2][1][RTW89_UK][0][105] = 127,
+ [0][1][2][1][RTW89_FCC][1][107] = 1,
+ [0][1][2][1][RTW89_FCC][2][107] = 127,
+ [0][1][2][1][RTW89_ETSI][1][107] = 127,
+ [0][1][2][1][RTW89_ETSI][0][107] = 127,
+ [0][1][2][1][RTW89_MKK][1][107] = 127,
+ [0][1][2][1][RTW89_MKK][0][107] = 127,
+ [0][1][2][1][RTW89_IC][1][107] = 1,
+ [0][1][2][1][RTW89_KCC][1][107] = 20,
+ [0][1][2][1][RTW89_KCC][0][107] = 127,
+ [0][1][2][1][RTW89_ACMA][1][107] = 127,
+ [0][1][2][1][RTW89_ACMA][0][107] = 127,
+ [0][1][2][1][RTW89_CHILE][1][107] = 1,
+ [0][1][2][1][RTW89_QATAR][1][107] = 127,
+ [0][1][2][1][RTW89_QATAR][0][107] = 127,
+ [0][1][2][1][RTW89_UK][1][107] = 127,
+ [0][1][2][1][RTW89_UK][0][107] = 127,
+ [0][1][2][1][RTW89_FCC][1][109] = 1,
+ [0][1][2][1][RTW89_FCC][2][109] = 127,
+ [0][1][2][1][RTW89_ETSI][1][109] = 127,
+ [0][1][2][1][RTW89_ETSI][0][109] = 127,
+ [0][1][2][1][RTW89_MKK][1][109] = 127,
+ [0][1][2][1][RTW89_MKK][0][109] = 127,
+ [0][1][2][1][RTW89_IC][1][109] = 1,
+ [0][1][2][1][RTW89_KCC][1][109] = 20,
+ [0][1][2][1][RTW89_KCC][0][109] = 127,
+ [0][1][2][1][RTW89_ACMA][1][109] = 127,
+ [0][1][2][1][RTW89_ACMA][0][109] = 127,
+ [0][1][2][1][RTW89_CHILE][1][109] = 1,
+ [0][1][2][1][RTW89_QATAR][1][109] = 127,
+ [0][1][2][1][RTW89_QATAR][0][109] = 127,
+ [0][1][2][1][RTW89_UK][1][109] = 127,
+ [0][1][2][1][RTW89_UK][0][109] = 127,
+ [0][1][2][1][RTW89_FCC][1][111] = 127,
+ [0][1][2][1][RTW89_FCC][2][111] = 127,
+ [0][1][2][1][RTW89_ETSI][1][111] = 127,
+ [0][1][2][1][RTW89_ETSI][0][111] = 127,
+ [0][1][2][1][RTW89_MKK][1][111] = 127,
+ [0][1][2][1][RTW89_MKK][0][111] = 127,
+ [0][1][2][1][RTW89_IC][1][111] = 127,
+ [0][1][2][1][RTW89_KCC][1][111] = 127,
+ [0][1][2][1][RTW89_KCC][0][111] = 127,
+ [0][1][2][1][RTW89_ACMA][1][111] = 127,
+ [0][1][2][1][RTW89_ACMA][0][111] = 127,
+ [0][1][2][1][RTW89_CHILE][1][111] = 127,
+ [0][1][2][1][RTW89_QATAR][1][111] = 127,
+ [0][1][2][1][RTW89_QATAR][0][111] = 127,
+ [0][1][2][1][RTW89_UK][1][111] = 127,
+ [0][1][2][1][RTW89_UK][0][111] = 127,
+ [0][1][2][1][RTW89_FCC][1][113] = 127,
+ [0][1][2][1][RTW89_FCC][2][113] = 127,
+ [0][1][2][1][RTW89_ETSI][1][113] = 127,
+ [0][1][2][1][RTW89_ETSI][0][113] = 127,
+ [0][1][2][1][RTW89_MKK][1][113] = 127,
+ [0][1][2][1][RTW89_MKK][0][113] = 127,
+ [0][1][2][1][RTW89_IC][1][113] = 127,
+ [0][1][2][1][RTW89_KCC][1][113] = 127,
+ [0][1][2][1][RTW89_KCC][0][113] = 127,
+ [0][1][2][1][RTW89_ACMA][1][113] = 127,
+ [0][1][2][1][RTW89_ACMA][0][113] = 127,
+ [0][1][2][1][RTW89_CHILE][1][113] = 127,
+ [0][1][2][1][RTW89_QATAR][1][113] = 127,
+ [0][1][2][1][RTW89_QATAR][0][113] = 127,
+ [0][1][2][1][RTW89_UK][1][113] = 127,
+ [0][1][2][1][RTW89_UK][0][113] = 127,
+ [0][1][2][1][RTW89_FCC][1][115] = 127,
+ [0][1][2][1][RTW89_FCC][2][115] = 127,
+ [0][1][2][1][RTW89_ETSI][1][115] = 127,
+ [0][1][2][1][RTW89_ETSI][0][115] = 127,
+ [0][1][2][1][RTW89_MKK][1][115] = 127,
+ [0][1][2][1][RTW89_MKK][0][115] = 127,
+ [0][1][2][1][RTW89_IC][1][115] = 127,
+ [0][1][2][1][RTW89_KCC][1][115] = 127,
+ [0][1][2][1][RTW89_KCC][0][115] = 127,
+ [0][1][2][1][RTW89_ACMA][1][115] = 127,
+ [0][1][2][1][RTW89_ACMA][0][115] = 127,
+ [0][1][2][1][RTW89_CHILE][1][115] = 127,
+ [0][1][2][1][RTW89_QATAR][1][115] = 127,
+ [0][1][2][1][RTW89_QATAR][0][115] = 127,
+ [0][1][2][1][RTW89_UK][1][115] = 127,
+ [0][1][2][1][RTW89_UK][0][115] = 127,
+ [0][1][2][1][RTW89_FCC][1][117] = 127,
+ [0][1][2][1][RTW89_FCC][2][117] = 127,
+ [0][1][2][1][RTW89_ETSI][1][117] = 127,
+ [0][1][2][1][RTW89_ETSI][0][117] = 127,
+ [0][1][2][1][RTW89_MKK][1][117] = 127,
+ [0][1][2][1][RTW89_MKK][0][117] = 127,
+ [0][1][2][1][RTW89_IC][1][117] = 127,
+ [0][1][2][1][RTW89_KCC][1][117] = 127,
+ [0][1][2][1][RTW89_KCC][0][117] = 127,
+ [0][1][2][1][RTW89_ACMA][1][117] = 127,
+ [0][1][2][1][RTW89_ACMA][0][117] = 127,
+ [0][1][2][1][RTW89_CHILE][1][117] = 127,
+ [0][1][2][1][RTW89_QATAR][1][117] = 127,
+ [0][1][2][1][RTW89_QATAR][0][117] = 127,
+ [0][1][2][1][RTW89_UK][1][117] = 127,
+ [0][1][2][1][RTW89_UK][0][117] = 127,
+ [0][1][2][1][RTW89_FCC][1][119] = 127,
+ [0][1][2][1][RTW89_FCC][2][119] = 127,
+ [0][1][2][1][RTW89_ETSI][1][119] = 127,
+ [0][1][2][1][RTW89_ETSI][0][119] = 127,
+ [0][1][2][1][RTW89_MKK][1][119] = 127,
+ [0][1][2][1][RTW89_MKK][0][119] = 127,
+ [0][1][2][1][RTW89_IC][1][119] = 127,
+ [0][1][2][1][RTW89_KCC][1][119] = 127,
+ [0][1][2][1][RTW89_KCC][0][119] = 127,
+ [0][1][2][1][RTW89_ACMA][1][119] = 127,
+ [0][1][2][1][RTW89_ACMA][0][119] = 127,
+ [0][1][2][1][RTW89_CHILE][1][119] = 127,
+ [0][1][2][1][RTW89_QATAR][1][119] = 127,
+ [0][1][2][1][RTW89_QATAR][0][119] = 127,
+ [0][1][2][1][RTW89_UK][1][119] = 127,
+ [0][1][2][1][RTW89_UK][0][119] = 127,
+ [1][0][2][0][RTW89_FCC][1][1] = 34,
+ [1][0][2][0][RTW89_FCC][2][1] = 70,
+ [1][0][2][0][RTW89_ETSI][1][1] = 66,
+ [1][0][2][0][RTW89_ETSI][0][1] = 30,
+ [1][0][2][0][RTW89_MKK][1][1] = 62,
+ [1][0][2][0][RTW89_MKK][0][1] = 26,
+ [1][0][2][0][RTW89_IC][1][1] = 34,
+ [1][0][2][0][RTW89_KCC][1][1] = 40,
+ [1][0][2][0][RTW89_KCC][0][1] = 24,
+ [1][0][2][0][RTW89_ACMA][1][1] = 66,
+ [1][0][2][0][RTW89_ACMA][0][1] = 30,
+ [1][0][2][0][RTW89_CHILE][1][1] = 34,
+ [1][0][2][0][RTW89_QATAR][1][1] = 66,
+ [1][0][2][0][RTW89_QATAR][0][1] = 30,
+ [1][0][2][0][RTW89_UK][1][1] = 66,
+ [1][0][2][0][RTW89_UK][0][1] = 30,
+ [1][0][2][0][RTW89_FCC][1][5] = 34,
+ [1][0][2][0][RTW89_FCC][2][5] = 70,
+ [1][0][2][0][RTW89_ETSI][1][5] = 66,
+ [1][0][2][0][RTW89_ETSI][0][5] = 30,
+ [1][0][2][0][RTW89_MKK][1][5] = 62,
+ [1][0][2][0][RTW89_MKK][0][5] = 26,
+ [1][0][2][0][RTW89_IC][1][5] = 34,
+ [1][0][2][0][RTW89_KCC][1][5] = 40,
+ [1][0][2][0][RTW89_KCC][0][5] = 24,
+ [1][0][2][0][RTW89_ACMA][1][5] = 66,
+ [1][0][2][0][RTW89_ACMA][0][5] = 30,
+ [1][0][2][0][RTW89_CHILE][1][5] = 34,
+ [1][0][2][0][RTW89_QATAR][1][5] = 66,
+ [1][0][2][0][RTW89_QATAR][0][5] = 30,
+ [1][0][2][0][RTW89_UK][1][5] = 66,
+ [1][0][2][0][RTW89_UK][0][5] = 30,
+ [1][0][2][0][RTW89_FCC][1][9] = 34,
+ [1][0][2][0][RTW89_FCC][2][9] = 70,
+ [1][0][2][0][RTW89_ETSI][1][9] = 66,
+ [1][0][2][0][RTW89_ETSI][0][9] = 30,
+ [1][0][2][0][RTW89_MKK][1][9] = 62,
+ [1][0][2][0][RTW89_MKK][0][9] = 26,
+ [1][0][2][0][RTW89_IC][1][9] = 34,
+ [1][0][2][0][RTW89_KCC][1][9] = 40,
+ [1][0][2][0][RTW89_KCC][0][9] = 24,
+ [1][0][2][0][RTW89_ACMA][1][9] = 66,
+ [1][0][2][0][RTW89_ACMA][0][9] = 30,
+ [1][0][2][0][RTW89_CHILE][1][9] = 34,
+ [1][0][2][0][RTW89_QATAR][1][9] = 66,
+ [1][0][2][0][RTW89_QATAR][0][9] = 30,
+ [1][0][2][0][RTW89_UK][1][9] = 66,
+ [1][0][2][0][RTW89_UK][0][9] = 30,
+ [1][0][2][0][RTW89_FCC][1][13] = 34,
+ [1][0][2][0][RTW89_FCC][2][13] = 70,
+ [1][0][2][0][RTW89_ETSI][1][13] = 66,
+ [1][0][2][0][RTW89_ETSI][0][13] = 30,
+ [1][0][2][0][RTW89_MKK][1][13] = 62,
+ [1][0][2][0][RTW89_MKK][0][13] = 26,
+ [1][0][2][0][RTW89_IC][1][13] = 34,
+ [1][0][2][0][RTW89_KCC][1][13] = 40,
+ [1][0][2][0][RTW89_KCC][0][13] = 24,
+ [1][0][2][0][RTW89_ACMA][1][13] = 66,
+ [1][0][2][0][RTW89_ACMA][0][13] = 30,
+ [1][0][2][0][RTW89_CHILE][1][13] = 34,
+ [1][0][2][0][RTW89_QATAR][1][13] = 66,
+ [1][0][2][0][RTW89_QATAR][0][13] = 30,
+ [1][0][2][0][RTW89_UK][1][13] = 66,
+ [1][0][2][0][RTW89_UK][0][13] = 30,
+ [1][0][2][0][RTW89_FCC][1][16] = 34,
+ [1][0][2][0][RTW89_FCC][2][16] = 70,
+ [1][0][2][0][RTW89_ETSI][1][16] = 66,
+ [1][0][2][0][RTW89_ETSI][0][16] = 30,
+ [1][0][2][0][RTW89_MKK][1][16] = 62,
+ [1][0][2][0][RTW89_MKK][0][16] = 26,
+ [1][0][2][0][RTW89_IC][1][16] = 34,
+ [1][0][2][0][RTW89_KCC][1][16] = 40,
+ [1][0][2][0][RTW89_KCC][0][16] = 24,
+ [1][0][2][0][RTW89_ACMA][1][16] = 66,
+ [1][0][2][0][RTW89_ACMA][0][16] = 30,
+ [1][0][2][0][RTW89_CHILE][1][16] = 34,
+ [1][0][2][0][RTW89_QATAR][1][16] = 66,
+ [1][0][2][0][RTW89_QATAR][0][16] = 30,
+ [1][0][2][0][RTW89_UK][1][16] = 66,
+ [1][0][2][0][RTW89_UK][0][16] = 30,
+ [1][0][2][0][RTW89_FCC][1][20] = 34,
+ [1][0][2][0][RTW89_FCC][2][20] = 70,
+ [1][0][2][0][RTW89_ETSI][1][20] = 66,
+ [1][0][2][0][RTW89_ETSI][0][20] = 30,
+ [1][0][2][0][RTW89_MKK][1][20] = 62,
+ [1][0][2][0][RTW89_MKK][0][20] = 26,
+ [1][0][2][0][RTW89_IC][1][20] = 34,
+ [1][0][2][0][RTW89_KCC][1][20] = 40,
+ [1][0][2][0][RTW89_KCC][0][20] = 24,
+ [1][0][2][0][RTW89_ACMA][1][20] = 66,
+ [1][0][2][0][RTW89_ACMA][0][20] = 30,
+ [1][0][2][0][RTW89_CHILE][1][20] = 34,
+ [1][0][2][0][RTW89_QATAR][1][20] = 66,
+ [1][0][2][0][RTW89_QATAR][0][20] = 30,
+ [1][0][2][0][RTW89_UK][1][20] = 66,
+ [1][0][2][0][RTW89_UK][0][20] = 30,
+ [1][0][2][0][RTW89_FCC][1][24] = 36,
+ [1][0][2][0][RTW89_FCC][2][24] = 70,
+ [1][0][2][0][RTW89_ETSI][1][24] = 66,
+ [1][0][2][0][RTW89_ETSI][0][24] = 30,
+ [1][0][2][0][RTW89_MKK][1][24] = 64,
+ [1][0][2][0][RTW89_MKK][0][24] = 28,
+ [1][0][2][0][RTW89_IC][1][24] = 36,
+ [1][0][2][0][RTW89_KCC][1][24] = 40,
+ [1][0][2][0][RTW89_KCC][0][24] = 26,
+ [1][0][2][0][RTW89_ACMA][1][24] = 66,
+ [1][0][2][0][RTW89_ACMA][0][24] = 30,
+ [1][0][2][0][RTW89_CHILE][1][24] = 36,
+ [1][0][2][0][RTW89_QATAR][1][24] = 66,
+ [1][0][2][0][RTW89_QATAR][0][24] = 30,
+ [1][0][2][0][RTW89_UK][1][24] = 66,
+ [1][0][2][0][RTW89_UK][0][24] = 30,
+ [1][0][2][0][RTW89_FCC][1][28] = 34,
+ [1][0][2][0][RTW89_FCC][2][28] = 70,
+ [1][0][2][0][RTW89_ETSI][1][28] = 66,
+ [1][0][2][0][RTW89_ETSI][0][28] = 30,
+ [1][0][2][0][RTW89_MKK][1][28] = 64,
+ [1][0][2][0][RTW89_MKK][0][28] = 26,
+ [1][0][2][0][RTW89_IC][1][28] = 34,
+ [1][0][2][0][RTW89_KCC][1][28] = 40,
+ [1][0][2][0][RTW89_KCC][0][28] = 26,
+ [1][0][2][0][RTW89_ACMA][1][28] = 66,
+ [1][0][2][0][RTW89_ACMA][0][28] = 30,
+ [1][0][2][0][RTW89_CHILE][1][28] = 34,
+ [1][0][2][0][RTW89_QATAR][1][28] = 66,
+ [1][0][2][0][RTW89_QATAR][0][28] = 30,
+ [1][0][2][0][RTW89_UK][1][28] = 66,
+ [1][0][2][0][RTW89_UK][0][28] = 30,
+ [1][0][2][0][RTW89_FCC][1][31] = 34,
+ [1][0][2][0][RTW89_FCC][2][31] = 70,
+ [1][0][2][0][RTW89_ETSI][1][31] = 66,
+ [1][0][2][0][RTW89_ETSI][0][31] = 30,
+ [1][0][2][0][RTW89_MKK][1][31] = 64,
+ [1][0][2][0][RTW89_MKK][0][31] = 26,
+ [1][0][2][0][RTW89_IC][1][31] = 34,
+ [1][0][2][0][RTW89_KCC][1][31] = 40,
+ [1][0][2][0][RTW89_KCC][0][31] = 26,
+ [1][0][2][0][RTW89_ACMA][1][31] = 66,
+ [1][0][2][0][RTW89_ACMA][0][31] = 30,
+ [1][0][2][0][RTW89_CHILE][1][31] = 34,
+ [1][0][2][0][RTW89_QATAR][1][31] = 66,
+ [1][0][2][0][RTW89_QATAR][0][31] = 30,
+ [1][0][2][0][RTW89_UK][1][31] = 66,
+ [1][0][2][0][RTW89_UK][0][31] = 30,
+ [1][0][2][0][RTW89_FCC][1][35] = 34,
+ [1][0][2][0][RTW89_FCC][2][35] = 70,
+ [1][0][2][0][RTW89_ETSI][1][35] = 66,
+ [1][0][2][0][RTW89_ETSI][0][35] = 30,
+ [1][0][2][0][RTW89_MKK][1][35] = 64,
+ [1][0][2][0][RTW89_MKK][0][35] = 26,
+ [1][0][2][0][RTW89_IC][1][35] = 34,
+ [1][0][2][0][RTW89_KCC][1][35] = 40,
+ [1][0][2][0][RTW89_KCC][0][35] = 26,
+ [1][0][2][0][RTW89_ACMA][1][35] = 66,
+ [1][0][2][0][RTW89_ACMA][0][35] = 30,
+ [1][0][2][0][RTW89_CHILE][1][35] = 34,
+ [1][0][2][0][RTW89_QATAR][1][35] = 66,
+ [1][0][2][0][RTW89_QATAR][0][35] = 30,
+ [1][0][2][0][RTW89_UK][1][35] = 66,
+ [1][0][2][0][RTW89_UK][0][35] = 30,
+ [1][0][2][0][RTW89_FCC][1][39] = 34,
+ [1][0][2][0][RTW89_FCC][2][39] = 70,
+ [1][0][2][0][RTW89_ETSI][1][39] = 66,
+ [1][0][2][0][RTW89_ETSI][0][39] = 30,
+ [1][0][2][0][RTW89_MKK][1][39] = 64,
+ [1][0][2][0][RTW89_MKK][0][39] = 26,
+ [1][0][2][0][RTW89_IC][1][39] = 34,
+ [1][0][2][0][RTW89_KCC][1][39] = 40,
+ [1][0][2][0][RTW89_KCC][0][39] = 26,
+ [1][0][2][0][RTW89_ACMA][1][39] = 66,
+ [1][0][2][0][RTW89_ACMA][0][39] = 30,
+ [1][0][2][0][RTW89_CHILE][1][39] = 34,
+ [1][0][2][0][RTW89_QATAR][1][39] = 66,
+ [1][0][2][0][RTW89_QATAR][0][39] = 30,
+ [1][0][2][0][RTW89_UK][1][39] = 66,
+ [1][0][2][0][RTW89_UK][0][39] = 30,
+ [1][0][2][0][RTW89_FCC][1][43] = 34,
+ [1][0][2][0][RTW89_FCC][2][43] = 70,
+ [1][0][2][0][RTW89_ETSI][1][43] = 66,
+ [1][0][2][0][RTW89_ETSI][0][43] = 30,
+ [1][0][2][0][RTW89_MKK][1][43] = 64,
+ [1][0][2][0][RTW89_MKK][0][43] = 26,
+ [1][0][2][0][RTW89_IC][1][43] = 34,
+ [1][0][2][0][RTW89_KCC][1][43] = 40,
+ [1][0][2][0][RTW89_KCC][0][43] = 26,
+ [1][0][2][0][RTW89_ACMA][1][43] = 66,
+ [1][0][2][0][RTW89_ACMA][0][43] = 30,
+ [1][0][2][0][RTW89_CHILE][1][43] = 34,
+ [1][0][2][0][RTW89_QATAR][1][43] = 66,
+ [1][0][2][0][RTW89_QATAR][0][43] = 30,
+ [1][0][2][0][RTW89_UK][1][43] = 66,
+ [1][0][2][0][RTW89_UK][0][43] = 30,
+ [1][0][2][0][RTW89_FCC][1][46] = 34,
+ [1][0][2][0][RTW89_FCC][2][46] = 127,
+ [1][0][2][0][RTW89_ETSI][1][46] = 127,
+ [1][0][2][0][RTW89_ETSI][0][46] = 127,
+ [1][0][2][0][RTW89_MKK][1][46] = 127,
+ [1][0][2][0][RTW89_MKK][0][46] = 127,
+ [1][0][2][0][RTW89_IC][1][46] = 34,
+ [1][0][2][0][RTW89_KCC][1][46] = 40,
+ [1][0][2][0][RTW89_KCC][0][46] = 127,
+ [1][0][2][0][RTW89_ACMA][1][46] = 127,
+ [1][0][2][0][RTW89_ACMA][0][46] = 127,
+ [1][0][2][0][RTW89_CHILE][1][46] = 34,
+ [1][0][2][0][RTW89_QATAR][1][46] = 127,
+ [1][0][2][0][RTW89_QATAR][0][46] = 127,
+ [1][0][2][0][RTW89_UK][1][46] = 127,
+ [1][0][2][0][RTW89_UK][0][46] = 127,
+ [1][0][2][0][RTW89_FCC][1][50] = 34,
+ [1][0][2][0][RTW89_FCC][2][50] = 127,
+ [1][0][2][0][RTW89_ETSI][1][50] = 127,
+ [1][0][2][0][RTW89_ETSI][0][50] = 127,
+ [1][0][2][0][RTW89_MKK][1][50] = 127,
+ [1][0][2][0][RTW89_MKK][0][50] = 127,
+ [1][0][2][0][RTW89_IC][1][50] = 34,
+ [1][0][2][0][RTW89_KCC][1][50] = 40,
+ [1][0][2][0][RTW89_KCC][0][50] = 127,
+ [1][0][2][0][RTW89_ACMA][1][50] = 127,
+ [1][0][2][0][RTW89_ACMA][0][50] = 127,
+ [1][0][2][0][RTW89_CHILE][1][50] = 34,
+ [1][0][2][0][RTW89_QATAR][1][50] = 127,
+ [1][0][2][0][RTW89_QATAR][0][50] = 127,
+ [1][0][2][0][RTW89_UK][1][50] = 127,
+ [1][0][2][0][RTW89_UK][0][50] = 127,
+ [1][0][2][0][RTW89_FCC][1][54] = 36,
+ [1][0][2][0][RTW89_FCC][2][54] = 127,
+ [1][0][2][0][RTW89_ETSI][1][54] = 127,
+ [1][0][2][0][RTW89_ETSI][0][54] = 127,
+ [1][0][2][0][RTW89_MKK][1][54] = 127,
+ [1][0][2][0][RTW89_MKK][0][54] = 127,
+ [1][0][2][0][RTW89_IC][1][54] = 36,
+ [1][0][2][0][RTW89_KCC][1][54] = 40,
+ [1][0][2][0][RTW89_KCC][0][54] = 127,
+ [1][0][2][0][RTW89_ACMA][1][54] = 127,
+ [1][0][2][0][RTW89_ACMA][0][54] = 127,
+ [1][0][2][0][RTW89_CHILE][1][54] = 36,
+ [1][0][2][0][RTW89_QATAR][1][54] = 127,
+ [1][0][2][0][RTW89_QATAR][0][54] = 127,
+ [1][0][2][0][RTW89_UK][1][54] = 127,
+ [1][0][2][0][RTW89_UK][0][54] = 127,
+ [1][0][2][0][RTW89_FCC][1][58] = 36,
+ [1][0][2][0][RTW89_FCC][2][58] = 66,
+ [1][0][2][0][RTW89_ETSI][1][58] = 127,
+ [1][0][2][0][RTW89_ETSI][0][58] = 127,
+ [1][0][2][0][RTW89_MKK][1][58] = 127,
+ [1][0][2][0][RTW89_MKK][0][58] = 127,
+ [1][0][2][0][RTW89_IC][1][58] = 36,
+ [1][0][2][0][RTW89_KCC][1][58] = 40,
+ [1][0][2][0][RTW89_KCC][0][58] = 127,
+ [1][0][2][0][RTW89_ACMA][1][58] = 127,
+ [1][0][2][0][RTW89_ACMA][0][58] = 127,
+ [1][0][2][0][RTW89_CHILE][1][58] = 36,
+ [1][0][2][0][RTW89_QATAR][1][58] = 127,
+ [1][0][2][0][RTW89_QATAR][0][58] = 127,
+ [1][0][2][0][RTW89_UK][1][58] = 127,
+ [1][0][2][0][RTW89_UK][0][58] = 127,
+ [1][0][2][0][RTW89_FCC][1][61] = 34,
+ [1][0][2][0][RTW89_FCC][2][61] = 66,
+ [1][0][2][0][RTW89_ETSI][1][61] = 127,
+ [1][0][2][0][RTW89_ETSI][0][61] = 127,
+ [1][0][2][0][RTW89_MKK][1][61] = 127,
+ [1][0][2][0][RTW89_MKK][0][61] = 127,
+ [1][0][2][0][RTW89_IC][1][61] = 34,
+ [1][0][2][0][RTW89_KCC][1][61] = 40,
+ [1][0][2][0][RTW89_KCC][0][61] = 127,
+ [1][0][2][0][RTW89_ACMA][1][61] = 127,
+ [1][0][2][0][RTW89_ACMA][0][61] = 127,
+ [1][0][2][0][RTW89_CHILE][1][61] = 34,
+ [1][0][2][0][RTW89_QATAR][1][61] = 127,
+ [1][0][2][0][RTW89_QATAR][0][61] = 127,
+ [1][0][2][0][RTW89_UK][1][61] = 127,
+ [1][0][2][0][RTW89_UK][0][61] = 127,
+ [1][0][2][0][RTW89_FCC][1][65] = 34,
+ [1][0][2][0][RTW89_FCC][2][65] = 66,
+ [1][0][2][0][RTW89_ETSI][1][65] = 127,
+ [1][0][2][0][RTW89_ETSI][0][65] = 127,
+ [1][0][2][0][RTW89_MKK][1][65] = 127,
+ [1][0][2][0][RTW89_MKK][0][65] = 127,
+ [1][0][2][0][RTW89_IC][1][65] = 34,
+ [1][0][2][0][RTW89_KCC][1][65] = 40,
+ [1][0][2][0][RTW89_KCC][0][65] = 127,
+ [1][0][2][0][RTW89_ACMA][1][65] = 127,
+ [1][0][2][0][RTW89_ACMA][0][65] = 127,
+ [1][0][2][0][RTW89_CHILE][1][65] = 34,
+ [1][0][2][0][RTW89_QATAR][1][65] = 127,
+ [1][0][2][0][RTW89_QATAR][0][65] = 127,
+ [1][0][2][0][RTW89_UK][1][65] = 127,
+ [1][0][2][0][RTW89_UK][0][65] = 127,
+ [1][0][2][0][RTW89_FCC][1][69] = 34,
+ [1][0][2][0][RTW89_FCC][2][69] = 66,
+ [1][0][2][0][RTW89_ETSI][1][69] = 127,
+ [1][0][2][0][RTW89_ETSI][0][69] = 127,
+ [1][0][2][0][RTW89_MKK][1][69] = 127,
+ [1][0][2][0][RTW89_MKK][0][69] = 127,
+ [1][0][2][0][RTW89_IC][1][69] = 34,
+ [1][0][2][0][RTW89_KCC][1][69] = 40,
+ [1][0][2][0][RTW89_KCC][0][69] = 127,
+ [1][0][2][0][RTW89_ACMA][1][69] = 127,
+ [1][0][2][0][RTW89_ACMA][0][69] = 127,
+ [1][0][2][0][RTW89_CHILE][1][69] = 34,
+ [1][0][2][0][RTW89_QATAR][1][69] = 127,
+ [1][0][2][0][RTW89_QATAR][0][69] = 127,
+ [1][0][2][0][RTW89_UK][1][69] = 127,
+ [1][0][2][0][RTW89_UK][0][69] = 127,
+ [1][0][2][0][RTW89_FCC][1][73] = 34,
+ [1][0][2][0][RTW89_FCC][2][73] = 66,
+ [1][0][2][0][RTW89_ETSI][1][73] = 127,
+ [1][0][2][0][RTW89_ETSI][0][73] = 127,
+ [1][0][2][0][RTW89_MKK][1][73] = 127,
+ [1][0][2][0][RTW89_MKK][0][73] = 127,
+ [1][0][2][0][RTW89_IC][1][73] = 34,
+ [1][0][2][0][RTW89_KCC][1][73] = 40,
+ [1][0][2][0][RTW89_KCC][0][73] = 127,
+ [1][0][2][0][RTW89_ACMA][1][73] = 127,
+ [1][0][2][0][RTW89_ACMA][0][73] = 127,
+ [1][0][2][0][RTW89_CHILE][1][73] = 34,
+ [1][0][2][0][RTW89_QATAR][1][73] = 127,
+ [1][0][2][0][RTW89_QATAR][0][73] = 127,
+ [1][0][2][0][RTW89_UK][1][73] = 127,
+ [1][0][2][0][RTW89_UK][0][73] = 127,
+ [1][0][2][0][RTW89_FCC][1][76] = 34,
+ [1][0][2][0][RTW89_FCC][2][76] = 66,
+ [1][0][2][0][RTW89_ETSI][1][76] = 127,
+ [1][0][2][0][RTW89_ETSI][0][76] = 127,
+ [1][0][2][0][RTW89_MKK][1][76] = 127,
+ [1][0][2][0][RTW89_MKK][0][76] = 127,
+ [1][0][2][0][RTW89_IC][1][76] = 34,
+ [1][0][2][0][RTW89_KCC][1][76] = 40,
+ [1][0][2][0][RTW89_KCC][0][76] = 127,
+ [1][0][2][0][RTW89_ACMA][1][76] = 127,
+ [1][0][2][0][RTW89_ACMA][0][76] = 127,
+ [1][0][2][0][RTW89_CHILE][1][76] = 34,
+ [1][0][2][0][RTW89_QATAR][1][76] = 127,
+ [1][0][2][0][RTW89_QATAR][0][76] = 127,
+ [1][0][2][0][RTW89_UK][1][76] = 127,
+ [1][0][2][0][RTW89_UK][0][76] = 127,
+ [1][0][2][0][RTW89_FCC][1][80] = 34,
+ [1][0][2][0][RTW89_FCC][2][80] = 66,
+ [1][0][2][0][RTW89_ETSI][1][80] = 127,
+ [1][0][2][0][RTW89_ETSI][0][80] = 127,
+ [1][0][2][0][RTW89_MKK][1][80] = 127,
+ [1][0][2][0][RTW89_MKK][0][80] = 127,
+ [1][0][2][0][RTW89_IC][1][80] = 34,
+ [1][0][2][0][RTW89_KCC][1][80] = 42,
+ [1][0][2][0][RTW89_KCC][0][80] = 127,
+ [1][0][2][0][RTW89_ACMA][1][80] = 127,
+ [1][0][2][0][RTW89_ACMA][0][80] = 127,
+ [1][0][2][0][RTW89_CHILE][1][80] = 34,
+ [1][0][2][0][RTW89_QATAR][1][80] = 127,
+ [1][0][2][0][RTW89_QATAR][0][80] = 127,
+ [1][0][2][0][RTW89_UK][1][80] = 127,
+ [1][0][2][0][RTW89_UK][0][80] = 127,
+ [1][0][2][0][RTW89_FCC][1][84] = 34,
+ [1][0][2][0][RTW89_FCC][2][84] = 66,
+ [1][0][2][0][RTW89_ETSI][1][84] = 127,
+ [1][0][2][0][RTW89_ETSI][0][84] = 127,
+ [1][0][2][0][RTW89_MKK][1][84] = 127,
+ [1][0][2][0][RTW89_MKK][0][84] = 127,
+ [1][0][2][0][RTW89_IC][1][84] = 34,
+ [1][0][2][0][RTW89_KCC][1][84] = 42,
+ [1][0][2][0][RTW89_KCC][0][84] = 127,
+ [1][0][2][0][RTW89_ACMA][1][84] = 127,
+ [1][0][2][0][RTW89_ACMA][0][84] = 127,
+ [1][0][2][0][RTW89_CHILE][1][84] = 34,
+ [1][0][2][0][RTW89_QATAR][1][84] = 127,
+ [1][0][2][0][RTW89_QATAR][0][84] = 127,
+ [1][0][2][0][RTW89_UK][1][84] = 127,
+ [1][0][2][0][RTW89_UK][0][84] = 127,
+ [1][0][2][0][RTW89_FCC][1][88] = 34,
+ [1][0][2][0][RTW89_FCC][2][88] = 127,
+ [1][0][2][0][RTW89_ETSI][1][88] = 127,
+ [1][0][2][0][RTW89_ETSI][0][88] = 127,
+ [1][0][2][0][RTW89_MKK][1][88] = 127,
+ [1][0][2][0][RTW89_MKK][0][88] = 127,
+ [1][0][2][0][RTW89_IC][1][88] = 34,
+ [1][0][2][0][RTW89_KCC][1][88] = 42,
+ [1][0][2][0][RTW89_KCC][0][88] = 127,
+ [1][0][2][0][RTW89_ACMA][1][88] = 127,
+ [1][0][2][0][RTW89_ACMA][0][88] = 127,
+ [1][0][2][0][RTW89_CHILE][1][88] = 34,
+ [1][0][2][0][RTW89_QATAR][1][88] = 127,
+ [1][0][2][0][RTW89_QATAR][0][88] = 127,
+ [1][0][2][0][RTW89_UK][1][88] = 127,
+ [1][0][2][0][RTW89_UK][0][88] = 127,
+ [1][0][2][0][RTW89_FCC][1][91] = 36,
+ [1][0][2][0][RTW89_FCC][2][91] = 127,
+ [1][0][2][0][RTW89_ETSI][1][91] = 127,
+ [1][0][2][0][RTW89_ETSI][0][91] = 127,
+ [1][0][2][0][RTW89_MKK][1][91] = 127,
+ [1][0][2][0][RTW89_MKK][0][91] = 127,
+ [1][0][2][0][RTW89_IC][1][91] = 36,
+ [1][0][2][0][RTW89_KCC][1][91] = 42,
+ [1][0][2][0][RTW89_KCC][0][91] = 127,
+ [1][0][2][0][RTW89_ACMA][1][91] = 127,
+ [1][0][2][0][RTW89_ACMA][0][91] = 127,
+ [1][0][2][0][RTW89_CHILE][1][91] = 36,
+ [1][0][2][0][RTW89_QATAR][1][91] = 127,
+ [1][0][2][0][RTW89_QATAR][0][91] = 127,
+ [1][0][2][0][RTW89_UK][1][91] = 127,
+ [1][0][2][0][RTW89_UK][0][91] = 127,
+ [1][0][2][0][RTW89_FCC][1][95] = 34,
+ [1][0][2][0][RTW89_FCC][2][95] = 127,
+ [1][0][2][0][RTW89_ETSI][1][95] = 127,
+ [1][0][2][0][RTW89_ETSI][0][95] = 127,
+ [1][0][2][0][RTW89_MKK][1][95] = 127,
+ [1][0][2][0][RTW89_MKK][0][95] = 127,
+ [1][0][2][0][RTW89_IC][1][95] = 34,
+ [1][0][2][0][RTW89_KCC][1][95] = 42,
+ [1][0][2][0][RTW89_KCC][0][95] = 127,
+ [1][0][2][0][RTW89_ACMA][1][95] = 127,
+ [1][0][2][0][RTW89_ACMA][0][95] = 127,
+ [1][0][2][0][RTW89_CHILE][1][95] = 34,
+ [1][0][2][0][RTW89_QATAR][1][95] = 127,
+ [1][0][2][0][RTW89_QATAR][0][95] = 127,
+ [1][0][2][0][RTW89_UK][1][95] = 127,
+ [1][0][2][0][RTW89_UK][0][95] = 127,
+ [1][0][2][0][RTW89_FCC][1][99] = 34,
+ [1][0][2][0][RTW89_FCC][2][99] = 127,
+ [1][0][2][0][RTW89_ETSI][1][99] = 127,
+ [1][0][2][0][RTW89_ETSI][0][99] = 127,
+ [1][0][2][0][RTW89_MKK][1][99] = 127,
+ [1][0][2][0][RTW89_MKK][0][99] = 127,
+ [1][0][2][0][RTW89_IC][1][99] = 34,
+ [1][0][2][0][RTW89_KCC][1][99] = 42,
+ [1][0][2][0][RTW89_KCC][0][99] = 127,
+ [1][0][2][0][RTW89_ACMA][1][99] = 127,
+ [1][0][2][0][RTW89_ACMA][0][99] = 127,
+ [1][0][2][0][RTW89_CHILE][1][99] = 34,
+ [1][0][2][0][RTW89_QATAR][1][99] = 127,
+ [1][0][2][0][RTW89_QATAR][0][99] = 127,
+ [1][0][2][0][RTW89_UK][1][99] = 127,
+ [1][0][2][0][RTW89_UK][0][99] = 127,
+ [1][0][2][0][RTW89_FCC][1][103] = 34,
+ [1][0][2][0][RTW89_FCC][2][103] = 127,
+ [1][0][2][0][RTW89_ETSI][1][103] = 127,
+ [1][0][2][0][RTW89_ETSI][0][103] = 127,
+ [1][0][2][0][RTW89_MKK][1][103] = 127,
+ [1][0][2][0][RTW89_MKK][0][103] = 127,
+ [1][0][2][0][RTW89_IC][1][103] = 34,
+ [1][0][2][0][RTW89_KCC][1][103] = 42,
+ [1][0][2][0][RTW89_KCC][0][103] = 127,
+ [1][0][2][0][RTW89_ACMA][1][103] = 127,
+ [1][0][2][0][RTW89_ACMA][0][103] = 127,
+ [1][0][2][0][RTW89_CHILE][1][103] = 34,
+ [1][0][2][0][RTW89_QATAR][1][103] = 127,
+ [1][0][2][0][RTW89_QATAR][0][103] = 127,
+ [1][0][2][0][RTW89_UK][1][103] = 127,
+ [1][0][2][0][RTW89_UK][0][103] = 127,
+ [1][0][2][0][RTW89_FCC][1][106] = 36,
+ [1][0][2][0][RTW89_FCC][2][106] = 127,
+ [1][0][2][0][RTW89_ETSI][1][106] = 127,
+ [1][0][2][0][RTW89_ETSI][0][106] = 127,
+ [1][0][2][0][RTW89_MKK][1][106] = 127,
+ [1][0][2][0][RTW89_MKK][0][106] = 127,
+ [1][0][2][0][RTW89_IC][1][106] = 36,
+ [1][0][2][0][RTW89_KCC][1][106] = 42,
+ [1][0][2][0][RTW89_KCC][0][106] = 127,
+ [1][0][2][0][RTW89_ACMA][1][106] = 127,
+ [1][0][2][0][RTW89_ACMA][0][106] = 127,
+ [1][0][2][0][RTW89_CHILE][1][106] = 36,
+ [1][0][2][0][RTW89_QATAR][1][106] = 127,
+ [1][0][2][0][RTW89_QATAR][0][106] = 127,
+ [1][0][2][0][RTW89_UK][1][106] = 127,
+ [1][0][2][0][RTW89_UK][0][106] = 127,
+ [1][0][2][0][RTW89_FCC][1][110] = 127,
+ [1][0][2][0][RTW89_FCC][2][110] = 127,
+ [1][0][2][0][RTW89_ETSI][1][110] = 127,
+ [1][0][2][0][RTW89_ETSI][0][110] = 127,
+ [1][0][2][0][RTW89_MKK][1][110] = 127,
+ [1][0][2][0][RTW89_MKK][0][110] = 127,
+ [1][0][2][0][RTW89_IC][1][110] = 127,
+ [1][0][2][0][RTW89_KCC][1][110] = 127,
+ [1][0][2][0][RTW89_KCC][0][110] = 127,
+ [1][0][2][0][RTW89_ACMA][1][110] = 127,
+ [1][0][2][0][RTW89_ACMA][0][110] = 127,
+ [1][0][2][0][RTW89_CHILE][1][110] = 127,
+ [1][0][2][0][RTW89_QATAR][1][110] = 127,
+ [1][0][2][0][RTW89_QATAR][0][110] = 127,
+ [1][0][2][0][RTW89_UK][1][110] = 127,
+ [1][0][2][0][RTW89_UK][0][110] = 127,
+ [1][0][2][0][RTW89_FCC][1][114] = 127,
+ [1][0][2][0][RTW89_FCC][2][114] = 127,
+ [1][0][2][0][RTW89_ETSI][1][114] = 127,
+ [1][0][2][0][RTW89_ETSI][0][114] = 127,
+ [1][0][2][0][RTW89_MKK][1][114] = 127,
+ [1][0][2][0][RTW89_MKK][0][114] = 127,
+ [1][0][2][0][RTW89_IC][1][114] = 127,
+ [1][0][2][0][RTW89_KCC][1][114] = 127,
+ [1][0][2][0][RTW89_KCC][0][114] = 127,
+ [1][0][2][0][RTW89_ACMA][1][114] = 127,
+ [1][0][2][0][RTW89_ACMA][0][114] = 127,
+ [1][0][2][0][RTW89_CHILE][1][114] = 127,
+ [1][0][2][0][RTW89_QATAR][1][114] = 127,
+ [1][0][2][0][RTW89_QATAR][0][114] = 127,
+ [1][0][2][0][RTW89_UK][1][114] = 127,
+ [1][0][2][0][RTW89_UK][0][114] = 127,
+ [1][0][2][0][RTW89_FCC][1][118] = 127,
+ [1][0][2][0][RTW89_FCC][2][118] = 127,
+ [1][0][2][0][RTW89_ETSI][1][118] = 127,
+ [1][0][2][0][RTW89_ETSI][0][118] = 127,
+ [1][0][2][0][RTW89_MKK][1][118] = 127,
+ [1][0][2][0][RTW89_MKK][0][118] = 127,
+ [1][0][2][0][RTW89_IC][1][118] = 127,
+ [1][0][2][0][RTW89_KCC][1][118] = 127,
+ [1][0][2][0][RTW89_KCC][0][118] = 127,
+ [1][0][2][0][RTW89_ACMA][1][118] = 127,
+ [1][0][2][0][RTW89_ACMA][0][118] = 127,
+ [1][0][2][0][RTW89_CHILE][1][118] = 127,
+ [1][0][2][0][RTW89_QATAR][1][118] = 127,
+ [1][0][2][0][RTW89_QATAR][0][118] = 127,
+ [1][0][2][0][RTW89_UK][1][118] = 127,
+ [1][0][2][0][RTW89_UK][0][118] = 127,
+ [1][1][2][0][RTW89_FCC][1][1] = 10,
+ [1][1][2][0][RTW89_FCC][2][1] = 58,
+ [1][1][2][0][RTW89_ETSI][1][1] = 54,
+ [1][1][2][0][RTW89_ETSI][0][1] = 18,
+ [1][1][2][0][RTW89_MKK][1][1] = 52,
+ [1][1][2][0][RTW89_MKK][0][1] = 12,
+ [1][1][2][0][RTW89_IC][1][1] = 10,
+ [1][1][2][0][RTW89_KCC][1][1] = 28,
+ [1][1][2][0][RTW89_KCC][0][1] = 12,
+ [1][1][2][0][RTW89_ACMA][1][1] = 54,
+ [1][1][2][0][RTW89_ACMA][0][1] = 18,
+ [1][1][2][0][RTW89_CHILE][1][1] = 10,
+ [1][1][2][0][RTW89_QATAR][1][1] = 54,
+ [1][1][2][0][RTW89_QATAR][0][1] = 18,
+ [1][1][2][0][RTW89_UK][1][1] = 54,
+ [1][1][2][0][RTW89_UK][0][1] = 18,
+ [1][1][2][0][RTW89_FCC][1][5] = 10,
+ [1][1][2][0][RTW89_FCC][2][5] = 58,
+ [1][1][2][0][RTW89_ETSI][1][5] = 54,
+ [1][1][2][0][RTW89_ETSI][0][5] = 16,
+ [1][1][2][0][RTW89_MKK][1][5] = 52,
+ [1][1][2][0][RTW89_MKK][0][5] = 12,
+ [1][1][2][0][RTW89_IC][1][5] = 10,
+ [1][1][2][0][RTW89_KCC][1][5] = 28,
+ [1][1][2][0][RTW89_KCC][0][5] = 12,
+ [1][1][2][0][RTW89_ACMA][1][5] = 54,
+ [1][1][2][0][RTW89_ACMA][0][5] = 16,
+ [1][1][2][0][RTW89_CHILE][1][5] = 10,
+ [1][1][2][0][RTW89_QATAR][1][5] = 54,
+ [1][1][2][0][RTW89_QATAR][0][5] = 16,
+ [1][1][2][0][RTW89_UK][1][5] = 54,
+ [1][1][2][0][RTW89_UK][0][5] = 16,
+ [1][1][2][0][RTW89_FCC][1][9] = 10,
+ [1][1][2][0][RTW89_FCC][2][9] = 58,
+ [1][1][2][0][RTW89_ETSI][1][9] = 54,
+ [1][1][2][0][RTW89_ETSI][0][9] = 16,
+ [1][1][2][0][RTW89_MKK][1][9] = 52,
+ [1][1][2][0][RTW89_MKK][0][9] = 12,
+ [1][1][2][0][RTW89_IC][1][9] = 10,
+ [1][1][2][0][RTW89_KCC][1][9] = 28,
+ [1][1][2][0][RTW89_KCC][0][9] = 12,
+ [1][1][2][0][RTW89_ACMA][1][9] = 54,
+ [1][1][2][0][RTW89_ACMA][0][9] = 16,
+ [1][1][2][0][RTW89_CHILE][1][9] = 10,
+ [1][1][2][0][RTW89_QATAR][1][9] = 54,
+ [1][1][2][0][RTW89_QATAR][0][9] = 16,
+ [1][1][2][0][RTW89_UK][1][9] = 54,
+ [1][1][2][0][RTW89_UK][0][9] = 16,
+ [1][1][2][0][RTW89_FCC][1][13] = 10,
+ [1][1][2][0][RTW89_FCC][2][13] = 58,
+ [1][1][2][0][RTW89_ETSI][1][13] = 54,
+ [1][1][2][0][RTW89_ETSI][0][13] = 16,
+ [1][1][2][0][RTW89_MKK][1][13] = 52,
+ [1][1][2][0][RTW89_MKK][0][13] = 12,
+ [1][1][2][0][RTW89_IC][1][13] = 10,
+ [1][1][2][0][RTW89_KCC][1][13] = 28,
+ [1][1][2][0][RTW89_KCC][0][13] = 12,
+ [1][1][2][0][RTW89_ACMA][1][13] = 54,
+ [1][1][2][0][RTW89_ACMA][0][13] = 16,
+ [1][1][2][0][RTW89_CHILE][1][13] = 10,
+ [1][1][2][0][RTW89_QATAR][1][13] = 54,
+ [1][1][2][0][RTW89_QATAR][0][13] = 16,
+ [1][1][2][0][RTW89_UK][1][13] = 54,
+ [1][1][2][0][RTW89_UK][0][13] = 16,
+ [1][1][2][0][RTW89_FCC][1][16] = 10,
+ [1][1][2][0][RTW89_FCC][2][16] = 58,
+ [1][1][2][0][RTW89_ETSI][1][16] = 54,
+ [1][1][2][0][RTW89_ETSI][0][16] = 16,
+ [1][1][2][0][RTW89_MKK][1][16] = 52,
+ [1][1][2][0][RTW89_MKK][0][16] = 12,
+ [1][1][2][0][RTW89_IC][1][16] = 10,
+ [1][1][2][0][RTW89_KCC][1][16] = 28,
+ [1][1][2][0][RTW89_KCC][0][16] = 12,
+ [1][1][2][0][RTW89_ACMA][1][16] = 54,
+ [1][1][2][0][RTW89_ACMA][0][16] = 16,
+ [1][1][2][0][RTW89_CHILE][1][16] = 10,
+ [1][1][2][0][RTW89_QATAR][1][16] = 54,
+ [1][1][2][0][RTW89_QATAR][0][16] = 16,
+ [1][1][2][0][RTW89_UK][1][16] = 54,
+ [1][1][2][0][RTW89_UK][0][16] = 16,
+ [1][1][2][0][RTW89_FCC][1][20] = 10,
+ [1][1][2][0][RTW89_FCC][2][20] = 58,
+ [1][1][2][0][RTW89_ETSI][1][20] = 54,
+ [1][1][2][0][RTW89_ETSI][0][20] = 16,
+ [1][1][2][0][RTW89_MKK][1][20] = 52,
+ [1][1][2][0][RTW89_MKK][0][20] = 12,
+ [1][1][2][0][RTW89_IC][1][20] = 10,
+ [1][1][2][0][RTW89_KCC][1][20] = 28,
+ [1][1][2][0][RTW89_KCC][0][20] = 12,
+ [1][1][2][0][RTW89_ACMA][1][20] = 54,
+ [1][1][2][0][RTW89_ACMA][0][20] = 16,
+ [1][1][2][0][RTW89_CHILE][1][20] = 10,
+ [1][1][2][0][RTW89_QATAR][1][20] = 54,
+ [1][1][2][0][RTW89_QATAR][0][20] = 16,
+ [1][1][2][0][RTW89_UK][1][20] = 54,
+ [1][1][2][0][RTW89_UK][0][20] = 16,
+ [1][1][2][0][RTW89_FCC][1][24] = 10,
+ [1][1][2][0][RTW89_FCC][2][24] = 70,
+ [1][1][2][0][RTW89_ETSI][1][24] = 54,
+ [1][1][2][0][RTW89_ETSI][0][24] = 16,
+ [1][1][2][0][RTW89_MKK][1][24] = 54,
+ [1][1][2][0][RTW89_MKK][0][24] = 14,
+ [1][1][2][0][RTW89_IC][1][24] = 10,
+ [1][1][2][0][RTW89_KCC][1][24] = 28,
+ [1][1][2][0][RTW89_KCC][0][24] = 12,
+ [1][1][2][0][RTW89_ACMA][1][24] = 54,
+ [1][1][2][0][RTW89_ACMA][0][24] = 16,
+ [1][1][2][0][RTW89_CHILE][1][24] = 10,
+ [1][1][2][0][RTW89_QATAR][1][24] = 54,
+ [1][1][2][0][RTW89_QATAR][0][24] = 16,
+ [1][1][2][0][RTW89_UK][1][24] = 54,
+ [1][1][2][0][RTW89_UK][0][24] = 16,
+ [1][1][2][0][RTW89_FCC][1][28] = 10,
+ [1][1][2][0][RTW89_FCC][2][28] = 70,
+ [1][1][2][0][RTW89_ETSI][1][28] = 54,
+ [1][1][2][0][RTW89_ETSI][0][28] = 16,
+ [1][1][2][0][RTW89_MKK][1][28] = 52,
+ [1][1][2][0][RTW89_MKK][0][28] = 14,
+ [1][1][2][0][RTW89_IC][1][28] = 10,
+ [1][1][2][0][RTW89_KCC][1][28] = 28,
+ [1][1][2][0][RTW89_KCC][0][28] = 14,
+ [1][1][2][0][RTW89_ACMA][1][28] = 54,
+ [1][1][2][0][RTW89_ACMA][0][28] = 16,
+ [1][1][2][0][RTW89_CHILE][1][28] = 10,
+ [1][1][2][0][RTW89_QATAR][1][28] = 54,
+ [1][1][2][0][RTW89_QATAR][0][28] = 16,
+ [1][1][2][0][RTW89_UK][1][28] = 54,
+ [1][1][2][0][RTW89_UK][0][28] = 16,
+ [1][1][2][0][RTW89_FCC][1][31] = 10,
+ [1][1][2][0][RTW89_FCC][2][31] = 70,
+ [1][1][2][0][RTW89_ETSI][1][31] = 54,
+ [1][1][2][0][RTW89_ETSI][0][31] = 16,
+ [1][1][2][0][RTW89_MKK][1][31] = 52,
+ [1][1][2][0][RTW89_MKK][0][31] = 14,
+ [1][1][2][0][RTW89_IC][1][31] = 10,
+ [1][1][2][0][RTW89_KCC][1][31] = 28,
+ [1][1][2][0][RTW89_KCC][0][31] = 14,
+ [1][1][2][0][RTW89_ACMA][1][31] = 54,
+ [1][1][2][0][RTW89_ACMA][0][31] = 16,
+ [1][1][2][0][RTW89_CHILE][1][31] = 10,
+ [1][1][2][0][RTW89_QATAR][1][31] = 54,
+ [1][1][2][0][RTW89_QATAR][0][31] = 16,
+ [1][1][2][0][RTW89_UK][1][31] = 54,
+ [1][1][2][0][RTW89_UK][0][31] = 16,
+ [1][1][2][0][RTW89_FCC][1][35] = 10,
+ [1][1][2][0][RTW89_FCC][2][35] = 70,
+ [1][1][2][0][RTW89_ETSI][1][35] = 54,
+ [1][1][2][0][RTW89_ETSI][0][35] = 16,
+ [1][1][2][0][RTW89_MKK][1][35] = 52,
+ [1][1][2][0][RTW89_MKK][0][35] = 14,
+ [1][1][2][0][RTW89_IC][1][35] = 10,
+ [1][1][2][0][RTW89_KCC][1][35] = 28,
+ [1][1][2][0][RTW89_KCC][0][35] = 14,
+ [1][1][2][0][RTW89_ACMA][1][35] = 54,
+ [1][1][2][0][RTW89_ACMA][0][35] = 16,
+ [1][1][2][0][RTW89_CHILE][1][35] = 10,
+ [1][1][2][0][RTW89_QATAR][1][35] = 54,
+ [1][1][2][0][RTW89_QATAR][0][35] = 16,
+ [1][1][2][0][RTW89_UK][1][35] = 54,
+ [1][1][2][0][RTW89_UK][0][35] = 16,
+ [1][1][2][0][RTW89_FCC][1][39] = 10,
+ [1][1][2][0][RTW89_FCC][2][39] = 70,
+ [1][1][2][0][RTW89_ETSI][1][39] = 54,
+ [1][1][2][0][RTW89_ETSI][0][39] = 16,
+ [1][1][2][0][RTW89_MKK][1][39] = 52,
+ [1][1][2][0][RTW89_MKK][0][39] = 14,
+ [1][1][2][0][RTW89_IC][1][39] = 10,
+ [1][1][2][0][RTW89_KCC][1][39] = 28,
+ [1][1][2][0][RTW89_KCC][0][39] = 14,
+ [1][1][2][0][RTW89_ACMA][1][39] = 54,
+ [1][1][2][0][RTW89_ACMA][0][39] = 16,
+ [1][1][2][0][RTW89_CHILE][1][39] = 10,
+ [1][1][2][0][RTW89_QATAR][1][39] = 54,
+ [1][1][2][0][RTW89_QATAR][0][39] = 16,
+ [1][1][2][0][RTW89_UK][1][39] = 54,
+ [1][1][2][0][RTW89_UK][0][39] = 16,
+ [1][1][2][0][RTW89_FCC][1][43] = 10,
+ [1][1][2][0][RTW89_FCC][2][43] = 70,
+ [1][1][2][0][RTW89_ETSI][1][43] = 54,
+ [1][1][2][0][RTW89_ETSI][0][43] = 16,
+ [1][1][2][0][RTW89_MKK][1][43] = 52,
+ [1][1][2][0][RTW89_MKK][0][43] = 14,
+ [1][1][2][0][RTW89_IC][1][43] = 10,
+ [1][1][2][0][RTW89_KCC][1][43] = 28,
+ [1][1][2][0][RTW89_KCC][0][43] = 14,
+ [1][1][2][0][RTW89_ACMA][1][43] = 54,
+ [1][1][2][0][RTW89_ACMA][0][43] = 16,
+ [1][1][2][0][RTW89_CHILE][1][43] = 10,
+ [1][1][2][0][RTW89_QATAR][1][43] = 54,
+ [1][1][2][0][RTW89_QATAR][0][43] = 16,
+ [1][1][2][0][RTW89_UK][1][43] = 54,
+ [1][1][2][0][RTW89_UK][0][43] = 16,
+ [1][1][2][0][RTW89_FCC][1][46] = 12,
+ [1][1][2][0][RTW89_FCC][2][46] = 127,
+ [1][1][2][0][RTW89_ETSI][1][46] = 127,
+ [1][1][2][0][RTW89_ETSI][0][46] = 127,
+ [1][1][2][0][RTW89_MKK][1][46] = 127,
+ [1][1][2][0][RTW89_MKK][0][46] = 127,
+ [1][1][2][0][RTW89_IC][1][46] = 12,
+ [1][1][2][0][RTW89_KCC][1][46] = 28,
+ [1][1][2][0][RTW89_KCC][0][46] = 127,
+ [1][1][2][0][RTW89_ACMA][1][46] = 127,
+ [1][1][2][0][RTW89_ACMA][0][46] = 127,
+ [1][1][2][0][RTW89_CHILE][1][46] = 12,
+ [1][1][2][0][RTW89_QATAR][1][46] = 127,
+ [1][1][2][0][RTW89_QATAR][0][46] = 127,
+ [1][1][2][0][RTW89_UK][1][46] = 127,
+ [1][1][2][0][RTW89_UK][0][46] = 127,
+ [1][1][2][0][RTW89_FCC][1][50] = 12,
+ [1][1][2][0][RTW89_FCC][2][50] = 127,
+ [1][1][2][0][RTW89_ETSI][1][50] = 127,
+ [1][1][2][0][RTW89_ETSI][0][50] = 127,
+ [1][1][2][0][RTW89_MKK][1][50] = 127,
+ [1][1][2][0][RTW89_MKK][0][50] = 127,
+ [1][1][2][0][RTW89_IC][1][50] = 12,
+ [1][1][2][0][RTW89_KCC][1][50] = 28,
+ [1][1][2][0][RTW89_KCC][0][50] = 127,
+ [1][1][2][0][RTW89_ACMA][1][50] = 127,
+ [1][1][2][0][RTW89_ACMA][0][50] = 127,
+ [1][1][2][0][RTW89_CHILE][1][50] = 12,
+ [1][1][2][0][RTW89_QATAR][1][50] = 127,
+ [1][1][2][0][RTW89_QATAR][0][50] = 127,
+ [1][1][2][0][RTW89_UK][1][50] = 127,
+ [1][1][2][0][RTW89_UK][0][50] = 127,
+ [1][1][2][0][RTW89_FCC][1][54] = 10,
+ [1][1][2][0][RTW89_FCC][2][54] = 127,
+ [1][1][2][0][RTW89_ETSI][1][54] = 127,
+ [1][1][2][0][RTW89_ETSI][0][54] = 127,
+ [1][1][2][0][RTW89_MKK][1][54] = 127,
+ [1][1][2][0][RTW89_MKK][0][54] = 127,
+ [1][1][2][0][RTW89_IC][1][54] = 10,
+ [1][1][2][0][RTW89_KCC][1][54] = 28,
+ [1][1][2][0][RTW89_KCC][0][54] = 127,
+ [1][1][2][0][RTW89_ACMA][1][54] = 127,
+ [1][1][2][0][RTW89_ACMA][0][54] = 127,
+ [1][1][2][0][RTW89_CHILE][1][54] = 10,
+ [1][1][2][0][RTW89_QATAR][1][54] = 127,
+ [1][1][2][0][RTW89_QATAR][0][54] = 127,
+ [1][1][2][0][RTW89_UK][1][54] = 127,
+ [1][1][2][0][RTW89_UK][0][54] = 127,
+ [1][1][2][0][RTW89_FCC][1][58] = 10,
+ [1][1][2][0][RTW89_FCC][2][58] = 66,
+ [1][1][2][0][RTW89_ETSI][1][58] = 127,
+ [1][1][2][0][RTW89_ETSI][0][58] = 127,
+ [1][1][2][0][RTW89_MKK][1][58] = 127,
+ [1][1][2][0][RTW89_MKK][0][58] = 127,
+ [1][1][2][0][RTW89_IC][1][58] = 10,
+ [1][1][2][0][RTW89_KCC][1][58] = 28,
+ [1][1][2][0][RTW89_KCC][0][58] = 127,
+ [1][1][2][0][RTW89_ACMA][1][58] = 127,
+ [1][1][2][0][RTW89_ACMA][0][58] = 127,
+ [1][1][2][0][RTW89_CHILE][1][58] = 10,
+ [1][1][2][0][RTW89_QATAR][1][58] = 127,
+ [1][1][2][0][RTW89_QATAR][0][58] = 127,
+ [1][1][2][0][RTW89_UK][1][58] = 127,
+ [1][1][2][0][RTW89_UK][0][58] = 127,
+ [1][1][2][0][RTW89_FCC][1][61] = 10,
+ [1][1][2][0][RTW89_FCC][2][61] = 66,
+ [1][1][2][0][RTW89_ETSI][1][61] = 127,
+ [1][1][2][0][RTW89_ETSI][0][61] = 127,
+ [1][1][2][0][RTW89_MKK][1][61] = 127,
+ [1][1][2][0][RTW89_MKK][0][61] = 127,
+ [1][1][2][0][RTW89_IC][1][61] = 10,
+ [1][1][2][0][RTW89_KCC][1][61] = 28,
+ [1][1][2][0][RTW89_KCC][0][61] = 127,
+ [1][1][2][0][RTW89_ACMA][1][61] = 127,
+ [1][1][2][0][RTW89_ACMA][0][61] = 127,
+ [1][1][2][0][RTW89_CHILE][1][61] = 10,
+ [1][1][2][0][RTW89_QATAR][1][61] = 127,
+ [1][1][2][0][RTW89_QATAR][0][61] = 127,
+ [1][1][2][0][RTW89_UK][1][61] = 127,
+ [1][1][2][0][RTW89_UK][0][61] = 127,
+ [1][1][2][0][RTW89_FCC][1][65] = 10,
+ [1][1][2][0][RTW89_FCC][2][65] = 66,
+ [1][1][2][0][RTW89_ETSI][1][65] = 127,
+ [1][1][2][0][RTW89_ETSI][0][65] = 127,
+ [1][1][2][0][RTW89_MKK][1][65] = 127,
+ [1][1][2][0][RTW89_MKK][0][65] = 127,
+ [1][1][2][0][RTW89_IC][1][65] = 10,
+ [1][1][2][0][RTW89_KCC][1][65] = 28,
+ [1][1][2][0][RTW89_KCC][0][65] = 127,
+ [1][1][2][0][RTW89_ACMA][1][65] = 127,
+ [1][1][2][0][RTW89_ACMA][0][65] = 127,
+ [1][1][2][0][RTW89_CHILE][1][65] = 10,
+ [1][1][2][0][RTW89_QATAR][1][65] = 127,
+ [1][1][2][0][RTW89_QATAR][0][65] = 127,
+ [1][1][2][0][RTW89_UK][1][65] = 127,
+ [1][1][2][0][RTW89_UK][0][65] = 127,
+ [1][1][2][0][RTW89_FCC][1][69] = 10,
+ [1][1][2][0][RTW89_FCC][2][69] = 66,
+ [1][1][2][0][RTW89_ETSI][1][69] = 127,
+ [1][1][2][0][RTW89_ETSI][0][69] = 127,
+ [1][1][2][0][RTW89_MKK][1][69] = 127,
+ [1][1][2][0][RTW89_MKK][0][69] = 127,
+ [1][1][2][0][RTW89_IC][1][69] = 10,
+ [1][1][2][0][RTW89_KCC][1][69] = 28,
+ [1][1][2][0][RTW89_KCC][0][69] = 127,
+ [1][1][2][0][RTW89_ACMA][1][69] = 127,
+ [1][1][2][0][RTW89_ACMA][0][69] = 127,
+ [1][1][2][0][RTW89_CHILE][1][69] = 10,
+ [1][1][2][0][RTW89_QATAR][1][69] = 127,
+ [1][1][2][0][RTW89_QATAR][0][69] = 127,
+ [1][1][2][0][RTW89_UK][1][69] = 127,
+ [1][1][2][0][RTW89_UK][0][69] = 127,
+ [1][1][2][0][RTW89_FCC][1][73] = 10,
+ [1][1][2][0][RTW89_FCC][2][73] = 66,
+ [1][1][2][0][RTW89_ETSI][1][73] = 127,
+ [1][1][2][0][RTW89_ETSI][0][73] = 127,
+ [1][1][2][0][RTW89_MKK][1][73] = 127,
+ [1][1][2][0][RTW89_MKK][0][73] = 127,
+ [1][1][2][0][RTW89_IC][1][73] = 10,
+ [1][1][2][0][RTW89_KCC][1][73] = 28,
+ [1][1][2][0][RTW89_KCC][0][73] = 127,
+ [1][1][2][0][RTW89_ACMA][1][73] = 127,
+ [1][1][2][0][RTW89_ACMA][0][73] = 127,
+ [1][1][2][0][RTW89_CHILE][1][73] = 10,
+ [1][1][2][0][RTW89_QATAR][1][73] = 127,
+ [1][1][2][0][RTW89_QATAR][0][73] = 127,
+ [1][1][2][0][RTW89_UK][1][73] = 127,
+ [1][1][2][0][RTW89_UK][0][73] = 127,
+ [1][1][2][0][RTW89_FCC][1][76] = 10,
+ [1][1][2][0][RTW89_FCC][2][76] = 66,
+ [1][1][2][0][RTW89_ETSI][1][76] = 127,
+ [1][1][2][0][RTW89_ETSI][0][76] = 127,
+ [1][1][2][0][RTW89_MKK][1][76] = 127,
+ [1][1][2][0][RTW89_MKK][0][76] = 127,
+ [1][1][2][0][RTW89_IC][1][76] = 10,
+ [1][1][2][0][RTW89_KCC][1][76] = 28,
+ [1][1][2][0][RTW89_KCC][0][76] = 127,
+ [1][1][2][0][RTW89_ACMA][1][76] = 127,
+ [1][1][2][0][RTW89_ACMA][0][76] = 127,
+ [1][1][2][0][RTW89_CHILE][1][76] = 10,
+ [1][1][2][0][RTW89_QATAR][1][76] = 127,
+ [1][1][2][0][RTW89_QATAR][0][76] = 127,
+ [1][1][2][0][RTW89_UK][1][76] = 127,
+ [1][1][2][0][RTW89_UK][0][76] = 127,
+ [1][1][2][0][RTW89_FCC][1][80] = 10,
+ [1][1][2][0][RTW89_FCC][2][80] = 66,
+ [1][1][2][0][RTW89_ETSI][1][80] = 127,
+ [1][1][2][0][RTW89_ETSI][0][80] = 127,
+ [1][1][2][0][RTW89_MKK][1][80] = 127,
+ [1][1][2][0][RTW89_MKK][0][80] = 127,
+ [1][1][2][0][RTW89_IC][1][80] = 10,
+ [1][1][2][0][RTW89_KCC][1][80] = 32,
+ [1][1][2][0][RTW89_KCC][0][80] = 127,
+ [1][1][2][0][RTW89_ACMA][1][80] = 127,
+ [1][1][2][0][RTW89_ACMA][0][80] = 127,
+ [1][1][2][0][RTW89_CHILE][1][80] = 10,
+ [1][1][2][0][RTW89_QATAR][1][80] = 127,
+ [1][1][2][0][RTW89_QATAR][0][80] = 127,
+ [1][1][2][0][RTW89_UK][1][80] = 127,
+ [1][1][2][0][RTW89_UK][0][80] = 127,
+ [1][1][2][0][RTW89_FCC][1][84] = 10,
+ [1][1][2][0][RTW89_FCC][2][84] = 66,
+ [1][1][2][0][RTW89_ETSI][1][84] = 127,
+ [1][1][2][0][RTW89_ETSI][0][84] = 127,
+ [1][1][2][0][RTW89_MKK][1][84] = 127,
+ [1][1][2][0][RTW89_MKK][0][84] = 127,
+ [1][1][2][0][RTW89_IC][1][84] = 10,
+ [1][1][2][0][RTW89_KCC][1][84] = 32,
+ [1][1][2][0][RTW89_KCC][0][84] = 127,
+ [1][1][2][0][RTW89_ACMA][1][84] = 127,
+ [1][1][2][0][RTW89_ACMA][0][84] = 127,
+ [1][1][2][0][RTW89_CHILE][1][84] = 10,
+ [1][1][2][0][RTW89_QATAR][1][84] = 127,
+ [1][1][2][0][RTW89_QATAR][0][84] = 127,
+ [1][1][2][0][RTW89_UK][1][84] = 127,
+ [1][1][2][0][RTW89_UK][0][84] = 127,
+ [1][1][2][0][RTW89_FCC][1][88] = 10,
+ [1][1][2][0][RTW89_FCC][2][88] = 127,
+ [1][1][2][0][RTW89_ETSI][1][88] = 127,
+ [1][1][2][0][RTW89_ETSI][0][88] = 127,
+ [1][1][2][0][RTW89_MKK][1][88] = 127,
+ [1][1][2][0][RTW89_MKK][0][88] = 127,
+ [1][1][2][0][RTW89_IC][1][88] = 10,
+ [1][1][2][0][RTW89_KCC][1][88] = 32,
+ [1][1][2][0][RTW89_KCC][0][88] = 127,
+ [1][1][2][0][RTW89_ACMA][1][88] = 127,
+ [1][1][2][0][RTW89_ACMA][0][88] = 127,
+ [1][1][2][0][RTW89_CHILE][1][88] = 10,
+ [1][1][2][0][RTW89_QATAR][1][88] = 127,
+ [1][1][2][0][RTW89_QATAR][0][88] = 127,
+ [1][1][2][0][RTW89_UK][1][88] = 127,
+ [1][1][2][0][RTW89_UK][0][88] = 127,
+ [1][1][2][0][RTW89_FCC][1][91] = 12,
+ [1][1][2][0][RTW89_FCC][2][91] = 127,
+ [1][1][2][0][RTW89_ETSI][1][91] = 127,
+ [1][1][2][0][RTW89_ETSI][0][91] = 127,
+ [1][1][2][0][RTW89_MKK][1][91] = 127,
+ [1][1][2][0][RTW89_MKK][0][91] = 127,
+ [1][1][2][0][RTW89_IC][1][91] = 12,
+ [1][1][2][0][RTW89_KCC][1][91] = 32,
+ [1][1][2][0][RTW89_KCC][0][91] = 127,
+ [1][1][2][0][RTW89_ACMA][1][91] = 127,
+ [1][1][2][0][RTW89_ACMA][0][91] = 127,
+ [1][1][2][0][RTW89_CHILE][1][91] = 12,
+ [1][1][2][0][RTW89_QATAR][1][91] = 127,
+ [1][1][2][0][RTW89_QATAR][0][91] = 127,
+ [1][1][2][0][RTW89_UK][1][91] = 127,
+ [1][1][2][0][RTW89_UK][0][91] = 127,
+ [1][1][2][0][RTW89_FCC][1][95] = 10,
+ [1][1][2][0][RTW89_FCC][2][95] = 127,
+ [1][1][2][0][RTW89_ETSI][1][95] = 127,
+ [1][1][2][0][RTW89_ETSI][0][95] = 127,
+ [1][1][2][0][RTW89_MKK][1][95] = 127,
+ [1][1][2][0][RTW89_MKK][0][95] = 127,
+ [1][1][2][0][RTW89_IC][1][95] = 10,
+ [1][1][2][0][RTW89_KCC][1][95] = 32,
+ [1][1][2][0][RTW89_KCC][0][95] = 127,
+ [1][1][2][0][RTW89_ACMA][1][95] = 127,
+ [1][1][2][0][RTW89_ACMA][0][95] = 127,
+ [1][1][2][0][RTW89_CHILE][1][95] = 10,
+ [1][1][2][0][RTW89_QATAR][1][95] = 127,
+ [1][1][2][0][RTW89_QATAR][0][95] = 127,
+ [1][1][2][0][RTW89_UK][1][95] = 127,
+ [1][1][2][0][RTW89_UK][0][95] = 127,
+ [1][1][2][0][RTW89_FCC][1][99] = 10,
+ [1][1][2][0][RTW89_FCC][2][99] = 127,
+ [1][1][2][0][RTW89_ETSI][1][99] = 127,
+ [1][1][2][0][RTW89_ETSI][0][99] = 127,
+ [1][1][2][0][RTW89_MKK][1][99] = 127,
+ [1][1][2][0][RTW89_MKK][0][99] = 127,
+ [1][1][2][0][RTW89_IC][1][99] = 10,
+ [1][1][2][0][RTW89_KCC][1][99] = 32,
+ [1][1][2][0][RTW89_KCC][0][99] = 127,
+ [1][1][2][0][RTW89_ACMA][1][99] = 127,
+ [1][1][2][0][RTW89_ACMA][0][99] = 127,
+ [1][1][2][0][RTW89_CHILE][1][99] = 10,
+ [1][1][2][0][RTW89_QATAR][1][99] = 127,
+ [1][1][2][0][RTW89_QATAR][0][99] = 127,
+ [1][1][2][0][RTW89_UK][1][99] = 127,
+ [1][1][2][0][RTW89_UK][0][99] = 127,
+ [1][1][2][0][RTW89_FCC][1][103] = 10,
+ [1][1][2][0][RTW89_FCC][2][103] = 127,
+ [1][1][2][0][RTW89_ETSI][1][103] = 127,
+ [1][1][2][0][RTW89_ETSI][0][103] = 127,
+ [1][1][2][0][RTW89_MKK][1][103] = 127,
+ [1][1][2][0][RTW89_MKK][0][103] = 127,
+ [1][1][2][0][RTW89_IC][1][103] = 10,
+ [1][1][2][0][RTW89_KCC][1][103] = 32,
+ [1][1][2][0][RTW89_KCC][0][103] = 127,
+ [1][1][2][0][RTW89_ACMA][1][103] = 127,
+ [1][1][2][0][RTW89_ACMA][0][103] = 127,
+ [1][1][2][0][RTW89_CHILE][1][103] = 10,
+ [1][1][2][0][RTW89_QATAR][1][103] = 127,
+ [1][1][2][0][RTW89_QATAR][0][103] = 127,
+ [1][1][2][0][RTW89_UK][1][103] = 127,
+ [1][1][2][0][RTW89_UK][0][103] = 127,
+ [1][1][2][0][RTW89_FCC][1][106] = 12,
+ [1][1][2][0][RTW89_FCC][2][106] = 127,
+ [1][1][2][0][RTW89_ETSI][1][106] = 127,
+ [1][1][2][0][RTW89_ETSI][0][106] = 127,
+ [1][1][2][0][RTW89_MKK][1][106] = 127,
+ [1][1][2][0][RTW89_MKK][0][106] = 127,
+ [1][1][2][0][RTW89_IC][1][106] = 12,
+ [1][1][2][0][RTW89_KCC][1][106] = 32,
+ [1][1][2][0][RTW89_KCC][0][106] = 127,
+ [1][1][2][0][RTW89_ACMA][1][106] = 127,
+ [1][1][2][0][RTW89_ACMA][0][106] = 127,
+ [1][1][2][0][RTW89_CHILE][1][106] = 12,
+ [1][1][2][0][RTW89_QATAR][1][106] = 127,
+ [1][1][2][0][RTW89_QATAR][0][106] = 127,
+ [1][1][2][0][RTW89_UK][1][106] = 127,
+ [1][1][2][0][RTW89_UK][0][106] = 127,
+ [1][1][2][0][RTW89_FCC][1][110] = 127,
+ [1][1][2][0][RTW89_FCC][2][110] = 127,
+ [1][1][2][0][RTW89_ETSI][1][110] = 127,
+ [1][1][2][0][RTW89_ETSI][0][110] = 127,
+ [1][1][2][0][RTW89_MKK][1][110] = 127,
+ [1][1][2][0][RTW89_MKK][0][110] = 127,
+ [1][1][2][0][RTW89_IC][1][110] = 127,
+ [1][1][2][0][RTW89_KCC][1][110] = 127,
+ [1][1][2][0][RTW89_KCC][0][110] = 127,
+ [1][1][2][0][RTW89_ACMA][1][110] = 127,
+ [1][1][2][0][RTW89_ACMA][0][110] = 127,
+ [1][1][2][0][RTW89_CHILE][1][110] = 127,
+ [1][1][2][0][RTW89_QATAR][1][110] = 127,
+ [1][1][2][0][RTW89_QATAR][0][110] = 127,
+ [1][1][2][0][RTW89_UK][1][110] = 127,
+ [1][1][2][0][RTW89_UK][0][110] = 127,
+ [1][1][2][0][RTW89_FCC][1][114] = 127,
+ [1][1][2][0][RTW89_FCC][2][114] = 127,
+ [1][1][2][0][RTW89_ETSI][1][114] = 127,
+ [1][1][2][0][RTW89_ETSI][0][114] = 127,
+ [1][1][2][0][RTW89_MKK][1][114] = 127,
+ [1][1][2][0][RTW89_MKK][0][114] = 127,
+ [1][1][2][0][RTW89_IC][1][114] = 127,
+ [1][1][2][0][RTW89_KCC][1][114] = 127,
+ [1][1][2][0][RTW89_KCC][0][114] = 127,
+ [1][1][2][0][RTW89_ACMA][1][114] = 127,
+ [1][1][2][0][RTW89_ACMA][0][114] = 127,
+ [1][1][2][0][RTW89_CHILE][1][114] = 127,
+ [1][1][2][0][RTW89_QATAR][1][114] = 127,
+ [1][1][2][0][RTW89_QATAR][0][114] = 127,
+ [1][1][2][0][RTW89_UK][1][114] = 127,
+ [1][1][2][0][RTW89_UK][0][114] = 127,
+ [1][1][2][0][RTW89_FCC][1][118] = 127,
+ [1][1][2][0][RTW89_FCC][2][118] = 127,
+ [1][1][2][0][RTW89_ETSI][1][118] = 127,
+ [1][1][2][0][RTW89_ETSI][0][118] = 127,
+ [1][1][2][0][RTW89_MKK][1][118] = 127,
+ [1][1][2][0][RTW89_MKK][0][118] = 127,
+ [1][1][2][0][RTW89_IC][1][118] = 127,
+ [1][1][2][0][RTW89_KCC][1][118] = 127,
+ [1][1][2][0][RTW89_KCC][0][118] = 127,
+ [1][1][2][0][RTW89_ACMA][1][118] = 127,
+ [1][1][2][0][RTW89_ACMA][0][118] = 127,
+ [1][1][2][0][RTW89_CHILE][1][118] = 127,
+ [1][1][2][0][RTW89_QATAR][1][118] = 127,
+ [1][1][2][0][RTW89_QATAR][0][118] = 127,
+ [1][1][2][0][RTW89_UK][1][118] = 127,
+ [1][1][2][0][RTW89_UK][0][118] = 127,
+ [1][1][2][1][RTW89_FCC][1][1] = 10,
+ [1][1][2][1][RTW89_FCC][2][1] = 58,
+ [1][1][2][1][RTW89_ETSI][1][1] = 42,
+ [1][1][2][1][RTW89_ETSI][0][1] = 6,
+ [1][1][2][1][RTW89_MKK][1][1] = 52,
+ [1][1][2][1][RTW89_MKK][0][1] = 12,
+ [1][1][2][1][RTW89_IC][1][1] = 10,
+ [1][1][2][1][RTW89_KCC][1][1] = 28,
+ [1][1][2][1][RTW89_KCC][0][1] = 12,
+ [1][1][2][1][RTW89_ACMA][1][1] = 42,
+ [1][1][2][1][RTW89_ACMA][0][1] = 6,
+ [1][1][2][1][RTW89_CHILE][1][1] = 10,
+ [1][1][2][1][RTW89_QATAR][1][1] = 42,
+ [1][1][2][1][RTW89_QATAR][0][1] = 6,
+ [1][1][2][1][RTW89_UK][1][1] = 42,
+ [1][1][2][1][RTW89_UK][0][1] = 6,
+ [1][1][2][1][RTW89_FCC][1][5] = 10,
+ [1][1][2][1][RTW89_FCC][2][5] = 58,
+ [1][1][2][1][RTW89_ETSI][1][5] = 42,
+ [1][1][2][1][RTW89_ETSI][0][5] = 6,
+ [1][1][2][1][RTW89_MKK][1][5] = 52,
+ [1][1][2][1][RTW89_MKK][0][5] = 12,
+ [1][1][2][1][RTW89_IC][1][5] = 10,
+ [1][1][2][1][RTW89_KCC][1][5] = 28,
+ [1][1][2][1][RTW89_KCC][0][5] = 12,
+ [1][1][2][1][RTW89_ACMA][1][5] = 42,
+ [1][1][2][1][RTW89_ACMA][0][5] = 6,
+ [1][1][2][1][RTW89_CHILE][1][5] = 10,
+ [1][1][2][1][RTW89_QATAR][1][5] = 42,
+ [1][1][2][1][RTW89_QATAR][0][5] = 6,
+ [1][1][2][1][RTW89_UK][1][5] = 42,
+ [1][1][2][1][RTW89_UK][0][5] = 6,
+ [1][1][2][1][RTW89_FCC][1][9] = 10,
+ [1][1][2][1][RTW89_FCC][2][9] = 58,
+ [1][1][2][1][RTW89_ETSI][1][9] = 42,
+ [1][1][2][1][RTW89_ETSI][0][9] = 6,
+ [1][1][2][1][RTW89_MKK][1][9] = 52,
+ [1][1][2][1][RTW89_MKK][0][9] = 12,
+ [1][1][2][1][RTW89_IC][1][9] = 10,
+ [1][1][2][1][RTW89_KCC][1][9] = 28,
+ [1][1][2][1][RTW89_KCC][0][9] = 12,
+ [1][1][2][1][RTW89_ACMA][1][9] = 42,
+ [1][1][2][1][RTW89_ACMA][0][9] = 6,
+ [1][1][2][1][RTW89_CHILE][1][9] = 10,
+ [1][1][2][1][RTW89_QATAR][1][9] = 42,
+ [1][1][2][1][RTW89_QATAR][0][9] = 6,
+ [1][1][2][1][RTW89_UK][1][9] = 42,
+ [1][1][2][1][RTW89_UK][0][9] = 6,
+ [1][1][2][1][RTW89_FCC][1][13] = 10,
+ [1][1][2][1][RTW89_FCC][2][13] = 58,
+ [1][1][2][1][RTW89_ETSI][1][13] = 42,
+ [1][1][2][1][RTW89_ETSI][0][13] = 6,
+ [1][1][2][1][RTW89_MKK][1][13] = 52,
+ [1][1][2][1][RTW89_MKK][0][13] = 12,
+ [1][1][2][1][RTW89_IC][1][13] = 10,
+ [1][1][2][1][RTW89_KCC][1][13] = 28,
+ [1][1][2][1][RTW89_KCC][0][13] = 12,
+ [1][1][2][1][RTW89_ACMA][1][13] = 42,
+ [1][1][2][1][RTW89_ACMA][0][13] = 6,
+ [1][1][2][1][RTW89_CHILE][1][13] = 10,
+ [1][1][2][1][RTW89_QATAR][1][13] = 42,
+ [1][1][2][1][RTW89_QATAR][0][13] = 6,
+ [1][1][2][1][RTW89_UK][1][13] = 42,
+ [1][1][2][1][RTW89_UK][0][13] = 6,
+ [1][1][2][1][RTW89_FCC][1][16] = 10,
+ [1][1][2][1][RTW89_FCC][2][16] = 58,
+ [1][1][2][1][RTW89_ETSI][1][16] = 42,
+ [1][1][2][1][RTW89_ETSI][0][16] = 6,
+ [1][1][2][1][RTW89_MKK][1][16] = 52,
+ [1][1][2][1][RTW89_MKK][0][16] = 12,
+ [1][1][2][1][RTW89_IC][1][16] = 10,
+ [1][1][2][1][RTW89_KCC][1][16] = 28,
+ [1][1][2][1][RTW89_KCC][0][16] = 12,
+ [1][1][2][1][RTW89_ACMA][1][16] = 42,
+ [1][1][2][1][RTW89_ACMA][0][16] = 6,
+ [1][1][2][1][RTW89_CHILE][1][16] = 10,
+ [1][1][2][1][RTW89_QATAR][1][16] = 42,
+ [1][1][2][1][RTW89_QATAR][0][16] = 6,
+ [1][1][2][1][RTW89_UK][1][16] = 42,
+ [1][1][2][1][RTW89_UK][0][16] = 6,
+ [1][1][2][1][RTW89_FCC][1][20] = 10,
+ [1][1][2][1][RTW89_FCC][2][20] = 58,
+ [1][1][2][1][RTW89_ETSI][1][20] = 42,
+ [1][1][2][1][RTW89_ETSI][0][20] = 6,
+ [1][1][2][1][RTW89_MKK][1][20] = 52,
+ [1][1][2][1][RTW89_MKK][0][20] = 12,
+ [1][1][2][1][RTW89_IC][1][20] = 10,
+ [1][1][2][1][RTW89_KCC][1][20] = 28,
+ [1][1][2][1][RTW89_KCC][0][20] = 12,
+ [1][1][2][1][RTW89_ACMA][1][20] = 42,
+ [1][1][2][1][RTW89_ACMA][0][20] = 6,
+ [1][1][2][1][RTW89_CHILE][1][20] = 10,
+ [1][1][2][1][RTW89_QATAR][1][20] = 42,
+ [1][1][2][1][RTW89_QATAR][0][20] = 6,
+ [1][1][2][1][RTW89_UK][1][20] = 42,
+ [1][1][2][1][RTW89_UK][0][20] = 6,
+ [1][1][2][1][RTW89_FCC][1][24] = 10,
+ [1][1][2][1][RTW89_FCC][2][24] = 70,
+ [1][1][2][1][RTW89_ETSI][1][24] = 42,
+ [1][1][2][1][RTW89_ETSI][0][24] = 6,
+ [1][1][2][1][RTW89_MKK][1][24] = 54,
+ [1][1][2][1][RTW89_MKK][0][24] = 14,
+ [1][1][2][1][RTW89_IC][1][24] = 10,
+ [1][1][2][1][RTW89_KCC][1][24] = 28,
+ [1][1][2][1][RTW89_KCC][0][24] = 12,
+ [1][1][2][1][RTW89_ACMA][1][24] = 42,
+ [1][1][2][1][RTW89_ACMA][0][24] = 6,
+ [1][1][2][1][RTW89_CHILE][1][24] = 10,
+ [1][1][2][1][RTW89_QATAR][1][24] = 42,
+ [1][1][2][1][RTW89_QATAR][0][24] = 6,
+ [1][1][2][1][RTW89_UK][1][24] = 42,
+ [1][1][2][1][RTW89_UK][0][24] = 6,
+ [1][1][2][1][RTW89_FCC][1][28] = 10,
+ [1][1][2][1][RTW89_FCC][2][28] = 70,
+ [1][1][2][1][RTW89_ETSI][1][28] = 42,
+ [1][1][2][1][RTW89_ETSI][0][28] = 6,
+ [1][1][2][1][RTW89_MKK][1][28] = 52,
+ [1][1][2][1][RTW89_MKK][0][28] = 14,
+ [1][1][2][1][RTW89_IC][1][28] = 10,
+ [1][1][2][1][RTW89_KCC][1][28] = 28,
+ [1][1][2][1][RTW89_KCC][0][28] = 14,
+ [1][1][2][1][RTW89_ACMA][1][28] = 42,
+ [1][1][2][1][RTW89_ACMA][0][28] = 6,
+ [1][1][2][1][RTW89_CHILE][1][28] = 10,
+ [1][1][2][1][RTW89_QATAR][1][28] = 42,
+ [1][1][2][1][RTW89_QATAR][0][28] = 6,
+ [1][1][2][1][RTW89_UK][1][28] = 42,
+ [1][1][2][1][RTW89_UK][0][28] = 6,
+ [1][1][2][1][RTW89_FCC][1][31] = 10,
+ [1][1][2][1][RTW89_FCC][2][31] = 70,
+ [1][1][2][1][RTW89_ETSI][1][31] = 42,
+ [1][1][2][1][RTW89_ETSI][0][31] = 6,
+ [1][1][2][1][RTW89_MKK][1][31] = 52,
+ [1][1][2][1][RTW89_MKK][0][31] = 14,
+ [1][1][2][1][RTW89_IC][1][31] = 10,
+ [1][1][2][1][RTW89_KCC][1][31] = 28,
+ [1][1][2][1][RTW89_KCC][0][31] = 14,
+ [1][1][2][1][RTW89_ACMA][1][31] = 42,
+ [1][1][2][1][RTW89_ACMA][0][31] = 6,
+ [1][1][2][1][RTW89_CHILE][1][31] = 10,
+ [1][1][2][1][RTW89_QATAR][1][31] = 42,
+ [1][1][2][1][RTW89_QATAR][0][31] = 6,
+ [1][1][2][1][RTW89_UK][1][31] = 42,
+ [1][1][2][1][RTW89_UK][0][31] = 6,
+ [1][1][2][1][RTW89_FCC][1][35] = 10,
+ [1][1][2][1][RTW89_FCC][2][35] = 70,
+ [1][1][2][1][RTW89_ETSI][1][35] = 42,
+ [1][1][2][1][RTW89_ETSI][0][35] = 6,
+ [1][1][2][1][RTW89_MKK][1][35] = 52,
+ [1][1][2][1][RTW89_MKK][0][35] = 14,
+ [1][1][2][1][RTW89_IC][1][35] = 10,
+ [1][1][2][1][RTW89_KCC][1][35] = 28,
+ [1][1][2][1][RTW89_KCC][0][35] = 14,
+ [1][1][2][1][RTW89_ACMA][1][35] = 42,
+ [1][1][2][1][RTW89_ACMA][0][35] = 6,
+ [1][1][2][1][RTW89_CHILE][1][35] = 10,
+ [1][1][2][1][RTW89_QATAR][1][35] = 42,
+ [1][1][2][1][RTW89_QATAR][0][35] = 6,
+ [1][1][2][1][RTW89_UK][1][35] = 42,
+ [1][1][2][1][RTW89_UK][0][35] = 6,
+ [1][1][2][1][RTW89_FCC][1][39] = 10,
+ [1][1][2][1][RTW89_FCC][2][39] = 70,
+ [1][1][2][1][RTW89_ETSI][1][39] = 42,
+ [1][1][2][1][RTW89_ETSI][0][39] = 6,
+ [1][1][2][1][RTW89_MKK][1][39] = 52,
+ [1][1][2][1][RTW89_MKK][0][39] = 14,
+ [1][1][2][1][RTW89_IC][1][39] = 10,
+ [1][1][2][1][RTW89_KCC][1][39] = 28,
+ [1][1][2][1][RTW89_KCC][0][39] = 14,
+ [1][1][2][1][RTW89_ACMA][1][39] = 42,
+ [1][1][2][1][RTW89_ACMA][0][39] = 6,
+ [1][1][2][1][RTW89_CHILE][1][39] = 10,
+ [1][1][2][1][RTW89_QATAR][1][39] = 42,
+ [1][1][2][1][RTW89_QATAR][0][39] = 6,
+ [1][1][2][1][RTW89_UK][1][39] = 42,
+ [1][1][2][1][RTW89_UK][0][39] = 6,
+ [1][1][2][1][RTW89_FCC][1][43] = 10,
+ [1][1][2][1][RTW89_FCC][2][43] = 70,
+ [1][1][2][1][RTW89_ETSI][1][43] = 42,
+ [1][1][2][1][RTW89_ETSI][0][43] = 6,
+ [1][1][2][1][RTW89_MKK][1][43] = 52,
+ [1][1][2][1][RTW89_MKK][0][43] = 14,
+ [1][1][2][1][RTW89_IC][1][43] = 10,
+ [1][1][2][1][RTW89_KCC][1][43] = 28,
+ [1][1][2][1][RTW89_KCC][0][43] = 14,
+ [1][1][2][1][RTW89_ACMA][1][43] = 42,
+ [1][1][2][1][RTW89_ACMA][0][43] = 6,
+ [1][1][2][1][RTW89_CHILE][1][43] = 10,
+ [1][1][2][1][RTW89_QATAR][1][43] = 42,
+ [1][1][2][1][RTW89_QATAR][0][43] = 6,
+ [1][1][2][1][RTW89_UK][1][43] = 42,
+ [1][1][2][1][RTW89_UK][0][43] = 6,
+ [1][1][2][1][RTW89_FCC][1][46] = 12,
+ [1][1][2][1][RTW89_FCC][2][46] = 127,
+ [1][1][2][1][RTW89_ETSI][1][46] = 127,
+ [1][1][2][1][RTW89_ETSI][0][46] = 127,
+ [1][1][2][1][RTW89_MKK][1][46] = 127,
+ [1][1][2][1][RTW89_MKK][0][46] = 127,
+ [1][1][2][1][RTW89_IC][1][46] = 12,
+ [1][1][2][1][RTW89_KCC][1][46] = 28,
+ [1][1][2][1][RTW89_KCC][0][46] = 127,
+ [1][1][2][1][RTW89_ACMA][1][46] = 127,
+ [1][1][2][1][RTW89_ACMA][0][46] = 127,
+ [1][1][2][1][RTW89_CHILE][1][46] = 12,
+ [1][1][2][1][RTW89_QATAR][1][46] = 127,
+ [1][1][2][1][RTW89_QATAR][0][46] = 127,
+ [1][1][2][1][RTW89_UK][1][46] = 127,
+ [1][1][2][1][RTW89_UK][0][46] = 127,
+ [1][1][2][1][RTW89_FCC][1][50] = 12,
+ [1][1][2][1][RTW89_FCC][2][50] = 127,
+ [1][1][2][1][RTW89_ETSI][1][50] = 127,
+ [1][1][2][1][RTW89_ETSI][0][50] = 127,
+ [1][1][2][1][RTW89_MKK][1][50] = 127,
+ [1][1][2][1][RTW89_MKK][0][50] = 127,
+ [1][1][2][1][RTW89_IC][1][50] = 12,
+ [1][1][2][1][RTW89_KCC][1][50] = 28,
+ [1][1][2][1][RTW89_KCC][0][50] = 127,
+ [1][1][2][1][RTW89_ACMA][1][50] = 127,
+ [1][1][2][1][RTW89_ACMA][0][50] = 127,
+ [1][1][2][1][RTW89_CHILE][1][50] = 12,
+ [1][1][2][1][RTW89_QATAR][1][50] = 127,
+ [1][1][2][1][RTW89_QATAR][0][50] = 127,
+ [1][1][2][1][RTW89_UK][1][50] = 127,
+ [1][1][2][1][RTW89_UK][0][50] = 127,
+ [1][1][2][1][RTW89_FCC][1][54] = 10,
+ [1][1][2][1][RTW89_FCC][2][54] = 127,
+ [1][1][2][1][RTW89_ETSI][1][54] = 127,
+ [1][1][2][1][RTW89_ETSI][0][54] = 127,
+ [1][1][2][1][RTW89_MKK][1][54] = 127,
+ [1][1][2][1][RTW89_MKK][0][54] = 127,
+ [1][1][2][1][RTW89_IC][1][54] = 10,
+ [1][1][2][1][RTW89_KCC][1][54] = 28,
+ [1][1][2][1][RTW89_KCC][0][54] = 127,
+ [1][1][2][1][RTW89_ACMA][1][54] = 127,
+ [1][1][2][1][RTW89_ACMA][0][54] = 127,
+ [1][1][2][1][RTW89_CHILE][1][54] = 10,
+ [1][1][2][1][RTW89_QATAR][1][54] = 127,
+ [1][1][2][1][RTW89_QATAR][0][54] = 127,
+ [1][1][2][1][RTW89_UK][1][54] = 127,
+ [1][1][2][1][RTW89_UK][0][54] = 127,
+ [1][1][2][1][RTW89_FCC][1][58] = 10,
+ [1][1][2][1][RTW89_FCC][2][58] = 66,
+ [1][1][2][1][RTW89_ETSI][1][58] = 127,
+ [1][1][2][1][RTW89_ETSI][0][58] = 127,
+ [1][1][2][1][RTW89_MKK][1][58] = 127,
+ [1][1][2][1][RTW89_MKK][0][58] = 127,
+ [1][1][2][1][RTW89_IC][1][58] = 10,
+ [1][1][2][1][RTW89_KCC][1][58] = 28,
+ [1][1][2][1][RTW89_KCC][0][58] = 127,
+ [1][1][2][1][RTW89_ACMA][1][58] = 127,
+ [1][1][2][1][RTW89_ACMA][0][58] = 127,
+ [1][1][2][1][RTW89_CHILE][1][58] = 10,
+ [1][1][2][1][RTW89_QATAR][1][58] = 127,
+ [1][1][2][1][RTW89_QATAR][0][58] = 127,
+ [1][1][2][1][RTW89_UK][1][58] = 127,
+ [1][1][2][1][RTW89_UK][0][58] = 127,
+ [1][1][2][1][RTW89_FCC][1][61] = 10,
+ [1][1][2][1][RTW89_FCC][2][61] = 66,
+ [1][1][2][1][RTW89_ETSI][1][61] = 127,
+ [1][1][2][1][RTW89_ETSI][0][61] = 127,
+ [1][1][2][1][RTW89_MKK][1][61] = 127,
+ [1][1][2][1][RTW89_MKK][0][61] = 127,
+ [1][1][2][1][RTW89_IC][1][61] = 10,
+ [1][1][2][1][RTW89_KCC][1][61] = 28,
+ [1][1][2][1][RTW89_KCC][0][61] = 127,
+ [1][1][2][1][RTW89_ACMA][1][61] = 127,
+ [1][1][2][1][RTW89_ACMA][0][61] = 127,
+ [1][1][2][1][RTW89_CHILE][1][61] = 10,
+ [1][1][2][1][RTW89_QATAR][1][61] = 127,
+ [1][1][2][1][RTW89_QATAR][0][61] = 127,
+ [1][1][2][1][RTW89_UK][1][61] = 127,
+ [1][1][2][1][RTW89_UK][0][61] = 127,
+ [1][1][2][1][RTW89_FCC][1][65] = 10,
+ [1][1][2][1][RTW89_FCC][2][65] = 66,
+ [1][1][2][1][RTW89_ETSI][1][65] = 127,
+ [1][1][2][1][RTW89_ETSI][0][65] = 127,
+ [1][1][2][1][RTW89_MKK][1][65] = 127,
+ [1][1][2][1][RTW89_MKK][0][65] = 127,
+ [1][1][2][1][RTW89_IC][1][65] = 10,
+ [1][1][2][1][RTW89_KCC][1][65] = 28,
+ [1][1][2][1][RTW89_KCC][0][65] = 127,
+ [1][1][2][1][RTW89_ACMA][1][65] = 127,
+ [1][1][2][1][RTW89_ACMA][0][65] = 127,
+ [1][1][2][1][RTW89_CHILE][1][65] = 10,
+ [1][1][2][1][RTW89_QATAR][1][65] = 127,
+ [1][1][2][1][RTW89_QATAR][0][65] = 127,
+ [1][1][2][1][RTW89_UK][1][65] = 127,
+ [1][1][2][1][RTW89_UK][0][65] = 127,
+ [1][1][2][1][RTW89_FCC][1][69] = 10,
+ [1][1][2][1][RTW89_FCC][2][69] = 66,
+ [1][1][2][1][RTW89_ETSI][1][69] = 127,
+ [1][1][2][1][RTW89_ETSI][0][69] = 127,
+ [1][1][2][1][RTW89_MKK][1][69] = 127,
+ [1][1][2][1][RTW89_MKK][0][69] = 127,
+ [1][1][2][1][RTW89_IC][1][69] = 10,
+ [1][1][2][1][RTW89_KCC][1][69] = 28,
+ [1][1][2][1][RTW89_KCC][0][69] = 127,
+ [1][1][2][1][RTW89_ACMA][1][69] = 127,
+ [1][1][2][1][RTW89_ACMA][0][69] = 127,
+ [1][1][2][1][RTW89_CHILE][1][69] = 10,
+ [1][1][2][1][RTW89_QATAR][1][69] = 127,
+ [1][1][2][1][RTW89_QATAR][0][69] = 127,
+ [1][1][2][1][RTW89_UK][1][69] = 127,
+ [1][1][2][1][RTW89_UK][0][69] = 127,
+ [1][1][2][1][RTW89_FCC][1][73] = 10,
+ [1][1][2][1][RTW89_FCC][2][73] = 66,
+ [1][1][2][1][RTW89_ETSI][1][73] = 127,
+ [1][1][2][1][RTW89_ETSI][0][73] = 127,
+ [1][1][2][1][RTW89_MKK][1][73] = 127,
+ [1][1][2][1][RTW89_MKK][0][73] = 127,
+ [1][1][2][1][RTW89_IC][1][73] = 10,
+ [1][1][2][1][RTW89_KCC][1][73] = 28,
+ [1][1][2][1][RTW89_KCC][0][73] = 127,
+ [1][1][2][1][RTW89_ACMA][1][73] = 127,
+ [1][1][2][1][RTW89_ACMA][0][73] = 127,
+ [1][1][2][1][RTW89_CHILE][1][73] = 10,
+ [1][1][2][1][RTW89_QATAR][1][73] = 127,
+ [1][1][2][1][RTW89_QATAR][0][73] = 127,
+ [1][1][2][1][RTW89_UK][1][73] = 127,
+ [1][1][2][1][RTW89_UK][0][73] = 127,
+ [1][1][2][1][RTW89_FCC][1][76] = 10,
+ [1][1][2][1][RTW89_FCC][2][76] = 66,
+ [1][1][2][1][RTW89_ETSI][1][76] = 127,
+ [1][1][2][1][RTW89_ETSI][0][76] = 127,
+ [1][1][2][1][RTW89_MKK][1][76] = 127,
+ [1][1][2][1][RTW89_MKK][0][76] = 127,
+ [1][1][2][1][RTW89_IC][1][76] = 10,
+ [1][1][2][1][RTW89_KCC][1][76] = 28,
+ [1][1][2][1][RTW89_KCC][0][76] = 127,
+ [1][1][2][1][RTW89_ACMA][1][76] = 127,
+ [1][1][2][1][RTW89_ACMA][0][76] = 127,
+ [1][1][2][1][RTW89_CHILE][1][76] = 10,
+ [1][1][2][1][RTW89_QATAR][1][76] = 127,
+ [1][1][2][1][RTW89_QATAR][0][76] = 127,
+ [1][1][2][1][RTW89_UK][1][76] = 127,
+ [1][1][2][1][RTW89_UK][0][76] = 127,
+ [1][1][2][1][RTW89_FCC][1][80] = 10,
+ [1][1][2][1][RTW89_FCC][2][80] = 66,
+ [1][1][2][1][RTW89_ETSI][1][80] = 127,
+ [1][1][2][1][RTW89_ETSI][0][80] = 127,
+ [1][1][2][1][RTW89_MKK][1][80] = 127,
+ [1][1][2][1][RTW89_MKK][0][80] = 127,
+ [1][1][2][1][RTW89_IC][1][80] = 10,
+ [1][1][2][1][RTW89_KCC][1][80] = 32,
+ [1][1][2][1][RTW89_KCC][0][80] = 127,
+ [1][1][2][1][RTW89_ACMA][1][80] = 127,
+ [1][1][2][1][RTW89_ACMA][0][80] = 127,
+ [1][1][2][1][RTW89_CHILE][1][80] = 10,
+ [1][1][2][1][RTW89_QATAR][1][80] = 127,
+ [1][1][2][1][RTW89_QATAR][0][80] = 127,
+ [1][1][2][1][RTW89_UK][1][80] = 127,
+ [1][1][2][1][RTW89_UK][0][80] = 127,
+ [1][1][2][1][RTW89_FCC][1][84] = 10,
+ [1][1][2][1][RTW89_FCC][2][84] = 66,
+ [1][1][2][1][RTW89_ETSI][1][84] = 127,
+ [1][1][2][1][RTW89_ETSI][0][84] = 127,
+ [1][1][2][1][RTW89_MKK][1][84] = 127,
+ [1][1][2][1][RTW89_MKK][0][84] = 127,
+ [1][1][2][1][RTW89_IC][1][84] = 10,
+ [1][1][2][1][RTW89_KCC][1][84] = 32,
+ [1][1][2][1][RTW89_KCC][0][84] = 127,
+ [1][1][2][1][RTW89_ACMA][1][84] = 127,
+ [1][1][2][1][RTW89_ACMA][0][84] = 127,
+ [1][1][2][1][RTW89_CHILE][1][84] = 10,
+ [1][1][2][1][RTW89_QATAR][1][84] = 127,
+ [1][1][2][1][RTW89_QATAR][0][84] = 127,
+ [1][1][2][1][RTW89_UK][1][84] = 127,
+ [1][1][2][1][RTW89_UK][0][84] = 127,
+ [1][1][2][1][RTW89_FCC][1][88] = 10,
+ [1][1][2][1][RTW89_FCC][2][88] = 127,
+ [1][1][2][1][RTW89_ETSI][1][88] = 127,
+ [1][1][2][1][RTW89_ETSI][0][88] = 127,
+ [1][1][2][1][RTW89_MKK][1][88] = 127,
+ [1][1][2][1][RTW89_MKK][0][88] = 127,
+ [1][1][2][1][RTW89_IC][1][88] = 10,
+ [1][1][2][1][RTW89_KCC][1][88] = 32,
+ [1][1][2][1][RTW89_KCC][0][88] = 127,
+ [1][1][2][1][RTW89_ACMA][1][88] = 127,
+ [1][1][2][1][RTW89_ACMA][0][88] = 127,
+ [1][1][2][1][RTW89_CHILE][1][88] = 10,
+ [1][1][2][1][RTW89_QATAR][1][88] = 127,
+ [1][1][2][1][RTW89_QATAR][0][88] = 127,
+ [1][1][2][1][RTW89_UK][1][88] = 127,
+ [1][1][2][1][RTW89_UK][0][88] = 127,
+ [1][1][2][1][RTW89_FCC][1][91] = 12,
+ [1][1][2][1][RTW89_FCC][2][91] = 127,
+ [1][1][2][1][RTW89_ETSI][1][91] = 127,
+ [1][1][2][1][RTW89_ETSI][0][91] = 127,
+ [1][1][2][1][RTW89_MKK][1][91] = 127,
+ [1][1][2][1][RTW89_MKK][0][91] = 127,
+ [1][1][2][1][RTW89_IC][1][91] = 12,
+ [1][1][2][1][RTW89_KCC][1][91] = 32,
+ [1][1][2][1][RTW89_KCC][0][91] = 127,
+ [1][1][2][1][RTW89_ACMA][1][91] = 127,
+ [1][1][2][1][RTW89_ACMA][0][91] = 127,
+ [1][1][2][1][RTW89_CHILE][1][91] = 12,
+ [1][1][2][1][RTW89_QATAR][1][91] = 127,
+ [1][1][2][1][RTW89_QATAR][0][91] = 127,
+ [1][1][2][1][RTW89_UK][1][91] = 127,
+ [1][1][2][1][RTW89_UK][0][91] = 127,
+ [1][1][2][1][RTW89_FCC][1][95] = 10,
+ [1][1][2][1][RTW89_FCC][2][95] = 127,
+ [1][1][2][1][RTW89_ETSI][1][95] = 127,
+ [1][1][2][1][RTW89_ETSI][0][95] = 127,
+ [1][1][2][1][RTW89_MKK][1][95] = 127,
+ [1][1][2][1][RTW89_MKK][0][95] = 127,
+ [1][1][2][1][RTW89_IC][1][95] = 10,
+ [1][1][2][1][RTW89_KCC][1][95] = 32,
+ [1][1][2][1][RTW89_KCC][0][95] = 127,
+ [1][1][2][1][RTW89_ACMA][1][95] = 127,
+ [1][1][2][1][RTW89_ACMA][0][95] = 127,
+ [1][1][2][1][RTW89_CHILE][1][95] = 10,
+ [1][1][2][1][RTW89_QATAR][1][95] = 127,
+ [1][1][2][1][RTW89_QATAR][0][95] = 127,
+ [1][1][2][1][RTW89_UK][1][95] = 127,
+ [1][1][2][1][RTW89_UK][0][95] = 127,
+ [1][1][2][1][RTW89_FCC][1][99] = 10,
+ [1][1][2][1][RTW89_FCC][2][99] = 127,
+ [1][1][2][1][RTW89_ETSI][1][99] = 127,
+ [1][1][2][1][RTW89_ETSI][0][99] = 127,
+ [1][1][2][1][RTW89_MKK][1][99] = 127,
+ [1][1][2][1][RTW89_MKK][0][99] = 127,
+ [1][1][2][1][RTW89_IC][1][99] = 10,
+ [1][1][2][1][RTW89_KCC][1][99] = 32,
+ [1][1][2][1][RTW89_KCC][0][99] = 127,
+ [1][1][2][1][RTW89_ACMA][1][99] = 127,
+ [1][1][2][1][RTW89_ACMA][0][99] = 127,
+ [1][1][2][1][RTW89_CHILE][1][99] = 10,
+ [1][1][2][1][RTW89_QATAR][1][99] = 127,
+ [1][1][2][1][RTW89_QATAR][0][99] = 127,
+ [1][1][2][1][RTW89_UK][1][99] = 127,
+ [1][1][2][1][RTW89_UK][0][99] = 127,
+ [1][1][2][1][RTW89_FCC][1][103] = 10,
+ [1][1][2][1][RTW89_FCC][2][103] = 127,
+ [1][1][2][1][RTW89_ETSI][1][103] = 127,
+ [1][1][2][1][RTW89_ETSI][0][103] = 127,
+ [1][1][2][1][RTW89_MKK][1][103] = 127,
+ [1][1][2][1][RTW89_MKK][0][103] = 127,
+ [1][1][2][1][RTW89_IC][1][103] = 10,
+ [1][1][2][1][RTW89_KCC][1][103] = 32,
+ [1][1][2][1][RTW89_KCC][0][103] = 127,
+ [1][1][2][1][RTW89_ACMA][1][103] = 127,
+ [1][1][2][1][RTW89_ACMA][0][103] = 127,
+ [1][1][2][1][RTW89_CHILE][1][103] = 10,
+ [1][1][2][1][RTW89_QATAR][1][103] = 127,
+ [1][1][2][1][RTW89_QATAR][0][103] = 127,
+ [1][1][2][1][RTW89_UK][1][103] = 127,
+ [1][1][2][1][RTW89_UK][0][103] = 127,
+ [1][1][2][1][RTW89_FCC][1][106] = 12,
+ [1][1][2][1][RTW89_FCC][2][106] = 127,
+ [1][1][2][1][RTW89_ETSI][1][106] = 127,
+ [1][1][2][1][RTW89_ETSI][0][106] = 127,
+ [1][1][2][1][RTW89_MKK][1][106] = 127,
+ [1][1][2][1][RTW89_MKK][0][106] = 127,
+ [1][1][2][1][RTW89_IC][1][106] = 12,
+ [1][1][2][1][RTW89_KCC][1][106] = 32,
+ [1][1][2][1][RTW89_KCC][0][106] = 127,
+ [1][1][2][1][RTW89_ACMA][1][106] = 127,
+ [1][1][2][1][RTW89_ACMA][0][106] = 127,
+ [1][1][2][1][RTW89_CHILE][1][106] = 12,
+ [1][1][2][1][RTW89_QATAR][1][106] = 127,
+ [1][1][2][1][RTW89_QATAR][0][106] = 127,
+ [1][1][2][1][RTW89_UK][1][106] = 127,
+ [1][1][2][1][RTW89_UK][0][106] = 127,
+ [1][1][2][1][RTW89_FCC][1][110] = 127,
+ [1][1][2][1][RTW89_FCC][2][110] = 127,
+ [1][1][2][1][RTW89_ETSI][1][110] = 127,
+ [1][1][2][1][RTW89_ETSI][0][110] = 127,
+ [1][1][2][1][RTW89_MKK][1][110] = 127,
+ [1][1][2][1][RTW89_MKK][0][110] = 127,
+ [1][1][2][1][RTW89_IC][1][110] = 127,
+ [1][1][2][1][RTW89_KCC][1][110] = 127,
+ [1][1][2][1][RTW89_KCC][0][110] = 127,
+ [1][1][2][1][RTW89_ACMA][1][110] = 127,
+ [1][1][2][1][RTW89_ACMA][0][110] = 127,
+ [1][1][2][1][RTW89_CHILE][1][110] = 127,
+ [1][1][2][1][RTW89_QATAR][1][110] = 127,
+ [1][1][2][1][RTW89_QATAR][0][110] = 127,
+ [1][1][2][1][RTW89_UK][1][110] = 127,
+ [1][1][2][1][RTW89_UK][0][110] = 127,
+ [1][1][2][1][RTW89_FCC][1][114] = 127,
+ [1][1][2][1][RTW89_FCC][2][114] = 127,
+ [1][1][2][1][RTW89_ETSI][1][114] = 127,
+ [1][1][2][1][RTW89_ETSI][0][114] = 127,
+ [1][1][2][1][RTW89_MKK][1][114] = 127,
+ [1][1][2][1][RTW89_MKK][0][114] = 127,
+ [1][1][2][1][RTW89_IC][1][114] = 127,
+ [1][1][2][1][RTW89_KCC][1][114] = 127,
+ [1][1][2][1][RTW89_KCC][0][114] = 127,
+ [1][1][2][1][RTW89_ACMA][1][114] = 127,
+ [1][1][2][1][RTW89_ACMA][0][114] = 127,
+ [1][1][2][1][RTW89_CHILE][1][114] = 127,
+ [1][1][2][1][RTW89_QATAR][1][114] = 127,
+ [1][1][2][1][RTW89_QATAR][0][114] = 127,
+ [1][1][2][1][RTW89_UK][1][114] = 127,
+ [1][1][2][1][RTW89_UK][0][114] = 127,
+ [1][1][2][1][RTW89_FCC][1][118] = 127,
+ [1][1][2][1][RTW89_FCC][2][118] = 127,
+ [1][1][2][1][RTW89_ETSI][1][118] = 127,
+ [1][1][2][1][RTW89_ETSI][0][118] = 127,
+ [1][1][2][1][RTW89_MKK][1][118] = 127,
+ [1][1][2][1][RTW89_MKK][0][118] = 127,
+ [1][1][2][1][RTW89_IC][1][118] = 127,
+ [1][1][2][1][RTW89_KCC][1][118] = 127,
+ [1][1][2][1][RTW89_KCC][0][118] = 127,
+ [1][1][2][1][RTW89_ACMA][1][118] = 127,
+ [1][1][2][1][RTW89_ACMA][0][118] = 127,
+ [1][1][2][1][RTW89_CHILE][1][118] = 127,
+ [1][1][2][1][RTW89_QATAR][1][118] = 127,
+ [1][1][2][1][RTW89_QATAR][0][118] = 127,
+ [1][1][2][1][RTW89_UK][1][118] = 127,
+ [1][1][2][1][RTW89_UK][0][118] = 127,
+ [2][0][2][0][RTW89_FCC][1][3] = 46,
+ [2][0][2][0][RTW89_FCC][2][3] = 60,
+ [2][0][2][0][RTW89_ETSI][1][3] = 58,
+ [2][0][2][0][RTW89_ETSI][0][3] = 30,
+ [2][0][2][0][RTW89_MKK][1][3] = 58,
+ [2][0][2][0][RTW89_MKK][0][3] = 26,
+ [2][0][2][0][RTW89_IC][1][3] = 46,
+ [2][0][2][0][RTW89_KCC][1][3] = 50,
+ [2][0][2][0][RTW89_KCC][0][3] = 24,
+ [2][0][2][0][RTW89_ACMA][1][3] = 58,
+ [2][0][2][0][RTW89_ACMA][0][3] = 30,
+ [2][0][2][0][RTW89_CHILE][1][3] = 46,
+ [2][0][2][0][RTW89_QATAR][1][3] = 58,
+ [2][0][2][0][RTW89_QATAR][0][3] = 30,
+ [2][0][2][0][RTW89_UK][1][3] = 58,
+ [2][0][2][0][RTW89_UK][0][3] = 30,
+ [2][0][2][0][RTW89_FCC][1][11] = 46,
+ [2][0][2][0][RTW89_FCC][2][11] = 60,
+ [2][0][2][0][RTW89_ETSI][1][11] = 58,
+ [2][0][2][0][RTW89_ETSI][0][11] = 30,
+ [2][0][2][0][RTW89_MKK][1][11] = 58,
+ [2][0][2][0][RTW89_MKK][0][11] = 24,
+ [2][0][2][0][RTW89_IC][1][11] = 46,
+ [2][0][2][0][RTW89_KCC][1][11] = 50,
+ [2][0][2][0][RTW89_KCC][0][11] = 24,
+ [2][0][2][0][RTW89_ACMA][1][11] = 58,
+ [2][0][2][0][RTW89_ACMA][0][11] = 30,
+ [2][0][2][0][RTW89_CHILE][1][11] = 46,
+ [2][0][2][0][RTW89_QATAR][1][11] = 58,
+ [2][0][2][0][RTW89_QATAR][0][11] = 30,
+ [2][0][2][0][RTW89_UK][1][11] = 58,
+ [2][0][2][0][RTW89_UK][0][11] = 30,
+ [2][0][2][0][RTW89_FCC][1][18] = 46,
+ [2][0][2][0][RTW89_FCC][2][18] = 60,
+ [2][0][2][0][RTW89_ETSI][1][18] = 58,
+ [2][0][2][0][RTW89_ETSI][0][18] = 30,
+ [2][0][2][0][RTW89_MKK][1][18] = 58,
+ [2][0][2][0][RTW89_MKK][0][18] = 24,
+ [2][0][2][0][RTW89_IC][1][18] = 46,
+ [2][0][2][0][RTW89_KCC][1][18] = 50,
+ [2][0][2][0][RTW89_KCC][0][18] = 24,
+ [2][0][2][0][RTW89_ACMA][1][18] = 58,
+ [2][0][2][0][RTW89_ACMA][0][18] = 30,
+ [2][0][2][0][RTW89_CHILE][1][18] = 46,
+ [2][0][2][0][RTW89_QATAR][1][18] = 58,
+ [2][0][2][0][RTW89_QATAR][0][18] = 30,
+ [2][0][2][0][RTW89_UK][1][18] = 58,
+ [2][0][2][0][RTW89_UK][0][18] = 30,
+ [2][0][2][0][RTW89_FCC][1][26] = 46,
+ [2][0][2][0][RTW89_FCC][2][26] = 60,
+ [2][0][2][0][RTW89_ETSI][1][26] = 58,
+ [2][0][2][0][RTW89_ETSI][0][26] = 30,
+ [2][0][2][0][RTW89_MKK][1][26] = 58,
+ [2][0][2][0][RTW89_MKK][0][26] = 24,
+ [2][0][2][0][RTW89_IC][1][26] = 46,
+ [2][0][2][0][RTW89_KCC][1][26] = 50,
+ [2][0][2][0][RTW89_KCC][0][26] = 26,
+ [2][0][2][0][RTW89_ACMA][1][26] = 58,
+ [2][0][2][0][RTW89_ACMA][0][26] = 30,
+ [2][0][2][0][RTW89_CHILE][1][26] = 46,
+ [2][0][2][0][RTW89_QATAR][1][26] = 58,
+ [2][0][2][0][RTW89_QATAR][0][26] = 30,
+ [2][0][2][0][RTW89_UK][1][26] = 58,
+ [2][0][2][0][RTW89_UK][0][26] = 30,
+ [2][0][2][0][RTW89_FCC][1][33] = 46,
+ [2][0][2][0][RTW89_FCC][2][33] = 60,
+ [2][0][2][0][RTW89_ETSI][1][33] = 58,
+ [2][0][2][0][RTW89_ETSI][0][33] = 30,
+ [2][0][2][0][RTW89_MKK][1][33] = 58,
+ [2][0][2][0][RTW89_MKK][0][33] = 24,
+ [2][0][2][0][RTW89_IC][1][33] = 46,
+ [2][0][2][0][RTW89_KCC][1][33] = 50,
+ [2][0][2][0][RTW89_KCC][0][33] = 24,
+ [2][0][2][0][RTW89_ACMA][1][33] = 58,
+ [2][0][2][0][RTW89_ACMA][0][33] = 30,
+ [2][0][2][0][RTW89_CHILE][1][33] = 46,
+ [2][0][2][0][RTW89_QATAR][1][33] = 58,
+ [2][0][2][0][RTW89_QATAR][0][33] = 30,
+ [2][0][2][0][RTW89_UK][1][33] = 58,
+ [2][0][2][0][RTW89_UK][0][33] = 30,
+ [2][0][2][0][RTW89_FCC][1][41] = 46,
+ [2][0][2][0][RTW89_FCC][2][41] = 60,
+ [2][0][2][0][RTW89_ETSI][1][41] = 58,
+ [2][0][2][0][RTW89_ETSI][0][41] = 30,
+ [2][0][2][0][RTW89_MKK][1][41] = 58,
+ [2][0][2][0][RTW89_MKK][0][41] = 24,
+ [2][0][2][0][RTW89_IC][1][41] = 46,
+ [2][0][2][0][RTW89_KCC][1][41] = 50,
+ [2][0][2][0][RTW89_KCC][0][41] = 24,
+ [2][0][2][0][RTW89_ACMA][1][41] = 58,
+ [2][0][2][0][RTW89_ACMA][0][41] = 30,
+ [2][0][2][0][RTW89_CHILE][1][41] = 46,
+ [2][0][2][0][RTW89_QATAR][1][41] = 58,
+ [2][0][2][0][RTW89_QATAR][0][41] = 30,
+ [2][0][2][0][RTW89_UK][1][41] = 58,
+ [2][0][2][0][RTW89_UK][0][41] = 30,
+ [2][0][2][0][RTW89_FCC][1][48] = 46,
+ [2][0][2][0][RTW89_FCC][2][48] = 127,
+ [2][0][2][0][RTW89_ETSI][1][48] = 127,
+ [2][0][2][0][RTW89_ETSI][0][48] = 127,
+ [2][0][2][0][RTW89_MKK][1][48] = 127,
+ [2][0][2][0][RTW89_MKK][0][48] = 127,
+ [2][0][2][0][RTW89_IC][1][48] = 46,
+ [2][0][2][0][RTW89_KCC][1][48] = 48,
+ [2][0][2][0][RTW89_KCC][0][48] = 127,
+ [2][0][2][0][RTW89_ACMA][1][48] = 127,
+ [2][0][2][0][RTW89_ACMA][0][48] = 127,
+ [2][0][2][0][RTW89_CHILE][1][48] = 46,
+ [2][0][2][0][RTW89_QATAR][1][48] = 127,
+ [2][0][2][0][RTW89_QATAR][0][48] = 127,
+ [2][0][2][0][RTW89_UK][1][48] = 127,
+ [2][0][2][0][RTW89_UK][0][48] = 127,
+ [2][0][2][0][RTW89_FCC][1][56] = 46,
+ [2][0][2][0][RTW89_FCC][2][56] = 127,
+ [2][0][2][0][RTW89_ETSI][1][56] = 127,
+ [2][0][2][0][RTW89_ETSI][0][56] = 127,
+ [2][0][2][0][RTW89_MKK][1][56] = 127,
+ [2][0][2][0][RTW89_MKK][0][56] = 127,
+ [2][0][2][0][RTW89_IC][1][56] = 46,
+ [2][0][2][0][RTW89_KCC][1][56] = 48,
+ [2][0][2][0][RTW89_KCC][0][56] = 127,
+ [2][0][2][0][RTW89_ACMA][1][56] = 127,
+ [2][0][2][0][RTW89_ACMA][0][56] = 127,
+ [2][0][2][0][RTW89_CHILE][1][56] = 46,
+ [2][0][2][0][RTW89_QATAR][1][56] = 127,
+ [2][0][2][0][RTW89_QATAR][0][56] = 127,
+ [2][0][2][0][RTW89_UK][1][56] = 127,
+ [2][0][2][0][RTW89_UK][0][56] = 127,
+ [2][0][2][0][RTW89_FCC][1][63] = 46,
+ [2][0][2][0][RTW89_FCC][2][63] = 58,
+ [2][0][2][0][RTW89_ETSI][1][63] = 127,
+ [2][0][2][0][RTW89_ETSI][0][63] = 127,
+ [2][0][2][0][RTW89_MKK][1][63] = 127,
+ [2][0][2][0][RTW89_MKK][0][63] = 127,
+ [2][0][2][0][RTW89_IC][1][63] = 46,
+ [2][0][2][0][RTW89_KCC][1][63] = 48,
+ [2][0][2][0][RTW89_KCC][0][63] = 127,
+ [2][0][2][0][RTW89_ACMA][1][63] = 127,
+ [2][0][2][0][RTW89_ACMA][0][63] = 127,
+ [2][0][2][0][RTW89_CHILE][1][63] = 46,
+ [2][0][2][0][RTW89_QATAR][1][63] = 127,
+ [2][0][2][0][RTW89_QATAR][0][63] = 127,
+ [2][0][2][0][RTW89_UK][1][63] = 127,
+ [2][0][2][0][RTW89_UK][0][63] = 127,
+ [2][0][2][0][RTW89_FCC][1][71] = 46,
+ [2][0][2][0][RTW89_FCC][2][71] = 58,
+ [2][0][2][0][RTW89_ETSI][1][71] = 127,
+ [2][0][2][0][RTW89_ETSI][0][71] = 127,
+ [2][0][2][0][RTW89_MKK][1][71] = 127,
+ [2][0][2][0][RTW89_MKK][0][71] = 127,
+ [2][0][2][0][RTW89_IC][1][71] = 46,
+ [2][0][2][0][RTW89_KCC][1][71] = 48,
+ [2][0][2][0][RTW89_KCC][0][71] = 127,
+ [2][0][2][0][RTW89_ACMA][1][71] = 127,
+ [2][0][2][0][RTW89_ACMA][0][71] = 127,
+ [2][0][2][0][RTW89_CHILE][1][71] = 46,
+ [2][0][2][0][RTW89_QATAR][1][71] = 127,
+ [2][0][2][0][RTW89_QATAR][0][71] = 127,
+ [2][0][2][0][RTW89_UK][1][71] = 127,
+ [2][0][2][0][RTW89_UK][0][71] = 127,
+ [2][0][2][0][RTW89_FCC][1][78] = 46,
+ [2][0][2][0][RTW89_FCC][2][78] = 58,
+ [2][0][2][0][RTW89_ETSI][1][78] = 127,
+ [2][0][2][0][RTW89_ETSI][0][78] = 127,
+ [2][0][2][0][RTW89_MKK][1][78] = 127,
+ [2][0][2][0][RTW89_MKK][0][78] = 127,
+ [2][0][2][0][RTW89_IC][1][78] = 46,
+ [2][0][2][0][RTW89_KCC][1][78] = 52,
+ [2][0][2][0][RTW89_KCC][0][78] = 127,
+ [2][0][2][0][RTW89_ACMA][1][78] = 127,
+ [2][0][2][0][RTW89_ACMA][0][78] = 127,
+ [2][0][2][0][RTW89_CHILE][1][78] = 46,
+ [2][0][2][0][RTW89_QATAR][1][78] = 127,
+ [2][0][2][0][RTW89_QATAR][0][78] = 127,
+ [2][0][2][0][RTW89_UK][1][78] = 127,
+ [2][0][2][0][RTW89_UK][0][78] = 127,
+ [2][0][2][0][RTW89_FCC][1][86] = 46,
+ [2][0][2][0][RTW89_FCC][2][86] = 127,
+ [2][0][2][0][RTW89_ETSI][1][86] = 127,
+ [2][0][2][0][RTW89_ETSI][0][86] = 127,
+ [2][0][2][0][RTW89_MKK][1][86] = 127,
+ [2][0][2][0][RTW89_MKK][0][86] = 127,
+ [2][0][2][0][RTW89_IC][1][86] = 46,
+ [2][0][2][0][RTW89_KCC][1][86] = 52,
+ [2][0][2][0][RTW89_KCC][0][86] = 127,
+ [2][0][2][0][RTW89_ACMA][1][86] = 127,
+ [2][0][2][0][RTW89_ACMA][0][86] = 127,
+ [2][0][2][0][RTW89_CHILE][1][86] = 46,
+ [2][0][2][0][RTW89_QATAR][1][86] = 127,
+ [2][0][2][0][RTW89_QATAR][0][86] = 127,
+ [2][0][2][0][RTW89_UK][1][86] = 127,
+ [2][0][2][0][RTW89_UK][0][86] = 127,
+ [2][0][2][0][RTW89_FCC][1][93] = 46,
+ [2][0][2][0][RTW89_FCC][2][93] = 127,
+ [2][0][2][0][RTW89_ETSI][1][93] = 127,
+ [2][0][2][0][RTW89_ETSI][0][93] = 127,
+ [2][0][2][0][RTW89_MKK][1][93] = 127,
+ [2][0][2][0][RTW89_MKK][0][93] = 127,
+ [2][0][2][0][RTW89_IC][1][93] = 46,
+ [2][0][2][0][RTW89_KCC][1][93] = 50,
+ [2][0][2][0][RTW89_KCC][0][93] = 127,
+ [2][0][2][0][RTW89_ACMA][1][93] = 127,
+ [2][0][2][0][RTW89_ACMA][0][93] = 127,
+ [2][0][2][0][RTW89_CHILE][1][93] = 46,
+ [2][0][2][0][RTW89_QATAR][1][93] = 127,
+ [2][0][2][0][RTW89_QATAR][0][93] = 127,
+ [2][0][2][0][RTW89_UK][1][93] = 127,
+ [2][0][2][0][RTW89_UK][0][93] = 127,
+ [2][0][2][0][RTW89_FCC][1][101] = 44,
+ [2][0][2][0][RTW89_FCC][2][101] = 127,
+ [2][0][2][0][RTW89_ETSI][1][101] = 127,
+ [2][0][2][0][RTW89_ETSI][0][101] = 127,
+ [2][0][2][0][RTW89_MKK][1][101] = 127,
+ [2][0][2][0][RTW89_MKK][0][101] = 127,
+ [2][0][2][0][RTW89_IC][1][101] = 44,
+ [2][0][2][0][RTW89_KCC][1][101] = 50,
+ [2][0][2][0][RTW89_KCC][0][101] = 127,
+ [2][0][2][0][RTW89_ACMA][1][101] = 127,
+ [2][0][2][0][RTW89_ACMA][0][101] = 127,
+ [2][0][2][0][RTW89_CHILE][1][101] = 44,
+ [2][0][2][0][RTW89_QATAR][1][101] = 127,
+ [2][0][2][0][RTW89_QATAR][0][101] = 127,
+ [2][0][2][0][RTW89_UK][1][101] = 127,
+ [2][0][2][0][RTW89_UK][0][101] = 127,
+ [2][0][2][0][RTW89_FCC][1][108] = 127,
+ [2][0][2][0][RTW89_FCC][2][108] = 127,
+ [2][0][2][0][RTW89_ETSI][1][108] = 127,
+ [2][0][2][0][RTW89_ETSI][0][108] = 127,
+ [2][0][2][0][RTW89_MKK][1][108] = 127,
+ [2][0][2][0][RTW89_MKK][0][108] = 127,
+ [2][0][2][0][RTW89_IC][1][108] = 127,
+ [2][0][2][0][RTW89_KCC][1][108] = 127,
+ [2][0][2][0][RTW89_KCC][0][108] = 127,
+ [2][0][2][0][RTW89_ACMA][1][108] = 127,
+ [2][0][2][0][RTW89_ACMA][0][108] = 127,
+ [2][0][2][0][RTW89_CHILE][1][108] = 127,
+ [2][0][2][0][RTW89_QATAR][1][108] = 127,
+ [2][0][2][0][RTW89_QATAR][0][108] = 127,
+ [2][0][2][0][RTW89_UK][1][108] = 127,
+ [2][0][2][0][RTW89_UK][0][108] = 127,
+ [2][0][2][0][RTW89_FCC][1][116] = 127,
+ [2][0][2][0][RTW89_FCC][2][116] = 127,
+ [2][0][2][0][RTW89_ETSI][1][116] = 127,
+ [2][0][2][0][RTW89_ETSI][0][116] = 127,
+ [2][0][2][0][RTW89_MKK][1][116] = 127,
+ [2][0][2][0][RTW89_MKK][0][116] = 127,
+ [2][0][2][0][RTW89_IC][1][116] = 127,
+ [2][0][2][0][RTW89_KCC][1][116] = 127,
+ [2][0][2][0][RTW89_KCC][0][116] = 127,
+ [2][0][2][0][RTW89_ACMA][1][116] = 127,
+ [2][0][2][0][RTW89_ACMA][0][116] = 127,
+ [2][0][2][0][RTW89_CHILE][1][116] = 127,
+ [2][0][2][0][RTW89_QATAR][1][116] = 127,
+ [2][0][2][0][RTW89_QATAR][0][116] = 127,
+ [2][0][2][0][RTW89_UK][1][116] = 127,
+ [2][0][2][0][RTW89_UK][0][116] = 127,
+ [2][1][2][0][RTW89_FCC][1][3] = 22,
+ [2][1][2][0][RTW89_FCC][2][3] = 50,
+ [2][1][2][0][RTW89_ETSI][1][3] = 54,
+ [2][1][2][0][RTW89_ETSI][0][3] = 16,
+ [2][1][2][0][RTW89_MKK][1][3] = 52,
+ [2][1][2][0][RTW89_MKK][0][3] = 14,
+ [2][1][2][0][RTW89_IC][1][3] = 22,
+ [2][1][2][0][RTW89_KCC][1][3] = 38,
+ [2][1][2][0][RTW89_KCC][0][3] = 12,
+ [2][1][2][0][RTW89_ACMA][1][3] = 54,
+ [2][1][2][0][RTW89_ACMA][0][3] = 16,
+ [2][1][2][0][RTW89_CHILE][1][3] = 22,
+ [2][1][2][0][RTW89_QATAR][1][3] = 54,
+ [2][1][2][0][RTW89_QATAR][0][3] = 16,
+ [2][1][2][0][RTW89_UK][1][3] = 54,
+ [2][1][2][0][RTW89_UK][0][3] = 16,
+ [2][1][2][0][RTW89_FCC][1][11] = 20,
+ [2][1][2][0][RTW89_FCC][2][11] = 50,
+ [2][1][2][0][RTW89_ETSI][1][11] = 54,
+ [2][1][2][0][RTW89_ETSI][0][11] = 16,
+ [2][1][2][0][RTW89_MKK][1][11] = 52,
+ [2][1][2][0][RTW89_MKK][0][11] = 12,
+ [2][1][2][0][RTW89_IC][1][11] = 20,
+ [2][1][2][0][RTW89_KCC][1][11] = 38,
+ [2][1][2][0][RTW89_KCC][0][11] = 12,
+ [2][1][2][0][RTW89_ACMA][1][11] = 54,
+ [2][1][2][0][RTW89_ACMA][0][11] = 16,
+ [2][1][2][0][RTW89_CHILE][1][11] = 20,
+ [2][1][2][0][RTW89_QATAR][1][11] = 54,
+ [2][1][2][0][RTW89_QATAR][0][11] = 16,
+ [2][1][2][0][RTW89_UK][1][11] = 54,
+ [2][1][2][0][RTW89_UK][0][11] = 16,
+ [2][1][2][0][RTW89_FCC][1][18] = 20,
+ [2][1][2][0][RTW89_FCC][2][18] = 50,
+ [2][1][2][0][RTW89_ETSI][1][18] = 54,
+ [2][1][2][0][RTW89_ETSI][0][18] = 16,
+ [2][1][2][0][RTW89_MKK][1][18] = 52,
+ [2][1][2][0][RTW89_MKK][0][18] = 12,
+ [2][1][2][0][RTW89_IC][1][18] = 20,
+ [2][1][2][0][RTW89_KCC][1][18] = 38,
+ [2][1][2][0][RTW89_KCC][0][18] = 12,
+ [2][1][2][0][RTW89_ACMA][1][18] = 54,
+ [2][1][2][0][RTW89_ACMA][0][18] = 16,
+ [2][1][2][0][RTW89_CHILE][1][18] = 20,
+ [2][1][2][0][RTW89_QATAR][1][18] = 54,
+ [2][1][2][0][RTW89_QATAR][0][18] = 16,
+ [2][1][2][0][RTW89_UK][1][18] = 54,
+ [2][1][2][0][RTW89_UK][0][18] = 16,
+ [2][1][2][0][RTW89_FCC][1][26] = 20,
+ [2][1][2][0][RTW89_FCC][2][26] = 60,
+ [2][1][2][0][RTW89_ETSI][1][26] = 54,
+ [2][1][2][0][RTW89_ETSI][0][26] = 16,
+ [2][1][2][0][RTW89_MKK][1][26] = 52,
+ [2][1][2][0][RTW89_MKK][0][26] = 12,
+ [2][1][2][0][RTW89_IC][1][26] = 20,
+ [2][1][2][0][RTW89_KCC][1][26] = 38,
+ [2][1][2][0][RTW89_KCC][0][26] = 12,
+ [2][1][2][0][RTW89_ACMA][1][26] = 54,
+ [2][1][2][0][RTW89_ACMA][0][26] = 16,
+ [2][1][2][0][RTW89_CHILE][1][26] = 20,
+ [2][1][2][0][RTW89_QATAR][1][26] = 54,
+ [2][1][2][0][RTW89_QATAR][0][26] = 16,
+ [2][1][2][0][RTW89_UK][1][26] = 54,
+ [2][1][2][0][RTW89_UK][0][26] = 16,
+ [2][1][2][0][RTW89_FCC][1][33] = 20,
+ [2][1][2][0][RTW89_FCC][2][33] = 60,
+ [2][1][2][0][RTW89_ETSI][1][33] = 54,
+ [2][1][2][0][RTW89_ETSI][0][33] = 16,
+ [2][1][2][0][RTW89_MKK][1][33] = 48,
+ [2][1][2][0][RTW89_MKK][0][33] = 12,
+ [2][1][2][0][RTW89_IC][1][33] = 20,
+ [2][1][2][0][RTW89_KCC][1][33] = 38,
+ [2][1][2][0][RTW89_KCC][0][33] = 12,
+ [2][1][2][0][RTW89_ACMA][1][33] = 54,
+ [2][1][2][0][RTW89_ACMA][0][33] = 16,
+ [2][1][2][0][RTW89_CHILE][1][33] = 20,
+ [2][1][2][0][RTW89_QATAR][1][33] = 54,
+ [2][1][2][0][RTW89_QATAR][0][33] = 16,
+ [2][1][2][0][RTW89_UK][1][33] = 54,
+ [2][1][2][0][RTW89_UK][0][33] = 16,
+ [2][1][2][0][RTW89_FCC][1][41] = 22,
+ [2][1][2][0][RTW89_FCC][2][41] = 60,
+ [2][1][2][0][RTW89_ETSI][1][41] = 54,
+ [2][1][2][0][RTW89_ETSI][0][41] = 18,
+ [2][1][2][0][RTW89_MKK][1][41] = 48,
+ [2][1][2][0][RTW89_MKK][0][41] = 12,
+ [2][1][2][0][RTW89_IC][1][41] = 22,
+ [2][1][2][0][RTW89_KCC][1][41] = 38,
+ [2][1][2][0][RTW89_KCC][0][41] = 12,
+ [2][1][2][0][RTW89_ACMA][1][41] = 54,
+ [2][1][2][0][RTW89_ACMA][0][41] = 18,
+ [2][1][2][0][RTW89_CHILE][1][41] = 22,
+ [2][1][2][0][RTW89_QATAR][1][41] = 54,
+ [2][1][2][0][RTW89_QATAR][0][41] = 18,
+ [2][1][2][0][RTW89_UK][1][41] = 54,
+ [2][1][2][0][RTW89_UK][0][41] = 18,
+ [2][1][2][0][RTW89_FCC][1][48] = 22,
+ [2][1][2][0][RTW89_FCC][2][48] = 127,
+ [2][1][2][0][RTW89_ETSI][1][48] = 127,
+ [2][1][2][0][RTW89_ETSI][0][48] = 127,
+ [2][1][2][0][RTW89_MKK][1][48] = 127,
+ [2][1][2][0][RTW89_MKK][0][48] = 127,
+ [2][1][2][0][RTW89_IC][1][48] = 22,
+ [2][1][2][0][RTW89_KCC][1][48] = 38,
+ [2][1][2][0][RTW89_KCC][0][48] = 127,
+ [2][1][2][0][RTW89_ACMA][1][48] = 127,
+ [2][1][2][0][RTW89_ACMA][0][48] = 127,
+ [2][1][2][0][RTW89_CHILE][1][48] = 22,
+ [2][1][2][0][RTW89_QATAR][1][48] = 127,
+ [2][1][2][0][RTW89_QATAR][0][48] = 127,
+ [2][1][2][0][RTW89_UK][1][48] = 127,
+ [2][1][2][0][RTW89_UK][0][48] = 127,
+ [2][1][2][0][RTW89_FCC][1][56] = 20,
+ [2][1][2][0][RTW89_FCC][2][56] = 127,
+ [2][1][2][0][RTW89_ETSI][1][56] = 127,
+ [2][1][2][0][RTW89_ETSI][0][56] = 127,
+ [2][1][2][0][RTW89_MKK][1][56] = 127,
+ [2][1][2][0][RTW89_MKK][0][56] = 127,
+ [2][1][2][0][RTW89_IC][1][56] = 20,
+ [2][1][2][0][RTW89_KCC][1][56] = 38,
+ [2][1][2][0][RTW89_KCC][0][56] = 127,
+ [2][1][2][0][RTW89_ACMA][1][56] = 127,
+ [2][1][2][0][RTW89_ACMA][0][56] = 127,
+ [2][1][2][0][RTW89_CHILE][1][56] = 20,
+ [2][1][2][0][RTW89_QATAR][1][56] = 127,
+ [2][1][2][0][RTW89_QATAR][0][56] = 127,
+ [2][1][2][0][RTW89_UK][1][56] = 127,
+ [2][1][2][0][RTW89_UK][0][56] = 127,
+ [2][1][2][0][RTW89_FCC][1][63] = 22,
+ [2][1][2][0][RTW89_FCC][2][63] = 58,
+ [2][1][2][0][RTW89_ETSI][1][63] = 127,
+ [2][1][2][0][RTW89_ETSI][0][63] = 127,
+ [2][1][2][0][RTW89_MKK][1][63] = 127,
+ [2][1][2][0][RTW89_MKK][0][63] = 127,
+ [2][1][2][0][RTW89_IC][1][63] = 22,
+ [2][1][2][0][RTW89_KCC][1][63] = 38,
+ [2][1][2][0][RTW89_KCC][0][63] = 127,
+ [2][1][2][0][RTW89_ACMA][1][63] = 127,
+ [2][1][2][0][RTW89_ACMA][0][63] = 127,
+ [2][1][2][0][RTW89_CHILE][1][63] = 22,
+ [2][1][2][0][RTW89_QATAR][1][63] = 127,
+ [2][1][2][0][RTW89_QATAR][0][63] = 127,
+ [2][1][2][0][RTW89_UK][1][63] = 127,
+ [2][1][2][0][RTW89_UK][0][63] = 127,
+ [2][1][2][0][RTW89_FCC][1][71] = 20,
+ [2][1][2][0][RTW89_FCC][2][71] = 58,
+ [2][1][2][0][RTW89_ETSI][1][71] = 127,
+ [2][1][2][0][RTW89_ETSI][0][71] = 127,
+ [2][1][2][0][RTW89_MKK][1][71] = 127,
+ [2][1][2][0][RTW89_MKK][0][71] = 127,
+ [2][1][2][0][RTW89_IC][1][71] = 20,
+ [2][1][2][0][RTW89_KCC][1][71] = 38,
+ [2][1][2][0][RTW89_KCC][0][71] = 127,
+ [2][1][2][0][RTW89_ACMA][1][71] = 127,
+ [2][1][2][0][RTW89_ACMA][0][71] = 127,
+ [2][1][2][0][RTW89_CHILE][1][71] = 20,
+ [2][1][2][0][RTW89_QATAR][1][71] = 127,
+ [2][1][2][0][RTW89_QATAR][0][71] = 127,
+ [2][1][2][0][RTW89_UK][1][71] = 127,
+ [2][1][2][0][RTW89_UK][0][71] = 127,
+ [2][1][2][0][RTW89_FCC][1][78] = 20,
+ [2][1][2][0][RTW89_FCC][2][78] = 58,
+ [2][1][2][0][RTW89_ETSI][1][78] = 127,
+ [2][1][2][0][RTW89_ETSI][0][78] = 127,
+ [2][1][2][0][RTW89_MKK][1][78] = 127,
+ [2][1][2][0][RTW89_MKK][0][78] = 127,
+ [2][1][2][0][RTW89_IC][1][78] = 20,
+ [2][1][2][0][RTW89_KCC][1][78] = 38,
+ [2][1][2][0][RTW89_KCC][0][78] = 127,
+ [2][1][2][0][RTW89_ACMA][1][78] = 127,
+ [2][1][2][0][RTW89_ACMA][0][78] = 127,
+ [2][1][2][0][RTW89_CHILE][1][78] = 20,
+ [2][1][2][0][RTW89_QATAR][1][78] = 127,
+ [2][1][2][0][RTW89_QATAR][0][78] = 127,
+ [2][1][2][0][RTW89_UK][1][78] = 127,
+ [2][1][2][0][RTW89_UK][0][78] = 127,
+ [2][1][2][0][RTW89_FCC][1][86] = 20,
+ [2][1][2][0][RTW89_FCC][2][86] = 127,
+ [2][1][2][0][RTW89_ETSI][1][86] = 127,
+ [2][1][2][0][RTW89_ETSI][0][86] = 127,
+ [2][1][2][0][RTW89_MKK][1][86] = 127,
+ [2][1][2][0][RTW89_MKK][0][86] = 127,
+ [2][1][2][0][RTW89_IC][1][86] = 20,
+ [2][1][2][0][RTW89_KCC][1][86] = 38,
+ [2][1][2][0][RTW89_KCC][0][86] = 127,
+ [2][1][2][0][RTW89_ACMA][1][86] = 127,
+ [2][1][2][0][RTW89_ACMA][0][86] = 127,
+ [2][1][2][0][RTW89_CHILE][1][86] = 20,
+ [2][1][2][0][RTW89_QATAR][1][86] = 127,
+ [2][1][2][0][RTW89_QATAR][0][86] = 127,
+ [2][1][2][0][RTW89_UK][1][86] = 127,
+ [2][1][2][0][RTW89_UK][0][86] = 127,
+ [2][1][2][0][RTW89_FCC][1][93] = 22,
+ [2][1][2][0][RTW89_FCC][2][93] = 127,
+ [2][1][2][0][RTW89_ETSI][1][93] = 127,
+ [2][1][2][0][RTW89_ETSI][0][93] = 127,
+ [2][1][2][0][RTW89_MKK][1][93] = 127,
+ [2][1][2][0][RTW89_MKK][0][93] = 127,
+ [2][1][2][0][RTW89_IC][1][93] = 22,
+ [2][1][2][0][RTW89_KCC][1][93] = 38,
+ [2][1][2][0][RTW89_KCC][0][93] = 127,
+ [2][1][2][0][RTW89_ACMA][1][93] = 127,
+ [2][1][2][0][RTW89_ACMA][0][93] = 127,
+ [2][1][2][0][RTW89_CHILE][1][93] = 22,
+ [2][1][2][0][RTW89_QATAR][1][93] = 127,
+ [2][1][2][0][RTW89_QATAR][0][93] = 127,
+ [2][1][2][0][RTW89_UK][1][93] = 127,
+ [2][1][2][0][RTW89_UK][0][93] = 127,
+ [2][1][2][0][RTW89_FCC][1][101] = 22,
+ [2][1][2][0][RTW89_FCC][2][101] = 127,
+ [2][1][2][0][RTW89_ETSI][1][101] = 127,
+ [2][1][2][0][RTW89_ETSI][0][101] = 127,
+ [2][1][2][0][RTW89_MKK][1][101] = 127,
+ [2][1][2][0][RTW89_MKK][0][101] = 127,
+ [2][1][2][0][RTW89_IC][1][101] = 22,
+ [2][1][2][0][RTW89_KCC][1][101] = 38,
+ [2][1][2][0][RTW89_KCC][0][101] = 127,
+ [2][1][2][0][RTW89_ACMA][1][101] = 127,
+ [2][1][2][0][RTW89_ACMA][0][101] = 127,
+ [2][1][2][0][RTW89_CHILE][1][101] = 22,
+ [2][1][2][0][RTW89_QATAR][1][101] = 127,
+ [2][1][2][0][RTW89_QATAR][0][101] = 127,
+ [2][1][2][0][RTW89_UK][1][101] = 127,
+ [2][1][2][0][RTW89_UK][0][101] = 127,
+ [2][1][2][0][RTW89_FCC][1][108] = 127,
+ [2][1][2][0][RTW89_FCC][2][108] = 127,
+ [2][1][2][0][RTW89_ETSI][1][108] = 127,
+ [2][1][2][0][RTW89_ETSI][0][108] = 127,
+ [2][1][2][0][RTW89_MKK][1][108] = 127,
+ [2][1][2][0][RTW89_MKK][0][108] = 127,
+ [2][1][2][0][RTW89_IC][1][108] = 127,
+ [2][1][2][0][RTW89_KCC][1][108] = 127,
+ [2][1][2][0][RTW89_KCC][0][108] = 127,
+ [2][1][2][0][RTW89_ACMA][1][108] = 127,
+ [2][1][2][0][RTW89_ACMA][0][108] = 127,
+ [2][1][2][0][RTW89_CHILE][1][108] = 127,
+ [2][1][2][0][RTW89_QATAR][1][108] = 127,
+ [2][1][2][0][RTW89_QATAR][0][108] = 127,
+ [2][1][2][0][RTW89_UK][1][108] = 127,
+ [2][1][2][0][RTW89_UK][0][108] = 127,
+ [2][1][2][0][RTW89_FCC][1][116] = 127,
+ [2][1][2][0][RTW89_FCC][2][116] = 127,
+ [2][1][2][0][RTW89_ETSI][1][116] = 127,
+ [2][1][2][0][RTW89_ETSI][0][116] = 127,
+ [2][1][2][0][RTW89_MKK][1][116] = 127,
+ [2][1][2][0][RTW89_MKK][0][116] = 127,
+ [2][1][2][0][RTW89_IC][1][116] = 127,
+ [2][1][2][0][RTW89_KCC][1][116] = 127,
+ [2][1][2][0][RTW89_KCC][0][116] = 127,
+ [2][1][2][0][RTW89_ACMA][1][116] = 127,
+ [2][1][2][0][RTW89_ACMA][0][116] = 127,
+ [2][1][2][0][RTW89_CHILE][1][116] = 127,
+ [2][1][2][0][RTW89_QATAR][1][116] = 127,
+ [2][1][2][0][RTW89_QATAR][0][116] = 127,
+ [2][1][2][0][RTW89_UK][1][116] = 127,
+ [2][1][2][0][RTW89_UK][0][116] = 127,
+ [2][1][2][1][RTW89_FCC][1][3] = 22,
+ [2][1][2][1][RTW89_FCC][2][3] = 50,
+ [2][1][2][1][RTW89_ETSI][1][3] = 42,
+ [2][1][2][1][RTW89_ETSI][0][3] = 6,
+ [2][1][2][1][RTW89_MKK][1][3] = 52,
+ [2][1][2][1][RTW89_MKK][0][3] = 14,
+ [2][1][2][1][RTW89_IC][1][3] = 22,
+ [2][1][2][1][RTW89_KCC][1][3] = 38,
+ [2][1][2][1][RTW89_KCC][0][3] = 12,
+ [2][1][2][1][RTW89_ACMA][1][3] = 42,
+ [2][1][2][1][RTW89_ACMA][0][3] = 6,
+ [2][1][2][1][RTW89_CHILE][1][3] = 22,
+ [2][1][2][1][RTW89_QATAR][1][3] = 42,
+ [2][1][2][1][RTW89_QATAR][0][3] = 6,
+ [2][1][2][1][RTW89_UK][1][3] = 42,
+ [2][1][2][1][RTW89_UK][0][3] = 6,
+ [2][1][2][1][RTW89_FCC][1][11] = 20,
+ [2][1][2][1][RTW89_FCC][2][11] = 50,
+ [2][1][2][1][RTW89_ETSI][1][11] = 42,
+ [2][1][2][1][RTW89_ETSI][0][11] = 6,
+ [2][1][2][1][RTW89_MKK][1][11] = 52,
+ [2][1][2][1][RTW89_MKK][0][11] = 12,
+ [2][1][2][1][RTW89_IC][1][11] = 20,
+ [2][1][2][1][RTW89_KCC][1][11] = 38,
+ [2][1][2][1][RTW89_KCC][0][11] = 12,
+ [2][1][2][1][RTW89_ACMA][1][11] = 42,
+ [2][1][2][1][RTW89_ACMA][0][11] = 6,
+ [2][1][2][1][RTW89_CHILE][1][11] = 20,
+ [2][1][2][1][RTW89_QATAR][1][11] = 42,
+ [2][1][2][1][RTW89_QATAR][0][11] = 6,
+ [2][1][2][1][RTW89_UK][1][11] = 42,
+ [2][1][2][1][RTW89_UK][0][11] = 6,
+ [2][1][2][1][RTW89_FCC][1][18] = 20,
+ [2][1][2][1][RTW89_FCC][2][18] = 50,
+ [2][1][2][1][RTW89_ETSI][1][18] = 42,
+ [2][1][2][1][RTW89_ETSI][0][18] = 6,
+ [2][1][2][1][RTW89_MKK][1][18] = 52,
+ [2][1][2][1][RTW89_MKK][0][18] = 12,
+ [2][1][2][1][RTW89_IC][1][18] = 20,
+ [2][1][2][1][RTW89_KCC][1][18] = 38,
+ [2][1][2][1][RTW89_KCC][0][18] = 12,
+ [2][1][2][1][RTW89_ACMA][1][18] = 42,
+ [2][1][2][1][RTW89_ACMA][0][18] = 6,
+ [2][1][2][1][RTW89_CHILE][1][18] = 20,
+ [2][1][2][1][RTW89_QATAR][1][18] = 42,
+ [2][1][2][1][RTW89_QATAR][0][18] = 6,
+ [2][1][2][1][RTW89_UK][1][18] = 42,
+ [2][1][2][1][RTW89_UK][0][18] = 6,
+ [2][1][2][1][RTW89_FCC][1][26] = 20,
+ [2][1][2][1][RTW89_FCC][2][26] = 60,
+ [2][1][2][1][RTW89_ETSI][1][26] = 42,
+ [2][1][2][1][RTW89_ETSI][0][26] = 6,
+ [2][1][2][1][RTW89_MKK][1][26] = 52,
+ [2][1][2][1][RTW89_MKK][0][26] = 12,
+ [2][1][2][1][RTW89_IC][1][26] = 20,
+ [2][1][2][1][RTW89_KCC][1][26] = 38,
+ [2][1][2][1][RTW89_KCC][0][26] = 12,
+ [2][1][2][1][RTW89_ACMA][1][26] = 42,
+ [2][1][2][1][RTW89_ACMA][0][26] = 6,
+ [2][1][2][1][RTW89_CHILE][1][26] = 20,
+ [2][1][2][1][RTW89_QATAR][1][26] = 42,
+ [2][1][2][1][RTW89_QATAR][0][26] = 6,
+ [2][1][2][1][RTW89_UK][1][26] = 42,
+ [2][1][2][1][RTW89_UK][0][26] = 6,
+ [2][1][2][1][RTW89_FCC][1][33] = 20,
+ [2][1][2][1][RTW89_FCC][2][33] = 60,
+ [2][1][2][1][RTW89_ETSI][1][33] = 42,
+ [2][1][2][1][RTW89_ETSI][0][33] = 6,
+ [2][1][2][1][RTW89_MKK][1][33] = 48,
+ [2][1][2][1][RTW89_MKK][0][33] = 12,
+ [2][1][2][1][RTW89_IC][1][33] = 20,
+ [2][1][2][1][RTW89_KCC][1][33] = 38,
+ [2][1][2][1][RTW89_KCC][0][33] = 12,
+ [2][1][2][1][RTW89_ACMA][1][33] = 42,
+ [2][1][2][1][RTW89_ACMA][0][33] = 6,
+ [2][1][2][1][RTW89_CHILE][1][33] = 20,
+ [2][1][2][1][RTW89_QATAR][1][33] = 42,
+ [2][1][2][1][RTW89_QATAR][0][33] = 6,
+ [2][1][2][1][RTW89_UK][1][33] = 42,
+ [2][1][2][1][RTW89_UK][0][33] = 6,
+ [2][1][2][1][RTW89_FCC][1][41] = 22,
+ [2][1][2][1][RTW89_FCC][2][41] = 60,
+ [2][1][2][1][RTW89_ETSI][1][41] = 42,
+ [2][1][2][1][RTW89_ETSI][0][41] = 6,
+ [2][1][2][1][RTW89_MKK][1][41] = 48,
+ [2][1][2][1][RTW89_MKK][0][41] = 12,
+ [2][1][2][1][RTW89_IC][1][41] = 22,
+ [2][1][2][1][RTW89_KCC][1][41] = 38,
+ [2][1][2][1][RTW89_KCC][0][41] = 12,
+ [2][1][2][1][RTW89_ACMA][1][41] = 42,
+ [2][1][2][1][RTW89_ACMA][0][41] = 6,
+ [2][1][2][1][RTW89_CHILE][1][41] = 22,
+ [2][1][2][1][RTW89_QATAR][1][41] = 42,
+ [2][1][2][1][RTW89_QATAR][0][41] = 6,
+ [2][1][2][1][RTW89_UK][1][41] = 42,
+ [2][1][2][1][RTW89_UK][0][41] = 6,
+ [2][1][2][1][RTW89_FCC][1][48] = 22,
+ [2][1][2][1][RTW89_FCC][2][48] = 127,
+ [2][1][2][1][RTW89_ETSI][1][48] = 127,
+ [2][1][2][1][RTW89_ETSI][0][48] = 127,
+ [2][1][2][1][RTW89_MKK][1][48] = 127,
+ [2][1][2][1][RTW89_MKK][0][48] = 127,
+ [2][1][2][1][RTW89_IC][1][48] = 22,
+ [2][1][2][1][RTW89_KCC][1][48] = 38,
+ [2][1][2][1][RTW89_KCC][0][48] = 127,
+ [2][1][2][1][RTW89_ACMA][1][48] = 127,
+ [2][1][2][1][RTW89_ACMA][0][48] = 127,
+ [2][1][2][1][RTW89_CHILE][1][48] = 22,
+ [2][1][2][1][RTW89_QATAR][1][48] = 127,
+ [2][1][2][1][RTW89_QATAR][0][48] = 127,
+ [2][1][2][1][RTW89_UK][1][48] = 127,
+ [2][1][2][1][RTW89_UK][0][48] = 127,
+ [2][1][2][1][RTW89_FCC][1][56] = 20,
+ [2][1][2][1][RTW89_FCC][2][56] = 127,
+ [2][1][2][1][RTW89_ETSI][1][56] = 127,
+ [2][1][2][1][RTW89_ETSI][0][56] = 127,
+ [2][1][2][1][RTW89_MKK][1][56] = 127,
+ [2][1][2][1][RTW89_MKK][0][56] = 127,
+ [2][1][2][1][RTW89_IC][1][56] = 20,
+ [2][1][2][1][RTW89_KCC][1][56] = 38,
+ [2][1][2][1][RTW89_KCC][0][56] = 127,
+ [2][1][2][1][RTW89_ACMA][1][56] = 127,
+ [2][1][2][1][RTW89_ACMA][0][56] = 127,
+ [2][1][2][1][RTW89_CHILE][1][56] = 20,
+ [2][1][2][1][RTW89_QATAR][1][56] = 127,
+ [2][1][2][1][RTW89_QATAR][0][56] = 127,
+ [2][1][2][1][RTW89_UK][1][56] = 127,
+ [2][1][2][1][RTW89_UK][0][56] = 127,
+ [2][1][2][1][RTW89_FCC][1][63] = 22,
+ [2][1][2][1][RTW89_FCC][2][63] = 58,
+ [2][1][2][1][RTW89_ETSI][1][63] = 127,
+ [2][1][2][1][RTW89_ETSI][0][63] = 127,
+ [2][1][2][1][RTW89_MKK][1][63] = 127,
+ [2][1][2][1][RTW89_MKK][0][63] = 127,
+ [2][1][2][1][RTW89_IC][1][63] = 22,
+ [2][1][2][1][RTW89_KCC][1][63] = 38,
+ [2][1][2][1][RTW89_KCC][0][63] = 127,
+ [2][1][2][1][RTW89_ACMA][1][63] = 127,
+ [2][1][2][1][RTW89_ACMA][0][63] = 127,
+ [2][1][2][1][RTW89_CHILE][1][63] = 22,
+ [2][1][2][1][RTW89_QATAR][1][63] = 127,
+ [2][1][2][1][RTW89_QATAR][0][63] = 127,
+ [2][1][2][1][RTW89_UK][1][63] = 127,
+ [2][1][2][1][RTW89_UK][0][63] = 127,
+ [2][1][2][1][RTW89_FCC][1][71] = 20,
+ [2][1][2][1][RTW89_FCC][2][71] = 58,
+ [2][1][2][1][RTW89_ETSI][1][71] = 127,
+ [2][1][2][1][RTW89_ETSI][0][71] = 127,
+ [2][1][2][1][RTW89_MKK][1][71] = 127,
+ [2][1][2][1][RTW89_MKK][0][71] = 127,
+ [2][1][2][1][RTW89_IC][1][71] = 20,
+ [2][1][2][1][RTW89_KCC][1][71] = 38,
+ [2][1][2][1][RTW89_KCC][0][71] = 127,
+ [2][1][2][1][RTW89_ACMA][1][71] = 127,
+ [2][1][2][1][RTW89_ACMA][0][71] = 127,
+ [2][1][2][1][RTW89_CHILE][1][71] = 20,
+ [2][1][2][1][RTW89_QATAR][1][71] = 127,
+ [2][1][2][1][RTW89_QATAR][0][71] = 127,
+ [2][1][2][1][RTW89_UK][1][71] = 127,
+ [2][1][2][1][RTW89_UK][0][71] = 127,
+ [2][1][2][1][RTW89_FCC][1][78] = 20,
+ [2][1][2][1][RTW89_FCC][2][78] = 58,
+ [2][1][2][1][RTW89_ETSI][1][78] = 127,
+ [2][1][2][1][RTW89_ETSI][0][78] = 127,
+ [2][1][2][1][RTW89_MKK][1][78] = 127,
+ [2][1][2][1][RTW89_MKK][0][78] = 127,
+ [2][1][2][1][RTW89_IC][1][78] = 20,
+ [2][1][2][1][RTW89_KCC][1][78] = 38,
+ [2][1][2][1][RTW89_KCC][0][78] = 127,
+ [2][1][2][1][RTW89_ACMA][1][78] = 127,
+ [2][1][2][1][RTW89_ACMA][0][78] = 127,
+ [2][1][2][1][RTW89_CHILE][1][78] = 20,
+ [2][1][2][1][RTW89_QATAR][1][78] = 127,
+ [2][1][2][1][RTW89_QATAR][0][78] = 127,
+ [2][1][2][1][RTW89_UK][1][78] = 127,
+ [2][1][2][1][RTW89_UK][0][78] = 127,
+ [2][1][2][1][RTW89_FCC][1][86] = 20,
+ [2][1][2][1][RTW89_FCC][2][86] = 127,
+ [2][1][2][1][RTW89_ETSI][1][86] = 127,
+ [2][1][2][1][RTW89_ETSI][0][86] = 127,
+ [2][1][2][1][RTW89_MKK][1][86] = 127,
+ [2][1][2][1][RTW89_MKK][0][86] = 127,
+ [2][1][2][1][RTW89_IC][1][86] = 20,
+ [2][1][2][1][RTW89_KCC][1][86] = 38,
+ [2][1][2][1][RTW89_KCC][0][86] = 127,
+ [2][1][2][1][RTW89_ACMA][1][86] = 127,
+ [2][1][2][1][RTW89_ACMA][0][86] = 127,
+ [2][1][2][1][RTW89_CHILE][1][86] = 20,
+ [2][1][2][1][RTW89_QATAR][1][86] = 127,
+ [2][1][2][1][RTW89_QATAR][0][86] = 127,
+ [2][1][2][1][RTW89_UK][1][86] = 127,
+ [2][1][2][1][RTW89_UK][0][86] = 127,
+ [2][1][2][1][RTW89_FCC][1][93] = 22,
+ [2][1][2][1][RTW89_FCC][2][93] = 127,
+ [2][1][2][1][RTW89_ETSI][1][93] = 127,
+ [2][1][2][1][RTW89_ETSI][0][93] = 127,
+ [2][1][2][1][RTW89_MKK][1][93] = 127,
+ [2][1][2][1][RTW89_MKK][0][93] = 127,
+ [2][1][2][1][RTW89_IC][1][93] = 22,
+ [2][1][2][1][RTW89_KCC][1][93] = 38,
+ [2][1][2][1][RTW89_KCC][0][93] = 127,
+ [2][1][2][1][RTW89_ACMA][1][93] = 127,
+ [2][1][2][1][RTW89_ACMA][0][93] = 127,
+ [2][1][2][1][RTW89_CHILE][1][93] = 22,
+ [2][1][2][1][RTW89_QATAR][1][93] = 127,
+ [2][1][2][1][RTW89_QATAR][0][93] = 127,
+ [2][1][2][1][RTW89_UK][1][93] = 127,
+ [2][1][2][1][RTW89_UK][0][93] = 127,
+ [2][1][2][1][RTW89_FCC][1][101] = 22,
+ [2][1][2][1][RTW89_FCC][2][101] = 127,
+ [2][1][2][1][RTW89_ETSI][1][101] = 127,
+ [2][1][2][1][RTW89_ETSI][0][101] = 127,
+ [2][1][2][1][RTW89_MKK][1][101] = 127,
+ [2][1][2][1][RTW89_MKK][0][101] = 127,
+ [2][1][2][1][RTW89_IC][1][101] = 22,
+ [2][1][2][1][RTW89_KCC][1][101] = 38,
+ [2][1][2][1][RTW89_KCC][0][101] = 127,
+ [2][1][2][1][RTW89_ACMA][1][101] = 127,
+ [2][1][2][1][RTW89_ACMA][0][101] = 127,
+ [2][1][2][1][RTW89_CHILE][1][101] = 22,
+ [2][1][2][1][RTW89_QATAR][1][101] = 127,
+ [2][1][2][1][RTW89_QATAR][0][101] = 127,
+ [2][1][2][1][RTW89_UK][1][101] = 127,
+ [2][1][2][1][RTW89_UK][0][101] = 127,
+ [2][1][2][1][RTW89_FCC][1][108] = 127,
+ [2][1][2][1][RTW89_FCC][2][108] = 127,
+ [2][1][2][1][RTW89_ETSI][1][108] = 127,
+ [2][1][2][1][RTW89_ETSI][0][108] = 127,
+ [2][1][2][1][RTW89_MKK][1][108] = 127,
+ [2][1][2][1][RTW89_MKK][0][108] = 127,
+ [2][1][2][1][RTW89_IC][1][108] = 127,
+ [2][1][2][1][RTW89_KCC][1][108] = 127,
+ [2][1][2][1][RTW89_KCC][0][108] = 127,
+ [2][1][2][1][RTW89_ACMA][1][108] = 127,
+ [2][1][2][1][RTW89_ACMA][0][108] = 127,
+ [2][1][2][1][RTW89_CHILE][1][108] = 127,
+ [2][1][2][1][RTW89_QATAR][1][108] = 127,
+ [2][1][2][1][RTW89_QATAR][0][108] = 127,
+ [2][1][2][1][RTW89_UK][1][108] = 127,
+ [2][1][2][1][RTW89_UK][0][108] = 127,
+ [2][1][2][1][RTW89_FCC][1][116] = 127,
+ [2][1][2][1][RTW89_FCC][2][116] = 127,
+ [2][1][2][1][RTW89_ETSI][1][116] = 127,
+ [2][1][2][1][RTW89_ETSI][0][116] = 127,
+ [2][1][2][1][RTW89_MKK][1][116] = 127,
+ [2][1][2][1][RTW89_MKK][0][116] = 127,
+ [2][1][2][1][RTW89_IC][1][116] = 127,
+ [2][1][2][1][RTW89_KCC][1][116] = 127,
+ [2][1][2][1][RTW89_KCC][0][116] = 127,
+ [2][1][2][1][RTW89_ACMA][1][116] = 127,
+ [2][1][2][1][RTW89_ACMA][0][116] = 127,
+ [2][1][2][1][RTW89_CHILE][1][116] = 127,
+ [2][1][2][1][RTW89_QATAR][1][116] = 127,
+ [2][1][2][1][RTW89_QATAR][0][116] = 127,
+ [2][1][2][1][RTW89_UK][1][116] = 127,
+ [2][1][2][1][RTW89_UK][0][116] = 127,
+ [3][0][2][0][RTW89_FCC][1][7] = 52,
+ [3][0][2][0][RTW89_FCC][2][7] = 52,
+ [3][0][2][0][RTW89_ETSI][1][7] = 50,
+ [3][0][2][0][RTW89_ETSI][0][7] = 30,
+ [3][0][2][0][RTW89_MKK][1][7] = 50,
+ [3][0][2][0][RTW89_MKK][0][7] = 22,
+ [3][0][2][0][RTW89_IC][1][7] = 52,
+ [3][0][2][0][RTW89_KCC][1][7] = 42,
+ [3][0][2][0][RTW89_KCC][0][7] = 24,
+ [3][0][2][0][RTW89_ACMA][1][7] = 50,
+ [3][0][2][0][RTW89_ACMA][0][7] = 30,
+ [3][0][2][0][RTW89_CHILE][1][7] = 52,
+ [3][0][2][0][RTW89_QATAR][1][7] = 50,
+ [3][0][2][0][RTW89_QATAR][0][7] = 30,
+ [3][0][2][0][RTW89_UK][1][7] = 50,
+ [3][0][2][0][RTW89_UK][0][7] = 30,
+ [3][0][2][0][RTW89_FCC][1][22] = 52,
+ [3][0][2][0][RTW89_FCC][2][22] = 52,
+ [3][0][2][0][RTW89_ETSI][1][22] = 50,
+ [3][0][2][0][RTW89_ETSI][0][22] = 30,
+ [3][0][2][0][RTW89_MKK][1][22] = 50,
+ [3][0][2][0][RTW89_MKK][0][22] = 20,
+ [3][0][2][0][RTW89_IC][1][22] = 52,
+ [3][0][2][0][RTW89_KCC][1][22] = 42,
+ [3][0][2][0][RTW89_KCC][0][22] = 24,
+ [3][0][2][0][RTW89_ACMA][1][22] = 50,
+ [3][0][2][0][RTW89_ACMA][0][22] = 30,
+ [3][0][2][0][RTW89_CHILE][1][22] = 52,
+ [3][0][2][0][RTW89_QATAR][1][22] = 50,
+ [3][0][2][0][RTW89_QATAR][0][22] = 30,
+ [3][0][2][0][RTW89_UK][1][22] = 50,
+ [3][0][2][0][RTW89_UK][0][22] = 30,
+ [3][0][2][0][RTW89_FCC][1][37] = 52,
+ [3][0][2][0][RTW89_FCC][2][37] = 52,
+ [3][0][2][0][RTW89_ETSI][1][37] = 50,
+ [3][0][2][0][RTW89_ETSI][0][37] = 30,
+ [3][0][2][0][RTW89_MKK][1][37] = 50,
+ [3][0][2][0][RTW89_MKK][0][37] = 20,
+ [3][0][2][0][RTW89_IC][1][37] = 52,
+ [3][0][2][0][RTW89_KCC][1][37] = 42,
+ [3][0][2][0][RTW89_KCC][0][37] = 24,
+ [3][0][2][0][RTW89_ACMA][1][37] = 50,
+ [3][0][2][0][RTW89_ACMA][0][37] = 30,
+ [3][0][2][0][RTW89_CHILE][1][37] = 52,
+ [3][0][2][0][RTW89_QATAR][1][37] = 50,
+ [3][0][2][0][RTW89_QATAR][0][37] = 30,
+ [3][0][2][0][RTW89_UK][1][37] = 50,
+ [3][0][2][0][RTW89_UK][0][37] = 30,
+ [3][0][2][0][RTW89_FCC][1][52] = 54,
+ [3][0][2][0][RTW89_FCC][2][52] = 127,
+ [3][0][2][0][RTW89_ETSI][1][52] = 127,
+ [3][0][2][0][RTW89_ETSI][0][52] = 127,
+ [3][0][2][0][RTW89_MKK][1][52] = 127,
+ [3][0][2][0][RTW89_MKK][0][52] = 127,
+ [3][0][2][0][RTW89_IC][1][52] = 54,
+ [3][0][2][0][RTW89_KCC][1][52] = 56,
+ [3][0][2][0][RTW89_KCC][0][52] = 127,
+ [3][0][2][0][RTW89_ACMA][1][52] = 127,
+ [3][0][2][0][RTW89_ACMA][0][52] = 127,
+ [3][0][2][0][RTW89_CHILE][1][52] = 54,
+ [3][0][2][0][RTW89_QATAR][1][52] = 127,
+ [3][0][2][0][RTW89_QATAR][0][52] = 127,
+ [3][0][2][0][RTW89_UK][1][52] = 127,
+ [3][0][2][0][RTW89_UK][0][52] = 127,
+ [3][0][2][0][RTW89_FCC][1][67] = 54,
+ [3][0][2][0][RTW89_FCC][2][67] = 54,
+ [3][0][2][0][RTW89_ETSI][1][67] = 127,
+ [3][0][2][0][RTW89_ETSI][0][67] = 127,
+ [3][0][2][0][RTW89_MKK][1][67] = 127,
+ [3][0][2][0][RTW89_MKK][0][67] = 127,
+ [3][0][2][0][RTW89_IC][1][67] = 54,
+ [3][0][2][0][RTW89_KCC][1][67] = 54,
+ [3][0][2][0][RTW89_KCC][0][67] = 127,
+ [3][0][2][0][RTW89_ACMA][1][67] = 127,
+ [3][0][2][0][RTW89_ACMA][0][67] = 127,
+ [3][0][2][0][RTW89_CHILE][1][67] = 54,
+ [3][0][2][0][RTW89_QATAR][1][67] = 127,
+ [3][0][2][0][RTW89_QATAR][0][67] = 127,
+ [3][0][2][0][RTW89_UK][1][67] = 127,
+ [3][0][2][0][RTW89_UK][0][67] = 127,
+ [3][0][2][0][RTW89_FCC][1][82] = 46,
+ [3][0][2][0][RTW89_FCC][2][82] = 127,
+ [3][0][2][0][RTW89_ETSI][1][82] = 127,
+ [3][0][2][0][RTW89_ETSI][0][82] = 127,
+ [3][0][2][0][RTW89_MKK][1][82] = 127,
+ [3][0][2][0][RTW89_MKK][0][82] = 127,
+ [3][0][2][0][RTW89_IC][1][82] = 46,
+ [3][0][2][0][RTW89_KCC][1][82] = 26,
+ [3][0][2][0][RTW89_KCC][0][82] = 127,
+ [3][0][2][0][RTW89_ACMA][1][82] = 127,
+ [3][0][2][0][RTW89_ACMA][0][82] = 127,
+ [3][0][2][0][RTW89_CHILE][1][82] = 46,
+ [3][0][2][0][RTW89_QATAR][1][82] = 127,
+ [3][0][2][0][RTW89_QATAR][0][82] = 127,
+ [3][0][2][0][RTW89_UK][1][82] = 127,
+ [3][0][2][0][RTW89_UK][0][82] = 127,
+ [3][0][2][0][RTW89_FCC][1][97] = 40,
+ [3][0][2][0][RTW89_FCC][2][97] = 127,
+ [3][0][2][0][RTW89_ETSI][1][97] = 127,
+ [3][0][2][0][RTW89_ETSI][0][97] = 127,
+ [3][0][2][0][RTW89_MKK][1][97] = 127,
+ [3][0][2][0][RTW89_MKK][0][97] = 127,
+ [3][0][2][0][RTW89_IC][1][97] = 40,
+ [3][0][2][0][RTW89_KCC][1][97] = 26,
+ [3][0][2][0][RTW89_KCC][0][97] = 127,
+ [3][0][2][0][RTW89_ACMA][1][97] = 127,
+ [3][0][2][0][RTW89_ACMA][0][97] = 127,
+ [3][0][2][0][RTW89_CHILE][1][97] = 40,
+ [3][0][2][0][RTW89_QATAR][1][97] = 127,
+ [3][0][2][0][RTW89_QATAR][0][97] = 127,
+ [3][0][2][0][RTW89_UK][1][97] = 127,
+ [3][0][2][0][RTW89_UK][0][97] = 127,
+ [3][0][2][0][RTW89_FCC][1][112] = 127,
+ [3][0][2][0][RTW89_FCC][2][112] = 127,
+ [3][0][2][0][RTW89_ETSI][1][112] = 127,
+ [3][0][2][0][RTW89_ETSI][0][112] = 127,
+ [3][0][2][0][RTW89_MKK][1][112] = 127,
+ [3][0][2][0][RTW89_MKK][0][112] = 127,
+ [3][0][2][0][RTW89_IC][1][112] = 127,
+ [3][0][2][0][RTW89_KCC][1][112] = 127,
+ [3][0][2][0][RTW89_KCC][0][112] = 127,
+ [3][0][2][0][RTW89_ACMA][1][112] = 127,
+ [3][0][2][0][RTW89_ACMA][0][112] = 127,
+ [3][0][2][0][RTW89_CHILE][1][112] = 127,
+ [3][0][2][0][RTW89_QATAR][1][112] = 127,
+ [3][0][2][0][RTW89_QATAR][0][112] = 127,
+ [3][0][2][0][RTW89_UK][1][112] = 127,
+ [3][0][2][0][RTW89_UK][0][112] = 127,
+ [3][1][2][0][RTW89_FCC][1][7] = 32,
+ [3][1][2][0][RTW89_FCC][2][7] = 46,
+ [3][1][2][0][RTW89_ETSI][1][7] = 50,
+ [3][1][2][0][RTW89_ETSI][0][7] = 18,
+ [3][1][2][0][RTW89_MKK][1][7] = 38,
+ [3][1][2][0][RTW89_MKK][0][7] = 10,
+ [3][1][2][0][RTW89_IC][1][7] = 32,
+ [3][1][2][0][RTW89_KCC][1][7] = 40,
+ [3][1][2][0][RTW89_KCC][0][7] = 12,
+ [3][1][2][0][RTW89_ACMA][1][7] = 50,
+ [3][1][2][0][RTW89_ACMA][0][7] = 18,
+ [3][1][2][0][RTW89_CHILE][1][7] = 32,
+ [3][1][2][0][RTW89_QATAR][1][7] = 50,
+ [3][1][2][0][RTW89_QATAR][0][7] = 18,
+ [3][1][2][0][RTW89_UK][1][7] = 50,
+ [3][1][2][0][RTW89_UK][0][7] = 18,
+ [3][1][2][0][RTW89_FCC][1][22] = 30,
+ [3][1][2][0][RTW89_FCC][2][22] = 52,
+ [3][1][2][0][RTW89_ETSI][1][22] = 46,
+ [3][1][2][0][RTW89_ETSI][0][22] = 16,
+ [3][1][2][0][RTW89_MKK][1][22] = 48,
+ [3][1][2][0][RTW89_MKK][0][22] = 8,
+ [3][1][2][0][RTW89_IC][1][22] = 30,
+ [3][1][2][0][RTW89_KCC][1][22] = 40,
+ [3][1][2][0][RTW89_KCC][0][22] = 12,
+ [3][1][2][0][RTW89_ACMA][1][22] = 46,
+ [3][1][2][0][RTW89_ACMA][0][22] = 16,
+ [3][1][2][0][RTW89_CHILE][1][22] = 30,
+ [3][1][2][0][RTW89_QATAR][1][22] = 46,
+ [3][1][2][0][RTW89_QATAR][0][22] = 16,
+ [3][1][2][0][RTW89_UK][1][22] = 46,
+ [3][1][2][0][RTW89_UK][0][22] = 16,
+ [3][1][2][0][RTW89_FCC][1][37] = 30,
+ [3][1][2][0][RTW89_FCC][2][37] = 52,
+ [3][1][2][0][RTW89_ETSI][1][37] = 46,
+ [3][1][2][0][RTW89_ETSI][0][37] = 16,
+ [3][1][2][0][RTW89_MKK][1][37] = 48,
+ [3][1][2][0][RTW89_MKK][0][37] = 8,
+ [3][1][2][0][RTW89_IC][1][37] = 30,
+ [3][1][2][0][RTW89_KCC][1][37] = 40,
+ [3][1][2][0][RTW89_KCC][0][37] = 12,
+ [3][1][2][0][RTW89_ACMA][1][37] = 46,
+ [3][1][2][0][RTW89_ACMA][0][37] = 16,
+ [3][1][2][0][RTW89_CHILE][1][37] = 30,
+ [3][1][2][0][RTW89_QATAR][1][37] = 46,
+ [3][1][2][0][RTW89_QATAR][0][37] = 16,
+ [3][1][2][0][RTW89_UK][1][37] = 46,
+ [3][1][2][0][RTW89_UK][0][37] = 16,
+ [3][1][2][0][RTW89_FCC][1][52] = 30,
+ [3][1][2][0][RTW89_FCC][2][52] = 127,
+ [3][1][2][0][RTW89_ETSI][1][52] = 127,
+ [3][1][2][0][RTW89_ETSI][0][52] = 127,
+ [3][1][2][0][RTW89_MKK][1][52] = 127,
+ [3][1][2][0][RTW89_MKK][0][52] = 127,
+ [3][1][2][0][RTW89_IC][1][52] = 30,
+ [3][1][2][0][RTW89_KCC][1][52] = 48,
+ [3][1][2][0][RTW89_KCC][0][52] = 127,
+ [3][1][2][0][RTW89_ACMA][1][52] = 127,
+ [3][1][2][0][RTW89_ACMA][0][52] = 127,
+ [3][1][2][0][RTW89_CHILE][1][52] = 30,
+ [3][1][2][0][RTW89_QATAR][1][52] = 127,
+ [3][1][2][0][RTW89_QATAR][0][52] = 127,
+ [3][1][2][0][RTW89_UK][1][52] = 127,
+ [3][1][2][0][RTW89_UK][0][52] = 127,
+ [3][1][2][0][RTW89_FCC][1][67] = 32,
+ [3][1][2][0][RTW89_FCC][2][67] = 54,
+ [3][1][2][0][RTW89_ETSI][1][67] = 127,
+ [3][1][2][0][RTW89_ETSI][0][67] = 127,
+ [3][1][2][0][RTW89_MKK][1][67] = 127,
+ [3][1][2][0][RTW89_MKK][0][67] = 127,
+ [3][1][2][0][RTW89_IC][1][67] = 32,
+ [3][1][2][0][RTW89_KCC][1][67] = 48,
+ [3][1][2][0][RTW89_KCC][0][67] = 127,
+ [3][1][2][0][RTW89_ACMA][1][67] = 127,
+ [3][1][2][0][RTW89_ACMA][0][67] = 127,
+ [3][1][2][0][RTW89_CHILE][1][67] = 32,
+ [3][1][2][0][RTW89_QATAR][1][67] = 127,
+ [3][1][2][0][RTW89_QATAR][0][67] = 127,
+ [3][1][2][0][RTW89_UK][1][67] = 127,
+ [3][1][2][0][RTW89_UK][0][67] = 127,
+ [3][1][2][0][RTW89_FCC][1][82] = 32,
+ [3][1][2][0][RTW89_FCC][2][82] = 127,
+ [3][1][2][0][RTW89_ETSI][1][82] = 127,
+ [3][1][2][0][RTW89_ETSI][0][82] = 127,
+ [3][1][2][0][RTW89_MKK][1][82] = 127,
+ [3][1][2][0][RTW89_MKK][0][82] = 127,
+ [3][1][2][0][RTW89_IC][1][82] = 32,
+ [3][1][2][0][RTW89_KCC][1][82] = 24,
+ [3][1][2][0][RTW89_KCC][0][82] = 127,
+ [3][1][2][0][RTW89_ACMA][1][82] = 127,
+ [3][1][2][0][RTW89_ACMA][0][82] = 127,
+ [3][1][2][0][RTW89_CHILE][1][82] = 32,
+ [3][1][2][0][RTW89_QATAR][1][82] = 127,
+ [3][1][2][0][RTW89_QATAR][0][82] = 127,
+ [3][1][2][0][RTW89_UK][1][82] = 127,
+ [3][1][2][0][RTW89_UK][0][82] = 127,
+ [3][1][2][0][RTW89_FCC][1][97] = 32,
+ [3][1][2][0][RTW89_FCC][2][97] = 127,
+ [3][1][2][0][RTW89_ETSI][1][97] = 127,
+ [3][1][2][0][RTW89_ETSI][0][97] = 127,
+ [3][1][2][0][RTW89_MKK][1][97] = 127,
+ [3][1][2][0][RTW89_MKK][0][97] = 127,
+ [3][1][2][0][RTW89_IC][1][97] = 32,
+ [3][1][2][0][RTW89_KCC][1][97] = 24,
+ [3][1][2][0][RTW89_KCC][0][97] = 127,
+ [3][1][2][0][RTW89_ACMA][1][97] = 127,
+ [3][1][2][0][RTW89_ACMA][0][97] = 127,
+ [3][1][2][0][RTW89_CHILE][1][97] = 32,
+ [3][1][2][0][RTW89_QATAR][1][97] = 127,
+ [3][1][2][0][RTW89_QATAR][0][97] = 127,
+ [3][1][2][0][RTW89_UK][1][97] = 127,
+ [3][1][2][0][RTW89_UK][0][97] = 127,
+ [3][1][2][0][RTW89_FCC][1][112] = 127,
+ [3][1][2][0][RTW89_FCC][2][112] = 127,
+ [3][1][2][0][RTW89_ETSI][1][112] = 127,
+ [3][1][2][0][RTW89_ETSI][0][112] = 127,
+ [3][1][2][0][RTW89_MKK][1][112] = 127,
+ [3][1][2][0][RTW89_MKK][0][112] = 127,
+ [3][1][2][0][RTW89_IC][1][112] = 127,
+ [3][1][2][0][RTW89_KCC][1][112] = 127,
+ [3][1][2][0][RTW89_KCC][0][112] = 127,
+ [3][1][2][0][RTW89_ACMA][1][112] = 127,
+ [3][1][2][0][RTW89_ACMA][0][112] = 127,
+ [3][1][2][0][RTW89_CHILE][1][112] = 127,
+ [3][1][2][0][RTW89_QATAR][1][112] = 127,
+ [3][1][2][0][RTW89_QATAR][0][112] = 127,
+ [3][1][2][0][RTW89_UK][1][112] = 127,
+ [3][1][2][0][RTW89_UK][0][112] = 127,
+ [3][1][2][1][RTW89_FCC][1][7] = 32,
+ [3][1][2][1][RTW89_FCC][2][7] = 46,
+ [3][1][2][1][RTW89_ETSI][1][7] = 42,
+ [3][1][2][1][RTW89_ETSI][0][7] = 6,
+ [3][1][2][1][RTW89_MKK][1][7] = 38,
+ [3][1][2][1][RTW89_MKK][0][7] = 10,
+ [3][1][2][1][RTW89_IC][1][7] = 32,
+ [3][1][2][1][RTW89_KCC][1][7] = 40,
+ [3][1][2][1][RTW89_KCC][0][7] = 12,
+ [3][1][2][1][RTW89_ACMA][1][7] = 42,
+ [3][1][2][1][RTW89_ACMA][0][7] = 6,
+ [3][1][2][1][RTW89_CHILE][1][7] = 32,
+ [3][1][2][1][RTW89_QATAR][1][7] = 42,
+ [3][1][2][1][RTW89_QATAR][0][7] = 6,
+ [3][1][2][1][RTW89_UK][1][7] = 42,
+ [3][1][2][1][RTW89_UK][0][7] = 6,
+ [3][1][2][1][RTW89_FCC][1][22] = 30,
+ [3][1][2][1][RTW89_FCC][2][22] = 52,
+ [3][1][2][1][RTW89_ETSI][1][22] = 42,
+ [3][1][2][1][RTW89_ETSI][0][22] = 6,
+ [3][1][2][1][RTW89_MKK][1][22] = 48,
+ [3][1][2][1][RTW89_MKK][0][22] = 8,
+ [3][1][2][1][RTW89_IC][1][22] = 30,
+ [3][1][2][1][RTW89_KCC][1][22] = 40,
+ [3][1][2][1][RTW89_KCC][0][22] = 12,
+ [3][1][2][1][RTW89_ACMA][1][22] = 42,
+ [3][1][2][1][RTW89_ACMA][0][22] = 6,
+ [3][1][2][1][RTW89_CHILE][1][22] = 30,
+ [3][1][2][1][RTW89_QATAR][1][22] = 42,
+ [3][1][2][1][RTW89_QATAR][0][22] = 6,
+ [3][1][2][1][RTW89_UK][1][22] = 42,
+ [3][1][2][1][RTW89_UK][0][22] = 6,
+ [3][1][2][1][RTW89_FCC][1][37] = 30,
+ [3][1][2][1][RTW89_FCC][2][37] = 52,
+ [3][1][2][1][RTW89_ETSI][1][37] = 42,
+ [3][1][2][1][RTW89_ETSI][0][37] = 6,
+ [3][1][2][1][RTW89_MKK][1][37] = 48,
+ [3][1][2][1][RTW89_MKK][0][37] = 8,
+ [3][1][2][1][RTW89_IC][1][37] = 30,
+ [3][1][2][1][RTW89_KCC][1][37] = 40,
+ [3][1][2][1][RTW89_KCC][0][37] = 12,
+ [3][1][2][1][RTW89_ACMA][1][37] = 42,
+ [3][1][2][1][RTW89_ACMA][0][37] = 6,
+ [3][1][2][1][RTW89_CHILE][1][37] = 30,
+ [3][1][2][1][RTW89_QATAR][1][37] = 42,
+ [3][1][2][1][RTW89_QATAR][0][37] = 6,
+ [3][1][2][1][RTW89_UK][1][37] = 42,
+ [3][1][2][1][RTW89_UK][0][37] = 6,
+ [3][1][2][1][RTW89_FCC][1][52] = 30,
+ [3][1][2][1][RTW89_FCC][2][52] = 127,
+ [3][1][2][1][RTW89_ETSI][1][52] = 127,
+ [3][1][2][1][RTW89_ETSI][0][52] = 127,
+ [3][1][2][1][RTW89_MKK][1][52] = 127,
+ [3][1][2][1][RTW89_MKK][0][52] = 127,
+ [3][1][2][1][RTW89_IC][1][52] = 30,
+ [3][1][2][1][RTW89_KCC][1][52] = 48,
+ [3][1][2][1][RTW89_KCC][0][52] = 127,
+ [3][1][2][1][RTW89_ACMA][1][52] = 127,
+ [3][1][2][1][RTW89_ACMA][0][52] = 127,
+ [3][1][2][1][RTW89_CHILE][1][52] = 30,
+ [3][1][2][1][RTW89_QATAR][1][52] = 127,
+ [3][1][2][1][RTW89_QATAR][0][52] = 127,
+ [3][1][2][1][RTW89_UK][1][52] = 127,
+ [3][1][2][1][RTW89_UK][0][52] = 127,
+ [3][1][2][1][RTW89_FCC][1][67] = 32,
+ [3][1][2][1][RTW89_FCC][2][67] = 54,
+ [3][1][2][1][RTW89_ETSI][1][67] = 127,
+ [3][1][2][1][RTW89_ETSI][0][67] = 127,
+ [3][1][2][1][RTW89_MKK][1][67] = 127,
+ [3][1][2][1][RTW89_MKK][0][67] = 127,
+ [3][1][2][1][RTW89_IC][1][67] = 32,
+ [3][1][2][1][RTW89_KCC][1][67] = 48,
+ [3][1][2][1][RTW89_KCC][0][67] = 127,
+ [3][1][2][1][RTW89_ACMA][1][67] = 127,
+ [3][1][2][1][RTW89_ACMA][0][67] = 127,
+ [3][1][2][1][RTW89_CHILE][1][67] = 32,
+ [3][1][2][1][RTW89_QATAR][1][67] = 127,
+ [3][1][2][1][RTW89_QATAR][0][67] = 127,
+ [3][1][2][1][RTW89_UK][1][67] = 127,
+ [3][1][2][1][RTW89_UK][0][67] = 127,
+ [3][1][2][1][RTW89_FCC][1][82] = 32,
+ [3][1][2][1][RTW89_FCC][2][82] = 127,
+ [3][1][2][1][RTW89_ETSI][1][82] = 127,
+ [3][1][2][1][RTW89_ETSI][0][82] = 127,
+ [3][1][2][1][RTW89_MKK][1][82] = 127,
+ [3][1][2][1][RTW89_MKK][0][82] = 127,
+ [3][1][2][1][RTW89_IC][1][82] = 32,
+ [3][1][2][1][RTW89_KCC][1][82] = 24,
+ [3][1][2][1][RTW89_KCC][0][82] = 127,
+ [3][1][2][1][RTW89_ACMA][1][82] = 127,
+ [3][1][2][1][RTW89_ACMA][0][82] = 127,
+ [3][1][2][1][RTW89_CHILE][1][82] = 32,
+ [3][1][2][1][RTW89_QATAR][1][82] = 127,
+ [3][1][2][1][RTW89_QATAR][0][82] = 127,
+ [3][1][2][1][RTW89_UK][1][82] = 127,
+ [3][1][2][1][RTW89_UK][0][82] = 127,
+ [3][1][2][1][RTW89_FCC][1][97] = 32,
+ [3][1][2][1][RTW89_FCC][2][97] = 127,
+ [3][1][2][1][RTW89_ETSI][1][97] = 127,
+ [3][1][2][1][RTW89_ETSI][0][97] = 127,
+ [3][1][2][1][RTW89_MKK][1][97] = 127,
+ [3][1][2][1][RTW89_MKK][0][97] = 127,
+ [3][1][2][1][RTW89_IC][1][97] = 32,
+ [3][1][2][1][RTW89_KCC][1][97] = 24,
+ [3][1][2][1][RTW89_KCC][0][97] = 127,
+ [3][1][2][1][RTW89_ACMA][1][97] = 127,
+ [3][1][2][1][RTW89_ACMA][0][97] = 127,
+ [3][1][2][1][RTW89_CHILE][1][97] = 32,
+ [3][1][2][1][RTW89_QATAR][1][97] = 127,
+ [3][1][2][1][RTW89_QATAR][0][97] = 127,
+ [3][1][2][1][RTW89_UK][1][97] = 127,
+ [3][1][2][1][RTW89_UK][0][97] = 127,
+ [3][1][2][1][RTW89_FCC][1][112] = 127,
+ [3][1][2][1][RTW89_FCC][2][112] = 127,
+ [3][1][2][1][RTW89_ETSI][1][112] = 127,
+ [3][1][2][1][RTW89_ETSI][0][112] = 127,
+ [3][1][2][1][RTW89_MKK][1][112] = 127,
+ [3][1][2][1][RTW89_MKK][0][112] = 127,
+ [3][1][2][1][RTW89_IC][1][112] = 127,
+ [3][1][2][1][RTW89_KCC][1][112] = 127,
+ [3][1][2][1][RTW89_KCC][0][112] = 127,
+ [3][1][2][1][RTW89_ACMA][1][112] = 127,
+ [3][1][2][1][RTW89_ACMA][0][112] = 127,
+ [3][1][2][1][RTW89_CHILE][1][112] = 127,
+ [3][1][2][1][RTW89_QATAR][1][112] = 127,
+ [3][1][2][1][RTW89_QATAR][0][112] = 127,
+ [3][1][2][1][RTW89_UK][1][112] = 127,
+ [3][1][2][1][RTW89_UK][0][112] = 127,
};
static
@@ -34017,10 +45842,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM]
[1][0][RTW89_WW][3] = 44,
[1][0][RTW89_WW][4] = 44,
[1][0][RTW89_WW][5] = 44,
- [1][0][RTW89_WW][6] = 44,
- [1][0][RTW89_WW][7] = 44,
- [1][0][RTW89_WW][8] = 44,
- [1][0][RTW89_WW][9] = 44,
+ [1][0][RTW89_WW][6] = 40,
+ [1][0][RTW89_WW][7] = 40,
+ [1][0][RTW89_WW][8] = 40,
+ [1][0][RTW89_WW][9] = 40,
[1][0][RTW89_WW][10] = 44,
[1][0][RTW89_WW][11] = 36,
[1][0][RTW89_WW][12] = 4,
@@ -34031,24 +45856,24 @@ const s8 rtw89_8852c_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM]
[1][1][RTW89_WW][3] = 32,
[1][1][RTW89_WW][4] = 32,
[1][1][RTW89_WW][5] = 32,
- [1][1][RTW89_WW][6] = 32,
- [1][1][RTW89_WW][7] = 32,
- [1][1][RTW89_WW][8] = 32,
- [1][1][RTW89_WW][9] = 32,
+ [1][1][RTW89_WW][6] = 30,
+ [1][1][RTW89_WW][7] = 30,
+ [1][1][RTW89_WW][8] = 30,
+ [1][1][RTW89_WW][9] = 30,
[1][1][RTW89_WW][10] = 32,
[1][1][RTW89_WW][11] = 30,
[1][1][RTW89_WW][12] = -6,
[1][1][RTW89_WW][13] = 0,
[2][0][RTW89_WW][0] = 56,
- [2][0][RTW89_WW][1] = 56,
- [2][0][RTW89_WW][2] = 56,
- [2][0][RTW89_WW][3] = 56,
- [2][0][RTW89_WW][4] = 56,
+ [2][0][RTW89_WW][1] = 54,
+ [2][0][RTW89_WW][2] = 54,
+ [2][0][RTW89_WW][3] = 54,
+ [2][0][RTW89_WW][4] = 54,
[2][0][RTW89_WW][5] = 56,
- [2][0][RTW89_WW][6] = 56,
- [2][0][RTW89_WW][7] = 56,
- [2][0][RTW89_WW][8] = 56,
- [2][0][RTW89_WW][9] = 56,
+ [2][0][RTW89_WW][6] = 48,
+ [2][0][RTW89_WW][7] = 48,
+ [2][0][RTW89_WW][8] = 48,
+ [2][0][RTW89_WW][9] = 48,
[2][0][RTW89_WW][10] = 56,
[2][0][RTW89_WW][11] = 48,
[2][0][RTW89_WW][12] = 16,
@@ -34059,10 +45884,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM]
[2][1][RTW89_WW][3] = 44,
[2][1][RTW89_WW][4] = 44,
[2][1][RTW89_WW][5] = 44,
- [2][1][RTW89_WW][6] = 44,
- [2][1][RTW89_WW][7] = 44,
- [2][1][RTW89_WW][8] = 44,
- [2][1][RTW89_WW][9] = 44,
+ [2][1][RTW89_WW][6] = 42,
+ [2][1][RTW89_WW][7] = 42,
+ [2][1][RTW89_WW][8] = 42,
+ [2][1][RTW89_WW][9] = 42,
[2][1][RTW89_WW][10] = 44,
[2][1][RTW89_WW][11] = 44,
[2][1][RTW89_WW][12] = 6,
@@ -34075,6 +45900,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][0][RTW89_ACMA][0] = 34,
[0][0][RTW89_CN][0] = 32,
[0][0][RTW89_UK][0] = 34,
+ [0][0][RTW89_MEXICO][0] = 60,
+ [0][0][RTW89_UKRAINE][0] = 34,
+ [0][0][RTW89_CHILE][0] = 60,
+ [0][0][RTW89_QATAR][0] = 34,
[0][0][RTW89_FCC][1] = 60,
[0][0][RTW89_ETSI][1] = 38,
[0][0][RTW89_MKK][1] = 40,
@@ -34083,6 +45912,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][0][RTW89_ACMA][1] = 38,
[0][0][RTW89_CN][1] = 32,
[0][0][RTW89_UK][1] = 38,
+ [0][0][RTW89_MEXICO][1] = 60,
+ [0][0][RTW89_UKRAINE][1] = 38,
+ [0][0][RTW89_CHILE][1] = 50,
+ [0][0][RTW89_QATAR][1] = 38,
[0][0][RTW89_FCC][2] = 64,
[0][0][RTW89_ETSI][2] = 38,
[0][0][RTW89_MKK][2] = 40,
@@ -34091,6 +45924,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][0][RTW89_ACMA][2] = 38,
[0][0][RTW89_CN][2] = 32,
[0][0][RTW89_UK][2] = 38,
+ [0][0][RTW89_MEXICO][2] = 64,
+ [0][0][RTW89_UKRAINE][2] = 38,
+ [0][0][RTW89_CHILE][2] = 50,
+ [0][0][RTW89_QATAR][2] = 38,
[0][0][RTW89_FCC][3] = 68,
[0][0][RTW89_ETSI][3] = 38,
[0][0][RTW89_MKK][3] = 40,
@@ -34099,78 +45936,118 @@ const s8 rtw89_8852c_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][0][RTW89_ACMA][3] = 38,
[0][0][RTW89_CN][3] = 32,
[0][0][RTW89_UK][3] = 38,
+ [0][0][RTW89_MEXICO][3] = 68,
+ [0][0][RTW89_UKRAINE][3] = 38,
+ [0][0][RTW89_CHILE][3] = 50,
+ [0][0][RTW89_QATAR][3] = 38,
[0][0][RTW89_FCC][4] = 68,
[0][0][RTW89_ETSI][4] = 38,
[0][0][RTW89_MKK][4] = 40,
[0][0][RTW89_IC][4] = 68,
- [0][0][RTW89_KCC][4] = 42,
+ [0][0][RTW89_KCC][4] = 44,
[0][0][RTW89_ACMA][4] = 38,
[0][0][RTW89_CN][4] = 32,
[0][0][RTW89_UK][4] = 38,
+ [0][0][RTW89_MEXICO][4] = 68,
+ [0][0][RTW89_UKRAINE][4] = 38,
+ [0][0][RTW89_CHILE][4] = 50,
+ [0][0][RTW89_QATAR][4] = 38,
[0][0][RTW89_FCC][5] = 78,
[0][0][RTW89_ETSI][5] = 38,
[0][0][RTW89_MKK][5] = 40,
[0][0][RTW89_IC][5] = 78,
- [0][0][RTW89_KCC][5] = 42,
+ [0][0][RTW89_KCC][5] = 44,
[0][0][RTW89_ACMA][5] = 38,
[0][0][RTW89_CN][5] = 32,
[0][0][RTW89_UK][5] = 38,
+ [0][0][RTW89_MEXICO][5] = 78,
+ [0][0][RTW89_UKRAINE][5] = 38,
+ [0][0][RTW89_CHILE][5] = 78,
+ [0][0][RTW89_QATAR][5] = 38,
[0][0][RTW89_FCC][6] = 54,
[0][0][RTW89_ETSI][6] = 38,
[0][0][RTW89_MKK][6] = 40,
[0][0][RTW89_IC][6] = 54,
- [0][0][RTW89_KCC][6] = 42,
+ [0][0][RTW89_KCC][6] = 44,
[0][0][RTW89_ACMA][6] = 38,
[0][0][RTW89_CN][6] = 32,
[0][0][RTW89_UK][6] = 38,
+ [0][0][RTW89_MEXICO][6] = 54,
+ [0][0][RTW89_UKRAINE][6] = 38,
+ [0][0][RTW89_CHILE][6] = 36,
+ [0][0][RTW89_QATAR][6] = 38,
[0][0][RTW89_FCC][7] = 54,
[0][0][RTW89_ETSI][7] = 38,
[0][0][RTW89_MKK][7] = 40,
[0][0][RTW89_IC][7] = 54,
- [0][0][RTW89_KCC][7] = 42,
+ [0][0][RTW89_KCC][7] = 44,
[0][0][RTW89_ACMA][7] = 38,
[0][0][RTW89_CN][7] = 32,
[0][0][RTW89_UK][7] = 38,
+ [0][0][RTW89_MEXICO][7] = 54,
+ [0][0][RTW89_UKRAINE][7] = 38,
+ [0][0][RTW89_CHILE][7] = 36,
+ [0][0][RTW89_QATAR][7] = 38,
[0][0][RTW89_FCC][8] = 50,
[0][0][RTW89_ETSI][8] = 38,
[0][0][RTW89_MKK][8] = 40,
[0][0][RTW89_IC][8] = 50,
- [0][0][RTW89_KCC][8] = 42,
+ [0][0][RTW89_KCC][8] = 44,
[0][0][RTW89_ACMA][8] = 38,
[0][0][RTW89_CN][8] = 32,
[0][0][RTW89_UK][8] = 38,
+ [0][0][RTW89_MEXICO][8] = 50,
+ [0][0][RTW89_UKRAINE][8] = 38,
+ [0][0][RTW89_CHILE][8] = 36,
+ [0][0][RTW89_QATAR][8] = 38,
[0][0][RTW89_FCC][9] = 46,
[0][0][RTW89_ETSI][9] = 38,
[0][0][RTW89_MKK][9] = 40,
[0][0][RTW89_IC][9] = 46,
- [0][0][RTW89_KCC][9] = 40,
+ [0][0][RTW89_KCC][9] = 42,
[0][0][RTW89_ACMA][9] = 38,
[0][0][RTW89_CN][9] = 32,
[0][0][RTW89_UK][9] = 38,
+ [0][0][RTW89_MEXICO][9] = 46,
+ [0][0][RTW89_UKRAINE][9] = 38,
+ [0][0][RTW89_CHILE][9] = 36,
+ [0][0][RTW89_QATAR][9] = 38,
[0][0][RTW89_FCC][10] = 46,
[0][0][RTW89_ETSI][10] = 38,
[0][0][RTW89_MKK][10] = 40,
[0][0][RTW89_IC][10] = 46,
- [0][0][RTW89_KCC][10] = 40,
+ [0][0][RTW89_KCC][10] = 42,
[0][0][RTW89_ACMA][10] = 38,
[0][0][RTW89_CN][10] = 32,
[0][0][RTW89_UK][10] = 38,
+ [0][0][RTW89_MEXICO][10] = 46,
+ [0][0][RTW89_UKRAINE][10] = 38,
+ [0][0][RTW89_CHILE][10] = 46,
+ [0][0][RTW89_QATAR][10] = 38,
[0][0][RTW89_FCC][11] = 26,
[0][0][RTW89_ETSI][11] = 38,
[0][0][RTW89_MKK][11] = 40,
[0][0][RTW89_IC][11] = 26,
- [0][0][RTW89_KCC][11] = 40,
+ [0][0][RTW89_KCC][11] = 42,
[0][0][RTW89_ACMA][11] = 38,
[0][0][RTW89_CN][11] = 32,
[0][0][RTW89_UK][11] = 38,
+ [0][0][RTW89_MEXICO][11] = 26,
+ [0][0][RTW89_UKRAINE][11] = 38,
+ [0][0][RTW89_CHILE][11] = 26,
+ [0][0][RTW89_QATAR][11] = 38,
[0][0][RTW89_FCC][12] = -20,
[0][0][RTW89_ETSI][12] = 34,
[0][0][RTW89_MKK][12] = 36,
[0][0][RTW89_IC][12] = -20,
- [0][0][RTW89_KCC][12] = 40,
+ [0][0][RTW89_KCC][12] = 42,
[0][0][RTW89_ACMA][12] = 34,
[0][0][RTW89_CN][12] = 32,
[0][0][RTW89_UK][12] = 34,
+ [0][0][RTW89_MEXICO][12] = -20,
+ [0][0][RTW89_UKRAINE][12] = 34,
+ [0][0][RTW89_CHILE][12] = -20,
+ [0][0][RTW89_QATAR][12] = 34,
[0][0][RTW89_FCC][13] = 127,
[0][0][RTW89_ETSI][13] = 127,
[0][0][RTW89_MKK][13] = 127,
@@ -34179,6 +46056,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][0][RTW89_ACMA][13] = 127,
[0][0][RTW89_CN][13] = 127,
[0][0][RTW89_UK][13] = 127,
+ [0][0][RTW89_MEXICO][13] = 127,
+ [0][0][RTW89_UKRAINE][13] = 127,
+ [0][0][RTW89_CHILE][13] = 127,
+ [0][0][RTW89_QATAR][13] = 127,
[0][1][RTW89_FCC][0] = 56,
[0][1][RTW89_ETSI][0] = 22,
[0][1][RTW89_MKK][0] = 24,
@@ -34187,6 +46068,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][1][RTW89_ACMA][0] = 22,
[0][1][RTW89_CN][0] = 20,
[0][1][RTW89_UK][0] = 22,
+ [0][1][RTW89_MEXICO][0] = 56,
+ [0][1][RTW89_UKRAINE][0] = 22,
+ [0][1][RTW89_CHILE][0] = 56,
+ [0][1][RTW89_QATAR][0] = 22,
[0][1][RTW89_FCC][1] = 56,
[0][1][RTW89_ETSI][1] = 24,
[0][1][RTW89_MKK][1] = 30,
@@ -34195,6 +46080,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][1][RTW89_ACMA][1] = 24,
[0][1][RTW89_CN][1] = 22,
[0][1][RTW89_UK][1] = 24,
+ [0][1][RTW89_MEXICO][1] = 56,
+ [0][1][RTW89_UKRAINE][1] = 24,
+ [0][1][RTW89_CHILE][1] = 40,
+ [0][1][RTW89_QATAR][1] = 24,
[0][1][RTW89_FCC][2] = 60,
[0][1][RTW89_ETSI][2] = 24,
[0][1][RTW89_MKK][2] = 30,
@@ -34203,6 +46092,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][1][RTW89_ACMA][2] = 24,
[0][1][RTW89_CN][2] = 22,
[0][1][RTW89_UK][2] = 24,
+ [0][1][RTW89_MEXICO][2] = 60,
+ [0][1][RTW89_UKRAINE][2] = 24,
+ [0][1][RTW89_CHILE][2] = 40,
+ [0][1][RTW89_QATAR][2] = 24,
[0][1][RTW89_FCC][3] = 64,
[0][1][RTW89_ETSI][3] = 24,
[0][1][RTW89_MKK][3] = 30,
@@ -34211,78 +46104,118 @@ const s8 rtw89_8852c_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][1][RTW89_ACMA][3] = 24,
[0][1][RTW89_CN][3] = 22,
[0][1][RTW89_UK][3] = 24,
+ [0][1][RTW89_MEXICO][3] = 64,
+ [0][1][RTW89_UKRAINE][3] = 24,
+ [0][1][RTW89_CHILE][3] = 40,
+ [0][1][RTW89_QATAR][3] = 24,
[0][1][RTW89_FCC][4] = 68,
[0][1][RTW89_ETSI][4] = 24,
[0][1][RTW89_MKK][4] = 30,
[0][1][RTW89_IC][4] = 68,
- [0][1][RTW89_KCC][4] = 28,
+ [0][1][RTW89_KCC][4] = 34,
[0][1][RTW89_ACMA][4] = 24,
[0][1][RTW89_CN][4] = 22,
[0][1][RTW89_UK][4] = 24,
+ [0][1][RTW89_MEXICO][4] = 68,
+ [0][1][RTW89_UKRAINE][4] = 24,
+ [0][1][RTW89_CHILE][4] = 40,
+ [0][1][RTW89_QATAR][4] = 24,
[0][1][RTW89_FCC][5] = 76,
[0][1][RTW89_ETSI][5] = 24,
[0][1][RTW89_MKK][5] = 30,
[0][1][RTW89_IC][5] = 76,
- [0][1][RTW89_KCC][5] = 28,
+ [0][1][RTW89_KCC][5] = 34,
[0][1][RTW89_ACMA][5] = 24,
[0][1][RTW89_CN][5] = 22,
[0][1][RTW89_UK][5] = 24,
+ [0][1][RTW89_MEXICO][5] = 76,
+ [0][1][RTW89_UKRAINE][5] = 24,
+ [0][1][RTW89_CHILE][5] = 76,
+ [0][1][RTW89_QATAR][5] = 24,
[0][1][RTW89_FCC][6] = 54,
[0][1][RTW89_ETSI][6] = 24,
[0][1][RTW89_MKK][6] = 30,
[0][1][RTW89_IC][6] = 54,
- [0][1][RTW89_KCC][6] = 28,
+ [0][1][RTW89_KCC][6] = 34,
[0][1][RTW89_ACMA][6] = 24,
[0][1][RTW89_CN][6] = 22,
[0][1][RTW89_UK][6] = 24,
+ [0][1][RTW89_MEXICO][6] = 54,
+ [0][1][RTW89_UKRAINE][6] = 24,
+ [0][1][RTW89_CHILE][6] = 26,
+ [0][1][RTW89_QATAR][6] = 24,
[0][1][RTW89_FCC][7] = 50,
[0][1][RTW89_ETSI][7] = 24,
[0][1][RTW89_MKK][7] = 30,
[0][1][RTW89_IC][7] = 50,
- [0][1][RTW89_KCC][7] = 28,
+ [0][1][RTW89_KCC][7] = 34,
[0][1][RTW89_ACMA][7] = 24,
[0][1][RTW89_CN][7] = 22,
[0][1][RTW89_UK][7] = 24,
+ [0][1][RTW89_MEXICO][7] = 50,
+ [0][1][RTW89_UKRAINE][7] = 24,
+ [0][1][RTW89_CHILE][7] = 26,
+ [0][1][RTW89_QATAR][7] = 24,
[0][1][RTW89_FCC][8] = 46,
[0][1][RTW89_ETSI][8] = 24,
[0][1][RTW89_MKK][8] = 30,
[0][1][RTW89_IC][8] = 46,
- [0][1][RTW89_KCC][8] = 28,
+ [0][1][RTW89_KCC][8] = 34,
[0][1][RTW89_ACMA][8] = 24,
[0][1][RTW89_CN][8] = 22,
[0][1][RTW89_UK][8] = 24,
+ [0][1][RTW89_MEXICO][8] = 46,
+ [0][1][RTW89_UKRAINE][8] = 24,
+ [0][1][RTW89_CHILE][8] = 26,
+ [0][1][RTW89_QATAR][8] = 24,
[0][1][RTW89_FCC][9] = 42,
[0][1][RTW89_ETSI][9] = 24,
[0][1][RTW89_MKK][9] = 30,
[0][1][RTW89_IC][9] = 42,
- [0][1][RTW89_KCC][9] = 28,
+ [0][1][RTW89_KCC][9] = 32,
[0][1][RTW89_ACMA][9] = 24,
[0][1][RTW89_CN][9] = 22,
[0][1][RTW89_UK][9] = 24,
+ [0][1][RTW89_MEXICO][9] = 42,
+ [0][1][RTW89_UKRAINE][9] = 24,
+ [0][1][RTW89_CHILE][9] = 26,
+ [0][1][RTW89_QATAR][9] = 24,
[0][1][RTW89_FCC][10] = 42,
[0][1][RTW89_ETSI][10] = 24,
[0][1][RTW89_MKK][10] = 30,
[0][1][RTW89_IC][10] = 42,
- [0][1][RTW89_KCC][10] = 28,
+ [0][1][RTW89_KCC][10] = 32,
[0][1][RTW89_ACMA][10] = 24,
[0][1][RTW89_CN][10] = 22,
[0][1][RTW89_UK][10] = 24,
+ [0][1][RTW89_MEXICO][10] = 42,
+ [0][1][RTW89_UKRAINE][10] = 24,
+ [0][1][RTW89_CHILE][10] = 42,
+ [0][1][RTW89_QATAR][10] = 24,
[0][1][RTW89_FCC][11] = 22,
[0][1][RTW89_ETSI][11] = 24,
[0][1][RTW89_MKK][11] = 30,
[0][1][RTW89_IC][11] = 22,
- [0][1][RTW89_KCC][11] = 28,
+ [0][1][RTW89_KCC][11] = 32,
[0][1][RTW89_ACMA][11] = 24,
[0][1][RTW89_CN][11] = 22,
[0][1][RTW89_UK][11] = 24,
+ [0][1][RTW89_MEXICO][11] = 22,
+ [0][1][RTW89_UKRAINE][11] = 24,
+ [0][1][RTW89_CHILE][11] = 22,
+ [0][1][RTW89_QATAR][11] = 24,
[0][1][RTW89_FCC][12] = -30,
[0][1][RTW89_ETSI][12] = 20,
[0][1][RTW89_MKK][12] = 24,
[0][1][RTW89_IC][12] = -30,
- [0][1][RTW89_KCC][12] = 28,
+ [0][1][RTW89_KCC][12] = 32,
[0][1][RTW89_ACMA][12] = 20,
[0][1][RTW89_CN][12] = 20,
[0][1][RTW89_UK][12] = 20,
+ [0][1][RTW89_MEXICO][12] = -30,
+ [0][1][RTW89_UKRAINE][12] = 20,
+ [0][1][RTW89_CHILE][12] = -30,
+ [0][1][RTW89_QATAR][12] = 20,
[0][1][RTW89_FCC][13] = 127,
[0][1][RTW89_ETSI][13] = 127,
[0][1][RTW89_MKK][13] = 127,
@@ -34291,110 +46224,166 @@ const s8 rtw89_8852c_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][1][RTW89_ACMA][13] = 127,
[0][1][RTW89_CN][13] = 127,
[0][1][RTW89_UK][13] = 127,
+ [0][1][RTW89_MEXICO][13] = 127,
+ [0][1][RTW89_UKRAINE][13] = 127,
+ [0][1][RTW89_CHILE][13] = 127,
+ [0][1][RTW89_QATAR][13] = 127,
[1][0][RTW89_FCC][0] = 66,
[1][0][RTW89_ETSI][0] = 46,
[1][0][RTW89_MKK][0] = 48,
[1][0][RTW89_IC][0] = 66,
- [1][0][RTW89_KCC][0] = 50,
+ [1][0][RTW89_KCC][0] = 54,
[1][0][RTW89_ACMA][0] = 46,
[1][0][RTW89_CN][0] = 42,
[1][0][RTW89_UK][0] = 46,
+ [1][0][RTW89_MEXICO][0] = 66,
+ [1][0][RTW89_UKRAINE][0] = 46,
+ [1][0][RTW89_CHILE][0] = 66,
+ [1][0][RTW89_QATAR][0] = 46,
[1][0][RTW89_FCC][1] = 66,
[1][0][RTW89_ETSI][1] = 46,
[1][0][RTW89_MKK][1] = 48,
[1][0][RTW89_IC][1] = 66,
- [1][0][RTW89_KCC][1] = 50,
+ [1][0][RTW89_KCC][1] = 54,
[1][0][RTW89_ACMA][1] = 46,
[1][0][RTW89_CN][1] = 44,
[1][0][RTW89_UK][1] = 46,
+ [1][0][RTW89_MEXICO][1] = 66,
+ [1][0][RTW89_UKRAINE][1] = 46,
+ [1][0][RTW89_CHILE][1] = 54,
+ [1][0][RTW89_QATAR][1] = 46,
[1][0][RTW89_FCC][2] = 70,
[1][0][RTW89_ETSI][2] = 46,
[1][0][RTW89_MKK][2] = 48,
[1][0][RTW89_IC][2] = 70,
- [1][0][RTW89_KCC][2] = 50,
+ [1][0][RTW89_KCC][2] = 54,
[1][0][RTW89_ACMA][2] = 46,
[1][0][RTW89_CN][2] = 44,
[1][0][RTW89_UK][2] = 46,
+ [1][0][RTW89_MEXICO][2] = 70,
+ [1][0][RTW89_UKRAINE][2] = 46,
+ [1][0][RTW89_CHILE][2] = 54,
+ [1][0][RTW89_QATAR][2] = 46,
[1][0][RTW89_FCC][3] = 72,
[1][0][RTW89_ETSI][3] = 46,
[1][0][RTW89_MKK][3] = 48,
[1][0][RTW89_IC][3] = 72,
- [1][0][RTW89_KCC][3] = 50,
+ [1][0][RTW89_KCC][3] = 54,
[1][0][RTW89_ACMA][3] = 46,
[1][0][RTW89_CN][3] = 44,
[1][0][RTW89_UK][3] = 46,
+ [1][0][RTW89_MEXICO][3] = 72,
+ [1][0][RTW89_UKRAINE][3] = 46,
+ [1][0][RTW89_CHILE][3] = 54,
+ [1][0][RTW89_QATAR][3] = 46,
[1][0][RTW89_FCC][4] = 72,
[1][0][RTW89_ETSI][4] = 46,
[1][0][RTW89_MKK][4] = 48,
[1][0][RTW89_IC][4] = 72,
- [1][0][RTW89_KCC][4] = 50,
+ [1][0][RTW89_KCC][4] = 56,
[1][0][RTW89_ACMA][4] = 46,
[1][0][RTW89_CN][4] = 44,
[1][0][RTW89_UK][4] = 46,
+ [1][0][RTW89_MEXICO][4] = 72,
+ [1][0][RTW89_UKRAINE][4] = 46,
+ [1][0][RTW89_CHILE][4] = 54,
+ [1][0][RTW89_QATAR][4] = 46,
[1][0][RTW89_FCC][5] = 82,
[1][0][RTW89_ETSI][5] = 46,
[1][0][RTW89_MKK][5] = 48,
[1][0][RTW89_IC][5] = 82,
- [1][0][RTW89_KCC][5] = 50,
+ [1][0][RTW89_KCC][5] = 56,
[1][0][RTW89_ACMA][5] = 46,
[1][0][RTW89_CN][5] = 44,
[1][0][RTW89_UK][5] = 46,
+ [1][0][RTW89_MEXICO][5] = 82,
+ [1][0][RTW89_UKRAINE][5] = 46,
+ [1][0][RTW89_CHILE][5] = 82,
+ [1][0][RTW89_QATAR][5] = 46,
[1][0][RTW89_FCC][6] = 58,
[1][0][RTW89_ETSI][6] = 44,
[1][0][RTW89_MKK][6] = 48,
[1][0][RTW89_IC][6] = 58,
- [1][0][RTW89_KCC][6] = 50,
+ [1][0][RTW89_KCC][6] = 56,
[1][0][RTW89_ACMA][6] = 44,
[1][0][RTW89_CN][6] = 44,
[1][0][RTW89_UK][6] = 44,
+ [1][0][RTW89_MEXICO][6] = 58,
+ [1][0][RTW89_UKRAINE][6] = 44,
+ [1][0][RTW89_CHILE][6] = 40,
+ [1][0][RTW89_QATAR][6] = 44,
[1][0][RTW89_FCC][7] = 58,
[1][0][RTW89_ETSI][7] = 46,
[1][0][RTW89_MKK][7] = 48,
[1][0][RTW89_IC][7] = 58,
- [1][0][RTW89_KCC][7] = 50,
+ [1][0][RTW89_KCC][7] = 56,
[1][0][RTW89_ACMA][7] = 46,
[1][0][RTW89_CN][7] = 44,
[1][0][RTW89_UK][7] = 46,
+ [1][0][RTW89_MEXICO][7] = 58,
+ [1][0][RTW89_UKRAINE][7] = 46,
+ [1][0][RTW89_CHILE][7] = 40,
+ [1][0][RTW89_QATAR][7] = 46,
[1][0][RTW89_FCC][8] = 58,
[1][0][RTW89_ETSI][8] = 46,
[1][0][RTW89_MKK][8] = 48,
[1][0][RTW89_IC][8] = 58,
- [1][0][RTW89_KCC][8] = 50,
+ [1][0][RTW89_KCC][8] = 56,
[1][0][RTW89_ACMA][8] = 46,
[1][0][RTW89_CN][8] = 44,
[1][0][RTW89_UK][8] = 46,
+ [1][0][RTW89_MEXICO][8] = 58,
+ [1][0][RTW89_UKRAINE][8] = 46,
+ [1][0][RTW89_CHILE][8] = 40,
+ [1][0][RTW89_QATAR][8] = 46,
[1][0][RTW89_FCC][9] = 54,
[1][0][RTW89_ETSI][9] = 46,
[1][0][RTW89_MKK][9] = 48,
[1][0][RTW89_IC][9] = 54,
- [1][0][RTW89_KCC][9] = 50,
+ [1][0][RTW89_KCC][9] = 56,
[1][0][RTW89_ACMA][9] = 46,
[1][0][RTW89_CN][9] = 44,
[1][0][RTW89_UK][9] = 46,
+ [1][0][RTW89_MEXICO][9] = 54,
+ [1][0][RTW89_UKRAINE][9] = 46,
+ [1][0][RTW89_CHILE][9] = 40,
+ [1][0][RTW89_QATAR][9] = 46,
[1][0][RTW89_FCC][10] = 54,
[1][0][RTW89_ETSI][10] = 46,
[1][0][RTW89_MKK][10] = 48,
[1][0][RTW89_IC][10] = 54,
- [1][0][RTW89_KCC][10] = 50,
+ [1][0][RTW89_KCC][10] = 56,
[1][0][RTW89_ACMA][10] = 46,
[1][0][RTW89_CN][10] = 44,
[1][0][RTW89_UK][10] = 46,
+ [1][0][RTW89_MEXICO][10] = 54,
+ [1][0][RTW89_UKRAINE][10] = 46,
+ [1][0][RTW89_CHILE][10] = 54,
+ [1][0][RTW89_QATAR][10] = 46,
[1][0][RTW89_FCC][11] = 36,
[1][0][RTW89_ETSI][11] = 46,
[1][0][RTW89_MKK][11] = 48,
[1][0][RTW89_IC][11] = 36,
- [1][0][RTW89_KCC][11] = 50,
+ [1][0][RTW89_KCC][11] = 56,
[1][0][RTW89_ACMA][11] = 46,
[1][0][RTW89_CN][11] = 44,
[1][0][RTW89_UK][11] = 46,
+ [1][0][RTW89_MEXICO][11] = 36,
+ [1][0][RTW89_UKRAINE][11] = 46,
+ [1][0][RTW89_CHILE][11] = 36,
+ [1][0][RTW89_QATAR][11] = 46,
[1][0][RTW89_FCC][12] = 4,
[1][0][RTW89_ETSI][12] = 46,
[1][0][RTW89_MKK][12] = 46,
[1][0][RTW89_IC][12] = 4,
- [1][0][RTW89_KCC][12] = 50,
+ [1][0][RTW89_KCC][12] = 56,
[1][0][RTW89_ACMA][12] = 46,
[1][0][RTW89_CN][12] = 42,
[1][0][RTW89_UK][12] = 46,
+ [1][0][RTW89_MEXICO][12] = 4,
+ [1][0][RTW89_UKRAINE][12] = 46,
+ [1][0][RTW89_CHILE][12] = 4,
+ [1][0][RTW89_QATAR][12] = 46,
[1][0][RTW89_FCC][13] = 127,
[1][0][RTW89_ETSI][13] = 127,
[1][0][RTW89_MKK][13] = 127,
@@ -34403,110 +46392,166 @@ const s8 rtw89_8852c_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM]
[1][0][RTW89_ACMA][13] = 127,
[1][0][RTW89_CN][13] = 127,
[1][0][RTW89_UK][13] = 127,
+ [1][0][RTW89_MEXICO][13] = 127,
+ [1][0][RTW89_UKRAINE][13] = 127,
+ [1][0][RTW89_CHILE][13] = 127,
+ [1][0][RTW89_QATAR][13] = 127,
[1][1][RTW89_FCC][0] = 58,
[1][1][RTW89_ETSI][0] = 32,
[1][1][RTW89_MKK][0] = 34,
[1][1][RTW89_IC][0] = 58,
- [1][1][RTW89_KCC][0] = 38,
+ [1][1][RTW89_KCC][0] = 42,
[1][1][RTW89_ACMA][0] = 32,
[1][1][RTW89_CN][0] = 32,
[1][1][RTW89_UK][0] = 32,
+ [1][1][RTW89_MEXICO][0] = 58,
+ [1][1][RTW89_UKRAINE][0] = 32,
+ [1][1][RTW89_CHILE][0] = 58,
+ [1][1][RTW89_QATAR][0] = 32,
[1][1][RTW89_FCC][1] = 58,
[1][1][RTW89_ETSI][1] = 34,
[1][1][RTW89_MKK][1] = 34,
[1][1][RTW89_IC][1] = 58,
- [1][1][RTW89_KCC][1] = 38,
+ [1][1][RTW89_KCC][1] = 42,
[1][1][RTW89_ACMA][1] = 34,
[1][1][RTW89_CN][1] = 32,
[1][1][RTW89_UK][1] = 34,
+ [1][1][RTW89_MEXICO][1] = 58,
+ [1][1][RTW89_UKRAINE][1] = 34,
+ [1][1][RTW89_CHILE][1] = 40,
+ [1][1][RTW89_QATAR][1] = 34,
[1][1][RTW89_FCC][2] = 62,
[1][1][RTW89_ETSI][2] = 34,
[1][1][RTW89_MKK][2] = 34,
[1][1][RTW89_IC][2] = 62,
- [1][1][RTW89_KCC][2] = 38,
+ [1][1][RTW89_KCC][2] = 42,
[1][1][RTW89_ACMA][2] = 34,
[1][1][RTW89_CN][2] = 32,
[1][1][RTW89_UK][2] = 34,
+ [1][1][RTW89_MEXICO][2] = 62,
+ [1][1][RTW89_UKRAINE][2] = 34,
+ [1][1][RTW89_CHILE][2] = 40,
+ [1][1][RTW89_QATAR][2] = 34,
[1][1][RTW89_FCC][3] = 66,
[1][1][RTW89_ETSI][3] = 34,
[1][1][RTW89_MKK][3] = 34,
[1][1][RTW89_IC][3] = 66,
- [1][1][RTW89_KCC][3] = 38,
+ [1][1][RTW89_KCC][3] = 42,
[1][1][RTW89_ACMA][3] = 34,
[1][1][RTW89_CN][3] = 32,
[1][1][RTW89_UK][3] = 34,
+ [1][1][RTW89_MEXICO][3] = 66,
+ [1][1][RTW89_UKRAINE][3] = 34,
+ [1][1][RTW89_CHILE][3] = 40,
+ [1][1][RTW89_QATAR][3] = 34,
[1][1][RTW89_FCC][4] = 70,
[1][1][RTW89_ETSI][4] = 34,
[1][1][RTW89_MKK][4] = 34,
[1][1][RTW89_IC][4] = 70,
- [1][1][RTW89_KCC][4] = 38,
+ [1][1][RTW89_KCC][4] = 44,
[1][1][RTW89_ACMA][4] = 34,
[1][1][RTW89_CN][4] = 32,
[1][1][RTW89_UK][4] = 34,
+ [1][1][RTW89_MEXICO][4] = 70,
+ [1][1][RTW89_UKRAINE][4] = 34,
+ [1][1][RTW89_CHILE][4] = 40,
+ [1][1][RTW89_QATAR][4] = 34,
[1][1][RTW89_FCC][5] = 82,
[1][1][RTW89_ETSI][5] = 34,
[1][1][RTW89_MKK][5] = 34,
[1][1][RTW89_IC][5] = 82,
- [1][1][RTW89_KCC][5] = 38,
+ [1][1][RTW89_KCC][5] = 44,
[1][1][RTW89_ACMA][5] = 34,
[1][1][RTW89_CN][5] = 32,
[1][1][RTW89_UK][5] = 34,
+ [1][1][RTW89_MEXICO][5] = 82,
+ [1][1][RTW89_UKRAINE][5] = 34,
+ [1][1][RTW89_CHILE][5] = 78,
+ [1][1][RTW89_QATAR][5] = 34,
[1][1][RTW89_FCC][6] = 60,
[1][1][RTW89_ETSI][6] = 34,
[1][1][RTW89_MKK][6] = 34,
[1][1][RTW89_IC][6] = 60,
- [1][1][RTW89_KCC][6] = 38,
+ [1][1][RTW89_KCC][6] = 44,
[1][1][RTW89_ACMA][6] = 34,
[1][1][RTW89_CN][6] = 32,
[1][1][RTW89_UK][6] = 34,
+ [1][1][RTW89_MEXICO][6] = 60,
+ [1][1][RTW89_UKRAINE][6] = 34,
+ [1][1][RTW89_CHILE][6] = 30,
+ [1][1][RTW89_QATAR][6] = 34,
[1][1][RTW89_FCC][7] = 56,
[1][1][RTW89_ETSI][7] = 34,
[1][1][RTW89_MKK][7] = 34,
[1][1][RTW89_IC][7] = 56,
- [1][1][RTW89_KCC][7] = 38,
+ [1][1][RTW89_KCC][7] = 44,
[1][1][RTW89_ACMA][7] = 34,
[1][1][RTW89_CN][7] = 32,
[1][1][RTW89_UK][7] = 34,
+ [1][1][RTW89_MEXICO][7] = 56,
+ [1][1][RTW89_UKRAINE][7] = 34,
+ [1][1][RTW89_CHILE][7] = 30,
+ [1][1][RTW89_QATAR][7] = 34,
[1][1][RTW89_FCC][8] = 52,
[1][1][RTW89_ETSI][8] = 34,
[1][1][RTW89_MKK][8] = 34,
[1][1][RTW89_IC][8] = 52,
- [1][1][RTW89_KCC][8] = 38,
+ [1][1][RTW89_KCC][8] = 44,
[1][1][RTW89_ACMA][8] = 34,
[1][1][RTW89_CN][8] = 32,
[1][1][RTW89_UK][8] = 34,
+ [1][1][RTW89_MEXICO][8] = 52,
+ [1][1][RTW89_UKRAINE][8] = 34,
+ [1][1][RTW89_CHILE][8] = 30,
+ [1][1][RTW89_QATAR][8] = 34,
[1][1][RTW89_FCC][9] = 48,
[1][1][RTW89_ETSI][9] = 34,
[1][1][RTW89_MKK][9] = 34,
[1][1][RTW89_IC][9] = 48,
- [1][1][RTW89_KCC][9] = 38,
+ [1][1][RTW89_KCC][9] = 44,
[1][1][RTW89_ACMA][9] = 34,
[1][1][RTW89_CN][9] = 32,
[1][1][RTW89_UK][9] = 34,
+ [1][1][RTW89_MEXICO][9] = 48,
+ [1][1][RTW89_UKRAINE][9] = 34,
+ [1][1][RTW89_CHILE][9] = 30,
+ [1][1][RTW89_QATAR][9] = 34,
[1][1][RTW89_FCC][10] = 48,
[1][1][RTW89_ETSI][10] = 34,
[1][1][RTW89_MKK][10] = 34,
[1][1][RTW89_IC][10] = 48,
- [1][1][RTW89_KCC][10] = 38,
+ [1][1][RTW89_KCC][10] = 44,
[1][1][RTW89_ACMA][10] = 34,
[1][1][RTW89_CN][10] = 32,
[1][1][RTW89_UK][10] = 34,
+ [1][1][RTW89_MEXICO][10] = 48,
+ [1][1][RTW89_UKRAINE][10] = 34,
+ [1][1][RTW89_CHILE][10] = 48,
+ [1][1][RTW89_QATAR][10] = 34,
[1][1][RTW89_FCC][11] = 30,
[1][1][RTW89_ETSI][11] = 34,
[1][1][RTW89_MKK][11] = 34,
[1][1][RTW89_IC][11] = 30,
- [1][1][RTW89_KCC][11] = 38,
+ [1][1][RTW89_KCC][11] = 44,
[1][1][RTW89_ACMA][11] = 34,
[1][1][RTW89_CN][11] = 32,
[1][1][RTW89_UK][11] = 34,
+ [1][1][RTW89_MEXICO][11] = 30,
+ [1][1][RTW89_UKRAINE][11] = 34,
+ [1][1][RTW89_CHILE][11] = 30,
+ [1][1][RTW89_QATAR][11] = 34,
[1][1][RTW89_FCC][12] = -6,
[1][1][RTW89_ETSI][12] = 34,
[1][1][RTW89_MKK][12] = 34,
[1][1][RTW89_IC][12] = -6,
- [1][1][RTW89_KCC][12] = 38,
+ [1][1][RTW89_KCC][12] = 44,
[1][1][RTW89_ACMA][12] = 34,
[1][1][RTW89_CN][12] = 32,
[1][1][RTW89_UK][12] = 34,
+ [1][1][RTW89_MEXICO][12] = -6,
+ [1][1][RTW89_UKRAINE][12] = 34,
+ [1][1][RTW89_CHILE][12] = -6,
+ [1][1][RTW89_QATAR][12] = 34,
[1][1][RTW89_FCC][13] = 127,
[1][1][RTW89_ETSI][13] = 127,
[1][1][RTW89_MKK][13] = 127,
@@ -34515,110 +46560,166 @@ const s8 rtw89_8852c_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM]
[1][1][RTW89_ACMA][13] = 127,
[1][1][RTW89_CN][13] = 127,
[1][1][RTW89_UK][13] = 127,
+ [1][1][RTW89_MEXICO][13] = 127,
+ [1][1][RTW89_UKRAINE][13] = 127,
+ [1][1][RTW89_CHILE][13] = 127,
+ [1][1][RTW89_QATAR][13] = 127,
[2][0][RTW89_FCC][0] = 70,
[2][0][RTW89_ETSI][0] = 58,
[2][0][RTW89_MKK][0] = 58,
[2][0][RTW89_IC][0] = 70,
- [2][0][RTW89_KCC][0] = 64,
+ [2][0][RTW89_KCC][0] = 60,
[2][0][RTW89_ACMA][0] = 58,
[2][0][RTW89_CN][0] = 56,
[2][0][RTW89_UK][0] = 58,
+ [2][0][RTW89_MEXICO][0] = 70,
+ [2][0][RTW89_UKRAINE][0] = 58,
+ [2][0][RTW89_CHILE][0] = 70,
+ [2][0][RTW89_QATAR][0] = 58,
[2][0][RTW89_FCC][1] = 70,
[2][0][RTW89_ETSI][1] = 58,
[2][0][RTW89_MKK][1] = 58,
[2][0][RTW89_IC][1] = 70,
- [2][0][RTW89_KCC][1] = 64,
+ [2][0][RTW89_KCC][1] = 60,
[2][0][RTW89_ACMA][1] = 58,
[2][0][RTW89_CN][1] = 56,
[2][0][RTW89_UK][1] = 58,
+ [2][0][RTW89_MEXICO][1] = 70,
+ [2][0][RTW89_UKRAINE][1] = 58,
+ [2][0][RTW89_CHILE][1] = 54,
+ [2][0][RTW89_QATAR][1] = 58,
[2][0][RTW89_FCC][2] = 72,
[2][0][RTW89_ETSI][2] = 58,
[2][0][RTW89_MKK][2] = 58,
[2][0][RTW89_IC][2] = 72,
- [2][0][RTW89_KCC][2] = 64,
+ [2][0][RTW89_KCC][2] = 60,
[2][0][RTW89_ACMA][2] = 58,
[2][0][RTW89_CN][2] = 56,
[2][0][RTW89_UK][2] = 58,
+ [2][0][RTW89_MEXICO][2] = 72,
+ [2][0][RTW89_UKRAINE][2] = 58,
+ [2][0][RTW89_CHILE][2] = 54,
+ [2][0][RTW89_QATAR][2] = 58,
[2][0][RTW89_FCC][3] = 72,
[2][0][RTW89_ETSI][3] = 58,
[2][0][RTW89_MKK][3] = 58,
[2][0][RTW89_IC][3] = 72,
- [2][0][RTW89_KCC][3] = 64,
+ [2][0][RTW89_KCC][3] = 60,
[2][0][RTW89_ACMA][3] = 58,
[2][0][RTW89_CN][3] = 56,
[2][0][RTW89_UK][3] = 58,
+ [2][0][RTW89_MEXICO][3] = 72,
+ [2][0][RTW89_UKRAINE][3] = 58,
+ [2][0][RTW89_CHILE][3] = 54,
+ [2][0][RTW89_QATAR][3] = 58,
[2][0][RTW89_FCC][4] = 72,
[2][0][RTW89_ETSI][4] = 58,
[2][0][RTW89_MKK][4] = 58,
[2][0][RTW89_IC][4] = 72,
- [2][0][RTW89_KCC][4] = 64,
+ [2][0][RTW89_KCC][4] = 60,
[2][0][RTW89_ACMA][4] = 58,
[2][0][RTW89_CN][4] = 56,
[2][0][RTW89_UK][4] = 58,
+ [2][0][RTW89_MEXICO][4] = 72,
+ [2][0][RTW89_UKRAINE][4] = 58,
+ [2][0][RTW89_CHILE][4] = 54,
+ [2][0][RTW89_QATAR][4] = 58,
[2][0][RTW89_FCC][5] = 82,
[2][0][RTW89_ETSI][5] = 58,
[2][0][RTW89_MKK][5] = 58,
[2][0][RTW89_IC][5] = 82,
- [2][0][RTW89_KCC][5] = 64,
+ [2][0][RTW89_KCC][5] = 60,
[2][0][RTW89_ACMA][5] = 58,
[2][0][RTW89_CN][5] = 56,
[2][0][RTW89_UK][5] = 58,
+ [2][0][RTW89_MEXICO][5] = 82,
+ [2][0][RTW89_UKRAINE][5] = 58,
+ [2][0][RTW89_CHILE][5] = 82,
+ [2][0][RTW89_QATAR][5] = 58,
[2][0][RTW89_FCC][6] = 66,
[2][0][RTW89_ETSI][6] = 56,
[2][0][RTW89_MKK][6] = 58,
[2][0][RTW89_IC][6] = 66,
- [2][0][RTW89_KCC][6] = 64,
+ [2][0][RTW89_KCC][6] = 60,
[2][0][RTW89_ACMA][6] = 56,
[2][0][RTW89_CN][6] = 56,
[2][0][RTW89_UK][6] = 56,
+ [2][0][RTW89_MEXICO][6] = 66,
+ [2][0][RTW89_UKRAINE][6] = 56,
+ [2][0][RTW89_CHILE][6] = 48,
+ [2][0][RTW89_QATAR][6] = 56,
[2][0][RTW89_FCC][7] = 66,
[2][0][RTW89_ETSI][7] = 58,
[2][0][RTW89_MKK][7] = 58,
[2][0][RTW89_IC][7] = 66,
- [2][0][RTW89_KCC][7] = 64,
+ [2][0][RTW89_KCC][7] = 60,
[2][0][RTW89_ACMA][7] = 58,
[2][0][RTW89_CN][7] = 56,
[2][0][RTW89_UK][7] = 58,
+ [2][0][RTW89_MEXICO][7] = 66,
+ [2][0][RTW89_UKRAINE][7] = 58,
+ [2][0][RTW89_CHILE][7] = 48,
+ [2][0][RTW89_QATAR][7] = 58,
[2][0][RTW89_FCC][8] = 66,
[2][0][RTW89_ETSI][8] = 58,
[2][0][RTW89_MKK][8] = 58,
[2][0][RTW89_IC][8] = 66,
- [2][0][RTW89_KCC][8] = 64,
+ [2][0][RTW89_KCC][8] = 60,
[2][0][RTW89_ACMA][8] = 58,
[2][0][RTW89_CN][8] = 56,
[2][0][RTW89_UK][8] = 58,
+ [2][0][RTW89_MEXICO][8] = 66,
+ [2][0][RTW89_UKRAINE][8] = 58,
+ [2][0][RTW89_CHILE][8] = 48,
+ [2][0][RTW89_QATAR][8] = 58,
[2][0][RTW89_FCC][9] = 64,
[2][0][RTW89_ETSI][9] = 58,
[2][0][RTW89_MKK][9] = 58,
[2][0][RTW89_IC][9] = 64,
- [2][0][RTW89_KCC][9] = 64,
+ [2][0][RTW89_KCC][9] = 60,
[2][0][RTW89_ACMA][9] = 58,
[2][0][RTW89_CN][9] = 56,
[2][0][RTW89_UK][9] = 58,
+ [2][0][RTW89_MEXICO][9] = 64,
+ [2][0][RTW89_UKRAINE][9] = 58,
+ [2][0][RTW89_CHILE][9] = 48,
+ [2][0][RTW89_QATAR][9] = 58,
[2][0][RTW89_FCC][10] = 64,
[2][0][RTW89_ETSI][10] = 58,
[2][0][RTW89_MKK][10] = 58,
[2][0][RTW89_IC][10] = 64,
- [2][0][RTW89_KCC][10] = 64,
+ [2][0][RTW89_KCC][10] = 60,
[2][0][RTW89_ACMA][10] = 58,
[2][0][RTW89_CN][10] = 56,
[2][0][RTW89_UK][10] = 58,
+ [2][0][RTW89_MEXICO][10] = 64,
+ [2][0][RTW89_UKRAINE][10] = 58,
+ [2][0][RTW89_CHILE][10] = 64,
+ [2][0][RTW89_QATAR][10] = 58,
[2][0][RTW89_FCC][11] = 48,
[2][0][RTW89_ETSI][11] = 58,
[2][0][RTW89_MKK][11] = 58,
[2][0][RTW89_IC][11] = 48,
- [2][0][RTW89_KCC][11] = 64,
+ [2][0][RTW89_KCC][11] = 60,
[2][0][RTW89_ACMA][11] = 58,
[2][0][RTW89_CN][11] = 56,
[2][0][RTW89_UK][11] = 58,
+ [2][0][RTW89_MEXICO][11] = 48,
+ [2][0][RTW89_UKRAINE][11] = 58,
+ [2][0][RTW89_CHILE][11] = 48,
+ [2][0][RTW89_QATAR][11] = 58,
[2][0][RTW89_FCC][12] = 16,
[2][0][RTW89_ETSI][12] = 58,
[2][0][RTW89_MKK][12] = 58,
[2][0][RTW89_IC][12] = 16,
- [2][0][RTW89_KCC][12] = 64,
+ [2][0][RTW89_KCC][12] = 60,
[2][0][RTW89_ACMA][12] = 58,
[2][0][RTW89_CN][12] = 56,
[2][0][RTW89_UK][12] = 58,
+ [2][0][RTW89_MEXICO][12] = 16,
+ [2][0][RTW89_UKRAINE][12] = 58,
+ [2][0][RTW89_CHILE][12] = 16,
+ [2][0][RTW89_QATAR][12] = 58,
[2][0][RTW89_FCC][13] = 127,
[2][0][RTW89_ETSI][13] = 127,
[2][0][RTW89_MKK][13] = 127,
@@ -34627,110 +46728,166 @@ const s8 rtw89_8852c_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM]
[2][0][RTW89_ACMA][13] = 127,
[2][0][RTW89_CN][13] = 127,
[2][0][RTW89_UK][13] = 127,
+ [2][0][RTW89_MEXICO][13] = 127,
+ [2][0][RTW89_UKRAINE][13] = 127,
+ [2][0][RTW89_CHILE][13] = 127,
+ [2][0][RTW89_QATAR][13] = 127,
[2][1][RTW89_FCC][0] = 64,
[2][1][RTW89_ETSI][0] = 46,
[2][1][RTW89_MKK][0] = 46,
[2][1][RTW89_IC][0] = 64,
- [2][1][RTW89_KCC][0] = 52,
+ [2][1][RTW89_KCC][0] = 48,
[2][1][RTW89_ACMA][0] = 46,
[2][1][RTW89_CN][0] = 44,
[2][1][RTW89_UK][0] = 46,
+ [2][1][RTW89_MEXICO][0] = 64,
+ [2][1][RTW89_UKRAINE][0] = 46,
+ [2][1][RTW89_CHILE][0] = 64,
+ [2][1][RTW89_QATAR][0] = 46,
[2][1][RTW89_FCC][1] = 64,
[2][1][RTW89_ETSI][1] = 46,
[2][1][RTW89_MKK][1] = 46,
[2][1][RTW89_IC][1] = 64,
- [2][1][RTW89_KCC][1] = 52,
+ [2][1][RTW89_KCC][1] = 48,
[2][1][RTW89_ACMA][1] = 46,
[2][1][RTW89_CN][1] = 44,
[2][1][RTW89_UK][1] = 46,
+ [2][1][RTW89_MEXICO][1] = 64,
+ [2][1][RTW89_UKRAINE][1] = 46,
+ [2][1][RTW89_CHILE][1] = 44,
+ [2][1][RTW89_QATAR][1] = 46,
[2][1][RTW89_FCC][2] = 68,
[2][1][RTW89_ETSI][2] = 46,
[2][1][RTW89_MKK][2] = 46,
[2][1][RTW89_IC][2] = 68,
- [2][1][RTW89_KCC][2] = 52,
+ [2][1][RTW89_KCC][2] = 48,
[2][1][RTW89_ACMA][2] = 46,
[2][1][RTW89_CN][2] = 44,
[2][1][RTW89_UK][2] = 46,
+ [2][1][RTW89_MEXICO][2] = 68,
+ [2][1][RTW89_UKRAINE][2] = 46,
+ [2][1][RTW89_CHILE][2] = 44,
+ [2][1][RTW89_QATAR][2] = 46,
[2][1][RTW89_FCC][3] = 72,
[2][1][RTW89_ETSI][3] = 46,
[2][1][RTW89_MKK][3] = 46,
[2][1][RTW89_IC][3] = 72,
- [2][1][RTW89_KCC][3] = 52,
+ [2][1][RTW89_KCC][3] = 48,
[2][1][RTW89_ACMA][3] = 46,
[2][1][RTW89_CN][3] = 44,
[2][1][RTW89_UK][3] = 46,
+ [2][1][RTW89_MEXICO][3] = 72,
+ [2][1][RTW89_UKRAINE][3] = 46,
+ [2][1][RTW89_CHILE][3] = 44,
+ [2][1][RTW89_QATAR][3] = 46,
[2][1][RTW89_FCC][4] = 74,
[2][1][RTW89_ETSI][4] = 46,
[2][1][RTW89_MKK][4] = 46,
[2][1][RTW89_IC][4] = 74,
- [2][1][RTW89_KCC][4] = 50,
+ [2][1][RTW89_KCC][4] = 48,
[2][1][RTW89_ACMA][4] = 46,
[2][1][RTW89_CN][4] = 44,
[2][1][RTW89_UK][4] = 46,
+ [2][1][RTW89_MEXICO][4] = 74,
+ [2][1][RTW89_UKRAINE][4] = 46,
+ [2][1][RTW89_CHILE][4] = 44,
+ [2][1][RTW89_QATAR][4] = 46,
[2][1][RTW89_FCC][5] = 82,
[2][1][RTW89_ETSI][5] = 46,
[2][1][RTW89_MKK][5] = 46,
[2][1][RTW89_IC][5] = 82,
- [2][1][RTW89_KCC][5] = 50,
+ [2][1][RTW89_KCC][5] = 48,
[2][1][RTW89_ACMA][5] = 46,
[2][1][RTW89_CN][5] = 44,
[2][1][RTW89_UK][5] = 46,
+ [2][1][RTW89_MEXICO][5] = 82,
+ [2][1][RTW89_UKRAINE][5] = 46,
+ [2][1][RTW89_CHILE][5] = 78,
+ [2][1][RTW89_QATAR][5] = 46,
[2][1][RTW89_FCC][6] = 72,
[2][1][RTW89_ETSI][6] = 44,
[2][1][RTW89_MKK][6] = 46,
[2][1][RTW89_IC][6] = 72,
- [2][1][RTW89_KCC][6] = 50,
+ [2][1][RTW89_KCC][6] = 48,
[2][1][RTW89_ACMA][6] = 44,
[2][1][RTW89_CN][6] = 44,
[2][1][RTW89_UK][6] = 44,
+ [2][1][RTW89_MEXICO][6] = 72,
+ [2][1][RTW89_UKRAINE][6] = 44,
+ [2][1][RTW89_CHILE][6] = 42,
+ [2][1][RTW89_QATAR][6] = 44,
[2][1][RTW89_FCC][7] = 72,
[2][1][RTW89_ETSI][7] = 46,
[2][1][RTW89_MKK][7] = 46,
[2][1][RTW89_IC][7] = 72,
- [2][1][RTW89_KCC][7] = 50,
+ [2][1][RTW89_KCC][7] = 48,
[2][1][RTW89_ACMA][7] = 46,
[2][1][RTW89_CN][7] = 44,
[2][1][RTW89_UK][7] = 46,
+ [2][1][RTW89_MEXICO][7] = 72,
+ [2][1][RTW89_UKRAINE][7] = 46,
+ [2][1][RTW89_CHILE][7] = 42,
+ [2][1][RTW89_QATAR][7] = 46,
[2][1][RTW89_FCC][8] = 68,
[2][1][RTW89_ETSI][8] = 46,
[2][1][RTW89_MKK][8] = 46,
[2][1][RTW89_IC][8] = 68,
- [2][1][RTW89_KCC][8] = 50,
+ [2][1][RTW89_KCC][8] = 48,
[2][1][RTW89_ACMA][8] = 46,
[2][1][RTW89_CN][8] = 44,
[2][1][RTW89_UK][8] = 46,
+ [2][1][RTW89_MEXICO][8] = 68,
+ [2][1][RTW89_UKRAINE][8] = 46,
+ [2][1][RTW89_CHILE][8] = 42,
+ [2][1][RTW89_QATAR][8] = 46,
[2][1][RTW89_FCC][9] = 64,
[2][1][RTW89_ETSI][9] = 46,
[2][1][RTW89_MKK][9] = 46,
[2][1][RTW89_IC][9] = 64,
- [2][1][RTW89_KCC][9] = 52,
+ [2][1][RTW89_KCC][9] = 48,
[2][1][RTW89_ACMA][9] = 46,
[2][1][RTW89_CN][9] = 44,
[2][1][RTW89_UK][9] = 46,
+ [2][1][RTW89_MEXICO][9] = 64,
+ [2][1][RTW89_UKRAINE][9] = 46,
+ [2][1][RTW89_CHILE][9] = 42,
+ [2][1][RTW89_QATAR][9] = 46,
[2][1][RTW89_FCC][10] = 64,
[2][1][RTW89_ETSI][10] = 46,
[2][1][RTW89_MKK][10] = 46,
[2][1][RTW89_IC][10] = 64,
- [2][1][RTW89_KCC][10] = 52,
+ [2][1][RTW89_KCC][10] = 48,
[2][1][RTW89_ACMA][10] = 46,
[2][1][RTW89_CN][10] = 44,
[2][1][RTW89_UK][10] = 46,
+ [2][1][RTW89_MEXICO][10] = 64,
+ [2][1][RTW89_UKRAINE][10] = 46,
+ [2][1][RTW89_CHILE][10] = 64,
+ [2][1][RTW89_QATAR][10] = 46,
[2][1][RTW89_FCC][11] = 46,
[2][1][RTW89_ETSI][11] = 46,
[2][1][RTW89_MKK][11] = 46,
[2][1][RTW89_IC][11] = 46,
- [2][1][RTW89_KCC][11] = 52,
+ [2][1][RTW89_KCC][11] = 48,
[2][1][RTW89_ACMA][11] = 46,
[2][1][RTW89_CN][11] = 44,
[2][1][RTW89_UK][11] = 46,
+ [2][1][RTW89_MEXICO][11] = 46,
+ [2][1][RTW89_UKRAINE][11] = 46,
+ [2][1][RTW89_CHILE][11] = 46,
+ [2][1][RTW89_QATAR][11] = 46,
[2][1][RTW89_FCC][12] = 6,
[2][1][RTW89_ETSI][12] = 44,
[2][1][RTW89_MKK][12] = 46,
[2][1][RTW89_IC][12] = 6,
- [2][1][RTW89_KCC][12] = 52,
+ [2][1][RTW89_KCC][12] = 48,
[2][1][RTW89_ACMA][12] = 44,
[2][1][RTW89_CN][12] = 42,
[2][1][RTW89_UK][12] = 44,
+ [2][1][RTW89_MEXICO][12] = 6,
+ [2][1][RTW89_UKRAINE][12] = 44,
+ [2][1][RTW89_CHILE][12] = 6,
+ [2][1][RTW89_QATAR][12] = 44,
[2][1][RTW89_FCC][13] = 127,
[2][1][RTW89_ETSI][13] = 127,
[2][1][RTW89_MKK][13] = 127,
@@ -34739,6 +46896,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM]
[2][1][RTW89_ACMA][13] = 127,
[2][1][RTW89_CN][13] = 127,
[2][1][RTW89_UK][13] = 127,
+ [2][1][RTW89_MEXICO][13] = 127,
+ [2][1][RTW89_UKRAINE][13] = 127,
+ [2][1][RTW89_CHILE][13] = 127,
+ [2][1][RTW89_QATAR][13] = 127,
};
static
@@ -34747,168 +46908,168 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][0][RTW89_WW][0] = 16,
[0][0][RTW89_WW][2] = 16,
[0][0][RTW89_WW][4] = 16,
- [0][0][RTW89_WW][6] = 10,
+ [0][0][RTW89_WW][6] = 16,
[0][0][RTW89_WW][8] = 16,
[0][0][RTW89_WW][10] = 16,
[0][0][RTW89_WW][12] = 16,
[0][0][RTW89_WW][14] = 16,
- [0][0][RTW89_WW][15] = 30,
- [0][0][RTW89_WW][17] = 30,
- [0][0][RTW89_WW][19] = 30,
- [0][0][RTW89_WW][21] = 30,
- [0][0][RTW89_WW][23] = 30,
- [0][0][RTW89_WW][25] = 30,
- [0][0][RTW89_WW][27] = 30,
- [0][0][RTW89_WW][29] = 30,
- [0][0][RTW89_WW][31] = 30,
- [0][0][RTW89_WW][33] = 30,
- [0][0][RTW89_WW][35] = 30,
+ [0][0][RTW89_WW][15] = 22,
+ [0][0][RTW89_WW][17] = 22,
+ [0][0][RTW89_WW][19] = 22,
+ [0][0][RTW89_WW][21] = 22,
+ [0][0][RTW89_WW][23] = 22,
+ [0][0][RTW89_WW][25] = 22,
+ [0][0][RTW89_WW][27] = 22,
+ [0][0][RTW89_WW][29] = 22,
+ [0][0][RTW89_WW][31] = 22,
+ [0][0][RTW89_WW][33] = 22,
+ [0][0][RTW89_WW][35] = 22,
[0][0][RTW89_WW][37] = 30,
- [0][0][RTW89_WW][38] = 28,
- [0][0][RTW89_WW][40] = 28,
- [0][0][RTW89_WW][42] = 28,
- [0][0][RTW89_WW][44] = 28,
- [0][0][RTW89_WW][46] = 28,
+ [0][0][RTW89_WW][38] = 26,
+ [0][0][RTW89_WW][40] = 26,
+ [0][0][RTW89_WW][42] = 26,
+ [0][0][RTW89_WW][44] = 26,
+ [0][0][RTW89_WW][46] = 26,
[0][0][RTW89_WW][48] = 46,
[0][0][RTW89_WW][50] = 44,
[0][0][RTW89_WW][52] = 34,
[0][1][RTW89_WW][0] = 4,
[0][1][RTW89_WW][2] = 4,
[0][1][RTW89_WW][4] = 4,
- [0][1][RTW89_WW][6] = 1,
+ [0][1][RTW89_WW][6] = 4,
[0][1][RTW89_WW][8] = 4,
[0][1][RTW89_WW][10] = 4,
[0][1][RTW89_WW][12] = 4,
[0][1][RTW89_WW][14] = 4,
- [0][1][RTW89_WW][15] = 18,
- [0][1][RTW89_WW][17] = 18,
- [0][1][RTW89_WW][19] = 18,
- [0][1][RTW89_WW][21] = 18,
- [0][1][RTW89_WW][23] = 18,
- [0][1][RTW89_WW][25] = 18,
- [0][1][RTW89_WW][27] = 16,
- [0][1][RTW89_WW][29] = 16,
- [0][1][RTW89_WW][31] = 16,
- [0][1][RTW89_WW][33] = 16,
- [0][1][RTW89_WW][35] = 16,
+ [0][1][RTW89_WW][15] = 10,
+ [0][1][RTW89_WW][17] = 10,
+ [0][1][RTW89_WW][19] = 10,
+ [0][1][RTW89_WW][21] = 10,
+ [0][1][RTW89_WW][23] = 10,
+ [0][1][RTW89_WW][25] = 10,
+ [0][1][RTW89_WW][27] = 10,
+ [0][1][RTW89_WW][29] = 10,
+ [0][1][RTW89_WW][31] = 10,
+ [0][1][RTW89_WW][33] = 10,
+ [0][1][RTW89_WW][35] = 10,
[0][1][RTW89_WW][37] = 18,
- [0][1][RTW89_WW][38] = 16,
- [0][1][RTW89_WW][40] = 16,
- [0][1][RTW89_WW][42] = 16,
- [0][1][RTW89_WW][44] = 16,
- [0][1][RTW89_WW][46] = 16,
+ [0][1][RTW89_WW][38] = 14,
+ [0][1][RTW89_WW][40] = 14,
+ [0][1][RTW89_WW][42] = 14,
+ [0][1][RTW89_WW][44] = 14,
+ [0][1][RTW89_WW][46] = 14,
[0][1][RTW89_WW][48] = 20,
[0][1][RTW89_WW][50] = 20,
[0][1][RTW89_WW][52] = 8,
[1][0][RTW89_WW][0] = 26,
[1][0][RTW89_WW][2] = 26,
[1][0][RTW89_WW][4] = 26,
- [1][0][RTW89_WW][6] = 24,
+ [1][0][RTW89_WW][6] = 26,
[1][0][RTW89_WW][8] = 26,
[1][0][RTW89_WW][10] = 26,
[1][0][RTW89_WW][12] = 26,
[1][0][RTW89_WW][14] = 26,
- [1][0][RTW89_WW][15] = 40,
- [1][0][RTW89_WW][17] = 40,
- [1][0][RTW89_WW][19] = 40,
- [1][0][RTW89_WW][21] = 40,
- [1][0][RTW89_WW][23] = 40,
- [1][0][RTW89_WW][25] = 40,
- [1][0][RTW89_WW][27] = 42,
- [1][0][RTW89_WW][29] = 42,
- [1][0][RTW89_WW][31] = 42,
- [1][0][RTW89_WW][33] = 42,
- [1][0][RTW89_WW][35] = 42,
+ [1][0][RTW89_WW][15] = 32,
+ [1][0][RTW89_WW][17] = 32,
+ [1][0][RTW89_WW][19] = 32,
+ [1][0][RTW89_WW][21] = 32,
+ [1][0][RTW89_WW][23] = 32,
+ [1][0][RTW89_WW][25] = 32,
+ [1][0][RTW89_WW][27] = 32,
+ [1][0][RTW89_WW][29] = 32,
+ [1][0][RTW89_WW][31] = 32,
+ [1][0][RTW89_WW][33] = 32,
+ [1][0][RTW89_WW][35] = 32,
[1][0][RTW89_WW][37] = 42,
- [1][0][RTW89_WW][38] = 28,
- [1][0][RTW89_WW][40] = 28,
- [1][0][RTW89_WW][42] = 28,
- [1][0][RTW89_WW][44] = 28,
- [1][0][RTW89_WW][46] = 28,
+ [1][0][RTW89_WW][38] = 26,
+ [1][0][RTW89_WW][40] = 26,
+ [1][0][RTW89_WW][42] = 26,
+ [1][0][RTW89_WW][44] = 26,
+ [1][0][RTW89_WW][46] = 26,
[1][0][RTW89_WW][48] = 56,
[1][0][RTW89_WW][50] = 58,
[1][0][RTW89_WW][52] = 56,
[1][1][RTW89_WW][0] = 14,
[1][1][RTW89_WW][2] = 14,
[1][1][RTW89_WW][4] = 14,
- [1][1][RTW89_WW][6] = 8,
+ [1][1][RTW89_WW][6] = 14,
[1][1][RTW89_WW][8] = 14,
[1][1][RTW89_WW][10] = 14,
[1][1][RTW89_WW][12] = 14,
[1][1][RTW89_WW][14] = 14,
- [1][1][RTW89_WW][15] = 28,
- [1][1][RTW89_WW][17] = 28,
- [1][1][RTW89_WW][19] = 28,
- [1][1][RTW89_WW][21] = 28,
- [1][1][RTW89_WW][23] = 28,
- [1][1][RTW89_WW][25] = 28,
- [1][1][RTW89_WW][27] = 30,
- [1][1][RTW89_WW][29] = 30,
- [1][1][RTW89_WW][31] = 30,
- [1][1][RTW89_WW][33] = 30,
- [1][1][RTW89_WW][35] = 30,
+ [1][1][RTW89_WW][15] = 20,
+ [1][1][RTW89_WW][17] = 20,
+ [1][1][RTW89_WW][19] = 20,
+ [1][1][RTW89_WW][21] = 20,
+ [1][1][RTW89_WW][23] = 20,
+ [1][1][RTW89_WW][25] = 20,
+ [1][1][RTW89_WW][27] = 20,
+ [1][1][RTW89_WW][29] = 20,
+ [1][1][RTW89_WW][31] = 20,
+ [1][1][RTW89_WW][33] = 20,
+ [1][1][RTW89_WW][35] = 20,
[1][1][RTW89_WW][37] = 32,
- [1][1][RTW89_WW][38] = 16,
- [1][1][RTW89_WW][40] = 16,
- [1][1][RTW89_WW][42] = 16,
- [1][1][RTW89_WW][44] = 16,
- [1][1][RTW89_WW][46] = 16,
+ [1][1][RTW89_WW][38] = 14,
+ [1][1][RTW89_WW][40] = 14,
+ [1][1][RTW89_WW][42] = 14,
+ [1][1][RTW89_WW][44] = 14,
+ [1][1][RTW89_WW][46] = 14,
[1][1][RTW89_WW][48] = 34,
[1][1][RTW89_WW][50] = 34,
[1][1][RTW89_WW][52] = 30,
[2][0][RTW89_WW][0] = 40,
[2][0][RTW89_WW][2] = 40,
[2][0][RTW89_WW][4] = 40,
- [2][0][RTW89_WW][6] = 36,
+ [2][0][RTW89_WW][6] = 38,
[2][0][RTW89_WW][8] = 40,
[2][0][RTW89_WW][10] = 40,
[2][0][RTW89_WW][12] = 40,
[2][0][RTW89_WW][14] = 40,
- [2][0][RTW89_WW][15] = 52,
- [2][0][RTW89_WW][17] = 52,
- [2][0][RTW89_WW][19] = 52,
- [2][0][RTW89_WW][21] = 52,
- [2][0][RTW89_WW][23] = 52,
- [2][0][RTW89_WW][25] = 52,
- [2][0][RTW89_WW][27] = 52,
- [2][0][RTW89_WW][29] = 52,
- [2][0][RTW89_WW][31] = 52,
- [2][0][RTW89_WW][33] = 52,
- [2][0][RTW89_WW][35] = 52,
+ [2][0][RTW89_WW][15] = 46,
+ [2][0][RTW89_WW][17] = 46,
+ [2][0][RTW89_WW][19] = 46,
+ [2][0][RTW89_WW][21] = 46,
+ [2][0][RTW89_WW][23] = 46,
+ [2][0][RTW89_WW][25] = 46,
+ [2][0][RTW89_WW][27] = 46,
+ [2][0][RTW89_WW][29] = 46,
+ [2][0][RTW89_WW][31] = 46,
+ [2][0][RTW89_WW][33] = 46,
+ [2][0][RTW89_WW][35] = 46,
[2][0][RTW89_WW][37] = 52,
- [2][0][RTW89_WW][38] = 28,
- [2][0][RTW89_WW][40] = 28,
- [2][0][RTW89_WW][42] = 28,
- [2][0][RTW89_WW][44] = 28,
- [2][0][RTW89_WW][46] = 28,
+ [2][0][RTW89_WW][38] = 26,
+ [2][0][RTW89_WW][40] = 26,
+ [2][0][RTW89_WW][42] = 26,
+ [2][0][RTW89_WW][44] = 26,
+ [2][0][RTW89_WW][46] = 26,
[2][0][RTW89_WW][48] = 64,
[2][0][RTW89_WW][50] = 64,
[2][0][RTW89_WW][52] = 64,
[2][1][RTW89_WW][0] = 26,
[2][1][RTW89_WW][2] = 26,
[2][1][RTW89_WW][4] = 26,
- [2][1][RTW89_WW][6] = 20,
+ [2][1][RTW89_WW][6] = 26,
[2][1][RTW89_WW][8] = 28,
[2][1][RTW89_WW][10] = 28,
[2][1][RTW89_WW][12] = 28,
[2][1][RTW89_WW][14] = 28,
- [2][1][RTW89_WW][15] = 40,
- [2][1][RTW89_WW][17] = 40,
- [2][1][RTW89_WW][19] = 40,
- [2][1][RTW89_WW][21] = 40,
- [2][1][RTW89_WW][23] = 40,
- [2][1][RTW89_WW][25] = 40,
- [2][1][RTW89_WW][27] = 40,
- [2][1][RTW89_WW][29] = 40,
- [2][1][RTW89_WW][31] = 40,
- [2][1][RTW89_WW][33] = 40,
- [2][1][RTW89_WW][35] = 40,
+ [2][1][RTW89_WW][15] = 34,
+ [2][1][RTW89_WW][17] = 34,
+ [2][1][RTW89_WW][19] = 34,
+ [2][1][RTW89_WW][21] = 34,
+ [2][1][RTW89_WW][23] = 34,
+ [2][1][RTW89_WW][25] = 34,
+ [2][1][RTW89_WW][27] = 34,
+ [2][1][RTW89_WW][29] = 34,
+ [2][1][RTW89_WW][31] = 34,
+ [2][1][RTW89_WW][33] = 34,
+ [2][1][RTW89_WW][35] = 34,
[2][1][RTW89_WW][37] = 42,
- [2][1][RTW89_WW][38] = 16,
- [2][1][RTW89_WW][40] = 16,
- [2][1][RTW89_WW][42] = 16,
- [2][1][RTW89_WW][44] = 16,
- [2][1][RTW89_WW][46] = 16,
+ [2][1][RTW89_WW][38] = 14,
+ [2][1][RTW89_WW][40] = 14,
+ [2][1][RTW89_WW][42] = 14,
+ [2][1][RTW89_WW][44] = 14,
+ [2][1][RTW89_WW][46] = 14,
[2][1][RTW89_WW][48] = 40,
[2][1][RTW89_WW][50] = 40,
[2][1][RTW89_WW][52] = 40,
@@ -34920,6 +47081,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][0][RTW89_ACMA][0] = 30,
[0][0][RTW89_CN][0] = 16,
[0][0][RTW89_UK][0] = 30,
+ [0][0][RTW89_MEXICO][0] = 50,
+ [0][0][RTW89_UKRAINE][0] = 22,
+ [0][0][RTW89_CHILE][0] = 50,
+ [0][0][RTW89_QATAR][0] = 30,
[0][0][RTW89_FCC][2] = 50,
[0][0][RTW89_ETSI][2] = 30,
[0][0][RTW89_MKK][2] = 36,
@@ -34928,6 +47093,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][0][RTW89_ACMA][2] = 30,
[0][0][RTW89_CN][2] = 16,
[0][0][RTW89_UK][2] = 30,
+ [0][0][RTW89_MEXICO][2] = 50,
+ [0][0][RTW89_UKRAINE][2] = 22,
+ [0][0][RTW89_CHILE][2] = 50,
+ [0][0][RTW89_QATAR][2] = 30,
[0][0][RTW89_FCC][4] = 50,
[0][0][RTW89_ETSI][4] = 30,
[0][0][RTW89_MKK][4] = 22,
@@ -34936,30 +47105,46 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][0][RTW89_ACMA][4] = 30,
[0][0][RTW89_CN][4] = 16,
[0][0][RTW89_UK][4] = 30,
+ [0][0][RTW89_MEXICO][4] = 50,
+ [0][0][RTW89_UKRAINE][4] = 22,
+ [0][0][RTW89_CHILE][4] = 50,
+ [0][0][RTW89_QATAR][4] = 30,
[0][0][RTW89_FCC][6] = 50,
[0][0][RTW89_ETSI][6] = 30,
[0][0][RTW89_MKK][6] = 22,
[0][0][RTW89_IC][6] = 32,
- [0][0][RTW89_KCC][6] = 10,
+ [0][0][RTW89_KCC][6] = 18,
[0][0][RTW89_ACMA][6] = 30,
[0][0][RTW89_CN][6] = 16,
[0][0][RTW89_UK][6] = 30,
+ [0][0][RTW89_MEXICO][6] = 50,
+ [0][0][RTW89_UKRAINE][6] = 22,
+ [0][0][RTW89_CHILE][6] = 50,
+ [0][0][RTW89_QATAR][6] = 30,
[0][0][RTW89_FCC][8] = 52,
[0][0][RTW89_ETSI][8] = 28,
[0][0][RTW89_MKK][8] = 18,
[0][0][RTW89_IC][8] = 52,
- [0][0][RTW89_KCC][8] = 44,
+ [0][0][RTW89_KCC][8] = 40,
[0][0][RTW89_ACMA][8] = 28,
[0][0][RTW89_CN][8] = 16,
[0][0][RTW89_UK][8] = 28,
+ [0][0][RTW89_MEXICO][8] = 52,
+ [0][0][RTW89_UKRAINE][8] = 22,
+ [0][0][RTW89_CHILE][8] = 52,
+ [0][0][RTW89_QATAR][8] = 28,
[0][0][RTW89_FCC][10] = 52,
[0][0][RTW89_ETSI][10] = 28,
[0][0][RTW89_MKK][10] = 18,
[0][0][RTW89_IC][10] = 52,
- [0][0][RTW89_KCC][10] = 44,
+ [0][0][RTW89_KCC][10] = 40,
[0][0][RTW89_ACMA][10] = 28,
[0][0][RTW89_CN][10] = 16,
[0][0][RTW89_UK][10] = 28,
+ [0][0][RTW89_MEXICO][10] = 52,
+ [0][0][RTW89_UKRAINE][10] = 22,
+ [0][0][RTW89_CHILE][10] = 52,
+ [0][0][RTW89_QATAR][10] = 28,
[0][0][RTW89_FCC][12] = 52,
[0][0][RTW89_ETSI][12] = 28,
[0][0][RTW89_MKK][12] = 34,
@@ -34968,6 +47153,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][0][RTW89_ACMA][12] = 28,
[0][0][RTW89_CN][12] = 16,
[0][0][RTW89_UK][12] = 28,
+ [0][0][RTW89_MEXICO][12] = 52,
+ [0][0][RTW89_UKRAINE][12] = 22,
+ [0][0][RTW89_CHILE][12] = 52,
+ [0][0][RTW89_QATAR][12] = 28,
[0][0][RTW89_FCC][14] = 52,
[0][0][RTW89_ETSI][14] = 28,
[0][0][RTW89_MKK][14] = 34,
@@ -34976,70 +47165,106 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][0][RTW89_ACMA][14] = 28,
[0][0][RTW89_CN][14] = 16,
[0][0][RTW89_UK][14] = 28,
+ [0][0][RTW89_MEXICO][14] = 52,
+ [0][0][RTW89_UKRAINE][14] = 22,
+ [0][0][RTW89_CHILE][14] = 52,
+ [0][0][RTW89_QATAR][14] = 28,
[0][0][RTW89_FCC][15] = 52,
[0][0][RTW89_ETSI][15] = 30,
[0][0][RTW89_MKK][15] = 56,
[0][0][RTW89_IC][15] = 52,
- [0][0][RTW89_KCC][15] = 42,
+ [0][0][RTW89_KCC][15] = 40,
[0][0][RTW89_ACMA][15] = 30,
[0][0][RTW89_CN][15] = 127,
[0][0][RTW89_UK][15] = 30,
+ [0][0][RTW89_MEXICO][15] = 52,
+ [0][0][RTW89_UKRAINE][15] = 22,
+ [0][0][RTW89_CHILE][15] = 52,
+ [0][0][RTW89_QATAR][15] = 30,
[0][0][RTW89_FCC][17] = 52,
[0][0][RTW89_ETSI][17] = 30,
[0][0][RTW89_MKK][17] = 58,
[0][0][RTW89_IC][17] = 52,
- [0][0][RTW89_KCC][17] = 42,
+ [0][0][RTW89_KCC][17] = 40,
[0][0][RTW89_ACMA][17] = 30,
[0][0][RTW89_CN][17] = 127,
[0][0][RTW89_UK][17] = 30,
+ [0][0][RTW89_MEXICO][17] = 52,
+ [0][0][RTW89_UKRAINE][17] = 22,
+ [0][0][RTW89_CHILE][17] = 52,
+ [0][0][RTW89_QATAR][17] = 30,
[0][0][RTW89_FCC][19] = 52,
[0][0][RTW89_ETSI][19] = 30,
[0][0][RTW89_MKK][19] = 58,
[0][0][RTW89_IC][19] = 52,
- [0][0][RTW89_KCC][19] = 42,
+ [0][0][RTW89_KCC][19] = 40,
[0][0][RTW89_ACMA][19] = 30,
[0][0][RTW89_CN][19] = 127,
[0][0][RTW89_UK][19] = 30,
+ [0][0][RTW89_MEXICO][19] = 52,
+ [0][0][RTW89_UKRAINE][19] = 22,
+ [0][0][RTW89_CHILE][19] = 52,
+ [0][0][RTW89_QATAR][19] = 30,
[0][0][RTW89_FCC][21] = 52,
[0][0][RTW89_ETSI][21] = 30,
[0][0][RTW89_MKK][21] = 58,
[0][0][RTW89_IC][21] = 52,
- [0][0][RTW89_KCC][21] = 42,
+ [0][0][RTW89_KCC][21] = 40,
[0][0][RTW89_ACMA][21] = 30,
[0][0][RTW89_CN][21] = 127,
[0][0][RTW89_UK][21] = 30,
+ [0][0][RTW89_MEXICO][21] = 52,
+ [0][0][RTW89_UKRAINE][21] = 22,
+ [0][0][RTW89_CHILE][21] = 52,
+ [0][0][RTW89_QATAR][21] = 30,
[0][0][RTW89_FCC][23] = 52,
[0][0][RTW89_ETSI][23] = 30,
[0][0][RTW89_MKK][23] = 58,
[0][0][RTW89_IC][23] = 52,
- [0][0][RTW89_KCC][23] = 42,
+ [0][0][RTW89_KCC][23] = 40,
[0][0][RTW89_ACMA][23] = 30,
[0][0][RTW89_CN][23] = 127,
[0][0][RTW89_UK][23] = 30,
+ [0][0][RTW89_MEXICO][23] = 52,
+ [0][0][RTW89_UKRAINE][23] = 22,
+ [0][0][RTW89_CHILE][23] = 52,
+ [0][0][RTW89_QATAR][23] = 30,
[0][0][RTW89_FCC][25] = 52,
[0][0][RTW89_ETSI][25] = 30,
[0][0][RTW89_MKK][25] = 58,
[0][0][RTW89_IC][25] = 127,
- [0][0][RTW89_KCC][25] = 42,
+ [0][0][RTW89_KCC][25] = 40,
[0][0][RTW89_ACMA][25] = 127,
[0][0][RTW89_CN][25] = 127,
[0][0][RTW89_UK][25] = 30,
+ [0][0][RTW89_MEXICO][25] = 52,
+ [0][0][RTW89_UKRAINE][25] = 22,
+ [0][0][RTW89_CHILE][25] = 52,
+ [0][0][RTW89_QATAR][25] = 30,
[0][0][RTW89_FCC][27] = 52,
[0][0][RTW89_ETSI][27] = 30,
[0][0][RTW89_MKK][27] = 58,
[0][0][RTW89_IC][27] = 127,
- [0][0][RTW89_KCC][27] = 42,
+ [0][0][RTW89_KCC][27] = 40,
[0][0][RTW89_ACMA][27] = 127,
[0][0][RTW89_CN][27] = 127,
[0][0][RTW89_UK][27] = 30,
+ [0][0][RTW89_MEXICO][27] = 52,
+ [0][0][RTW89_UKRAINE][27] = 22,
+ [0][0][RTW89_CHILE][27] = 52,
+ [0][0][RTW89_QATAR][27] = 30,
[0][0][RTW89_FCC][29] = 52,
[0][0][RTW89_ETSI][29] = 30,
[0][0][RTW89_MKK][29] = 58,
[0][0][RTW89_IC][29] = 127,
- [0][0][RTW89_KCC][29] = 42,
+ [0][0][RTW89_KCC][29] = 40,
[0][0][RTW89_ACMA][29] = 127,
[0][0][RTW89_CN][29] = 127,
[0][0][RTW89_UK][29] = 30,
+ [0][0][RTW89_MEXICO][29] = 52,
+ [0][0][RTW89_UKRAINE][29] = 22,
+ [0][0][RTW89_CHILE][29] = 52,
+ [0][0][RTW89_QATAR][29] = 30,
[0][0][RTW89_FCC][31] = 52,
[0][0][RTW89_ETSI][31] = 30,
[0][0][RTW89_MKK][31] = 58,
@@ -35048,6 +47273,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][0][RTW89_ACMA][31] = 30,
[0][0][RTW89_CN][31] = 127,
[0][0][RTW89_UK][31] = 30,
+ [0][0][RTW89_MEXICO][31] = 52,
+ [0][0][RTW89_UKRAINE][31] = 22,
+ [0][0][RTW89_CHILE][31] = 52,
+ [0][0][RTW89_QATAR][31] = 30,
[0][0][RTW89_FCC][33] = 44,
[0][0][RTW89_ETSI][33] = 30,
[0][0][RTW89_MKK][33] = 58,
@@ -35056,6 +47285,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][0][RTW89_ACMA][33] = 30,
[0][0][RTW89_CN][33] = 127,
[0][0][RTW89_UK][33] = 30,
+ [0][0][RTW89_MEXICO][33] = 44,
+ [0][0][RTW89_UKRAINE][33] = 22,
+ [0][0][RTW89_CHILE][33] = 44,
+ [0][0][RTW89_QATAR][33] = 30,
[0][0][RTW89_FCC][35] = 44,
[0][0][RTW89_ETSI][35] = 30,
[0][0][RTW89_MKK][35] = 58,
@@ -35064,6 +47297,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][0][RTW89_ACMA][35] = 30,
[0][0][RTW89_CN][35] = 127,
[0][0][RTW89_UK][35] = 30,
+ [0][0][RTW89_MEXICO][35] = 44,
+ [0][0][RTW89_UKRAINE][35] = 22,
+ [0][0][RTW89_CHILE][35] = 44,
+ [0][0][RTW89_QATAR][35] = 30,
[0][0][RTW89_FCC][37] = 52,
[0][0][RTW89_ETSI][37] = 127,
[0][0][RTW89_MKK][37] = 58,
@@ -35072,6 +47309,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][0][RTW89_ACMA][37] = 52,
[0][0][RTW89_CN][37] = 127,
[0][0][RTW89_UK][37] = 30,
+ [0][0][RTW89_MEXICO][37] = 52,
+ [0][0][RTW89_UKRAINE][37] = 127,
+ [0][0][RTW89_CHILE][37] = 52,
+ [0][0][RTW89_QATAR][37] = 127,
[0][0][RTW89_FCC][38] = 64,
[0][0][RTW89_ETSI][38] = 28,
[0][0][RTW89_MKK][38] = 127,
@@ -35080,6 +47321,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][0][RTW89_ACMA][38] = 64,
[0][0][RTW89_CN][38] = 54,
[0][0][RTW89_UK][38] = 30,
+ [0][0][RTW89_MEXICO][38] = 64,
+ [0][0][RTW89_UKRAINE][38] = 26,
+ [0][0][RTW89_CHILE][38] = 64,
+ [0][0][RTW89_QATAR][38] = 26,
[0][0][RTW89_FCC][40] = 64,
[0][0][RTW89_ETSI][40] = 28,
[0][0][RTW89_MKK][40] = 127,
@@ -35088,6 +47333,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][0][RTW89_ACMA][40] = 64,
[0][0][RTW89_CN][40] = 54,
[0][0][RTW89_UK][40] = 30,
+ [0][0][RTW89_MEXICO][40] = 64,
+ [0][0][RTW89_UKRAINE][40] = 26,
+ [0][0][RTW89_CHILE][40] = 64,
+ [0][0][RTW89_QATAR][40] = 26,
[0][0][RTW89_FCC][42] = 60,
[0][0][RTW89_ETSI][42] = 28,
[0][0][RTW89_MKK][42] = 127,
@@ -35096,6 +47345,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][0][RTW89_ACMA][42] = 60,
[0][0][RTW89_CN][42] = 54,
[0][0][RTW89_UK][42] = 30,
+ [0][0][RTW89_MEXICO][42] = 60,
+ [0][0][RTW89_UKRAINE][42] = 26,
+ [0][0][RTW89_CHILE][42] = 60,
+ [0][0][RTW89_QATAR][42] = 26,
[0][0][RTW89_FCC][44] = 60,
[0][0][RTW89_ETSI][44] = 28,
[0][0][RTW89_MKK][44] = 127,
@@ -35104,6 +47357,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][0][RTW89_ACMA][44] = 60,
[0][0][RTW89_CN][44] = 54,
[0][0][RTW89_UK][44] = 30,
+ [0][0][RTW89_MEXICO][44] = 60,
+ [0][0][RTW89_UKRAINE][44] = 26,
+ [0][0][RTW89_CHILE][44] = 60,
+ [0][0][RTW89_QATAR][44] = 26,
[0][0][RTW89_FCC][46] = 60,
[0][0][RTW89_ETSI][46] = 28,
[0][0][RTW89_MKK][46] = 127,
@@ -35112,6 +47369,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][0][RTW89_ACMA][46] = 60,
[0][0][RTW89_CN][46] = 54,
[0][0][RTW89_UK][46] = 30,
+ [0][0][RTW89_MEXICO][46] = 60,
+ [0][0][RTW89_UKRAINE][46] = 26,
+ [0][0][RTW89_CHILE][46] = 60,
+ [0][0][RTW89_QATAR][46] = 26,
[0][0][RTW89_FCC][48] = 46,
[0][0][RTW89_ETSI][48] = 127,
[0][0][RTW89_MKK][48] = 127,
@@ -35120,6 +47381,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][0][RTW89_ACMA][48] = 127,
[0][0][RTW89_CN][48] = 127,
[0][0][RTW89_UK][48] = 127,
+ [0][0][RTW89_MEXICO][48] = 127,
+ [0][0][RTW89_UKRAINE][48] = 127,
+ [0][0][RTW89_CHILE][48] = 127,
+ [0][0][RTW89_QATAR][48] = 127,
[0][0][RTW89_FCC][50] = 44,
[0][0][RTW89_ETSI][50] = 127,
[0][0][RTW89_MKK][50] = 127,
@@ -35128,6 +47393,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][0][RTW89_ACMA][50] = 127,
[0][0][RTW89_CN][50] = 127,
[0][0][RTW89_UK][50] = 127,
+ [0][0][RTW89_MEXICO][50] = 127,
+ [0][0][RTW89_UKRAINE][50] = 127,
+ [0][0][RTW89_CHILE][50] = 127,
+ [0][0][RTW89_QATAR][50] = 127,
[0][0][RTW89_FCC][52] = 34,
[0][0][RTW89_ETSI][52] = 127,
[0][0][RTW89_MKK][52] = 127,
@@ -35136,38 +47405,58 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][0][RTW89_ACMA][52] = 127,
[0][0][RTW89_CN][52] = 127,
[0][0][RTW89_UK][52] = 127,
+ [0][0][RTW89_MEXICO][52] = 127,
+ [0][0][RTW89_UKRAINE][52] = 127,
+ [0][0][RTW89_CHILE][52] = 127,
+ [0][0][RTW89_QATAR][52] = 127,
[0][1][RTW89_FCC][0] = 30,
[0][1][RTW89_ETSI][0] = 18,
[0][1][RTW89_MKK][0] = 20,
[0][1][RTW89_IC][0] = 8,
- [0][1][RTW89_KCC][0] = 26,
+ [0][1][RTW89_KCC][0] = 32,
[0][1][RTW89_ACMA][0] = 18,
[0][1][RTW89_CN][0] = 4,
[0][1][RTW89_UK][0] = 18,
+ [0][1][RTW89_MEXICO][0] = 30,
+ [0][1][RTW89_UKRAINE][0] = 10,
+ [0][1][RTW89_CHILE][0] = 30,
+ [0][1][RTW89_QATAR][0] = 18,
[0][1][RTW89_FCC][2] = 32,
[0][1][RTW89_ETSI][2] = 18,
[0][1][RTW89_MKK][2] = 20,
[0][1][RTW89_IC][2] = 8,
- [0][1][RTW89_KCC][2] = 26,
+ [0][1][RTW89_KCC][2] = 32,
[0][1][RTW89_ACMA][2] = 18,
[0][1][RTW89_CN][2] = 4,
[0][1][RTW89_UK][2] = 18,
+ [0][1][RTW89_MEXICO][2] = 32,
+ [0][1][RTW89_UKRAINE][2] = 10,
+ [0][1][RTW89_CHILE][2] = 32,
+ [0][1][RTW89_QATAR][2] = 18,
[0][1][RTW89_FCC][4] = 30,
[0][1][RTW89_ETSI][4] = 18,
[0][1][RTW89_MKK][4] = 8,
[0][1][RTW89_IC][4] = 8,
- [0][1][RTW89_KCC][4] = 26,
+ [0][1][RTW89_KCC][4] = 32,
[0][1][RTW89_ACMA][4] = 18,
[0][1][RTW89_CN][4] = 4,
[0][1][RTW89_UK][4] = 18,
+ [0][1][RTW89_MEXICO][4] = 30,
+ [0][1][RTW89_UKRAINE][4] = 10,
+ [0][1][RTW89_CHILE][4] = 30,
+ [0][1][RTW89_QATAR][4] = 18,
[0][1][RTW89_FCC][6] = 30,
[0][1][RTW89_ETSI][6] = 18,
[0][1][RTW89_MKK][6] = 8,
[0][1][RTW89_IC][6] = 8,
- [0][1][RTW89_KCC][6] = 0,
+ [0][1][RTW89_KCC][6] = 6,
[0][1][RTW89_ACMA][6] = 18,
[0][1][RTW89_CN][6] = 4,
[0][1][RTW89_UK][6] = 18,
+ [0][1][RTW89_MEXICO][6] = 30,
+ [0][1][RTW89_UKRAINE][6] = 10,
+ [0][1][RTW89_CHILE][6] = 30,
+ [0][1][RTW89_QATAR][6] = 18,
[0][1][RTW89_FCC][8] = 30,
[0][1][RTW89_ETSI][8] = 16,
[0][1][RTW89_MKK][8] = 20,
@@ -35176,6 +47465,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][1][RTW89_ACMA][8] = 16,
[0][1][RTW89_CN][8] = 4,
[0][1][RTW89_UK][8] = 16,
+ [0][1][RTW89_MEXICO][8] = 30,
+ [0][1][RTW89_UKRAINE][8] = 10,
+ [0][1][RTW89_CHILE][8] = 30,
+ [0][1][RTW89_QATAR][8] = 16,
[0][1][RTW89_FCC][10] = 30,
[0][1][RTW89_ETSI][10] = 16,
[0][1][RTW89_MKK][10] = 20,
@@ -35184,22 +47477,34 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][1][RTW89_ACMA][10] = 16,
[0][1][RTW89_CN][10] = 4,
[0][1][RTW89_UK][10] = 16,
+ [0][1][RTW89_MEXICO][10] = 30,
+ [0][1][RTW89_UKRAINE][10] = 10,
+ [0][1][RTW89_CHILE][10] = 30,
+ [0][1][RTW89_QATAR][10] = 16,
[0][1][RTW89_FCC][12] = 30,
[0][1][RTW89_ETSI][12] = 16,
[0][1][RTW89_MKK][12] = 34,
[0][1][RTW89_IC][12] = 30,
- [0][1][RTW89_KCC][12] = 28,
+ [0][1][RTW89_KCC][12] = 26,
[0][1][RTW89_ACMA][12] = 16,
[0][1][RTW89_CN][12] = 4,
[0][1][RTW89_UK][12] = 16,
+ [0][1][RTW89_MEXICO][12] = 30,
+ [0][1][RTW89_UKRAINE][12] = 10,
+ [0][1][RTW89_CHILE][12] = 30,
+ [0][1][RTW89_QATAR][12] = 16,
[0][1][RTW89_FCC][14] = 30,
[0][1][RTW89_ETSI][14] = 16,
[0][1][RTW89_MKK][14] = 34,
[0][1][RTW89_IC][14] = 30,
- [0][1][RTW89_KCC][14] = 28,
+ [0][1][RTW89_KCC][14] = 26,
[0][1][RTW89_ACMA][14] = 16,
[0][1][RTW89_CN][14] = 4,
[0][1][RTW89_UK][14] = 16,
+ [0][1][RTW89_MEXICO][14] = 30,
+ [0][1][RTW89_UKRAINE][14] = 10,
+ [0][1][RTW89_CHILE][14] = 30,
+ [0][1][RTW89_QATAR][14] = 16,
[0][1][RTW89_FCC][15] = 32,
[0][1][RTW89_ETSI][15] = 18,
[0][1][RTW89_MKK][15] = 44,
@@ -35208,6 +47513,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][1][RTW89_ACMA][15] = 18,
[0][1][RTW89_CN][15] = 127,
[0][1][RTW89_UK][15] = 18,
+ [0][1][RTW89_MEXICO][15] = 32,
+ [0][1][RTW89_UKRAINE][15] = 10,
+ [0][1][RTW89_CHILE][15] = 32,
+ [0][1][RTW89_QATAR][15] = 18,
[0][1][RTW89_FCC][17] = 32,
[0][1][RTW89_ETSI][17] = 18,
[0][1][RTW89_MKK][17] = 44,
@@ -35216,6 +47525,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][1][RTW89_ACMA][17] = 18,
[0][1][RTW89_CN][17] = 127,
[0][1][RTW89_UK][17] = 18,
+ [0][1][RTW89_MEXICO][17] = 32,
+ [0][1][RTW89_UKRAINE][17] = 10,
+ [0][1][RTW89_CHILE][17] = 32,
+ [0][1][RTW89_QATAR][17] = 18,
[0][1][RTW89_FCC][19] = 32,
[0][1][RTW89_ETSI][19] = 18,
[0][1][RTW89_MKK][19] = 44,
@@ -35224,6 +47537,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][1][RTW89_ACMA][19] = 18,
[0][1][RTW89_CN][19] = 127,
[0][1][RTW89_UK][19] = 18,
+ [0][1][RTW89_MEXICO][19] = 32,
+ [0][1][RTW89_UKRAINE][19] = 10,
+ [0][1][RTW89_CHILE][19] = 32,
+ [0][1][RTW89_QATAR][19] = 18,
[0][1][RTW89_FCC][21] = 32,
[0][1][RTW89_ETSI][21] = 18,
[0][1][RTW89_MKK][21] = 44,
@@ -35232,6 +47549,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][1][RTW89_ACMA][21] = 18,
[0][1][RTW89_CN][21] = 127,
[0][1][RTW89_UK][21] = 18,
+ [0][1][RTW89_MEXICO][21] = 32,
+ [0][1][RTW89_UKRAINE][21] = 10,
+ [0][1][RTW89_CHILE][21] = 32,
+ [0][1][RTW89_QATAR][21] = 18,
[0][1][RTW89_FCC][23] = 32,
[0][1][RTW89_ETSI][23] = 18,
[0][1][RTW89_MKK][23] = 44,
@@ -35240,6 +47561,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][1][RTW89_ACMA][23] = 18,
[0][1][RTW89_CN][23] = 127,
[0][1][RTW89_UK][23] = 18,
+ [0][1][RTW89_MEXICO][23] = 32,
+ [0][1][RTW89_UKRAINE][23] = 10,
+ [0][1][RTW89_CHILE][23] = 32,
+ [0][1][RTW89_QATAR][23] = 18,
[0][1][RTW89_FCC][25] = 32,
[0][1][RTW89_ETSI][25] = 18,
[0][1][RTW89_MKK][25] = 44,
@@ -35248,6 +47573,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][1][RTW89_ACMA][25] = 127,
[0][1][RTW89_CN][25] = 127,
[0][1][RTW89_UK][25] = 18,
+ [0][1][RTW89_MEXICO][25] = 32,
+ [0][1][RTW89_UKRAINE][25] = 10,
+ [0][1][RTW89_CHILE][25] = 32,
+ [0][1][RTW89_QATAR][25] = 18,
[0][1][RTW89_FCC][27] = 32,
[0][1][RTW89_ETSI][27] = 16,
[0][1][RTW89_MKK][27] = 44,
@@ -35256,6 +47585,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][1][RTW89_ACMA][27] = 127,
[0][1][RTW89_CN][27] = 127,
[0][1][RTW89_UK][27] = 16,
+ [0][1][RTW89_MEXICO][27] = 32,
+ [0][1][RTW89_UKRAINE][27] = 10,
+ [0][1][RTW89_CHILE][27] = 32,
+ [0][1][RTW89_QATAR][27] = 16,
[0][1][RTW89_FCC][29] = 32,
[0][1][RTW89_ETSI][29] = 16,
[0][1][RTW89_MKK][29] = 44,
@@ -35264,6 +47597,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][1][RTW89_ACMA][29] = 127,
[0][1][RTW89_CN][29] = 127,
[0][1][RTW89_UK][29] = 16,
+ [0][1][RTW89_MEXICO][29] = 32,
+ [0][1][RTW89_UKRAINE][29] = 10,
+ [0][1][RTW89_CHILE][29] = 32,
+ [0][1][RTW89_QATAR][29] = 16,
[0][1][RTW89_FCC][31] = 32,
[0][1][RTW89_ETSI][31] = 16,
[0][1][RTW89_MKK][31] = 44,
@@ -35272,6 +47609,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][1][RTW89_ACMA][31] = 16,
[0][1][RTW89_CN][31] = 127,
[0][1][RTW89_UK][31] = 16,
+ [0][1][RTW89_MEXICO][31] = 32,
+ [0][1][RTW89_UKRAINE][31] = 10,
+ [0][1][RTW89_CHILE][31] = 32,
+ [0][1][RTW89_QATAR][31] = 16,
[0][1][RTW89_FCC][33] = 30,
[0][1][RTW89_ETSI][33] = 16,
[0][1][RTW89_MKK][33] = 44,
@@ -35280,6 +47621,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][1][RTW89_ACMA][33] = 16,
[0][1][RTW89_CN][33] = 127,
[0][1][RTW89_UK][33] = 16,
+ [0][1][RTW89_MEXICO][33] = 30,
+ [0][1][RTW89_UKRAINE][33] = 10,
+ [0][1][RTW89_CHILE][33] = 30,
+ [0][1][RTW89_QATAR][33] = 16,
[0][1][RTW89_FCC][35] = 30,
[0][1][RTW89_ETSI][35] = 16,
[0][1][RTW89_MKK][35] = 44,
@@ -35288,6 +47633,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][1][RTW89_ACMA][35] = 16,
[0][1][RTW89_CN][35] = 127,
[0][1][RTW89_UK][35] = 16,
+ [0][1][RTW89_MEXICO][35] = 30,
+ [0][1][RTW89_UKRAINE][35] = 10,
+ [0][1][RTW89_CHILE][35] = 30,
+ [0][1][RTW89_QATAR][35] = 16,
[0][1][RTW89_FCC][37] = 34,
[0][1][RTW89_ETSI][37] = 127,
[0][1][RTW89_MKK][37] = 44,
@@ -35296,46 +47645,70 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][1][RTW89_ACMA][37] = 34,
[0][1][RTW89_CN][37] = 127,
[0][1][RTW89_UK][37] = 18,
+ [0][1][RTW89_MEXICO][37] = 34,
+ [0][1][RTW89_UKRAINE][37] = 127,
+ [0][1][RTW89_CHILE][37] = 34,
+ [0][1][RTW89_QATAR][37] = 127,
[0][1][RTW89_FCC][38] = 62,
[0][1][RTW89_ETSI][38] = 16,
[0][1][RTW89_MKK][38] = 127,
[0][1][RTW89_IC][38] = 62,
- [0][1][RTW89_KCC][38] = 28,
+ [0][1][RTW89_KCC][38] = 30,
[0][1][RTW89_ACMA][38] = 62,
[0][1][RTW89_CN][38] = 42,
[0][1][RTW89_UK][38] = 18,
+ [0][1][RTW89_MEXICO][38] = 62,
+ [0][1][RTW89_UKRAINE][38] = 14,
+ [0][1][RTW89_CHILE][38] = 62,
+ [0][1][RTW89_QATAR][38] = 14,
[0][1][RTW89_FCC][40] = 62,
[0][1][RTW89_ETSI][40] = 16,
[0][1][RTW89_MKK][40] = 127,
[0][1][RTW89_IC][40] = 62,
- [0][1][RTW89_KCC][40] = 28,
+ [0][1][RTW89_KCC][40] = 30,
[0][1][RTW89_ACMA][40] = 62,
[0][1][RTW89_CN][40] = 42,
[0][1][RTW89_UK][40] = 18,
+ [0][1][RTW89_MEXICO][40] = 62,
+ [0][1][RTW89_UKRAINE][40] = 14,
+ [0][1][RTW89_CHILE][40] = 62,
+ [0][1][RTW89_QATAR][40] = 14,
[0][1][RTW89_FCC][42] = 58,
[0][1][RTW89_ETSI][42] = 16,
[0][1][RTW89_MKK][42] = 127,
[0][1][RTW89_IC][42] = 58,
- [0][1][RTW89_KCC][42] = 28,
+ [0][1][RTW89_KCC][42] = 30,
[0][1][RTW89_ACMA][42] = 58,
[0][1][RTW89_CN][42] = 42,
[0][1][RTW89_UK][42] = 18,
+ [0][1][RTW89_MEXICO][42] = 58,
+ [0][1][RTW89_UKRAINE][42] = 14,
+ [0][1][RTW89_CHILE][42] = 58,
+ [0][1][RTW89_QATAR][42] = 14,
[0][1][RTW89_FCC][44] = 56,
[0][1][RTW89_ETSI][44] = 16,
[0][1][RTW89_MKK][44] = 127,
[0][1][RTW89_IC][44] = 56,
- [0][1][RTW89_KCC][44] = 28,
+ [0][1][RTW89_KCC][44] = 30,
[0][1][RTW89_ACMA][44] = 56,
[0][1][RTW89_CN][44] = 42,
[0][1][RTW89_UK][44] = 18,
+ [0][1][RTW89_MEXICO][44] = 56,
+ [0][1][RTW89_UKRAINE][44] = 14,
+ [0][1][RTW89_CHILE][44] = 56,
+ [0][1][RTW89_QATAR][44] = 14,
[0][1][RTW89_FCC][46] = 56,
[0][1][RTW89_ETSI][46] = 16,
[0][1][RTW89_MKK][46] = 127,
[0][1][RTW89_IC][46] = 56,
- [0][1][RTW89_KCC][46] = 28,
+ [0][1][RTW89_KCC][46] = 30,
[0][1][RTW89_ACMA][46] = 56,
[0][1][RTW89_CN][46] = 42,
[0][1][RTW89_UK][46] = 18,
+ [0][1][RTW89_MEXICO][46] = 56,
+ [0][1][RTW89_UKRAINE][46] = 14,
+ [0][1][RTW89_CHILE][46] = 56,
+ [0][1][RTW89_QATAR][46] = 14,
[0][1][RTW89_FCC][48] = 20,
[0][1][RTW89_ETSI][48] = 127,
[0][1][RTW89_MKK][48] = 127,
@@ -35344,6 +47717,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][1][RTW89_ACMA][48] = 127,
[0][1][RTW89_CN][48] = 127,
[0][1][RTW89_UK][48] = 127,
+ [0][1][RTW89_MEXICO][48] = 127,
+ [0][1][RTW89_UKRAINE][48] = 127,
+ [0][1][RTW89_CHILE][48] = 127,
+ [0][1][RTW89_QATAR][48] = 127,
[0][1][RTW89_FCC][50] = 20,
[0][1][RTW89_ETSI][50] = 127,
[0][1][RTW89_MKK][50] = 127,
@@ -35352,6 +47729,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][1][RTW89_ACMA][50] = 127,
[0][1][RTW89_CN][50] = 127,
[0][1][RTW89_UK][50] = 127,
+ [0][1][RTW89_MEXICO][50] = 127,
+ [0][1][RTW89_UKRAINE][50] = 127,
+ [0][1][RTW89_CHILE][50] = 127,
+ [0][1][RTW89_QATAR][50] = 127,
[0][1][RTW89_FCC][52] = 8,
[0][1][RTW89_ETSI][52] = 127,
[0][1][RTW89_MKK][52] = 127,
@@ -35360,70 +47741,106 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[0][1][RTW89_ACMA][52] = 127,
[0][1][RTW89_CN][52] = 127,
[0][1][RTW89_UK][52] = 127,
+ [0][1][RTW89_MEXICO][52] = 127,
+ [0][1][RTW89_UKRAINE][52] = 127,
+ [0][1][RTW89_CHILE][52] = 127,
+ [0][1][RTW89_QATAR][52] = 127,
[1][0][RTW89_FCC][0] = 62,
[1][0][RTW89_ETSI][0] = 40,
[1][0][RTW89_MKK][0] = 48,
[1][0][RTW89_IC][0] = 42,
- [1][0][RTW89_KCC][0] = 50,
+ [1][0][RTW89_KCC][0] = 54,
[1][0][RTW89_ACMA][0] = 40,
[1][0][RTW89_CN][0] = 26,
[1][0][RTW89_UK][0] = 40,
+ [1][0][RTW89_MEXICO][0] = 62,
+ [1][0][RTW89_UKRAINE][0] = 32,
+ [1][0][RTW89_CHILE][0] = 62,
+ [1][0][RTW89_QATAR][0] = 40,
[1][0][RTW89_FCC][2] = 62,
[1][0][RTW89_ETSI][2] = 40,
[1][0][RTW89_MKK][2] = 48,
[1][0][RTW89_IC][2] = 42,
- [1][0][RTW89_KCC][2] = 50,
+ [1][0][RTW89_KCC][2] = 54,
[1][0][RTW89_ACMA][2] = 40,
[1][0][RTW89_CN][2] = 26,
[1][0][RTW89_UK][2] = 40,
+ [1][0][RTW89_MEXICO][2] = 62,
+ [1][0][RTW89_UKRAINE][2] = 32,
+ [1][0][RTW89_CHILE][2] = 62,
+ [1][0][RTW89_QATAR][2] = 40,
[1][0][RTW89_FCC][4] = 64,
[1][0][RTW89_ETSI][4] = 40,
[1][0][RTW89_MKK][4] = 40,
[1][0][RTW89_IC][4] = 42,
- [1][0][RTW89_KCC][4] = 50,
+ [1][0][RTW89_KCC][4] = 54,
[1][0][RTW89_ACMA][4] = 40,
[1][0][RTW89_CN][4] = 26,
[1][0][RTW89_UK][4] = 40,
+ [1][0][RTW89_MEXICO][4] = 64,
+ [1][0][RTW89_UKRAINE][4] = 32,
+ [1][0][RTW89_CHILE][4] = 64,
+ [1][0][RTW89_QATAR][4] = 40,
[1][0][RTW89_FCC][6] = 64,
[1][0][RTW89_ETSI][6] = 40,
[1][0][RTW89_MKK][6] = 40,
[1][0][RTW89_IC][6] = 42,
- [1][0][RTW89_KCC][6] = 24,
+ [1][0][RTW89_KCC][6] = 32,
[1][0][RTW89_ACMA][6] = 40,
[1][0][RTW89_CN][6] = 26,
[1][0][RTW89_UK][6] = 40,
+ [1][0][RTW89_MEXICO][6] = 64,
+ [1][0][RTW89_UKRAINE][6] = 32,
+ [1][0][RTW89_CHILE][6] = 64,
+ [1][0][RTW89_QATAR][6] = 40,
[1][0][RTW89_FCC][8] = 62,
[1][0][RTW89_ETSI][8] = 40,
[1][0][RTW89_MKK][8] = 34,
[1][0][RTW89_IC][8] = 62,
- [1][0][RTW89_KCC][8] = 52,
+ [1][0][RTW89_KCC][8] = 50,
[1][0][RTW89_ACMA][8] = 40,
[1][0][RTW89_CN][8] = 26,
[1][0][RTW89_UK][8] = 40,
+ [1][0][RTW89_MEXICO][8] = 62,
+ [1][0][RTW89_UKRAINE][8] = 32,
+ [1][0][RTW89_CHILE][8] = 62,
+ [1][0][RTW89_QATAR][8] = 40,
[1][0][RTW89_FCC][10] = 62,
[1][0][RTW89_ETSI][10] = 40,
[1][0][RTW89_MKK][10] = 34,
[1][0][RTW89_IC][10] = 62,
- [1][0][RTW89_KCC][10] = 52,
+ [1][0][RTW89_KCC][10] = 50,
[1][0][RTW89_ACMA][10] = 40,
[1][0][RTW89_CN][10] = 26,
[1][0][RTW89_UK][10] = 40,
+ [1][0][RTW89_MEXICO][10] = 62,
+ [1][0][RTW89_UKRAINE][10] = 32,
+ [1][0][RTW89_CHILE][10] = 62,
+ [1][0][RTW89_QATAR][10] = 40,
[1][0][RTW89_FCC][12] = 62,
[1][0][RTW89_ETSI][12] = 40,
[1][0][RTW89_MKK][12] = 46,
[1][0][RTW89_IC][12] = 62,
- [1][0][RTW89_KCC][12] = 52,
+ [1][0][RTW89_KCC][12] = 50,
[1][0][RTW89_ACMA][12] = 40,
[1][0][RTW89_CN][12] = 26,
[1][0][RTW89_UK][12] = 40,
+ [1][0][RTW89_MEXICO][12] = 62,
+ [1][0][RTW89_UKRAINE][12] = 32,
+ [1][0][RTW89_CHILE][12] = 62,
+ [1][0][RTW89_QATAR][12] = 40,
[1][0][RTW89_FCC][14] = 62,
[1][0][RTW89_ETSI][14] = 40,
[1][0][RTW89_MKK][14] = 46,
[1][0][RTW89_IC][14] = 62,
- [1][0][RTW89_KCC][14] = 52,
+ [1][0][RTW89_KCC][14] = 50,
[1][0][RTW89_ACMA][14] = 40,
[1][0][RTW89_CN][14] = 26,
[1][0][RTW89_UK][14] = 40,
+ [1][0][RTW89_MEXICO][14] = 62,
+ [1][0][RTW89_UKRAINE][14] = 32,
+ [1][0][RTW89_CHILE][14] = 62,
+ [1][0][RTW89_QATAR][14] = 40,
[1][0][RTW89_FCC][15] = 62,
[1][0][RTW89_ETSI][15] = 40,
[1][0][RTW89_MKK][15] = 62,
@@ -35432,6 +47849,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[1][0][RTW89_ACMA][15] = 40,
[1][0][RTW89_CN][15] = 127,
[1][0][RTW89_UK][15] = 40,
+ [1][0][RTW89_MEXICO][15] = 62,
+ [1][0][RTW89_UKRAINE][15] = 32,
+ [1][0][RTW89_CHILE][15] = 62,
+ [1][0][RTW89_QATAR][15] = 40,
[1][0][RTW89_FCC][17] = 62,
[1][0][RTW89_ETSI][17] = 40,
[1][0][RTW89_MKK][17] = 68,
@@ -35440,6 +47861,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[1][0][RTW89_ACMA][17] = 40,
[1][0][RTW89_CN][17] = 127,
[1][0][RTW89_UK][17] = 40,
+ [1][0][RTW89_MEXICO][17] = 62,
+ [1][0][RTW89_UKRAINE][17] = 32,
+ [1][0][RTW89_CHILE][17] = 62,
+ [1][0][RTW89_QATAR][17] = 40,
[1][0][RTW89_FCC][19] = 64,
[1][0][RTW89_ETSI][19] = 40,
[1][0][RTW89_MKK][19] = 68,
@@ -35448,6 +47873,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[1][0][RTW89_ACMA][19] = 40,
[1][0][RTW89_CN][19] = 127,
[1][0][RTW89_UK][19] = 40,
+ [1][0][RTW89_MEXICO][19] = 64,
+ [1][0][RTW89_UKRAINE][19] = 32,
+ [1][0][RTW89_CHILE][19] = 64,
+ [1][0][RTW89_QATAR][19] = 40,
[1][0][RTW89_FCC][21] = 64,
[1][0][RTW89_ETSI][21] = 40,
[1][0][RTW89_MKK][21] = 68,
@@ -35456,6 +47885,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[1][0][RTW89_ACMA][21] = 40,
[1][0][RTW89_CN][21] = 127,
[1][0][RTW89_UK][21] = 40,
+ [1][0][RTW89_MEXICO][21] = 64,
+ [1][0][RTW89_UKRAINE][21] = 32,
+ [1][0][RTW89_CHILE][21] = 64,
+ [1][0][RTW89_QATAR][21] = 40,
[1][0][RTW89_FCC][23] = 64,
[1][0][RTW89_ETSI][23] = 40,
[1][0][RTW89_MKK][23] = 68,
@@ -35464,6 +47897,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[1][0][RTW89_ACMA][23] = 40,
[1][0][RTW89_CN][23] = 127,
[1][0][RTW89_UK][23] = 40,
+ [1][0][RTW89_MEXICO][23] = 64,
+ [1][0][RTW89_UKRAINE][23] = 32,
+ [1][0][RTW89_CHILE][23] = 64,
+ [1][0][RTW89_QATAR][23] = 40,
[1][0][RTW89_FCC][25] = 64,
[1][0][RTW89_ETSI][25] = 40,
[1][0][RTW89_MKK][25] = 68,
@@ -35472,6 +47909,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[1][0][RTW89_ACMA][25] = 127,
[1][0][RTW89_CN][25] = 127,
[1][0][RTW89_UK][25] = 40,
+ [1][0][RTW89_MEXICO][25] = 64,
+ [1][0][RTW89_UKRAINE][25] = 32,
+ [1][0][RTW89_CHILE][25] = 64,
+ [1][0][RTW89_QATAR][25] = 40,
[1][0][RTW89_FCC][27] = 64,
[1][0][RTW89_ETSI][27] = 42,
[1][0][RTW89_MKK][27] = 68,
@@ -35480,6 +47921,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[1][0][RTW89_ACMA][27] = 127,
[1][0][RTW89_CN][27] = 127,
[1][0][RTW89_UK][27] = 42,
+ [1][0][RTW89_MEXICO][27] = 64,
+ [1][0][RTW89_UKRAINE][27] = 32,
+ [1][0][RTW89_CHILE][27] = 64,
+ [1][0][RTW89_QATAR][27] = 42,
[1][0][RTW89_FCC][29] = 64,
[1][0][RTW89_ETSI][29] = 42,
[1][0][RTW89_MKK][29] = 68,
@@ -35488,38 +47933,58 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[1][0][RTW89_ACMA][29] = 127,
[1][0][RTW89_CN][29] = 127,
[1][0][RTW89_UK][29] = 42,
+ [1][0][RTW89_MEXICO][29] = 64,
+ [1][0][RTW89_UKRAINE][29] = 32,
+ [1][0][RTW89_CHILE][29] = 64,
+ [1][0][RTW89_QATAR][29] = 42,
[1][0][RTW89_FCC][31] = 64,
[1][0][RTW89_ETSI][31] = 42,
[1][0][RTW89_MKK][31] = 68,
[1][0][RTW89_IC][31] = 56,
- [1][0][RTW89_KCC][31] = 52,
+ [1][0][RTW89_KCC][31] = 50,
[1][0][RTW89_ACMA][31] = 42,
[1][0][RTW89_CN][31] = 127,
[1][0][RTW89_UK][31] = 42,
+ [1][0][RTW89_MEXICO][31] = 64,
+ [1][0][RTW89_UKRAINE][31] = 32,
+ [1][0][RTW89_CHILE][31] = 64,
+ [1][0][RTW89_QATAR][31] = 42,
[1][0][RTW89_FCC][33] = 56,
[1][0][RTW89_ETSI][33] = 42,
[1][0][RTW89_MKK][33] = 68,
[1][0][RTW89_IC][33] = 56,
- [1][0][RTW89_KCC][33] = 52,
+ [1][0][RTW89_KCC][33] = 50,
[1][0][RTW89_ACMA][33] = 42,
[1][0][RTW89_CN][33] = 127,
[1][0][RTW89_UK][33] = 42,
+ [1][0][RTW89_MEXICO][33] = 56,
+ [1][0][RTW89_UKRAINE][33] = 32,
+ [1][0][RTW89_CHILE][33] = 56,
+ [1][0][RTW89_QATAR][33] = 42,
[1][0][RTW89_FCC][35] = 56,
[1][0][RTW89_ETSI][35] = 42,
[1][0][RTW89_MKK][35] = 68,
[1][0][RTW89_IC][35] = 56,
- [1][0][RTW89_KCC][35] = 52,
+ [1][0][RTW89_KCC][35] = 50,
[1][0][RTW89_ACMA][35] = 42,
[1][0][RTW89_CN][35] = 127,
[1][0][RTW89_UK][35] = 42,
+ [1][0][RTW89_MEXICO][35] = 56,
+ [1][0][RTW89_UKRAINE][35] = 32,
+ [1][0][RTW89_CHILE][35] = 56,
+ [1][0][RTW89_QATAR][35] = 42,
[1][0][RTW89_FCC][37] = 66,
[1][0][RTW89_ETSI][37] = 127,
[1][0][RTW89_MKK][37] = 68,
[1][0][RTW89_IC][37] = 66,
- [1][0][RTW89_KCC][37] = 52,
+ [1][0][RTW89_KCC][37] = 50,
[1][0][RTW89_ACMA][37] = 66,
[1][0][RTW89_CN][37] = 127,
[1][0][RTW89_UK][37] = 42,
+ [1][0][RTW89_MEXICO][37] = 66,
+ [1][0][RTW89_UKRAINE][37] = 127,
+ [1][0][RTW89_CHILE][37] = 66,
+ [1][0][RTW89_QATAR][37] = 127,
[1][0][RTW89_FCC][38] = 76,
[1][0][RTW89_ETSI][38] = 28,
[1][0][RTW89_MKK][38] = 127,
@@ -35528,6 +47993,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[1][0][RTW89_ACMA][38] = 76,
[1][0][RTW89_CN][38] = 66,
[1][0][RTW89_UK][38] = 44,
+ [1][0][RTW89_MEXICO][38] = 76,
+ [1][0][RTW89_UKRAINE][38] = 26,
+ [1][0][RTW89_CHILE][38] = 76,
+ [1][0][RTW89_QATAR][38] = 26,
[1][0][RTW89_FCC][40] = 76,
[1][0][RTW89_ETSI][40] = 28,
[1][0][RTW89_MKK][40] = 127,
@@ -35536,6 +48005,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[1][0][RTW89_ACMA][40] = 76,
[1][0][RTW89_CN][40] = 66,
[1][0][RTW89_UK][40] = 44,
+ [1][0][RTW89_MEXICO][40] = 76,
+ [1][0][RTW89_UKRAINE][40] = 26,
+ [1][0][RTW89_CHILE][40] = 76,
+ [1][0][RTW89_QATAR][40] = 26,
[1][0][RTW89_FCC][42] = 68,
[1][0][RTW89_ETSI][42] = 28,
[1][0][RTW89_MKK][42] = 127,
@@ -35544,6 +48017,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[1][0][RTW89_ACMA][42] = 68,
[1][0][RTW89_CN][42] = 66,
[1][0][RTW89_UK][42] = 44,
+ [1][0][RTW89_MEXICO][42] = 68,
+ [1][0][RTW89_UKRAINE][42] = 26,
+ [1][0][RTW89_CHILE][42] = 68,
+ [1][0][RTW89_QATAR][42] = 26,
[1][0][RTW89_FCC][44] = 70,
[1][0][RTW89_ETSI][44] = 28,
[1][0][RTW89_MKK][44] = 127,
@@ -35552,6 +48029,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[1][0][RTW89_ACMA][44] = 70,
[1][0][RTW89_CN][44] = 66,
[1][0][RTW89_UK][44] = 42,
+ [1][0][RTW89_MEXICO][44] = 70,
+ [1][0][RTW89_UKRAINE][44] = 26,
+ [1][0][RTW89_CHILE][44] = 70,
+ [1][0][RTW89_QATAR][44] = 26,
[1][0][RTW89_FCC][46] = 70,
[1][0][RTW89_ETSI][46] = 28,
[1][0][RTW89_MKK][46] = 127,
@@ -35560,6 +48041,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[1][0][RTW89_ACMA][46] = 70,
[1][0][RTW89_CN][46] = 66,
[1][0][RTW89_UK][46] = 42,
+ [1][0][RTW89_MEXICO][46] = 70,
+ [1][0][RTW89_UKRAINE][46] = 26,
+ [1][0][RTW89_CHILE][46] = 70,
+ [1][0][RTW89_QATAR][46] = 26,
[1][0][RTW89_FCC][48] = 56,
[1][0][RTW89_ETSI][48] = 127,
[1][0][RTW89_MKK][48] = 127,
@@ -35568,6 +48053,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[1][0][RTW89_ACMA][48] = 127,
[1][0][RTW89_CN][48] = 127,
[1][0][RTW89_UK][48] = 127,
+ [1][0][RTW89_MEXICO][48] = 127,
+ [1][0][RTW89_UKRAINE][48] = 127,
+ [1][0][RTW89_CHILE][48] = 127,
+ [1][0][RTW89_QATAR][48] = 127,
[1][0][RTW89_FCC][50] = 58,
[1][0][RTW89_ETSI][50] = 127,
[1][0][RTW89_MKK][50] = 127,
@@ -35576,6 +48065,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[1][0][RTW89_ACMA][50] = 127,
[1][0][RTW89_CN][50] = 127,
[1][0][RTW89_UK][50] = 127,
+ [1][0][RTW89_MEXICO][50] = 127,
+ [1][0][RTW89_UKRAINE][50] = 127,
+ [1][0][RTW89_CHILE][50] = 127,
+ [1][0][RTW89_QATAR][50] = 127,
[1][0][RTW89_FCC][52] = 56,
[1][0][RTW89_ETSI][52] = 127,
[1][0][RTW89_MKK][52] = 127,
@@ -35584,54 +48077,82 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[1][0][RTW89_ACMA][52] = 127,
[1][0][RTW89_CN][52] = 127,
[1][0][RTW89_UK][52] = 127,
+ [1][0][RTW89_MEXICO][52] = 127,
+ [1][0][RTW89_UKRAINE][52] = 127,
+ [1][0][RTW89_CHILE][52] = 127,
+ [1][0][RTW89_QATAR][52] = 127,
[1][1][RTW89_FCC][0] = 44,
[1][1][RTW89_ETSI][0] = 30,
[1][1][RTW89_MKK][0] = 34,
[1][1][RTW89_IC][0] = 20,
- [1][1][RTW89_KCC][0] = 34,
+ [1][1][RTW89_KCC][0] = 40,
[1][1][RTW89_ACMA][0] = 30,
[1][1][RTW89_CN][0] = 14,
[1][1][RTW89_UK][0] = 30,
+ [1][1][RTW89_MEXICO][0] = 44,
+ [1][1][RTW89_UKRAINE][0] = 20,
+ [1][1][RTW89_CHILE][0] = 44,
+ [1][1][RTW89_QATAR][0] = 30,
[1][1][RTW89_FCC][2] = 44,
[1][1][RTW89_ETSI][2] = 30,
[1][1][RTW89_MKK][2] = 34,
[1][1][RTW89_IC][2] = 18,
- [1][1][RTW89_KCC][2] = 34,
+ [1][1][RTW89_KCC][2] = 40,
[1][1][RTW89_ACMA][2] = 30,
[1][1][RTW89_CN][2] = 14,
[1][1][RTW89_UK][2] = 30,
+ [1][1][RTW89_MEXICO][2] = 44,
+ [1][1][RTW89_UKRAINE][2] = 20,
+ [1][1][RTW89_CHILE][2] = 44,
+ [1][1][RTW89_QATAR][2] = 30,
[1][1][RTW89_FCC][4] = 46,
[1][1][RTW89_ETSI][4] = 30,
[1][1][RTW89_MKK][4] = 26,
[1][1][RTW89_IC][4] = 20,
- [1][1][RTW89_KCC][4] = 34,
+ [1][1][RTW89_KCC][4] = 40,
[1][1][RTW89_ACMA][4] = 30,
[1][1][RTW89_CN][4] = 14,
[1][1][RTW89_UK][4] = 30,
+ [1][1][RTW89_MEXICO][4] = 46,
+ [1][1][RTW89_UKRAINE][4] = 20,
+ [1][1][RTW89_CHILE][4] = 46,
+ [1][1][RTW89_QATAR][4] = 30,
[1][1][RTW89_FCC][6] = 46,
[1][1][RTW89_ETSI][6] = 30,
[1][1][RTW89_MKK][6] = 26,
[1][1][RTW89_IC][6] = 20,
- [1][1][RTW89_KCC][6] = 8,
+ [1][1][RTW89_KCC][6] = 18,
[1][1][RTW89_ACMA][6] = 30,
[1][1][RTW89_CN][6] = 14,
[1][1][RTW89_UK][6] = 30,
+ [1][1][RTW89_MEXICO][6] = 46,
+ [1][1][RTW89_UKRAINE][6] = 20,
+ [1][1][RTW89_CHILE][6] = 46,
+ [1][1][RTW89_QATAR][6] = 30,
[1][1][RTW89_FCC][8] = 44,
[1][1][RTW89_ETSI][8] = 30,
[1][1][RTW89_MKK][8] = 20,
[1][1][RTW89_IC][8] = 44,
- [1][1][RTW89_KCC][8] = 34,
+ [1][1][RTW89_KCC][8] = 38,
[1][1][RTW89_ACMA][8] = 30,
[1][1][RTW89_CN][8] = 14,
[1][1][RTW89_UK][8] = 30,
+ [1][1][RTW89_MEXICO][8] = 44,
+ [1][1][RTW89_UKRAINE][8] = 20,
+ [1][1][RTW89_CHILE][8] = 44,
+ [1][1][RTW89_QATAR][8] = 30,
[1][1][RTW89_FCC][10] = 44,
[1][1][RTW89_ETSI][10] = 30,
[1][1][RTW89_MKK][10] = 20,
[1][1][RTW89_IC][10] = 44,
- [1][1][RTW89_KCC][10] = 34,
+ [1][1][RTW89_KCC][10] = 38,
[1][1][RTW89_ACMA][10] = 30,
[1][1][RTW89_CN][10] = 14,
[1][1][RTW89_UK][10] = 30,
+ [1][1][RTW89_MEXICO][10] = 44,
+ [1][1][RTW89_UKRAINE][10] = 20,
+ [1][1][RTW89_CHILE][10] = 44,
+ [1][1][RTW89_QATAR][10] = 30,
[1][1][RTW89_FCC][12] = 44,
[1][1][RTW89_ETSI][12] = 30,
[1][1][RTW89_MKK][12] = 34,
@@ -35640,6 +48161,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[1][1][RTW89_ACMA][12] = 30,
[1][1][RTW89_CN][12] = 14,
[1][1][RTW89_UK][12] = 30,
+ [1][1][RTW89_MEXICO][12] = 44,
+ [1][1][RTW89_UKRAINE][12] = 20,
+ [1][1][RTW89_CHILE][12] = 44,
+ [1][1][RTW89_QATAR][12] = 30,
[1][1][RTW89_FCC][14] = 44,
[1][1][RTW89_ETSI][14] = 30,
[1][1][RTW89_MKK][14] = 34,
@@ -35648,142 +48173,214 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[1][1][RTW89_ACMA][14] = 30,
[1][1][RTW89_CN][14] = 14,
[1][1][RTW89_UK][14] = 30,
+ [1][1][RTW89_MEXICO][14] = 44,
+ [1][1][RTW89_UKRAINE][14] = 20,
+ [1][1][RTW89_CHILE][14] = 44,
+ [1][1][RTW89_QATAR][14] = 30,
[1][1][RTW89_FCC][15] = 44,
[1][1][RTW89_ETSI][15] = 28,
[1][1][RTW89_MKK][15] = 56,
[1][1][RTW89_IC][15] = 44,
- [1][1][RTW89_KCC][15] = 36,
+ [1][1][RTW89_KCC][15] = 38,
[1][1][RTW89_ACMA][15] = 28,
[1][1][RTW89_CN][15] = 127,
[1][1][RTW89_UK][15] = 28,
+ [1][1][RTW89_MEXICO][15] = 44,
+ [1][1][RTW89_UKRAINE][15] = 20,
+ [1][1][RTW89_CHILE][15] = 44,
+ [1][1][RTW89_QATAR][15] = 28,
[1][1][RTW89_FCC][17] = 44,
[1][1][RTW89_ETSI][17] = 28,
[1][1][RTW89_MKK][17] = 58,
[1][1][RTW89_IC][17] = 44,
- [1][1][RTW89_KCC][17] = 36,
+ [1][1][RTW89_KCC][17] = 38,
[1][1][RTW89_ACMA][17] = 28,
[1][1][RTW89_CN][17] = 127,
[1][1][RTW89_UK][17] = 28,
+ [1][1][RTW89_MEXICO][17] = 44,
+ [1][1][RTW89_UKRAINE][17] = 20,
+ [1][1][RTW89_CHILE][17] = 44,
+ [1][1][RTW89_QATAR][17] = 28,
[1][1][RTW89_FCC][19] = 44,
[1][1][RTW89_ETSI][19] = 28,
[1][1][RTW89_MKK][19] = 58,
[1][1][RTW89_IC][19] = 44,
- [1][1][RTW89_KCC][19] = 36,
+ [1][1][RTW89_KCC][19] = 38,
[1][1][RTW89_ACMA][19] = 28,
[1][1][RTW89_CN][19] = 127,
[1][1][RTW89_UK][19] = 28,
+ [1][1][RTW89_MEXICO][19] = 44,
+ [1][1][RTW89_UKRAINE][19] = 20,
+ [1][1][RTW89_CHILE][19] = 44,
+ [1][1][RTW89_QATAR][19] = 28,
[1][1][RTW89_FCC][21] = 44,
[1][1][RTW89_ETSI][21] = 28,
[1][1][RTW89_MKK][21] = 58,
[1][1][RTW89_IC][21] = 44,
- [1][1][RTW89_KCC][21] = 36,
+ [1][1][RTW89_KCC][21] = 38,
[1][1][RTW89_ACMA][21] = 28,
[1][1][RTW89_CN][21] = 127,
[1][1][RTW89_UK][21] = 28,
+ [1][1][RTW89_MEXICO][21] = 44,
+ [1][1][RTW89_UKRAINE][21] = 20,
+ [1][1][RTW89_CHILE][21] = 44,
+ [1][1][RTW89_QATAR][21] = 28,
[1][1][RTW89_FCC][23] = 44,
[1][1][RTW89_ETSI][23] = 28,
[1][1][RTW89_MKK][23] = 58,
[1][1][RTW89_IC][23] = 44,
- [1][1][RTW89_KCC][23] = 36,
+ [1][1][RTW89_KCC][23] = 38,
[1][1][RTW89_ACMA][23] = 28,
[1][1][RTW89_CN][23] = 127,
[1][1][RTW89_UK][23] = 28,
+ [1][1][RTW89_MEXICO][23] = 44,
+ [1][1][RTW89_UKRAINE][23] = 20,
+ [1][1][RTW89_CHILE][23] = 44,
+ [1][1][RTW89_QATAR][23] = 28,
[1][1][RTW89_FCC][25] = 44,
[1][1][RTW89_ETSI][25] = 28,
[1][1][RTW89_MKK][25] = 58,
[1][1][RTW89_IC][25] = 127,
- [1][1][RTW89_KCC][25] = 36,
+ [1][1][RTW89_KCC][25] = 38,
[1][1][RTW89_ACMA][25] = 127,
[1][1][RTW89_CN][25] = 127,
[1][1][RTW89_UK][25] = 28,
+ [1][1][RTW89_MEXICO][25] = 44,
+ [1][1][RTW89_UKRAINE][25] = 20,
+ [1][1][RTW89_CHILE][25] = 44,
+ [1][1][RTW89_QATAR][25] = 28,
[1][1][RTW89_FCC][27] = 44,
[1][1][RTW89_ETSI][27] = 30,
[1][1][RTW89_MKK][27] = 58,
[1][1][RTW89_IC][27] = 127,
- [1][1][RTW89_KCC][27] = 36,
+ [1][1][RTW89_KCC][27] = 38,
[1][1][RTW89_ACMA][27] = 127,
[1][1][RTW89_CN][27] = 127,
[1][1][RTW89_UK][27] = 30,
+ [1][1][RTW89_MEXICO][27] = 44,
+ [1][1][RTW89_UKRAINE][27] = 20,
+ [1][1][RTW89_CHILE][27] = 44,
+ [1][1][RTW89_QATAR][27] = 30,
[1][1][RTW89_FCC][29] = 44,
[1][1][RTW89_ETSI][29] = 30,
[1][1][RTW89_MKK][29] = 58,
[1][1][RTW89_IC][29] = 127,
- [1][1][RTW89_KCC][29] = 36,
+ [1][1][RTW89_KCC][29] = 38,
[1][1][RTW89_ACMA][29] = 127,
[1][1][RTW89_CN][29] = 127,
[1][1][RTW89_UK][29] = 30,
+ [1][1][RTW89_MEXICO][29] = 44,
+ [1][1][RTW89_UKRAINE][29] = 20,
+ [1][1][RTW89_CHILE][29] = 44,
+ [1][1][RTW89_QATAR][29] = 30,
[1][1][RTW89_FCC][31] = 44,
[1][1][RTW89_ETSI][31] = 30,
[1][1][RTW89_MKK][31] = 58,
[1][1][RTW89_IC][31] = 38,
- [1][1][RTW89_KCC][31] = 36,
+ [1][1][RTW89_KCC][31] = 40,
[1][1][RTW89_ACMA][31] = 30,
[1][1][RTW89_CN][31] = 127,
[1][1][RTW89_UK][31] = 30,
+ [1][1][RTW89_MEXICO][31] = 44,
+ [1][1][RTW89_UKRAINE][31] = 20,
+ [1][1][RTW89_CHILE][31] = 44,
+ [1][1][RTW89_QATAR][31] = 30,
[1][1][RTW89_FCC][33] = 38,
[1][1][RTW89_ETSI][33] = 30,
[1][1][RTW89_MKK][33] = 58,
[1][1][RTW89_IC][33] = 38,
- [1][1][RTW89_KCC][33] = 36,
+ [1][1][RTW89_KCC][33] = 40,
[1][1][RTW89_ACMA][33] = 30,
[1][1][RTW89_CN][33] = 127,
[1][1][RTW89_UK][33] = 30,
+ [1][1][RTW89_MEXICO][33] = 38,
+ [1][1][RTW89_UKRAINE][33] = 20,
+ [1][1][RTW89_CHILE][33] = 38,
+ [1][1][RTW89_QATAR][33] = 30,
[1][1][RTW89_FCC][35] = 38,
[1][1][RTW89_ETSI][35] = 30,
[1][1][RTW89_MKK][35] = 58,
[1][1][RTW89_IC][35] = 38,
- [1][1][RTW89_KCC][35] = 36,
+ [1][1][RTW89_KCC][35] = 40,
[1][1][RTW89_ACMA][35] = 30,
[1][1][RTW89_CN][35] = 127,
[1][1][RTW89_UK][35] = 30,
+ [1][1][RTW89_MEXICO][35] = 38,
+ [1][1][RTW89_UKRAINE][35] = 20,
+ [1][1][RTW89_CHILE][35] = 38,
+ [1][1][RTW89_QATAR][35] = 30,
[1][1][RTW89_FCC][37] = 46,
[1][1][RTW89_ETSI][37] = 127,
[1][1][RTW89_MKK][37] = 58,
[1][1][RTW89_IC][37] = 46,
- [1][1][RTW89_KCC][37] = 36,
+ [1][1][RTW89_KCC][37] = 40,
[1][1][RTW89_ACMA][37] = 46,
[1][1][RTW89_CN][37] = 127,
[1][1][RTW89_UK][37] = 32,
+ [1][1][RTW89_MEXICO][37] = 46,
+ [1][1][RTW89_UKRAINE][37] = 127,
+ [1][1][RTW89_CHILE][37] = 46,
+ [1][1][RTW89_QATAR][37] = 127,
[1][1][RTW89_FCC][38] = 74,
[1][1][RTW89_ETSI][38] = 16,
[1][1][RTW89_MKK][38] = 127,
[1][1][RTW89_IC][38] = 74,
- [1][1][RTW89_KCC][38] = 36,
+ [1][1][RTW89_KCC][38] = 38,
[1][1][RTW89_ACMA][38] = 74,
[1][1][RTW89_CN][38] = 54,
[1][1][RTW89_UK][38] = 30,
+ [1][1][RTW89_MEXICO][38] = 74,
+ [1][1][RTW89_UKRAINE][38] = 14,
+ [1][1][RTW89_CHILE][38] = 72,
+ [1][1][RTW89_QATAR][38] = 14,
[1][1][RTW89_FCC][40] = 74,
[1][1][RTW89_ETSI][40] = 16,
[1][1][RTW89_MKK][40] = 127,
[1][1][RTW89_IC][40] = 74,
- [1][1][RTW89_KCC][40] = 36,
+ [1][1][RTW89_KCC][40] = 38,
[1][1][RTW89_ACMA][40] = 74,
[1][1][RTW89_CN][40] = 54,
[1][1][RTW89_UK][40] = 30,
+ [1][1][RTW89_MEXICO][40] = 74,
+ [1][1][RTW89_UKRAINE][40] = 14,
+ [1][1][RTW89_CHILE][40] = 72,
+ [1][1][RTW89_QATAR][40] = 14,
[1][1][RTW89_FCC][42] = 74,
[1][1][RTW89_ETSI][42] = 16,
[1][1][RTW89_MKK][42] = 127,
[1][1][RTW89_IC][42] = 74,
- [1][1][RTW89_KCC][42] = 36,
+ [1][1][RTW89_KCC][42] = 38,
[1][1][RTW89_ACMA][42] = 74,
[1][1][RTW89_CN][42] = 54,
[1][1][RTW89_UK][42] = 30,
+ [1][1][RTW89_MEXICO][42] = 74,
+ [1][1][RTW89_UKRAINE][42] = 14,
+ [1][1][RTW89_CHILE][42] = 72,
+ [1][1][RTW89_QATAR][42] = 14,
[1][1][RTW89_FCC][44] = 74,
[1][1][RTW89_ETSI][44] = 16,
[1][1][RTW89_MKK][44] = 127,
[1][1][RTW89_IC][44] = 74,
- [1][1][RTW89_KCC][44] = 36,
+ [1][1][RTW89_KCC][44] = 38,
[1][1][RTW89_ACMA][44] = 74,
[1][1][RTW89_CN][44] = 54,
[1][1][RTW89_UK][44] = 30,
+ [1][1][RTW89_MEXICO][44] = 74,
+ [1][1][RTW89_UKRAINE][44] = 14,
+ [1][1][RTW89_CHILE][44] = 72,
+ [1][1][RTW89_QATAR][44] = 14,
[1][1][RTW89_FCC][46] = 74,
[1][1][RTW89_ETSI][46] = 16,
[1][1][RTW89_MKK][46] = 127,
[1][1][RTW89_IC][46] = 74,
- [1][1][RTW89_KCC][46] = 36,
+ [1][1][RTW89_KCC][46] = 38,
[1][1][RTW89_ACMA][46] = 74,
[1][1][RTW89_CN][46] = 54,
[1][1][RTW89_UK][46] = 30,
+ [1][1][RTW89_MEXICO][46] = 74,
+ [1][1][RTW89_UKRAINE][46] = 14,
+ [1][1][RTW89_CHILE][46] = 72,
+ [1][1][RTW89_QATAR][46] = 14,
[1][1][RTW89_FCC][48] = 34,
[1][1][RTW89_ETSI][48] = 127,
[1][1][RTW89_MKK][48] = 127,
@@ -35792,6 +48389,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[1][1][RTW89_ACMA][48] = 127,
[1][1][RTW89_CN][48] = 127,
[1][1][RTW89_UK][48] = 127,
+ [1][1][RTW89_MEXICO][48] = 127,
+ [1][1][RTW89_UKRAINE][48] = 127,
+ [1][1][RTW89_CHILE][48] = 127,
+ [1][1][RTW89_QATAR][48] = 127,
[1][1][RTW89_FCC][50] = 34,
[1][1][RTW89_ETSI][50] = 127,
[1][1][RTW89_MKK][50] = 127,
@@ -35800,6 +48401,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[1][1][RTW89_ACMA][50] = 127,
[1][1][RTW89_CN][50] = 127,
[1][1][RTW89_UK][50] = 127,
+ [1][1][RTW89_MEXICO][50] = 127,
+ [1][1][RTW89_UKRAINE][50] = 127,
+ [1][1][RTW89_CHILE][50] = 127,
+ [1][1][RTW89_QATAR][50] = 127,
[1][1][RTW89_FCC][52] = 30,
[1][1][RTW89_ETSI][52] = 127,
[1][1][RTW89_MKK][52] = 127,
@@ -35808,206 +48413,310 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[1][1][RTW89_ACMA][52] = 127,
[1][1][RTW89_CN][52] = 127,
[1][1][RTW89_UK][52] = 127,
+ [1][1][RTW89_MEXICO][52] = 127,
+ [1][1][RTW89_UKRAINE][52] = 127,
+ [1][1][RTW89_CHILE][52] = 127,
+ [1][1][RTW89_QATAR][52] = 127,
[2][0][RTW89_FCC][0] = 68,
[2][0][RTW89_ETSI][0] = 52,
[2][0][RTW89_MKK][0] = 60,
[2][0][RTW89_IC][0] = 52,
- [2][0][RTW89_KCC][0] = 64,
+ [2][0][RTW89_KCC][0] = 60,
[2][0][RTW89_ACMA][0] = 52,
[2][0][RTW89_CN][0] = 40,
[2][0][RTW89_UK][0] = 52,
+ [2][0][RTW89_MEXICO][0] = 62,
+ [2][0][RTW89_UKRAINE][0] = 46,
+ [2][0][RTW89_CHILE][0] = 68,
+ [2][0][RTW89_QATAR][0] = 52,
[2][0][RTW89_FCC][2] = 64,
[2][0][RTW89_ETSI][2] = 52,
[2][0][RTW89_MKK][2] = 60,
[2][0][RTW89_IC][2] = 50,
- [2][0][RTW89_KCC][2] = 64,
+ [2][0][RTW89_KCC][2] = 60,
[2][0][RTW89_ACMA][2] = 52,
[2][0][RTW89_CN][2] = 40,
[2][0][RTW89_UK][2] = 52,
+ [2][0][RTW89_MEXICO][2] = 62,
+ [2][0][RTW89_UKRAINE][2] = 46,
+ [2][0][RTW89_CHILE][2] = 64,
+ [2][0][RTW89_QATAR][2] = 52,
[2][0][RTW89_FCC][4] = 68,
[2][0][RTW89_ETSI][4] = 52,
[2][0][RTW89_MKK][4] = 50,
[2][0][RTW89_IC][4] = 50,
- [2][0][RTW89_KCC][4] = 64,
+ [2][0][RTW89_KCC][4] = 60,
[2][0][RTW89_ACMA][4] = 52,
[2][0][RTW89_CN][4] = 40,
[2][0][RTW89_UK][4] = 52,
+ [2][0][RTW89_MEXICO][4] = 62,
+ [2][0][RTW89_UKRAINE][4] = 46,
+ [2][0][RTW89_CHILE][4] = 68,
+ [2][0][RTW89_QATAR][4] = 52,
[2][0][RTW89_FCC][6] = 68,
[2][0][RTW89_ETSI][6] = 52,
[2][0][RTW89_MKK][6] = 50,
[2][0][RTW89_IC][6] = 50,
- [2][0][RTW89_KCC][6] = 36,
+ [2][0][RTW89_KCC][6] = 38,
[2][0][RTW89_ACMA][6] = 52,
[2][0][RTW89_CN][6] = 40,
[2][0][RTW89_UK][6] = 52,
+ [2][0][RTW89_MEXICO][6] = 62,
+ [2][0][RTW89_UKRAINE][6] = 46,
+ [2][0][RTW89_CHILE][6] = 68,
+ [2][0][RTW89_QATAR][6] = 52,
[2][0][RTW89_FCC][8] = 68,
[2][0][RTW89_ETSI][8] = 52,
[2][0][RTW89_MKK][8] = 44,
[2][0][RTW89_IC][8] = 64,
- [2][0][RTW89_KCC][8] = 62,
+ [2][0][RTW89_KCC][8] = 56,
[2][0][RTW89_ACMA][8] = 52,
[2][0][RTW89_CN][8] = 40,
[2][0][RTW89_UK][8] = 52,
+ [2][0][RTW89_MEXICO][8] = 68,
+ [2][0][RTW89_UKRAINE][8] = 46,
+ [2][0][RTW89_CHILE][8] = 68,
+ [2][0][RTW89_QATAR][8] = 52,
[2][0][RTW89_FCC][10] = 68,
[2][0][RTW89_ETSI][10] = 52,
[2][0][RTW89_MKK][10] = 44,
[2][0][RTW89_IC][10] = 64,
- [2][0][RTW89_KCC][10] = 62,
+ [2][0][RTW89_KCC][10] = 56,
[2][0][RTW89_ACMA][10] = 52,
[2][0][RTW89_CN][10] = 40,
[2][0][RTW89_UK][10] = 52,
+ [2][0][RTW89_MEXICO][10] = 68,
+ [2][0][RTW89_UKRAINE][10] = 46,
+ [2][0][RTW89_CHILE][10] = 68,
+ [2][0][RTW89_QATAR][10] = 52,
[2][0][RTW89_FCC][12] = 68,
[2][0][RTW89_ETSI][12] = 52,
[2][0][RTW89_MKK][12] = 58,
[2][0][RTW89_IC][12] = 64,
- [2][0][RTW89_KCC][12] = 62,
+ [2][0][RTW89_KCC][12] = 58,
[2][0][RTW89_ACMA][12] = 52,
[2][0][RTW89_CN][12] = 40,
[2][0][RTW89_UK][12] = 52,
+ [2][0][RTW89_MEXICO][12] = 68,
+ [2][0][RTW89_UKRAINE][12] = 46,
+ [2][0][RTW89_CHILE][12] = 68,
+ [2][0][RTW89_QATAR][12] = 52,
[2][0][RTW89_FCC][14] = 68,
[2][0][RTW89_ETSI][14] = 52,
[2][0][RTW89_MKK][14] = 58,
[2][0][RTW89_IC][14] = 64,
- [2][0][RTW89_KCC][14] = 62,
+ [2][0][RTW89_KCC][14] = 58,
[2][0][RTW89_ACMA][14] = 52,
[2][0][RTW89_CN][14] = 40,
[2][0][RTW89_UK][14] = 52,
+ [2][0][RTW89_MEXICO][14] = 68,
+ [2][0][RTW89_UKRAINE][14] = 46,
+ [2][0][RTW89_CHILE][14] = 68,
+ [2][0][RTW89_QATAR][14] = 52,
[2][0][RTW89_FCC][15] = 68,
[2][0][RTW89_ETSI][15] = 52,
[2][0][RTW89_MKK][15] = 68,
[2][0][RTW89_IC][15] = 68,
- [2][0][RTW89_KCC][15] = 62,
+ [2][0][RTW89_KCC][15] = 58,
[2][0][RTW89_ACMA][15] = 52,
[2][0][RTW89_CN][15] = 127,
[2][0][RTW89_UK][15] = 52,
+ [2][0][RTW89_MEXICO][15] = 68,
+ [2][0][RTW89_UKRAINE][15] = 46,
+ [2][0][RTW89_CHILE][15] = 68,
+ [2][0][RTW89_QATAR][15] = 52,
[2][0][RTW89_FCC][17] = 68,
[2][0][RTW89_ETSI][17] = 52,
[2][0][RTW89_MKK][17] = 74,
[2][0][RTW89_IC][17] = 68,
- [2][0][RTW89_KCC][17] = 62,
+ [2][0][RTW89_KCC][17] = 58,
[2][0][RTW89_ACMA][17] = 52,
[2][0][RTW89_CN][17] = 127,
[2][0][RTW89_UK][17] = 52,
+ [2][0][RTW89_MEXICO][17] = 68,
+ [2][0][RTW89_UKRAINE][17] = 46,
+ [2][0][RTW89_CHILE][17] = 68,
+ [2][0][RTW89_QATAR][17] = 52,
[2][0][RTW89_FCC][19] = 70,
[2][0][RTW89_ETSI][19] = 52,
[2][0][RTW89_MKK][19] = 74,
[2][0][RTW89_IC][19] = 70,
- [2][0][RTW89_KCC][19] = 62,
+ [2][0][RTW89_KCC][19] = 58,
[2][0][RTW89_ACMA][19] = 52,
[2][0][RTW89_CN][19] = 127,
[2][0][RTW89_UK][19] = 52,
+ [2][0][RTW89_MEXICO][19] = 70,
+ [2][0][RTW89_UKRAINE][19] = 46,
+ [2][0][RTW89_CHILE][19] = 70,
+ [2][0][RTW89_QATAR][19] = 52,
[2][0][RTW89_FCC][21] = 70,
[2][0][RTW89_ETSI][21] = 52,
[2][0][RTW89_MKK][21] = 74,
[2][0][RTW89_IC][21] = 70,
- [2][0][RTW89_KCC][21] = 62,
+ [2][0][RTW89_KCC][21] = 58,
[2][0][RTW89_ACMA][21] = 52,
[2][0][RTW89_CN][21] = 127,
[2][0][RTW89_UK][21] = 52,
+ [2][0][RTW89_MEXICO][21] = 70,
+ [2][0][RTW89_UKRAINE][21] = 46,
+ [2][0][RTW89_CHILE][21] = 70,
+ [2][0][RTW89_QATAR][21] = 52,
[2][0][RTW89_FCC][23] = 70,
[2][0][RTW89_ETSI][23] = 52,
[2][0][RTW89_MKK][23] = 74,
[2][0][RTW89_IC][23] = 70,
- [2][0][RTW89_KCC][23] = 62,
+ [2][0][RTW89_KCC][23] = 58,
[2][0][RTW89_ACMA][23] = 52,
[2][0][RTW89_CN][23] = 127,
[2][0][RTW89_UK][23] = 52,
+ [2][0][RTW89_MEXICO][23] = 70,
+ [2][0][RTW89_UKRAINE][23] = 46,
+ [2][0][RTW89_CHILE][23] = 70,
+ [2][0][RTW89_QATAR][23] = 52,
[2][0][RTW89_FCC][25] = 70,
[2][0][RTW89_ETSI][25] = 52,
[2][0][RTW89_MKK][25] = 74,
[2][0][RTW89_IC][25] = 127,
- [2][0][RTW89_KCC][25] = 62,
+ [2][0][RTW89_KCC][25] = 58,
[2][0][RTW89_ACMA][25] = 127,
[2][0][RTW89_CN][25] = 127,
[2][0][RTW89_UK][25] = 52,
+ [2][0][RTW89_MEXICO][25] = 70,
+ [2][0][RTW89_UKRAINE][25] = 46,
+ [2][0][RTW89_CHILE][25] = 70,
+ [2][0][RTW89_QATAR][25] = 52,
[2][0][RTW89_FCC][27] = 70,
[2][0][RTW89_ETSI][27] = 52,
[2][0][RTW89_MKK][27] = 74,
[2][0][RTW89_IC][27] = 127,
- [2][0][RTW89_KCC][27] = 62,
+ [2][0][RTW89_KCC][27] = 58,
[2][0][RTW89_ACMA][27] = 127,
[2][0][RTW89_CN][27] = 127,
[2][0][RTW89_UK][27] = 52,
+ [2][0][RTW89_MEXICO][27] = 70,
+ [2][0][RTW89_UKRAINE][27] = 46,
+ [2][0][RTW89_CHILE][27] = 70,
+ [2][0][RTW89_QATAR][27] = 52,
[2][0][RTW89_FCC][29] = 70,
[2][0][RTW89_ETSI][29] = 52,
[2][0][RTW89_MKK][29] = 74,
[2][0][RTW89_IC][29] = 127,
- [2][0][RTW89_KCC][29] = 62,
+ [2][0][RTW89_KCC][29] = 58,
[2][0][RTW89_ACMA][29] = 127,
[2][0][RTW89_CN][29] = 127,
[2][0][RTW89_UK][29] = 52,
+ [2][0][RTW89_MEXICO][29] = 70,
+ [2][0][RTW89_UKRAINE][29] = 46,
+ [2][0][RTW89_CHILE][29] = 70,
+ [2][0][RTW89_QATAR][29] = 52,
[2][0][RTW89_FCC][31] = 70,
[2][0][RTW89_ETSI][31] = 52,
[2][0][RTW89_MKK][31] = 74,
[2][0][RTW89_IC][31] = 62,
- [2][0][RTW89_KCC][31] = 62,
+ [2][0][RTW89_KCC][31] = 56,
[2][0][RTW89_ACMA][31] = 52,
[2][0][RTW89_CN][31] = 127,
[2][0][RTW89_UK][31] = 52,
+ [2][0][RTW89_MEXICO][31] = 70,
+ [2][0][RTW89_UKRAINE][31] = 46,
+ [2][0][RTW89_CHILE][31] = 70,
+ [2][0][RTW89_QATAR][31] = 52,
[2][0][RTW89_FCC][33] = 62,
[2][0][RTW89_ETSI][33] = 52,
[2][0][RTW89_MKK][33] = 74,
[2][0][RTW89_IC][33] = 62,
- [2][0][RTW89_KCC][33] = 62,
+ [2][0][RTW89_KCC][33] = 56,
[2][0][RTW89_ACMA][33] = 52,
[2][0][RTW89_CN][33] = 127,
[2][0][RTW89_UK][33] = 52,
+ [2][0][RTW89_MEXICO][33] = 62,
+ [2][0][RTW89_UKRAINE][33] = 46,
+ [2][0][RTW89_CHILE][33] = 62,
+ [2][0][RTW89_QATAR][33] = 52,
[2][0][RTW89_FCC][35] = 62,
[2][0][RTW89_ETSI][35] = 52,
[2][0][RTW89_MKK][35] = 74,
[2][0][RTW89_IC][35] = 62,
- [2][0][RTW89_KCC][35] = 62,
+ [2][0][RTW89_KCC][35] = 56,
[2][0][RTW89_ACMA][35] = 52,
[2][0][RTW89_CN][35] = 127,
[2][0][RTW89_UK][35] = 52,
+ [2][0][RTW89_MEXICO][35] = 62,
+ [2][0][RTW89_UKRAINE][35] = 46,
+ [2][0][RTW89_CHILE][35] = 62,
+ [2][0][RTW89_QATAR][35] = 52,
[2][0][RTW89_FCC][37] = 70,
[2][0][RTW89_ETSI][37] = 127,
[2][0][RTW89_MKK][37] = 74,
[2][0][RTW89_IC][37] = 70,
- [2][0][RTW89_KCC][37] = 62,
+ [2][0][RTW89_KCC][37] = 56,
[2][0][RTW89_ACMA][37] = 70,
[2][0][RTW89_CN][37] = 127,
[2][0][RTW89_UK][37] = 52,
+ [2][0][RTW89_MEXICO][37] = 70,
+ [2][0][RTW89_UKRAINE][37] = 127,
+ [2][0][RTW89_CHILE][37] = 70,
+ [2][0][RTW89_QATAR][37] = 127,
[2][0][RTW89_FCC][38] = 82,
[2][0][RTW89_ETSI][38] = 28,
[2][0][RTW89_MKK][38] = 127,
[2][0][RTW89_IC][38] = 82,
- [2][0][RTW89_KCC][38] = 64,
+ [2][0][RTW89_KCC][38] = 60,
[2][0][RTW89_ACMA][38] = 82,
[2][0][RTW89_CN][38] = 68,
[2][0][RTW89_UK][38] = 54,
+ [2][0][RTW89_MEXICO][38] = 82,
+ [2][0][RTW89_UKRAINE][38] = 26,
+ [2][0][RTW89_CHILE][38] = 82,
+ [2][0][RTW89_QATAR][38] = 26,
[2][0][RTW89_FCC][40] = 82,
[2][0][RTW89_ETSI][40] = 28,
[2][0][RTW89_MKK][40] = 127,
[2][0][RTW89_IC][40] = 82,
- [2][0][RTW89_KCC][40] = 64,
+ [2][0][RTW89_KCC][40] = 60,
[2][0][RTW89_ACMA][40] = 82,
[2][0][RTW89_CN][40] = 68,
[2][0][RTW89_UK][40] = 54,
+ [2][0][RTW89_MEXICO][40] = 82,
+ [2][0][RTW89_UKRAINE][40] = 26,
+ [2][0][RTW89_CHILE][40] = 82,
+ [2][0][RTW89_QATAR][40] = 26,
[2][0][RTW89_FCC][42] = 76,
[2][0][RTW89_ETSI][42] = 28,
[2][0][RTW89_MKK][42] = 127,
[2][0][RTW89_IC][42] = 76,
- [2][0][RTW89_KCC][42] = 64,
+ [2][0][RTW89_KCC][42] = 60,
[2][0][RTW89_ACMA][42] = 76,
[2][0][RTW89_CN][42] = 68,
[2][0][RTW89_UK][42] = 54,
+ [2][0][RTW89_MEXICO][42] = 76,
+ [2][0][RTW89_UKRAINE][42] = 26,
+ [2][0][RTW89_CHILE][42] = 76,
+ [2][0][RTW89_QATAR][42] = 26,
[2][0][RTW89_FCC][44] = 80,
[2][0][RTW89_ETSI][44] = 28,
[2][0][RTW89_MKK][44] = 127,
[2][0][RTW89_IC][44] = 80,
- [2][0][RTW89_KCC][44] = 64,
+ [2][0][RTW89_KCC][44] = 60,
[2][0][RTW89_ACMA][44] = 80,
[2][0][RTW89_CN][44] = 68,
[2][0][RTW89_UK][44] = 54,
+ [2][0][RTW89_MEXICO][44] = 80,
+ [2][0][RTW89_UKRAINE][44] = 26,
+ [2][0][RTW89_CHILE][44] = 80,
+ [2][0][RTW89_QATAR][44] = 26,
[2][0][RTW89_FCC][46] = 80,
[2][0][RTW89_ETSI][46] = 28,
[2][0][RTW89_MKK][46] = 127,
[2][0][RTW89_IC][46] = 80,
- [2][0][RTW89_KCC][46] = 64,
+ [2][0][RTW89_KCC][46] = 60,
[2][0][RTW89_ACMA][46] = 80,
[2][0][RTW89_CN][46] = 68,
[2][0][RTW89_UK][46] = 54,
+ [2][0][RTW89_MEXICO][46] = 80,
+ [2][0][RTW89_UKRAINE][46] = 26,
+ [2][0][RTW89_CHILE][46] = 80,
+ [2][0][RTW89_QATAR][46] = 26,
[2][0][RTW89_FCC][48] = 64,
[2][0][RTW89_ETSI][48] = 127,
[2][0][RTW89_MKK][48] = 127,
@@ -36016,6 +48725,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[2][0][RTW89_ACMA][48] = 127,
[2][0][RTW89_CN][48] = 127,
[2][0][RTW89_UK][48] = 127,
+ [2][0][RTW89_MEXICO][48] = 127,
+ [2][0][RTW89_UKRAINE][48] = 127,
+ [2][0][RTW89_CHILE][48] = 127,
+ [2][0][RTW89_QATAR][48] = 127,
[2][0][RTW89_FCC][50] = 64,
[2][0][RTW89_ETSI][50] = 127,
[2][0][RTW89_MKK][50] = 127,
@@ -36024,6 +48737,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[2][0][RTW89_ACMA][50] = 127,
[2][0][RTW89_CN][50] = 127,
[2][0][RTW89_UK][50] = 127,
+ [2][0][RTW89_MEXICO][50] = 127,
+ [2][0][RTW89_UKRAINE][50] = 127,
+ [2][0][RTW89_CHILE][50] = 127,
+ [2][0][RTW89_QATAR][50] = 127,
[2][0][RTW89_FCC][52] = 64,
[2][0][RTW89_ETSI][52] = 127,
[2][0][RTW89_MKK][52] = 127,
@@ -36032,206 +48749,310 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[2][0][RTW89_ACMA][52] = 127,
[2][0][RTW89_CN][52] = 127,
[2][0][RTW89_UK][52] = 127,
+ [2][0][RTW89_MEXICO][52] = 127,
+ [2][0][RTW89_UKRAINE][52] = 127,
+ [2][0][RTW89_CHILE][52] = 127,
+ [2][0][RTW89_QATAR][52] = 127,
[2][1][RTW89_FCC][0] = 50,
[2][1][RTW89_ETSI][0] = 40,
[2][1][RTW89_MKK][0] = 44,
[2][1][RTW89_IC][0] = 26,
- [2][1][RTW89_KCC][0] = 44,
+ [2][1][RTW89_KCC][0] = 52,
[2][1][RTW89_ACMA][0] = 40,
[2][1][RTW89_CN][0] = 28,
[2][1][RTW89_UK][0] = 40,
+ [2][1][RTW89_MEXICO][0] = 50,
+ [2][1][RTW89_UKRAINE][0] = 34,
+ [2][1][RTW89_CHILE][0] = 50,
+ [2][1][RTW89_QATAR][0] = 40,
[2][1][RTW89_FCC][2] = 50,
[2][1][RTW89_ETSI][2] = 40,
[2][1][RTW89_MKK][2] = 44,
[2][1][RTW89_IC][2] = 26,
- [2][1][RTW89_KCC][2] = 44,
+ [2][1][RTW89_KCC][2] = 52,
[2][1][RTW89_ACMA][2] = 40,
[2][1][RTW89_CN][2] = 28,
[2][1][RTW89_UK][2] = 40,
+ [2][1][RTW89_MEXICO][2] = 50,
+ [2][1][RTW89_UKRAINE][2] = 34,
+ [2][1][RTW89_CHILE][2] = 50,
+ [2][1][RTW89_QATAR][2] = 40,
[2][1][RTW89_FCC][4] = 50,
[2][1][RTW89_ETSI][4] = 40,
[2][1][RTW89_MKK][4] = 36,
[2][1][RTW89_IC][4] = 26,
- [2][1][RTW89_KCC][4] = 44,
+ [2][1][RTW89_KCC][4] = 52,
[2][1][RTW89_ACMA][4] = 40,
[2][1][RTW89_CN][4] = 28,
[2][1][RTW89_UK][4] = 40,
+ [2][1][RTW89_MEXICO][4] = 50,
+ [2][1][RTW89_UKRAINE][4] = 34,
+ [2][1][RTW89_CHILE][4] = 50,
+ [2][1][RTW89_QATAR][4] = 40,
[2][1][RTW89_FCC][6] = 50,
[2][1][RTW89_ETSI][6] = 40,
[2][1][RTW89_MKK][6] = 36,
[2][1][RTW89_IC][6] = 26,
- [2][1][RTW89_KCC][6] = 20,
+ [2][1][RTW89_KCC][6] = 30,
[2][1][RTW89_ACMA][6] = 40,
[2][1][RTW89_CN][6] = 28,
[2][1][RTW89_UK][6] = 40,
+ [2][1][RTW89_MEXICO][6] = 50,
+ [2][1][RTW89_UKRAINE][6] = 34,
+ [2][1][RTW89_CHILE][6] = 50,
+ [2][1][RTW89_QATAR][6] = 40,
[2][1][RTW89_FCC][8] = 50,
[2][1][RTW89_ETSI][8] = 40,
[2][1][RTW89_MKK][8] = 32,
[2][1][RTW89_IC][8] = 50,
- [2][1][RTW89_KCC][8] = 46,
+ [2][1][RTW89_KCC][8] = 50,
[2][1][RTW89_ACMA][8] = 40,
[2][1][RTW89_CN][8] = 28,
[2][1][RTW89_UK][8] = 40,
+ [2][1][RTW89_MEXICO][8] = 50,
+ [2][1][RTW89_UKRAINE][8] = 34,
+ [2][1][RTW89_CHILE][8] = 50,
+ [2][1][RTW89_QATAR][8] = 40,
[2][1][RTW89_FCC][10] = 50,
[2][1][RTW89_ETSI][10] = 40,
[2][1][RTW89_MKK][10] = 32,
[2][1][RTW89_IC][10] = 50,
- [2][1][RTW89_KCC][10] = 46,
+ [2][1][RTW89_KCC][10] = 50,
[2][1][RTW89_ACMA][10] = 40,
[2][1][RTW89_CN][10] = 28,
[2][1][RTW89_UK][10] = 40,
+ [2][1][RTW89_MEXICO][10] = 50,
+ [2][1][RTW89_UKRAINE][10] = 34,
+ [2][1][RTW89_CHILE][10] = 50,
+ [2][1][RTW89_QATAR][10] = 40,
[2][1][RTW89_FCC][12] = 48,
[2][1][RTW89_ETSI][12] = 40,
[2][1][RTW89_MKK][12] = 44,
[2][1][RTW89_IC][12] = 48,
- [2][1][RTW89_KCC][12] = 46,
+ [2][1][RTW89_KCC][12] = 48,
[2][1][RTW89_ACMA][12] = 40,
[2][1][RTW89_CN][12] = 28,
[2][1][RTW89_UK][12] = 40,
+ [2][1][RTW89_MEXICO][12] = 48,
+ [2][1][RTW89_UKRAINE][12] = 34,
+ [2][1][RTW89_CHILE][12] = 48,
+ [2][1][RTW89_QATAR][12] = 40,
[2][1][RTW89_FCC][14] = 48,
[2][1][RTW89_ETSI][14] = 40,
[2][1][RTW89_MKK][14] = 44,
[2][1][RTW89_IC][14] = 48,
- [2][1][RTW89_KCC][14] = 46,
+ [2][1][RTW89_KCC][14] = 48,
[2][1][RTW89_ACMA][14] = 40,
[2][1][RTW89_CN][14] = 28,
[2][1][RTW89_UK][14] = 40,
+ [2][1][RTW89_MEXICO][14] = 48,
+ [2][1][RTW89_UKRAINE][14] = 34,
+ [2][1][RTW89_CHILE][14] = 48,
+ [2][1][RTW89_QATAR][14] = 40,
[2][1][RTW89_FCC][15] = 50,
[2][1][RTW89_ETSI][15] = 40,
[2][1][RTW89_MKK][15] = 66,
[2][1][RTW89_IC][15] = 50,
- [2][1][RTW89_KCC][15] = 46,
+ [2][1][RTW89_KCC][15] = 48,
[2][1][RTW89_ACMA][15] = 40,
[2][1][RTW89_CN][15] = 127,
[2][1][RTW89_UK][15] = 40,
+ [2][1][RTW89_MEXICO][15] = 50,
+ [2][1][RTW89_UKRAINE][15] = 34,
+ [2][1][RTW89_CHILE][15] = 50,
+ [2][1][RTW89_QATAR][15] = 40,
[2][1][RTW89_FCC][17] = 50,
[2][1][RTW89_ETSI][17] = 40,
[2][1][RTW89_MKK][17] = 66,
[2][1][RTW89_IC][17] = 50,
- [2][1][RTW89_KCC][17] = 46,
+ [2][1][RTW89_KCC][17] = 48,
[2][1][RTW89_ACMA][17] = 40,
[2][1][RTW89_CN][17] = 127,
[2][1][RTW89_UK][17] = 40,
+ [2][1][RTW89_MEXICO][17] = 50,
+ [2][1][RTW89_UKRAINE][17] = 34,
+ [2][1][RTW89_CHILE][17] = 50,
+ [2][1][RTW89_QATAR][17] = 40,
[2][1][RTW89_FCC][19] = 50,
[2][1][RTW89_ETSI][19] = 40,
[2][1][RTW89_MKK][19] = 66,
[2][1][RTW89_IC][19] = 50,
- [2][1][RTW89_KCC][19] = 46,
+ [2][1][RTW89_KCC][19] = 48,
[2][1][RTW89_ACMA][19] = 40,
[2][1][RTW89_CN][19] = 127,
[2][1][RTW89_UK][19] = 40,
+ [2][1][RTW89_MEXICO][19] = 50,
+ [2][1][RTW89_UKRAINE][19] = 34,
+ [2][1][RTW89_CHILE][19] = 50,
+ [2][1][RTW89_QATAR][19] = 40,
[2][1][RTW89_FCC][21] = 50,
[2][1][RTW89_ETSI][21] = 40,
[2][1][RTW89_MKK][21] = 66,
[2][1][RTW89_IC][21] = 50,
- [2][1][RTW89_KCC][21] = 46,
+ [2][1][RTW89_KCC][21] = 48,
[2][1][RTW89_ACMA][21] = 40,
[2][1][RTW89_CN][21] = 127,
[2][1][RTW89_UK][21] = 40,
+ [2][1][RTW89_MEXICO][21] = 50,
+ [2][1][RTW89_UKRAINE][21] = 34,
+ [2][1][RTW89_CHILE][21] = 50,
+ [2][1][RTW89_QATAR][21] = 40,
[2][1][RTW89_FCC][23] = 50,
[2][1][RTW89_ETSI][23] = 40,
[2][1][RTW89_MKK][23] = 66,
[2][1][RTW89_IC][23] = 50,
- [2][1][RTW89_KCC][23] = 46,
+ [2][1][RTW89_KCC][23] = 48,
[2][1][RTW89_ACMA][23] = 40,
[2][1][RTW89_CN][23] = 127,
[2][1][RTW89_UK][23] = 40,
+ [2][1][RTW89_MEXICO][23] = 50,
+ [2][1][RTW89_UKRAINE][23] = 34,
+ [2][1][RTW89_CHILE][23] = 50,
+ [2][1][RTW89_QATAR][23] = 40,
[2][1][RTW89_FCC][25] = 50,
[2][1][RTW89_ETSI][25] = 40,
[2][1][RTW89_MKK][25] = 66,
[2][1][RTW89_IC][25] = 127,
- [2][1][RTW89_KCC][25] = 46,
+ [2][1][RTW89_KCC][25] = 48,
[2][1][RTW89_ACMA][25] = 127,
[2][1][RTW89_CN][25] = 127,
[2][1][RTW89_UK][25] = 40,
+ [2][1][RTW89_MEXICO][25] = 50,
+ [2][1][RTW89_UKRAINE][25] = 34,
+ [2][1][RTW89_CHILE][25] = 50,
+ [2][1][RTW89_QATAR][25] = 40,
[2][1][RTW89_FCC][27] = 50,
[2][1][RTW89_ETSI][27] = 40,
[2][1][RTW89_MKK][27] = 66,
[2][1][RTW89_IC][27] = 127,
- [2][1][RTW89_KCC][27] = 46,
+ [2][1][RTW89_KCC][27] = 48,
[2][1][RTW89_ACMA][27] = 127,
[2][1][RTW89_CN][27] = 127,
[2][1][RTW89_UK][27] = 40,
+ [2][1][RTW89_MEXICO][27] = 50,
+ [2][1][RTW89_UKRAINE][27] = 34,
+ [2][1][RTW89_CHILE][27] = 50,
+ [2][1][RTW89_QATAR][27] = 40,
[2][1][RTW89_FCC][29] = 50,
[2][1][RTW89_ETSI][29] = 40,
[2][1][RTW89_MKK][29] = 66,
[2][1][RTW89_IC][29] = 127,
- [2][1][RTW89_KCC][29] = 46,
+ [2][1][RTW89_KCC][29] = 48,
[2][1][RTW89_ACMA][29] = 127,
[2][1][RTW89_CN][29] = 127,
[2][1][RTW89_UK][29] = 40,
+ [2][1][RTW89_MEXICO][29] = 50,
+ [2][1][RTW89_UKRAINE][29] = 34,
+ [2][1][RTW89_CHILE][29] = 50,
+ [2][1][RTW89_QATAR][29] = 40,
[2][1][RTW89_FCC][31] = 50,
[2][1][RTW89_ETSI][31] = 40,
[2][1][RTW89_MKK][31] = 66,
[2][1][RTW89_IC][31] = 48,
- [2][1][RTW89_KCC][31] = 46,
+ [2][1][RTW89_KCC][31] = 48,
[2][1][RTW89_ACMA][31] = 40,
[2][1][RTW89_CN][31] = 127,
[2][1][RTW89_UK][31] = 40,
+ [2][1][RTW89_MEXICO][31] = 50,
+ [2][1][RTW89_UKRAINE][31] = 34,
+ [2][1][RTW89_CHILE][31] = 50,
+ [2][1][RTW89_QATAR][31] = 40,
[2][1][RTW89_FCC][33] = 48,
[2][1][RTW89_ETSI][33] = 40,
[2][1][RTW89_MKK][33] = 66,
[2][1][RTW89_IC][33] = 48,
- [2][1][RTW89_KCC][33] = 46,
+ [2][1][RTW89_KCC][33] = 48,
[2][1][RTW89_ACMA][33] = 40,
[2][1][RTW89_CN][33] = 127,
[2][1][RTW89_UK][33] = 40,
+ [2][1][RTW89_MEXICO][33] = 48,
+ [2][1][RTW89_UKRAINE][33] = 34,
+ [2][1][RTW89_CHILE][33] = 48,
+ [2][1][RTW89_QATAR][33] = 40,
[2][1][RTW89_FCC][35] = 48,
[2][1][RTW89_ETSI][35] = 40,
[2][1][RTW89_MKK][35] = 66,
[2][1][RTW89_IC][35] = 48,
- [2][1][RTW89_KCC][35] = 46,
+ [2][1][RTW89_KCC][35] = 48,
[2][1][RTW89_ACMA][35] = 40,
[2][1][RTW89_CN][35] = 127,
[2][1][RTW89_UK][35] = 40,
+ [2][1][RTW89_MEXICO][35] = 48,
+ [2][1][RTW89_UKRAINE][35] = 34,
+ [2][1][RTW89_CHILE][35] = 48,
+ [2][1][RTW89_QATAR][35] = 40,
[2][1][RTW89_FCC][37] = 52,
[2][1][RTW89_ETSI][37] = 127,
[2][1][RTW89_MKK][37] = 66,
[2][1][RTW89_IC][37] = 52,
- [2][1][RTW89_KCC][37] = 46,
+ [2][1][RTW89_KCC][37] = 48,
[2][1][RTW89_ACMA][37] = 52,
[2][1][RTW89_CN][37] = 127,
[2][1][RTW89_UK][37] = 42,
+ [2][1][RTW89_MEXICO][37] = 52,
+ [2][1][RTW89_UKRAINE][37] = 127,
+ [2][1][RTW89_CHILE][37] = 52,
+ [2][1][RTW89_QATAR][37] = 127,
[2][1][RTW89_FCC][38] = 78,
[2][1][RTW89_ETSI][38] = 16,
[2][1][RTW89_MKK][38] = 127,
[2][1][RTW89_IC][38] = 78,
- [2][1][RTW89_KCC][38] = 46,
+ [2][1][RTW89_KCC][38] = 50,
[2][1][RTW89_ACMA][38] = 78,
[2][1][RTW89_CN][38] = 56,
[2][1][RTW89_UK][38] = 42,
+ [2][1][RTW89_MEXICO][38] = 78,
+ [2][1][RTW89_UKRAINE][38] = 14,
+ [2][1][RTW89_CHILE][38] = 72,
+ [2][1][RTW89_QATAR][38] = 14,
[2][1][RTW89_FCC][40] = 78,
[2][1][RTW89_ETSI][40] = 16,
[2][1][RTW89_MKK][40] = 127,
[2][1][RTW89_IC][40] = 78,
- [2][1][RTW89_KCC][40] = 46,
+ [2][1][RTW89_KCC][40] = 50,
[2][1][RTW89_ACMA][40] = 78,
[2][1][RTW89_CN][40] = 56,
[2][1][RTW89_UK][40] = 42,
+ [2][1][RTW89_MEXICO][40] = 78,
+ [2][1][RTW89_UKRAINE][40] = 14,
+ [2][1][RTW89_CHILE][40] = 72,
+ [2][1][RTW89_QATAR][40] = 14,
[2][1][RTW89_FCC][42] = 78,
[2][1][RTW89_ETSI][42] = 16,
[2][1][RTW89_MKK][42] = 127,
[2][1][RTW89_IC][42] = 78,
- [2][1][RTW89_KCC][42] = 46,
+ [2][1][RTW89_KCC][42] = 50,
[2][1][RTW89_ACMA][42] = 78,
[2][1][RTW89_CN][42] = 56,
[2][1][RTW89_UK][42] = 42,
+ [2][1][RTW89_MEXICO][42] = 78,
+ [2][1][RTW89_UKRAINE][42] = 14,
+ [2][1][RTW89_CHILE][42] = 72,
+ [2][1][RTW89_QATAR][42] = 14,
[2][1][RTW89_FCC][44] = 74,
[2][1][RTW89_ETSI][44] = 16,
[2][1][RTW89_MKK][44] = 127,
[2][1][RTW89_IC][44] = 74,
- [2][1][RTW89_KCC][44] = 46,
+ [2][1][RTW89_KCC][44] = 50,
[2][1][RTW89_ACMA][44] = 74,
[2][1][RTW89_CN][44] = 56,
[2][1][RTW89_UK][44] = 42,
+ [2][1][RTW89_MEXICO][44] = 74,
+ [2][1][RTW89_UKRAINE][44] = 14,
+ [2][1][RTW89_CHILE][44] = 72,
+ [2][1][RTW89_QATAR][44] = 14,
[2][1][RTW89_FCC][46] = 74,
[2][1][RTW89_ETSI][46] = 16,
[2][1][RTW89_MKK][46] = 127,
[2][1][RTW89_IC][46] = 74,
- [2][1][RTW89_KCC][46] = 46,
+ [2][1][RTW89_KCC][46] = 50,
[2][1][RTW89_ACMA][46] = 74,
[2][1][RTW89_CN][46] = 56,
[2][1][RTW89_UK][46] = 42,
+ [2][1][RTW89_MEXICO][46] = 74,
+ [2][1][RTW89_UKRAINE][46] = 14,
+ [2][1][RTW89_CHILE][46] = 72,
+ [2][1][RTW89_QATAR][46] = 14,
[2][1][RTW89_FCC][48] = 40,
[2][1][RTW89_ETSI][48] = 127,
[2][1][RTW89_MKK][48] = 127,
@@ -36240,6 +49061,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[2][1][RTW89_ACMA][48] = 127,
[2][1][RTW89_CN][48] = 127,
[2][1][RTW89_UK][48] = 127,
+ [2][1][RTW89_MEXICO][48] = 127,
+ [2][1][RTW89_UKRAINE][48] = 127,
+ [2][1][RTW89_CHILE][48] = 127,
+ [2][1][RTW89_QATAR][48] = 127,
[2][1][RTW89_FCC][50] = 40,
[2][1][RTW89_ETSI][50] = 127,
[2][1][RTW89_MKK][50] = 127,
@@ -36248,6 +49073,10 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[2][1][RTW89_ACMA][50] = 127,
[2][1][RTW89_CN][50] = 127,
[2][1][RTW89_UK][50] = 127,
+ [2][1][RTW89_MEXICO][50] = 127,
+ [2][1][RTW89_UKRAINE][50] = 127,
+ [2][1][RTW89_CHILE][50] = 127,
+ [2][1][RTW89_QATAR][50] = 127,
[2][1][RTW89_FCC][52] = 40,
[2][1][RTW89_ETSI][52] = 127,
[2][1][RTW89_MKK][52] = 127,
@@ -36256,1163 +49085,7312 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[2][1][RTW89_ACMA][52] = 127,
[2][1][RTW89_CN][52] = 127,
[2][1][RTW89_UK][52] = 127,
+ [2][1][RTW89_MEXICO][52] = 127,
+ [2][1][RTW89_UKRAINE][52] = 127,
+ [2][1][RTW89_CHILE][52] = 127,
+ [2][1][RTW89_QATAR][52] = 127,
};
static
const s8 rtw89_8852c_txpwr_lmt_ru_6g[RTW89_RU_NUM][RTW89_NTX_NUM]
- [RTW89_REGD_NUM][RTW89_6G_CH_NUM] = {
- [0][0][RTW89_WW][0] = -16,
- [0][0][RTW89_WW][2] = -18,
- [0][0][RTW89_WW][4] = -18,
- [0][0][RTW89_WW][6] = -18,
- [0][0][RTW89_WW][8] = -18,
- [0][0][RTW89_WW][10] = -18,
- [0][0][RTW89_WW][12] = -18,
- [0][0][RTW89_WW][14] = -18,
- [0][0][RTW89_WW][15] = -18,
- [0][0][RTW89_WW][17] = -18,
- [0][0][RTW89_WW][19] = -18,
- [0][0][RTW89_WW][21] = -18,
- [0][0][RTW89_WW][23] = -18,
- [0][0][RTW89_WW][25] = -18,
- [0][0][RTW89_WW][27] = -18,
- [0][0][RTW89_WW][29] = -18,
- [0][0][RTW89_WW][30] = -18,
- [0][0][RTW89_WW][32] = -18,
- [0][0][RTW89_WW][34] = -18,
- [0][0][RTW89_WW][36] = -18,
- [0][0][RTW89_WW][38] = -18,
- [0][0][RTW89_WW][40] = -18,
- [0][0][RTW89_WW][42] = -18,
- [0][0][RTW89_WW][44] = -16,
- [0][0][RTW89_WW][45] = -16,
- [0][0][RTW89_WW][47] = -18,
- [0][0][RTW89_WW][49] = -18,
- [0][0][RTW89_WW][51] = -18,
- [0][0][RTW89_WW][53] = -16,
- [0][0][RTW89_WW][55] = -18,
- [0][0][RTW89_WW][57] = -18,
- [0][0][RTW89_WW][59] = -18,
- [0][0][RTW89_WW][60] = -18,
- [0][0][RTW89_WW][62] = -18,
- [0][0][RTW89_WW][64] = -18,
- [0][0][RTW89_WW][66] = -18,
- [0][0][RTW89_WW][68] = -18,
- [0][0][RTW89_WW][70] = -16,
- [0][0][RTW89_WW][72] = -18,
- [0][0][RTW89_WW][74] = -18,
- [0][0][RTW89_WW][75] = -18,
- [0][0][RTW89_WW][77] = -18,
- [0][0][RTW89_WW][79] = -18,
- [0][0][RTW89_WW][81] = -18,
- [0][0][RTW89_WW][83] = -18,
- [0][0][RTW89_WW][85] = -18,
- [0][0][RTW89_WW][87] = -16,
- [0][0][RTW89_WW][89] = -16,
- [0][0][RTW89_WW][90] = -16,
- [0][0][RTW89_WW][92] = -16,
- [0][0][RTW89_WW][94] = -16,
- [0][0][RTW89_WW][96] = -16,
- [0][0][RTW89_WW][98] = -16,
- [0][0][RTW89_WW][100] = -16,
- [0][0][RTW89_WW][102] = -16,
- [0][0][RTW89_WW][104] = -16,
- [0][0][RTW89_WW][105] = -16,
- [0][0][RTW89_WW][107] = -12,
- [0][0][RTW89_WW][109] = -12,
- [0][0][RTW89_WW][111] = 0,
- [0][0][RTW89_WW][113] = 0,
- [0][0][RTW89_WW][115] = 0,
- [0][0][RTW89_WW][117] = 0,
- [0][0][RTW89_WW][119] = 0,
- [0][1][RTW89_WW][0] = -40,
- [0][1][RTW89_WW][2] = -40,
- [0][1][RTW89_WW][4] = -40,
- [0][1][RTW89_WW][6] = -40,
- [0][1][RTW89_WW][8] = -40,
- [0][1][RTW89_WW][10] = -40,
- [0][1][RTW89_WW][12] = -40,
- [0][1][RTW89_WW][14] = -40,
- [0][1][RTW89_WW][15] = -40,
- [0][1][RTW89_WW][17] = -40,
- [0][1][RTW89_WW][19] = -40,
- [0][1][RTW89_WW][21] = -40,
- [0][1][RTW89_WW][23] = -40,
- [0][1][RTW89_WW][25] = -40,
- [0][1][RTW89_WW][27] = -40,
- [0][1][RTW89_WW][29] = -40,
- [0][1][RTW89_WW][30] = -40,
- [0][1][RTW89_WW][32] = -40,
- [0][1][RTW89_WW][34] = -40,
- [0][1][RTW89_WW][36] = -40,
- [0][1][RTW89_WW][38] = -40,
- [0][1][RTW89_WW][40] = -40,
- [0][1][RTW89_WW][42] = -40,
- [0][1][RTW89_WW][44] = -40,
- [0][1][RTW89_WW][45] = -40,
- [0][1][RTW89_WW][47] = -40,
- [0][1][RTW89_WW][49] = -40,
- [0][1][RTW89_WW][51] = -40,
- [0][1][RTW89_WW][53] = -40,
- [0][1][RTW89_WW][55] = -40,
- [0][1][RTW89_WW][57] = -40,
- [0][1][RTW89_WW][59] = -40,
- [0][1][RTW89_WW][60] = -40,
- [0][1][RTW89_WW][62] = -40,
- [0][1][RTW89_WW][64] = -40,
- [0][1][RTW89_WW][66] = -40,
- [0][1][RTW89_WW][68] = -40,
- [0][1][RTW89_WW][70] = -38,
- [0][1][RTW89_WW][72] = -38,
- [0][1][RTW89_WW][74] = -38,
- [0][1][RTW89_WW][75] = -38,
- [0][1][RTW89_WW][77] = -38,
- [0][1][RTW89_WW][79] = -38,
- [0][1][RTW89_WW][81] = -38,
- [0][1][RTW89_WW][83] = -38,
- [0][1][RTW89_WW][85] = -38,
- [0][1][RTW89_WW][87] = -40,
- [0][1][RTW89_WW][89] = -38,
- [0][1][RTW89_WW][90] = -38,
- [0][1][RTW89_WW][92] = -38,
- [0][1][RTW89_WW][94] = -38,
- [0][1][RTW89_WW][96] = -38,
- [0][1][RTW89_WW][98] = -38,
- [0][1][RTW89_WW][100] = -38,
- [0][1][RTW89_WW][102] = -38,
- [0][1][RTW89_WW][104] = -38,
- [0][1][RTW89_WW][105] = -38,
- [0][1][RTW89_WW][107] = -34,
- [0][1][RTW89_WW][109] = -34,
- [0][1][RTW89_WW][111] = 0,
- [0][1][RTW89_WW][113] = 0,
- [0][1][RTW89_WW][115] = 0,
- [0][1][RTW89_WW][117] = 0,
- [0][1][RTW89_WW][119] = 0,
- [1][0][RTW89_WW][0] = -4,
- [1][0][RTW89_WW][2] = -4,
- [1][0][RTW89_WW][4] = -4,
- [1][0][RTW89_WW][6] = -4,
- [1][0][RTW89_WW][8] = -4,
- [1][0][RTW89_WW][10] = -4,
- [1][0][RTW89_WW][12] = -4,
- [1][0][RTW89_WW][14] = -4,
- [1][0][RTW89_WW][15] = -4,
- [1][0][RTW89_WW][17] = -4,
- [1][0][RTW89_WW][19] = -4,
- [1][0][RTW89_WW][21] = -4,
- [1][0][RTW89_WW][23] = -4,
- [1][0][RTW89_WW][25] = -4,
- [1][0][RTW89_WW][27] = -4,
- [1][0][RTW89_WW][29] = -4,
- [1][0][RTW89_WW][30] = -4,
- [1][0][RTW89_WW][32] = -4,
- [1][0][RTW89_WW][34] = -4,
- [1][0][RTW89_WW][36] = -4,
- [1][0][RTW89_WW][38] = -4,
- [1][0][RTW89_WW][40] = -4,
- [1][0][RTW89_WW][42] = -4,
- [1][0][RTW89_WW][44] = -4,
- [1][0][RTW89_WW][45] = -4,
- [1][0][RTW89_WW][47] = -4,
- [1][0][RTW89_WW][49] = -4,
- [1][0][RTW89_WW][51] = -4,
- [1][0][RTW89_WW][53] = -4,
- [1][0][RTW89_WW][55] = -4,
- [1][0][RTW89_WW][57] = -4,
- [1][0][RTW89_WW][59] = -4,
- [1][0][RTW89_WW][60] = -4,
- [1][0][RTW89_WW][62] = -4,
- [1][0][RTW89_WW][64] = -4,
- [1][0][RTW89_WW][66] = -4,
- [1][0][RTW89_WW][68] = -4,
- [1][0][RTW89_WW][70] = -4,
- [1][0][RTW89_WW][72] = -4,
- [1][0][RTW89_WW][74] = -4,
- [1][0][RTW89_WW][75] = -4,
- [1][0][RTW89_WW][77] = -4,
- [1][0][RTW89_WW][79] = -4,
- [1][0][RTW89_WW][81] = -4,
- [1][0][RTW89_WW][83] = -4,
- [1][0][RTW89_WW][85] = -4,
- [1][0][RTW89_WW][87] = -4,
- [1][0][RTW89_WW][89] = -4,
- [1][0][RTW89_WW][90] = -4,
- [1][0][RTW89_WW][92] = -4,
- [1][0][RTW89_WW][94] = -4,
- [1][0][RTW89_WW][96] = -4,
- [1][0][RTW89_WW][98] = -4,
- [1][0][RTW89_WW][100] = -4,
- [1][0][RTW89_WW][102] = -4,
- [1][0][RTW89_WW][104] = -4,
- [1][0][RTW89_WW][105] = -4,
- [1][0][RTW89_WW][107] = 1,
- [1][0][RTW89_WW][109] = 2,
- [1][0][RTW89_WW][111] = 0,
- [1][0][RTW89_WW][113] = 0,
- [1][0][RTW89_WW][115] = 0,
- [1][0][RTW89_WW][117] = 0,
- [1][0][RTW89_WW][119] = 0,
- [1][1][RTW89_WW][0] = -26,
- [1][1][RTW89_WW][2] = -28,
- [1][1][RTW89_WW][4] = -28,
- [1][1][RTW89_WW][6] = -28,
- [1][1][RTW89_WW][8] = -28,
- [1][1][RTW89_WW][10] = -28,
- [1][1][RTW89_WW][12] = -28,
- [1][1][RTW89_WW][14] = -28,
- [1][1][RTW89_WW][15] = -28,
- [1][1][RTW89_WW][17] = -28,
- [1][1][RTW89_WW][19] = -28,
- [1][1][RTW89_WW][21] = -28,
- [1][1][RTW89_WW][23] = -28,
- [1][1][RTW89_WW][25] = -28,
- [1][1][RTW89_WW][27] = -28,
- [1][1][RTW89_WW][29] = -28,
- [1][1][RTW89_WW][30] = -28,
- [1][1][RTW89_WW][32] = -28,
- [1][1][RTW89_WW][34] = -28,
- [1][1][RTW89_WW][36] = -28,
- [1][1][RTW89_WW][38] = -28,
- [1][1][RTW89_WW][40] = -28,
- [1][1][RTW89_WW][42] = -28,
- [1][1][RTW89_WW][44] = -28,
- [1][1][RTW89_WW][45] = -26,
- [1][1][RTW89_WW][47] = -28,
- [1][1][RTW89_WW][49] = -28,
- [1][1][RTW89_WW][51] = -28,
- [1][1][RTW89_WW][53] = -26,
- [1][1][RTW89_WW][55] = -28,
- [1][1][RTW89_WW][57] = -28,
- [1][1][RTW89_WW][59] = -28,
- [1][1][RTW89_WW][60] = -28,
- [1][1][RTW89_WW][62] = -28,
- [1][1][RTW89_WW][64] = -28,
- [1][1][RTW89_WW][66] = -28,
- [1][1][RTW89_WW][68] = -28,
- [1][1][RTW89_WW][70] = -26,
- [1][1][RTW89_WW][72] = -28,
- [1][1][RTW89_WW][74] = -28,
- [1][1][RTW89_WW][75] = -28,
- [1][1][RTW89_WW][77] = -28,
- [1][1][RTW89_WW][79] = -28,
- [1][1][RTW89_WW][81] = -28,
- [1][1][RTW89_WW][83] = -28,
- [1][1][RTW89_WW][85] = -28,
- [1][1][RTW89_WW][87] = -28,
- [1][1][RTW89_WW][89] = -26,
- [1][1][RTW89_WW][90] = -26,
- [1][1][RTW89_WW][92] = -26,
- [1][1][RTW89_WW][94] = -26,
- [1][1][RTW89_WW][96] = -26,
- [1][1][RTW89_WW][98] = -26,
- [1][1][RTW89_WW][100] = -26,
- [1][1][RTW89_WW][102] = -26,
- [1][1][RTW89_WW][104] = -26,
- [1][1][RTW89_WW][105] = -26,
- [1][1][RTW89_WW][107] = -22,
- [1][1][RTW89_WW][109] = -22,
- [1][1][RTW89_WW][111] = 0,
- [1][1][RTW89_WW][113] = 0,
- [1][1][RTW89_WW][115] = 0,
- [1][1][RTW89_WW][117] = 0,
- [1][1][RTW89_WW][119] = 0,
- [2][0][RTW89_WW][0] = 8,
- [2][0][RTW89_WW][2] = 8,
- [2][0][RTW89_WW][4] = 8,
- [2][0][RTW89_WW][6] = 8,
- [2][0][RTW89_WW][8] = 8,
- [2][0][RTW89_WW][10] = 8,
- [2][0][RTW89_WW][12] = 8,
- [2][0][RTW89_WW][14] = 8,
- [2][0][RTW89_WW][15] = 8,
- [2][0][RTW89_WW][17] = 8,
- [2][0][RTW89_WW][19] = 8,
- [2][0][RTW89_WW][21] = 8,
- [2][0][RTW89_WW][23] = 8,
- [2][0][RTW89_WW][25] = 8,
- [2][0][RTW89_WW][27] = 8,
- [2][0][RTW89_WW][29] = 8,
- [2][0][RTW89_WW][30] = 8,
- [2][0][RTW89_WW][32] = 8,
- [2][0][RTW89_WW][34] = 8,
- [2][0][RTW89_WW][36] = 8,
- [2][0][RTW89_WW][38] = 8,
- [2][0][RTW89_WW][40] = 8,
- [2][0][RTW89_WW][42] = 8,
- [2][0][RTW89_WW][44] = 8,
- [2][0][RTW89_WW][45] = 8,
- [2][0][RTW89_WW][47] = 8,
- [2][0][RTW89_WW][49] = 8,
- [2][0][RTW89_WW][51] = 8,
- [2][0][RTW89_WW][53] = 8,
- [2][0][RTW89_WW][55] = 8,
- [2][0][RTW89_WW][57] = 8,
- [2][0][RTW89_WW][59] = 8,
- [2][0][RTW89_WW][60] = 8,
- [2][0][RTW89_WW][62] = 8,
- [2][0][RTW89_WW][64] = 8,
- [2][0][RTW89_WW][66] = 8,
- [2][0][RTW89_WW][68] = 8,
- [2][0][RTW89_WW][70] = 8,
- [2][0][RTW89_WW][72] = 8,
- [2][0][RTW89_WW][74] = 8,
- [2][0][RTW89_WW][75] = 8,
- [2][0][RTW89_WW][77] = 8,
- [2][0][RTW89_WW][79] = 8,
- [2][0][RTW89_WW][81] = 8,
- [2][0][RTW89_WW][83] = 8,
- [2][0][RTW89_WW][85] = 8,
- [2][0][RTW89_WW][87] = 8,
- [2][0][RTW89_WW][89] = 8,
- [2][0][RTW89_WW][90] = 8,
- [2][0][RTW89_WW][92] = 8,
- [2][0][RTW89_WW][94] = 8,
- [2][0][RTW89_WW][96] = 8,
- [2][0][RTW89_WW][98] = 8,
- [2][0][RTW89_WW][100] = 8,
- [2][0][RTW89_WW][102] = 8,
- [2][0][RTW89_WW][104] = 8,
- [2][0][RTW89_WW][105] = 8,
- [2][0][RTW89_WW][107] = 10,
- [2][0][RTW89_WW][109] = 12,
- [2][0][RTW89_WW][111] = 0,
- [2][0][RTW89_WW][113] = 0,
- [2][0][RTW89_WW][115] = 0,
- [2][0][RTW89_WW][117] = 0,
- [2][0][RTW89_WW][119] = 0,
- [2][1][RTW89_WW][0] = -16,
- [2][1][RTW89_WW][2] = -16,
- [2][1][RTW89_WW][4] = -16,
- [2][1][RTW89_WW][6] = -16,
- [2][1][RTW89_WW][8] = -16,
- [2][1][RTW89_WW][10] = -16,
- [2][1][RTW89_WW][12] = -16,
- [2][1][RTW89_WW][14] = -16,
- [2][1][RTW89_WW][15] = -16,
- [2][1][RTW89_WW][17] = -16,
- [2][1][RTW89_WW][19] = -16,
- [2][1][RTW89_WW][21] = -16,
- [2][1][RTW89_WW][23] = -16,
- [2][1][RTW89_WW][25] = -16,
- [2][1][RTW89_WW][27] = -16,
- [2][1][RTW89_WW][29] = -16,
- [2][1][RTW89_WW][30] = -16,
- [2][1][RTW89_WW][32] = -16,
- [2][1][RTW89_WW][34] = -16,
- [2][1][RTW89_WW][36] = -16,
- [2][1][RTW89_WW][38] = -16,
- [2][1][RTW89_WW][40] = -16,
- [2][1][RTW89_WW][42] = -16,
- [2][1][RTW89_WW][44] = -16,
- [2][1][RTW89_WW][45] = -16,
- [2][1][RTW89_WW][47] = -16,
- [2][1][RTW89_WW][49] = -16,
- [2][1][RTW89_WW][51] = -16,
- [2][1][RTW89_WW][53] = -16,
- [2][1][RTW89_WW][55] = -16,
- [2][1][RTW89_WW][57] = -16,
- [2][1][RTW89_WW][59] = -16,
- [2][1][RTW89_WW][60] = -16,
- [2][1][RTW89_WW][62] = -16,
- [2][1][RTW89_WW][64] = -16,
- [2][1][RTW89_WW][66] = -16,
- [2][1][RTW89_WW][68] = -16,
- [2][1][RTW89_WW][70] = -16,
- [2][1][RTW89_WW][72] = -16,
- [2][1][RTW89_WW][74] = -16,
- [2][1][RTW89_WW][75] = -16,
- [2][1][RTW89_WW][77] = -16,
- [2][1][RTW89_WW][79] = -16,
- [2][1][RTW89_WW][81] = -16,
- [2][1][RTW89_WW][83] = -16,
- [2][1][RTW89_WW][85] = -18,
- [2][1][RTW89_WW][87] = -16,
- [2][1][RTW89_WW][89] = -16,
- [2][1][RTW89_WW][90] = -16,
- [2][1][RTW89_WW][92] = -16,
- [2][1][RTW89_WW][94] = -16,
- [2][1][RTW89_WW][96] = -16,
- [2][1][RTW89_WW][98] = -16,
- [2][1][RTW89_WW][100] = -16,
- [2][1][RTW89_WW][102] = -16,
- [2][1][RTW89_WW][104] = -16,
- [2][1][RTW89_WW][105] = -16,
- [2][1][RTW89_WW][107] = -12,
- [2][1][RTW89_WW][109] = -10,
- [2][1][RTW89_WW][111] = 0,
- [2][1][RTW89_WW][113] = 0,
- [2][1][RTW89_WW][115] = 0,
- [2][1][RTW89_WW][117] = 0,
- [2][1][RTW89_WW][119] = 0,
- [0][0][RTW89_FCC][0] = -16,
- [0][0][RTW89_ETSI][0] = 32,
- [0][0][RTW89_FCC][2] = -18,
- [0][0][RTW89_ETSI][2] = 32,
- [0][0][RTW89_FCC][4] = -18,
- [0][0][RTW89_ETSI][4] = 32,
- [0][0][RTW89_FCC][6] = -18,
- [0][0][RTW89_ETSI][6] = 32,
- [0][0][RTW89_FCC][8] = -18,
- [0][0][RTW89_ETSI][8] = 32,
- [0][0][RTW89_FCC][10] = -18,
- [0][0][RTW89_ETSI][10] = 32,
- [0][0][RTW89_FCC][12] = -18,
- [0][0][RTW89_ETSI][12] = 32,
- [0][0][RTW89_FCC][14] = -18,
- [0][0][RTW89_ETSI][14] = 32,
- [0][0][RTW89_FCC][15] = -18,
- [0][0][RTW89_ETSI][15] = 32,
- [0][0][RTW89_FCC][17] = -18,
- [0][0][RTW89_ETSI][17] = 32,
- [0][0][RTW89_FCC][19] = -18,
- [0][0][RTW89_ETSI][19] = 32,
- [0][0][RTW89_FCC][21] = -18,
- [0][0][RTW89_ETSI][21] = 32,
- [0][0][RTW89_FCC][23] = -18,
- [0][0][RTW89_ETSI][23] = 32,
- [0][0][RTW89_FCC][25] = -18,
- [0][0][RTW89_ETSI][25] = 32,
- [0][0][RTW89_FCC][27] = -18,
- [0][0][RTW89_ETSI][27] = 32,
- [0][0][RTW89_FCC][29] = -18,
- [0][0][RTW89_ETSI][29] = 32,
- [0][0][RTW89_FCC][30] = -18,
- [0][0][RTW89_ETSI][30] = 32,
- [0][0][RTW89_FCC][32] = -18,
- [0][0][RTW89_ETSI][32] = 32,
- [0][0][RTW89_FCC][34] = -18,
- [0][0][RTW89_ETSI][34] = 32,
- [0][0][RTW89_FCC][36] = -18,
- [0][0][RTW89_ETSI][36] = 32,
- [0][0][RTW89_FCC][38] = -18,
- [0][0][RTW89_ETSI][38] = 32,
- [0][0][RTW89_FCC][40] = -18,
- [0][0][RTW89_ETSI][40] = 32,
- [0][0][RTW89_FCC][42] = -18,
- [0][0][RTW89_ETSI][42] = 32,
- [0][0][RTW89_FCC][44] = -16,
- [0][0][RTW89_ETSI][44] = 32,
- [0][0][RTW89_FCC][45] = -16,
- [0][0][RTW89_ETSI][45] = 127,
- [0][0][RTW89_FCC][47] = -18,
- [0][0][RTW89_ETSI][47] = 127,
- [0][0][RTW89_FCC][49] = -18,
- [0][0][RTW89_ETSI][49] = 127,
- [0][0][RTW89_FCC][51] = -18,
- [0][0][RTW89_ETSI][51] = 127,
- [0][0][RTW89_FCC][53] = -16,
- [0][0][RTW89_ETSI][53] = 127,
- [0][0][RTW89_FCC][55] = -18,
- [0][0][RTW89_ETSI][55] = 127,
- [0][0][RTW89_FCC][57] = -18,
- [0][0][RTW89_ETSI][57] = 127,
- [0][0][RTW89_FCC][59] = -18,
- [0][0][RTW89_ETSI][59] = 127,
- [0][0][RTW89_FCC][60] = -18,
- [0][0][RTW89_ETSI][60] = 127,
- [0][0][RTW89_FCC][62] = -18,
- [0][0][RTW89_ETSI][62] = 127,
- [0][0][RTW89_FCC][64] = -18,
- [0][0][RTW89_ETSI][64] = 127,
- [0][0][RTW89_FCC][66] = -18,
- [0][0][RTW89_ETSI][66] = 127,
- [0][0][RTW89_FCC][68] = -18,
- [0][0][RTW89_ETSI][68] = 127,
- [0][0][RTW89_FCC][70] = -16,
- [0][0][RTW89_ETSI][70] = 127,
- [0][0][RTW89_FCC][72] = -18,
- [0][0][RTW89_ETSI][72] = 127,
- [0][0][RTW89_FCC][74] = -18,
- [0][0][RTW89_ETSI][74] = 127,
- [0][0][RTW89_FCC][75] = -18,
- [0][0][RTW89_ETSI][75] = 127,
- [0][0][RTW89_FCC][77] = -18,
- [0][0][RTW89_ETSI][77] = 127,
- [0][0][RTW89_FCC][79] = -18,
- [0][0][RTW89_ETSI][79] = 127,
- [0][0][RTW89_FCC][81] = -18,
- [0][0][RTW89_ETSI][81] = 127,
- [0][0][RTW89_FCC][83] = -18,
- [0][0][RTW89_ETSI][83] = 127,
- [0][0][RTW89_FCC][85] = -18,
- [0][0][RTW89_ETSI][85] = 127,
- [0][0][RTW89_FCC][87] = -16,
- [0][0][RTW89_ETSI][87] = 127,
- [0][0][RTW89_FCC][89] = -16,
- [0][0][RTW89_ETSI][89] = 127,
- [0][0][RTW89_FCC][90] = -16,
- [0][0][RTW89_ETSI][90] = 127,
- [0][0][RTW89_FCC][92] = -16,
- [0][0][RTW89_ETSI][92] = 127,
- [0][0][RTW89_FCC][94] = -16,
- [0][0][RTW89_ETSI][94] = 127,
- [0][0][RTW89_FCC][96] = -16,
- [0][0][RTW89_ETSI][96] = 127,
- [0][0][RTW89_FCC][98] = -16,
- [0][0][RTW89_ETSI][98] = 127,
- [0][0][RTW89_FCC][100] = -16,
- [0][0][RTW89_ETSI][100] = 127,
- [0][0][RTW89_FCC][102] = -16,
- [0][0][RTW89_ETSI][102] = 127,
- [0][0][RTW89_FCC][104] = -16,
- [0][0][RTW89_ETSI][104] = 127,
- [0][0][RTW89_FCC][105] = -16,
- [0][0][RTW89_ETSI][105] = 127,
- [0][0][RTW89_FCC][107] = -12,
- [0][0][RTW89_ETSI][107] = 127,
- [0][0][RTW89_FCC][109] = -12,
- [0][0][RTW89_ETSI][109] = 127,
- [0][0][RTW89_FCC][111] = 127,
- [0][0][RTW89_ETSI][111] = 127,
- [0][0][RTW89_FCC][113] = 127,
- [0][0][RTW89_ETSI][113] = 127,
- [0][0][RTW89_FCC][115] = 127,
- [0][0][RTW89_ETSI][115] = 127,
- [0][0][RTW89_FCC][117] = 127,
- [0][0][RTW89_ETSI][117] = 127,
- [0][0][RTW89_FCC][119] = 127,
- [0][0][RTW89_ETSI][119] = 127,
- [0][1][RTW89_FCC][0] = -40,
- [0][1][RTW89_ETSI][0] = 20,
- [0][1][RTW89_FCC][2] = -40,
- [0][1][RTW89_ETSI][2] = 20,
- [0][1][RTW89_FCC][4] = -40,
- [0][1][RTW89_ETSI][4] = 20,
- [0][1][RTW89_FCC][6] = -40,
- [0][1][RTW89_ETSI][6] = 20,
- [0][1][RTW89_FCC][8] = -40,
- [0][1][RTW89_ETSI][8] = 20,
- [0][1][RTW89_FCC][10] = -40,
- [0][1][RTW89_ETSI][10] = 20,
- [0][1][RTW89_FCC][12] = -40,
- [0][1][RTW89_ETSI][12] = 20,
- [0][1][RTW89_FCC][14] = -40,
- [0][1][RTW89_ETSI][14] = 20,
- [0][1][RTW89_FCC][15] = -40,
- [0][1][RTW89_ETSI][15] = 20,
- [0][1][RTW89_FCC][17] = -40,
- [0][1][RTW89_ETSI][17] = 20,
- [0][1][RTW89_FCC][19] = -40,
- [0][1][RTW89_ETSI][19] = 20,
- [0][1][RTW89_FCC][21] = -40,
- [0][1][RTW89_ETSI][21] = 20,
- [0][1][RTW89_FCC][23] = -40,
- [0][1][RTW89_ETSI][23] = 20,
- [0][1][RTW89_FCC][25] = -40,
- [0][1][RTW89_ETSI][25] = 20,
- [0][1][RTW89_FCC][27] = -40,
- [0][1][RTW89_ETSI][27] = 20,
- [0][1][RTW89_FCC][29] = -40,
- [0][1][RTW89_ETSI][29] = 20,
- [0][1][RTW89_FCC][30] = -40,
- [0][1][RTW89_ETSI][30] = 20,
- [0][1][RTW89_FCC][32] = -40,
- [0][1][RTW89_ETSI][32] = 20,
- [0][1][RTW89_FCC][34] = -40,
- [0][1][RTW89_ETSI][34] = 20,
- [0][1][RTW89_FCC][36] = -40,
- [0][1][RTW89_ETSI][36] = 20,
- [0][1][RTW89_FCC][38] = -40,
- [0][1][RTW89_ETSI][38] = 20,
- [0][1][RTW89_FCC][40] = -40,
- [0][1][RTW89_ETSI][40] = 20,
- [0][1][RTW89_FCC][42] = -40,
- [0][1][RTW89_ETSI][42] = 20,
- [0][1][RTW89_FCC][44] = -40,
- [0][1][RTW89_ETSI][44] = 20,
- [0][1][RTW89_FCC][45] = -40,
- [0][1][RTW89_ETSI][45] = 127,
- [0][1][RTW89_FCC][47] = -40,
- [0][1][RTW89_ETSI][47] = 127,
- [0][1][RTW89_FCC][49] = -40,
- [0][1][RTW89_ETSI][49] = 127,
- [0][1][RTW89_FCC][51] = -40,
- [0][1][RTW89_ETSI][51] = 127,
- [0][1][RTW89_FCC][53] = -40,
- [0][1][RTW89_ETSI][53] = 127,
- [0][1][RTW89_FCC][55] = -40,
- [0][1][RTW89_ETSI][55] = 127,
- [0][1][RTW89_FCC][57] = -40,
- [0][1][RTW89_ETSI][57] = 127,
- [0][1][RTW89_FCC][59] = -40,
- [0][1][RTW89_ETSI][59] = 127,
- [0][1][RTW89_FCC][60] = -40,
- [0][1][RTW89_ETSI][60] = 127,
- [0][1][RTW89_FCC][62] = -40,
- [0][1][RTW89_ETSI][62] = 127,
- [0][1][RTW89_FCC][64] = -40,
- [0][1][RTW89_ETSI][64] = 127,
- [0][1][RTW89_FCC][66] = -40,
- [0][1][RTW89_ETSI][66] = 127,
- [0][1][RTW89_FCC][68] = -40,
- [0][1][RTW89_ETSI][68] = 127,
- [0][1][RTW89_FCC][70] = -38,
- [0][1][RTW89_ETSI][70] = 127,
- [0][1][RTW89_FCC][72] = -38,
- [0][1][RTW89_ETSI][72] = 127,
- [0][1][RTW89_FCC][74] = -38,
- [0][1][RTW89_ETSI][74] = 127,
- [0][1][RTW89_FCC][75] = -38,
- [0][1][RTW89_ETSI][75] = 127,
- [0][1][RTW89_FCC][77] = -38,
- [0][1][RTW89_ETSI][77] = 127,
- [0][1][RTW89_FCC][79] = -38,
- [0][1][RTW89_ETSI][79] = 127,
- [0][1][RTW89_FCC][81] = -38,
- [0][1][RTW89_ETSI][81] = 127,
- [0][1][RTW89_FCC][83] = -38,
- [0][1][RTW89_ETSI][83] = 127,
- [0][1][RTW89_FCC][85] = -38,
- [0][1][RTW89_ETSI][85] = 127,
- [0][1][RTW89_FCC][87] = -40,
- [0][1][RTW89_ETSI][87] = 127,
- [0][1][RTW89_FCC][89] = -38,
- [0][1][RTW89_ETSI][89] = 127,
- [0][1][RTW89_FCC][90] = -38,
- [0][1][RTW89_ETSI][90] = 127,
- [0][1][RTW89_FCC][92] = -38,
- [0][1][RTW89_ETSI][92] = 127,
- [0][1][RTW89_FCC][94] = -38,
- [0][1][RTW89_ETSI][94] = 127,
- [0][1][RTW89_FCC][96] = -38,
- [0][1][RTW89_ETSI][96] = 127,
- [0][1][RTW89_FCC][98] = -38,
- [0][1][RTW89_ETSI][98] = 127,
- [0][1][RTW89_FCC][100] = -38,
- [0][1][RTW89_ETSI][100] = 127,
- [0][1][RTW89_FCC][102] = -38,
- [0][1][RTW89_ETSI][102] = 127,
- [0][1][RTW89_FCC][104] = -38,
- [0][1][RTW89_ETSI][104] = 127,
- [0][1][RTW89_FCC][105] = -38,
- [0][1][RTW89_ETSI][105] = 127,
- [0][1][RTW89_FCC][107] = -34,
- [0][1][RTW89_ETSI][107] = 127,
- [0][1][RTW89_FCC][109] = -34,
- [0][1][RTW89_ETSI][109] = 127,
- [0][1][RTW89_FCC][111] = 127,
- [0][1][RTW89_ETSI][111] = 127,
- [0][1][RTW89_FCC][113] = 127,
- [0][1][RTW89_ETSI][113] = 127,
- [0][1][RTW89_FCC][115] = 127,
- [0][1][RTW89_ETSI][115] = 127,
- [0][1][RTW89_FCC][117] = 127,
- [0][1][RTW89_ETSI][117] = 127,
- [0][1][RTW89_FCC][119] = 127,
- [0][1][RTW89_ETSI][119] = 127,
- [1][0][RTW89_FCC][0] = -4,
- [1][0][RTW89_ETSI][0] = 46,
- [1][0][RTW89_FCC][2] = -4,
- [1][0][RTW89_ETSI][2] = 46,
- [1][0][RTW89_FCC][4] = -4,
- [1][0][RTW89_ETSI][4] = 46,
- [1][0][RTW89_FCC][6] = -4,
- [1][0][RTW89_ETSI][6] = 46,
- [1][0][RTW89_FCC][8] = -4,
- [1][0][RTW89_ETSI][8] = 46,
- [1][0][RTW89_FCC][10] = -4,
- [1][0][RTW89_ETSI][10] = 46,
- [1][0][RTW89_FCC][12] = -4,
- [1][0][RTW89_ETSI][12] = 46,
- [1][0][RTW89_FCC][14] = -4,
- [1][0][RTW89_ETSI][14] = 46,
- [1][0][RTW89_FCC][15] = -4,
- [1][0][RTW89_ETSI][15] = 46,
- [1][0][RTW89_FCC][17] = -4,
- [1][0][RTW89_ETSI][17] = 46,
- [1][0][RTW89_FCC][19] = -4,
- [1][0][RTW89_ETSI][19] = 46,
- [1][0][RTW89_FCC][21] = -4,
- [1][0][RTW89_ETSI][21] = 46,
- [1][0][RTW89_FCC][23] = -4,
- [1][0][RTW89_ETSI][23] = 46,
- [1][0][RTW89_FCC][25] = -4,
- [1][0][RTW89_ETSI][25] = 46,
- [1][0][RTW89_FCC][27] = -4,
- [1][0][RTW89_ETSI][27] = 46,
- [1][0][RTW89_FCC][29] = -4,
- [1][0][RTW89_ETSI][29] = 46,
- [1][0][RTW89_FCC][30] = -4,
- [1][0][RTW89_ETSI][30] = 46,
- [1][0][RTW89_FCC][32] = -4,
- [1][0][RTW89_ETSI][32] = 46,
- [1][0][RTW89_FCC][34] = -4,
- [1][0][RTW89_ETSI][34] = 46,
- [1][0][RTW89_FCC][36] = -4,
- [1][0][RTW89_ETSI][36] = 46,
- [1][0][RTW89_FCC][38] = -4,
- [1][0][RTW89_ETSI][38] = 46,
- [1][0][RTW89_FCC][40] = -4,
- [1][0][RTW89_ETSI][40] = 46,
- [1][0][RTW89_FCC][42] = -4,
- [1][0][RTW89_ETSI][42] = 46,
- [1][0][RTW89_FCC][44] = -4,
- [1][0][RTW89_ETSI][44] = 46,
- [1][0][RTW89_FCC][45] = -4,
- [1][0][RTW89_ETSI][45] = 127,
- [1][0][RTW89_FCC][47] = -4,
- [1][0][RTW89_ETSI][47] = 127,
- [1][0][RTW89_FCC][49] = -4,
- [1][0][RTW89_ETSI][49] = 127,
- [1][0][RTW89_FCC][51] = -4,
- [1][0][RTW89_ETSI][51] = 127,
- [1][0][RTW89_FCC][53] = -4,
- [1][0][RTW89_ETSI][53] = 127,
- [1][0][RTW89_FCC][55] = -4,
- [1][0][RTW89_ETSI][55] = 127,
- [1][0][RTW89_FCC][57] = -4,
- [1][0][RTW89_ETSI][57] = 127,
- [1][0][RTW89_FCC][59] = -4,
- [1][0][RTW89_ETSI][59] = 127,
- [1][0][RTW89_FCC][60] = -4,
- [1][0][RTW89_ETSI][60] = 127,
- [1][0][RTW89_FCC][62] = -4,
- [1][0][RTW89_ETSI][62] = 127,
- [1][0][RTW89_FCC][64] = -4,
- [1][0][RTW89_ETSI][64] = 127,
- [1][0][RTW89_FCC][66] = -4,
- [1][0][RTW89_ETSI][66] = 127,
- [1][0][RTW89_FCC][68] = -4,
- [1][0][RTW89_ETSI][68] = 127,
- [1][0][RTW89_FCC][70] = -4,
- [1][0][RTW89_ETSI][70] = 127,
- [1][0][RTW89_FCC][72] = -4,
- [1][0][RTW89_ETSI][72] = 127,
- [1][0][RTW89_FCC][74] = -4,
- [1][0][RTW89_ETSI][74] = 127,
- [1][0][RTW89_FCC][75] = -4,
- [1][0][RTW89_ETSI][75] = 127,
- [1][0][RTW89_FCC][77] = -4,
- [1][0][RTW89_ETSI][77] = 127,
- [1][0][RTW89_FCC][79] = -4,
- [1][0][RTW89_ETSI][79] = 127,
- [1][0][RTW89_FCC][81] = -4,
- [1][0][RTW89_ETSI][81] = 127,
- [1][0][RTW89_FCC][83] = -4,
- [1][0][RTW89_ETSI][83] = 127,
- [1][0][RTW89_FCC][85] = -4,
- [1][0][RTW89_ETSI][85] = 127,
- [1][0][RTW89_FCC][87] = -4,
- [1][0][RTW89_ETSI][87] = 127,
- [1][0][RTW89_FCC][89] = -4,
- [1][0][RTW89_ETSI][89] = 127,
- [1][0][RTW89_FCC][90] = -4,
- [1][0][RTW89_ETSI][90] = 127,
- [1][0][RTW89_FCC][92] = -4,
- [1][0][RTW89_ETSI][92] = 127,
- [1][0][RTW89_FCC][94] = -4,
- [1][0][RTW89_ETSI][94] = 127,
- [1][0][RTW89_FCC][96] = -4,
- [1][0][RTW89_ETSI][96] = 127,
- [1][0][RTW89_FCC][98] = -4,
- [1][0][RTW89_ETSI][98] = 127,
- [1][0][RTW89_FCC][100] = -4,
- [1][0][RTW89_ETSI][100] = 127,
- [1][0][RTW89_FCC][102] = -4,
- [1][0][RTW89_ETSI][102] = 127,
- [1][0][RTW89_FCC][104] = -4,
- [1][0][RTW89_ETSI][104] = 127,
- [1][0][RTW89_FCC][105] = -4,
- [1][0][RTW89_ETSI][105] = 127,
- [1][0][RTW89_FCC][107] = 0,
- [1][0][RTW89_ETSI][107] = 127,
- [1][0][RTW89_FCC][109] = 2,
- [1][0][RTW89_ETSI][109] = 127,
- [1][0][RTW89_FCC][111] = 127,
- [1][0][RTW89_ETSI][111] = 127,
- [1][0][RTW89_FCC][113] = 127,
- [1][0][RTW89_ETSI][113] = 127,
- [1][0][RTW89_FCC][115] = 127,
- [1][0][RTW89_ETSI][115] = 127,
- [1][0][RTW89_FCC][117] = 127,
- [1][0][RTW89_ETSI][117] = 127,
- [1][0][RTW89_FCC][119] = 127,
- [1][0][RTW89_ETSI][119] = 127,
- [1][1][RTW89_FCC][0] = -26,
- [1][1][RTW89_ETSI][0] = 32,
- [1][1][RTW89_FCC][2] = -28,
- [1][1][RTW89_ETSI][2] = 32,
- [1][1][RTW89_FCC][4] = -28,
- [1][1][RTW89_ETSI][4] = 32,
- [1][1][RTW89_FCC][6] = -28,
- [1][1][RTW89_ETSI][6] = 32,
- [1][1][RTW89_FCC][8] = -28,
- [1][1][RTW89_ETSI][8] = 32,
- [1][1][RTW89_FCC][10] = -28,
- [1][1][RTW89_ETSI][10] = 32,
- [1][1][RTW89_FCC][12] = -28,
- [1][1][RTW89_ETSI][12] = 32,
- [1][1][RTW89_FCC][14] = -28,
- [1][1][RTW89_ETSI][14] = 32,
- [1][1][RTW89_FCC][15] = -28,
- [1][1][RTW89_ETSI][15] = 32,
- [1][1][RTW89_FCC][17] = -28,
- [1][1][RTW89_ETSI][17] = 32,
- [1][1][RTW89_FCC][19] = -28,
- [1][1][RTW89_ETSI][19] = 32,
- [1][1][RTW89_FCC][21] = -28,
- [1][1][RTW89_ETSI][21] = 32,
- [1][1][RTW89_FCC][23] = -28,
- [1][1][RTW89_ETSI][23] = 32,
- [1][1][RTW89_FCC][25] = -28,
- [1][1][RTW89_ETSI][25] = 32,
- [1][1][RTW89_FCC][27] = -28,
- [1][1][RTW89_ETSI][27] = 32,
- [1][1][RTW89_FCC][29] = -28,
- [1][1][RTW89_ETSI][29] = 32,
- [1][1][RTW89_FCC][30] = -28,
- [1][1][RTW89_ETSI][30] = 32,
- [1][1][RTW89_FCC][32] = -28,
- [1][1][RTW89_ETSI][32] = 32,
- [1][1][RTW89_FCC][34] = -28,
- [1][1][RTW89_ETSI][34] = 32,
- [1][1][RTW89_FCC][36] = -28,
- [1][1][RTW89_ETSI][36] = 32,
- [1][1][RTW89_FCC][38] = -28,
- [1][1][RTW89_ETSI][38] = 32,
- [1][1][RTW89_FCC][40] = -28,
- [1][1][RTW89_ETSI][40] = 32,
- [1][1][RTW89_FCC][42] = -28,
- [1][1][RTW89_ETSI][42] = 32,
- [1][1][RTW89_FCC][44] = -28,
- [1][1][RTW89_ETSI][44] = 34,
- [1][1][RTW89_FCC][45] = -26,
- [1][1][RTW89_ETSI][45] = 127,
- [1][1][RTW89_FCC][47] = -28,
- [1][1][RTW89_ETSI][47] = 127,
- [1][1][RTW89_FCC][49] = -28,
- [1][1][RTW89_ETSI][49] = 127,
- [1][1][RTW89_FCC][51] = -28,
- [1][1][RTW89_ETSI][51] = 127,
- [1][1][RTW89_FCC][53] = -26,
- [1][1][RTW89_ETSI][53] = 127,
- [1][1][RTW89_FCC][55] = -28,
- [1][1][RTW89_ETSI][55] = 127,
- [1][1][RTW89_FCC][57] = -28,
- [1][1][RTW89_ETSI][57] = 127,
- [1][1][RTW89_FCC][59] = -28,
- [1][1][RTW89_ETSI][59] = 127,
- [1][1][RTW89_FCC][60] = -28,
- [1][1][RTW89_ETSI][60] = 127,
- [1][1][RTW89_FCC][62] = -28,
- [1][1][RTW89_ETSI][62] = 127,
- [1][1][RTW89_FCC][64] = -28,
- [1][1][RTW89_ETSI][64] = 127,
- [1][1][RTW89_FCC][66] = -28,
- [1][1][RTW89_ETSI][66] = 127,
- [1][1][RTW89_FCC][68] = -28,
- [1][1][RTW89_ETSI][68] = 127,
- [1][1][RTW89_FCC][70] = -26,
- [1][1][RTW89_ETSI][70] = 127,
- [1][1][RTW89_FCC][72] = -28,
- [1][1][RTW89_ETSI][72] = 127,
- [1][1][RTW89_FCC][74] = -28,
- [1][1][RTW89_ETSI][74] = 127,
- [1][1][RTW89_FCC][75] = -28,
- [1][1][RTW89_ETSI][75] = 127,
- [1][1][RTW89_FCC][77] = -28,
- [1][1][RTW89_ETSI][77] = 127,
- [1][1][RTW89_FCC][79] = -28,
- [1][1][RTW89_ETSI][79] = 127,
- [1][1][RTW89_FCC][81] = -28,
- [1][1][RTW89_ETSI][81] = 127,
- [1][1][RTW89_FCC][83] = -28,
- [1][1][RTW89_ETSI][83] = 127,
- [1][1][RTW89_FCC][85] = -28,
- [1][1][RTW89_ETSI][85] = 127,
- [1][1][RTW89_FCC][87] = -28,
- [1][1][RTW89_ETSI][87] = 127,
- [1][1][RTW89_FCC][89] = -26,
- [1][1][RTW89_ETSI][89] = 127,
- [1][1][RTW89_FCC][90] = -26,
- [1][1][RTW89_ETSI][90] = 127,
- [1][1][RTW89_FCC][92] = -26,
- [1][1][RTW89_ETSI][92] = 127,
- [1][1][RTW89_FCC][94] = -26,
- [1][1][RTW89_ETSI][94] = 127,
- [1][1][RTW89_FCC][96] = -26,
- [1][1][RTW89_ETSI][96] = 127,
- [1][1][RTW89_FCC][98] = -26,
- [1][1][RTW89_ETSI][98] = 127,
- [1][1][RTW89_FCC][100] = -26,
- [1][1][RTW89_ETSI][100] = 127,
- [1][1][RTW89_FCC][102] = -26,
- [1][1][RTW89_ETSI][102] = 127,
- [1][1][RTW89_FCC][104] = -26,
- [1][1][RTW89_ETSI][104] = 127,
- [1][1][RTW89_FCC][105] = -26,
- [1][1][RTW89_ETSI][105] = 127,
- [1][1][RTW89_FCC][107] = -22,
- [1][1][RTW89_ETSI][107] = 127,
- [1][1][RTW89_FCC][109] = -22,
- [1][1][RTW89_ETSI][109] = 127,
- [1][1][RTW89_FCC][111] = 127,
- [1][1][RTW89_ETSI][111] = 127,
- [1][1][RTW89_FCC][113] = 127,
- [1][1][RTW89_ETSI][113] = 127,
- [1][1][RTW89_FCC][115] = 127,
- [1][1][RTW89_ETSI][115] = 127,
- [1][1][RTW89_FCC][117] = 127,
- [1][1][RTW89_ETSI][117] = 127,
- [1][1][RTW89_FCC][119] = 127,
- [1][1][RTW89_ETSI][119] = 127,
- [2][0][RTW89_FCC][0] = 8,
- [2][0][RTW89_ETSI][0] = 56,
- [2][0][RTW89_FCC][2] = 8,
- [2][0][RTW89_ETSI][2] = 56,
- [2][0][RTW89_FCC][4] = 8,
- [2][0][RTW89_ETSI][4] = 56,
- [2][0][RTW89_FCC][6] = 8,
- [2][0][RTW89_ETSI][6] = 56,
- [2][0][RTW89_FCC][8] = 8,
- [2][0][RTW89_ETSI][8] = 56,
- [2][0][RTW89_FCC][10] = 8,
- [2][0][RTW89_ETSI][10] = 56,
- [2][0][RTW89_FCC][12] = 8,
- [2][0][RTW89_ETSI][12] = 56,
- [2][0][RTW89_FCC][14] = 8,
- [2][0][RTW89_ETSI][14] = 56,
- [2][0][RTW89_FCC][15] = 8,
- [2][0][RTW89_ETSI][15] = 56,
- [2][0][RTW89_FCC][17] = 8,
- [2][0][RTW89_ETSI][17] = 56,
- [2][0][RTW89_FCC][19] = 8,
- [2][0][RTW89_ETSI][19] = 56,
- [2][0][RTW89_FCC][21] = 8,
- [2][0][RTW89_ETSI][21] = 56,
- [2][0][RTW89_FCC][23] = 8,
- [2][0][RTW89_ETSI][23] = 56,
- [2][0][RTW89_FCC][25] = 8,
- [2][0][RTW89_ETSI][25] = 56,
- [2][0][RTW89_FCC][27] = 8,
- [2][0][RTW89_ETSI][27] = 56,
- [2][0][RTW89_FCC][29] = 8,
- [2][0][RTW89_ETSI][29] = 56,
- [2][0][RTW89_FCC][30] = 8,
- [2][0][RTW89_ETSI][30] = 56,
- [2][0][RTW89_FCC][32] = 8,
- [2][0][RTW89_ETSI][32] = 56,
- [2][0][RTW89_FCC][34] = 8,
- [2][0][RTW89_ETSI][34] = 56,
- [2][0][RTW89_FCC][36] = 8,
- [2][0][RTW89_ETSI][36] = 56,
- [2][0][RTW89_FCC][38] = 8,
- [2][0][RTW89_ETSI][38] = 56,
- [2][0][RTW89_FCC][40] = 8,
- [2][0][RTW89_ETSI][40] = 56,
- [2][0][RTW89_FCC][42] = 8,
- [2][0][RTW89_ETSI][42] = 56,
- [2][0][RTW89_FCC][44] = 8,
- [2][0][RTW89_ETSI][44] = 56,
- [2][0][RTW89_FCC][45] = 8,
- [2][0][RTW89_ETSI][45] = 127,
- [2][0][RTW89_FCC][47] = 8,
- [2][0][RTW89_ETSI][47] = 127,
- [2][0][RTW89_FCC][49] = 8,
- [2][0][RTW89_ETSI][49] = 127,
- [2][0][RTW89_FCC][51] = 8,
- [2][0][RTW89_ETSI][51] = 127,
- [2][0][RTW89_FCC][53] = 8,
- [2][0][RTW89_ETSI][53] = 127,
- [2][0][RTW89_FCC][55] = 8,
- [2][0][RTW89_ETSI][55] = 127,
- [2][0][RTW89_FCC][57] = 8,
- [2][0][RTW89_ETSI][57] = 127,
- [2][0][RTW89_FCC][59] = 8,
- [2][0][RTW89_ETSI][59] = 127,
- [2][0][RTW89_FCC][60] = 8,
- [2][0][RTW89_ETSI][60] = 127,
- [2][0][RTW89_FCC][62] = 8,
- [2][0][RTW89_ETSI][62] = 127,
- [2][0][RTW89_FCC][64] = 8,
- [2][0][RTW89_ETSI][64] = 127,
- [2][0][RTW89_FCC][66] = 8,
- [2][0][RTW89_ETSI][66] = 127,
- [2][0][RTW89_FCC][68] = 8,
- [2][0][RTW89_ETSI][68] = 127,
- [2][0][RTW89_FCC][70] = 8,
- [2][0][RTW89_ETSI][70] = 127,
- [2][0][RTW89_FCC][72] = 8,
- [2][0][RTW89_ETSI][72] = 127,
- [2][0][RTW89_FCC][74] = 8,
- [2][0][RTW89_ETSI][74] = 127,
- [2][0][RTW89_FCC][75] = 8,
- [2][0][RTW89_ETSI][75] = 127,
- [2][0][RTW89_FCC][77] = 8,
- [2][0][RTW89_ETSI][77] = 127,
- [2][0][RTW89_FCC][79] = 8,
- [2][0][RTW89_ETSI][79] = 127,
- [2][0][RTW89_FCC][81] = 8,
- [2][0][RTW89_ETSI][81] = 127,
- [2][0][RTW89_FCC][83] = 8,
- [2][0][RTW89_ETSI][83] = 127,
- [2][0][RTW89_FCC][85] = 8,
- [2][0][RTW89_ETSI][85] = 127,
- [2][0][RTW89_FCC][87] = 8,
- [2][0][RTW89_ETSI][87] = 127,
- [2][0][RTW89_FCC][89] = 8,
- [2][0][RTW89_ETSI][89] = 127,
- [2][0][RTW89_FCC][90] = 8,
- [2][0][RTW89_ETSI][90] = 127,
- [2][0][RTW89_FCC][92] = 8,
- [2][0][RTW89_ETSI][92] = 127,
- [2][0][RTW89_FCC][94] = 8,
- [2][0][RTW89_ETSI][94] = 127,
- [2][0][RTW89_FCC][96] = 8,
- [2][0][RTW89_ETSI][96] = 127,
- [2][0][RTW89_FCC][98] = 8,
- [2][0][RTW89_ETSI][98] = 127,
- [2][0][RTW89_FCC][100] = 8,
- [2][0][RTW89_ETSI][100] = 127,
- [2][0][RTW89_FCC][102] = 8,
- [2][0][RTW89_ETSI][102] = 127,
- [2][0][RTW89_FCC][104] = 8,
- [2][0][RTW89_ETSI][104] = 127,
- [2][0][RTW89_FCC][105] = 8,
- [2][0][RTW89_ETSI][105] = 127,
- [2][0][RTW89_FCC][107] = 10,
- [2][0][RTW89_ETSI][107] = 127,
- [2][0][RTW89_FCC][109] = 12,
- [2][0][RTW89_ETSI][109] = 127,
- [2][0][RTW89_FCC][111] = 127,
- [2][0][RTW89_ETSI][111] = 127,
- [2][0][RTW89_FCC][113] = 127,
- [2][0][RTW89_ETSI][113] = 127,
- [2][0][RTW89_FCC][115] = 127,
- [2][0][RTW89_ETSI][115] = 127,
- [2][0][RTW89_FCC][117] = 127,
- [2][0][RTW89_ETSI][117] = 127,
- [2][0][RTW89_FCC][119] = 127,
- [2][0][RTW89_ETSI][119] = 127,
- [2][1][RTW89_FCC][0] = -16,
- [2][1][RTW89_ETSI][0] = 44,
- [2][1][RTW89_FCC][2] = -16,
- [2][1][RTW89_ETSI][2] = 44,
- [2][1][RTW89_FCC][4] = -16,
- [2][1][RTW89_ETSI][4] = 44,
- [2][1][RTW89_FCC][6] = -16,
- [2][1][RTW89_ETSI][6] = 44,
- [2][1][RTW89_FCC][8] = -16,
- [2][1][RTW89_ETSI][8] = 44,
- [2][1][RTW89_FCC][10] = -16,
- [2][1][RTW89_ETSI][10] = 44,
- [2][1][RTW89_FCC][12] = -16,
- [2][1][RTW89_ETSI][12] = 44,
- [2][1][RTW89_FCC][14] = -16,
- [2][1][RTW89_ETSI][14] = 44,
- [2][1][RTW89_FCC][15] = -16,
- [2][1][RTW89_ETSI][15] = 44,
- [2][1][RTW89_FCC][17] = -16,
- [2][1][RTW89_ETSI][17] = 44,
- [2][1][RTW89_FCC][19] = -16,
- [2][1][RTW89_ETSI][19] = 44,
- [2][1][RTW89_FCC][21] = -16,
- [2][1][RTW89_ETSI][21] = 44,
- [2][1][RTW89_FCC][23] = -16,
- [2][1][RTW89_ETSI][23] = 44,
- [2][1][RTW89_FCC][25] = -16,
- [2][1][RTW89_ETSI][25] = 44,
- [2][1][RTW89_FCC][27] = -16,
- [2][1][RTW89_ETSI][27] = 44,
- [2][1][RTW89_FCC][29] = -16,
- [2][1][RTW89_ETSI][29] = 44,
- [2][1][RTW89_FCC][30] = -16,
- [2][1][RTW89_ETSI][30] = 44,
- [2][1][RTW89_FCC][32] = -16,
- [2][1][RTW89_ETSI][32] = 44,
- [2][1][RTW89_FCC][34] = -16,
- [2][1][RTW89_ETSI][34] = 44,
- [2][1][RTW89_FCC][36] = -16,
- [2][1][RTW89_ETSI][36] = 44,
- [2][1][RTW89_FCC][38] = -16,
- [2][1][RTW89_ETSI][38] = 44,
- [2][1][RTW89_FCC][40] = -16,
- [2][1][RTW89_ETSI][40] = 44,
- [2][1][RTW89_FCC][42] = -16,
- [2][1][RTW89_ETSI][42] = 44,
- [2][1][RTW89_FCC][44] = -16,
- [2][1][RTW89_ETSI][44] = 44,
- [2][1][RTW89_FCC][45] = -16,
- [2][1][RTW89_ETSI][45] = 127,
- [2][1][RTW89_FCC][47] = -16,
- [2][1][RTW89_ETSI][47] = 127,
- [2][1][RTW89_FCC][49] = -16,
- [2][1][RTW89_ETSI][49] = 127,
- [2][1][RTW89_FCC][51] = -16,
- [2][1][RTW89_ETSI][51] = 127,
- [2][1][RTW89_FCC][53] = -16,
- [2][1][RTW89_ETSI][53] = 127,
- [2][1][RTW89_FCC][55] = -16,
- [2][1][RTW89_ETSI][55] = 127,
- [2][1][RTW89_FCC][57] = -16,
- [2][1][RTW89_ETSI][57] = 127,
- [2][1][RTW89_FCC][59] = -16,
- [2][1][RTW89_ETSI][59] = 127,
- [2][1][RTW89_FCC][60] = -16,
- [2][1][RTW89_ETSI][60] = 127,
- [2][1][RTW89_FCC][62] = -16,
- [2][1][RTW89_ETSI][62] = 127,
- [2][1][RTW89_FCC][64] = -16,
- [2][1][RTW89_ETSI][64] = 127,
- [2][1][RTW89_FCC][66] = -16,
- [2][1][RTW89_ETSI][66] = 127,
- [2][1][RTW89_FCC][68] = -16,
- [2][1][RTW89_ETSI][68] = 127,
- [2][1][RTW89_FCC][70] = -16,
- [2][1][RTW89_ETSI][70] = 127,
- [2][1][RTW89_FCC][72] = -16,
- [2][1][RTW89_ETSI][72] = 127,
- [2][1][RTW89_FCC][74] = -16,
- [2][1][RTW89_ETSI][74] = 127,
- [2][1][RTW89_FCC][75] = -16,
- [2][1][RTW89_ETSI][75] = 127,
- [2][1][RTW89_FCC][77] = -16,
- [2][1][RTW89_ETSI][77] = 127,
- [2][1][RTW89_FCC][79] = -16,
- [2][1][RTW89_ETSI][79] = 127,
- [2][1][RTW89_FCC][81] = -16,
- [2][1][RTW89_ETSI][81] = 127,
- [2][1][RTW89_FCC][83] = -16,
- [2][1][RTW89_ETSI][83] = 127,
- [2][1][RTW89_FCC][85] = -18,
- [2][1][RTW89_ETSI][85] = 127,
- [2][1][RTW89_FCC][87] = -16,
- [2][1][RTW89_ETSI][87] = 127,
- [2][1][RTW89_FCC][89] = -16,
- [2][1][RTW89_ETSI][89] = 127,
- [2][1][RTW89_FCC][90] = -16,
- [2][1][RTW89_ETSI][90] = 127,
- [2][1][RTW89_FCC][92] = -16,
- [2][1][RTW89_ETSI][92] = 127,
- [2][1][RTW89_FCC][94] = -16,
- [2][1][RTW89_ETSI][94] = 127,
- [2][1][RTW89_FCC][96] = -16,
- [2][1][RTW89_ETSI][96] = 127,
- [2][1][RTW89_FCC][98] = -16,
- [2][1][RTW89_ETSI][98] = 127,
- [2][1][RTW89_FCC][100] = -16,
- [2][1][RTW89_ETSI][100] = 127,
- [2][1][RTW89_FCC][102] = -16,
- [2][1][RTW89_ETSI][102] = 127,
- [2][1][RTW89_FCC][104] = -16,
- [2][1][RTW89_ETSI][104] = 127,
- [2][1][RTW89_FCC][105] = -16,
- [2][1][RTW89_ETSI][105] = 127,
- [2][1][RTW89_FCC][107] = -12,
- [2][1][RTW89_ETSI][107] = 127,
- [2][1][RTW89_FCC][109] = -10,
- [2][1][RTW89_ETSI][109] = 127,
- [2][1][RTW89_FCC][111] = 127,
- [2][1][RTW89_ETSI][111] = 127,
- [2][1][RTW89_FCC][113] = 127,
- [2][1][RTW89_ETSI][113] = 127,
- [2][1][RTW89_FCC][115] = 127,
- [2][1][RTW89_ETSI][115] = 127,
- [2][1][RTW89_FCC][117] = 127,
- [2][1][RTW89_ETSI][117] = 127,
- [2][1][RTW89_FCC][119] = 127,
- [2][1][RTW89_ETSI][119] = 127,
+ [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
+ [RTW89_6G_CH_NUM] = {
+ [0][0][RTW89_WW][0][0] = -16,
+ [0][0][RTW89_WW][1][0] = -16,
+ [0][0][RTW89_WW][2][0] = 44,
+ [0][0][RTW89_WW][0][2] = -18,
+ [0][0][RTW89_WW][1][2] = -18,
+ [0][0][RTW89_WW][2][2] = 44,
+ [0][0][RTW89_WW][0][4] = -18,
+ [0][0][RTW89_WW][1][4] = -18,
+ [0][0][RTW89_WW][2][4] = 44,
+ [0][0][RTW89_WW][0][6] = -18,
+ [0][0][RTW89_WW][1][6] = -18,
+ [0][0][RTW89_WW][2][6] = 44,
+ [0][0][RTW89_WW][0][8] = -18,
+ [0][0][RTW89_WW][1][8] = -18,
+ [0][0][RTW89_WW][2][8] = 44,
+ [0][0][RTW89_WW][0][10] = -18,
+ [0][0][RTW89_WW][1][10] = -18,
+ [0][0][RTW89_WW][2][10] = 44,
+ [0][0][RTW89_WW][0][12] = -18,
+ [0][0][RTW89_WW][1][12] = -18,
+ [0][0][RTW89_WW][2][12] = 44,
+ [0][0][RTW89_WW][0][14] = -18,
+ [0][0][RTW89_WW][1][14] = -18,
+ [0][0][RTW89_WW][2][14] = 44,
+ [0][0][RTW89_WW][0][15] = -18,
+ [0][0][RTW89_WW][1][15] = -18,
+ [0][0][RTW89_WW][2][15] = 44,
+ [0][0][RTW89_WW][0][17] = -18,
+ [0][0][RTW89_WW][1][17] = -18,
+ [0][0][RTW89_WW][2][17] = 44,
+ [0][0][RTW89_WW][0][19] = -18,
+ [0][0][RTW89_WW][1][19] = -18,
+ [0][0][RTW89_WW][2][19] = 44,
+ [0][0][RTW89_WW][0][21] = -18,
+ [0][0][RTW89_WW][1][21] = -18,
+ [0][0][RTW89_WW][2][21] = 44,
+ [0][0][RTW89_WW][0][23] = -18,
+ [0][0][RTW89_WW][1][23] = -18,
+ [0][0][RTW89_WW][2][23] = 54,
+ [0][0][RTW89_WW][0][25] = -18,
+ [0][0][RTW89_WW][1][25] = -18,
+ [0][0][RTW89_WW][2][25] = 54,
+ [0][0][RTW89_WW][0][27] = -18,
+ [0][0][RTW89_WW][1][27] = -18,
+ [0][0][RTW89_WW][2][27] = 54,
+ [0][0][RTW89_WW][0][29] = -18,
+ [0][0][RTW89_WW][1][29] = -18,
+ [0][0][RTW89_WW][2][29] = 54,
+ [0][0][RTW89_WW][0][30] = -18,
+ [0][0][RTW89_WW][1][30] = -18,
+ [0][0][RTW89_WW][2][30] = 54,
+ [0][0][RTW89_WW][0][32] = -18,
+ [0][0][RTW89_WW][1][32] = -18,
+ [0][0][RTW89_WW][2][32] = 54,
+ [0][0][RTW89_WW][0][34] = -18,
+ [0][0][RTW89_WW][1][34] = -18,
+ [0][0][RTW89_WW][2][34] = 54,
+ [0][0][RTW89_WW][0][36] = -18,
+ [0][0][RTW89_WW][1][36] = -18,
+ [0][0][RTW89_WW][2][36] = 54,
+ [0][0][RTW89_WW][0][38] = -18,
+ [0][0][RTW89_WW][1][38] = -18,
+ [0][0][RTW89_WW][2][38] = 54,
+ [0][0][RTW89_WW][0][40] = -18,
+ [0][0][RTW89_WW][1][40] = -18,
+ [0][0][RTW89_WW][2][40] = 54,
+ [0][0][RTW89_WW][0][42] = -18,
+ [0][0][RTW89_WW][1][42] = -18,
+ [0][0][RTW89_WW][2][42] = 54,
+ [0][0][RTW89_WW][0][44] = -16,
+ [0][0][RTW89_WW][1][44] = -16,
+ [0][0][RTW89_WW][2][44] = 56,
+ [0][0][RTW89_WW][0][45] = -16,
+ [0][0][RTW89_WW][1][45] = -16,
+ [0][0][RTW89_WW][2][45] = 0,
+ [0][0][RTW89_WW][0][47] = -18,
+ [0][0][RTW89_WW][1][47] = -18,
+ [0][0][RTW89_WW][2][47] = 0,
+ [0][0][RTW89_WW][0][49] = -18,
+ [0][0][RTW89_WW][1][49] = -18,
+ [0][0][RTW89_WW][2][49] = 0,
+ [0][0][RTW89_WW][0][51] = -18,
+ [0][0][RTW89_WW][1][51] = -18,
+ [0][0][RTW89_WW][2][51] = 0,
+ [0][0][RTW89_WW][0][53] = -16,
+ [0][0][RTW89_WW][1][53] = -16,
+ [0][0][RTW89_WW][2][53] = 0,
+ [0][0][RTW89_WW][0][55] = -18,
+ [0][0][RTW89_WW][1][55] = -18,
+ [0][0][RTW89_WW][2][55] = 56,
+ [0][0][RTW89_WW][0][57] = -18,
+ [0][0][RTW89_WW][1][57] = -18,
+ [0][0][RTW89_WW][2][57] = 56,
+ [0][0][RTW89_WW][0][59] = -18,
+ [0][0][RTW89_WW][1][59] = -18,
+ [0][0][RTW89_WW][2][59] = 56,
+ [0][0][RTW89_WW][0][60] = -18,
+ [0][0][RTW89_WW][1][60] = -18,
+ [0][0][RTW89_WW][2][60] = 56,
+ [0][0][RTW89_WW][0][62] = -18,
+ [0][0][RTW89_WW][1][62] = -18,
+ [0][0][RTW89_WW][2][62] = 56,
+ [0][0][RTW89_WW][0][64] = -18,
+ [0][0][RTW89_WW][1][64] = -18,
+ [0][0][RTW89_WW][2][64] = 56,
+ [0][0][RTW89_WW][0][66] = -18,
+ [0][0][RTW89_WW][1][66] = -18,
+ [0][0][RTW89_WW][2][66] = 56,
+ [0][0][RTW89_WW][0][68] = -18,
+ [0][0][RTW89_WW][1][68] = -18,
+ [0][0][RTW89_WW][2][68] = 56,
+ [0][0][RTW89_WW][0][70] = -16,
+ [0][0][RTW89_WW][1][70] = -16,
+ [0][0][RTW89_WW][2][70] = 56,
+ [0][0][RTW89_WW][0][72] = -18,
+ [0][0][RTW89_WW][1][72] = -18,
+ [0][0][RTW89_WW][2][72] = 56,
+ [0][0][RTW89_WW][0][74] = -18,
+ [0][0][RTW89_WW][1][74] = -18,
+ [0][0][RTW89_WW][2][74] = 56,
+ [0][0][RTW89_WW][0][75] = -18,
+ [0][0][RTW89_WW][1][75] = -18,
+ [0][0][RTW89_WW][2][75] = 56,
+ [0][0][RTW89_WW][0][77] = -18,
+ [0][0][RTW89_WW][1][77] = -18,
+ [0][0][RTW89_WW][2][77] = 56,
+ [0][0][RTW89_WW][0][79] = -18,
+ [0][0][RTW89_WW][1][79] = -18,
+ [0][0][RTW89_WW][2][79] = 56,
+ [0][0][RTW89_WW][0][81] = -18,
+ [0][0][RTW89_WW][1][81] = -18,
+ [0][0][RTW89_WW][2][81] = 56,
+ [0][0][RTW89_WW][0][83] = -18,
+ [0][0][RTW89_WW][1][83] = -18,
+ [0][0][RTW89_WW][2][83] = 56,
+ [0][0][RTW89_WW][0][85] = -18,
+ [0][0][RTW89_WW][1][85] = -18,
+ [0][0][RTW89_WW][2][85] = 56,
+ [0][0][RTW89_WW][0][87] = -16,
+ [0][0][RTW89_WW][1][87] = -16,
+ [0][0][RTW89_WW][2][87] = 0,
+ [0][0][RTW89_WW][0][89] = -16,
+ [0][0][RTW89_WW][1][89] = -16,
+ [0][0][RTW89_WW][2][89] = 0,
+ [0][0][RTW89_WW][0][90] = -16,
+ [0][0][RTW89_WW][1][90] = -16,
+ [0][0][RTW89_WW][2][90] = 0,
+ [0][0][RTW89_WW][0][92] = -16,
+ [0][0][RTW89_WW][1][92] = -16,
+ [0][0][RTW89_WW][2][92] = 0,
+ [0][0][RTW89_WW][0][94] = -16,
+ [0][0][RTW89_WW][1][94] = -16,
+ [0][0][RTW89_WW][2][94] = 0,
+ [0][0][RTW89_WW][0][96] = -16,
+ [0][0][RTW89_WW][1][96] = -16,
+ [0][0][RTW89_WW][2][96] = 0,
+ [0][0][RTW89_WW][0][98] = -16,
+ [0][0][RTW89_WW][1][98] = -16,
+ [0][0][RTW89_WW][2][98] = 0,
+ [0][0][RTW89_WW][0][100] = -16,
+ [0][0][RTW89_WW][1][100] = -16,
+ [0][0][RTW89_WW][2][100] = 0,
+ [0][0][RTW89_WW][0][102] = -16,
+ [0][0][RTW89_WW][1][102] = -16,
+ [0][0][RTW89_WW][2][102] = 0,
+ [0][0][RTW89_WW][0][104] = -16,
+ [0][0][RTW89_WW][1][104] = -16,
+ [0][0][RTW89_WW][2][104] = 0,
+ [0][0][RTW89_WW][0][105] = -16,
+ [0][0][RTW89_WW][1][105] = -16,
+ [0][0][RTW89_WW][2][105] = 0,
+ [0][0][RTW89_WW][0][107] = -12,
+ [0][0][RTW89_WW][1][107] = -12,
+ [0][0][RTW89_WW][2][107] = 0,
+ [0][0][RTW89_WW][0][109] = -12,
+ [0][0][RTW89_WW][1][109] = -12,
+ [0][0][RTW89_WW][2][109] = 0,
+ [0][0][RTW89_WW][0][111] = 0,
+ [0][0][RTW89_WW][1][111] = 0,
+ [0][0][RTW89_WW][2][111] = 0,
+ [0][0][RTW89_WW][0][113] = 0,
+ [0][0][RTW89_WW][1][113] = 0,
+ [0][0][RTW89_WW][2][113] = 0,
+ [0][0][RTW89_WW][0][115] = 0,
+ [0][0][RTW89_WW][1][115] = 0,
+ [0][0][RTW89_WW][2][115] = 0,
+ [0][0][RTW89_WW][0][117] = 0,
+ [0][0][RTW89_WW][1][117] = 0,
+ [0][0][RTW89_WW][2][117] = 0,
+ [0][0][RTW89_WW][0][119] = 0,
+ [0][0][RTW89_WW][1][119] = 0,
+ [0][0][RTW89_WW][2][119] = 0,
+ [0][1][RTW89_WW][0][0] = -40,
+ [0][1][RTW89_WW][1][0] = -40,
+ [0][1][RTW89_WW][2][0] = 32,
+ [0][1][RTW89_WW][0][2] = -40,
+ [0][1][RTW89_WW][1][2] = -40,
+ [0][1][RTW89_WW][2][2] = 32,
+ [0][1][RTW89_WW][0][4] = -40,
+ [0][1][RTW89_WW][1][4] = -40,
+ [0][1][RTW89_WW][2][4] = 32,
+ [0][1][RTW89_WW][0][6] = -40,
+ [0][1][RTW89_WW][1][6] = -40,
+ [0][1][RTW89_WW][2][6] = 32,
+ [0][1][RTW89_WW][0][8] = -40,
+ [0][1][RTW89_WW][1][8] = -40,
+ [0][1][RTW89_WW][2][8] = 32,
+ [0][1][RTW89_WW][0][10] = -40,
+ [0][1][RTW89_WW][1][10] = -40,
+ [0][1][RTW89_WW][2][10] = 32,
+ [0][1][RTW89_WW][0][12] = -40,
+ [0][1][RTW89_WW][1][12] = -40,
+ [0][1][RTW89_WW][2][12] = 32,
+ [0][1][RTW89_WW][0][14] = -40,
+ [0][1][RTW89_WW][1][14] = -40,
+ [0][1][RTW89_WW][2][14] = 32,
+ [0][1][RTW89_WW][0][15] = -40,
+ [0][1][RTW89_WW][1][15] = -40,
+ [0][1][RTW89_WW][2][15] = 32,
+ [0][1][RTW89_WW][0][17] = -40,
+ [0][1][RTW89_WW][1][17] = -40,
+ [0][1][RTW89_WW][2][17] = 32,
+ [0][1][RTW89_WW][0][19] = -40,
+ [0][1][RTW89_WW][1][19] = -40,
+ [0][1][RTW89_WW][2][19] = 32,
+ [0][1][RTW89_WW][0][21] = -40,
+ [0][1][RTW89_WW][1][21] = -40,
+ [0][1][RTW89_WW][2][21] = 32,
+ [0][1][RTW89_WW][0][23] = -40,
+ [0][1][RTW89_WW][1][23] = -40,
+ [0][1][RTW89_WW][2][23] = 32,
+ [0][1][RTW89_WW][0][25] = -40,
+ [0][1][RTW89_WW][1][25] = -40,
+ [0][1][RTW89_WW][2][25] = 32,
+ [0][1][RTW89_WW][0][27] = -40,
+ [0][1][RTW89_WW][1][27] = -40,
+ [0][1][RTW89_WW][2][27] = 32,
+ [0][1][RTW89_WW][0][29] = -40,
+ [0][1][RTW89_WW][1][29] = -40,
+ [0][1][RTW89_WW][2][29] = 32,
+ [0][1][RTW89_WW][0][30] = -40,
+ [0][1][RTW89_WW][1][30] = -40,
+ [0][1][RTW89_WW][2][30] = 32,
+ [0][1][RTW89_WW][0][32] = -40,
+ [0][1][RTW89_WW][1][32] = -40,
+ [0][1][RTW89_WW][2][32] = 32,
+ [0][1][RTW89_WW][0][34] = -40,
+ [0][1][RTW89_WW][1][34] = -40,
+ [0][1][RTW89_WW][2][34] = 32,
+ [0][1][RTW89_WW][0][36] = -40,
+ [0][1][RTW89_WW][1][36] = -40,
+ [0][1][RTW89_WW][2][36] = 32,
+ [0][1][RTW89_WW][0][38] = -40,
+ [0][1][RTW89_WW][1][38] = -40,
+ [0][1][RTW89_WW][2][38] = 32,
+ [0][1][RTW89_WW][0][40] = -40,
+ [0][1][RTW89_WW][1][40] = -40,
+ [0][1][RTW89_WW][2][40] = 32,
+ [0][1][RTW89_WW][0][42] = -40,
+ [0][1][RTW89_WW][1][42] = -40,
+ [0][1][RTW89_WW][2][42] = 32,
+ [0][1][RTW89_WW][0][44] = -40,
+ [0][1][RTW89_WW][1][44] = -40,
+ [0][1][RTW89_WW][2][44] = 32,
+ [0][1][RTW89_WW][0][45] = -40,
+ [0][1][RTW89_WW][1][45] = -40,
+ [0][1][RTW89_WW][2][45] = 0,
+ [0][1][RTW89_WW][0][47] = -40,
+ [0][1][RTW89_WW][1][47] = -40,
+ [0][1][RTW89_WW][2][47] = 0,
+ [0][1][RTW89_WW][0][49] = -40,
+ [0][1][RTW89_WW][1][49] = -40,
+ [0][1][RTW89_WW][2][49] = 0,
+ [0][1][RTW89_WW][0][51] = -40,
+ [0][1][RTW89_WW][1][51] = -40,
+ [0][1][RTW89_WW][2][51] = 0,
+ [0][1][RTW89_WW][0][53] = -40,
+ [0][1][RTW89_WW][1][53] = -40,
+ [0][1][RTW89_WW][2][53] = 0,
+ [0][1][RTW89_WW][0][55] = -40,
+ [0][1][RTW89_WW][1][55] = -40,
+ [0][1][RTW89_WW][2][55] = 30,
+ [0][1][RTW89_WW][0][57] = -40,
+ [0][1][RTW89_WW][1][57] = -40,
+ [0][1][RTW89_WW][2][57] = 30,
+ [0][1][RTW89_WW][0][59] = -40,
+ [0][1][RTW89_WW][1][59] = -40,
+ [0][1][RTW89_WW][2][59] = 30,
+ [0][1][RTW89_WW][0][60] = -40,
+ [0][1][RTW89_WW][1][60] = -40,
+ [0][1][RTW89_WW][2][60] = 30,
+ [0][1][RTW89_WW][0][62] = -40,
+ [0][1][RTW89_WW][1][62] = -40,
+ [0][1][RTW89_WW][2][62] = 30,
+ [0][1][RTW89_WW][0][64] = -40,
+ [0][1][RTW89_WW][1][64] = -40,
+ [0][1][RTW89_WW][2][64] = 30,
+ [0][1][RTW89_WW][0][66] = -40,
+ [0][1][RTW89_WW][1][66] = -40,
+ [0][1][RTW89_WW][2][66] = 30,
+ [0][1][RTW89_WW][0][68] = -40,
+ [0][1][RTW89_WW][1][68] = -40,
+ [0][1][RTW89_WW][2][68] = 30,
+ [0][1][RTW89_WW][0][70] = -38,
+ [0][1][RTW89_WW][1][70] = -38,
+ [0][1][RTW89_WW][2][70] = 30,
+ [0][1][RTW89_WW][0][72] = -38,
+ [0][1][RTW89_WW][1][72] = -38,
+ [0][1][RTW89_WW][2][72] = 30,
+ [0][1][RTW89_WW][0][74] = -38,
+ [0][1][RTW89_WW][1][74] = -38,
+ [0][1][RTW89_WW][2][74] = 30,
+ [0][1][RTW89_WW][0][75] = -38,
+ [0][1][RTW89_WW][1][75] = -38,
+ [0][1][RTW89_WW][2][75] = 30,
+ [0][1][RTW89_WW][0][77] = -38,
+ [0][1][RTW89_WW][1][77] = -38,
+ [0][1][RTW89_WW][2][77] = 30,
+ [0][1][RTW89_WW][0][79] = -38,
+ [0][1][RTW89_WW][1][79] = -38,
+ [0][1][RTW89_WW][2][79] = 30,
+ [0][1][RTW89_WW][0][81] = -38,
+ [0][1][RTW89_WW][1][81] = -38,
+ [0][1][RTW89_WW][2][81] = 30,
+ [0][1][RTW89_WW][0][83] = -38,
+ [0][1][RTW89_WW][1][83] = -38,
+ [0][1][RTW89_WW][2][83] = 30,
+ [0][1][RTW89_WW][0][85] = -38,
+ [0][1][RTW89_WW][1][85] = -38,
+ [0][1][RTW89_WW][2][85] = 30,
+ [0][1][RTW89_WW][0][87] = -40,
+ [0][1][RTW89_WW][1][87] = -40,
+ [0][1][RTW89_WW][2][87] = 0,
+ [0][1][RTW89_WW][0][89] = -38,
+ [0][1][RTW89_WW][1][89] = -38,
+ [0][1][RTW89_WW][2][89] = 0,
+ [0][1][RTW89_WW][0][90] = -38,
+ [0][1][RTW89_WW][1][90] = -38,
+ [0][1][RTW89_WW][2][90] = 0,
+ [0][1][RTW89_WW][0][92] = -38,
+ [0][1][RTW89_WW][1][92] = -38,
+ [0][1][RTW89_WW][2][92] = 0,
+ [0][1][RTW89_WW][0][94] = -38,
+ [0][1][RTW89_WW][1][94] = -38,
+ [0][1][RTW89_WW][2][94] = 0,
+ [0][1][RTW89_WW][0][96] = -38,
+ [0][1][RTW89_WW][1][96] = -38,
+ [0][1][RTW89_WW][2][96] = 0,
+ [0][1][RTW89_WW][0][98] = -38,
+ [0][1][RTW89_WW][1][98] = -38,
+ [0][1][RTW89_WW][2][98] = 0,
+ [0][1][RTW89_WW][0][100] = -38,
+ [0][1][RTW89_WW][1][100] = -38,
+ [0][1][RTW89_WW][2][100] = 0,
+ [0][1][RTW89_WW][0][102] = -38,
+ [0][1][RTW89_WW][1][102] = -38,
+ [0][1][RTW89_WW][2][102] = 0,
+ [0][1][RTW89_WW][0][104] = -38,
+ [0][1][RTW89_WW][1][104] = -38,
+ [0][1][RTW89_WW][2][104] = 0,
+ [0][1][RTW89_WW][0][105] = -38,
+ [0][1][RTW89_WW][1][105] = -38,
+ [0][1][RTW89_WW][2][105] = 0,
+ [0][1][RTW89_WW][0][107] = -34,
+ [0][1][RTW89_WW][1][107] = -34,
+ [0][1][RTW89_WW][2][107] = 0,
+ [0][1][RTW89_WW][0][109] = -34,
+ [0][1][RTW89_WW][1][109] = -34,
+ [0][1][RTW89_WW][2][109] = 0,
+ [0][1][RTW89_WW][0][111] = 0,
+ [0][1][RTW89_WW][1][111] = 0,
+ [0][1][RTW89_WW][2][111] = 0,
+ [0][1][RTW89_WW][0][113] = 0,
+ [0][1][RTW89_WW][1][113] = 0,
+ [0][1][RTW89_WW][2][113] = 0,
+ [0][1][RTW89_WW][0][115] = 0,
+ [0][1][RTW89_WW][1][115] = 0,
+ [0][1][RTW89_WW][2][115] = 0,
+ [0][1][RTW89_WW][0][117] = 0,
+ [0][1][RTW89_WW][1][117] = 0,
+ [0][1][RTW89_WW][2][117] = 0,
+ [0][1][RTW89_WW][0][119] = 0,
+ [0][1][RTW89_WW][1][119] = 0,
+ [0][1][RTW89_WW][2][119] = 0,
+ [1][0][RTW89_WW][0][0] = -4,
+ [1][0][RTW89_WW][1][0] = -4,
+ [1][0][RTW89_WW][2][0] = 52,
+ [1][0][RTW89_WW][0][2] = -4,
+ [1][0][RTW89_WW][1][2] = -4,
+ [1][0][RTW89_WW][2][2] = 52,
+ [1][0][RTW89_WW][0][4] = -4,
+ [1][0][RTW89_WW][1][4] = -4,
+ [1][0][RTW89_WW][2][4] = 52,
+ [1][0][RTW89_WW][0][6] = -4,
+ [1][0][RTW89_WW][1][6] = -4,
+ [1][0][RTW89_WW][2][6] = 52,
+ [1][0][RTW89_WW][0][8] = -4,
+ [1][0][RTW89_WW][1][8] = -4,
+ [1][0][RTW89_WW][2][8] = 52,
+ [1][0][RTW89_WW][0][10] = -4,
+ [1][0][RTW89_WW][1][10] = -4,
+ [1][0][RTW89_WW][2][10] = 52,
+ [1][0][RTW89_WW][0][12] = -4,
+ [1][0][RTW89_WW][1][12] = -4,
+ [1][0][RTW89_WW][2][12] = 52,
+ [1][0][RTW89_WW][0][14] = -4,
+ [1][0][RTW89_WW][1][14] = -4,
+ [1][0][RTW89_WW][2][14] = 52,
+ [1][0][RTW89_WW][0][15] = -4,
+ [1][0][RTW89_WW][1][15] = -4,
+ [1][0][RTW89_WW][2][15] = 52,
+ [1][0][RTW89_WW][0][17] = -4,
+ [1][0][RTW89_WW][1][17] = -4,
+ [1][0][RTW89_WW][2][17] = 52,
+ [1][0][RTW89_WW][0][19] = -4,
+ [1][0][RTW89_WW][1][19] = -4,
+ [1][0][RTW89_WW][2][19] = 52,
+ [1][0][RTW89_WW][0][21] = -4,
+ [1][0][RTW89_WW][1][21] = -4,
+ [1][0][RTW89_WW][2][21] = 52,
+ [1][0][RTW89_WW][0][23] = -4,
+ [1][0][RTW89_WW][1][23] = -4,
+ [1][0][RTW89_WW][2][23] = 66,
+ [1][0][RTW89_WW][0][25] = -4,
+ [1][0][RTW89_WW][1][25] = -4,
+ [1][0][RTW89_WW][2][25] = 66,
+ [1][0][RTW89_WW][0][27] = -4,
+ [1][0][RTW89_WW][1][27] = -4,
+ [1][0][RTW89_WW][2][27] = 66,
+ [1][0][RTW89_WW][0][29] = -4,
+ [1][0][RTW89_WW][1][29] = -4,
+ [1][0][RTW89_WW][2][29] = 66,
+ [1][0][RTW89_WW][0][30] = -4,
+ [1][0][RTW89_WW][1][30] = -4,
+ [1][0][RTW89_WW][2][30] = 66,
+ [1][0][RTW89_WW][0][32] = -4,
+ [1][0][RTW89_WW][1][32] = -4,
+ [1][0][RTW89_WW][2][32] = 66,
+ [1][0][RTW89_WW][0][34] = -4,
+ [1][0][RTW89_WW][1][34] = -4,
+ [1][0][RTW89_WW][2][34] = 66,
+ [1][0][RTW89_WW][0][36] = -4,
+ [1][0][RTW89_WW][1][36] = -4,
+ [1][0][RTW89_WW][2][36] = 66,
+ [1][0][RTW89_WW][0][38] = -4,
+ [1][0][RTW89_WW][1][38] = -4,
+ [1][0][RTW89_WW][2][38] = 66,
+ [1][0][RTW89_WW][0][40] = -4,
+ [1][0][RTW89_WW][1][40] = -4,
+ [1][0][RTW89_WW][2][40] = 66,
+ [1][0][RTW89_WW][0][42] = -4,
+ [1][0][RTW89_WW][1][42] = -4,
+ [1][0][RTW89_WW][2][42] = 66,
+ [1][0][RTW89_WW][0][44] = -4,
+ [1][0][RTW89_WW][1][44] = -4,
+ [1][0][RTW89_WW][2][44] = 66,
+ [1][0][RTW89_WW][0][45] = -4,
+ [1][0][RTW89_WW][1][45] = -4,
+ [1][0][RTW89_WW][2][45] = 0,
+ [1][0][RTW89_WW][0][47] = -4,
+ [1][0][RTW89_WW][1][47] = -4,
+ [1][0][RTW89_WW][2][47] = 0,
+ [1][0][RTW89_WW][0][49] = -4,
+ [1][0][RTW89_WW][1][49] = -4,
+ [1][0][RTW89_WW][2][49] = 0,
+ [1][0][RTW89_WW][0][51] = -4,
+ [1][0][RTW89_WW][1][51] = -4,
+ [1][0][RTW89_WW][2][51] = 0,
+ [1][0][RTW89_WW][0][53] = -4,
+ [1][0][RTW89_WW][1][53] = -4,
+ [1][0][RTW89_WW][2][53] = 0,
+ [1][0][RTW89_WW][0][55] = -4,
+ [1][0][RTW89_WW][1][55] = -4,
+ [1][0][RTW89_WW][2][55] = 68,
+ [1][0][RTW89_WW][0][57] = -4,
+ [1][0][RTW89_WW][1][57] = -4,
+ [1][0][RTW89_WW][2][57] = 68,
+ [1][0][RTW89_WW][0][59] = -4,
+ [1][0][RTW89_WW][1][59] = -4,
+ [1][0][RTW89_WW][2][59] = 68,
+ [1][0][RTW89_WW][0][60] = -4,
+ [1][0][RTW89_WW][1][60] = -4,
+ [1][0][RTW89_WW][2][60] = 68,
+ [1][0][RTW89_WW][0][62] = -4,
+ [1][0][RTW89_WW][1][62] = -4,
+ [1][0][RTW89_WW][2][62] = 68,
+ [1][0][RTW89_WW][0][64] = -4,
+ [1][0][RTW89_WW][1][64] = -4,
+ [1][0][RTW89_WW][2][64] = 68,
+ [1][0][RTW89_WW][0][66] = -4,
+ [1][0][RTW89_WW][1][66] = -4,
+ [1][0][RTW89_WW][2][66] = 68,
+ [1][0][RTW89_WW][0][68] = -4,
+ [1][0][RTW89_WW][1][68] = -4,
+ [1][0][RTW89_WW][2][68] = 68,
+ [1][0][RTW89_WW][0][70] = -4,
+ [1][0][RTW89_WW][1][70] = -4,
+ [1][0][RTW89_WW][2][70] = 68,
+ [1][0][RTW89_WW][0][72] = -4,
+ [1][0][RTW89_WW][1][72] = -4,
+ [1][0][RTW89_WW][2][72] = 68,
+ [1][0][RTW89_WW][0][74] = -4,
+ [1][0][RTW89_WW][1][74] = -4,
+ [1][0][RTW89_WW][2][74] = 68,
+ [1][0][RTW89_WW][0][75] = -4,
+ [1][0][RTW89_WW][1][75] = -4,
+ [1][0][RTW89_WW][2][75] = 68,
+ [1][0][RTW89_WW][0][77] = -4,
+ [1][0][RTW89_WW][1][77] = -4,
+ [1][0][RTW89_WW][2][77] = 68,
+ [1][0][RTW89_WW][0][79] = -4,
+ [1][0][RTW89_WW][1][79] = -4,
+ [1][0][RTW89_WW][2][79] = 68,
+ [1][0][RTW89_WW][0][81] = -4,
+ [1][0][RTW89_WW][1][81] = -4,
+ [1][0][RTW89_WW][2][81] = 68,
+ [1][0][RTW89_WW][0][83] = -4,
+ [1][0][RTW89_WW][1][83] = -4,
+ [1][0][RTW89_WW][2][83] = 68,
+ [1][0][RTW89_WW][0][85] = -4,
+ [1][0][RTW89_WW][1][85] = -4,
+ [1][0][RTW89_WW][2][85] = 68,
+ [1][0][RTW89_WW][0][87] = -4,
+ [1][0][RTW89_WW][1][87] = -4,
+ [1][0][RTW89_WW][2][87] = 0,
+ [1][0][RTW89_WW][0][89] = -4,
+ [1][0][RTW89_WW][1][89] = -4,
+ [1][0][RTW89_WW][2][89] = 0,
+ [1][0][RTW89_WW][0][90] = -4,
+ [1][0][RTW89_WW][1][90] = -4,
+ [1][0][RTW89_WW][2][90] = 0,
+ [1][0][RTW89_WW][0][92] = -4,
+ [1][0][RTW89_WW][1][92] = -4,
+ [1][0][RTW89_WW][2][92] = 0,
+ [1][0][RTW89_WW][0][94] = -4,
+ [1][0][RTW89_WW][1][94] = -4,
+ [1][0][RTW89_WW][2][94] = 0,
+ [1][0][RTW89_WW][0][96] = -4,
+ [1][0][RTW89_WW][1][96] = -4,
+ [1][0][RTW89_WW][2][96] = 0,
+ [1][0][RTW89_WW][0][98] = -4,
+ [1][0][RTW89_WW][1][98] = -4,
+ [1][0][RTW89_WW][2][98] = 0,
+ [1][0][RTW89_WW][0][100] = -4,
+ [1][0][RTW89_WW][1][100] = -4,
+ [1][0][RTW89_WW][2][100] = 0,
+ [1][0][RTW89_WW][0][102] = -4,
+ [1][0][RTW89_WW][1][102] = -4,
+ [1][0][RTW89_WW][2][102] = 0,
+ [1][0][RTW89_WW][0][104] = -4,
+ [1][0][RTW89_WW][1][104] = -4,
+ [1][0][RTW89_WW][2][104] = 0,
+ [1][0][RTW89_WW][0][105] = -4,
+ [1][0][RTW89_WW][1][105] = -4,
+ [1][0][RTW89_WW][2][105] = 0,
+ [1][0][RTW89_WW][0][107] = -2,
+ [1][0][RTW89_WW][1][107] = -2,
+ [1][0][RTW89_WW][2][107] = 0,
+ [1][0][RTW89_WW][0][109] = 2,
+ [1][0][RTW89_WW][1][109] = 2,
+ [1][0][RTW89_WW][2][109] = 0,
+ [1][0][RTW89_WW][0][111] = 0,
+ [1][0][RTW89_WW][1][111] = 0,
+ [1][0][RTW89_WW][2][111] = 0,
+ [1][0][RTW89_WW][0][113] = 0,
+ [1][0][RTW89_WW][1][113] = 0,
+ [1][0][RTW89_WW][2][113] = 0,
+ [1][0][RTW89_WW][0][115] = 0,
+ [1][0][RTW89_WW][1][115] = 0,
+ [1][0][RTW89_WW][2][115] = 0,
+ [1][0][RTW89_WW][0][117] = 0,
+ [1][0][RTW89_WW][1][117] = 0,
+ [1][0][RTW89_WW][2][117] = 0,
+ [1][0][RTW89_WW][0][119] = 0,
+ [1][0][RTW89_WW][1][119] = 0,
+ [1][0][RTW89_WW][2][119] = 0,
+ [1][1][RTW89_WW][0][0] = -26,
+ [1][1][RTW89_WW][1][0] = -26,
+ [1][1][RTW89_WW][2][0] = 44,
+ [1][1][RTW89_WW][0][2] = -28,
+ [1][1][RTW89_WW][1][2] = -28,
+ [1][1][RTW89_WW][2][2] = 44,
+ [1][1][RTW89_WW][0][4] = -28,
+ [1][1][RTW89_WW][1][4] = -28,
+ [1][1][RTW89_WW][2][4] = 44,
+ [1][1][RTW89_WW][0][6] = -28,
+ [1][1][RTW89_WW][1][6] = -28,
+ [1][1][RTW89_WW][2][6] = 44,
+ [1][1][RTW89_WW][0][8] = -28,
+ [1][1][RTW89_WW][1][8] = -28,
+ [1][1][RTW89_WW][2][8] = 44,
+ [1][1][RTW89_WW][0][10] = -28,
+ [1][1][RTW89_WW][1][10] = -28,
+ [1][1][RTW89_WW][2][10] = 44,
+ [1][1][RTW89_WW][0][12] = -28,
+ [1][1][RTW89_WW][1][12] = -28,
+ [1][1][RTW89_WW][2][12] = 44,
+ [1][1][RTW89_WW][0][14] = -28,
+ [1][1][RTW89_WW][1][14] = -28,
+ [1][1][RTW89_WW][2][14] = 44,
+ [1][1][RTW89_WW][0][15] = -28,
+ [1][1][RTW89_WW][1][15] = -28,
+ [1][1][RTW89_WW][2][15] = 44,
+ [1][1][RTW89_WW][0][17] = -28,
+ [1][1][RTW89_WW][1][17] = -28,
+ [1][1][RTW89_WW][2][17] = 44,
+ [1][1][RTW89_WW][0][19] = -28,
+ [1][1][RTW89_WW][1][19] = -28,
+ [1][1][RTW89_WW][2][19] = 44,
+ [1][1][RTW89_WW][0][21] = -28,
+ [1][1][RTW89_WW][1][21] = -28,
+ [1][1][RTW89_WW][2][21] = 44,
+ [1][1][RTW89_WW][0][23] = -28,
+ [1][1][RTW89_WW][1][23] = -28,
+ [1][1][RTW89_WW][2][23] = 44,
+ [1][1][RTW89_WW][0][25] = -28,
+ [1][1][RTW89_WW][1][25] = -28,
+ [1][1][RTW89_WW][2][25] = 44,
+ [1][1][RTW89_WW][0][27] = -28,
+ [1][1][RTW89_WW][1][27] = -28,
+ [1][1][RTW89_WW][2][27] = 44,
+ [1][1][RTW89_WW][0][29] = -28,
+ [1][1][RTW89_WW][1][29] = -28,
+ [1][1][RTW89_WW][2][29] = 44,
+ [1][1][RTW89_WW][0][30] = -28,
+ [1][1][RTW89_WW][1][30] = -28,
+ [1][1][RTW89_WW][2][30] = 44,
+ [1][1][RTW89_WW][0][32] = -28,
+ [1][1][RTW89_WW][1][32] = -28,
+ [1][1][RTW89_WW][2][32] = 44,
+ [1][1][RTW89_WW][0][34] = -28,
+ [1][1][RTW89_WW][1][34] = -28,
+ [1][1][RTW89_WW][2][34] = 44,
+ [1][1][RTW89_WW][0][36] = -28,
+ [1][1][RTW89_WW][1][36] = -28,
+ [1][1][RTW89_WW][2][36] = 44,
+ [1][1][RTW89_WW][0][38] = -28,
+ [1][1][RTW89_WW][1][38] = -28,
+ [1][1][RTW89_WW][2][38] = 44,
+ [1][1][RTW89_WW][0][40] = -28,
+ [1][1][RTW89_WW][1][40] = -28,
+ [1][1][RTW89_WW][2][40] = 44,
+ [1][1][RTW89_WW][0][42] = -28,
+ [1][1][RTW89_WW][1][42] = -28,
+ [1][1][RTW89_WW][2][42] = 44,
+ [1][1][RTW89_WW][0][44] = -28,
+ [1][1][RTW89_WW][1][44] = -28,
+ [1][1][RTW89_WW][2][44] = 44,
+ [1][1][RTW89_WW][0][45] = -26,
+ [1][1][RTW89_WW][1][45] = -26,
+ [1][1][RTW89_WW][2][45] = 0,
+ [1][1][RTW89_WW][0][47] = -28,
+ [1][1][RTW89_WW][1][47] = -28,
+ [1][1][RTW89_WW][2][47] = 0,
+ [1][1][RTW89_WW][0][49] = -28,
+ [1][1][RTW89_WW][1][49] = -28,
+ [1][1][RTW89_WW][2][49] = 0,
+ [1][1][RTW89_WW][0][51] = -28,
+ [1][1][RTW89_WW][1][51] = -28,
+ [1][1][RTW89_WW][2][51] = 0,
+ [1][1][RTW89_WW][0][53] = -26,
+ [1][1][RTW89_WW][1][53] = -26,
+ [1][1][RTW89_WW][2][53] = 0,
+ [1][1][RTW89_WW][0][55] = -28,
+ [1][1][RTW89_WW][1][55] = -28,
+ [1][1][RTW89_WW][2][55] = 44,
+ [1][1][RTW89_WW][0][57] = -28,
+ [1][1][RTW89_WW][1][57] = -28,
+ [1][1][RTW89_WW][2][57] = 44,
+ [1][1][RTW89_WW][0][59] = -28,
+ [1][1][RTW89_WW][1][59] = -28,
+ [1][1][RTW89_WW][2][59] = 44,
+ [1][1][RTW89_WW][0][60] = -28,
+ [1][1][RTW89_WW][1][60] = -28,
+ [1][1][RTW89_WW][2][60] = 44,
+ [1][1][RTW89_WW][0][62] = -28,
+ [1][1][RTW89_WW][1][62] = -28,
+ [1][1][RTW89_WW][2][62] = 44,
+ [1][1][RTW89_WW][0][64] = -28,
+ [1][1][RTW89_WW][1][64] = -28,
+ [1][1][RTW89_WW][2][64] = 44,
+ [1][1][RTW89_WW][0][66] = -28,
+ [1][1][RTW89_WW][1][66] = -28,
+ [1][1][RTW89_WW][2][66] = 44,
+ [1][1][RTW89_WW][0][68] = -28,
+ [1][1][RTW89_WW][1][68] = -28,
+ [1][1][RTW89_WW][2][68] = 44,
+ [1][1][RTW89_WW][0][70] = -26,
+ [1][1][RTW89_WW][1][70] = -26,
+ [1][1][RTW89_WW][2][70] = 44,
+ [1][1][RTW89_WW][0][72] = -28,
+ [1][1][RTW89_WW][1][72] = -28,
+ [1][1][RTW89_WW][2][72] = 44,
+ [1][1][RTW89_WW][0][74] = -28,
+ [1][1][RTW89_WW][1][74] = -28,
+ [1][1][RTW89_WW][2][74] = 44,
+ [1][1][RTW89_WW][0][75] = -28,
+ [1][1][RTW89_WW][1][75] = -28,
+ [1][1][RTW89_WW][2][75] = 44,
+ [1][1][RTW89_WW][0][77] = -28,
+ [1][1][RTW89_WW][1][77] = -28,
+ [1][1][RTW89_WW][2][77] = 44,
+ [1][1][RTW89_WW][0][79] = -28,
+ [1][1][RTW89_WW][1][79] = -28,
+ [1][1][RTW89_WW][2][79] = 44,
+ [1][1][RTW89_WW][0][81] = -28,
+ [1][1][RTW89_WW][1][81] = -28,
+ [1][1][RTW89_WW][2][81] = 44,
+ [1][1][RTW89_WW][0][83] = -28,
+ [1][1][RTW89_WW][1][83] = -28,
+ [1][1][RTW89_WW][2][83] = 44,
+ [1][1][RTW89_WW][0][85] = -28,
+ [1][1][RTW89_WW][1][85] = -28,
+ [1][1][RTW89_WW][2][85] = 44,
+ [1][1][RTW89_WW][0][87] = -28,
+ [1][1][RTW89_WW][1][87] = -28,
+ [1][1][RTW89_WW][2][87] = 0,
+ [1][1][RTW89_WW][0][89] = -26,
+ [1][1][RTW89_WW][1][89] = -26,
+ [1][1][RTW89_WW][2][89] = 0,
+ [1][1][RTW89_WW][0][90] = -26,
+ [1][1][RTW89_WW][1][90] = -26,
+ [1][1][RTW89_WW][2][90] = 0,
+ [1][1][RTW89_WW][0][92] = -26,
+ [1][1][RTW89_WW][1][92] = -26,
+ [1][1][RTW89_WW][2][92] = 0,
+ [1][1][RTW89_WW][0][94] = -26,
+ [1][1][RTW89_WW][1][94] = -26,
+ [1][1][RTW89_WW][2][94] = 0,
+ [1][1][RTW89_WW][0][96] = -26,
+ [1][1][RTW89_WW][1][96] = -26,
+ [1][1][RTW89_WW][2][96] = 0,
+ [1][1][RTW89_WW][0][98] = -26,
+ [1][1][RTW89_WW][1][98] = -26,
+ [1][1][RTW89_WW][2][98] = 0,
+ [1][1][RTW89_WW][0][100] = -26,
+ [1][1][RTW89_WW][1][100] = -26,
+ [1][1][RTW89_WW][2][100] = 0,
+ [1][1][RTW89_WW][0][102] = -26,
+ [1][1][RTW89_WW][1][102] = -26,
+ [1][1][RTW89_WW][2][102] = 0,
+ [1][1][RTW89_WW][0][104] = -26,
+ [1][1][RTW89_WW][1][104] = -26,
+ [1][1][RTW89_WW][2][104] = 0,
+ [1][1][RTW89_WW][0][105] = -26,
+ [1][1][RTW89_WW][1][105] = -26,
+ [1][1][RTW89_WW][2][105] = 0,
+ [1][1][RTW89_WW][0][107] = -22,
+ [1][1][RTW89_WW][1][107] = -22,
+ [1][1][RTW89_WW][2][107] = 0,
+ [1][1][RTW89_WW][0][109] = -22,
+ [1][1][RTW89_WW][1][109] = -22,
+ [1][1][RTW89_WW][2][109] = 0,
+ [1][1][RTW89_WW][0][111] = 0,
+ [1][1][RTW89_WW][1][111] = 0,
+ [1][1][RTW89_WW][2][111] = 0,
+ [1][1][RTW89_WW][0][113] = 0,
+ [1][1][RTW89_WW][1][113] = 0,
+ [1][1][RTW89_WW][2][113] = 0,
+ [1][1][RTW89_WW][0][115] = 0,
+ [1][1][RTW89_WW][1][115] = 0,
+ [1][1][RTW89_WW][2][115] = 0,
+ [1][1][RTW89_WW][0][117] = 0,
+ [1][1][RTW89_WW][1][117] = 0,
+ [1][1][RTW89_WW][2][117] = 0,
+ [1][1][RTW89_WW][0][119] = 0,
+ [1][1][RTW89_WW][1][119] = 0,
+ [1][1][RTW89_WW][2][119] = 0,
+ [2][0][RTW89_WW][0][0] = -2,
+ [2][0][RTW89_WW][1][0] = -2,
+ [2][0][RTW89_WW][2][0] = 60,
+ [2][0][RTW89_WW][0][2] = -2,
+ [2][0][RTW89_WW][1][2] = -2,
+ [2][0][RTW89_WW][2][2] = 60,
+ [2][0][RTW89_WW][0][4] = -2,
+ [2][0][RTW89_WW][1][4] = -2,
+ [2][0][RTW89_WW][2][4] = 60,
+ [2][0][RTW89_WW][0][6] = -2,
+ [2][0][RTW89_WW][1][6] = -2,
+ [2][0][RTW89_WW][2][6] = 60,
+ [2][0][RTW89_WW][0][8] = -2,
+ [2][0][RTW89_WW][1][8] = -2,
+ [2][0][RTW89_WW][2][8] = 60,
+ [2][0][RTW89_WW][0][10] = -2,
+ [2][0][RTW89_WW][1][10] = -2,
+ [2][0][RTW89_WW][2][10] = 60,
+ [2][0][RTW89_WW][0][12] = -2,
+ [2][0][RTW89_WW][1][12] = -2,
+ [2][0][RTW89_WW][2][12] = 60,
+ [2][0][RTW89_WW][0][14] = -2,
+ [2][0][RTW89_WW][1][14] = -2,
+ [2][0][RTW89_WW][2][14] = 60,
+ [2][0][RTW89_WW][0][15] = -2,
+ [2][0][RTW89_WW][1][15] = -2,
+ [2][0][RTW89_WW][2][15] = 60,
+ [2][0][RTW89_WW][0][17] = -2,
+ [2][0][RTW89_WW][1][17] = -2,
+ [2][0][RTW89_WW][2][17] = 60,
+ [2][0][RTW89_WW][0][19] = -2,
+ [2][0][RTW89_WW][1][19] = -2,
+ [2][0][RTW89_WW][2][19] = 60,
+ [2][0][RTW89_WW][0][21] = -2,
+ [2][0][RTW89_WW][1][21] = -2,
+ [2][0][RTW89_WW][2][21] = 60,
+ [2][0][RTW89_WW][0][23] = -2,
+ [2][0][RTW89_WW][1][23] = -2,
+ [2][0][RTW89_WW][2][23] = 78,
+ [2][0][RTW89_WW][0][25] = -2,
+ [2][0][RTW89_WW][1][25] = -2,
+ [2][0][RTW89_WW][2][25] = 78,
+ [2][0][RTW89_WW][0][27] = -2,
+ [2][0][RTW89_WW][1][27] = -2,
+ [2][0][RTW89_WW][2][27] = 78,
+ [2][0][RTW89_WW][0][29] = -2,
+ [2][0][RTW89_WW][1][29] = -2,
+ [2][0][RTW89_WW][2][29] = 78,
+ [2][0][RTW89_WW][0][30] = -2,
+ [2][0][RTW89_WW][1][30] = -2,
+ [2][0][RTW89_WW][2][30] = 78,
+ [2][0][RTW89_WW][0][32] = -2,
+ [2][0][RTW89_WW][1][32] = -2,
+ [2][0][RTW89_WW][2][32] = 78,
+ [2][0][RTW89_WW][0][34] = -2,
+ [2][0][RTW89_WW][1][34] = -2,
+ [2][0][RTW89_WW][2][34] = 78,
+ [2][0][RTW89_WW][0][36] = -2,
+ [2][0][RTW89_WW][1][36] = -2,
+ [2][0][RTW89_WW][2][36] = 78,
+ [2][0][RTW89_WW][0][38] = -2,
+ [2][0][RTW89_WW][1][38] = -2,
+ [2][0][RTW89_WW][2][38] = 78,
+ [2][0][RTW89_WW][0][40] = -2,
+ [2][0][RTW89_WW][1][40] = -2,
+ [2][0][RTW89_WW][2][40] = 78,
+ [2][0][RTW89_WW][0][42] = -2,
+ [2][0][RTW89_WW][1][42] = -2,
+ [2][0][RTW89_WW][2][42] = 78,
+ [2][0][RTW89_WW][0][44] = -2,
+ [2][0][RTW89_WW][1][44] = -2,
+ [2][0][RTW89_WW][2][44] = 78,
+ [2][0][RTW89_WW][0][45] = -2,
+ [2][0][RTW89_WW][1][45] = -2,
+ [2][0][RTW89_WW][2][45] = 0,
+ [2][0][RTW89_WW][0][47] = -2,
+ [2][0][RTW89_WW][1][47] = -2,
+ [2][0][RTW89_WW][2][47] = 0,
+ [2][0][RTW89_WW][0][49] = -2,
+ [2][0][RTW89_WW][1][49] = -2,
+ [2][0][RTW89_WW][2][49] = 0,
+ [2][0][RTW89_WW][0][51] = -2,
+ [2][0][RTW89_WW][1][51] = -2,
+ [2][0][RTW89_WW][2][51] = 0,
+ [2][0][RTW89_WW][0][53] = -2,
+ [2][0][RTW89_WW][1][53] = -2,
+ [2][0][RTW89_WW][2][53] = 0,
+ [2][0][RTW89_WW][0][55] = -2,
+ [2][0][RTW89_WW][1][55] = -2,
+ [2][0][RTW89_WW][2][55] = 78,
+ [2][0][RTW89_WW][0][57] = -2,
+ [2][0][RTW89_WW][1][57] = -2,
+ [2][0][RTW89_WW][2][57] = 78,
+ [2][0][RTW89_WW][0][59] = -2,
+ [2][0][RTW89_WW][1][59] = -2,
+ [2][0][RTW89_WW][2][59] = 78,
+ [2][0][RTW89_WW][0][60] = -2,
+ [2][0][RTW89_WW][1][60] = -2,
+ [2][0][RTW89_WW][2][60] = 78,
+ [2][0][RTW89_WW][0][62] = -2,
+ [2][0][RTW89_WW][1][62] = -2,
+ [2][0][RTW89_WW][2][62] = 78,
+ [2][0][RTW89_WW][0][64] = -2,
+ [2][0][RTW89_WW][1][64] = -2,
+ [2][0][RTW89_WW][2][64] = 78,
+ [2][0][RTW89_WW][0][66] = -2,
+ [2][0][RTW89_WW][1][66] = -2,
+ [2][0][RTW89_WW][2][66] = 78,
+ [2][0][RTW89_WW][0][68] = -2,
+ [2][0][RTW89_WW][1][68] = -2,
+ [2][0][RTW89_WW][2][68] = 78,
+ [2][0][RTW89_WW][0][70] = -2,
+ [2][0][RTW89_WW][1][70] = -2,
+ [2][0][RTW89_WW][2][70] = 78,
+ [2][0][RTW89_WW][0][72] = -2,
+ [2][0][RTW89_WW][1][72] = -2,
+ [2][0][RTW89_WW][2][72] = 78,
+ [2][0][RTW89_WW][0][74] = -2,
+ [2][0][RTW89_WW][1][74] = -2,
+ [2][0][RTW89_WW][2][74] = 78,
+ [2][0][RTW89_WW][0][75] = -2,
+ [2][0][RTW89_WW][1][75] = -2,
+ [2][0][RTW89_WW][2][75] = 78,
+ [2][0][RTW89_WW][0][77] = -2,
+ [2][0][RTW89_WW][1][77] = -2,
+ [2][0][RTW89_WW][2][77] = 78,
+ [2][0][RTW89_WW][0][79] = -2,
+ [2][0][RTW89_WW][1][79] = -2,
+ [2][0][RTW89_WW][2][79] = 78,
+ [2][0][RTW89_WW][0][81] = -2,
+ [2][0][RTW89_WW][1][81] = -2,
+ [2][0][RTW89_WW][2][81] = 78,
+ [2][0][RTW89_WW][0][83] = -2,
+ [2][0][RTW89_WW][1][83] = -2,
+ [2][0][RTW89_WW][2][83] = 78,
+ [2][0][RTW89_WW][0][85] = -2,
+ [2][0][RTW89_WW][1][85] = -2,
+ [2][0][RTW89_WW][2][85] = 78,
+ [2][0][RTW89_WW][0][87] = -2,
+ [2][0][RTW89_WW][1][87] = -2,
+ [2][0][RTW89_WW][2][87] = 0,
+ [2][0][RTW89_WW][0][89] = -2,
+ [2][0][RTW89_WW][1][89] = -2,
+ [2][0][RTW89_WW][2][89] = 0,
+ [2][0][RTW89_WW][0][90] = -2,
+ [2][0][RTW89_WW][1][90] = -2,
+ [2][0][RTW89_WW][2][90] = 0,
+ [2][0][RTW89_WW][0][92] = -2,
+ [2][0][RTW89_WW][1][92] = -2,
+ [2][0][RTW89_WW][2][92] = 0,
+ [2][0][RTW89_WW][0][94] = -2,
+ [2][0][RTW89_WW][1][94] = -2,
+ [2][0][RTW89_WW][2][94] = 0,
+ [2][0][RTW89_WW][0][96] = -2,
+ [2][0][RTW89_WW][1][96] = -2,
+ [2][0][RTW89_WW][2][96] = 0,
+ [2][0][RTW89_WW][0][98] = -2,
+ [2][0][RTW89_WW][1][98] = -2,
+ [2][0][RTW89_WW][2][98] = 0,
+ [2][0][RTW89_WW][0][100] = -2,
+ [2][0][RTW89_WW][1][100] = -2,
+ [2][0][RTW89_WW][2][100] = 0,
+ [2][0][RTW89_WW][0][102] = -2,
+ [2][0][RTW89_WW][1][102] = -2,
+ [2][0][RTW89_WW][2][102] = 0,
+ [2][0][RTW89_WW][0][104] = -2,
+ [2][0][RTW89_WW][1][104] = -2,
+ [2][0][RTW89_WW][2][104] = 0,
+ [2][0][RTW89_WW][0][105] = -2,
+ [2][0][RTW89_WW][1][105] = -2,
+ [2][0][RTW89_WW][2][105] = 0,
+ [2][0][RTW89_WW][0][107] = -2,
+ [2][0][RTW89_WW][1][107] = -2,
+ [2][0][RTW89_WW][2][107] = 0,
+ [2][0][RTW89_WW][0][109] = 12,
+ [2][0][RTW89_WW][1][109] = 12,
+ [2][0][RTW89_WW][2][109] = 0,
+ [2][0][RTW89_WW][0][111] = 0,
+ [2][0][RTW89_WW][1][111] = 0,
+ [2][0][RTW89_WW][2][111] = 0,
+ [2][0][RTW89_WW][0][113] = 0,
+ [2][0][RTW89_WW][1][113] = 0,
+ [2][0][RTW89_WW][2][113] = 0,
+ [2][0][RTW89_WW][0][115] = 0,
+ [2][0][RTW89_WW][1][115] = 0,
+ [2][0][RTW89_WW][2][115] = 0,
+ [2][0][RTW89_WW][0][117] = 0,
+ [2][0][RTW89_WW][1][117] = 0,
+ [2][0][RTW89_WW][2][117] = 0,
+ [2][0][RTW89_WW][0][119] = 0,
+ [2][0][RTW89_WW][1][119] = 0,
+ [2][0][RTW89_WW][2][119] = 0,
+ [2][1][RTW89_WW][0][0] = -16,
+ [2][1][RTW89_WW][1][0] = -16,
+ [2][1][RTW89_WW][2][0] = 54,
+ [2][1][RTW89_WW][0][2] = -16,
+ [2][1][RTW89_WW][1][2] = -16,
+ [2][1][RTW89_WW][2][2] = 54,
+ [2][1][RTW89_WW][0][4] = -16,
+ [2][1][RTW89_WW][1][4] = -16,
+ [2][1][RTW89_WW][2][4] = 54,
+ [2][1][RTW89_WW][0][6] = -16,
+ [2][1][RTW89_WW][1][6] = -16,
+ [2][1][RTW89_WW][2][6] = 54,
+ [2][1][RTW89_WW][0][8] = -16,
+ [2][1][RTW89_WW][1][8] = -16,
+ [2][1][RTW89_WW][2][8] = 54,
+ [2][1][RTW89_WW][0][10] = -16,
+ [2][1][RTW89_WW][1][10] = -16,
+ [2][1][RTW89_WW][2][10] = 54,
+ [2][1][RTW89_WW][0][12] = -16,
+ [2][1][RTW89_WW][1][12] = -16,
+ [2][1][RTW89_WW][2][12] = 54,
+ [2][1][RTW89_WW][0][14] = -16,
+ [2][1][RTW89_WW][1][14] = -16,
+ [2][1][RTW89_WW][2][14] = 54,
+ [2][1][RTW89_WW][0][15] = -16,
+ [2][1][RTW89_WW][1][15] = -16,
+ [2][1][RTW89_WW][2][15] = 54,
+ [2][1][RTW89_WW][0][17] = -16,
+ [2][1][RTW89_WW][1][17] = -16,
+ [2][1][RTW89_WW][2][17] = 54,
+ [2][1][RTW89_WW][0][19] = -16,
+ [2][1][RTW89_WW][1][19] = -16,
+ [2][1][RTW89_WW][2][19] = 54,
+ [2][1][RTW89_WW][0][21] = -16,
+ [2][1][RTW89_WW][1][21] = -16,
+ [2][1][RTW89_WW][2][21] = 54,
+ [2][1][RTW89_WW][0][23] = -16,
+ [2][1][RTW89_WW][1][23] = -16,
+ [2][1][RTW89_WW][2][23] = 54,
+ [2][1][RTW89_WW][0][25] = -16,
+ [2][1][RTW89_WW][1][25] = -16,
+ [2][1][RTW89_WW][2][25] = 54,
+ [2][1][RTW89_WW][0][27] = -16,
+ [2][1][RTW89_WW][1][27] = -16,
+ [2][1][RTW89_WW][2][27] = 54,
+ [2][1][RTW89_WW][0][29] = -16,
+ [2][1][RTW89_WW][1][29] = -16,
+ [2][1][RTW89_WW][2][29] = 54,
+ [2][1][RTW89_WW][0][30] = -16,
+ [2][1][RTW89_WW][1][30] = -16,
+ [2][1][RTW89_WW][2][30] = 54,
+ [2][1][RTW89_WW][0][32] = -16,
+ [2][1][RTW89_WW][1][32] = -16,
+ [2][1][RTW89_WW][2][32] = 54,
+ [2][1][RTW89_WW][0][34] = -16,
+ [2][1][RTW89_WW][1][34] = -16,
+ [2][1][RTW89_WW][2][34] = 54,
+ [2][1][RTW89_WW][0][36] = -16,
+ [2][1][RTW89_WW][1][36] = -16,
+ [2][1][RTW89_WW][2][36] = 54,
+ [2][1][RTW89_WW][0][38] = -16,
+ [2][1][RTW89_WW][1][38] = -16,
+ [2][1][RTW89_WW][2][38] = 54,
+ [2][1][RTW89_WW][0][40] = -16,
+ [2][1][RTW89_WW][1][40] = -16,
+ [2][1][RTW89_WW][2][40] = 54,
+ [2][1][RTW89_WW][0][42] = -16,
+ [2][1][RTW89_WW][1][42] = -16,
+ [2][1][RTW89_WW][2][42] = 54,
+ [2][1][RTW89_WW][0][44] = -16,
+ [2][1][RTW89_WW][1][44] = -16,
+ [2][1][RTW89_WW][2][44] = 54,
+ [2][1][RTW89_WW][0][45] = -16,
+ [2][1][RTW89_WW][1][45] = -16,
+ [2][1][RTW89_WW][2][45] = 0,
+ [2][1][RTW89_WW][0][47] = -16,
+ [2][1][RTW89_WW][1][47] = -16,
+ [2][1][RTW89_WW][2][47] = 0,
+ [2][1][RTW89_WW][0][49] = -16,
+ [2][1][RTW89_WW][1][49] = -16,
+ [2][1][RTW89_WW][2][49] = 0,
+ [2][1][RTW89_WW][0][51] = -16,
+ [2][1][RTW89_WW][1][51] = -16,
+ [2][1][RTW89_WW][2][51] = 0,
+ [2][1][RTW89_WW][0][53] = -16,
+ [2][1][RTW89_WW][1][53] = -16,
+ [2][1][RTW89_WW][2][53] = 0,
+ [2][1][RTW89_WW][0][55] = -16,
+ [2][1][RTW89_WW][1][55] = -16,
+ [2][1][RTW89_WW][2][55] = 54,
+ [2][1][RTW89_WW][0][57] = -16,
+ [2][1][RTW89_WW][1][57] = -16,
+ [2][1][RTW89_WW][2][57] = 54,
+ [2][1][RTW89_WW][0][59] = -16,
+ [2][1][RTW89_WW][1][59] = -16,
+ [2][1][RTW89_WW][2][59] = 54,
+ [2][1][RTW89_WW][0][60] = -16,
+ [2][1][RTW89_WW][1][60] = -16,
+ [2][1][RTW89_WW][2][60] = 54,
+ [2][1][RTW89_WW][0][62] = -16,
+ [2][1][RTW89_WW][1][62] = -16,
+ [2][1][RTW89_WW][2][62] = 54,
+ [2][1][RTW89_WW][0][64] = -16,
+ [2][1][RTW89_WW][1][64] = -16,
+ [2][1][RTW89_WW][2][64] = 54,
+ [2][1][RTW89_WW][0][66] = -16,
+ [2][1][RTW89_WW][1][66] = -16,
+ [2][1][RTW89_WW][2][66] = 54,
+ [2][1][RTW89_WW][0][68] = -16,
+ [2][1][RTW89_WW][1][68] = -16,
+ [2][1][RTW89_WW][2][68] = 54,
+ [2][1][RTW89_WW][0][70] = -16,
+ [2][1][RTW89_WW][1][70] = -16,
+ [2][1][RTW89_WW][2][70] = 56,
+ [2][1][RTW89_WW][0][72] = -16,
+ [2][1][RTW89_WW][1][72] = -16,
+ [2][1][RTW89_WW][2][72] = 56,
+ [2][1][RTW89_WW][0][74] = -16,
+ [2][1][RTW89_WW][1][74] = -16,
+ [2][1][RTW89_WW][2][74] = 56,
+ [2][1][RTW89_WW][0][75] = -16,
+ [2][1][RTW89_WW][1][75] = -16,
+ [2][1][RTW89_WW][2][75] = 56,
+ [2][1][RTW89_WW][0][77] = -16,
+ [2][1][RTW89_WW][1][77] = -16,
+ [2][1][RTW89_WW][2][77] = 56,
+ [2][1][RTW89_WW][0][79] = -16,
+ [2][1][RTW89_WW][1][79] = -16,
+ [2][1][RTW89_WW][2][79] = 56,
+ [2][1][RTW89_WW][0][81] = -16,
+ [2][1][RTW89_WW][1][81] = -16,
+ [2][1][RTW89_WW][2][81] = 56,
+ [2][1][RTW89_WW][0][83] = -16,
+ [2][1][RTW89_WW][1][83] = -16,
+ [2][1][RTW89_WW][2][83] = 56,
+ [2][1][RTW89_WW][0][85] = -18,
+ [2][1][RTW89_WW][1][85] = -18,
+ [2][1][RTW89_WW][2][85] = 56,
+ [2][1][RTW89_WW][0][87] = -16,
+ [2][1][RTW89_WW][1][87] = -16,
+ [2][1][RTW89_WW][2][87] = 0,
+ [2][1][RTW89_WW][0][89] = -16,
+ [2][1][RTW89_WW][1][89] = -16,
+ [2][1][RTW89_WW][2][89] = 0,
+ [2][1][RTW89_WW][0][90] = -16,
+ [2][1][RTW89_WW][1][90] = -16,
+ [2][1][RTW89_WW][2][90] = 0,
+ [2][1][RTW89_WW][0][92] = -16,
+ [2][1][RTW89_WW][1][92] = -16,
+ [2][1][RTW89_WW][2][92] = 0,
+ [2][1][RTW89_WW][0][94] = -16,
+ [2][1][RTW89_WW][1][94] = -16,
+ [2][1][RTW89_WW][2][94] = 0,
+ [2][1][RTW89_WW][0][96] = -16,
+ [2][1][RTW89_WW][1][96] = -16,
+ [2][1][RTW89_WW][2][96] = 0,
+ [2][1][RTW89_WW][0][98] = -16,
+ [2][1][RTW89_WW][1][98] = -16,
+ [2][1][RTW89_WW][2][98] = 0,
+ [2][1][RTW89_WW][0][100] = -16,
+ [2][1][RTW89_WW][1][100] = -16,
+ [2][1][RTW89_WW][2][100] = 0,
+ [2][1][RTW89_WW][0][102] = -16,
+ [2][1][RTW89_WW][1][102] = -16,
+ [2][1][RTW89_WW][2][102] = 0,
+ [2][1][RTW89_WW][0][104] = -16,
+ [2][1][RTW89_WW][1][104] = -16,
+ [2][1][RTW89_WW][2][104] = 0,
+ [2][1][RTW89_WW][0][105] = -16,
+ [2][1][RTW89_WW][1][105] = -16,
+ [2][1][RTW89_WW][2][105] = 0,
+ [2][1][RTW89_WW][0][107] = -14,
+ [2][1][RTW89_WW][1][107] = -14,
+ [2][1][RTW89_WW][2][107] = 0,
+ [2][1][RTW89_WW][0][109] = -10,
+ [2][1][RTW89_WW][1][109] = -10,
+ [2][1][RTW89_WW][2][109] = 0,
+ [2][1][RTW89_WW][0][111] = 0,
+ [2][1][RTW89_WW][1][111] = 0,
+ [2][1][RTW89_WW][2][111] = 0,
+ [2][1][RTW89_WW][0][113] = 0,
+ [2][1][RTW89_WW][1][113] = 0,
+ [2][1][RTW89_WW][2][113] = 0,
+ [2][1][RTW89_WW][0][115] = 0,
+ [2][1][RTW89_WW][1][115] = 0,
+ [2][1][RTW89_WW][2][115] = 0,
+ [2][1][RTW89_WW][0][117] = 0,
+ [2][1][RTW89_WW][1][117] = 0,
+ [2][1][RTW89_WW][2][117] = 0,
+ [2][1][RTW89_WW][0][119] = 0,
+ [2][1][RTW89_WW][1][119] = 0,
+ [2][1][RTW89_WW][2][119] = 0,
+ [0][0][RTW89_FCC][1][0] = -16,
+ [0][0][RTW89_FCC][2][0] = 44,
+ [0][0][RTW89_ETSI][1][0] = 32,
+ [0][0][RTW89_ETSI][0][0] = -8,
+ [0][0][RTW89_MKK][1][0] = 30,
+ [0][0][RTW89_MKK][0][0] = -8,
+ [0][0][RTW89_IC][1][0] = -16,
+ [0][0][RTW89_KCC][1][0] = -2,
+ [0][0][RTW89_KCC][0][0] = -2,
+ [0][0][RTW89_ACMA][1][0] = 32,
+ [0][0][RTW89_ACMA][0][0] = -8,
+ [0][0][RTW89_CHILE][1][0] = -16,
+ [0][0][RTW89_QATAR][1][0] = 32,
+ [0][0][RTW89_QATAR][0][0] = -8,
+ [0][0][RTW89_UK][1][0] = 32,
+ [0][0][RTW89_UK][0][0] = -8,
+ [0][0][RTW89_FCC][1][2] = -18,
+ [0][0][RTW89_FCC][2][2] = 44,
+ [0][0][RTW89_ETSI][1][2] = 32,
+ [0][0][RTW89_ETSI][0][2] = -8,
+ [0][0][RTW89_MKK][1][2] = 30,
+ [0][0][RTW89_MKK][0][2] = -8,
+ [0][0][RTW89_IC][1][2] = -18,
+ [0][0][RTW89_KCC][1][2] = -2,
+ [0][0][RTW89_KCC][0][2] = -2,
+ [0][0][RTW89_ACMA][1][2] = 32,
+ [0][0][RTW89_ACMA][0][2] = -8,
+ [0][0][RTW89_CHILE][1][2] = -18,
+ [0][0][RTW89_QATAR][1][2] = 32,
+ [0][0][RTW89_QATAR][0][2] = -8,
+ [0][0][RTW89_UK][1][2] = 32,
+ [0][0][RTW89_UK][0][2] = -8,
+ [0][0][RTW89_FCC][1][4] = -18,
+ [0][0][RTW89_FCC][2][4] = 44,
+ [0][0][RTW89_ETSI][1][4] = 32,
+ [0][0][RTW89_ETSI][0][4] = -8,
+ [0][0][RTW89_MKK][1][4] = 30,
+ [0][0][RTW89_MKK][0][4] = -8,
+ [0][0][RTW89_IC][1][4] = -18,
+ [0][0][RTW89_KCC][1][4] = -2,
+ [0][0][RTW89_KCC][0][4] = -2,
+ [0][0][RTW89_ACMA][1][4] = 32,
+ [0][0][RTW89_ACMA][0][4] = -8,
+ [0][0][RTW89_CHILE][1][4] = -18,
+ [0][0][RTW89_QATAR][1][4] = 32,
+ [0][0][RTW89_QATAR][0][4] = -8,
+ [0][0][RTW89_UK][1][4] = 32,
+ [0][0][RTW89_UK][0][4] = -8,
+ [0][0][RTW89_FCC][1][6] = -18,
+ [0][0][RTW89_FCC][2][6] = 44,
+ [0][0][RTW89_ETSI][1][6] = 32,
+ [0][0][RTW89_ETSI][0][6] = -8,
+ [0][0][RTW89_MKK][1][6] = 30,
+ [0][0][RTW89_MKK][0][6] = -8,
+ [0][0][RTW89_IC][1][6] = -18,
+ [0][0][RTW89_KCC][1][6] = -2,
+ [0][0][RTW89_KCC][0][6] = -2,
+ [0][0][RTW89_ACMA][1][6] = 32,
+ [0][0][RTW89_ACMA][0][6] = -8,
+ [0][0][RTW89_CHILE][1][6] = -18,
+ [0][0][RTW89_QATAR][1][6] = 32,
+ [0][0][RTW89_QATAR][0][6] = -8,
+ [0][0][RTW89_UK][1][6] = 32,
+ [0][0][RTW89_UK][0][6] = -8,
+ [0][0][RTW89_FCC][1][8] = -18,
+ [0][0][RTW89_FCC][2][8] = 44,
+ [0][0][RTW89_ETSI][1][8] = 32,
+ [0][0][RTW89_ETSI][0][8] = -8,
+ [0][0][RTW89_MKK][1][8] = 30,
+ [0][0][RTW89_MKK][0][8] = -8,
+ [0][0][RTW89_IC][1][8] = -18,
+ [0][0][RTW89_KCC][1][8] = -2,
+ [0][0][RTW89_KCC][0][8] = -2,
+ [0][0][RTW89_ACMA][1][8] = 32,
+ [0][0][RTW89_ACMA][0][8] = -8,
+ [0][0][RTW89_CHILE][1][8] = -18,
+ [0][0][RTW89_QATAR][1][8] = 32,
+ [0][0][RTW89_QATAR][0][8] = -8,
+ [0][0][RTW89_UK][1][8] = 32,
+ [0][0][RTW89_UK][0][8] = -8,
+ [0][0][RTW89_FCC][1][10] = -18,
+ [0][0][RTW89_FCC][2][10] = 44,
+ [0][0][RTW89_ETSI][1][10] = 32,
+ [0][0][RTW89_ETSI][0][10] = -8,
+ [0][0][RTW89_MKK][1][10] = 30,
+ [0][0][RTW89_MKK][0][10] = -8,
+ [0][0][RTW89_IC][1][10] = -18,
+ [0][0][RTW89_KCC][1][10] = -2,
+ [0][0][RTW89_KCC][0][10] = -2,
+ [0][0][RTW89_ACMA][1][10] = 32,
+ [0][0][RTW89_ACMA][0][10] = -8,
+ [0][0][RTW89_CHILE][1][10] = -18,
+ [0][0][RTW89_QATAR][1][10] = 32,
+ [0][0][RTW89_QATAR][0][10] = -8,
+ [0][0][RTW89_UK][1][10] = 32,
+ [0][0][RTW89_UK][0][10] = -8,
+ [0][0][RTW89_FCC][1][12] = -18,
+ [0][0][RTW89_FCC][2][12] = 44,
+ [0][0][RTW89_ETSI][1][12] = 32,
+ [0][0][RTW89_ETSI][0][12] = -8,
+ [0][0][RTW89_MKK][1][12] = 30,
+ [0][0][RTW89_MKK][0][12] = -8,
+ [0][0][RTW89_IC][1][12] = -18,
+ [0][0][RTW89_KCC][1][12] = -2,
+ [0][0][RTW89_KCC][0][12] = -2,
+ [0][0][RTW89_ACMA][1][12] = 32,
+ [0][0][RTW89_ACMA][0][12] = -8,
+ [0][0][RTW89_CHILE][1][12] = -18,
+ [0][0][RTW89_QATAR][1][12] = 32,
+ [0][0][RTW89_QATAR][0][12] = -8,
+ [0][0][RTW89_UK][1][12] = 32,
+ [0][0][RTW89_UK][0][12] = -8,
+ [0][0][RTW89_FCC][1][14] = -18,
+ [0][0][RTW89_FCC][2][14] = 44,
+ [0][0][RTW89_ETSI][1][14] = 32,
+ [0][0][RTW89_ETSI][0][14] = -8,
+ [0][0][RTW89_MKK][1][14] = 30,
+ [0][0][RTW89_MKK][0][14] = -8,
+ [0][0][RTW89_IC][1][14] = -18,
+ [0][0][RTW89_KCC][1][14] = -2,
+ [0][0][RTW89_KCC][0][14] = -2,
+ [0][0][RTW89_ACMA][1][14] = 32,
+ [0][0][RTW89_ACMA][0][14] = -8,
+ [0][0][RTW89_CHILE][1][14] = -18,
+ [0][0][RTW89_QATAR][1][14] = 32,
+ [0][0][RTW89_QATAR][0][14] = -8,
+ [0][0][RTW89_UK][1][14] = 32,
+ [0][0][RTW89_UK][0][14] = -8,
+ [0][0][RTW89_FCC][1][15] = -18,
+ [0][0][RTW89_FCC][2][15] = 44,
+ [0][0][RTW89_ETSI][1][15] = 32,
+ [0][0][RTW89_ETSI][0][15] = -8,
+ [0][0][RTW89_MKK][1][15] = 30,
+ [0][0][RTW89_MKK][0][15] = -8,
+ [0][0][RTW89_IC][1][15] = -18,
+ [0][0][RTW89_KCC][1][15] = -2,
+ [0][0][RTW89_KCC][0][15] = -2,
+ [0][0][RTW89_ACMA][1][15] = 32,
+ [0][0][RTW89_ACMA][0][15] = -8,
+ [0][0][RTW89_CHILE][1][15] = -18,
+ [0][0][RTW89_QATAR][1][15] = 32,
+ [0][0][RTW89_QATAR][0][15] = -8,
+ [0][0][RTW89_UK][1][15] = 32,
+ [0][0][RTW89_UK][0][15] = -8,
+ [0][0][RTW89_FCC][1][17] = -18,
+ [0][0][RTW89_FCC][2][17] = 44,
+ [0][0][RTW89_ETSI][1][17] = 32,
+ [0][0][RTW89_ETSI][0][17] = -8,
+ [0][0][RTW89_MKK][1][17] = 30,
+ [0][0][RTW89_MKK][0][17] = -8,
+ [0][0][RTW89_IC][1][17] = -18,
+ [0][0][RTW89_KCC][1][17] = -2,
+ [0][0][RTW89_KCC][0][17] = -2,
+ [0][0][RTW89_ACMA][1][17] = 32,
+ [0][0][RTW89_ACMA][0][17] = -8,
+ [0][0][RTW89_CHILE][1][17] = -18,
+ [0][0][RTW89_QATAR][1][17] = 32,
+ [0][0][RTW89_QATAR][0][17] = -8,
+ [0][0][RTW89_UK][1][17] = 32,
+ [0][0][RTW89_UK][0][17] = -8,
+ [0][0][RTW89_FCC][1][19] = -18,
+ [0][0][RTW89_FCC][2][19] = 44,
+ [0][0][RTW89_ETSI][1][19] = 32,
+ [0][0][RTW89_ETSI][0][19] = -8,
+ [0][0][RTW89_MKK][1][19] = 30,
+ [0][0][RTW89_MKK][0][19] = -8,
+ [0][0][RTW89_IC][1][19] = -18,
+ [0][0][RTW89_KCC][1][19] = -2,
+ [0][0][RTW89_KCC][0][19] = -2,
+ [0][0][RTW89_ACMA][1][19] = 32,
+ [0][0][RTW89_ACMA][0][19] = -8,
+ [0][0][RTW89_CHILE][1][19] = -18,
+ [0][0][RTW89_QATAR][1][19] = 32,
+ [0][0][RTW89_QATAR][0][19] = -8,
+ [0][0][RTW89_UK][1][19] = 32,
+ [0][0][RTW89_UK][0][19] = -8,
+ [0][0][RTW89_FCC][1][21] = -18,
+ [0][0][RTW89_FCC][2][21] = 44,
+ [0][0][RTW89_ETSI][1][21] = 32,
+ [0][0][RTW89_ETSI][0][21] = -8,
+ [0][0][RTW89_MKK][1][21] = 30,
+ [0][0][RTW89_MKK][0][21] = -8,
+ [0][0][RTW89_IC][1][21] = -18,
+ [0][0][RTW89_KCC][1][21] = -2,
+ [0][0][RTW89_KCC][0][21] = -2,
+ [0][0][RTW89_ACMA][1][21] = 32,
+ [0][0][RTW89_ACMA][0][21] = -8,
+ [0][0][RTW89_CHILE][1][21] = -18,
+ [0][0][RTW89_QATAR][1][21] = 32,
+ [0][0][RTW89_QATAR][0][21] = -8,
+ [0][0][RTW89_UK][1][21] = 32,
+ [0][0][RTW89_UK][0][21] = -8,
+ [0][0][RTW89_FCC][1][23] = -18,
+ [0][0][RTW89_FCC][2][23] = 54,
+ [0][0][RTW89_ETSI][1][23] = 32,
+ [0][0][RTW89_ETSI][0][23] = -8,
+ [0][0][RTW89_MKK][1][23] = 30,
+ [0][0][RTW89_MKK][0][23] = -8,
+ [0][0][RTW89_IC][1][23] = -18,
+ [0][0][RTW89_KCC][1][23] = -2,
+ [0][0][RTW89_KCC][0][23] = -2,
+ [0][0][RTW89_ACMA][1][23] = 32,
+ [0][0][RTW89_ACMA][0][23] = -8,
+ [0][0][RTW89_CHILE][1][23] = -18,
+ [0][0][RTW89_QATAR][1][23] = 32,
+ [0][0][RTW89_QATAR][0][23] = -8,
+ [0][0][RTW89_UK][1][23] = 32,
+ [0][0][RTW89_UK][0][23] = -8,
+ [0][0][RTW89_FCC][1][25] = -18,
+ [0][0][RTW89_FCC][2][25] = 54,
+ [0][0][RTW89_ETSI][1][25] = 32,
+ [0][0][RTW89_ETSI][0][25] = -8,
+ [0][0][RTW89_MKK][1][25] = 30,
+ [0][0][RTW89_MKK][0][25] = -8,
+ [0][0][RTW89_IC][1][25] = -18,
+ [0][0][RTW89_KCC][1][25] = -2,
+ [0][0][RTW89_KCC][0][25] = -2,
+ [0][0][RTW89_ACMA][1][25] = 32,
+ [0][0][RTW89_ACMA][0][25] = -8,
+ [0][0][RTW89_CHILE][1][25] = -18,
+ [0][0][RTW89_QATAR][1][25] = 32,
+ [0][0][RTW89_QATAR][0][25] = -8,
+ [0][0][RTW89_UK][1][25] = 32,
+ [0][0][RTW89_UK][0][25] = -8,
+ [0][0][RTW89_FCC][1][27] = -18,
+ [0][0][RTW89_FCC][2][27] = 54,
+ [0][0][RTW89_ETSI][1][27] = 32,
+ [0][0][RTW89_ETSI][0][27] = -8,
+ [0][0][RTW89_MKK][1][27] = 30,
+ [0][0][RTW89_MKK][0][27] = -8,
+ [0][0][RTW89_IC][1][27] = -18,
+ [0][0][RTW89_KCC][1][27] = -2,
+ [0][0][RTW89_KCC][0][27] = -2,
+ [0][0][RTW89_ACMA][1][27] = 32,
+ [0][0][RTW89_ACMA][0][27] = -8,
+ [0][0][RTW89_CHILE][1][27] = -18,
+ [0][0][RTW89_QATAR][1][27] = 32,
+ [0][0][RTW89_QATAR][0][27] = -8,
+ [0][0][RTW89_UK][1][27] = 32,
+ [0][0][RTW89_UK][0][27] = -8,
+ [0][0][RTW89_FCC][1][29] = -18,
+ [0][0][RTW89_FCC][2][29] = 54,
+ [0][0][RTW89_ETSI][1][29] = 32,
+ [0][0][RTW89_ETSI][0][29] = -8,
+ [0][0][RTW89_MKK][1][29] = 30,
+ [0][0][RTW89_MKK][0][29] = -8,
+ [0][0][RTW89_IC][1][29] = -18,
+ [0][0][RTW89_KCC][1][29] = -2,
+ [0][0][RTW89_KCC][0][29] = -2,
+ [0][0][RTW89_ACMA][1][29] = 32,
+ [0][0][RTW89_ACMA][0][29] = -8,
+ [0][0][RTW89_CHILE][1][29] = -18,
+ [0][0][RTW89_QATAR][1][29] = 32,
+ [0][0][RTW89_QATAR][0][29] = -8,
+ [0][0][RTW89_UK][1][29] = 32,
+ [0][0][RTW89_UK][0][29] = -8,
+ [0][0][RTW89_FCC][1][30] = -18,
+ [0][0][RTW89_FCC][2][30] = 54,
+ [0][0][RTW89_ETSI][1][30] = 32,
+ [0][0][RTW89_ETSI][0][30] = -8,
+ [0][0][RTW89_MKK][1][30] = 30,
+ [0][0][RTW89_MKK][0][30] = -8,
+ [0][0][RTW89_IC][1][30] = -18,
+ [0][0][RTW89_KCC][1][30] = -2,
+ [0][0][RTW89_KCC][0][30] = -2,
+ [0][0][RTW89_ACMA][1][30] = 32,
+ [0][0][RTW89_ACMA][0][30] = -8,
+ [0][0][RTW89_CHILE][1][30] = -18,
+ [0][0][RTW89_QATAR][1][30] = 32,
+ [0][0][RTW89_QATAR][0][30] = -8,
+ [0][0][RTW89_UK][1][30] = 32,
+ [0][0][RTW89_UK][0][30] = -8,
+ [0][0][RTW89_FCC][1][32] = -18,
+ [0][0][RTW89_FCC][2][32] = 54,
+ [0][0][RTW89_ETSI][1][32] = 32,
+ [0][0][RTW89_ETSI][0][32] = -8,
+ [0][0][RTW89_MKK][1][32] = 30,
+ [0][0][RTW89_MKK][0][32] = -8,
+ [0][0][RTW89_IC][1][32] = -18,
+ [0][0][RTW89_KCC][1][32] = -2,
+ [0][0][RTW89_KCC][0][32] = -2,
+ [0][0][RTW89_ACMA][1][32] = 32,
+ [0][0][RTW89_ACMA][0][32] = -8,
+ [0][0][RTW89_CHILE][1][32] = -18,
+ [0][0][RTW89_QATAR][1][32] = 32,
+ [0][0][RTW89_QATAR][0][32] = -8,
+ [0][0][RTW89_UK][1][32] = 32,
+ [0][0][RTW89_UK][0][32] = -8,
+ [0][0][RTW89_FCC][1][34] = -18,
+ [0][0][RTW89_FCC][2][34] = 54,
+ [0][0][RTW89_ETSI][1][34] = 32,
+ [0][0][RTW89_ETSI][0][34] = -8,
+ [0][0][RTW89_MKK][1][34] = 30,
+ [0][0][RTW89_MKK][0][34] = -8,
+ [0][0][RTW89_IC][1][34] = -18,
+ [0][0][RTW89_KCC][1][34] = -2,
+ [0][0][RTW89_KCC][0][34] = -2,
+ [0][0][RTW89_ACMA][1][34] = 32,
+ [0][0][RTW89_ACMA][0][34] = -8,
+ [0][0][RTW89_CHILE][1][34] = -18,
+ [0][0][RTW89_QATAR][1][34] = 32,
+ [0][0][RTW89_QATAR][0][34] = -8,
+ [0][0][RTW89_UK][1][34] = 32,
+ [0][0][RTW89_UK][0][34] = -8,
+ [0][0][RTW89_FCC][1][36] = -18,
+ [0][0][RTW89_FCC][2][36] = 54,
+ [0][0][RTW89_ETSI][1][36] = 32,
+ [0][0][RTW89_ETSI][0][36] = -8,
+ [0][0][RTW89_MKK][1][36] = 30,
+ [0][0][RTW89_MKK][0][36] = -8,
+ [0][0][RTW89_IC][1][36] = -18,
+ [0][0][RTW89_KCC][1][36] = -2,
+ [0][0][RTW89_KCC][0][36] = -2,
+ [0][0][RTW89_ACMA][1][36] = 32,
+ [0][0][RTW89_ACMA][0][36] = -8,
+ [0][0][RTW89_CHILE][1][36] = -18,
+ [0][0][RTW89_QATAR][1][36] = 32,
+ [0][0][RTW89_QATAR][0][36] = -8,
+ [0][0][RTW89_UK][1][36] = 32,
+ [0][0][RTW89_UK][0][36] = -8,
+ [0][0][RTW89_FCC][1][38] = -18,
+ [0][0][RTW89_FCC][2][38] = 54,
+ [0][0][RTW89_ETSI][1][38] = 32,
+ [0][0][RTW89_ETSI][0][38] = -8,
+ [0][0][RTW89_MKK][1][38] = 30,
+ [0][0][RTW89_MKK][0][38] = -8,
+ [0][0][RTW89_IC][1][38] = -18,
+ [0][0][RTW89_KCC][1][38] = -2,
+ [0][0][RTW89_KCC][0][38] = -2,
+ [0][0][RTW89_ACMA][1][38] = 32,
+ [0][0][RTW89_ACMA][0][38] = -8,
+ [0][0][RTW89_CHILE][1][38] = -18,
+ [0][0][RTW89_QATAR][1][38] = 32,
+ [0][0][RTW89_QATAR][0][38] = -8,
+ [0][0][RTW89_UK][1][38] = 32,
+ [0][0][RTW89_UK][0][38] = -8,
+ [0][0][RTW89_FCC][1][40] = -18,
+ [0][0][RTW89_FCC][2][40] = 54,
+ [0][0][RTW89_ETSI][1][40] = 32,
+ [0][0][RTW89_ETSI][0][40] = -8,
+ [0][0][RTW89_MKK][1][40] = 30,
+ [0][0][RTW89_MKK][0][40] = -8,
+ [0][0][RTW89_IC][1][40] = -18,
+ [0][0][RTW89_KCC][1][40] = -2,
+ [0][0][RTW89_KCC][0][40] = -2,
+ [0][0][RTW89_ACMA][1][40] = 32,
+ [0][0][RTW89_ACMA][0][40] = -8,
+ [0][0][RTW89_CHILE][1][40] = -18,
+ [0][0][RTW89_QATAR][1][40] = 32,
+ [0][0][RTW89_QATAR][0][40] = -8,
+ [0][0][RTW89_UK][1][40] = 32,
+ [0][0][RTW89_UK][0][40] = -8,
+ [0][0][RTW89_FCC][1][42] = -18,
+ [0][0][RTW89_FCC][2][42] = 54,
+ [0][0][RTW89_ETSI][1][42] = 32,
+ [0][0][RTW89_ETSI][0][42] = -8,
+ [0][0][RTW89_MKK][1][42] = 30,
+ [0][0][RTW89_MKK][0][42] = -8,
+ [0][0][RTW89_IC][1][42] = -18,
+ [0][0][RTW89_KCC][1][42] = -2,
+ [0][0][RTW89_KCC][0][42] = -2,
+ [0][0][RTW89_ACMA][1][42] = 32,
+ [0][0][RTW89_ACMA][0][42] = -8,
+ [0][0][RTW89_CHILE][1][42] = -18,
+ [0][0][RTW89_QATAR][1][42] = 32,
+ [0][0][RTW89_QATAR][0][42] = -8,
+ [0][0][RTW89_UK][1][42] = 32,
+ [0][0][RTW89_UK][0][42] = -8,
+ [0][0][RTW89_FCC][1][44] = -16,
+ [0][0][RTW89_FCC][2][44] = 56,
+ [0][0][RTW89_ETSI][1][44] = 32,
+ [0][0][RTW89_ETSI][0][44] = -6,
+ [0][0][RTW89_MKK][1][44] = 8,
+ [0][0][RTW89_MKK][0][44] = -10,
+ [0][0][RTW89_IC][1][44] = -16,
+ [0][0][RTW89_KCC][1][44] = -2,
+ [0][0][RTW89_KCC][0][44] = -2,
+ [0][0][RTW89_ACMA][1][44] = 32,
+ [0][0][RTW89_ACMA][0][44] = -6,
+ [0][0][RTW89_CHILE][1][44] = -16,
+ [0][0][RTW89_QATAR][1][44] = 32,
+ [0][0][RTW89_QATAR][0][44] = -6,
+ [0][0][RTW89_UK][1][44] = 32,
+ [0][0][RTW89_UK][0][44] = -6,
+ [0][0][RTW89_FCC][1][45] = -16,
+ [0][0][RTW89_FCC][2][45] = 127,
+ [0][0][RTW89_ETSI][1][45] = 127,
+ [0][0][RTW89_ETSI][0][45] = 127,
+ [0][0][RTW89_MKK][1][45] = 127,
+ [0][0][RTW89_MKK][0][45] = 127,
+ [0][0][RTW89_IC][1][45] = -16,
+ [0][0][RTW89_KCC][1][45] = -2,
+ [0][0][RTW89_KCC][0][45] = 127,
+ [0][0][RTW89_ACMA][1][45] = 127,
+ [0][0][RTW89_ACMA][0][45] = 127,
+ [0][0][RTW89_CHILE][1][45] = 127,
+ [0][0][RTW89_QATAR][1][45] = 127,
+ [0][0][RTW89_QATAR][0][45] = 127,
+ [0][0][RTW89_UK][1][45] = 127,
+ [0][0][RTW89_UK][0][45] = 127,
+ [0][0][RTW89_FCC][1][47] = -18,
+ [0][0][RTW89_FCC][2][47] = 127,
+ [0][0][RTW89_ETSI][1][47] = 127,
+ [0][0][RTW89_ETSI][0][47] = 127,
+ [0][0][RTW89_MKK][1][47] = 127,
+ [0][0][RTW89_MKK][0][47] = 127,
+ [0][0][RTW89_IC][1][47] = -18,
+ [0][0][RTW89_KCC][1][47] = -2,
+ [0][0][RTW89_KCC][0][47] = 127,
+ [0][0][RTW89_ACMA][1][47] = 127,
+ [0][0][RTW89_ACMA][0][47] = 127,
+ [0][0][RTW89_CHILE][1][47] = 127,
+ [0][0][RTW89_QATAR][1][47] = 127,
+ [0][0][RTW89_QATAR][0][47] = 127,
+ [0][0][RTW89_UK][1][47] = 127,
+ [0][0][RTW89_UK][0][47] = 127,
+ [0][0][RTW89_FCC][1][49] = -18,
+ [0][0][RTW89_FCC][2][49] = 127,
+ [0][0][RTW89_ETSI][1][49] = 127,
+ [0][0][RTW89_ETSI][0][49] = 127,
+ [0][0][RTW89_MKK][1][49] = 127,
+ [0][0][RTW89_MKK][0][49] = 127,
+ [0][0][RTW89_IC][1][49] = -18,
+ [0][0][RTW89_KCC][1][49] = -2,
+ [0][0][RTW89_KCC][0][49] = 127,
+ [0][0][RTW89_ACMA][1][49] = 127,
+ [0][0][RTW89_ACMA][0][49] = 127,
+ [0][0][RTW89_CHILE][1][49] = 127,
+ [0][0][RTW89_QATAR][1][49] = 127,
+ [0][0][RTW89_QATAR][0][49] = 127,
+ [0][0][RTW89_UK][1][49] = 127,
+ [0][0][RTW89_UK][0][49] = 127,
+ [0][0][RTW89_FCC][1][51] = -18,
+ [0][0][RTW89_FCC][2][51] = 127,
+ [0][0][RTW89_ETSI][1][51] = 127,
+ [0][0][RTW89_ETSI][0][51] = 127,
+ [0][0][RTW89_MKK][1][51] = 127,
+ [0][0][RTW89_MKK][0][51] = 127,
+ [0][0][RTW89_IC][1][51] = -18,
+ [0][0][RTW89_KCC][1][51] = -2,
+ [0][0][RTW89_KCC][0][51] = 127,
+ [0][0][RTW89_ACMA][1][51] = 127,
+ [0][0][RTW89_ACMA][0][51] = 127,
+ [0][0][RTW89_CHILE][1][51] = 127,
+ [0][0][RTW89_QATAR][1][51] = 127,
+ [0][0][RTW89_QATAR][0][51] = 127,
+ [0][0][RTW89_UK][1][51] = 127,
+ [0][0][RTW89_UK][0][51] = 127,
+ [0][0][RTW89_FCC][1][53] = -16,
+ [0][0][RTW89_FCC][2][53] = 127,
+ [0][0][RTW89_ETSI][1][53] = 127,
+ [0][0][RTW89_ETSI][0][53] = 127,
+ [0][0][RTW89_MKK][1][53] = 127,
+ [0][0][RTW89_MKK][0][53] = 127,
+ [0][0][RTW89_IC][1][53] = -16,
+ [0][0][RTW89_KCC][1][53] = -2,
+ [0][0][RTW89_KCC][0][53] = 127,
+ [0][0][RTW89_ACMA][1][53] = 127,
+ [0][0][RTW89_ACMA][0][53] = 127,
+ [0][0][RTW89_CHILE][1][53] = 127,
+ [0][0][RTW89_QATAR][1][53] = 127,
+ [0][0][RTW89_QATAR][0][53] = 127,
+ [0][0][RTW89_UK][1][53] = 127,
+ [0][0][RTW89_UK][0][53] = 127,
+ [0][0][RTW89_FCC][1][55] = -18,
+ [0][0][RTW89_FCC][2][55] = 56,
+ [0][0][RTW89_ETSI][1][55] = 127,
+ [0][0][RTW89_ETSI][0][55] = 127,
+ [0][0][RTW89_MKK][1][55] = 127,
+ [0][0][RTW89_MKK][0][55] = 127,
+ [0][0][RTW89_IC][1][55] = -18,
+ [0][0][RTW89_KCC][1][55] = -2,
+ [0][0][RTW89_KCC][0][55] = 127,
+ [0][0][RTW89_ACMA][1][55] = 127,
+ [0][0][RTW89_ACMA][0][55] = 127,
+ [0][0][RTW89_CHILE][1][55] = 127,
+ [0][0][RTW89_QATAR][1][55] = 127,
+ [0][0][RTW89_QATAR][0][55] = 127,
+ [0][0][RTW89_UK][1][55] = 127,
+ [0][0][RTW89_UK][0][55] = 127,
+ [0][0][RTW89_FCC][1][57] = -18,
+ [0][0][RTW89_FCC][2][57] = 56,
+ [0][0][RTW89_ETSI][1][57] = 127,
+ [0][0][RTW89_ETSI][0][57] = 127,
+ [0][0][RTW89_MKK][1][57] = 127,
+ [0][0][RTW89_MKK][0][57] = 127,
+ [0][0][RTW89_IC][1][57] = -18,
+ [0][0][RTW89_KCC][1][57] = -2,
+ [0][0][RTW89_KCC][0][57] = 127,
+ [0][0][RTW89_ACMA][1][57] = 127,
+ [0][0][RTW89_ACMA][0][57] = 127,
+ [0][0][RTW89_CHILE][1][57] = 127,
+ [0][0][RTW89_QATAR][1][57] = 127,
+ [0][0][RTW89_QATAR][0][57] = 127,
+ [0][0][RTW89_UK][1][57] = 127,
+ [0][0][RTW89_UK][0][57] = 127,
+ [0][0][RTW89_FCC][1][59] = -18,
+ [0][0][RTW89_FCC][2][59] = 56,
+ [0][0][RTW89_ETSI][1][59] = 127,
+ [0][0][RTW89_ETSI][0][59] = 127,
+ [0][0][RTW89_MKK][1][59] = 127,
+ [0][0][RTW89_MKK][0][59] = 127,
+ [0][0][RTW89_IC][1][59] = -18,
+ [0][0][RTW89_KCC][1][59] = -2,
+ [0][0][RTW89_KCC][0][59] = 127,
+ [0][0][RTW89_ACMA][1][59] = 127,
+ [0][0][RTW89_ACMA][0][59] = 127,
+ [0][0][RTW89_CHILE][1][59] = 127,
+ [0][0][RTW89_QATAR][1][59] = 127,
+ [0][0][RTW89_QATAR][0][59] = 127,
+ [0][0][RTW89_UK][1][59] = 127,
+ [0][0][RTW89_UK][0][59] = 127,
+ [0][0][RTW89_FCC][1][60] = -18,
+ [0][0][RTW89_FCC][2][60] = 56,
+ [0][0][RTW89_ETSI][1][60] = 127,
+ [0][0][RTW89_ETSI][0][60] = 127,
+ [0][0][RTW89_MKK][1][60] = 127,
+ [0][0][RTW89_MKK][0][60] = 127,
+ [0][0][RTW89_IC][1][60] = -18,
+ [0][0][RTW89_KCC][1][60] = -2,
+ [0][0][RTW89_KCC][0][60] = 127,
+ [0][0][RTW89_ACMA][1][60] = 127,
+ [0][0][RTW89_ACMA][0][60] = 127,
+ [0][0][RTW89_CHILE][1][60] = 127,
+ [0][0][RTW89_QATAR][1][60] = 127,
+ [0][0][RTW89_QATAR][0][60] = 127,
+ [0][0][RTW89_UK][1][60] = 127,
+ [0][0][RTW89_UK][0][60] = 127,
+ [0][0][RTW89_FCC][1][62] = -18,
+ [0][0][RTW89_FCC][2][62] = 56,
+ [0][0][RTW89_ETSI][1][62] = 127,
+ [0][0][RTW89_ETSI][0][62] = 127,
+ [0][0][RTW89_MKK][1][62] = 127,
+ [0][0][RTW89_MKK][0][62] = 127,
+ [0][0][RTW89_IC][1][62] = -18,
+ [0][0][RTW89_KCC][1][62] = -2,
+ [0][0][RTW89_KCC][0][62] = 127,
+ [0][0][RTW89_ACMA][1][62] = 127,
+ [0][0][RTW89_ACMA][0][62] = 127,
+ [0][0][RTW89_CHILE][1][62] = 127,
+ [0][0][RTW89_QATAR][1][62] = 127,
+ [0][0][RTW89_QATAR][0][62] = 127,
+ [0][0][RTW89_UK][1][62] = 127,
+ [0][0][RTW89_UK][0][62] = 127,
+ [0][0][RTW89_FCC][1][64] = -18,
+ [0][0][RTW89_FCC][2][64] = 56,
+ [0][0][RTW89_ETSI][1][64] = 127,
+ [0][0][RTW89_ETSI][0][64] = 127,
+ [0][0][RTW89_MKK][1][64] = 127,
+ [0][0][RTW89_MKK][0][64] = 127,
+ [0][0][RTW89_IC][1][64] = -18,
+ [0][0][RTW89_KCC][1][64] = -2,
+ [0][0][RTW89_KCC][0][64] = 127,
+ [0][0][RTW89_ACMA][1][64] = 127,
+ [0][0][RTW89_ACMA][0][64] = 127,
+ [0][0][RTW89_CHILE][1][64] = 127,
+ [0][0][RTW89_QATAR][1][64] = 127,
+ [0][0][RTW89_QATAR][0][64] = 127,
+ [0][0][RTW89_UK][1][64] = 127,
+ [0][0][RTW89_UK][0][64] = 127,
+ [0][0][RTW89_FCC][1][66] = -18,
+ [0][0][RTW89_FCC][2][66] = 56,
+ [0][0][RTW89_ETSI][1][66] = 127,
+ [0][0][RTW89_ETSI][0][66] = 127,
+ [0][0][RTW89_MKK][1][66] = 127,
+ [0][0][RTW89_MKK][0][66] = 127,
+ [0][0][RTW89_IC][1][66] = -18,
+ [0][0][RTW89_KCC][1][66] = -2,
+ [0][0][RTW89_KCC][0][66] = 127,
+ [0][0][RTW89_ACMA][1][66] = 127,
+ [0][0][RTW89_ACMA][0][66] = 127,
+ [0][0][RTW89_CHILE][1][66] = 127,
+ [0][0][RTW89_QATAR][1][66] = 127,
+ [0][0][RTW89_QATAR][0][66] = 127,
+ [0][0][RTW89_UK][1][66] = 127,
+ [0][0][RTW89_UK][0][66] = 127,
+ [0][0][RTW89_FCC][1][68] = -18,
+ [0][0][RTW89_FCC][2][68] = 56,
+ [0][0][RTW89_ETSI][1][68] = 127,
+ [0][0][RTW89_ETSI][0][68] = 127,
+ [0][0][RTW89_MKK][1][68] = 127,
+ [0][0][RTW89_MKK][0][68] = 127,
+ [0][0][RTW89_IC][1][68] = -18,
+ [0][0][RTW89_KCC][1][68] = -2,
+ [0][0][RTW89_KCC][0][68] = 127,
+ [0][0][RTW89_ACMA][1][68] = 127,
+ [0][0][RTW89_ACMA][0][68] = 127,
+ [0][0][RTW89_CHILE][1][68] = 127,
+ [0][0][RTW89_QATAR][1][68] = 127,
+ [0][0][RTW89_QATAR][0][68] = 127,
+ [0][0][RTW89_UK][1][68] = 127,
+ [0][0][RTW89_UK][0][68] = 127,
+ [0][0][RTW89_FCC][1][70] = -16,
+ [0][0][RTW89_FCC][2][70] = 56,
+ [0][0][RTW89_ETSI][1][70] = 127,
+ [0][0][RTW89_ETSI][0][70] = 127,
+ [0][0][RTW89_MKK][1][70] = 127,
+ [0][0][RTW89_MKK][0][70] = 127,
+ [0][0][RTW89_IC][1][70] = -16,
+ [0][0][RTW89_KCC][1][70] = -2,
+ [0][0][RTW89_KCC][0][70] = 127,
+ [0][0][RTW89_ACMA][1][70] = 127,
+ [0][0][RTW89_ACMA][0][70] = 127,
+ [0][0][RTW89_CHILE][1][70] = 127,
+ [0][0][RTW89_QATAR][1][70] = 127,
+ [0][0][RTW89_QATAR][0][70] = 127,
+ [0][0][RTW89_UK][1][70] = 127,
+ [0][0][RTW89_UK][0][70] = 127,
+ [0][0][RTW89_FCC][1][72] = -18,
+ [0][0][RTW89_FCC][2][72] = 56,
+ [0][0][RTW89_ETSI][1][72] = 127,
+ [0][0][RTW89_ETSI][0][72] = 127,
+ [0][0][RTW89_MKK][1][72] = 127,
+ [0][0][RTW89_MKK][0][72] = 127,
+ [0][0][RTW89_IC][1][72] = -18,
+ [0][0][RTW89_KCC][1][72] = -2,
+ [0][0][RTW89_KCC][0][72] = 127,
+ [0][0][RTW89_ACMA][1][72] = 127,
+ [0][0][RTW89_ACMA][0][72] = 127,
+ [0][0][RTW89_CHILE][1][72] = 127,
+ [0][0][RTW89_QATAR][1][72] = 127,
+ [0][0][RTW89_QATAR][0][72] = 127,
+ [0][0][RTW89_UK][1][72] = 127,
+ [0][0][RTW89_UK][0][72] = 127,
+ [0][0][RTW89_FCC][1][74] = -18,
+ [0][0][RTW89_FCC][2][74] = 56,
+ [0][0][RTW89_ETSI][1][74] = 127,
+ [0][0][RTW89_ETSI][0][74] = 127,
+ [0][0][RTW89_MKK][1][74] = 127,
+ [0][0][RTW89_MKK][0][74] = 127,
+ [0][0][RTW89_IC][1][74] = -18,
+ [0][0][RTW89_KCC][1][74] = -2,
+ [0][0][RTW89_KCC][0][74] = 127,
+ [0][0][RTW89_ACMA][1][74] = 127,
+ [0][0][RTW89_ACMA][0][74] = 127,
+ [0][0][RTW89_CHILE][1][74] = 127,
+ [0][0][RTW89_QATAR][1][74] = 127,
+ [0][0][RTW89_QATAR][0][74] = 127,
+ [0][0][RTW89_UK][1][74] = 127,
+ [0][0][RTW89_UK][0][74] = 127,
+ [0][0][RTW89_FCC][1][75] = -18,
+ [0][0][RTW89_FCC][2][75] = 56,
+ [0][0][RTW89_ETSI][1][75] = 127,
+ [0][0][RTW89_ETSI][0][75] = 127,
+ [0][0][RTW89_MKK][1][75] = 127,
+ [0][0][RTW89_MKK][0][75] = 127,
+ [0][0][RTW89_IC][1][75] = -18,
+ [0][0][RTW89_KCC][1][75] = -2,
+ [0][0][RTW89_KCC][0][75] = 127,
+ [0][0][RTW89_ACMA][1][75] = 127,
+ [0][0][RTW89_ACMA][0][75] = 127,
+ [0][0][RTW89_CHILE][1][75] = 127,
+ [0][0][RTW89_QATAR][1][75] = 127,
+ [0][0][RTW89_QATAR][0][75] = 127,
+ [0][0][RTW89_UK][1][75] = 127,
+ [0][0][RTW89_UK][0][75] = 127,
+ [0][0][RTW89_FCC][1][77] = -18,
+ [0][0][RTW89_FCC][2][77] = 56,
+ [0][0][RTW89_ETSI][1][77] = 127,
+ [0][0][RTW89_ETSI][0][77] = 127,
+ [0][0][RTW89_MKK][1][77] = 127,
+ [0][0][RTW89_MKK][0][77] = 127,
+ [0][0][RTW89_IC][1][77] = -18,
+ [0][0][RTW89_KCC][1][77] = -2,
+ [0][0][RTW89_KCC][0][77] = 127,
+ [0][0][RTW89_ACMA][1][77] = 127,
+ [0][0][RTW89_ACMA][0][77] = 127,
+ [0][0][RTW89_CHILE][1][77] = 127,
+ [0][0][RTW89_QATAR][1][77] = 127,
+ [0][0][RTW89_QATAR][0][77] = 127,
+ [0][0][RTW89_UK][1][77] = 127,
+ [0][0][RTW89_UK][0][77] = 127,
+ [0][0][RTW89_FCC][1][79] = -18,
+ [0][0][RTW89_FCC][2][79] = 56,
+ [0][0][RTW89_ETSI][1][79] = 127,
+ [0][0][RTW89_ETSI][0][79] = 127,
+ [0][0][RTW89_MKK][1][79] = 127,
+ [0][0][RTW89_MKK][0][79] = 127,
+ [0][0][RTW89_IC][1][79] = -18,
+ [0][0][RTW89_KCC][1][79] = -2,
+ [0][0][RTW89_KCC][0][79] = 127,
+ [0][0][RTW89_ACMA][1][79] = 127,
+ [0][0][RTW89_ACMA][0][79] = 127,
+ [0][0][RTW89_CHILE][1][79] = 127,
+ [0][0][RTW89_QATAR][1][79] = 127,
+ [0][0][RTW89_QATAR][0][79] = 127,
+ [0][0][RTW89_UK][1][79] = 127,
+ [0][0][RTW89_UK][0][79] = 127,
+ [0][0][RTW89_FCC][1][81] = -18,
+ [0][0][RTW89_FCC][2][81] = 56,
+ [0][0][RTW89_ETSI][1][81] = 127,
+ [0][0][RTW89_ETSI][0][81] = 127,
+ [0][0][RTW89_MKK][1][81] = 127,
+ [0][0][RTW89_MKK][0][81] = 127,
+ [0][0][RTW89_IC][1][81] = -18,
+ [0][0][RTW89_KCC][1][81] = -2,
+ [0][0][RTW89_KCC][0][81] = 127,
+ [0][0][RTW89_ACMA][1][81] = 127,
+ [0][0][RTW89_ACMA][0][81] = 127,
+ [0][0][RTW89_CHILE][1][81] = 127,
+ [0][0][RTW89_QATAR][1][81] = 127,
+ [0][0][RTW89_QATAR][0][81] = 127,
+ [0][0][RTW89_UK][1][81] = 127,
+ [0][0][RTW89_UK][0][81] = 127,
+ [0][0][RTW89_FCC][1][83] = -18,
+ [0][0][RTW89_FCC][2][83] = 56,
+ [0][0][RTW89_ETSI][1][83] = 127,
+ [0][0][RTW89_ETSI][0][83] = 127,
+ [0][0][RTW89_MKK][1][83] = 127,
+ [0][0][RTW89_MKK][0][83] = 127,
+ [0][0][RTW89_IC][1][83] = -18,
+ [0][0][RTW89_KCC][1][83] = -2,
+ [0][0][RTW89_KCC][0][83] = 127,
+ [0][0][RTW89_ACMA][1][83] = 127,
+ [0][0][RTW89_ACMA][0][83] = 127,
+ [0][0][RTW89_CHILE][1][83] = 127,
+ [0][0][RTW89_QATAR][1][83] = 127,
+ [0][0][RTW89_QATAR][0][83] = 127,
+ [0][0][RTW89_UK][1][83] = 127,
+ [0][0][RTW89_UK][0][83] = 127,
+ [0][0][RTW89_FCC][1][85] = -18,
+ [0][0][RTW89_FCC][2][85] = 56,
+ [0][0][RTW89_ETSI][1][85] = 127,
+ [0][0][RTW89_ETSI][0][85] = 127,
+ [0][0][RTW89_MKK][1][85] = 127,
+ [0][0][RTW89_MKK][0][85] = 127,
+ [0][0][RTW89_IC][1][85] = -18,
+ [0][0][RTW89_KCC][1][85] = -2,
+ [0][0][RTW89_KCC][0][85] = 127,
+ [0][0][RTW89_ACMA][1][85] = 127,
+ [0][0][RTW89_ACMA][0][85] = 127,
+ [0][0][RTW89_CHILE][1][85] = 127,
+ [0][0][RTW89_QATAR][1][85] = 127,
+ [0][0][RTW89_QATAR][0][85] = 127,
+ [0][0][RTW89_UK][1][85] = 127,
+ [0][0][RTW89_UK][0][85] = 127,
+ [0][0][RTW89_FCC][1][87] = -16,
+ [0][0][RTW89_FCC][2][87] = 127,
+ [0][0][RTW89_ETSI][1][87] = 127,
+ [0][0][RTW89_ETSI][0][87] = 127,
+ [0][0][RTW89_MKK][1][87] = 127,
+ [0][0][RTW89_MKK][0][87] = 127,
+ [0][0][RTW89_IC][1][87] = -16,
+ [0][0][RTW89_KCC][1][87] = -2,
+ [0][0][RTW89_KCC][0][87] = 127,
+ [0][0][RTW89_ACMA][1][87] = 127,
+ [0][0][RTW89_ACMA][0][87] = 127,
+ [0][0][RTW89_CHILE][1][87] = 127,
+ [0][0][RTW89_QATAR][1][87] = 127,
+ [0][0][RTW89_QATAR][0][87] = 127,
+ [0][0][RTW89_UK][1][87] = 127,
+ [0][0][RTW89_UK][0][87] = 127,
+ [0][0][RTW89_FCC][1][89] = -16,
+ [0][0][RTW89_FCC][2][89] = 127,
+ [0][0][RTW89_ETSI][1][89] = 127,
+ [0][0][RTW89_ETSI][0][89] = 127,
+ [0][0][RTW89_MKK][1][89] = 127,
+ [0][0][RTW89_MKK][0][89] = 127,
+ [0][0][RTW89_IC][1][89] = -16,
+ [0][0][RTW89_KCC][1][89] = -2,
+ [0][0][RTW89_KCC][0][89] = 127,
+ [0][0][RTW89_ACMA][1][89] = 127,
+ [0][0][RTW89_ACMA][0][89] = 127,
+ [0][0][RTW89_CHILE][1][89] = 127,
+ [0][0][RTW89_QATAR][1][89] = 127,
+ [0][0][RTW89_QATAR][0][89] = 127,
+ [0][0][RTW89_UK][1][89] = 127,
+ [0][0][RTW89_UK][0][89] = 127,
+ [0][0][RTW89_FCC][1][90] = -16,
+ [0][0][RTW89_FCC][2][90] = 127,
+ [0][0][RTW89_ETSI][1][90] = 127,
+ [0][0][RTW89_ETSI][0][90] = 127,
+ [0][0][RTW89_MKK][1][90] = 127,
+ [0][0][RTW89_MKK][0][90] = 127,
+ [0][0][RTW89_IC][1][90] = -16,
+ [0][0][RTW89_KCC][1][90] = -2,
+ [0][0][RTW89_KCC][0][90] = 127,
+ [0][0][RTW89_ACMA][1][90] = 127,
+ [0][0][RTW89_ACMA][0][90] = 127,
+ [0][0][RTW89_CHILE][1][90] = 127,
+ [0][0][RTW89_QATAR][1][90] = 127,
+ [0][0][RTW89_QATAR][0][90] = 127,
+ [0][0][RTW89_UK][1][90] = 127,
+ [0][0][RTW89_UK][0][90] = 127,
+ [0][0][RTW89_FCC][1][92] = -16,
+ [0][0][RTW89_FCC][2][92] = 127,
+ [0][0][RTW89_ETSI][1][92] = 127,
+ [0][0][RTW89_ETSI][0][92] = 127,
+ [0][0][RTW89_MKK][1][92] = 127,
+ [0][0][RTW89_MKK][0][92] = 127,
+ [0][0][RTW89_IC][1][92] = -16,
+ [0][0][RTW89_KCC][1][92] = -2,
+ [0][0][RTW89_KCC][0][92] = 127,
+ [0][0][RTW89_ACMA][1][92] = 127,
+ [0][0][RTW89_ACMA][0][92] = 127,
+ [0][0][RTW89_CHILE][1][92] = 127,
+ [0][0][RTW89_QATAR][1][92] = 127,
+ [0][0][RTW89_QATAR][0][92] = 127,
+ [0][0][RTW89_UK][1][92] = 127,
+ [0][0][RTW89_UK][0][92] = 127,
+ [0][0][RTW89_FCC][1][94] = -16,
+ [0][0][RTW89_FCC][2][94] = 127,
+ [0][0][RTW89_ETSI][1][94] = 127,
+ [0][0][RTW89_ETSI][0][94] = 127,
+ [0][0][RTW89_MKK][1][94] = 127,
+ [0][0][RTW89_MKK][0][94] = 127,
+ [0][0][RTW89_IC][1][94] = -16,
+ [0][0][RTW89_KCC][1][94] = -2,
+ [0][0][RTW89_KCC][0][94] = 127,
+ [0][0][RTW89_ACMA][1][94] = 127,
+ [0][0][RTW89_ACMA][0][94] = 127,
+ [0][0][RTW89_CHILE][1][94] = 127,
+ [0][0][RTW89_QATAR][1][94] = 127,
+ [0][0][RTW89_QATAR][0][94] = 127,
+ [0][0][RTW89_UK][1][94] = 127,
+ [0][0][RTW89_UK][0][94] = 127,
+ [0][0][RTW89_FCC][1][96] = -16,
+ [0][0][RTW89_FCC][2][96] = 127,
+ [0][0][RTW89_ETSI][1][96] = 127,
+ [0][0][RTW89_ETSI][0][96] = 127,
+ [0][0][RTW89_MKK][1][96] = 127,
+ [0][0][RTW89_MKK][0][96] = 127,
+ [0][0][RTW89_IC][1][96] = -16,
+ [0][0][RTW89_KCC][1][96] = -2,
+ [0][0][RTW89_KCC][0][96] = 127,
+ [0][0][RTW89_ACMA][1][96] = 127,
+ [0][0][RTW89_ACMA][0][96] = 127,
+ [0][0][RTW89_CHILE][1][96] = 127,
+ [0][0][RTW89_QATAR][1][96] = 127,
+ [0][0][RTW89_QATAR][0][96] = 127,
+ [0][0][RTW89_UK][1][96] = 127,
+ [0][0][RTW89_UK][0][96] = 127,
+ [0][0][RTW89_FCC][1][98] = -16,
+ [0][0][RTW89_FCC][2][98] = 127,
+ [0][0][RTW89_ETSI][1][98] = 127,
+ [0][0][RTW89_ETSI][0][98] = 127,
+ [0][0][RTW89_MKK][1][98] = 127,
+ [0][0][RTW89_MKK][0][98] = 127,
+ [0][0][RTW89_IC][1][98] = -16,
+ [0][0][RTW89_KCC][1][98] = -2,
+ [0][0][RTW89_KCC][0][98] = 127,
+ [0][0][RTW89_ACMA][1][98] = 127,
+ [0][0][RTW89_ACMA][0][98] = 127,
+ [0][0][RTW89_CHILE][1][98] = 127,
+ [0][0][RTW89_QATAR][1][98] = 127,
+ [0][0][RTW89_QATAR][0][98] = 127,
+ [0][0][RTW89_UK][1][98] = 127,
+ [0][0][RTW89_UK][0][98] = 127,
+ [0][0][RTW89_FCC][1][100] = -16,
+ [0][0][RTW89_FCC][2][100] = 127,
+ [0][0][RTW89_ETSI][1][100] = 127,
+ [0][0][RTW89_ETSI][0][100] = 127,
+ [0][0][RTW89_MKK][1][100] = 127,
+ [0][0][RTW89_MKK][0][100] = 127,
+ [0][0][RTW89_IC][1][100] = -16,
+ [0][0][RTW89_KCC][1][100] = -2,
+ [0][0][RTW89_KCC][0][100] = 127,
+ [0][0][RTW89_ACMA][1][100] = 127,
+ [0][0][RTW89_ACMA][0][100] = 127,
+ [0][0][RTW89_CHILE][1][100] = 127,
+ [0][0][RTW89_QATAR][1][100] = 127,
+ [0][0][RTW89_QATAR][0][100] = 127,
+ [0][0][RTW89_UK][1][100] = 127,
+ [0][0][RTW89_UK][0][100] = 127,
+ [0][0][RTW89_FCC][1][102] = -16,
+ [0][0][RTW89_FCC][2][102] = 127,
+ [0][0][RTW89_ETSI][1][102] = 127,
+ [0][0][RTW89_ETSI][0][102] = 127,
+ [0][0][RTW89_MKK][1][102] = 127,
+ [0][0][RTW89_MKK][0][102] = 127,
+ [0][0][RTW89_IC][1][102] = -16,
+ [0][0][RTW89_KCC][1][102] = -2,
+ [0][0][RTW89_KCC][0][102] = 127,
+ [0][0][RTW89_ACMA][1][102] = 127,
+ [0][0][RTW89_ACMA][0][102] = 127,
+ [0][0][RTW89_CHILE][1][102] = 127,
+ [0][0][RTW89_QATAR][1][102] = 127,
+ [0][0][RTW89_QATAR][0][102] = 127,
+ [0][0][RTW89_UK][1][102] = 127,
+ [0][0][RTW89_UK][0][102] = 127,
+ [0][0][RTW89_FCC][1][104] = -16,
+ [0][0][RTW89_FCC][2][104] = 127,
+ [0][0][RTW89_ETSI][1][104] = 127,
+ [0][0][RTW89_ETSI][0][104] = 127,
+ [0][0][RTW89_MKK][1][104] = 127,
+ [0][0][RTW89_MKK][0][104] = 127,
+ [0][0][RTW89_IC][1][104] = -16,
+ [0][0][RTW89_KCC][1][104] = -2,
+ [0][0][RTW89_KCC][0][104] = 127,
+ [0][0][RTW89_ACMA][1][104] = 127,
+ [0][0][RTW89_ACMA][0][104] = 127,
+ [0][0][RTW89_CHILE][1][104] = 127,
+ [0][0][RTW89_QATAR][1][104] = 127,
+ [0][0][RTW89_QATAR][0][104] = 127,
+ [0][0][RTW89_UK][1][104] = 127,
+ [0][0][RTW89_UK][0][104] = 127,
+ [0][0][RTW89_FCC][1][105] = -16,
+ [0][0][RTW89_FCC][2][105] = 127,
+ [0][0][RTW89_ETSI][1][105] = 127,
+ [0][0][RTW89_ETSI][0][105] = 127,
+ [0][0][RTW89_MKK][1][105] = 127,
+ [0][0][RTW89_MKK][0][105] = 127,
+ [0][0][RTW89_IC][1][105] = -16,
+ [0][0][RTW89_KCC][1][105] = -2,
+ [0][0][RTW89_KCC][0][105] = 127,
+ [0][0][RTW89_ACMA][1][105] = 127,
+ [0][0][RTW89_ACMA][0][105] = 127,
+ [0][0][RTW89_CHILE][1][105] = 127,
+ [0][0][RTW89_QATAR][1][105] = 127,
+ [0][0][RTW89_QATAR][0][105] = 127,
+ [0][0][RTW89_UK][1][105] = 127,
+ [0][0][RTW89_UK][0][105] = 127,
+ [0][0][RTW89_FCC][1][107] = -12,
+ [0][0][RTW89_FCC][2][107] = 127,
+ [0][0][RTW89_ETSI][1][107] = 127,
+ [0][0][RTW89_ETSI][0][107] = 127,
+ [0][0][RTW89_MKK][1][107] = 127,
+ [0][0][RTW89_MKK][0][107] = 127,
+ [0][0][RTW89_IC][1][107] = -12,
+ [0][0][RTW89_KCC][1][107] = -2,
+ [0][0][RTW89_KCC][0][107] = 127,
+ [0][0][RTW89_ACMA][1][107] = 127,
+ [0][0][RTW89_ACMA][0][107] = 127,
+ [0][0][RTW89_CHILE][1][107] = 127,
+ [0][0][RTW89_QATAR][1][107] = 127,
+ [0][0][RTW89_QATAR][0][107] = 127,
+ [0][0][RTW89_UK][1][107] = 127,
+ [0][0][RTW89_UK][0][107] = 127,
+ [0][0][RTW89_FCC][1][109] = -12,
+ [0][0][RTW89_FCC][2][109] = 127,
+ [0][0][RTW89_ETSI][1][109] = 127,
+ [0][0][RTW89_ETSI][0][109] = 127,
+ [0][0][RTW89_MKK][1][109] = 127,
+ [0][0][RTW89_MKK][0][109] = 127,
+ [0][0][RTW89_IC][1][109] = -12,
+ [0][0][RTW89_KCC][1][109] = 127,
+ [0][0][RTW89_KCC][0][109] = 127,
+ [0][0][RTW89_ACMA][1][109] = 127,
+ [0][0][RTW89_ACMA][0][109] = 127,
+ [0][0][RTW89_CHILE][1][109] = 127,
+ [0][0][RTW89_QATAR][1][109] = 127,
+ [0][0][RTW89_QATAR][0][109] = 127,
+ [0][0][RTW89_UK][1][109] = 127,
+ [0][0][RTW89_UK][0][109] = 127,
+ [0][0][RTW89_FCC][1][111] = 127,
+ [0][0][RTW89_FCC][2][111] = 127,
+ [0][0][RTW89_ETSI][1][111] = 127,
+ [0][0][RTW89_ETSI][0][111] = 127,
+ [0][0][RTW89_MKK][1][111] = 127,
+ [0][0][RTW89_MKK][0][111] = 127,
+ [0][0][RTW89_IC][1][111] = 127,
+ [0][0][RTW89_KCC][1][111] = 127,
+ [0][0][RTW89_KCC][0][111] = 127,
+ [0][0][RTW89_ACMA][1][111] = 127,
+ [0][0][RTW89_ACMA][0][111] = 127,
+ [0][0][RTW89_CHILE][1][111] = 127,
+ [0][0][RTW89_QATAR][1][111] = 127,
+ [0][0][RTW89_QATAR][0][111] = 127,
+ [0][0][RTW89_UK][1][111] = 127,
+ [0][0][RTW89_UK][0][111] = 127,
+ [0][0][RTW89_FCC][1][113] = 127,
+ [0][0][RTW89_FCC][2][113] = 127,
+ [0][0][RTW89_ETSI][1][113] = 127,
+ [0][0][RTW89_ETSI][0][113] = 127,
+ [0][0][RTW89_MKK][1][113] = 127,
+ [0][0][RTW89_MKK][0][113] = 127,
+ [0][0][RTW89_IC][1][113] = 127,
+ [0][0][RTW89_KCC][1][113] = 127,
+ [0][0][RTW89_KCC][0][113] = 127,
+ [0][0][RTW89_ACMA][1][113] = 127,
+ [0][0][RTW89_ACMA][0][113] = 127,
+ [0][0][RTW89_CHILE][1][113] = 127,
+ [0][0][RTW89_QATAR][1][113] = 127,
+ [0][0][RTW89_QATAR][0][113] = 127,
+ [0][0][RTW89_UK][1][113] = 127,
+ [0][0][RTW89_UK][0][113] = 127,
+ [0][0][RTW89_FCC][1][115] = 127,
+ [0][0][RTW89_FCC][2][115] = 127,
+ [0][0][RTW89_ETSI][1][115] = 127,
+ [0][0][RTW89_ETSI][0][115] = 127,
+ [0][0][RTW89_MKK][1][115] = 127,
+ [0][0][RTW89_MKK][0][115] = 127,
+ [0][0][RTW89_IC][1][115] = 127,
+ [0][0][RTW89_KCC][1][115] = 127,
+ [0][0][RTW89_KCC][0][115] = 127,
+ [0][0][RTW89_ACMA][1][115] = 127,
+ [0][0][RTW89_ACMA][0][115] = 127,
+ [0][0][RTW89_CHILE][1][115] = 127,
+ [0][0][RTW89_QATAR][1][115] = 127,
+ [0][0][RTW89_QATAR][0][115] = 127,
+ [0][0][RTW89_UK][1][115] = 127,
+ [0][0][RTW89_UK][0][115] = 127,
+ [0][0][RTW89_FCC][1][117] = 127,
+ [0][0][RTW89_FCC][2][117] = 127,
+ [0][0][RTW89_ETSI][1][117] = 127,
+ [0][0][RTW89_ETSI][0][117] = 127,
+ [0][0][RTW89_MKK][1][117] = 127,
+ [0][0][RTW89_MKK][0][117] = 127,
+ [0][0][RTW89_IC][1][117] = 127,
+ [0][0][RTW89_KCC][1][117] = 127,
+ [0][0][RTW89_KCC][0][117] = 127,
+ [0][0][RTW89_ACMA][1][117] = 127,
+ [0][0][RTW89_ACMA][0][117] = 127,
+ [0][0][RTW89_CHILE][1][117] = 127,
+ [0][0][RTW89_QATAR][1][117] = 127,
+ [0][0][RTW89_QATAR][0][117] = 127,
+ [0][0][RTW89_UK][1][117] = 127,
+ [0][0][RTW89_UK][0][117] = 127,
+ [0][0][RTW89_FCC][1][119] = 127,
+ [0][0][RTW89_FCC][2][119] = 127,
+ [0][0][RTW89_ETSI][1][119] = 127,
+ [0][0][RTW89_ETSI][0][119] = 127,
+ [0][0][RTW89_MKK][1][119] = 127,
+ [0][0][RTW89_MKK][0][119] = 127,
+ [0][0][RTW89_IC][1][119] = 127,
+ [0][0][RTW89_KCC][1][119] = 127,
+ [0][0][RTW89_KCC][0][119] = 127,
+ [0][0][RTW89_ACMA][1][119] = 127,
+ [0][0][RTW89_ACMA][0][119] = 127,
+ [0][0][RTW89_CHILE][1][119] = 127,
+ [0][0][RTW89_QATAR][1][119] = 127,
+ [0][0][RTW89_QATAR][0][119] = 127,
+ [0][0][RTW89_UK][1][119] = 127,
+ [0][0][RTW89_UK][0][119] = 127,
+ [0][1][RTW89_FCC][1][0] = -40,
+ [0][1][RTW89_FCC][2][0] = 32,
+ [0][1][RTW89_ETSI][1][0] = 20,
+ [0][1][RTW89_ETSI][0][0] = -18,
+ [0][1][RTW89_MKK][1][0] = 18,
+ [0][1][RTW89_MKK][0][0] = -20,
+ [0][1][RTW89_IC][1][0] = -40,
+ [0][1][RTW89_KCC][1][0] = -14,
+ [0][1][RTW89_KCC][0][0] = -14,
+ [0][1][RTW89_ACMA][1][0] = 20,
+ [0][1][RTW89_ACMA][0][0] = -18,
+ [0][1][RTW89_CHILE][1][0] = -40,
+ [0][1][RTW89_QATAR][1][0] = 20,
+ [0][1][RTW89_QATAR][0][0] = -18,
+ [0][1][RTW89_UK][1][0] = 20,
+ [0][1][RTW89_UK][0][0] = -18,
+ [0][1][RTW89_FCC][1][2] = -40,
+ [0][1][RTW89_FCC][2][2] = 32,
+ [0][1][RTW89_ETSI][1][2] = 20,
+ [0][1][RTW89_ETSI][0][2] = -18,
+ [0][1][RTW89_MKK][1][2] = 18,
+ [0][1][RTW89_MKK][0][2] = -22,
+ [0][1][RTW89_IC][1][2] = -40,
+ [0][1][RTW89_KCC][1][2] = -14,
+ [0][1][RTW89_KCC][0][2] = -14,
+ [0][1][RTW89_ACMA][1][2] = 20,
+ [0][1][RTW89_ACMA][0][2] = -18,
+ [0][1][RTW89_CHILE][1][2] = -40,
+ [0][1][RTW89_QATAR][1][2] = 20,
+ [0][1][RTW89_QATAR][0][2] = -18,
+ [0][1][RTW89_UK][1][2] = 20,
+ [0][1][RTW89_UK][0][2] = -18,
+ [0][1][RTW89_FCC][1][4] = -40,
+ [0][1][RTW89_FCC][2][4] = 32,
+ [0][1][RTW89_ETSI][1][4] = 20,
+ [0][1][RTW89_ETSI][0][4] = -18,
+ [0][1][RTW89_MKK][1][4] = 18,
+ [0][1][RTW89_MKK][0][4] = -22,
+ [0][1][RTW89_IC][1][4] = -40,
+ [0][1][RTW89_KCC][1][4] = -14,
+ [0][1][RTW89_KCC][0][4] = -14,
+ [0][1][RTW89_ACMA][1][4] = 20,
+ [0][1][RTW89_ACMA][0][4] = -18,
+ [0][1][RTW89_CHILE][1][4] = -40,
+ [0][1][RTW89_QATAR][1][4] = 20,
+ [0][1][RTW89_QATAR][0][4] = -18,
+ [0][1][RTW89_UK][1][4] = 20,
+ [0][1][RTW89_UK][0][4] = -18,
+ [0][1][RTW89_FCC][1][6] = -40,
+ [0][1][RTW89_FCC][2][6] = 32,
+ [0][1][RTW89_ETSI][1][6] = 20,
+ [0][1][RTW89_ETSI][0][6] = -18,
+ [0][1][RTW89_MKK][1][6] = 18,
+ [0][1][RTW89_MKK][0][6] = -22,
+ [0][1][RTW89_IC][1][6] = -40,
+ [0][1][RTW89_KCC][1][6] = -14,
+ [0][1][RTW89_KCC][0][6] = -14,
+ [0][1][RTW89_ACMA][1][6] = 20,
+ [0][1][RTW89_ACMA][0][6] = -18,
+ [0][1][RTW89_CHILE][1][6] = -40,
+ [0][1][RTW89_QATAR][1][6] = 20,
+ [0][1][RTW89_QATAR][0][6] = -18,
+ [0][1][RTW89_UK][1][6] = 20,
+ [0][1][RTW89_UK][0][6] = -18,
+ [0][1][RTW89_FCC][1][8] = -40,
+ [0][1][RTW89_FCC][2][8] = 32,
+ [0][1][RTW89_ETSI][1][8] = 20,
+ [0][1][RTW89_ETSI][0][8] = -18,
+ [0][1][RTW89_MKK][1][8] = 18,
+ [0][1][RTW89_MKK][0][8] = -22,
+ [0][1][RTW89_IC][1][8] = -40,
+ [0][1][RTW89_KCC][1][8] = -14,
+ [0][1][RTW89_KCC][0][8] = -14,
+ [0][1][RTW89_ACMA][1][8] = 20,
+ [0][1][RTW89_ACMA][0][8] = -18,
+ [0][1][RTW89_CHILE][1][8] = -40,
+ [0][1][RTW89_QATAR][1][8] = 20,
+ [0][1][RTW89_QATAR][0][8] = -18,
+ [0][1][RTW89_UK][1][8] = 20,
+ [0][1][RTW89_UK][0][8] = -18,
+ [0][1][RTW89_FCC][1][10] = -40,
+ [0][1][RTW89_FCC][2][10] = 32,
+ [0][1][RTW89_ETSI][1][10] = 20,
+ [0][1][RTW89_ETSI][0][10] = -18,
+ [0][1][RTW89_MKK][1][10] = 18,
+ [0][1][RTW89_MKK][0][10] = -22,
+ [0][1][RTW89_IC][1][10] = -40,
+ [0][1][RTW89_KCC][1][10] = -14,
+ [0][1][RTW89_KCC][0][10] = -14,
+ [0][1][RTW89_ACMA][1][10] = 20,
+ [0][1][RTW89_ACMA][0][10] = -18,
+ [0][1][RTW89_CHILE][1][10] = -40,
+ [0][1][RTW89_QATAR][1][10] = 20,
+ [0][1][RTW89_QATAR][0][10] = -18,
+ [0][1][RTW89_UK][1][10] = 20,
+ [0][1][RTW89_UK][0][10] = -18,
+ [0][1][RTW89_FCC][1][12] = -40,
+ [0][1][RTW89_FCC][2][12] = 32,
+ [0][1][RTW89_ETSI][1][12] = 20,
+ [0][1][RTW89_ETSI][0][12] = -18,
+ [0][1][RTW89_MKK][1][12] = 18,
+ [0][1][RTW89_MKK][0][12] = -22,
+ [0][1][RTW89_IC][1][12] = -40,
+ [0][1][RTW89_KCC][1][12] = -14,
+ [0][1][RTW89_KCC][0][12] = -14,
+ [0][1][RTW89_ACMA][1][12] = 20,
+ [0][1][RTW89_ACMA][0][12] = -18,
+ [0][1][RTW89_CHILE][1][12] = -40,
+ [0][1][RTW89_QATAR][1][12] = 20,
+ [0][1][RTW89_QATAR][0][12] = -18,
+ [0][1][RTW89_UK][1][12] = 20,
+ [0][1][RTW89_UK][0][12] = -18,
+ [0][1][RTW89_FCC][1][14] = -40,
+ [0][1][RTW89_FCC][2][14] = 32,
+ [0][1][RTW89_ETSI][1][14] = 20,
+ [0][1][RTW89_ETSI][0][14] = -18,
+ [0][1][RTW89_MKK][1][14] = 18,
+ [0][1][RTW89_MKK][0][14] = -22,
+ [0][1][RTW89_IC][1][14] = -40,
+ [0][1][RTW89_KCC][1][14] = -14,
+ [0][1][RTW89_KCC][0][14] = -14,
+ [0][1][RTW89_ACMA][1][14] = 20,
+ [0][1][RTW89_ACMA][0][14] = -18,
+ [0][1][RTW89_CHILE][1][14] = -40,
+ [0][1][RTW89_QATAR][1][14] = 20,
+ [0][1][RTW89_QATAR][0][14] = -18,
+ [0][1][RTW89_UK][1][14] = 20,
+ [0][1][RTW89_UK][0][14] = -18,
+ [0][1][RTW89_FCC][1][15] = -40,
+ [0][1][RTW89_FCC][2][15] = 32,
+ [0][1][RTW89_ETSI][1][15] = 20,
+ [0][1][RTW89_ETSI][0][15] = -18,
+ [0][1][RTW89_MKK][1][15] = 18,
+ [0][1][RTW89_MKK][0][15] = -22,
+ [0][1][RTW89_IC][1][15] = -40,
+ [0][1][RTW89_KCC][1][15] = -14,
+ [0][1][RTW89_KCC][0][15] = -14,
+ [0][1][RTW89_ACMA][1][15] = 20,
+ [0][1][RTW89_ACMA][0][15] = -18,
+ [0][1][RTW89_CHILE][1][15] = -40,
+ [0][1][RTW89_QATAR][1][15] = 20,
+ [0][1][RTW89_QATAR][0][15] = -18,
+ [0][1][RTW89_UK][1][15] = 20,
+ [0][1][RTW89_UK][0][15] = -18,
+ [0][1][RTW89_FCC][1][17] = -40,
+ [0][1][RTW89_FCC][2][17] = 32,
+ [0][1][RTW89_ETSI][1][17] = 20,
+ [0][1][RTW89_ETSI][0][17] = -18,
+ [0][1][RTW89_MKK][1][17] = 18,
+ [0][1][RTW89_MKK][0][17] = -22,
+ [0][1][RTW89_IC][1][17] = -40,
+ [0][1][RTW89_KCC][1][17] = -14,
+ [0][1][RTW89_KCC][0][17] = -14,
+ [0][1][RTW89_ACMA][1][17] = 20,
+ [0][1][RTW89_ACMA][0][17] = -18,
+ [0][1][RTW89_CHILE][1][17] = -40,
+ [0][1][RTW89_QATAR][1][17] = 20,
+ [0][1][RTW89_QATAR][0][17] = -18,
+ [0][1][RTW89_UK][1][17] = 20,
+ [0][1][RTW89_UK][0][17] = -18,
+ [0][1][RTW89_FCC][1][19] = -40,
+ [0][1][RTW89_FCC][2][19] = 32,
+ [0][1][RTW89_ETSI][1][19] = 20,
+ [0][1][RTW89_ETSI][0][19] = -18,
+ [0][1][RTW89_MKK][1][19] = 18,
+ [0][1][RTW89_MKK][0][19] = -22,
+ [0][1][RTW89_IC][1][19] = -40,
+ [0][1][RTW89_KCC][1][19] = -14,
+ [0][1][RTW89_KCC][0][19] = -14,
+ [0][1][RTW89_ACMA][1][19] = 20,
+ [0][1][RTW89_ACMA][0][19] = -18,
+ [0][1][RTW89_CHILE][1][19] = -40,
+ [0][1][RTW89_QATAR][1][19] = 20,
+ [0][1][RTW89_QATAR][0][19] = -18,
+ [0][1][RTW89_UK][1][19] = 20,
+ [0][1][RTW89_UK][0][19] = -18,
+ [0][1][RTW89_FCC][1][21] = -40,
+ [0][1][RTW89_FCC][2][21] = 32,
+ [0][1][RTW89_ETSI][1][21] = 20,
+ [0][1][RTW89_ETSI][0][21] = -18,
+ [0][1][RTW89_MKK][1][21] = 18,
+ [0][1][RTW89_MKK][0][21] = -22,
+ [0][1][RTW89_IC][1][21] = -40,
+ [0][1][RTW89_KCC][1][21] = -14,
+ [0][1][RTW89_KCC][0][21] = -14,
+ [0][1][RTW89_ACMA][1][21] = 20,
+ [0][1][RTW89_ACMA][0][21] = -18,
+ [0][1][RTW89_CHILE][1][21] = -40,
+ [0][1][RTW89_QATAR][1][21] = 20,
+ [0][1][RTW89_QATAR][0][21] = -18,
+ [0][1][RTW89_UK][1][21] = 20,
+ [0][1][RTW89_UK][0][21] = -18,
+ [0][1][RTW89_FCC][1][23] = -40,
+ [0][1][RTW89_FCC][2][23] = 32,
+ [0][1][RTW89_ETSI][1][23] = 20,
+ [0][1][RTW89_ETSI][0][23] = -18,
+ [0][1][RTW89_MKK][1][23] = 18,
+ [0][1][RTW89_MKK][0][23] = -22,
+ [0][1][RTW89_IC][1][23] = -40,
+ [0][1][RTW89_KCC][1][23] = -14,
+ [0][1][RTW89_KCC][0][23] = -14,
+ [0][1][RTW89_ACMA][1][23] = 20,
+ [0][1][RTW89_ACMA][0][23] = -18,
+ [0][1][RTW89_CHILE][1][23] = -40,
+ [0][1][RTW89_QATAR][1][23] = 20,
+ [0][1][RTW89_QATAR][0][23] = -18,
+ [0][1][RTW89_UK][1][23] = 20,
+ [0][1][RTW89_UK][0][23] = -18,
+ [0][1][RTW89_FCC][1][25] = -40,
+ [0][1][RTW89_FCC][2][25] = 32,
+ [0][1][RTW89_ETSI][1][25] = 20,
+ [0][1][RTW89_ETSI][0][25] = -18,
+ [0][1][RTW89_MKK][1][25] = -4,
+ [0][1][RTW89_MKK][0][25] = -22,
+ [0][1][RTW89_IC][1][25] = -40,
+ [0][1][RTW89_KCC][1][25] = -14,
+ [0][1][RTW89_KCC][0][25] = -14,
+ [0][1][RTW89_ACMA][1][25] = 20,
+ [0][1][RTW89_ACMA][0][25] = -18,
+ [0][1][RTW89_CHILE][1][25] = -40,
+ [0][1][RTW89_QATAR][1][25] = 20,
+ [0][1][RTW89_QATAR][0][25] = -18,
+ [0][1][RTW89_UK][1][25] = 20,
+ [0][1][RTW89_UK][0][25] = -18,
+ [0][1][RTW89_FCC][1][27] = -40,
+ [0][1][RTW89_FCC][2][27] = 32,
+ [0][1][RTW89_ETSI][1][27] = 20,
+ [0][1][RTW89_ETSI][0][27] = -18,
+ [0][1][RTW89_MKK][1][27] = -4,
+ [0][1][RTW89_MKK][0][27] = -22,
+ [0][1][RTW89_IC][1][27] = -40,
+ [0][1][RTW89_KCC][1][27] = -14,
+ [0][1][RTW89_KCC][0][27] = -14,
+ [0][1][RTW89_ACMA][1][27] = 20,
+ [0][1][RTW89_ACMA][0][27] = -18,
+ [0][1][RTW89_CHILE][1][27] = -40,
+ [0][1][RTW89_QATAR][1][27] = 20,
+ [0][1][RTW89_QATAR][0][27] = -18,
+ [0][1][RTW89_UK][1][27] = 20,
+ [0][1][RTW89_UK][0][27] = -18,
+ [0][1][RTW89_FCC][1][29] = -40,
+ [0][1][RTW89_FCC][2][29] = 32,
+ [0][1][RTW89_ETSI][1][29] = 20,
+ [0][1][RTW89_ETSI][0][29] = -18,
+ [0][1][RTW89_MKK][1][29] = -4,
+ [0][1][RTW89_MKK][0][29] = -22,
+ [0][1][RTW89_IC][1][29] = -40,
+ [0][1][RTW89_KCC][1][29] = -14,
+ [0][1][RTW89_KCC][0][29] = -14,
+ [0][1][RTW89_ACMA][1][29] = 20,
+ [0][1][RTW89_ACMA][0][29] = -18,
+ [0][1][RTW89_CHILE][1][29] = -40,
+ [0][1][RTW89_QATAR][1][29] = 20,
+ [0][1][RTW89_QATAR][0][29] = -18,
+ [0][1][RTW89_UK][1][29] = 20,
+ [0][1][RTW89_UK][0][29] = -18,
+ [0][1][RTW89_FCC][1][30] = -40,
+ [0][1][RTW89_FCC][2][30] = 32,
+ [0][1][RTW89_ETSI][1][30] = 20,
+ [0][1][RTW89_ETSI][0][30] = -18,
+ [0][1][RTW89_MKK][1][30] = -4,
+ [0][1][RTW89_MKK][0][30] = -22,
+ [0][1][RTW89_IC][1][30] = -40,
+ [0][1][RTW89_KCC][1][30] = -14,
+ [0][1][RTW89_KCC][0][30] = -14,
+ [0][1][RTW89_ACMA][1][30] = 20,
+ [0][1][RTW89_ACMA][0][30] = -18,
+ [0][1][RTW89_CHILE][1][30] = -40,
+ [0][1][RTW89_QATAR][1][30] = 20,
+ [0][1][RTW89_QATAR][0][30] = -18,
+ [0][1][RTW89_UK][1][30] = 20,
+ [0][1][RTW89_UK][0][30] = -18,
+ [0][1][RTW89_FCC][1][32] = -40,
+ [0][1][RTW89_FCC][2][32] = 32,
+ [0][1][RTW89_ETSI][1][32] = 20,
+ [0][1][RTW89_ETSI][0][32] = -18,
+ [0][1][RTW89_MKK][1][32] = -4,
+ [0][1][RTW89_MKK][0][32] = -22,
+ [0][1][RTW89_IC][1][32] = -40,
+ [0][1][RTW89_KCC][1][32] = -14,
+ [0][1][RTW89_KCC][0][32] = -14,
+ [0][1][RTW89_ACMA][1][32] = 20,
+ [0][1][RTW89_ACMA][0][32] = -18,
+ [0][1][RTW89_CHILE][1][32] = -40,
+ [0][1][RTW89_QATAR][1][32] = 20,
+ [0][1][RTW89_QATAR][0][32] = -18,
+ [0][1][RTW89_UK][1][32] = 20,
+ [0][1][RTW89_UK][0][32] = -18,
+ [0][1][RTW89_FCC][1][34] = -40,
+ [0][1][RTW89_FCC][2][34] = 32,
+ [0][1][RTW89_ETSI][1][34] = 20,
+ [0][1][RTW89_ETSI][0][34] = -18,
+ [0][1][RTW89_MKK][1][34] = -4,
+ [0][1][RTW89_MKK][0][34] = -22,
+ [0][1][RTW89_IC][1][34] = -40,
+ [0][1][RTW89_KCC][1][34] = -14,
+ [0][1][RTW89_KCC][0][34] = -14,
+ [0][1][RTW89_ACMA][1][34] = 20,
+ [0][1][RTW89_ACMA][0][34] = -18,
+ [0][1][RTW89_CHILE][1][34] = -40,
+ [0][1][RTW89_QATAR][1][34] = 20,
+ [0][1][RTW89_QATAR][0][34] = -18,
+ [0][1][RTW89_UK][1][34] = 20,
+ [0][1][RTW89_UK][0][34] = -18,
+ [0][1][RTW89_FCC][1][36] = -40,
+ [0][1][RTW89_FCC][2][36] = 32,
+ [0][1][RTW89_ETSI][1][36] = 20,
+ [0][1][RTW89_ETSI][0][36] = -18,
+ [0][1][RTW89_MKK][1][36] = -4,
+ [0][1][RTW89_MKK][0][36] = -22,
+ [0][1][RTW89_IC][1][36] = -40,
+ [0][1][RTW89_KCC][1][36] = -14,
+ [0][1][RTW89_KCC][0][36] = -14,
+ [0][1][RTW89_ACMA][1][36] = 20,
+ [0][1][RTW89_ACMA][0][36] = -18,
+ [0][1][RTW89_CHILE][1][36] = -40,
+ [0][1][RTW89_QATAR][1][36] = 20,
+ [0][1][RTW89_QATAR][0][36] = -18,
+ [0][1][RTW89_UK][1][36] = 20,
+ [0][1][RTW89_UK][0][36] = -18,
+ [0][1][RTW89_FCC][1][38] = -40,
+ [0][1][RTW89_FCC][2][38] = 32,
+ [0][1][RTW89_ETSI][1][38] = 20,
+ [0][1][RTW89_ETSI][0][38] = -18,
+ [0][1][RTW89_MKK][1][38] = -4,
+ [0][1][RTW89_MKK][0][38] = -22,
+ [0][1][RTW89_IC][1][38] = -40,
+ [0][1][RTW89_KCC][1][38] = -14,
+ [0][1][RTW89_KCC][0][38] = -14,
+ [0][1][RTW89_ACMA][1][38] = 20,
+ [0][1][RTW89_ACMA][0][38] = -18,
+ [0][1][RTW89_CHILE][1][38] = -40,
+ [0][1][RTW89_QATAR][1][38] = 20,
+ [0][1][RTW89_QATAR][0][38] = -18,
+ [0][1][RTW89_UK][1][38] = 20,
+ [0][1][RTW89_UK][0][38] = -18,
+ [0][1][RTW89_FCC][1][40] = -40,
+ [0][1][RTW89_FCC][2][40] = 32,
+ [0][1][RTW89_ETSI][1][40] = 20,
+ [0][1][RTW89_ETSI][0][40] = -18,
+ [0][1][RTW89_MKK][1][40] = -4,
+ [0][1][RTW89_MKK][0][40] = -22,
+ [0][1][RTW89_IC][1][40] = -40,
+ [0][1][RTW89_KCC][1][40] = -14,
+ [0][1][RTW89_KCC][0][40] = -14,
+ [0][1][RTW89_ACMA][1][40] = 20,
+ [0][1][RTW89_ACMA][0][40] = -18,
+ [0][1][RTW89_CHILE][1][40] = -40,
+ [0][1][RTW89_QATAR][1][40] = 20,
+ [0][1][RTW89_QATAR][0][40] = -18,
+ [0][1][RTW89_UK][1][40] = 20,
+ [0][1][RTW89_UK][0][40] = -18,
+ [0][1][RTW89_FCC][1][42] = -40,
+ [0][1][RTW89_FCC][2][42] = 32,
+ [0][1][RTW89_ETSI][1][42] = 20,
+ [0][1][RTW89_ETSI][0][42] = -18,
+ [0][1][RTW89_MKK][1][42] = -4,
+ [0][1][RTW89_MKK][0][42] = -22,
+ [0][1][RTW89_IC][1][42] = -40,
+ [0][1][RTW89_KCC][1][42] = -14,
+ [0][1][RTW89_KCC][0][42] = -14,
+ [0][1][RTW89_ACMA][1][42] = 20,
+ [0][1][RTW89_ACMA][0][42] = -18,
+ [0][1][RTW89_CHILE][1][42] = -40,
+ [0][1][RTW89_QATAR][1][42] = 20,
+ [0][1][RTW89_QATAR][0][42] = -18,
+ [0][1][RTW89_UK][1][42] = 20,
+ [0][1][RTW89_UK][0][42] = -18,
+ [0][1][RTW89_FCC][1][44] = -40,
+ [0][1][RTW89_FCC][2][44] = 32,
+ [0][1][RTW89_ETSI][1][44] = 20,
+ [0][1][RTW89_ETSI][0][44] = -18,
+ [0][1][RTW89_MKK][1][44] = -4,
+ [0][1][RTW89_MKK][0][44] = -22,
+ [0][1][RTW89_IC][1][44] = -40,
+ [0][1][RTW89_KCC][1][44] = -14,
+ [0][1][RTW89_KCC][0][44] = -14,
+ [0][1][RTW89_ACMA][1][44] = 20,
+ [0][1][RTW89_ACMA][0][44] = -18,
+ [0][1][RTW89_CHILE][1][44] = -40,
+ [0][1][RTW89_QATAR][1][44] = 20,
+ [0][1][RTW89_QATAR][0][44] = -18,
+ [0][1][RTW89_UK][1][44] = 20,
+ [0][1][RTW89_UK][0][44] = -18,
+ [0][1][RTW89_FCC][1][45] = -40,
+ [0][1][RTW89_FCC][2][45] = 127,
+ [0][1][RTW89_ETSI][1][45] = 127,
+ [0][1][RTW89_ETSI][0][45] = 127,
+ [0][1][RTW89_MKK][1][45] = 127,
+ [0][1][RTW89_MKK][0][45] = 127,
+ [0][1][RTW89_IC][1][45] = -40,
+ [0][1][RTW89_KCC][1][45] = -14,
+ [0][1][RTW89_KCC][0][45] = 127,
+ [0][1][RTW89_ACMA][1][45] = 127,
+ [0][1][RTW89_ACMA][0][45] = 127,
+ [0][1][RTW89_CHILE][1][45] = 127,
+ [0][1][RTW89_QATAR][1][45] = 127,
+ [0][1][RTW89_QATAR][0][45] = 127,
+ [0][1][RTW89_UK][1][45] = 127,
+ [0][1][RTW89_UK][0][45] = 127,
+ [0][1][RTW89_FCC][1][47] = -40,
+ [0][1][RTW89_FCC][2][47] = 127,
+ [0][1][RTW89_ETSI][1][47] = 127,
+ [0][1][RTW89_ETSI][0][47] = 127,
+ [0][1][RTW89_MKK][1][47] = 127,
+ [0][1][RTW89_MKK][0][47] = 127,
+ [0][1][RTW89_IC][1][47] = -40,
+ [0][1][RTW89_KCC][1][47] = -14,
+ [0][1][RTW89_KCC][0][47] = 127,
+ [0][1][RTW89_ACMA][1][47] = 127,
+ [0][1][RTW89_ACMA][0][47] = 127,
+ [0][1][RTW89_CHILE][1][47] = 127,
+ [0][1][RTW89_QATAR][1][47] = 127,
+ [0][1][RTW89_QATAR][0][47] = 127,
+ [0][1][RTW89_UK][1][47] = 127,
+ [0][1][RTW89_UK][0][47] = 127,
+ [0][1][RTW89_FCC][1][49] = -40,
+ [0][1][RTW89_FCC][2][49] = 127,
+ [0][1][RTW89_ETSI][1][49] = 127,
+ [0][1][RTW89_ETSI][0][49] = 127,
+ [0][1][RTW89_MKK][1][49] = 127,
+ [0][1][RTW89_MKK][0][49] = 127,
+ [0][1][RTW89_IC][1][49] = -40,
+ [0][1][RTW89_KCC][1][49] = -14,
+ [0][1][RTW89_KCC][0][49] = 127,
+ [0][1][RTW89_ACMA][1][49] = 127,
+ [0][1][RTW89_ACMA][0][49] = 127,
+ [0][1][RTW89_CHILE][1][49] = 127,
+ [0][1][RTW89_QATAR][1][49] = 127,
+ [0][1][RTW89_QATAR][0][49] = 127,
+ [0][1][RTW89_UK][1][49] = 127,
+ [0][1][RTW89_UK][0][49] = 127,
+ [0][1][RTW89_FCC][1][51] = -40,
+ [0][1][RTW89_FCC][2][51] = 127,
+ [0][1][RTW89_ETSI][1][51] = 127,
+ [0][1][RTW89_ETSI][0][51] = 127,
+ [0][1][RTW89_MKK][1][51] = 127,
+ [0][1][RTW89_MKK][0][51] = 127,
+ [0][1][RTW89_IC][1][51] = -40,
+ [0][1][RTW89_KCC][1][51] = -14,
+ [0][1][RTW89_KCC][0][51] = 127,
+ [0][1][RTW89_ACMA][1][51] = 127,
+ [0][1][RTW89_ACMA][0][51] = 127,
+ [0][1][RTW89_CHILE][1][51] = 127,
+ [0][1][RTW89_QATAR][1][51] = 127,
+ [0][1][RTW89_QATAR][0][51] = 127,
+ [0][1][RTW89_UK][1][51] = 127,
+ [0][1][RTW89_UK][0][51] = 127,
+ [0][1][RTW89_FCC][1][53] = -40,
+ [0][1][RTW89_FCC][2][53] = 127,
+ [0][1][RTW89_ETSI][1][53] = 127,
+ [0][1][RTW89_ETSI][0][53] = 127,
+ [0][1][RTW89_MKK][1][53] = 127,
+ [0][1][RTW89_MKK][0][53] = 127,
+ [0][1][RTW89_IC][1][53] = -40,
+ [0][1][RTW89_KCC][1][53] = -14,
+ [0][1][RTW89_KCC][0][53] = 127,
+ [0][1][RTW89_ACMA][1][53] = 127,
+ [0][1][RTW89_ACMA][0][53] = 127,
+ [0][1][RTW89_CHILE][1][53] = 127,
+ [0][1][RTW89_QATAR][1][53] = 127,
+ [0][1][RTW89_QATAR][0][53] = 127,
+ [0][1][RTW89_UK][1][53] = 127,
+ [0][1][RTW89_UK][0][53] = 127,
+ [0][1][RTW89_FCC][1][55] = -40,
+ [0][1][RTW89_FCC][2][55] = 30,
+ [0][1][RTW89_ETSI][1][55] = 127,
+ [0][1][RTW89_ETSI][0][55] = 127,
+ [0][1][RTW89_MKK][1][55] = 127,
+ [0][1][RTW89_MKK][0][55] = 127,
+ [0][1][RTW89_IC][1][55] = -40,
+ [0][1][RTW89_KCC][1][55] = -14,
+ [0][1][RTW89_KCC][0][55] = 127,
+ [0][1][RTW89_ACMA][1][55] = 127,
+ [0][1][RTW89_ACMA][0][55] = 127,
+ [0][1][RTW89_CHILE][1][55] = 127,
+ [0][1][RTW89_QATAR][1][55] = 127,
+ [0][1][RTW89_QATAR][0][55] = 127,
+ [0][1][RTW89_UK][1][55] = 127,
+ [0][1][RTW89_UK][0][55] = 127,
+ [0][1][RTW89_FCC][1][57] = -40,
+ [0][1][RTW89_FCC][2][57] = 30,
+ [0][1][RTW89_ETSI][1][57] = 127,
+ [0][1][RTW89_ETSI][0][57] = 127,
+ [0][1][RTW89_MKK][1][57] = 127,
+ [0][1][RTW89_MKK][0][57] = 127,
+ [0][1][RTW89_IC][1][57] = -40,
+ [0][1][RTW89_KCC][1][57] = -14,
+ [0][1][RTW89_KCC][0][57] = 127,
+ [0][1][RTW89_ACMA][1][57] = 127,
+ [0][1][RTW89_ACMA][0][57] = 127,
+ [0][1][RTW89_CHILE][1][57] = 127,
+ [0][1][RTW89_QATAR][1][57] = 127,
+ [0][1][RTW89_QATAR][0][57] = 127,
+ [0][1][RTW89_UK][1][57] = 127,
+ [0][1][RTW89_UK][0][57] = 127,
+ [0][1][RTW89_FCC][1][59] = -40,
+ [0][1][RTW89_FCC][2][59] = 30,
+ [0][1][RTW89_ETSI][1][59] = 127,
+ [0][1][RTW89_ETSI][0][59] = 127,
+ [0][1][RTW89_MKK][1][59] = 127,
+ [0][1][RTW89_MKK][0][59] = 127,
+ [0][1][RTW89_IC][1][59] = -40,
+ [0][1][RTW89_KCC][1][59] = -14,
+ [0][1][RTW89_KCC][0][59] = 127,
+ [0][1][RTW89_ACMA][1][59] = 127,
+ [0][1][RTW89_ACMA][0][59] = 127,
+ [0][1][RTW89_CHILE][1][59] = 127,
+ [0][1][RTW89_QATAR][1][59] = 127,
+ [0][1][RTW89_QATAR][0][59] = 127,
+ [0][1][RTW89_UK][1][59] = 127,
+ [0][1][RTW89_UK][0][59] = 127,
+ [0][1][RTW89_FCC][1][60] = -40,
+ [0][1][RTW89_FCC][2][60] = 30,
+ [0][1][RTW89_ETSI][1][60] = 127,
+ [0][1][RTW89_ETSI][0][60] = 127,
+ [0][1][RTW89_MKK][1][60] = 127,
+ [0][1][RTW89_MKK][0][60] = 127,
+ [0][1][RTW89_IC][1][60] = -40,
+ [0][1][RTW89_KCC][1][60] = -14,
+ [0][1][RTW89_KCC][0][60] = 127,
+ [0][1][RTW89_ACMA][1][60] = 127,
+ [0][1][RTW89_ACMA][0][60] = 127,
+ [0][1][RTW89_CHILE][1][60] = 127,
+ [0][1][RTW89_QATAR][1][60] = 127,
+ [0][1][RTW89_QATAR][0][60] = 127,
+ [0][1][RTW89_UK][1][60] = 127,
+ [0][1][RTW89_UK][0][60] = 127,
+ [0][1][RTW89_FCC][1][62] = -40,
+ [0][1][RTW89_FCC][2][62] = 30,
+ [0][1][RTW89_ETSI][1][62] = 127,
+ [0][1][RTW89_ETSI][0][62] = 127,
+ [0][1][RTW89_MKK][1][62] = 127,
+ [0][1][RTW89_MKK][0][62] = 127,
+ [0][1][RTW89_IC][1][62] = -40,
+ [0][1][RTW89_KCC][1][62] = -14,
+ [0][1][RTW89_KCC][0][62] = 127,
+ [0][1][RTW89_ACMA][1][62] = 127,
+ [0][1][RTW89_ACMA][0][62] = 127,
+ [0][1][RTW89_CHILE][1][62] = 127,
+ [0][1][RTW89_QATAR][1][62] = 127,
+ [0][1][RTW89_QATAR][0][62] = 127,
+ [0][1][RTW89_UK][1][62] = 127,
+ [0][1][RTW89_UK][0][62] = 127,
+ [0][1][RTW89_FCC][1][64] = -40,
+ [0][1][RTW89_FCC][2][64] = 30,
+ [0][1][RTW89_ETSI][1][64] = 127,
+ [0][1][RTW89_ETSI][0][64] = 127,
+ [0][1][RTW89_MKK][1][64] = 127,
+ [0][1][RTW89_MKK][0][64] = 127,
+ [0][1][RTW89_IC][1][64] = -40,
+ [0][1][RTW89_KCC][1][64] = -14,
+ [0][1][RTW89_KCC][0][64] = 127,
+ [0][1][RTW89_ACMA][1][64] = 127,
+ [0][1][RTW89_ACMA][0][64] = 127,
+ [0][1][RTW89_CHILE][1][64] = 127,
+ [0][1][RTW89_QATAR][1][64] = 127,
+ [0][1][RTW89_QATAR][0][64] = 127,
+ [0][1][RTW89_UK][1][64] = 127,
+ [0][1][RTW89_UK][0][64] = 127,
+ [0][1][RTW89_FCC][1][66] = -40,
+ [0][1][RTW89_FCC][2][66] = 30,
+ [0][1][RTW89_ETSI][1][66] = 127,
+ [0][1][RTW89_ETSI][0][66] = 127,
+ [0][1][RTW89_MKK][1][66] = 127,
+ [0][1][RTW89_MKK][0][66] = 127,
+ [0][1][RTW89_IC][1][66] = -40,
+ [0][1][RTW89_KCC][1][66] = -14,
+ [0][1][RTW89_KCC][0][66] = 127,
+ [0][1][RTW89_ACMA][1][66] = 127,
+ [0][1][RTW89_ACMA][0][66] = 127,
+ [0][1][RTW89_CHILE][1][66] = 127,
+ [0][1][RTW89_QATAR][1][66] = 127,
+ [0][1][RTW89_QATAR][0][66] = 127,
+ [0][1][RTW89_UK][1][66] = 127,
+ [0][1][RTW89_UK][0][66] = 127,
+ [0][1][RTW89_FCC][1][68] = -40,
+ [0][1][RTW89_FCC][2][68] = 30,
+ [0][1][RTW89_ETSI][1][68] = 127,
+ [0][1][RTW89_ETSI][0][68] = 127,
+ [0][1][RTW89_MKK][1][68] = 127,
+ [0][1][RTW89_MKK][0][68] = 127,
+ [0][1][RTW89_IC][1][68] = -40,
+ [0][1][RTW89_KCC][1][68] = -14,
+ [0][1][RTW89_KCC][0][68] = 127,
+ [0][1][RTW89_ACMA][1][68] = 127,
+ [0][1][RTW89_ACMA][0][68] = 127,
+ [0][1][RTW89_CHILE][1][68] = 127,
+ [0][1][RTW89_QATAR][1][68] = 127,
+ [0][1][RTW89_QATAR][0][68] = 127,
+ [0][1][RTW89_UK][1][68] = 127,
+ [0][1][RTW89_UK][0][68] = 127,
+ [0][1][RTW89_FCC][1][70] = -38,
+ [0][1][RTW89_FCC][2][70] = 30,
+ [0][1][RTW89_ETSI][1][70] = 127,
+ [0][1][RTW89_ETSI][0][70] = 127,
+ [0][1][RTW89_MKK][1][70] = 127,
+ [0][1][RTW89_MKK][0][70] = 127,
+ [0][1][RTW89_IC][1][70] = -38,
+ [0][1][RTW89_KCC][1][70] = -14,
+ [0][1][RTW89_KCC][0][70] = 127,
+ [0][1][RTW89_ACMA][1][70] = 127,
+ [0][1][RTW89_ACMA][0][70] = 127,
+ [0][1][RTW89_CHILE][1][70] = 127,
+ [0][1][RTW89_QATAR][1][70] = 127,
+ [0][1][RTW89_QATAR][0][70] = 127,
+ [0][1][RTW89_UK][1][70] = 127,
+ [0][1][RTW89_UK][0][70] = 127,
+ [0][1][RTW89_FCC][1][72] = -38,
+ [0][1][RTW89_FCC][2][72] = 30,
+ [0][1][RTW89_ETSI][1][72] = 127,
+ [0][1][RTW89_ETSI][0][72] = 127,
+ [0][1][RTW89_MKK][1][72] = 127,
+ [0][1][RTW89_MKK][0][72] = 127,
+ [0][1][RTW89_IC][1][72] = -38,
+ [0][1][RTW89_KCC][1][72] = -14,
+ [0][1][RTW89_KCC][0][72] = 127,
+ [0][1][RTW89_ACMA][1][72] = 127,
+ [0][1][RTW89_ACMA][0][72] = 127,
+ [0][1][RTW89_CHILE][1][72] = 127,
+ [0][1][RTW89_QATAR][1][72] = 127,
+ [0][1][RTW89_QATAR][0][72] = 127,
+ [0][1][RTW89_UK][1][72] = 127,
+ [0][1][RTW89_UK][0][72] = 127,
+ [0][1][RTW89_FCC][1][74] = -38,
+ [0][1][RTW89_FCC][2][74] = 30,
+ [0][1][RTW89_ETSI][1][74] = 127,
+ [0][1][RTW89_ETSI][0][74] = 127,
+ [0][1][RTW89_MKK][1][74] = 127,
+ [0][1][RTW89_MKK][0][74] = 127,
+ [0][1][RTW89_IC][1][74] = -38,
+ [0][1][RTW89_KCC][1][74] = -14,
+ [0][1][RTW89_KCC][0][74] = 127,
+ [0][1][RTW89_ACMA][1][74] = 127,
+ [0][1][RTW89_ACMA][0][74] = 127,
+ [0][1][RTW89_CHILE][1][74] = 127,
+ [0][1][RTW89_QATAR][1][74] = 127,
+ [0][1][RTW89_QATAR][0][74] = 127,
+ [0][1][RTW89_UK][1][74] = 127,
+ [0][1][RTW89_UK][0][74] = 127,
+ [0][1][RTW89_FCC][1][75] = -38,
+ [0][1][RTW89_FCC][2][75] = 30,
+ [0][1][RTW89_ETSI][1][75] = 127,
+ [0][1][RTW89_ETSI][0][75] = 127,
+ [0][1][RTW89_MKK][1][75] = 127,
+ [0][1][RTW89_MKK][0][75] = 127,
+ [0][1][RTW89_IC][1][75] = -38,
+ [0][1][RTW89_KCC][1][75] = -14,
+ [0][1][RTW89_KCC][0][75] = 127,
+ [0][1][RTW89_ACMA][1][75] = 127,
+ [0][1][RTW89_ACMA][0][75] = 127,
+ [0][1][RTW89_CHILE][1][75] = 127,
+ [0][1][RTW89_QATAR][1][75] = 127,
+ [0][1][RTW89_QATAR][0][75] = 127,
+ [0][1][RTW89_UK][1][75] = 127,
+ [0][1][RTW89_UK][0][75] = 127,
+ [0][1][RTW89_FCC][1][77] = -38,
+ [0][1][RTW89_FCC][2][77] = 30,
+ [0][1][RTW89_ETSI][1][77] = 127,
+ [0][1][RTW89_ETSI][0][77] = 127,
+ [0][1][RTW89_MKK][1][77] = 127,
+ [0][1][RTW89_MKK][0][77] = 127,
+ [0][1][RTW89_IC][1][77] = -38,
+ [0][1][RTW89_KCC][1][77] = -14,
+ [0][1][RTW89_KCC][0][77] = 127,
+ [0][1][RTW89_ACMA][1][77] = 127,
+ [0][1][RTW89_ACMA][0][77] = 127,
+ [0][1][RTW89_CHILE][1][77] = 127,
+ [0][1][RTW89_QATAR][1][77] = 127,
+ [0][1][RTW89_QATAR][0][77] = 127,
+ [0][1][RTW89_UK][1][77] = 127,
+ [0][1][RTW89_UK][0][77] = 127,
+ [0][1][RTW89_FCC][1][79] = -38,
+ [0][1][RTW89_FCC][2][79] = 30,
+ [0][1][RTW89_ETSI][1][79] = 127,
+ [0][1][RTW89_ETSI][0][79] = 127,
+ [0][1][RTW89_MKK][1][79] = 127,
+ [0][1][RTW89_MKK][0][79] = 127,
+ [0][1][RTW89_IC][1][79] = -38,
+ [0][1][RTW89_KCC][1][79] = -14,
+ [0][1][RTW89_KCC][0][79] = 127,
+ [0][1][RTW89_ACMA][1][79] = 127,
+ [0][1][RTW89_ACMA][0][79] = 127,
+ [0][1][RTW89_CHILE][1][79] = 127,
+ [0][1][RTW89_QATAR][1][79] = 127,
+ [0][1][RTW89_QATAR][0][79] = 127,
+ [0][1][RTW89_UK][1][79] = 127,
+ [0][1][RTW89_UK][0][79] = 127,
+ [0][1][RTW89_FCC][1][81] = -38,
+ [0][1][RTW89_FCC][2][81] = 30,
+ [0][1][RTW89_ETSI][1][81] = 127,
+ [0][1][RTW89_ETSI][0][81] = 127,
+ [0][1][RTW89_MKK][1][81] = 127,
+ [0][1][RTW89_MKK][0][81] = 127,
+ [0][1][RTW89_IC][1][81] = -38,
+ [0][1][RTW89_KCC][1][81] = -14,
+ [0][1][RTW89_KCC][0][81] = 127,
+ [0][1][RTW89_ACMA][1][81] = 127,
+ [0][1][RTW89_ACMA][0][81] = 127,
+ [0][1][RTW89_CHILE][1][81] = 127,
+ [0][1][RTW89_QATAR][1][81] = 127,
+ [0][1][RTW89_QATAR][0][81] = 127,
+ [0][1][RTW89_UK][1][81] = 127,
+ [0][1][RTW89_UK][0][81] = 127,
+ [0][1][RTW89_FCC][1][83] = -38,
+ [0][1][RTW89_FCC][2][83] = 30,
+ [0][1][RTW89_ETSI][1][83] = 127,
+ [0][1][RTW89_ETSI][0][83] = 127,
+ [0][1][RTW89_MKK][1][83] = 127,
+ [0][1][RTW89_MKK][0][83] = 127,
+ [0][1][RTW89_IC][1][83] = -38,
+ [0][1][RTW89_KCC][1][83] = -14,
+ [0][1][RTW89_KCC][0][83] = 127,
+ [0][1][RTW89_ACMA][1][83] = 127,
+ [0][1][RTW89_ACMA][0][83] = 127,
+ [0][1][RTW89_CHILE][1][83] = 127,
+ [0][1][RTW89_QATAR][1][83] = 127,
+ [0][1][RTW89_QATAR][0][83] = 127,
+ [0][1][RTW89_UK][1][83] = 127,
+ [0][1][RTW89_UK][0][83] = 127,
+ [0][1][RTW89_FCC][1][85] = -38,
+ [0][1][RTW89_FCC][2][85] = 30,
+ [0][1][RTW89_ETSI][1][85] = 127,
+ [0][1][RTW89_ETSI][0][85] = 127,
+ [0][1][RTW89_MKK][1][85] = 127,
+ [0][1][RTW89_MKK][0][85] = 127,
+ [0][1][RTW89_IC][1][85] = -38,
+ [0][1][RTW89_KCC][1][85] = -14,
+ [0][1][RTW89_KCC][0][85] = 127,
+ [0][1][RTW89_ACMA][1][85] = 127,
+ [0][1][RTW89_ACMA][0][85] = 127,
+ [0][1][RTW89_CHILE][1][85] = 127,
+ [0][1][RTW89_QATAR][1][85] = 127,
+ [0][1][RTW89_QATAR][0][85] = 127,
+ [0][1][RTW89_UK][1][85] = 127,
+ [0][1][RTW89_UK][0][85] = 127,
+ [0][1][RTW89_FCC][1][87] = -40,
+ [0][1][RTW89_FCC][2][87] = 127,
+ [0][1][RTW89_ETSI][1][87] = 127,
+ [0][1][RTW89_ETSI][0][87] = 127,
+ [0][1][RTW89_MKK][1][87] = 127,
+ [0][1][RTW89_MKK][0][87] = 127,
+ [0][1][RTW89_IC][1][87] = -40,
+ [0][1][RTW89_KCC][1][87] = -14,
+ [0][1][RTW89_KCC][0][87] = 127,
+ [0][1][RTW89_ACMA][1][87] = 127,
+ [0][1][RTW89_ACMA][0][87] = 127,
+ [0][1][RTW89_CHILE][1][87] = 127,
+ [0][1][RTW89_QATAR][1][87] = 127,
+ [0][1][RTW89_QATAR][0][87] = 127,
+ [0][1][RTW89_UK][1][87] = 127,
+ [0][1][RTW89_UK][0][87] = 127,
+ [0][1][RTW89_FCC][1][89] = -38,
+ [0][1][RTW89_FCC][2][89] = 127,
+ [0][1][RTW89_ETSI][1][89] = 127,
+ [0][1][RTW89_ETSI][0][89] = 127,
+ [0][1][RTW89_MKK][1][89] = 127,
+ [0][1][RTW89_MKK][0][89] = 127,
+ [0][1][RTW89_IC][1][89] = -38,
+ [0][1][RTW89_KCC][1][89] = -14,
+ [0][1][RTW89_KCC][0][89] = 127,
+ [0][1][RTW89_ACMA][1][89] = 127,
+ [0][1][RTW89_ACMA][0][89] = 127,
+ [0][1][RTW89_CHILE][1][89] = 127,
+ [0][1][RTW89_QATAR][1][89] = 127,
+ [0][1][RTW89_QATAR][0][89] = 127,
+ [0][1][RTW89_UK][1][89] = 127,
+ [0][1][RTW89_UK][0][89] = 127,
+ [0][1][RTW89_FCC][1][90] = -38,
+ [0][1][RTW89_FCC][2][90] = 127,
+ [0][1][RTW89_ETSI][1][90] = 127,
+ [0][1][RTW89_ETSI][0][90] = 127,
+ [0][1][RTW89_MKK][1][90] = 127,
+ [0][1][RTW89_MKK][0][90] = 127,
+ [0][1][RTW89_IC][1][90] = -38,
+ [0][1][RTW89_KCC][1][90] = -14,
+ [0][1][RTW89_KCC][0][90] = 127,
+ [0][1][RTW89_ACMA][1][90] = 127,
+ [0][1][RTW89_ACMA][0][90] = 127,
+ [0][1][RTW89_CHILE][1][90] = 127,
+ [0][1][RTW89_QATAR][1][90] = 127,
+ [0][1][RTW89_QATAR][0][90] = 127,
+ [0][1][RTW89_UK][1][90] = 127,
+ [0][1][RTW89_UK][0][90] = 127,
+ [0][1][RTW89_FCC][1][92] = -38,
+ [0][1][RTW89_FCC][2][92] = 127,
+ [0][1][RTW89_ETSI][1][92] = 127,
+ [0][1][RTW89_ETSI][0][92] = 127,
+ [0][1][RTW89_MKK][1][92] = 127,
+ [0][1][RTW89_MKK][0][92] = 127,
+ [0][1][RTW89_IC][1][92] = -38,
+ [0][1][RTW89_KCC][1][92] = -14,
+ [0][1][RTW89_KCC][0][92] = 127,
+ [0][1][RTW89_ACMA][1][92] = 127,
+ [0][1][RTW89_ACMA][0][92] = 127,
+ [0][1][RTW89_CHILE][1][92] = 127,
+ [0][1][RTW89_QATAR][1][92] = 127,
+ [0][1][RTW89_QATAR][0][92] = 127,
+ [0][1][RTW89_UK][1][92] = 127,
+ [0][1][RTW89_UK][0][92] = 127,
+ [0][1][RTW89_FCC][1][94] = -38,
+ [0][1][RTW89_FCC][2][94] = 127,
+ [0][1][RTW89_ETSI][1][94] = 127,
+ [0][1][RTW89_ETSI][0][94] = 127,
+ [0][1][RTW89_MKK][1][94] = 127,
+ [0][1][RTW89_MKK][0][94] = 127,
+ [0][1][RTW89_IC][1][94] = -38,
+ [0][1][RTW89_KCC][1][94] = -14,
+ [0][1][RTW89_KCC][0][94] = 127,
+ [0][1][RTW89_ACMA][1][94] = 127,
+ [0][1][RTW89_ACMA][0][94] = 127,
+ [0][1][RTW89_CHILE][1][94] = 127,
+ [0][1][RTW89_QATAR][1][94] = 127,
+ [0][1][RTW89_QATAR][0][94] = 127,
+ [0][1][RTW89_UK][1][94] = 127,
+ [0][1][RTW89_UK][0][94] = 127,
+ [0][1][RTW89_FCC][1][96] = -38,
+ [0][1][RTW89_FCC][2][96] = 127,
+ [0][1][RTW89_ETSI][1][96] = 127,
+ [0][1][RTW89_ETSI][0][96] = 127,
+ [0][1][RTW89_MKK][1][96] = 127,
+ [0][1][RTW89_MKK][0][96] = 127,
+ [0][1][RTW89_IC][1][96] = -38,
+ [0][1][RTW89_KCC][1][96] = -14,
+ [0][1][RTW89_KCC][0][96] = 127,
+ [0][1][RTW89_ACMA][1][96] = 127,
+ [0][1][RTW89_ACMA][0][96] = 127,
+ [0][1][RTW89_CHILE][1][96] = 127,
+ [0][1][RTW89_QATAR][1][96] = 127,
+ [0][1][RTW89_QATAR][0][96] = 127,
+ [0][1][RTW89_UK][1][96] = 127,
+ [0][1][RTW89_UK][0][96] = 127,
+ [0][1][RTW89_FCC][1][98] = -38,
+ [0][1][RTW89_FCC][2][98] = 127,
+ [0][1][RTW89_ETSI][1][98] = 127,
+ [0][1][RTW89_ETSI][0][98] = 127,
+ [0][1][RTW89_MKK][1][98] = 127,
+ [0][1][RTW89_MKK][0][98] = 127,
+ [0][1][RTW89_IC][1][98] = -38,
+ [0][1][RTW89_KCC][1][98] = -14,
+ [0][1][RTW89_KCC][0][98] = 127,
+ [0][1][RTW89_ACMA][1][98] = 127,
+ [0][1][RTW89_ACMA][0][98] = 127,
+ [0][1][RTW89_CHILE][1][98] = 127,
+ [0][1][RTW89_QATAR][1][98] = 127,
+ [0][1][RTW89_QATAR][0][98] = 127,
+ [0][1][RTW89_UK][1][98] = 127,
+ [0][1][RTW89_UK][0][98] = 127,
+ [0][1][RTW89_FCC][1][100] = -38,
+ [0][1][RTW89_FCC][2][100] = 127,
+ [0][1][RTW89_ETSI][1][100] = 127,
+ [0][1][RTW89_ETSI][0][100] = 127,
+ [0][1][RTW89_MKK][1][100] = 127,
+ [0][1][RTW89_MKK][0][100] = 127,
+ [0][1][RTW89_IC][1][100] = -38,
+ [0][1][RTW89_KCC][1][100] = -14,
+ [0][1][RTW89_KCC][0][100] = 127,
+ [0][1][RTW89_ACMA][1][100] = 127,
+ [0][1][RTW89_ACMA][0][100] = 127,
+ [0][1][RTW89_CHILE][1][100] = 127,
+ [0][1][RTW89_QATAR][1][100] = 127,
+ [0][1][RTW89_QATAR][0][100] = 127,
+ [0][1][RTW89_UK][1][100] = 127,
+ [0][1][RTW89_UK][0][100] = 127,
+ [0][1][RTW89_FCC][1][102] = -38,
+ [0][1][RTW89_FCC][2][102] = 127,
+ [0][1][RTW89_ETSI][1][102] = 127,
+ [0][1][RTW89_ETSI][0][102] = 127,
+ [0][1][RTW89_MKK][1][102] = 127,
+ [0][1][RTW89_MKK][0][102] = 127,
+ [0][1][RTW89_IC][1][102] = -38,
+ [0][1][RTW89_KCC][1][102] = -14,
+ [0][1][RTW89_KCC][0][102] = 127,
+ [0][1][RTW89_ACMA][1][102] = 127,
+ [0][1][RTW89_ACMA][0][102] = 127,
+ [0][1][RTW89_CHILE][1][102] = 127,
+ [0][1][RTW89_QATAR][1][102] = 127,
+ [0][1][RTW89_QATAR][0][102] = 127,
+ [0][1][RTW89_UK][1][102] = 127,
+ [0][1][RTW89_UK][0][102] = 127,
+ [0][1][RTW89_FCC][1][104] = -38,
+ [0][1][RTW89_FCC][2][104] = 127,
+ [0][1][RTW89_ETSI][1][104] = 127,
+ [0][1][RTW89_ETSI][0][104] = 127,
+ [0][1][RTW89_MKK][1][104] = 127,
+ [0][1][RTW89_MKK][0][104] = 127,
+ [0][1][RTW89_IC][1][104] = -38,
+ [0][1][RTW89_KCC][1][104] = -14,
+ [0][1][RTW89_KCC][0][104] = 127,
+ [0][1][RTW89_ACMA][1][104] = 127,
+ [0][1][RTW89_ACMA][0][104] = 127,
+ [0][1][RTW89_CHILE][1][104] = 127,
+ [0][1][RTW89_QATAR][1][104] = 127,
+ [0][1][RTW89_QATAR][0][104] = 127,
+ [0][1][RTW89_UK][1][104] = 127,
+ [0][1][RTW89_UK][0][104] = 127,
+ [0][1][RTW89_FCC][1][105] = -38,
+ [0][1][RTW89_FCC][2][105] = 127,
+ [0][1][RTW89_ETSI][1][105] = 127,
+ [0][1][RTW89_ETSI][0][105] = 127,
+ [0][1][RTW89_MKK][1][105] = 127,
+ [0][1][RTW89_MKK][0][105] = 127,
+ [0][1][RTW89_IC][1][105] = -38,
+ [0][1][RTW89_KCC][1][105] = -14,
+ [0][1][RTW89_KCC][0][105] = 127,
+ [0][1][RTW89_ACMA][1][105] = 127,
+ [0][1][RTW89_ACMA][0][105] = 127,
+ [0][1][RTW89_CHILE][1][105] = 127,
+ [0][1][RTW89_QATAR][1][105] = 127,
+ [0][1][RTW89_QATAR][0][105] = 127,
+ [0][1][RTW89_UK][1][105] = 127,
+ [0][1][RTW89_UK][0][105] = 127,
+ [0][1][RTW89_FCC][1][107] = -34,
+ [0][1][RTW89_FCC][2][107] = 127,
+ [0][1][RTW89_ETSI][1][107] = 127,
+ [0][1][RTW89_ETSI][0][107] = 127,
+ [0][1][RTW89_MKK][1][107] = 127,
+ [0][1][RTW89_MKK][0][107] = 127,
+ [0][1][RTW89_IC][1][107] = -34,
+ [0][1][RTW89_KCC][1][107] = -14,
+ [0][1][RTW89_KCC][0][107] = 127,
+ [0][1][RTW89_ACMA][1][107] = 127,
+ [0][1][RTW89_ACMA][0][107] = 127,
+ [0][1][RTW89_CHILE][1][107] = 127,
+ [0][1][RTW89_QATAR][1][107] = 127,
+ [0][1][RTW89_QATAR][0][107] = 127,
+ [0][1][RTW89_UK][1][107] = 127,
+ [0][1][RTW89_UK][0][107] = 127,
+ [0][1][RTW89_FCC][1][109] = -34,
+ [0][1][RTW89_FCC][2][109] = 127,
+ [0][1][RTW89_ETSI][1][109] = 127,
+ [0][1][RTW89_ETSI][0][109] = 127,
+ [0][1][RTW89_MKK][1][109] = 127,
+ [0][1][RTW89_MKK][0][109] = 127,
+ [0][1][RTW89_IC][1][109] = -34,
+ [0][1][RTW89_KCC][1][109] = 127,
+ [0][1][RTW89_KCC][0][109] = 127,
+ [0][1][RTW89_ACMA][1][109] = 127,
+ [0][1][RTW89_ACMA][0][109] = 127,
+ [0][1][RTW89_CHILE][1][109] = 127,
+ [0][1][RTW89_QATAR][1][109] = 127,
+ [0][1][RTW89_QATAR][0][109] = 127,
+ [0][1][RTW89_UK][1][109] = 127,
+ [0][1][RTW89_UK][0][109] = 127,
+ [0][1][RTW89_FCC][1][111] = 127,
+ [0][1][RTW89_FCC][2][111] = 127,
+ [0][1][RTW89_ETSI][1][111] = 127,
+ [0][1][RTW89_ETSI][0][111] = 127,
+ [0][1][RTW89_MKK][1][111] = 127,
+ [0][1][RTW89_MKK][0][111] = 127,
+ [0][1][RTW89_IC][1][111] = 127,
+ [0][1][RTW89_KCC][1][111] = 127,
+ [0][1][RTW89_KCC][0][111] = 127,
+ [0][1][RTW89_ACMA][1][111] = 127,
+ [0][1][RTW89_ACMA][0][111] = 127,
+ [0][1][RTW89_CHILE][1][111] = 127,
+ [0][1][RTW89_QATAR][1][111] = 127,
+ [0][1][RTW89_QATAR][0][111] = 127,
+ [0][1][RTW89_UK][1][111] = 127,
+ [0][1][RTW89_UK][0][111] = 127,
+ [0][1][RTW89_FCC][1][113] = 127,
+ [0][1][RTW89_FCC][2][113] = 127,
+ [0][1][RTW89_ETSI][1][113] = 127,
+ [0][1][RTW89_ETSI][0][113] = 127,
+ [0][1][RTW89_MKK][1][113] = 127,
+ [0][1][RTW89_MKK][0][113] = 127,
+ [0][1][RTW89_IC][1][113] = 127,
+ [0][1][RTW89_KCC][1][113] = 127,
+ [0][1][RTW89_KCC][0][113] = 127,
+ [0][1][RTW89_ACMA][1][113] = 127,
+ [0][1][RTW89_ACMA][0][113] = 127,
+ [0][1][RTW89_CHILE][1][113] = 127,
+ [0][1][RTW89_QATAR][1][113] = 127,
+ [0][1][RTW89_QATAR][0][113] = 127,
+ [0][1][RTW89_UK][1][113] = 127,
+ [0][1][RTW89_UK][0][113] = 127,
+ [0][1][RTW89_FCC][1][115] = 127,
+ [0][1][RTW89_FCC][2][115] = 127,
+ [0][1][RTW89_ETSI][1][115] = 127,
+ [0][1][RTW89_ETSI][0][115] = 127,
+ [0][1][RTW89_MKK][1][115] = 127,
+ [0][1][RTW89_MKK][0][115] = 127,
+ [0][1][RTW89_IC][1][115] = 127,
+ [0][1][RTW89_KCC][1][115] = 127,
+ [0][1][RTW89_KCC][0][115] = 127,
+ [0][1][RTW89_ACMA][1][115] = 127,
+ [0][1][RTW89_ACMA][0][115] = 127,
+ [0][1][RTW89_CHILE][1][115] = 127,
+ [0][1][RTW89_QATAR][1][115] = 127,
+ [0][1][RTW89_QATAR][0][115] = 127,
+ [0][1][RTW89_UK][1][115] = 127,
+ [0][1][RTW89_UK][0][115] = 127,
+ [0][1][RTW89_FCC][1][117] = 127,
+ [0][1][RTW89_FCC][2][117] = 127,
+ [0][1][RTW89_ETSI][1][117] = 127,
+ [0][1][RTW89_ETSI][0][117] = 127,
+ [0][1][RTW89_MKK][1][117] = 127,
+ [0][1][RTW89_MKK][0][117] = 127,
+ [0][1][RTW89_IC][1][117] = 127,
+ [0][1][RTW89_KCC][1][117] = 127,
+ [0][1][RTW89_KCC][0][117] = 127,
+ [0][1][RTW89_ACMA][1][117] = 127,
+ [0][1][RTW89_ACMA][0][117] = 127,
+ [0][1][RTW89_CHILE][1][117] = 127,
+ [0][1][RTW89_QATAR][1][117] = 127,
+ [0][1][RTW89_QATAR][0][117] = 127,
+ [0][1][RTW89_UK][1][117] = 127,
+ [0][1][RTW89_UK][0][117] = 127,
+ [0][1][RTW89_FCC][1][119] = 127,
+ [0][1][RTW89_FCC][2][119] = 127,
+ [0][1][RTW89_ETSI][1][119] = 127,
+ [0][1][RTW89_ETSI][0][119] = 127,
+ [0][1][RTW89_MKK][1][119] = 127,
+ [0][1][RTW89_MKK][0][119] = 127,
+ [0][1][RTW89_IC][1][119] = 127,
+ [0][1][RTW89_KCC][1][119] = 127,
+ [0][1][RTW89_KCC][0][119] = 127,
+ [0][1][RTW89_ACMA][1][119] = 127,
+ [0][1][RTW89_ACMA][0][119] = 127,
+ [0][1][RTW89_CHILE][1][119] = 127,
+ [0][1][RTW89_QATAR][1][119] = 127,
+ [0][1][RTW89_QATAR][0][119] = 127,
+ [0][1][RTW89_UK][1][119] = 127,
+ [0][1][RTW89_UK][0][119] = 127,
+ [1][0][RTW89_FCC][1][0] = -4,
+ [1][0][RTW89_FCC][2][0] = 52,
+ [1][0][RTW89_ETSI][1][0] = 46,
+ [1][0][RTW89_ETSI][0][0] = 6,
+ [1][0][RTW89_MKK][1][0] = 42,
+ [1][0][RTW89_MKK][0][0] = 2,
+ [1][0][RTW89_IC][1][0] = -4,
+ [1][0][RTW89_KCC][1][0] = -2,
+ [1][0][RTW89_KCC][0][0] = -2,
+ [1][0][RTW89_ACMA][1][0] = 46,
+ [1][0][RTW89_ACMA][0][0] = 6,
+ [1][0][RTW89_CHILE][1][0] = -4,
+ [1][0][RTW89_QATAR][1][0] = 46,
+ [1][0][RTW89_QATAR][0][0] = 6,
+ [1][0][RTW89_UK][1][0] = 46,
+ [1][0][RTW89_UK][0][0] = 6,
+ [1][0][RTW89_FCC][1][2] = -4,
+ [1][0][RTW89_FCC][2][2] = 52,
+ [1][0][RTW89_ETSI][1][2] = 46,
+ [1][0][RTW89_ETSI][0][2] = 6,
+ [1][0][RTW89_MKK][1][2] = 42,
+ [1][0][RTW89_MKK][0][2] = 2,
+ [1][0][RTW89_IC][1][2] = -4,
+ [1][0][RTW89_KCC][1][2] = -2,
+ [1][0][RTW89_KCC][0][2] = -2,
+ [1][0][RTW89_ACMA][1][2] = 46,
+ [1][0][RTW89_ACMA][0][2] = 6,
+ [1][0][RTW89_CHILE][1][2] = -4,
+ [1][0][RTW89_QATAR][1][2] = 46,
+ [1][0][RTW89_QATAR][0][2] = 6,
+ [1][0][RTW89_UK][1][2] = 46,
+ [1][0][RTW89_UK][0][2] = 6,
+ [1][0][RTW89_FCC][1][4] = -4,
+ [1][0][RTW89_FCC][2][4] = 52,
+ [1][0][RTW89_ETSI][1][4] = 46,
+ [1][0][RTW89_ETSI][0][4] = 6,
+ [1][0][RTW89_MKK][1][4] = 42,
+ [1][0][RTW89_MKK][0][4] = 2,
+ [1][0][RTW89_IC][1][4] = -4,
+ [1][0][RTW89_KCC][1][4] = -2,
+ [1][0][RTW89_KCC][0][4] = -2,
+ [1][0][RTW89_ACMA][1][4] = 46,
+ [1][0][RTW89_ACMA][0][4] = 6,
+ [1][0][RTW89_CHILE][1][4] = -4,
+ [1][0][RTW89_QATAR][1][4] = 46,
+ [1][0][RTW89_QATAR][0][4] = 6,
+ [1][0][RTW89_UK][1][4] = 46,
+ [1][0][RTW89_UK][0][4] = 6,
+ [1][0][RTW89_FCC][1][6] = -4,
+ [1][0][RTW89_FCC][2][6] = 52,
+ [1][0][RTW89_ETSI][1][6] = 46,
+ [1][0][RTW89_ETSI][0][6] = 6,
+ [1][0][RTW89_MKK][1][6] = 42,
+ [1][0][RTW89_MKK][0][6] = 2,
+ [1][0][RTW89_IC][1][6] = -4,
+ [1][0][RTW89_KCC][1][6] = -2,
+ [1][0][RTW89_KCC][0][6] = -2,
+ [1][0][RTW89_ACMA][1][6] = 46,
+ [1][0][RTW89_ACMA][0][6] = 6,
+ [1][0][RTW89_CHILE][1][6] = -4,
+ [1][0][RTW89_QATAR][1][6] = 46,
+ [1][0][RTW89_QATAR][0][6] = 6,
+ [1][0][RTW89_UK][1][6] = 46,
+ [1][0][RTW89_UK][0][6] = 6,
+ [1][0][RTW89_FCC][1][8] = -4,
+ [1][0][RTW89_FCC][2][8] = 52,
+ [1][0][RTW89_ETSI][1][8] = 46,
+ [1][0][RTW89_ETSI][0][8] = 6,
+ [1][0][RTW89_MKK][1][8] = 42,
+ [1][0][RTW89_MKK][0][8] = 2,
+ [1][0][RTW89_IC][1][8] = -4,
+ [1][0][RTW89_KCC][1][8] = -2,
+ [1][0][RTW89_KCC][0][8] = -2,
+ [1][0][RTW89_ACMA][1][8] = 46,
+ [1][0][RTW89_ACMA][0][8] = 6,
+ [1][0][RTW89_CHILE][1][8] = -4,
+ [1][0][RTW89_QATAR][1][8] = 46,
+ [1][0][RTW89_QATAR][0][8] = 6,
+ [1][0][RTW89_UK][1][8] = 46,
+ [1][0][RTW89_UK][0][8] = 6,
+ [1][0][RTW89_FCC][1][10] = -4,
+ [1][0][RTW89_FCC][2][10] = 52,
+ [1][0][RTW89_ETSI][1][10] = 46,
+ [1][0][RTW89_ETSI][0][10] = 6,
+ [1][0][RTW89_MKK][1][10] = 42,
+ [1][0][RTW89_MKK][0][10] = 2,
+ [1][0][RTW89_IC][1][10] = -4,
+ [1][0][RTW89_KCC][1][10] = -2,
+ [1][0][RTW89_KCC][0][10] = -2,
+ [1][0][RTW89_ACMA][1][10] = 46,
+ [1][0][RTW89_ACMA][0][10] = 6,
+ [1][0][RTW89_CHILE][1][10] = -4,
+ [1][0][RTW89_QATAR][1][10] = 46,
+ [1][0][RTW89_QATAR][0][10] = 6,
+ [1][0][RTW89_UK][1][10] = 46,
+ [1][0][RTW89_UK][0][10] = 6,
+ [1][0][RTW89_FCC][1][12] = -4,
+ [1][0][RTW89_FCC][2][12] = 52,
+ [1][0][RTW89_ETSI][1][12] = 46,
+ [1][0][RTW89_ETSI][0][12] = 6,
+ [1][0][RTW89_MKK][1][12] = 42,
+ [1][0][RTW89_MKK][0][12] = 2,
+ [1][0][RTW89_IC][1][12] = -4,
+ [1][0][RTW89_KCC][1][12] = -2,
+ [1][0][RTW89_KCC][0][12] = -2,
+ [1][0][RTW89_ACMA][1][12] = 46,
+ [1][0][RTW89_ACMA][0][12] = 6,
+ [1][0][RTW89_CHILE][1][12] = -4,
+ [1][0][RTW89_QATAR][1][12] = 46,
+ [1][0][RTW89_QATAR][0][12] = 6,
+ [1][0][RTW89_UK][1][12] = 46,
+ [1][0][RTW89_UK][0][12] = 6,
+ [1][0][RTW89_FCC][1][14] = -4,
+ [1][0][RTW89_FCC][2][14] = 52,
+ [1][0][RTW89_ETSI][1][14] = 46,
+ [1][0][RTW89_ETSI][0][14] = 6,
+ [1][0][RTW89_MKK][1][14] = 42,
+ [1][0][RTW89_MKK][0][14] = 2,
+ [1][0][RTW89_IC][1][14] = -4,
+ [1][0][RTW89_KCC][1][14] = -2,
+ [1][0][RTW89_KCC][0][14] = -2,
+ [1][0][RTW89_ACMA][1][14] = 46,
+ [1][0][RTW89_ACMA][0][14] = 6,
+ [1][0][RTW89_CHILE][1][14] = -4,
+ [1][0][RTW89_QATAR][1][14] = 46,
+ [1][0][RTW89_QATAR][0][14] = 6,
+ [1][0][RTW89_UK][1][14] = 46,
+ [1][0][RTW89_UK][0][14] = 6,
+ [1][0][RTW89_FCC][1][15] = -4,
+ [1][0][RTW89_FCC][2][15] = 52,
+ [1][0][RTW89_ETSI][1][15] = 46,
+ [1][0][RTW89_ETSI][0][15] = 6,
+ [1][0][RTW89_MKK][1][15] = 42,
+ [1][0][RTW89_MKK][0][15] = 2,
+ [1][0][RTW89_IC][1][15] = -4,
+ [1][0][RTW89_KCC][1][15] = -2,
+ [1][0][RTW89_KCC][0][15] = -2,
+ [1][0][RTW89_ACMA][1][15] = 46,
+ [1][0][RTW89_ACMA][0][15] = 6,
+ [1][0][RTW89_CHILE][1][15] = -4,
+ [1][0][RTW89_QATAR][1][15] = 46,
+ [1][0][RTW89_QATAR][0][15] = 6,
+ [1][0][RTW89_UK][1][15] = 46,
+ [1][0][RTW89_UK][0][15] = 6,
+ [1][0][RTW89_FCC][1][17] = -4,
+ [1][0][RTW89_FCC][2][17] = 52,
+ [1][0][RTW89_ETSI][1][17] = 46,
+ [1][0][RTW89_ETSI][0][17] = 6,
+ [1][0][RTW89_MKK][1][17] = 42,
+ [1][0][RTW89_MKK][0][17] = 2,
+ [1][0][RTW89_IC][1][17] = -4,
+ [1][0][RTW89_KCC][1][17] = -2,
+ [1][0][RTW89_KCC][0][17] = -2,
+ [1][0][RTW89_ACMA][1][17] = 46,
+ [1][0][RTW89_ACMA][0][17] = 6,
+ [1][0][RTW89_CHILE][1][17] = -4,
+ [1][0][RTW89_QATAR][1][17] = 46,
+ [1][0][RTW89_QATAR][0][17] = 6,
+ [1][0][RTW89_UK][1][17] = 46,
+ [1][0][RTW89_UK][0][17] = 6,
+ [1][0][RTW89_FCC][1][19] = -4,
+ [1][0][RTW89_FCC][2][19] = 52,
+ [1][0][RTW89_ETSI][1][19] = 46,
+ [1][0][RTW89_ETSI][0][19] = 6,
+ [1][0][RTW89_MKK][1][19] = 42,
+ [1][0][RTW89_MKK][0][19] = 2,
+ [1][0][RTW89_IC][1][19] = -4,
+ [1][0][RTW89_KCC][1][19] = -2,
+ [1][0][RTW89_KCC][0][19] = -2,
+ [1][0][RTW89_ACMA][1][19] = 46,
+ [1][0][RTW89_ACMA][0][19] = 6,
+ [1][0][RTW89_CHILE][1][19] = -4,
+ [1][0][RTW89_QATAR][1][19] = 46,
+ [1][0][RTW89_QATAR][0][19] = 6,
+ [1][0][RTW89_UK][1][19] = 46,
+ [1][0][RTW89_UK][0][19] = 6,
+ [1][0][RTW89_FCC][1][21] = -4,
+ [1][0][RTW89_FCC][2][21] = 52,
+ [1][0][RTW89_ETSI][1][21] = 46,
+ [1][0][RTW89_ETSI][0][21] = 6,
+ [1][0][RTW89_MKK][1][21] = 42,
+ [1][0][RTW89_MKK][0][21] = 2,
+ [1][0][RTW89_IC][1][21] = -4,
+ [1][0][RTW89_KCC][1][21] = -2,
+ [1][0][RTW89_KCC][0][21] = -2,
+ [1][0][RTW89_ACMA][1][21] = 46,
+ [1][0][RTW89_ACMA][0][21] = 6,
+ [1][0][RTW89_CHILE][1][21] = -4,
+ [1][0][RTW89_QATAR][1][21] = 46,
+ [1][0][RTW89_QATAR][0][21] = 6,
+ [1][0][RTW89_UK][1][21] = 46,
+ [1][0][RTW89_UK][0][21] = 6,
+ [1][0][RTW89_FCC][1][23] = -4,
+ [1][0][RTW89_FCC][2][23] = 66,
+ [1][0][RTW89_ETSI][1][23] = 46,
+ [1][0][RTW89_ETSI][0][23] = 6,
+ [1][0][RTW89_MKK][1][23] = 42,
+ [1][0][RTW89_MKK][0][23] = 2,
+ [1][0][RTW89_IC][1][23] = -4,
+ [1][0][RTW89_KCC][1][23] = -2,
+ [1][0][RTW89_KCC][0][23] = -2,
+ [1][0][RTW89_ACMA][1][23] = 46,
+ [1][0][RTW89_ACMA][0][23] = 6,
+ [1][0][RTW89_CHILE][1][23] = -4,
+ [1][0][RTW89_QATAR][1][23] = 46,
+ [1][0][RTW89_QATAR][0][23] = 6,
+ [1][0][RTW89_UK][1][23] = 46,
+ [1][0][RTW89_UK][0][23] = 6,
+ [1][0][RTW89_FCC][1][25] = -4,
+ [1][0][RTW89_FCC][2][25] = 66,
+ [1][0][RTW89_ETSI][1][25] = 46,
+ [1][0][RTW89_ETSI][0][25] = 6,
+ [1][0][RTW89_MKK][1][25] = 42,
+ [1][0][RTW89_MKK][0][25] = 2,
+ [1][0][RTW89_IC][1][25] = -4,
+ [1][0][RTW89_KCC][1][25] = -2,
+ [1][0][RTW89_KCC][0][25] = -2,
+ [1][0][RTW89_ACMA][1][25] = 46,
+ [1][0][RTW89_ACMA][0][25] = 6,
+ [1][0][RTW89_CHILE][1][25] = -4,
+ [1][0][RTW89_QATAR][1][25] = 46,
+ [1][0][RTW89_QATAR][0][25] = 6,
+ [1][0][RTW89_UK][1][25] = 46,
+ [1][0][RTW89_UK][0][25] = 6,
+ [1][0][RTW89_FCC][1][27] = -4,
+ [1][0][RTW89_FCC][2][27] = 66,
+ [1][0][RTW89_ETSI][1][27] = 46,
+ [1][0][RTW89_ETSI][0][27] = 6,
+ [1][0][RTW89_MKK][1][27] = 42,
+ [1][0][RTW89_MKK][0][27] = 2,
+ [1][0][RTW89_IC][1][27] = -4,
+ [1][0][RTW89_KCC][1][27] = -2,
+ [1][0][RTW89_KCC][0][27] = -2,
+ [1][0][RTW89_ACMA][1][27] = 46,
+ [1][0][RTW89_ACMA][0][27] = 6,
+ [1][0][RTW89_CHILE][1][27] = -4,
+ [1][0][RTW89_QATAR][1][27] = 46,
+ [1][0][RTW89_QATAR][0][27] = 6,
+ [1][0][RTW89_UK][1][27] = 46,
+ [1][0][RTW89_UK][0][27] = 6,
+ [1][0][RTW89_FCC][1][29] = -4,
+ [1][0][RTW89_FCC][2][29] = 66,
+ [1][0][RTW89_ETSI][1][29] = 46,
+ [1][0][RTW89_ETSI][0][29] = 6,
+ [1][0][RTW89_MKK][1][29] = 42,
+ [1][0][RTW89_MKK][0][29] = 2,
+ [1][0][RTW89_IC][1][29] = -4,
+ [1][0][RTW89_KCC][1][29] = -2,
+ [1][0][RTW89_KCC][0][29] = -2,
+ [1][0][RTW89_ACMA][1][29] = 46,
+ [1][0][RTW89_ACMA][0][29] = 6,
+ [1][0][RTW89_CHILE][1][29] = -4,
+ [1][0][RTW89_QATAR][1][29] = 46,
+ [1][0][RTW89_QATAR][0][29] = 6,
+ [1][0][RTW89_UK][1][29] = 46,
+ [1][0][RTW89_UK][0][29] = 6,
+ [1][0][RTW89_FCC][1][30] = -4,
+ [1][0][RTW89_FCC][2][30] = 66,
+ [1][0][RTW89_ETSI][1][30] = 46,
+ [1][0][RTW89_ETSI][0][30] = 6,
+ [1][0][RTW89_MKK][1][30] = 42,
+ [1][0][RTW89_MKK][0][30] = 2,
+ [1][0][RTW89_IC][1][30] = -4,
+ [1][0][RTW89_KCC][1][30] = -2,
+ [1][0][RTW89_KCC][0][30] = -2,
+ [1][0][RTW89_ACMA][1][30] = 46,
+ [1][0][RTW89_ACMA][0][30] = 6,
+ [1][0][RTW89_CHILE][1][30] = -4,
+ [1][0][RTW89_QATAR][1][30] = 46,
+ [1][0][RTW89_QATAR][0][30] = 6,
+ [1][0][RTW89_UK][1][30] = 46,
+ [1][0][RTW89_UK][0][30] = 6,
+ [1][0][RTW89_FCC][1][32] = -4,
+ [1][0][RTW89_FCC][2][32] = 66,
+ [1][0][RTW89_ETSI][1][32] = 46,
+ [1][0][RTW89_ETSI][0][32] = 6,
+ [1][0][RTW89_MKK][1][32] = 42,
+ [1][0][RTW89_MKK][0][32] = 2,
+ [1][0][RTW89_IC][1][32] = -4,
+ [1][0][RTW89_KCC][1][32] = -2,
+ [1][0][RTW89_KCC][0][32] = -2,
+ [1][0][RTW89_ACMA][1][32] = 46,
+ [1][0][RTW89_ACMA][0][32] = 6,
+ [1][0][RTW89_CHILE][1][32] = -4,
+ [1][0][RTW89_QATAR][1][32] = 46,
+ [1][0][RTW89_QATAR][0][32] = 6,
+ [1][0][RTW89_UK][1][32] = 46,
+ [1][0][RTW89_UK][0][32] = 6,
+ [1][0][RTW89_FCC][1][34] = -4,
+ [1][0][RTW89_FCC][2][34] = 66,
+ [1][0][RTW89_ETSI][1][34] = 46,
+ [1][0][RTW89_ETSI][0][34] = 6,
+ [1][0][RTW89_MKK][1][34] = 42,
+ [1][0][RTW89_MKK][0][34] = 2,
+ [1][0][RTW89_IC][1][34] = -4,
+ [1][0][RTW89_KCC][1][34] = -2,
+ [1][0][RTW89_KCC][0][34] = -2,
+ [1][0][RTW89_ACMA][1][34] = 46,
+ [1][0][RTW89_ACMA][0][34] = 6,
+ [1][0][RTW89_CHILE][1][34] = -4,
+ [1][0][RTW89_QATAR][1][34] = 46,
+ [1][0][RTW89_QATAR][0][34] = 6,
+ [1][0][RTW89_UK][1][34] = 46,
+ [1][0][RTW89_UK][0][34] = 6,
+ [1][0][RTW89_FCC][1][36] = -4,
+ [1][0][RTW89_FCC][2][36] = 66,
+ [1][0][RTW89_ETSI][1][36] = 46,
+ [1][0][RTW89_ETSI][0][36] = 6,
+ [1][0][RTW89_MKK][1][36] = 42,
+ [1][0][RTW89_MKK][0][36] = 2,
+ [1][0][RTW89_IC][1][36] = -4,
+ [1][0][RTW89_KCC][1][36] = -2,
+ [1][0][RTW89_KCC][0][36] = -2,
+ [1][0][RTW89_ACMA][1][36] = 46,
+ [1][0][RTW89_ACMA][0][36] = 6,
+ [1][0][RTW89_CHILE][1][36] = -4,
+ [1][0][RTW89_QATAR][1][36] = 46,
+ [1][0][RTW89_QATAR][0][36] = 6,
+ [1][0][RTW89_UK][1][36] = 46,
+ [1][0][RTW89_UK][0][36] = 6,
+ [1][0][RTW89_FCC][1][38] = -4,
+ [1][0][RTW89_FCC][2][38] = 66,
+ [1][0][RTW89_ETSI][1][38] = 46,
+ [1][0][RTW89_ETSI][0][38] = 6,
+ [1][0][RTW89_MKK][1][38] = 42,
+ [1][0][RTW89_MKK][0][38] = 2,
+ [1][0][RTW89_IC][1][38] = -4,
+ [1][0][RTW89_KCC][1][38] = -2,
+ [1][0][RTW89_KCC][0][38] = -2,
+ [1][0][RTW89_ACMA][1][38] = 46,
+ [1][0][RTW89_ACMA][0][38] = 6,
+ [1][0][RTW89_CHILE][1][38] = -4,
+ [1][0][RTW89_QATAR][1][38] = 46,
+ [1][0][RTW89_QATAR][0][38] = 6,
+ [1][0][RTW89_UK][1][38] = 46,
+ [1][0][RTW89_UK][0][38] = 6,
+ [1][0][RTW89_FCC][1][40] = -4,
+ [1][0][RTW89_FCC][2][40] = 66,
+ [1][0][RTW89_ETSI][1][40] = 46,
+ [1][0][RTW89_ETSI][0][40] = 6,
+ [1][0][RTW89_MKK][1][40] = 42,
+ [1][0][RTW89_MKK][0][40] = 2,
+ [1][0][RTW89_IC][1][40] = -4,
+ [1][0][RTW89_KCC][1][40] = -2,
+ [1][0][RTW89_KCC][0][40] = -2,
+ [1][0][RTW89_ACMA][1][40] = 46,
+ [1][0][RTW89_ACMA][0][40] = 6,
+ [1][0][RTW89_CHILE][1][40] = -4,
+ [1][0][RTW89_QATAR][1][40] = 46,
+ [1][0][RTW89_QATAR][0][40] = 6,
+ [1][0][RTW89_UK][1][40] = 46,
+ [1][0][RTW89_UK][0][40] = 6,
+ [1][0][RTW89_FCC][1][42] = -4,
+ [1][0][RTW89_FCC][2][42] = 66,
+ [1][0][RTW89_ETSI][1][42] = 46,
+ [1][0][RTW89_ETSI][0][42] = 6,
+ [1][0][RTW89_MKK][1][42] = 42,
+ [1][0][RTW89_MKK][0][42] = 2,
+ [1][0][RTW89_IC][1][42] = -4,
+ [1][0][RTW89_KCC][1][42] = -2,
+ [1][0][RTW89_KCC][0][42] = -2,
+ [1][0][RTW89_ACMA][1][42] = 46,
+ [1][0][RTW89_ACMA][0][42] = 6,
+ [1][0][RTW89_CHILE][1][42] = -4,
+ [1][0][RTW89_QATAR][1][42] = 46,
+ [1][0][RTW89_QATAR][0][42] = 6,
+ [1][0][RTW89_UK][1][42] = 46,
+ [1][0][RTW89_UK][0][42] = 6,
+ [1][0][RTW89_FCC][1][44] = -4,
+ [1][0][RTW89_FCC][2][44] = 66,
+ [1][0][RTW89_ETSI][1][44] = 46,
+ [1][0][RTW89_ETSI][0][44] = 8,
+ [1][0][RTW89_MKK][1][44] = 22,
+ [1][0][RTW89_MKK][0][44] = 4,
+ [1][0][RTW89_IC][1][44] = -4,
+ [1][0][RTW89_KCC][1][44] = -2,
+ [1][0][RTW89_KCC][0][44] = -2,
+ [1][0][RTW89_ACMA][1][44] = 46,
+ [1][0][RTW89_ACMA][0][44] = 8,
+ [1][0][RTW89_CHILE][1][44] = -4,
+ [1][0][RTW89_QATAR][1][44] = 46,
+ [1][0][RTW89_QATAR][0][44] = 8,
+ [1][0][RTW89_UK][1][44] = 46,
+ [1][0][RTW89_UK][0][44] = 8,
+ [1][0][RTW89_FCC][1][45] = -4,
+ [1][0][RTW89_FCC][2][45] = 127,
+ [1][0][RTW89_ETSI][1][45] = 127,
+ [1][0][RTW89_ETSI][0][45] = 127,
+ [1][0][RTW89_MKK][1][45] = 127,
+ [1][0][RTW89_MKK][0][45] = 127,
+ [1][0][RTW89_IC][1][45] = -4,
+ [1][0][RTW89_KCC][1][45] = -2,
+ [1][0][RTW89_KCC][0][45] = 127,
+ [1][0][RTW89_ACMA][1][45] = 127,
+ [1][0][RTW89_ACMA][0][45] = 127,
+ [1][0][RTW89_CHILE][1][45] = 127,
+ [1][0][RTW89_QATAR][1][45] = 127,
+ [1][0][RTW89_QATAR][0][45] = 127,
+ [1][0][RTW89_UK][1][45] = 127,
+ [1][0][RTW89_UK][0][45] = 127,
+ [1][0][RTW89_FCC][1][47] = -4,
+ [1][0][RTW89_FCC][2][47] = 127,
+ [1][0][RTW89_ETSI][1][47] = 127,
+ [1][0][RTW89_ETSI][0][47] = 127,
+ [1][0][RTW89_MKK][1][47] = 127,
+ [1][0][RTW89_MKK][0][47] = 127,
+ [1][0][RTW89_IC][1][47] = -4,
+ [1][0][RTW89_KCC][1][47] = -2,
+ [1][0][RTW89_KCC][0][47] = 127,
+ [1][0][RTW89_ACMA][1][47] = 127,
+ [1][0][RTW89_ACMA][0][47] = 127,
+ [1][0][RTW89_CHILE][1][47] = 127,
+ [1][0][RTW89_QATAR][1][47] = 127,
+ [1][0][RTW89_QATAR][0][47] = 127,
+ [1][0][RTW89_UK][1][47] = 127,
+ [1][0][RTW89_UK][0][47] = 127,
+ [1][0][RTW89_FCC][1][49] = -4,
+ [1][0][RTW89_FCC][2][49] = 127,
+ [1][0][RTW89_ETSI][1][49] = 127,
+ [1][0][RTW89_ETSI][0][49] = 127,
+ [1][0][RTW89_MKK][1][49] = 127,
+ [1][0][RTW89_MKK][0][49] = 127,
+ [1][0][RTW89_IC][1][49] = -4,
+ [1][0][RTW89_KCC][1][49] = -2,
+ [1][0][RTW89_KCC][0][49] = 127,
+ [1][0][RTW89_ACMA][1][49] = 127,
+ [1][0][RTW89_ACMA][0][49] = 127,
+ [1][0][RTW89_CHILE][1][49] = 127,
+ [1][0][RTW89_QATAR][1][49] = 127,
+ [1][0][RTW89_QATAR][0][49] = 127,
+ [1][0][RTW89_UK][1][49] = 127,
+ [1][0][RTW89_UK][0][49] = 127,
+ [1][0][RTW89_FCC][1][51] = -4,
+ [1][0][RTW89_FCC][2][51] = 127,
+ [1][0][RTW89_ETSI][1][51] = 127,
+ [1][0][RTW89_ETSI][0][51] = 127,
+ [1][0][RTW89_MKK][1][51] = 127,
+ [1][0][RTW89_MKK][0][51] = 127,
+ [1][0][RTW89_IC][1][51] = -4,
+ [1][0][RTW89_KCC][1][51] = -2,
+ [1][0][RTW89_KCC][0][51] = 127,
+ [1][0][RTW89_ACMA][1][51] = 127,
+ [1][0][RTW89_ACMA][0][51] = 127,
+ [1][0][RTW89_CHILE][1][51] = 127,
+ [1][0][RTW89_QATAR][1][51] = 127,
+ [1][0][RTW89_QATAR][0][51] = 127,
+ [1][0][RTW89_UK][1][51] = 127,
+ [1][0][RTW89_UK][0][51] = 127,
+ [1][0][RTW89_FCC][1][53] = -4,
+ [1][0][RTW89_FCC][2][53] = 127,
+ [1][0][RTW89_ETSI][1][53] = 127,
+ [1][0][RTW89_ETSI][0][53] = 127,
+ [1][0][RTW89_MKK][1][53] = 127,
+ [1][0][RTW89_MKK][0][53] = 127,
+ [1][0][RTW89_IC][1][53] = -4,
+ [1][0][RTW89_KCC][1][53] = -2,
+ [1][0][RTW89_KCC][0][53] = 127,
+ [1][0][RTW89_ACMA][1][53] = 127,
+ [1][0][RTW89_ACMA][0][53] = 127,
+ [1][0][RTW89_CHILE][1][53] = 127,
+ [1][0][RTW89_QATAR][1][53] = 127,
+ [1][0][RTW89_QATAR][0][53] = 127,
+ [1][0][RTW89_UK][1][53] = 127,
+ [1][0][RTW89_UK][0][53] = 127,
+ [1][0][RTW89_FCC][1][55] = -4,
+ [1][0][RTW89_FCC][2][55] = 68,
+ [1][0][RTW89_ETSI][1][55] = 127,
+ [1][0][RTW89_ETSI][0][55] = 127,
+ [1][0][RTW89_MKK][1][55] = 127,
+ [1][0][RTW89_MKK][0][55] = 127,
+ [1][0][RTW89_IC][1][55] = -4,
+ [1][0][RTW89_KCC][1][55] = -2,
+ [1][0][RTW89_KCC][0][55] = 127,
+ [1][0][RTW89_ACMA][1][55] = 127,
+ [1][0][RTW89_ACMA][0][55] = 127,
+ [1][0][RTW89_CHILE][1][55] = 127,
+ [1][0][RTW89_QATAR][1][55] = 127,
+ [1][0][RTW89_QATAR][0][55] = 127,
+ [1][0][RTW89_UK][1][55] = 127,
+ [1][0][RTW89_UK][0][55] = 127,
+ [1][0][RTW89_FCC][1][57] = -4,
+ [1][0][RTW89_FCC][2][57] = 68,
+ [1][0][RTW89_ETSI][1][57] = 127,
+ [1][0][RTW89_ETSI][0][57] = 127,
+ [1][0][RTW89_MKK][1][57] = 127,
+ [1][0][RTW89_MKK][0][57] = 127,
+ [1][0][RTW89_IC][1][57] = -4,
+ [1][0][RTW89_KCC][1][57] = -2,
+ [1][0][RTW89_KCC][0][57] = 127,
+ [1][0][RTW89_ACMA][1][57] = 127,
+ [1][0][RTW89_ACMA][0][57] = 127,
+ [1][0][RTW89_CHILE][1][57] = 127,
+ [1][0][RTW89_QATAR][1][57] = 127,
+ [1][0][RTW89_QATAR][0][57] = 127,
+ [1][0][RTW89_UK][1][57] = 127,
+ [1][0][RTW89_UK][0][57] = 127,
+ [1][0][RTW89_FCC][1][59] = -4,
+ [1][0][RTW89_FCC][2][59] = 68,
+ [1][0][RTW89_ETSI][1][59] = 127,
+ [1][0][RTW89_ETSI][0][59] = 127,
+ [1][0][RTW89_MKK][1][59] = 127,
+ [1][0][RTW89_MKK][0][59] = 127,
+ [1][0][RTW89_IC][1][59] = -4,
+ [1][0][RTW89_KCC][1][59] = -2,
+ [1][0][RTW89_KCC][0][59] = 127,
+ [1][0][RTW89_ACMA][1][59] = 127,
+ [1][0][RTW89_ACMA][0][59] = 127,
+ [1][0][RTW89_CHILE][1][59] = 127,
+ [1][0][RTW89_QATAR][1][59] = 127,
+ [1][0][RTW89_QATAR][0][59] = 127,
+ [1][0][RTW89_UK][1][59] = 127,
+ [1][0][RTW89_UK][0][59] = 127,
+ [1][0][RTW89_FCC][1][60] = -4,
+ [1][0][RTW89_FCC][2][60] = 68,
+ [1][0][RTW89_ETSI][1][60] = 127,
+ [1][0][RTW89_ETSI][0][60] = 127,
+ [1][0][RTW89_MKK][1][60] = 127,
+ [1][0][RTW89_MKK][0][60] = 127,
+ [1][0][RTW89_IC][1][60] = -4,
+ [1][0][RTW89_KCC][1][60] = -2,
+ [1][0][RTW89_KCC][0][60] = 127,
+ [1][0][RTW89_ACMA][1][60] = 127,
+ [1][0][RTW89_ACMA][0][60] = 127,
+ [1][0][RTW89_CHILE][1][60] = 127,
+ [1][0][RTW89_QATAR][1][60] = 127,
+ [1][0][RTW89_QATAR][0][60] = 127,
+ [1][0][RTW89_UK][1][60] = 127,
+ [1][0][RTW89_UK][0][60] = 127,
+ [1][0][RTW89_FCC][1][62] = -4,
+ [1][0][RTW89_FCC][2][62] = 68,
+ [1][0][RTW89_ETSI][1][62] = 127,
+ [1][0][RTW89_ETSI][0][62] = 127,
+ [1][0][RTW89_MKK][1][62] = 127,
+ [1][0][RTW89_MKK][0][62] = 127,
+ [1][0][RTW89_IC][1][62] = -4,
+ [1][0][RTW89_KCC][1][62] = -2,
+ [1][0][RTW89_KCC][0][62] = 127,
+ [1][0][RTW89_ACMA][1][62] = 127,
+ [1][0][RTW89_ACMA][0][62] = 127,
+ [1][0][RTW89_CHILE][1][62] = 127,
+ [1][0][RTW89_QATAR][1][62] = 127,
+ [1][0][RTW89_QATAR][0][62] = 127,
+ [1][0][RTW89_UK][1][62] = 127,
+ [1][0][RTW89_UK][0][62] = 127,
+ [1][0][RTW89_FCC][1][64] = -4,
+ [1][0][RTW89_FCC][2][64] = 68,
+ [1][0][RTW89_ETSI][1][64] = 127,
+ [1][0][RTW89_ETSI][0][64] = 127,
+ [1][0][RTW89_MKK][1][64] = 127,
+ [1][0][RTW89_MKK][0][64] = 127,
+ [1][0][RTW89_IC][1][64] = -4,
+ [1][0][RTW89_KCC][1][64] = -2,
+ [1][0][RTW89_KCC][0][64] = 127,
+ [1][0][RTW89_ACMA][1][64] = 127,
+ [1][0][RTW89_ACMA][0][64] = 127,
+ [1][0][RTW89_CHILE][1][64] = 127,
+ [1][0][RTW89_QATAR][1][64] = 127,
+ [1][0][RTW89_QATAR][0][64] = 127,
+ [1][0][RTW89_UK][1][64] = 127,
+ [1][0][RTW89_UK][0][64] = 127,
+ [1][0][RTW89_FCC][1][66] = -4,
+ [1][0][RTW89_FCC][2][66] = 68,
+ [1][0][RTW89_ETSI][1][66] = 127,
+ [1][0][RTW89_ETSI][0][66] = 127,
+ [1][0][RTW89_MKK][1][66] = 127,
+ [1][0][RTW89_MKK][0][66] = 127,
+ [1][0][RTW89_IC][1][66] = -4,
+ [1][0][RTW89_KCC][1][66] = -2,
+ [1][0][RTW89_KCC][0][66] = 127,
+ [1][0][RTW89_ACMA][1][66] = 127,
+ [1][0][RTW89_ACMA][0][66] = 127,
+ [1][0][RTW89_CHILE][1][66] = 127,
+ [1][0][RTW89_QATAR][1][66] = 127,
+ [1][0][RTW89_QATAR][0][66] = 127,
+ [1][0][RTW89_UK][1][66] = 127,
+ [1][0][RTW89_UK][0][66] = 127,
+ [1][0][RTW89_FCC][1][68] = -4,
+ [1][0][RTW89_FCC][2][68] = 68,
+ [1][0][RTW89_ETSI][1][68] = 127,
+ [1][0][RTW89_ETSI][0][68] = 127,
+ [1][0][RTW89_MKK][1][68] = 127,
+ [1][0][RTW89_MKK][0][68] = 127,
+ [1][0][RTW89_IC][1][68] = -4,
+ [1][0][RTW89_KCC][1][68] = -2,
+ [1][0][RTW89_KCC][0][68] = 127,
+ [1][0][RTW89_ACMA][1][68] = 127,
+ [1][0][RTW89_ACMA][0][68] = 127,
+ [1][0][RTW89_CHILE][1][68] = 127,
+ [1][0][RTW89_QATAR][1][68] = 127,
+ [1][0][RTW89_QATAR][0][68] = 127,
+ [1][0][RTW89_UK][1][68] = 127,
+ [1][0][RTW89_UK][0][68] = 127,
+ [1][0][RTW89_FCC][1][70] = -4,
+ [1][0][RTW89_FCC][2][70] = 68,
+ [1][0][RTW89_ETSI][1][70] = 127,
+ [1][0][RTW89_ETSI][0][70] = 127,
+ [1][0][RTW89_MKK][1][70] = 127,
+ [1][0][RTW89_MKK][0][70] = 127,
+ [1][0][RTW89_IC][1][70] = -4,
+ [1][0][RTW89_KCC][1][70] = -2,
+ [1][0][RTW89_KCC][0][70] = 127,
+ [1][0][RTW89_ACMA][1][70] = 127,
+ [1][0][RTW89_ACMA][0][70] = 127,
+ [1][0][RTW89_CHILE][1][70] = 127,
+ [1][0][RTW89_QATAR][1][70] = 127,
+ [1][0][RTW89_QATAR][0][70] = 127,
+ [1][0][RTW89_UK][1][70] = 127,
+ [1][0][RTW89_UK][0][70] = 127,
+ [1][0][RTW89_FCC][1][72] = -4,
+ [1][0][RTW89_FCC][2][72] = 68,
+ [1][0][RTW89_ETSI][1][72] = 127,
+ [1][0][RTW89_ETSI][0][72] = 127,
+ [1][0][RTW89_MKK][1][72] = 127,
+ [1][0][RTW89_MKK][0][72] = 127,
+ [1][0][RTW89_IC][1][72] = -4,
+ [1][0][RTW89_KCC][1][72] = -2,
+ [1][0][RTW89_KCC][0][72] = 127,
+ [1][0][RTW89_ACMA][1][72] = 127,
+ [1][0][RTW89_ACMA][0][72] = 127,
+ [1][0][RTW89_CHILE][1][72] = 127,
+ [1][0][RTW89_QATAR][1][72] = 127,
+ [1][0][RTW89_QATAR][0][72] = 127,
+ [1][0][RTW89_UK][1][72] = 127,
+ [1][0][RTW89_UK][0][72] = 127,
+ [1][0][RTW89_FCC][1][74] = -4,
+ [1][0][RTW89_FCC][2][74] = 68,
+ [1][0][RTW89_ETSI][1][74] = 127,
+ [1][0][RTW89_ETSI][0][74] = 127,
+ [1][0][RTW89_MKK][1][74] = 127,
+ [1][0][RTW89_MKK][0][74] = 127,
+ [1][0][RTW89_IC][1][74] = -4,
+ [1][0][RTW89_KCC][1][74] = -2,
+ [1][0][RTW89_KCC][0][74] = 127,
+ [1][0][RTW89_ACMA][1][74] = 127,
+ [1][0][RTW89_ACMA][0][74] = 127,
+ [1][0][RTW89_CHILE][1][74] = 127,
+ [1][0][RTW89_QATAR][1][74] = 127,
+ [1][0][RTW89_QATAR][0][74] = 127,
+ [1][0][RTW89_UK][1][74] = 127,
+ [1][0][RTW89_UK][0][74] = 127,
+ [1][0][RTW89_FCC][1][75] = -4,
+ [1][0][RTW89_FCC][2][75] = 68,
+ [1][0][RTW89_ETSI][1][75] = 127,
+ [1][0][RTW89_ETSI][0][75] = 127,
+ [1][0][RTW89_MKK][1][75] = 127,
+ [1][0][RTW89_MKK][0][75] = 127,
+ [1][0][RTW89_IC][1][75] = -4,
+ [1][0][RTW89_KCC][1][75] = -2,
+ [1][0][RTW89_KCC][0][75] = 127,
+ [1][0][RTW89_ACMA][1][75] = 127,
+ [1][0][RTW89_ACMA][0][75] = 127,
+ [1][0][RTW89_CHILE][1][75] = 127,
+ [1][0][RTW89_QATAR][1][75] = 127,
+ [1][0][RTW89_QATAR][0][75] = 127,
+ [1][0][RTW89_UK][1][75] = 127,
+ [1][0][RTW89_UK][0][75] = 127,
+ [1][0][RTW89_FCC][1][77] = -4,
+ [1][0][RTW89_FCC][2][77] = 68,
+ [1][0][RTW89_ETSI][1][77] = 127,
+ [1][0][RTW89_ETSI][0][77] = 127,
+ [1][0][RTW89_MKK][1][77] = 127,
+ [1][0][RTW89_MKK][0][77] = 127,
+ [1][0][RTW89_IC][1][77] = -4,
+ [1][0][RTW89_KCC][1][77] = -2,
+ [1][0][RTW89_KCC][0][77] = 127,
+ [1][0][RTW89_ACMA][1][77] = 127,
+ [1][0][RTW89_ACMA][0][77] = 127,
+ [1][0][RTW89_CHILE][1][77] = 127,
+ [1][0][RTW89_QATAR][1][77] = 127,
+ [1][0][RTW89_QATAR][0][77] = 127,
+ [1][0][RTW89_UK][1][77] = 127,
+ [1][0][RTW89_UK][0][77] = 127,
+ [1][0][RTW89_FCC][1][79] = -4,
+ [1][0][RTW89_FCC][2][79] = 68,
+ [1][0][RTW89_ETSI][1][79] = 127,
+ [1][0][RTW89_ETSI][0][79] = 127,
+ [1][0][RTW89_MKK][1][79] = 127,
+ [1][0][RTW89_MKK][0][79] = 127,
+ [1][0][RTW89_IC][1][79] = -4,
+ [1][0][RTW89_KCC][1][79] = -2,
+ [1][0][RTW89_KCC][0][79] = 127,
+ [1][0][RTW89_ACMA][1][79] = 127,
+ [1][0][RTW89_ACMA][0][79] = 127,
+ [1][0][RTW89_CHILE][1][79] = 127,
+ [1][0][RTW89_QATAR][1][79] = 127,
+ [1][0][RTW89_QATAR][0][79] = 127,
+ [1][0][RTW89_UK][1][79] = 127,
+ [1][0][RTW89_UK][0][79] = 127,
+ [1][0][RTW89_FCC][1][81] = -4,
+ [1][0][RTW89_FCC][2][81] = 68,
+ [1][0][RTW89_ETSI][1][81] = 127,
+ [1][0][RTW89_ETSI][0][81] = 127,
+ [1][0][RTW89_MKK][1][81] = 127,
+ [1][0][RTW89_MKK][0][81] = 127,
+ [1][0][RTW89_IC][1][81] = -4,
+ [1][0][RTW89_KCC][1][81] = -2,
+ [1][0][RTW89_KCC][0][81] = 127,
+ [1][0][RTW89_ACMA][1][81] = 127,
+ [1][0][RTW89_ACMA][0][81] = 127,
+ [1][0][RTW89_CHILE][1][81] = 127,
+ [1][0][RTW89_QATAR][1][81] = 127,
+ [1][0][RTW89_QATAR][0][81] = 127,
+ [1][0][RTW89_UK][1][81] = 127,
+ [1][0][RTW89_UK][0][81] = 127,
+ [1][0][RTW89_FCC][1][83] = -4,
+ [1][0][RTW89_FCC][2][83] = 68,
+ [1][0][RTW89_ETSI][1][83] = 127,
+ [1][0][RTW89_ETSI][0][83] = 127,
+ [1][0][RTW89_MKK][1][83] = 127,
+ [1][0][RTW89_MKK][0][83] = 127,
+ [1][0][RTW89_IC][1][83] = -4,
+ [1][0][RTW89_KCC][1][83] = -2,
+ [1][0][RTW89_KCC][0][83] = 127,
+ [1][0][RTW89_ACMA][1][83] = 127,
+ [1][0][RTW89_ACMA][0][83] = 127,
+ [1][0][RTW89_CHILE][1][83] = 127,
+ [1][0][RTW89_QATAR][1][83] = 127,
+ [1][0][RTW89_QATAR][0][83] = 127,
+ [1][0][RTW89_UK][1][83] = 127,
+ [1][0][RTW89_UK][0][83] = 127,
+ [1][0][RTW89_FCC][1][85] = -4,
+ [1][0][RTW89_FCC][2][85] = 68,
+ [1][0][RTW89_ETSI][1][85] = 127,
+ [1][0][RTW89_ETSI][0][85] = 127,
+ [1][0][RTW89_MKK][1][85] = 127,
+ [1][0][RTW89_MKK][0][85] = 127,
+ [1][0][RTW89_IC][1][85] = -4,
+ [1][0][RTW89_KCC][1][85] = -2,
+ [1][0][RTW89_KCC][0][85] = 127,
+ [1][0][RTW89_ACMA][1][85] = 127,
+ [1][0][RTW89_ACMA][0][85] = 127,
+ [1][0][RTW89_CHILE][1][85] = 127,
+ [1][0][RTW89_QATAR][1][85] = 127,
+ [1][0][RTW89_QATAR][0][85] = 127,
+ [1][0][RTW89_UK][1][85] = 127,
+ [1][0][RTW89_UK][0][85] = 127,
+ [1][0][RTW89_FCC][1][87] = -4,
+ [1][0][RTW89_FCC][2][87] = 127,
+ [1][0][RTW89_ETSI][1][87] = 127,
+ [1][0][RTW89_ETSI][0][87] = 127,
+ [1][0][RTW89_MKK][1][87] = 127,
+ [1][0][RTW89_MKK][0][87] = 127,
+ [1][0][RTW89_IC][1][87] = -4,
+ [1][0][RTW89_KCC][1][87] = -2,
+ [1][0][RTW89_KCC][0][87] = 127,
+ [1][0][RTW89_ACMA][1][87] = 127,
+ [1][0][RTW89_ACMA][0][87] = 127,
+ [1][0][RTW89_CHILE][1][87] = 127,
+ [1][0][RTW89_QATAR][1][87] = 127,
+ [1][0][RTW89_QATAR][0][87] = 127,
+ [1][0][RTW89_UK][1][87] = 127,
+ [1][0][RTW89_UK][0][87] = 127,
+ [1][0][RTW89_FCC][1][89] = -4,
+ [1][0][RTW89_FCC][2][89] = 127,
+ [1][0][RTW89_ETSI][1][89] = 127,
+ [1][0][RTW89_ETSI][0][89] = 127,
+ [1][0][RTW89_MKK][1][89] = 127,
+ [1][0][RTW89_MKK][0][89] = 127,
+ [1][0][RTW89_IC][1][89] = -4,
+ [1][0][RTW89_KCC][1][89] = -2,
+ [1][0][RTW89_KCC][0][89] = 127,
+ [1][0][RTW89_ACMA][1][89] = 127,
+ [1][0][RTW89_ACMA][0][89] = 127,
+ [1][0][RTW89_CHILE][1][89] = 127,
+ [1][0][RTW89_QATAR][1][89] = 127,
+ [1][0][RTW89_QATAR][0][89] = 127,
+ [1][0][RTW89_UK][1][89] = 127,
+ [1][0][RTW89_UK][0][89] = 127,
+ [1][0][RTW89_FCC][1][90] = -4,
+ [1][0][RTW89_FCC][2][90] = 127,
+ [1][0][RTW89_ETSI][1][90] = 127,
+ [1][0][RTW89_ETSI][0][90] = 127,
+ [1][0][RTW89_MKK][1][90] = 127,
+ [1][0][RTW89_MKK][0][90] = 127,
+ [1][0][RTW89_IC][1][90] = -4,
+ [1][0][RTW89_KCC][1][90] = -2,
+ [1][0][RTW89_KCC][0][90] = 127,
+ [1][0][RTW89_ACMA][1][90] = 127,
+ [1][0][RTW89_ACMA][0][90] = 127,
+ [1][0][RTW89_CHILE][1][90] = 127,
+ [1][0][RTW89_QATAR][1][90] = 127,
+ [1][0][RTW89_QATAR][0][90] = 127,
+ [1][0][RTW89_UK][1][90] = 127,
+ [1][0][RTW89_UK][0][90] = 127,
+ [1][0][RTW89_FCC][1][92] = -4,
+ [1][0][RTW89_FCC][2][92] = 127,
+ [1][0][RTW89_ETSI][1][92] = 127,
+ [1][0][RTW89_ETSI][0][92] = 127,
+ [1][0][RTW89_MKK][1][92] = 127,
+ [1][0][RTW89_MKK][0][92] = 127,
+ [1][0][RTW89_IC][1][92] = -4,
+ [1][0][RTW89_KCC][1][92] = -2,
+ [1][0][RTW89_KCC][0][92] = 127,
+ [1][0][RTW89_ACMA][1][92] = 127,
+ [1][0][RTW89_ACMA][0][92] = 127,
+ [1][0][RTW89_CHILE][1][92] = 127,
+ [1][0][RTW89_QATAR][1][92] = 127,
+ [1][0][RTW89_QATAR][0][92] = 127,
+ [1][0][RTW89_UK][1][92] = 127,
+ [1][0][RTW89_UK][0][92] = 127,
+ [1][0][RTW89_FCC][1][94] = -4,
+ [1][0][RTW89_FCC][2][94] = 127,
+ [1][0][RTW89_ETSI][1][94] = 127,
+ [1][0][RTW89_ETSI][0][94] = 127,
+ [1][0][RTW89_MKK][1][94] = 127,
+ [1][0][RTW89_MKK][0][94] = 127,
+ [1][0][RTW89_IC][1][94] = -4,
+ [1][0][RTW89_KCC][1][94] = -2,
+ [1][0][RTW89_KCC][0][94] = 127,
+ [1][0][RTW89_ACMA][1][94] = 127,
+ [1][0][RTW89_ACMA][0][94] = 127,
+ [1][0][RTW89_CHILE][1][94] = 127,
+ [1][0][RTW89_QATAR][1][94] = 127,
+ [1][0][RTW89_QATAR][0][94] = 127,
+ [1][0][RTW89_UK][1][94] = 127,
+ [1][0][RTW89_UK][0][94] = 127,
+ [1][0][RTW89_FCC][1][96] = -4,
+ [1][0][RTW89_FCC][2][96] = 127,
+ [1][0][RTW89_ETSI][1][96] = 127,
+ [1][0][RTW89_ETSI][0][96] = 127,
+ [1][0][RTW89_MKK][1][96] = 127,
+ [1][0][RTW89_MKK][0][96] = 127,
+ [1][0][RTW89_IC][1][96] = -4,
+ [1][0][RTW89_KCC][1][96] = -2,
+ [1][0][RTW89_KCC][0][96] = 127,
+ [1][0][RTW89_ACMA][1][96] = 127,
+ [1][0][RTW89_ACMA][0][96] = 127,
+ [1][0][RTW89_CHILE][1][96] = 127,
+ [1][0][RTW89_QATAR][1][96] = 127,
+ [1][0][RTW89_QATAR][0][96] = 127,
+ [1][0][RTW89_UK][1][96] = 127,
+ [1][0][RTW89_UK][0][96] = 127,
+ [1][0][RTW89_FCC][1][98] = -4,
+ [1][0][RTW89_FCC][2][98] = 127,
+ [1][0][RTW89_ETSI][1][98] = 127,
+ [1][0][RTW89_ETSI][0][98] = 127,
+ [1][0][RTW89_MKK][1][98] = 127,
+ [1][0][RTW89_MKK][0][98] = 127,
+ [1][0][RTW89_IC][1][98] = -4,
+ [1][0][RTW89_KCC][1][98] = -2,
+ [1][0][RTW89_KCC][0][98] = 127,
+ [1][0][RTW89_ACMA][1][98] = 127,
+ [1][0][RTW89_ACMA][0][98] = 127,
+ [1][0][RTW89_CHILE][1][98] = 127,
+ [1][0][RTW89_QATAR][1][98] = 127,
+ [1][0][RTW89_QATAR][0][98] = 127,
+ [1][0][RTW89_UK][1][98] = 127,
+ [1][0][RTW89_UK][0][98] = 127,
+ [1][0][RTW89_FCC][1][100] = -4,
+ [1][0][RTW89_FCC][2][100] = 127,
+ [1][0][RTW89_ETSI][1][100] = 127,
+ [1][0][RTW89_ETSI][0][100] = 127,
+ [1][0][RTW89_MKK][1][100] = 127,
+ [1][0][RTW89_MKK][0][100] = 127,
+ [1][0][RTW89_IC][1][100] = -4,
+ [1][0][RTW89_KCC][1][100] = -2,
+ [1][0][RTW89_KCC][0][100] = 127,
+ [1][0][RTW89_ACMA][1][100] = 127,
+ [1][0][RTW89_ACMA][0][100] = 127,
+ [1][0][RTW89_CHILE][1][100] = 127,
+ [1][0][RTW89_QATAR][1][100] = 127,
+ [1][0][RTW89_QATAR][0][100] = 127,
+ [1][0][RTW89_UK][1][100] = 127,
+ [1][0][RTW89_UK][0][100] = 127,
+ [1][0][RTW89_FCC][1][102] = -4,
+ [1][0][RTW89_FCC][2][102] = 127,
+ [1][0][RTW89_ETSI][1][102] = 127,
+ [1][0][RTW89_ETSI][0][102] = 127,
+ [1][0][RTW89_MKK][1][102] = 127,
+ [1][0][RTW89_MKK][0][102] = 127,
+ [1][0][RTW89_IC][1][102] = -4,
+ [1][0][RTW89_KCC][1][102] = -2,
+ [1][0][RTW89_KCC][0][102] = 127,
+ [1][0][RTW89_ACMA][1][102] = 127,
+ [1][0][RTW89_ACMA][0][102] = 127,
+ [1][0][RTW89_CHILE][1][102] = 127,
+ [1][0][RTW89_QATAR][1][102] = 127,
+ [1][0][RTW89_QATAR][0][102] = 127,
+ [1][0][RTW89_UK][1][102] = 127,
+ [1][0][RTW89_UK][0][102] = 127,
+ [1][0][RTW89_FCC][1][104] = -4,
+ [1][0][RTW89_FCC][2][104] = 127,
+ [1][0][RTW89_ETSI][1][104] = 127,
+ [1][0][RTW89_ETSI][0][104] = 127,
+ [1][0][RTW89_MKK][1][104] = 127,
+ [1][0][RTW89_MKK][0][104] = 127,
+ [1][0][RTW89_IC][1][104] = -4,
+ [1][0][RTW89_KCC][1][104] = -2,
+ [1][0][RTW89_KCC][0][104] = 127,
+ [1][0][RTW89_ACMA][1][104] = 127,
+ [1][0][RTW89_ACMA][0][104] = 127,
+ [1][0][RTW89_CHILE][1][104] = 127,
+ [1][0][RTW89_QATAR][1][104] = 127,
+ [1][0][RTW89_QATAR][0][104] = 127,
+ [1][0][RTW89_UK][1][104] = 127,
+ [1][0][RTW89_UK][0][104] = 127,
+ [1][0][RTW89_FCC][1][105] = -4,
+ [1][0][RTW89_FCC][2][105] = 127,
+ [1][0][RTW89_ETSI][1][105] = 127,
+ [1][0][RTW89_ETSI][0][105] = 127,
+ [1][0][RTW89_MKK][1][105] = 127,
+ [1][0][RTW89_MKK][0][105] = 127,
+ [1][0][RTW89_IC][1][105] = -4,
+ [1][0][RTW89_KCC][1][105] = -2,
+ [1][0][RTW89_KCC][0][105] = 127,
+ [1][0][RTW89_ACMA][1][105] = 127,
+ [1][0][RTW89_ACMA][0][105] = 127,
+ [1][0][RTW89_CHILE][1][105] = 127,
+ [1][0][RTW89_QATAR][1][105] = 127,
+ [1][0][RTW89_QATAR][0][105] = 127,
+ [1][0][RTW89_UK][1][105] = 127,
+ [1][0][RTW89_UK][0][105] = 127,
+ [1][0][RTW89_FCC][1][107] = 1,
+ [1][0][RTW89_FCC][2][107] = 127,
+ [1][0][RTW89_ETSI][1][107] = 127,
+ [1][0][RTW89_ETSI][0][107] = 127,
+ [1][0][RTW89_MKK][1][107] = 127,
+ [1][0][RTW89_MKK][0][107] = 127,
+ [1][0][RTW89_IC][1][107] = 1,
+ [1][0][RTW89_KCC][1][107] = -2,
+ [1][0][RTW89_KCC][0][107] = 127,
+ [1][0][RTW89_ACMA][1][107] = 127,
+ [1][0][RTW89_ACMA][0][107] = 127,
+ [1][0][RTW89_CHILE][1][107] = 127,
+ [1][0][RTW89_QATAR][1][107] = 127,
+ [1][0][RTW89_QATAR][0][107] = 127,
+ [1][0][RTW89_UK][1][107] = 127,
+ [1][0][RTW89_UK][0][107] = 127,
+ [1][0][RTW89_FCC][1][109] = 2,
+ [1][0][RTW89_FCC][2][109] = 127,
+ [1][0][RTW89_ETSI][1][109] = 127,
+ [1][0][RTW89_ETSI][0][109] = 127,
+ [1][0][RTW89_MKK][1][109] = 127,
+ [1][0][RTW89_MKK][0][109] = 127,
+ [1][0][RTW89_IC][1][109] = 2,
+ [1][0][RTW89_KCC][1][109] = 127,
+ [1][0][RTW89_KCC][0][109] = 127,
+ [1][0][RTW89_ACMA][1][109] = 127,
+ [1][0][RTW89_ACMA][0][109] = 127,
+ [1][0][RTW89_CHILE][1][109] = 127,
+ [1][0][RTW89_QATAR][1][109] = 127,
+ [1][0][RTW89_QATAR][0][109] = 127,
+ [1][0][RTW89_UK][1][109] = 127,
+ [1][0][RTW89_UK][0][109] = 127,
+ [1][0][RTW89_FCC][1][111] = 127,
+ [1][0][RTW89_FCC][2][111] = 127,
+ [1][0][RTW89_ETSI][1][111] = 127,
+ [1][0][RTW89_ETSI][0][111] = 127,
+ [1][0][RTW89_MKK][1][111] = 127,
+ [1][0][RTW89_MKK][0][111] = 127,
+ [1][0][RTW89_IC][1][111] = 127,
+ [1][0][RTW89_KCC][1][111] = 127,
+ [1][0][RTW89_KCC][0][111] = 127,
+ [1][0][RTW89_ACMA][1][111] = 127,
+ [1][0][RTW89_ACMA][0][111] = 127,
+ [1][0][RTW89_CHILE][1][111] = 127,
+ [1][0][RTW89_QATAR][1][111] = 127,
+ [1][0][RTW89_QATAR][0][111] = 127,
+ [1][0][RTW89_UK][1][111] = 127,
+ [1][0][RTW89_UK][0][111] = 127,
+ [1][0][RTW89_FCC][1][113] = 127,
+ [1][0][RTW89_FCC][2][113] = 127,
+ [1][0][RTW89_ETSI][1][113] = 127,
+ [1][0][RTW89_ETSI][0][113] = 127,
+ [1][0][RTW89_MKK][1][113] = 127,
+ [1][0][RTW89_MKK][0][113] = 127,
+ [1][0][RTW89_IC][1][113] = 127,
+ [1][0][RTW89_KCC][1][113] = 127,
+ [1][0][RTW89_KCC][0][113] = 127,
+ [1][0][RTW89_ACMA][1][113] = 127,
+ [1][0][RTW89_ACMA][0][113] = 127,
+ [1][0][RTW89_CHILE][1][113] = 127,
+ [1][0][RTW89_QATAR][1][113] = 127,
+ [1][0][RTW89_QATAR][0][113] = 127,
+ [1][0][RTW89_UK][1][113] = 127,
+ [1][0][RTW89_UK][0][113] = 127,
+ [1][0][RTW89_FCC][1][115] = 127,
+ [1][0][RTW89_FCC][2][115] = 127,
+ [1][0][RTW89_ETSI][1][115] = 127,
+ [1][0][RTW89_ETSI][0][115] = 127,
+ [1][0][RTW89_MKK][1][115] = 127,
+ [1][0][RTW89_MKK][0][115] = 127,
+ [1][0][RTW89_IC][1][115] = 127,
+ [1][0][RTW89_KCC][1][115] = 127,
+ [1][0][RTW89_KCC][0][115] = 127,
+ [1][0][RTW89_ACMA][1][115] = 127,
+ [1][0][RTW89_ACMA][0][115] = 127,
+ [1][0][RTW89_CHILE][1][115] = 127,
+ [1][0][RTW89_QATAR][1][115] = 127,
+ [1][0][RTW89_QATAR][0][115] = 127,
+ [1][0][RTW89_UK][1][115] = 127,
+ [1][0][RTW89_UK][0][115] = 127,
+ [1][0][RTW89_FCC][1][117] = 127,
+ [1][0][RTW89_FCC][2][117] = 127,
+ [1][0][RTW89_ETSI][1][117] = 127,
+ [1][0][RTW89_ETSI][0][117] = 127,
+ [1][0][RTW89_MKK][1][117] = 127,
+ [1][0][RTW89_MKK][0][117] = 127,
+ [1][0][RTW89_IC][1][117] = 127,
+ [1][0][RTW89_KCC][1][117] = 127,
+ [1][0][RTW89_KCC][0][117] = 127,
+ [1][0][RTW89_ACMA][1][117] = 127,
+ [1][0][RTW89_ACMA][0][117] = 127,
+ [1][0][RTW89_CHILE][1][117] = 127,
+ [1][0][RTW89_QATAR][1][117] = 127,
+ [1][0][RTW89_QATAR][0][117] = 127,
+ [1][0][RTW89_UK][1][117] = 127,
+ [1][0][RTW89_UK][0][117] = 127,
+ [1][0][RTW89_FCC][1][119] = 127,
+ [1][0][RTW89_FCC][2][119] = 127,
+ [1][0][RTW89_ETSI][1][119] = 127,
+ [1][0][RTW89_ETSI][0][119] = 127,
+ [1][0][RTW89_MKK][1][119] = 127,
+ [1][0][RTW89_MKK][0][119] = 127,
+ [1][0][RTW89_IC][1][119] = 127,
+ [1][0][RTW89_KCC][1][119] = 127,
+ [1][0][RTW89_KCC][0][119] = 127,
+ [1][0][RTW89_ACMA][1][119] = 127,
+ [1][0][RTW89_ACMA][0][119] = 127,
+ [1][0][RTW89_CHILE][1][119] = 127,
+ [1][0][RTW89_QATAR][1][119] = 127,
+ [1][0][RTW89_QATAR][0][119] = 127,
+ [1][0][RTW89_UK][1][119] = 127,
+ [1][0][RTW89_UK][0][119] = 127,
+ [1][1][RTW89_FCC][1][0] = -26,
+ [1][1][RTW89_FCC][2][0] = 44,
+ [1][1][RTW89_ETSI][1][0] = 32,
+ [1][1][RTW89_ETSI][0][0] = -6,
+ [1][1][RTW89_MKK][1][0] = 30,
+ [1][1][RTW89_MKK][0][0] = -10,
+ [1][1][RTW89_IC][1][0] = -26,
+ [1][1][RTW89_KCC][1][0] = -14,
+ [1][1][RTW89_KCC][0][0] = -14,
+ [1][1][RTW89_ACMA][1][0] = 32,
+ [1][1][RTW89_ACMA][0][0] = -6,
+ [1][1][RTW89_CHILE][1][0] = -26,
+ [1][1][RTW89_QATAR][1][0] = 32,
+ [1][1][RTW89_QATAR][0][0] = -6,
+ [1][1][RTW89_UK][1][0] = 32,
+ [1][1][RTW89_UK][0][0] = -6,
+ [1][1][RTW89_FCC][1][2] = -28,
+ [1][1][RTW89_FCC][2][2] = 44,
+ [1][1][RTW89_ETSI][1][2] = 32,
+ [1][1][RTW89_ETSI][0][2] = -6,
+ [1][1][RTW89_MKK][1][2] = 30,
+ [1][1][RTW89_MKK][0][2] = -10,
+ [1][1][RTW89_IC][1][2] = -28,
+ [1][1][RTW89_KCC][1][2] = -14,
+ [1][1][RTW89_KCC][0][2] = -14,
+ [1][1][RTW89_ACMA][1][2] = 32,
+ [1][1][RTW89_ACMA][0][2] = -6,
+ [1][1][RTW89_CHILE][1][2] = -28,
+ [1][1][RTW89_QATAR][1][2] = 32,
+ [1][1][RTW89_QATAR][0][2] = -6,
+ [1][1][RTW89_UK][1][2] = 32,
+ [1][1][RTW89_UK][0][2] = -6,
+ [1][1][RTW89_FCC][1][4] = -28,
+ [1][1][RTW89_FCC][2][4] = 44,
+ [1][1][RTW89_ETSI][1][4] = 32,
+ [1][1][RTW89_ETSI][0][4] = -6,
+ [1][1][RTW89_MKK][1][4] = 30,
+ [1][1][RTW89_MKK][0][4] = -10,
+ [1][1][RTW89_IC][1][4] = -28,
+ [1][1][RTW89_KCC][1][4] = -14,
+ [1][1][RTW89_KCC][0][4] = -14,
+ [1][1][RTW89_ACMA][1][4] = 32,
+ [1][1][RTW89_ACMA][0][4] = -6,
+ [1][1][RTW89_CHILE][1][4] = -28,
+ [1][1][RTW89_QATAR][1][4] = 32,
+ [1][1][RTW89_QATAR][0][4] = -6,
+ [1][1][RTW89_UK][1][4] = 32,
+ [1][1][RTW89_UK][0][4] = -6,
+ [1][1][RTW89_FCC][1][6] = -28,
+ [1][1][RTW89_FCC][2][6] = 44,
+ [1][1][RTW89_ETSI][1][6] = 32,
+ [1][1][RTW89_ETSI][0][6] = -6,
+ [1][1][RTW89_MKK][1][6] = 30,
+ [1][1][RTW89_MKK][0][6] = -10,
+ [1][1][RTW89_IC][1][6] = -28,
+ [1][1][RTW89_KCC][1][6] = -14,
+ [1][1][RTW89_KCC][0][6] = -14,
+ [1][1][RTW89_ACMA][1][6] = 32,
+ [1][1][RTW89_ACMA][0][6] = -6,
+ [1][1][RTW89_CHILE][1][6] = -28,
+ [1][1][RTW89_QATAR][1][6] = 32,
+ [1][1][RTW89_QATAR][0][6] = -6,
+ [1][1][RTW89_UK][1][6] = 32,
+ [1][1][RTW89_UK][0][6] = -6,
+ [1][1][RTW89_FCC][1][8] = -28,
+ [1][1][RTW89_FCC][2][8] = 44,
+ [1][1][RTW89_ETSI][1][8] = 32,
+ [1][1][RTW89_ETSI][0][8] = -6,
+ [1][1][RTW89_MKK][1][8] = 30,
+ [1][1][RTW89_MKK][0][8] = -10,
+ [1][1][RTW89_IC][1][8] = -28,
+ [1][1][RTW89_KCC][1][8] = -14,
+ [1][1][RTW89_KCC][0][8] = -14,
+ [1][1][RTW89_ACMA][1][8] = 32,
+ [1][1][RTW89_ACMA][0][8] = -6,
+ [1][1][RTW89_CHILE][1][8] = -28,
+ [1][1][RTW89_QATAR][1][8] = 32,
+ [1][1][RTW89_QATAR][0][8] = -6,
+ [1][1][RTW89_UK][1][8] = 32,
+ [1][1][RTW89_UK][0][8] = -6,
+ [1][1][RTW89_FCC][1][10] = -28,
+ [1][1][RTW89_FCC][2][10] = 44,
+ [1][1][RTW89_ETSI][1][10] = 32,
+ [1][1][RTW89_ETSI][0][10] = -6,
+ [1][1][RTW89_MKK][1][10] = 30,
+ [1][1][RTW89_MKK][0][10] = -10,
+ [1][1][RTW89_IC][1][10] = -28,
+ [1][1][RTW89_KCC][1][10] = -14,
+ [1][1][RTW89_KCC][0][10] = -14,
+ [1][1][RTW89_ACMA][1][10] = 32,
+ [1][1][RTW89_ACMA][0][10] = -6,
+ [1][1][RTW89_CHILE][1][10] = -28,
+ [1][1][RTW89_QATAR][1][10] = 32,
+ [1][1][RTW89_QATAR][0][10] = -6,
+ [1][1][RTW89_UK][1][10] = 32,
+ [1][1][RTW89_UK][0][10] = -6,
+ [1][1][RTW89_FCC][1][12] = -28,
+ [1][1][RTW89_FCC][2][12] = 44,
+ [1][1][RTW89_ETSI][1][12] = 32,
+ [1][1][RTW89_ETSI][0][12] = -6,
+ [1][1][RTW89_MKK][1][12] = 30,
+ [1][1][RTW89_MKK][0][12] = -10,
+ [1][1][RTW89_IC][1][12] = -28,
+ [1][1][RTW89_KCC][1][12] = -14,
+ [1][1][RTW89_KCC][0][12] = -14,
+ [1][1][RTW89_ACMA][1][12] = 32,
+ [1][1][RTW89_ACMA][0][12] = -6,
+ [1][1][RTW89_CHILE][1][12] = -28,
+ [1][1][RTW89_QATAR][1][12] = 32,
+ [1][1][RTW89_QATAR][0][12] = -6,
+ [1][1][RTW89_UK][1][12] = 32,
+ [1][1][RTW89_UK][0][12] = -6,
+ [1][1][RTW89_FCC][1][14] = -28,
+ [1][1][RTW89_FCC][2][14] = 44,
+ [1][1][RTW89_ETSI][1][14] = 32,
+ [1][1][RTW89_ETSI][0][14] = -6,
+ [1][1][RTW89_MKK][1][14] = 30,
+ [1][1][RTW89_MKK][0][14] = -10,
+ [1][1][RTW89_IC][1][14] = -28,
+ [1][1][RTW89_KCC][1][14] = -14,
+ [1][1][RTW89_KCC][0][14] = -14,
+ [1][1][RTW89_ACMA][1][14] = 32,
+ [1][1][RTW89_ACMA][0][14] = -6,
+ [1][1][RTW89_CHILE][1][14] = -28,
+ [1][1][RTW89_QATAR][1][14] = 32,
+ [1][1][RTW89_QATAR][0][14] = -6,
+ [1][1][RTW89_UK][1][14] = 32,
+ [1][1][RTW89_UK][0][14] = -6,
+ [1][1][RTW89_FCC][1][15] = -28,
+ [1][1][RTW89_FCC][2][15] = 44,
+ [1][1][RTW89_ETSI][1][15] = 32,
+ [1][1][RTW89_ETSI][0][15] = -6,
+ [1][1][RTW89_MKK][1][15] = 30,
+ [1][1][RTW89_MKK][0][15] = -10,
+ [1][1][RTW89_IC][1][15] = -28,
+ [1][1][RTW89_KCC][1][15] = -14,
+ [1][1][RTW89_KCC][0][15] = -14,
+ [1][1][RTW89_ACMA][1][15] = 32,
+ [1][1][RTW89_ACMA][0][15] = -6,
+ [1][1][RTW89_CHILE][1][15] = -28,
+ [1][1][RTW89_QATAR][1][15] = 32,
+ [1][1][RTW89_QATAR][0][15] = -6,
+ [1][1][RTW89_UK][1][15] = 32,
+ [1][1][RTW89_UK][0][15] = -6,
+ [1][1][RTW89_FCC][1][17] = -28,
+ [1][1][RTW89_FCC][2][17] = 44,
+ [1][1][RTW89_ETSI][1][17] = 32,
+ [1][1][RTW89_ETSI][0][17] = -6,
+ [1][1][RTW89_MKK][1][17] = 30,
+ [1][1][RTW89_MKK][0][17] = -10,
+ [1][1][RTW89_IC][1][17] = -28,
+ [1][1][RTW89_KCC][1][17] = -14,
+ [1][1][RTW89_KCC][0][17] = -14,
+ [1][1][RTW89_ACMA][1][17] = 32,
+ [1][1][RTW89_ACMA][0][17] = -6,
+ [1][1][RTW89_CHILE][1][17] = -28,
+ [1][1][RTW89_QATAR][1][17] = 32,
+ [1][1][RTW89_QATAR][0][17] = -6,
+ [1][1][RTW89_UK][1][17] = 32,
+ [1][1][RTW89_UK][0][17] = -6,
+ [1][1][RTW89_FCC][1][19] = -28,
+ [1][1][RTW89_FCC][2][19] = 44,
+ [1][1][RTW89_ETSI][1][19] = 32,
+ [1][1][RTW89_ETSI][0][19] = -6,
+ [1][1][RTW89_MKK][1][19] = 30,
+ [1][1][RTW89_MKK][0][19] = -10,
+ [1][1][RTW89_IC][1][19] = -28,
+ [1][1][RTW89_KCC][1][19] = -14,
+ [1][1][RTW89_KCC][0][19] = -14,
+ [1][1][RTW89_ACMA][1][19] = 32,
+ [1][1][RTW89_ACMA][0][19] = -6,
+ [1][1][RTW89_CHILE][1][19] = -28,
+ [1][1][RTW89_QATAR][1][19] = 32,
+ [1][1][RTW89_QATAR][0][19] = -6,
+ [1][1][RTW89_UK][1][19] = 32,
+ [1][1][RTW89_UK][0][19] = -6,
+ [1][1][RTW89_FCC][1][21] = -28,
+ [1][1][RTW89_FCC][2][21] = 44,
+ [1][1][RTW89_ETSI][1][21] = 32,
+ [1][1][RTW89_ETSI][0][21] = -6,
+ [1][1][RTW89_MKK][1][21] = 30,
+ [1][1][RTW89_MKK][0][21] = -10,
+ [1][1][RTW89_IC][1][21] = -28,
+ [1][1][RTW89_KCC][1][21] = -14,
+ [1][1][RTW89_KCC][0][21] = -14,
+ [1][1][RTW89_ACMA][1][21] = 32,
+ [1][1][RTW89_ACMA][0][21] = -6,
+ [1][1][RTW89_CHILE][1][21] = -28,
+ [1][1][RTW89_QATAR][1][21] = 32,
+ [1][1][RTW89_QATAR][0][21] = -6,
+ [1][1][RTW89_UK][1][21] = 32,
+ [1][1][RTW89_UK][0][21] = -6,
+ [1][1][RTW89_FCC][1][23] = -28,
+ [1][1][RTW89_FCC][2][23] = 44,
+ [1][1][RTW89_ETSI][1][23] = 32,
+ [1][1][RTW89_ETSI][0][23] = -6,
+ [1][1][RTW89_MKK][1][23] = 32,
+ [1][1][RTW89_MKK][0][23] = -10,
+ [1][1][RTW89_IC][1][23] = -28,
+ [1][1][RTW89_KCC][1][23] = -14,
+ [1][1][RTW89_KCC][0][23] = -14,
+ [1][1][RTW89_ACMA][1][23] = 32,
+ [1][1][RTW89_ACMA][0][23] = -6,
+ [1][1][RTW89_CHILE][1][23] = -28,
+ [1][1][RTW89_QATAR][1][23] = 32,
+ [1][1][RTW89_QATAR][0][23] = -6,
+ [1][1][RTW89_UK][1][23] = 32,
+ [1][1][RTW89_UK][0][23] = -6,
+ [1][1][RTW89_FCC][1][25] = -28,
+ [1][1][RTW89_FCC][2][25] = 44,
+ [1][1][RTW89_ETSI][1][25] = 32,
+ [1][1][RTW89_ETSI][0][25] = -6,
+ [1][1][RTW89_MKK][1][25] = 32,
+ [1][1][RTW89_MKK][0][25] = -10,
+ [1][1][RTW89_IC][1][25] = -28,
+ [1][1][RTW89_KCC][1][25] = -14,
+ [1][1][RTW89_KCC][0][25] = -14,
+ [1][1][RTW89_ACMA][1][25] = 32,
+ [1][1][RTW89_ACMA][0][25] = -6,
+ [1][1][RTW89_CHILE][1][25] = -28,
+ [1][1][RTW89_QATAR][1][25] = 32,
+ [1][1][RTW89_QATAR][0][25] = -6,
+ [1][1][RTW89_UK][1][25] = 32,
+ [1][1][RTW89_UK][0][25] = -6,
+ [1][1][RTW89_FCC][1][27] = -28,
+ [1][1][RTW89_FCC][2][27] = 44,
+ [1][1][RTW89_ETSI][1][27] = 32,
+ [1][1][RTW89_ETSI][0][27] = -6,
+ [1][1][RTW89_MKK][1][27] = 32,
+ [1][1][RTW89_MKK][0][27] = -10,
+ [1][1][RTW89_IC][1][27] = -28,
+ [1][1][RTW89_KCC][1][27] = -14,
+ [1][1][RTW89_KCC][0][27] = -14,
+ [1][1][RTW89_ACMA][1][27] = 32,
+ [1][1][RTW89_ACMA][0][27] = -6,
+ [1][1][RTW89_CHILE][1][27] = -28,
+ [1][1][RTW89_QATAR][1][27] = 32,
+ [1][1][RTW89_QATAR][0][27] = -6,
+ [1][1][RTW89_UK][1][27] = 32,
+ [1][1][RTW89_UK][0][27] = -6,
+ [1][1][RTW89_FCC][1][29] = -28,
+ [1][1][RTW89_FCC][2][29] = 44,
+ [1][1][RTW89_ETSI][1][29] = 32,
+ [1][1][RTW89_ETSI][0][29] = -6,
+ [1][1][RTW89_MKK][1][29] = 32,
+ [1][1][RTW89_MKK][0][29] = -10,
+ [1][1][RTW89_IC][1][29] = -28,
+ [1][1][RTW89_KCC][1][29] = -14,
+ [1][1][RTW89_KCC][0][29] = -14,
+ [1][1][RTW89_ACMA][1][29] = 32,
+ [1][1][RTW89_ACMA][0][29] = -6,
+ [1][1][RTW89_CHILE][1][29] = -28,
+ [1][1][RTW89_QATAR][1][29] = 32,
+ [1][1][RTW89_QATAR][0][29] = -6,
+ [1][1][RTW89_UK][1][29] = 32,
+ [1][1][RTW89_UK][0][29] = -6,
+ [1][1][RTW89_FCC][1][30] = -28,
+ [1][1][RTW89_FCC][2][30] = 44,
+ [1][1][RTW89_ETSI][1][30] = 32,
+ [1][1][RTW89_ETSI][0][30] = -6,
+ [1][1][RTW89_MKK][1][30] = 32,
+ [1][1][RTW89_MKK][0][30] = -10,
+ [1][1][RTW89_IC][1][30] = -28,
+ [1][1][RTW89_KCC][1][30] = -14,
+ [1][1][RTW89_KCC][0][30] = -14,
+ [1][1][RTW89_ACMA][1][30] = 32,
+ [1][1][RTW89_ACMA][0][30] = -6,
+ [1][1][RTW89_CHILE][1][30] = -28,
+ [1][1][RTW89_QATAR][1][30] = 32,
+ [1][1][RTW89_QATAR][0][30] = -6,
+ [1][1][RTW89_UK][1][30] = 32,
+ [1][1][RTW89_UK][0][30] = -6,
+ [1][1][RTW89_FCC][1][32] = -28,
+ [1][1][RTW89_FCC][2][32] = 44,
+ [1][1][RTW89_ETSI][1][32] = 32,
+ [1][1][RTW89_ETSI][0][32] = -6,
+ [1][1][RTW89_MKK][1][32] = 32,
+ [1][1][RTW89_MKK][0][32] = -10,
+ [1][1][RTW89_IC][1][32] = -28,
+ [1][1][RTW89_KCC][1][32] = -14,
+ [1][1][RTW89_KCC][0][32] = -14,
+ [1][1][RTW89_ACMA][1][32] = 32,
+ [1][1][RTW89_ACMA][0][32] = -6,
+ [1][1][RTW89_CHILE][1][32] = -28,
+ [1][1][RTW89_QATAR][1][32] = 32,
+ [1][1][RTW89_QATAR][0][32] = -6,
+ [1][1][RTW89_UK][1][32] = 32,
+ [1][1][RTW89_UK][0][32] = -6,
+ [1][1][RTW89_FCC][1][34] = -28,
+ [1][1][RTW89_FCC][2][34] = 44,
+ [1][1][RTW89_ETSI][1][34] = 32,
+ [1][1][RTW89_ETSI][0][34] = -6,
+ [1][1][RTW89_MKK][1][34] = 32,
+ [1][1][RTW89_MKK][0][34] = -10,
+ [1][1][RTW89_IC][1][34] = -28,
+ [1][1][RTW89_KCC][1][34] = -14,
+ [1][1][RTW89_KCC][0][34] = -14,
+ [1][1][RTW89_ACMA][1][34] = 32,
+ [1][1][RTW89_ACMA][0][34] = -6,
+ [1][1][RTW89_CHILE][1][34] = -28,
+ [1][1][RTW89_QATAR][1][34] = 32,
+ [1][1][RTW89_QATAR][0][34] = -6,
+ [1][1][RTW89_UK][1][34] = 32,
+ [1][1][RTW89_UK][0][34] = -6,
+ [1][1][RTW89_FCC][1][36] = -28,
+ [1][1][RTW89_FCC][2][36] = 44,
+ [1][1][RTW89_ETSI][1][36] = 32,
+ [1][1][RTW89_ETSI][0][36] = -6,
+ [1][1][RTW89_MKK][1][36] = 32,
+ [1][1][RTW89_MKK][0][36] = -10,
+ [1][1][RTW89_IC][1][36] = -28,
+ [1][1][RTW89_KCC][1][36] = -14,
+ [1][1][RTW89_KCC][0][36] = -14,
+ [1][1][RTW89_ACMA][1][36] = 32,
+ [1][1][RTW89_ACMA][0][36] = -6,
+ [1][1][RTW89_CHILE][1][36] = -28,
+ [1][1][RTW89_QATAR][1][36] = 32,
+ [1][1][RTW89_QATAR][0][36] = -6,
+ [1][1][RTW89_UK][1][36] = 32,
+ [1][1][RTW89_UK][0][36] = -6,
+ [1][1][RTW89_FCC][1][38] = -28,
+ [1][1][RTW89_FCC][2][38] = 44,
+ [1][1][RTW89_ETSI][1][38] = 32,
+ [1][1][RTW89_ETSI][0][38] = -6,
+ [1][1][RTW89_MKK][1][38] = 32,
+ [1][1][RTW89_MKK][0][38] = -10,
+ [1][1][RTW89_IC][1][38] = -28,
+ [1][1][RTW89_KCC][1][38] = -14,
+ [1][1][RTW89_KCC][0][38] = -14,
+ [1][1][RTW89_ACMA][1][38] = 32,
+ [1][1][RTW89_ACMA][0][38] = -6,
+ [1][1][RTW89_CHILE][1][38] = -28,
+ [1][1][RTW89_QATAR][1][38] = 32,
+ [1][1][RTW89_QATAR][0][38] = -6,
+ [1][1][RTW89_UK][1][38] = 32,
+ [1][1][RTW89_UK][0][38] = -6,
+ [1][1][RTW89_FCC][1][40] = -28,
+ [1][1][RTW89_FCC][2][40] = 44,
+ [1][1][RTW89_ETSI][1][40] = 32,
+ [1][1][RTW89_ETSI][0][40] = -6,
+ [1][1][RTW89_MKK][1][40] = 32,
+ [1][1][RTW89_MKK][0][40] = -10,
+ [1][1][RTW89_IC][1][40] = -28,
+ [1][1][RTW89_KCC][1][40] = -14,
+ [1][1][RTW89_KCC][0][40] = -14,
+ [1][1][RTW89_ACMA][1][40] = 32,
+ [1][1][RTW89_ACMA][0][40] = -6,
+ [1][1][RTW89_CHILE][1][40] = -28,
+ [1][1][RTW89_QATAR][1][40] = 32,
+ [1][1][RTW89_QATAR][0][40] = -6,
+ [1][1][RTW89_UK][1][40] = 32,
+ [1][1][RTW89_UK][0][40] = -6,
+ [1][1][RTW89_FCC][1][42] = -28,
+ [1][1][RTW89_FCC][2][42] = 44,
+ [1][1][RTW89_ETSI][1][42] = 32,
+ [1][1][RTW89_ETSI][0][42] = -6,
+ [1][1][RTW89_MKK][1][42] = 32,
+ [1][1][RTW89_MKK][0][42] = -10,
+ [1][1][RTW89_IC][1][42] = -28,
+ [1][1][RTW89_KCC][1][42] = -14,
+ [1][1][RTW89_KCC][0][42] = -14,
+ [1][1][RTW89_ACMA][1][42] = 32,
+ [1][1][RTW89_ACMA][0][42] = -6,
+ [1][1][RTW89_CHILE][1][42] = -28,
+ [1][1][RTW89_QATAR][1][42] = 32,
+ [1][1][RTW89_QATAR][0][42] = -6,
+ [1][1][RTW89_UK][1][42] = 32,
+ [1][1][RTW89_UK][0][42] = -6,
+ [1][1][RTW89_FCC][1][44] = -28,
+ [1][1][RTW89_FCC][2][44] = 44,
+ [1][1][RTW89_ETSI][1][44] = 34,
+ [1][1][RTW89_ETSI][0][44] = -4,
+ [1][1][RTW89_MKK][1][44] = 4,
+ [1][1][RTW89_MKK][0][44] = -8,
+ [1][1][RTW89_IC][1][44] = -28,
+ [1][1][RTW89_KCC][1][44] = -14,
+ [1][1][RTW89_KCC][0][44] = -14,
+ [1][1][RTW89_ACMA][1][44] = 34,
+ [1][1][RTW89_ACMA][0][44] = -4,
+ [1][1][RTW89_CHILE][1][44] = -28,
+ [1][1][RTW89_QATAR][1][44] = 34,
+ [1][1][RTW89_QATAR][0][44] = -4,
+ [1][1][RTW89_UK][1][44] = 34,
+ [1][1][RTW89_UK][0][44] = -4,
+ [1][1][RTW89_FCC][1][45] = -26,
+ [1][1][RTW89_FCC][2][45] = 127,
+ [1][1][RTW89_ETSI][1][45] = 127,
+ [1][1][RTW89_ETSI][0][45] = 127,
+ [1][1][RTW89_MKK][1][45] = 127,
+ [1][1][RTW89_MKK][0][45] = 127,
+ [1][1][RTW89_IC][1][45] = -26,
+ [1][1][RTW89_KCC][1][45] = -14,
+ [1][1][RTW89_KCC][0][45] = 127,
+ [1][1][RTW89_ACMA][1][45] = 127,
+ [1][1][RTW89_ACMA][0][45] = 127,
+ [1][1][RTW89_CHILE][1][45] = 127,
+ [1][1][RTW89_QATAR][1][45] = 127,
+ [1][1][RTW89_QATAR][0][45] = 127,
+ [1][1][RTW89_UK][1][45] = 127,
+ [1][1][RTW89_UK][0][45] = 127,
+ [1][1][RTW89_FCC][1][47] = -28,
+ [1][1][RTW89_FCC][2][47] = 127,
+ [1][1][RTW89_ETSI][1][47] = 127,
+ [1][1][RTW89_ETSI][0][47] = 127,
+ [1][1][RTW89_MKK][1][47] = 127,
+ [1][1][RTW89_MKK][0][47] = 127,
+ [1][1][RTW89_IC][1][47] = -28,
+ [1][1][RTW89_KCC][1][47] = -14,
+ [1][1][RTW89_KCC][0][47] = 127,
+ [1][1][RTW89_ACMA][1][47] = 127,
+ [1][1][RTW89_ACMA][0][47] = 127,
+ [1][1][RTW89_CHILE][1][47] = 127,
+ [1][1][RTW89_QATAR][1][47] = 127,
+ [1][1][RTW89_QATAR][0][47] = 127,
+ [1][1][RTW89_UK][1][47] = 127,
+ [1][1][RTW89_UK][0][47] = 127,
+ [1][1][RTW89_FCC][1][49] = -28,
+ [1][1][RTW89_FCC][2][49] = 127,
+ [1][1][RTW89_ETSI][1][49] = 127,
+ [1][1][RTW89_ETSI][0][49] = 127,
+ [1][1][RTW89_MKK][1][49] = 127,
+ [1][1][RTW89_MKK][0][49] = 127,
+ [1][1][RTW89_IC][1][49] = -28,
+ [1][1][RTW89_KCC][1][49] = -14,
+ [1][1][RTW89_KCC][0][49] = 127,
+ [1][1][RTW89_ACMA][1][49] = 127,
+ [1][1][RTW89_ACMA][0][49] = 127,
+ [1][1][RTW89_CHILE][1][49] = 127,
+ [1][1][RTW89_QATAR][1][49] = 127,
+ [1][1][RTW89_QATAR][0][49] = 127,
+ [1][1][RTW89_UK][1][49] = 127,
+ [1][1][RTW89_UK][0][49] = 127,
+ [1][1][RTW89_FCC][1][51] = -28,
+ [1][1][RTW89_FCC][2][51] = 127,
+ [1][1][RTW89_ETSI][1][51] = 127,
+ [1][1][RTW89_ETSI][0][51] = 127,
+ [1][1][RTW89_MKK][1][51] = 127,
+ [1][1][RTW89_MKK][0][51] = 127,
+ [1][1][RTW89_IC][1][51] = -28,
+ [1][1][RTW89_KCC][1][51] = -14,
+ [1][1][RTW89_KCC][0][51] = 127,
+ [1][1][RTW89_ACMA][1][51] = 127,
+ [1][1][RTW89_ACMA][0][51] = 127,
+ [1][1][RTW89_CHILE][1][51] = 127,
+ [1][1][RTW89_QATAR][1][51] = 127,
+ [1][1][RTW89_QATAR][0][51] = 127,
+ [1][1][RTW89_UK][1][51] = 127,
+ [1][1][RTW89_UK][0][51] = 127,
+ [1][1][RTW89_FCC][1][53] = -26,
+ [1][1][RTW89_FCC][2][53] = 127,
+ [1][1][RTW89_ETSI][1][53] = 127,
+ [1][1][RTW89_ETSI][0][53] = 127,
+ [1][1][RTW89_MKK][1][53] = 127,
+ [1][1][RTW89_MKK][0][53] = 127,
+ [1][1][RTW89_IC][1][53] = -26,
+ [1][1][RTW89_KCC][1][53] = -14,
+ [1][1][RTW89_KCC][0][53] = 127,
+ [1][1][RTW89_ACMA][1][53] = 127,
+ [1][1][RTW89_ACMA][0][53] = 127,
+ [1][1][RTW89_CHILE][1][53] = 127,
+ [1][1][RTW89_QATAR][1][53] = 127,
+ [1][1][RTW89_QATAR][0][53] = 127,
+ [1][1][RTW89_UK][1][53] = 127,
+ [1][1][RTW89_UK][0][53] = 127,
+ [1][1][RTW89_FCC][1][55] = -28,
+ [1][1][RTW89_FCC][2][55] = 44,
+ [1][1][RTW89_ETSI][1][55] = 127,
+ [1][1][RTW89_ETSI][0][55] = 127,
+ [1][1][RTW89_MKK][1][55] = 127,
+ [1][1][RTW89_MKK][0][55] = 127,
+ [1][1][RTW89_IC][1][55] = -28,
+ [1][1][RTW89_KCC][1][55] = -14,
+ [1][1][RTW89_KCC][0][55] = 127,
+ [1][1][RTW89_ACMA][1][55] = 127,
+ [1][1][RTW89_ACMA][0][55] = 127,
+ [1][1][RTW89_CHILE][1][55] = 127,
+ [1][1][RTW89_QATAR][1][55] = 127,
+ [1][1][RTW89_QATAR][0][55] = 127,
+ [1][1][RTW89_UK][1][55] = 127,
+ [1][1][RTW89_UK][0][55] = 127,
+ [1][1][RTW89_FCC][1][57] = -28,
+ [1][1][RTW89_FCC][2][57] = 44,
+ [1][1][RTW89_ETSI][1][57] = 127,
+ [1][1][RTW89_ETSI][0][57] = 127,
+ [1][1][RTW89_MKK][1][57] = 127,
+ [1][1][RTW89_MKK][0][57] = 127,
+ [1][1][RTW89_IC][1][57] = -28,
+ [1][1][RTW89_KCC][1][57] = -14,
+ [1][1][RTW89_KCC][0][57] = 127,
+ [1][1][RTW89_ACMA][1][57] = 127,
+ [1][1][RTW89_ACMA][0][57] = 127,
+ [1][1][RTW89_CHILE][1][57] = 127,
+ [1][1][RTW89_QATAR][1][57] = 127,
+ [1][1][RTW89_QATAR][0][57] = 127,
+ [1][1][RTW89_UK][1][57] = 127,
+ [1][1][RTW89_UK][0][57] = 127,
+ [1][1][RTW89_FCC][1][59] = -28,
+ [1][1][RTW89_FCC][2][59] = 44,
+ [1][1][RTW89_ETSI][1][59] = 127,
+ [1][1][RTW89_ETSI][0][59] = 127,
+ [1][1][RTW89_MKK][1][59] = 127,
+ [1][1][RTW89_MKK][0][59] = 127,
+ [1][1][RTW89_IC][1][59] = -28,
+ [1][1][RTW89_KCC][1][59] = -14,
+ [1][1][RTW89_KCC][0][59] = 127,
+ [1][1][RTW89_ACMA][1][59] = 127,
+ [1][1][RTW89_ACMA][0][59] = 127,
+ [1][1][RTW89_CHILE][1][59] = 127,
+ [1][1][RTW89_QATAR][1][59] = 127,
+ [1][1][RTW89_QATAR][0][59] = 127,
+ [1][1][RTW89_UK][1][59] = 127,
+ [1][1][RTW89_UK][0][59] = 127,
+ [1][1][RTW89_FCC][1][60] = -28,
+ [1][1][RTW89_FCC][2][60] = 44,
+ [1][1][RTW89_ETSI][1][60] = 127,
+ [1][1][RTW89_ETSI][0][60] = 127,
+ [1][1][RTW89_MKK][1][60] = 127,
+ [1][1][RTW89_MKK][0][60] = 127,
+ [1][1][RTW89_IC][1][60] = -28,
+ [1][1][RTW89_KCC][1][60] = -14,
+ [1][1][RTW89_KCC][0][60] = 127,
+ [1][1][RTW89_ACMA][1][60] = 127,
+ [1][1][RTW89_ACMA][0][60] = 127,
+ [1][1][RTW89_CHILE][1][60] = 127,
+ [1][1][RTW89_QATAR][1][60] = 127,
+ [1][1][RTW89_QATAR][0][60] = 127,
+ [1][1][RTW89_UK][1][60] = 127,
+ [1][1][RTW89_UK][0][60] = 127,
+ [1][1][RTW89_FCC][1][62] = -28,
+ [1][1][RTW89_FCC][2][62] = 44,
+ [1][1][RTW89_ETSI][1][62] = 127,
+ [1][1][RTW89_ETSI][0][62] = 127,
+ [1][1][RTW89_MKK][1][62] = 127,
+ [1][1][RTW89_MKK][0][62] = 127,
+ [1][1][RTW89_IC][1][62] = -28,
+ [1][1][RTW89_KCC][1][62] = -14,
+ [1][1][RTW89_KCC][0][62] = 127,
+ [1][1][RTW89_ACMA][1][62] = 127,
+ [1][1][RTW89_ACMA][0][62] = 127,
+ [1][1][RTW89_CHILE][1][62] = 127,
+ [1][1][RTW89_QATAR][1][62] = 127,
+ [1][1][RTW89_QATAR][0][62] = 127,
+ [1][1][RTW89_UK][1][62] = 127,
+ [1][1][RTW89_UK][0][62] = 127,
+ [1][1][RTW89_FCC][1][64] = -28,
+ [1][1][RTW89_FCC][2][64] = 44,
+ [1][1][RTW89_ETSI][1][64] = 127,
+ [1][1][RTW89_ETSI][0][64] = 127,
+ [1][1][RTW89_MKK][1][64] = 127,
+ [1][1][RTW89_MKK][0][64] = 127,
+ [1][1][RTW89_IC][1][64] = -28,
+ [1][1][RTW89_KCC][1][64] = -14,
+ [1][1][RTW89_KCC][0][64] = 127,
+ [1][1][RTW89_ACMA][1][64] = 127,
+ [1][1][RTW89_ACMA][0][64] = 127,
+ [1][1][RTW89_CHILE][1][64] = 127,
+ [1][1][RTW89_QATAR][1][64] = 127,
+ [1][1][RTW89_QATAR][0][64] = 127,
+ [1][1][RTW89_UK][1][64] = 127,
+ [1][1][RTW89_UK][0][64] = 127,
+ [1][1][RTW89_FCC][1][66] = -28,
+ [1][1][RTW89_FCC][2][66] = 44,
+ [1][1][RTW89_ETSI][1][66] = 127,
+ [1][1][RTW89_ETSI][0][66] = 127,
+ [1][1][RTW89_MKK][1][66] = 127,
+ [1][1][RTW89_MKK][0][66] = 127,
+ [1][1][RTW89_IC][1][66] = -28,
+ [1][1][RTW89_KCC][1][66] = -14,
+ [1][1][RTW89_KCC][0][66] = 127,
+ [1][1][RTW89_ACMA][1][66] = 127,
+ [1][1][RTW89_ACMA][0][66] = 127,
+ [1][1][RTW89_CHILE][1][66] = 127,
+ [1][1][RTW89_QATAR][1][66] = 127,
+ [1][1][RTW89_QATAR][0][66] = 127,
+ [1][1][RTW89_UK][1][66] = 127,
+ [1][1][RTW89_UK][0][66] = 127,
+ [1][1][RTW89_FCC][1][68] = -28,
+ [1][1][RTW89_FCC][2][68] = 44,
+ [1][1][RTW89_ETSI][1][68] = 127,
+ [1][1][RTW89_ETSI][0][68] = 127,
+ [1][1][RTW89_MKK][1][68] = 127,
+ [1][1][RTW89_MKK][0][68] = 127,
+ [1][1][RTW89_IC][1][68] = -28,
+ [1][1][RTW89_KCC][1][68] = -14,
+ [1][1][RTW89_KCC][0][68] = 127,
+ [1][1][RTW89_ACMA][1][68] = 127,
+ [1][1][RTW89_ACMA][0][68] = 127,
+ [1][1][RTW89_CHILE][1][68] = 127,
+ [1][1][RTW89_QATAR][1][68] = 127,
+ [1][1][RTW89_QATAR][0][68] = 127,
+ [1][1][RTW89_UK][1][68] = 127,
+ [1][1][RTW89_UK][0][68] = 127,
+ [1][1][RTW89_FCC][1][70] = -26,
+ [1][1][RTW89_FCC][2][70] = 44,
+ [1][1][RTW89_ETSI][1][70] = 127,
+ [1][1][RTW89_ETSI][0][70] = 127,
+ [1][1][RTW89_MKK][1][70] = 127,
+ [1][1][RTW89_MKK][0][70] = 127,
+ [1][1][RTW89_IC][1][70] = -26,
+ [1][1][RTW89_KCC][1][70] = -14,
+ [1][1][RTW89_KCC][0][70] = 127,
+ [1][1][RTW89_ACMA][1][70] = 127,
+ [1][1][RTW89_ACMA][0][70] = 127,
+ [1][1][RTW89_CHILE][1][70] = 127,
+ [1][1][RTW89_QATAR][1][70] = 127,
+ [1][1][RTW89_QATAR][0][70] = 127,
+ [1][1][RTW89_UK][1][70] = 127,
+ [1][1][RTW89_UK][0][70] = 127,
+ [1][1][RTW89_FCC][1][72] = -28,
+ [1][1][RTW89_FCC][2][72] = 44,
+ [1][1][RTW89_ETSI][1][72] = 127,
+ [1][1][RTW89_ETSI][0][72] = 127,
+ [1][1][RTW89_MKK][1][72] = 127,
+ [1][1][RTW89_MKK][0][72] = 127,
+ [1][1][RTW89_IC][1][72] = -28,
+ [1][1][RTW89_KCC][1][72] = -14,
+ [1][1][RTW89_KCC][0][72] = 127,
+ [1][1][RTW89_ACMA][1][72] = 127,
+ [1][1][RTW89_ACMA][0][72] = 127,
+ [1][1][RTW89_CHILE][1][72] = 127,
+ [1][1][RTW89_QATAR][1][72] = 127,
+ [1][1][RTW89_QATAR][0][72] = 127,
+ [1][1][RTW89_UK][1][72] = 127,
+ [1][1][RTW89_UK][0][72] = 127,
+ [1][1][RTW89_FCC][1][74] = -28,
+ [1][1][RTW89_FCC][2][74] = 44,
+ [1][1][RTW89_ETSI][1][74] = 127,
+ [1][1][RTW89_ETSI][0][74] = 127,
+ [1][1][RTW89_MKK][1][74] = 127,
+ [1][1][RTW89_MKK][0][74] = 127,
+ [1][1][RTW89_IC][1][74] = -28,
+ [1][1][RTW89_KCC][1][74] = -14,
+ [1][1][RTW89_KCC][0][74] = 127,
+ [1][1][RTW89_ACMA][1][74] = 127,
+ [1][1][RTW89_ACMA][0][74] = 127,
+ [1][1][RTW89_CHILE][1][74] = 127,
+ [1][1][RTW89_QATAR][1][74] = 127,
+ [1][1][RTW89_QATAR][0][74] = 127,
+ [1][1][RTW89_UK][1][74] = 127,
+ [1][1][RTW89_UK][0][74] = 127,
+ [1][1][RTW89_FCC][1][75] = -28,
+ [1][1][RTW89_FCC][2][75] = 44,
+ [1][1][RTW89_ETSI][1][75] = 127,
+ [1][1][RTW89_ETSI][0][75] = 127,
+ [1][1][RTW89_MKK][1][75] = 127,
+ [1][1][RTW89_MKK][0][75] = 127,
+ [1][1][RTW89_IC][1][75] = -28,
+ [1][1][RTW89_KCC][1][75] = -14,
+ [1][1][RTW89_KCC][0][75] = 127,
+ [1][1][RTW89_ACMA][1][75] = 127,
+ [1][1][RTW89_ACMA][0][75] = 127,
+ [1][1][RTW89_CHILE][1][75] = 127,
+ [1][1][RTW89_QATAR][1][75] = 127,
+ [1][1][RTW89_QATAR][0][75] = 127,
+ [1][1][RTW89_UK][1][75] = 127,
+ [1][1][RTW89_UK][0][75] = 127,
+ [1][1][RTW89_FCC][1][77] = -28,
+ [1][1][RTW89_FCC][2][77] = 44,
+ [1][1][RTW89_ETSI][1][77] = 127,
+ [1][1][RTW89_ETSI][0][77] = 127,
+ [1][1][RTW89_MKK][1][77] = 127,
+ [1][1][RTW89_MKK][0][77] = 127,
+ [1][1][RTW89_IC][1][77] = -28,
+ [1][1][RTW89_KCC][1][77] = -14,
+ [1][1][RTW89_KCC][0][77] = 127,
+ [1][1][RTW89_ACMA][1][77] = 127,
+ [1][1][RTW89_ACMA][0][77] = 127,
+ [1][1][RTW89_CHILE][1][77] = 127,
+ [1][1][RTW89_QATAR][1][77] = 127,
+ [1][1][RTW89_QATAR][0][77] = 127,
+ [1][1][RTW89_UK][1][77] = 127,
+ [1][1][RTW89_UK][0][77] = 127,
+ [1][1][RTW89_FCC][1][79] = -28,
+ [1][1][RTW89_FCC][2][79] = 44,
+ [1][1][RTW89_ETSI][1][79] = 127,
+ [1][1][RTW89_ETSI][0][79] = 127,
+ [1][1][RTW89_MKK][1][79] = 127,
+ [1][1][RTW89_MKK][0][79] = 127,
+ [1][1][RTW89_IC][1][79] = -28,
+ [1][1][RTW89_KCC][1][79] = -14,
+ [1][1][RTW89_KCC][0][79] = 127,
+ [1][1][RTW89_ACMA][1][79] = 127,
+ [1][1][RTW89_ACMA][0][79] = 127,
+ [1][1][RTW89_CHILE][1][79] = 127,
+ [1][1][RTW89_QATAR][1][79] = 127,
+ [1][1][RTW89_QATAR][0][79] = 127,
+ [1][1][RTW89_UK][1][79] = 127,
+ [1][1][RTW89_UK][0][79] = 127,
+ [1][1][RTW89_FCC][1][81] = -28,
+ [1][1][RTW89_FCC][2][81] = 44,
+ [1][1][RTW89_ETSI][1][81] = 127,
+ [1][1][RTW89_ETSI][0][81] = 127,
+ [1][1][RTW89_MKK][1][81] = 127,
+ [1][1][RTW89_MKK][0][81] = 127,
+ [1][1][RTW89_IC][1][81] = -28,
+ [1][1][RTW89_KCC][1][81] = -14,
+ [1][1][RTW89_KCC][0][81] = 127,
+ [1][1][RTW89_ACMA][1][81] = 127,
+ [1][1][RTW89_ACMA][0][81] = 127,
+ [1][1][RTW89_CHILE][1][81] = 127,
+ [1][1][RTW89_QATAR][1][81] = 127,
+ [1][1][RTW89_QATAR][0][81] = 127,
+ [1][1][RTW89_UK][1][81] = 127,
+ [1][1][RTW89_UK][0][81] = 127,
+ [1][1][RTW89_FCC][1][83] = -28,
+ [1][1][RTW89_FCC][2][83] = 44,
+ [1][1][RTW89_ETSI][1][83] = 127,
+ [1][1][RTW89_ETSI][0][83] = 127,
+ [1][1][RTW89_MKK][1][83] = 127,
+ [1][1][RTW89_MKK][0][83] = 127,
+ [1][1][RTW89_IC][1][83] = -28,
+ [1][1][RTW89_KCC][1][83] = -14,
+ [1][1][RTW89_KCC][0][83] = 127,
+ [1][1][RTW89_ACMA][1][83] = 127,
+ [1][1][RTW89_ACMA][0][83] = 127,
+ [1][1][RTW89_CHILE][1][83] = 127,
+ [1][1][RTW89_QATAR][1][83] = 127,
+ [1][1][RTW89_QATAR][0][83] = 127,
+ [1][1][RTW89_UK][1][83] = 127,
+ [1][1][RTW89_UK][0][83] = 127,
+ [1][1][RTW89_FCC][1][85] = -28,
+ [1][1][RTW89_FCC][2][85] = 44,
+ [1][1][RTW89_ETSI][1][85] = 127,
+ [1][1][RTW89_ETSI][0][85] = 127,
+ [1][1][RTW89_MKK][1][85] = 127,
+ [1][1][RTW89_MKK][0][85] = 127,
+ [1][1][RTW89_IC][1][85] = -28,
+ [1][1][RTW89_KCC][1][85] = -14,
+ [1][1][RTW89_KCC][0][85] = 127,
+ [1][1][RTW89_ACMA][1][85] = 127,
+ [1][1][RTW89_ACMA][0][85] = 127,
+ [1][1][RTW89_CHILE][1][85] = 127,
+ [1][1][RTW89_QATAR][1][85] = 127,
+ [1][1][RTW89_QATAR][0][85] = 127,
+ [1][1][RTW89_UK][1][85] = 127,
+ [1][1][RTW89_UK][0][85] = 127,
+ [1][1][RTW89_FCC][1][87] = -28,
+ [1][1][RTW89_FCC][2][87] = 127,
+ [1][1][RTW89_ETSI][1][87] = 127,
+ [1][1][RTW89_ETSI][0][87] = 127,
+ [1][1][RTW89_MKK][1][87] = 127,
+ [1][1][RTW89_MKK][0][87] = 127,
+ [1][1][RTW89_IC][1][87] = -28,
+ [1][1][RTW89_KCC][1][87] = -14,
+ [1][1][RTW89_KCC][0][87] = 127,
+ [1][1][RTW89_ACMA][1][87] = 127,
+ [1][1][RTW89_ACMA][0][87] = 127,
+ [1][1][RTW89_CHILE][1][87] = 127,
+ [1][1][RTW89_QATAR][1][87] = 127,
+ [1][1][RTW89_QATAR][0][87] = 127,
+ [1][1][RTW89_UK][1][87] = 127,
+ [1][1][RTW89_UK][0][87] = 127,
+ [1][1][RTW89_FCC][1][89] = -26,
+ [1][1][RTW89_FCC][2][89] = 127,
+ [1][1][RTW89_ETSI][1][89] = 127,
+ [1][1][RTW89_ETSI][0][89] = 127,
+ [1][1][RTW89_MKK][1][89] = 127,
+ [1][1][RTW89_MKK][0][89] = 127,
+ [1][1][RTW89_IC][1][89] = -26,
+ [1][1][RTW89_KCC][1][89] = -14,
+ [1][1][RTW89_KCC][0][89] = 127,
+ [1][1][RTW89_ACMA][1][89] = 127,
+ [1][1][RTW89_ACMA][0][89] = 127,
+ [1][1][RTW89_CHILE][1][89] = 127,
+ [1][1][RTW89_QATAR][1][89] = 127,
+ [1][1][RTW89_QATAR][0][89] = 127,
+ [1][1][RTW89_UK][1][89] = 127,
+ [1][1][RTW89_UK][0][89] = 127,
+ [1][1][RTW89_FCC][1][90] = -26,
+ [1][1][RTW89_FCC][2][90] = 127,
+ [1][1][RTW89_ETSI][1][90] = 127,
+ [1][1][RTW89_ETSI][0][90] = 127,
+ [1][1][RTW89_MKK][1][90] = 127,
+ [1][1][RTW89_MKK][0][90] = 127,
+ [1][1][RTW89_IC][1][90] = -26,
+ [1][1][RTW89_KCC][1][90] = -14,
+ [1][1][RTW89_KCC][0][90] = 127,
+ [1][1][RTW89_ACMA][1][90] = 127,
+ [1][1][RTW89_ACMA][0][90] = 127,
+ [1][1][RTW89_CHILE][1][90] = 127,
+ [1][1][RTW89_QATAR][1][90] = 127,
+ [1][1][RTW89_QATAR][0][90] = 127,
+ [1][1][RTW89_UK][1][90] = 127,
+ [1][1][RTW89_UK][0][90] = 127,
+ [1][1][RTW89_FCC][1][92] = -26,
+ [1][1][RTW89_FCC][2][92] = 127,
+ [1][1][RTW89_ETSI][1][92] = 127,
+ [1][1][RTW89_ETSI][0][92] = 127,
+ [1][1][RTW89_MKK][1][92] = 127,
+ [1][1][RTW89_MKK][0][92] = 127,
+ [1][1][RTW89_IC][1][92] = -26,
+ [1][1][RTW89_KCC][1][92] = -14,
+ [1][1][RTW89_KCC][0][92] = 127,
+ [1][1][RTW89_ACMA][1][92] = 127,
+ [1][1][RTW89_ACMA][0][92] = 127,
+ [1][1][RTW89_CHILE][1][92] = 127,
+ [1][1][RTW89_QATAR][1][92] = 127,
+ [1][1][RTW89_QATAR][0][92] = 127,
+ [1][1][RTW89_UK][1][92] = 127,
+ [1][1][RTW89_UK][0][92] = 127,
+ [1][1][RTW89_FCC][1][94] = -26,
+ [1][1][RTW89_FCC][2][94] = 127,
+ [1][1][RTW89_ETSI][1][94] = 127,
+ [1][1][RTW89_ETSI][0][94] = 127,
+ [1][1][RTW89_MKK][1][94] = 127,
+ [1][1][RTW89_MKK][0][94] = 127,
+ [1][1][RTW89_IC][1][94] = -26,
+ [1][1][RTW89_KCC][1][94] = -14,
+ [1][1][RTW89_KCC][0][94] = 127,
+ [1][1][RTW89_ACMA][1][94] = 127,
+ [1][1][RTW89_ACMA][0][94] = 127,
+ [1][1][RTW89_CHILE][1][94] = 127,
+ [1][1][RTW89_QATAR][1][94] = 127,
+ [1][1][RTW89_QATAR][0][94] = 127,
+ [1][1][RTW89_UK][1][94] = 127,
+ [1][1][RTW89_UK][0][94] = 127,
+ [1][1][RTW89_FCC][1][96] = -26,
+ [1][1][RTW89_FCC][2][96] = 127,
+ [1][1][RTW89_ETSI][1][96] = 127,
+ [1][1][RTW89_ETSI][0][96] = 127,
+ [1][1][RTW89_MKK][1][96] = 127,
+ [1][1][RTW89_MKK][0][96] = 127,
+ [1][1][RTW89_IC][1][96] = -26,
+ [1][1][RTW89_KCC][1][96] = -14,
+ [1][1][RTW89_KCC][0][96] = 127,
+ [1][1][RTW89_ACMA][1][96] = 127,
+ [1][1][RTW89_ACMA][0][96] = 127,
+ [1][1][RTW89_CHILE][1][96] = 127,
+ [1][1][RTW89_QATAR][1][96] = 127,
+ [1][1][RTW89_QATAR][0][96] = 127,
+ [1][1][RTW89_UK][1][96] = 127,
+ [1][1][RTW89_UK][0][96] = 127,
+ [1][1][RTW89_FCC][1][98] = -26,
+ [1][1][RTW89_FCC][2][98] = 127,
+ [1][1][RTW89_ETSI][1][98] = 127,
+ [1][1][RTW89_ETSI][0][98] = 127,
+ [1][1][RTW89_MKK][1][98] = 127,
+ [1][1][RTW89_MKK][0][98] = 127,
+ [1][1][RTW89_IC][1][98] = -26,
+ [1][1][RTW89_KCC][1][98] = -14,
+ [1][1][RTW89_KCC][0][98] = 127,
+ [1][1][RTW89_ACMA][1][98] = 127,
+ [1][1][RTW89_ACMA][0][98] = 127,
+ [1][1][RTW89_CHILE][1][98] = 127,
+ [1][1][RTW89_QATAR][1][98] = 127,
+ [1][1][RTW89_QATAR][0][98] = 127,
+ [1][1][RTW89_UK][1][98] = 127,
+ [1][1][RTW89_UK][0][98] = 127,
+ [1][1][RTW89_FCC][1][100] = -26,
+ [1][1][RTW89_FCC][2][100] = 127,
+ [1][1][RTW89_ETSI][1][100] = 127,
+ [1][1][RTW89_ETSI][0][100] = 127,
+ [1][1][RTW89_MKK][1][100] = 127,
+ [1][1][RTW89_MKK][0][100] = 127,
+ [1][1][RTW89_IC][1][100] = -26,
+ [1][1][RTW89_KCC][1][100] = -14,
+ [1][1][RTW89_KCC][0][100] = 127,
+ [1][1][RTW89_ACMA][1][100] = 127,
+ [1][1][RTW89_ACMA][0][100] = 127,
+ [1][1][RTW89_CHILE][1][100] = 127,
+ [1][1][RTW89_QATAR][1][100] = 127,
+ [1][1][RTW89_QATAR][0][100] = 127,
+ [1][1][RTW89_UK][1][100] = 127,
+ [1][1][RTW89_UK][0][100] = 127,
+ [1][1][RTW89_FCC][1][102] = -26,
+ [1][1][RTW89_FCC][2][102] = 127,
+ [1][1][RTW89_ETSI][1][102] = 127,
+ [1][1][RTW89_ETSI][0][102] = 127,
+ [1][1][RTW89_MKK][1][102] = 127,
+ [1][1][RTW89_MKK][0][102] = 127,
+ [1][1][RTW89_IC][1][102] = -26,
+ [1][1][RTW89_KCC][1][102] = -14,
+ [1][1][RTW89_KCC][0][102] = 127,
+ [1][1][RTW89_ACMA][1][102] = 127,
+ [1][1][RTW89_ACMA][0][102] = 127,
+ [1][1][RTW89_CHILE][1][102] = 127,
+ [1][1][RTW89_QATAR][1][102] = 127,
+ [1][1][RTW89_QATAR][0][102] = 127,
+ [1][1][RTW89_UK][1][102] = 127,
+ [1][1][RTW89_UK][0][102] = 127,
+ [1][1][RTW89_FCC][1][104] = -26,
+ [1][1][RTW89_FCC][2][104] = 127,
+ [1][1][RTW89_ETSI][1][104] = 127,
+ [1][1][RTW89_ETSI][0][104] = 127,
+ [1][1][RTW89_MKK][1][104] = 127,
+ [1][1][RTW89_MKK][0][104] = 127,
+ [1][1][RTW89_IC][1][104] = -26,
+ [1][1][RTW89_KCC][1][104] = -14,
+ [1][1][RTW89_KCC][0][104] = 127,
+ [1][1][RTW89_ACMA][1][104] = 127,
+ [1][1][RTW89_ACMA][0][104] = 127,
+ [1][1][RTW89_CHILE][1][104] = 127,
+ [1][1][RTW89_QATAR][1][104] = 127,
+ [1][1][RTW89_QATAR][0][104] = 127,
+ [1][1][RTW89_UK][1][104] = 127,
+ [1][1][RTW89_UK][0][104] = 127,
+ [1][1][RTW89_FCC][1][105] = -26,
+ [1][1][RTW89_FCC][2][105] = 127,
+ [1][1][RTW89_ETSI][1][105] = 127,
+ [1][1][RTW89_ETSI][0][105] = 127,
+ [1][1][RTW89_MKK][1][105] = 127,
+ [1][1][RTW89_MKK][0][105] = 127,
+ [1][1][RTW89_IC][1][105] = -26,
+ [1][1][RTW89_KCC][1][105] = -14,
+ [1][1][RTW89_KCC][0][105] = 127,
+ [1][1][RTW89_ACMA][1][105] = 127,
+ [1][1][RTW89_ACMA][0][105] = 127,
+ [1][1][RTW89_CHILE][1][105] = 127,
+ [1][1][RTW89_QATAR][1][105] = 127,
+ [1][1][RTW89_QATAR][0][105] = 127,
+ [1][1][RTW89_UK][1][105] = 127,
+ [1][1][RTW89_UK][0][105] = 127,
+ [1][1][RTW89_FCC][1][107] = -22,
+ [1][1][RTW89_FCC][2][107] = 127,
+ [1][1][RTW89_ETSI][1][107] = 127,
+ [1][1][RTW89_ETSI][0][107] = 127,
+ [1][1][RTW89_MKK][1][107] = 127,
+ [1][1][RTW89_MKK][0][107] = 127,
+ [1][1][RTW89_IC][1][107] = -22,
+ [1][1][RTW89_KCC][1][107] = -14,
+ [1][1][RTW89_KCC][0][107] = 127,
+ [1][1][RTW89_ACMA][1][107] = 127,
+ [1][1][RTW89_ACMA][0][107] = 127,
+ [1][1][RTW89_CHILE][1][107] = 127,
+ [1][1][RTW89_QATAR][1][107] = 127,
+ [1][1][RTW89_QATAR][0][107] = 127,
+ [1][1][RTW89_UK][1][107] = 127,
+ [1][1][RTW89_UK][0][107] = 127,
+ [1][1][RTW89_FCC][1][109] = -22,
+ [1][1][RTW89_FCC][2][109] = 127,
+ [1][1][RTW89_ETSI][1][109] = 127,
+ [1][1][RTW89_ETSI][0][109] = 127,
+ [1][1][RTW89_MKK][1][109] = 127,
+ [1][1][RTW89_MKK][0][109] = 127,
+ [1][1][RTW89_IC][1][109] = -22,
+ [1][1][RTW89_KCC][1][109] = 127,
+ [1][1][RTW89_KCC][0][109] = 127,
+ [1][1][RTW89_ACMA][1][109] = 127,
+ [1][1][RTW89_ACMA][0][109] = 127,
+ [1][1][RTW89_CHILE][1][109] = 127,
+ [1][1][RTW89_QATAR][1][109] = 127,
+ [1][1][RTW89_QATAR][0][109] = 127,
+ [1][1][RTW89_UK][1][109] = 127,
+ [1][1][RTW89_UK][0][109] = 127,
+ [1][1][RTW89_FCC][1][111] = 127,
+ [1][1][RTW89_FCC][2][111] = 127,
+ [1][1][RTW89_ETSI][1][111] = 127,
+ [1][1][RTW89_ETSI][0][111] = 127,
+ [1][1][RTW89_MKK][1][111] = 127,
+ [1][1][RTW89_MKK][0][111] = 127,
+ [1][1][RTW89_IC][1][111] = 127,
+ [1][1][RTW89_KCC][1][111] = 127,
+ [1][1][RTW89_KCC][0][111] = 127,
+ [1][1][RTW89_ACMA][1][111] = 127,
+ [1][1][RTW89_ACMA][0][111] = 127,
+ [1][1][RTW89_CHILE][1][111] = 127,
+ [1][1][RTW89_QATAR][1][111] = 127,
+ [1][1][RTW89_QATAR][0][111] = 127,
+ [1][1][RTW89_UK][1][111] = 127,
+ [1][1][RTW89_UK][0][111] = 127,
+ [1][1][RTW89_FCC][1][113] = 127,
+ [1][1][RTW89_FCC][2][113] = 127,
+ [1][1][RTW89_ETSI][1][113] = 127,
+ [1][1][RTW89_ETSI][0][113] = 127,
+ [1][1][RTW89_MKK][1][113] = 127,
+ [1][1][RTW89_MKK][0][113] = 127,
+ [1][1][RTW89_IC][1][113] = 127,
+ [1][1][RTW89_KCC][1][113] = 127,
+ [1][1][RTW89_KCC][0][113] = 127,
+ [1][1][RTW89_ACMA][1][113] = 127,
+ [1][1][RTW89_ACMA][0][113] = 127,
+ [1][1][RTW89_CHILE][1][113] = 127,
+ [1][1][RTW89_QATAR][1][113] = 127,
+ [1][1][RTW89_QATAR][0][113] = 127,
+ [1][1][RTW89_UK][1][113] = 127,
+ [1][1][RTW89_UK][0][113] = 127,
+ [1][1][RTW89_FCC][1][115] = 127,
+ [1][1][RTW89_FCC][2][115] = 127,
+ [1][1][RTW89_ETSI][1][115] = 127,
+ [1][1][RTW89_ETSI][0][115] = 127,
+ [1][1][RTW89_MKK][1][115] = 127,
+ [1][1][RTW89_MKK][0][115] = 127,
+ [1][1][RTW89_IC][1][115] = 127,
+ [1][1][RTW89_KCC][1][115] = 127,
+ [1][1][RTW89_KCC][0][115] = 127,
+ [1][1][RTW89_ACMA][1][115] = 127,
+ [1][1][RTW89_ACMA][0][115] = 127,
+ [1][1][RTW89_CHILE][1][115] = 127,
+ [1][1][RTW89_QATAR][1][115] = 127,
+ [1][1][RTW89_QATAR][0][115] = 127,
+ [1][1][RTW89_UK][1][115] = 127,
+ [1][1][RTW89_UK][0][115] = 127,
+ [1][1][RTW89_FCC][1][117] = 127,
+ [1][1][RTW89_FCC][2][117] = 127,
+ [1][1][RTW89_ETSI][1][117] = 127,
+ [1][1][RTW89_ETSI][0][117] = 127,
+ [1][1][RTW89_MKK][1][117] = 127,
+ [1][1][RTW89_MKK][0][117] = 127,
+ [1][1][RTW89_IC][1][117] = 127,
+ [1][1][RTW89_KCC][1][117] = 127,
+ [1][1][RTW89_KCC][0][117] = 127,
+ [1][1][RTW89_ACMA][1][117] = 127,
+ [1][1][RTW89_ACMA][0][117] = 127,
+ [1][1][RTW89_CHILE][1][117] = 127,
+ [1][1][RTW89_QATAR][1][117] = 127,
+ [1][1][RTW89_QATAR][0][117] = 127,
+ [1][1][RTW89_UK][1][117] = 127,
+ [1][1][RTW89_UK][0][117] = 127,
+ [1][1][RTW89_FCC][1][119] = 127,
+ [1][1][RTW89_FCC][2][119] = 127,
+ [1][1][RTW89_ETSI][1][119] = 127,
+ [1][1][RTW89_ETSI][0][119] = 127,
+ [1][1][RTW89_MKK][1][119] = 127,
+ [1][1][RTW89_MKK][0][119] = 127,
+ [1][1][RTW89_IC][1][119] = 127,
+ [1][1][RTW89_KCC][1][119] = 127,
+ [1][1][RTW89_KCC][0][119] = 127,
+ [1][1][RTW89_ACMA][1][119] = 127,
+ [1][1][RTW89_ACMA][0][119] = 127,
+ [1][1][RTW89_CHILE][1][119] = 127,
+ [1][1][RTW89_QATAR][1][119] = 127,
+ [1][1][RTW89_QATAR][0][119] = 127,
+ [1][1][RTW89_UK][1][119] = 127,
+ [1][1][RTW89_UK][0][119] = 127,
+ [2][0][RTW89_FCC][1][0] = 8,
+ [2][0][RTW89_FCC][2][0] = 60,
+ [2][0][RTW89_ETSI][1][0] = 56,
+ [2][0][RTW89_ETSI][0][0] = 18,
+ [2][0][RTW89_MKK][1][0] = 54,
+ [2][0][RTW89_MKK][0][0] = 14,
+ [2][0][RTW89_IC][1][0] = 8,
+ [2][0][RTW89_KCC][1][0] = -2,
+ [2][0][RTW89_KCC][0][0] = -2,
+ [2][0][RTW89_ACMA][1][0] = 56,
+ [2][0][RTW89_ACMA][0][0] = 18,
+ [2][0][RTW89_CHILE][1][0] = 8,
+ [2][0][RTW89_QATAR][1][0] = 56,
+ [2][0][RTW89_QATAR][0][0] = 18,
+ [2][0][RTW89_UK][1][0] = 56,
+ [2][0][RTW89_UK][0][0] = 18,
+ [2][0][RTW89_FCC][1][2] = 8,
+ [2][0][RTW89_FCC][2][2] = 60,
+ [2][0][RTW89_ETSI][1][2] = 56,
+ [2][0][RTW89_ETSI][0][2] = 18,
+ [2][0][RTW89_MKK][1][2] = 54,
+ [2][0][RTW89_MKK][0][2] = 14,
+ [2][0][RTW89_IC][1][2] = 8,
+ [2][0][RTW89_KCC][1][2] = -2,
+ [2][0][RTW89_KCC][0][2] = -2,
+ [2][0][RTW89_ACMA][1][2] = 56,
+ [2][0][RTW89_ACMA][0][2] = 18,
+ [2][0][RTW89_CHILE][1][2] = 8,
+ [2][0][RTW89_QATAR][1][2] = 56,
+ [2][0][RTW89_QATAR][0][2] = 18,
+ [2][0][RTW89_UK][1][2] = 56,
+ [2][0][RTW89_UK][0][2] = 18,
+ [2][0][RTW89_FCC][1][4] = 8,
+ [2][0][RTW89_FCC][2][4] = 60,
+ [2][0][RTW89_ETSI][1][4] = 56,
+ [2][0][RTW89_ETSI][0][4] = 18,
+ [2][0][RTW89_MKK][1][4] = 54,
+ [2][0][RTW89_MKK][0][4] = 14,
+ [2][0][RTW89_IC][1][4] = 8,
+ [2][0][RTW89_KCC][1][4] = -2,
+ [2][0][RTW89_KCC][0][4] = -2,
+ [2][0][RTW89_ACMA][1][4] = 56,
+ [2][0][RTW89_ACMA][0][4] = 18,
+ [2][0][RTW89_CHILE][1][4] = 8,
+ [2][0][RTW89_QATAR][1][4] = 56,
+ [2][0][RTW89_QATAR][0][4] = 18,
+ [2][0][RTW89_UK][1][4] = 56,
+ [2][0][RTW89_UK][0][4] = 18,
+ [2][0][RTW89_FCC][1][6] = 8,
+ [2][0][RTW89_FCC][2][6] = 60,
+ [2][0][RTW89_ETSI][1][6] = 56,
+ [2][0][RTW89_ETSI][0][6] = 18,
+ [2][0][RTW89_MKK][1][6] = 54,
+ [2][0][RTW89_MKK][0][6] = 14,
+ [2][0][RTW89_IC][1][6] = 8,
+ [2][0][RTW89_KCC][1][6] = -2,
+ [2][0][RTW89_KCC][0][6] = -2,
+ [2][0][RTW89_ACMA][1][6] = 56,
+ [2][0][RTW89_ACMA][0][6] = 18,
+ [2][0][RTW89_CHILE][1][6] = 8,
+ [2][0][RTW89_QATAR][1][6] = 56,
+ [2][0][RTW89_QATAR][0][6] = 18,
+ [2][0][RTW89_UK][1][6] = 56,
+ [2][0][RTW89_UK][0][6] = 18,
+ [2][0][RTW89_FCC][1][8] = 8,
+ [2][0][RTW89_FCC][2][8] = 60,
+ [2][0][RTW89_ETSI][1][8] = 56,
+ [2][0][RTW89_ETSI][0][8] = 18,
+ [2][0][RTW89_MKK][1][8] = 54,
+ [2][0][RTW89_MKK][0][8] = 14,
+ [2][0][RTW89_IC][1][8] = 8,
+ [2][0][RTW89_KCC][1][8] = -2,
+ [2][0][RTW89_KCC][0][8] = -2,
+ [2][0][RTW89_ACMA][1][8] = 56,
+ [2][0][RTW89_ACMA][0][8] = 18,
+ [2][0][RTW89_CHILE][1][8] = 8,
+ [2][0][RTW89_QATAR][1][8] = 56,
+ [2][0][RTW89_QATAR][0][8] = 18,
+ [2][0][RTW89_UK][1][8] = 56,
+ [2][0][RTW89_UK][0][8] = 18,
+ [2][0][RTW89_FCC][1][10] = 8,
+ [2][0][RTW89_FCC][2][10] = 60,
+ [2][0][RTW89_ETSI][1][10] = 56,
+ [2][0][RTW89_ETSI][0][10] = 18,
+ [2][0][RTW89_MKK][1][10] = 54,
+ [2][0][RTW89_MKK][0][10] = 14,
+ [2][0][RTW89_IC][1][10] = 8,
+ [2][0][RTW89_KCC][1][10] = -2,
+ [2][0][RTW89_KCC][0][10] = -2,
+ [2][0][RTW89_ACMA][1][10] = 56,
+ [2][0][RTW89_ACMA][0][10] = 18,
+ [2][0][RTW89_CHILE][1][10] = 8,
+ [2][0][RTW89_QATAR][1][10] = 56,
+ [2][0][RTW89_QATAR][0][10] = 18,
+ [2][0][RTW89_UK][1][10] = 56,
+ [2][0][RTW89_UK][0][10] = 18,
+ [2][0][RTW89_FCC][1][12] = 8,
+ [2][0][RTW89_FCC][2][12] = 60,
+ [2][0][RTW89_ETSI][1][12] = 56,
+ [2][0][RTW89_ETSI][0][12] = 18,
+ [2][0][RTW89_MKK][1][12] = 54,
+ [2][0][RTW89_MKK][0][12] = 14,
+ [2][0][RTW89_IC][1][12] = 8,
+ [2][0][RTW89_KCC][1][12] = -2,
+ [2][0][RTW89_KCC][0][12] = -2,
+ [2][0][RTW89_ACMA][1][12] = 56,
+ [2][0][RTW89_ACMA][0][12] = 18,
+ [2][0][RTW89_CHILE][1][12] = 8,
+ [2][0][RTW89_QATAR][1][12] = 56,
+ [2][0][RTW89_QATAR][0][12] = 18,
+ [2][0][RTW89_UK][1][12] = 56,
+ [2][0][RTW89_UK][0][12] = 18,
+ [2][0][RTW89_FCC][1][14] = 8,
+ [2][0][RTW89_FCC][2][14] = 60,
+ [2][0][RTW89_ETSI][1][14] = 56,
+ [2][0][RTW89_ETSI][0][14] = 18,
+ [2][0][RTW89_MKK][1][14] = 54,
+ [2][0][RTW89_MKK][0][14] = 14,
+ [2][0][RTW89_IC][1][14] = 8,
+ [2][0][RTW89_KCC][1][14] = -2,
+ [2][0][RTW89_KCC][0][14] = -2,
+ [2][0][RTW89_ACMA][1][14] = 56,
+ [2][0][RTW89_ACMA][0][14] = 18,
+ [2][0][RTW89_CHILE][1][14] = 8,
+ [2][0][RTW89_QATAR][1][14] = 56,
+ [2][0][RTW89_QATAR][0][14] = 18,
+ [2][0][RTW89_UK][1][14] = 56,
+ [2][0][RTW89_UK][0][14] = 18,
+ [2][0][RTW89_FCC][1][15] = 8,
+ [2][0][RTW89_FCC][2][15] = 60,
+ [2][0][RTW89_ETSI][1][15] = 56,
+ [2][0][RTW89_ETSI][0][15] = 18,
+ [2][0][RTW89_MKK][1][15] = 54,
+ [2][0][RTW89_MKK][0][15] = 14,
+ [2][0][RTW89_IC][1][15] = 8,
+ [2][0][RTW89_KCC][1][15] = -2,
+ [2][0][RTW89_KCC][0][15] = -2,
+ [2][0][RTW89_ACMA][1][15] = 56,
+ [2][0][RTW89_ACMA][0][15] = 18,
+ [2][0][RTW89_CHILE][1][15] = 8,
+ [2][0][RTW89_QATAR][1][15] = 56,
+ [2][0][RTW89_QATAR][0][15] = 18,
+ [2][0][RTW89_UK][1][15] = 56,
+ [2][0][RTW89_UK][0][15] = 18,
+ [2][0][RTW89_FCC][1][17] = 8,
+ [2][0][RTW89_FCC][2][17] = 60,
+ [2][0][RTW89_ETSI][1][17] = 56,
+ [2][0][RTW89_ETSI][0][17] = 18,
+ [2][0][RTW89_MKK][1][17] = 54,
+ [2][0][RTW89_MKK][0][17] = 14,
+ [2][0][RTW89_IC][1][17] = 8,
+ [2][0][RTW89_KCC][1][17] = -2,
+ [2][0][RTW89_KCC][0][17] = -2,
+ [2][0][RTW89_ACMA][1][17] = 56,
+ [2][0][RTW89_ACMA][0][17] = 18,
+ [2][0][RTW89_CHILE][1][17] = 8,
+ [2][0][RTW89_QATAR][1][17] = 56,
+ [2][0][RTW89_QATAR][0][17] = 18,
+ [2][0][RTW89_UK][1][17] = 56,
+ [2][0][RTW89_UK][0][17] = 18,
+ [2][0][RTW89_FCC][1][19] = 8,
+ [2][0][RTW89_FCC][2][19] = 60,
+ [2][0][RTW89_ETSI][1][19] = 56,
+ [2][0][RTW89_ETSI][0][19] = 18,
+ [2][0][RTW89_MKK][1][19] = 54,
+ [2][0][RTW89_MKK][0][19] = 14,
+ [2][0][RTW89_IC][1][19] = 8,
+ [2][0][RTW89_KCC][1][19] = -2,
+ [2][0][RTW89_KCC][0][19] = -2,
+ [2][0][RTW89_ACMA][1][19] = 56,
+ [2][0][RTW89_ACMA][0][19] = 18,
+ [2][0][RTW89_CHILE][1][19] = 8,
+ [2][0][RTW89_QATAR][1][19] = 56,
+ [2][0][RTW89_QATAR][0][19] = 18,
+ [2][0][RTW89_UK][1][19] = 56,
+ [2][0][RTW89_UK][0][19] = 18,
+ [2][0][RTW89_FCC][1][21] = 8,
+ [2][0][RTW89_FCC][2][21] = 60,
+ [2][0][RTW89_ETSI][1][21] = 56,
+ [2][0][RTW89_ETSI][0][21] = 18,
+ [2][0][RTW89_MKK][1][21] = 54,
+ [2][0][RTW89_MKK][0][21] = 14,
+ [2][0][RTW89_IC][1][21] = 8,
+ [2][0][RTW89_KCC][1][21] = -2,
+ [2][0][RTW89_KCC][0][21] = -2,
+ [2][0][RTW89_ACMA][1][21] = 56,
+ [2][0][RTW89_ACMA][0][21] = 18,
+ [2][0][RTW89_CHILE][1][21] = 8,
+ [2][0][RTW89_QATAR][1][21] = 56,
+ [2][0][RTW89_QATAR][0][21] = 18,
+ [2][0][RTW89_UK][1][21] = 56,
+ [2][0][RTW89_UK][0][21] = 18,
+ [2][0][RTW89_FCC][1][23] = 8,
+ [2][0][RTW89_FCC][2][23] = 78,
+ [2][0][RTW89_ETSI][1][23] = 56,
+ [2][0][RTW89_ETSI][0][23] = 18,
+ [2][0][RTW89_MKK][1][23] = 56,
+ [2][0][RTW89_MKK][0][23] = 14,
+ [2][0][RTW89_IC][1][23] = 8,
+ [2][0][RTW89_KCC][1][23] = -2,
+ [2][0][RTW89_KCC][0][23] = -2,
+ [2][0][RTW89_ACMA][1][23] = 56,
+ [2][0][RTW89_ACMA][0][23] = 18,
+ [2][0][RTW89_CHILE][1][23] = 8,
+ [2][0][RTW89_QATAR][1][23] = 56,
+ [2][0][RTW89_QATAR][0][23] = 18,
+ [2][0][RTW89_UK][1][23] = 56,
+ [2][0][RTW89_UK][0][23] = 18,
+ [2][0][RTW89_FCC][1][25] = 8,
+ [2][0][RTW89_FCC][2][25] = 78,
+ [2][0][RTW89_ETSI][1][25] = 56,
+ [2][0][RTW89_ETSI][0][25] = 18,
+ [2][0][RTW89_MKK][1][25] = 56,
+ [2][0][RTW89_MKK][0][25] = 14,
+ [2][0][RTW89_IC][1][25] = 8,
+ [2][0][RTW89_KCC][1][25] = -2,
+ [2][0][RTW89_KCC][0][25] = -2,
+ [2][0][RTW89_ACMA][1][25] = 56,
+ [2][0][RTW89_ACMA][0][25] = 18,
+ [2][0][RTW89_CHILE][1][25] = 8,
+ [2][0][RTW89_QATAR][1][25] = 56,
+ [2][0][RTW89_QATAR][0][25] = 18,
+ [2][0][RTW89_UK][1][25] = 56,
+ [2][0][RTW89_UK][0][25] = 18,
+ [2][0][RTW89_FCC][1][27] = 8,
+ [2][0][RTW89_FCC][2][27] = 78,
+ [2][0][RTW89_ETSI][1][27] = 56,
+ [2][0][RTW89_ETSI][0][27] = 18,
+ [2][0][RTW89_MKK][1][27] = 56,
+ [2][0][RTW89_MKK][0][27] = 14,
+ [2][0][RTW89_IC][1][27] = 8,
+ [2][0][RTW89_KCC][1][27] = -2,
+ [2][0][RTW89_KCC][0][27] = -2,
+ [2][0][RTW89_ACMA][1][27] = 56,
+ [2][0][RTW89_ACMA][0][27] = 18,
+ [2][0][RTW89_CHILE][1][27] = 8,
+ [2][0][RTW89_QATAR][1][27] = 56,
+ [2][0][RTW89_QATAR][0][27] = 18,
+ [2][0][RTW89_UK][1][27] = 56,
+ [2][0][RTW89_UK][0][27] = 18,
+ [2][0][RTW89_FCC][1][29] = 8,
+ [2][0][RTW89_FCC][2][29] = 78,
+ [2][0][RTW89_ETSI][1][29] = 56,
+ [2][0][RTW89_ETSI][0][29] = 18,
+ [2][0][RTW89_MKK][1][29] = 56,
+ [2][0][RTW89_MKK][0][29] = 14,
+ [2][0][RTW89_IC][1][29] = 8,
+ [2][0][RTW89_KCC][1][29] = -2,
+ [2][0][RTW89_KCC][0][29] = -2,
+ [2][0][RTW89_ACMA][1][29] = 56,
+ [2][0][RTW89_ACMA][0][29] = 18,
+ [2][0][RTW89_CHILE][1][29] = 8,
+ [2][0][RTW89_QATAR][1][29] = 56,
+ [2][0][RTW89_QATAR][0][29] = 18,
+ [2][0][RTW89_UK][1][29] = 56,
+ [2][0][RTW89_UK][0][29] = 18,
+ [2][0][RTW89_FCC][1][30] = 8,
+ [2][0][RTW89_FCC][2][30] = 78,
+ [2][0][RTW89_ETSI][1][30] = 56,
+ [2][0][RTW89_ETSI][0][30] = 18,
+ [2][0][RTW89_MKK][1][30] = 56,
+ [2][0][RTW89_MKK][0][30] = 14,
+ [2][0][RTW89_IC][1][30] = 8,
+ [2][0][RTW89_KCC][1][30] = -2,
+ [2][0][RTW89_KCC][0][30] = -2,
+ [2][0][RTW89_ACMA][1][30] = 56,
+ [2][0][RTW89_ACMA][0][30] = 18,
+ [2][0][RTW89_CHILE][1][30] = 8,
+ [2][0][RTW89_QATAR][1][30] = 56,
+ [2][0][RTW89_QATAR][0][30] = 18,
+ [2][0][RTW89_UK][1][30] = 56,
+ [2][0][RTW89_UK][0][30] = 18,
+ [2][0][RTW89_FCC][1][32] = 8,
+ [2][0][RTW89_FCC][2][32] = 78,
+ [2][0][RTW89_ETSI][1][32] = 56,
+ [2][0][RTW89_ETSI][0][32] = 18,
+ [2][0][RTW89_MKK][1][32] = 56,
+ [2][0][RTW89_MKK][0][32] = 14,
+ [2][0][RTW89_IC][1][32] = 8,
+ [2][0][RTW89_KCC][1][32] = -2,
+ [2][0][RTW89_KCC][0][32] = -2,
+ [2][0][RTW89_ACMA][1][32] = 56,
+ [2][0][RTW89_ACMA][0][32] = 18,
+ [2][0][RTW89_CHILE][1][32] = 8,
+ [2][0][RTW89_QATAR][1][32] = 56,
+ [2][0][RTW89_QATAR][0][32] = 18,
+ [2][0][RTW89_UK][1][32] = 56,
+ [2][0][RTW89_UK][0][32] = 18,
+ [2][0][RTW89_FCC][1][34] = 8,
+ [2][0][RTW89_FCC][2][34] = 78,
+ [2][0][RTW89_ETSI][1][34] = 56,
+ [2][0][RTW89_ETSI][0][34] = 18,
+ [2][0][RTW89_MKK][1][34] = 56,
+ [2][0][RTW89_MKK][0][34] = 14,
+ [2][0][RTW89_IC][1][34] = 8,
+ [2][0][RTW89_KCC][1][34] = -2,
+ [2][0][RTW89_KCC][0][34] = -2,
+ [2][0][RTW89_ACMA][1][34] = 56,
+ [2][0][RTW89_ACMA][0][34] = 18,
+ [2][0][RTW89_CHILE][1][34] = 8,
+ [2][0][RTW89_QATAR][1][34] = 56,
+ [2][0][RTW89_QATAR][0][34] = 18,
+ [2][0][RTW89_UK][1][34] = 56,
+ [2][0][RTW89_UK][0][34] = 18,
+ [2][0][RTW89_FCC][1][36] = 8,
+ [2][0][RTW89_FCC][2][36] = 78,
+ [2][0][RTW89_ETSI][1][36] = 56,
+ [2][0][RTW89_ETSI][0][36] = 18,
+ [2][0][RTW89_MKK][1][36] = 56,
+ [2][0][RTW89_MKK][0][36] = 14,
+ [2][0][RTW89_IC][1][36] = 8,
+ [2][0][RTW89_KCC][1][36] = -2,
+ [2][0][RTW89_KCC][0][36] = -2,
+ [2][0][RTW89_ACMA][1][36] = 56,
+ [2][0][RTW89_ACMA][0][36] = 18,
+ [2][0][RTW89_CHILE][1][36] = 8,
+ [2][0][RTW89_QATAR][1][36] = 56,
+ [2][0][RTW89_QATAR][0][36] = 18,
+ [2][0][RTW89_UK][1][36] = 56,
+ [2][0][RTW89_UK][0][36] = 18,
+ [2][0][RTW89_FCC][1][38] = 8,
+ [2][0][RTW89_FCC][2][38] = 78,
+ [2][0][RTW89_ETSI][1][38] = 56,
+ [2][0][RTW89_ETSI][0][38] = 18,
+ [2][0][RTW89_MKK][1][38] = 56,
+ [2][0][RTW89_MKK][0][38] = 14,
+ [2][0][RTW89_IC][1][38] = 8,
+ [2][0][RTW89_KCC][1][38] = -2,
+ [2][0][RTW89_KCC][0][38] = -2,
+ [2][0][RTW89_ACMA][1][38] = 56,
+ [2][0][RTW89_ACMA][0][38] = 18,
+ [2][0][RTW89_CHILE][1][38] = 8,
+ [2][0][RTW89_QATAR][1][38] = 56,
+ [2][0][RTW89_QATAR][0][38] = 18,
+ [2][0][RTW89_UK][1][38] = 56,
+ [2][0][RTW89_UK][0][38] = 18,
+ [2][0][RTW89_FCC][1][40] = 8,
+ [2][0][RTW89_FCC][2][40] = 78,
+ [2][0][RTW89_ETSI][1][40] = 56,
+ [2][0][RTW89_ETSI][0][40] = 18,
+ [2][0][RTW89_MKK][1][40] = 56,
+ [2][0][RTW89_MKK][0][40] = 14,
+ [2][0][RTW89_IC][1][40] = 8,
+ [2][0][RTW89_KCC][1][40] = -2,
+ [2][0][RTW89_KCC][0][40] = -2,
+ [2][0][RTW89_ACMA][1][40] = 56,
+ [2][0][RTW89_ACMA][0][40] = 18,
+ [2][0][RTW89_CHILE][1][40] = 8,
+ [2][0][RTW89_QATAR][1][40] = 56,
+ [2][0][RTW89_QATAR][0][40] = 18,
+ [2][0][RTW89_UK][1][40] = 56,
+ [2][0][RTW89_UK][0][40] = 18,
+ [2][0][RTW89_FCC][1][42] = 8,
+ [2][0][RTW89_FCC][2][42] = 78,
+ [2][0][RTW89_ETSI][1][42] = 56,
+ [2][0][RTW89_ETSI][0][42] = 18,
+ [2][0][RTW89_MKK][1][42] = 56,
+ [2][0][RTW89_MKK][0][42] = 14,
+ [2][0][RTW89_IC][1][42] = 8,
+ [2][0][RTW89_KCC][1][42] = -2,
+ [2][0][RTW89_KCC][0][42] = -2,
+ [2][0][RTW89_ACMA][1][42] = 56,
+ [2][0][RTW89_ACMA][0][42] = 18,
+ [2][0][RTW89_CHILE][1][42] = 8,
+ [2][0][RTW89_QATAR][1][42] = 56,
+ [2][0][RTW89_QATAR][0][42] = 18,
+ [2][0][RTW89_UK][1][42] = 56,
+ [2][0][RTW89_UK][0][42] = 18,
+ [2][0][RTW89_FCC][1][44] = 8,
+ [2][0][RTW89_FCC][2][44] = 78,
+ [2][0][RTW89_ETSI][1][44] = 56,
+ [2][0][RTW89_ETSI][0][44] = 18,
+ [2][0][RTW89_MKK][1][44] = 32,
+ [2][0][RTW89_MKK][0][44] = 14,
+ [2][0][RTW89_IC][1][44] = 8,
+ [2][0][RTW89_KCC][1][44] = -2,
+ [2][0][RTW89_KCC][0][44] = -2,
+ [2][0][RTW89_ACMA][1][44] = 56,
+ [2][0][RTW89_ACMA][0][44] = 18,
+ [2][0][RTW89_CHILE][1][44] = 8,
+ [2][0][RTW89_QATAR][1][44] = 56,
+ [2][0][RTW89_QATAR][0][44] = 18,
+ [2][0][RTW89_UK][1][44] = 56,
+ [2][0][RTW89_UK][0][44] = 18,
+ [2][0][RTW89_FCC][1][45] = 8,
+ [2][0][RTW89_FCC][2][45] = 127,
+ [2][0][RTW89_ETSI][1][45] = 127,
+ [2][0][RTW89_ETSI][0][45] = 127,
+ [2][0][RTW89_MKK][1][45] = 127,
+ [2][0][RTW89_MKK][0][45] = 127,
+ [2][0][RTW89_IC][1][45] = 8,
+ [2][0][RTW89_KCC][1][45] = -2,
+ [2][0][RTW89_KCC][0][45] = 127,
+ [2][0][RTW89_ACMA][1][45] = 127,
+ [2][0][RTW89_ACMA][0][45] = 127,
+ [2][0][RTW89_CHILE][1][45] = 127,
+ [2][0][RTW89_QATAR][1][45] = 127,
+ [2][0][RTW89_QATAR][0][45] = 127,
+ [2][0][RTW89_UK][1][45] = 127,
+ [2][0][RTW89_UK][0][45] = 127,
+ [2][0][RTW89_FCC][1][47] = 8,
+ [2][0][RTW89_FCC][2][47] = 127,
+ [2][0][RTW89_ETSI][1][47] = 127,
+ [2][0][RTW89_ETSI][0][47] = 127,
+ [2][0][RTW89_MKK][1][47] = 127,
+ [2][0][RTW89_MKK][0][47] = 127,
+ [2][0][RTW89_IC][1][47] = 8,
+ [2][0][RTW89_KCC][1][47] = -2,
+ [2][0][RTW89_KCC][0][47] = 127,
+ [2][0][RTW89_ACMA][1][47] = 127,
+ [2][0][RTW89_ACMA][0][47] = 127,
+ [2][0][RTW89_CHILE][1][47] = 127,
+ [2][0][RTW89_QATAR][1][47] = 127,
+ [2][0][RTW89_QATAR][0][47] = 127,
+ [2][0][RTW89_UK][1][47] = 127,
+ [2][0][RTW89_UK][0][47] = 127,
+ [2][0][RTW89_FCC][1][49] = 8,
+ [2][0][RTW89_FCC][2][49] = 127,
+ [2][0][RTW89_ETSI][1][49] = 127,
+ [2][0][RTW89_ETSI][0][49] = 127,
+ [2][0][RTW89_MKK][1][49] = 127,
+ [2][0][RTW89_MKK][0][49] = 127,
+ [2][0][RTW89_IC][1][49] = 8,
+ [2][0][RTW89_KCC][1][49] = -2,
+ [2][0][RTW89_KCC][0][49] = 127,
+ [2][0][RTW89_ACMA][1][49] = 127,
+ [2][0][RTW89_ACMA][0][49] = 127,
+ [2][0][RTW89_CHILE][1][49] = 127,
+ [2][0][RTW89_QATAR][1][49] = 127,
+ [2][0][RTW89_QATAR][0][49] = 127,
+ [2][0][RTW89_UK][1][49] = 127,
+ [2][0][RTW89_UK][0][49] = 127,
+ [2][0][RTW89_FCC][1][51] = 8,
+ [2][0][RTW89_FCC][2][51] = 127,
+ [2][0][RTW89_ETSI][1][51] = 127,
+ [2][0][RTW89_ETSI][0][51] = 127,
+ [2][0][RTW89_MKK][1][51] = 127,
+ [2][0][RTW89_MKK][0][51] = 127,
+ [2][0][RTW89_IC][1][51] = 8,
+ [2][0][RTW89_KCC][1][51] = -2,
+ [2][0][RTW89_KCC][0][51] = 127,
+ [2][0][RTW89_ACMA][1][51] = 127,
+ [2][0][RTW89_ACMA][0][51] = 127,
+ [2][0][RTW89_CHILE][1][51] = 127,
+ [2][0][RTW89_QATAR][1][51] = 127,
+ [2][0][RTW89_QATAR][0][51] = 127,
+ [2][0][RTW89_UK][1][51] = 127,
+ [2][0][RTW89_UK][0][51] = 127,
+ [2][0][RTW89_FCC][1][53] = 8,
+ [2][0][RTW89_FCC][2][53] = 127,
+ [2][0][RTW89_ETSI][1][53] = 127,
+ [2][0][RTW89_ETSI][0][53] = 127,
+ [2][0][RTW89_MKK][1][53] = 127,
+ [2][0][RTW89_MKK][0][53] = 127,
+ [2][0][RTW89_IC][1][53] = 8,
+ [2][0][RTW89_KCC][1][53] = -2,
+ [2][0][RTW89_KCC][0][53] = 127,
+ [2][0][RTW89_ACMA][1][53] = 127,
+ [2][0][RTW89_ACMA][0][53] = 127,
+ [2][0][RTW89_CHILE][1][53] = 127,
+ [2][0][RTW89_QATAR][1][53] = 127,
+ [2][0][RTW89_QATAR][0][53] = 127,
+ [2][0][RTW89_UK][1][53] = 127,
+ [2][0][RTW89_UK][0][53] = 127,
+ [2][0][RTW89_FCC][1][55] = 8,
+ [2][0][RTW89_FCC][2][55] = 78,
+ [2][0][RTW89_ETSI][1][55] = 127,
+ [2][0][RTW89_ETSI][0][55] = 127,
+ [2][0][RTW89_MKK][1][55] = 127,
+ [2][0][RTW89_MKK][0][55] = 127,
+ [2][0][RTW89_IC][1][55] = 8,
+ [2][0][RTW89_KCC][1][55] = -2,
+ [2][0][RTW89_KCC][0][55] = 127,
+ [2][0][RTW89_ACMA][1][55] = 127,
+ [2][0][RTW89_ACMA][0][55] = 127,
+ [2][0][RTW89_CHILE][1][55] = 127,
+ [2][0][RTW89_QATAR][1][55] = 127,
+ [2][0][RTW89_QATAR][0][55] = 127,
+ [2][0][RTW89_UK][1][55] = 127,
+ [2][0][RTW89_UK][0][55] = 127,
+ [2][0][RTW89_FCC][1][57] = 8,
+ [2][0][RTW89_FCC][2][57] = 78,
+ [2][0][RTW89_ETSI][1][57] = 127,
+ [2][0][RTW89_ETSI][0][57] = 127,
+ [2][0][RTW89_MKK][1][57] = 127,
+ [2][0][RTW89_MKK][0][57] = 127,
+ [2][0][RTW89_IC][1][57] = 8,
+ [2][0][RTW89_KCC][1][57] = -2,
+ [2][0][RTW89_KCC][0][57] = 127,
+ [2][0][RTW89_ACMA][1][57] = 127,
+ [2][0][RTW89_ACMA][0][57] = 127,
+ [2][0][RTW89_CHILE][1][57] = 127,
+ [2][0][RTW89_QATAR][1][57] = 127,
+ [2][0][RTW89_QATAR][0][57] = 127,
+ [2][0][RTW89_UK][1][57] = 127,
+ [2][0][RTW89_UK][0][57] = 127,
+ [2][0][RTW89_FCC][1][59] = 8,
+ [2][0][RTW89_FCC][2][59] = 78,
+ [2][0][RTW89_ETSI][1][59] = 127,
+ [2][0][RTW89_ETSI][0][59] = 127,
+ [2][0][RTW89_MKK][1][59] = 127,
+ [2][0][RTW89_MKK][0][59] = 127,
+ [2][0][RTW89_IC][1][59] = 8,
+ [2][0][RTW89_KCC][1][59] = -2,
+ [2][0][RTW89_KCC][0][59] = 127,
+ [2][0][RTW89_ACMA][1][59] = 127,
+ [2][0][RTW89_ACMA][0][59] = 127,
+ [2][0][RTW89_CHILE][1][59] = 127,
+ [2][0][RTW89_QATAR][1][59] = 127,
+ [2][0][RTW89_QATAR][0][59] = 127,
+ [2][0][RTW89_UK][1][59] = 127,
+ [2][0][RTW89_UK][0][59] = 127,
+ [2][0][RTW89_FCC][1][60] = 8,
+ [2][0][RTW89_FCC][2][60] = 78,
+ [2][0][RTW89_ETSI][1][60] = 127,
+ [2][0][RTW89_ETSI][0][60] = 127,
+ [2][0][RTW89_MKK][1][60] = 127,
+ [2][0][RTW89_MKK][0][60] = 127,
+ [2][0][RTW89_IC][1][60] = 8,
+ [2][0][RTW89_KCC][1][60] = -2,
+ [2][0][RTW89_KCC][0][60] = 127,
+ [2][0][RTW89_ACMA][1][60] = 127,
+ [2][0][RTW89_ACMA][0][60] = 127,
+ [2][0][RTW89_CHILE][1][60] = 127,
+ [2][0][RTW89_QATAR][1][60] = 127,
+ [2][0][RTW89_QATAR][0][60] = 127,
+ [2][0][RTW89_UK][1][60] = 127,
+ [2][0][RTW89_UK][0][60] = 127,
+ [2][0][RTW89_FCC][1][62] = 8,
+ [2][0][RTW89_FCC][2][62] = 78,
+ [2][0][RTW89_ETSI][1][62] = 127,
+ [2][0][RTW89_ETSI][0][62] = 127,
+ [2][0][RTW89_MKK][1][62] = 127,
+ [2][0][RTW89_MKK][0][62] = 127,
+ [2][0][RTW89_IC][1][62] = 8,
+ [2][0][RTW89_KCC][1][62] = -2,
+ [2][0][RTW89_KCC][0][62] = 127,
+ [2][0][RTW89_ACMA][1][62] = 127,
+ [2][0][RTW89_ACMA][0][62] = 127,
+ [2][0][RTW89_CHILE][1][62] = 127,
+ [2][0][RTW89_QATAR][1][62] = 127,
+ [2][0][RTW89_QATAR][0][62] = 127,
+ [2][0][RTW89_UK][1][62] = 127,
+ [2][0][RTW89_UK][0][62] = 127,
+ [2][0][RTW89_FCC][1][64] = 8,
+ [2][0][RTW89_FCC][2][64] = 78,
+ [2][0][RTW89_ETSI][1][64] = 127,
+ [2][0][RTW89_ETSI][0][64] = 127,
+ [2][0][RTW89_MKK][1][64] = 127,
+ [2][0][RTW89_MKK][0][64] = 127,
+ [2][0][RTW89_IC][1][64] = 8,
+ [2][0][RTW89_KCC][1][64] = -2,
+ [2][0][RTW89_KCC][0][64] = 127,
+ [2][0][RTW89_ACMA][1][64] = 127,
+ [2][0][RTW89_ACMA][0][64] = 127,
+ [2][0][RTW89_CHILE][1][64] = 127,
+ [2][0][RTW89_QATAR][1][64] = 127,
+ [2][0][RTW89_QATAR][0][64] = 127,
+ [2][0][RTW89_UK][1][64] = 127,
+ [2][0][RTW89_UK][0][64] = 127,
+ [2][0][RTW89_FCC][1][66] = 8,
+ [2][0][RTW89_FCC][2][66] = 78,
+ [2][0][RTW89_ETSI][1][66] = 127,
+ [2][0][RTW89_ETSI][0][66] = 127,
+ [2][0][RTW89_MKK][1][66] = 127,
+ [2][0][RTW89_MKK][0][66] = 127,
+ [2][0][RTW89_IC][1][66] = 8,
+ [2][0][RTW89_KCC][1][66] = -2,
+ [2][0][RTW89_KCC][0][66] = 127,
+ [2][0][RTW89_ACMA][1][66] = 127,
+ [2][0][RTW89_ACMA][0][66] = 127,
+ [2][0][RTW89_CHILE][1][66] = 127,
+ [2][0][RTW89_QATAR][1][66] = 127,
+ [2][0][RTW89_QATAR][0][66] = 127,
+ [2][0][RTW89_UK][1][66] = 127,
+ [2][0][RTW89_UK][0][66] = 127,
+ [2][0][RTW89_FCC][1][68] = 8,
+ [2][0][RTW89_FCC][2][68] = 78,
+ [2][0][RTW89_ETSI][1][68] = 127,
+ [2][0][RTW89_ETSI][0][68] = 127,
+ [2][0][RTW89_MKK][1][68] = 127,
+ [2][0][RTW89_MKK][0][68] = 127,
+ [2][0][RTW89_IC][1][68] = 8,
+ [2][0][RTW89_KCC][1][68] = -2,
+ [2][0][RTW89_KCC][0][68] = 127,
+ [2][0][RTW89_ACMA][1][68] = 127,
+ [2][0][RTW89_ACMA][0][68] = 127,
+ [2][0][RTW89_CHILE][1][68] = 127,
+ [2][0][RTW89_QATAR][1][68] = 127,
+ [2][0][RTW89_QATAR][0][68] = 127,
+ [2][0][RTW89_UK][1][68] = 127,
+ [2][0][RTW89_UK][0][68] = 127,
+ [2][0][RTW89_FCC][1][70] = 8,
+ [2][0][RTW89_FCC][2][70] = 78,
+ [2][0][RTW89_ETSI][1][70] = 127,
+ [2][0][RTW89_ETSI][0][70] = 127,
+ [2][0][RTW89_MKK][1][70] = 127,
+ [2][0][RTW89_MKK][0][70] = 127,
+ [2][0][RTW89_IC][1][70] = 8,
+ [2][0][RTW89_KCC][1][70] = -2,
+ [2][0][RTW89_KCC][0][70] = 127,
+ [2][0][RTW89_ACMA][1][70] = 127,
+ [2][0][RTW89_ACMA][0][70] = 127,
+ [2][0][RTW89_CHILE][1][70] = 127,
+ [2][0][RTW89_QATAR][1][70] = 127,
+ [2][0][RTW89_QATAR][0][70] = 127,
+ [2][0][RTW89_UK][1][70] = 127,
+ [2][0][RTW89_UK][0][70] = 127,
+ [2][0][RTW89_FCC][1][72] = 8,
+ [2][0][RTW89_FCC][2][72] = 78,
+ [2][0][RTW89_ETSI][1][72] = 127,
+ [2][0][RTW89_ETSI][0][72] = 127,
+ [2][0][RTW89_MKK][1][72] = 127,
+ [2][0][RTW89_MKK][0][72] = 127,
+ [2][0][RTW89_IC][1][72] = 8,
+ [2][0][RTW89_KCC][1][72] = -2,
+ [2][0][RTW89_KCC][0][72] = 127,
+ [2][0][RTW89_ACMA][1][72] = 127,
+ [2][0][RTW89_ACMA][0][72] = 127,
+ [2][0][RTW89_CHILE][1][72] = 127,
+ [2][0][RTW89_QATAR][1][72] = 127,
+ [2][0][RTW89_QATAR][0][72] = 127,
+ [2][0][RTW89_UK][1][72] = 127,
+ [2][0][RTW89_UK][0][72] = 127,
+ [2][0][RTW89_FCC][1][74] = 8,
+ [2][0][RTW89_FCC][2][74] = 78,
+ [2][0][RTW89_ETSI][1][74] = 127,
+ [2][0][RTW89_ETSI][0][74] = 127,
+ [2][0][RTW89_MKK][1][74] = 127,
+ [2][0][RTW89_MKK][0][74] = 127,
+ [2][0][RTW89_IC][1][74] = 8,
+ [2][0][RTW89_KCC][1][74] = -2,
+ [2][0][RTW89_KCC][0][74] = 127,
+ [2][0][RTW89_ACMA][1][74] = 127,
+ [2][0][RTW89_ACMA][0][74] = 127,
+ [2][0][RTW89_CHILE][1][74] = 127,
+ [2][0][RTW89_QATAR][1][74] = 127,
+ [2][0][RTW89_QATAR][0][74] = 127,
+ [2][0][RTW89_UK][1][74] = 127,
+ [2][0][RTW89_UK][0][74] = 127,
+ [2][0][RTW89_FCC][1][75] = 8,
+ [2][0][RTW89_FCC][2][75] = 78,
+ [2][0][RTW89_ETSI][1][75] = 127,
+ [2][0][RTW89_ETSI][0][75] = 127,
+ [2][0][RTW89_MKK][1][75] = 127,
+ [2][0][RTW89_MKK][0][75] = 127,
+ [2][0][RTW89_IC][1][75] = 8,
+ [2][0][RTW89_KCC][1][75] = -2,
+ [2][0][RTW89_KCC][0][75] = 127,
+ [2][0][RTW89_ACMA][1][75] = 127,
+ [2][0][RTW89_ACMA][0][75] = 127,
+ [2][0][RTW89_CHILE][1][75] = 127,
+ [2][0][RTW89_QATAR][1][75] = 127,
+ [2][0][RTW89_QATAR][0][75] = 127,
+ [2][0][RTW89_UK][1][75] = 127,
+ [2][0][RTW89_UK][0][75] = 127,
+ [2][0][RTW89_FCC][1][77] = 8,
+ [2][0][RTW89_FCC][2][77] = 78,
+ [2][0][RTW89_ETSI][1][77] = 127,
+ [2][0][RTW89_ETSI][0][77] = 127,
+ [2][0][RTW89_MKK][1][77] = 127,
+ [2][0][RTW89_MKK][0][77] = 127,
+ [2][0][RTW89_IC][1][77] = 8,
+ [2][0][RTW89_KCC][1][77] = -2,
+ [2][0][RTW89_KCC][0][77] = 127,
+ [2][0][RTW89_ACMA][1][77] = 127,
+ [2][0][RTW89_ACMA][0][77] = 127,
+ [2][0][RTW89_CHILE][1][77] = 127,
+ [2][0][RTW89_QATAR][1][77] = 127,
+ [2][0][RTW89_QATAR][0][77] = 127,
+ [2][0][RTW89_UK][1][77] = 127,
+ [2][0][RTW89_UK][0][77] = 127,
+ [2][0][RTW89_FCC][1][79] = 8,
+ [2][0][RTW89_FCC][2][79] = 78,
+ [2][0][RTW89_ETSI][1][79] = 127,
+ [2][0][RTW89_ETSI][0][79] = 127,
+ [2][0][RTW89_MKK][1][79] = 127,
+ [2][0][RTW89_MKK][0][79] = 127,
+ [2][0][RTW89_IC][1][79] = 8,
+ [2][0][RTW89_KCC][1][79] = -2,
+ [2][0][RTW89_KCC][0][79] = 127,
+ [2][0][RTW89_ACMA][1][79] = 127,
+ [2][0][RTW89_ACMA][0][79] = 127,
+ [2][0][RTW89_CHILE][1][79] = 127,
+ [2][0][RTW89_QATAR][1][79] = 127,
+ [2][0][RTW89_QATAR][0][79] = 127,
+ [2][0][RTW89_UK][1][79] = 127,
+ [2][0][RTW89_UK][0][79] = 127,
+ [2][0][RTW89_FCC][1][81] = 8,
+ [2][0][RTW89_FCC][2][81] = 78,
+ [2][0][RTW89_ETSI][1][81] = 127,
+ [2][0][RTW89_ETSI][0][81] = 127,
+ [2][0][RTW89_MKK][1][81] = 127,
+ [2][0][RTW89_MKK][0][81] = 127,
+ [2][0][RTW89_IC][1][81] = 8,
+ [2][0][RTW89_KCC][1][81] = -2,
+ [2][0][RTW89_KCC][0][81] = 127,
+ [2][0][RTW89_ACMA][1][81] = 127,
+ [2][0][RTW89_ACMA][0][81] = 127,
+ [2][0][RTW89_CHILE][1][81] = 127,
+ [2][0][RTW89_QATAR][1][81] = 127,
+ [2][0][RTW89_QATAR][0][81] = 127,
+ [2][0][RTW89_UK][1][81] = 127,
+ [2][0][RTW89_UK][0][81] = 127,
+ [2][0][RTW89_FCC][1][83] = 8,
+ [2][0][RTW89_FCC][2][83] = 78,
+ [2][0][RTW89_ETSI][1][83] = 127,
+ [2][0][RTW89_ETSI][0][83] = 127,
+ [2][0][RTW89_MKK][1][83] = 127,
+ [2][0][RTW89_MKK][0][83] = 127,
+ [2][0][RTW89_IC][1][83] = 8,
+ [2][0][RTW89_KCC][1][83] = -2,
+ [2][0][RTW89_KCC][0][83] = 127,
+ [2][0][RTW89_ACMA][1][83] = 127,
+ [2][0][RTW89_ACMA][0][83] = 127,
+ [2][0][RTW89_CHILE][1][83] = 127,
+ [2][0][RTW89_QATAR][1][83] = 127,
+ [2][0][RTW89_QATAR][0][83] = 127,
+ [2][0][RTW89_UK][1][83] = 127,
+ [2][0][RTW89_UK][0][83] = 127,
+ [2][0][RTW89_FCC][1][85] = 8,
+ [2][0][RTW89_FCC][2][85] = 78,
+ [2][0][RTW89_ETSI][1][85] = 127,
+ [2][0][RTW89_ETSI][0][85] = 127,
+ [2][0][RTW89_MKK][1][85] = 127,
+ [2][0][RTW89_MKK][0][85] = 127,
+ [2][0][RTW89_IC][1][85] = 8,
+ [2][0][RTW89_KCC][1][85] = -2,
+ [2][0][RTW89_KCC][0][85] = 127,
+ [2][0][RTW89_ACMA][1][85] = 127,
+ [2][0][RTW89_ACMA][0][85] = 127,
+ [2][0][RTW89_CHILE][1][85] = 127,
+ [2][0][RTW89_QATAR][1][85] = 127,
+ [2][0][RTW89_QATAR][0][85] = 127,
+ [2][0][RTW89_UK][1][85] = 127,
+ [2][0][RTW89_UK][0][85] = 127,
+ [2][0][RTW89_FCC][1][87] = 8,
+ [2][0][RTW89_FCC][2][87] = 127,
+ [2][0][RTW89_ETSI][1][87] = 127,
+ [2][0][RTW89_ETSI][0][87] = 127,
+ [2][0][RTW89_MKK][1][87] = 127,
+ [2][0][RTW89_MKK][0][87] = 127,
+ [2][0][RTW89_IC][1][87] = 8,
+ [2][0][RTW89_KCC][1][87] = -2,
+ [2][0][RTW89_KCC][0][87] = 127,
+ [2][0][RTW89_ACMA][1][87] = 127,
+ [2][0][RTW89_ACMA][0][87] = 127,
+ [2][0][RTW89_CHILE][1][87] = 127,
+ [2][0][RTW89_QATAR][1][87] = 127,
+ [2][0][RTW89_QATAR][0][87] = 127,
+ [2][0][RTW89_UK][1][87] = 127,
+ [2][0][RTW89_UK][0][87] = 127,
+ [2][0][RTW89_FCC][1][89] = 8,
+ [2][0][RTW89_FCC][2][89] = 127,
+ [2][0][RTW89_ETSI][1][89] = 127,
+ [2][0][RTW89_ETSI][0][89] = 127,
+ [2][0][RTW89_MKK][1][89] = 127,
+ [2][0][RTW89_MKK][0][89] = 127,
+ [2][0][RTW89_IC][1][89] = 8,
+ [2][0][RTW89_KCC][1][89] = -2,
+ [2][0][RTW89_KCC][0][89] = 127,
+ [2][0][RTW89_ACMA][1][89] = 127,
+ [2][0][RTW89_ACMA][0][89] = 127,
+ [2][0][RTW89_CHILE][1][89] = 127,
+ [2][0][RTW89_QATAR][1][89] = 127,
+ [2][0][RTW89_QATAR][0][89] = 127,
+ [2][0][RTW89_UK][1][89] = 127,
+ [2][0][RTW89_UK][0][89] = 127,
+ [2][0][RTW89_FCC][1][90] = 8,
+ [2][0][RTW89_FCC][2][90] = 127,
+ [2][0][RTW89_ETSI][1][90] = 127,
+ [2][0][RTW89_ETSI][0][90] = 127,
+ [2][0][RTW89_MKK][1][90] = 127,
+ [2][0][RTW89_MKK][0][90] = 127,
+ [2][0][RTW89_IC][1][90] = 8,
+ [2][0][RTW89_KCC][1][90] = -2,
+ [2][0][RTW89_KCC][0][90] = 127,
+ [2][0][RTW89_ACMA][1][90] = 127,
+ [2][0][RTW89_ACMA][0][90] = 127,
+ [2][0][RTW89_CHILE][1][90] = 127,
+ [2][0][RTW89_QATAR][1][90] = 127,
+ [2][0][RTW89_QATAR][0][90] = 127,
+ [2][0][RTW89_UK][1][90] = 127,
+ [2][0][RTW89_UK][0][90] = 127,
+ [2][0][RTW89_FCC][1][92] = 8,
+ [2][0][RTW89_FCC][2][92] = 127,
+ [2][0][RTW89_ETSI][1][92] = 127,
+ [2][0][RTW89_ETSI][0][92] = 127,
+ [2][0][RTW89_MKK][1][92] = 127,
+ [2][0][RTW89_MKK][0][92] = 127,
+ [2][0][RTW89_IC][1][92] = 8,
+ [2][0][RTW89_KCC][1][92] = -2,
+ [2][0][RTW89_KCC][0][92] = 127,
+ [2][0][RTW89_ACMA][1][92] = 127,
+ [2][0][RTW89_ACMA][0][92] = 127,
+ [2][0][RTW89_CHILE][1][92] = 127,
+ [2][0][RTW89_QATAR][1][92] = 127,
+ [2][0][RTW89_QATAR][0][92] = 127,
+ [2][0][RTW89_UK][1][92] = 127,
+ [2][0][RTW89_UK][0][92] = 127,
+ [2][0][RTW89_FCC][1][94] = 8,
+ [2][0][RTW89_FCC][2][94] = 127,
+ [2][0][RTW89_ETSI][1][94] = 127,
+ [2][0][RTW89_ETSI][0][94] = 127,
+ [2][0][RTW89_MKK][1][94] = 127,
+ [2][0][RTW89_MKK][0][94] = 127,
+ [2][0][RTW89_IC][1][94] = 8,
+ [2][0][RTW89_KCC][1][94] = -2,
+ [2][0][RTW89_KCC][0][94] = 127,
+ [2][0][RTW89_ACMA][1][94] = 127,
+ [2][0][RTW89_ACMA][0][94] = 127,
+ [2][0][RTW89_CHILE][1][94] = 127,
+ [2][0][RTW89_QATAR][1][94] = 127,
+ [2][0][RTW89_QATAR][0][94] = 127,
+ [2][0][RTW89_UK][1][94] = 127,
+ [2][0][RTW89_UK][0][94] = 127,
+ [2][0][RTW89_FCC][1][96] = 8,
+ [2][0][RTW89_FCC][2][96] = 127,
+ [2][0][RTW89_ETSI][1][96] = 127,
+ [2][0][RTW89_ETSI][0][96] = 127,
+ [2][0][RTW89_MKK][1][96] = 127,
+ [2][0][RTW89_MKK][0][96] = 127,
+ [2][0][RTW89_IC][1][96] = 8,
+ [2][0][RTW89_KCC][1][96] = -2,
+ [2][0][RTW89_KCC][0][96] = 127,
+ [2][0][RTW89_ACMA][1][96] = 127,
+ [2][0][RTW89_ACMA][0][96] = 127,
+ [2][0][RTW89_CHILE][1][96] = 127,
+ [2][0][RTW89_QATAR][1][96] = 127,
+ [2][0][RTW89_QATAR][0][96] = 127,
+ [2][0][RTW89_UK][1][96] = 127,
+ [2][0][RTW89_UK][0][96] = 127,
+ [2][0][RTW89_FCC][1][98] = 8,
+ [2][0][RTW89_FCC][2][98] = 127,
+ [2][0][RTW89_ETSI][1][98] = 127,
+ [2][0][RTW89_ETSI][0][98] = 127,
+ [2][0][RTW89_MKK][1][98] = 127,
+ [2][0][RTW89_MKK][0][98] = 127,
+ [2][0][RTW89_IC][1][98] = 8,
+ [2][0][RTW89_KCC][1][98] = -2,
+ [2][0][RTW89_KCC][0][98] = 127,
+ [2][0][RTW89_ACMA][1][98] = 127,
+ [2][0][RTW89_ACMA][0][98] = 127,
+ [2][0][RTW89_CHILE][1][98] = 127,
+ [2][0][RTW89_QATAR][1][98] = 127,
+ [2][0][RTW89_QATAR][0][98] = 127,
+ [2][0][RTW89_UK][1][98] = 127,
+ [2][0][RTW89_UK][0][98] = 127,
+ [2][0][RTW89_FCC][1][100] = 8,
+ [2][0][RTW89_FCC][2][100] = 127,
+ [2][0][RTW89_ETSI][1][100] = 127,
+ [2][0][RTW89_ETSI][0][100] = 127,
+ [2][0][RTW89_MKK][1][100] = 127,
+ [2][0][RTW89_MKK][0][100] = 127,
+ [2][0][RTW89_IC][1][100] = 8,
+ [2][0][RTW89_KCC][1][100] = -2,
+ [2][0][RTW89_KCC][0][100] = 127,
+ [2][0][RTW89_ACMA][1][100] = 127,
+ [2][0][RTW89_ACMA][0][100] = 127,
+ [2][0][RTW89_CHILE][1][100] = 127,
+ [2][0][RTW89_QATAR][1][100] = 127,
+ [2][0][RTW89_QATAR][0][100] = 127,
+ [2][0][RTW89_UK][1][100] = 127,
+ [2][0][RTW89_UK][0][100] = 127,
+ [2][0][RTW89_FCC][1][102] = 8,
+ [2][0][RTW89_FCC][2][102] = 127,
+ [2][0][RTW89_ETSI][1][102] = 127,
+ [2][0][RTW89_ETSI][0][102] = 127,
+ [2][0][RTW89_MKK][1][102] = 127,
+ [2][0][RTW89_MKK][0][102] = 127,
+ [2][0][RTW89_IC][1][102] = 8,
+ [2][0][RTW89_KCC][1][102] = -2,
+ [2][0][RTW89_KCC][0][102] = 127,
+ [2][0][RTW89_ACMA][1][102] = 127,
+ [2][0][RTW89_ACMA][0][102] = 127,
+ [2][0][RTW89_CHILE][1][102] = 127,
+ [2][0][RTW89_QATAR][1][102] = 127,
+ [2][0][RTW89_QATAR][0][102] = 127,
+ [2][0][RTW89_UK][1][102] = 127,
+ [2][0][RTW89_UK][0][102] = 127,
+ [2][0][RTW89_FCC][1][104] = 8,
+ [2][0][RTW89_FCC][2][104] = 127,
+ [2][0][RTW89_ETSI][1][104] = 127,
+ [2][0][RTW89_ETSI][0][104] = 127,
+ [2][0][RTW89_MKK][1][104] = 127,
+ [2][0][RTW89_MKK][0][104] = 127,
+ [2][0][RTW89_IC][1][104] = 8,
+ [2][0][RTW89_KCC][1][104] = -2,
+ [2][0][RTW89_KCC][0][104] = 127,
+ [2][0][RTW89_ACMA][1][104] = 127,
+ [2][0][RTW89_ACMA][0][104] = 127,
+ [2][0][RTW89_CHILE][1][104] = 127,
+ [2][0][RTW89_QATAR][1][104] = 127,
+ [2][0][RTW89_QATAR][0][104] = 127,
+ [2][0][RTW89_UK][1][104] = 127,
+ [2][0][RTW89_UK][0][104] = 127,
+ [2][0][RTW89_FCC][1][105] = 8,
+ [2][0][RTW89_FCC][2][105] = 127,
+ [2][0][RTW89_ETSI][1][105] = 127,
+ [2][0][RTW89_ETSI][0][105] = 127,
+ [2][0][RTW89_MKK][1][105] = 127,
+ [2][0][RTW89_MKK][0][105] = 127,
+ [2][0][RTW89_IC][1][105] = 8,
+ [2][0][RTW89_KCC][1][105] = -2,
+ [2][0][RTW89_KCC][0][105] = 127,
+ [2][0][RTW89_ACMA][1][105] = 127,
+ [2][0][RTW89_ACMA][0][105] = 127,
+ [2][0][RTW89_CHILE][1][105] = 127,
+ [2][0][RTW89_QATAR][1][105] = 127,
+ [2][0][RTW89_QATAR][0][105] = 127,
+ [2][0][RTW89_UK][1][105] = 127,
+ [2][0][RTW89_UK][0][105] = 127,
+ [2][0][RTW89_FCC][1][107] = 10,
+ [2][0][RTW89_FCC][2][107] = 127,
+ [2][0][RTW89_ETSI][1][107] = 127,
+ [2][0][RTW89_ETSI][0][107] = 127,
+ [2][0][RTW89_MKK][1][107] = 127,
+ [2][0][RTW89_MKK][0][107] = 127,
+ [2][0][RTW89_IC][1][107] = 10,
+ [2][0][RTW89_KCC][1][107] = -2,
+ [2][0][RTW89_KCC][0][107] = 127,
+ [2][0][RTW89_ACMA][1][107] = 127,
+ [2][0][RTW89_ACMA][0][107] = 127,
+ [2][0][RTW89_CHILE][1][107] = 127,
+ [2][0][RTW89_QATAR][1][107] = 127,
+ [2][0][RTW89_QATAR][0][107] = 127,
+ [2][0][RTW89_UK][1][107] = 127,
+ [2][0][RTW89_UK][0][107] = 127,
+ [2][0][RTW89_FCC][1][109] = 12,
+ [2][0][RTW89_FCC][2][109] = 127,
+ [2][0][RTW89_ETSI][1][109] = 127,
+ [2][0][RTW89_ETSI][0][109] = 127,
+ [2][0][RTW89_MKK][1][109] = 127,
+ [2][0][RTW89_MKK][0][109] = 127,
+ [2][0][RTW89_IC][1][109] = 12,
+ [2][0][RTW89_KCC][1][109] = 127,
+ [2][0][RTW89_KCC][0][109] = 127,
+ [2][0][RTW89_ACMA][1][109] = 127,
+ [2][0][RTW89_ACMA][0][109] = 127,
+ [2][0][RTW89_CHILE][1][109] = 127,
+ [2][0][RTW89_QATAR][1][109] = 127,
+ [2][0][RTW89_QATAR][0][109] = 127,
+ [2][0][RTW89_UK][1][109] = 127,
+ [2][0][RTW89_UK][0][109] = 127,
+ [2][0][RTW89_FCC][1][111] = 127,
+ [2][0][RTW89_FCC][2][111] = 127,
+ [2][0][RTW89_ETSI][1][111] = 127,
+ [2][0][RTW89_ETSI][0][111] = 127,
+ [2][0][RTW89_MKK][1][111] = 127,
+ [2][0][RTW89_MKK][0][111] = 127,
+ [2][0][RTW89_IC][1][111] = 127,
+ [2][0][RTW89_KCC][1][111] = 127,
+ [2][0][RTW89_KCC][0][111] = 127,
+ [2][0][RTW89_ACMA][1][111] = 127,
+ [2][0][RTW89_ACMA][0][111] = 127,
+ [2][0][RTW89_CHILE][1][111] = 127,
+ [2][0][RTW89_QATAR][1][111] = 127,
+ [2][0][RTW89_QATAR][0][111] = 127,
+ [2][0][RTW89_UK][1][111] = 127,
+ [2][0][RTW89_UK][0][111] = 127,
+ [2][0][RTW89_FCC][1][113] = 127,
+ [2][0][RTW89_FCC][2][113] = 127,
+ [2][0][RTW89_ETSI][1][113] = 127,
+ [2][0][RTW89_ETSI][0][113] = 127,
+ [2][0][RTW89_MKK][1][113] = 127,
+ [2][0][RTW89_MKK][0][113] = 127,
+ [2][0][RTW89_IC][1][113] = 127,
+ [2][0][RTW89_KCC][1][113] = 127,
+ [2][0][RTW89_KCC][0][113] = 127,
+ [2][0][RTW89_ACMA][1][113] = 127,
+ [2][0][RTW89_ACMA][0][113] = 127,
+ [2][0][RTW89_CHILE][1][113] = 127,
+ [2][0][RTW89_QATAR][1][113] = 127,
+ [2][0][RTW89_QATAR][0][113] = 127,
+ [2][0][RTW89_UK][1][113] = 127,
+ [2][0][RTW89_UK][0][113] = 127,
+ [2][0][RTW89_FCC][1][115] = 127,
+ [2][0][RTW89_FCC][2][115] = 127,
+ [2][0][RTW89_ETSI][1][115] = 127,
+ [2][0][RTW89_ETSI][0][115] = 127,
+ [2][0][RTW89_MKK][1][115] = 127,
+ [2][0][RTW89_MKK][0][115] = 127,
+ [2][0][RTW89_IC][1][115] = 127,
+ [2][0][RTW89_KCC][1][115] = 127,
+ [2][0][RTW89_KCC][0][115] = 127,
+ [2][0][RTW89_ACMA][1][115] = 127,
+ [2][0][RTW89_ACMA][0][115] = 127,
+ [2][0][RTW89_CHILE][1][115] = 127,
+ [2][0][RTW89_QATAR][1][115] = 127,
+ [2][0][RTW89_QATAR][0][115] = 127,
+ [2][0][RTW89_UK][1][115] = 127,
+ [2][0][RTW89_UK][0][115] = 127,
+ [2][0][RTW89_FCC][1][117] = 127,
+ [2][0][RTW89_FCC][2][117] = 127,
+ [2][0][RTW89_ETSI][1][117] = 127,
+ [2][0][RTW89_ETSI][0][117] = 127,
+ [2][0][RTW89_MKK][1][117] = 127,
+ [2][0][RTW89_MKK][0][117] = 127,
+ [2][0][RTW89_IC][1][117] = 127,
+ [2][0][RTW89_KCC][1][117] = 127,
+ [2][0][RTW89_KCC][0][117] = 127,
+ [2][0][RTW89_ACMA][1][117] = 127,
+ [2][0][RTW89_ACMA][0][117] = 127,
+ [2][0][RTW89_CHILE][1][117] = 127,
+ [2][0][RTW89_QATAR][1][117] = 127,
+ [2][0][RTW89_QATAR][0][117] = 127,
+ [2][0][RTW89_UK][1][117] = 127,
+ [2][0][RTW89_UK][0][117] = 127,
+ [2][0][RTW89_FCC][1][119] = 127,
+ [2][0][RTW89_FCC][2][119] = 127,
+ [2][0][RTW89_ETSI][1][119] = 127,
+ [2][0][RTW89_ETSI][0][119] = 127,
+ [2][0][RTW89_MKK][1][119] = 127,
+ [2][0][RTW89_MKK][0][119] = 127,
+ [2][0][RTW89_IC][1][119] = 127,
+ [2][0][RTW89_KCC][1][119] = 127,
+ [2][0][RTW89_KCC][0][119] = 127,
+ [2][0][RTW89_ACMA][1][119] = 127,
+ [2][0][RTW89_ACMA][0][119] = 127,
+ [2][0][RTW89_CHILE][1][119] = 127,
+ [2][0][RTW89_QATAR][1][119] = 127,
+ [2][0][RTW89_QATAR][0][119] = 127,
+ [2][0][RTW89_UK][1][119] = 127,
+ [2][0][RTW89_UK][0][119] = 127,
+ [2][1][RTW89_FCC][1][0] = -16,
+ [2][1][RTW89_FCC][2][0] = 54,
+ [2][1][RTW89_ETSI][1][0] = 44,
+ [2][1][RTW89_ETSI][0][0] = 6,
+ [2][1][RTW89_MKK][1][0] = 42,
+ [2][1][RTW89_MKK][0][0] = 2,
+ [2][1][RTW89_IC][1][0] = -16,
+ [2][1][RTW89_KCC][1][0] = -14,
+ [2][1][RTW89_KCC][0][0] = -14,
+ [2][1][RTW89_ACMA][1][0] = 44,
+ [2][1][RTW89_ACMA][0][0] = 6,
+ [2][1][RTW89_CHILE][1][0] = -16,
+ [2][1][RTW89_QATAR][1][0] = 44,
+ [2][1][RTW89_QATAR][0][0] = 6,
+ [2][1][RTW89_UK][1][0] = 44,
+ [2][1][RTW89_UK][0][0] = 6,
+ [2][1][RTW89_FCC][1][2] = -16,
+ [2][1][RTW89_FCC][2][2] = 54,
+ [2][1][RTW89_ETSI][1][2] = 44,
+ [2][1][RTW89_ETSI][0][2] = 6,
+ [2][1][RTW89_MKK][1][2] = 40,
+ [2][1][RTW89_MKK][0][2] = 2,
+ [2][1][RTW89_IC][1][2] = -16,
+ [2][1][RTW89_KCC][1][2] = -14,
+ [2][1][RTW89_KCC][0][2] = -14,
+ [2][1][RTW89_ACMA][1][2] = 44,
+ [2][1][RTW89_ACMA][0][2] = 6,
+ [2][1][RTW89_CHILE][1][2] = -16,
+ [2][1][RTW89_QATAR][1][2] = 44,
+ [2][1][RTW89_QATAR][0][2] = 6,
+ [2][1][RTW89_UK][1][2] = 44,
+ [2][1][RTW89_UK][0][2] = 6,
+ [2][1][RTW89_FCC][1][4] = -16,
+ [2][1][RTW89_FCC][2][4] = 54,
+ [2][1][RTW89_ETSI][1][4] = 44,
+ [2][1][RTW89_ETSI][0][4] = 6,
+ [2][1][RTW89_MKK][1][4] = 40,
+ [2][1][RTW89_MKK][0][4] = 2,
+ [2][1][RTW89_IC][1][4] = -16,
+ [2][1][RTW89_KCC][1][4] = -14,
+ [2][1][RTW89_KCC][0][4] = -14,
+ [2][1][RTW89_ACMA][1][4] = 44,
+ [2][1][RTW89_ACMA][0][4] = 6,
+ [2][1][RTW89_CHILE][1][4] = -16,
+ [2][1][RTW89_QATAR][1][4] = 44,
+ [2][1][RTW89_QATAR][0][4] = 6,
+ [2][1][RTW89_UK][1][4] = 44,
+ [2][1][RTW89_UK][0][4] = 6,
+ [2][1][RTW89_FCC][1][6] = -16,
+ [2][1][RTW89_FCC][2][6] = 54,
+ [2][1][RTW89_ETSI][1][6] = 44,
+ [2][1][RTW89_ETSI][0][6] = 6,
+ [2][1][RTW89_MKK][1][6] = 40,
+ [2][1][RTW89_MKK][0][6] = 2,
+ [2][1][RTW89_IC][1][6] = -16,
+ [2][1][RTW89_KCC][1][6] = -14,
+ [2][1][RTW89_KCC][0][6] = -14,
+ [2][1][RTW89_ACMA][1][6] = 44,
+ [2][1][RTW89_ACMA][0][6] = 6,
+ [2][1][RTW89_CHILE][1][6] = -16,
+ [2][1][RTW89_QATAR][1][6] = 44,
+ [2][1][RTW89_QATAR][0][6] = 6,
+ [2][1][RTW89_UK][1][6] = 44,
+ [2][1][RTW89_UK][0][6] = 6,
+ [2][1][RTW89_FCC][1][8] = -16,
+ [2][1][RTW89_FCC][2][8] = 54,
+ [2][1][RTW89_ETSI][1][8] = 44,
+ [2][1][RTW89_ETSI][0][8] = 6,
+ [2][1][RTW89_MKK][1][8] = 40,
+ [2][1][RTW89_MKK][0][8] = 2,
+ [2][1][RTW89_IC][1][8] = -16,
+ [2][1][RTW89_KCC][1][8] = -14,
+ [2][1][RTW89_KCC][0][8] = -14,
+ [2][1][RTW89_ACMA][1][8] = 44,
+ [2][1][RTW89_ACMA][0][8] = 6,
+ [2][1][RTW89_CHILE][1][8] = -16,
+ [2][1][RTW89_QATAR][1][8] = 44,
+ [2][1][RTW89_QATAR][0][8] = 6,
+ [2][1][RTW89_UK][1][8] = 44,
+ [2][1][RTW89_UK][0][8] = 6,
+ [2][1][RTW89_FCC][1][10] = -16,
+ [2][1][RTW89_FCC][2][10] = 54,
+ [2][1][RTW89_ETSI][1][10] = 44,
+ [2][1][RTW89_ETSI][0][10] = 6,
+ [2][1][RTW89_MKK][1][10] = 40,
+ [2][1][RTW89_MKK][0][10] = 2,
+ [2][1][RTW89_IC][1][10] = -16,
+ [2][1][RTW89_KCC][1][10] = -14,
+ [2][1][RTW89_KCC][0][10] = -14,
+ [2][1][RTW89_ACMA][1][10] = 44,
+ [2][1][RTW89_ACMA][0][10] = 6,
+ [2][1][RTW89_CHILE][1][10] = -16,
+ [2][1][RTW89_QATAR][1][10] = 44,
+ [2][1][RTW89_QATAR][0][10] = 6,
+ [2][1][RTW89_UK][1][10] = 44,
+ [2][1][RTW89_UK][0][10] = 6,
+ [2][1][RTW89_FCC][1][12] = -16,
+ [2][1][RTW89_FCC][2][12] = 54,
+ [2][1][RTW89_ETSI][1][12] = 44,
+ [2][1][RTW89_ETSI][0][12] = 6,
+ [2][1][RTW89_MKK][1][12] = 40,
+ [2][1][RTW89_MKK][0][12] = 2,
+ [2][1][RTW89_IC][1][12] = -16,
+ [2][1][RTW89_KCC][1][12] = -14,
+ [2][1][RTW89_KCC][0][12] = -14,
+ [2][1][RTW89_ACMA][1][12] = 44,
+ [2][1][RTW89_ACMA][0][12] = 6,
+ [2][1][RTW89_CHILE][1][12] = -16,
+ [2][1][RTW89_QATAR][1][12] = 44,
+ [2][1][RTW89_QATAR][0][12] = 6,
+ [2][1][RTW89_UK][1][12] = 44,
+ [2][1][RTW89_UK][0][12] = 6,
+ [2][1][RTW89_FCC][1][14] = -16,
+ [2][1][RTW89_FCC][2][14] = 54,
+ [2][1][RTW89_ETSI][1][14] = 44,
+ [2][1][RTW89_ETSI][0][14] = 6,
+ [2][1][RTW89_MKK][1][14] = 40,
+ [2][1][RTW89_MKK][0][14] = 2,
+ [2][1][RTW89_IC][1][14] = -16,
+ [2][1][RTW89_KCC][1][14] = -14,
+ [2][1][RTW89_KCC][0][14] = -14,
+ [2][1][RTW89_ACMA][1][14] = 44,
+ [2][1][RTW89_ACMA][0][14] = 6,
+ [2][1][RTW89_CHILE][1][14] = -16,
+ [2][1][RTW89_QATAR][1][14] = 44,
+ [2][1][RTW89_QATAR][0][14] = 6,
+ [2][1][RTW89_UK][1][14] = 44,
+ [2][1][RTW89_UK][0][14] = 6,
+ [2][1][RTW89_FCC][1][15] = -16,
+ [2][1][RTW89_FCC][2][15] = 54,
+ [2][1][RTW89_ETSI][1][15] = 44,
+ [2][1][RTW89_ETSI][0][15] = 6,
+ [2][1][RTW89_MKK][1][15] = 40,
+ [2][1][RTW89_MKK][0][15] = 2,
+ [2][1][RTW89_IC][1][15] = -16,
+ [2][1][RTW89_KCC][1][15] = -14,
+ [2][1][RTW89_KCC][0][15] = -14,
+ [2][1][RTW89_ACMA][1][15] = 44,
+ [2][1][RTW89_ACMA][0][15] = 6,
+ [2][1][RTW89_CHILE][1][15] = -16,
+ [2][1][RTW89_QATAR][1][15] = 44,
+ [2][1][RTW89_QATAR][0][15] = 6,
+ [2][1][RTW89_UK][1][15] = 44,
+ [2][1][RTW89_UK][0][15] = 6,
+ [2][1][RTW89_FCC][1][17] = -16,
+ [2][1][RTW89_FCC][2][17] = 54,
+ [2][1][RTW89_ETSI][1][17] = 44,
+ [2][1][RTW89_ETSI][0][17] = 6,
+ [2][1][RTW89_MKK][1][17] = 40,
+ [2][1][RTW89_MKK][0][17] = 2,
+ [2][1][RTW89_IC][1][17] = -16,
+ [2][1][RTW89_KCC][1][17] = -14,
+ [2][1][RTW89_KCC][0][17] = -14,
+ [2][1][RTW89_ACMA][1][17] = 44,
+ [2][1][RTW89_ACMA][0][17] = 6,
+ [2][1][RTW89_CHILE][1][17] = -16,
+ [2][1][RTW89_QATAR][1][17] = 44,
+ [2][1][RTW89_QATAR][0][17] = 6,
+ [2][1][RTW89_UK][1][17] = 44,
+ [2][1][RTW89_UK][0][17] = 6,
+ [2][1][RTW89_FCC][1][19] = -16,
+ [2][1][RTW89_FCC][2][19] = 54,
+ [2][1][RTW89_ETSI][1][19] = 44,
+ [2][1][RTW89_ETSI][0][19] = 6,
+ [2][1][RTW89_MKK][1][19] = 40,
+ [2][1][RTW89_MKK][0][19] = 2,
+ [2][1][RTW89_IC][1][19] = -16,
+ [2][1][RTW89_KCC][1][19] = -14,
+ [2][1][RTW89_KCC][0][19] = -14,
+ [2][1][RTW89_ACMA][1][19] = 44,
+ [2][1][RTW89_ACMA][0][19] = 6,
+ [2][1][RTW89_CHILE][1][19] = -16,
+ [2][1][RTW89_QATAR][1][19] = 44,
+ [2][1][RTW89_QATAR][0][19] = 6,
+ [2][1][RTW89_UK][1][19] = 44,
+ [2][1][RTW89_UK][0][19] = 6,
+ [2][1][RTW89_FCC][1][21] = -16,
+ [2][1][RTW89_FCC][2][21] = 54,
+ [2][1][RTW89_ETSI][1][21] = 44,
+ [2][1][RTW89_ETSI][0][21] = 6,
+ [2][1][RTW89_MKK][1][21] = 40,
+ [2][1][RTW89_MKK][0][21] = 2,
+ [2][1][RTW89_IC][1][21] = -16,
+ [2][1][RTW89_KCC][1][21] = -14,
+ [2][1][RTW89_KCC][0][21] = -14,
+ [2][1][RTW89_ACMA][1][21] = 44,
+ [2][1][RTW89_ACMA][0][21] = 6,
+ [2][1][RTW89_CHILE][1][21] = -16,
+ [2][1][RTW89_QATAR][1][21] = 44,
+ [2][1][RTW89_QATAR][0][21] = 6,
+ [2][1][RTW89_UK][1][21] = 44,
+ [2][1][RTW89_UK][0][21] = 6,
+ [2][1][RTW89_FCC][1][23] = -16,
+ [2][1][RTW89_FCC][2][23] = 54,
+ [2][1][RTW89_ETSI][1][23] = 44,
+ [2][1][RTW89_ETSI][0][23] = 6,
+ [2][1][RTW89_MKK][1][23] = 40,
+ [2][1][RTW89_MKK][0][23] = 2,
+ [2][1][RTW89_IC][1][23] = -16,
+ [2][1][RTW89_KCC][1][23] = -14,
+ [2][1][RTW89_KCC][0][23] = -14,
+ [2][1][RTW89_ACMA][1][23] = 44,
+ [2][1][RTW89_ACMA][0][23] = 6,
+ [2][1][RTW89_CHILE][1][23] = -16,
+ [2][1][RTW89_QATAR][1][23] = 44,
+ [2][1][RTW89_QATAR][0][23] = 6,
+ [2][1][RTW89_UK][1][23] = 44,
+ [2][1][RTW89_UK][0][23] = 6,
+ [2][1][RTW89_FCC][1][25] = -16,
+ [2][1][RTW89_FCC][2][25] = 54,
+ [2][1][RTW89_ETSI][1][25] = 44,
+ [2][1][RTW89_ETSI][0][25] = 6,
+ [2][1][RTW89_MKK][1][25] = 40,
+ [2][1][RTW89_MKK][0][25] = 2,
+ [2][1][RTW89_IC][1][25] = -16,
+ [2][1][RTW89_KCC][1][25] = -14,
+ [2][1][RTW89_KCC][0][25] = -14,
+ [2][1][RTW89_ACMA][1][25] = 44,
+ [2][1][RTW89_ACMA][0][25] = 6,
+ [2][1][RTW89_CHILE][1][25] = -16,
+ [2][1][RTW89_QATAR][1][25] = 44,
+ [2][1][RTW89_QATAR][0][25] = 6,
+ [2][1][RTW89_UK][1][25] = 44,
+ [2][1][RTW89_UK][0][25] = 6,
+ [2][1][RTW89_FCC][1][27] = -16,
+ [2][1][RTW89_FCC][2][27] = 54,
+ [2][1][RTW89_ETSI][1][27] = 44,
+ [2][1][RTW89_ETSI][0][27] = 6,
+ [2][1][RTW89_MKK][1][27] = 40,
+ [2][1][RTW89_MKK][0][27] = 2,
+ [2][1][RTW89_IC][1][27] = -16,
+ [2][1][RTW89_KCC][1][27] = -14,
+ [2][1][RTW89_KCC][0][27] = -14,
+ [2][1][RTW89_ACMA][1][27] = 44,
+ [2][1][RTW89_ACMA][0][27] = 6,
+ [2][1][RTW89_CHILE][1][27] = -16,
+ [2][1][RTW89_QATAR][1][27] = 44,
+ [2][1][RTW89_QATAR][0][27] = 6,
+ [2][1][RTW89_UK][1][27] = 44,
+ [2][1][RTW89_UK][0][27] = 6,
+ [2][1][RTW89_FCC][1][29] = -16,
+ [2][1][RTW89_FCC][2][29] = 54,
+ [2][1][RTW89_ETSI][1][29] = 44,
+ [2][1][RTW89_ETSI][0][29] = 6,
+ [2][1][RTW89_MKK][1][29] = 40,
+ [2][1][RTW89_MKK][0][29] = 2,
+ [2][1][RTW89_IC][1][29] = -16,
+ [2][1][RTW89_KCC][1][29] = -14,
+ [2][1][RTW89_KCC][0][29] = -14,
+ [2][1][RTW89_ACMA][1][29] = 44,
+ [2][1][RTW89_ACMA][0][29] = 6,
+ [2][1][RTW89_CHILE][1][29] = -16,
+ [2][1][RTW89_QATAR][1][29] = 44,
+ [2][1][RTW89_QATAR][0][29] = 6,
+ [2][1][RTW89_UK][1][29] = 44,
+ [2][1][RTW89_UK][0][29] = 6,
+ [2][1][RTW89_FCC][1][30] = -16,
+ [2][1][RTW89_FCC][2][30] = 54,
+ [2][1][RTW89_ETSI][1][30] = 44,
+ [2][1][RTW89_ETSI][0][30] = 6,
+ [2][1][RTW89_MKK][1][30] = 40,
+ [2][1][RTW89_MKK][0][30] = 2,
+ [2][1][RTW89_IC][1][30] = -16,
+ [2][1][RTW89_KCC][1][30] = -14,
+ [2][1][RTW89_KCC][0][30] = -14,
+ [2][1][RTW89_ACMA][1][30] = 44,
+ [2][1][RTW89_ACMA][0][30] = 6,
+ [2][1][RTW89_CHILE][1][30] = -16,
+ [2][1][RTW89_QATAR][1][30] = 44,
+ [2][1][RTW89_QATAR][0][30] = 6,
+ [2][1][RTW89_UK][1][30] = 44,
+ [2][1][RTW89_UK][0][30] = 6,
+ [2][1][RTW89_FCC][1][32] = -16,
+ [2][1][RTW89_FCC][2][32] = 54,
+ [2][1][RTW89_ETSI][1][32] = 44,
+ [2][1][RTW89_ETSI][0][32] = 6,
+ [2][1][RTW89_MKK][1][32] = 40,
+ [2][1][RTW89_MKK][0][32] = 2,
+ [2][1][RTW89_IC][1][32] = -16,
+ [2][1][RTW89_KCC][1][32] = -14,
+ [2][1][RTW89_KCC][0][32] = -14,
+ [2][1][RTW89_ACMA][1][32] = 44,
+ [2][1][RTW89_ACMA][0][32] = 6,
+ [2][1][RTW89_CHILE][1][32] = -16,
+ [2][1][RTW89_QATAR][1][32] = 44,
+ [2][1][RTW89_QATAR][0][32] = 6,
+ [2][1][RTW89_UK][1][32] = 44,
+ [2][1][RTW89_UK][0][32] = 6,
+ [2][1][RTW89_FCC][1][34] = -16,
+ [2][1][RTW89_FCC][2][34] = 54,
+ [2][1][RTW89_ETSI][1][34] = 44,
+ [2][1][RTW89_ETSI][0][34] = 6,
+ [2][1][RTW89_MKK][1][34] = 40,
+ [2][1][RTW89_MKK][0][34] = 2,
+ [2][1][RTW89_IC][1][34] = -16,
+ [2][1][RTW89_KCC][1][34] = -14,
+ [2][1][RTW89_KCC][0][34] = -14,
+ [2][1][RTW89_ACMA][1][34] = 44,
+ [2][1][RTW89_ACMA][0][34] = 6,
+ [2][1][RTW89_CHILE][1][34] = -16,
+ [2][1][RTW89_QATAR][1][34] = 44,
+ [2][1][RTW89_QATAR][0][34] = 6,
+ [2][1][RTW89_UK][1][34] = 44,
+ [2][1][RTW89_UK][0][34] = 6,
+ [2][1][RTW89_FCC][1][36] = -16,
+ [2][1][RTW89_FCC][2][36] = 54,
+ [2][1][RTW89_ETSI][1][36] = 44,
+ [2][1][RTW89_ETSI][0][36] = 6,
+ [2][1][RTW89_MKK][1][36] = 40,
+ [2][1][RTW89_MKK][0][36] = 2,
+ [2][1][RTW89_IC][1][36] = -16,
+ [2][1][RTW89_KCC][1][36] = -14,
+ [2][1][RTW89_KCC][0][36] = -14,
+ [2][1][RTW89_ACMA][1][36] = 44,
+ [2][1][RTW89_ACMA][0][36] = 6,
+ [2][1][RTW89_CHILE][1][36] = -16,
+ [2][1][RTW89_QATAR][1][36] = 44,
+ [2][1][RTW89_QATAR][0][36] = 6,
+ [2][1][RTW89_UK][1][36] = 44,
+ [2][1][RTW89_UK][0][36] = 6,
+ [2][1][RTW89_FCC][1][38] = -16,
+ [2][1][RTW89_FCC][2][38] = 54,
+ [2][1][RTW89_ETSI][1][38] = 44,
+ [2][1][RTW89_ETSI][0][38] = 6,
+ [2][1][RTW89_MKK][1][38] = 40,
+ [2][1][RTW89_MKK][0][38] = 2,
+ [2][1][RTW89_IC][1][38] = -16,
+ [2][1][RTW89_KCC][1][38] = -14,
+ [2][1][RTW89_KCC][0][38] = -14,
+ [2][1][RTW89_ACMA][1][38] = 44,
+ [2][1][RTW89_ACMA][0][38] = 6,
+ [2][1][RTW89_CHILE][1][38] = -16,
+ [2][1][RTW89_QATAR][1][38] = 44,
+ [2][1][RTW89_QATAR][0][38] = 6,
+ [2][1][RTW89_UK][1][38] = 44,
+ [2][1][RTW89_UK][0][38] = 6,
+ [2][1][RTW89_FCC][1][40] = -16,
+ [2][1][RTW89_FCC][2][40] = 54,
+ [2][1][RTW89_ETSI][1][40] = 44,
+ [2][1][RTW89_ETSI][0][40] = 6,
+ [2][1][RTW89_MKK][1][40] = 40,
+ [2][1][RTW89_MKK][0][40] = 2,
+ [2][1][RTW89_IC][1][40] = -16,
+ [2][1][RTW89_KCC][1][40] = -14,
+ [2][1][RTW89_KCC][0][40] = -14,
+ [2][1][RTW89_ACMA][1][40] = 44,
+ [2][1][RTW89_ACMA][0][40] = 6,
+ [2][1][RTW89_CHILE][1][40] = -16,
+ [2][1][RTW89_QATAR][1][40] = 44,
+ [2][1][RTW89_QATAR][0][40] = 6,
+ [2][1][RTW89_UK][1][40] = 44,
+ [2][1][RTW89_UK][0][40] = 6,
+ [2][1][RTW89_FCC][1][42] = -16,
+ [2][1][RTW89_FCC][2][42] = 54,
+ [2][1][RTW89_ETSI][1][42] = 44,
+ [2][1][RTW89_ETSI][0][42] = 6,
+ [2][1][RTW89_MKK][1][42] = 40,
+ [2][1][RTW89_MKK][0][42] = 2,
+ [2][1][RTW89_IC][1][42] = -16,
+ [2][1][RTW89_KCC][1][42] = -14,
+ [2][1][RTW89_KCC][0][42] = -14,
+ [2][1][RTW89_ACMA][1][42] = 44,
+ [2][1][RTW89_ACMA][0][42] = 6,
+ [2][1][RTW89_CHILE][1][42] = -16,
+ [2][1][RTW89_QATAR][1][42] = 44,
+ [2][1][RTW89_QATAR][0][42] = 6,
+ [2][1][RTW89_UK][1][42] = 44,
+ [2][1][RTW89_UK][0][42] = 6,
+ [2][1][RTW89_FCC][1][44] = -16,
+ [2][1][RTW89_FCC][2][44] = 54,
+ [2][1][RTW89_ETSI][1][44] = 44,
+ [2][1][RTW89_ETSI][0][44] = 6,
+ [2][1][RTW89_MKK][1][44] = 16,
+ [2][1][RTW89_MKK][0][44] = 2,
+ [2][1][RTW89_IC][1][44] = -16,
+ [2][1][RTW89_KCC][1][44] = -14,
+ [2][1][RTW89_KCC][0][44] = -14,
+ [2][1][RTW89_ACMA][1][44] = 44,
+ [2][1][RTW89_ACMA][0][44] = 6,
+ [2][1][RTW89_CHILE][1][44] = -16,
+ [2][1][RTW89_QATAR][1][44] = 44,
+ [2][1][RTW89_QATAR][0][44] = 6,
+ [2][1][RTW89_UK][1][44] = 44,
+ [2][1][RTW89_UK][0][44] = 6,
+ [2][1][RTW89_FCC][1][45] = -16,
+ [2][1][RTW89_FCC][2][45] = 127,
+ [2][1][RTW89_ETSI][1][45] = 127,
+ [2][1][RTW89_ETSI][0][45] = 127,
+ [2][1][RTW89_MKK][1][45] = 127,
+ [2][1][RTW89_MKK][0][45] = 127,
+ [2][1][RTW89_IC][1][45] = -16,
+ [2][1][RTW89_KCC][1][45] = -14,
+ [2][1][RTW89_KCC][0][45] = 127,
+ [2][1][RTW89_ACMA][1][45] = 127,
+ [2][1][RTW89_ACMA][0][45] = 127,
+ [2][1][RTW89_CHILE][1][45] = 127,
+ [2][1][RTW89_QATAR][1][45] = 127,
+ [2][1][RTW89_QATAR][0][45] = 127,
+ [2][1][RTW89_UK][1][45] = 127,
+ [2][1][RTW89_UK][0][45] = 127,
+ [2][1][RTW89_FCC][1][47] = -16,
+ [2][1][RTW89_FCC][2][47] = 127,
+ [2][1][RTW89_ETSI][1][47] = 127,
+ [2][1][RTW89_ETSI][0][47] = 127,
+ [2][1][RTW89_MKK][1][47] = 127,
+ [2][1][RTW89_MKK][0][47] = 127,
+ [2][1][RTW89_IC][1][47] = -16,
+ [2][1][RTW89_KCC][1][47] = -14,
+ [2][1][RTW89_KCC][0][47] = 127,
+ [2][1][RTW89_ACMA][1][47] = 127,
+ [2][1][RTW89_ACMA][0][47] = 127,
+ [2][1][RTW89_CHILE][1][47] = 127,
+ [2][1][RTW89_QATAR][1][47] = 127,
+ [2][1][RTW89_QATAR][0][47] = 127,
+ [2][1][RTW89_UK][1][47] = 127,
+ [2][1][RTW89_UK][0][47] = 127,
+ [2][1][RTW89_FCC][1][49] = -16,
+ [2][1][RTW89_FCC][2][49] = 127,
+ [2][1][RTW89_ETSI][1][49] = 127,
+ [2][1][RTW89_ETSI][0][49] = 127,
+ [2][1][RTW89_MKK][1][49] = 127,
+ [2][1][RTW89_MKK][0][49] = 127,
+ [2][1][RTW89_IC][1][49] = -16,
+ [2][1][RTW89_KCC][1][49] = -14,
+ [2][1][RTW89_KCC][0][49] = 127,
+ [2][1][RTW89_ACMA][1][49] = 127,
+ [2][1][RTW89_ACMA][0][49] = 127,
+ [2][1][RTW89_CHILE][1][49] = 127,
+ [2][1][RTW89_QATAR][1][49] = 127,
+ [2][1][RTW89_QATAR][0][49] = 127,
+ [2][1][RTW89_UK][1][49] = 127,
+ [2][1][RTW89_UK][0][49] = 127,
+ [2][1][RTW89_FCC][1][51] = -16,
+ [2][1][RTW89_FCC][2][51] = 127,
+ [2][1][RTW89_ETSI][1][51] = 127,
+ [2][1][RTW89_ETSI][0][51] = 127,
+ [2][1][RTW89_MKK][1][51] = 127,
+ [2][1][RTW89_MKK][0][51] = 127,
+ [2][1][RTW89_IC][1][51] = -16,
+ [2][1][RTW89_KCC][1][51] = -14,
+ [2][1][RTW89_KCC][0][51] = 127,
+ [2][1][RTW89_ACMA][1][51] = 127,
+ [2][1][RTW89_ACMA][0][51] = 127,
+ [2][1][RTW89_CHILE][1][51] = 127,
+ [2][1][RTW89_QATAR][1][51] = 127,
+ [2][1][RTW89_QATAR][0][51] = 127,
+ [2][1][RTW89_UK][1][51] = 127,
+ [2][1][RTW89_UK][0][51] = 127,
+ [2][1][RTW89_FCC][1][53] = -16,
+ [2][1][RTW89_FCC][2][53] = 127,
+ [2][1][RTW89_ETSI][1][53] = 127,
+ [2][1][RTW89_ETSI][0][53] = 127,
+ [2][1][RTW89_MKK][1][53] = 127,
+ [2][1][RTW89_MKK][0][53] = 127,
+ [2][1][RTW89_IC][1][53] = -16,
+ [2][1][RTW89_KCC][1][53] = -14,
+ [2][1][RTW89_KCC][0][53] = 127,
+ [2][1][RTW89_ACMA][1][53] = 127,
+ [2][1][RTW89_ACMA][0][53] = 127,
+ [2][1][RTW89_CHILE][1][53] = 127,
+ [2][1][RTW89_QATAR][1][53] = 127,
+ [2][1][RTW89_QATAR][0][53] = 127,
+ [2][1][RTW89_UK][1][53] = 127,
+ [2][1][RTW89_UK][0][53] = 127,
+ [2][1][RTW89_FCC][1][55] = -16,
+ [2][1][RTW89_FCC][2][55] = 54,
+ [2][1][RTW89_ETSI][1][55] = 127,
+ [2][1][RTW89_ETSI][0][55] = 127,
+ [2][1][RTW89_MKK][1][55] = 127,
+ [2][1][RTW89_MKK][0][55] = 127,
+ [2][1][RTW89_IC][1][55] = -16,
+ [2][1][RTW89_KCC][1][55] = -14,
+ [2][1][RTW89_KCC][0][55] = 127,
+ [2][1][RTW89_ACMA][1][55] = 127,
+ [2][1][RTW89_ACMA][0][55] = 127,
+ [2][1][RTW89_CHILE][1][55] = 127,
+ [2][1][RTW89_QATAR][1][55] = 127,
+ [2][1][RTW89_QATAR][0][55] = 127,
+ [2][1][RTW89_UK][1][55] = 127,
+ [2][1][RTW89_UK][0][55] = 127,
+ [2][1][RTW89_FCC][1][57] = -16,
+ [2][1][RTW89_FCC][2][57] = 54,
+ [2][1][RTW89_ETSI][1][57] = 127,
+ [2][1][RTW89_ETSI][0][57] = 127,
+ [2][1][RTW89_MKK][1][57] = 127,
+ [2][1][RTW89_MKK][0][57] = 127,
+ [2][1][RTW89_IC][1][57] = -16,
+ [2][1][RTW89_KCC][1][57] = -14,
+ [2][1][RTW89_KCC][0][57] = 127,
+ [2][1][RTW89_ACMA][1][57] = 127,
+ [2][1][RTW89_ACMA][0][57] = 127,
+ [2][1][RTW89_CHILE][1][57] = 127,
+ [2][1][RTW89_QATAR][1][57] = 127,
+ [2][1][RTW89_QATAR][0][57] = 127,
+ [2][1][RTW89_UK][1][57] = 127,
+ [2][1][RTW89_UK][0][57] = 127,
+ [2][1][RTW89_FCC][1][59] = -16,
+ [2][1][RTW89_FCC][2][59] = 54,
+ [2][1][RTW89_ETSI][1][59] = 127,
+ [2][1][RTW89_ETSI][0][59] = 127,
+ [2][1][RTW89_MKK][1][59] = 127,
+ [2][1][RTW89_MKK][0][59] = 127,
+ [2][1][RTW89_IC][1][59] = -16,
+ [2][1][RTW89_KCC][1][59] = -14,
+ [2][1][RTW89_KCC][0][59] = 127,
+ [2][1][RTW89_ACMA][1][59] = 127,
+ [2][1][RTW89_ACMA][0][59] = 127,
+ [2][1][RTW89_CHILE][1][59] = 127,
+ [2][1][RTW89_QATAR][1][59] = 127,
+ [2][1][RTW89_QATAR][0][59] = 127,
+ [2][1][RTW89_UK][1][59] = 127,
+ [2][1][RTW89_UK][0][59] = 127,
+ [2][1][RTW89_FCC][1][60] = -16,
+ [2][1][RTW89_FCC][2][60] = 54,
+ [2][1][RTW89_ETSI][1][60] = 127,
+ [2][1][RTW89_ETSI][0][60] = 127,
+ [2][1][RTW89_MKK][1][60] = 127,
+ [2][1][RTW89_MKK][0][60] = 127,
+ [2][1][RTW89_IC][1][60] = -16,
+ [2][1][RTW89_KCC][1][60] = -14,
+ [2][1][RTW89_KCC][0][60] = 127,
+ [2][1][RTW89_ACMA][1][60] = 127,
+ [2][1][RTW89_ACMA][0][60] = 127,
+ [2][1][RTW89_CHILE][1][60] = 127,
+ [2][1][RTW89_QATAR][1][60] = 127,
+ [2][1][RTW89_QATAR][0][60] = 127,
+ [2][1][RTW89_UK][1][60] = 127,
+ [2][1][RTW89_UK][0][60] = 127,
+ [2][1][RTW89_FCC][1][62] = -16,
+ [2][1][RTW89_FCC][2][62] = 54,
+ [2][1][RTW89_ETSI][1][62] = 127,
+ [2][1][RTW89_ETSI][0][62] = 127,
+ [2][1][RTW89_MKK][1][62] = 127,
+ [2][1][RTW89_MKK][0][62] = 127,
+ [2][1][RTW89_IC][1][62] = -16,
+ [2][1][RTW89_KCC][1][62] = -14,
+ [2][1][RTW89_KCC][0][62] = 127,
+ [2][1][RTW89_ACMA][1][62] = 127,
+ [2][1][RTW89_ACMA][0][62] = 127,
+ [2][1][RTW89_CHILE][1][62] = 127,
+ [2][1][RTW89_QATAR][1][62] = 127,
+ [2][1][RTW89_QATAR][0][62] = 127,
+ [2][1][RTW89_UK][1][62] = 127,
+ [2][1][RTW89_UK][0][62] = 127,
+ [2][1][RTW89_FCC][1][64] = -16,
+ [2][1][RTW89_FCC][2][64] = 54,
+ [2][1][RTW89_ETSI][1][64] = 127,
+ [2][1][RTW89_ETSI][0][64] = 127,
+ [2][1][RTW89_MKK][1][64] = 127,
+ [2][1][RTW89_MKK][0][64] = 127,
+ [2][1][RTW89_IC][1][64] = -16,
+ [2][1][RTW89_KCC][1][64] = -14,
+ [2][1][RTW89_KCC][0][64] = 127,
+ [2][1][RTW89_ACMA][1][64] = 127,
+ [2][1][RTW89_ACMA][0][64] = 127,
+ [2][1][RTW89_CHILE][1][64] = 127,
+ [2][1][RTW89_QATAR][1][64] = 127,
+ [2][1][RTW89_QATAR][0][64] = 127,
+ [2][1][RTW89_UK][1][64] = 127,
+ [2][1][RTW89_UK][0][64] = 127,
+ [2][1][RTW89_FCC][1][66] = -16,
+ [2][1][RTW89_FCC][2][66] = 54,
+ [2][1][RTW89_ETSI][1][66] = 127,
+ [2][1][RTW89_ETSI][0][66] = 127,
+ [2][1][RTW89_MKK][1][66] = 127,
+ [2][1][RTW89_MKK][0][66] = 127,
+ [2][1][RTW89_IC][1][66] = -16,
+ [2][1][RTW89_KCC][1][66] = -14,
+ [2][1][RTW89_KCC][0][66] = 127,
+ [2][1][RTW89_ACMA][1][66] = 127,
+ [2][1][RTW89_ACMA][0][66] = 127,
+ [2][1][RTW89_CHILE][1][66] = 127,
+ [2][1][RTW89_QATAR][1][66] = 127,
+ [2][1][RTW89_QATAR][0][66] = 127,
+ [2][1][RTW89_UK][1][66] = 127,
+ [2][1][RTW89_UK][0][66] = 127,
+ [2][1][RTW89_FCC][1][68] = -16,
+ [2][1][RTW89_FCC][2][68] = 54,
+ [2][1][RTW89_ETSI][1][68] = 127,
+ [2][1][RTW89_ETSI][0][68] = 127,
+ [2][1][RTW89_MKK][1][68] = 127,
+ [2][1][RTW89_MKK][0][68] = 127,
+ [2][1][RTW89_IC][1][68] = -16,
+ [2][1][RTW89_KCC][1][68] = -14,
+ [2][1][RTW89_KCC][0][68] = 127,
+ [2][1][RTW89_ACMA][1][68] = 127,
+ [2][1][RTW89_ACMA][0][68] = 127,
+ [2][1][RTW89_CHILE][1][68] = 127,
+ [2][1][RTW89_QATAR][1][68] = 127,
+ [2][1][RTW89_QATAR][0][68] = 127,
+ [2][1][RTW89_UK][1][68] = 127,
+ [2][1][RTW89_UK][0][68] = 127,
+ [2][1][RTW89_FCC][1][70] = -16,
+ [2][1][RTW89_FCC][2][70] = 56,
+ [2][1][RTW89_ETSI][1][70] = 127,
+ [2][1][RTW89_ETSI][0][70] = 127,
+ [2][1][RTW89_MKK][1][70] = 127,
+ [2][1][RTW89_MKK][0][70] = 127,
+ [2][1][RTW89_IC][1][70] = -16,
+ [2][1][RTW89_KCC][1][70] = -14,
+ [2][1][RTW89_KCC][0][70] = 127,
+ [2][1][RTW89_ACMA][1][70] = 127,
+ [2][1][RTW89_ACMA][0][70] = 127,
+ [2][1][RTW89_CHILE][1][70] = 127,
+ [2][1][RTW89_QATAR][1][70] = 127,
+ [2][1][RTW89_QATAR][0][70] = 127,
+ [2][1][RTW89_UK][1][70] = 127,
+ [2][1][RTW89_UK][0][70] = 127,
+ [2][1][RTW89_FCC][1][72] = -16,
+ [2][1][RTW89_FCC][2][72] = 56,
+ [2][1][RTW89_ETSI][1][72] = 127,
+ [2][1][RTW89_ETSI][0][72] = 127,
+ [2][1][RTW89_MKK][1][72] = 127,
+ [2][1][RTW89_MKK][0][72] = 127,
+ [2][1][RTW89_IC][1][72] = -16,
+ [2][1][RTW89_KCC][1][72] = -14,
+ [2][1][RTW89_KCC][0][72] = 127,
+ [2][1][RTW89_ACMA][1][72] = 127,
+ [2][1][RTW89_ACMA][0][72] = 127,
+ [2][1][RTW89_CHILE][1][72] = 127,
+ [2][1][RTW89_QATAR][1][72] = 127,
+ [2][1][RTW89_QATAR][0][72] = 127,
+ [2][1][RTW89_UK][1][72] = 127,
+ [2][1][RTW89_UK][0][72] = 127,
+ [2][1][RTW89_FCC][1][74] = -16,
+ [2][1][RTW89_FCC][2][74] = 56,
+ [2][1][RTW89_ETSI][1][74] = 127,
+ [2][1][RTW89_ETSI][0][74] = 127,
+ [2][1][RTW89_MKK][1][74] = 127,
+ [2][1][RTW89_MKK][0][74] = 127,
+ [2][1][RTW89_IC][1][74] = -16,
+ [2][1][RTW89_KCC][1][74] = -14,
+ [2][1][RTW89_KCC][0][74] = 127,
+ [2][1][RTW89_ACMA][1][74] = 127,
+ [2][1][RTW89_ACMA][0][74] = 127,
+ [2][1][RTW89_CHILE][1][74] = 127,
+ [2][1][RTW89_QATAR][1][74] = 127,
+ [2][1][RTW89_QATAR][0][74] = 127,
+ [2][1][RTW89_UK][1][74] = 127,
+ [2][1][RTW89_UK][0][74] = 127,
+ [2][1][RTW89_FCC][1][75] = -16,
+ [2][1][RTW89_FCC][2][75] = 56,
+ [2][1][RTW89_ETSI][1][75] = 127,
+ [2][1][RTW89_ETSI][0][75] = 127,
+ [2][1][RTW89_MKK][1][75] = 127,
+ [2][1][RTW89_MKK][0][75] = 127,
+ [2][1][RTW89_IC][1][75] = -16,
+ [2][1][RTW89_KCC][1][75] = -14,
+ [2][1][RTW89_KCC][0][75] = 127,
+ [2][1][RTW89_ACMA][1][75] = 127,
+ [2][1][RTW89_ACMA][0][75] = 127,
+ [2][1][RTW89_CHILE][1][75] = 127,
+ [2][1][RTW89_QATAR][1][75] = 127,
+ [2][1][RTW89_QATAR][0][75] = 127,
+ [2][1][RTW89_UK][1][75] = 127,
+ [2][1][RTW89_UK][0][75] = 127,
+ [2][1][RTW89_FCC][1][77] = -16,
+ [2][1][RTW89_FCC][2][77] = 56,
+ [2][1][RTW89_ETSI][1][77] = 127,
+ [2][1][RTW89_ETSI][0][77] = 127,
+ [2][1][RTW89_MKK][1][77] = 127,
+ [2][1][RTW89_MKK][0][77] = 127,
+ [2][1][RTW89_IC][1][77] = -16,
+ [2][1][RTW89_KCC][1][77] = -14,
+ [2][1][RTW89_KCC][0][77] = 127,
+ [2][1][RTW89_ACMA][1][77] = 127,
+ [2][1][RTW89_ACMA][0][77] = 127,
+ [2][1][RTW89_CHILE][1][77] = 127,
+ [2][1][RTW89_QATAR][1][77] = 127,
+ [2][1][RTW89_QATAR][0][77] = 127,
+ [2][1][RTW89_UK][1][77] = 127,
+ [2][1][RTW89_UK][0][77] = 127,
+ [2][1][RTW89_FCC][1][79] = -16,
+ [2][1][RTW89_FCC][2][79] = 56,
+ [2][1][RTW89_ETSI][1][79] = 127,
+ [2][1][RTW89_ETSI][0][79] = 127,
+ [2][1][RTW89_MKK][1][79] = 127,
+ [2][1][RTW89_MKK][0][79] = 127,
+ [2][1][RTW89_IC][1][79] = -16,
+ [2][1][RTW89_KCC][1][79] = -14,
+ [2][1][RTW89_KCC][0][79] = 127,
+ [2][1][RTW89_ACMA][1][79] = 127,
+ [2][1][RTW89_ACMA][0][79] = 127,
+ [2][1][RTW89_CHILE][1][79] = 127,
+ [2][1][RTW89_QATAR][1][79] = 127,
+ [2][1][RTW89_QATAR][0][79] = 127,
+ [2][1][RTW89_UK][1][79] = 127,
+ [2][1][RTW89_UK][0][79] = 127,
+ [2][1][RTW89_FCC][1][81] = -16,
+ [2][1][RTW89_FCC][2][81] = 56,
+ [2][1][RTW89_ETSI][1][81] = 127,
+ [2][1][RTW89_ETSI][0][81] = 127,
+ [2][1][RTW89_MKK][1][81] = 127,
+ [2][1][RTW89_MKK][0][81] = 127,
+ [2][1][RTW89_IC][1][81] = -16,
+ [2][1][RTW89_KCC][1][81] = -14,
+ [2][1][RTW89_KCC][0][81] = 127,
+ [2][1][RTW89_ACMA][1][81] = 127,
+ [2][1][RTW89_ACMA][0][81] = 127,
+ [2][1][RTW89_CHILE][1][81] = 127,
+ [2][1][RTW89_QATAR][1][81] = 127,
+ [2][1][RTW89_QATAR][0][81] = 127,
+ [2][1][RTW89_UK][1][81] = 127,
+ [2][1][RTW89_UK][0][81] = 127,
+ [2][1][RTW89_FCC][1][83] = -16,
+ [2][1][RTW89_FCC][2][83] = 56,
+ [2][1][RTW89_ETSI][1][83] = 127,
+ [2][1][RTW89_ETSI][0][83] = 127,
+ [2][1][RTW89_MKK][1][83] = 127,
+ [2][1][RTW89_MKK][0][83] = 127,
+ [2][1][RTW89_IC][1][83] = -16,
+ [2][1][RTW89_KCC][1][83] = -14,
+ [2][1][RTW89_KCC][0][83] = 127,
+ [2][1][RTW89_ACMA][1][83] = 127,
+ [2][1][RTW89_ACMA][0][83] = 127,
+ [2][1][RTW89_CHILE][1][83] = 127,
+ [2][1][RTW89_QATAR][1][83] = 127,
+ [2][1][RTW89_QATAR][0][83] = 127,
+ [2][1][RTW89_UK][1][83] = 127,
+ [2][1][RTW89_UK][0][83] = 127,
+ [2][1][RTW89_FCC][1][85] = -18,
+ [2][1][RTW89_FCC][2][85] = 56,
+ [2][1][RTW89_ETSI][1][85] = 127,
+ [2][1][RTW89_ETSI][0][85] = 127,
+ [2][1][RTW89_MKK][1][85] = 127,
+ [2][1][RTW89_MKK][0][85] = 127,
+ [2][1][RTW89_IC][1][85] = -18,
+ [2][1][RTW89_KCC][1][85] = -14,
+ [2][1][RTW89_KCC][0][85] = 127,
+ [2][1][RTW89_ACMA][1][85] = 127,
+ [2][1][RTW89_ACMA][0][85] = 127,
+ [2][1][RTW89_CHILE][1][85] = 127,
+ [2][1][RTW89_QATAR][1][85] = 127,
+ [2][1][RTW89_QATAR][0][85] = 127,
+ [2][1][RTW89_UK][1][85] = 127,
+ [2][1][RTW89_UK][0][85] = 127,
+ [2][1][RTW89_FCC][1][87] = -16,
+ [2][1][RTW89_FCC][2][87] = 127,
+ [2][1][RTW89_ETSI][1][87] = 127,
+ [2][1][RTW89_ETSI][0][87] = 127,
+ [2][1][RTW89_MKK][1][87] = 127,
+ [2][1][RTW89_MKK][0][87] = 127,
+ [2][1][RTW89_IC][1][87] = -16,
+ [2][1][RTW89_KCC][1][87] = -14,
+ [2][1][RTW89_KCC][0][87] = 127,
+ [2][1][RTW89_ACMA][1][87] = 127,
+ [2][1][RTW89_ACMA][0][87] = 127,
+ [2][1][RTW89_CHILE][1][87] = 127,
+ [2][1][RTW89_QATAR][1][87] = 127,
+ [2][1][RTW89_QATAR][0][87] = 127,
+ [2][1][RTW89_UK][1][87] = 127,
+ [2][1][RTW89_UK][0][87] = 127,
+ [2][1][RTW89_FCC][1][89] = -16,
+ [2][1][RTW89_FCC][2][89] = 127,
+ [2][1][RTW89_ETSI][1][89] = 127,
+ [2][1][RTW89_ETSI][0][89] = 127,
+ [2][1][RTW89_MKK][1][89] = 127,
+ [2][1][RTW89_MKK][0][89] = 127,
+ [2][1][RTW89_IC][1][89] = -16,
+ [2][1][RTW89_KCC][1][89] = -14,
+ [2][1][RTW89_KCC][0][89] = 127,
+ [2][1][RTW89_ACMA][1][89] = 127,
+ [2][1][RTW89_ACMA][0][89] = 127,
+ [2][1][RTW89_CHILE][1][89] = 127,
+ [2][1][RTW89_QATAR][1][89] = 127,
+ [2][1][RTW89_QATAR][0][89] = 127,
+ [2][1][RTW89_UK][1][89] = 127,
+ [2][1][RTW89_UK][0][89] = 127,
+ [2][1][RTW89_FCC][1][90] = -16,
+ [2][1][RTW89_FCC][2][90] = 127,
+ [2][1][RTW89_ETSI][1][90] = 127,
+ [2][1][RTW89_ETSI][0][90] = 127,
+ [2][1][RTW89_MKK][1][90] = 127,
+ [2][1][RTW89_MKK][0][90] = 127,
+ [2][1][RTW89_IC][1][90] = -16,
+ [2][1][RTW89_KCC][1][90] = -14,
+ [2][1][RTW89_KCC][0][90] = 127,
+ [2][1][RTW89_ACMA][1][90] = 127,
+ [2][1][RTW89_ACMA][0][90] = 127,
+ [2][1][RTW89_CHILE][1][90] = 127,
+ [2][1][RTW89_QATAR][1][90] = 127,
+ [2][1][RTW89_QATAR][0][90] = 127,
+ [2][1][RTW89_UK][1][90] = 127,
+ [2][1][RTW89_UK][0][90] = 127,
+ [2][1][RTW89_FCC][1][92] = -16,
+ [2][1][RTW89_FCC][2][92] = 127,
+ [2][1][RTW89_ETSI][1][92] = 127,
+ [2][1][RTW89_ETSI][0][92] = 127,
+ [2][1][RTW89_MKK][1][92] = 127,
+ [2][1][RTW89_MKK][0][92] = 127,
+ [2][1][RTW89_IC][1][92] = -16,
+ [2][1][RTW89_KCC][1][92] = -14,
+ [2][1][RTW89_KCC][0][92] = 127,
+ [2][1][RTW89_ACMA][1][92] = 127,
+ [2][1][RTW89_ACMA][0][92] = 127,
+ [2][1][RTW89_CHILE][1][92] = 127,
+ [2][1][RTW89_QATAR][1][92] = 127,
+ [2][1][RTW89_QATAR][0][92] = 127,
+ [2][1][RTW89_UK][1][92] = 127,
+ [2][1][RTW89_UK][0][92] = 127,
+ [2][1][RTW89_FCC][1][94] = -16,
+ [2][1][RTW89_FCC][2][94] = 127,
+ [2][1][RTW89_ETSI][1][94] = 127,
+ [2][1][RTW89_ETSI][0][94] = 127,
+ [2][1][RTW89_MKK][1][94] = 127,
+ [2][1][RTW89_MKK][0][94] = 127,
+ [2][1][RTW89_IC][1][94] = -16,
+ [2][1][RTW89_KCC][1][94] = -14,
+ [2][1][RTW89_KCC][0][94] = 127,
+ [2][1][RTW89_ACMA][1][94] = 127,
+ [2][1][RTW89_ACMA][0][94] = 127,
+ [2][1][RTW89_CHILE][1][94] = 127,
+ [2][1][RTW89_QATAR][1][94] = 127,
+ [2][1][RTW89_QATAR][0][94] = 127,
+ [2][1][RTW89_UK][1][94] = 127,
+ [2][1][RTW89_UK][0][94] = 127,
+ [2][1][RTW89_FCC][1][96] = -16,
+ [2][1][RTW89_FCC][2][96] = 127,
+ [2][1][RTW89_ETSI][1][96] = 127,
+ [2][1][RTW89_ETSI][0][96] = 127,
+ [2][1][RTW89_MKK][1][96] = 127,
+ [2][1][RTW89_MKK][0][96] = 127,
+ [2][1][RTW89_IC][1][96] = -16,
+ [2][1][RTW89_KCC][1][96] = -14,
+ [2][1][RTW89_KCC][0][96] = 127,
+ [2][1][RTW89_ACMA][1][96] = 127,
+ [2][1][RTW89_ACMA][0][96] = 127,
+ [2][1][RTW89_CHILE][1][96] = 127,
+ [2][1][RTW89_QATAR][1][96] = 127,
+ [2][1][RTW89_QATAR][0][96] = 127,
+ [2][1][RTW89_UK][1][96] = 127,
+ [2][1][RTW89_UK][0][96] = 127,
+ [2][1][RTW89_FCC][1][98] = -16,
+ [2][1][RTW89_FCC][2][98] = 127,
+ [2][1][RTW89_ETSI][1][98] = 127,
+ [2][1][RTW89_ETSI][0][98] = 127,
+ [2][1][RTW89_MKK][1][98] = 127,
+ [2][1][RTW89_MKK][0][98] = 127,
+ [2][1][RTW89_IC][1][98] = -16,
+ [2][1][RTW89_KCC][1][98] = -14,
+ [2][1][RTW89_KCC][0][98] = 127,
+ [2][1][RTW89_ACMA][1][98] = 127,
+ [2][1][RTW89_ACMA][0][98] = 127,
+ [2][1][RTW89_CHILE][1][98] = 127,
+ [2][1][RTW89_QATAR][1][98] = 127,
+ [2][1][RTW89_QATAR][0][98] = 127,
+ [2][1][RTW89_UK][1][98] = 127,
+ [2][1][RTW89_UK][0][98] = 127,
+ [2][1][RTW89_FCC][1][100] = -16,
+ [2][1][RTW89_FCC][2][100] = 127,
+ [2][1][RTW89_ETSI][1][100] = 127,
+ [2][1][RTW89_ETSI][0][100] = 127,
+ [2][1][RTW89_MKK][1][100] = 127,
+ [2][1][RTW89_MKK][0][100] = 127,
+ [2][1][RTW89_IC][1][100] = -16,
+ [2][1][RTW89_KCC][1][100] = -14,
+ [2][1][RTW89_KCC][0][100] = 127,
+ [2][1][RTW89_ACMA][1][100] = 127,
+ [2][1][RTW89_ACMA][0][100] = 127,
+ [2][1][RTW89_CHILE][1][100] = 127,
+ [2][1][RTW89_QATAR][1][100] = 127,
+ [2][1][RTW89_QATAR][0][100] = 127,
+ [2][1][RTW89_UK][1][100] = 127,
+ [2][1][RTW89_UK][0][100] = 127,
+ [2][1][RTW89_FCC][1][102] = -16,
+ [2][1][RTW89_FCC][2][102] = 127,
+ [2][1][RTW89_ETSI][1][102] = 127,
+ [2][1][RTW89_ETSI][0][102] = 127,
+ [2][1][RTW89_MKK][1][102] = 127,
+ [2][1][RTW89_MKK][0][102] = 127,
+ [2][1][RTW89_IC][1][102] = -16,
+ [2][1][RTW89_KCC][1][102] = -14,
+ [2][1][RTW89_KCC][0][102] = 127,
+ [2][1][RTW89_ACMA][1][102] = 127,
+ [2][1][RTW89_ACMA][0][102] = 127,
+ [2][1][RTW89_CHILE][1][102] = 127,
+ [2][1][RTW89_QATAR][1][102] = 127,
+ [2][1][RTW89_QATAR][0][102] = 127,
+ [2][1][RTW89_UK][1][102] = 127,
+ [2][1][RTW89_UK][0][102] = 127,
+ [2][1][RTW89_FCC][1][104] = -16,
+ [2][1][RTW89_FCC][2][104] = 127,
+ [2][1][RTW89_ETSI][1][104] = 127,
+ [2][1][RTW89_ETSI][0][104] = 127,
+ [2][1][RTW89_MKK][1][104] = 127,
+ [2][1][RTW89_MKK][0][104] = 127,
+ [2][1][RTW89_IC][1][104] = -16,
+ [2][1][RTW89_KCC][1][104] = -14,
+ [2][1][RTW89_KCC][0][104] = 127,
+ [2][1][RTW89_ACMA][1][104] = 127,
+ [2][1][RTW89_ACMA][0][104] = 127,
+ [2][1][RTW89_CHILE][1][104] = 127,
+ [2][1][RTW89_QATAR][1][104] = 127,
+ [2][1][RTW89_QATAR][0][104] = 127,
+ [2][1][RTW89_UK][1][104] = 127,
+ [2][1][RTW89_UK][0][104] = 127,
+ [2][1][RTW89_FCC][1][105] = -16,
+ [2][1][RTW89_FCC][2][105] = 127,
+ [2][1][RTW89_ETSI][1][105] = 127,
+ [2][1][RTW89_ETSI][0][105] = 127,
+ [2][1][RTW89_MKK][1][105] = 127,
+ [2][1][RTW89_MKK][0][105] = 127,
+ [2][1][RTW89_IC][1][105] = -16,
+ [2][1][RTW89_KCC][1][105] = -14,
+ [2][1][RTW89_KCC][0][105] = 127,
+ [2][1][RTW89_ACMA][1][105] = 127,
+ [2][1][RTW89_ACMA][0][105] = 127,
+ [2][1][RTW89_CHILE][1][105] = 127,
+ [2][1][RTW89_QATAR][1][105] = 127,
+ [2][1][RTW89_QATAR][0][105] = 127,
+ [2][1][RTW89_UK][1][105] = 127,
+ [2][1][RTW89_UK][0][105] = 127,
+ [2][1][RTW89_FCC][1][107] = -12,
+ [2][1][RTW89_FCC][2][107] = 127,
+ [2][1][RTW89_ETSI][1][107] = 127,
+ [2][1][RTW89_ETSI][0][107] = 127,
+ [2][1][RTW89_MKK][1][107] = 127,
+ [2][1][RTW89_MKK][0][107] = 127,
+ [2][1][RTW89_IC][1][107] = -12,
+ [2][1][RTW89_KCC][1][107] = -14,
+ [2][1][RTW89_KCC][0][107] = 127,
+ [2][1][RTW89_ACMA][1][107] = 127,
+ [2][1][RTW89_ACMA][0][107] = 127,
+ [2][1][RTW89_CHILE][1][107] = 127,
+ [2][1][RTW89_QATAR][1][107] = 127,
+ [2][1][RTW89_QATAR][0][107] = 127,
+ [2][1][RTW89_UK][1][107] = 127,
+ [2][1][RTW89_UK][0][107] = 127,
+ [2][1][RTW89_FCC][1][109] = -10,
+ [2][1][RTW89_FCC][2][109] = 127,
+ [2][1][RTW89_ETSI][1][109] = 127,
+ [2][1][RTW89_ETSI][0][109] = 127,
+ [2][1][RTW89_MKK][1][109] = 127,
+ [2][1][RTW89_MKK][0][109] = 127,
+ [2][1][RTW89_IC][1][109] = -10,
+ [2][1][RTW89_KCC][1][109] = 127,
+ [2][1][RTW89_KCC][0][109] = 127,
+ [2][1][RTW89_ACMA][1][109] = 127,
+ [2][1][RTW89_ACMA][0][109] = 127,
+ [2][1][RTW89_CHILE][1][109] = 127,
+ [2][1][RTW89_QATAR][1][109] = 127,
+ [2][1][RTW89_QATAR][0][109] = 127,
+ [2][1][RTW89_UK][1][109] = 127,
+ [2][1][RTW89_UK][0][109] = 127,
+ [2][1][RTW89_FCC][1][111] = 127,
+ [2][1][RTW89_FCC][2][111] = 127,
+ [2][1][RTW89_ETSI][1][111] = 127,
+ [2][1][RTW89_ETSI][0][111] = 127,
+ [2][1][RTW89_MKK][1][111] = 127,
+ [2][1][RTW89_MKK][0][111] = 127,
+ [2][1][RTW89_IC][1][111] = 127,
+ [2][1][RTW89_KCC][1][111] = 127,
+ [2][1][RTW89_KCC][0][111] = 127,
+ [2][1][RTW89_ACMA][1][111] = 127,
+ [2][1][RTW89_ACMA][0][111] = 127,
+ [2][1][RTW89_CHILE][1][111] = 127,
+ [2][1][RTW89_QATAR][1][111] = 127,
+ [2][1][RTW89_QATAR][0][111] = 127,
+ [2][1][RTW89_UK][1][111] = 127,
+ [2][1][RTW89_UK][0][111] = 127,
+ [2][1][RTW89_FCC][1][113] = 127,
+ [2][1][RTW89_FCC][2][113] = 127,
+ [2][1][RTW89_ETSI][1][113] = 127,
+ [2][1][RTW89_ETSI][0][113] = 127,
+ [2][1][RTW89_MKK][1][113] = 127,
+ [2][1][RTW89_MKK][0][113] = 127,
+ [2][1][RTW89_IC][1][113] = 127,
+ [2][1][RTW89_KCC][1][113] = 127,
+ [2][1][RTW89_KCC][0][113] = 127,
+ [2][1][RTW89_ACMA][1][113] = 127,
+ [2][1][RTW89_ACMA][0][113] = 127,
+ [2][1][RTW89_CHILE][1][113] = 127,
+ [2][1][RTW89_QATAR][1][113] = 127,
+ [2][1][RTW89_QATAR][0][113] = 127,
+ [2][1][RTW89_UK][1][113] = 127,
+ [2][1][RTW89_UK][0][113] = 127,
+ [2][1][RTW89_FCC][1][115] = 127,
+ [2][1][RTW89_FCC][2][115] = 127,
+ [2][1][RTW89_ETSI][1][115] = 127,
+ [2][1][RTW89_ETSI][0][115] = 127,
+ [2][1][RTW89_MKK][1][115] = 127,
+ [2][1][RTW89_MKK][0][115] = 127,
+ [2][1][RTW89_IC][1][115] = 127,
+ [2][1][RTW89_KCC][1][115] = 127,
+ [2][1][RTW89_KCC][0][115] = 127,
+ [2][1][RTW89_ACMA][1][115] = 127,
+ [2][1][RTW89_ACMA][0][115] = 127,
+ [2][1][RTW89_CHILE][1][115] = 127,
+ [2][1][RTW89_QATAR][1][115] = 127,
+ [2][1][RTW89_QATAR][0][115] = 127,
+ [2][1][RTW89_UK][1][115] = 127,
+ [2][1][RTW89_UK][0][115] = 127,
+ [2][1][RTW89_FCC][1][117] = 127,
+ [2][1][RTW89_FCC][2][117] = 127,
+ [2][1][RTW89_ETSI][1][117] = 127,
+ [2][1][RTW89_ETSI][0][117] = 127,
+ [2][1][RTW89_MKK][1][117] = 127,
+ [2][1][RTW89_MKK][0][117] = 127,
+ [2][1][RTW89_IC][1][117] = 127,
+ [2][1][RTW89_KCC][1][117] = 127,
+ [2][1][RTW89_KCC][0][117] = 127,
+ [2][1][RTW89_ACMA][1][117] = 127,
+ [2][1][RTW89_ACMA][0][117] = 127,
+ [2][1][RTW89_CHILE][1][117] = 127,
+ [2][1][RTW89_QATAR][1][117] = 127,
+ [2][1][RTW89_QATAR][0][117] = 127,
+ [2][1][RTW89_UK][1][117] = 127,
+ [2][1][RTW89_UK][0][117] = 127,
+ [2][1][RTW89_FCC][1][119] = 127,
+ [2][1][RTW89_FCC][2][119] = 127,
+ [2][1][RTW89_ETSI][1][119] = 127,
+ [2][1][RTW89_ETSI][0][119] = 127,
+ [2][1][RTW89_MKK][1][119] = 127,
+ [2][1][RTW89_MKK][0][119] = 127,
+ [2][1][RTW89_IC][1][119] = 127,
+ [2][1][RTW89_KCC][1][119] = 127,
+ [2][1][RTW89_KCC][0][119] = 127,
+ [2][1][RTW89_ACMA][1][119] = 127,
+ [2][1][RTW89_ACMA][0][119] = 127,
+ [2][1][RTW89_CHILE][1][119] = 127,
+ [2][1][RTW89_QATAR][1][119] = 127,
+ [2][1][RTW89_QATAR][0][119] = 127,
+ [2][1][RTW89_UK][1][119] = 127,
+ [2][1][RTW89_UK][0][119] = 127,
};
const struct rtw89_phy_table rtw89_8852c_phy_bb_table = {
diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852c_table.h b/drivers/net/wireless/realtek/rtw89/rtw8852c_table.h
index 6da1849fb1fa..3eb0c4995174 100644
--- a/drivers/net/wireless/realtek/rtw89/rtw8852c_table.h
+++ b/drivers/net/wireless/realtek/rtw89/rtw8852c_table.h
@@ -15,7 +15,7 @@ extern const struct rtw89_phy_table rtw89_8852c_phy_nctl_table;
extern const struct rtw89_txpwr_table rtw89_8852c_byr_table;
extern const struct rtw89_phy_tssi_dbw_table rtw89_8852c_tssi_dbw_table;
extern const struct rtw89_txpwr_track_cfg rtw89_8852c_trk_cfg;
-extern const u8 rtw89_8852c_tx_shape[RTW89_BAND_MAX][RTW89_RS_TX_SHAPE_NUM]
+extern const u8 rtw89_8852c_tx_shape[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM]
[RTW89_REGD_NUM];
extern const struct rtw89_rfe_parms rtw89_8852c_dflt_parms;
diff --git a/drivers/net/wireless/realtek/rtw89/ser.c b/drivers/net/wireless/realtek/rtw89/ser.c
index 9e9f6947e7f1..0462ba693f6f 100644
--- a/drivers/net/wireless/realtek/rtw89/ser.c
+++ b/drivers/net/wireless/realtek/rtw89/ser.c
@@ -20,12 +20,14 @@ enum ser_evt {
SER_EV_NONE,
SER_EV_STATE_IN,
SER_EV_STATE_OUT,
+ SER_EV_L1_RESET_PREPARE, /* pre-M0 */
SER_EV_L1_RESET, /* M1 */
SER_EV_DO_RECOVERY, /* M3 */
SER_EV_MAC_RESET_DONE, /* M5 */
SER_EV_L2_RESET,
SER_EV_L2_RECFG_DONE,
SER_EV_L2_RECFG_TIMEOUT,
+ SER_EV_M1_TIMEOUT,
SER_EV_M3_TIMEOUT,
SER_EV_FW_M5_TIMEOUT,
SER_EV_L0_RESET,
@@ -34,6 +36,7 @@ enum ser_evt {
enum ser_state {
SER_IDLE_ST,
+ SER_L1_RESET_PRE_ST,
SER_RESET_TRX_ST,
SER_DO_HCI_ST,
SER_L2_RESET_ST,
@@ -300,6 +303,7 @@ static void ser_reset_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
rtw89_core_release_bit_map(rtwdev->hw_port, rtwvif->port);
rtwvif->net_type = RTW89_NET_TYPE_NO_LINK;
rtwvif->trigger = false;
+ rtwvif->tdls_peer = 0;
}
static void ser_sta_deinit_cam_iter(void *data, struct ieee80211_sta *sta)
@@ -338,6 +342,8 @@ static void ser_reset_mac_binding(struct rtw89_dev *rtwdev)
rtw89_core_release_all_bits_map(rtwdev->mac_id_map, RTW89_MAX_MAC_ID_NUM);
rtw89_for_each_rtwvif(rtwdev, rtwvif)
ser_reset_vif(rtwdev, rtwvif);
+
+ rtwdev->total_sta_assoc = 0;
}
/* hal function */
@@ -374,6 +380,13 @@ static int hal_stop_dma(struct rtw89_ser *ser)
return ret;
}
+static void hal_send_post_m0_event(struct rtw89_ser *ser)
+{
+ struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
+
+ rtw89_mac_set_err_status(rtwdev, MAC_AX_ERR_L1_RESET_START_DMAC);
+}
+
static void hal_send_m2_event(struct rtw89_ser *ser)
{
struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
@@ -396,8 +409,12 @@ static void ser_idle_st_hdl(struct rtw89_ser *ser, u8 evt)
switch (evt) {
case SER_EV_STATE_IN:
rtw89_hci_recovery_complete(rtwdev);
+ clear_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags);
clear_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags);
break;
+ case SER_EV_L1_RESET_PREPARE:
+ ser_state_goto(ser, SER_L1_RESET_PRE_ST);
+ break;
case SER_EV_L1_RESET:
ser_state_goto(ser, SER_RESET_TRX_ST);
break;
@@ -405,6 +422,7 @@ static void ser_idle_st_hdl(struct rtw89_ser *ser, u8 evt)
ser_state_goto(ser, SER_L2_RESET_ST);
break;
case SER_EV_STATE_OUT:
+ set_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags);
rtw89_hci_recovery_start(rtwdev);
break;
default:
@@ -412,6 +430,28 @@ static void ser_idle_st_hdl(struct rtw89_ser *ser, u8 evt)
}
}
+static void ser_l1_reset_pre_st_hdl(struct rtw89_ser *ser, u8 evt)
+{
+ switch (evt) {
+ case SER_EV_STATE_IN:
+ ser->prehandle_l1 = true;
+ hal_send_post_m0_event(ser);
+ ser_set_alarm(ser, 1000, SER_EV_M1_TIMEOUT);
+ break;
+ case SER_EV_L1_RESET:
+ ser_state_goto(ser, SER_RESET_TRX_ST);
+ break;
+ case SER_EV_M1_TIMEOUT:
+ ser_state_goto(ser, SER_L2_RESET_ST);
+ break;
+ case SER_EV_STATE_OUT:
+ ser_del_alarm(ser);
+ break;
+ default:
+ break;
+ }
+}
+
static void ser_reset_trx_st_hdl(struct rtw89_ser *ser, u8 evt)
{
struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
@@ -654,12 +694,14 @@ static const struct event_ent ser_ev_tbl[] = {
{SER_EV_NONE, "SER_EV_NONE"},
{SER_EV_STATE_IN, "SER_EV_STATE_IN"},
{SER_EV_STATE_OUT, "SER_EV_STATE_OUT"},
- {SER_EV_L1_RESET, "SER_EV_L1_RESET"},
+ {SER_EV_L1_RESET_PREPARE, "SER_EV_L1_RESET_PREPARE pre-m0"},
+ {SER_EV_L1_RESET, "SER_EV_L1_RESET m1"},
{SER_EV_DO_RECOVERY, "SER_EV_DO_RECOVERY m3"},
{SER_EV_MAC_RESET_DONE, "SER_EV_MAC_RESET_DONE m5"},
{SER_EV_L2_RESET, "SER_EV_L2_RESET"},
{SER_EV_L2_RECFG_DONE, "SER_EV_L2_RECFG_DONE"},
{SER_EV_L2_RECFG_TIMEOUT, "SER_EV_L2_RECFG_TIMEOUT"},
+ {SER_EV_M1_TIMEOUT, "SER_EV_M1_TIMEOUT"},
{SER_EV_M3_TIMEOUT, "SER_EV_M3_TIMEOUT"},
{SER_EV_FW_M5_TIMEOUT, "SER_EV_FW_M5_TIMEOUT"},
{SER_EV_L0_RESET, "SER_EV_L0_RESET"},
@@ -668,6 +710,7 @@ static const struct event_ent ser_ev_tbl[] = {
static const struct state_ent ser_st_tbl[] = {
{SER_IDLE_ST, "SER_IDLE_ST", ser_idle_st_hdl},
+ {SER_L1_RESET_PRE_ST, "SER_L1_RESET_PRE_ST", ser_l1_reset_pre_st_hdl},
{SER_RESET_TRX_ST, "SER_RESET_TRX_ST", ser_reset_trx_st_hdl},
{SER_DO_HCI_ST, "SER_DO_HCI_ST", ser_do_hci_st_hdl},
{SER_L2_RESET_ST, "SER_L2_RESET_ST", ser_l2_reset_st_hdl}
@@ -713,6 +756,9 @@ int rtw89_ser_notify(struct rtw89_dev *rtwdev, u32 err)
rtw89_info(rtwdev, "SER catches error: 0x%x\n", err);
switch (err) {
+ case MAC_AX_ERR_L1_PREERR_DMAC: /* pre-M0 */
+ event = SER_EV_L1_RESET_PREPARE;
+ break;
case MAC_AX_ERR_L1_ERR_DMAC:
case MAC_AX_ERR_L0_PROMOTE_TO_L1:
event = SER_EV_L1_RESET; /* M1 */
diff --git a/drivers/net/wireless/realtek/rtw89/txrx.h b/drivers/net/wireless/realtek/rtw89/txrx.h
index 98eb9607cd21..ec96da36eacc 100644
--- a/drivers/net/wireless/realtek/rtw89/txrx.h
+++ b/drivers/net/wireless/realtek/rtw89/txrx.h
@@ -186,124 +186,64 @@
#define AX_RXD_BIP_KEYID BIT(27)
#define AX_RXD_BIP_ENC BIT(28)
-/* RX DESC helpers */
-/* Short Descriptor */
-#define RTW89_GET_RXWD_LONG_RXD(rxdesc) \
- le32_get_bits((rxdesc)->dword0, BIT(31))
-#define RTW89_GET_RXWD_DRV_INFO_SIZE(rxdesc) \
- le32_get_bits((rxdesc)->dword0, GENMASK(30, 28))
-#define RTW89_GET_RXWD_RPKT_TYPE(rxdesc) \
- le32_get_bits((rxdesc)->dword0, GENMASK(27, 24))
-#define RTW89_GET_RXWD_MAC_INFO_VALID(rxdesc) \
- le32_get_bits((rxdesc)->dword0, BIT(23))
-#define RTW89_GET_RXWD_BB_SEL(rxdesc) \
- le32_get_bits((rxdesc)->dword0, BIT(22))
-#define RTW89_GET_RXWD_HD_IV_LEN(rxdesc) \
- le32_get_bits((rxdesc)->dword0, GENMASK(21, 16))
-#define RTW89_GET_RXWD_SHIFT(rxdesc) \
- le32_get_bits((rxdesc)->dword0, GENMASK(15, 14))
-#define RTW89_GET_RXWD_PKT_SIZE(rxdesc) \
- le32_get_bits((rxdesc)->dword0, GENMASK(13, 0))
-#define RTW89_GET_RXWD_BW(rxdesc) \
- le32_get_bits((rxdesc)->dword1, GENMASK(31, 30))
-#define RTW89_GET_RXWD_BW_V1(rxdesc) \
- le32_get_bits((rxdesc)->dword1, GENMASK(31, 29))
-#define RTW89_GET_RXWD_GI_LTF(rxdesc) \
- le32_get_bits((rxdesc)->dword1, GENMASK(27, 25))
-#define RTW89_GET_RXWD_DATA_RATE(rxdesc) \
- le32_get_bits((rxdesc)->dword1, GENMASK(24, 16))
-#define RTW89_GET_RXWD_USER_ID(rxdesc) \
- le32_get_bits((rxdesc)->dword1, GENMASK(15, 8))
-#define RTW89_GET_RXWD_SR_EN(rxdesc) \
- le32_get_bits((rxdesc)->dword1, BIT(7))
-#define RTW89_GET_RXWD_PPDU_CNT(rxdesc) \
- le32_get_bits((rxdesc)->dword1, GENMASK(6, 4))
-#define RTW89_GET_RXWD_PPDU_TYPE(rxdesc) \
- le32_get_bits((rxdesc)->dword1, GENMASK(3, 0))
-#define RTW89_GET_RXWD_FREE_RUN_CNT(rxdesc) \
- le32_get_bits((rxdesc)->dword2, GENMASK(31, 0))
-#define RTW89_GET_RXWD_ICV_ERR(rxdesc) \
- le32_get_bits((rxdesc)->dword3, BIT(10))
-#define RTW89_GET_RXWD_CRC32_ERR(rxdesc) \
- le32_get_bits((rxdesc)->dword3, BIT(9))
-#define RTW89_GET_RXWD_HW_DEC(rxdesc) \
- le32_get_bits((rxdesc)->dword3, BIT(2))
-#define RTW89_GET_RXWD_SW_DEC(rxdesc) \
- le32_get_bits((rxdesc)->dword3, BIT(1))
-#define RTW89_GET_RXWD_A1_MATCH(rxdesc) \
- le32_get_bits((rxdesc)->dword3, BIT(0))
-
-/* Long Descriptor */
-#define RTW89_GET_RXWD_FRAG(rxdesc) \
- le32_get_bits((rxdesc)->dword4, GENMASK(31, 28))
-#define RTW89_GET_RXWD_SEQ(rxdesc) \
- le32_get_bits((rxdesc)->dword4, GENMASK(27, 16))
-#define RTW89_GET_RXWD_TYPE(rxdesc) \
- le32_get_bits((rxdesc)->dword4, GENMASK(1, 0))
-#define RTW89_GET_RXWD_ADDR_CAM_VLD(rxdesc) \
- le32_get_bits((rxdesc)->dword5, BIT(28))
-#define RTW89_GET_RXWD_RX_PL_ID(rxdesc) \
- le32_get_bits((rxdesc)->dword5, GENMASK(27, 24))
-#define RTW89_GET_RXWD_MAC_ID(rxdesc) \
- le32_get_bits((rxdesc)->dword5, GENMASK(23, 16))
-#define RTW89_GET_RXWD_ADDR_CAM_ID(rxdesc) \
- le32_get_bits((rxdesc)->dword5, GENMASK(15, 8))
-#define RTW89_GET_RXWD_SEC_CAM_ID(rxdesc) \
- le32_get_bits((rxdesc)->dword5, GENMASK(7, 0))
-
-#define RTW89_GET_RXINFO_USR_NUM(rpt) \
- le32_get_bits(*((const __le32 *)rpt), GENMASK(3, 0))
-#define RTW89_GET_RXINFO_FW_DEFINE(rpt) \
- le32_get_bits(*((const __le32 *)rpt), GENMASK(15, 8))
-#define RTW89_GET_RXINFO_LSIG_LEN(rpt) \
- le32_get_bits(*((const __le32 *)rpt), GENMASK(27, 16))
-#define RTW89_GET_RXINFO_IS_TO_SELF(rpt) \
- le32_get_bits(*((const __le32 *)rpt), BIT(28))
-#define RTW89_GET_RXINFO_RX_CNT_VLD(rpt) \
- le32_get_bits(*((const __le32 *)rpt), BIT(29))
-#define RTW89_GET_RXINFO_LONG_RXD(rpt) \
- le32_get_bits(*((const __le32 *)rpt), GENMASK(31, 30))
-#define RTW89_GET_RXINFO_SERVICE(rpt) \
- le32_get_bits(*((const __le32 *)(rpt) + 1), GENMASK(15, 0))
-#define RTW89_GET_RXINFO_PLCP_LEN(rpt) \
- le32_get_bits(*((const __le32 *)(rpt) + 1), GENMASK(23, 16))
-#define RTW89_GET_RXINFO_MAC_ID_VALID(rpt, usr) \
- le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), BIT(0))
-#define RTW89_GET_RXINFO_DATA(rpt, usr) \
- le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), BIT(1))
-#define RTW89_GET_RXINFO_CTRL(rpt, usr) \
- le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), BIT(2))
-#define RTW89_GET_RXINFO_MGMT(rpt, usr) \
- le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), BIT(3))
-#define RTW89_GET_RXINFO_BCM(rpt, usr) \
- le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), BIT(4))
-#define RTW89_GET_RXINFO_MACID(rpt, usr) \
- le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), GENMASK(15, 8))
-
-#define RTW89_GET_PHY_STS_IE_MAP(sts) \
- le32_get_bits(*((const __le32 *)(sts)), GENMASK(4, 0))
-#define RTW89_GET_PHY_STS_RSSI_A(sts) \
- le32_get_bits(*((const __le32 *)(sts) + 1), GENMASK(7, 0))
-#define RTW89_GET_PHY_STS_RSSI_B(sts) \
- le32_get_bits(*((const __le32 *)(sts) + 1), GENMASK(15, 8))
-#define RTW89_GET_PHY_STS_RSSI_C(sts) \
- le32_get_bits(*((const __le32 *)(sts) + 1), GENMASK(23, 16))
-#define RTW89_GET_PHY_STS_RSSI_D(sts) \
- le32_get_bits(*((const __le32 *)(sts) + 1), GENMASK(31, 24))
-#define RTW89_GET_PHY_STS_LEN(sts) \
- le32_get_bits(*((const __le32 *)sts), GENMASK(15, 8))
-#define RTW89_GET_PHY_STS_RSSI_AVG(sts) \
- le32_get_bits(*((const __le32 *)sts), GENMASK(31, 24))
-#define RTW89_GET_PHY_STS_IE_TYPE(ie) \
- le32_get_bits(*((const __le32 *)ie), GENMASK(4, 0))
-#define RTW89_GET_PHY_STS_IE_LEN(ie) \
- le32_get_bits(*((const __le32 *)ie), GENMASK(11, 5))
-#define RTW89_GET_PHY_STS_IE01_CH_IDX(ie) \
- le32_get_bits(*((const __le32 *)ie), GENMASK(23, 16))
-#define RTW89_GET_PHY_STS_IE01_FD_CFO(ie) \
- le32_get_bits(*((const __le32 *)(ie) + 1), GENMASK(19, 8))
-#define RTW89_GET_PHY_STS_IE01_PREMB_CFO(ie) \
- le32_get_bits(*((const __le32 *)(ie) + 1), GENMASK(31, 20))
+struct rtw89_rxinfo_user {
+ __le32 w0;
+};
+
+#define RTW89_RXINFO_USER_MAC_ID_VALID BIT(0)
+#define RTW89_RXINFO_USER_DATA BIT(1)
+#define RTW89_RXINFO_USER_CTRL BIT(2)
+#define RTW89_RXINFO_USER_MGMT BIT(3)
+#define RTW89_RXINFO_USER_BCM BIT(4)
+#define RTW89_RXINFO_USER_MACID GENMASK(15, 8)
+
+struct rtw89_rxinfo {
+ __le32 w0;
+ __le32 w1;
+ struct rtw89_rxinfo_user user[];
+} __packed;
+
+#define RTW89_RXINFO_W0_USR_NUM GENMASK(3, 0)
+#define RTW89_RXINFO_W0_FW_DEFINE GENMASK(15, 8)
+#define RTW89_RXINFO_W0_LSIG_LEN GENMASK(27, 16)
+#define RTW89_RXINFO_W0_IS_TO_SELF BIT(28)
+#define RTW89_RXINFO_W0_RX_CNT_VLD BIT(29)
+#define RTW89_RXINFO_W0_LONG_RXD GENMASK(31, 30)
+#define RTW89_RXINFO_W1_SERVICE GENMASK(15, 0)
+#define RTW89_RXINFO_W1_PLCP_LEN GENMASK(23, 16)
+
+struct rtw89_phy_sts_hdr {
+ __le32 w0;
+ __le32 w1;
+} __packed;
+
+#define RTW89_PHY_STS_HDR_W0_IE_MAP GENMASK(4, 0)
+#define RTW89_PHY_STS_HDR_W0_LEN GENMASK(15, 8)
+#define RTW89_PHY_STS_HDR_W0_RSSI_AVG GENMASK(31, 24)
+#define RTW89_PHY_STS_HDR_W1_RSSI_A GENMASK(7, 0)
+#define RTW89_PHY_STS_HDR_W1_RSSI_B GENMASK(15, 8)
+#define RTW89_PHY_STS_HDR_W1_RSSI_C GENMASK(23, 16)
+#define RTW89_PHY_STS_HDR_W1_RSSI_D GENMASK(31, 24)
+
+struct rtw89_phy_sts_iehdr {
+ __le32 w0;
+};
+
+#define RTW89_PHY_STS_IEHDR_TYPE GENMASK(4, 0)
+#define RTW89_PHY_STS_IEHDR_LEN GENMASK(11, 5)
+
+struct rtw89_phy_sts_ie0 {
+ __le32 w0;
+ __le32 w1;
+ __le32 w2;
+} __packed;
+
+#define RTW89_PHY_STS_IE01_W0_CH_IDX GENMASK(23, 16)
+#define RTW89_PHY_STS_IE01_W1_FD_CFO GENMASK(19, 8)
+#define RTW89_PHY_STS_IE01_W1_PREMB_CFO GENMASK(31, 20)
+#define RTW89_PHY_STS_IE01_W2_AVG_SNR GENMASK(5, 0)
+#define RTW89_PHY_STS_IE01_W2_EVM_MAX GENMASK(15, 8)
+#define RTW89_PHY_STS_IE01_W2_EVM_MIN GENMASK(23, 16)
enum rtw89_tx_channel {
RTW89_TXCH_ACH0 = 0,
diff --git a/drivers/net/wireless/realtek/rtw89/wow.c b/drivers/net/wireless/realtek/rtw89/wow.c
index 2ca8abb70f11..364e54622150 100644
--- a/drivers/net/wireless/realtek/rtw89/wow.c
+++ b/drivers/net/wireless/realtek/rtw89/wow.c
@@ -91,7 +91,7 @@ static void rtw89_wow_show_wakeup_reason(struct rtw89_dev *rtwdev)
u32 wow_reason_reg;
u8 reason;
- if (chip_id == RTL8852A || chip_id == RTL8852B)
+ if (chip_id == RTL8852A || chip_id == RTL8852B || chip_id == RTL8851B)
wow_reason_reg = R_AX_C2HREG_DATA3 + 3;
else
wow_reason_reg = R_AX_C2HREG_DATA3_V1 + 3;
diff --git a/drivers/net/wireless/rsi/rsi_91x_sdio.c b/drivers/net/wireless/rsi/rsi_91x_sdio.c
index d09998796ac0..1911fef3bbad 100644
--- a/drivers/net/wireless/rsi/rsi_91x_sdio.c
+++ b/drivers/net/wireless/rsi/rsi_91x_sdio.c
@@ -1463,10 +1463,8 @@ static void rsi_shutdown(struct device *dev)
rsi_dbg(ERR_ZONE, "SDIO Bus shutdown =====>\n");
- if (hw) {
- struct cfg80211_wowlan *wowlan = hw->wiphy->wowlan_config;
-
- if (rsi_config_wowlan(adapter, wowlan))
+ if (hw && hw->wiphy && hw->wiphy->wowlan_config) {
+ if (rsi_config_wowlan(adapter, hw->wiphy->wowlan_config))
rsi_dbg(ERR_ZONE, "Failed to configure WoWLAN\n");
}
@@ -1481,9 +1479,6 @@ static void rsi_shutdown(struct device *dev)
if (sdev->write_fail)
rsi_dbg(INFO_ZONE, "###### Device is not ready #######\n");
- if (rsi_set_sdio_pm_caps(adapter))
- rsi_dbg(INFO_ZONE, "Setting power management caps failed\n");
-
rsi_dbg(INFO_ZONE, "***** RSI module shut down *****\n");
}
diff --git a/drivers/net/wireless/virtual/mac80211_hwsim.c b/drivers/net/wireless/virtual/mac80211_hwsim.c
index 89c7a1420381..f446fd0e8cd0 100644
--- a/drivers/net/wireless/virtual/mac80211_hwsim.c
+++ b/drivers/net/wireless/virtual/mac80211_hwsim.c
@@ -4,7 +4,7 @@
* Copyright (c) 2008, Jouni Malinen <j@w1.fi>
* Copyright (c) 2011, Javier Lopez <jlopex@gmail.com>
* Copyright (c) 2016 - 2017 Intel Deutschland GmbH
- * Copyright (C) 2018 - 2022 Intel Corporation
+ * Copyright (C) 2018 - 2023 Intel Corporation
*/
/*
@@ -582,8 +582,9 @@ static int mac80211_hwsim_vendor_cmd_test(struct wiphy *wiphy,
*/
/* Add vendor data */
- nla_put_u32(skb, QCA_WLAN_VENDOR_ATTR_TEST, val + 1);
-
+ err = nla_put_u32(skb, QCA_WLAN_VENDOR_ATTR_TEST, val + 1);
+ if (err)
+ return err;
/* Send the event - this will call nla_nest_end() */
cfg80211_vendor_event(skb, GFP_KERNEL);
}
@@ -1859,12 +1860,12 @@ mac80211_hwsim_select_tx_link(struct mac80211_hwsim_data *data,
struct hwsim_sta_priv *sp = (void *)sta->drv_priv;
int i;
- if (!vif->valid_links)
+ if (!ieee80211_vif_is_mld(vif))
return &vif->bss_conf;
WARN_ON(is_multicast_ether_addr(hdr->addr1));
- if (WARN_ON_ONCE(!sta->valid_links))
+ if (WARN_ON_ONCE(!sta || !sta->valid_links))
return &vif->bss_conf;
for (i = 0; i < ARRAY_SIZE(vif->link_conf); i++) {
@@ -1940,7 +1941,14 @@ static void mac80211_hwsim_tx(struct ieee80211_hw *hw,
hdr, &link_sta);
}
- if (WARN_ON(!bss_conf)) {
+ if (unlikely(!bss_conf)) {
+ /* if it's an MLO STA, it might have deactivated all
+ * links temporarily - but we don't handle real PS in
+ * this code yet, so just drop the frame in that case
+ */
+ WARN(link != IEEE80211_LINK_UNSPECIFIED || !sta || !sta->mlo,
+ "link:%d, sta:%pM, sta->mlo:%d\n",
+ link, sta ? sta->addr : NULL, sta ? sta->mlo : -1);
ieee80211_free_txskb(hw, skb);
return;
}
@@ -2628,7 +2636,8 @@ static int mac80211_hwsim_sta_state(struct ieee80211_hw *hw,
*/
if (vif->type == NL80211_IFTYPE_STATION &&
new_state == IEEE80211_STA_AUTHORIZED && !sta->tdls)
- ieee80211_set_active_links_async(vif, vif->valid_links);
+ ieee80211_set_active_links_async(vif,
+ ieee80211_vif_usable_links(vif));
return 0;
}