diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/haswell/other.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/haswell/other.json | 40 |
1 files changed, 20 insertions, 20 deletions
diff --git a/tools/perf/pmu-events/arch/x86/haswell/other.json b/tools/perf/pmu-events/arch/x86/haswell/other.json index 8a4d898d76c1..4c6b9d34325a 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/other.json +++ b/tools/perf/pmu-events/arch/x86/haswell/other.json @@ -1,43 +1,43 @@ [ { - "PublicDescription": "Unhalted core cycles when the thread is in ring 0.", - "EventCode": "0x5C", + "BriefDescription": "Unhalted core cycles when the thread is in ring 0", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING0", + "PublicDescription": "Unhalted core cycles when the thread is in ring 0.", "SampleAfterValue": "2000003", - "BriefDescription": "Unhalted core cycles when the thread is in ring 0", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x5C", + "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", "EdgeDetect": "1", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING0_TRANS", "SampleAfterValue": "100003", - "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.", - "EventCode": "0x5C", + "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING123", + "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.", "SampleAfterValue": "2000003", - "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.", - "EventCode": "0x63", + "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", + "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" } ]
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