linux - linux

	Commit message (Collapse)	Author	Age	Files	Lines
*	dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs	Xingyu Wu	2023-07-19	1	-2/+16
\| \| \| \| \| \| \| \| \|	Add PLL clock inputs from PLL clock generator. Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
*	dt-bindings: clock: Add StarFive JH7110 system clock and reset generator	Emil Renner Berthing	2023-04-05	1	-0/+104
	Add bindings for the system clock and reset generator (SYSCRG) on the JH7110 RISC-V SoC by StarFive Ltd. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>