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path: root/arch/arc/include/asm/cache.h (follow)
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* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner2019-06-191-4/+1
* ARC: define ARCH_SLAB_MINALIGN = 8Alexey Brodkin2019-02-211-0/+11
* ARC: IOC: panic if kernel was started with previously enabled IOCEugeniy Paltsev2018-11-121-0/+2
* ARC: dma [non-IOC] setup SMP_CACHE_BYTES and cache_line_sizeEugeniy Paltsev2018-07-271-1/+3
* ARCv2: SLC: provide a line based flush routine for debuggingVineet Gupta2017-08-301-0/+2
* ARC: Hardcode ARCH_DMA_MINALIGN to max line length we may haveAlexey Brodkin2017-08-301-1/+2
* ARCv2: PAE40: Explicitly set MSB counterpart of SLC region ops addressesAlexey Brodkin2017-08-041-0/+2
* ARCv2: mm: micro-optimize region flush generated codeVineet Gupta2017-05-031-1/+1
* ARCv2: mm: Implement cache region flush operationsVineet Gupta2017-05-031-0/+6
* ARCv2: IOC: Adhere to progamming model guidelines to avoid DMA corruptionVineet Gupta2017-01-181-3/+4
* ARCv2: IOC: refactor the IOC and SLC operations into own functionsVineet Gupta2017-01-181-1/+1
* ARCv2: IOC: use @ioc_enable not @ioc_exist where intendedVineet Gupta2016-10-241-1/+1
* ARCv2: Support dynamic peripheral address space in HS38 rel 3.0 coresVineet Gupta2016-09-301-1/+1
* ARCv2: ioremap: Support dynamic peripheral address spaceVineet Gupta2016-03-191-0/+1
* ARC: mm: fix building for MMU v2Alexey Brodkin2015-12-211-2/+0
* ARC: mm: PAE40 supportVineet Gupta2015-10-291-0/+2
* ARCv2: Support IO Coherency and permutations involving L1 and L2 cachesAlexey Brodkin2015-08-201-0/+8
* ARCv2: SLC: Handle explcit flush for DMA ops (w/o IO-coherency)Vineet Gupta2015-06-251-0/+11
* ARCv2: MMUv4: support aliasing icache configVineet Gupta2015-06-221-3/+1
* ARCv2: MMUv4: cache programming model changesVineet Gupta2015-06-221-0/+3
* ARC: Update comments about uncached address spaceVineet Gupta2014-10-131-1/+1
* ARC: remove checks for CONFIG_ARC_MMU_V4Paul Bolle2014-06-161-2/+2
* ARC: Disable caches in early boot if so configuredVineet Gupta2014-06-031-0/+27
* ARC: cacheflush refactor #2: I and D caches lines to have same sizeVineet Gupta2013-11-061-7/+1
* ARC: fix new Section mismatches in build (post __cpuinit cleanup)Vineet Gupta2013-09-051-1/+1
* ARC: cache detection code bitrotVineet Gupta2013-06-221-10/+1
* ARC: Disintegrate arcregs.hVineet Gupta2013-06-221-10/+9
* ARC: Use kconfig helper IS_ENABLED() to get rid of defines.hVineet Gupta2013-06-221-0/+2
* ARC: [mm] Aliasing VIPT dcache support 4/4Vineet Gupta2013-05-091-3/+0
* ARC: Cache Flush ManagementVineet Gupta2013-02-151-0/+54
* ARC: Fundamental ARCH data-types/definesVineet Gupta2013-02-111-0/+21
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