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* Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds2019-12-051-0/+14
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ARM Device-tree updates from Olof Johansson: "As always, the bulk of updates. Some of the news this cycle: New SoC descriptions: - Broadcom BCM2711 - Amlogic Meson A1 and G12 - Freescale S32V234 - Marvell Armada AP807/AP807-quad and CP115 - Realtek RTD1293 and RTD1296 - Rockchip RK3308 New boards and platforms: - Allwinner: NanoPi Duo2 - Amlogic: Ugoos am6 - Atmel at91: Overkiz Kizbox2/4 - Broadcom: RPi4, Luxul XWC-2000 - Marvell: New Espressobin flavor - NXP: i.MX8MN LPDDR4 EVK, i.MX8QXP Colibri, S32V234 EVB, Netronix E60K02 and Kobo Clara HD, Kontron N6311 and N6411, OPOS6UL and OPOS6ULDev - Renesas: Salvator-XS - Rockchip: Beelink A1 (rk3308), rk3308 eval boards, rk3399-roc-pc" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (653 commits) ARM: dts: logicpd-torpedo: Disable USB Host arm: dts: mt6323: add keys, power-controller, rtc and codec arm64: dts: mt8183: add systimer0 device node dt-bindings: mediatek: update bindings for MT8183 systimer arm64: dts: rockchip: fix sdmmc detection on boot on rk3328-roc-cc arm64: dts: rockchip: Split rk3399-roc-pc for with and without mezzanine board. arm64: dts: rockchip: Add Beelink A1 dt-bindings: ARM: rockchip: Add Beelink A1 arm64: dts: rockchip: Add RK3328 audio pipelines arm64: dts: ti: k3-j721e-common-proc-board: Add USB ports arm64: dts: ti: k3-j721e-main: add USB controller nodes ARM: dts: aspeed-g6: Add timer description ARM: dts: aspeed: ast2600evb: Enable i2c buses ARM: dts: at91: add a dts and dtsi file for kizbox2 based boards dt-bindings: arm: at91: Document Kizbox2-2 board binding arm64: dts: meson-gx: fix i2c compatible arm64: dts: meson-gx: cec node should be disabled by default arm64: dts: meson-g12b-odroid-n2: add missing amlogic, s922x compatible arm64: dts: meson-gxm: fix gpu irq order arm64: dts: meson-g12a: fix gpu irq order ...
| * ARM: dts: sunxi: h3/h5: Add MBUS controller nodeJernej Skrabec2019-11-051-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | Both, H3 and H5, contain MBUS, which is the bus used by DMA devices to access system memory. MBUS controller is responsible for arbitration between channels based on set priority and can do some other things as well, like report bandwidth used. It also maps RAM region to different address than CPU. Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
| * ARM: dts: sunxi: h3/h5: add missing uart2 rts/cts pinsKarl Palsson2019-11-011-0/+5
| | | | | | | | | | | | | | | | | | uart1 and uart3 had existing pin definitions for the rts/cts pairs. Add definitions for uart2 as well. Signed-off-by: Karl Palsson <karlp@tweak.net.au> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
* | ARM: dts: sunxi: Revert phy-names removal for ECHI and OHCIMaxime Ripard2019-10-041-0/+6
|/ | | | | | | | | | | | | | | | | | | This reverts commits 3d109bdca981 ("ARM: dts: sunxi: Remove useless phy-names from EHCI and OHCI"), 0a3df8bb6dad ("ARM: dts: sunxi: h3/h5: Remove useless phy-names from EHCI and OHCI") and 3c7ab90aaa28 ("arm64: dts: allwinner: Remove useless phy-names from EHCI and OHCI"). It turns out that while the USB bindings were not mentionning it, the PHY client bindings were mandating that phy-names is set when phys is. Let's add it back. Fixes: 3d109bdca981 ("ARM: dts: sunxi: Remove useless phy-names from EHCI and OHCI") Fixes: 0a3df8bb6dad ("ARM: dts: sunxi: h3/h5: Remove useless phy-names from EHCI and OHCI") Fixes: 3c7ab90aaa28 ("arm64: dts: allwinner: Remove useless phy-names from EHCI and OHCI") Reported-by: Emmanuel Vadot <manu@bidouilliste.com> Signed-off-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/20191002112651.100504-1-mripard@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* ARM: dts: sunxi: Add missing watchdog clocksMaxime Ripard2019-08-231-0/+1
| | | | | | | The watchdog has a clock on all our SoCs, but it wasn't always listed. Add it to the devicetree where it's missing. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: dts: h3: Change the timers compatibleMaxime Ripard2019-08-231-1/+1
| | | | | | | | Unlike the A10 that has 6 timers available, the H3 has only two, with only two interrupts, just like the A23. Let's change the compatible to reflect that. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: dts: sunxi: Prefer A31 bindings for IRClément Péron2019-07-241-1/+1
| | | | | | | | | | Since A31, memory mapping of the IR driver has changed. Prefer the A31 bindings instead of A13. Signed-off-by: Clément Péron <peron.clem@gmail.com> Acked-by: Sean Young <sean@mess.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: dts: sunxi: Fix the HDMI PHY nameMaxime Ripard2019-07-231-1/+1
| | | | | | | | | | | Even though the binding mentions that the PHY name must be "phy", it turns out that all our DTs had "hdmi-phy" instead. The code doesn't care about the phy-names property, so we can just change our DTs to match the binding, without any side effect. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: dts: sunxi: Unify the DE2 bus clocks orderMaxime Ripard2019-07-221-4/+4
| | | | | | | | | | | | The DE2 bus takes two clocks, named bus and mod according to the binding. However, the order of these clocks change from one SoC to another. Even though it might not be an issue in most cases, having consistency will help if we ever need to have some code to deal with deprecated bindings, and in general it's just better. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: dts: sunxi: h3/h5: Remove useless phy-names from EHCI and OHCIMaxime Ripard2019-04-171-6/+0
| | | | | | | | Neither the OHCI or EHCI bindings are using the phy-names property, so we can just drop it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: dts: sun8i: h3: Add default dr_modeMaxime Ripard2019-03-261-0/+1
| | | | | | | | | | | The USB OTG binding we have mandates to have a dr_mode property, yet not all boards are setting it. Since the generic otg binding states that the default mode should be the OTG mode, let's use that one in our DTSI. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: dts: sun8i: h3: Refactor the pinctrl node namesMaxime Ripard2019-03-251-19/+19
| | | | | | | | | | The H3 and H5 have never been converted to the new convention we want to have for the pinctrl nodes. Convert them. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: dts: sunxi: h3/h5: Add device node for SIDChen-Yu Tsai2019-03-211-0/+5
| | | | | | | | The device tree binding already lists compatible strings for these two SoCs. Add a device node for them. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
* ARM: dts: sunxi: h3/h5: Drop A31 fallback compatible for CSI controllerChen-Yu Tsai2019-01-241-2/+1
| | | | | | | | | | | | | | The CSI controller found on the H3 (and H5) is a reduced version of the one found on the A31. It only has 1 channel, instead of 4 channels for time-multiplexed BT.656. Since the H3 is a reduced version, it cannot "fallback" to a compatible that implements more features than it supports. Drop the A31 fallback compatible. Fixes: f89120b6f554 ("ARM: dts: sun8i: Add the H3/H5 CSI controller") Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
* Merge tag 'sunxi-h3-h5-for-4.21' of ↵Olof Johansson2018-12-121-6/+22
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt Allwinner H3/H5 changes for 4.21 Our usual pull request with the changes shared between the H3 and H5 SoCs. The major changes for this release are: - Addition of the video engine for the H5 - H3 Camera support - New board: Emlid Neutis N5, Mapleboard MP130 * tag 'sunxi-h3-h5-for-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: arm64: dts: allwinner: h5: Add Video Engine node ARM/arm64: dts: allwinner: Move H3/H5 syscon label over to soc-specific nodes arm64: dts: allwinner: h5: Add system-control node with SRAM C1 ARM: dts: sun8i: h3: Fix the system-control register range ARM: dts: sun8i: Add the H3/H5 CSI controller ARM: dts: sun8i-h3: Add dts for the Mapleboard MP130 arm64: dts: allwinner: new board - Emlid Neutis N5 dt-bindings: vendor-prefix: new vendor - Emlid ARM: dts: sun8i-h3: add sy8106a to orange pi plus Signed-off-by: Olof Johansson <olof@lixom.net>
| * ARM/arm64: dts: allwinner: Move H3/H5 syscon label over to soc-specific nodesPaul Kocialkowski2018-12-051-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The EMAC driver requires a syscon node to access the EMAC clock configuration register (that is part of the system-control register range and controlled). For this purpose, a dummy syscon node was introduced to let the driver access the register freely. Recently, the EMAC driver was tuned to get access to the register when the SRAM driver is registered (as used on the A64). As a result, it is no longer necessary to have a dummy syscon node for that purpose. Now that we have a proper system-control node for both the H3 and H5, we can get rid of that dummy syscon node and have the EMAC driver use the node corresponding to the proper SRAM driver (by switching the syscon label over to each dtsi). This way, we no longer have two separate nodes for the same register space. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
| * ARM: dts: sun8i: Add the H3/H5 CSI controllerMylène Josserand2018-11-271-0/+22
| | | | | | | | | | | | | | | | | | | | The H3 and H5 features the same CSI controller that was initially found on the A31. Add a DT node for it. Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* | ARM: dts: sunxi: h3/h5: Fix up RTC device node and clock referencesChen-Yu Tsai2018-12-071-16/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RTC module on the H3 was claimed to be the same as on the A31, when in fact it is not. The A31 does not have an RTC external clock output, and its internal RC oscillator's average clock rate is not in the same range. The H5's RTC has some extra crypto-related registers compared to the H3. Their exact functions are not clear. Also the RTC-VIO regulator has different settings. This patch fixes the compatible string and clock properties to conform to the updated bindings. The device node for the internal oscillator is removed, as it is internalized into the RTC device. Clock references to the IOSC and LOSC are also fixed. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
* | ARM: dts: sunxi: h3/h5: Add clock accuracy for external oscillatorsChen-Yu Tsai2018-12-061-0/+2
|/ | | | | | | | | | The H3 datasheet specifies a tolerance range for the external oscillators used. Add them to the device tree as the clock accuracy. The internal oscillator is left unchanged, as it will be removed later. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
* ARM: dts: sun8i: h3-h5: ir register size should be the whole memory blockPhilipp Rossak2018-09-291-1/+1
| | | | | | | | | The size of the register should be the size of the whole memory block, not just the registers, that are needed. Signed-off-by: Philipp Rossak <embed3d@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
* ARM: dts: sunxi-h3-h5: Remove unused address-cells/size-cells of dwmac-sun8iCorentin Labbe2018-07-191-2/+0
| | | | | | | | | | | | address-cells/size-cells is unnecessary for dwmac-sun8i node. It was in early days, but since a mdio node is used, it could be removed. This patch fix the following DT warning: Warning (avoid_unnecessary_addr_size): /soc/ethernet@1c50000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Corentin Labbe <clabbe@baylibre.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: dts: sunxi: h3/h5: Add r_i2c I2C controllerOndrej Jirman2018-04-201-0/+13
| | | | | | | | | | | | Allwinner H3/H5 SoCs have an I2C controller at PL GPIO bank. Add support for it in the device tree. Signed-off-by: Ondrej Jirman <megous@megous.com> [Icenowy: Change to use r_ccu and change pinmux node name] Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
* ARM: dts: sunxi: h3/h5: Add r_i2c pinmux nodeOndrej Jirman2018-04-201-0/+5
| | | | | | | | | | | | H3/H5 SoCs contain an I2C controller optionally available on the PL0 and PL1 pins. This patch adds pinmux configuration for this controller. Signed-off-by: Ondrej Jirman <megous@megous.com> [Icenowy: change commit message, node name and function name] Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
* ARM: dts: sunxi: h3/h5: Add HDMI pipelineJernej Skrabec2018-03-021-0/+108
| | | | | | | This commit adds all entries needed for HDMI to function properly. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: dts: sunxi: h3-h5: rename mmc0_pins_a and mmc1_pins_aJoonas Kylmälä2018-02-151-4/+4
| | | | | | | | There is only one pinctrl configuration for mmc0 and mmc1 so let's drop the _a suffix from both of them. Signed-off-by: Joonas Kylmälä <joonas.kylmala@iki.fi> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: dts: sunxi: h3-h5: Move pinctrl of mmc1 from dts to dtsiJoonas Kylmälä2018-02-151-0/+2
| | | | | | | | | | Most of the boards use the mmc1 pins and their attributes defined in mmc1_pins_a. Let's default to that by moving the pinctrl attributes to the dtsi file. This makes it easier to modify device trees in the future as there is only one place to change the pinctrl attributes. Signed-off-by: Joonas Kylmälä <joonas.kylmala@iki.fi> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: dts: sunxi: h3-h5: Move pinctrl of mmc0 from dts to dtsiJoonas Kylmälä2018-02-141-0/+2
| | | | | | | | | | Most of the boards use the mmc0 pins and their attributes defined in mmc0_pins_a. Let's default to those by moving the pinctrl attributes to the dtsi file. This makes it easier to modify device trees in the future as there is only one place to change the pinctrl attributes. Signed-off-by: Joonas Kylmälä <joonas.kylmala@iki.fi> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: dts: sunxi: h3-h5: remove mmc0 card detection pin from pinctrlJoonas Kylmälä2018-02-141-6/+0
| | | | | | | | | The GPIO card detection pin (mmc0_cd_pin) is already requested and configured by mmc_gpiod_request_cd() in drivers/mmc/core/slot-gpio.c so pinctrl is not needed. Signed-off-by: Joonas Kylmälä <joonas.kylmala@iki.fi> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: sunxi: h3/h5: add simplefb nodesIcenowy Zheng2018-01-031-0/+24
| | | | | | | | | The H3/H5 SoCs have a HDMI output and a TV Composite output. Add simplefb nodes for these outputs. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
* ARM: sun8i: h3/h5: add DE2 CCU device node for H3Icenowy Zheng2017-12-291-0/+14
| | | | | | | | | | | | | The DE2 in H3/H5 has a clock control unit in it, and the behavior is slightly different between H3 and H5. Add the common parts in H3/H5 DTSI, and add the compatible string in H3 DTSI. The compatible string of H5 DE2 CCU will be added in a separated patch. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
* ARM: dts: sunxi: h3/h5: represent the mdio switch used by sun8i-h3-emacCorentin Labbe2017-11-021-4/+27
| | | | | | | | | | | Since dwmac-sun8i could use either an integrated PHY or an external PHY (which could be at same MDIO address), we need to represent this selection by a MDIO switch. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* arm: dts: sunxi: h3/h5: Restore EMAC changesCorentin Labbe2017-11-021-0/+26
| | | | | | | | | | | | | The original dwmac-sun8i DT bindings have some issue on how to handle integrated PHY and was reverted in last RC of 4.13. But now we have a solution so we need to get back that was reverted. This patch restore sunxi-h3-h5.dtsi This reverts partially commit fe45174b72ae ("arm: dts: sunxi: Revert EMAC changes") Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sunxi: h3/h5: Fix node with unit name and no reg propertyCorentin LABBE2017-09-261-6/+6
| | | | | | | | | This patch fix the warning "xxx has a unit name, but no reg property" by removing "@0" from such node. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
* ARM: dts: sunxi: h3/h5: Fix i2c2 register addressCorentin LABBE2017-09-261-1/+1
| | | | | | | | | The unit address and register address does not match. This patch fix the register address with the good one. Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
* ARM: dts: sunxi: h3/h5: Fix simple-bus unit address format errorCorentin LABBE2017-09-261-37/+37
| | | | | | | | | This patch remove leading 0 of unit address and so remove lots of warning when building DT with W=1. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
* ARM: dts: sunxi: h3/h5: Add DAI nodesMarcus Cooper2017-09-171-0/+26
| | | | | | | | Add the new DAI blocks to the device tree. I2S0 and I2S1 are for connecting to an external codec. Signed-off-by: Marcus Cooper <codekipper@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun8i: h3: Adding UART3 RTS and CTS PinsPhilipp Rossak2017-09-171-0/+5
| | | | | | | | | This node adds the definition for the UART3 RTS and CTS Pins That makes it able to use UART3 with RTS and CTS. Signed-off-by: Philipp Rossak <embed3d@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* arm: dts: sunxi: Revert EMAC changesMaxime Ripard2017-08-281-26/+0
| | | | | | | | | Since the discussion is not settled yet for the EMAC, and that the release in getting really close, let's revert the changes for now, and we'll reintroduce them later. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sunxi: h3/h5: Correct emac register sizeCorentin Labbe2017-07-271-1/+1
| | | | | | | | | The datasheet said that emac register size is 0x10000 not 0x104 Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> [wens@csie.org: Fixed commit subject prefix] Signed-off-by: Chen-Yu Tsai <wens@csie.org>
* Merge tag 'armsoc-dt' of ↵Linus Torvalds2017-07-041-3/+45
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM device-tree updates from Arnd Bergmann: "Device-tree continues to see lots of updates. The majority of patches here are smaller changes for new hardware on existing platforms, and there are a few larger changes worth pointing out. New machines: - The new Action Semi S500 platform is added along with initial support for the LeMaker Guitar board. - STM32 gains support for three new boards: stm32h743-disco, stm32f746-disco, and stm32f769-disco, along with new device support for the existing stm32f429 boards. - Renesas adds two new boards, the tiny GR-Peach based on RZ/A1H with 10MB on-chip SRAM, and the iWave G20D-Q7 System-on-Module plus board. - On Marvell "mvebu", we gain support for the Linksys WRT3200ACM wireless router. - For NXP i.MX, we gain support for the Gateworks Ventana GW5600 and the Technexion Pico i.MX7D single-board computers. - The BeagleBone Blue is added for OMAP, it's the latest variation of the popular Beaglebone Black single-board computer. - The Allwinner based Lichee Pi Zero and NanoPi M1 Plus boards are added, these are the latest variations of a seemingly endless supply of similar single-board computers. Other updates: - Linus Walleij improves support for the "Faraday" based SoC platforms from various SoC makers (Moxart, Aspeed, Gemini) - The ARM Mali GPU is now describe on Rockchips SoCs - Mediatek MT7623 is extended significantly, making it much more useful. - Lots of individual updates on Renesas, OMAP, Rockchips, Broadcom, Allwinner, Qualcomm, iMX - For Amlogic, the clock support is extended a lot on meson8b. - We now build the devicetree file for the Raspberry Pi 3 on 32-bit ARM, in addition to the existing ARM64 support, to help users wanting to run a 32-bit system on it" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (345 commits) ARM: dts: socfpga: set the i2c frequency ARM: dts: socfpga: Add second ethernet alias to VINING FPGA ARM: dts: socfpga: Drop LED node from VINING FPGA ARM: dts: socfpga: Remove I2C EEPROMs from VINING FPGA ARM: dts: socfpga: Enable QSPI support on VINING FPGA ARM: dts: socfpga: Fix the ethernet clock phandle ARM: pxa: Use - instead of @ for DT OPP entries ARM: dts: owl-s500: Add SPS node ARM: dts: owl-s500: Set CPU enable-method dt-bindings: arm: cpus: Add S500 enable-method ARM: dts: Add Actions Semi S500 and LeMaker Guitar dt-bindings: arm: Document Actions Semi S900 dt-bindings: timer: Document Owl timer ARM: dts: imx6q-cm-fx6: add sdio wifi/bt nodes dt-bindings: arm: Document Actions Semi S500 dt-bindings: Add vendor prefix for Actions Semi ARM: dts: turris-omnia: Add generic compatible string for I2C EEPROM ARM: dts: mvebu: add support for Linksys WRT3200ACM (Rango) ARM: dts: armada-385-linksys: fixup button node names ARM: dts: armada-385-linksys: group pins in pinctrl ...
| * arm: sun8i: sunxi-h3-h5: add dwmac-sun8i ethernet driverCorentin Labbe2017-06-061-0/+34
| | | | | | | | | | | | | | | | | | | | | | The dwmac-sun8i is an ethernet MAC hardware that support 10/100/1000 speed. This patch enable the dwmac-sun8i on Allwinner H3/H5 SoC Device-tree. SoC H3/H5 have an internal PHY, so optionals syscon and ephy are set. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * arm: sun8i: sunxi-h3-h5: Add dt node for the syscon control moduleCorentin Labbe2017-06-061-0/+6
| | | | | | | | | | | | | | | | | | | | | | This patch add the dt node for the syscon register present on the Allwinner H3/H5 Only two register are present in this syscon and the only one useful is the one dedicated to EMAC clock.. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * ARM: sunxi: h3-h5: Convert R_CCU raw numbers to macrosChen-Yu Tsai2017-06-061-3/+5
| | | | | | | | | | | | | | | | | | Now that the R_CCU device tree binding headers have been merged, we can convert the raw number references in the device trees to use the defined macros. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | ARM: sunxi: h3-h5: Add PLL_PERIPH0 clock to the R_CCUChen-Yu Tsai2017-06-031-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | The AR100 clock within the R_CCU (PRCM) has the PLL_PERIPH0 as one of its parents. This adds the reference in the device tree describing this relationship. This patch uses a raw number for the clock index to ease merging by avoiding cross tree dependencies. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | ARM: sunxi: h3/h5: fix the compatible of R_CCUIcenowy Zheng2017-05-141-1/+1
|/ | | | | | | | | The R_CCU of H3/H5 currently wrongly used A64 R_CCU compatible. Fix it by changing it to the correct H3 compatible. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccuIcenowy Zheng2017-04-041-31/+14
| | | | | | | | | | | | Now we have driver for the PRCM CCU, switch to use it instead of old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi . The mux 3 of R_CCU is still the internal oscillator, which is said to be 16MHz plus minus 30%, and get a measured value of 15MHz~16MHz on my two H3 boards and one H5 board. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sunxi: h3/h5: add usb_otg and OHCI/EHCI for usbc0 on H3/H5Icenowy Zheng2017-03-271-0/+32
| | | | | | | | | | Allwinner H3/H5 have a dual-routed USB PHY0 -- routed to either OHCI/EHCI or MUSB controller. Add device nodes for these controllers. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* arm: sun8i: h3: split Allwinner H3 .dtsiAndre Przywara2017-03-271-0/+586
The new Allwinner H5 SoC is pin-compatible to the H3 SoC, but with the Cortex-A7 cores replaced by Cortex-A53 cores and the MMC controller updated. So we should really share almost the whole .dtsi. In preparation for that move the peripheral parts of the existing sun8i-h3.dtsi into a new sunxi-h3-h5.dtsi. The actual sun8i-h3.dtsi then includes that and defines the H3 specific parts on top of it. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [Icenowy: also split out mmc and gic, as well as pio and ccu's compatible, and make drop of skeleton into a seperated patch] Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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