| Commit message (Expand) | Author | Age | Files | Lines |
* | arm64: Kill detection of VPIPT i-cache policy | Marc Zyngier | 2023-12-05 | 1 | -6/+0 |
* | arm64: allow kmalloc() caches aligned to the smaller cache_line_size() | Catalin Marinas | 2023-06-20 | 1 | -0/+3 |
* | KVM: arm64: Normalize cache configuration | Akihiko Odaki | 2023-01-21 | 1 | -0/+3 |
* | arm64/cache: Move CLIDR macro definitions | Akihiko Odaki | 2023-01-12 | 1 | -0/+6 |
* | arm64: cache: Remove unused CTR_CACHE_MINLINE_MASK | Kristina Martsenko | 2022-09-09 | 1 | -4/+0 |
* | arm64/cache: Fix cache_type_cwg() for register generation | Mark Brown | 2022-08-23 | 1 | -1/+1 |
* | arm64/sysreg: Standardise naming for CTR_EL0 fields | Mark Brown | 2022-07-05 | 1 | -22/+9 |
* | arm64/cache: Restrict which headers are included in __ASSEMBLY__ | Mark Brown | 2022-07-05 | 1 | -6/+5 |
* | arm64/cpuinfo: Remove references to reserved cache type | Mark Brown | 2022-07-05 | 1 | -1/+0 |
* | mm: make minimum slab alignment a runtime property | Peter Collingbourne | 2022-05-13 | 1 | -5/+12 |
* | Revert "arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES)" | Will Deacon | 2021-07-12 | 1 | -1/+1 |
* | arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES) | Will Deacon | 2021-06-01 | 1 | -1/+1 |
* | arm64: kasan: simplify and inline MTE functions | Andrey Konovalov | 2021-02-26 | 1 | -1/+0 |
* | arm64: kasan: align allocations for HW_TAGS | Andrey Konovalov | 2020-12-22 | 1 | -0/+3 |
* | arm64: avoid -Woverride-init warning | Arnd Bergmann | 2020-10-28 | 1 | -0/+1 |
* | treewide: Convert macro and uses of __section(foo) to __section("foo") | Joe Perches | 2020-10-25 | 1 | -1/+1 |
* | arm64: Ask the compiler to __always_inline functions used by KVM at HYP | James Morse | 2020-02-22 | 1 | -1/+1 |
* | arm64: Fake the IminLine size on systems affected by Neoverse-N1 #1542419 | James Morse | 2019-10-25 | 1 | -1/+2 |
* | arm64: prefer __section from compiler_attributes.h | Nick Desaulniers | 2019-08-13 | 1 | -1/+1 |
* | Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/a... | Linus Torvalds | 2019-07-08 | 1 | -1/+4 |
|\ |
|
| * | arm64/mm: Correct the cache line size warning with non coherent device | Masayoshi Mizuma | 2019-06-17 | 1 | -0/+7 |
| * | arm64: cacheinfo: Update cache_line_size detected from DT or PPTT | Shaokun Zhang | 2019-06-04 | 1 | -5/+1 |
* | | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234 | Thomas Gleixner | 2019-06-19 | 1 | -12/+1 |
|/ |
|
* | kasan, arm64: remove redundant ARCH_SLAB_MINALIGN define | Andrey Konovalov | 2019-01-16 | 1 | -2/+0 |
* | kasan, arm64: use ARCH_SLAB_MINALIGN instead of manual aligning | Andrey Konovalov | 2019-01-09 | 1 | -0/+6 |
* | arm64: cpufeature: Fix handling of CTR_EL0.IDC field | Suzuki K Poulose | 2018-10-16 | 1 | -0/+40 |
* | arm64: Fix mismatched cache line size detection | Suzuki K Poulose | 2018-07-05 | 1 | -0/+4 |
* | arm64: Increase ARCH_DMA_MINALIGN to 128 | Catalin Marinas | 2018-05-15 | 1 | -2/+2 |
* | Revert "arm64: Increase the max granular size" | Catalin Marinas | 2018-05-11 | 1 | -1/+1 |
* | Revert "arm64: Revert L1_CACHE_SHIFT back to 6 (64-byte cache line size)" | Will Deacon | 2018-03-27 | 1 | -3/+3 |
* | arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC | Shanker Donthineni | 2018-03-09 | 1 | -0/+4 |
* | arm64: Revert L1_CACHE_SHIFT back to 6 (64-byte cache line size) | Catalin Marinas | 2018-03-06 | 1 | -3/+3 |
* | arm64: cache: Identify VPIPT I-caches | Will Deacon | 2017-03-20 | 1 | -0/+7 |
* | arm64: cache: Merge cachetype.h into cache.h | Will Deacon | 2017-03-20 | 1 | -1/+30 |
* | arm64: Increase the max granular size | Tirumalesh Chalamarla | 2015-10-28 | 1 | -1/+1 |
* | arm64: Implement support for read-mostly sections | Jungseok Lee | 2014-12-03 | 1 | -0/+2 |
* | arm64: Implement cache_line_size() based on CTR_EL0.CWG | Catalin Marinas | 2014-05-09 | 1 | -1/+12 |
* | arm64: Cache maintenance routines | Catalin Marinas | 2012-09-17 | 1 | -0/+32 |