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* MIPS: malta: remove mach-malta/malta-dtshim.h header fileThomas Bogendoerfer2020-09-211-25/+0
* MIPS: malta: remove unused header fileThomas Bogendoerfer2020-09-211-33/+0
* MIPS: Remove mach-*/war.hThomas Bogendoerfer2020-09-071-11/+0
* MIPS: Get rid of BCM1250_M3_WARThomas Bogendoerfer2020-09-071-2/+0
* MIPS: Replace SIBYTE_1956_WAR by CONFIG_SB1_PASS_2_WORKAROUNDSThomas Bogendoerfer2020-09-071-1/+0
* MIPS: Convert MIPS34K_MISSED_ITLB_WAR into a config optionThomas Bogendoerfer2020-09-071-1/+0
* MIPS: Convert R10000_LLSC_WAR info a config optionThomas Bogendoerfer2020-09-071-1/+0
* MIPS: Convert ICACHE_REFILLS_WORKAROUND_WAR into a config optionThomas Bogendoerfer2020-09-071-1/+0
* MIPS: Convert TX49XX_ICACHE_INDEX_INV into a config optionThomas Bogendoerfer2020-09-071-1/+0
* MIPS: Remove MIPS4K_ICACHE_REFILL_WAR and MIPS_CACHE_SYNC_WARThomas Bogendoerfer2020-09-071-2/+0
* MIPS: Convert R4600_V2_HIT_CACHEOP into a config optionThomas Bogendoerfer2020-09-071-1/+0
* MIPS: Convert R4600_V1_HIT_CACHEOP into a config optionThomas Bogendoerfer2020-09-071-1/+0
* MIPS: Convert R4600_V1_INDEX_ICACHEOP into a config optionThomas Bogendoerfer2020-09-071-1/+0
* MIPS: Add header files reference with path prefixbibo mao2020-03-191-1/+1
* MIPS: Remove unused R5432_CP0_INTERRUPT_WARPaul Burton2019-07-231-1/+0
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 182Thomas Gleixner2019-05-301-13/+1
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152Thomas Gleixner2019-05-302-10/+2
* Update MIPS email addressesPaul Burton2017-11-032-2/+2
* License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman2017-11-022-0/+2
* MIPS: Add definitions of SegCtl registers and use themMatt Redfearn2016-05-281-3/+3
* MIPS: Malta: Setup RAM regions via DTPaul Burton2015-11-111-0/+29
* irqchip: mips-gic: Probe for number of external interruptsAndrew Bresticker2014-11-241-1/+0
* MIPS: Malta: EVA: Rename 'eva_entry' to 'platform_eva_init'Markos Chandras2014-08-191-6/+16
* MIPS: GIC: Move GIC_NUM_INTRS into platform irq.hJeffrey Deans2014-08-021-0/+1
* MIPS: Malta: add suspend state entry codePaul Burton2014-05-301-0/+37
* MIPS: MT: Remove SMTC supportRalf Baechle2014-05-241-30/+0
* MIPS: malta: Add support for SMP EVAMarkos Chandras2014-03-261-0/+6
* MIPS: malta: spaces.h: Add spaces.h file for Malta (EVA)Markos Chandras2014-03-261-0/+46
* MIPS: malta: Configure Segment Control registers for EVA bootMarkos Chandras2014-03-261-1/+108
* MIPS: Whitespace cleanup.Ralf Baechle2013-02-013-6/+6
* MIPS: PMC-Sierra Yosemite: Remove support.Ralf Baechle2012-12-131-1/+0
* MIPS: Enable cpu_has_clo_clz for MIPS Technologies' platformsShinya Kuribayashi2011-07-251-0/+2
* MIPS: Malta: Remove pointless use use of CONFIG_CPU_HAS_LLSCRalf Baechle2009-09-171-4/+0
* MIPS: Move headfiles to new location below arch/mips/includeRalf Baechle2008-10-116-0/+225
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