linux - linux

	Commit message (Expand)	Author	Age	Files	Lines
*	MIPS: Remove mach-*/war.h	Thomas Bogendoerfer	2020-09-07	1	-11/+0
*	MIPS: Get rid of BCM1250_M3_WAR	Thomas Bogendoerfer	2020-09-07	1	-14/+0
*	MIPS: Replace SIBYTE_1956_WAR by CONFIG_SB1_PASS_2_WORKAROUNDS	Thomas Bogendoerfer	2020-09-07	1	-2/+0
*	MIPS: Convert MIPS34K_MISSED_ITLB_WAR into a config option	Thomas Bogendoerfer	2020-09-07	1	-2/+0
*	MIPS: Convert R10000_LLSC_WAR info a config option	Thomas Bogendoerfer	2020-09-07	1	-1/+0
*	MIPS: Convert ICACHE_REFILLS_WORKAROUND_WAR into a config option	Thomas Bogendoerfer	2020-09-07	1	-1/+0
*	MIPS: Convert TX49XX_ICACHE_INDEX_INV into a config option	Thomas Bogendoerfer	2020-09-07	1	-1/+0
*	MIPS: Remove MIPS4K_ICACHE_REFILL_WAR and MIPS_CACHE_SYNC_WAR	Thomas Bogendoerfer	2020-09-07	1	-2/+0
*	MIPS: Convert R4600_V2_HIT_CACHEOP into a config option	Thomas Bogendoerfer	2020-09-07	1	-2/+0
*	MIPS: Convert R4600_V1_HIT_CACHEOP into a config option	Thomas Bogendoerfer	2020-09-07	1	-1/+0
*	MIPS: Convert R4600_V1_INDEX_ICACHEOP into a config option	Thomas Bogendoerfer	2020-09-07	1	-1/+0
*	MIPS: Remove unused R5432_CP0_INTERRUPT_WAR	Paul Burton	2019-07-23	1	-1/+0
*	MIPS: SB1: Remove support for Pass 1 parts.	Ralf Baechle	2015-07-14	1	-2/+1
*	MIPS: Whitespace cleanup.	Ralf Baechle	2013-02-01	1	-2/+2
*	MIPS: PMC-Sierra Yosemite: Remove support.	Ralf Baechle	2012-12-13	1	-1/+0
*	MIPS: Sibyte: Apply M3 workaround only on affected chip types and versions.	Ralf Baechle	2010-04-12	1	-1/+5
*	MIPS: Move headfiles to new location below arch/mips/include	Ralf Baechle	2008-10-11	1	-0/+37