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mips
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cpu-probe.c
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Author
Age
Files
Lines
*
Merge tag 'mips_6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Linus Torvalds
2024-01-17
1
-1
/
+1
|
\
|
*
MIPS: Fix typos
Bjorn Helgaas
2024-01-08
1
-1
/
+1
*
|
mips: move cache declarations into header
Arnd Bergmann
2023-12-11
1
-1
/
+0
|
/
*
MIPS: Loongson: Fix cpu_probe_loongson() again
Huacai Chen
2023-07-03
1
-6
/
+3
*
MIPS: Restore Au1300 support
Manuel Lauss
2023-05-23
1
-0
/
+5
*
MIPS: Octeon: Opt-out 4k_cache feature
Jiaxun Yang
2023-04-05
1
-0
/
+2
*
MIPS: Remove VR41xx support
Thomas Bogendoerfer
2022-07-14
1
-40
/
+0
*
MIPS: fix typos in comments
Julia Lawall
2022-05-04
1
-1
/
+1
*
MIPS: Remove TX39XX support
Thomas Bogendoerfer
2022-03-01
1
-23
/
+0
*
MIPS: loongson64: fix FTLB configuration
Huang Pei
2021-11-25
1
-2
/
+2
*
MIPS: Remove NETLOGIC support
Thomas Bogendoerfer
2021-10-24
1
-84
/
+0
*
MIPS: cpu-probe: Fix FPU detection on Ingenic JZ4760(B)
Paul Cercueil
2021-06-01
1
-0
/
+5
*
MIPS: Loongson64: Use _CACHE_UNCACHED instead of _CACHE_UNCACHED_ACCELERATED
Tiezhu Yang
2021-04-06
1
-3
/
+0
*
MIPS: kernel: Reserve exception base early to prevent corruption
Thomas Bogendoerfer
2021-03-09
1
-0
/
+6
*
Revert "MIPS: Remove unused R4300 CPU support"
Lauri Kasanen
2021-01-22
1
-0
/
+9
*
MIPS: Ingenic: Disable HPTLB for D0 XBurst CPUs too
Paul Cercueil
2021-01-18
1
-7
/
+8
*
MIPS: cpu-probe: remove MIPS_CPU_BP_GHIST option bit
Thomas Bogendoerfer
2020-10-12
1
-6
/
+4
*
MIPS: cpu-probe: move fpu probing/handling into its own file
Thomas Bogendoerfer
2020-10-12
1
-324
/
+2
*
MIPS: cpu-probe: ingenic: Fix broken BUG_ON
Paul Cercueil
2020-09-18
1
-1
/
+1
*
MIPS: cpu-probe: Mark XBurst CPU as having vtagged caches
Paul Cercueil
2020-09-18
1
-0
/
+3
*
MIPS: cpu-probe: Set Ingenic's writecombine to _CACHE_CACHABLE_WA
Paul Cercueil
2020-09-18
1
-1
/
+2
*
MIPS: handle Loongson-specific GSExc exception
WANG Xuerui
2020-07-31
1
-0
/
+3
*
MIPS: only register FTLBPar exception handler for supported models
WANG Xuerui
2020-07-31
1
-0
/
+13
*
MIPS: X2000: Add X2000 system type.
周琰杰 (Zhou Yanjie)
2020-07-24
1
-0
/
+11
*
MIPS: Unify naming style of vendor CP0.Config6 bits
Huacai Chen
2020-07-08
1
-6
/
+6
*
KVM: MIPS: Enable KVM support for Loongson-3
Huacai Chen
2020-06-04
1
-0
/
+1
*
KVM: MIPS: Introduce and use cpu_guest_has_ldpte
Huacai Chen
2020-06-04
1
-1
/
+3
*
MIPS: emulate CPUCFG instruction on older Loongson64 cores
WANG Xuerui
2020-05-24
1
-0
/
+9
*
MIPS: Tidy up CP0.Config6 bits definition
Huacai Chen
2020-05-24
1
-6
/
+6
*
mips: Add CP0 Write Merge config support
Serge Semin
2020-05-22
1
-0
/
+48
*
mips: Add MIPS Release 5 support
Serge Semin
2020-05-22
1
-0
/
+17
*
MIPS: Use fallthrough for arch/mips
Liangliang Huang
2020-05-07
1
-11
/
+11
*
MIPS: Loongson64: Correct TLB type for Loongson-3 Classic
Jiaxun Yang
2020-05-02
1
-1
/
+4
*
MIPS: Loongson64: Probe CPU features via CPUCFG
Jiaxun Yang
2020-04-30
1
-8
/
+37
*
MIPS: Kernel: Identify Loongson-2K processors
Jiaxun Yang
2020-04-26
1
-1
/
+18
*
Use ELF_BASE_PLATFORM to pass ISA level
YunQiang Su
2020-03-19
1
-0
/
+18
*
MIPS: Add MAC2008 Support
Jiaxun Yang
2020-01-23
1
-1
/
+15
*
MIPS: X1830: Add X1830 system type.
周琰杰 (Zhou Yanjie)
2020-01-09
1
-29
/
+36
*
MIPS: Ingenic: Disable abandoned HPTLB function.
Zhou Yanjie
2019-11-22
1
-2
/
+19
*
MIPS: Loongson: Rename LOONGSON1 to LOONGSON32
Huacai Chen
2019-11-11
1
-1
/
+1
*
Merge tag 'mips_fixes_5.4_3' into mips-next
Paul Burton
2019-11-01
1
-0
/
+33
|
\
|
*
MIPS: elf_hwcap: Export userspace ASEs
Jiaxun Yang
2019-10-10
1
-0
/
+33
*
|
MIPS: Loongson64: Rename CPU TYPES
Jiaxun Yang
2019-10-31
1
-8
/
+8
*
|
MIPS: Loongson: Add Loongson-3A R4 basic support
Huacai Chen
2019-10-07
1
-2
/
+14
|
/
*
MIPS: Treat Loongson Extensions as ASEs
Jiaxun Yang
2019-08-26
1
-0
/
+6
*
MIPS: Ingenic: Disable broken BTB lookup optimization.
Zhou Yanjie
2019-08-06
1
-0
/
+7
*
MIPS: Remove unused R8000 CPU support
Paul Burton
2019-07-23
1
-9
/
+0
*
MIPS: Remove unused R5432 CPU support
Paul Burton
2019-07-23
1
-8
/
+0
*
MIPS: Remove unused R4300 CPU support
Paul Burton
2019-07-23
1
-9
/
+0
*
MIPS: Decode config3 register on Ingenic SoCs
Paul Cercueil
2019-07-22
1
-0
/
+8
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