Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | MIPS: Loongson1B: Change the OSC clock name | Kelvin Cheung | 2017-01-03 | 1 | -1/+1 |
* | MIPS: Loongson1: Add watchdog support for Loongson1 board | Yang Ling | 2017-01-03 | 3 | -6/+24 |
* | MIPS: Loongson1: Remove several redundant RTC-related macros | Yang Ling | 2017-01-03 | 1 | -16/+11 |
* | clocksource: Use a plain u64 instead of cycle_t | Thomas Gleixner | 2016-12-25 | 1 | -2/+2 |
* | MIPS: Add RTC support for Loongson1C board | Yang Ling | 2016-10-04 | 3 | -6/+18 |
* | MIPS: Loongson1C: Add board support | Yang Ling | 2016-10-04 | 8 | -3/+130 |
* | MIPS: Loongson1B: Some updates/fixes for LS1B | Kelvin Cheung | 2016-05-13 | 4 | -28/+184 |
* | MIPS: loongsoon32: Migrate to new 'set-state' interface | Viresh Kumar | 2015-09-03 | 1 | -23/+34 |
* | MIPS: Loongson: Naming style cleanup and rework | Huacai Chen | 2015-06-21 | 12 | -0/+894 |