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path: root/arch/mips/mm/c-r4k.c (follow)
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* mips: add support for folded p4d page tablesMike Rapoport2019-11-221-1/+3
* MIPS: Loongson64: Rename CPU TYPESJiaxun Yang2019-10-311-16/+16
* MIPS: Provide unroll() macro, use it for cache opsPaul Burton2019-10-091-4/+8
* MIPS: Loongson: Add Loongson-3A R4 basic supportHuacai Chen2019-10-071-1/+2
* MIPS: Remove unused R5432 CPU supportPaul Burton2019-07-231-1/+0
* MIPS: Remove unused R4300 CPU supportPaul Burton2019-07-231-1/+0
* MIPS: Delete unused flush_cache_sigtramp()Paul Burton2019-02-071-116/+0
* MIPS: MemoryMapID (MMID) SupportPaul Burton2019-02-041-0/+3
* MIPS: mm: Consolidate drop_mmu_context() has-ASID checksPaul Burton2019-02-041-4/+1
* MIPS: mm: Remove redundant drop_mmu_context() cpu argumentPaul Burton2019-02-041-1/+1
* mips: annotate implicit fall throughsMathieu Malaterre2018-12-031-0/+2
* MIPS: c-r4k: Add r4k_blast_scache_node for Loongson-3Huacai Chen2018-11-211-7/+37
* MIPS: Loongson: Add Loongson-3A R2.1 basic supportHuacai Chen2018-11-201-1/+1
* MIPS: don't select DMA_MAYBE_COHERENT from DMA_PERDEV_COHERENTChristoph Hellwig2018-09-201-9/+8
* MIPS: WARN_ON invalid DMA cache maintenance, not BUG_ONPaul Burton2018-07-261-2/+4
* MIPS: Set MIPS_IC_SNOOPS_REMOTE for systems with CMPaul Burton2018-06-241-0/+8
* MIPS: simplify CONFIG_DMA_NONCOHERENT ifdefsChristoph Hellwig2018-06-241-2/+2
* MIPS: c-r4k: Fix data corruption related to cache coherenceNeilBrown2018-05-151-3/+6
* MIPS: CPS: Have asm/mips-cps.h include CM & CPC headersPaul Burton2017-08-301-1/+1
* MIPS: Probe the I6500 CPUPaul Burton2017-06-281-0/+2
* MIPS: c-r4k: Fix Loongson-3's vcache/scache waysize calculationHuacai Chen2017-03-211-0/+2
* MIPS: c-r4k: Treat physically indexed dcaches as not aliasingPaul Burton2017-01-031-0/+4
* MIPS: c-r4k: Treat I6400 dcache as though physically indexedPaul Burton2017-01-031-1/+1
* MIPS: Support per-device DMA coherencePaul Burton2016-10-061-0/+4
* MIPS: Sanitise coherentio semanticsPaul Burton2016-10-061-1/+2
* MIPS: mm: Audit and remove any unnecessary uses of module.hPaul Gortmaker2016-10-051-1/+1
* MIPS: c-r4k: Fix flush_icache_range() for EVAJames Hogan2016-10-051-8/+35
* MIPS: c-r4k: Split user/kernel flush_icache_range()James Hogan2016-10-041-0/+2
* MIPS: c-r4k: Drop bc_wback_inv() from icache flushJames Hogan2016-10-041-11/+0
* MIPS: c-r4k: Fix size calc when avoiding IPIs for small icache flushesPaul Burton2016-09-131-1/+1
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2016-08-061-57/+227
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| * MIPS: c-r4k: Use SMP calls for CM indexed cache opsJames Hogan2016-07-291-1/+1
| * MIPS: c-r4k: Avoid small flush_icache_range SMP callsJames Hogan2016-07-291-0/+21
| * MIPS: c-r4k: Local flush_icache_range cache op overrideJames Hogan2016-07-291-6/+18
| * MIPS: c-r4k: Split r4k_flush_kernel_vmap_range()James Hogan2016-07-291-8/+17
| * MIPS: c-r4k: Exclude sibling CPUs in SMP callsJames Hogan2016-07-291-4/+13
| * MIPS: c-r4k: Fix valid ASID optimisationJames Hogan2016-07-291-13/+35
| * MIPS: c-r4k: Add r4k_on_each_cpu cache op type argJames Hogan2016-07-291-19/+51
| * MIPS: c-r4k: Avoid dcache flush for sigtrampsJames Hogan2016-07-291-6/+10
| * MIPS: c-r4k: Fix sigtramp SMP call to use kmapJames Hogan2016-07-291-6/+69
| * MIPS: SMP: Clear ASID without confusing has_valid_asid()James Hogan2016-07-291-0/+4
| * MIPS: Remove cpu_has_safe_index_cacheopsRalf Baechle2016-07-061-9/+3
* | MIPS: Add define for Config.VI (virtual icache) bitJames Hogan2016-06-151-1/+1
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* MIPS: remove aliasing alignment if HW has antialising supportLeonid Yegoshin2016-05-131-1/+1
* MIPS: Loongson-3: Introduce CONFIG_LOONGSON3_ENHANCEMENTHuacai Chen2016-05-131-0/+2
* MIPS: Loongson-3: Set cache flush handlers to cache_noopHuacai Chen2016-05-131-0/+14
* MIPS: Loongson: Add Loongson-3A R2 basic supportHuacai Chen2016-05-131-0/+27
* MIPS: BMIPS: local_r4k___flush_cache_all needs to blast S-cacheFlorian Fainelli2016-05-131-0/+5
* MIPS: BMIPS: Clear MIPS_CACHE_ALIASES earlierFlorian Fainelli2016-05-131-2/+2
* MIPS: BMIPS: BMIPS5000 has I cache filing from D cacheFlorian Fainelli2016-05-131-0/+4
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