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* riscv: errata: Add Andes alternative portsLad Prabhakar2023-09-011-0/+1
* riscv: Fix relocatable kernels with early alternatives using -fno-pieAlexandre Ghiti2023-05-311-0/+4
* riscv: add memory-type errata for T-HeadHeiko Stuebner2022-05-121-0/+1
* riscv: integrate alternatives better into the main architectureHeiko Stuebner2022-05-121-1/+0
* riscv: sifive: Add SiFive alternative portsVincent Chen2021-04-261-0/+1
* riscv: Introduce alternative mechanism to apply errata solutionVincent Chen2021-04-261-0/+1