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* riscv: errata: sifive: Use SYM_*() assembly macrosJisheng Zhang2024-09-151-4/+4
* riscv: Extend cpufeature.c to detect vendor extensionsCharlie Jenkins2024-07-233-0/+9
* Merge tag 'riscv-for-linus-6.10-mw1' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2024-05-221-0/+5
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| * riscv: Avoid TLB flush loops when affected by SiFive CIP-1200Samuel Holland2024-04-291-0/+5
* | Merge patch series "RISC-V: Test th.sxstatus.MAEE bit before enabling MAEE"Palmer Dabbelt2024-04-261-9/+15
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| * riscv: T-Head: Test availability bit before enabling MAE errataChristoph Müllner2024-04-251-4/+10
| * riscv: thead: Rename T-Head PBMT to MAEChristoph Müllner2024-04-251-5/+5
* | riscv: errata: Rename defines for AndesYu Chien Peter Lin2024-03-121-5/+5
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* Merge patch series "riscv: errata: thead: use riscv_nonstd_cache_ops for CMO"Palmer Dabbelt2024-01-111-2/+67
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| * riscv: errata: thead: use pa based instructions for CMOJisheng Zhang2024-01-101-12/+6
| * riscv: errata: thead: use riscv_nonstd_cache_ops for CMOJisheng Zhang2024-01-101-2/+73
* | riscv: errata: andes: Probe for IOCP only once in boot stageLad Prabhakar2023-12-061-7/+13
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* riscv: errata: andes: Makefile: Fix randconfig build issueLad Prabhakar2023-09-271-0/+4
* Merge patch series "Add non-coherent DMA support for AX45MP"Palmer Dabbelt2023-09-083-0/+68
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| * riscv: errata: Add Andes alternative portsLad Prabhakar2023-09-013-0/+68
* | RISC-V: alternative: Remove feature_probe_funcEvan Green2023-09-011-8/+0
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* Merge patch series "riscv: some CMO alternative related clean up"Palmer Dabbelt2023-07-061-2/+5
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| * riscv: errata: thead: only set cbom size & noncoherent during bootJisheng Zhang2023-07-061-2/+5
* | riscv: Fix relocatable kernels with early alternatives using -fno-pieAlexandre Ghiti2023-05-311-0/+4
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* RISC-V: fix sifive and thead section mismatches in errataRandy Dunlap2023-04-292-8/+6
* Merge tag 'riscv-for-linus-6.4-mw1' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2023-04-292-6/+16
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| * RISC-V: hwprobe: Remove __init on probe_vendor_features()Evan Green2023-04-261-3/+3
| * Merge patch series "RISC-V Hardware Probing User Interface"Palmer Dabbelt2023-04-191-0/+10
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| | * RISC-V: hwprobe: Support probing of misaligned access performanceEvan Green2023-04-191-0/+10
| * | riscv: alternatives: Rename errata_id to patch_idAndrew Jones2023-03-152-5/+5
| * | riscv: alternatives: Remove unnecessary define and unused structAndrew Jones2023-03-151-1/+1
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* / RISC-V: fix taking the text_mutex twice during sifive errata patchingConor Dooley2023-03-071-1/+1
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* RISC-V: take text_mutex during alternative patchingConor Dooley2023-02-222-2/+9
* riscv: Fix early alternative patchingSamuel Holland2023-02-151-3/+1
* riscv: switch to relative alternative entriesJisheng Zhang2023-02-012-4/+10
* drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx coresHeiko Stuebner2022-10-271-0/+19
* Merge patch series "Some style cleanups for recent extension additions"Palmer Dabbelt2022-10-131-6/+8
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| * riscv: check for kernel config option in t-head memory types errataHeiko Stuebner2022-10-131-0/+3
| * riscv: use BIT() macros in t-head errata initHeiko Stuebner2022-10-131-2/+2
| * riscv: drop some idefs from CMO initializationHeiko Stuebner2022-10-131-4/+3
* | RISC-V: Clean up the Zicbom block size probingPalmer Dabbelt2022-09-131-0/+1
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* riscv: implement Zicbom-based CMO instructions + the t-head variantPalmer Dabbelt2022-08-111-0/+20
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| * riscv: implement cache-management errata for T-Head SoCsHeiko Stuebner2022-08-041-0/+20
* | Merge tag 'riscv-for-linus-5.20-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2022-08-071-26/+12
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| * riscv: remove usage of function-pointers from cpufeatures and t-head errataHeiko Stuebner2022-06-171-26/+12
* | riscv: don't warn for sifive erratas in modulesHeiko Stuebner2022-07-081-1/+2
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* riscv: add memory-type errata for T-HeadHeiko Stuebner2022-05-124-1/+100
* riscv: implement module alternativesHeiko Stuebner2022-05-121-5/+9
* riscv: allow different stages with alternativesHeiko Stuebner2022-05-121-1/+2
* riscv: integrate alternatives better into the main architectureHeiko Stuebner2022-05-122-76/+0
* riscv: errata: alternative: mark vendor_patch_func __initdataJisheng Zhang2022-01-091-1/+2
* riscv: skip errata_cip_453.o if CONFIG_ERRATA_SIFIVE_CIP_453 is disabledVincent2021-06-021-1/+1
* riscv: sifive: Apply errata "cip-1200" patchVincent Chen2021-04-261-0/+18
* riscv: sifive: Apply errata "cip-453" patchVincent Chen2021-04-263-0/+59
* riscv: sifive: Add SiFive alternative portsVincent Chen2021-04-264-0/+75
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