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path: root/arch/riscv/include/asm/cacheflush.h (follow)
Commit message (Expand)AuthorAgeFilesLines
* mm: Introduce flush_cache_vmap_early()Alexandre Ghiti2023-12-141-1/+2
* Merge tag 'riscv-for-linus-6.6-mw1' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2023-09-011-0/+2
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| * riscv: allow kmalloc() caches aligned to the smallest valueJisheng Zhang2023-08-231-0/+2
* | Merge tag 'mm-stable-2023-08-28-18-26' of git://git.kernel.org/pub/scm/linux/...Linus Torvalds2023-08-291-10/+9
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| * | riscv: implement the new page table range APIMatthew Wilcox (Oracle)2023-08-251-10/+9
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* / riscv: Implement flush_cache_vmap()Alexandre Ghiti2023-08-101-0/+4
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* RISC-V: Add Zicboz detection and block size parsingAndrew Jones2023-03-151-1/+2
* Merge patch series "RISC-V: Ensure Zicbom has a valid block size"Palmer Dabbelt2022-12-101-8/+0
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| * RISC-V: Fix compilation without RISCV_ISA_ZICBOMAndrew Jones2022-10-211-8/+0
* | riscv/mm: hugepage's PG_dcache_clean flag is only set in head pageTong Tiangen2022-12-021-0/+7
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* Merge patch series "Some style cleanups for recent extension additions"Palmer Dabbelt2022-10-131-0/+2
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| * riscv: drop some idefs from CMO initializationHeiko Stuebner2022-10-131-0/+2
* | RISC-V: Avoid coupling the T-Head CMOs and ZicbomPalmer Dabbelt2022-09-171-1/+5
* | RISC-V: Clean up the Zicbom block size probingPalmer Dabbelt2022-09-131-0/+1
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* riscv: Add support for non-coherent devices using zicbom extensionHeiko Stuebner2022-07-291-0/+10
* mm: rename flush_icache_user_range to flush_icache_user_pageChristoph Hellwig2020-06-081-1/+2
* riscv: use asm-generic/cacheflush.hChristoph Hellwig2020-06-081-59/+3
* riscv: Use flush_icache_mm for flush_icache_user_rangeGuo Ren2020-03-031-1/+1
* riscv: fix build break after macro-to-function conversion in generic cacheflu...Paul Walmsley2019-07-181-4/+59
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner2019-06-051-9/+1
* riscv: move flush_icache_{all,mm} to cacheflush.cGary Guo2019-05-171-1/+1
* riscv: use NULL instead of a plain 0Luc Van Oostenryck2018-06-071-1/+1
* RISC-V: Allow userspace to flush the instruction cacheAndrew Waterman2017-11-301-0/+6
* RISC-V: Flush I$ when making a dirty page executableAndrew Waterman2017-11-301-4/+20
* RISC-V: Atomic and Locking CodePalmer Dabbelt2017-09-271-0/+39
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