linux - linux

	Commit message (Expand)	Author	Age	Files	Lines
*	Merge tag 'riscv-for-linus-5.13-mw0' of git://git.kernel.org/pub/scm/linux/ke...	Linus Torvalds	2021-05-06	1	-0/+3
\|\
\| *	riscv: Add 3 SBI wrapper functions to get cpu manufacturer information	Vincent Chen	2021-04-26	1	-0/+3
* \|	RISC-V: correct enum sbi_ext_rfence_fid	Heinrich Schuchardt	2021-03-10	1	-2/+2
\|/
*	RISC-V: Add a non-void return for sbi v02 functions	Atish Patra	2021-02-23	1	-5/+5
*	riscv: Cleanup sbi function stubs when RISCV_SBI disabled	Kefeng Wang	2021-01-08	1	-7/+3
*	RISC-V: Add SBI HSM extension definitions	Atish Patra	2020-03-31	1	-0/+14
*	RISC-V: Export SBI error to linux error mapping function	Atish Patra	2020-03-31	1	-0/+2
*	RISC-V: Implement new SBI v0.2 extensions	Atish Patra	2020-03-31	1	-0/+14
*	RISC-V: Introduce a new config for SBI v0.1	Atish Patra	2020-03-31	1	-0/+2
*	RISC-V: Add SBI v0.2 extension definitions	Atish Patra	2020-03-31	1	-0/+21
*	RISC-V: Add basic support for SBI v0.2	Atish Patra	2020-03-31	1	-71/+68
*	RISC-V: Mark existing SBI as 0.1 SBI.	Atish Patra	2020-03-31	1	-19/+22
*	riscv: provide native clint access for M-mode	Christoph Hellwig	2019-11-18	1	-0/+2
*	riscv: add support for MMIO access to the timer registers	Christoph Hellwig	2019-11-13	1	-1/+2
*	riscv: implement remote sfence.i using IPIs	Christoph Hellwig	2019-11-13	1	-0/+3
*	riscv: poison SBI calls for M-mode	Christoph Hellwig	2019-11-13	1	-2/+3
*	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286	Thomas Gleixner	2019-06-05	1	-9/+1
*	riscv: fix sbi_remote_sfence_vma{,_asid}.	Gary Guo	2019-05-17	1	-7/+12
*	RISC-V: Device, timer, IRQs, and the SBI	Palmer Dabbelt	2017-09-27	1	-0/+100