summaryrefslogtreecommitdiffstats
path: root/arch/riscv/include/asm/sbi.h (follow)
Commit message (Expand)AuthorAgeFilesLines
* RISC-V: Align SBI probe implementation with specAndrew Jones2023-04-291-1/+1
* RISC-V: Treat IPIs as normal Linux IRQsAnup Patel2023-04-081-2/+7
* RISC-V: Improve SBI PMU extension related definitionsAtish Patra2023-02-071-2/+5
* RISC-V: Cache SBI vendor valuesHeiko Stuebner2022-10-271-0/+5
* RISC-V: Improve SBI definitionsAtish Patra2022-08-111-2/+16
* RISC-V: Move counter info definition to sbi header fileAtish Patra2022-08-111-0/+14
* Merge tag 'riscv-for-linus-5.18-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2022-03-251-0/+95
|\
| * RISC-V: Add RISC-V SBI PMU extension definitionsAtish Patra2022-03-211-0/+95
* | RISC-V: Add SBI HSM suspend related definesAnup Patel2022-03-111-5/+22
|/
* RISC-V: Do not use cpumask data structure for hartid bitmapAtish Patra2022-01-201-9/+10
* Merge tag 'riscv-for-linus-5.17-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2022-01-191-0/+24
|\
| * RISC-V: Use SBI SRST extension when availableAnup Patel2022-01-111-0/+24
* | RISC-V: KVM: Add SBI HSM extension in KVMAtish Patra2022-01-061-0/+1
* | RISC-V: KVM: Add SBI v0.2 base extensionAtish Patra2022-01-061-0/+8
|/
* Merge tag 'riscv-for-linus-5.13-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2021-05-061-0/+3
|\
| * riscv: Add 3 SBI wrapper functions to get cpu manufacturer informationVincent Chen2021-04-261-0/+3
* | RISC-V: correct enum sbi_ext_rfence_fidHeinrich Schuchardt2021-03-101-2/+2
|/
* RISC-V: Add a non-void return for sbi v02 functionsAtish Patra2021-02-231-5/+5
* riscv: Cleanup sbi function stubs when RISCV_SBI disabledKefeng Wang2021-01-081-7/+3
* RISC-V: Add SBI HSM extension definitionsAtish Patra2020-03-311-0/+14
* RISC-V: Export SBI error to linux error mapping functionAtish Patra2020-03-311-0/+2
* RISC-V: Implement new SBI v0.2 extensionsAtish Patra2020-03-311-0/+14
* RISC-V: Introduce a new config for SBI v0.1Atish Patra2020-03-311-0/+2
* RISC-V: Add SBI v0.2 extension definitionsAtish Patra2020-03-311-0/+21
* RISC-V: Add basic support for SBI v0.2Atish Patra2020-03-311-71/+68
* RISC-V: Mark existing SBI as 0.1 SBI.Atish Patra2020-03-311-19/+22
* riscv: provide native clint access for M-modeChristoph Hellwig2019-11-181-0/+2
* riscv: add support for MMIO access to the timer registersChristoph Hellwig2019-11-131-1/+2
* riscv: implement remote sfence.i using IPIsChristoph Hellwig2019-11-131-0/+3
* riscv: poison SBI calls for M-modeChristoph Hellwig2019-11-131-2/+3
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner2019-06-051-9/+1
* riscv: fix sbi_remote_sfence_vma{,_asid}.Gary Guo2019-05-171-7/+12
* RISC-V: Device, timer, IRQs, and the SBIPalmer Dabbelt2017-09-271-0/+100
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-30 23:45:55 +0100