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path: root/arch/riscv/include/asm/tlbflush.h (follow)
Commit message (Expand)AuthorAgeFilesLines
* riscv: mm: Use a fixed layout for the MM context IDSamuel Holland2024-04-291-2/+0
* riscv: Avoid TLB flush loops when affected by SiFive CIP-1200Samuel Holland2024-04-291-0/+2
* riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vmaSamuel Holland2024-04-291-1/+18
* riscv: mm: Combine the SMP and UP TLB flush codeSamuel Holland2024-04-291-28/+3
* riscv: mm: execute local TLB flush after populating vmemmapVincent Chen2024-01-311-0/+1
* Merge tag 'riscv-for-linus-6.8-mw4' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2024-01-201-0/+8
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| * riscv: Add support for BATCHED_UNMAP_TLB_FLUSHAlexandre Ghiti2024-01-111-0/+8
* | mm: Introduce flush_cache_vmap_early()Alexandre Ghiti2023-12-141-0/+1
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* riscv: Improve flush_tlb_kernel_range()Alexandre Ghiti2023-11-061-5/+6
* riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlbAlexandre Ghiti2023-11-061-0/+3
* riscv: Improve tlb_flush()Alexandre Ghiti2023-11-061-0/+3
* riscv: mm: Fix incorrect ASID argument when flushing TLBDylan Jhong2023-03-211-0/+2
* Revert "riscv: mm: notify remote harts about mmu cache updates"Sergey Matyukevich2023-03-101-18/+0
* riscv: mm: notify remote harts about mmu cache updatesSergey Matyukevich2022-12-091-0/+18
* riscv: fix build error when CONFIG_SMP is disabledBixuan Cui2021-06-091-0/+5
* riscv: sifive: Apply errata "cip-1200" patchVincent Chen2021-04-261-1/+2
* riscv: add nommu supportChristoph Hellwig2019-11-181-3/+9
* riscv: tlbflush: remove confusing comment on local_flush_tlb_all()Paul Walmsley2019-10-141-4/+0
* riscv: move the TLB flush logic out of lineChristoph Hellwig2019-09-051-30/+7
* riscv: cleanup riscv_cpuid_to_hartid_maskChristoph Hellwig2019-09-051-1/+0
* riscv: fix flush_tlb_range() end address for flush_tlb_page()Paul Walmsley2019-08-131-2/+9
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner2019-06-051-9/+1
* RISC-V: Use Linux logical CPU number instead of hartidAtish Patra2018-10-231-3/+13
* riscv: use NULL instead of a plain 0Luc Van Oostenryck2018-06-071-1/+1
* RISC-V: Limit the scope of TLB shootdownsAndrew Waterman2018-01-311-8/+12
* riscv: remove CONFIG_MMU ifdefsChristoph Hellwig2018-01-081-4/+0
* RISC-V: User-Visible ChangesPalmer Dabbelt2017-12-011-0/+2
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| * RISC-V: Flush I$ when making a dirty page executableAndrew Waterman2017-11-301-0/+2
* | RISC-V: `sfence.vma` orderes the instruction cachePalmer Dabbelt2017-11-281-1/+4
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* RISC-V: Atomic and Locking CodePalmer Dabbelt2017-09-271-0/+64
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