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* riscv: Less inefficient gcc tishift helpers (and export their symbols)Olof Johansson2020-01-191-0/+4
* riscv: move sifive_l2_cache.h to include/socYash Shah2020-01-121-16/+0
* riscv: prefix IRQ_ macro names with an RV_ namespacePaul Walmsley2020-01-051-9/+9
* riscv: define vmemmap before pfn_to_page callsDavid Abdurachmanov2019-12-201-17/+21
* Merge tag 'pci-v5.5-changes' of git://git.kernel.org/pub/scm/linux/kernel/git...Linus Torvalds2019-12-031-1/+0
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| * asm-generic: Make msi.h a mandatory include/asm headerMichal Simek2019-11-261-1/+0
* | Merge tag 'ioremap-5.5' of git://git.infradead.org/users/hch/ioremapLinus Torvalds2019-11-282-14/+7
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| * | riscv: use the generic ioremap codeChristoph Hellwig2019-11-112-3/+6
| * | arch: rely on asm-generic/io.h for default ioremap_* definitionsChristoph Hellwig2019-11-111-10/+0
* | | Merge branch 'next/nommu' into for-nextPaul Walmsley2019-11-2320-226/+417
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| * | | riscv: add nommu supportChristoph Hellwig2019-11-1812-49/+102
| * | | riscv: clear the instruction cache and all registers when bootingChristoph Hellwig2019-11-181-0/+1
| * | | riscv: read the hart ID from mhartid on bootDamien Le Moal2019-11-181-0/+1
| * | | riscv: provide native clint access for M-modeChristoph Hellwig2019-11-182-0/+41
| * | | riscv: add support for MMIO access to the timer registersChristoph Hellwig2019-11-132-3/+19
| * | | riscv: implement remote sfence.i using IPIsChristoph Hellwig2019-11-131-0/+3
| * | | riscv: poison SBI calls for M-modeChristoph Hellwig2019-11-131-2/+3
| * | | riscv: abstract out CSR names for supervisor vs machine modeChristoph Hellwig2019-11-055-30/+82
| * | | riscv: separate MMIO functions into their own header filePaul Walmsley2019-11-052-144/+167
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* | | Merge branch 'next/misc' into for-nextPaul Walmsley2019-11-2312-24/+31
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| * | | riscv: clean up the macro format in each header fileZong Li2019-11-1212-24/+31
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* / / riscv: add support for SECCOMP and SECCOMP_FILTERDavid Abdurachmanov2019-10-292-1/+14
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* | RISC-V: Add PCIe I/O BAR memory mappingYash Shah2019-10-282-1/+13
* | riscv: add missing header file includesPaul Walmsley2019-10-282-0/+4
* | riscv: cleanup <asm/bug.h>Christoph Hellwig2019-10-231-13/+3
* | riscv: Fix implicit declaration of 'page_to_section'Kefeng Wang2019-10-231-4/+1
* | riscv: fix fs/proc/kcore.c compilation with sparsemem enabledDavid Abdurachmanov2019-10-231-2/+0
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* RISC-V: fix virtual address overlapped in FIXADDR_START and VMEMMAP_STARTGreentime Hu2019-10-161-8/+8
* riscv: tlbflush: remove confusing comment on local_flush_tlb_all()Paul Walmsley2019-10-141-4/+0
* RISC-V: Clear load reservations while restoring hart contextsPalmer Dabbelt2019-10-011-0/+1
* Merge tag 'riscv/for-v5.4-rc1-b' of git://git.kernel.org/pub/scm/linux/kernel...Linus Torvalds2019-09-271-12/+12
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| * RISC-V: Fix building error when CONFIG_SPARSEMEM_MANUAL=yGreentime Hu2019-09-191-12/+12
* | mm: treewide: clarify pgtable_page_{ctor,dtor}() namingMark Rutland2019-09-261-1/+1
* | mm: consolidate pgtable_cache_init() and pgd_cache_init()Mike Rapoport2019-09-251-5/+0
* | mm: remove quicklist page table cachesNicholas Piggin2019-09-251-4/+0
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* Merge tag 'riscv/for-v5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g...Linus Torvalds2019-09-176-60/+54
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| * riscv: move the TLB flush logic out of lineChristoph Hellwig2019-09-051-30/+7
| * riscv: don't use the rdtime(h) pseudo-instructionsChristoph Hellwig2019-09-051-23/+21
| * riscv: cleanup riscv_cpuid_to_hartid_maskChristoph Hellwig2019-09-052-7/+0
| * RISC-V: Implement sparsememLogan Gunthorpe2019-08-303-0/+26
* | riscv: modify the Image header to improve compatibility with the ARM64 headerPaul Walmsley2019-09-141-6/+6
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* RISC-V: Fix FIXMAP area corruption on RV32 systemsAnup Patel2019-08-292-6/+10
* riscv: Make __fstate_clean() work correctly.Vincent Chen2019-08-141-1/+1
* riscv: Correct the initialized flow of FP registerVincent Chen2019-08-141-0/+6
* riscv: fix flush_tlb_range() end address for flush_tlb_page()Paul Walmsley2019-08-131-2/+9
* riscv: include generic support for MSI irqdomainsWesley Terpstra2019-07-221-0/+1
* Merge tag 'riscv/for-v5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g...Linus Torvalds2019-07-187-10/+176
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| * riscv: fix build break after macro-to-function conversion in generic cacheflu...Paul Walmsley2019-07-181-4/+59
| * RISC-V: Add an Image header that boot loader can parse.Atish Patra2019-07-111-0/+65
| * RISC-V: Setup initial page tables in two stagesAnup Patel2019-07-093-0/+18
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