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path: root/arch/riscv/kernel/cpu.c (follow)
Commit message (Expand)AuthorAgeFilesLines
* riscv: Add vendor extensions to /proc/cpuinfoCharlie Jenkins2024-07-231-3/+32
* riscv: cpufeature: Fix thead vector hwcap removalCharlie Jenkins2024-05-221-4/+36
* Merge patch series "Linux RISC-V AIA Preparatory Series"Palmer Dabbelt2023-11-091-5/+6
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| * RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTsAnup Patel2023-11-091-5/+6
* | RISC-V: Show accurate per-hart isa in /proc/cpuinfoEvan Green2023-11-081-4/+18
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* Merge tag 'riscv-for-linus-6.6-mw1' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2023-09-011-118/+63
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| * RISC-V: cpu: refactor deprecated strncpyJustin Stitt2023-08-021-6/+6
| * RISC-V: provide Kconfig & commandline options to control parsing "riscv,isa"Conor Dooley2023-07-261-1/+7
| * RISC-V: try new extension properties in of_early_processor_hartid()Conor Dooley2023-07-261-1/+28
| * RISC-V: add single letter extensions to riscv_isa_extConor Dooley2023-07-261-26/+11
| * RISC-V: repurpose riscv_isa_ext array in riscv_fill_hwcap()Conor Dooley2023-07-261-2/+3
| * RISC-V: shunt isa_ext_arr to cpufeature.cConor Dooley2023-07-261-73/+2
| * RISC-V: drop a needless check in print_isa_ext()Conor Dooley2023-07-261-4/+0
| * RISC-V: don't parse dt/acpi isa string to get rv32/rv64Heiko Stuebner2023-07-261-12/+9
| * RISC-V: Provide a more helpful error message on invalid ISA stringsPalmer Dabbelt2023-07-261-2/+6
* | riscv: Fix CPU feature detection with SMP disabledSamuel Holland2023-08-091-0/+5
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* Merge patch series "ISA string parser cleanups"Palmer Dabbelt2023-06-231-4/+30
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| * RISC-V: always report presence of extensions formerly part of the base ISAConor Dooley2023-06-211-0/+4
| * RISC-V: validate riscv,isa at boot, not during ISA string parsingConor Dooley2023-06-211-3/+5
| * RISC-V: split early & late of_node to hartid mappingConor Dooley2023-06-211-1/+21
* | Merge patch series "RISC-V: Export Zba, Zbb to usermode via hwprobe"Palmer Dabbelt2023-06-191-0/+2
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| * RISC-V: Add Zba, Zbs extension probingEvan Green2023-06-191-0/+2
* | Merge patch series "riscv: allow case-insensitive ISA string parsing"Palmer Dabbelt2023-06-071-1/+2
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| * | riscv: allow case-insensitive ISA string parsingYangyu Chen2023-06-071-1/+2
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* / RISC-V: cpu: Enable cpuinfo for ACPI systemsSunil V L2023-06-011-8/+22
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* Merge tag 'kvm-riscv-6.4-1' of https://github.com/kvm-riscv/linux into HEADPaolo Bonzini2023-05-051-0/+2
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| * RISC-V: Detect AIA CSRs from ISA stringAnup Patel2023-04-211-0/+2
* | Merge patch series "RISC-V Hardware Probing User Interface"Palmer Dabbelt2023-04-191-6/+2
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| * | RISC-V: Move struct riscv_cpuinfo to new headerEvan Green2023-04-191-6/+2
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* | Merge patch series "RISC-V: Apply Zicboz to clear_page"Palmer Dabbelt2023-03-151-0/+1
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| * | RISC-V: Add Zicboz detection and block size parsingAndrew Jones2023-03-151-0/+1
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* | Merge patch series "riscv, mm: detect svnapot cpu support at runtime"Palmer Dabbelt2023-03-101-0/+1
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| * riscv: mm: modify pte format for SvnapotQinglin Pan2023-03-081-0/+1
* | RISC-V: fix ordering of Zbb extensionHeiko Stuebner2023-02-221-1/+1
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* RISC-V: add zbb support to string functionsHeiko Stuebner2023-01-311-0/+1
* Merge patch series "Putting some basic order on isa extension lists"Palmer Dabbelt2023-01-201-15/+38
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| * RISC-V: resort all extensions in consistent ordersConor Dooley2023-01-181-2/+2
| * RISC-V: clarify ISA string ordering rules in cpu.cConor Dooley2023-01-181-13/+36
* | Merge tag 'riscv-for-linus-6.2-mw1' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2022-12-151-3/+27
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| * | RISC-V: Cache SBI vendor valuesHeiko Stuebner2022-10-271-3/+27
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* / RISC-V: Fix /proc/cpuinfo cpumask warningAndrew Jones2022-10-281-0/+3
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* Merge tag 'riscv-for-linus-6.1-mw2' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2022-10-141-0/+51
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| * RISC-V: Add mvendorid, marchid, and mimpid to /proc/cpuinfo outputPalmer Dabbelt2022-10-131-0/+51
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| | * RISC-V: Add mvendorid, marchid, and mimpid to /proc/cpuinfo outputAnup Patel2022-10-041-0/+51
* | | Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds2022-10-121-0/+1
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| * | RISC-V: Probe Svinval extension form ISA stringMayuresh Chitale2022-10-021-0/+1
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* / RISC-V: Print SSTC in canonical orderPalmer Dabbelt2022-10-071-1/+1
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* RISC-V: Add Sstc extension supportPalmer Dabbelt2022-08-111-0/+1
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| * RISC-V: Enable sstc extension parsing from DTAtish Patra2022-08-111-0/+1
* | arch/riscv: add Zihintpause supportDao Lu2022-08-111-0/+1