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path: root/arch/riscv/kernel/cpufeature.c (follow)
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* RISC-V: Don't include Zicsr or Zifencei in I from ACPIPalmer Dabbelt2023-07-121-7/+2
* Merge patch series "ISA string parser cleanups"Palmer Dabbelt2023-06-231-23/+85
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| * RISC-V: always report presence of extensions formerly part of the base ISAConor Dooley2023-06-211-0/+17
| * RISC-V: remove decrement/increment dance in ISA string parserConor Dooley2023-06-211-8/+6
| * RISC-V: rework comments in ISA string parserConor Dooley2023-06-211-11/+59
| * RISC-V: validate riscv,isa at boot, not during ISA string parsingConor Dooley2023-06-211-6/+6
| * RISC-V: simplify register width check in ISA string parsingConor Dooley2023-06-211-8/+7
* | Merge patch series "RISC-V: Export Zba, Zbb to usermode via hwprobe"Palmer Dabbelt2023-06-191-6/+10
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| * | RISC-V: Track ISA extensions per hartEvan Green2023-06-191-6/+12
| * | RISC-V: Add Zba, Zbs extension probingEvan Green2023-06-191-0/+2
* | | riscv: say disabling zicbom if no or bad riscv,cbom-block-size foundBen Dooks2023-06-141-2/+2
* | | Merge patch series "riscv: Add vector ISA support"Palmer Dabbelt2023-06-081-0/+25
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| * | riscv: Add prctl controls for userspace vector managementAndy Chiu2023-06-081-1/+8
| * | riscv: hwcap: change ELF_HWCAP to a functionAndy Chiu2023-06-081-0/+5
| * | riscv: Introduce riscv_v_vsize to record size of Vector contextGreentime Hu2023-06-081-0/+2
| * | riscv: Extending cpufeature.c to detect V-extensionGuo Ren2023-06-081-0/+11
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* | Merge patch series "riscv: allow case-insensitive ISA string parsing"Palmer Dabbelt2023-06-071-18/+17
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| * | riscv: allow case-insensitive ISA string parsingYangyu Chen2023-06-071-18/+17
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* | RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap()Sunil V L2023-06-011-10/+31
* | RISC-V: only iterate over possible CPUs in ISA string parserSunil V L2023-06-011-5/+10
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* Merge tag 'riscv-for-linus-6.4-mw2' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2023-05-051-0/+1
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| * RISC-V: include cpufeature.h in cpufeature.cConor Dooley2023-05-021-0/+1
* | Merge tag 'kvm-riscv-6.4-1' of https://github.com/kvm-riscv/linux into HEADPaolo Bonzini2023-05-051-0/+2
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| * RISC-V: Detect AIA CSRs from ISA stringAnup Patel2023-04-211-0/+2
* | Merge patch series "RISC-V Hardware Probing User Interface"Palmer Dabbelt2023-04-191-0/+3
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| * | RISC-V: hwprobe: Support probing of misaligned access performanceEvan Green2023-04-191-0/+3
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* | Merge patch series "RISC-V: Apply Zicboz to clear_page"Palmer Dabbelt2023-03-151-4/+54
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| * | RISC-V: Use Zicboz in clear_page when availableAndrew Jones2023-03-151-0/+11
| * | RISC-V: cpufeatures: Put the upper 16 bits of patch ID to workAndrew Jones2023-03-151-4/+33
| * | RISC-V: Add Zicboz detection and block size parsingAndrew Jones2023-03-151-0/+10
* | | Merge patch series "riscv: alternative/cpufeature related cleanups"Palmer Dabbelt2023-03-151-8/+3
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| * | riscv: cpufeature: Drop errata_list.h and other unused includesAndrew Jones2023-03-151-5/+0
| * | riscv: alternatives: Rename errata_id to patch_idAndrew Jones2023-03-151-3/+3
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* | Merge patch series "riscv, mm: detect svnapot cpu support at runtime"Palmer Dabbelt2023-03-101-0/+1
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| * riscv: mm: modify pte format for SvnapotQinglin Pan2023-03-081-0/+1
* | RISC-V: take text_mutex during alternative patchingConor Dooley2023-02-221-0/+4
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* Merge patch series "riscv: improve boot time isa extensions handling"Palmer Dabbelt2023-02-021-83/+13
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| * riscv: remove riscv_isa_ext_keys[] array and related usageJisheng Zhang2023-02-011-9/+0
| * riscv: switch to relative alternative entriesJisheng Zhang2023-02-011-3/+5
| * riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA extensionsJisheng Zhang2023-02-011-56/+8
| * riscv: cpufeature: detect RISCV_ALTERNATIVES_EARLY_BOOT earlierJisheng Zhang2023-02-011-0/+3
| * riscv: move riscv_noncoherent_supported() out of ZICBOM probeJisheng Zhang2023-02-011-1/+0
* | RISC-V: add zbb support to string functionsHeiko Stuebner2023-01-311-0/+18
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* Merge patch series "Putting some basic order on isa extension lists"Palmer Dabbelt2023-01-201-2/+4
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| * RISC-V: resort all extensions in consistent ordersConor Dooley2023-01-181-2/+4
* | RISC-V: fix auipc-jalr addresses in patched alternativesHeiko Stuebner2022-12-291-1/+4
* | RISC-V: Ensure Zicbom has a valid block sizeAndrew Jones2022-12-101-0/+13
* | RISC-V: Introduce riscv_isa_extension_checkAndrew Jones2022-12-101-3/+11
* | RISC-V: Improve use of isa2hwcap[]Andrew Jones2022-12-101-9/+11
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* Merge tag 'riscv-for-linus-6.1-mw2' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2022-10-141-23/+16
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