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Age
Files
Lines
*
arch/riscv: disable excess harts before picking main boot hart
Xiang Wang
2019-09-20
1
-3
/
+5
*
Merge tag 'riscv/for-v5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g...
Linus Torvalds
2019-09-17
1
-1
/
+1
|
\
|
*
riscv: Using CSR numbers to access CSRs
Bin Meng
2019-08-30
1
-1
/
+1
*
|
riscv: modify the Image header to improve compatibility with the ARM64 header
Paul Walmsley
2019-09-14
1
-2
/
+2
|
/
*
RISC-V: Add an Image header that boot loader can parse.
Atish Patra
2019-07-11
1
-0
/
+32
*
RISC-V: Setup initial page tables in two stages
Anup Patel
2019-07-09
1
-8
/
+9
*
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286
Thomas Gleixner
2019-06-05
1
-9
/
+1
*
RISC-V: Avoid using invalid intermediate translations
Palmer Dabbelt
2019-05-17
1
-2
/
+10
*
RISC-V: Access CSRs using CSR numbers
Anup Patel
2019-05-17
1
-8
/
+8
*
riscv: cleanup the parse_dtb calling conventions
Christoph Hellwig
2019-04-25
1
-2
/
+1
*
riscv: simplify the stack pointer setup in head.S
Christoph Hellwig
2019-04-25
1
-4
/
+1
*
riscv: clear all pending interrupts when booting
Christoph Hellwig
2019-04-25
1
-1
/
+2
*
RISC-V: Build flat and compressed kernel images
Anup Patel
2018-11-20
1
-0
/
+10
*
RISC-V: Use Linux logical CPU number instead of hartid
Atish Patra
2018-10-23
1
-1
/
+3
*
RISC-V: Add the directive for alignment of stvec's value
Zong Li
2018-08-13
1
-0
/
+2
*
Rename sbi_save to parse_dtb to improve code readability
Michael Clark
2018-02-20
1
-1
/
+1
*
riscv: rename sptbr to satp
Christoph Hellwig
2018-01-31
1
-3
/
+3
*
RISC-V: move empty_zero_page definition to C and export it
Olof Johansson
2017-11-30
1
-3
/
+0
*
RISC-V: Init and Halt Code
Palmer Dabbelt
2017-09-27
1
-0
/
+157