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path: root/arch/riscv/kernel/smpboot.c (follow)
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* Merge tag 'riscv-for-linus-6.9-mw2' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2024-03-221-1/+0
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| * RISC-V: Remove duplicated include in smpboot.cYang Li2024-01-251-1/+0
* | smp: Consolidate smp_prepare_boot_cpu()Thomas Gleixner2024-03-041-4/+0
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* riscv: Use the same CPU operations for all CPUsSamuel Holland2024-01-051-8/+5
* riscv: Remove unused members from struct cpu_operationsSamuel Holland2024-01-051-6/+0
* riscv: Deduplicate code in setup_smp()Samuel Holland2024-01-051-20/+11
* RISC-V: Probe misaligned access speed in parallelEvan Green2023-11-081-1/+0
* Merge patch series "Add support to handle misaligned accesses in S-mode"Palmer Dabbelt2023-11-051-1/+1
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| * riscv: report misaligned accesses emulation to hwprobeClément Léger2023-11-011-1/+1
* | RISC-V: Enable cbo.zero in usermodeAndrew Jones2023-09-211-0/+4
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* RISC-V: alternative: Remove feature_probe_funcEvan Green2023-09-011-1/+0
* RISC-V: Probe for unaligned access speedEvan Green2023-09-011-0/+2
* risc-v: Fix order of IPI enablement vs RCU startupMarc Zyngier2023-07-051-2/+3
* Merge patch series "ISA string parser cleanups"Palmer Dabbelt2023-06-231-1/+1
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| * RISC-V: split early & late of_node to hartid mappingConor Dooley2023-06-211-1/+1
* | Merge patch series "riscv: Add vector ISA support"Palmer Dabbelt2023-06-081-0/+7
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| * riscv: Introduce riscv_v_vsize to record size of Vector contextGreentime Hu2023-06-081-0/+7
* | RISC-V: smpboot: Add ACPI support in setup_smp()Sunil V L2023-06-011-1/+71
* | RISC-V: smpboot: Create wrapper setup_smp()Sunil V L2023-06-011-1/+6
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* Merge tag 'riscv-for-linus-6.4-mw1' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2023-04-291-0/+1
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| * RISC-V: hwprobe: Support probing of misaligned access performanceEvan Green2023-04-191-0/+1
* | RISC-V: Treat IPIs as normal Linux IRQsAnup Patel2023-04-081-3/+2
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* riscv: Move call to init_cpu_topology() to later initialization stageLey Foon Tan2023-01-251-1/+2
* riscv: topology: fix default topology reportingConor Dooley2022-08-151-1/+2
* riscv: cpu: Add 64bit hartid support on RV64Sunil V L2022-07-201-4/+5
* riscv: move boot alternatives to after fill_hwcapHeiko Stuebner2022-05-121-2/+0
* riscv: integrate alternatives better into the main architectureHeiko Stuebner2022-05-121-2/+0
* RISC-V: Do not use cpumask data structure for hartid bitmapAtish Patra2022-01-201-1/+1
* sched/core: Initialize the idle task with preemption disabledValentin Schneider2021-05-121-1/+0
* riscv: Introduce alternative mechanism to apply errata solutionVincent Chen2021-04-261-0/+4
* riscv: Add numa support for riscv64 platformAtish Patra2021-01-151-1/+11
* RISC-V: Remove CLINT related code from timer and archAnup Patel2020-08-201-1/+0
* RISC-V: Add mechanism to provide custom IPI operationsAnup Patel2020-08-201-2/+1
* RISC-V: Fix build warning for smpboot.cAtish Patra2020-08-051-1/+1
* RISC-V: Setup exception vector earlyAtish Patra2020-07-301-1/+1
* riscv: Fixup lockdep_assert_held with wrong param cpu_runningZong Li2020-07-301-1/+0
* RISC-V: Use a local variable instead of smp_processor_id()Greentime Hu2020-06-301-3/+4
* RISC-V: Add supported for ordered booting method using HSMAtish Patra2020-03-311-1/+1
* RISC-V: Add cpu_ops and modify default booting methodAtish Patra2020-03-311-21/+30
* riscv: provide native clint access for M-modeChristoph Hellwig2019-11-181-0/+4
* riscv: for C functions called only from assembly, mark with __visiblePaul Walmsley2019-10-281-1/+1
* riscv: add missing header file includesPaul Walmsley2019-10-281-0/+1
* riscv: add prototypes for assembly language functions from head.SPaul Walmsley2019-10-281-0/+2
* RISC-V: Parse cpu topology during boot.Atish Patra2019-07-221-0/+3
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner2019-05-301-9/+1
* RISC-V: Support nr_cpus command line option.Atish Patra2019-05-171-1/+9
* RISC-V: Implement nosmp commandline option.Atish Patra2019-04-301-1/+11
* RISC-V: Compare cpuid with NR_CPUS before mapping.Atish Patra2019-03-041-0/+5
* RISC-V: Do not wait indefinitely in __cpu_upAtish Patra2019-03-041-3/+12
* riscv: use for_each_of_cpu_node iteratorJohan Hovold2019-02-121-2/+2
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