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path: root/arch/riscv/kernel/traps.c (follow)
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* RISC-V: Don't enable all interrupts in trap_init()Anup Patel2020-02-181-2/+2
* riscv: abstract out CSR names for supervisor vs machine modeChristoph Hellwig2019-11-051-8/+8
* riscv: for C functions called only from assembly, mark with __visiblePaul Walmsley2019-10-281-2/+2
* riscv: add missing header file includesPaul Walmsley2019-10-281-0/+1
* riscv: cleanup do_trap_breakChristoph Hellwig2019-10-261-20/+6
* riscv: remove the switch statement in do_trap_break()Vincent Chen2019-10-141-11/+11
* riscv: Correct the handling of unexpected ebreak in do_trap_break()Vincent Chen2019-10-071-3/+3
* riscv: avoid sending a SIGTRAP to a user thread trapped in WARN()Vincent Chen2019-10-071-1/+1
* riscv: avoid kernel hangs when trapped in BUG()Vincent Chen2019-10-071-3/+3
* Merge branch 'siginfo-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...Linus Torvalds2019-07-091-5/+6
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| * signal: Remove the task parameter from force_sig_faultEric W. Biederman2019-05-291-2/+2
| * signal: Explicitly call force_sig_fault on currentEric W. Biederman2019-05-291-1/+1
| * signal/riscv: Remove tsk parameter from do_trapEric W. Biederman2019-05-291-3/+4
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner2019-06-051-9/+1
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* riscv: Support BUG() in kernel moduleVincent Chen2019-05-171-1/+1
* riscv: Add the support for c.ebreak check in is_valid_bugaddr()Vincent Chen2019-05-171-3/+17
* RISC-V: Access CSRs using CSR numbersAnup Patel2019-05-171-3/+3
* riscv: remove duplicate macros from ptrace.hChristoph Hellwig2019-04-251-1/+1
* RISC-V: Don't increment sepc after breakpoint.Jim Wilson2018-08-131-1/+0
* Merge tag 'riscv-for-linus-4.18-merge_window' of git://git.kernel.org/pub/scm...Linus Torvalds2018-06-151-1/+1
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| * riscv: no __user for probe_kernel_address()Luc Van Oostenryck2018-06-071-1/+1
* | signal/riscv: Replace do_trap_siginfo with force_sig_faultEric W. Biederman2018-04-251-8/+2
* | signal/riscv: Use force_sig_fault where appropriateEric W. Biederman2018-04-251-8/+1
* | signal: Ensure every siginfo we send has all bits initializedEric W. Biederman2018-04-251-0/+1
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* RISC-V: Init and Halt CodePalmer Dabbelt2017-09-271-0/+180
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