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* riscv: Optimize crc32 with Zbc extensionXiao Wang2024-07-102-0/+295
* riscv: vector: adjust minimum Vector requirement to ZVE32XAndy Chiu2024-05-301-1/+1
* riscv: uaccess: Relax the threshold for fast pathXiao Wang2024-05-231-1/+1
* riscv: uaccess: Allow the last potential unrolled copyXiao Wang2024-05-231-1/+1
* Merge tag 'riscv-for-linus-6.9-mw2' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2024-03-222-6/+2
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| * Merge patch series "riscv: Use Kconfig to set unaligned access speed"Palmer Dabbelt2024-03-131-5/+2
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| | * riscv: lib: Introduce has_fast_unaligned_access()Charlie Jenkins2024-03-131-5/+2
| * | riscv: remove unneeded #include <asm-generic/export.h>Masahiro Yamada2024-01-221-1/+0
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* / work around gcc bugs with 'asm goto' with outputsLinus Torvalds2024-02-101-5/+5
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* riscv: lib: Check if output in asm goto supportedCharlie Jenkins2024-01-181-0/+2
* Merge patch series "riscv: Add fine-tuned checksum functions"Palmer Dabbelt2024-01-182-1/+328
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| * riscv: Add checksum libraryCharlie Jenkins2024-01-182-0/+327
* | Merge patch series "riscv: support kernel-mode Vector"Palmer Dabbelt2024-01-165-1/+195
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| * | riscv: lib: vectorize copy_to_user/copy_from_userAndy Chiu2024-01-164-1/+113
| * | riscv: Add vector extension XOR implementationGreentime Hu2024-01-162-0/+82
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* / use linux/export.h rather than asm-generic/export.hAl Viro2024-01-103-3/+3
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* riscv: Use SYM_*() assembly macros instead of deprecated onesClément Léger2023-11-064-14/+12
* riscv: use ".L" local labels in assembly when applicableClément Léger2023-11-061-27/+27
* RISC-V: capitalise CMO op macrosConor Dooley2023-11-051-16/+16
* riscv: uaccess: Return the number of bytes effectively not copiedAlexandre Ghiti2023-08-161-4/+7
* riscv: Allow to downgrade paging mode from the command lineAlexandre Ghiti2023-04-263-0/+5
* RISC-V: Use Zicboz in clear_page when availableAndrew Jones2023-03-152-0/+75
* riscv: lib: Include hwcap.h directlyAndrew Jones2023-03-153-6/+3
* riscv, lib: Fix Zbb strncmpBjörn Töpel2023-03-011-1/+3
* RISC-V: improve string-function assemblyHeiko Stuebner2023-02-283-16/+16
* riscv: Fix Zbb alternative IDsSamuel Holland2023-02-153-3/+3
* RISC-V: add zbb support to string functionsHeiko Stuebner2023-01-313-0/+288
* RISC-V: add infrastructure to allow different str* implementationsHeiko Stuebner2023-01-314-0/+108
* riscv: lib: uaccess: fix CSR_STATUS SR_SUM bitChen Lifu2022-08-101-2/+2
* riscv: Fixed misaligned memory access. Fixed pointer comparison.Michael T. Kloos2022-03-101-58/+310
* riscv: extable: consolidate definitionsJisheng Zhang2022-01-061-4/+2
* riscv: lib: uaccess: fold fixups into bodyJisheng Zhang2022-01-061-11/+11
* riscv: switch to relative exception tablesJisheng Zhang2022-01-061-2/+2
* include/linux/delay.h: replace kernel.h with the necessary inclusionsAndy Shevchenko2021-11-091-0/+4
* riscv: __asm_copy_to-from_user: Fix: Typos in commentsAkira Tsukamoto2021-07-241-9/+9
* riscv: __asm_copy_to-from_user: Remove unnecessary size checkAkira Tsukamoto2021-07-241-1/+0
* riscv: __asm_copy_to-from_user: Fix: fail on RV32Akira Tsukamoto2021-07-241-1/+1
* riscv: __asm_copy_to-from_user: Fix: overrun copyAkira Tsukamoto2021-07-241-3/+3
* riscv: __asm_copy_to-from_user: Optimize unaligned memory access and pipeline...Akira Tsukamoto2021-07-071-35/+146
* riscv: Add support for function error injectionGuo Ren2021-01-152-0/+12
* riscv: provide memmove implementationNylon Chen2020-12-112-0/+65
* riscv: use memcpy based uaccess for nommu againChristoph Hellwig2020-10-041-1/+1
* Merge tag 'riscv-for-linus-5.7' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds2020-04-091-4/+2
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| * RISC-V: Stop using LOCAL for the uaccess fixupsPalmer Dabbelt2020-03-031-4/+2
* | riscv: uaccess should be used in nommu modeGreentime Hu2020-03-191-1/+1
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* riscv: Add KASAN supportNick Hu2020-01-222-4/+6
* riscv: Less inefficient gcc tishift helpers (and export their symbols)Olof Johansson2020-01-191-18/+57
* riscv: fix compile failure with EXPORT_SYMBOL() & !MMULuc Van Oostenryck2019-12-281-0/+4
* riscv: add nommu supportChristoph Hellwig2019-11-181-6/+5
* riscv: abstract out CSR names for supervisor vs machine modeChristoph Hellwig2019-11-051-6/+6
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