summaryrefslogtreecommitdiffstats
path: root/arch/riscv (follow)
Commit message (Expand)AuthorAgeFilesLines
* riscv: mm: Fix code commentShihPo Hung2019-06-271-3/+0
* riscv: dts: Re-organize the DT nodesYash Shah2019-06-262-0/+19
* RISC-V: defconfig: enable MMC & SPI for RISC-VAtish Patra2019-06-261-0/+5
* Merge tag 'spdx-5.2-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/gre...Linus Torvalds2019-06-2112-136/+12
|\
| * treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner2019-06-191-4/+1
| * treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234Thomas Gleixner2019-06-1911-132/+11
* | Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/netLinus Torvalds2019-06-181-0/+24
|\ \
| * \ Merge git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpfDavid S. Miller2019-06-071-0/+24
| |\ \
| | * | bpf, riscv: clear high 32 bits for ALU32 add/sub/neg/lsh/rsh/arshLuke Nelson2019-06-011-0/+18
| | * | bpf, riscv: clear target register high 32-bits for and/or/xor on ALU32Björn Töpel2019-05-231-0/+6
* | | | Merge tag 'riscv-for-v5.2/fixes-rc6' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2019-06-179-6/+303
|\ \ \ \ | |_|_|/ |/| | |
| * | | riscv: remove unused barrier definesRolf Eike Beer2019-06-171-5/+0
| * | | riscv: mm: synchronize MMU after pte changeShihPo Hung2019-06-171-0/+13
| * | | riscv: dts: add initial board data for the SiFive HiFive UnleashedPaul Walmsley2019-06-172-0/+67
| * | | riscv: dts: add initial support for the SiFive FU540-C000 SoCPaul Walmsley2019-06-171-0/+215
| * | | arch: riscv: add support for building DTB files from DT source dataPaul Walmsley2019-06-171-0/+2
| * | | riscv: Fix udelay in RV32.Nick Hu2019-06-111-1/+1
| * | | riscv: export pm_power_off againAndreas Schwab2019-06-111-0/+1
| * | | RISC-V: defconfig: enable clocks, serial consoleKevin Hilman2019-06-111-0/+4
| | |/ | |/|
* | | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner2019-06-0568-611/+68
| |/ |/|
* | treewide: Add SPDX license identifier - KbuildGreg Kroah-Hartman2019-05-302-0/+2
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner2019-05-303-27/+3
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157Thomas Gleixner2019-05-301-9/+1
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152Thomas Gleixner2019-05-301-5/+1
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 120Thomas Gleixner2019-05-245-70/+5
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 36Thomas Gleixner2019-05-241-5/+1
* | treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner2019-05-216-0/+6
|/
* Merge tag 'kbuild-v5.2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/ma...Linus Torvalds2019-05-191-4/+0
|\
| * arch: remove dangling asm-generic wrappersMasahiro Yamada2019-05-181-4/+0
* | Merge tag 'riscv-for-linus-5.2-mw2' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2019-05-1934-320/+584
|\ \ | |/ |/|
| * riscv: fix locking violation in page fault handlerAndreas Schwab2019-05-171-1/+2
| * RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCsYash Shah2019-05-173-0/+192
| * RISC-V: Avoid using invalid intermediate translationsPalmer Dabbelt2019-05-171-2/+10
| * riscv: Support BUG() in kernel moduleVincent Chen2019-05-171-1/+1
| * riscv: Add the support for c.ebreak check in is_valid_bugaddr()Vincent Chen2019-05-172-4/+23
| * riscv: support trap-based WARN()Vincent Chen2019-05-171-10/+18
| * riscv: fix sbi_remote_sfence_vma{,_asid}.Gary Guo2019-05-171-7/+12
| * riscv: move switch_mm to its own fileGary Guo2019-05-173-52/+72
| * riscv: move flush_icache_{all,mm} to cacheflush.cGary Guo2019-05-173-50/+62
| * RISC-V: Access CSRs using CSR numbersAnup Patel2019-05-179-48/+57
| * RISC-V: Add interrupt related SCAUSE defines in asm/csr.hAnup Patel2019-05-172-16/+21
| * RISC-V: Use tabs to align macro values in asm/csr.hAnup Patel2019-05-171-38/+38
| * RISC-V: Fix minor checkpatch issues.Atish Patra2019-05-171-2/+2
| * RISC-V: Support nr_cpus command line option.Atish Patra2019-05-171-1/+9
| * RISC-V: Implement nosmp commandline option.Atish Patra2019-04-301-1/+11
| * RISC-V: Add RISC-V specific arch_match_cpu_phys_idAtish Patra2019-04-302-2/+7
| * riscv: vdso: drop unnecessary cc-ldoptionNick Desaulniers2019-04-301-1/+1
| * riscv: call pm_power_off from machine_halt / machine_power_offChristoph Hellwig2019-04-251-6/+9
| * riscv: print the unexpected interrupt causeChristoph Hellwig2019-04-251-1/+2
| * riscv: remove duplicate macros from ptrace.hChristoph Hellwig2019-04-253-21/+12
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-04 00:29:50 +0100