| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | x86/cpu: Move cpu_l[l2]c_id into topology info | Thomas Gleixner | 2023-10-10 | 1 | -3/+0 |
| * | x86/cacheinfo: Switch cache_ap_init() to hotplug callback | Juergen Gross | 2022-11-10 | 1 | -1/+0 |
| * | x86/mtrr: Add a stop_machine() handler calling only cache_cpu_init() | Juergen Gross | 2022-11-10 | 1 | -1/+4 |
| * | x86/mtrr: Let cache_aps_delayed_init replace mtrr_aps_delayed_init | Juergen Gross | 2022-11-10 | 1 | -0/+2 |
| * | x86/mtrr: Disentangle MTRR init from PAT init | Juergen Gross | 2022-11-10 | 1 | -0/+1 |
| * | x86/mtrr: Rename prepare_set() and post_set() | Juergen Gross | 2022-11-10 | 1 | -0/+3 |
| * | x86/mtrr: Replace use_intel() with a local flag | Juergen Gross | 2022-11-10 | 1 | -0/+5 |
| * | x86/CPU/AMD: Save AMD NodeId as cpu_die_id | Yazen Ghannam | 2020-11-19 | 1 | -2/+2 |
| * | x86/cpu: Get cache info and setup cache cpumap for Hygon Dhyana | Pu Wen | 2018-09-27 | 1 | -0/+1 |
| * | x86/CPU/AMD: Calculate last level cache ID from number of sharing threads | Suravee Suthikulpanit | 2018-05-06 | 1 | -0/+7 |
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