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* Merge tag 'sched-core-2023-02-20' of git://git.kernel.org/pub/scm/linux/kerne...Linus Torvalds2023-02-211-1/+1
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| * x86/perf/amd: Remove tracing from perf_lopwr_cb()Peter Zijlstra2023-01-131-1/+1
* | perf/x86/intel: Support Architectural PerfMon Extension leafKan Liang2023-01-091-0/+8
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* perf/x86/core: Zero @lbr instead of returning -1 in x86_perf_get_lbr() stubSean Christopherson2022-11-091-3/+3
* perf/x86/amd/lbr: Detect LbrExtV2 supportSandipan Das2022-08-271-1/+2
* Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds2022-08-041-2/+9
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| * perf: x86/core: Add interface to query perfmon_event_map[] directlyLike Xu2022-06-081-0/+6
| * perf/x86/core: Pass "struct kvm_pmu *" to determine the guest valuesLike Xu2022-06-081-2/+2
| * perf/x86/intel: Add EPT-Friendly PEBS for Ice Lake ServerLike Xu2022-06-081-0/+1
* | perf/x86/amd/uncore: Add PerfMonV2 DF event formatSandipan Das2022-06-131-0/+13
* | perf/x86/amd/uncore: Detect available DF countersSandipan Das2022-06-131-0/+3
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* perf/amd/ibs: Add support for L3 miss filteringRavi Bangoria2022-05-111-0/+3
* Merge branch 'v5.18-rc5'Peter Zijlstra2022-05-111-0/+5
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| * perf/x86/intel: Don't extend the pseudo-encoding to GP countersKan Liang2022-04-051-0/+5
* | perf/x86/amd/core: Detect available countersSandipan Das2022-05-041-0/+17
* | perf/x86/amd: Add idle hooks for branch samplingStephane Eranian2022-04-051-0/+23
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* perf/x86/intel: Increase max number of the fixed countersKan Liang2022-02-021-1/+1
* perf/x86: Reset the dirty counter to prevent the leak for an RDPMC taskKan Liang2021-06-171-0/+1
* perf/x86/intel: Add perf core PMU support for Sapphire RapidsKan Liang2021-02-011-2/+6
* perf/x86/intel: Filter unsupported Topdown metrics eventKan Liang2021-02-011-2/+8
* x86/perf: Use static_call for x86_pmu.guest_get_msrsLike Xu2021-01-271-5/+1
* perf/x86/intel: Make anythread filter support conditionalStephane Eranian2020-11-091-1/+3
* perf/x86/amd/ibs: Support 27-bit extended Op/cycle counterKim Phillips2020-09-101-0/+1
* perf/x86/intel: Support TopDown metrics on Ice LakeKan Liang2020-08-181-0/+2
* perf/x86: Add a macro for RDPMC offset of fixed countersKan Liang2020-08-181-0/+3
* perf/x86/intel: Generic support for hardware TopDown metricsKan Liang2020-08-181-0/+47
* perf/x86/intel: Move BTS index to 47Kan Liang2020-08-181-2/+2
* perf/x86/intel: Introduce the fourth fixed counterKan Liang2020-08-181-3/+20
* perf/x86/intel: Name the global status bit in NMI handlerKan Liang2020-08-181-10/+12
* perf/x86/intel/lbr: Support XSAVES/XRSTORS for LBR context switchKan Liang2020-07-081-4/+0
* perf/x86/intel/lbr: Unify the stored format of LBR informationKan Liang2020-07-081-5/+1
* perf/x86: Expose CPUID enumeration bits for arch LBRKan Liang2020-07-081-0/+40
* perf/x86: Add constraint to create guest LBR event without hw counterLike Xu2020-07-021-1/+21
* perf/x86/lbr: Add interface to get LBR informationLike Xu2020-07-021-0/+12
* perf/amd/uncore: Add support for Family 19h L3 PMUKim Phillips2020-03-171-2/+13
* perf/x86: Provide stubs of KVM helpers for non-Intel CPUsSean Christopherson2020-01-131-7/+15
* perf/x86/amd/ibs: Fix sample bias for dispatched micro-opsKim Phillips2019-08-301-4/+8
* perf/x86: Make perf callchains work without CONFIG_FRAME_POINTERKairui Song2019-04-291-6/+1
* perf/x86/intel: Add Icelake supportKan Liang2019-04-161-1/+1
* perf/x86/intel: Support adaptive PEBS v4Kan Liang2019-04-161-0/+43
* perf/x86: Support outputting XMM registersKan Liang2019-04-161-0/+5
* Merge branch 'x86/cache' into perf/core, to resolve conflictsIngo Molnar2018-10-021-0/+1
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| * perf/x86: Add helper to obtain performance counter indexReinette Chatre2018-09-281-0/+1
* | perf/x86/amd/uncore: Set ThreadMask and SliceMask for L3 Cache perf eventsNatarajan, Janakarajan2018-10-021-0/+8
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* License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman2017-11-021-0/+1
* perf/x86/intel/pt: Don't die on VMXONAlexander Shishkin2016-04-281-0/+4
* perf/x86/intel: Add definition for PT PMI bitStephane Eranian2016-03-081-0/+1
* x86: Add new MSRs and MSR bits used for Intel Skylake PMU supportAndi Kleen2015-08-041-0/+7
* perf/x86/amd/ibs: Update IBS MSRs and feature definitionsAravind Gopalakrishnan2014-11-121-0/+3
* perf/x86: Revamp PEBS event selectionAndi Kleen2014-08-131-0/+8
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