summaryrefslogtreecommitdiffstats
path: root/arch/x86/include/asm/tlbflush.h (follow)
Commit message (Expand)AuthorAgeFilesLines
* x86/mm: Avoid redundant interrupt disable in load_mm_cr4()Jan Kiszka2019-07-241-7/+23
* Merge branch 'x86-mm-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds2019-05-071-0/+2
|\
| * mm/tlb: Provide default nmi_uaccess_okay()Nadav Amit2019-04-301-0/+2
* | x86/mm/tlb: Define LOADED_MM_SWITCHING with pointer-sized numberJann Horn2019-03-291-1/+1
|/
* x86/speculation: Prepare for conditional IBPB in switch_mm()Thomas Gleixner2018-11-281-2/+6
* x86/mm/pat: Disable preemption around __flush_tlb_all()Sebastian Andrzej Siewior2018-10-291-0/+6
* x86/mm/tlb: Add freed_tables element to flush_tlb_infoRik van Riel2018-10-091-0/+1
* x86/mm/tlb: Add freed_tables argument to flush_tlb_mm_rangeRik van Riel2018-10-091-4/+6
* x86/mm/tlb: Always use lazy TLB modeRik van Riel2018-10-091-16/+0
* x86/mm: Page size aware flush_tlb_mm_range()Peter Zijlstra2018-10-091-4/+8
* x86/nmi: Fix NMI uaccess race against CR3 switchingAndy Lutomirski2018-08-311-0/+40
* x86/mm: Only use tlb_remove_table() for paravirtPeter Zijlstra2018-08-231-0/+3
* x86/mm/tlb: Revert the recent lazy TLB patchesPeter Zijlstra2018-08-231-5/+16
* x86/mm/tlb: Always use lazy TLB modeRik van Riel2018-07-171-16/+0
* x86/mm/tlb: Leave lazy TLB mode at page table free timeRik van Riel2018-07-171-0/+5
* x86/mm: Fix bogus warning during EFI bootup, use boot_cpu_has() instead of th...Sai Praneeth2018-04-051-1/+6
* x86/mm: Rename flush_tlb_single() and flush_tlb_one() to __flush_tlb_one_[use...Andy Lutomirski2018-02-151-7/+20
* x86/speculation: Use Indirect Branch Prediction Barrier in context switchTim Chen2018-01-301-0/+2
* Merge branch 'x86-pti-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...Linus Torvalds2018-01-141-3/+3
|\
| * x86/pti: Fix !PCID and sanitize definesThomas Gleixner2018-01-141-3/+3
* | Merge branch 'x86-pti-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...Linus Torvalds2017-12-311-6/+8
|\|
| * x86/mm: Remove preempt_disable/enable() from __native_flush_tlb()Thomas Gleixner2017-12-311-6/+8
* | Merge branch 'x86-pti-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...Linus Torvalds2017-12-301-31/+171
|\|
| * x86/mm: Clarify the whole ASID/kernel PCID/user PCID namingPeter Zijlstra2017-12-231-12/+43
| * x86/mm: Use INVPCID for __native_flush_tlb_single()Dave Hansen2017-12-231-1/+22
| * x86/mm: Use/Fix PCID to optimize user/kernel switchesPeter Zijlstra2017-12-231-12/+79
| * x86/mm: Allow flushing for future ASID switchesDave Hansen2017-12-231-8/+29
* | Merge branch 'x86-pti-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...Linus Torvalds2017-12-231-64/+72
|\|
| * x86/mm: Create asm/invpcid.hPeter Zijlstra2017-12-221-48/+1
| * x86/mm: Put MMU to hardware ASID translation in one placeDave Hansen2017-12-221-11/+18
| * x86/mm: Remove hard-coded ASID limit checksDave Hansen2017-12-221-2/+18
| * x86/mm: Move the CR3 construction functions to tlbflush.hDave Hansen2017-12-221-0/+26
| * x86/mm: Add comments to clarify which TLB-flush functions are supposed to flu...Peter Zijlstra2017-12-221-2/+21
| * x86/mm: Remove superfluous barriersPeter Zijlstra2017-12-221-7/+1
| * x86/microcode: Dont abuse the TLB-flush interfacePeter Zijlstra2017-12-221-13/+6
* | x86/tlb: Disable interrupts when changing CR4Nadav Amit2017-11-251-3/+8
* | x86/tlb: Refactor CR4 setting and shadow writeNadav Amit2017-11-251-13/+11
|/
* License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman2017-11-021-0/+1
* x86/mm: Remove debug/x86/tlb_defer_switch_to_init_mmAndy Lutomirski2017-10-181-8/+12
* x86/mm: Tidy up "x86/mm: Flush more aggressively in lazy TLB mode"Andy Lutomirski2017-10-181-1/+6
* x86/mm: Flush more aggressively in lazy TLB modeAndy Lutomirski2017-10-141-0/+24
* x86/mm: Reinitialize TLB state on hotplug and resumeAndy Lutomirski2017-09-071-0/+2
* x86/mm: Implement PCID based optimization: try to preserve old TLB entries us...Andy Lutomirski2017-07-251-2/+16
* x86/mm: Enable CR4.PCIDE on supported systemsAndy Lutomirski2017-07-051-0/+8
* x86/mm: Rework lazy TLB mode and TLB freshness trackingAndy Lutomirski2017-07-051-4/+0
* x86/mm: Track the TLB's tlb_gen and update the flushing algorithmAndy Lutomirski2017-07-051-3/+40
* x86/mm: Give each mm TLB flush generation a unique IDAndy Lutomirski2017-07-051-0/+18
* x86/mm: Remove reset_lazy_tlbstate()Andy Lutomirski2017-06-221-8/+0
* x86/mm: Split read_cr3() into read_cr3_pa() and __read_cr3()Andy Lutomirski2017-06-131-2/+2
* x86/mm: Rework lazy TLB to track the actual loaded mmAndy Lutomirski2017-06-051-2/+10