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* Merge tag 'x86_mtrr_for_v6.9_rc1' of git://git.kernel.org/pub/scm/linux/kerne...Linus Torvalds2024-03-121-3/+4
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| * x86/pat: Simplify the PAT programming protocolKirill A. Shutemov2024-02-201-3/+4
* | x86/cpu/topology: Get rid of cpuinfo::x86_max_coresThomas Gleixner2024-02-161-1/+1
* | x86/cpu: Provide an AMD/HYGON specific topology parserThomas Gleixner2024-02-151-2/+2
* | x86/cpu/amd: Provide a separate accessor for Node IDThomas Gleixner2024-02-151-1/+1
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* x86/cpu: Move cpu_l[l2]c_id into topology infoThomas Gleixner2023-10-101-21/+12
* x86/cpu: Move cpu_die_id into topology infoThomas Gleixner2023-10-101-1/+1
* x86/cpu: Move phys_proc_id into topology infoThomas Gleixner2023-10-101-2/+2
* x86/cpu: Encapsulate topology information in cpuinfo_x86Thomas Gleixner2023-10-101-10/+10
* x86/cpu/cacheinfo: Remove cpu_callout_mask dependencyThomas Gleixner2023-05-151-4/+17
* x86/cacheinfo: Remove unused trace variableBorislav Petkov (AMD)2023-02-111-4/+1
* x86/cacheinfo: Switch cache_ap_init() to hotplug callbackJuergen Gross2022-11-101-3/+15
* x86: Decouple PAT and MTRR handlingJuergen Gross2022-11-101-1/+2
* x86/mtrr: Add a stop_machine() handler calling only cache_cpu_init()Juergen Gross2022-11-101-1/+58
* x86/mtrr: Let cache_aps_delayed_init replace mtrr_aps_delayed_initJuergen Gross2022-11-101-0/+12
* x86/mtrr: Disentangle MTRR init from PAT initJuergen Gross2022-11-101-0/+17
* x86/mtrr: Move cache control code to cacheinfo.cJuergen Gross2022-11-101-0/+77
* x86/mtrr: Replace use_intel() with a local flagJuergen Gross2022-11-101-0/+3
* x86/cacheinfo: move shared cache map definitionsSander Vanheule2022-07-181-0/+6
* sched: Add cluster scheduler level for x86Tim Chen2021-10-151-0/+1
* drivers: base: cacheinfo: Get rid of DEFINE_SMP_CALL_CACHE_FUNCTION()Thomas Gleixner2021-09-011-5/+2
* x86/cacheinfo: Remove unneeded dead-store initializationYang Li2021-04-071-1/+1
* x86/CPU/AMD: Remove amd_get_nb_id()Yazen Ghannam2020-11-191-1/+1
* x86/CPU/AMD: Save AMD NodeId as cpu_die_idYazen Ghannam2020-11-191-3/+3
* treewide: Use fallthrough pseudo-keywordGustavo A. R. Silva2020-08-241-1/+1
* x86/cacheinfo: Fix a -Wtype-limits warningQian Cai2019-06-191-2/+1
* x86/kernel: Mark expected switch-case fall-throughsGustavo A. R. Silva2019-01-261-0/+1
* x86/kernel: Fix more -Wmissing-prototypes warningsBorislav Petkov2018-12-081-0/+1
* x86/cpu: Get cache info and setup cache cpumap for Hygon DhyanaPu Wen2018-09-271-2/+29
* x86/CPU/AMD: Fix LLC ID bit-shift calculationSuravee Suthikulpanit2018-06-221-1/+1
* x86/CPU: Move cpu_detect_cache_sizes() into init_intel_cacheinfo()David Wang2018-05-131-2/+3
* x86/CPU: Move cpu local function declarations to local headerThomas Gleixner2018-05-131-0/+2
* x86/CPU/AMD: Calculate last level cache ID from number of sharing threadsSuravee Suthikulpanit2018-05-061-0/+39
* x86/CPU: Rename intel_cacheinfo.c to cacheinfo.cBorislav Petkov2018-05-061-0/+968
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