| Commit message (Expand) | Author | Age | Files | Lines |
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| * | perf/x86: Move perf_event.h to its new home | Borislav Petkov | 2016-02-17 | 1 | -955/+0 |
| * | perf/x86/intel: Add perf core PMU support for Intel Knights Landing | Harish Chegondi | 2016-01-06 | 1 | -0/+2 |
| * | perf/x86: Use INST_RETIRED.PREC_DIST for cycles: ppp | Andi Kleen | 2016-01-06 | 1 | -1/+2 |
| * | perf/x86: Remove old MSR perf tracing code | Andi Kleen | 2015-12-06 | 1 | -11/+1 |
| * | Merge branch 'perf/urgent' into perf/core, to pick up fixes | Ingo Molnar | 2015-12-06 | 1 | -1/+1 |
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| | * | perf/x86/intel: Fix INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA macro | Jiri Olsa | 2015-12-06 | 1 | -1/+1 |
| * | | perf/x86: Handle multiple umask bits for BDW CYCLE_ACTIVITY.* | Andi Kleen | 2015-11-23 | 1 | -0/+4 |
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| * | treewide: Remove old email address | Peter Zijlstra | 2015-11-23 | 1 | -1/+1 |
| * | perf/x86: Fix LBR call stack save/restore | Andi Kleen | 2015-11-23 | 1 | -0/+1 |
| * | Merge branch 'perf/urgent' into perf/core, to pick up fixes before applying n... | Ingo Molnar | 2015-09-18 | 1 | -0/+1 |
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| | * | perf/x86/intel/pebs: Add PEBS frontend profiling for Skylake | Andi Kleen | 2015-09-18 | 1 | -0/+1 |
| * | | perf/core: Drop PERF_EVENT_TXN | Sukadev Bhattiprolu | 2015-09-13 | 1 | -1/+0 |
| * | | perf/core: Add a 'flags' parameter to the PMU transactional interfaces | Sukadev Bhattiprolu | 2015-09-13 | 1 | -0/+1 |
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| * | perf/x86: Make merge_attr() global to use from perf_event_intel | Andi Kleen | 2015-08-04 | 1 | -0/+3 |
| * | perf/x86/intel: Add Intel Skylake PMU support | Andi Kleen | 2015-08-04 | 1 | -1/+5 |
| * | perf/x86/intel/lbr: Add support for LBRv5 | Andi Kleen | 2015-08-04 | 1 | -0/+1 |
| * | perf/x86/intel/lbr: Allow time stamp for free running PEBSv3 | Andi Kleen | 2015-08-04 | 1 | -0/+1 |
| * | perf/x86/intel/lbr: Kill off intel_pmu_needs_lbr_smpl for good | Alexander Shishkin | 2015-08-04 | 1 | -14/+0 |
| * | Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/ke... | Linus Torvalds | 2015-06-23 | 1 | -0/+4 |
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| | * | perf/x86/intel/bts: Fix DS area sharing with x86_pmu events | Alexander Shishkin | 2015-06-19 | 1 | -0/+4 |
| * | | perf/x86/intel: Drain the PEBS buffer during context switches | Yan, Zheng | 2015-06-07 | 1 | -1/+5 |
| * | | perf/x86/intel: Implement batched PEBS interrupt handling (large PEBS interru... | Yan, Zheng | 2015-06-07 | 1 | -0/+11 |
| * | | perf/x86/intel: Use the PEBS auto reload mechanism when possible | Yan, Zheng | 2015-06-07 | 1 | -0/+1 |
| * | | perf/x86/intel: Remove intel_excl_states::init_state | Peter Zijlstra | 2015-05-27 | 1 | -1/+0 |
| * | | perf/x86/intel: Clean up intel_commit_scheduling() placement | Peter Zijlstra | 2015-05-27 | 1 | -2/+2 |
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| * | perf/x86: Improve HT workaround GP counter constraint | Peter Zijlstra | 2015-05-27 | 1 | -3/+12 |
| * | perf/x86: Fix event/group validation | Peter Zijlstra | 2015-05-27 | 1 | -4/+5 |
| * | perf/x86: Fix hw_perf_event::flags collision | Peter Zijlstra | 2015-04-17 | 1 | -9/+9 |
| * | perf/x86/intel: Streamline LBR MSR handling in PMI | Andi Kleen | 2015-04-02 | 1 | -1/+1 |
| * | perf/x86/intel: Make the HT bug workaround conditional on HT enabled | Stephane Eranian | 2015-04-02 | 1 | -0/+5 |
| * | perf/x86/intel: Limit to half counters when the HT workaround is enabled, to ... | Stephane Eranian | 2015-04-02 | 1 | -0/+2 |
| * | perf/x86/intel: Enforce HT bug workaround with PEBS for SNB/IVB/HSW | Maria Dimakopoulou | 2015-04-02 | 1 | -1/+19 |
| * | perf/x86/intel: Implement cross-HT corruption bug workaround | Maria Dimakopoulou | 2015-04-02 | 1 | -0/+6 |
| * | perf/x86/intel: Add cross-HT counter exclusion infrastructure | Maria Dimakopoulou | 2015-04-02 | 1 | -0/+32 |
| * | perf/x86: Add 'index' param to get_event_constraint() callback | Stephane Eranian | 2015-04-02 | 1 | -1/+3 |
| * | perf/x86: Add 3 new scheduling callbacks | Maria Dimakopoulou | 2015-04-02 | 1 | -0/+9 |
| * | perf/x86: Vectorize cpuc->kfree_on_online | Stephane Eranian | 2015-04-02 | 1 | -1/+7 |
| * | perf/x86: Rename x86_pmu::er_flags to 'flags' | Stephane Eranian | 2015-04-02 | 1 | -3/+6 |
| * | perf/x86/intel/bts: Add BTS PMU driver | Alexander Shishkin | 2015-04-02 | 1 | -0/+7 |
| * | perf/x86/intel/pt: Add Intel PT PMU driver | Alexander Shishkin | 2015-04-02 | 1 | -0/+2 |
| * | perf/x86: Mark Intel PT and LBR/BTS as mutually exclusive | Alexander Shishkin | 2015-04-02 | 1 | -0/+40 |
| * | perf/x86/intel: Add INST_RETIRED.ALL workarounds | Andi Kleen | 2015-03-27 | 1 | -0/+1 |
| * | perf/x86/intel: Expose LBR callstack to user space tooling | Peter Zijlstra | 2015-02-18 | 1 | -8/+0 |
| * | perf/x86/intel: Allocate space for storing LBR stack | Yan, Zheng | 2015-02-18 | 1 | -0/+7 |
| * | perf/x86/intel: Add basic Haswell LBR call stack support | Yan, Zheng | 2015-02-18 | 1 | -1/+13 |
| * | perf/x86/intel: Use context switch callback to flush LBR stack | Yan, Zheng | 2015-02-18 | 1 | -1/+2 |
| * | perf: Introduce pmu context switch callback | Yan, Zheng | 2015-02-18 | 1 | -0/+2 |
| * | perf/x86/intel: Reduce lbr_sel_map[] size | Yan, Zheng | 2015-02-18 | 1 | -0/+4 |
| * | perf/x86: Only allow rdpmc if a perf_event is mapped | Andy Lutomirski | 2015-02-04 | 1 | -0/+2 |
| * | perf/x86: Add INTEL_FLAGS_UEVENT_CONSTRAINT | Andi Kleen | 2014-11-16 | 1 | -0/+4 |
