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path: root/arch/x86/lib/insn-eval.c (follow)
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* x86/insn-eval: Fix function param name in get_eff_addr_sib()Randy Dunlap2024-02-131-3/+3
* x86/insn: Avoid namespace clash by separating instruction decoder MMIO type f...Jason A. Donenfeld2023-01-031-10/+10
* x86/32: Remove lazy GS macrosBrian Gerst2022-04-141-2/+3
* Merge tag 'x86_core_for_v5.17_rc1' of git://git.kernel.org/pub/scm/linux/kern...Linus Torvalds2022-01-131-24/+47
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| * x86/entry_32: Fix segment exceptionsPeter Zijlstra2022-01-121-0/+5
| * x86/extable: Extend extable functionalityPeter Zijlstra2021-12-111-24/+42
* | x86/insn-eval: Introduce insn_decode_mmio()Kirill A. Shutemov2021-11-301-0/+84
* | x86/insn-eval: Introduce insn_get_modrm_reg_ptr()Kirill A. Shutemov2021-11-301-0/+20
* | x86/insn-eval: Handle insn_get_opcode() failureKirill A. Shutemov2021-11-301-2/+3
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* x86/iopl: Fake iopl(3) CLI/STI usagePeter Zijlstra2021-09-211-1/+1
* x86/insn: Extend error reporting from insn_fetch_from_user[_inatomic]()Joerg Roedel2021-06-151-8/+8
* x86/insn-eval: Make 0 a valid RIP for insn_get_effective_ip()Joerg Roedel2021-06-151-7/+7
* Merge tag 'x86_core_for_v5.13' of git://git.kernel.org/pub/scm/linux/kernel/g...Linus Torvalds2021-04-281-20/+24
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| * x86/insn-eval: Handle return values from the decoderBorislav Petkov2021-03-151-13/+21
| * x86/insn: Rename insn_decode() to insn_decode_from_regs()Borislav Petkov2021-03-151-3/+3
| * Merge tag 'v5.12-rc3' into x86/coreBorislav Petkov2021-03-151-14/+52
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| * | x86/stackprotector/32: Make the canary into a regular percpu variableAndy Lutomirski2021-03-081-4/+0
* | | x86: Fix various typos in commentsIngo Molnar2021-03-181-3/+3
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* | x86/sev-es: Use __copy_from_user_inatomic()Joerg Roedel2021-03-091-14/+52
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* x86/insn-eval: Use new for_each_insn_prefix() macro to loop over prefixes bytesMasami Hiramatsu2020-12-061-5/+5
* x86/insn: Add insn_has_rep_prefix() helperJoerg Roedel2020-09-071-0/+24
* x86/insn: Add insn_get_modrm_reg_off()Joerg Roedel2020-09-071-0/+23
* x86/umip: Factor out instruction decodingJoerg Roedel2020-09-071-0/+45
* x86/umip: Factor out instruction fetchJoerg Roedel2020-09-071-0/+38
* treewide: Use fallthrough pseudo-keywordGustavo A. R. Silva2020-08-241-4/+2
* x86/insn-eval: Add support for 64-bit kernel modeJann Horn2019-12-301-11/+15
* x86/insn-eval: Fix use-after-free access to LDT entryJann Horn2019-06-071-23/+24
* x86/insn-eval: Mark expected switch-case fall-throughGustavo A. R. Silva2019-01-261-0/+2
* x86/umip: Fix insn_get_code_seg_params()'s return valueBorislav Petkov2017-11-231-2/+2
* x86/insn-eval: Add support to resolve 16-bit address encodingsRicardo Neri2017-11-081-1/+212
* x86/insn-eval: Handle 32-bit address encodings in virtual-8086 modeRicardo Neri2017-11-081-0/+11
* x86/insn-eval: Add wrapper function for 32 and 64-bit addressesRicardo Neri2017-11-081-5/+55
* x86/insn-eval: Add support to resolve 32-bit address encodingsRicardo Neri2017-11-081-6/+106
* x86/insn-eval: Compute linear address in several utility functionsRicardo Neri2017-11-081-58/+185
* x86/insn-eval: Extend get_seg_base_addr() to also obtain segment limitRicardo Neri2017-11-021-8/+19
* x86/insn-eval: Incorporate segment base in linear address computationRicardo Neri2017-11-011-3/+52
* x86/insn-eval: Indicate a 32-bit displacement if ModRM.mod is 0 and ModRM.rm ...Ricardo Neri2017-11-011-3/+22
* x86/insn-eval: Add function to get default params of code segmentRicardo Neri2017-11-011-0/+64
* x86/insn-eval: Add utility functions to get segment descriptor base address a...Ricardo Neri2017-11-011-0/+114
* x86/insn-eval: Add utility function to get segment descriptorRicardo Neri2017-11-011-0/+57
* x86/insn-eval: Add utility functions to get segment selectorRicardo Neri2017-11-011-0/+340
* x86/insn-eval: Add utility function to identify string instructionsRicardo Neri2017-11-011-0/+28
* x86/insn-eval: Add a utility function to get register offsetsRicardo Neri2017-11-011-0/+17
* x86/insn-eval: Do not BUG on invalid register typeRicardo Neri2017-11-011-3/+6
* x86/mpx, x86/insn: Relocate insn util functions to a new insn-eval fileRicardo Neri2017-11-011-0/+163
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