| Commit message (Expand) | Author | Age | Files | Lines |
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157 | Thomas Gleixner | 2019-05-30 | 1 | -10/+1 |
* | clk: vc5: Abort clock configuration without upstream clock | Marek Vasut | 2019-01-09 | 1 | -1/+3 |
* | clk: vc5: Add suspend/resume support | Marek Vasut | 2018-12-14 | 1 | -0/+25 |
* | clk: vc5: Add support for IDT VersaClock 5P49V5925 | Vladimir Barinov | 2017-07-17 | 1 | -0/+11 |
* | clk: vc5: Add support for IDT VersaClock 5P49V6901 | Marek Vasut | 2017-07-17 | 1 | -0/+11 |
* | clk: vc5: Add support for the input frequency doubler | Marek Vasut | 2017-07-17 | 1 | -1/+77 |
* | clk: vc5: Split clock input mux and predivider | Marek Vasut | 2017-07-17 | 1 | -12/+34 |
* | clk: vc5: Configure the output buffer input mux on prepare | Marek Vasut | 2017-07-17 | 1 | -0/+19 |
* | clk: vc5: Do not warn about disabled output buffer input muxes | Marek Vasut | 2017-07-17 | 1 | -0/+3 |
* | clk: vc5: Fix trivial typo | Marek Vasut | 2017-07-17 | 1 | -1/+1 |
* | clk: vc5: Prevent division by zero on unconfigured outputs | Marek Vasut | 2017-07-17 | 1 | -0/+4 |
* | clk: vc5: Add support for IDT VersaClock 5P49V5935 | Alexey Firago | 2017-04-19 | 1 | -2/+13 |
* | clk: vc5: Add structure to describe particular chip features | Alexey Firago | 2017-04-19 | 1 | -18/+47 |
* | clk: vc5: Add support for IDT VersaClock 5P49V5923 and 5P49V5933 | Marek Vasut | 2017-01-21 | 1 | -0/+791 |