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path: root/drivers/clk/clk-versaclock5.c (follow)
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* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157Thomas Gleixner2019-05-301-10/+1
* clk: vc5: Abort clock configuration without upstream clockMarek Vasut2019-01-091-1/+3
* clk: vc5: Add suspend/resume supportMarek Vasut2018-12-141-0/+25
* clk: vc5: Add support for IDT VersaClock 5P49V5925Vladimir Barinov2017-07-171-0/+11
* clk: vc5: Add support for IDT VersaClock 5P49V6901Marek Vasut2017-07-171-0/+11
* clk: vc5: Add support for the input frequency doublerMarek Vasut2017-07-171-1/+77
* clk: vc5: Split clock input mux and predividerMarek Vasut2017-07-171-12/+34
* clk: vc5: Configure the output buffer input mux on prepareMarek Vasut2017-07-171-0/+19
* clk: vc5: Do not warn about disabled output buffer input muxesMarek Vasut2017-07-171-0/+3
* clk: vc5: Fix trivial typoMarek Vasut2017-07-171-1/+1
* clk: vc5: Prevent division by zero on unconfigured outputsMarek Vasut2017-07-171-0/+4
* clk: vc5: Add support for IDT VersaClock 5P49V5935Alexey Firago2017-04-191-2/+13
* clk: vc5: Add structure to describe particular chip featuresAlexey Firago2017-04-191-18/+47
* clk: vc5: Add support for IDT VersaClock 5P49V5923 and 5P49V5933Marek Vasut2017-01-211-0/+791