| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk: Explicitly include correct DT includes | Rob Herring | 2023-07-19 | 1 | -1/+1 |
| * | clk: hisilicon: fix sparse warnings in clk-hi3660.c | Ben Dooks | 2019-10-03 | 1 | -30/+30 |
| * | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152 | Thomas Gleixner | 2019-05-30 | 1 | -5/+1 |
| * | clk: hi3660: Mark clk_gate_ufs_subsys as critical | Leo Yan | 2019-04-20 | 1 | -1/+5 |
| * | clk: hi3660: fix incorrect uart3 clock freqency | Zhong Kaihua | 2017-11-14 | 1 | -1/+1 |
| * | clk: hi3660: Set PPLL2 to 2880M | Zhong Kaihua | 2017-06-20 | 1 | -2/+2 |
| * | clk: hi3660: add clocks for video encoder, decoder and ISP | Chen Jun | 2017-06-20 | 1 | -0/+40 |
| * | clk: hi3660: fix wrong parent name of clk_mux_sysbus | Chen Jun | 2017-06-20 | 1 | -2/+4 |
| * | clk: Hi3660: register fixed_rate_clks with CLK_OF_DECLARE_DRIVER | Leo Yan | 2017-06-20 | 1 | -10/+38 |
| * | clk: hisilicon: Add clock driver for hi3660 SoC | Zhangfei Gao | 2017-01-10 | 1 | -0/+567 |
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