| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk: imx: remove redundant re-assignment of pll->base | Colin Ian King | 2022-03-09 | 1 | -1/+0 |
| * | clk: imx: Support building i.MX common clock driver as module | Anson Huang | 2020-08-22 | 1 | -0/+2 |
| * | clk: imx: clk-sscg-pll: Remove unnecessary blank lines | Anson Huang | 2020-04-20 | 1 | -10/+0 |
| * | clk: imx: clk-sscg-pll: Drop unnecessary initialization | Anson Huang | 2020-02-24 | 1 | -7/+7 |
| * | clk: imx: Rename sccg and frac pll register to suggest clk_hw | Abel Vesa | 2019-12-11 | 1 | -2/+2 |
| * | clk: imx: Rename the SCCG to SSCG | Abel Vesa | 2019-12-11 | 1 | -0/+549 |
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