| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk: ingenic: Mark critical clocks in Ingenic SoCs | Aidan MacDonald | 2022-05-18 | 1 | -0/+10 |
| * | clk: jz4725b: fix mmc0 clock gating | Siarhei Volkau | 2022-02-18 | 1 | -2/+1 |
| * | dt-bindings: Rename Ingenic CGU headers to ingenic,*.h | Paul Cercueil | 2021-11-12 | 1 | -1/+1 |
| * | clk: Support bypassing dividers | Paul Cercueil | 2021-06-28 | 1 | -6/+6 |
| * | clk: Ingenic: Adjust cgu code to make it compatible with X1830. | 周琰杰 (Zhou Yanjie) | 2020-05-29 | 1 | -0/+4 |
| * | clk: ingenic: Use CLK_OF_DECLARE_DRIVER macro | Paul Cercueil | 2019-08-12 | 1 | -1/+1 |
| * | clk: ingenic: Handle setting the Low-Power Mode bit | Paul Cercueil | 2019-06-26 | 1 | -0/+3 |
| * | clk: ingenic/jz4725b: Fix "pll half" divider not read/written properly | Paul Cercueil | 2019-06-07 | 1 | -1/+8 |
| * | clk: ingenic/jz4725b: Fix incorrect dividers for main clocks | Paul Cercueil | 2019-06-07 | 1 | -5/+24 |
| * | clk: ingenic: jz4725b: Add UDC PHY clock | Paul Cercueil | 2019-04-11 | 1 | -0/+6 |
| * | clk: Add Ingenic jz4725b CGU driver | Paul Cercueil | 2018-10-17 | 1 | -0/+225 |
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