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path: root/drivers/clk/ingenic (follow)
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* clk: ingenic: tcu: Switch to determine_rateMaxime Ripard2023-06-091-8/+11
* clk: ingenic: cgu: Switch to determine_rateMaxime Ripard2023-06-091-7/+8
* clk: ingenic: jz4760: Update M/N/OD calculation algorithmPaul Cercueil2023-01-261-10/+8
* clk: Add Ingenic JZ4755 CGU driverSiarhei Volkau2022-11-013-0/+357
* clk: ingenic: Minor cosmetic fixups for X1000Aidan MacDonald2022-10-271-25/+24
* clk: ingenic: Add X1000 audio clocksAidan MacDonald2022-10-271-0/+70
* clk: ingenic: Add .set_rate_hook() for PLL clocksAidan MacDonald2022-10-272-0/+7
* clk: ingenic: Make PLL clock enable_bit and stable_bit optionalAidan MacDonald2022-10-272-5/+19
* clk: ingenic: Make PLL clock "od" field optionalAidan MacDonald2022-10-272-9/+19
* clk: ingenic-tcu: Properly enable registers before accessing timersAidan MacDonald2022-09-011-10/+5
* clk: ingenic-tcu: Fix missing TCU clock for X1000 SoCsAidan MacDonald2022-05-191-10/+25
* clk: ingenic: Mark critical clocks in Ingenic SoCsAidan MacDonald2022-05-187-0/+76
* clk: ingenic: Allow specifying common clock flagsAidan MacDonald2022-05-182-1/+4
* clk: jz4725b: fix mmc0 clock gatingSiarhei Volkau2022-02-181-2/+1
* clk: ingenic: Add MDMA and BDMA clocksPaul Cercueil2022-01-072-0/+15
* Merge tag 'devicetree-fixes-for-5.16-1' of git://git.kernel.org/pub/scm/linux...Linus Torvalds2021-11-147-7/+7
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| * dt-bindings: Rename Ingenic CGU headers to ingenic,*.hPaul Cercueil2021-11-127-7/+7
* | clk: ingenic: Fix bugs with divided dividersPaul Cercueil2021-11-021-3/+3
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* clk: ingenic: Add support for the JZ4760Paul Cercueil2021-06-284-0/+441
* clk: ingenic: Support overriding PLLs M/N/OD calc algorithmPaul Cercueil2021-06-282-13/+30
* clk: ingenic: Remove pll_info.no_bypass_bitPaul Cercueil2021-06-283-8/+6
* clk: ingenic: Read bypass register only when there is onePaul Cercueil2021-06-281-8/+11
* clk: Support bypassing dividersPaul Cercueil2021-06-285-29/+42
* clk: ingenic: Fix divider calculation with div tablesPaul Cercueil2020-12-201-4/+10
* clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_ratePaul Cercueil2020-10-141-0/+2
* clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENTPaul Cercueil2020-10-141-7/+7
* clk: ingenic: Don't use CLK_SET_RATE_GATE for PLLPaul Cercueil2020-10-141-2/+7
* clk: ingenic: Use readl_poll_timeout instead of custom loopPaul Cercueil2020-10-141-26/+29
* clk: ingenic: Use to_clk_info() macro for all clocksPaul Cercueil2020-10-141-39/+15
* clk: X1000: Add support for calculat REFCLK of USB PHY.周琰杰 (Zhou Yanjie)2020-07-281-1/+83
* clk: JZ4780: Reformat the code to align it.周琰杰 (Zhou Yanjie)2020-07-281-45/+45
* clk: JZ4780: Add functions for enable and disable USB PHY.周琰杰 (Zhou Yanjie)2020-07-281-30/+35
* clk: Ingenic: Add RTC related clocks for Ingenic SoCs.周琰杰 (Zhou Yanjie)2020-07-283-0/+38
* clk: ingenic: Mark ingenic_tcu_of_match as __maybe_unusedStephen Boyd2020-05-291-1/+1
* clk: X1000: Add FIXDIV for SSI clock of X1000.周琰杰 (Zhou Yanjie)2020-05-291-6/+111
* clk: Ingenic: Add CGU driver for X1830.周琰杰 (Zhou Yanjie)2020-05-293-0/+459
* clk: Ingenic: Adjust cgu code to make it compatible with X1830.周琰杰 (Zhou Yanjie)2020-05-297-4/+41
* clk: Ingenic: Remove unnecessary spinlock when reading registers.周琰杰 (Zhou Yanjie)2020-05-291-11/+1
* clk: ingenic/TCU: Fix round_rate returning errorPaul Cercueil2020-03-211-1/+1
* clk: ingenic/jz4770: Exit with error if CGU init failedPaul Cercueil2020-03-211-1/+3
* clk: JZ4780: Add function for enable the second core.周琰杰 (Zhou Yanjie)2020-03-211-5/+50
* clk: Ingenic: Add support for TCU of X1000.周琰杰 (Zhou Yanjie)2020-03-211-0/+8
*-. Merge branches 'clk-ingenic', 'clk-init-leak', 'clk-ux500' and 'clk-bitmain' ...Stephen Boyd2019-11-273-1/+286
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| * | clk: ingenic: Allow drivers to be built with COMPILE_TESTStephen Boyd2019-11-221-1/+1
| * | clk: Ingenic: Add CGU driver for X1000.Zhou Yanjie2019-11-143-0/+285
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* / drivers/clk: convert VL struct to struct_sizeStephen Kitt2019-11-081-2/+1
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* Merge tag 'mips_5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linuxLinus Torvalds2019-09-224-1/+490
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| * clk: jz4740: Add TCU clockPaul Cercueil2019-08-091-0/+6
| * clk: ingenic: Add driver for the TCU clocksPaul Cercueil2019-08-093-1/+484
* | clk: ingenic: Use CLK_OF_DECLARE_DRIVER macroPaul Cercueil2019-08-124-4/+4
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-18 23:26:46 +0100