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path: root/drivers/clk/mediatek/Makefile (follow)
Commit message (Expand)AuthorAgeFilesLines
* clk: mediatek: add MT7981 clock supportDaniel Golle2023-01-311-0/+4
* clk: mediatek: mt8173: Break down clock drivers and allow module buildAngeloGioacchino Del Regno2023-01-311-1/+5
* clk: mediatek: Add new clock driver to handle FHCTL hardwareJohnson Wang2022-11-291-0/+1
* clk: mediatek: add driver for MT8365 SoCFabien Parent2022-10-011-0/+7
* clk: mediatek: Add MediaTek Helio X10 MT6795 clock driversAngeloGioacchino Del Regno2022-09-261-0/+6
* clk: mediatek: Add MT8186 ipesys clock supportChun-Jie Chen2022-04-261-1/+1
* clk: mediatek: Add MT8186 mdpsys clock supportChun-Jie Chen2022-04-261-1/+1
* clk: mediatek: Add MT8186 camsys clock supportChun-Jie Chen2022-04-261-1/+2
* clk: mediatek: Add MT8186 vencsys clock supportChun-Jie Chen2022-04-261-1/+1
* clk: mediatek: Add MT8186 vdecsys clock supportChun-Jie Chen2022-04-261-1/+1
* clk: mediatek: Add MT8186 imgsys clock supportChun-Jie Chen2022-04-261-1/+2
* clk: mediatek: Add MT8186 wpesys clock supportChun-Jie Chen2022-04-261-1/+1
* clk: mediatek: Add MT8186 mmsys clock supportChun-Jie Chen2022-04-261-1/+1
* clk: mediatek: Add MT8186 mfgsys clock supportChun-Jie Chen2022-04-261-1/+2
* clk: mediatek: Add MT8186 imp i2c wrapper clock supportChun-Jie Chen2022-04-261-1/+1
* clk: mediatek: Add MT8186 apmixedsys clock supportChun-Jie Chen2022-04-261-1/+2
* clk: mediatek: Add MT8186 infrastructure clock supportChun-Jie Chen2022-04-261-1/+1
* clk: mediatek: Add MT8186 topckgen clock supportChun-Jie Chen2022-04-261-1/+1
* clk: mediatek: Add MT8186 mcusys clock supportChun-Jie Chen2022-04-261-0/+1
* clk: mediatek: add mt7986 clock supportSam Shih2022-01-071-0/+4
* clk: mediatek: Add MT8195 apusys clock supportChun-Jie Chen2021-09-151-1/+2
* clk: mediatek: Add MT8195 imp i2c wrapper clock supportChun-Jie Chen2021-09-151-1/+1
* clk: mediatek: Add MT8195 wpesys clock supportChun-Jie Chen2021-09-151-1/+2
* clk: mediatek: Add MT8195 vppsys1 clock supportChun-Jie Chen2021-09-151-1/+1
* clk: mediatek: Add MT8195 vppsys0 clock supportChun-Jie Chen2021-09-151-1/+1
* clk: mediatek: Add MT8195 vencsys clock supportChun-Jie Chen2021-09-151-1/+2
* clk: mediatek: Add MT8195 vdosys1 clock supportChun-Jie Chen2021-09-151-1/+1
* clk: mediatek: Add MT8195 vdosys0 clock supportChun-Jie Chen2021-09-151-1/+1
* clk: mediatek: Add MT8195 vdecsys clock supportChun-Jie Chen2021-09-151-1/+2
* clk: mediatek: Add MT8195 scp adsp clock supportChun-Jie Chen2021-09-151-1/+1
* clk: mediatek: Add MT8195 mfgcfg clock supportChun-Jie Chen2021-09-151-1/+1
* clk: mediatek: Add MT8195 ipesys clock supportChun-Jie Chen2021-09-151-1/+2
* clk: mediatek: Add MT8195 imgsys clock supportChun-Jie Chen2021-09-151-1/+1
* clk: mediatek: Add MT8195 ccusys clock supportChun-Jie Chen2021-09-151-1/+1
* clk: mediatek: Add MT8195 camsys clock supportChun-Jie Chen2021-09-151-1/+2
* clk: mediatek: Add MT8195 infrastructure clock supportChun-Jie Chen2021-09-151-1/+1
* clk: mediatek: Add MT8195 peripheral clock supportChun-Jie Chen2021-09-151-1/+2
* clk: mediatek: Add MT8195 topckgen clock supportChun-Jie Chen2021-09-151-1/+1
* clk: mediatek: Add MT8195 apmixedsys clock supportChun-Jie Chen2021-09-151-0/+1
* clk: mediatek: Add MT8192 vencsys clock supportChun-Jie Chen2021-07-271-0/+1
* clk: mediatek: Add MT8192 vdecsys clock supportChun-Jie Chen2021-07-271-0/+1
* clk: mediatek: Add MT8192 scp adsp clock supportChun-Jie Chen2021-07-271-0/+1
* clk: mediatek: Add MT8192 msdc clock supportChun-Jie Chen2021-07-271-0/+1
* clk: mediatek: Add MT8192 mmsys clock supportChun-Jie Chen2021-07-271-0/+1
* clk: mediatek: Add MT8192 mfgcfg clock supportChun-Jie Chen2021-07-271-0/+1
* clk: mediatek: Add MT8192 mdpsys clock supportChun-Jie Chen2021-07-271-0/+1
* clk: mediatek: Add MT8192 ipesys clock supportChun-Jie Chen2021-07-271-0/+1
* clk: mediatek: Add MT8192 imp i2c wrapper clock supportChun-Jie Chen2021-07-271-0/+1
* clk: mediatek: Add MT8192 imgsys clock supportChun-Jie Chen2021-07-271-0/+1
* clk: mediatek: Add MT8192 camsys clock supportChun-Jie Chen2021-07-271-0/+1
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-14 05:18:34 +0100