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path: root/drivers/clk/mediatek/clk-mt2701.c (follow)
Commit message (Expand)AuthorAgeFilesLines
* clk: mediatek: clk-mt2701: Add check for mtk_alloc_clk_dataJiasheng Jiang2023-10-191-0/+8
* clk: mediatek: Convert to devm_platform_ioremap_resource()Yangtao Li2023-08-221-4/+2
* clk: Explicitly include correct DT includesRob Herring2023-07-191-3/+1
* clk: mediatek: Add MODULE_DEVICE_TABLE() where appropriateAngeloGioacchino Del Regno2023-03-131-0/+1
* clk: mediatek: Add MODULE_LICENSE() where missingAngeloGioacchino Del Regno2023-03-131-0/+1
* clk: mediatek: Propagate struct device with mtk_clk_register_dividers()AngeloGioacchino Del Regno2023-03-131-1/+1
* clk: mediatek: Consistently use GATE_MTK() macroAngeloGioacchino Del Regno2023-03-131-32/+8
* clk: mediatek: clk-mtk: Propagate struct device for compositesAngeloGioacchino Del Regno2023-01-311-4/+6
* clk: mediatek: cpumux: Propagate struct device where possibleAngeloGioacchino Del Regno2023-01-311-1/+1
* clk: mediatek: clk-gate: Propagate struct device with mtk_clk_register_gates()AngeloGioacchino Del Regno2023-01-311-6/+6
* clk: mediatek: reset: Add new register reset function with deviceRex-BC Chen2022-06-161-2/+2
* clk: mediatek: reset: Support nonsequence base offsets of reset registersRex-BC Chen2022-06-161-4/+7
* clk: mediatek: reset: Revise structure to control reset registerRex-BC Chen2022-06-161-2/+17
* clk: mediatek: reset: Merge and revise reset register functionRex-BC Chen2022-06-161-2/+2
* clk: mediatek: Replace 'struct clk' with 'struct clk_hw'Chen-Yu Tsai2022-05-201-12/+14
* clk: mediatek: use en_mask as a pure div_en_maskChun-Jie Chen2022-05-191-4/+4
* clk: mediatek: pll: Split definitions into separate header fileChen-Yu Tsai2022-02-171-2/+3
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner2019-05-301-9/+1
* clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_selchunhui dai2019-02-251-2/+2
* clk: mediatek: remove unused array audio_parentsColin Ian King2018-08-311-5/+0
* clk: mediatek: correct the clocks for MT2701 HDMI PHY moduleRyder Lee2018-05-161-2/+6
* clk: mediatek: fix PWM clock source by adding a fixed-factor clockSean Wang2018-03-191-7/+8
* clk: mediatek: mark mtk_infrasys_init_early __initArnd Bergmann2017-11-021-1/+1
* clk: mediatek: export cpu multiplexer clock for MT2701/MT7623 SoCsSean Wang2017-06-201-0/+8
* reset: mediatek: Add MT2701 reset driverShunli Wang2016-11-091-2/+10
* clk: mediatek: Add MT2701 clock supportShunli Wang2016-11-091-0/+1027
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