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path: root/drivers/clk/mediatek/clk-mt7622-eth.c (follow)
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* clk: Explicitly include correct DT includesRob Herring2023-07-191-3/+1
* clk: mediatek: Make mtk_clk_simple_remove() return voidUwe Kleine-König2023-05-101-1/+1
* clk: mediatek: Add MODULE_DEVICE_TABLE() where appropriateAngeloGioacchino Del Regno2023-03-131-0/+1
* clk: mediatek: Add MODULE_LICENSE() where missingAngeloGioacchino Del Regno2023-03-131-0/+1
* clk: mediatek: Switch to module_platform_driver() where possibleAngeloGioacchino Del Regno2023-03-131-2/+1
* clk: mediatek: Consistently use GATE_MTK() macroAngeloGioacchino Del Regno2023-03-131-16/+4
* clk: mediatek: Switch to mtk_clk_simple_probe() where possibleAngeloGioacchino Del Regno2023-01-311-68/+14
* clk: mediatek: clk-gate: Propagate struct device with mtk_clk_register_gates()AngeloGioacchino Del Regno2023-01-311-4/+4
* clk: mediatek: reset: Add new register reset function with deviceRex-BC Chen2022-06-161-1/+1
* clk: mediatek: reset: Support nonsequence base offsets of reset registersRex-BC Chen2022-06-161-2/+4
* clk: mediatek: reset: Revise structure to control reset registerRex-BC Chen2022-06-161-1/+7
* clk: mediatek: reset: Merge and revise reset register functionRex-BC Chen2022-06-161-1/+1
* clk: mediatek: Replace 'struct clk' with 'struct clk_hw'Chen-Yu Tsai2022-05-201-4/+4
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner2019-05-301-9/+1
* clk: mediatek: add clock support for MT7622 SoCSean Wang2017-11-021-0/+156