summaryrefslogtreecommitdiffstats
path: root/drivers/clk/mediatek/clk-pll.c (follow)
Commit message (Expand)AuthorAgeFilesLines
* clk: mediatek: Export PLL operations symbolsJohnson Wang2022-11-291-50/+34
* clk: mediatek: Switch to clk_hw provider APIsChen-Yu Tsai2022-05-201-17/+18
* clk: mediatek: Replace 'struct clk' with 'struct clk_hw'Chen-Yu Tsai2022-05-201-12/+11
* clk: mediatek: use en_mask as a pure div_en_maskChun-Jie Chen2022-05-191-8/+4
* clk: mediatek: Warn if clk IDs are duplicatedChen-Yu Tsai2022-02-171-0/+6
* clk: mediatek: pll: Implement error handling in register APIChen-Yu Tsai2022-02-171-4/+19
* clk: mediatek: pll: Clean up included headersChen-Yu Tsai2022-02-171-5/+7
* clk: mediatek: pll: Implement unregister APIChen-Yu Tsai2022-02-171-0/+55
* clk: mediatek: pll: Split definitions into separate header fileChen-Yu Tsai2022-02-171-0/+1
* clk: mediatek: Use %pe to print errorsChen-Yu Tsai2022-02-171-2/+1
* clk: mediatek: support COMMON_CLK_MEDIATEK module buildMiles Chen2021-09-151-0/+4
* clk: mediatek: Fix corner case of tuner_en_regChun-Jie Chen2021-09-151-1/+1
* clk: mediatek: Add configurable enable control to mtk_pll_dataChun-Jie Chen2021-07-271-5/+10
* clk: mediatek: Fix asymmetrical PLL enable and disable controlChun-Jie Chen2021-07-271-4/+16
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner2019-05-301-9/+1
* clk: mediatek: Allow changing PLL rate when it is offJames Liao2019-04-111-11/+2
* clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_dataWeiyi Lu2019-04-111-6/+11
* clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_dataOwen Chen2019-04-111-4/+11
* clk: mediatek: Disable tuner_en before change PLL rateOwen Chen2019-04-111-14/+34
* clk: mediatek: add the option for determining PLL source clockChen Zhong2017-11-021-1/+4
* clk: mediatek: Add MT2712 clock supportweiyi.lu@mediatek.com2017-11-021-2/+11
* clk: mediatek: Add MT2701 clock supportShunli Wang2016-11-091-0/+1
* clk: mediatek: remove __init from clk registration functionsJames Liao2016-08-191-1/+1
* clk: mediatek: Add USB clock support in MT8173 APMIXEDSYSJames Liao2015-10-011-6/+1
* clk: mediatek: Add MT8173 MMPLL change rate supportJames Liao2015-07-281-3/+15
* clk: mediatek: Fix calculation of PLL rate settingsJames Liao2015-07-281-2/+2
* clk: mediatek: Fix PLL registers setting flowJames Liao2015-07-281-9/+12
* clk: mediatek: Initialize clk_init_dataRicky Liang2015-05-201-1/+1
* clk: mediatek: Add initial common clock support for Mediatek SoCs.James Liao2015-05-061-0/+332
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-10 10:38:00 +0100