| Commit message (Expand) | Author | Age | Files | Lines |
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174 | Thomas Gleixner | 2019-05-30 | 35 | -315/+35 |
* | treewide: Add SPDX license identifier - Makefile/Kconfig | Thomas Gleixner | 2019-05-21 | 1 | -0/+1 |
*-. | Merge branches 'clk-renesas', 'clk-qcom', 'clk-mtk', 'clk-milbeaut' and 'clk-... | Stephen Boyd | 2019-05-07 | 20 | -33/+3392 |
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| | * | clk: mediatek: add clock driver for MT8516 | Fabien Parent | 2019-04-25 | 3 | -0/+824 |
| | * | clk: mediatek: Allow changing PLL rate when it is off | James Liao | 2019-04-11 | 1 | -11/+2 |
| | * | clk: mediatek: Add MT8183 clock support | Weiyi Lu | 2019-04-11 | 15 | -0/+2196 |
| | * | clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_data | Weiyi Lu | 2019-04-11 | 2 | -6/+12 |
| | * | clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data | Owen Chen | 2019-04-11 | 2 | -4/+13 |
| | * | clk: mediatek: Add new clkmux register API | Owen Chen | 2019-04-11 | 3 | -1/+314 |
| | * | clk: mediatek: Disable tuner_en before change PLL rate | Owen Chen | 2019-04-11 | 1 | -14/+34 |
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* / | clk: mediatek: fix clk-gate flag setting | Weiyi Lu | 2019-04-12 | 1 | -2/+1 |
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*-. | Merge branches 'clk-typo', 'clk-json-schema', 'clk-mtk-2712-eco' and 'clk-roc... | Stephen Boyd | 2019-03-08 | 1 | -2/+6 |
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| | * | clk: mediatek: update clock driver of MT2712 | Weiyi Lu | 2019-02-05 | 1 | -2/+6 |
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*-----. \ | Merge branches 'clk-ingenic', 'clk-mtk-mux', 'clk-qcom-sdm845-pcie', 'clk-mtk... | Stephen Boyd | 2019-03-08 | 7 | -41/+75 |
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| | | | * | clk: mediatek: correct cpu clock name for MT8173 SoC | Seiya Wang | 2019-02-26 | 1 | -2/+2 |
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| | | * | clk: mediatek: Mark bus and DRAM related clocks as critical | Jasper Mattsson | 2019-02-26 | 1 | -25/+43 |
| | | * | clk: mediatek: Add flags to mtk_gate | Jasper Mattsson | 2019-02-26 | 4 | -3/+7 |
| | | * | clk: mediatek: Add MUX_FLAGS macro | Jasper Mattsson | 2019-02-26 | 1 | -2/+6 |
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| | * | clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel | chunhui dai | 2019-02-25 | 1 | -2/+2 |
| | * | clk: mediatek: add MUX_GATE_FLAGS_2 | chunhui dai | 2019-02-25 | 2 | -7/+15 |
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* / | clk: mediatek: fix platform_no_drv_owner.cocci warnings | YueHaibing | 2019-02-22 | 1 | -1/+0 |
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* | clk: mediatek: fix the PCIe MAC clock parent | Ryder Lee | 2018-12-05 | 1 | -2/+2 |
* | clk: mediatek: Drop more __init markings for driver probe | Stephen Boyd | 2018-11-30 | 1 | -2/+2 |
* | clk: mediatek: Drop __init from mtk_clk_register_cpumuxes() | Stephen Boyd | 2018-11-30 | 1 | -4/+4 |
* | clk: mediatek: add clock support for MT7629 SoC | Ryder Lee | 2018-11-30 | 5 | -0/+1064 |
* | clk: mediatek: remove unused array audio_parents | Colin Ian King | 2018-08-31 | 1 | -5/+0 |
*-. | Merge branches 'clk-hisi-usb', 'clk-silent-bulk', 'clk-mtk-hdmi', 'clk-mtk-ma... | Stephen Boyd | 2018-06-04 | 4 | -2/+108 |
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| | * | clk: mediatek: add g3dsys support for MT2701 and MT7623 | Sean Wang | 2018-05-16 | 3 | -0/+102 |
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| * | clk: mediatek: correct the clocks for MT2701 HDMI PHY module | Ryder Lee | 2018-05-16 | 1 | -2/+6 |
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*-. | Merge branches 'clk-mediatek', 'clk-hisi', 'clk-allwinner', 'clk-ux500' and '... | Stephen Boyd | 2018-04-06 | 5 | -8/+215 |
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| * | | clk: mediatek: add audsys support for MT2701 | Ryder Lee | 2018-03-20 | 3 | -0/+193 |
| * | | clk: mediatek: add devm_of_platform_populate() for MT7622 audsys | Ryder Lee | 2018-03-20 | 1 | -1/+13 |
| * | | clk: mediatek: update missing clock data for MT7622 audsys | Ryder Lee | 2018-03-19 | 1 | -0/+1 |
| * | | clk: mediatek: fix PWM clock source by adding a fixed-factor clock | Sean Wang | 2018-03-19 | 1 | -7/+8 |
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* / | clk: mediatek: update clock driver of MT2712 | Weiyi Lu | 2018-03-19 | 1 | -14/+55 |
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* | clk: mediatek: adjust dependency of reset.c to avoid unexpectedly being built | Sean Wang | 2018-01-10 | 3 | -9/+2 |
* | clk: mediatek: Fix all warnings for missing struct clk_onecell_data | Sean Wang | 2017-12-27 | 1 | -0/+1 |
* | clk: mediatek: group drivers under indpendent menu | Sean Wang | 2017-12-22 | 1 | -46/+50 |
* | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl... | Linus Torvalds | 2017-11-18 | 17 | -4/+3520 |
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| * | clk: mediatek: add clock support for MT7622 SoC | Sean Wang | 2017-11-02 | 6 | -0/+1334 |
| * | clk: mediatek: add the option for determining PLL source clock | Chen Zhong | 2017-11-02 | 2 | -1/+5 |
| * | clk: mediatek: mark mtk_infrasys_init_early __init | Arnd Bergmann | 2017-11-02 | 1 | -1/+1 |
| * | clk: mediatek: Add MT2712 clock support | weiyi.lu@mediatek.com | 2017-11-02 | 12 | -2/+2180 |
* | | License cleanup: add SPDX GPL-2.0 license identifier to files with no license | Greg Kroah-Hartman | 2017-11-02 | 1 | -0/+1 |
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* | clk: Convert to using %pOF instead of full_name | Rob Herring | 2017-07-22 | 3 | -3/+3 |
* | clk: mediatek: fixed static checker warning in clk_cpumux_get_parent call | Sean Wang | 2017-07-18 | 1 | -4/+0 |
* | clk: mediatek: export cpu multiplexer clock for MT8173 SoCs | Sean Wang | 2017-06-20 | 1 | -0/+23 |
* | clk: mediatek: export cpu multiplexer clock for MT2701/MT7623 SoCs | Sean Wang | 2017-06-20 | 1 | -0/+8 |
* | clk: mediatek: add missing cpu mux causing Mediatek cpufreq can't work | Sean Wang | 2017-06-20 | 3 | -1/+151 |
* | clk: mediatek: add mt2701 ethernet reset | John Crispin | 2017-04-22 | 1 | -0/+2 |